Datasets:

davide221

/

hdl-raw-35k

like 0

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/ip_repo/ac.uk_user_lms_pcore_1.0/hdl/vhdl/lms_pcore.vhd

-- ------------------------------------------------------------- -- -- File Name: hdl_prj\hdlsrc\lms\lms_pcore.vhd -- Created: 2015-06-19 16:39:46 -- -- Generated by MATLAB 8.5 and HDL Coder 3.6 -- -- -- ------------------------------------------------------------- -- Rate and Clocking Details -- ------------------------------------------------------------- -- Model base rate: -1 -- Target subsystem base rate: -1 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: lms_pcore -- Source Path: lms_pcore -- Hierarchy Level: 0 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY lms_pcore IS PORT( IPCORE_CLK : IN std_logic; -- ufix1 IPCORE_RESETN : IN std_logic; -- ufix1 AXI4_Lite_ACLK : IN std_logic; -- ufix1 AXI4_Lite_ARESETN : IN std_logic; -- ufix1 AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_AWVALID : IN std_logic; -- ufix1 AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4 AXI4_Lite_WVALID : IN std_logic; -- ufix1 AXI4_Lite_BREADY : IN std_logic; -- ufix1 AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_ARVALID : IN std_logic; -- ufix1 AXI4_Lite_RREADY : IN std_logic; -- ufix1 AXI4_Lite_AWREADY : OUT std_logic; -- ufix1 AXI4_Lite_WREADY : OUT std_logic; -- ufix1 AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_BVALID : OUT std_logic; -- ufix1 AXI4_Lite_ARREADY : OUT std_logic; -- ufix1 AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_RVALID : OUT std_logic -- ufix1 ); END lms_pcore; ARCHITECTURE rtl OF lms_pcore IS -- Component Declarations COMPONENT lms_pcore_dut PORT( clk : IN std_logic; -- ufix1 reset : IN std_logic; dut_enable : IN std_logic; -- ufix1 x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 ce_out : OUT std_logic; -- ufix1 e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14 ); END COMPONENT; COMPONENT lms_pcore_cop PORT( clk : IN std_logic; -- ufix1 reset : IN std_logic; in_strobe : IN std_logic; -- ufix1 cop_enable : IN std_logic; -- ufix1 out_ready : OUT std_logic; -- ufix1 dut_enable : OUT std_logic; -- ufix1 reg_strobe : OUT std_logic -- ufix1 ); END COMPONENT; COMPONENT lms_pcore_axi_lite PORT( reset : IN std_logic; AXI4_Lite_ACLK : IN std_logic; -- ufix1 AXI4_Lite_ARESETN : IN std_logic; -- ufix1 AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_AWVALID : IN std_logic; -- ufix1 AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4 AXI4_Lite_WVALID : IN std_logic; -- ufix1 AXI4_Lite_BREADY : IN std_logic; -- ufix1 AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_ARVALID : IN std_logic; -- ufix1 AXI4_Lite_RREADY : IN std_logic; -- ufix1 read_cop_out_ready : IN std_logic; -- ufix1 cop_reg_strobe : IN std_logic; -- ufix1 read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 AXI4_Lite_AWREADY : OUT std_logic; -- ufix1 AXI4_Lite_WREADY : OUT std_logic; -- ufix1 AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_BVALID : OUT std_logic; -- ufix1 AXI4_Lite_ARREADY : OUT std_logic; -- ufix1 AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_RVALID : OUT std_logic; -- ufix1 write_axi_enable : OUT std_logic; -- ufix1 strobe_cop_in_strobe : OUT std_logic; -- ufix1 write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14 write_d_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14 reset_internal : OUT std_logic -- ufix1 ); END COMPONENT; -- Component Configuration Statements FOR ALL : lms_pcore_dut USE ENTITY work.lms_pcore_dut(rtl); FOR ALL : lms_pcore_cop USE ENTITY work.lms_pcore_cop(rtl); FOR ALL : lms_pcore_axi_lite USE ENTITY work.lms_pcore_axi_lite(rtl); -- Signals SIGNAL reset : std_logic; SIGNAL reset_cm : std_logic; -- ufix1 SIGNAL cop_dut_enable : std_logic; -- ufix1 SIGNAL write_x_k : std_logic_vector(15 DOWNTO 0); -- ufix16 SIGNAL write_d_k : std_logic_vector(15 DOWNTO 0); -- ufix16 SIGNAL ce_out_sig : std_logic; -- ufix1 SIGNAL e_k_sig : std_logic_vector(15 DOWNTO 0); -- ufix16 SIGNAL reset_internal : std_logic; -- ufix1 SIGNAL strobe_cop_in_strobe : std_logic; -- ufix1 SIGNAL write_axi_enable : std_logic; -- ufix1 SIGNAL cop_out_ready : std_logic; -- ufix1 SIGNAL cop_reg_strobe : std_logic; -- ufix1 SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2 SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); -- ufix32 SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2 BEGIN u_lms_pcore_dut_inst : lms_pcore_dut PORT MAP( clk => IPCORE_CLK, -- ufix1 reset => reset, dut_enable => cop_dut_enable, -- ufix1 x_k => write_x_k, -- sfix16_En14 d_k => write_d_k, -- sfix16_En14 ce_out => ce_out_sig, -- ufix1 e_k => e_k_sig -- sfix16_En14 ); u_lms_pcore_cop_inst : lms_pcore_cop PORT MAP( clk => IPCORE_CLK, -- ufix1 reset => reset, in_strobe => strobe_cop_in_strobe, -- ufix1 cop_enable => write_axi_enable, -- ufix1 out_ready => cop_out_ready, -- ufix1 dut_enable => cop_dut_enable, -- ufix1 reg_strobe => cop_reg_strobe -- ufix1 ); u_lms_pcore_axi_lite_inst : lms_pcore_axi_lite PORT MAP( reset => reset, AXI4_Lite_ACLK => AXI4_Lite_ACLK, -- ufix1 AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, -- ufix1 AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, -- ufix16 AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, -- ufix1 AXI4_Lite_WDATA => AXI4_Lite_WDATA, -- ufix32 AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, -- ufix4 AXI4_Lite_WVALID => AXI4_Lite_WVALID, -- ufix1 AXI4_Lite_BREADY => AXI4_Lite_BREADY, -- ufix1 AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, -- ufix16 AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, -- ufix1 AXI4_Lite_RREADY => AXI4_Lite_RREADY, -- ufix1 read_cop_out_ready => cop_out_ready, -- ufix1 cop_reg_strobe => strobe_cop_in_strobe, -- ufix1 read_e_k => e_k_sig, -- sfix16_En14 AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, -- ufix1 AXI4_Lite_WREADY => AXI4_Lite_WREADY, -- ufix1 AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, -- ufix2 AXI4_Lite_BVALID => AXI4_Lite_BVALID, -- ufix1 AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, -- ufix1 AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, -- ufix32 AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, -- ufix2 AXI4_Lite_RVALID => AXI4_Lite_RVALID, -- ufix1 write_axi_enable => write_axi_enable, -- ufix1 strobe_cop_in_strobe => strobe_cop_in_strobe, -- ufix1 write_x_k => write_x_k, -- sfix16_En14 write_d_k => write_d_k, -- sfix16_En14 reset_internal => reset_internal -- ufix1 ); reset_cm <= NOT IPCORE_RESETN; reset <= reset_cm OR reset_internal; AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp; AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp; AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp; END rtl;

mit

d711bf82d855aaa216d90c6277268f80

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp601/config.vhd

----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench configuration -- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------ library techmap; use techmap.gencomp.all; package config is -- Technology and synthesis options constant CFG_FABTECH : integer := spartan6; constant CFG_MEMTECH : integer := spartan6; constant CFG_PADTECH : integer := spartan6; constant CFG_NOASYNC : integer := 0; constant CFG_SCAN : integer := 0; -- Clock generator constant CFG_CLKTECH : integer := spartan6; constant CFG_CLKMUL : integer := (18); constant CFG_CLKDIV : integer := (9); constant CFG_OCLKDIV : integer := 1; constant CFG_OCLKBDIV : integer := 0; constant CFG_OCLKCDIV : integer := 0; constant CFG_PCIDLL : integer := 0; constant CFG_PCISYSCLK: integer := 0; constant CFG_CLK_NOFB : integer := 0; -- LEON3 processor core constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); constant CFG_V8 : integer := 16#32# + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 1; constant CFG_SVT : integer := 1; constant CFG_RSTADDR : integer := 16#00000#; constant CFG_LDDEL : integer := (1); constant CFG_NOTAG : integer := 1; constant CFG_NWP : integer := (0); constant CFG_PWD : integer := 1*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; constant CFG_ISETS : integer := 1; constant CFG_ISETSZ : integer := 8; constant CFG_ILINE : integer := 8; constant CFG_IREPL : integer := 0; constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; constant CFG_ILRAMSZ : integer := 1; constant CFG_DCEN : integer := 1; constant CFG_DSETS : integer := 1; constant CFG_DSETSZ : integer := 4; constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; constant CFG_DLRAMSZ : integer := 1; constant CFG_MMUEN : integer := 1; constant CFG_ITLBNUM : integer := 8; constant CFG_DTLBNUM : integer := 8; constant CFG_TLB_TYPE : integer := 0 + 1*2; constant CFG_TLB_REP : integer := 0; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 1; constant CFG_ITBSZ : integer := 2; constant CFG_ATBSZ : integer := 2; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; constant CFG_RF_ERRINJ : integer := 0; constant CFG_CACHE_FT_EN : integer := 0; constant CFG_CACHE_ERRINJ : integer := 0; constant CFG_LEON3_NETLIST: integer := 0; constant CFG_DISAS : integer := 0 + 0; constant CFG_PCLOW : integer := 2; -- AMBA settings constant CFG_DEFMST : integer := (0); constant CFG_RROBIN : integer := 1; constant CFG_SPLIT : integer := 0; constant CFG_FPNPEN : integer := 0; constant CFG_AHBIO : integer := 16#FFF#; constant CFG_APBADDR : integer := 16#800#; constant CFG_AHB_MON : integer := 0; constant CFG_AHB_MONERR : integer := 0; constant CFG_AHB_MONWAR : integer := 0; constant CFG_AHB_DTRACE : integer := 0; -- DSU UART constant CFG_AHB_UART : integer := 0; -- JTAG based DSU interface constant CFG_AHB_JTAG : integer := 1; -- Ethernet DSU constant CFG_DSU_ETH : integer := 0 + 0 + 0; constant CFG_ETH_BUF : integer := 1; constant CFG_ETH_IPM : integer := 16#C0A8#; constant CFG_ETH_IPL : integer := 16#0033#; constant CFG_ETH_ENM : integer := 16#020000#; constant CFG_ETH_ENL : integer := 16#000009#; -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 1; constant CFG_MCTRL_RAM8BIT : integer := 1; constant CFG_MCTRL_RAM16BIT : integer := 0; constant CFG_MCTRL_5CS : integer := 0; constant CFG_MCTRL_SDEN : integer := 0; constant CFG_MCTRL_SEPBUS : integer := 0; constant CFG_MCTRL_INVCLK : integer := 0; constant CFG_MCTRL_SD64 : integer := 0; constant CFG_MCTRL_PAGE : integer := 0 + 0; -- DDR controller constant CFG_DDR2SP : integer := 0; constant CFG_DDR2SP_INIT : integer := 0; constant CFG_DDR2SP_FREQ : integer := 100; constant CFG_DDR2SP_TRFC : integer := 130; constant CFG_DDR2SP_DATAWIDTH : integer := 64; constant CFG_DDR2SP_FTEN : integer := 0; constant CFG_DDR2SP_FTWIDTH : integer := 0; constant CFG_DDR2SP_COL : integer := 9; constant CFG_DDR2SP_SIZE : integer := 8; constant CFG_DDR2SP_DELAY0 : integer := 0; constant CFG_DDR2SP_DELAY1 : integer := 0; constant CFG_DDR2SP_DELAY2 : integer := 0; constant CFG_DDR2SP_DELAY3 : integer := 0; constant CFG_DDR2SP_DELAY4 : integer := 0; constant CFG_DDR2SP_DELAY5 : integer := 0; constant CFG_DDR2SP_DELAY6 : integer := 0; constant CFG_DDR2SP_DELAY7 : integer := 0; constant CFG_DDR2SP_NOSYNC : integer := 0; -- Xilinx MIG constant CFG_MIG_DDR2 : integer := 1; constant CFG_MIG_RANKS : integer := (1); constant CFG_MIG_COLBITS : integer := (10); constant CFG_MIG_ROWBITS : integer := (13); constant CFG_MIG_BANKBITS: integer := (2); constant CFG_MIG_HMASK : integer := 16#F00#; -- AHB ROM constant CFG_AHBROMEN : integer := 0; constant CFG_AHBROPIP : integer := 0; constant CFG_AHBRODDR : integer := 16#000#; constant CFG_ROMADDR : integer := 16#000#; constant CFG_ROMMASK : integer := 16#E00# + 16#000#; -- AHB RAM constant CFG_AHBRAMEN : integer := 0; constant CFG_AHBRSZ : integer := 1; constant CFG_AHBRADDR : integer := 16#A00#; constant CFG_AHBRPIPE : integer := 0; -- Gaisler Ethernet core constant CFG_GRETH : integer := 1; constant CFG_GRETH1G : integer := 0; constant CFG_ETH_FIFO : integer := 32; -- UART 1 constant CFG_UART1_ENABLE : integer := 1; constant CFG_UART1_FIFO : integer := 4; -- LEON3 interrupt controller constant CFG_IRQ3_ENABLE : integer := 1; constant CFG_IRQ3_NSEC : integer := 0; -- Modular timer constant CFG_GPT_ENABLE : integer := 1; constant CFG_GPT_NTIM : integer := (2); constant CFG_GPT_SW : integer := (8); constant CFG_GPT_TW : integer := (32); constant CFG_GPT_IRQ : integer := (8); constant CFG_GPT_SEPIRQ : integer := 1; constant CFG_GPT_WDOGEN : integer := 0; constant CFG_GPT_WDOG : integer := 16#0#; -- GPIO port constant CFG_GRGPIO_ENABLE : integer := 1; constant CFG_GRGPIO_IMASK : integer := 16#0000#; constant CFG_GRGPIO_WIDTH : integer := (8); -- SPI memory controller constant CFG_SPIMCTRL : integer := 0; constant CFG_SPIMCTRL_SDCARD : integer := 0; constant CFG_SPIMCTRL_READCMD : integer := 16#0#; constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0; constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0; constant CFG_SPIMCTRL_SCALER : integer := 1; constant CFG_SPIMCTRL_ASCALER : integer := 1; constant CFG_SPIMCTRL_PWRUPCNT : integer := 0; constant CFG_SPIMCTRL_OFFSET : integer := 16#0#; -- SPI controller constant CFG_SPICTRL_ENABLE : integer := 0; constant CFG_SPICTRL_NUM : integer := 1; constant CFG_SPICTRL_SLVS : integer := 1; constant CFG_SPICTRL_FIFO : integer := 1; constant CFG_SPICTRL_SLVREG : integer := 0; constant CFG_SPICTRL_ODMODE : integer := 0; constant CFG_SPICTRL_AM : integer := 0; constant CFG_SPICTRL_ASEL : integer := 0; constant CFG_SPICTRL_TWEN : integer := 0; constant CFG_SPICTRL_MAXWLEN : integer := 0; constant CFG_SPICTRL_SYNCRAM : integer := 0; constant CFG_SPICTRL_FT : integer := 0; -- GRLIB debugging constant CFG_DUART : integer := 0; end;

gpl-2.0

9835c8c497790126896958e5a65424eb

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-asic/spw_lvttl_pads.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- -- Copyright (C) 2009-2013, Aeroflex Gaisler AB ------------------------------------------------------------------------------- -- Entity: spw_2x_lvttl_pads -- File: spw_2x_lvttl_pads.vhd -- Author: Marko Isomaki, Aeroflex Gaisler -- Contact: [email protected] -- Description: pads for SpW signals in router ASIC LVTTL ports ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.config.all; library techmap; use techmap.gencomp.all; library grlib; use grlib.stdlib.conv_std_logic; entity spw_lvttl_pads is generic ( padtech : integer := 0; oepol : integer := 0; level : integer := 0; voltage : integer := 0; filter : integer := 0; strength : integer := 4; slew : integer := 0; input_type : integer := 0 ); port ( --------------------------------------------------------------------------- -- Signals going off-chip --------------------------------------------------------------------------- spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1); spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1); spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1); spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1); --------------------------------------------------------------------------- -- Signals to core --------------------------------------------------------------------------- lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1); lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1); lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1); lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1) ); end entity; architecture rtl of spw_lvttl_pads is begin ------------------------------------------------------------------------------ -- SpW port pads ------------------------------------------------------------------------------ spw_pads : for i in 0 to CFG_SPW_NUM-1 generate spw_pad_input: if input_type <= 3 generate spw_rxd_pad : inpad generic map ( tech => padtech, level => level, voltage => voltage, filter => filter, strength => strength) port map ( pad => spw_rxd(i), o => lspw_rxd(i)); spw_rxs_pad : inpad generic map ( tech => padtech, level => level, voltage => voltage, filter => filter, strength => strength) port map ( pad => spw_rxs(i), o => lspw_rxs(i)); end generate; spw_no_pad_input: if input_type >= 4 generate lspw_rxd(i) <= spw_rxd(i); lspw_rxs(i) <= spw_rxs(i); end generate; spw_txd_pad : outpad generic map ( tech => padtech, level => level, slew => slew, voltage => voltage, strength => strength) port map ( pad => spw_txd(i), i => lspw_txd(i)); spw_txs_pad : outpad generic map ( tech => padtech, level => level, slew => slew, voltage => voltage, strength => strength) port map ( pad => spw_txs(i), i => lspw_txs(i)); end generate; end;

gpl-2.0

8f496fb23106a8c86566c0a26306c002

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/techmap/maps/outpad_ddr.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: outpad_ddr, outpad_ddrv -- File: outpad_ddr.vhd -- Author: Jan Andersson - Aeroflex Gaisler -- Description: Wrapper that instantiates a DDR register connected to an -- output pad. The generic tech wrappers are not used for nextreme -- since this technology requires that the output enable signal is -- connected between the DDR register and the pad. ------------------------------------------------------------------------------ library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allddr.all; use techmap.allpads.all; entity outpad_ddr is generic ( tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := x33v; strength : integer := 12 ); port ( pad : out std_ulogic; i1, i2 : in std_ulogic; c1, c2 : in std_ulogic; ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic ); end; architecture rtl of outpad_ddr is signal q, oe, vcc : std_ulogic; begin vcc <= '1'; def: if (tech /= easic90) and (tech /= easic45) generate ddrreg : ddr_oreg generic map (tech) port map (q, c1, c2, ce, i1, i2, r, s); p : outpad generic map (tech, level, slew, voltage, strength) port map (pad, q); oe <= '0'; end generate def; nex : if (tech = easic90) generate ddrreg : nextreme_oddr_reg port map (ck => c1, dh => i1, dl => i2, doe => vcc, q => q, oe => oe, rstb => r); p : nextreme_toutpad generic map (level, slew, voltage, strength) port map(pad, q, oe); end generate; n2x : if (tech = easic45) generate -- ddrpad : n2x_outpad_ddr generic map (level, slew, voltage, strength) -- port map (); --pragma translate_off assert false report "outpad_ddr: Not yet supported on Nextreme2" severity failure; --pragma translate_on q <= '0'; oe <= '0'; end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity outpad_ddrv is generic ( tech : integer := 0; level : integer := 0; slew : integer := 0; voltage : integer := 0; strength : integer := 12; width : integer := 1 ); port ( pad : out std_logic_vector(width-1 downto 0); i1, i2 : in std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic; ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic ); end; architecture rtl of outpad_ddrv is begin v : for j in width-1 downto 0 generate x0 : outpad_ddr generic map (tech, level, slew, voltage, strength) port map (pad(j), i1(j), i2(j), c1, c2, ce, r, s); end generate; end;

gpl-2.0

b7dfe212c5aa90933655c205ae3de39c

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_1/zqynq_lab_1_design_axi_timer_0_1_sim_netlist.vhdl

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Fri Sep 22 23:00:38 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_1/zqynq_lab_1_design_axi_timer_0_1_sim_netlist.vhdl -- Design : zqynq_lab_1_design_axi_timer_0_1 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_cdc_sync is port ( captureTrig0_d0 : out STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 ); capturetrig0 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_cdc_sync : entity is "cdc_sync"; end zqynq_lab_1_design_axi_timer_0_1_cdc_sync; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_cdc_sync is signal CaptureTrig0_int : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute BOX_TYPE : string; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; begin \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => capturetrig0, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d3, Q => CaptureTrig0_int, R => '0' ); captureTrig0_d_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => read_Mux_In(0), I1 => CaptureTrig0_int, O => captureTrig0_d0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1 is port ( captureTrig1_d0 : out STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 ); capturetrig1 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1 : entity is "cdc_sync"; end zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1 is signal CaptureTrig1_int : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute BOX_TYPE : string; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; begin \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => capturetrig1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d3, Q => CaptureTrig1_int, R => '0' ); captureTrig1_d_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => read_Mux_In(0), I1 => CaptureTrig1_int, O => captureTrig1_d0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2 is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); \INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); S : out STD_LOGIC_VECTOR ( 0 to 0 ); \INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC; counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 ); read_Mux_In : in STD_LOGIC_VECTOR ( 7 downto 0 ); generateOutPre0 : in STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC; Load_Counter_Reg030_out : in STD_LOGIC; Load_Counter_Reg031_out : in STD_LOGIC; \Load_Counter_Reg0__0\ : in STD_LOGIC; Load_Counter_Reg028_out : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); freeze : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2 : entity is "cdc_sync"; end zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2 is signal \Counter_En041_out__2\ : STD_LOGIC; signal \Counter_En043_out__0\ : STD_LOGIC; signal \Counter_En045_out__1\ : STD_LOGIC; signal \Counter_En0__4\ : STD_LOGIC; signal Freeze_int : STD_LOGIC; signal counter_En : STD_LOGIC_VECTOR ( 0 to 1 ); signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute BOX_TYPE : string; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; begin \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => freeze, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d3, Q => Freeze_int, R => '0' ); \INFERRED_GEN.icount_out[31]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FCFFFCAA" ) port map ( I0 => Load_Counter_Reg030_out, I1 => Load_Counter_Reg031_out, I2 => \Counter_En043_out__0\, I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\, I4 => \Counter_En041_out__2\, O => E(0) ); \INFERRED_GEN.icount_out[31]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FCFFFCAA" ) port map ( I0 => \Load_Counter_Reg0__0\, I1 => Load_Counter_Reg028_out, I2 => \Counter_En045_out__1\, I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\, I4 => \Counter_En0__4\, O => \INFERRED_GEN.icount_out_reg[0]\(0) ); \INFERRED_GEN.icount_out[31]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"00FB0000" ) port map ( I0 => read_Mux_In(4), I1 => counter_TC(1), I2 => read_Mux_In(6), I3 => Freeze_int, I4 => \TCSR0_GENERATE[24].TCSR0_FF_I\, O => \Counter_En043_out__0\ ); \INFERRED_GEN.icount_out[31]_i_5__0\: unisim.vcomponents.LUT6 generic map( INIT => X"4040404040004040" ) port map ( I0 => Freeze_int, I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\, I2 => generateOutPre0, I3 => read_Mux_In(6), I4 => counter_TC(1), I5 => read_Mux_In(4), O => \Counter_En045_out__1\ ); \INFERRED_GEN.icount_out[31]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"4444444444444404" ) port map ( I0 => Freeze_int, I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\, I2 => counter_TC(0), I3 => read_Mux_In(7), I4 => read_Mux_In(6), I5 => read_Mux_In(4), O => \Counter_En041_out__2\ ); \INFERRED_GEN.icount_out[31]_i_6__0\: unisim.vcomponents.LUT6 generic map( INIT => X"2222222222202222" ) port map ( I0 => \TCSR1_GENERATE[24].TCSR1_FF_I\, I1 => Freeze_int, I2 => read_Mux_In(3), I3 => read_Mux_In(2), I4 => counter_TC(1), I5 => read_Mux_In(0), O => \Counter_En0__4\ ); icount_out0_carry_i_5: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \INFERRED_GEN.icount_out_reg[1]\(1), I1 => counter_En(0), I2 => read_Mux_In(5), O => S(0) ); \icount_out0_carry_i_5__0\: unisim.vcomponents.LUT5 generic map( INIT => X"6A666AAA" ) port map ( I0 => \INFERRED_GEN.icount_out_reg[1]\(0), I1 => counter_En(1), I2 => read_Mux_In(5), I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\, I4 => read_Mux_In(1), O => \INFERRED_GEN.icount_out_reg[4]\(0) ); icount_out0_carry_i_6: unisim.vcomponents.MUXF7 port map ( I0 => \Counter_En041_out__2\, I1 => \Counter_En043_out__0\, O => counter_En(0), S => \TCSR0_GENERATE[20].TCSR0_FF_I\ ); \icount_out0_carry_i_6__0\: unisim.vcomponents.MUXF7 port map ( I0 => \Counter_En0__4\, I1 => \Counter_En045_out__1\, O => counter_En(1), S => \TCSR0_GENERATE[20].TCSR0_FF_I\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_counter_f is port ( Q : out STD_LOGIC_VECTOR ( 31 downto 0 ); SR : out STD_LOGIC_VECTOR ( 0 to 0 ); \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[1]\ : out STD_LOGIC; \s_axi_rdata_i_reg[2]\ : out STD_LOGIC; \s_axi_rdata_i_reg[3]\ : out STD_LOGIC; \s_axi_rdata_i_reg[4]\ : out STD_LOGIC; \s_axi_rdata_i_reg[5]\ : out STD_LOGIC; \s_axi_rdata_i_reg[6]\ : out STD_LOGIC; \s_axi_rdata_i_reg[7]\ : out STD_LOGIC; \s_axi_rdata_i_reg[8]\ : out STD_LOGIC; \s_axi_rdata_i_reg[9]\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; \s_axi_rdata_i_reg[11]\ : out STD_LOGIC; \s_axi_rdata_i_reg[12]\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC; generateOutPre1_reg : out STD_LOGIC; counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 ); S : in STD_LOGIC_VECTOR ( 0 to 0 ); read_Mux_In : in STD_LOGIC_VECTOR ( 31 downto 0 ); load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_counter_f : entity is "counter_f"; end zqynq_lab_1_design_axi_timer_0_1_counter_f; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_counter_f is signal \INFERRED_GEN.icount_out[0]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[10]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[11]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[12]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[13]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[14]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[15]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[16]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[17]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[18]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[19]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[1]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[20]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[21]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[22]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[23]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[24]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[25]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[26]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[27]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[28]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[29]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[2]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[30]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[31]_i_2_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[3]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[4]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[5]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[6]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[7]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[8]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[9]_i_1_n_0\ : STD_LOGIC; signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \icount_out0_carry__0_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_n_1\ : STD_LOGIC; signal \icount_out0_carry__0_n_2\ : STD_LOGIC; signal \icount_out0_carry__0_n_3\ : STD_LOGIC; signal \icount_out0_carry__0_n_4\ : STD_LOGIC; signal \icount_out0_carry__0_n_5\ : STD_LOGIC; signal \icount_out0_carry__0_n_6\ : STD_LOGIC; signal \icount_out0_carry__0_n_7\ : STD_LOGIC; signal \icount_out0_carry__1_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_n_1\ : STD_LOGIC; signal \icount_out0_carry__1_n_2\ : STD_LOGIC; signal \icount_out0_carry__1_n_3\ : STD_LOGIC; signal \icount_out0_carry__1_n_4\ : STD_LOGIC; signal \icount_out0_carry__1_n_5\ : STD_LOGIC; signal \icount_out0_carry__1_n_6\ : STD_LOGIC; signal \icount_out0_carry__1_n_7\ : STD_LOGIC; signal \icount_out0_carry__2_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_n_1\ : STD_LOGIC; signal \icount_out0_carry__2_n_2\ : STD_LOGIC; signal \icount_out0_carry__2_n_3\ : STD_LOGIC; signal \icount_out0_carry__2_n_4\ : STD_LOGIC; signal \icount_out0_carry__2_n_5\ : STD_LOGIC; signal \icount_out0_carry__2_n_6\ : STD_LOGIC; signal \icount_out0_carry__2_n_7\ : STD_LOGIC; signal \icount_out0_carry__3_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_n_1\ : STD_LOGIC; signal \icount_out0_carry__3_n_2\ : STD_LOGIC; signal \icount_out0_carry__3_n_3\ : STD_LOGIC; signal \icount_out0_carry__3_n_4\ : STD_LOGIC; signal \icount_out0_carry__3_n_5\ : STD_LOGIC; signal \icount_out0_carry__3_n_6\ : STD_LOGIC; signal \icount_out0_carry__3_n_7\ : STD_LOGIC; signal \icount_out0_carry__4_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_n_1\ : STD_LOGIC; signal \icount_out0_carry__4_n_2\ : STD_LOGIC; signal \icount_out0_carry__4_n_3\ : STD_LOGIC; signal \icount_out0_carry__4_n_4\ : STD_LOGIC; signal \icount_out0_carry__4_n_5\ : STD_LOGIC; signal \icount_out0_carry__4_n_6\ : STD_LOGIC; signal \icount_out0_carry__4_n_7\ : STD_LOGIC; signal \icount_out0_carry__5_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_n_1\ : STD_LOGIC; signal \icount_out0_carry__5_n_2\ : STD_LOGIC; signal \icount_out0_carry__5_n_3\ : STD_LOGIC; signal \icount_out0_carry__5_n_4\ : STD_LOGIC; signal \icount_out0_carry__5_n_5\ : STD_LOGIC; signal \icount_out0_carry__5_n_6\ : STD_LOGIC; signal \icount_out0_carry__5_n_7\ : STD_LOGIC; signal \icount_out0_carry__6_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_n_1\ : STD_LOGIC; signal \icount_out0_carry__6_n_2\ : STD_LOGIC; signal \icount_out0_carry__6_n_3\ : STD_LOGIC; signal \icount_out0_carry__6_n_4\ : STD_LOGIC; signal \icount_out0_carry__6_n_5\ : STD_LOGIC; signal \icount_out0_carry__6_n_6\ : STD_LOGIC; signal \icount_out0_carry__6_n_7\ : STD_LOGIC; signal icount_out0_carry_i_1_n_0 : STD_LOGIC; signal icount_out0_carry_i_2_n_0 : STD_LOGIC; signal icount_out0_carry_i_3_n_0 : STD_LOGIC; signal icount_out0_carry_i_4_n_0 : STD_LOGIC; signal icount_out0_carry_n_0 : STD_LOGIC; signal icount_out0_carry_n_1 : STD_LOGIC; signal icount_out0_carry_n_2 : STD_LOGIC; signal icount_out0_carry_n_3 : STD_LOGIC; signal icount_out0_carry_n_4 : STD_LOGIC; signal icount_out0_carry_n_5 : STD_LOGIC; signal icount_out0_carry_n_6 : STD_LOGIC; signal icount_out0_carry_n_7 : STD_LOGIC; signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1\ : label is "soft_lutpair45"; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(31 downto 0) <= \^q\(31 downto 0); SR(0) <= \^sr\(0); counter_TC(0) <= \^counter_tc\(0); \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(31), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(31), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(31), O => \s_axi_rdata_i_reg[31]\ ); \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(21), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(21), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(21), O => \s_axi_rdata_i_reg[21]\ ); \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(20), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(20), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(20), O => \s_axi_rdata_i_reg[20]\ ); \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(19), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(19), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(19), O => \s_axi_rdata_i_reg[19]\ ); \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(18), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(18), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(18), O => \s_axi_rdata_i_reg[18]\ ); \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(17), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(17), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(17), O => \s_axi_rdata_i_reg[17]\ ); \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(16), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(16), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(16), O => \s_axi_rdata_i_reg[16]\ ); \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(15), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(15), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(15), O => \s_axi_rdata_i_reg[15]\ ); \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(14), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(14), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(14), O => \s_axi_rdata_i_reg[14]\ ); \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(13), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(13), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(13), O => \s_axi_rdata_i_reg[13]\ ); \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(12), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(12), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(12), O => \s_axi_rdata_i_reg[12]\ ); \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(30), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(30), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(30), O => \s_axi_rdata_i_reg[30]\ ); \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(11), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(11), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(11), O => \s_axi_rdata_i_reg[11]\ ); \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(10), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(10), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(10), O => \s_axi_rdata_i_reg[10]\ ); \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(9), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(9), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(9), O => \s_axi_rdata_i_reg[9]\ ); \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(8), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(8), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(8), O => \s_axi_rdata_i_reg[8]\ ); \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(7), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(7), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(7), O => \s_axi_rdata_i_reg[7]\ ); \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(6), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(6), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(6), O => \s_axi_rdata_i_reg[6]\ ); \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(5), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(5), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(5), O => \s_axi_rdata_i_reg[5]\ ); \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(4), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(4), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(4), O => \s_axi_rdata_i_reg[4]\ ); \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(3), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(3), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(3), O => \s_axi_rdata_i_reg[3]\ ); \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(2), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(2), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(2), O => \s_axi_rdata_i_reg[2]\ ); \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(29), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(29), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(29), O => \s_axi_rdata_i_reg[29]\ ); \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(1), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(1), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(1), O => \s_axi_rdata_i_reg[1]\ ); \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(0), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(0), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(0), O => \s_axi_rdata_i_reg[0]\ ); \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(28), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(28), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(28), O => \s_axi_rdata_i_reg[28]\ ); \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(27), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(27), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(27), O => \s_axi_rdata_i_reg[27]\ ); \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(26), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(26), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(26), O => \s_axi_rdata_i_reg[26]\ ); \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(25), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(25), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(25), O => \s_axi_rdata_i_reg[25]\ ); \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(24), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(24), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(24), O => \s_axi_rdata_i_reg[24]\ ); \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(23), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(23), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(23), O => \s_axi_rdata_i_reg[23]\ ); \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(22), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(22), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(22), O => \s_axi_rdata_i_reg[22]\ ); GenerateOut0_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => s_axi_aresetn, O => \^sr\(0) ); \INFERRED_GEN.icount_out[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"A3" ) port map ( I0 => read_Mux_In(0), I1 => \^q\(0), I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[0]_i_1_n_0\ ); \INFERRED_GEN.icount_out[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(10), I1 => \icount_out0_carry__1_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[10]_i_1_n_0\ ); \INFERRED_GEN.icount_out[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(11), I1 => \icount_out0_carry__1_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[11]_i_1_n_0\ ); \INFERRED_GEN.icount_out[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(12), I1 => \icount_out0_carry__1_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[12]_i_1_n_0\ ); \INFERRED_GEN.icount_out[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(13), I1 => \icount_out0_carry__2_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[13]_i_1_n_0\ ); \INFERRED_GEN.icount_out[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(14), I1 => \icount_out0_carry__2_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[14]_i_1_n_0\ ); \INFERRED_GEN.icount_out[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(15), I1 => \icount_out0_carry__2_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[15]_i_1_n_0\ ); \INFERRED_GEN.icount_out[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(16), I1 => \icount_out0_carry__2_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[16]_i_1_n_0\ ); \INFERRED_GEN.icount_out[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(17), I1 => \icount_out0_carry__3_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[17]_i_1_n_0\ ); \INFERRED_GEN.icount_out[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(18), I1 => \icount_out0_carry__3_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[18]_i_1_n_0\ ); \INFERRED_GEN.icount_out[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(19), I1 => \icount_out0_carry__3_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[19]_i_1_n_0\ ); \INFERRED_GEN.icount_out[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(1), I1 => icount_out0_carry_n_7, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[1]_i_1_n_0\ ); \INFERRED_GEN.icount_out[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(20), I1 => \icount_out0_carry__3_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[20]_i_1_n_0\ ); \INFERRED_GEN.icount_out[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(21), I1 => \icount_out0_carry__4_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[21]_i_1_n_0\ ); \INFERRED_GEN.icount_out[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(22), I1 => \icount_out0_carry__4_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[22]_i_1_n_0\ ); \INFERRED_GEN.icount_out[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(23), I1 => \icount_out0_carry__4_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[23]_i_1_n_0\ ); \INFERRED_GEN.icount_out[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(24), I1 => \icount_out0_carry__4_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[24]_i_1_n_0\ ); \INFERRED_GEN.icount_out[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(25), I1 => \icount_out0_carry__5_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[25]_i_1_n_0\ ); \INFERRED_GEN.icount_out[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(26), I1 => \icount_out0_carry__5_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[26]_i_1_n_0\ ); \INFERRED_GEN.icount_out[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(27), I1 => \icount_out0_carry__5_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[27]_i_1_n_0\ ); \INFERRED_GEN.icount_out[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(28), I1 => \icount_out0_carry__5_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[28]_i_1_n_0\ ); \INFERRED_GEN.icount_out[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(29), I1 => \icount_out0_carry__6_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[29]_i_1_n_0\ ); \INFERRED_GEN.icount_out[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(2), I1 => icount_out0_carry_n_6, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[2]_i_1_n_0\ ); \INFERRED_GEN.icount_out[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(30), I1 => \icount_out0_carry__6_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[30]_i_1_n_0\ ); \INFERRED_GEN.icount_out[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(31), I1 => \icount_out0_carry__6_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[31]_i_2_n_0\ ); \INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0000E200" ) port map ( I0 => \^counter_tc\(0), I1 => E(0), I2 => \icount_out0_carry__6_n_4\, I3 => s_axi_aresetn, I4 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[32]_i_1_n_0\ ); \INFERRED_GEN.icount_out[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(3), I1 => icount_out0_carry_n_5, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[3]_i_1_n_0\ ); \INFERRED_GEN.icount_out[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(4), I1 => icount_out0_carry_n_4, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[4]_i_1_n_0\ ); \INFERRED_GEN.icount_out[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(5), I1 => \icount_out0_carry__0_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[5]_i_1_n_0\ ); \INFERRED_GEN.icount_out[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(6), I1 => \icount_out0_carry__0_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[6]_i_1_n_0\ ); \INFERRED_GEN.icount_out[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(7), I1 => \icount_out0_carry__0_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[7]_i_1_n_0\ ); \INFERRED_GEN.icount_out[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(8), I1 => \icount_out0_carry__0_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[8]_i_1_n_0\ ); \INFERRED_GEN.icount_out[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(9), I1 => \icount_out0_carry__1_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[9]_i_1_n_0\ ); \INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[0]_i_1_n_0\, Q => \^q\(0), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[10]_i_1_n_0\, Q => \^q\(10), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[11]_i_1_n_0\, Q => \^q\(11), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[12]_i_1_n_0\, Q => \^q\(12), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[13]_i_1_n_0\, Q => \^q\(13), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[14]_i_1_n_0\, Q => \^q\(14), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[15]_i_1_n_0\, Q => \^q\(15), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[16]_i_1_n_0\, Q => \^q\(16), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[17]_i_1_n_0\, Q => \^q\(17), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[18]_i_1_n_0\, Q => \^q\(18), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[19]_i_1_n_0\, Q => \^q\(19), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[1]_i_1_n_0\, Q => \^q\(1), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[20]_i_1_n_0\, Q => \^q\(20), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[21]_i_1_n_0\, Q => \^q\(21), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[22]_i_1_n_0\, Q => \^q\(22), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[23]_i_1_n_0\, Q => \^q\(23), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[24]_i_1_n_0\, Q => \^q\(24), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[25]_i_1_n_0\, Q => \^q\(25), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[26]_i_1_n_0\, Q => \^q\(26), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[27]_i_1_n_0\, Q => \^q\(27), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[28]_i_1_n_0\, Q => \^q\(28), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[29]_i_1_n_0\, Q => \^q\(29), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[2]_i_1_n_0\, Q => \^q\(2), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[30]_i_1_n_0\, Q => \^q\(30), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[31]_i_2_n_0\, Q => \^q\(31), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \INFERRED_GEN.icount_out[32]_i_1_n_0\, Q => \^counter_tc\(0), R => '0' ); \INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[3]_i_1_n_0\, Q => \^q\(3), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[4]_i_1_n_0\, Q => \^q\(4), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[5]_i_1_n_0\, Q => \^q\(5), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[6]_i_1_n_0\, Q => \^q\(6), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[7]_i_1_n_0\, Q => \^q\(7), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[8]_i_1_n_0\, Q => \^q\(8), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[9]_i_1_n_0\, Q => \^q\(9), R => \^sr\(0) ); generateOutPre1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^counter_tc\(0), I1 => \counter_TC_Reg_reg[1]\(0), O => generateOutPre1_reg ); icount_out0_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => icount_out0_carry_n_0, CO(2) => icount_out0_carry_n_1, CO(1) => icount_out0_carry_n_2, CO(0) => icount_out0_carry_n_3, CYINIT => \^q\(0), DI(3 downto 1) => \^q\(3 downto 1), DI(0) => icount_out0_carry_i_1_n_0, O(3) => icount_out0_carry_n_4, O(2) => icount_out0_carry_n_5, O(1) => icount_out0_carry_n_6, O(0) => icount_out0_carry_n_7, S(3) => icount_out0_carry_i_2_n_0, S(2) => icount_out0_carry_i_3_n_0, S(1) => icount_out0_carry_i_4_n_0, S(0) => S(0) ); \icount_out0_carry__0\: unisim.vcomponents.CARRY4 port map ( CI => icount_out0_carry_n_0, CO(3) => \icount_out0_carry__0_n_0\, CO(2) => \icount_out0_carry__0_n_1\, CO(1) => \icount_out0_carry__0_n_2\, CO(0) => \icount_out0_carry__0_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(7 downto 4), O(3) => \icount_out0_carry__0_n_4\, O(2) => \icount_out0_carry__0_n_5\, O(1) => \icount_out0_carry__0_n_6\, O(0) => \icount_out0_carry__0_n_7\, S(3) => \icount_out0_carry__0_i_1_n_0\, S(2) => \icount_out0_carry__0_i_2_n_0\, S(1) => \icount_out0_carry__0_i_3_n_0\, S(0) => \icount_out0_carry__0_i_4_n_0\ ); \icount_out0_carry__0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \^q\(8), O => \icount_out0_carry__0_i_1_n_0\ ); \icount_out0_carry__0_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \^q\(7), O => \icount_out0_carry__0_i_2_n_0\ ); \icount_out0_carry__0_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \^q\(6), O => \icount_out0_carry__0_i_3_n_0\ ); \icount_out0_carry__0_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \^q\(5), O => \icount_out0_carry__0_i_4_n_0\ ); \icount_out0_carry__1\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__0_n_0\, CO(3) => \icount_out0_carry__1_n_0\, CO(2) => \icount_out0_carry__1_n_1\, CO(1) => \icount_out0_carry__1_n_2\, CO(0) => \icount_out0_carry__1_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(11 downto 8), O(3) => \icount_out0_carry__1_n_4\, O(2) => \icount_out0_carry__1_n_5\, O(1) => \icount_out0_carry__1_n_6\, O(0) => \icount_out0_carry__1_n_7\, S(3) => \icount_out0_carry__1_i_1_n_0\, S(2) => \icount_out0_carry__1_i_2_n_0\, S(1) => \icount_out0_carry__1_i_3_n_0\, S(0) => \icount_out0_carry__1_i_4_n_0\ ); \icount_out0_carry__1_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(11), I1 => \^q\(12), O => \icount_out0_carry__1_i_1_n_0\ ); \icount_out0_carry__1_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(10), I1 => \^q\(11), O => \icount_out0_carry__1_i_2_n_0\ ); \icount_out0_carry__1_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(9), I1 => \^q\(10), O => \icount_out0_carry__1_i_3_n_0\ ); \icount_out0_carry__1_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \^q\(9), O => \icount_out0_carry__1_i_4_n_0\ ); \icount_out0_carry__2\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__1_n_0\, CO(3) => \icount_out0_carry__2_n_0\, CO(2) => \icount_out0_carry__2_n_1\, CO(1) => \icount_out0_carry__2_n_2\, CO(0) => \icount_out0_carry__2_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(15 downto 12), O(3) => \icount_out0_carry__2_n_4\, O(2) => \icount_out0_carry__2_n_5\, O(1) => \icount_out0_carry__2_n_6\, O(0) => \icount_out0_carry__2_n_7\, S(3) => \icount_out0_carry__2_i_1_n_0\, S(2) => \icount_out0_carry__2_i_2_n_0\, S(1) => \icount_out0_carry__2_i_3_n_0\, S(0) => \icount_out0_carry__2_i_4_n_0\ ); \icount_out0_carry__2_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(15), I1 => \^q\(16), O => \icount_out0_carry__2_i_1_n_0\ ); \icount_out0_carry__2_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(14), I1 => \^q\(15), O => \icount_out0_carry__2_i_2_n_0\ ); \icount_out0_carry__2_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(13), I1 => \^q\(14), O => \icount_out0_carry__2_i_3_n_0\ ); \icount_out0_carry__2_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(12), I1 => \^q\(13), O => \icount_out0_carry__2_i_4_n_0\ ); \icount_out0_carry__3\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__2_n_0\, CO(3) => \icount_out0_carry__3_n_0\, CO(2) => \icount_out0_carry__3_n_1\, CO(1) => \icount_out0_carry__3_n_2\, CO(0) => \icount_out0_carry__3_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(19 downto 16), O(3) => \icount_out0_carry__3_n_4\, O(2) => \icount_out0_carry__3_n_5\, O(1) => \icount_out0_carry__3_n_6\, O(0) => \icount_out0_carry__3_n_7\, S(3) => \icount_out0_carry__3_i_1_n_0\, S(2) => \icount_out0_carry__3_i_2_n_0\, S(1) => \icount_out0_carry__3_i_3_n_0\, S(0) => \icount_out0_carry__3_i_4_n_0\ ); \icount_out0_carry__3_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(19), I1 => \^q\(20), O => \icount_out0_carry__3_i_1_n_0\ ); \icount_out0_carry__3_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(18), I1 => \^q\(19), O => \icount_out0_carry__3_i_2_n_0\ ); \icount_out0_carry__3_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(17), I1 => \^q\(18), O => \icount_out0_carry__3_i_3_n_0\ ); \icount_out0_carry__3_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(16), I1 => \^q\(17), O => \icount_out0_carry__3_i_4_n_0\ ); \icount_out0_carry__4\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__3_n_0\, CO(3) => \icount_out0_carry__4_n_0\, CO(2) => \icount_out0_carry__4_n_1\, CO(1) => \icount_out0_carry__4_n_2\, CO(0) => \icount_out0_carry__4_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(23 downto 20), O(3) => \icount_out0_carry__4_n_4\, O(2) => \icount_out0_carry__4_n_5\, O(1) => \icount_out0_carry__4_n_6\, O(0) => \icount_out0_carry__4_n_7\, S(3) => \icount_out0_carry__4_i_1_n_0\, S(2) => \icount_out0_carry__4_i_2_n_0\, S(1) => \icount_out0_carry__4_i_3_n_0\, S(0) => \icount_out0_carry__4_i_4_n_0\ ); \icount_out0_carry__4_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(23), I1 => \^q\(24), O => \icount_out0_carry__4_i_1_n_0\ ); \icount_out0_carry__4_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(22), I1 => \^q\(23), O => \icount_out0_carry__4_i_2_n_0\ ); \icount_out0_carry__4_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(21), I1 => \^q\(22), O => \icount_out0_carry__4_i_3_n_0\ ); \icount_out0_carry__4_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(20), I1 => \^q\(21), O => \icount_out0_carry__4_i_4_n_0\ ); \icount_out0_carry__5\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__4_n_0\, CO(3) => \icount_out0_carry__5_n_0\, CO(2) => \icount_out0_carry__5_n_1\, CO(1) => \icount_out0_carry__5_n_2\, CO(0) => \icount_out0_carry__5_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(27 downto 24), O(3) => \icount_out0_carry__5_n_4\, O(2) => \icount_out0_carry__5_n_5\, O(1) => \icount_out0_carry__5_n_6\, O(0) => \icount_out0_carry__5_n_7\, S(3) => \icount_out0_carry__5_i_1_n_0\, S(2) => \icount_out0_carry__5_i_2_n_0\, S(1) => \icount_out0_carry__5_i_3_n_0\, S(0) => \icount_out0_carry__5_i_4_n_0\ ); \icount_out0_carry__5_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(27), I1 => \^q\(28), O => \icount_out0_carry__5_i_1_n_0\ ); \icount_out0_carry__5_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(26), I1 => \^q\(27), O => \icount_out0_carry__5_i_2_n_0\ ); \icount_out0_carry__5_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(25), I1 => \^q\(26), O => \icount_out0_carry__5_i_3_n_0\ ); \icount_out0_carry__5_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(24), I1 => \^q\(25), O => \icount_out0_carry__5_i_4_n_0\ ); \icount_out0_carry__6\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__5_n_0\, CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3), CO(2) => \icount_out0_carry__6_n_1\, CO(1) => \icount_out0_carry__6_n_2\, CO(0) => \icount_out0_carry__6_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => \^q\(30 downto 28), O(3) => \icount_out0_carry__6_n_4\, O(2) => \icount_out0_carry__6_n_5\, O(1) => \icount_out0_carry__6_n_6\, O(0) => \icount_out0_carry__6_n_7\, S(3) => \icount_out0_carry__6_i_1_n_0\, S(2) => \icount_out0_carry__6_i_2_n_0\, S(1) => \icount_out0_carry__6_i_3_n_0\, S(0) => \icount_out0_carry__6_i_4_n_0\ ); \icount_out0_carry__6_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(31), O => \icount_out0_carry__6_i_1_n_0\ ); \icount_out0_carry__6_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(30), I1 => \^q\(31), O => \icount_out0_carry__6_i_2_n_0\ ); \icount_out0_carry__6_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(29), I1 => \^q\(30), O => \icount_out0_carry__6_i_3_n_0\ ); \icount_out0_carry__6_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(28), I1 => \^q\(29), O => \icount_out0_carry__6_i_4_n_0\ ); icount_out0_carry_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(1), O => icount_out0_carry_i_1_n_0 ); icount_out0_carry_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \^q\(4), O => icount_out0_carry_i_2_n_0 ); icount_out0_carry_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \^q\(3), O => icount_out0_carry_i_3_n_0 ); icount_out0_carry_i_4: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \^q\(2), O => icount_out0_carry_i_4_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_counter_f_3 is port ( \LOAD_REG_GEN[0].LOAD_REG_I\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); generateOutPre0_reg : out STD_LOGIC; counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 ); S : in STD_LOGIC_VECTOR ( 0 to 0 ); read_Mux_In : in STD_LOGIC_VECTOR ( 10 downto 0 ); load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \LOAD_REG_GEN[0].LOAD_REG_I_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 ); Q : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_counter_f_3 : entity is "counter_f"; end zqynq_lab_1_design_axi_timer_0_1_counter_f_3; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_counter_f_3 is signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC; signal \^load_reg_gen[0].load_reg_i\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \icount_out0_carry__0_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_n_1\ : STD_LOGIC; signal \icount_out0_carry__0_n_2\ : STD_LOGIC; signal \icount_out0_carry__0_n_3\ : STD_LOGIC; signal \icount_out0_carry__0_n_4\ : STD_LOGIC; signal \icount_out0_carry__0_n_5\ : STD_LOGIC; signal \icount_out0_carry__0_n_6\ : STD_LOGIC; signal \icount_out0_carry__0_n_7\ : STD_LOGIC; signal \icount_out0_carry__1_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_n_1\ : STD_LOGIC; signal \icount_out0_carry__1_n_2\ : STD_LOGIC; signal \icount_out0_carry__1_n_3\ : STD_LOGIC; signal \icount_out0_carry__1_n_4\ : STD_LOGIC; signal \icount_out0_carry__1_n_5\ : STD_LOGIC; signal \icount_out0_carry__1_n_6\ : STD_LOGIC; signal \icount_out0_carry__1_n_7\ : STD_LOGIC; signal \icount_out0_carry__2_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_n_1\ : STD_LOGIC; signal \icount_out0_carry__2_n_2\ : STD_LOGIC; signal \icount_out0_carry__2_n_3\ : STD_LOGIC; signal \icount_out0_carry__2_n_4\ : STD_LOGIC; signal \icount_out0_carry__2_n_5\ : STD_LOGIC; signal \icount_out0_carry__2_n_6\ : STD_LOGIC; signal \icount_out0_carry__2_n_7\ : STD_LOGIC; signal \icount_out0_carry__3_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_n_1\ : STD_LOGIC; signal \icount_out0_carry__3_n_2\ : STD_LOGIC; signal \icount_out0_carry__3_n_3\ : STD_LOGIC; signal \icount_out0_carry__3_n_4\ : STD_LOGIC; signal \icount_out0_carry__3_n_5\ : STD_LOGIC; signal \icount_out0_carry__3_n_6\ : STD_LOGIC; signal \icount_out0_carry__3_n_7\ : STD_LOGIC; signal \icount_out0_carry__4_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_n_1\ : STD_LOGIC; signal \icount_out0_carry__4_n_2\ : STD_LOGIC; signal \icount_out0_carry__4_n_3\ : STD_LOGIC; signal \icount_out0_carry__4_n_4\ : STD_LOGIC; signal \icount_out0_carry__4_n_5\ : STD_LOGIC; signal \icount_out0_carry__4_n_6\ : STD_LOGIC; signal \icount_out0_carry__4_n_7\ : STD_LOGIC; signal \icount_out0_carry__5_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_n_1\ : STD_LOGIC; signal \icount_out0_carry__5_n_2\ : STD_LOGIC; signal \icount_out0_carry__5_n_3\ : STD_LOGIC; signal \icount_out0_carry__5_n_4\ : STD_LOGIC; signal \icount_out0_carry__5_n_5\ : STD_LOGIC; signal \icount_out0_carry__5_n_6\ : STD_LOGIC; signal \icount_out0_carry__5_n_7\ : STD_LOGIC; signal \icount_out0_carry__6_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_n_1\ : STD_LOGIC; signal \icount_out0_carry__6_n_2\ : STD_LOGIC; signal \icount_out0_carry__6_n_3\ : STD_LOGIC; signal \icount_out0_carry__6_n_4\ : STD_LOGIC; signal \icount_out0_carry__6_n_5\ : STD_LOGIC; signal \icount_out0_carry__6_n_6\ : STD_LOGIC; signal \icount_out0_carry__6_n_7\ : STD_LOGIC; signal \icount_out0_carry_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry_i_4__0_n_0\ : STD_LOGIC; signal icount_out0_carry_n_0 : STD_LOGIC; signal icount_out0_carry_n_1 : STD_LOGIC; signal icount_out0_carry_n_2 : STD_LOGIC; signal icount_out0_carry_n_3 : STD_LOGIC; signal icount_out0_carry_n_4 : STD_LOGIC; signal icount_out0_carry_n_5 : STD_LOGIC; signal icount_out0_carry_n_6 : STD_LOGIC; signal icount_out0_carry_n_7 : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1__0\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1__0\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1__0\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1__0\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1__0\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2__0\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1__0\ : label is "soft_lutpair29"; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}"; begin \LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) <= \^load_reg_gen[0].load_reg_i\(31 downto 0); counter_TC(0) <= \^counter_tc\(0); \INFERRED_GEN.icount_out[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => read_Mux_In(0), I1 => load_Counter_Reg(0), I2 => \^load_reg_gen[0].load_reg_i\(0), O => p_1_in(0) ); \INFERRED_GEN.icount_out[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(10), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__1_n_6\, O => p_1_in(10) ); \INFERRED_GEN.icount_out[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(0), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__1_n_5\, O => p_1_in(11) ); \INFERRED_GEN.icount_out[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(1), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__1_n_4\, O => p_1_in(12) ); \INFERRED_GEN.icount_out[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(2), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__2_n_7\, O => p_1_in(13) ); \INFERRED_GEN.icount_out[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(3), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__2_n_6\, O => p_1_in(14) ); \INFERRED_GEN.icount_out[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(4), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__2_n_5\, O => p_1_in(15) ); \INFERRED_GEN.icount_out[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(5), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__2_n_4\, O => p_1_in(16) ); \INFERRED_GEN.icount_out[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(6), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__3_n_7\, O => p_1_in(17) ); \INFERRED_GEN.icount_out[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(7), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__3_n_6\, O => p_1_in(18) ); \INFERRED_GEN.icount_out[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(8), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__3_n_5\, O => p_1_in(19) ); \INFERRED_GEN.icount_out[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(1), I1 => load_Counter_Reg(0), I2 => icount_out0_carry_n_7, O => p_1_in(1) ); \INFERRED_GEN.icount_out[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(9), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__3_n_4\, O => p_1_in(20) ); \INFERRED_GEN.icount_out[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(10), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__4_n_7\, O => p_1_in(21) ); \INFERRED_GEN.icount_out[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(11), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__4_n_6\, O => p_1_in(22) ); \INFERRED_GEN.icount_out[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(12), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__4_n_5\, O => p_1_in(23) ); \INFERRED_GEN.icount_out[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(13), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__4_n_4\, O => p_1_in(24) ); \INFERRED_GEN.icount_out[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(14), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__5_n_7\, O => p_1_in(25) ); \INFERRED_GEN.icount_out[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(15), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__5_n_6\, O => p_1_in(26) ); \INFERRED_GEN.icount_out[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(16), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__5_n_5\, O => p_1_in(27) ); \INFERRED_GEN.icount_out[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(17), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__5_n_4\, O => p_1_in(28) ); \INFERRED_GEN.icount_out[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(18), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__6_n_7\, O => p_1_in(29) ); \INFERRED_GEN.icount_out[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(2), I1 => load_Counter_Reg(0), I2 => icount_out0_carry_n_6, O => p_1_in(2) ); \INFERRED_GEN.icount_out[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(19), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__6_n_6\, O => p_1_in(30) ); \INFERRED_GEN.icount_out[31]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(20), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__6_n_5\, O => p_1_in(31) ); \INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0000E200" ) port map ( I0 => \^counter_tc\(0), I1 => E(0), I2 => \icount_out0_carry__6_n_4\, I3 => s_axi_aresetn, I4 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[32]_i_1_n_0\ ); \INFERRED_GEN.icount_out[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(3), I1 => load_Counter_Reg(0), I2 => icount_out0_carry_n_5, O => p_1_in(3) ); \INFERRED_GEN.icount_out[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(4), I1 => load_Counter_Reg(0), I2 => icount_out0_carry_n_4, O => p_1_in(4) ); \INFERRED_GEN.icount_out[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(5), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__0_n_7\, O => p_1_in(5) ); \INFERRED_GEN.icount_out[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(6), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__0_n_6\, O => p_1_in(6) ); \INFERRED_GEN.icount_out[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(7), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__0_n_5\, O => p_1_in(7) ); \INFERRED_GEN.icount_out[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(8), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__0_n_4\, O => p_1_in(8) ); \INFERRED_GEN.icount_out[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(9), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__1_n_7\, O => p_1_in(9) ); \INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(0), Q => \^load_reg_gen[0].load_reg_i\(0), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(10), Q => \^load_reg_gen[0].load_reg_i\(10), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(11), Q => \^load_reg_gen[0].load_reg_i\(11), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(12), Q => \^load_reg_gen[0].load_reg_i\(12), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(13), Q => \^load_reg_gen[0].load_reg_i\(13), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(14), Q => \^load_reg_gen[0].load_reg_i\(14), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(15), Q => \^load_reg_gen[0].load_reg_i\(15), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(16), Q => \^load_reg_gen[0].load_reg_i\(16), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(17), Q => \^load_reg_gen[0].load_reg_i\(17), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(18), Q => \^load_reg_gen[0].load_reg_i\(18), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(19), Q => \^load_reg_gen[0].load_reg_i\(19), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(1), Q => \^load_reg_gen[0].load_reg_i\(1), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(20), Q => \^load_reg_gen[0].load_reg_i\(20), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(21), Q => \^load_reg_gen[0].load_reg_i\(21), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(22), Q => \^load_reg_gen[0].load_reg_i\(22), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(23), Q => \^load_reg_gen[0].load_reg_i\(23), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(24), Q => \^load_reg_gen[0].load_reg_i\(24), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(25), Q => \^load_reg_gen[0].load_reg_i\(25), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(26), Q => \^load_reg_gen[0].load_reg_i\(26), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(27), Q => \^load_reg_gen[0].load_reg_i\(27), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(28), Q => \^load_reg_gen[0].load_reg_i\(28), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(29), Q => \^load_reg_gen[0].load_reg_i\(29), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(2), Q => \^load_reg_gen[0].load_reg_i\(2), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(30), Q => \^load_reg_gen[0].load_reg_i\(30), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(31), Q => \^load_reg_gen[0].load_reg_i\(31), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \INFERRED_GEN.icount_out[32]_i_1_n_0\, Q => \^counter_tc\(0), R => '0' ); \INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(3), Q => \^load_reg_gen[0].load_reg_i\(3), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(4), Q => \^load_reg_gen[0].load_reg_i\(4), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(5), Q => \^load_reg_gen[0].load_reg_i\(5), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(6), Q => \^load_reg_gen[0].load_reg_i\(6), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(7), Q => \^load_reg_gen[0].load_reg_i\(7), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(8), Q => \^load_reg_gen[0].load_reg_i\(8), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(9), Q => \^load_reg_gen[0].load_reg_i\(9), R => s_axi_aresetn_0 ); generateOutPre0_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^counter_tc\(0), I1 => Q(0), O => generateOutPre0_reg ); icount_out0_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => icount_out0_carry_n_0, CO(2) => icount_out0_carry_n_1, CO(1) => icount_out0_carry_n_2, CO(0) => icount_out0_carry_n_3, CYINIT => \^load_reg_gen[0].load_reg_i\(0), DI(3 downto 1) => \^load_reg_gen[0].load_reg_i\(3 downto 1), DI(0) => \icount_out0_carry_i_1__0_n_0\, O(3) => icount_out0_carry_n_4, O(2) => icount_out0_carry_n_5, O(1) => icount_out0_carry_n_6, O(0) => icount_out0_carry_n_7, S(3) => \icount_out0_carry_i_2__0_n_0\, S(2) => \icount_out0_carry_i_3__0_n_0\, S(1) => \icount_out0_carry_i_4__0_n_0\, S(0) => S(0) ); \icount_out0_carry__0\: unisim.vcomponents.CARRY4 port map ( CI => icount_out0_carry_n_0, CO(3) => \icount_out0_carry__0_n_0\, CO(2) => \icount_out0_carry__0_n_1\, CO(1) => \icount_out0_carry__0_n_2\, CO(0) => \icount_out0_carry__0_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(7 downto 4), O(3) => \icount_out0_carry__0_n_4\, O(2) => \icount_out0_carry__0_n_5\, O(1) => \icount_out0_carry__0_n_6\, O(0) => \icount_out0_carry__0_n_7\, S(3) => \icount_out0_carry__0_i_1__0_n_0\, S(2) => \icount_out0_carry__0_i_2__0_n_0\, S(1) => \icount_out0_carry__0_i_3__0_n_0\, S(0) => \icount_out0_carry__0_i_4__0_n_0\ ); \icount_out0_carry__0_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(7), I1 => \^load_reg_gen[0].load_reg_i\(8), O => \icount_out0_carry__0_i_1__0_n_0\ ); \icount_out0_carry__0_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(6), I1 => \^load_reg_gen[0].load_reg_i\(7), O => \icount_out0_carry__0_i_2__0_n_0\ ); \icount_out0_carry__0_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(5), I1 => \^load_reg_gen[0].load_reg_i\(6), O => \icount_out0_carry__0_i_3__0_n_0\ ); \icount_out0_carry__0_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(4), I1 => \^load_reg_gen[0].load_reg_i\(5), O => \icount_out0_carry__0_i_4__0_n_0\ ); \icount_out0_carry__1\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__0_n_0\, CO(3) => \icount_out0_carry__1_n_0\, CO(2) => \icount_out0_carry__1_n_1\, CO(1) => \icount_out0_carry__1_n_2\, CO(0) => \icount_out0_carry__1_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(11 downto 8), O(3) => \icount_out0_carry__1_n_4\, O(2) => \icount_out0_carry__1_n_5\, O(1) => \icount_out0_carry__1_n_6\, O(0) => \icount_out0_carry__1_n_7\, S(3) => \icount_out0_carry__1_i_1__0_n_0\, S(2) => \icount_out0_carry__1_i_2__0_n_0\, S(1) => \icount_out0_carry__1_i_3__0_n_0\, S(0) => \icount_out0_carry__1_i_4__0_n_0\ ); \icount_out0_carry__1_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(11), I1 => \^load_reg_gen[0].load_reg_i\(12), O => \icount_out0_carry__1_i_1__0_n_0\ ); \icount_out0_carry__1_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(10), I1 => \^load_reg_gen[0].load_reg_i\(11), O => \icount_out0_carry__1_i_2__0_n_0\ ); \icount_out0_carry__1_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(9), I1 => \^load_reg_gen[0].load_reg_i\(10), O => \icount_out0_carry__1_i_3__0_n_0\ ); \icount_out0_carry__1_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(8), I1 => \^load_reg_gen[0].load_reg_i\(9), O => \icount_out0_carry__1_i_4__0_n_0\ ); \icount_out0_carry__2\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__1_n_0\, CO(3) => \icount_out0_carry__2_n_0\, CO(2) => \icount_out0_carry__2_n_1\, CO(1) => \icount_out0_carry__2_n_2\, CO(0) => \icount_out0_carry__2_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(15 downto 12), O(3) => \icount_out0_carry__2_n_4\, O(2) => \icount_out0_carry__2_n_5\, O(1) => \icount_out0_carry__2_n_6\, O(0) => \icount_out0_carry__2_n_7\, S(3) => \icount_out0_carry__2_i_1__0_n_0\, S(2) => \icount_out0_carry__2_i_2__0_n_0\, S(1) => \icount_out0_carry__2_i_3__0_n_0\, S(0) => \icount_out0_carry__2_i_4__0_n_0\ ); \icount_out0_carry__2_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(15), I1 => \^load_reg_gen[0].load_reg_i\(16), O => \icount_out0_carry__2_i_1__0_n_0\ ); \icount_out0_carry__2_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(14), I1 => \^load_reg_gen[0].load_reg_i\(15), O => \icount_out0_carry__2_i_2__0_n_0\ ); \icount_out0_carry__2_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(13), I1 => \^load_reg_gen[0].load_reg_i\(14), O => \icount_out0_carry__2_i_3__0_n_0\ ); \icount_out0_carry__2_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(12), I1 => \^load_reg_gen[0].load_reg_i\(13), O => \icount_out0_carry__2_i_4__0_n_0\ ); \icount_out0_carry__3\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__2_n_0\, CO(3) => \icount_out0_carry__3_n_0\, CO(2) => \icount_out0_carry__3_n_1\, CO(1) => \icount_out0_carry__3_n_2\, CO(0) => \icount_out0_carry__3_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(19 downto 16), O(3) => \icount_out0_carry__3_n_4\, O(2) => \icount_out0_carry__3_n_5\, O(1) => \icount_out0_carry__3_n_6\, O(0) => \icount_out0_carry__3_n_7\, S(3) => \icount_out0_carry__3_i_1__0_n_0\, S(2) => \icount_out0_carry__3_i_2__0_n_0\, S(1) => \icount_out0_carry__3_i_3__0_n_0\, S(0) => \icount_out0_carry__3_i_4__0_n_0\ ); \icount_out0_carry__3_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(19), I1 => \^load_reg_gen[0].load_reg_i\(20), O => \icount_out0_carry__3_i_1__0_n_0\ ); \icount_out0_carry__3_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(18), I1 => \^load_reg_gen[0].load_reg_i\(19), O => \icount_out0_carry__3_i_2__0_n_0\ ); \icount_out0_carry__3_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(17), I1 => \^load_reg_gen[0].load_reg_i\(18), O => \icount_out0_carry__3_i_3__0_n_0\ ); \icount_out0_carry__3_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(16), I1 => \^load_reg_gen[0].load_reg_i\(17), O => \icount_out0_carry__3_i_4__0_n_0\ ); \icount_out0_carry__4\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__3_n_0\, CO(3) => \icount_out0_carry__4_n_0\, CO(2) => \icount_out0_carry__4_n_1\, CO(1) => \icount_out0_carry__4_n_2\, CO(0) => \icount_out0_carry__4_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(23 downto 20), O(3) => \icount_out0_carry__4_n_4\, O(2) => \icount_out0_carry__4_n_5\, O(1) => \icount_out0_carry__4_n_6\, O(0) => \icount_out0_carry__4_n_7\, S(3) => \icount_out0_carry__4_i_1__0_n_0\, S(2) => \icount_out0_carry__4_i_2__0_n_0\, S(1) => \icount_out0_carry__4_i_3__0_n_0\, S(0) => \icount_out0_carry__4_i_4__0_n_0\ ); \icount_out0_carry__4_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(23), I1 => \^load_reg_gen[0].load_reg_i\(24), O => \icount_out0_carry__4_i_1__0_n_0\ ); \icount_out0_carry__4_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(22), I1 => \^load_reg_gen[0].load_reg_i\(23), O => \icount_out0_carry__4_i_2__0_n_0\ ); \icount_out0_carry__4_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(21), I1 => \^load_reg_gen[0].load_reg_i\(22), O => \icount_out0_carry__4_i_3__0_n_0\ ); \icount_out0_carry__4_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(20), I1 => \^load_reg_gen[0].load_reg_i\(21), O => \icount_out0_carry__4_i_4__0_n_0\ ); \icount_out0_carry__5\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__4_n_0\, CO(3) => \icount_out0_carry__5_n_0\, CO(2) => \icount_out0_carry__5_n_1\, CO(1) => \icount_out0_carry__5_n_2\, CO(0) => \icount_out0_carry__5_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(27 downto 24), O(3) => \icount_out0_carry__5_n_4\, O(2) => \icount_out0_carry__5_n_5\, O(1) => \icount_out0_carry__5_n_6\, O(0) => \icount_out0_carry__5_n_7\, S(3) => \icount_out0_carry__5_i_1__0_n_0\, S(2) => \icount_out0_carry__5_i_2__0_n_0\, S(1) => \icount_out0_carry__5_i_3__0_n_0\, S(0) => \icount_out0_carry__5_i_4__0_n_0\ ); \icount_out0_carry__5_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(27), I1 => \^load_reg_gen[0].load_reg_i\(28), O => \icount_out0_carry__5_i_1__0_n_0\ ); \icount_out0_carry__5_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(26), I1 => \^load_reg_gen[0].load_reg_i\(27), O => \icount_out0_carry__5_i_2__0_n_0\ ); \icount_out0_carry__5_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(25), I1 => \^load_reg_gen[0].load_reg_i\(26), O => \icount_out0_carry__5_i_3__0_n_0\ ); \icount_out0_carry__5_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(24), I1 => \^load_reg_gen[0].load_reg_i\(25), O => \icount_out0_carry__5_i_4__0_n_0\ ); \icount_out0_carry__6\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__5_n_0\, CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3), CO(2) => \icount_out0_carry__6_n_1\, CO(1) => \icount_out0_carry__6_n_2\, CO(0) => \icount_out0_carry__6_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => \^load_reg_gen[0].load_reg_i\(30 downto 28), O(3) => \icount_out0_carry__6_n_4\, O(2) => \icount_out0_carry__6_n_5\, O(1) => \icount_out0_carry__6_n_6\, O(0) => \icount_out0_carry__6_n_7\, S(3) => \icount_out0_carry__6_i_1__0_n_0\, S(2) => \icount_out0_carry__6_i_2__0_n_0\, S(1) => \icount_out0_carry__6_i_3__0_n_0\, S(0) => \icount_out0_carry__6_i_4__0_n_0\ ); \icount_out0_carry__6_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(31), O => \icount_out0_carry__6_i_1__0_n_0\ ); \icount_out0_carry__6_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(30), I1 => \^load_reg_gen[0].load_reg_i\(31), O => \icount_out0_carry__6_i_2__0_n_0\ ); \icount_out0_carry__6_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(29), I1 => \^load_reg_gen[0].load_reg_i\(30), O => \icount_out0_carry__6_i_3__0_n_0\ ); \icount_out0_carry__6_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(28), I1 => \^load_reg_gen[0].load_reg_i\(29), O => \icount_out0_carry__6_i_4__0_n_0\ ); \icount_out0_carry_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(1), O => \icount_out0_carry_i_1__0_n_0\ ); \icount_out0_carry_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(3), I1 => \^load_reg_gen[0].load_reg_i\(4), O => \icount_out0_carry_i_2__0_n_0\ ); \icount_out0_carry_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(2), I1 => \^load_reg_gen[0].load_reg_i\(3), O => \icount_out0_carry_i_3__0_n_0\ ); \icount_out0_carry_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(1), I1 => \^load_reg_gen[0].load_reg_i\(2), O => \icount_out0_carry_i_4__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f is port ( D : out STD_LOGIC_VECTOR ( 31 downto 0 ); Bus_RNW_reg_reg : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[31]\ : in STD_LOGIC; Bus_RNW_reg_reg_0 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC; Bus_RNW_reg_reg_1 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC; Bus_RNW_reg_reg_2 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC; Bus_RNW_reg_reg_3 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC; Bus_RNW_reg_reg_4 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC; Bus_RNW_reg_reg_5 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC; Bus_RNW_reg_reg_6 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC; Bus_RNW_reg_reg_7 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC; Bus_RNW_reg_reg_8 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC; Bus_RNW_reg_reg_9 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC; Bus_RNW_reg_reg_10 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC; Bus_RNW_reg_reg_11 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC; Bus_RNW_reg_reg_12 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC; Bus_RNW_reg_reg_13 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC; Bus_RNW_reg_reg_14 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC; Bus_RNW_reg_reg_15 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC; Bus_RNW_reg_reg_16 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC; Bus_RNW_reg_reg_17 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC; Bus_RNW_reg_reg_18 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC; \LOAD_REG_GEN[31].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f : entity is "mux_onehot_f"; end zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f is signal \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal cyout_1 : STD_LOGIC; signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; begin \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(31), CO(0) => cyout_1, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[31]\, S(0) => Bus_RNW_reg_reg ); \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(21), CO(0) => \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[21]\, S(0) => Bus_RNW_reg_reg_9 ); \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(20), CO(0) => \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[20]\, S(0) => Bus_RNW_reg_reg_10 ); \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(19), CO(0) => \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[19]\, S(0) => Bus_RNW_reg_reg_11 ); \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(18), CO(0) => \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[18]\, S(0) => Bus_RNW_reg_reg_12 ); \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(17), CO(0) => \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[17]\, S(0) => Bus_RNW_reg_reg_13 ); \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(16), CO(0) => \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[16]\, S(0) => Bus_RNW_reg_reg_14 ); \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(15), CO(0) => \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[15]\, S(0) => Bus_RNW_reg_reg_15 ); \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(14), CO(0) => \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[14]\, S(0) => Bus_RNW_reg_reg_16 ); \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(13), CO(0) => \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[13]\, S(0) => Bus_RNW_reg_reg_17 ); \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(12), CO(0) => \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[12]\, S(0) => Bus_RNW_reg_reg_18 ); \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(30), CO(0) => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[30]\, S(0) => Bus_RNW_reg_reg_0 ); \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(11), CO(0) => \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[11]\, S(0) => \LOAD_REG_GEN[20].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(10), CO(0) => \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[10]\, S(0) => \LOAD_REG_GEN[21].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(9), CO(0) => \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[9]\, S(0) => \LOAD_REG_GEN[22].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(8), CO(0) => \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[8]\, S(0) => \LOAD_REG_GEN[23].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(7), CO(0) => \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[7]\, S(0) => \LOAD_REG_GEN[24].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(6), CO(0) => \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[6]\, S(0) => \LOAD_REG_GEN[25].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(5), CO(0) => \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[5]\, S(0) => \LOAD_REG_GEN[26].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(4), CO(0) => \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[4]\, S(0) => \LOAD_REG_GEN[27].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(3), CO(0) => \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[3]\, S(0) => \LOAD_REG_GEN[28].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(2), CO(0) => \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[2]\, S(0) => \LOAD_REG_GEN[29].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(29), CO(0) => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[29]\, S(0) => Bus_RNW_reg_reg_1 ); \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(1), CO(0) => \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[1]\, S(0) => \LOAD_REG_GEN[30].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(0), CO(0) => \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[0]\, S(0) => \LOAD_REG_GEN[31].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(28), CO(0) => \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[28]\, S(0) => Bus_RNW_reg_reg_2 ); \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(27), CO(0) => \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[27]\, S(0) => Bus_RNW_reg_reg_3 ); \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(26), CO(0) => \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[26]\, S(0) => Bus_RNW_reg_reg_4 ); \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(25), CO(0) => \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[25]\, S(0) => Bus_RNW_reg_reg_5 ); \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(24), CO(0) => \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[24]\, S(0) => Bus_RNW_reg_reg_6 ); \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(23), CO(0) => \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[23]\, S(0) => Bus_RNW_reg_reg_7 ); \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(22), CO(0) => \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[22]\, S(0) => Bus_RNW_reg_reg_8 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_pselect_f is port ( ce_expnd_i_7 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_pselect_f : entity is "pselect_f"; end zqynq_lab_1_design_axi_timer_0_1_pselect_f; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_pselect_f is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"0010" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(2), I1 => \bus2ip_addr_i_reg[4]\(1), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(0), O => ce_expnd_i_7 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\ is port ( ce_expnd_i_5 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\ : entity is "pselect_f"; end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\; architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(2), I1 => \bus2ip_addr_i_reg[4]\(0), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(1), O => ce_expnd_i_5 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\ is port ( ce_expnd_i_3 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\ : entity is "pselect_f"; end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\; architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(1), I1 => \bus2ip_addr_i_reg[4]\(0), I2 => \bus2ip_addr_i_reg[4]\(2), I3 => Q, O => ce_expnd_i_3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\ is port ( ce_expnd_i_2 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\ : entity is "pselect_f"; end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\; architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(1), I1 => \bus2ip_addr_i_reg[4]\(2), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(0), O => ce_expnd_i_2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\ is port ( ce_expnd_i_1 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\ : entity is "pselect_f"; end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\; architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(0), I1 => \bus2ip_addr_i_reg[4]\(2), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(1), O => ce_expnd_i_1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\ is port ( ce_expnd_i_0 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\ : entity is "pselect_f"; end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\; architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(1), I1 => \bus2ip_addr_i_reg[4]\(0), I2 => \bus2ip_addr_i_reg[4]\(2), I3 => Q, O => ce_expnd_i_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_address_decoder is port ( \LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC; \s_axi_rdata_i_reg[12]\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC; pair0_Select : out STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \s_axi_rdata_i_reg[11]\ : out STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC; \LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC; D_0 : out STD_LOGIC; \bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 ); \LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC; D_1 : out STD_LOGIC; s_axi_rvalid_i_reg : out STD_LOGIC; s_axi_rvalid_i_reg_0 : out STD_LOGIC; s_axi_rvalid_i_reg_1 : out STD_LOGIC; s_axi_rvalid_i_reg_2 : out STD_LOGIC; s_axi_bvalid_i_reg : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC; \TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC; READ_DONE0_I : out STD_LOGIC; READ_DONE1_I : out STD_LOGIC; Q : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 ); s_axi_aresetn : in STD_LOGIC; \state1__2\ : in STD_LOGIC; s_axi_arvalid_0 : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arvalid : in STD_LOGIC; is_write_reg : in STD_LOGIC; is_read : in STD_LOGIC; \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_rready : in STD_LOGIC; s_axi_rvalid_i_reg_3 : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_bvalid_i_reg_0 : in STD_LOGIC; bus2ip_rnw_i : in STD_LOGIC; D_2 : in STD_LOGIC; read_done1 : in STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_address_decoder : entity is "address_decoder"; end zqynq_lab_1_design_axi_timer_0_1_address_decoder; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_address_decoder is signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\ : STD_LOGIC; signal \^load_reg_gen[31].load_reg_i\ : STD_LOGIC; signal \^tcsr0_generate[23].tcsr0_ff_i\ : STD_LOGIC; signal ce_expnd_i_0 : STD_LOGIC; signal ce_expnd_i_1 : STD_LOGIC; signal ce_expnd_i_2 : STD_LOGIC; signal ce_expnd_i_3 : STD_LOGIC; signal ce_expnd_i_5 : STD_LOGIC; signal ce_expnd_i_6 : STD_LOGIC; signal ce_expnd_i_7 : STD_LOGIC; signal cs_ce_clr : STD_LOGIC; signal \eqOp__4\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal s_axi_arready_INST_0_i_4_n_0 : STD_LOGIC; signal \^s_axi_rvalid_i_reg\ : STD_LOGIC; signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC; signal \^s_axi_rvalid_i_reg_1\ : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC; signal s_axi_wready_INST_0_i_2_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_7\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[9].LOAD_REG_I_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of READ_DONE0_I_i_2 : label is "soft_lutpair7"; attribute SOFT_HLUTNM of READ_DONE1_I_i_2 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \TCSR0_GENERATE[20].TCSR0_FF_I_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \TCSR0_GENERATE[21].TCSR0_FF_I_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \TCSR0_GENERATE[23].TCSR0_FF_I_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \TCSR0_GENERATE[24].TCSR0_FF_I_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \TCSR1_GENERATE[22].TCSR1_FF_I_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \TCSR1_GENERATE[23].TCSR1_FF_I_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \TCSR1_GENERATE[24].TCSR1_FF_I_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_2 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_3 : label is "soft_lutpair8"; attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_4 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_2 : label is "soft_lutpair2"; begin \LOAD_REG_GEN[31].LOAD_REG_I\ <= \^load_reg_gen[31].load_reg_i\; \TCSR0_GENERATE[23].TCSR0_FF_I\ <= \^tcsr0_generate[23].tcsr0_ff_i\; s_axi_arready <= \^s_axi_arready\; s_axi_rvalid_i_reg <= \^s_axi_rvalid_i_reg\; s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\; s_axi_rvalid_i_reg_1 <= \^s_axi_rvalid_i_reg_1\; s_axi_wready <= \^s_axi_wready\; Bus_RNW_reg_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => bus2ip_rnw_i, I1 => Q, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, O => Bus_RNW_reg_i_1_n_0 ); Bus_RNW_reg_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => Bus_RNW_reg_i_1_n_0, Q => \^tcsr0_generate[23].tcsr0_ff_i\, R => '0' ); \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(84), O => \s_axi_rdata_i_reg[31]\ ); \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \s_axi_rdata_i_reg[0]_0\ ); \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \s_axi_rdata_i_reg[0]\ ); \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(74), O => \s_axi_rdata_i_reg[21]\ ); \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(73), O => \s_axi_rdata_i_reg[20]\ ); \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(72), O => \s_axi_rdata_i_reg[19]\ ); \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(71), O => \s_axi_rdata_i_reg[18]\ ); \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(70), O => \s_axi_rdata_i_reg[17]\ ); \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(69), O => \s_axi_rdata_i_reg[16]\ ); \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(68), O => \s_axi_rdata_i_reg[15]\ ); \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(67), O => \s_axi_rdata_i_reg[14]\ ); \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(66), O => \s_axi_rdata_i_reg[13]\ ); \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(65), O => \s_axi_rdata_i_reg[12]\ ); \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(83), O => \s_axi_rdata_i_reg[30]\ ); \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0777FFFF" ) port map ( I0 => read_Mux_In(64), I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(87), I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I4 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \s_axi_rdata_i_reg[11]\ ); \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \s_axi_rdata_i_reg[10]\ ); \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(82), O => \s_axi_rdata_i_reg[29]\ ); \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(81), O => \s_axi_rdata_i_reg[28]\ ); \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(80), O => \s_axi_rdata_i_reg[27]\ ); \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(79), O => \s_axi_rdata_i_reg[26]\ ); \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(78), O => \s_axi_rdata_i_reg[25]\ ); \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(77), O => \s_axi_rdata_i_reg[24]\ ); \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(76), O => \s_axi_rdata_i_reg[23]\ ); \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(75), O => \s_axi_rdata_i_reg[22]\ ); \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_7, Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(2), I1 => \bus2ip_addr_i_reg[4]\(1), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(0), O => ce_expnd_i_6 ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_6, Q => \^load_reg_gen[31].load_reg_i\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_5, Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_3, Q => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_2, Q => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_1, Q => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"EF" ) port map ( I0 => \^s_axi_wready\, I1 => \^s_axi_arready\, I2 => s_axi_aresetn, O => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_0, Q => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\, R => cs_ce_clr ); \LOAD_REG_GEN[0].LOAD_REG_I_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(31), I1 => read_Mux_In(31), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => D_0 ); \LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(31), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(63), O => D_1 ); \LOAD_REG_GEN[0].LOAD_REG_I_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \bus2ip_wrce__0\(0) ); \LOAD_REG_GEN[10].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(21), I1 => read_Mux_In(21), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[10].LOAD_REG_I\ ); \LOAD_REG_GEN[10].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(21), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(53), O => \LOAD_REG_GEN[10].LOAD_REG_I_0\ ); \LOAD_REG_GEN[11].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(20), I1 => read_Mux_In(20), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[11].LOAD_REG_I\ ); \LOAD_REG_GEN[11].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(20), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(52), O => \LOAD_REG_GEN[11].LOAD_REG_I_0\ ); \LOAD_REG_GEN[12].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(19), I1 => read_Mux_In(19), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[12].LOAD_REG_I\ ); \LOAD_REG_GEN[12].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(19), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(51), O => \LOAD_REG_GEN[12].LOAD_REG_I_0\ ); \LOAD_REG_GEN[13].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(18), I1 => read_Mux_In(18), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[13].LOAD_REG_I\ ); \LOAD_REG_GEN[13].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(18), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(50), O => \LOAD_REG_GEN[13].LOAD_REG_I_0\ ); \LOAD_REG_GEN[14].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(17), I1 => read_Mux_In(17), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[14].LOAD_REG_I\ ); \LOAD_REG_GEN[14].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(17), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(49), O => \LOAD_REG_GEN[14].LOAD_REG_I_0\ ); \LOAD_REG_GEN[15].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(16), I1 => read_Mux_In(16), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[15].LOAD_REG_I\ ); \LOAD_REG_GEN[15].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(16), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(48), O => \LOAD_REG_GEN[15].LOAD_REG_I_0\ ); \LOAD_REG_GEN[16].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(15), I1 => read_Mux_In(15), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[16].LOAD_REG_I\ ); \LOAD_REG_GEN[16].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(15), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(47), O => \LOAD_REG_GEN[16].LOAD_REG_I_0\ ); \LOAD_REG_GEN[17].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(14), I1 => read_Mux_In(14), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[17].LOAD_REG_I\ ); \LOAD_REG_GEN[17].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(14), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(46), O => \LOAD_REG_GEN[17].LOAD_REG_I_0\ ); \LOAD_REG_GEN[18].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(13), I1 => read_Mux_In(13), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[18].LOAD_REG_I\ ); \LOAD_REG_GEN[18].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(13), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(45), O => \LOAD_REG_GEN[18].LOAD_REG_I_0\ ); \LOAD_REG_GEN[19].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(12), I1 => read_Mux_In(12), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[19].LOAD_REG_I\ ); \LOAD_REG_GEN[19].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(12), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(44), O => \LOAD_REG_GEN[19].LOAD_REG_I_0\ ); \LOAD_REG_GEN[1].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(30), I1 => read_Mux_In(30), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[1].LOAD_REG_I\ ); \LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(30), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(62), O => \LOAD_REG_GEN[1].LOAD_REG_I_0\ ); \LOAD_REG_GEN[20].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(11), I1 => read_Mux_In(11), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[20].LOAD_REG_I\ ); \LOAD_REG_GEN[20].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(11), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(43), O => \LOAD_REG_GEN[20].LOAD_REG_I_0\ ); \LOAD_REG_GEN[21].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(10), I1 => read_Mux_In(10), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[21].LOAD_REG_I\ ); \LOAD_REG_GEN[21].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(10), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(42), O => \LOAD_REG_GEN[21].LOAD_REG_I_0\ ); \LOAD_REG_GEN[22].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(9), I1 => read_Mux_In(9), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[22].LOAD_REG_I\ ); \LOAD_REG_GEN[22].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(9), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(41), O => \LOAD_REG_GEN[22].LOAD_REG_I_0\ ); \LOAD_REG_GEN[23].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(8), I1 => read_Mux_In(8), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[23].LOAD_REG_I\ ); \LOAD_REG_GEN[23].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(8), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(40), O => \LOAD_REG_GEN[23].LOAD_REG_I_0\ ); \LOAD_REG_GEN[24].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(7), I1 => read_Mux_In(7), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[24].LOAD_REG_I\ ); \LOAD_REG_GEN[24].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(7), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(39), O => \LOAD_REG_GEN[24].LOAD_REG_I_0\ ); \LOAD_REG_GEN[25].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(6), I1 => read_Mux_In(6), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[25].LOAD_REG_I\ ); \LOAD_REG_GEN[25].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(6), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(38), O => \LOAD_REG_GEN[25].LOAD_REG_I_0\ ); \LOAD_REG_GEN[26].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(5), I1 => read_Mux_In(5), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[26].LOAD_REG_I\ ); \LOAD_REG_GEN[26].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(5), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(37), O => \LOAD_REG_GEN[26].LOAD_REG_I_0\ ); \LOAD_REG_GEN[27].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(4), I1 => read_Mux_In(4), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[27].LOAD_REG_I\ ); \LOAD_REG_GEN[27].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(4), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(36), O => \LOAD_REG_GEN[27].LOAD_REG_I_0\ ); \LOAD_REG_GEN[28].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(3), I1 => read_Mux_In(3), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[28].LOAD_REG_I\ ); \LOAD_REG_GEN[28].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(3), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(35), O => \LOAD_REG_GEN[28].LOAD_REG_I_0\ ); \LOAD_REG_GEN[29].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(2), I1 => read_Mux_In(2), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[29].LOAD_REG_I\ ); \LOAD_REG_GEN[29].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(2), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(34), O => \LOAD_REG_GEN[29].LOAD_REG_I_0\ ); \LOAD_REG_GEN[2].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(29), I1 => read_Mux_In(29), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[2].LOAD_REG_I\ ); \LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(29), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(61), O => \LOAD_REG_GEN[2].LOAD_REG_I_0\ ); \LOAD_REG_GEN[30].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(1), I1 => read_Mux_In(1), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[30].LOAD_REG_I\ ); \LOAD_REG_GEN[30].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(1), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(33), O => \LOAD_REG_GEN[30].LOAD_REG_I_0\ ); \LOAD_REG_GEN[31].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(0), I1 => read_Mux_In(0), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[31].LOAD_REG_I_0\ ); \LOAD_REG_GEN[31].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(0), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(32), O => \LOAD_REG_GEN[31].LOAD_REG_I_1\ ); \LOAD_REG_GEN[3].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(28), I1 => read_Mux_In(28), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[3].LOAD_REG_I\ ); \LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(28), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(60), O => \LOAD_REG_GEN[3].LOAD_REG_I_0\ ); \LOAD_REG_GEN[4].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(27), I1 => read_Mux_In(27), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[4].LOAD_REG_I\ ); \LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(27), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(59), O => \LOAD_REG_GEN[4].LOAD_REG_I_0\ ); \LOAD_REG_GEN[5].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(26), I1 => read_Mux_In(26), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[5].LOAD_REG_I\ ); \LOAD_REG_GEN[5].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(26), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(58), O => \LOAD_REG_GEN[5].LOAD_REG_I_0\ ); \LOAD_REG_GEN[6].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(25), I1 => read_Mux_In(25), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[6].LOAD_REG_I\ ); \LOAD_REG_GEN[6].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(25), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(57), O => \LOAD_REG_GEN[6].LOAD_REG_I_0\ ); \LOAD_REG_GEN[7].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(24), I1 => read_Mux_In(24), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[7].LOAD_REG_I\ ); \LOAD_REG_GEN[7].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(24), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(56), O => \LOAD_REG_GEN[7].LOAD_REG_I_0\ ); \LOAD_REG_GEN[8].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(23), I1 => read_Mux_In(23), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[8].LOAD_REG_I\ ); \LOAD_REG_GEN[8].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(23), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(55), O => \LOAD_REG_GEN[8].LOAD_REG_I_0\ ); \LOAD_REG_GEN[9].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(22), I1 => read_Mux_In(22), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[9].LOAD_REG_I\ ); \LOAD_REG_GEN[9].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(22), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(54), O => \LOAD_REG_GEN[9].LOAD_REG_I_0\ ); \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.zqynq_lab_1_design_axi_timer_0_1_pselect_f port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_7 => ce_expnd_i_7 ); \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_5 => ce_expnd_i_5 ); \MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_3 => ce_expnd_i_3 ); \MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_2 => ce_expnd_i_2 ); \MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_1 => ce_expnd_i_1 ); \MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_0 => ce_expnd_i_0 ); READ_DONE0_I_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^load_reg_gen[31].load_reg_i\, I1 => D_2, O => READ_DONE0_I ); READ_DONE1_I_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => read_done1, O => READ_DONE1_I ); \TCSR0_GENERATE[20].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => bus2ip_wrce(1) ); \TCSR0_GENERATE[21].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"32" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, O => pair0_Select ); \TCSR0_GENERATE[23].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"20FF" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, I2 => s_axi_wdata(8), I3 => s_axi_aresetn, O => \TCSR0_GENERATE[23].TCSR0_FF_I_0\ ); \TCSR0_GENERATE[24].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFEEEAEE" ) port map ( I0 => s_axi_wdata(10), I1 => read_Mux_In(86), I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I4 => s_axi_wdata(7), O => \TCSR0_GENERATE[24].TCSR0_FF_I\ ); \TCSR1_GENERATE[22].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => bus2ip_wrce(0) ); \TCSR1_GENERATE[23].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"20FF" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, I2 => s_axi_wdata(8), I3 => s_axi_aresetn, O => \TCSR1_GENERATE[23].TCSR1_FF_I\ ); \TCSR1_GENERATE[24].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFEEEAEE" ) port map ( I0 => s_axi_wdata(10), I1 => read_Mux_In(85), I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I4 => s_axi_wdata(7), O => \TCSR1_GENERATE[24].TCSR1_FF_I\ ); s_axi_arready_INST_0: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFEFFFEFFFEFF" ) port map ( I0 => \^s_axi_rvalid_i_reg\, I1 => \^s_axi_rvalid_i_reg_0\, I2 => \^s_axi_rvalid_i_reg_1\, I3 => s_axi_arready_INST_0_i_4_n_0, I4 => is_read, I5 => \eqOp__4\, O => \^s_axi_arready\ ); s_axi_arready_INST_0_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^load_reg_gen[31].load_reg_i\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \^s_axi_rvalid_i_reg\ ); s_axi_arready_INST_0_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \^s_axi_rvalid_i_reg_0\ ); s_axi_arready_INST_0_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \^s_axi_rvalid_i_reg_1\ ); s_axi_arready_INST_0_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"00FF01FF" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\, I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, O => s_axi_arready_INST_0_i_4_n_0 ); s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"08FF0808" ) port map ( I0 => \^s_axi_wready\, I1 => \state_reg[1]\(1), I2 => \state_reg[1]\(0), I3 => s_axi_bready, I4 => s_axi_bvalid_i_reg_0, O => s_axi_bvalid_i_reg ); s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"08FF0808" ) port map ( I0 => \^s_axi_arready\, I1 => \state_reg[1]\(0), I2 => \state_reg[1]\(1), I3 => s_axi_rready, I4 => s_axi_rvalid_i_reg_3, O => s_axi_rvalid_i_reg_2 ); s_axi_wready_INST_0: unisim.vcomponents.LUT4 generic map( INIT => X"F777" ) port map ( I0 => s_axi_wready_INST_0_i_1_n_0, I1 => s_axi_wready_INST_0_i_2_n_0, I2 => is_write_reg, I3 => \eqOp__4\, O => \^s_axi_wready\ ); s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F0F1" ) port map ( I0 => \^load_reg_gen[31].load_reg_i\, I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, O => s_axi_wready_INST_0_i_1_n_0 ); s_axi_wready_INST_0_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FF00FF01" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\, I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, O => s_axi_wready_INST_0_i_2_n_0 ); s_axi_wready_INST_0_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000100" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(4), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(2), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(3), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5), I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0), I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1), O => \eqOp__4\ ); \state[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"77FC44FC" ) port map ( I0 => \state1__2\, I1 => \state_reg[1]\(0), I2 => s_axi_arvalid, I3 => \state_reg[1]\(1), I4 => \^s_axi_wready\, O => D(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"5FFC50FC" ) port map ( I0 => \state1__2\, I1 => s_axi_arvalid_0, I2 => \state_reg[1]\(1), I3 => \state_reg[1]\(0), I4 => \^s_axi_arready\, O => D(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_count_module is port ( \INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC_VECTOR ( 52 downto 0 ); read_Mux_In : out STD_LOGIC_VECTOR ( 10 downto 0 ); generateOutPre0_reg : out STD_LOGIC; counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn_0 : in STD_LOGIC; \TCSR0_GENERATE[27].TCSR0_FF_I\ : in STD_LOGIC; D_1 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 0 to 0 ); load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_count_module : entity is "count_module"; end zqynq_lab_1_design_axi_timer_0_1_count_module; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_count_module is signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC_VECTOR ( 52 downto 0 ); signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 10 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE"; begin \INFERRED_GEN.icount_out_reg[31]\(52 downto 0) <= \^inferred_gen.icount_out_reg[31]\(52 downto 0); read_Mux_In(10 downto 0) <= \^read_mux_in\(10 downto 0); COUNTER_I: entity work.zqynq_lab_1_design_axi_timer_0_1_counter_f_3 port map ( E(0) => E(0), \LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) => \^inferred_gen.icount_out_reg[31]\(31 downto 0), \LOAD_REG_GEN[0].LOAD_REG_I_0\(20 downto 0) => \^inferred_gen.icount_out_reg[31]\(52 downto 32), Q(0) => Q(0), S(0) => S(0), counter_TC(0) => counter_TC(0), generateOutPre0_reg => generateOutPre0_reg, load_Counter_Reg(0) => load_Counter_Reg(0), read_Mux_In(10 downto 0) => \^read_mux_in\(10 downto 0), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_aresetn_0 => s_axi_aresetn_0 ); \LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => D_1, Q => \^inferred_gen.icount_out_reg[31]\(52), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\, Q => \^inferred_gen.icount_out_reg[31]\(42), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\, Q => \^inferred_gen.icount_out_reg[31]\(41), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\, Q => \^inferred_gen.icount_out_reg[31]\(40), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\, Q => \^inferred_gen.icount_out_reg[31]\(39), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\, Q => \^inferred_gen.icount_out_reg[31]\(38), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\, Q => \^inferred_gen.icount_out_reg[31]\(37), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\, Q => \^inferred_gen.icount_out_reg[31]\(36), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\, Q => \^inferred_gen.icount_out_reg[31]\(35), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\, Q => \^inferred_gen.icount_out_reg[31]\(34), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\, Q => \^inferred_gen.icount_out_reg[31]\(33), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\, Q => \^inferred_gen.icount_out_reg[31]\(51), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\, Q => \^inferred_gen.icount_out_reg[31]\(32), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\, Q => \^read_mux_in\(10), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\, Q => \^read_mux_in\(9), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\, Q => \^read_mux_in\(8), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\, Q => \^read_mux_in\(7), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\, Q => \^read_mux_in\(6), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\, Q => \^read_mux_in\(5), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\, Q => \^read_mux_in\(4), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\, Q => \^read_mux_in\(3), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\, Q => \^read_mux_in\(2), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, Q => \^inferred_gen.icount_out_reg[31]\(50), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\, Q => \^read_mux_in\(1), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\, Q => \^read_mux_in\(0), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\, Q => \^inferred_gen.icount_out_reg[31]\(49), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\, Q => \^inferred_gen.icount_out_reg[31]\(48), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\, Q => \^inferred_gen.icount_out_reg[31]\(47), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\, Q => \^inferred_gen.icount_out_reg[31]\(46), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\, Q => \^inferred_gen.icount_out_reg[31]\(45), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\, Q => \^inferred_gen.icount_out_reg[31]\(44), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\, Q => \^inferred_gen.icount_out_reg[31]\(43), R => s_axi_aresetn_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_count_module_0 is port ( \INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 31 downto 0 ); \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[1]\ : out STD_LOGIC; \s_axi_rdata_i_reg[2]\ : out STD_LOGIC; \s_axi_rdata_i_reg[3]\ : out STD_LOGIC; \s_axi_rdata_i_reg[4]\ : out STD_LOGIC; \s_axi_rdata_i_reg[5]\ : out STD_LOGIC; \s_axi_rdata_i_reg[6]\ : out STD_LOGIC; \s_axi_rdata_i_reg[7]\ : out STD_LOGIC; \s_axi_rdata_i_reg[8]\ : out STD_LOGIC; \s_axi_rdata_i_reg[9]\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; \s_axi_rdata_i_reg[11]\ : out STD_LOGIC; \s_axi_rdata_i_reg[12]\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC; generateOutPre1_reg : out STD_LOGIC; counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 ); \TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC; D_2 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 0 to 0 ); load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_count_module_0 : entity is "count_module"; end zqynq_lab_1_design_axi_timer_0_1_count_module_0; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_count_module_0 is signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC; signal read_Mux_In : STD_LOGIC_VECTOR ( 96 to 127 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE"; begin \INFERRED_GEN.icount_out_reg[31]\ <= \^inferred_gen.icount_out_reg[31]\; COUNTER_I: entity work.zqynq_lab_1_design_axi_timer_0_1_counter_f port map ( E(0) => E(0), \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0), Q(31 downto 0) => Q(31 downto 0), S(0) => S(0), SR(0) => \^inferred_gen.icount_out_reg[31]\, counter_TC(0) => counter_TC(0), \counter_TC_Reg_reg[1]\(0) => \counter_TC_Reg_reg[1]\(0), generateOutPre1_reg => generateOutPre1_reg, load_Counter_Reg(0) => load_Counter_Reg(0), read_Mux_In(31) => read_Mux_In(96), read_Mux_In(30) => read_Mux_In(97), read_Mux_In(29) => read_Mux_In(98), read_Mux_In(28) => read_Mux_In(99), read_Mux_In(27) => read_Mux_In(100), read_Mux_In(26) => read_Mux_In(101), read_Mux_In(25) => read_Mux_In(102), read_Mux_In(24) => read_Mux_In(103), read_Mux_In(23) => read_Mux_In(104), read_Mux_In(22) => read_Mux_In(105), read_Mux_In(21) => read_Mux_In(106), read_Mux_In(20) => read_Mux_In(107), read_Mux_In(19) => read_Mux_In(108), read_Mux_In(18) => read_Mux_In(109), read_Mux_In(17) => read_Mux_In(110), read_Mux_In(16) => read_Mux_In(111), read_Mux_In(15) => read_Mux_In(112), read_Mux_In(14) => read_Mux_In(113), read_Mux_In(13) => read_Mux_In(114), read_Mux_In(12) => read_Mux_In(115), read_Mux_In(11) => read_Mux_In(116), read_Mux_In(10) => read_Mux_In(117), read_Mux_In(9) => read_Mux_In(118), read_Mux_In(8) => read_Mux_In(119), read_Mux_In(7) => read_Mux_In(120), read_Mux_In(6) => read_Mux_In(121), read_Mux_In(5) => read_Mux_In(122), read_Mux_In(4) => read_Mux_In(123), read_Mux_In(3) => read_Mux_In(124), read_Mux_In(2) => read_Mux_In(125), read_Mux_In(1) => read_Mux_In(126), read_Mux_In(0) => read_Mux_In(127), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, \s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]\, \s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]\, \s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]\, \s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]\, \s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]\, \s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]\, \s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]\, \s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]\, \s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]\, \s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]\, \s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]\, \s_axi_rdata_i_reg[1]\ => \s_axi_rdata_i_reg[1]\, \s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]\, \s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]\, \s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]\, \s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]\, \s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]\, \s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]\, \s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]\, \s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]\, \s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]\, \s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]\, \s_axi_rdata_i_reg[2]\ => \s_axi_rdata_i_reg[2]\, \s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]\, \s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]\, \s_axi_rdata_i_reg[3]\ => \s_axi_rdata_i_reg[3]\, \s_axi_rdata_i_reg[4]\ => \s_axi_rdata_i_reg[4]\, \s_axi_rdata_i_reg[5]\ => \s_axi_rdata_i_reg[5]\, \s_axi_rdata_i_reg[6]\ => \s_axi_rdata_i_reg[6]\, \s_axi_rdata_i_reg[7]\ => \s_axi_rdata_i_reg[7]\, \s_axi_rdata_i_reg[8]\ => \s_axi_rdata_i_reg[8]\, \s_axi_rdata_i_reg[9]\ => \s_axi_rdata_i_reg[9]\ ); \LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => D_2, Q => read_Mux_In(96), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[21]\, Q => read_Mux_In(106), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[20]\, Q => read_Mux_In(107), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[19]\, Q => read_Mux_In(108), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[18]\, Q => read_Mux_In(109), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[17]\, Q => read_Mux_In(110), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[16]\, Q => read_Mux_In(111), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[15]\, Q => read_Mux_In(112), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[14]\, Q => read_Mux_In(113), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[13]\, Q => read_Mux_In(114), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[12]\, Q => read_Mux_In(115), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[30]\, Q => read_Mux_In(97), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[11]\, Q => read_Mux_In(116), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[10]\, Q => read_Mux_In(117), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[9]\, Q => read_Mux_In(118), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[8]\, Q => read_Mux_In(119), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[7]\, Q => read_Mux_In(120), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[6]\, Q => read_Mux_In(121), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[5]\, Q => read_Mux_In(122), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[4]\, Q => read_Mux_In(123), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[3]\, Q => read_Mux_In(124), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[2]\, Q => read_Mux_In(125), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[29]\, Q => read_Mux_In(98), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[1]\, Q => read_Mux_In(126), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[0]\, Q => read_Mux_In(127), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[28]\, Q => read_Mux_In(99), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[27]\, Q => read_Mux_In(100), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[26]\, Q => read_Mux_In(101), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[25]\, Q => read_Mux_In(102), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[24]\, Q => read_Mux_In(103), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[23]\, Q => read_Mux_In(104), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[22]\, Q => read_Mux_In(105), R => \^inferred_gen.icount_out_reg[31]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_timer_control is port ( generateout0 : out STD_LOGIC; generateout1 : out STD_LOGIC; interrupt : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); \INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I_0\ : out STD_LOGIC; \TCSR1_GENERATE[23].TCSR1_FF_I_0\ : out STD_LOGIC; D_0 : out STD_LOGIC; read_done1 : out STD_LOGIC; load_Counter_Reg : out STD_LOGIC_VECTOR ( 0 to 1 ); \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[1]\ : out STD_LOGIC; \s_axi_rdata_i_reg[2]\ : out STD_LOGIC; \s_axi_rdata_i_reg[3]\ : out STD_LOGIC; \s_axi_rdata_i_reg[4]\ : out STD_LOGIC; \s_axi_rdata_i_reg[5]\ : out STD_LOGIC; \s_axi_rdata_i_reg[6]\ : out STD_LOGIC; \s_axi_rdata_i_reg[7]\ : out STD_LOGIC; \s_axi_rdata_i_reg[8]\ : out STD_LOGIC; \s_axi_rdata_i_reg[9]\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; R : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \INFERRED_GEN.icount_out_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); PWM_FF_I : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 0 to 0 ); \LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC; \INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); \INFERRED_GEN.icount_out_reg[32]\ : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[32]_0\ : in STD_LOGIC; bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 ); \LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); pair0_Select : in STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I_1\ : in STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC; counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC; pwm0 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); Bus_RNW_reg : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC; \bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); freeze : in STD_LOGIC; capturetrig0 : in STD_LOGIC; capturetrig1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_timer_control : entity is "timer_control"; end zqynq_lab_1_design_axi_timer_0_1_timer_control; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_timer_control is signal \^d_0\ : STD_LOGIC; signal GenerateOut00 : STD_LOGIC; signal GenerateOut10 : STD_LOGIC; signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC; signal Interrupt0 : STD_LOGIC; signal \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\ : STD_LOGIC; signal \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\ : STD_LOGIC; signal Load_Counter_Reg028_out : STD_LOGIC; signal Load_Counter_Reg030_out : STD_LOGIC; signal Load_Counter_Reg031_out : STD_LOGIC; signal \Load_Counter_Reg0__0\ : STD_LOGIC; signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal READ_DONE0_I_i_3_n_0 : STD_LOGIC; signal READ_DONE1_I_i_1_n_0 : STD_LOGIC; signal READ_DONE1_I_i_3_n_0 : STD_LOGIC; signal R_0 : STD_LOGIC; signal \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\ : STD_LOGIC; signal \^tcsr0_generate[24].tcsr0_ff_i_0\ : STD_LOGIC; signal \TCSR0_Set2__0\ : STD_LOGIC; signal \^tcsr1_generate[23].tcsr1_ff_i_0\ : STD_LOGIC; signal \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\ : STD_LOGIC; signal captureTrig0_d : STD_LOGIC; signal captureTrig0_d0 : STD_LOGIC; signal captureTrig0_d2 : STD_LOGIC; signal captureTrig0_pulse_d1 : STD_LOGIC; signal captureTrig0_pulse_d1_i_1_n_0 : STD_LOGIC; signal captureTrig0_pulse_d2 : STD_LOGIC; signal captureTrig1_d : STD_LOGIC; signal captureTrig1_d0 : STD_LOGIC; signal captureTrig1_d2 : STD_LOGIC; signal counter_TC_Reg2 : STD_LOGIC; signal generateOutPre0 : STD_LOGIC; signal generateOutPre1 : STD_LOGIC; signal \^generateout0\ : STD_LOGIC; signal \^generateout1\ : STD_LOGIC; signal p_33_in : STD_LOGIC; signal p_38_in : STD_LOGIC; signal read_Mux_In : STD_LOGIC_VECTOR ( 21 to 63 ); signal \^read_done1\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of GenerateOut0_i_2 : label is "soft_lutpair50"; attribute SOFT_HLUTNM of GenerateOut1_i_1 : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4__0\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_3\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_5\ : label is "soft_lutpair53"; attribute BOX_TYPE : string; attribute BOX_TYPE of READ_DONE0_I : label is "PRIMITIVE"; attribute IS_CE_INVERTED : string; attribute IS_CE_INVERTED of READ_DONE0_I : label is "1'b0"; attribute IS_S_INVERTED : string; attribute IS_S_INVERTED of READ_DONE0_I : label is "1'b0"; attribute BOX_TYPE of READ_DONE1_I : label is "PRIMITIVE"; attribute IS_CE_INVERTED of READ_DONE1_I : label is "1'b0"; attribute IS_S_INVERTED of READ_DONE1_I : label is "1'b0"; attribute SOFT_HLUTNM of READ_DONE1_I_i_3 : label is "soft_lutpair52"; attribute BOX_TYPE of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0"; attribute SOFT_HLUTNM of captureTrig0_pulse_d1_i_1 : label is "soft_lutpair52"; begin D_0 <= \^d_0\; \INFERRED_GEN.icount_out_reg[0]\ <= \^inferred_gen.icount_out_reg[0]\; Q(1 downto 0) <= \^q\(1 downto 0); \TCSR0_GENERATE[24].TCSR0_FF_I_0\ <= \^tcsr0_generate[24].tcsr0_ff_i_0\; \TCSR1_GENERATE[23].TCSR1_FF_I_0\ <= \^tcsr1_generate[23].tcsr1_ff_i_0\; generateout0 <= \^generateout0\; generateout1 <= \^generateout1\; read_done1 <= \^read_done1\; \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(10), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(21), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(53), O => \s_axi_rdata_i_reg[10]\ ); \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(9), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(22), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(54), O => \s_axi_rdata_i_reg[9]\ ); \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(8), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(23), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(55), O => \s_axi_rdata_i_reg[8]\ ); \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(7), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => \^tcsr0_generate[24].tcsr0_ff_i_0\, I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => \^tcsr1_generate[23].tcsr1_ff_i_0\, O => \s_axi_rdata_i_reg[7]\ ); \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(6), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(25), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(57), O => \s_axi_rdata_i_reg[6]\ ); \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(5), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(26), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(58), O => \s_axi_rdata_i_reg[5]\ ); \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(4), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(27), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(59), O => \s_axi_rdata_i_reg[4]\ ); \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(3), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(28), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(60), O => \s_axi_rdata_i_reg[3]\ ); \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(2), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(29), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(61), O => \s_axi_rdata_i_reg[2]\ ); \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(1), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(30), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(62), O => \s_axi_rdata_i_reg[1]\ ); \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(0), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(31), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(63), O => \s_axi_rdata_i_reg[0]\ ); GenerateOut0_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"B800" ) port map ( I0 => generateOutPre1, I1 => \^inferred_gen.icount_out_reg[0]\, I2 => generateOutPre0, I3 => read_Mux_In(29), O => GenerateOut00 ); GenerateOut0_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => GenerateOut00, Q => \^generateout0\, R => SR(0) ); GenerateOut1_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"8F808080" ) port map ( I0 => generateOutPre0, I1 => read_Mux_In(29), I2 => \^inferred_gen.icount_out_reg[0]\, I3 => read_Mux_In(61), I4 => generateOutPre1, O => GenerateOut10 ); GenerateOut1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => GenerateOut10, Q => \^generateout1\, R => SR(0) ); \INFERRED_GEN.icount_out[31]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"AAFEAAAA" ) port map ( I0 => read_Mux_In(26), I1 => read_Mux_In(22), I2 => read_Mux_In(27), I3 => read_Mux_In(31), I4 => counter_TC(0), O => Load_Counter_Reg030_out ); \INFERRED_GEN.icount_out[31]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFAAEAAAAAAAEA" ) port map ( I0 => read_Mux_In(58), I1 => counter_TC(1), I2 => read_Mux_In(59), I3 => read_Mux_In(63), I4 => read_Mux_In(54), I5 => counter_TC(0), O => \Load_Counter_Reg0__0\ ); \INFERRED_GEN.icount_out[31]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FF40" ) port map ( I0 => read_Mux_In(31), I1 => counter_TC(1), I2 => read_Mux_In(27), I3 => read_Mux_In(58), O => Load_Counter_Reg028_out ); \INFERRED_GEN.icount_out[31]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FF40" ) port map ( I0 => read_Mux_In(31), I1 => counter_TC(1), I2 => read_Mux_In(27), I3 => read_Mux_In(26), O => Load_Counter_Reg031_out ); \INFERRED_GEN.icount_out[31]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"FF40FFFFFF400000" ) port map ( I0 => read_Mux_In(31), I1 => counter_TC(1), I2 => read_Mux_In(27), I3 => read_Mux_In(58), I4 => \^inferred_gen.icount_out_reg[0]\, I5 => \Load_Counter_Reg0__0\, O => load_Counter_Reg(1) ); \INFERRED_GEN.icount_out[31]_i_7__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF40FFFFFF400000" ) port map ( I0 => read_Mux_In(31), I1 => counter_TC(1), I2 => read_Mux_In(27), I3 => read_Mux_In(26), I4 => \^inferred_gen.icount_out_reg[0]\, I5 => Load_Counter_Reg030_out, O => load_Counter_Reg(0) ); INPUT_DOUBLE_REGS: entity work.zqynq_lab_1_design_axi_timer_0_1_cdc_sync port map ( captureTrig0_d0 => captureTrig0_d0, capturetrig0 => capturetrig0, read_Mux_In(0) => read_Mux_In(28), s_axi_aclk => s_axi_aclk ); INPUT_DOUBLE_REGS2: entity work.zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1 port map ( captureTrig1_d0 => captureTrig1_d0, capturetrig1 => capturetrig1, read_Mux_In(0) => read_Mux_In(60), s_axi_aclk => s_axi_aclk ); INPUT_DOUBLE_REGS3: entity work.zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2 port map ( E(0) => E(0), \INFERRED_GEN.icount_out_reg[0]\(0) => \INFERRED_GEN.icount_out_reg[0]_0\(0), \INFERRED_GEN.icount_out_reg[1]\(1 downto 0) => \INFERRED_GEN.icount_out_reg[1]\(1 downto 0), \INFERRED_GEN.icount_out_reg[4]\(0) => \INFERRED_GEN.icount_out_reg[4]\(0), Load_Counter_Reg028_out => Load_Counter_Reg028_out, Load_Counter_Reg030_out => Load_Counter_Reg030_out, Load_Counter_Reg031_out => Load_Counter_Reg031_out, \Load_Counter_Reg0__0\ => \Load_Counter_Reg0__0\, S(0) => S(0), \TCSR0_GENERATE[20].TCSR0_FF_I\ => \^inferred_gen.icount_out_reg[0]\, \TCSR0_GENERATE[24].TCSR0_FF_I\ => \^tcsr0_generate[24].tcsr0_ff_i_0\, \TCSR1_GENERATE[24].TCSR1_FF_I\ => \^tcsr1_generate[23].tcsr1_ff_i_0\, counter_TC(0 to 1) => counter_TC(0 to 1), freeze => freeze, generateOutPre0 => generateOutPre0, read_Mux_In(7) => read_Mux_In(22), read_Mux_In(6) => read_Mux_In(27), read_Mux_In(5) => read_Mux_In(30), read_Mux_In(4) => read_Mux_In(31), read_Mux_In(3) => read_Mux_In(54), read_Mux_In(2) => read_Mux_In(59), read_Mux_In(1) => read_Mux_In(62), read_Mux_In(0) => read_Mux_In(63), s_axi_aclk => s_axi_aclk ); Interrupt_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F888" ) port map ( I0 => read_Mux_In(25), I1 => read_Mux_In(23), I2 => read_Mux_In(57), I3 => read_Mux_In(55), O => Interrupt0 ); Interrupt_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => Interrupt0, Q => interrupt, R => SR(0) ); \LOAD_REG_GEN[0].LOAD_REG_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"E000FFFFE000E000" ) port map ( I0 => read_Mux_In(27), I1 => \^d_0\, I2 => R_0, I3 => read_Mux_In(31), I4 => Bus_RNW_reg, I5 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, O => \LOAD_REG_GEN[24].LOAD_REG_I\ ); \LOAD_REG_GEN[0].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFF8080808" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\, I1 => p_38_in, I2 => \^inferred_gen.icount_out_reg[0]\, I3 => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\, I4 => p_33_in, I5 => \bus2ip_wrce__0\(0), O => \LOAD_REG_GEN[24].LOAD_REG_I_0\ ); \LOAD_REG_GEN[0].LOAD_REG_I_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => read_Mux_In(59), I1 => \^read_done1\, O => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\ ); \LOAD_REG_GEN[0].LOAD_REG_I_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"F4F4F40400000000" ) port map ( I0 => captureTrig1_d2, I1 => captureTrig1_d, I2 => \^inferred_gen.icount_out_reg[0]\, I3 => READ_DONE1_I_i_3_n_0, I4 => READ_DONE0_I_i_3_n_0, I5 => read_Mux_In(63), O => p_38_in ); \LOAD_REG_GEN[0].LOAD_REG_I_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => read_Mux_In(27), I1 => \^read_done1\, O => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\ ); \LOAD_REG_GEN[0].LOAD_REG_I_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"F4F4F40400000000" ) port map ( I0 => captureTrig1_d2, I1 => captureTrig1_d, I2 => \^inferred_gen.icount_out_reg[0]\, I3 => READ_DONE1_I_i_3_n_0, I4 => READ_DONE0_I_i_3_n_0, I5 => read_Mux_In(31), O => p_33_in ); PWM_FF_I_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"AB" ) port map ( I0 => \^generateout1\, I1 => read_Mux_In(22), I2 => read_Mux_In(54), O => R ); PWM_FF_I_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^generateout0\, I1 => pwm0, O => PWM_FF_I ); READ_DONE0_I: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\, Q => \^d_0\, R => R_0 ); READ_DONE0_I_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AA00AA00ABFFAA00" ) port map ( I0 => READ_DONE0_I_i_3_n_0, I1 => \^q\(1), I2 => counter_TC(0), I3 => \^inferred_gen.icount_out_reg[0]\, I4 => captureTrig0_d, I5 => captureTrig0_d2, O => R_0 ); READ_DONE0_I_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"A8" ) port map ( I0 => counter_TC_Reg2, I1 => captureTrig0_pulse_d2, I2 => captureTrig0_pulse_d1, O => READ_DONE0_I_i_3_n_0 ); READ_DONE1_I: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, Q => \^read_done1\, R => READ_DONE1_I_i_1_n_0 ); READ_DONE1_I_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"E0E0EFE0" ) port map ( I0 => READ_DONE0_I_i_3_n_0, I1 => READ_DONE1_I_i_3_n_0, I2 => \^inferred_gen.icount_out_reg[0]\, I3 => captureTrig1_d, I4 => captureTrig1_d2, O => READ_DONE1_I_i_1_n_0 ); READ_DONE1_I_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => captureTrig0_d2, I1 => captureTrig0_d, I2 => counter_TC(0), I3 => \^q\(1), O => READ_DONE1_I_i_3_n_0 ); \TCSR0_GENERATE[20].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(9), Q => \^inferred_gen.icount_out_reg[0]\, R => SR(0) ); \TCSR0_GENERATE[21].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => pair0_Select, D => s_axi_wdata(8), Q => read_Mux_In(21), R => SR(0) ); \TCSR0_GENERATE[22].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(7), Q => read_Mux_In(22), R => SR(0) ); \TCSR0_GENERATE[23].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\, Q => read_Mux_In(23), R => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ ); \TCSR0_GENERATE[23].TCSR0_FF_I_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFF3F2F0F2" ) port map ( I0 => generateOutPre0, I1 => read_Mux_In(31), I2 => \TCSR0_Set2__0\, I3 => \^inferred_gen.icount_out_reg[0]\, I4 => generateOutPre1, I5 => read_Mux_In(23), O => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\ ); \TCSR0_GENERATE[23].TCSR0_FF_I_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"A8AAA80000000000" ) port map ( I0 => read_Mux_In(31), I1 => READ_DONE0_I_i_3_n_0, I2 => READ_DONE1_I_i_3_n_0, I3 => \^inferred_gen.icount_out_reg[0]\, I4 => captureTrig0_pulse_d1_i_1_n_0, I5 => \^tcsr0_generate[24].tcsr0_ff_i_0\, O => \TCSR0_Set2__0\ ); \TCSR0_GENERATE[24].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => pair0_Select, D => \TCSR0_GENERATE[24].TCSR0_FF_I_1\, Q => \^tcsr0_generate[24].tcsr0_ff_i_0\, R => SR(0) ); \TCSR0_GENERATE[25].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(6), Q => read_Mux_In(25), R => SR(0) ); \TCSR0_GENERATE[26].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(5), Q => read_Mux_In(26), R => SR(0) ); \TCSR0_GENERATE[27].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(4), Q => read_Mux_In(27), R => SR(0) ); \TCSR0_GENERATE[28].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(3), Q => read_Mux_In(28), R => SR(0) ); \TCSR0_GENERATE[29].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(2), Q => read_Mux_In(29), R => SR(0) ); \TCSR0_GENERATE[30].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(1), Q => read_Mux_In(30), R => SR(0) ); \TCSR0_GENERATE[31].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(0), Q => read_Mux_In(31), R => SR(0) ); \TCSR1_GENERATE[21].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => pair0_Select, D => s_axi_wdata(8), Q => read_Mux_In(53), R => SR(0) ); \TCSR1_GENERATE[22].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(7), Q => read_Mux_In(54), R => SR(0) ); \TCSR1_GENERATE[23].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\, Q => read_Mux_In(55), R => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ ); \TCSR1_GENERATE[23].TCSR1_FF_I_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00008F80" ) port map ( I0 => \^tcsr1_generate[23].tcsr1_ff_i_0\, I1 => READ_DONE1_I_i_1_n_0, I2 => read_Mux_In(63), I3 => generateOutPre1, I4 => \^inferred_gen.icount_out_reg[0]\, I5 => read_Mux_In(55), O => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\ ); \TCSR1_GENERATE[24].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => pair0_Select, D => \TCSR1_GENERATE[24].TCSR1_FF_I_0\, Q => \^tcsr1_generate[23].tcsr1_ff_i_0\, R => SR(0) ); \TCSR1_GENERATE[25].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(6), Q => read_Mux_In(57), R => SR(0) ); \TCSR1_GENERATE[26].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(5), Q => read_Mux_In(58), R => SR(0) ); \TCSR1_GENERATE[27].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(4), Q => read_Mux_In(59), R => SR(0) ); \TCSR1_GENERATE[28].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(3), Q => read_Mux_In(60), R => SR(0) ); \TCSR1_GENERATE[29].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(2), Q => read_Mux_In(61), R => SR(0) ); \TCSR1_GENERATE[30].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(1), Q => read_Mux_In(62), R => SR(0) ); \TCSR1_GENERATE[31].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(0), Q => read_Mux_In(63), R => SR(0) ); captureTrig0_d2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig0_d, Q => captureTrig0_d2, R => SR(0) ); captureTrig0_d_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig0_d0, Q => captureTrig0_d, R => SR(0) ); captureTrig0_pulse_d1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => captureTrig0_d, I1 => captureTrig0_d2, O => captureTrig0_pulse_d1_i_1_n_0 ); captureTrig0_pulse_d1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig0_pulse_d1_i_1_n_0, Q => captureTrig0_pulse_d1, R => SR(0) ); captureTrig0_pulse_d2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig0_pulse_d1, Q => captureTrig0_pulse_d2, R => SR(0) ); captureTrig1_d2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig1_d, Q => captureTrig1_d2, R => SR(0) ); captureTrig1_d_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig1_d0, Q => captureTrig1_d, R => SR(0) ); counter_TC_Reg2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^q\(1), Q => counter_TC_Reg2, R => SR(0) ); \counter_TC_Reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => counter_TC(0), Q => \^q\(1), R => SR(0) ); \counter_TC_Reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => counter_TC(1), Q => \^q\(0), R => SR(0) ); generateOutPre0_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \INFERRED_GEN.icount_out_reg[32]_0\, Q => generateOutPre0, R => SR(0) ); generateOutPre1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \INFERRED_GEN.icount_out_reg[32]\, Q => generateOutPre1, R => SR(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_slave_attachment is port ( \LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; \s_axi_rdata_i_reg[12]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC; pair0_Select : out STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; \s_axi_rdata_i_reg[11]_0\ : out STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC; \LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC; D_0 : out STD_LOGIC; \bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 ); \LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC; D_1 : out STD_LOGIC; s_axi_rvalid_i_reg_0 : out STD_LOGIC; s_axi_rvalid_i_reg_1 : out STD_LOGIC; s_axi_rvalid_i_reg_2 : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC; \TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]_1\ : out STD_LOGIC; READ_DONE0_I : out STD_LOGIC; READ_DONE1_I : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); bus2ip_reset : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 ); s_axi_aresetn : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); D_2 : in STD_LOGIC; read_done1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_slave_attachment : entity is "slave_attachment"; end zqynq_lab_1_design_axi_timer_0_1_slave_attachment; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_slave_attachment is signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal I_DECODER_n_100 : STD_LOGIC; signal I_DECODER_n_101 : STD_LOGIC; signal I_DECODER_n_25 : STD_LOGIC; signal I_DECODER_n_26 : STD_LOGIC; signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 2 ); signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC; signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC; signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC; signal \bus2ip_addr_i[4]_i_2_n_0\ : STD_LOGIC; signal bus2ip_rnw_i : STD_LOGIC; signal bus2ip_rnw_i06_out : STD_LOGIC; signal clear : STD_LOGIC; signal is_read : STD_LOGIC; signal is_read_i_1_n_0 : STD_LOGIC; signal is_write : STD_LOGIC; signal is_write_i_1_n_0 : STD_LOGIC; signal is_write_reg_n_0 : STD_LOGIC; signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 ); signal rst : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal start2 : STD_LOGIC; signal start2_i_1_n_0 : STD_LOGIC; signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \state1__2\ : STD_LOGIC; signal \state[1]_i_3_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_2\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair14"; attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair16"; begin s_axi_bvalid <= \^s_axi_bvalid\; s_axi_rvalid <= \^s_axi_rvalid\; \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), O => plusOp(0) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), O => plusOp(1) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), O => plusOp(2) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), O => plusOp(3) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), O => plusOp(4) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => state(0), I1 => state(1), O => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5), O => plusOp(5) ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(0), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(1), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(2), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(3), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(4), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(5), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5), R => clear ); I_DECODER: entity work.zqynq_lab_1_design_axi_timer_0_1_address_decoder port map ( D(1) => I_DECODER_n_25, D(0) => I_DECODER_n_26, D_0 => D_0, D_1 => D_1, D_2 => D_2, \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5 downto 0), \LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\, \LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\, \LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\, \LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\, \LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\, \LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\, \LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\, \LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\, \LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\, \LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\, \LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\, \LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\, \LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\, \LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\, \LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\, \LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\, \LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\, \LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\, \LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\, \LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\, \LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\, \LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\, \LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\, \LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\, \LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\, \LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\, \LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\, \LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\, \LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\, \LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\, \LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\, \LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\, \LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\, \LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\, \LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\, \LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\, \LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\, \LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\, \LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\, \LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\, \LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\, \LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\, \LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\, \LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\, \LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\, \LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\, \LOAD_REG_GEN[31].LOAD_REG_I\ => \LOAD_REG_GEN[31].LOAD_REG_I\, \LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\, \LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_1\, \LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\, \LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\, \LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\, \LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\, \LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\, \LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\, \LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\, \LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\, \LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\, \LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\, \LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\, \LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\, \LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\, \LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\, Q => start2, READ_DONE0_I => READ_DONE0_I, READ_DONE1_I => READ_DONE1_I, \TCSR0_GENERATE[23].TCSR0_FF_I\ => \TCSR0_GENERATE[23].TCSR0_FF_I\, \TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I_0\, \TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\, \TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\, \TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\, \bus2ip_addr_i_reg[4]\(2) => bus2ip_addr(0), \bus2ip_addr_i_reg[4]\(1) => bus2ip_addr(1), \bus2ip_addr_i_reg[4]\(0) => bus2ip_addr(2), bus2ip_rnw_i => bus2ip_rnw_i, bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0), is_read => is_read, is_write_reg => is_write_reg_n_0, pair0_Select => pair0_Select, read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0), read_done1 => read_done1, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_arvalid_0 => \state[1]_i_3_n_0\, s_axi_bready => s_axi_bready, s_axi_bvalid_i_reg => I_DECODER_n_101, s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\, \s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]_0\, \s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]_1\, \s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]_0\, \s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]_0\, \s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]_0\, \s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]_0\, \s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]_0\, \s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]_0\, \s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]_0\, \s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]_0\, \s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]_0\, \s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]_0\, \s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]_0\, \s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]_0\, \s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]_0\, \s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]_0\, \s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]_0\, \s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]_0\, \s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]_0\, \s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]_0\, \s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]_0\, \s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]_0\, \s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]_0\, \s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]_0\, s_axi_rready => s_axi_rready, s_axi_rvalid_i_reg => s_axi_rvalid_i_reg_0, s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg_1, s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_2, s_axi_rvalid_i_reg_2 => I_DECODER_n_100, s_axi_rvalid_i_reg_3 => \^s_axi_rvalid\, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => s_axi_wready, \state1__2\ => \state1__2\, \state_reg[1]\(1 downto 0) => state(1 downto 0) ); \bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFF0200" ) port map ( I0 => s_axi_araddr(0), I1 => state(0), I2 => state(1), I3 => s_axi_arvalid, I4 => s_axi_awaddr(0), O => \bus2ip_addr_i[2]_i_1_n_0\ ); \bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFF0200" ) port map ( I0 => s_axi_araddr(1), I1 => state(0), I2 => state(1), I3 => s_axi_arvalid, I4 => s_axi_awaddr(1), O => \bus2ip_addr_i[3]_i_1_n_0\ ); \bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000000EA" ) port map ( I0 => s_axi_arvalid, I1 => s_axi_awvalid, I2 => s_axi_wvalid, I3 => state(1), I4 => state(0), O => \bus2ip_addr_i[4]_i_1_n_0\ ); \bus2ip_addr_i[4]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFF0200" ) port map ( I0 => s_axi_araddr(2), I1 => state(0), I2 => state(1), I3 => s_axi_arvalid, I4 => s_axi_awaddr(2), O => \bus2ip_addr_i[4]_i_2_n_0\ ); \bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[4]_i_1_n_0\, D => \bus2ip_addr_i[2]_i_1_n_0\, Q => bus2ip_addr(2), R => rst ); \bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[4]_i_1_n_0\, D => \bus2ip_addr_i[3]_i_1_n_0\, Q => bus2ip_addr(1), R => rst ); \bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[4]_i_1_n_0\, D => \bus2ip_addr_i[4]_i_2_n_0\, Q => bus2ip_addr(0), R => rst ); bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"10" ) port map ( I0 => state(0), I1 => state(1), I2 => s_axi_arvalid, O => bus2ip_rnw_i06_out ); bus2ip_rnw_i_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[4]_i_1_n_0\, D => bus2ip_rnw_i06_out, Q => bus2ip_rnw_i, R => rst ); is_read_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"3FFA000A" ) port map ( I0 => s_axi_arvalid, I1 => \state1__2\, I2 => state(0), I3 => state(1), I4 => is_read, O => is_read_i_1_n_0 ); is_read_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => is_read_i_1_n_0, Q => is_read, R => rst ); is_write_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0040FFFF00400000" ) port map ( I0 => s_axi_arvalid, I1 => s_axi_awvalid, I2 => s_axi_wvalid, I3 => state(1), I4 => is_write, I5 => is_write_reg_n_0, O => is_write_i_1_n_0 ); is_write_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F88800000000FFFF" ) port map ( I0 => \^s_axi_rvalid\, I1 => s_axi_rready, I2 => \^s_axi_bvalid\, I3 => s_axi_bready, I4 => state(0), I5 => state(1), O => is_write ); is_write_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => is_write_i_1_n_0, Q => is_write_reg_n_0, R => rst ); rst_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => bus2ip_reset, Q => rst, R => '0' ); s_axi_bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => I_DECODER_n_101, Q => \^s_axi_bvalid\, R => rst ); \s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => state(0), I1 => state(1), O => \s_axi_rdata_i[31]_i_1_n_0\ ); \s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(0), Q => s_axi_rdata(0), R => rst ); \s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(10), Q => s_axi_rdata(10), R => rst ); \s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(11), Q => s_axi_rdata(11), R => rst ); \s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(12), Q => s_axi_rdata(12), R => rst ); \s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(13), Q => s_axi_rdata(13), R => rst ); \s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(14), Q => s_axi_rdata(14), R => rst ); \s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(15), Q => s_axi_rdata(15), R => rst ); \s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(16), Q => s_axi_rdata(16), R => rst ); \s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(17), Q => s_axi_rdata(17), R => rst ); \s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(18), Q => s_axi_rdata(18), R => rst ); \s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(19), Q => s_axi_rdata(19), R => rst ); \s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(1), Q => s_axi_rdata(1), R => rst ); \s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(20), Q => s_axi_rdata(20), R => rst ); \s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(21), Q => s_axi_rdata(21), R => rst ); \s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(22), Q => s_axi_rdata(22), R => rst ); \s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(23), Q => s_axi_rdata(23), R => rst ); \s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(24), Q => s_axi_rdata(24), R => rst ); \s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(25), Q => s_axi_rdata(25), R => rst ); \s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(26), Q => s_axi_rdata(26), R => rst ); \s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(27), Q => s_axi_rdata(27), R => rst ); \s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(28), Q => s_axi_rdata(28), R => rst ); \s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(29), Q => s_axi_rdata(29), R => rst ); \s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(2), Q => s_axi_rdata(2), R => rst ); \s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(30), Q => s_axi_rdata(30), R => rst ); \s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(31), Q => s_axi_rdata(31), R => rst ); \s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(3), Q => s_axi_rdata(3), R => rst ); \s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(4), Q => s_axi_rdata(4), R => rst ); \s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(5), Q => s_axi_rdata(5), R => rst ); \s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(6), Q => s_axi_rdata(6), R => rst ); \s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(7), Q => s_axi_rdata(7), R => rst ); \s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(8), Q => s_axi_rdata(8), R => rst ); \s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(9), Q => s_axi_rdata(9), R => rst ); s_axi_rvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => I_DECODER_n_100, Q => \^s_axi_rvalid\, R => rst ); start2_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"000000F8" ) port map ( I0 => s_axi_awvalid, I1 => s_axi_wvalid, I2 => s_axi_arvalid, I3 => state(1), I4 => state(0), O => start2_i_1_n_0 ); start2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => start2_i_1_n_0, Q => start2, R => rst ); \state[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"F888" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \state1__2\ ); \state[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => s_axi_wvalid, I1 => s_axi_awvalid, I2 => s_axi_arvalid, O => \state[1]_i_3_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => I_DECODER_n_26, Q => state(0), R => rst ); \state_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => I_DECODER_n_25, Q => state(1), R => rst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_tc_core is port ( D : out STD_LOGIC_VECTOR ( 31 downto 0 ); \INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 87 downto 0 ); bus2ip_reset : out STD_LOGIC; generateout0 : out STD_LOGIC; generateout1 : out STD_LOGIC; interrupt : out STD_LOGIC; D_0 : out STD_LOGIC; read_done1 : out STD_LOGIC; pwm0 : out STD_LOGIC; Bus_RNW_reg_reg : in STD_LOGIC; Bus_RNW_reg_reg_0 : in STD_LOGIC; Bus_RNW_reg_reg_1 : in STD_LOGIC; Bus_RNW_reg_reg_2 : in STD_LOGIC; Bus_RNW_reg_reg_3 : in STD_LOGIC; Bus_RNW_reg_reg_4 : in STD_LOGIC; Bus_RNW_reg_reg_5 : in STD_LOGIC; Bus_RNW_reg_reg_6 : in STD_LOGIC; Bus_RNW_reg_reg_7 : in STD_LOGIC; Bus_RNW_reg_reg_8 : in STD_LOGIC; Bus_RNW_reg_reg_9 : in STD_LOGIC; Bus_RNW_reg_reg_10 : in STD_LOGIC; Bus_RNW_reg_reg_11 : in STD_LOGIC; Bus_RNW_reg_reg_12 : in STD_LOGIC; Bus_RNW_reg_reg_13 : in STD_LOGIC; Bus_RNW_reg_reg_14 : in STD_LOGIC; Bus_RNW_reg_reg_15 : in STD_LOGIC; Bus_RNW_reg_reg_16 : in STD_LOGIC; Bus_RNW_reg_reg_17 : in STD_LOGIC; Bus_RNW_reg_reg_18 : in STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC; D_1 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC; D_2 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[0]_0\ : in STD_LOGIC; bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 ); pair0_Select : in STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC; Bus_RNW_reg : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC; \bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); freeze : in STD_LOGIC; capturetrig0 : in STD_LOGIC; capturetrig1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_tc_core : entity is "tc_core"; end zqynq_lab_1_design_axi_timer_0_1_tc_core; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_tc_core is signal COUNTER_0_I_n_64 : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_33\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_34\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_35\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_36\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_37\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_38\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_39\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_40\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_41\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_42\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_43\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_44\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_45\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_46\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_47\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_48\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_49\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_50\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_51\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_52\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_53\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_54\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_55\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_56\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_57\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_58\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_59\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_60\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_61\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_62\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_63\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_64\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_65\ : STD_LOGIC; signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC_VECTOR ( 87 downto 0 ); signal R : STD_LOGIC; signal TIMER_CONTROL_I_n_12 : STD_LOGIC; signal TIMER_CONTROL_I_n_13 : STD_LOGIC; signal TIMER_CONTROL_I_n_14 : STD_LOGIC; signal TIMER_CONTROL_I_n_15 : STD_LOGIC; signal TIMER_CONTROL_I_n_16 : STD_LOGIC; signal TIMER_CONTROL_I_n_17 : STD_LOGIC; signal TIMER_CONTROL_I_n_18 : STD_LOGIC; signal TIMER_CONTROL_I_n_19 : STD_LOGIC; signal TIMER_CONTROL_I_n_20 : STD_LOGIC; signal TIMER_CONTROL_I_n_21 : STD_LOGIC; signal TIMER_CONTROL_I_n_22 : STD_LOGIC; signal TIMER_CONTROL_I_n_24 : STD_LOGIC; signal TIMER_CONTROL_I_n_25 : STD_LOGIC; signal TIMER_CONTROL_I_n_26 : STD_LOGIC; signal TIMER_CONTROL_I_n_27 : STD_LOGIC; signal TIMER_CONTROL_I_n_28 : STD_LOGIC; signal TIMER_CONTROL_I_n_29 : STD_LOGIC; signal TIMER_CONTROL_I_n_3 : STD_LOGIC; signal TIMER_CONTROL_I_n_30 : STD_LOGIC; signal TIMER_CONTROL_I_n_4 : STD_LOGIC; signal \^bus2ip_reset\ : STD_LOGIC; signal counter_TC : STD_LOGIC_VECTOR ( 0 to 1 ); signal load_Counter_Reg : STD_LOGIC_VECTOR ( 0 to 1 ); signal \^pwm0\ : STD_LOGIC; signal read_Mux_In : STD_LOGIC_VECTOR ( 85 to 95 ); attribute BOX_TYPE : string; attribute BOX_TYPE of PWM_FF_I : label is "PRIMITIVE"; attribute IS_S_INVERTED : string; attribute IS_S_INVERTED of PWM_FF_I : label is "1'b0"; begin \INFERRED_GEN.icount_out_reg[0]\(87 downto 0) <= \^inferred_gen.icount_out_reg[0]\(87 downto 0); bus2ip_reset <= \^bus2ip_reset\; pwm0 <= \^pwm0\; COUNTER_0_I: entity work.zqynq_lab_1_design_axi_timer_0_1_count_module port map ( D_1 => D_1, E(0) => TIMER_CONTROL_I_n_24, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\, \INFERRED_GEN.icount_out_reg[31]\(52 downto 0) => \^inferred_gen.icount_out_reg[0]\(84 downto 32), Q(0) => TIMER_CONTROL_I_n_3, S(0) => TIMER_CONTROL_I_n_27, \TCSR0_GENERATE[27].TCSR0_FF_I\ => TIMER_CONTROL_I_n_28, counter_TC(0) => counter_TC(0), generateOutPre0_reg => COUNTER_0_I_n_64, load_Counter_Reg(0) => load_Counter_Reg(0), read_Mux_In(10) => read_Mux_In(85), read_Mux_In(9) => read_Mux_In(86), read_Mux_In(8) => read_Mux_In(87), read_Mux_In(7) => read_Mux_In(88), read_Mux_In(6) => read_Mux_In(89), read_Mux_In(5) => read_Mux_In(90), read_Mux_In(4) => read_Mux_In(91), read_Mux_In(3) => read_Mux_In(92), read_Mux_In(2) => read_Mux_In(93), read_Mux_In(1) => read_Mux_In(94), read_Mux_In(0) => read_Mux_In(95), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_aresetn_0 => \^bus2ip_reset\ ); \GEN_SECOND_TIMER.COUNTER_1_I\: entity work.zqynq_lab_1_design_axi_timer_0_1_count_module_0 port map ( D_2 => D_2, E(0) => TIMER_CONTROL_I_n_25, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\, \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, \INFERRED_GEN.icount_out_reg[0]\ => \INFERRED_GEN.icount_out_reg[0]_0\, \INFERRED_GEN.icount_out_reg[10]\ => \INFERRED_GEN.icount_out_reg[10]\, \INFERRED_GEN.icount_out_reg[11]\ => \INFERRED_GEN.icount_out_reg[11]\, \INFERRED_GEN.icount_out_reg[12]\ => \INFERRED_GEN.icount_out_reg[12]\, \INFERRED_GEN.icount_out_reg[13]\ => \INFERRED_GEN.icount_out_reg[13]\, \INFERRED_GEN.icount_out_reg[14]\ => \INFERRED_GEN.icount_out_reg[14]\, \INFERRED_GEN.icount_out_reg[15]\ => \INFERRED_GEN.icount_out_reg[15]\, \INFERRED_GEN.icount_out_reg[16]\ => \INFERRED_GEN.icount_out_reg[16]\, \INFERRED_GEN.icount_out_reg[17]\ => \INFERRED_GEN.icount_out_reg[17]\, \INFERRED_GEN.icount_out_reg[18]\ => \INFERRED_GEN.icount_out_reg[18]\, \INFERRED_GEN.icount_out_reg[19]\ => \INFERRED_GEN.icount_out_reg[19]\, \INFERRED_GEN.icount_out_reg[1]\ => \INFERRED_GEN.icount_out_reg[1]\, \INFERRED_GEN.icount_out_reg[20]\ => \INFERRED_GEN.icount_out_reg[20]\, \INFERRED_GEN.icount_out_reg[21]\ => \INFERRED_GEN.icount_out_reg[21]\, \INFERRED_GEN.icount_out_reg[22]\ => \INFERRED_GEN.icount_out_reg[22]\, \INFERRED_GEN.icount_out_reg[23]\ => \INFERRED_GEN.icount_out_reg[23]\, \INFERRED_GEN.icount_out_reg[24]\ => \INFERRED_GEN.icount_out_reg[24]\, \INFERRED_GEN.icount_out_reg[25]\ => \INFERRED_GEN.icount_out_reg[25]\, \INFERRED_GEN.icount_out_reg[26]\ => \INFERRED_GEN.icount_out_reg[26]\, \INFERRED_GEN.icount_out_reg[27]\ => \INFERRED_GEN.icount_out_reg[27]\, \INFERRED_GEN.icount_out_reg[28]\ => \INFERRED_GEN.icount_out_reg[28]\, \INFERRED_GEN.icount_out_reg[29]\ => \INFERRED_GEN.icount_out_reg[29]\, \INFERRED_GEN.icount_out_reg[2]\ => \INFERRED_GEN.icount_out_reg[2]\, \INFERRED_GEN.icount_out_reg[30]\ => \INFERRED_GEN.icount_out_reg[30]\, \INFERRED_GEN.icount_out_reg[31]\ => \^bus2ip_reset\, \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(63 downto 32), \INFERRED_GEN.icount_out_reg[3]\ => \INFERRED_GEN.icount_out_reg[3]\, \INFERRED_GEN.icount_out_reg[4]\ => \INFERRED_GEN.icount_out_reg[4]\, \INFERRED_GEN.icount_out_reg[5]\ => \INFERRED_GEN.icount_out_reg[5]\, \INFERRED_GEN.icount_out_reg[6]\ => \INFERRED_GEN.icount_out_reg[6]\, \INFERRED_GEN.icount_out_reg[7]\ => \INFERRED_GEN.icount_out_reg[7]\, \INFERRED_GEN.icount_out_reg[8]\ => \INFERRED_GEN.icount_out_reg[8]\, \INFERRED_GEN.icount_out_reg[9]\ => \INFERRED_GEN.icount_out_reg[9]\, Q(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(31 downto 0), S(0) => TIMER_CONTROL_I_n_30, \TCSR0_GENERATE[20].TCSR0_FF_I\ => TIMER_CONTROL_I_n_29, counter_TC(0) => counter_TC(1), \counter_TC_Reg_reg[1]\(0) => TIMER_CONTROL_I_n_4, generateOutPre1_reg => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\, load_Counter_Reg(0) => load_Counter_Reg(1), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, \s_axi_rdata_i_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\, \s_axi_rdata_i_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\, \s_axi_rdata_i_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\, \s_axi_rdata_i_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\, \s_axi_rdata_i_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\, \s_axi_rdata_i_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\, \s_axi_rdata_i_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\, \s_axi_rdata_i_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\, \s_axi_rdata_i_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\, \s_axi_rdata_i_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\, \s_axi_rdata_i_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\, \s_axi_rdata_i_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\, \s_axi_rdata_i_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\, \s_axi_rdata_i_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\, \s_axi_rdata_i_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\, \s_axi_rdata_i_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\, \s_axi_rdata_i_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\, \s_axi_rdata_i_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\, \s_axi_rdata_i_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\, \s_axi_rdata_i_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\, \s_axi_rdata_i_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\, \s_axi_rdata_i_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\, \s_axi_rdata_i_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\, \s_axi_rdata_i_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\, \s_axi_rdata_i_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\, \s_axi_rdata_i_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\, \s_axi_rdata_i_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\, \s_axi_rdata_i_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\, \s_axi_rdata_i_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\, \s_axi_rdata_i_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\, \s_axi_rdata_i_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\, \s_axi_rdata_i_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\ ); PWM_FF_I: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => TIMER_CONTROL_I_n_26, Q => \^pwm0\, R => R ); READ_MUX_I: entity work.zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f port map ( Bus_RNW_reg_reg => Bus_RNW_reg_reg, Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg_0, Bus_RNW_reg_reg_1 => Bus_RNW_reg_reg_1, Bus_RNW_reg_reg_10 => Bus_RNW_reg_reg_10, Bus_RNW_reg_reg_11 => Bus_RNW_reg_reg_11, Bus_RNW_reg_reg_12 => Bus_RNW_reg_reg_12, Bus_RNW_reg_reg_13 => Bus_RNW_reg_reg_13, Bus_RNW_reg_reg_14 => Bus_RNW_reg_reg_14, Bus_RNW_reg_reg_15 => Bus_RNW_reg_reg_15, Bus_RNW_reg_reg_16 => Bus_RNW_reg_reg_16, Bus_RNW_reg_reg_17 => Bus_RNW_reg_reg_17, Bus_RNW_reg_reg_18 => Bus_RNW_reg_reg_18, Bus_RNW_reg_reg_2 => Bus_RNW_reg_reg_2, Bus_RNW_reg_reg_3 => Bus_RNW_reg_reg_3, Bus_RNW_reg_reg_4 => Bus_RNW_reg_reg_4, Bus_RNW_reg_reg_5 => Bus_RNW_reg_reg_5, Bus_RNW_reg_reg_6 => Bus_RNW_reg_reg_6, Bus_RNW_reg_reg_7 => Bus_RNW_reg_reg_7, Bus_RNW_reg_reg_8 => Bus_RNW_reg_reg_8, Bus_RNW_reg_reg_9 => Bus_RNW_reg_reg_9, D(31 downto 0) => D(31 downto 0), \INFERRED_GEN.icount_out_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\, \INFERRED_GEN.icount_out_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\, \INFERRED_GEN.icount_out_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\, \INFERRED_GEN.icount_out_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\, \INFERRED_GEN.icount_out_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\, \INFERRED_GEN.icount_out_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\, \INFERRED_GEN.icount_out_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\, \INFERRED_GEN.icount_out_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\, \INFERRED_GEN.icount_out_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\, \INFERRED_GEN.icount_out_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\, \INFERRED_GEN.icount_out_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\, \INFERRED_GEN.icount_out_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\, \INFERRED_GEN.icount_out_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\, \INFERRED_GEN.icount_out_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\, \INFERRED_GEN.icount_out_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\, \INFERRED_GEN.icount_out_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\, \INFERRED_GEN.icount_out_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\, \INFERRED_GEN.icount_out_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\, \INFERRED_GEN.icount_out_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\, \INFERRED_GEN.icount_out_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\, \INFERRED_GEN.icount_out_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\, \INFERRED_GEN.icount_out_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\, \INFERRED_GEN.icount_out_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\, \INFERRED_GEN.icount_out_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\, \INFERRED_GEN.icount_out_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\, \INFERRED_GEN.icount_out_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\, \INFERRED_GEN.icount_out_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\, \INFERRED_GEN.icount_out_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\, \INFERRED_GEN.icount_out_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\, \INFERRED_GEN.icount_out_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\, \INFERRED_GEN.icount_out_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\, \INFERRED_GEN.icount_out_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\, \LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\, \LOAD_REG_GEN[21].LOAD_REG_I\ => TIMER_CONTROL_I_n_22, \LOAD_REG_GEN[22].LOAD_REG_I\ => TIMER_CONTROL_I_n_21, \LOAD_REG_GEN[23].LOAD_REG_I\ => TIMER_CONTROL_I_n_20, \LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_19, \LOAD_REG_GEN[25].LOAD_REG_I\ => TIMER_CONTROL_I_n_18, \LOAD_REG_GEN[26].LOAD_REG_I\ => TIMER_CONTROL_I_n_17, \LOAD_REG_GEN[27].LOAD_REG_I\ => TIMER_CONTROL_I_n_16, \LOAD_REG_GEN[28].LOAD_REG_I\ => TIMER_CONTROL_I_n_15, \LOAD_REG_GEN[29].LOAD_REG_I\ => TIMER_CONTROL_I_n_14, \LOAD_REG_GEN[30].LOAD_REG_I\ => TIMER_CONTROL_I_n_13, \LOAD_REG_GEN[31].LOAD_REG_I\ => TIMER_CONTROL_I_n_12 ); TIMER_CONTROL_I: entity work.zqynq_lab_1_design_axi_timer_0_1_timer_control port map ( Bus_RNW_reg => Bus_RNW_reg, D_0 => D_0, E(0) => TIMER_CONTROL_I_n_24, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, \INFERRED_GEN.icount_out_reg[0]\ => \^inferred_gen.icount_out_reg[0]\(87), \INFERRED_GEN.icount_out_reg[0]_0\(0) => TIMER_CONTROL_I_n_25, \INFERRED_GEN.icount_out_reg[1]\(1) => \^inferred_gen.icount_out_reg[0]\(33), \INFERRED_GEN.icount_out_reg[1]\(0) => \^inferred_gen.icount_out_reg[0]\(1), \INFERRED_GEN.icount_out_reg[32]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\, \INFERRED_GEN.icount_out_reg[32]_0\ => COUNTER_0_I_n_64, \INFERRED_GEN.icount_out_reg[4]\(0) => TIMER_CONTROL_I_n_30, \LOAD_REG_GEN[21].LOAD_REG_I\(10) => read_Mux_In(85), \LOAD_REG_GEN[21].LOAD_REG_I\(9) => read_Mux_In(86), \LOAD_REG_GEN[21].LOAD_REG_I\(8) => read_Mux_In(87), \LOAD_REG_GEN[21].LOAD_REG_I\(7) => read_Mux_In(88), \LOAD_REG_GEN[21].LOAD_REG_I\(6) => read_Mux_In(89), \LOAD_REG_GEN[21].LOAD_REG_I\(5) => read_Mux_In(90), \LOAD_REG_GEN[21].LOAD_REG_I\(4) => read_Mux_In(91), \LOAD_REG_GEN[21].LOAD_REG_I\(3) => read_Mux_In(92), \LOAD_REG_GEN[21].LOAD_REG_I\(2) => read_Mux_In(93), \LOAD_REG_GEN[21].LOAD_REG_I\(1) => read_Mux_In(94), \LOAD_REG_GEN[21].LOAD_REG_I\(0) => read_Mux_In(95), \LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_28, \LOAD_REG_GEN[24].LOAD_REG_I_0\ => TIMER_CONTROL_I_n_29, PWM_FF_I => TIMER_CONTROL_I_n_26, Q(1) => TIMER_CONTROL_I_n_3, Q(0) => TIMER_CONTROL_I_n_4, R => R, S(0) => TIMER_CONTROL_I_n_27, SR(0) => \^bus2ip_reset\, \TCSR0_GENERATE[24].TCSR0_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(86), \TCSR0_GENERATE[24].TCSR0_FF_I_1\ => \TCSR0_GENERATE[24].TCSR0_FF_I\, \TCSR1_GENERATE[23].TCSR1_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(85), \TCSR1_GENERATE[24].TCSR1_FF_I_0\ => \TCSR1_GENERATE[24].TCSR1_FF_I\, bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0), capturetrig0 => capturetrig0, capturetrig1 => capturetrig1, counter_TC(0 to 1) => counter_TC(0 to 1), freeze => freeze, generateout0 => generateout0, generateout1 => generateout1, interrupt => interrupt, load_Counter_Reg(0 to 1) => load_Counter_Reg(0 to 1), pair0_Select => pair0_Select, pwm0 => \^pwm0\, read_done1 => read_done1, s_axi_aclk => s_axi_aclk, \s_axi_rdata_i_reg[0]\ => TIMER_CONTROL_I_n_12, \s_axi_rdata_i_reg[10]\ => TIMER_CONTROL_I_n_22, \s_axi_rdata_i_reg[1]\ => TIMER_CONTROL_I_n_13, \s_axi_rdata_i_reg[2]\ => TIMER_CONTROL_I_n_14, \s_axi_rdata_i_reg[3]\ => TIMER_CONTROL_I_n_15, \s_axi_rdata_i_reg[4]\ => TIMER_CONTROL_I_n_16, \s_axi_rdata_i_reg[5]\ => TIMER_CONTROL_I_n_17, \s_axi_rdata_i_reg[6]\ => TIMER_CONTROL_I_n_18, \s_axi_rdata_i_reg[7]\ => TIMER_CONTROL_I_n_19, \s_axi_rdata_i_reg[8]\ => TIMER_CONTROL_I_n_20, \s_axi_rdata_i_reg[9]\ => TIMER_CONTROL_I_n_21, s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif is port ( \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC; Bus_RNW_reg : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; \s_axi_rdata_i_reg[12]\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC; pair0_Select : out STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; \s_axi_rdata_i_reg[11]\ : out STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC; \LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC; D_0 : out STD_LOGIC; \bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 ); \LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC; D_1 : out STD_LOGIC; s_axi_rvalid_i_reg : out STD_LOGIC; s_axi_rvalid_i_reg_0 : out STD_LOGIC; s_axi_rvalid_i_reg_1 : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC; \TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC; READ_DONE0_I : out STD_LOGIC; READ_DONE1_I : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); bus2ip_reset : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 ); s_axi_aresetn : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); D_2 : in STD_LOGIC; read_done1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif : entity is "axi_lite_ipif"; end zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif is begin I_SLAVE_ATTACHMENT: entity work.zqynq_lab_1_design_axi_timer_0_1_slave_attachment port map ( D(31 downto 0) => D(31 downto 0), D_0 => D_0, D_1 => D_1, D_2 => D_2, \LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\, \LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\, \LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\, \LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\, \LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\, \LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\, \LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\, \LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\, \LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\, \LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\, \LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\, \LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\, \LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\, \LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\, \LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\, \LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\, \LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\, \LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\, \LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\, \LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\, \LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\, \LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\, \LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\, \LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\, \LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\, \LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\, \LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\, \LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\, \LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\, \LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\, \LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\, \LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\, \LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\, \LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\, \LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\, \LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\, \LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\, \LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\, \LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\, \LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\, \LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\, \LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\, \LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\, \LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\, \LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\, \LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\, \LOAD_REG_GEN[31].LOAD_REG_I\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I\, \LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\, \LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\, \LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\, \LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\, \LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\, \LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\, \LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\, \LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\, \LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\, \LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\, \LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\, \LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\, \LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\, \LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\, \LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\, READ_DONE0_I => READ_DONE0_I, READ_DONE1_I => READ_DONE1_I, \TCSR0_GENERATE[23].TCSR0_FF_I\ => Bus_RNW_reg, \TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I\, \TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\, \TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\, \TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\, bus2ip_reset => bus2ip_reset, bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0), pair0_Select => pair0_Select, read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0), read_done1 => read_done1, s_axi_aclk => s_axi_aclk, s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), \s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]\, \s_axi_rdata_i_reg[0]_1\ => \s_axi_rdata_i_reg[0]_0\, \s_axi_rdata_i_reg[10]_0\ => \s_axi_rdata_i_reg[10]\, \s_axi_rdata_i_reg[11]_0\ => \s_axi_rdata_i_reg[11]\, \s_axi_rdata_i_reg[12]_0\ => \s_axi_rdata_i_reg[12]\, \s_axi_rdata_i_reg[13]_0\ => \s_axi_rdata_i_reg[13]\, \s_axi_rdata_i_reg[14]_0\ => \s_axi_rdata_i_reg[14]\, \s_axi_rdata_i_reg[15]_0\ => \s_axi_rdata_i_reg[15]\, \s_axi_rdata_i_reg[16]_0\ => \s_axi_rdata_i_reg[16]\, \s_axi_rdata_i_reg[17]_0\ => \s_axi_rdata_i_reg[17]\, \s_axi_rdata_i_reg[18]_0\ => \s_axi_rdata_i_reg[18]\, \s_axi_rdata_i_reg[19]_0\ => \s_axi_rdata_i_reg[19]\, \s_axi_rdata_i_reg[20]_0\ => \s_axi_rdata_i_reg[20]\, \s_axi_rdata_i_reg[21]_0\ => \s_axi_rdata_i_reg[21]\, \s_axi_rdata_i_reg[22]_0\ => \s_axi_rdata_i_reg[22]\, \s_axi_rdata_i_reg[23]_0\ => \s_axi_rdata_i_reg[23]\, \s_axi_rdata_i_reg[24]_0\ => \s_axi_rdata_i_reg[24]\, \s_axi_rdata_i_reg[25]_0\ => \s_axi_rdata_i_reg[25]\, \s_axi_rdata_i_reg[26]_0\ => \s_axi_rdata_i_reg[26]\, \s_axi_rdata_i_reg[27]_0\ => \s_axi_rdata_i_reg[27]\, \s_axi_rdata_i_reg[28]_0\ => \s_axi_rdata_i_reg[28]\, \s_axi_rdata_i_reg[29]_0\ => \s_axi_rdata_i_reg[29]\, \s_axi_rdata_i_reg[30]_0\ => \s_axi_rdata_i_reg[30]\, \s_axi_rdata_i_reg[31]_0\ => \s_axi_rdata_i_reg[31]\, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg, s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_0, s_axi_rvalid_i_reg_2 => s_axi_rvalid_i_reg_1, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => s_axi_wready, s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1_axi_timer is port ( capturetrig0 : in STD_LOGIC; capturetrig1 : in STD_LOGIC; generateout0 : out STD_LOGIC; generateout1 : out STD_LOGIC; pwm0 : out STD_LOGIC; interrupt : out STD_LOGIC; freeze : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC ); attribute C_COUNT_WIDTH : integer; attribute C_COUNT_WIDTH of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is 32; attribute C_FAMILY : string; attribute C_FAMILY of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "zynq"; attribute C_GEN0_ASSERT : string; attribute C_GEN0_ASSERT of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "1'b1"; attribute C_GEN1_ASSERT : string; attribute C_GEN1_ASSERT of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "1'b1"; attribute C_ONE_TIMER_ONLY : integer; attribute C_ONE_TIMER_ONLY of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is 5; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is 32; attribute C_TRIG0_ASSERT : string; attribute C_TRIG0_ASSERT of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "1'b1"; attribute C_TRIG1_ASSERT : string; attribute C_TRIG1_ASSERT of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "1'b1"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "axi_timer"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "yes"; end zqynq_lab_1_design_axi_timer_0_1_axi_timer; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_axi_timer is signal \<const0>\ : STD_LOGIC; signal AXI4_LITE_I_n_10 : STD_LOGIC; signal AXI4_LITE_I_n_100 : STD_LOGIC; signal AXI4_LITE_I_n_101 : STD_LOGIC; signal AXI4_LITE_I_n_102 : STD_LOGIC; signal AXI4_LITE_I_n_103 : STD_LOGIC; signal AXI4_LITE_I_n_104 : STD_LOGIC; signal AXI4_LITE_I_n_105 : STD_LOGIC; signal AXI4_LITE_I_n_106 : STD_LOGIC; signal AXI4_LITE_I_n_11 : STD_LOGIC; signal AXI4_LITE_I_n_12 : STD_LOGIC; signal AXI4_LITE_I_n_13 : STD_LOGIC; signal AXI4_LITE_I_n_14 : STD_LOGIC; signal AXI4_LITE_I_n_15 : STD_LOGIC; signal AXI4_LITE_I_n_16 : STD_LOGIC; signal AXI4_LITE_I_n_17 : STD_LOGIC; signal AXI4_LITE_I_n_18 : STD_LOGIC; signal AXI4_LITE_I_n_19 : STD_LOGIC; signal AXI4_LITE_I_n_20 : STD_LOGIC; signal AXI4_LITE_I_n_21 : STD_LOGIC; signal AXI4_LITE_I_n_22 : STD_LOGIC; signal AXI4_LITE_I_n_23 : STD_LOGIC; signal AXI4_LITE_I_n_27 : STD_LOGIC; signal AXI4_LITE_I_n_28 : STD_LOGIC; signal AXI4_LITE_I_n_29 : STD_LOGIC; signal AXI4_LITE_I_n_30 : STD_LOGIC; signal AXI4_LITE_I_n_31 : STD_LOGIC; signal AXI4_LITE_I_n_32 : STD_LOGIC; signal AXI4_LITE_I_n_33 : STD_LOGIC; signal AXI4_LITE_I_n_34 : STD_LOGIC; signal AXI4_LITE_I_n_35 : STD_LOGIC; signal AXI4_LITE_I_n_36 : STD_LOGIC; signal AXI4_LITE_I_n_37 : STD_LOGIC; signal AXI4_LITE_I_n_38 : STD_LOGIC; signal AXI4_LITE_I_n_39 : STD_LOGIC; signal AXI4_LITE_I_n_4 : STD_LOGIC; signal AXI4_LITE_I_n_40 : STD_LOGIC; signal AXI4_LITE_I_n_41 : STD_LOGIC; signal AXI4_LITE_I_n_42 : STD_LOGIC; signal AXI4_LITE_I_n_43 : STD_LOGIC; signal AXI4_LITE_I_n_44 : STD_LOGIC; signal AXI4_LITE_I_n_45 : STD_LOGIC; signal AXI4_LITE_I_n_46 : STD_LOGIC; signal AXI4_LITE_I_n_47 : STD_LOGIC; signal AXI4_LITE_I_n_48 : STD_LOGIC; signal AXI4_LITE_I_n_49 : STD_LOGIC; signal AXI4_LITE_I_n_5 : STD_LOGIC; signal AXI4_LITE_I_n_50 : STD_LOGIC; signal AXI4_LITE_I_n_51 : STD_LOGIC; signal AXI4_LITE_I_n_52 : STD_LOGIC; signal AXI4_LITE_I_n_53 : STD_LOGIC; signal AXI4_LITE_I_n_54 : STD_LOGIC; signal AXI4_LITE_I_n_55 : STD_LOGIC; signal AXI4_LITE_I_n_56 : STD_LOGIC; signal AXI4_LITE_I_n_57 : STD_LOGIC; signal AXI4_LITE_I_n_58 : STD_LOGIC; signal AXI4_LITE_I_n_59 : STD_LOGIC; signal AXI4_LITE_I_n_6 : STD_LOGIC; signal AXI4_LITE_I_n_60 : STD_LOGIC; signal AXI4_LITE_I_n_65 : STD_LOGIC; signal AXI4_LITE_I_n_66 : STD_LOGIC; signal AXI4_LITE_I_n_67 : STD_LOGIC; signal AXI4_LITE_I_n_68 : STD_LOGIC; signal AXI4_LITE_I_n_69 : STD_LOGIC; signal AXI4_LITE_I_n_7 : STD_LOGIC; signal AXI4_LITE_I_n_70 : STD_LOGIC; signal AXI4_LITE_I_n_71 : STD_LOGIC; signal AXI4_LITE_I_n_72 : STD_LOGIC; signal AXI4_LITE_I_n_73 : STD_LOGIC; signal AXI4_LITE_I_n_74 : STD_LOGIC; signal AXI4_LITE_I_n_75 : STD_LOGIC; signal AXI4_LITE_I_n_76 : STD_LOGIC; signal AXI4_LITE_I_n_77 : STD_LOGIC; signal AXI4_LITE_I_n_78 : STD_LOGIC; signal AXI4_LITE_I_n_79 : STD_LOGIC; signal AXI4_LITE_I_n_8 : STD_LOGIC; signal AXI4_LITE_I_n_80 : STD_LOGIC; signal AXI4_LITE_I_n_81 : STD_LOGIC; signal AXI4_LITE_I_n_82 : STD_LOGIC; signal AXI4_LITE_I_n_83 : STD_LOGIC; signal AXI4_LITE_I_n_84 : STD_LOGIC; signal AXI4_LITE_I_n_85 : STD_LOGIC; signal AXI4_LITE_I_n_86 : STD_LOGIC; signal AXI4_LITE_I_n_87 : STD_LOGIC; signal AXI4_LITE_I_n_88 : STD_LOGIC; signal AXI4_LITE_I_n_89 : STD_LOGIC; signal AXI4_LITE_I_n_9 : STD_LOGIC; signal AXI4_LITE_I_n_90 : STD_LOGIC; signal AXI4_LITE_I_n_91 : STD_LOGIC; signal AXI4_LITE_I_n_92 : STD_LOGIC; signal AXI4_LITE_I_n_93 : STD_LOGIC; signal AXI4_LITE_I_n_94 : STD_LOGIC; signal AXI4_LITE_I_n_95 : STD_LOGIC; signal AXI4_LITE_I_n_97 : STD_LOGIC; signal AXI4_LITE_I_n_98 : STD_LOGIC; signal AXI4_LITE_I_n_99 : STD_LOGIC; signal \COUNTER_0_I/D\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I/D\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC; signal \TIMER_CONTROL_I/D\ : STD_LOGIC; signal \TIMER_CONTROL_I/pair0_Select\ : STD_LOGIC; signal \TIMER_CONTROL_I/read_done1\ : STD_LOGIC; signal bus2ip_reset : STD_LOGIC; signal bus2ip_wrce : STD_LOGIC_VECTOR ( 0 to 4 ); signal \bus2ip_wrce__0\ : STD_LOGIC_VECTOR ( 5 to 5 ); signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 ); signal read_Mux_In : STD_LOGIC_VECTOR ( 20 to 191 ); signal \^s_axi_wready\ : STD_LOGIC; begin s_axi_awready <= \^s_axi_wready\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_wready <= \^s_axi_wready\; AXI4_LITE_I: entity work.zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif port map ( Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, D(31) => ip2bus_data(0), D(30) => ip2bus_data(1), D(29) => ip2bus_data(2), D(28) => ip2bus_data(3), D(27) => ip2bus_data(4), D(26) => ip2bus_data(5), D(25) => ip2bus_data(6), D(24) => ip2bus_data(7), D(23) => ip2bus_data(8), D(22) => ip2bus_data(9), D(21) => ip2bus_data(10), D(20) => ip2bus_data(11), D(19) => ip2bus_data(12), D(18) => ip2bus_data(13), D(17) => ip2bus_data(14), D(16) => ip2bus_data(15), D(15) => ip2bus_data(16), D(14) => ip2bus_data(17), D(13) => ip2bus_data(18), D(12) => ip2bus_data(19), D(11) => ip2bus_data(20), D(10) => ip2bus_data(21), D(9) => ip2bus_data(22), D(8) => ip2bus_data(23), D(7) => ip2bus_data(24), D(6) => ip2bus_data(25), D(5) => ip2bus_data(26), D(4) => ip2bus_data(27), D(3) => ip2bus_data(28), D(2) => ip2bus_data(29), D(1) => ip2bus_data(30), D(0) => ip2bus_data(31), D_0 => \GEN_SECOND_TIMER.COUNTER_1_I/D\, D_1 => \COUNTER_0_I/D\, D_2 => \TIMER_CONTROL_I/D\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \LOAD_REG_GEN[10].LOAD_REG_I\ => AXI4_LITE_I_n_51, \LOAD_REG_GEN[10].LOAD_REG_I_0\ => AXI4_LITE_I_n_86, \LOAD_REG_GEN[11].LOAD_REG_I\ => AXI4_LITE_I_n_50, \LOAD_REG_GEN[11].LOAD_REG_I_0\ => AXI4_LITE_I_n_85, \LOAD_REG_GEN[12].LOAD_REG_I\ => AXI4_LITE_I_n_49, \LOAD_REG_GEN[12].LOAD_REG_I_0\ => AXI4_LITE_I_n_84, \LOAD_REG_GEN[13].LOAD_REG_I\ => AXI4_LITE_I_n_48, \LOAD_REG_GEN[13].LOAD_REG_I_0\ => AXI4_LITE_I_n_83, \LOAD_REG_GEN[14].LOAD_REG_I\ => AXI4_LITE_I_n_47, \LOAD_REG_GEN[14].LOAD_REG_I_0\ => AXI4_LITE_I_n_82, \LOAD_REG_GEN[15].LOAD_REG_I\ => AXI4_LITE_I_n_46, \LOAD_REG_GEN[15].LOAD_REG_I_0\ => AXI4_LITE_I_n_81, \LOAD_REG_GEN[16].LOAD_REG_I\ => AXI4_LITE_I_n_45, \LOAD_REG_GEN[16].LOAD_REG_I_0\ => AXI4_LITE_I_n_80, \LOAD_REG_GEN[17].LOAD_REG_I\ => AXI4_LITE_I_n_44, \LOAD_REG_GEN[17].LOAD_REG_I_0\ => AXI4_LITE_I_n_79, \LOAD_REG_GEN[18].LOAD_REG_I\ => AXI4_LITE_I_n_43, \LOAD_REG_GEN[18].LOAD_REG_I_0\ => AXI4_LITE_I_n_78, \LOAD_REG_GEN[19].LOAD_REG_I\ => AXI4_LITE_I_n_42, \LOAD_REG_GEN[19].LOAD_REG_I_0\ => AXI4_LITE_I_n_77, \LOAD_REG_GEN[1].LOAD_REG_I\ => AXI4_LITE_I_n_60, \LOAD_REG_GEN[1].LOAD_REG_I_0\ => AXI4_LITE_I_n_95, \LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_41, \LOAD_REG_GEN[20].LOAD_REG_I_0\ => AXI4_LITE_I_n_76, \LOAD_REG_GEN[21].LOAD_REG_I\ => AXI4_LITE_I_n_40, \LOAD_REG_GEN[21].LOAD_REG_I_0\ => AXI4_LITE_I_n_75, \LOAD_REG_GEN[22].LOAD_REG_I\ => AXI4_LITE_I_n_39, \LOAD_REG_GEN[22].LOAD_REG_I_0\ => AXI4_LITE_I_n_74, \LOAD_REG_GEN[23].LOAD_REG_I\ => AXI4_LITE_I_n_38, \LOAD_REG_GEN[23].LOAD_REG_I_0\ => AXI4_LITE_I_n_73, \LOAD_REG_GEN[24].LOAD_REG_I\ => AXI4_LITE_I_n_37, \LOAD_REG_GEN[24].LOAD_REG_I_0\ => AXI4_LITE_I_n_72, \LOAD_REG_GEN[25].LOAD_REG_I\ => AXI4_LITE_I_n_36, \LOAD_REG_GEN[25].LOAD_REG_I_0\ => AXI4_LITE_I_n_71, \LOAD_REG_GEN[26].LOAD_REG_I\ => AXI4_LITE_I_n_35, \LOAD_REG_GEN[26].LOAD_REG_I_0\ => AXI4_LITE_I_n_70, \LOAD_REG_GEN[27].LOAD_REG_I\ => AXI4_LITE_I_n_34, \LOAD_REG_GEN[27].LOAD_REG_I_0\ => AXI4_LITE_I_n_69, \LOAD_REG_GEN[28].LOAD_REG_I\ => AXI4_LITE_I_n_33, \LOAD_REG_GEN[28].LOAD_REG_I_0\ => AXI4_LITE_I_n_68, \LOAD_REG_GEN[29].LOAD_REG_I\ => AXI4_LITE_I_n_32, \LOAD_REG_GEN[29].LOAD_REG_I_0\ => AXI4_LITE_I_n_67, \LOAD_REG_GEN[2].LOAD_REG_I\ => AXI4_LITE_I_n_59, \LOAD_REG_GEN[2].LOAD_REG_I_0\ => AXI4_LITE_I_n_94, \LOAD_REG_GEN[30].LOAD_REG_I\ => AXI4_LITE_I_n_31, \LOAD_REG_GEN[30].LOAD_REG_I_0\ => AXI4_LITE_I_n_66, \LOAD_REG_GEN[31].LOAD_REG_I\ => AXI4_LITE_I_n_30, \LOAD_REG_GEN[31].LOAD_REG_I_0\ => AXI4_LITE_I_n_65, \LOAD_REG_GEN[3].LOAD_REG_I\ => AXI4_LITE_I_n_58, \LOAD_REG_GEN[3].LOAD_REG_I_0\ => AXI4_LITE_I_n_93, \LOAD_REG_GEN[4].LOAD_REG_I\ => AXI4_LITE_I_n_57, \LOAD_REG_GEN[4].LOAD_REG_I_0\ => AXI4_LITE_I_n_92, \LOAD_REG_GEN[5].LOAD_REG_I\ => AXI4_LITE_I_n_56, \LOAD_REG_GEN[5].LOAD_REG_I_0\ => AXI4_LITE_I_n_91, \LOAD_REG_GEN[6].LOAD_REG_I\ => AXI4_LITE_I_n_55, \LOAD_REG_GEN[6].LOAD_REG_I_0\ => AXI4_LITE_I_n_90, \LOAD_REG_GEN[7].LOAD_REG_I\ => AXI4_LITE_I_n_54, \LOAD_REG_GEN[7].LOAD_REG_I_0\ => AXI4_LITE_I_n_89, \LOAD_REG_GEN[8].LOAD_REG_I\ => AXI4_LITE_I_n_53, \LOAD_REG_GEN[8].LOAD_REG_I_0\ => AXI4_LITE_I_n_88, \LOAD_REG_GEN[9].LOAD_REG_I\ => AXI4_LITE_I_n_52, \LOAD_REG_GEN[9].LOAD_REG_I_0\ => AXI4_LITE_I_n_87, READ_DONE0_I => AXI4_LITE_I_n_105, READ_DONE1_I => AXI4_LITE_I_n_106, \TCSR0_GENERATE[23].TCSR0_FF_I\ => AXI4_LITE_I_n_100, \TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28, \TCSR1_GENERATE[23].TCSR1_FF_I\ => AXI4_LITE_I_n_101, \TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29, bus2ip_reset => bus2ip_reset, bus2ip_wrce(1) => bus2ip_wrce(0), bus2ip_wrce(0) => bus2ip_wrce(4), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5), pair0_Select => \TIMER_CONTROL_I/pair0_Select\, read_Mux_In(87) => read_Mux_In(20), read_Mux_In(86) => read_Mux_In(24), read_Mux_In(85) => read_Mux_In(56), read_Mux_In(84) => read_Mux_In(64), read_Mux_In(83) => read_Mux_In(65), read_Mux_In(82) => read_Mux_In(66), read_Mux_In(81) => read_Mux_In(67), read_Mux_In(80) => read_Mux_In(68), read_Mux_In(79) => read_Mux_In(69), read_Mux_In(78) => read_Mux_In(70), read_Mux_In(77) => read_Mux_In(71), read_Mux_In(76) => read_Mux_In(72), read_Mux_In(75) => read_Mux_In(73), read_Mux_In(74) => read_Mux_In(74), read_Mux_In(73) => read_Mux_In(75), read_Mux_In(72) => read_Mux_In(76), read_Mux_In(71) => read_Mux_In(77), read_Mux_In(70) => read_Mux_In(78), read_Mux_In(69) => read_Mux_In(79), read_Mux_In(68) => read_Mux_In(80), read_Mux_In(67) => read_Mux_In(81), read_Mux_In(66) => read_Mux_In(82), read_Mux_In(65) => read_Mux_In(83), read_Mux_In(64) => read_Mux_In(84), read_Mux_In(63) => read_Mux_In(128), read_Mux_In(62) => read_Mux_In(129), read_Mux_In(61) => read_Mux_In(130), read_Mux_In(60) => read_Mux_In(131), read_Mux_In(59) => read_Mux_In(132), read_Mux_In(58) => read_Mux_In(133), read_Mux_In(57) => read_Mux_In(134), read_Mux_In(56) => read_Mux_In(135), read_Mux_In(55) => read_Mux_In(136), read_Mux_In(54) => read_Mux_In(137), read_Mux_In(53) => read_Mux_In(138), read_Mux_In(52) => read_Mux_In(139), read_Mux_In(51) => read_Mux_In(140), read_Mux_In(50) => read_Mux_In(141), read_Mux_In(49) => read_Mux_In(142), read_Mux_In(48) => read_Mux_In(143), read_Mux_In(47) => read_Mux_In(144), read_Mux_In(46) => read_Mux_In(145), read_Mux_In(45) => read_Mux_In(146), read_Mux_In(44) => read_Mux_In(147), read_Mux_In(43) => read_Mux_In(148), read_Mux_In(42) => read_Mux_In(149), read_Mux_In(41) => read_Mux_In(150), read_Mux_In(40) => read_Mux_In(151), read_Mux_In(39) => read_Mux_In(152), read_Mux_In(38) => read_Mux_In(153), read_Mux_In(37) => read_Mux_In(154), read_Mux_In(36) => read_Mux_In(155), read_Mux_In(35) => read_Mux_In(156), read_Mux_In(34) => read_Mux_In(157), read_Mux_In(33) => read_Mux_In(158), read_Mux_In(32) => read_Mux_In(159), read_Mux_In(31) => read_Mux_In(160), read_Mux_In(30) => read_Mux_In(161), read_Mux_In(29) => read_Mux_In(162), read_Mux_In(28) => read_Mux_In(163), read_Mux_In(27) => read_Mux_In(164), read_Mux_In(26) => read_Mux_In(165), read_Mux_In(25) => read_Mux_In(166), read_Mux_In(24) => read_Mux_In(167), read_Mux_In(23) => read_Mux_In(168), read_Mux_In(22) => read_Mux_In(169), read_Mux_In(21) => read_Mux_In(170), read_Mux_In(20) => read_Mux_In(171), read_Mux_In(19) => read_Mux_In(172), read_Mux_In(18) => read_Mux_In(173), read_Mux_In(17) => read_Mux_In(174), read_Mux_In(16) => read_Mux_In(175), read_Mux_In(15) => read_Mux_In(176), read_Mux_In(14) => read_Mux_In(177), read_Mux_In(13) => read_Mux_In(178), read_Mux_In(12) => read_Mux_In(179), read_Mux_In(11) => read_Mux_In(180), read_Mux_In(10) => read_Mux_In(181), read_Mux_In(9) => read_Mux_In(182), read_Mux_In(8) => read_Mux_In(183), read_Mux_In(7) => read_Mux_In(184), read_Mux_In(6) => read_Mux_In(185), read_Mux_In(5) => read_Mux_In(186), read_Mux_In(4) => read_Mux_In(187), read_Mux_In(3) => read_Mux_In(188), read_Mux_In(2) => read_Mux_In(189), read_Mux_In(1) => read_Mux_In(190), read_Mux_In(0) => read_Mux_In(191), read_done1 => \TIMER_CONTROL_I/read_done1\, s_axi_aclk => s_axi_aclk, s_axi_araddr(2 downto 0) => s_axi_araddr(4 downto 2), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(2 downto 0) => s_axi_awaddr(4 downto 2), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), \s_axi_rdata_i_reg[0]\ => AXI4_LITE_I_n_103, \s_axi_rdata_i_reg[0]_0\ => AXI4_LITE_I_n_104, \s_axi_rdata_i_reg[10]\ => AXI4_LITE_I_n_102, \s_axi_rdata_i_reg[11]\ => AXI4_LITE_I_n_27, \s_axi_rdata_i_reg[12]\ => AXI4_LITE_I_n_4, \s_axi_rdata_i_reg[13]\ => AXI4_LITE_I_n_5, \s_axi_rdata_i_reg[14]\ => AXI4_LITE_I_n_6, \s_axi_rdata_i_reg[15]\ => AXI4_LITE_I_n_7, \s_axi_rdata_i_reg[16]\ => AXI4_LITE_I_n_8, \s_axi_rdata_i_reg[17]\ => AXI4_LITE_I_n_9, \s_axi_rdata_i_reg[18]\ => AXI4_LITE_I_n_10, \s_axi_rdata_i_reg[19]\ => AXI4_LITE_I_n_11, \s_axi_rdata_i_reg[20]\ => AXI4_LITE_I_n_12, \s_axi_rdata_i_reg[21]\ => AXI4_LITE_I_n_13, \s_axi_rdata_i_reg[22]\ => AXI4_LITE_I_n_14, \s_axi_rdata_i_reg[23]\ => AXI4_LITE_I_n_15, \s_axi_rdata_i_reg[24]\ => AXI4_LITE_I_n_16, \s_axi_rdata_i_reg[25]\ => AXI4_LITE_I_n_17, \s_axi_rdata_i_reg[26]\ => AXI4_LITE_I_n_18, \s_axi_rdata_i_reg[27]\ => AXI4_LITE_I_n_19, \s_axi_rdata_i_reg[28]\ => AXI4_LITE_I_n_20, \s_axi_rdata_i_reg[29]\ => AXI4_LITE_I_n_21, \s_axi_rdata_i_reg[30]\ => AXI4_LITE_I_n_22, \s_axi_rdata_i_reg[31]\ => AXI4_LITE_I_n_23, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_rvalid_i_reg => AXI4_LITE_I_n_97, s_axi_rvalid_i_reg_0 => AXI4_LITE_I_n_98, s_axi_rvalid_i_reg_1 => AXI4_LITE_I_n_99, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => \^s_axi_wready\, s_axi_wvalid => s_axi_wvalid ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); TC_CORE_I: entity work.zqynq_lab_1_design_axi_timer_0_1_tc_core port map ( Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, Bus_RNW_reg_reg => AXI4_LITE_I_n_23, Bus_RNW_reg_reg_0 => AXI4_LITE_I_n_22, Bus_RNW_reg_reg_1 => AXI4_LITE_I_n_21, Bus_RNW_reg_reg_10 => AXI4_LITE_I_n_12, Bus_RNW_reg_reg_11 => AXI4_LITE_I_n_11, Bus_RNW_reg_reg_12 => AXI4_LITE_I_n_10, Bus_RNW_reg_reg_13 => AXI4_LITE_I_n_9, Bus_RNW_reg_reg_14 => AXI4_LITE_I_n_8, Bus_RNW_reg_reg_15 => AXI4_LITE_I_n_7, Bus_RNW_reg_reg_16 => AXI4_LITE_I_n_6, Bus_RNW_reg_reg_17 => AXI4_LITE_I_n_5, Bus_RNW_reg_reg_18 => AXI4_LITE_I_n_4, Bus_RNW_reg_reg_2 => AXI4_LITE_I_n_20, Bus_RNW_reg_reg_3 => AXI4_LITE_I_n_19, Bus_RNW_reg_reg_4 => AXI4_LITE_I_n_18, Bus_RNW_reg_reg_5 => AXI4_LITE_I_n_17, Bus_RNW_reg_reg_6 => AXI4_LITE_I_n_16, Bus_RNW_reg_reg_7 => AXI4_LITE_I_n_15, Bus_RNW_reg_reg_8 => AXI4_LITE_I_n_14, Bus_RNW_reg_reg_9 => AXI4_LITE_I_n_13, D(31) => ip2bus_data(0), D(30) => ip2bus_data(1), D(29) => ip2bus_data(2), D(28) => ip2bus_data(3), D(27) => ip2bus_data(4), D(26) => ip2bus_data(5), D(25) => ip2bus_data(6), D(24) => ip2bus_data(7), D(23) => ip2bus_data(8), D(22) => ip2bus_data(9), D(21) => ip2bus_data(10), D(20) => ip2bus_data(11), D(19) => ip2bus_data(12), D(18) => ip2bus_data(13), D(17) => ip2bus_data(14), D(16) => ip2bus_data(15), D(15) => ip2bus_data(16), D(14) => ip2bus_data(17), D(13) => ip2bus_data(18), D(12) => ip2bus_data(19), D(11) => ip2bus_data(20), D(10) => ip2bus_data(21), D(9) => ip2bus_data(22), D(8) => ip2bus_data(23), D(7) => ip2bus_data(24), D(6) => ip2bus_data(25), D(5) => ip2bus_data(26), D(4) => ip2bus_data(27), D(3) => ip2bus_data(28), D(2) => ip2bus_data(29), D(1) => ip2bus_data(30), D(0) => ip2bus_data(31), D_0 => \TIMER_CONTROL_I/D\, D_1 => \COUNTER_0_I/D\, D_2 => \GEN_SECOND_TIMER.COUNTER_1_I/D\, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI4_LITE_I_n_100, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => AXI4_LITE_I_n_102, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI4_LITE_I_n_95, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => AXI4_LITE_I_n_94, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => AXI4_LITE_I_n_93, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => AXI4_LITE_I_n_84, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => AXI4_LITE_I_n_83, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => AXI4_LITE_I_n_82, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => AXI4_LITE_I_n_81, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => AXI4_LITE_I_n_80, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => AXI4_LITE_I_n_79, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => AXI4_LITE_I_n_78, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => AXI4_LITE_I_n_77, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => AXI4_LITE_I_n_76, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => AXI4_LITE_I_n_75, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => AXI4_LITE_I_n_92, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => AXI4_LITE_I_n_74, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => AXI4_LITE_I_n_73, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => AXI4_LITE_I_n_72, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => AXI4_LITE_I_n_71, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => AXI4_LITE_I_n_70, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => AXI4_LITE_I_n_69, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => AXI4_LITE_I_n_68, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => AXI4_LITE_I_n_67, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => AXI4_LITE_I_n_66, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => AXI4_LITE_I_n_65, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => AXI4_LITE_I_n_91, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ => AXI4_LITE_I_n_105, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ => AXI4_LITE_I_n_97, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => AXI4_LITE_I_n_90, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => AXI4_LITE_I_n_89, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => AXI4_LITE_I_n_88, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => AXI4_LITE_I_n_87, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => AXI4_LITE_I_n_86, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => AXI4_LITE_I_n_85, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => AXI4_LITE_I_n_99, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI4_LITE_I_n_101, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => AXI4_LITE_I_n_98, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => AXI4_LITE_I_n_106, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ => AXI4_LITE_I_n_103, \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => AXI4_LITE_I_n_104, \INFERRED_GEN.icount_out_reg[0]\(87) => read_Mux_In(20), \INFERRED_GEN.icount_out_reg[0]\(86) => read_Mux_In(24), \INFERRED_GEN.icount_out_reg[0]\(85) => read_Mux_In(56), \INFERRED_GEN.icount_out_reg[0]\(84) => read_Mux_In(64), \INFERRED_GEN.icount_out_reg[0]\(83) => read_Mux_In(65), \INFERRED_GEN.icount_out_reg[0]\(82) => read_Mux_In(66), \INFERRED_GEN.icount_out_reg[0]\(81) => read_Mux_In(67), \INFERRED_GEN.icount_out_reg[0]\(80) => read_Mux_In(68), \INFERRED_GEN.icount_out_reg[0]\(79) => read_Mux_In(69), \INFERRED_GEN.icount_out_reg[0]\(78) => read_Mux_In(70), \INFERRED_GEN.icount_out_reg[0]\(77) => read_Mux_In(71), \INFERRED_GEN.icount_out_reg[0]\(76) => read_Mux_In(72), \INFERRED_GEN.icount_out_reg[0]\(75) => read_Mux_In(73), \INFERRED_GEN.icount_out_reg[0]\(74) => read_Mux_In(74), \INFERRED_GEN.icount_out_reg[0]\(73) => read_Mux_In(75), \INFERRED_GEN.icount_out_reg[0]\(72) => read_Mux_In(76), \INFERRED_GEN.icount_out_reg[0]\(71) => read_Mux_In(77), \INFERRED_GEN.icount_out_reg[0]\(70) => read_Mux_In(78), \INFERRED_GEN.icount_out_reg[0]\(69) => read_Mux_In(79), \INFERRED_GEN.icount_out_reg[0]\(68) => read_Mux_In(80), \INFERRED_GEN.icount_out_reg[0]\(67) => read_Mux_In(81), \INFERRED_GEN.icount_out_reg[0]\(66) => read_Mux_In(82), \INFERRED_GEN.icount_out_reg[0]\(65) => read_Mux_In(83), \INFERRED_GEN.icount_out_reg[0]\(64) => read_Mux_In(84), \INFERRED_GEN.icount_out_reg[0]\(63) => read_Mux_In(128), \INFERRED_GEN.icount_out_reg[0]\(62) => read_Mux_In(129), \INFERRED_GEN.icount_out_reg[0]\(61) => read_Mux_In(130), \INFERRED_GEN.icount_out_reg[0]\(60) => read_Mux_In(131), \INFERRED_GEN.icount_out_reg[0]\(59) => read_Mux_In(132), \INFERRED_GEN.icount_out_reg[0]\(58) => read_Mux_In(133), \INFERRED_GEN.icount_out_reg[0]\(57) => read_Mux_In(134), \INFERRED_GEN.icount_out_reg[0]\(56) => read_Mux_In(135), \INFERRED_GEN.icount_out_reg[0]\(55) => read_Mux_In(136), \INFERRED_GEN.icount_out_reg[0]\(54) => read_Mux_In(137), \INFERRED_GEN.icount_out_reg[0]\(53) => read_Mux_In(138), \INFERRED_GEN.icount_out_reg[0]\(52) => read_Mux_In(139), \INFERRED_GEN.icount_out_reg[0]\(51) => read_Mux_In(140), \INFERRED_GEN.icount_out_reg[0]\(50) => read_Mux_In(141), \INFERRED_GEN.icount_out_reg[0]\(49) => read_Mux_In(142), \INFERRED_GEN.icount_out_reg[0]\(48) => read_Mux_In(143), \INFERRED_GEN.icount_out_reg[0]\(47) => read_Mux_In(144), \INFERRED_GEN.icount_out_reg[0]\(46) => read_Mux_In(145), \INFERRED_GEN.icount_out_reg[0]\(45) => read_Mux_In(146), \INFERRED_GEN.icount_out_reg[0]\(44) => read_Mux_In(147), \INFERRED_GEN.icount_out_reg[0]\(43) => read_Mux_In(148), \INFERRED_GEN.icount_out_reg[0]\(42) => read_Mux_In(149), \INFERRED_GEN.icount_out_reg[0]\(41) => read_Mux_In(150), \INFERRED_GEN.icount_out_reg[0]\(40) => read_Mux_In(151), \INFERRED_GEN.icount_out_reg[0]\(39) => read_Mux_In(152), \INFERRED_GEN.icount_out_reg[0]\(38) => read_Mux_In(153), \INFERRED_GEN.icount_out_reg[0]\(37) => read_Mux_In(154), \INFERRED_GEN.icount_out_reg[0]\(36) => read_Mux_In(155), \INFERRED_GEN.icount_out_reg[0]\(35) => read_Mux_In(156), \INFERRED_GEN.icount_out_reg[0]\(34) => read_Mux_In(157), \INFERRED_GEN.icount_out_reg[0]\(33) => read_Mux_In(158), \INFERRED_GEN.icount_out_reg[0]\(32) => read_Mux_In(159), \INFERRED_GEN.icount_out_reg[0]\(31) => read_Mux_In(160), \INFERRED_GEN.icount_out_reg[0]\(30) => read_Mux_In(161), \INFERRED_GEN.icount_out_reg[0]\(29) => read_Mux_In(162), \INFERRED_GEN.icount_out_reg[0]\(28) => read_Mux_In(163), \INFERRED_GEN.icount_out_reg[0]\(27) => read_Mux_In(164), \INFERRED_GEN.icount_out_reg[0]\(26) => read_Mux_In(165), \INFERRED_GEN.icount_out_reg[0]\(25) => read_Mux_In(166), \INFERRED_GEN.icount_out_reg[0]\(24) => read_Mux_In(167), \INFERRED_GEN.icount_out_reg[0]\(23) => read_Mux_In(168), \INFERRED_GEN.icount_out_reg[0]\(22) => read_Mux_In(169), \INFERRED_GEN.icount_out_reg[0]\(21) => read_Mux_In(170), \INFERRED_GEN.icount_out_reg[0]\(20) => read_Mux_In(171), \INFERRED_GEN.icount_out_reg[0]\(19) => read_Mux_In(172), \INFERRED_GEN.icount_out_reg[0]\(18) => read_Mux_In(173), \INFERRED_GEN.icount_out_reg[0]\(17) => read_Mux_In(174), \INFERRED_GEN.icount_out_reg[0]\(16) => read_Mux_In(175), \INFERRED_GEN.icount_out_reg[0]\(15) => read_Mux_In(176), \INFERRED_GEN.icount_out_reg[0]\(14) => read_Mux_In(177), \INFERRED_GEN.icount_out_reg[0]\(13) => read_Mux_In(178), \INFERRED_GEN.icount_out_reg[0]\(12) => read_Mux_In(179), \INFERRED_GEN.icount_out_reg[0]\(11) => read_Mux_In(180), \INFERRED_GEN.icount_out_reg[0]\(10) => read_Mux_In(181), \INFERRED_GEN.icount_out_reg[0]\(9) => read_Mux_In(182), \INFERRED_GEN.icount_out_reg[0]\(8) => read_Mux_In(183), \INFERRED_GEN.icount_out_reg[0]\(7) => read_Mux_In(184), \INFERRED_GEN.icount_out_reg[0]\(6) => read_Mux_In(185), \INFERRED_GEN.icount_out_reg[0]\(5) => read_Mux_In(186), \INFERRED_GEN.icount_out_reg[0]\(4) => read_Mux_In(187), \INFERRED_GEN.icount_out_reg[0]\(3) => read_Mux_In(188), \INFERRED_GEN.icount_out_reg[0]\(2) => read_Mux_In(189), \INFERRED_GEN.icount_out_reg[0]\(1) => read_Mux_In(190), \INFERRED_GEN.icount_out_reg[0]\(0) => read_Mux_In(191), \INFERRED_GEN.icount_out_reg[0]_0\ => AXI4_LITE_I_n_30, \INFERRED_GEN.icount_out_reg[10]\ => AXI4_LITE_I_n_40, \INFERRED_GEN.icount_out_reg[11]\ => AXI4_LITE_I_n_41, \INFERRED_GEN.icount_out_reg[12]\ => AXI4_LITE_I_n_42, \INFERRED_GEN.icount_out_reg[13]\ => AXI4_LITE_I_n_43, \INFERRED_GEN.icount_out_reg[14]\ => AXI4_LITE_I_n_44, \INFERRED_GEN.icount_out_reg[15]\ => AXI4_LITE_I_n_45, \INFERRED_GEN.icount_out_reg[16]\ => AXI4_LITE_I_n_46, \INFERRED_GEN.icount_out_reg[17]\ => AXI4_LITE_I_n_47, \INFERRED_GEN.icount_out_reg[18]\ => AXI4_LITE_I_n_48, \INFERRED_GEN.icount_out_reg[19]\ => AXI4_LITE_I_n_49, \INFERRED_GEN.icount_out_reg[1]\ => AXI4_LITE_I_n_31, \INFERRED_GEN.icount_out_reg[20]\ => AXI4_LITE_I_n_50, \INFERRED_GEN.icount_out_reg[21]\ => AXI4_LITE_I_n_51, \INFERRED_GEN.icount_out_reg[22]\ => AXI4_LITE_I_n_52, \INFERRED_GEN.icount_out_reg[23]\ => AXI4_LITE_I_n_53, \INFERRED_GEN.icount_out_reg[24]\ => AXI4_LITE_I_n_54, \INFERRED_GEN.icount_out_reg[25]\ => AXI4_LITE_I_n_55, \INFERRED_GEN.icount_out_reg[26]\ => AXI4_LITE_I_n_56, \INFERRED_GEN.icount_out_reg[27]\ => AXI4_LITE_I_n_57, \INFERRED_GEN.icount_out_reg[28]\ => AXI4_LITE_I_n_58, \INFERRED_GEN.icount_out_reg[29]\ => AXI4_LITE_I_n_59, \INFERRED_GEN.icount_out_reg[2]\ => AXI4_LITE_I_n_32, \INFERRED_GEN.icount_out_reg[30]\ => AXI4_LITE_I_n_60, \INFERRED_GEN.icount_out_reg[3]\ => AXI4_LITE_I_n_33, \INFERRED_GEN.icount_out_reg[4]\ => AXI4_LITE_I_n_34, \INFERRED_GEN.icount_out_reg[5]\ => AXI4_LITE_I_n_35, \INFERRED_GEN.icount_out_reg[6]\ => AXI4_LITE_I_n_36, \INFERRED_GEN.icount_out_reg[7]\ => AXI4_LITE_I_n_37, \INFERRED_GEN.icount_out_reg[8]\ => AXI4_LITE_I_n_38, \INFERRED_GEN.icount_out_reg[9]\ => AXI4_LITE_I_n_39, \LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_27, \TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28, \TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29, bus2ip_reset => bus2ip_reset, bus2ip_wrce(1) => bus2ip_wrce(0), bus2ip_wrce(0) => bus2ip_wrce(4), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5), capturetrig0 => capturetrig0, capturetrig1 => capturetrig1, freeze => freeze, generateout0 => generateout0, generateout1 => generateout1, interrupt => interrupt, pair0_Select => \TIMER_CONTROL_I/pair0_Select\, pwm0 => pwm0, read_done1 => \TIMER_CONTROL_I/read_done1\, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_wdata(9 downto 7) => s_axi_wdata(11 downto 9), s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_timer_0_1 is port ( capturetrig0 : in STD_LOGIC; capturetrig1 : in STD_LOGIC; generateout0 : out STD_LOGIC; generateout1 : out STD_LOGIC; pwm0 : out STD_LOGIC; interrupt : out STD_LOGIC; freeze : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of zqynq_lab_1_design_axi_timer_0_1 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_timer_0_1 : entity is "zqynq_lab_1_design_axi_timer_0_1,axi_timer,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_timer_0_1 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of zqynq_lab_1_design_axi_timer_0_1 : entity is "axi_timer,Vivado 2017.2"; end zqynq_lab_1_design_axi_timer_0_1; architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1 is attribute C_COUNT_WIDTH : integer; attribute C_COUNT_WIDTH of U0 : label is 32; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_GEN0_ASSERT : string; attribute C_GEN0_ASSERT of U0 : label is "1'b1"; attribute C_GEN1_ASSERT : string; attribute C_GEN1_ASSERT of U0 : label is "1'b1"; attribute C_ONE_TIMER_ONLY : integer; attribute C_ONE_TIMER_ONLY of U0 : label is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of U0 : label is 5; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of U0 : label is 32; attribute C_TRIG0_ASSERT : string; attribute C_TRIG0_ASSERT of U0 : label is "1'b1"; attribute C_TRIG1_ASSERT : string; attribute C_TRIG1_ASSERT of U0 : label is "1'b1"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.zqynq_lab_1_design_axi_timer_0_1_axi_timer port map ( capturetrig0 => capturetrig0, capturetrig1 => capturetrig1, freeze => freeze, generateout0 => generateout0, generateout1 => generateout1, interrupt => interrupt, pwm0 => pwm0, s_axi_aclk => s_axi_aclk, s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0), s_axi_awready => s_axi_awready, s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;

mit

8a1ad8661d6d94ecb8d99e9f6d9c5af9

MarkBlanco/FPGA_Sandbox

RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/syn/vhdl/convolve_kernel_fcud.vhd

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity convolve_kernel_fcud is generic ( ID : integer := 2; NUM_STAGE : integer := 8; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of convolve_kernel_fcud is --------------------- Component --------------------- component convolve_kernel_ap_fmul_6_max_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- convolve_kernel_ap_fmul_6_max_dsp_32_u : component convolve_kernel_ap_fmul_6_max_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;

mit

4950635698d661f07bba80f96b68c505

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/gaisler/srmmu/mmulrue.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: mmulrue -- File: mmulrue.vhd -- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research -- Description: MMU LRU logic ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.config_types.all; use grlib.config.all; use grlib.amba.all; use grlib.stdlib.all; library gaisler; use gaisler.mmuconfig.all; use gaisler.mmuiface.all; entity mmulrue is generic ( position : integer; entries : integer := 8 ); port ( rst : in std_logic; clk : in std_logic; lruei : in mmulrue_in_type; lrueo : out mmulrue_out_type ); end mmulrue; architecture rtl of mmulrue is constant entries_log : integer := log2(entries); type lru_rtype is record pos : std_logic_vector(entries_log-1 downto 0); movetop : std_logic; end record; constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; signal c,r : lru_rtype; begin p0: process (rst, r, lruei) variable v : lru_rtype; variable ov : mmulrue_out_type; begin v := r; ov := mmulrue_out_none; -- #init if (r.movetop) = '1' then if (lruei.fromleft) = '0' then v.pos := lruei.left(entries_log-1 downto 0); v.movetop := '0'; end if; elsif (lruei.fromright) = '1' then v.pos := lruei.right(entries_log-1 downto 0); v.movetop := not lruei.clear; end if; if (lruei.touch and not lruei.clear) = '1' then -- touch request if (v.pos = lruei.pos(entries_log-1 downto 0)) then -- check v.movetop := '1'; end if; end if; if ((not RESET_ALL) and (rst = '0')) or (lruei.flush = '1') then v.pos := conv_std_logic_vector(position, entries_log); v.movetop := '0'; end if; --# Drive signals ov.pos(entries_log-1 downto 0) := r.pos; ov.movetop := r.movetop; lrueo <= ov; c <= v; end process p0; p1: process (clk) begin if rising_edge(clk) then r <= c; if RESET_ALL and (rst = '0') then r.pos <= conv_std_logic_vector(position, entries_log); r.movetop <= '0'; end if; end if; end process p1; end rtl;

gpl-2.0

83813118491affbedc7956cd30611828

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/93db88faeb00921e/zqynq_lab_1_design_axi_timer_0_1_sim_netlist.vhdl

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Fri Sep 22 23:00:37 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_timer_0_1_sim_netlist.vhdl -- Design : zqynq_lab_1_design_axi_timer_0_1 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is port ( captureTrig0_d0 : out STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 ); capturetrig0 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is signal CaptureTrig0_int : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute BOX_TYPE : string; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; begin \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => capturetrig0, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d3, Q => CaptureTrig0_int, R => '0' ); captureTrig0_d_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => read_Mux_In(0), I1 => CaptureTrig0_int, O => captureTrig0_d0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 is port ( captureTrig1_d0 : out STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 ); capturetrig1 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 : entity is "cdc_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 is signal CaptureTrig1_int : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute BOX_TYPE : string; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; begin \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => capturetrig1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d3, Q => CaptureTrig1_int, R => '0' ); captureTrig1_d_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => read_Mux_In(0), I1 => CaptureTrig1_int, O => captureTrig1_d0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); \INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); S : out STD_LOGIC_VECTOR ( 0 to 0 ); \INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC; counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 ); read_Mux_In : in STD_LOGIC_VECTOR ( 7 downto 0 ); generateOutPre0 : in STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC; Load_Counter_Reg030_out : in STD_LOGIC; Load_Counter_Reg031_out : in STD_LOGIC; \Load_Counter_Reg0__0\ : in STD_LOGIC; Load_Counter_Reg028_out : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); freeze : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 : entity is "cdc_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 is signal \Counter_En041_out__2\ : STD_LOGIC; signal \Counter_En043_out__0\ : STD_LOGIC; signal \Counter_En045_out__1\ : STD_LOGIC; signal \Counter_En0__4\ : STD_LOGIC; signal Freeze_int : STD_LOGIC; signal counter_En : STD_LOGIC_VECTOR ( 0 to 1 ); signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute BOX_TYPE : string; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; begin \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => freeze, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_level_out_d3, Q => Freeze_int, R => '0' ); \INFERRED_GEN.icount_out[31]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FCFFFCAA" ) port map ( I0 => Load_Counter_Reg030_out, I1 => Load_Counter_Reg031_out, I2 => \Counter_En043_out__0\, I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\, I4 => \Counter_En041_out__2\, O => E(0) ); \INFERRED_GEN.icount_out[31]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FCFFFCAA" ) port map ( I0 => \Load_Counter_Reg0__0\, I1 => Load_Counter_Reg028_out, I2 => \Counter_En045_out__1\, I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\, I4 => \Counter_En0__4\, O => \INFERRED_GEN.icount_out_reg[0]\(0) ); \INFERRED_GEN.icount_out[31]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"00FB0000" ) port map ( I0 => read_Mux_In(4), I1 => counter_TC(1), I2 => read_Mux_In(6), I3 => Freeze_int, I4 => \TCSR0_GENERATE[24].TCSR0_FF_I\, O => \Counter_En043_out__0\ ); \INFERRED_GEN.icount_out[31]_i_5__0\: unisim.vcomponents.LUT6 generic map( INIT => X"4040404040004040" ) port map ( I0 => Freeze_int, I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\, I2 => generateOutPre0, I3 => read_Mux_In(6), I4 => counter_TC(1), I5 => read_Mux_In(4), O => \Counter_En045_out__1\ ); \INFERRED_GEN.icount_out[31]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"4444444444444404" ) port map ( I0 => Freeze_int, I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\, I2 => counter_TC(0), I3 => read_Mux_In(7), I4 => read_Mux_In(6), I5 => read_Mux_In(4), O => \Counter_En041_out__2\ ); \INFERRED_GEN.icount_out[31]_i_6__0\: unisim.vcomponents.LUT6 generic map( INIT => X"2222222222202222" ) port map ( I0 => \TCSR1_GENERATE[24].TCSR1_FF_I\, I1 => Freeze_int, I2 => read_Mux_In(3), I3 => read_Mux_In(2), I4 => counter_TC(1), I5 => read_Mux_In(0), O => \Counter_En0__4\ ); icount_out0_carry_i_5: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \INFERRED_GEN.icount_out_reg[1]\(1), I1 => counter_En(0), I2 => read_Mux_In(5), O => S(0) ); \icount_out0_carry_i_5__0\: unisim.vcomponents.LUT5 generic map( INIT => X"6A666AAA" ) port map ( I0 => \INFERRED_GEN.icount_out_reg[1]\(0), I1 => counter_En(1), I2 => read_Mux_In(5), I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\, I4 => read_Mux_In(1), O => \INFERRED_GEN.icount_out_reg[4]\(0) ); icount_out0_carry_i_6: unisim.vcomponents.MUXF7 port map ( I0 => \Counter_En041_out__2\, I1 => \Counter_En043_out__0\, O => counter_En(0), S => \TCSR0_GENERATE[20].TCSR0_FF_I\ ); \icount_out0_carry_i_6__0\: unisim.vcomponents.MUXF7 port map ( I0 => \Counter_En0__4\, I1 => \Counter_En045_out__1\, O => counter_En(1), S => \TCSR0_GENERATE[20].TCSR0_FF_I\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f is port ( Q : out STD_LOGIC_VECTOR ( 31 downto 0 ); SR : out STD_LOGIC_VECTOR ( 0 to 0 ); \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[1]\ : out STD_LOGIC; \s_axi_rdata_i_reg[2]\ : out STD_LOGIC; \s_axi_rdata_i_reg[3]\ : out STD_LOGIC; \s_axi_rdata_i_reg[4]\ : out STD_LOGIC; \s_axi_rdata_i_reg[5]\ : out STD_LOGIC; \s_axi_rdata_i_reg[6]\ : out STD_LOGIC; \s_axi_rdata_i_reg[7]\ : out STD_LOGIC; \s_axi_rdata_i_reg[8]\ : out STD_LOGIC; \s_axi_rdata_i_reg[9]\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; \s_axi_rdata_i_reg[11]\ : out STD_LOGIC; \s_axi_rdata_i_reg[12]\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC; generateOutPre1_reg : out STD_LOGIC; counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 ); S : in STD_LOGIC_VECTOR ( 0 to 0 ); read_Mux_In : in STD_LOGIC_VECTOR ( 31 downto 0 ); load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f is signal \INFERRED_GEN.icount_out[0]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[10]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[11]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[12]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[13]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[14]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[15]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[16]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[17]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[18]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[19]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[1]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[20]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[21]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[22]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[23]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[24]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[25]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[26]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[27]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[28]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[29]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[2]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[30]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[31]_i_2_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[3]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[4]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[5]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[6]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[7]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[8]_i_1_n_0\ : STD_LOGIC; signal \INFERRED_GEN.icount_out[9]_i_1_n_0\ : STD_LOGIC; signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \icount_out0_carry__0_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_n_1\ : STD_LOGIC; signal \icount_out0_carry__0_n_2\ : STD_LOGIC; signal \icount_out0_carry__0_n_3\ : STD_LOGIC; signal \icount_out0_carry__0_n_4\ : STD_LOGIC; signal \icount_out0_carry__0_n_5\ : STD_LOGIC; signal \icount_out0_carry__0_n_6\ : STD_LOGIC; signal \icount_out0_carry__0_n_7\ : STD_LOGIC; signal \icount_out0_carry__1_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_n_1\ : STD_LOGIC; signal \icount_out0_carry__1_n_2\ : STD_LOGIC; signal \icount_out0_carry__1_n_3\ : STD_LOGIC; signal \icount_out0_carry__1_n_4\ : STD_LOGIC; signal \icount_out0_carry__1_n_5\ : STD_LOGIC; signal \icount_out0_carry__1_n_6\ : STD_LOGIC; signal \icount_out0_carry__1_n_7\ : STD_LOGIC; signal \icount_out0_carry__2_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_n_1\ : STD_LOGIC; signal \icount_out0_carry__2_n_2\ : STD_LOGIC; signal \icount_out0_carry__2_n_3\ : STD_LOGIC; signal \icount_out0_carry__2_n_4\ : STD_LOGIC; signal \icount_out0_carry__2_n_5\ : STD_LOGIC; signal \icount_out0_carry__2_n_6\ : STD_LOGIC; signal \icount_out0_carry__2_n_7\ : STD_LOGIC; signal \icount_out0_carry__3_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_n_1\ : STD_LOGIC; signal \icount_out0_carry__3_n_2\ : STD_LOGIC; signal \icount_out0_carry__3_n_3\ : STD_LOGIC; signal \icount_out0_carry__3_n_4\ : STD_LOGIC; signal \icount_out0_carry__3_n_5\ : STD_LOGIC; signal \icount_out0_carry__3_n_6\ : STD_LOGIC; signal \icount_out0_carry__3_n_7\ : STD_LOGIC; signal \icount_out0_carry__4_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_n_1\ : STD_LOGIC; signal \icount_out0_carry__4_n_2\ : STD_LOGIC; signal \icount_out0_carry__4_n_3\ : STD_LOGIC; signal \icount_out0_carry__4_n_4\ : STD_LOGIC; signal \icount_out0_carry__4_n_5\ : STD_LOGIC; signal \icount_out0_carry__4_n_6\ : STD_LOGIC; signal \icount_out0_carry__4_n_7\ : STD_LOGIC; signal \icount_out0_carry__5_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_n_1\ : STD_LOGIC; signal \icount_out0_carry__5_n_2\ : STD_LOGIC; signal \icount_out0_carry__5_n_3\ : STD_LOGIC; signal \icount_out0_carry__5_n_4\ : STD_LOGIC; signal \icount_out0_carry__5_n_5\ : STD_LOGIC; signal \icount_out0_carry__5_n_6\ : STD_LOGIC; signal \icount_out0_carry__5_n_7\ : STD_LOGIC; signal \icount_out0_carry__6_i_1_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_2_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_3_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_4_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_n_1\ : STD_LOGIC; signal \icount_out0_carry__6_n_2\ : STD_LOGIC; signal \icount_out0_carry__6_n_3\ : STD_LOGIC; signal \icount_out0_carry__6_n_4\ : STD_LOGIC; signal \icount_out0_carry__6_n_5\ : STD_LOGIC; signal \icount_out0_carry__6_n_6\ : STD_LOGIC; signal \icount_out0_carry__6_n_7\ : STD_LOGIC; signal icount_out0_carry_i_1_n_0 : STD_LOGIC; signal icount_out0_carry_i_2_n_0 : STD_LOGIC; signal icount_out0_carry_i_3_n_0 : STD_LOGIC; signal icount_out0_carry_i_4_n_0 : STD_LOGIC; signal icount_out0_carry_n_0 : STD_LOGIC; signal icount_out0_carry_n_1 : STD_LOGIC; signal icount_out0_carry_n_2 : STD_LOGIC; signal icount_out0_carry_n_3 : STD_LOGIC; signal icount_out0_carry_n_4 : STD_LOGIC; signal icount_out0_carry_n_5 : STD_LOGIC; signal icount_out0_carry_n_6 : STD_LOGIC; signal icount_out0_carry_n_7 : STD_LOGIC; signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1\ : label is "soft_lutpair45"; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}"; begin Q(31 downto 0) <= \^q\(31 downto 0); SR(0) <= \^sr\(0); counter_TC(0) <= \^counter_tc\(0); \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(31), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(31), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(31), O => \s_axi_rdata_i_reg[31]\ ); \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(21), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(21), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(21), O => \s_axi_rdata_i_reg[21]\ ); \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(20), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(20), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(20), O => \s_axi_rdata_i_reg[20]\ ); \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(19), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(19), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(19), O => \s_axi_rdata_i_reg[19]\ ); \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(18), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(18), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(18), O => \s_axi_rdata_i_reg[18]\ ); \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(17), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(17), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(17), O => \s_axi_rdata_i_reg[17]\ ); \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(16), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(16), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(16), O => \s_axi_rdata_i_reg[16]\ ); \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(15), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(15), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(15), O => \s_axi_rdata_i_reg[15]\ ); \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(14), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(14), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(14), O => \s_axi_rdata_i_reg[14]\ ); \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(13), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(13), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(13), O => \s_axi_rdata_i_reg[13]\ ); \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(12), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(12), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(12), O => \s_axi_rdata_i_reg[12]\ ); \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(30), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(30), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(30), O => \s_axi_rdata_i_reg[30]\ ); \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(11), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(11), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(11), O => \s_axi_rdata_i_reg[11]\ ); \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(10), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(10), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(10), O => \s_axi_rdata_i_reg[10]\ ); \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(9), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(9), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(9), O => \s_axi_rdata_i_reg[9]\ ); \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(8), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(8), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(8), O => \s_axi_rdata_i_reg[8]\ ); \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(7), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(7), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(7), O => \s_axi_rdata_i_reg[7]\ ); \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(6), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(6), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(6), O => \s_axi_rdata_i_reg[6]\ ); \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(5), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(5), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(5), O => \s_axi_rdata_i_reg[5]\ ); \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(4), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(4), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(4), O => \s_axi_rdata_i_reg[4]\ ); \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(3), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(3), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(3), O => \s_axi_rdata_i_reg[3]\ ); \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(2), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(2), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(2), O => \s_axi_rdata_i_reg[2]\ ); \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(29), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(29), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(29), O => \s_axi_rdata_i_reg[29]\ ); \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(1), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(1), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(1), O => \s_axi_rdata_i_reg[1]\ ); \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(0), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(0), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(0), O => \s_axi_rdata_i_reg[0]\ ); \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(28), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(28), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(28), O => \s_axi_rdata_i_reg[28]\ ); \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(27), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(27), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(27), O => \s_axi_rdata_i_reg[27]\ ); \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(26), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(26), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(26), O => \s_axi_rdata_i_reg[26]\ ); \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(25), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(25), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(25), O => \s_axi_rdata_i_reg[25]\ ); \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(24), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(24), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(24), O => \s_axi_rdata_i_reg[24]\ ); \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(23), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(23), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(23), O => \s_axi_rdata_i_reg[23]\ ); \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \^q\(22), I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, I3 => read_Mux_In(22), I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, I5 => \INFERRED_GEN.icount_out_reg[31]_0\(22), O => \s_axi_rdata_i_reg[22]\ ); GenerateOut0_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => s_axi_aresetn, O => \^sr\(0) ); \INFERRED_GEN.icount_out[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"A3" ) port map ( I0 => read_Mux_In(0), I1 => \^q\(0), I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[0]_i_1_n_0\ ); \INFERRED_GEN.icount_out[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(10), I1 => \icount_out0_carry__1_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[10]_i_1_n_0\ ); \INFERRED_GEN.icount_out[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(11), I1 => \icount_out0_carry__1_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[11]_i_1_n_0\ ); \INFERRED_GEN.icount_out[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(12), I1 => \icount_out0_carry__1_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[12]_i_1_n_0\ ); \INFERRED_GEN.icount_out[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(13), I1 => \icount_out0_carry__2_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[13]_i_1_n_0\ ); \INFERRED_GEN.icount_out[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(14), I1 => \icount_out0_carry__2_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[14]_i_1_n_0\ ); \INFERRED_GEN.icount_out[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(15), I1 => \icount_out0_carry__2_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[15]_i_1_n_0\ ); \INFERRED_GEN.icount_out[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(16), I1 => \icount_out0_carry__2_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[16]_i_1_n_0\ ); \INFERRED_GEN.icount_out[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(17), I1 => \icount_out0_carry__3_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[17]_i_1_n_0\ ); \INFERRED_GEN.icount_out[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(18), I1 => \icount_out0_carry__3_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[18]_i_1_n_0\ ); \INFERRED_GEN.icount_out[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(19), I1 => \icount_out0_carry__3_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[19]_i_1_n_0\ ); \INFERRED_GEN.icount_out[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(1), I1 => icount_out0_carry_n_7, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[1]_i_1_n_0\ ); \INFERRED_GEN.icount_out[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(20), I1 => \icount_out0_carry__3_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[20]_i_1_n_0\ ); \INFERRED_GEN.icount_out[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(21), I1 => \icount_out0_carry__4_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[21]_i_1_n_0\ ); \INFERRED_GEN.icount_out[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(22), I1 => \icount_out0_carry__4_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[22]_i_1_n_0\ ); \INFERRED_GEN.icount_out[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(23), I1 => \icount_out0_carry__4_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[23]_i_1_n_0\ ); \INFERRED_GEN.icount_out[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(24), I1 => \icount_out0_carry__4_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[24]_i_1_n_0\ ); \INFERRED_GEN.icount_out[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(25), I1 => \icount_out0_carry__5_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[25]_i_1_n_0\ ); \INFERRED_GEN.icount_out[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(26), I1 => \icount_out0_carry__5_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[26]_i_1_n_0\ ); \INFERRED_GEN.icount_out[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(27), I1 => \icount_out0_carry__5_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[27]_i_1_n_0\ ); \INFERRED_GEN.icount_out[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(28), I1 => \icount_out0_carry__5_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[28]_i_1_n_0\ ); \INFERRED_GEN.icount_out[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(29), I1 => \icount_out0_carry__6_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[29]_i_1_n_0\ ); \INFERRED_GEN.icount_out[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(2), I1 => icount_out0_carry_n_6, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[2]_i_1_n_0\ ); \INFERRED_GEN.icount_out[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(30), I1 => \icount_out0_carry__6_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[30]_i_1_n_0\ ); \INFERRED_GEN.icount_out[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(31), I1 => \icount_out0_carry__6_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[31]_i_2_n_0\ ); \INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0000E200" ) port map ( I0 => \^counter_tc\(0), I1 => E(0), I2 => \icount_out0_carry__6_n_4\, I3 => s_axi_aresetn, I4 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[32]_i_1_n_0\ ); \INFERRED_GEN.icount_out[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(3), I1 => icount_out0_carry_n_5, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[3]_i_1_n_0\ ); \INFERRED_GEN.icount_out[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(4), I1 => icount_out0_carry_n_4, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[4]_i_1_n_0\ ); \INFERRED_GEN.icount_out[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(5), I1 => \icount_out0_carry__0_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[5]_i_1_n_0\ ); \INFERRED_GEN.icount_out[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(6), I1 => \icount_out0_carry__0_n_6\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[6]_i_1_n_0\ ); \INFERRED_GEN.icount_out[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(7), I1 => \icount_out0_carry__0_n_5\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[7]_i_1_n_0\ ); \INFERRED_GEN.icount_out[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(8), I1 => \icount_out0_carry__0_n_4\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[8]_i_1_n_0\ ); \INFERRED_GEN.icount_out[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => read_Mux_In(9), I1 => \icount_out0_carry__1_n_7\, I2 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[9]_i_1_n_0\ ); \INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[0]_i_1_n_0\, Q => \^q\(0), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[10]_i_1_n_0\, Q => \^q\(10), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[11]_i_1_n_0\, Q => \^q\(11), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[12]_i_1_n_0\, Q => \^q\(12), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[13]_i_1_n_0\, Q => \^q\(13), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[14]_i_1_n_0\, Q => \^q\(14), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[15]_i_1_n_0\, Q => \^q\(15), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[16]_i_1_n_0\, Q => \^q\(16), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[17]_i_1_n_0\, Q => \^q\(17), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[18]_i_1_n_0\, Q => \^q\(18), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[19]_i_1_n_0\, Q => \^q\(19), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[1]_i_1_n_0\, Q => \^q\(1), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[20]_i_1_n_0\, Q => \^q\(20), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[21]_i_1_n_0\, Q => \^q\(21), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[22]_i_1_n_0\, Q => \^q\(22), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[23]_i_1_n_0\, Q => \^q\(23), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[24]_i_1_n_0\, Q => \^q\(24), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[25]_i_1_n_0\, Q => \^q\(25), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[26]_i_1_n_0\, Q => \^q\(26), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[27]_i_1_n_0\, Q => \^q\(27), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[28]_i_1_n_0\, Q => \^q\(28), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[29]_i_1_n_0\, Q => \^q\(29), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[2]_i_1_n_0\, Q => \^q\(2), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[30]_i_1_n_0\, Q => \^q\(30), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[31]_i_2_n_0\, Q => \^q\(31), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \INFERRED_GEN.icount_out[32]_i_1_n_0\, Q => \^counter_tc\(0), R => '0' ); \INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[3]_i_1_n_0\, Q => \^q\(3), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[4]_i_1_n_0\, Q => \^q\(4), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[5]_i_1_n_0\, Q => \^q\(5), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[6]_i_1_n_0\, Q => \^q\(6), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[7]_i_1_n_0\, Q => \^q\(7), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[8]_i_1_n_0\, Q => \^q\(8), R => \^sr\(0) ); \INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => \INFERRED_GEN.icount_out[9]_i_1_n_0\, Q => \^q\(9), R => \^sr\(0) ); generateOutPre1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^counter_tc\(0), I1 => \counter_TC_Reg_reg[1]\(0), O => generateOutPre1_reg ); icount_out0_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => icount_out0_carry_n_0, CO(2) => icount_out0_carry_n_1, CO(1) => icount_out0_carry_n_2, CO(0) => icount_out0_carry_n_3, CYINIT => \^q\(0), DI(3 downto 1) => \^q\(3 downto 1), DI(0) => icount_out0_carry_i_1_n_0, O(3) => icount_out0_carry_n_4, O(2) => icount_out0_carry_n_5, O(1) => icount_out0_carry_n_6, O(0) => icount_out0_carry_n_7, S(3) => icount_out0_carry_i_2_n_0, S(2) => icount_out0_carry_i_3_n_0, S(1) => icount_out0_carry_i_4_n_0, S(0) => S(0) ); \icount_out0_carry__0\: unisim.vcomponents.CARRY4 port map ( CI => icount_out0_carry_n_0, CO(3) => \icount_out0_carry__0_n_0\, CO(2) => \icount_out0_carry__0_n_1\, CO(1) => \icount_out0_carry__0_n_2\, CO(0) => \icount_out0_carry__0_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(7 downto 4), O(3) => \icount_out0_carry__0_n_4\, O(2) => \icount_out0_carry__0_n_5\, O(1) => \icount_out0_carry__0_n_6\, O(0) => \icount_out0_carry__0_n_7\, S(3) => \icount_out0_carry__0_i_1_n_0\, S(2) => \icount_out0_carry__0_i_2_n_0\, S(1) => \icount_out0_carry__0_i_3_n_0\, S(0) => \icount_out0_carry__0_i_4_n_0\ ); \icount_out0_carry__0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(7), I1 => \^q\(8), O => \icount_out0_carry__0_i_1_n_0\ ); \icount_out0_carry__0_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(6), I1 => \^q\(7), O => \icount_out0_carry__0_i_2_n_0\ ); \icount_out0_carry__0_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(5), I1 => \^q\(6), O => \icount_out0_carry__0_i_3_n_0\ ); \icount_out0_carry__0_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(4), I1 => \^q\(5), O => \icount_out0_carry__0_i_4_n_0\ ); \icount_out0_carry__1\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__0_n_0\, CO(3) => \icount_out0_carry__1_n_0\, CO(2) => \icount_out0_carry__1_n_1\, CO(1) => \icount_out0_carry__1_n_2\, CO(0) => \icount_out0_carry__1_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(11 downto 8), O(3) => \icount_out0_carry__1_n_4\, O(2) => \icount_out0_carry__1_n_5\, O(1) => \icount_out0_carry__1_n_6\, O(0) => \icount_out0_carry__1_n_7\, S(3) => \icount_out0_carry__1_i_1_n_0\, S(2) => \icount_out0_carry__1_i_2_n_0\, S(1) => \icount_out0_carry__1_i_3_n_0\, S(0) => \icount_out0_carry__1_i_4_n_0\ ); \icount_out0_carry__1_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(11), I1 => \^q\(12), O => \icount_out0_carry__1_i_1_n_0\ ); \icount_out0_carry__1_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(10), I1 => \^q\(11), O => \icount_out0_carry__1_i_2_n_0\ ); \icount_out0_carry__1_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(9), I1 => \^q\(10), O => \icount_out0_carry__1_i_3_n_0\ ); \icount_out0_carry__1_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(8), I1 => \^q\(9), O => \icount_out0_carry__1_i_4_n_0\ ); \icount_out0_carry__2\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__1_n_0\, CO(3) => \icount_out0_carry__2_n_0\, CO(2) => \icount_out0_carry__2_n_1\, CO(1) => \icount_out0_carry__2_n_2\, CO(0) => \icount_out0_carry__2_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(15 downto 12), O(3) => \icount_out0_carry__2_n_4\, O(2) => \icount_out0_carry__2_n_5\, O(1) => \icount_out0_carry__2_n_6\, O(0) => \icount_out0_carry__2_n_7\, S(3) => \icount_out0_carry__2_i_1_n_0\, S(2) => \icount_out0_carry__2_i_2_n_0\, S(1) => \icount_out0_carry__2_i_3_n_0\, S(0) => \icount_out0_carry__2_i_4_n_0\ ); \icount_out0_carry__2_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(15), I1 => \^q\(16), O => \icount_out0_carry__2_i_1_n_0\ ); \icount_out0_carry__2_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(14), I1 => \^q\(15), O => \icount_out0_carry__2_i_2_n_0\ ); \icount_out0_carry__2_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(13), I1 => \^q\(14), O => \icount_out0_carry__2_i_3_n_0\ ); \icount_out0_carry__2_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(12), I1 => \^q\(13), O => \icount_out0_carry__2_i_4_n_0\ ); \icount_out0_carry__3\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__2_n_0\, CO(3) => \icount_out0_carry__3_n_0\, CO(2) => \icount_out0_carry__3_n_1\, CO(1) => \icount_out0_carry__3_n_2\, CO(0) => \icount_out0_carry__3_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(19 downto 16), O(3) => \icount_out0_carry__3_n_4\, O(2) => \icount_out0_carry__3_n_5\, O(1) => \icount_out0_carry__3_n_6\, O(0) => \icount_out0_carry__3_n_7\, S(3) => \icount_out0_carry__3_i_1_n_0\, S(2) => \icount_out0_carry__3_i_2_n_0\, S(1) => \icount_out0_carry__3_i_3_n_0\, S(0) => \icount_out0_carry__3_i_4_n_0\ ); \icount_out0_carry__3_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(19), I1 => \^q\(20), O => \icount_out0_carry__3_i_1_n_0\ ); \icount_out0_carry__3_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(18), I1 => \^q\(19), O => \icount_out0_carry__3_i_2_n_0\ ); \icount_out0_carry__3_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(17), I1 => \^q\(18), O => \icount_out0_carry__3_i_3_n_0\ ); \icount_out0_carry__3_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(16), I1 => \^q\(17), O => \icount_out0_carry__3_i_4_n_0\ ); \icount_out0_carry__4\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__3_n_0\, CO(3) => \icount_out0_carry__4_n_0\, CO(2) => \icount_out0_carry__4_n_1\, CO(1) => \icount_out0_carry__4_n_2\, CO(0) => \icount_out0_carry__4_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(23 downto 20), O(3) => \icount_out0_carry__4_n_4\, O(2) => \icount_out0_carry__4_n_5\, O(1) => \icount_out0_carry__4_n_6\, O(0) => \icount_out0_carry__4_n_7\, S(3) => \icount_out0_carry__4_i_1_n_0\, S(2) => \icount_out0_carry__4_i_2_n_0\, S(1) => \icount_out0_carry__4_i_3_n_0\, S(0) => \icount_out0_carry__4_i_4_n_0\ ); \icount_out0_carry__4_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(23), I1 => \^q\(24), O => \icount_out0_carry__4_i_1_n_0\ ); \icount_out0_carry__4_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(22), I1 => \^q\(23), O => \icount_out0_carry__4_i_2_n_0\ ); \icount_out0_carry__4_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(21), I1 => \^q\(22), O => \icount_out0_carry__4_i_3_n_0\ ); \icount_out0_carry__4_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(20), I1 => \^q\(21), O => \icount_out0_carry__4_i_4_n_0\ ); \icount_out0_carry__5\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__4_n_0\, CO(3) => \icount_out0_carry__5_n_0\, CO(2) => \icount_out0_carry__5_n_1\, CO(1) => \icount_out0_carry__5_n_2\, CO(0) => \icount_out0_carry__5_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(27 downto 24), O(3) => \icount_out0_carry__5_n_4\, O(2) => \icount_out0_carry__5_n_5\, O(1) => \icount_out0_carry__5_n_6\, O(0) => \icount_out0_carry__5_n_7\, S(3) => \icount_out0_carry__5_i_1_n_0\, S(2) => \icount_out0_carry__5_i_2_n_0\, S(1) => \icount_out0_carry__5_i_3_n_0\, S(0) => \icount_out0_carry__5_i_4_n_0\ ); \icount_out0_carry__5_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(27), I1 => \^q\(28), O => \icount_out0_carry__5_i_1_n_0\ ); \icount_out0_carry__5_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(26), I1 => \^q\(27), O => \icount_out0_carry__5_i_2_n_0\ ); \icount_out0_carry__5_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(25), I1 => \^q\(26), O => \icount_out0_carry__5_i_3_n_0\ ); \icount_out0_carry__5_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(24), I1 => \^q\(25), O => \icount_out0_carry__5_i_4_n_0\ ); \icount_out0_carry__6\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__5_n_0\, CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3), CO(2) => \icount_out0_carry__6_n_1\, CO(1) => \icount_out0_carry__6_n_2\, CO(0) => \icount_out0_carry__6_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => \^q\(30 downto 28), O(3) => \icount_out0_carry__6_n_4\, O(2) => \icount_out0_carry__6_n_5\, O(1) => \icount_out0_carry__6_n_6\, O(0) => \icount_out0_carry__6_n_7\, S(3) => \icount_out0_carry__6_i_1_n_0\, S(2) => \icount_out0_carry__6_i_2_n_0\, S(1) => \icount_out0_carry__6_i_3_n_0\, S(0) => \icount_out0_carry__6_i_4_n_0\ ); \icount_out0_carry__6_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(31), O => \icount_out0_carry__6_i_1_n_0\ ); \icount_out0_carry__6_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(30), I1 => \^q\(31), O => \icount_out0_carry__6_i_2_n_0\ ); \icount_out0_carry__6_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(29), I1 => \^q\(30), O => \icount_out0_carry__6_i_3_n_0\ ); \icount_out0_carry__6_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(28), I1 => \^q\(29), O => \icount_out0_carry__6_i_4_n_0\ ); icount_out0_carry_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(1), O => icount_out0_carry_i_1_n_0 ); icount_out0_carry_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(3), I1 => \^q\(4), O => icount_out0_carry_i_2_n_0 ); icount_out0_carry_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(2), I1 => \^q\(3), O => icount_out0_carry_i_3_n_0 ); icount_out0_carry_i_4: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^q\(1), I1 => \^q\(2), O => icount_out0_carry_i_4_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 is port ( \LOAD_REG_GEN[0].LOAD_REG_I\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); generateOutPre0_reg : out STD_LOGIC; counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 ); S : in STD_LOGIC_VECTOR ( 0 to 0 ); read_Mux_In : in STD_LOGIC_VECTOR ( 10 downto 0 ); load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \LOAD_REG_GEN[0].LOAD_REG_I_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 ); Q : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 : entity is "counter_f"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 is signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC; signal \^load_reg_gen[0].load_reg_i\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \icount_out0_carry__0_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__0_n_1\ : STD_LOGIC; signal \icount_out0_carry__0_n_2\ : STD_LOGIC; signal \icount_out0_carry__0_n_3\ : STD_LOGIC; signal \icount_out0_carry__0_n_4\ : STD_LOGIC; signal \icount_out0_carry__0_n_5\ : STD_LOGIC; signal \icount_out0_carry__0_n_6\ : STD_LOGIC; signal \icount_out0_carry__0_n_7\ : STD_LOGIC; signal \icount_out0_carry__1_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_n_0\ : STD_LOGIC; signal \icount_out0_carry__1_n_1\ : STD_LOGIC; signal \icount_out0_carry__1_n_2\ : STD_LOGIC; signal \icount_out0_carry__1_n_3\ : STD_LOGIC; signal \icount_out0_carry__1_n_4\ : STD_LOGIC; signal \icount_out0_carry__1_n_5\ : STD_LOGIC; signal \icount_out0_carry__1_n_6\ : STD_LOGIC; signal \icount_out0_carry__1_n_7\ : STD_LOGIC; signal \icount_out0_carry__2_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_n_0\ : STD_LOGIC; signal \icount_out0_carry__2_n_1\ : STD_LOGIC; signal \icount_out0_carry__2_n_2\ : STD_LOGIC; signal \icount_out0_carry__2_n_3\ : STD_LOGIC; signal \icount_out0_carry__2_n_4\ : STD_LOGIC; signal \icount_out0_carry__2_n_5\ : STD_LOGIC; signal \icount_out0_carry__2_n_6\ : STD_LOGIC; signal \icount_out0_carry__2_n_7\ : STD_LOGIC; signal \icount_out0_carry__3_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_n_0\ : STD_LOGIC; signal \icount_out0_carry__3_n_1\ : STD_LOGIC; signal \icount_out0_carry__3_n_2\ : STD_LOGIC; signal \icount_out0_carry__3_n_3\ : STD_LOGIC; signal \icount_out0_carry__3_n_4\ : STD_LOGIC; signal \icount_out0_carry__3_n_5\ : STD_LOGIC; signal \icount_out0_carry__3_n_6\ : STD_LOGIC; signal \icount_out0_carry__3_n_7\ : STD_LOGIC; signal \icount_out0_carry__4_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_n_0\ : STD_LOGIC; signal \icount_out0_carry__4_n_1\ : STD_LOGIC; signal \icount_out0_carry__4_n_2\ : STD_LOGIC; signal \icount_out0_carry__4_n_3\ : STD_LOGIC; signal \icount_out0_carry__4_n_4\ : STD_LOGIC; signal \icount_out0_carry__4_n_5\ : STD_LOGIC; signal \icount_out0_carry__4_n_6\ : STD_LOGIC; signal \icount_out0_carry__4_n_7\ : STD_LOGIC; signal \icount_out0_carry__5_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_n_0\ : STD_LOGIC; signal \icount_out0_carry__5_n_1\ : STD_LOGIC; signal \icount_out0_carry__5_n_2\ : STD_LOGIC; signal \icount_out0_carry__5_n_3\ : STD_LOGIC; signal \icount_out0_carry__5_n_4\ : STD_LOGIC; signal \icount_out0_carry__5_n_5\ : STD_LOGIC; signal \icount_out0_carry__5_n_6\ : STD_LOGIC; signal \icount_out0_carry__5_n_7\ : STD_LOGIC; signal \icount_out0_carry__6_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_i_4__0_n_0\ : STD_LOGIC; signal \icount_out0_carry__6_n_1\ : STD_LOGIC; signal \icount_out0_carry__6_n_2\ : STD_LOGIC; signal \icount_out0_carry__6_n_3\ : STD_LOGIC; signal \icount_out0_carry__6_n_4\ : STD_LOGIC; signal \icount_out0_carry__6_n_5\ : STD_LOGIC; signal \icount_out0_carry__6_n_6\ : STD_LOGIC; signal \icount_out0_carry__6_n_7\ : STD_LOGIC; signal \icount_out0_carry_i_1__0_n_0\ : STD_LOGIC; signal \icount_out0_carry_i_2__0_n_0\ : STD_LOGIC; signal \icount_out0_carry_i_3__0_n_0\ : STD_LOGIC; signal \icount_out0_carry_i_4__0_n_0\ : STD_LOGIC; signal icount_out0_carry_n_0 : STD_LOGIC; signal icount_out0_carry_n_1 : STD_LOGIC; signal icount_out0_carry_n_2 : STD_LOGIC; signal icount_out0_carry_n_3 : STD_LOGIC; signal icount_out0_carry_n_4 : STD_LOGIC; signal icount_out0_carry_n_5 : STD_LOGIC; signal icount_out0_carry_n_6 : STD_LOGIC; signal icount_out0_carry_n_7 : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1__0\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1__0\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1__0\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1__0\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1__0\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2__0\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1__0\ : label is "soft_lutpair29"; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}"; attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}"; begin \LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) <= \^load_reg_gen[0].load_reg_i\(31 downto 0); counter_TC(0) <= \^counter_tc\(0); \INFERRED_GEN.icount_out[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => read_Mux_In(0), I1 => load_Counter_Reg(0), I2 => \^load_reg_gen[0].load_reg_i\(0), O => p_1_in(0) ); \INFERRED_GEN.icount_out[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(10), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__1_n_6\, O => p_1_in(10) ); \INFERRED_GEN.icount_out[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(0), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__1_n_5\, O => p_1_in(11) ); \INFERRED_GEN.icount_out[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(1), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__1_n_4\, O => p_1_in(12) ); \INFERRED_GEN.icount_out[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(2), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__2_n_7\, O => p_1_in(13) ); \INFERRED_GEN.icount_out[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(3), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__2_n_6\, O => p_1_in(14) ); \INFERRED_GEN.icount_out[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(4), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__2_n_5\, O => p_1_in(15) ); \INFERRED_GEN.icount_out[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(5), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__2_n_4\, O => p_1_in(16) ); \INFERRED_GEN.icount_out[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(6), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__3_n_7\, O => p_1_in(17) ); \INFERRED_GEN.icount_out[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(7), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__3_n_6\, O => p_1_in(18) ); \INFERRED_GEN.icount_out[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(8), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__3_n_5\, O => p_1_in(19) ); \INFERRED_GEN.icount_out[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(1), I1 => load_Counter_Reg(0), I2 => icount_out0_carry_n_7, O => p_1_in(1) ); \INFERRED_GEN.icount_out[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(9), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__3_n_4\, O => p_1_in(20) ); \INFERRED_GEN.icount_out[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(10), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__4_n_7\, O => p_1_in(21) ); \INFERRED_GEN.icount_out[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(11), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__4_n_6\, O => p_1_in(22) ); \INFERRED_GEN.icount_out[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(12), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__4_n_5\, O => p_1_in(23) ); \INFERRED_GEN.icount_out[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(13), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__4_n_4\, O => p_1_in(24) ); \INFERRED_GEN.icount_out[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(14), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__5_n_7\, O => p_1_in(25) ); \INFERRED_GEN.icount_out[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(15), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__5_n_6\, O => p_1_in(26) ); \INFERRED_GEN.icount_out[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(16), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__5_n_5\, O => p_1_in(27) ); \INFERRED_GEN.icount_out[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(17), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__5_n_4\, O => p_1_in(28) ); \INFERRED_GEN.icount_out[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(18), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__6_n_7\, O => p_1_in(29) ); \INFERRED_GEN.icount_out[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(2), I1 => load_Counter_Reg(0), I2 => icount_out0_carry_n_6, O => p_1_in(2) ); \INFERRED_GEN.icount_out[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(19), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__6_n_6\, O => p_1_in(30) ); \INFERRED_GEN.icount_out[31]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(20), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__6_n_5\, O => p_1_in(31) ); \INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0000E200" ) port map ( I0 => \^counter_tc\(0), I1 => E(0), I2 => \icount_out0_carry__6_n_4\, I3 => s_axi_aresetn, I4 => load_Counter_Reg(0), O => \INFERRED_GEN.icount_out[32]_i_1_n_0\ ); \INFERRED_GEN.icount_out[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(3), I1 => load_Counter_Reg(0), I2 => icount_out0_carry_n_5, O => p_1_in(3) ); \INFERRED_GEN.icount_out[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(4), I1 => load_Counter_Reg(0), I2 => icount_out0_carry_n_4, O => p_1_in(4) ); \INFERRED_GEN.icount_out[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(5), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__0_n_7\, O => p_1_in(5) ); \INFERRED_GEN.icount_out[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(6), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__0_n_6\, O => p_1_in(6) ); \INFERRED_GEN.icount_out[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(7), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__0_n_5\, O => p_1_in(7) ); \INFERRED_GEN.icount_out[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(8), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__0_n_4\, O => p_1_in(8) ); \INFERRED_GEN.icount_out[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => read_Mux_In(9), I1 => load_Counter_Reg(0), I2 => \icount_out0_carry__1_n_7\, O => p_1_in(9) ); \INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(0), Q => \^load_reg_gen[0].load_reg_i\(0), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(10), Q => \^load_reg_gen[0].load_reg_i\(10), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(11), Q => \^load_reg_gen[0].load_reg_i\(11), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(12), Q => \^load_reg_gen[0].load_reg_i\(12), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(13), Q => \^load_reg_gen[0].load_reg_i\(13), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(14), Q => \^load_reg_gen[0].load_reg_i\(14), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(15), Q => \^load_reg_gen[0].load_reg_i\(15), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(16), Q => \^load_reg_gen[0].load_reg_i\(16), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(17), Q => \^load_reg_gen[0].load_reg_i\(17), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(18), Q => \^load_reg_gen[0].load_reg_i\(18), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(19), Q => \^load_reg_gen[0].load_reg_i\(19), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(1), Q => \^load_reg_gen[0].load_reg_i\(1), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(20), Q => \^load_reg_gen[0].load_reg_i\(20), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(21), Q => \^load_reg_gen[0].load_reg_i\(21), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(22), Q => \^load_reg_gen[0].load_reg_i\(22), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(23), Q => \^load_reg_gen[0].load_reg_i\(23), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(24), Q => \^load_reg_gen[0].load_reg_i\(24), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(25), Q => \^load_reg_gen[0].load_reg_i\(25), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(26), Q => \^load_reg_gen[0].load_reg_i\(26), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(27), Q => \^load_reg_gen[0].load_reg_i\(27), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(28), Q => \^load_reg_gen[0].load_reg_i\(28), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(29), Q => \^load_reg_gen[0].load_reg_i\(29), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(2), Q => \^load_reg_gen[0].load_reg_i\(2), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(30), Q => \^load_reg_gen[0].load_reg_i\(30), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(31), Q => \^load_reg_gen[0].load_reg_i\(31), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \INFERRED_GEN.icount_out[32]_i_1_n_0\, Q => \^counter_tc\(0), R => '0' ); \INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(3), Q => \^load_reg_gen[0].load_reg_i\(3), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(4), Q => \^load_reg_gen[0].load_reg_i\(4), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(5), Q => \^load_reg_gen[0].load_reg_i\(5), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(6), Q => \^load_reg_gen[0].load_reg_i\(6), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(7), Q => \^load_reg_gen[0].load_reg_i\(7), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(8), Q => \^load_reg_gen[0].load_reg_i\(8), R => s_axi_aresetn_0 ); \INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => E(0), D => p_1_in(9), Q => \^load_reg_gen[0].load_reg_i\(9), R => s_axi_aresetn_0 ); generateOutPre0_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^counter_tc\(0), I1 => Q(0), O => generateOutPre0_reg ); icount_out0_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => icount_out0_carry_n_0, CO(2) => icount_out0_carry_n_1, CO(1) => icount_out0_carry_n_2, CO(0) => icount_out0_carry_n_3, CYINIT => \^load_reg_gen[0].load_reg_i\(0), DI(3 downto 1) => \^load_reg_gen[0].load_reg_i\(3 downto 1), DI(0) => \icount_out0_carry_i_1__0_n_0\, O(3) => icount_out0_carry_n_4, O(2) => icount_out0_carry_n_5, O(1) => icount_out0_carry_n_6, O(0) => icount_out0_carry_n_7, S(3) => \icount_out0_carry_i_2__0_n_0\, S(2) => \icount_out0_carry_i_3__0_n_0\, S(1) => \icount_out0_carry_i_4__0_n_0\, S(0) => S(0) ); \icount_out0_carry__0\: unisim.vcomponents.CARRY4 port map ( CI => icount_out0_carry_n_0, CO(3) => \icount_out0_carry__0_n_0\, CO(2) => \icount_out0_carry__0_n_1\, CO(1) => \icount_out0_carry__0_n_2\, CO(0) => \icount_out0_carry__0_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(7 downto 4), O(3) => \icount_out0_carry__0_n_4\, O(2) => \icount_out0_carry__0_n_5\, O(1) => \icount_out0_carry__0_n_6\, O(0) => \icount_out0_carry__0_n_7\, S(3) => \icount_out0_carry__0_i_1__0_n_0\, S(2) => \icount_out0_carry__0_i_2__0_n_0\, S(1) => \icount_out0_carry__0_i_3__0_n_0\, S(0) => \icount_out0_carry__0_i_4__0_n_0\ ); \icount_out0_carry__0_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(7), I1 => \^load_reg_gen[0].load_reg_i\(8), O => \icount_out0_carry__0_i_1__0_n_0\ ); \icount_out0_carry__0_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(6), I1 => \^load_reg_gen[0].load_reg_i\(7), O => \icount_out0_carry__0_i_2__0_n_0\ ); \icount_out0_carry__0_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(5), I1 => \^load_reg_gen[0].load_reg_i\(6), O => \icount_out0_carry__0_i_3__0_n_0\ ); \icount_out0_carry__0_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(4), I1 => \^load_reg_gen[0].load_reg_i\(5), O => \icount_out0_carry__0_i_4__0_n_0\ ); \icount_out0_carry__1\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__0_n_0\, CO(3) => \icount_out0_carry__1_n_0\, CO(2) => \icount_out0_carry__1_n_1\, CO(1) => \icount_out0_carry__1_n_2\, CO(0) => \icount_out0_carry__1_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(11 downto 8), O(3) => \icount_out0_carry__1_n_4\, O(2) => \icount_out0_carry__1_n_5\, O(1) => \icount_out0_carry__1_n_6\, O(0) => \icount_out0_carry__1_n_7\, S(3) => \icount_out0_carry__1_i_1__0_n_0\, S(2) => \icount_out0_carry__1_i_2__0_n_0\, S(1) => \icount_out0_carry__1_i_3__0_n_0\, S(0) => \icount_out0_carry__1_i_4__0_n_0\ ); \icount_out0_carry__1_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(11), I1 => \^load_reg_gen[0].load_reg_i\(12), O => \icount_out0_carry__1_i_1__0_n_0\ ); \icount_out0_carry__1_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(10), I1 => \^load_reg_gen[0].load_reg_i\(11), O => \icount_out0_carry__1_i_2__0_n_0\ ); \icount_out0_carry__1_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(9), I1 => \^load_reg_gen[0].load_reg_i\(10), O => \icount_out0_carry__1_i_3__0_n_0\ ); \icount_out0_carry__1_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(8), I1 => \^load_reg_gen[0].load_reg_i\(9), O => \icount_out0_carry__1_i_4__0_n_0\ ); \icount_out0_carry__2\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__1_n_0\, CO(3) => \icount_out0_carry__2_n_0\, CO(2) => \icount_out0_carry__2_n_1\, CO(1) => \icount_out0_carry__2_n_2\, CO(0) => \icount_out0_carry__2_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(15 downto 12), O(3) => \icount_out0_carry__2_n_4\, O(2) => \icount_out0_carry__2_n_5\, O(1) => \icount_out0_carry__2_n_6\, O(0) => \icount_out0_carry__2_n_7\, S(3) => \icount_out0_carry__2_i_1__0_n_0\, S(2) => \icount_out0_carry__2_i_2__0_n_0\, S(1) => \icount_out0_carry__2_i_3__0_n_0\, S(0) => \icount_out0_carry__2_i_4__0_n_0\ ); \icount_out0_carry__2_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(15), I1 => \^load_reg_gen[0].load_reg_i\(16), O => \icount_out0_carry__2_i_1__0_n_0\ ); \icount_out0_carry__2_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(14), I1 => \^load_reg_gen[0].load_reg_i\(15), O => \icount_out0_carry__2_i_2__0_n_0\ ); \icount_out0_carry__2_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(13), I1 => \^load_reg_gen[0].load_reg_i\(14), O => \icount_out0_carry__2_i_3__0_n_0\ ); \icount_out0_carry__2_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(12), I1 => \^load_reg_gen[0].load_reg_i\(13), O => \icount_out0_carry__2_i_4__0_n_0\ ); \icount_out0_carry__3\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__2_n_0\, CO(3) => \icount_out0_carry__3_n_0\, CO(2) => \icount_out0_carry__3_n_1\, CO(1) => \icount_out0_carry__3_n_2\, CO(0) => \icount_out0_carry__3_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(19 downto 16), O(3) => \icount_out0_carry__3_n_4\, O(2) => \icount_out0_carry__3_n_5\, O(1) => \icount_out0_carry__3_n_6\, O(0) => \icount_out0_carry__3_n_7\, S(3) => \icount_out0_carry__3_i_1__0_n_0\, S(2) => \icount_out0_carry__3_i_2__0_n_0\, S(1) => \icount_out0_carry__3_i_3__0_n_0\, S(0) => \icount_out0_carry__3_i_4__0_n_0\ ); \icount_out0_carry__3_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(19), I1 => \^load_reg_gen[0].load_reg_i\(20), O => \icount_out0_carry__3_i_1__0_n_0\ ); \icount_out0_carry__3_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(18), I1 => \^load_reg_gen[0].load_reg_i\(19), O => \icount_out0_carry__3_i_2__0_n_0\ ); \icount_out0_carry__3_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(17), I1 => \^load_reg_gen[0].load_reg_i\(18), O => \icount_out0_carry__3_i_3__0_n_0\ ); \icount_out0_carry__3_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(16), I1 => \^load_reg_gen[0].load_reg_i\(17), O => \icount_out0_carry__3_i_4__0_n_0\ ); \icount_out0_carry__4\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__3_n_0\, CO(3) => \icount_out0_carry__4_n_0\, CO(2) => \icount_out0_carry__4_n_1\, CO(1) => \icount_out0_carry__4_n_2\, CO(0) => \icount_out0_carry__4_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(23 downto 20), O(3) => \icount_out0_carry__4_n_4\, O(2) => \icount_out0_carry__4_n_5\, O(1) => \icount_out0_carry__4_n_6\, O(0) => \icount_out0_carry__4_n_7\, S(3) => \icount_out0_carry__4_i_1__0_n_0\, S(2) => \icount_out0_carry__4_i_2__0_n_0\, S(1) => \icount_out0_carry__4_i_3__0_n_0\, S(0) => \icount_out0_carry__4_i_4__0_n_0\ ); \icount_out0_carry__4_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(23), I1 => \^load_reg_gen[0].load_reg_i\(24), O => \icount_out0_carry__4_i_1__0_n_0\ ); \icount_out0_carry__4_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(22), I1 => \^load_reg_gen[0].load_reg_i\(23), O => \icount_out0_carry__4_i_2__0_n_0\ ); \icount_out0_carry__4_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(21), I1 => \^load_reg_gen[0].load_reg_i\(22), O => \icount_out0_carry__4_i_3__0_n_0\ ); \icount_out0_carry__4_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(20), I1 => \^load_reg_gen[0].load_reg_i\(21), O => \icount_out0_carry__4_i_4__0_n_0\ ); \icount_out0_carry__5\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__4_n_0\, CO(3) => \icount_out0_carry__5_n_0\, CO(2) => \icount_out0_carry__5_n_1\, CO(1) => \icount_out0_carry__5_n_2\, CO(0) => \icount_out0_carry__5_n_3\, CYINIT => '0', DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(27 downto 24), O(3) => \icount_out0_carry__5_n_4\, O(2) => \icount_out0_carry__5_n_5\, O(1) => \icount_out0_carry__5_n_6\, O(0) => \icount_out0_carry__5_n_7\, S(3) => \icount_out0_carry__5_i_1__0_n_0\, S(2) => \icount_out0_carry__5_i_2__0_n_0\, S(1) => \icount_out0_carry__5_i_3__0_n_0\, S(0) => \icount_out0_carry__5_i_4__0_n_0\ ); \icount_out0_carry__5_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(27), I1 => \^load_reg_gen[0].load_reg_i\(28), O => \icount_out0_carry__5_i_1__0_n_0\ ); \icount_out0_carry__5_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(26), I1 => \^load_reg_gen[0].load_reg_i\(27), O => \icount_out0_carry__5_i_2__0_n_0\ ); \icount_out0_carry__5_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(25), I1 => \^load_reg_gen[0].load_reg_i\(26), O => \icount_out0_carry__5_i_3__0_n_0\ ); \icount_out0_carry__5_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(24), I1 => \^load_reg_gen[0].load_reg_i\(25), O => \icount_out0_carry__5_i_4__0_n_0\ ); \icount_out0_carry__6\: unisim.vcomponents.CARRY4 port map ( CI => \icount_out0_carry__5_n_0\, CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3), CO(2) => \icount_out0_carry__6_n_1\, CO(1) => \icount_out0_carry__6_n_2\, CO(0) => \icount_out0_carry__6_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => \^load_reg_gen[0].load_reg_i\(30 downto 28), O(3) => \icount_out0_carry__6_n_4\, O(2) => \icount_out0_carry__6_n_5\, O(1) => \icount_out0_carry__6_n_6\, O(0) => \icount_out0_carry__6_n_7\, S(3) => \icount_out0_carry__6_i_1__0_n_0\, S(2) => \icount_out0_carry__6_i_2__0_n_0\, S(1) => \icount_out0_carry__6_i_3__0_n_0\, S(0) => \icount_out0_carry__6_i_4__0_n_0\ ); \icount_out0_carry__6_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(31), O => \icount_out0_carry__6_i_1__0_n_0\ ); \icount_out0_carry__6_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(30), I1 => \^load_reg_gen[0].load_reg_i\(31), O => \icount_out0_carry__6_i_2__0_n_0\ ); \icount_out0_carry__6_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(29), I1 => \^load_reg_gen[0].load_reg_i\(30), O => \icount_out0_carry__6_i_3__0_n_0\ ); \icount_out0_carry__6_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(28), I1 => \^load_reg_gen[0].load_reg_i\(29), O => \icount_out0_carry__6_i_4__0_n_0\ ); \icount_out0_carry_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(1), O => \icount_out0_carry_i_1__0_n_0\ ); \icount_out0_carry_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(3), I1 => \^load_reg_gen[0].load_reg_i\(4), O => \icount_out0_carry_i_2__0_n_0\ ); \icount_out0_carry_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(2), I1 => \^load_reg_gen[0].load_reg_i\(3), O => \icount_out0_carry_i_3__0_n_0\ ); \icount_out0_carry_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^load_reg_gen[0].load_reg_i\(1), I1 => \^load_reg_gen[0].load_reg_i\(2), O => \icount_out0_carry_i_4__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f is port ( D : out STD_LOGIC_VECTOR ( 31 downto 0 ); Bus_RNW_reg_reg : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[31]\ : in STD_LOGIC; Bus_RNW_reg_reg_0 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC; Bus_RNW_reg_reg_1 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC; Bus_RNW_reg_reg_2 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC; Bus_RNW_reg_reg_3 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC; Bus_RNW_reg_reg_4 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC; Bus_RNW_reg_reg_5 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC; Bus_RNW_reg_reg_6 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC; Bus_RNW_reg_reg_7 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC; Bus_RNW_reg_reg_8 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC; Bus_RNW_reg_reg_9 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC; Bus_RNW_reg_reg_10 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC; Bus_RNW_reg_reg_11 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC; Bus_RNW_reg_reg_12 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC; Bus_RNW_reg_reg_13 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC; Bus_RNW_reg_reg_14 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC; Bus_RNW_reg_reg_15 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC; Bus_RNW_reg_reg_16 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC; Bus_RNW_reg_reg_17 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC; Bus_RNW_reg_reg_18 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC; \LOAD_REG_GEN[31].LOAD_REG_I\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f is signal \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC; signal cyout_1 : STD_LOGIC; signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)"; begin \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(31), CO(0) => cyout_1, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[31]\, S(0) => Bus_RNW_reg_reg ); \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(21), CO(0) => \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[21]\, S(0) => Bus_RNW_reg_reg_9 ); \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(20), CO(0) => \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[20]\, S(0) => Bus_RNW_reg_reg_10 ); \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(19), CO(0) => \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[19]\, S(0) => Bus_RNW_reg_reg_11 ); \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(18), CO(0) => \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[18]\, S(0) => Bus_RNW_reg_reg_12 ); \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(17), CO(0) => \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[17]\, S(0) => Bus_RNW_reg_reg_13 ); \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(16), CO(0) => \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[16]\, S(0) => Bus_RNW_reg_reg_14 ); \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(15), CO(0) => \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[15]\, S(0) => Bus_RNW_reg_reg_15 ); \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(14), CO(0) => \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[14]\, S(0) => Bus_RNW_reg_reg_16 ); \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(13), CO(0) => \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[13]\, S(0) => Bus_RNW_reg_reg_17 ); \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(12), CO(0) => \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[12]\, S(0) => Bus_RNW_reg_reg_18 ); \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(30), CO(0) => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[30]\, S(0) => Bus_RNW_reg_reg_0 ); \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(11), CO(0) => \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[11]\, S(0) => \LOAD_REG_GEN[20].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(10), CO(0) => \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[10]\, S(0) => \LOAD_REG_GEN[21].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(9), CO(0) => \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[9]\, S(0) => \LOAD_REG_GEN[22].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(8), CO(0) => \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[8]\, S(0) => \LOAD_REG_GEN[23].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(7), CO(0) => \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[7]\, S(0) => \LOAD_REG_GEN[24].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(6), CO(0) => \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[6]\, S(0) => \LOAD_REG_GEN[25].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(5), CO(0) => \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[5]\, S(0) => \LOAD_REG_GEN[26].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(4), CO(0) => \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[4]\, S(0) => \LOAD_REG_GEN[27].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(3), CO(0) => \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[3]\, S(0) => \LOAD_REG_GEN[28].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(2), CO(0) => \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[2]\, S(0) => \LOAD_REG_GEN[29].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(29), CO(0) => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[29]\, S(0) => Bus_RNW_reg_reg_1 ); \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(1), CO(0) => \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[1]\, S(0) => \LOAD_REG_GEN[30].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(0), CO(0) => \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[0]\, S(0) => \LOAD_REG_GEN[31].LOAD_REG_I\ ); \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(28), CO(0) => \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[28]\, S(0) => Bus_RNW_reg_reg_2 ); \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(27), CO(0) => \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[27]\, S(0) => Bus_RNW_reg_reg_3 ); \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(26), CO(0) => \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[26]\, S(0) => Bus_RNW_reg_reg_4 ); \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(25), CO(0) => \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[25]\, S(0) => Bus_RNW_reg_reg_5 ); \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(24), CO(0) => \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[24]\, S(0) => Bus_RNW_reg_reg_6 ); \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(23), CO(0) => \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[23]\, S(0) => Bus_RNW_reg_reg_7 ); \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2), CO(1) => D(22), CO(0) => \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\, CYINIT => '0', DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2), DI(1 downto 0) => B"11", O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2), S(1) => \INFERRED_GEN.icount_out_reg[22]\, S(0) => Bus_RNW_reg_reg_8 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f is port ( ce_expnd_i_7 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"0010" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(2), I1 => \bus2ip_addr_i_reg[4]\(1), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(0), O => ce_expnd_i_7 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ is port ( ce_expnd_i_5 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ : entity is "pselect_f"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(2), I1 => \bus2ip_addr_i_reg[4]\(0), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(1), O => ce_expnd_i_5 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ is port ( ce_expnd_i_3 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ : entity is "pselect_f"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(1), I1 => \bus2ip_addr_i_reg[4]\(0), I2 => \bus2ip_addr_i_reg[4]\(2), I3 => Q, O => ce_expnd_i_3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ is port ( ce_expnd_i_2 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ : entity is "pselect_f"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(1), I1 => \bus2ip_addr_i_reg[4]\(2), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(0), O => ce_expnd_i_2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ is port ( ce_expnd_i_1 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ : entity is "pselect_f"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(0), I1 => \bus2ip_addr_i_reg[4]\(2), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(1), O => ce_expnd_i_1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ is port ( ce_expnd_i_0 : out STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ : entity is "pselect_f"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ is begin CS: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(1), I1 => \bus2ip_addr_i_reg[4]\(0), I2 => \bus2ip_addr_i_reg[4]\(2), I3 => Q, O => ce_expnd_i_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is port ( \LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC; \s_axi_rdata_i_reg[12]\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC; pair0_Select : out STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \s_axi_rdata_i_reg[11]\ : out STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC; \LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC; D_0 : out STD_LOGIC; \bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 ); \LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC; D_1 : out STD_LOGIC; s_axi_rvalid_i_reg : out STD_LOGIC; s_axi_rvalid_i_reg_0 : out STD_LOGIC; s_axi_rvalid_i_reg_1 : out STD_LOGIC; s_axi_rvalid_i_reg_2 : out STD_LOGIC; s_axi_bvalid_i_reg : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC; \TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC; READ_DONE0_I : out STD_LOGIC; READ_DONE1_I : out STD_LOGIC; Q : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 ); s_axi_aresetn : in STD_LOGIC; \state1__2\ : in STD_LOGIC; s_axi_arvalid_0 : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arvalid : in STD_LOGIC; is_write_reg : in STD_LOGIC; is_read : in STD_LOGIC; \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_rready : in STD_LOGIC; s_axi_rvalid_i_reg_3 : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_bvalid_i_reg_0 : in STD_LOGIC; bus2ip_rnw_i : in STD_LOGIC; D_2 : in STD_LOGIC; read_done1 : in STD_LOGIC; \bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\ : STD_LOGIC; signal \^load_reg_gen[31].load_reg_i\ : STD_LOGIC; signal \^tcsr0_generate[23].tcsr0_ff_i\ : STD_LOGIC; signal ce_expnd_i_0 : STD_LOGIC; signal ce_expnd_i_1 : STD_LOGIC; signal ce_expnd_i_2 : STD_LOGIC; signal ce_expnd_i_3 : STD_LOGIC; signal ce_expnd_i_5 : STD_LOGIC; signal ce_expnd_i_6 : STD_LOGIC; signal ce_expnd_i_7 : STD_LOGIC; signal cs_ce_clr : STD_LOGIC; signal \eqOp__4\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal s_axi_arready_INST_0_i_4_n_0 : STD_LOGIC; signal \^s_axi_rvalid_i_reg\ : STD_LOGIC; signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC; signal \^s_axi_rvalid_i_reg_1\ : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC; signal s_axi_wready_INST_0_i_2_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_7\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[9].LOAD_REG_I_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of READ_DONE0_I_i_2 : label is "soft_lutpair7"; attribute SOFT_HLUTNM of READ_DONE1_I_i_2 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \TCSR0_GENERATE[20].TCSR0_FF_I_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \TCSR0_GENERATE[21].TCSR0_FF_I_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \TCSR0_GENERATE[23].TCSR0_FF_I_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \TCSR0_GENERATE[24].TCSR0_FF_I_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \TCSR1_GENERATE[22].TCSR1_FF_I_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \TCSR1_GENERATE[23].TCSR1_FF_I_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \TCSR1_GENERATE[24].TCSR1_FF_I_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_2 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_3 : label is "soft_lutpair8"; attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_4 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_2 : label is "soft_lutpair2"; begin \LOAD_REG_GEN[31].LOAD_REG_I\ <= \^load_reg_gen[31].load_reg_i\; \TCSR0_GENERATE[23].TCSR0_FF_I\ <= \^tcsr0_generate[23].tcsr0_ff_i\; s_axi_arready <= \^s_axi_arready\; s_axi_rvalid_i_reg <= \^s_axi_rvalid_i_reg\; s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\; s_axi_rvalid_i_reg_1 <= \^s_axi_rvalid_i_reg_1\; s_axi_wready <= \^s_axi_wready\; Bus_RNW_reg_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => bus2ip_rnw_i, I1 => Q, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, O => Bus_RNW_reg_i_1_n_0 ); Bus_RNW_reg_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => Bus_RNW_reg_i_1_n_0, Q => \^tcsr0_generate[23].tcsr0_ff_i\, R => '0' ); \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(84), O => \s_axi_rdata_i_reg[31]\ ); \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \s_axi_rdata_i_reg[0]_0\ ); \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \s_axi_rdata_i_reg[0]\ ); \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(74), O => \s_axi_rdata_i_reg[21]\ ); \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(73), O => \s_axi_rdata_i_reg[20]\ ); \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(72), O => \s_axi_rdata_i_reg[19]\ ); \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(71), O => \s_axi_rdata_i_reg[18]\ ); \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(70), O => \s_axi_rdata_i_reg[17]\ ); \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(69), O => \s_axi_rdata_i_reg[16]\ ); \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(68), O => \s_axi_rdata_i_reg[15]\ ); \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(67), O => \s_axi_rdata_i_reg[14]\ ); \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(66), O => \s_axi_rdata_i_reg[13]\ ); \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(65), O => \s_axi_rdata_i_reg[12]\ ); \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(83), O => \s_axi_rdata_i_reg[30]\ ); \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0777FFFF" ) port map ( I0 => read_Mux_In(64), I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(87), I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I4 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \s_axi_rdata_i_reg[11]\ ); \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \s_axi_rdata_i_reg[10]\ ); \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(82), O => \s_axi_rdata_i_reg[29]\ ); \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(81), O => \s_axi_rdata_i_reg[28]\ ); \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(80), O => \s_axi_rdata_i_reg[27]\ ); \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(79), O => \s_axi_rdata_i_reg[26]\ ); \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(78), O => \s_axi_rdata_i_reg[25]\ ); \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(77), O => \s_axi_rdata_i_reg[24]\ ); \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(76), O => \s_axi_rdata_i_reg[23]\ ); \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^tcsr0_generate[23].tcsr0_ff_i\, I1 => \^load_reg_gen[31].load_reg_i\, I2 => read_Mux_In(75), O => \s_axi_rdata_i_reg[22]\ ); \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_7, Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => \bus2ip_addr_i_reg[4]\(2), I1 => \bus2ip_addr_i_reg[4]\(1), I2 => Q, I3 => \bus2ip_addr_i_reg[4]\(0), O => ce_expnd_i_6 ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_6, Q => \^load_reg_gen[31].load_reg_i\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_5, Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_3, Q => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_2, Q => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_1, Q => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"EF" ) port map ( I0 => \^s_axi_wready\, I1 => \^s_axi_arready\, I2 => s_axi_aresetn, O => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => Q, D => ce_expnd_i_0, Q => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\, R => cs_ce_clr ); \LOAD_REG_GEN[0].LOAD_REG_I_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(31), I1 => read_Mux_In(31), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => D_0 ); \LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(31), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(63), O => D_1 ); \LOAD_REG_GEN[0].LOAD_REG_I_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \bus2ip_wrce__0\(0) ); \LOAD_REG_GEN[10].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(21), I1 => read_Mux_In(21), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[10].LOAD_REG_I\ ); \LOAD_REG_GEN[10].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(21), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(53), O => \LOAD_REG_GEN[10].LOAD_REG_I_0\ ); \LOAD_REG_GEN[11].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(20), I1 => read_Mux_In(20), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[11].LOAD_REG_I\ ); \LOAD_REG_GEN[11].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(20), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(52), O => \LOAD_REG_GEN[11].LOAD_REG_I_0\ ); \LOAD_REG_GEN[12].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(19), I1 => read_Mux_In(19), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[12].LOAD_REG_I\ ); \LOAD_REG_GEN[12].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(19), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(51), O => \LOAD_REG_GEN[12].LOAD_REG_I_0\ ); \LOAD_REG_GEN[13].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(18), I1 => read_Mux_In(18), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[13].LOAD_REG_I\ ); \LOAD_REG_GEN[13].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(18), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(50), O => \LOAD_REG_GEN[13].LOAD_REG_I_0\ ); \LOAD_REG_GEN[14].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(17), I1 => read_Mux_In(17), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[14].LOAD_REG_I\ ); \LOAD_REG_GEN[14].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(17), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(49), O => \LOAD_REG_GEN[14].LOAD_REG_I_0\ ); \LOAD_REG_GEN[15].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(16), I1 => read_Mux_In(16), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[15].LOAD_REG_I\ ); \LOAD_REG_GEN[15].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(16), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(48), O => \LOAD_REG_GEN[15].LOAD_REG_I_0\ ); \LOAD_REG_GEN[16].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(15), I1 => read_Mux_In(15), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[16].LOAD_REG_I\ ); \LOAD_REG_GEN[16].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(15), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(47), O => \LOAD_REG_GEN[16].LOAD_REG_I_0\ ); \LOAD_REG_GEN[17].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(14), I1 => read_Mux_In(14), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[17].LOAD_REG_I\ ); \LOAD_REG_GEN[17].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(14), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(46), O => \LOAD_REG_GEN[17].LOAD_REG_I_0\ ); \LOAD_REG_GEN[18].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(13), I1 => read_Mux_In(13), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[18].LOAD_REG_I\ ); \LOAD_REG_GEN[18].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(13), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(45), O => \LOAD_REG_GEN[18].LOAD_REG_I_0\ ); \LOAD_REG_GEN[19].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(12), I1 => read_Mux_In(12), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[19].LOAD_REG_I\ ); \LOAD_REG_GEN[19].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(12), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(44), O => \LOAD_REG_GEN[19].LOAD_REG_I_0\ ); \LOAD_REG_GEN[1].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(30), I1 => read_Mux_In(30), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[1].LOAD_REG_I\ ); \LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(30), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(62), O => \LOAD_REG_GEN[1].LOAD_REG_I_0\ ); \LOAD_REG_GEN[20].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(11), I1 => read_Mux_In(11), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[20].LOAD_REG_I\ ); \LOAD_REG_GEN[20].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(11), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(43), O => \LOAD_REG_GEN[20].LOAD_REG_I_0\ ); \LOAD_REG_GEN[21].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(10), I1 => read_Mux_In(10), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[21].LOAD_REG_I\ ); \LOAD_REG_GEN[21].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(10), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(42), O => \LOAD_REG_GEN[21].LOAD_REG_I_0\ ); \LOAD_REG_GEN[22].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(9), I1 => read_Mux_In(9), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[22].LOAD_REG_I\ ); \LOAD_REG_GEN[22].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(9), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(41), O => \LOAD_REG_GEN[22].LOAD_REG_I_0\ ); \LOAD_REG_GEN[23].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(8), I1 => read_Mux_In(8), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[23].LOAD_REG_I\ ); \LOAD_REG_GEN[23].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(8), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(40), O => \LOAD_REG_GEN[23].LOAD_REG_I_0\ ); \LOAD_REG_GEN[24].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(7), I1 => read_Mux_In(7), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[24].LOAD_REG_I\ ); \LOAD_REG_GEN[24].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(7), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(39), O => \LOAD_REG_GEN[24].LOAD_REG_I_0\ ); \LOAD_REG_GEN[25].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(6), I1 => read_Mux_In(6), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[25].LOAD_REG_I\ ); \LOAD_REG_GEN[25].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(6), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(38), O => \LOAD_REG_GEN[25].LOAD_REG_I_0\ ); \LOAD_REG_GEN[26].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(5), I1 => read_Mux_In(5), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[26].LOAD_REG_I\ ); \LOAD_REG_GEN[26].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(5), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(37), O => \LOAD_REG_GEN[26].LOAD_REG_I_0\ ); \LOAD_REG_GEN[27].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(4), I1 => read_Mux_In(4), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[27].LOAD_REG_I\ ); \LOAD_REG_GEN[27].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(4), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(36), O => \LOAD_REG_GEN[27].LOAD_REG_I_0\ ); \LOAD_REG_GEN[28].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(3), I1 => read_Mux_In(3), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[28].LOAD_REG_I\ ); \LOAD_REG_GEN[28].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(3), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(35), O => \LOAD_REG_GEN[28].LOAD_REG_I_0\ ); \LOAD_REG_GEN[29].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(2), I1 => read_Mux_In(2), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[29].LOAD_REG_I\ ); \LOAD_REG_GEN[29].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(2), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(34), O => \LOAD_REG_GEN[29].LOAD_REG_I_0\ ); \LOAD_REG_GEN[2].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(29), I1 => read_Mux_In(29), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[2].LOAD_REG_I\ ); \LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(29), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(61), O => \LOAD_REG_GEN[2].LOAD_REG_I_0\ ); \LOAD_REG_GEN[30].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(1), I1 => read_Mux_In(1), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[30].LOAD_REG_I\ ); \LOAD_REG_GEN[30].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(1), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(33), O => \LOAD_REG_GEN[30].LOAD_REG_I_0\ ); \LOAD_REG_GEN[31].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(0), I1 => read_Mux_In(0), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[31].LOAD_REG_I_0\ ); \LOAD_REG_GEN[31].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(0), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(32), O => \LOAD_REG_GEN[31].LOAD_REG_I_1\ ); \LOAD_REG_GEN[3].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(28), I1 => read_Mux_In(28), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[3].LOAD_REG_I\ ); \LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(28), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(60), O => \LOAD_REG_GEN[3].LOAD_REG_I_0\ ); \LOAD_REG_GEN[4].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(27), I1 => read_Mux_In(27), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[4].LOAD_REG_I\ ); \LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(27), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(59), O => \LOAD_REG_GEN[4].LOAD_REG_I_0\ ); \LOAD_REG_GEN[5].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(26), I1 => read_Mux_In(26), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[5].LOAD_REG_I\ ); \LOAD_REG_GEN[5].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(26), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(58), O => \LOAD_REG_GEN[5].LOAD_REG_I_0\ ); \LOAD_REG_GEN[6].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(25), I1 => read_Mux_In(25), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[6].LOAD_REG_I\ ); \LOAD_REG_GEN[6].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(25), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(57), O => \LOAD_REG_GEN[6].LOAD_REG_I_0\ ); \LOAD_REG_GEN[7].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(24), I1 => read_Mux_In(24), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[7].LOAD_REG_I\ ); \LOAD_REG_GEN[7].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(24), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(56), O => \LOAD_REG_GEN[7].LOAD_REG_I_0\ ); \LOAD_REG_GEN[8].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(23), I1 => read_Mux_In(23), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[8].LOAD_REG_I\ ); \LOAD_REG_GEN[8].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(23), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(55), O => \LOAD_REG_GEN[8].LOAD_REG_I_0\ ); \LOAD_REG_GEN[9].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCAC" ) port map ( I0 => s_axi_wdata(22), I1 => read_Mux_In(22), I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \LOAD_REG_GEN[9].LOAD_REG_I\ ); \LOAD_REG_GEN[9].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(22), I1 => \^load_reg_gen[31].load_reg_i\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => read_Mux_In(54), O => \LOAD_REG_GEN[9].LOAD_REG_I_0\ ); \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_7 => ce_expnd_i_7 ); \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_5 => ce_expnd_i_5 ); \MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_3 => ce_expnd_i_3 ); \MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_2 => ce_expnd_i_2 ); \MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_1 => ce_expnd_i_1 ); \MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ port map ( Q => Q, \bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0), ce_expnd_i_0 => ce_expnd_i_0 ); READ_DONE0_I_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^load_reg_gen[31].load_reg_i\, I1 => D_2, O => READ_DONE0_I ); READ_DONE1_I_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => read_done1, O => READ_DONE1_I ); \TCSR0_GENERATE[20].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => bus2ip_wrce(1) ); \TCSR0_GENERATE[21].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"32" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, O => pair0_Select ); \TCSR0_GENERATE[23].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"20FF" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, I2 => s_axi_wdata(8), I3 => s_axi_aresetn, O => \TCSR0_GENERATE[23].TCSR0_FF_I_0\ ); \TCSR0_GENERATE[24].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFEEEAEE" ) port map ( I0 => s_axi_wdata(10), I1 => read_Mux_In(86), I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, I4 => s_axi_wdata(7), O => \TCSR0_GENERATE[24].TCSR0_FF_I\ ); \TCSR1_GENERATE[22].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => bus2ip_wrce(0) ); \TCSR1_GENERATE[23].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"20FF" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, I2 => s_axi_wdata(8), I3 => s_axi_aresetn, O => \TCSR1_GENERATE[23].TCSR1_FF_I\ ); \TCSR1_GENERATE[24].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFEEEAEE" ) port map ( I0 => s_axi_wdata(10), I1 => read_Mux_In(85), I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I4 => s_axi_wdata(7), O => \TCSR1_GENERATE[24].TCSR1_FF_I\ ); s_axi_arready_INST_0: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFEFFFEFFFEFF" ) port map ( I0 => \^s_axi_rvalid_i_reg\, I1 => \^s_axi_rvalid_i_reg_0\, I2 => \^s_axi_rvalid_i_reg_1\, I3 => s_axi_arready_INST_0_i_4_n_0, I4 => is_read, I5 => \eqOp__4\, O => \^s_axi_arready\ ); s_axi_arready_INST_0_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^load_reg_gen[31].load_reg_i\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \^s_axi_rvalid_i_reg\ ); s_axi_arready_INST_0_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \^s_axi_rvalid_i_reg_0\ ); s_axi_arready_INST_0_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, I1 => \^tcsr0_generate[23].tcsr0_ff_i\, O => \^s_axi_rvalid_i_reg_1\ ); s_axi_arready_INST_0_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"00FF01FF" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\, I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, O => s_axi_arready_INST_0_i_4_n_0 ); s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"08FF0808" ) port map ( I0 => \^s_axi_wready\, I1 => \state_reg[1]\(1), I2 => \state_reg[1]\(0), I3 => s_axi_bready, I4 => s_axi_bvalid_i_reg_0, O => s_axi_bvalid_i_reg ); s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"08FF0808" ) port map ( I0 => \^s_axi_arready\, I1 => \state_reg[1]\(0), I2 => \state_reg[1]\(1), I3 => s_axi_rready, I4 => s_axi_rvalid_i_reg_3, O => s_axi_rvalid_i_reg_2 ); s_axi_wready_INST_0: unisim.vcomponents.LUT4 generic map( INIT => X"F777" ) port map ( I0 => s_axi_wready_INST_0_i_1_n_0, I1 => s_axi_wready_INST_0_i_2_n_0, I2 => is_write_reg, I3 => \eqOp__4\, O => \^s_axi_wready\ ); s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F0F1" ) port map ( I0 => \^load_reg_gen[31].load_reg_i\, I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I2 => \^tcsr0_generate[23].tcsr0_ff_i\, I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, O => s_axi_wready_INST_0_i_1_n_0 ); s_axi_wready_INST_0_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FF00FF01" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\, I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\, I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\, I3 => \^tcsr0_generate[23].tcsr0_ff_i\, I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, O => s_axi_wready_INST_0_i_2_n_0 ); s_axi_wready_INST_0_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000100" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(4), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(2), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(3), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5), I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0), I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1), O => \eqOp__4\ ); \state[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"77FC44FC" ) port map ( I0 => \state1__2\, I1 => \state_reg[1]\(0), I2 => s_axi_arvalid, I3 => \state_reg[1]\(1), I4 => \^s_axi_wready\, O => D(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"5FFC50FC" ) port map ( I0 => \state1__2\, I1 => s_axi_arvalid_0, I2 => \state_reg[1]\(1), I3 => \state_reg[1]\(0), I4 => \^s_axi_arready\, O => D(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module is port ( \INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC_VECTOR ( 52 downto 0 ); read_Mux_In : out STD_LOGIC_VECTOR ( 10 downto 0 ); generateOutPre0_reg : out STD_LOGIC; counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn_0 : in STD_LOGIC; \TCSR0_GENERATE[27].TCSR0_FF_I\ : in STD_LOGIC; D_1 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 0 to 0 ); load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module is signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC_VECTOR ( 52 downto 0 ); signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 10 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE"; begin \INFERRED_GEN.icount_out_reg[31]\(52 downto 0) <= \^inferred_gen.icount_out_reg[31]\(52 downto 0); read_Mux_In(10 downto 0) <= \^read_mux_in\(10 downto 0); COUNTER_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 port map ( E(0) => E(0), \LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) => \^inferred_gen.icount_out_reg[31]\(31 downto 0), \LOAD_REG_GEN[0].LOAD_REG_I_0\(20 downto 0) => \^inferred_gen.icount_out_reg[31]\(52 downto 32), Q(0) => Q(0), S(0) => S(0), counter_TC(0) => counter_TC(0), generateOutPre0_reg => generateOutPre0_reg, load_Counter_Reg(0) => load_Counter_Reg(0), read_Mux_In(10 downto 0) => \^read_mux_in\(10 downto 0), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_aresetn_0 => s_axi_aresetn_0 ); \LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => D_1, Q => \^inferred_gen.icount_out_reg[31]\(52), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\, Q => \^inferred_gen.icount_out_reg[31]\(42), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\, Q => \^inferred_gen.icount_out_reg[31]\(41), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\, Q => \^inferred_gen.icount_out_reg[31]\(40), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\, Q => \^inferred_gen.icount_out_reg[31]\(39), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\, Q => \^inferred_gen.icount_out_reg[31]\(38), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\, Q => \^inferred_gen.icount_out_reg[31]\(37), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\, Q => \^inferred_gen.icount_out_reg[31]\(36), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\, Q => \^inferred_gen.icount_out_reg[31]\(35), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\, Q => \^inferred_gen.icount_out_reg[31]\(34), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\, Q => \^inferred_gen.icount_out_reg[31]\(33), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\, Q => \^inferred_gen.icount_out_reg[31]\(51), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\, Q => \^inferred_gen.icount_out_reg[31]\(32), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\, Q => \^read_mux_in\(10), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\, Q => \^read_mux_in\(9), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\, Q => \^read_mux_in\(8), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\, Q => \^read_mux_in\(7), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\, Q => \^read_mux_in\(6), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\, Q => \^read_mux_in\(5), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\, Q => \^read_mux_in\(4), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\, Q => \^read_mux_in\(3), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\, Q => \^read_mux_in\(2), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, Q => \^inferred_gen.icount_out_reg[31]\(50), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\, Q => \^read_mux_in\(1), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\, Q => \^read_mux_in\(0), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\, Q => \^inferred_gen.icount_out_reg[31]\(49), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\, Q => \^inferred_gen.icount_out_reg[31]\(48), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\, Q => \^inferred_gen.icount_out_reg[31]\(47), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\, Q => \^inferred_gen.icount_out_reg[31]\(46), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\, Q => \^inferred_gen.icount_out_reg[31]\(45), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\, Q => \^inferred_gen.icount_out_reg[31]\(44), R => s_axi_aresetn_0 ); \LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[27].TCSR0_FF_I\, D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\, Q => \^inferred_gen.icount_out_reg[31]\(43), R => s_axi_aresetn_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 is port ( \INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 31 downto 0 ); \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[1]\ : out STD_LOGIC; \s_axi_rdata_i_reg[2]\ : out STD_LOGIC; \s_axi_rdata_i_reg[3]\ : out STD_LOGIC; \s_axi_rdata_i_reg[4]\ : out STD_LOGIC; \s_axi_rdata_i_reg[5]\ : out STD_LOGIC; \s_axi_rdata_i_reg[6]\ : out STD_LOGIC; \s_axi_rdata_i_reg[7]\ : out STD_LOGIC; \s_axi_rdata_i_reg[8]\ : out STD_LOGIC; \s_axi_rdata_i_reg[9]\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; \s_axi_rdata_i_reg[11]\ : out STD_LOGIC; \s_axi_rdata_i_reg[12]\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC; generateOutPre1_reg : out STD_LOGIC; counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 ); \TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC; D_2 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 0 to 0 ); load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_aresetn : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 : entity is "count_module"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 is signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC; signal read_Mux_In : STD_LOGIC_VECTOR ( 96 to 127 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE"; begin \INFERRED_GEN.icount_out_reg[31]\ <= \^inferred_gen.icount_out_reg[31]\; COUNTER_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f port map ( E(0) => E(0), \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0), Q(31 downto 0) => Q(31 downto 0), S(0) => S(0), SR(0) => \^inferred_gen.icount_out_reg[31]\, counter_TC(0) => counter_TC(0), \counter_TC_Reg_reg[1]\(0) => \counter_TC_Reg_reg[1]\(0), generateOutPre1_reg => generateOutPre1_reg, load_Counter_Reg(0) => load_Counter_Reg(0), read_Mux_In(31) => read_Mux_In(96), read_Mux_In(30) => read_Mux_In(97), read_Mux_In(29) => read_Mux_In(98), read_Mux_In(28) => read_Mux_In(99), read_Mux_In(27) => read_Mux_In(100), read_Mux_In(26) => read_Mux_In(101), read_Mux_In(25) => read_Mux_In(102), read_Mux_In(24) => read_Mux_In(103), read_Mux_In(23) => read_Mux_In(104), read_Mux_In(22) => read_Mux_In(105), read_Mux_In(21) => read_Mux_In(106), read_Mux_In(20) => read_Mux_In(107), read_Mux_In(19) => read_Mux_In(108), read_Mux_In(18) => read_Mux_In(109), read_Mux_In(17) => read_Mux_In(110), read_Mux_In(16) => read_Mux_In(111), read_Mux_In(15) => read_Mux_In(112), read_Mux_In(14) => read_Mux_In(113), read_Mux_In(13) => read_Mux_In(114), read_Mux_In(12) => read_Mux_In(115), read_Mux_In(11) => read_Mux_In(116), read_Mux_In(10) => read_Mux_In(117), read_Mux_In(9) => read_Mux_In(118), read_Mux_In(8) => read_Mux_In(119), read_Mux_In(7) => read_Mux_In(120), read_Mux_In(6) => read_Mux_In(121), read_Mux_In(5) => read_Mux_In(122), read_Mux_In(4) => read_Mux_In(123), read_Mux_In(3) => read_Mux_In(124), read_Mux_In(2) => read_Mux_In(125), read_Mux_In(1) => read_Mux_In(126), read_Mux_In(0) => read_Mux_In(127), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, \s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]\, \s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]\, \s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]\, \s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]\, \s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]\, \s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]\, \s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]\, \s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]\, \s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]\, \s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]\, \s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]\, \s_axi_rdata_i_reg[1]\ => \s_axi_rdata_i_reg[1]\, \s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]\, \s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]\, \s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]\, \s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]\, \s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]\, \s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]\, \s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]\, \s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]\, \s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]\, \s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]\, \s_axi_rdata_i_reg[2]\ => \s_axi_rdata_i_reg[2]\, \s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]\, \s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]\, \s_axi_rdata_i_reg[3]\ => \s_axi_rdata_i_reg[3]\, \s_axi_rdata_i_reg[4]\ => \s_axi_rdata_i_reg[4]\, \s_axi_rdata_i_reg[5]\ => \s_axi_rdata_i_reg[5]\, \s_axi_rdata_i_reg[6]\ => \s_axi_rdata_i_reg[6]\, \s_axi_rdata_i_reg[7]\ => \s_axi_rdata_i_reg[7]\, \s_axi_rdata_i_reg[8]\ => \s_axi_rdata_i_reg[8]\, \s_axi_rdata_i_reg[9]\ => \s_axi_rdata_i_reg[9]\ ); \LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => D_2, Q => read_Mux_In(96), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[21]\, Q => read_Mux_In(106), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[20]\, Q => read_Mux_In(107), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[19]\, Q => read_Mux_In(108), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[18]\, Q => read_Mux_In(109), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[17]\, Q => read_Mux_In(110), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[16]\, Q => read_Mux_In(111), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[15]\, Q => read_Mux_In(112), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[14]\, Q => read_Mux_In(113), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[13]\, Q => read_Mux_In(114), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[12]\, Q => read_Mux_In(115), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[30]\, Q => read_Mux_In(97), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[11]\, Q => read_Mux_In(116), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[10]\, Q => read_Mux_In(117), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[9]\, Q => read_Mux_In(118), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[8]\, Q => read_Mux_In(119), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[7]\, Q => read_Mux_In(120), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[6]\, Q => read_Mux_In(121), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[5]\, Q => read_Mux_In(122), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[4]\, Q => read_Mux_In(123), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[3]\, Q => read_Mux_In(124), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[2]\, Q => read_Mux_In(125), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[29]\, Q => read_Mux_In(98), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[1]\, Q => read_Mux_In(126), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[0]\, Q => read_Mux_In(127), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[28]\, Q => read_Mux_In(99), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[27]\, Q => read_Mux_In(100), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[26]\, Q => read_Mux_In(101), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[25]\, Q => read_Mux_In(102), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[24]\, Q => read_Mux_In(103), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[23]\, Q => read_Mux_In(104), R => \^inferred_gen.icount_out_reg[31]\ ); \LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => \TCSR0_GENERATE[20].TCSR0_FF_I\, D => \INFERRED_GEN.icount_out_reg[22]\, Q => read_Mux_In(105), R => \^inferred_gen.icount_out_reg[31]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control is port ( generateout0 : out STD_LOGIC; generateout1 : out STD_LOGIC; interrupt : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); \INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I_0\ : out STD_LOGIC; \TCSR1_GENERATE[23].TCSR1_FF_I_0\ : out STD_LOGIC; D_0 : out STD_LOGIC; read_done1 : out STD_LOGIC; load_Counter_Reg : out STD_LOGIC_VECTOR ( 0 to 1 ); \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[1]\ : out STD_LOGIC; \s_axi_rdata_i_reg[2]\ : out STD_LOGIC; \s_axi_rdata_i_reg[3]\ : out STD_LOGIC; \s_axi_rdata_i_reg[4]\ : out STD_LOGIC; \s_axi_rdata_i_reg[5]\ : out STD_LOGIC; \s_axi_rdata_i_reg[6]\ : out STD_LOGIC; \s_axi_rdata_i_reg[7]\ : out STD_LOGIC; \s_axi_rdata_i_reg[8]\ : out STD_LOGIC; \s_axi_rdata_i_reg[9]\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; R : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \INFERRED_GEN.icount_out_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); PWM_FF_I : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 0 to 0 ); \LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC; \INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); \INFERRED_GEN.icount_out_reg[32]\ : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[32]_0\ : in STD_LOGIC; bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 ); \LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); pair0_Select : in STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I_1\ : in STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC; counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC; pwm0 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); Bus_RNW_reg : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC; \bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); freeze : in STD_LOGIC; capturetrig0 : in STD_LOGIC; capturetrig1 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control is signal \^d_0\ : STD_LOGIC; signal GenerateOut00 : STD_LOGIC; signal GenerateOut10 : STD_LOGIC; signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC; signal Interrupt0 : STD_LOGIC; signal \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\ : STD_LOGIC; signal \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\ : STD_LOGIC; signal Load_Counter_Reg028_out : STD_LOGIC; signal Load_Counter_Reg030_out : STD_LOGIC; signal Load_Counter_Reg031_out : STD_LOGIC; signal \Load_Counter_Reg0__0\ : STD_LOGIC; signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal READ_DONE0_I_i_3_n_0 : STD_LOGIC; signal READ_DONE1_I_i_1_n_0 : STD_LOGIC; signal READ_DONE1_I_i_3_n_0 : STD_LOGIC; signal R_0 : STD_LOGIC; signal \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\ : STD_LOGIC; signal \^tcsr0_generate[24].tcsr0_ff_i_0\ : STD_LOGIC; signal \TCSR0_Set2__0\ : STD_LOGIC; signal \^tcsr1_generate[23].tcsr1_ff_i_0\ : STD_LOGIC; signal \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\ : STD_LOGIC; signal captureTrig0_d : STD_LOGIC; signal captureTrig0_d0 : STD_LOGIC; signal captureTrig0_d2 : STD_LOGIC; signal captureTrig0_pulse_d1 : STD_LOGIC; signal captureTrig0_pulse_d1_i_1_n_0 : STD_LOGIC; signal captureTrig0_pulse_d2 : STD_LOGIC; signal captureTrig1_d : STD_LOGIC; signal captureTrig1_d0 : STD_LOGIC; signal captureTrig1_d2 : STD_LOGIC; signal counter_TC_Reg2 : STD_LOGIC; signal generateOutPre0 : STD_LOGIC; signal generateOutPre1 : STD_LOGIC; signal \^generateout0\ : STD_LOGIC; signal \^generateout1\ : STD_LOGIC; signal p_33_in : STD_LOGIC; signal p_38_in : STD_LOGIC; signal read_Mux_In : STD_LOGIC_VECTOR ( 21 to 63 ); signal \^read_done1\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of GenerateOut0_i_2 : label is "soft_lutpair50"; attribute SOFT_HLUTNM of GenerateOut1_i_1 : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4__0\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_3\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_5\ : label is "soft_lutpair53"; attribute BOX_TYPE : string; attribute BOX_TYPE of READ_DONE0_I : label is "PRIMITIVE"; attribute IS_CE_INVERTED : string; attribute IS_CE_INVERTED of READ_DONE0_I : label is "1'b0"; attribute IS_S_INVERTED : string; attribute IS_S_INVERTED of READ_DONE0_I : label is "1'b0"; attribute BOX_TYPE of READ_DONE1_I : label is "PRIMITIVE"; attribute IS_CE_INVERTED of READ_DONE1_I : label is "1'b0"; attribute IS_S_INVERTED of READ_DONE1_I : label is "1'b0"; attribute SOFT_HLUTNM of READ_DONE1_I_i_3 : label is "soft_lutpair52"; attribute BOX_TYPE of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0"; attribute BOX_TYPE of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "PRIMITIVE"; attribute IS_CE_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0"; attribute IS_S_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0"; attribute SOFT_HLUTNM of captureTrig0_pulse_d1_i_1 : label is "soft_lutpair52"; begin D_0 <= \^d_0\; \INFERRED_GEN.icount_out_reg[0]\ <= \^inferred_gen.icount_out_reg[0]\; Q(1 downto 0) <= \^q\(1 downto 0); \TCSR0_GENERATE[24].TCSR0_FF_I_0\ <= \^tcsr0_generate[24].tcsr0_ff_i_0\; \TCSR1_GENERATE[23].TCSR1_FF_I_0\ <= \^tcsr1_generate[23].tcsr1_ff_i_0\; generateout0 <= \^generateout0\; generateout1 <= \^generateout1\; read_done1 <= \^read_done1\; \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(10), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(21), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(53), O => \s_axi_rdata_i_reg[10]\ ); \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(9), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(22), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(54), O => \s_axi_rdata_i_reg[9]\ ); \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(8), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(23), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(55), O => \s_axi_rdata_i_reg[8]\ ); \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(7), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => \^tcsr0_generate[24].tcsr0_ff_i_0\, I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => \^tcsr1_generate[23].tcsr1_ff_i_0\, O => \s_axi_rdata_i_reg[7]\ ); \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(6), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(25), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(57), O => \s_axi_rdata_i_reg[6]\ ); \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(5), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(26), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(58), O => \s_axi_rdata_i_reg[5]\ ); \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(4), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(27), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(59), O => \s_axi_rdata_i_reg[4]\ ); \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(3), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(28), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(60), O => \s_axi_rdata_i_reg[3]\ ); \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(2), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(29), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(61), O => \s_axi_rdata_i_reg[2]\ ); \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(1), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(30), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(62), O => \s_axi_rdata_i_reg[1]\ ); \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000077707770777" ) port map ( I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(0), I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, I3 => read_Mux_In(31), I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I5 => read_Mux_In(63), O => \s_axi_rdata_i_reg[0]\ ); GenerateOut0_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"B800" ) port map ( I0 => generateOutPre1, I1 => \^inferred_gen.icount_out_reg[0]\, I2 => generateOutPre0, I3 => read_Mux_In(29), O => GenerateOut00 ); GenerateOut0_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => GenerateOut00, Q => \^generateout0\, R => SR(0) ); GenerateOut1_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"8F808080" ) port map ( I0 => generateOutPre0, I1 => read_Mux_In(29), I2 => \^inferred_gen.icount_out_reg[0]\, I3 => read_Mux_In(61), I4 => generateOutPre1, O => GenerateOut10 ); GenerateOut1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => GenerateOut10, Q => \^generateout1\, R => SR(0) ); \INFERRED_GEN.icount_out[31]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"AAFEAAAA" ) port map ( I0 => read_Mux_In(26), I1 => read_Mux_In(22), I2 => read_Mux_In(27), I3 => read_Mux_In(31), I4 => counter_TC(0), O => Load_Counter_Reg030_out ); \INFERRED_GEN.icount_out[31]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFAAEAAAAAAAEA" ) port map ( I0 => read_Mux_In(58), I1 => counter_TC(1), I2 => read_Mux_In(59), I3 => read_Mux_In(63), I4 => read_Mux_In(54), I5 => counter_TC(0), O => \Load_Counter_Reg0__0\ ); \INFERRED_GEN.icount_out[31]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FF40" ) port map ( I0 => read_Mux_In(31), I1 => counter_TC(1), I2 => read_Mux_In(27), I3 => read_Mux_In(58), O => Load_Counter_Reg028_out ); \INFERRED_GEN.icount_out[31]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FF40" ) port map ( I0 => read_Mux_In(31), I1 => counter_TC(1), I2 => read_Mux_In(27), I3 => read_Mux_In(26), O => Load_Counter_Reg031_out ); \INFERRED_GEN.icount_out[31]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"FF40FFFFFF400000" ) port map ( I0 => read_Mux_In(31), I1 => counter_TC(1), I2 => read_Mux_In(27), I3 => read_Mux_In(58), I4 => \^inferred_gen.icount_out_reg[0]\, I5 => \Load_Counter_Reg0__0\, O => load_Counter_Reg(1) ); \INFERRED_GEN.icount_out[31]_i_7__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF40FFFFFF400000" ) port map ( I0 => read_Mux_In(31), I1 => counter_TC(1), I2 => read_Mux_In(27), I3 => read_Mux_In(26), I4 => \^inferred_gen.icount_out_reg[0]\, I5 => Load_Counter_Reg030_out, O => load_Counter_Reg(0) ); INPUT_DOUBLE_REGS: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync port map ( captureTrig0_d0 => captureTrig0_d0, capturetrig0 => capturetrig0, read_Mux_In(0) => read_Mux_In(28), s_axi_aclk => s_axi_aclk ); INPUT_DOUBLE_REGS2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 port map ( captureTrig1_d0 => captureTrig1_d0, capturetrig1 => capturetrig1, read_Mux_In(0) => read_Mux_In(60), s_axi_aclk => s_axi_aclk ); INPUT_DOUBLE_REGS3: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 port map ( E(0) => E(0), \INFERRED_GEN.icount_out_reg[0]\(0) => \INFERRED_GEN.icount_out_reg[0]_0\(0), \INFERRED_GEN.icount_out_reg[1]\(1 downto 0) => \INFERRED_GEN.icount_out_reg[1]\(1 downto 0), \INFERRED_GEN.icount_out_reg[4]\(0) => \INFERRED_GEN.icount_out_reg[4]\(0), Load_Counter_Reg028_out => Load_Counter_Reg028_out, Load_Counter_Reg030_out => Load_Counter_Reg030_out, Load_Counter_Reg031_out => Load_Counter_Reg031_out, \Load_Counter_Reg0__0\ => \Load_Counter_Reg0__0\, S(0) => S(0), \TCSR0_GENERATE[20].TCSR0_FF_I\ => \^inferred_gen.icount_out_reg[0]\, \TCSR0_GENERATE[24].TCSR0_FF_I\ => \^tcsr0_generate[24].tcsr0_ff_i_0\, \TCSR1_GENERATE[24].TCSR1_FF_I\ => \^tcsr1_generate[23].tcsr1_ff_i_0\, counter_TC(0 to 1) => counter_TC(0 to 1), freeze => freeze, generateOutPre0 => generateOutPre0, read_Mux_In(7) => read_Mux_In(22), read_Mux_In(6) => read_Mux_In(27), read_Mux_In(5) => read_Mux_In(30), read_Mux_In(4) => read_Mux_In(31), read_Mux_In(3) => read_Mux_In(54), read_Mux_In(2) => read_Mux_In(59), read_Mux_In(1) => read_Mux_In(62), read_Mux_In(0) => read_Mux_In(63), s_axi_aclk => s_axi_aclk ); Interrupt_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F888" ) port map ( I0 => read_Mux_In(25), I1 => read_Mux_In(23), I2 => read_Mux_In(57), I3 => read_Mux_In(55), O => Interrupt0 ); Interrupt_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => Interrupt0, Q => interrupt, R => SR(0) ); \LOAD_REG_GEN[0].LOAD_REG_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"E000FFFFE000E000" ) port map ( I0 => read_Mux_In(27), I1 => \^d_0\, I2 => R_0, I3 => read_Mux_In(31), I4 => Bus_RNW_reg, I5 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, O => \LOAD_REG_GEN[24].LOAD_REG_I\ ); \LOAD_REG_GEN[0].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFF8080808" ) port map ( I0 => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\, I1 => p_38_in, I2 => \^inferred_gen.icount_out_reg[0]\, I3 => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\, I4 => p_33_in, I5 => \bus2ip_wrce__0\(0), O => \LOAD_REG_GEN[24].LOAD_REG_I_0\ ); \LOAD_REG_GEN[0].LOAD_REG_I_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => read_Mux_In(59), I1 => \^read_done1\, O => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\ ); \LOAD_REG_GEN[0].LOAD_REG_I_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"F4F4F40400000000" ) port map ( I0 => captureTrig1_d2, I1 => captureTrig1_d, I2 => \^inferred_gen.icount_out_reg[0]\, I3 => READ_DONE1_I_i_3_n_0, I4 => READ_DONE0_I_i_3_n_0, I5 => read_Mux_In(63), O => p_38_in ); \LOAD_REG_GEN[0].LOAD_REG_I_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => read_Mux_In(27), I1 => \^read_done1\, O => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\ ); \LOAD_REG_GEN[0].LOAD_REG_I_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"F4F4F40400000000" ) port map ( I0 => captureTrig1_d2, I1 => captureTrig1_d, I2 => \^inferred_gen.icount_out_reg[0]\, I3 => READ_DONE1_I_i_3_n_0, I4 => READ_DONE0_I_i_3_n_0, I5 => read_Mux_In(31), O => p_33_in ); PWM_FF_I_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"AB" ) port map ( I0 => \^generateout1\, I1 => read_Mux_In(22), I2 => read_Mux_In(54), O => R ); PWM_FF_I_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^generateout0\, I1 => pwm0, O => PWM_FF_I ); READ_DONE0_I: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\, Q => \^d_0\, R => R_0 ); READ_DONE0_I_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AA00AA00ABFFAA00" ) port map ( I0 => READ_DONE0_I_i_3_n_0, I1 => \^q\(1), I2 => counter_TC(0), I3 => \^inferred_gen.icount_out_reg[0]\, I4 => captureTrig0_d, I5 => captureTrig0_d2, O => R_0 ); READ_DONE0_I_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"A8" ) port map ( I0 => counter_TC_Reg2, I1 => captureTrig0_pulse_d2, I2 => captureTrig0_pulse_d1, O => READ_DONE0_I_i_3_n_0 ); READ_DONE1_I: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, Q => \^read_done1\, R => READ_DONE1_I_i_1_n_0 ); READ_DONE1_I_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"E0E0EFE0" ) port map ( I0 => READ_DONE0_I_i_3_n_0, I1 => READ_DONE1_I_i_3_n_0, I2 => \^inferred_gen.icount_out_reg[0]\, I3 => captureTrig1_d, I4 => captureTrig1_d2, O => READ_DONE1_I_i_1_n_0 ); READ_DONE1_I_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => captureTrig0_d2, I1 => captureTrig0_d, I2 => counter_TC(0), I3 => \^q\(1), O => READ_DONE1_I_i_3_n_0 ); \TCSR0_GENERATE[20].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(9), Q => \^inferred_gen.icount_out_reg[0]\, R => SR(0) ); \TCSR0_GENERATE[21].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => pair0_Select, D => s_axi_wdata(8), Q => read_Mux_In(21), R => SR(0) ); \TCSR0_GENERATE[22].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(7), Q => read_Mux_In(22), R => SR(0) ); \TCSR0_GENERATE[23].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\, Q => read_Mux_In(23), R => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ ); \TCSR0_GENERATE[23].TCSR0_FF_I_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFF3F2F0F2" ) port map ( I0 => generateOutPre0, I1 => read_Mux_In(31), I2 => \TCSR0_Set2__0\, I3 => \^inferred_gen.icount_out_reg[0]\, I4 => generateOutPre1, I5 => read_Mux_In(23), O => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\ ); \TCSR0_GENERATE[23].TCSR0_FF_I_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"A8AAA80000000000" ) port map ( I0 => read_Mux_In(31), I1 => READ_DONE0_I_i_3_n_0, I2 => READ_DONE1_I_i_3_n_0, I3 => \^inferred_gen.icount_out_reg[0]\, I4 => captureTrig0_pulse_d1_i_1_n_0, I5 => \^tcsr0_generate[24].tcsr0_ff_i_0\, O => \TCSR0_Set2__0\ ); \TCSR0_GENERATE[24].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => pair0_Select, D => \TCSR0_GENERATE[24].TCSR0_FF_I_1\, Q => \^tcsr0_generate[24].tcsr0_ff_i_0\, R => SR(0) ); \TCSR0_GENERATE[25].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(6), Q => read_Mux_In(25), R => SR(0) ); \TCSR0_GENERATE[26].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(5), Q => read_Mux_In(26), R => SR(0) ); \TCSR0_GENERATE[27].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(4), Q => read_Mux_In(27), R => SR(0) ); \TCSR0_GENERATE[28].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(3), Q => read_Mux_In(28), R => SR(0) ); \TCSR0_GENERATE[29].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(2), Q => read_Mux_In(29), R => SR(0) ); \TCSR0_GENERATE[30].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(1), Q => read_Mux_In(30), R => SR(0) ); \TCSR0_GENERATE[31].TCSR0_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(1), D => s_axi_wdata(0), Q => read_Mux_In(31), R => SR(0) ); \TCSR1_GENERATE[21].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => pair0_Select, D => s_axi_wdata(8), Q => read_Mux_In(53), R => SR(0) ); \TCSR1_GENERATE[22].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(7), Q => read_Mux_In(54), R => SR(0) ); \TCSR1_GENERATE[23].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\, Q => read_Mux_In(55), R => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ ); \TCSR1_GENERATE[23].TCSR1_FF_I_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00008F80" ) port map ( I0 => \^tcsr1_generate[23].tcsr1_ff_i_0\, I1 => READ_DONE1_I_i_1_n_0, I2 => read_Mux_In(63), I3 => generateOutPre1, I4 => \^inferred_gen.icount_out_reg[0]\, I5 => read_Mux_In(55), O => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\ ); \TCSR1_GENERATE[24].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => pair0_Select, D => \TCSR1_GENERATE[24].TCSR1_FF_I_0\, Q => \^tcsr1_generate[23].tcsr1_ff_i_0\, R => SR(0) ); \TCSR1_GENERATE[25].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(6), Q => read_Mux_In(57), R => SR(0) ); \TCSR1_GENERATE[26].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(5), Q => read_Mux_In(58), R => SR(0) ); \TCSR1_GENERATE[27].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(4), Q => read_Mux_In(59), R => SR(0) ); \TCSR1_GENERATE[28].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(3), Q => read_Mux_In(60), R => SR(0) ); \TCSR1_GENERATE[29].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(2), Q => read_Mux_In(61), R => SR(0) ); \TCSR1_GENERATE[30].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(1), Q => read_Mux_In(62), R => SR(0) ); \TCSR1_GENERATE[31].TCSR1_FF_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bus2ip_wrce(0), D => s_axi_wdata(0), Q => read_Mux_In(63), R => SR(0) ); captureTrig0_d2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig0_d, Q => captureTrig0_d2, R => SR(0) ); captureTrig0_d_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig0_d0, Q => captureTrig0_d, R => SR(0) ); captureTrig0_pulse_d1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => captureTrig0_d, I1 => captureTrig0_d2, O => captureTrig0_pulse_d1_i_1_n_0 ); captureTrig0_pulse_d1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig0_pulse_d1_i_1_n_0, Q => captureTrig0_pulse_d1, R => SR(0) ); captureTrig0_pulse_d2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig0_pulse_d1, Q => captureTrig0_pulse_d2, R => SR(0) ); captureTrig1_d2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig1_d, Q => captureTrig1_d2, R => SR(0) ); captureTrig1_d_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => captureTrig1_d0, Q => captureTrig1_d, R => SR(0) ); counter_TC_Reg2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^q\(1), Q => counter_TC_Reg2, R => SR(0) ); \counter_TC_Reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => counter_TC(0), Q => \^q\(1), R => SR(0) ); \counter_TC_Reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => counter_TC(1), Q => \^q\(0), R => SR(0) ); generateOutPre0_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \INFERRED_GEN.icount_out_reg[32]_0\, Q => generateOutPre0, R => SR(0) ); generateOutPre1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \INFERRED_GEN.icount_out_reg[32]\, Q => generateOutPre1, R => SR(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is port ( \LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; \s_axi_rdata_i_reg[12]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC; pair0_Select : out STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; \s_axi_rdata_i_reg[11]_0\ : out STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC; \LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC; D_0 : out STD_LOGIC; \bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 ); \LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC; D_1 : out STD_LOGIC; s_axi_rvalid_i_reg_0 : out STD_LOGIC; s_axi_rvalid_i_reg_1 : out STD_LOGIC; s_axi_rvalid_i_reg_2 : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC; \TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]_1\ : out STD_LOGIC; READ_DONE0_I : out STD_LOGIC; READ_DONE1_I : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); bus2ip_reset : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 ); s_axi_aresetn : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); D_2 : in STD_LOGIC; read_done1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal I_DECODER_n_100 : STD_LOGIC; signal I_DECODER_n_101 : STD_LOGIC; signal I_DECODER_n_25 : STD_LOGIC; signal I_DECODER_n_26 : STD_LOGIC; signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 2 ); signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC; signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC; signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC; signal \bus2ip_addr_i[4]_i_2_n_0\ : STD_LOGIC; signal bus2ip_rnw_i : STD_LOGIC; signal bus2ip_rnw_i06_out : STD_LOGIC; signal clear : STD_LOGIC; signal is_read : STD_LOGIC; signal is_read_i_1_n_0 : STD_LOGIC; signal is_write : STD_LOGIC; signal is_write_i_1_n_0 : STD_LOGIC; signal is_write_reg_n_0 : STD_LOGIC; signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 ); signal rst : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal start2 : STD_LOGIC; signal start2_i_1_n_0 : STD_LOGIC; signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \state1__2\ : STD_LOGIC; signal \state[1]_i_3_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_2\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair14"; attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair16"; begin s_axi_bvalid <= \^s_axi_bvalid\; s_axi_rvalid <= \^s_axi_rvalid\; \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), O => plusOp(0) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), O => plusOp(1) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), O => plusOp(2) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), O => plusOp(3) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), O => plusOp(4) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => state(0), I1 => state(1), O => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5), O => plusOp(5) ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(0), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(1), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(2), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(3), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(4), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(5), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5), R => clear ); I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder port map ( D(1) => I_DECODER_n_25, D(0) => I_DECODER_n_26, D_0 => D_0, D_1 => D_1, D_2 => D_2, \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5 downto 0), \LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\, \LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\, \LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\, \LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\, \LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\, \LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\, \LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\, \LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\, \LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\, \LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\, \LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\, \LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\, \LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\, \LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\, \LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\, \LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\, \LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\, \LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\, \LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\, \LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\, \LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\, \LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\, \LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\, \LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\, \LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\, \LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\, \LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\, \LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\, \LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\, \LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\, \LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\, \LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\, \LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\, \LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\, \LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\, \LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\, \LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\, \LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\, \LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\, \LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\, \LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\, \LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\, \LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\, \LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\, \LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\, \LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\, \LOAD_REG_GEN[31].LOAD_REG_I\ => \LOAD_REG_GEN[31].LOAD_REG_I\, \LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\, \LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_1\, \LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\, \LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\, \LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\, \LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\, \LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\, \LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\, \LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\, \LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\, \LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\, \LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\, \LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\, \LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\, \LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\, \LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\, Q => start2, READ_DONE0_I => READ_DONE0_I, READ_DONE1_I => READ_DONE1_I, \TCSR0_GENERATE[23].TCSR0_FF_I\ => \TCSR0_GENERATE[23].TCSR0_FF_I\, \TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I_0\, \TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\, \TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\, \TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\, \bus2ip_addr_i_reg[4]\(2) => bus2ip_addr(0), \bus2ip_addr_i_reg[4]\(1) => bus2ip_addr(1), \bus2ip_addr_i_reg[4]\(0) => bus2ip_addr(2), bus2ip_rnw_i => bus2ip_rnw_i, bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0), is_read => is_read, is_write_reg => is_write_reg_n_0, pair0_Select => pair0_Select, read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0), read_done1 => read_done1, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_arvalid_0 => \state[1]_i_3_n_0\, s_axi_bready => s_axi_bready, s_axi_bvalid_i_reg => I_DECODER_n_101, s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\, \s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]_0\, \s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]_1\, \s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]_0\, \s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]_0\, \s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]_0\, \s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]_0\, \s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]_0\, \s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]_0\, \s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]_0\, \s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]_0\, \s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]_0\, \s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]_0\, \s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]_0\, \s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]_0\, \s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]_0\, \s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]_0\, \s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]_0\, \s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]_0\, \s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]_0\, \s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]_0\, \s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]_0\, \s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]_0\, \s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]_0\, \s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]_0\, s_axi_rready => s_axi_rready, s_axi_rvalid_i_reg => s_axi_rvalid_i_reg_0, s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg_1, s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_2, s_axi_rvalid_i_reg_2 => I_DECODER_n_100, s_axi_rvalid_i_reg_3 => \^s_axi_rvalid\, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => s_axi_wready, \state1__2\ => \state1__2\, \state_reg[1]\(1 downto 0) => state(1 downto 0) ); \bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFF0200" ) port map ( I0 => s_axi_araddr(0), I1 => state(0), I2 => state(1), I3 => s_axi_arvalid, I4 => s_axi_awaddr(0), O => \bus2ip_addr_i[2]_i_1_n_0\ ); \bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFF0200" ) port map ( I0 => s_axi_araddr(1), I1 => state(0), I2 => state(1), I3 => s_axi_arvalid, I4 => s_axi_awaddr(1), O => \bus2ip_addr_i[3]_i_1_n_0\ ); \bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000000EA" ) port map ( I0 => s_axi_arvalid, I1 => s_axi_awvalid, I2 => s_axi_wvalid, I3 => state(1), I4 => state(0), O => \bus2ip_addr_i[4]_i_1_n_0\ ); \bus2ip_addr_i[4]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFF0200" ) port map ( I0 => s_axi_araddr(2), I1 => state(0), I2 => state(1), I3 => s_axi_arvalid, I4 => s_axi_awaddr(2), O => \bus2ip_addr_i[4]_i_2_n_0\ ); \bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[4]_i_1_n_0\, D => \bus2ip_addr_i[2]_i_1_n_0\, Q => bus2ip_addr(2), R => rst ); \bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[4]_i_1_n_0\, D => \bus2ip_addr_i[3]_i_1_n_0\, Q => bus2ip_addr(1), R => rst ); \bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[4]_i_1_n_0\, D => \bus2ip_addr_i[4]_i_2_n_0\, Q => bus2ip_addr(0), R => rst ); bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"10" ) port map ( I0 => state(0), I1 => state(1), I2 => s_axi_arvalid, O => bus2ip_rnw_i06_out ); bus2ip_rnw_i_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[4]_i_1_n_0\, D => bus2ip_rnw_i06_out, Q => bus2ip_rnw_i, R => rst ); is_read_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"3FFA000A" ) port map ( I0 => s_axi_arvalid, I1 => \state1__2\, I2 => state(0), I3 => state(1), I4 => is_read, O => is_read_i_1_n_0 ); is_read_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => is_read_i_1_n_0, Q => is_read, R => rst ); is_write_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0040FFFF00400000" ) port map ( I0 => s_axi_arvalid, I1 => s_axi_awvalid, I2 => s_axi_wvalid, I3 => state(1), I4 => is_write, I5 => is_write_reg_n_0, O => is_write_i_1_n_0 ); is_write_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F88800000000FFFF" ) port map ( I0 => \^s_axi_rvalid\, I1 => s_axi_rready, I2 => \^s_axi_bvalid\, I3 => s_axi_bready, I4 => state(0), I5 => state(1), O => is_write ); is_write_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => is_write_i_1_n_0, Q => is_write_reg_n_0, R => rst ); rst_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => bus2ip_reset, Q => rst, R => '0' ); s_axi_bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => I_DECODER_n_101, Q => \^s_axi_bvalid\, R => rst ); \s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => state(0), I1 => state(1), O => \s_axi_rdata_i[31]_i_1_n_0\ ); \s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(0), Q => s_axi_rdata(0), R => rst ); \s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(10), Q => s_axi_rdata(10), R => rst ); \s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(11), Q => s_axi_rdata(11), R => rst ); \s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(12), Q => s_axi_rdata(12), R => rst ); \s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(13), Q => s_axi_rdata(13), R => rst ); \s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(14), Q => s_axi_rdata(14), R => rst ); \s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(15), Q => s_axi_rdata(15), R => rst ); \s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(16), Q => s_axi_rdata(16), R => rst ); \s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(17), Q => s_axi_rdata(17), R => rst ); \s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(18), Q => s_axi_rdata(18), R => rst ); \s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(19), Q => s_axi_rdata(19), R => rst ); \s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(1), Q => s_axi_rdata(1), R => rst ); \s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(20), Q => s_axi_rdata(20), R => rst ); \s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(21), Q => s_axi_rdata(21), R => rst ); \s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(22), Q => s_axi_rdata(22), R => rst ); \s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(23), Q => s_axi_rdata(23), R => rst ); \s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(24), Q => s_axi_rdata(24), R => rst ); \s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(25), Q => s_axi_rdata(25), R => rst ); \s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(26), Q => s_axi_rdata(26), R => rst ); \s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(27), Q => s_axi_rdata(27), R => rst ); \s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(28), Q => s_axi_rdata(28), R => rst ); \s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(29), Q => s_axi_rdata(29), R => rst ); \s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(2), Q => s_axi_rdata(2), R => rst ); \s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(30), Q => s_axi_rdata(30), R => rst ); \s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(31), Q => s_axi_rdata(31), R => rst ); \s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(3), Q => s_axi_rdata(3), R => rst ); \s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(4), Q => s_axi_rdata(4), R => rst ); \s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(5), Q => s_axi_rdata(5), R => rst ); \s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(6), Q => s_axi_rdata(6), R => rst ); \s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(7), Q => s_axi_rdata(7), R => rst ); \s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(8), Q => s_axi_rdata(8), R => rst ); \s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[31]_i_1_n_0\, D => D(9), Q => s_axi_rdata(9), R => rst ); s_axi_rvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => I_DECODER_n_100, Q => \^s_axi_rvalid\, R => rst ); start2_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"000000F8" ) port map ( I0 => s_axi_awvalid, I1 => s_axi_wvalid, I2 => s_axi_arvalid, I3 => state(1), I4 => state(0), O => start2_i_1_n_0 ); start2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => start2_i_1_n_0, Q => start2, R => rst ); \state[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"F888" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \state1__2\ ); \state[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => s_axi_wvalid, I1 => s_axi_awvalid, I2 => s_axi_arvalid, O => \state[1]_i_3_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => I_DECODER_n_26, Q => state(0), R => rst ); \state_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => I_DECODER_n_25, Q => state(1), R => rst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core is port ( D : out STD_LOGIC_VECTOR ( 31 downto 0 ); \INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 87 downto 0 ); bus2ip_reset : out STD_LOGIC; generateout0 : out STD_LOGIC; generateout1 : out STD_LOGIC; interrupt : out STD_LOGIC; D_0 : out STD_LOGIC; read_done1 : out STD_LOGIC; pwm0 : out STD_LOGIC; Bus_RNW_reg_reg : in STD_LOGIC; Bus_RNW_reg_reg_0 : in STD_LOGIC; Bus_RNW_reg_reg_1 : in STD_LOGIC; Bus_RNW_reg_reg_2 : in STD_LOGIC; Bus_RNW_reg_reg_3 : in STD_LOGIC; Bus_RNW_reg_reg_4 : in STD_LOGIC; Bus_RNW_reg_reg_5 : in STD_LOGIC; Bus_RNW_reg_reg_6 : in STD_LOGIC; Bus_RNW_reg_reg_7 : in STD_LOGIC; Bus_RNW_reg_reg_8 : in STD_LOGIC; Bus_RNW_reg_reg_9 : in STD_LOGIC; Bus_RNW_reg_reg_10 : in STD_LOGIC; Bus_RNW_reg_reg_11 : in STD_LOGIC; Bus_RNW_reg_reg_12 : in STD_LOGIC; Bus_RNW_reg_reg_13 : in STD_LOGIC; Bus_RNW_reg_reg_14 : in STD_LOGIC; Bus_RNW_reg_reg_15 : in STD_LOGIC; Bus_RNW_reg_reg_16 : in STD_LOGIC; Bus_RNW_reg_reg_17 : in STD_LOGIC; Bus_RNW_reg_reg_18 : in STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC; D_1 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC; D_2 : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC; \INFERRED_GEN.icount_out_reg[0]_0\ : in STD_LOGIC; bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 ); pair0_Select : in STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC; Bus_RNW_reg : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC; \bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); freeze : in STD_LOGIC; capturetrig0 : in STD_LOGIC; capturetrig1 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core is signal COUNTER_0_I_n_64 : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_33\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_34\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_35\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_36\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_37\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_38\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_39\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_40\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_41\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_42\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_43\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_44\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_45\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_46\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_47\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_48\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_49\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_50\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_51\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_52\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_53\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_54\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_55\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_56\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_57\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_58\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_59\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_60\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_61\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_62\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_63\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_64\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I_n_65\ : STD_LOGIC; signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC_VECTOR ( 87 downto 0 ); signal R : STD_LOGIC; signal TIMER_CONTROL_I_n_12 : STD_LOGIC; signal TIMER_CONTROL_I_n_13 : STD_LOGIC; signal TIMER_CONTROL_I_n_14 : STD_LOGIC; signal TIMER_CONTROL_I_n_15 : STD_LOGIC; signal TIMER_CONTROL_I_n_16 : STD_LOGIC; signal TIMER_CONTROL_I_n_17 : STD_LOGIC; signal TIMER_CONTROL_I_n_18 : STD_LOGIC; signal TIMER_CONTROL_I_n_19 : STD_LOGIC; signal TIMER_CONTROL_I_n_20 : STD_LOGIC; signal TIMER_CONTROL_I_n_21 : STD_LOGIC; signal TIMER_CONTROL_I_n_22 : STD_LOGIC; signal TIMER_CONTROL_I_n_24 : STD_LOGIC; signal TIMER_CONTROL_I_n_25 : STD_LOGIC; signal TIMER_CONTROL_I_n_26 : STD_LOGIC; signal TIMER_CONTROL_I_n_27 : STD_LOGIC; signal TIMER_CONTROL_I_n_28 : STD_LOGIC; signal TIMER_CONTROL_I_n_29 : STD_LOGIC; signal TIMER_CONTROL_I_n_3 : STD_LOGIC; signal TIMER_CONTROL_I_n_30 : STD_LOGIC; signal TIMER_CONTROL_I_n_4 : STD_LOGIC; signal \^bus2ip_reset\ : STD_LOGIC; signal counter_TC : STD_LOGIC_VECTOR ( 0 to 1 ); signal load_Counter_Reg : STD_LOGIC_VECTOR ( 0 to 1 ); signal \^pwm0\ : STD_LOGIC; signal read_Mux_In : STD_LOGIC_VECTOR ( 85 to 95 ); attribute BOX_TYPE : string; attribute BOX_TYPE of PWM_FF_I : label is "PRIMITIVE"; attribute IS_S_INVERTED : string; attribute IS_S_INVERTED of PWM_FF_I : label is "1'b0"; begin \INFERRED_GEN.icount_out_reg[0]\(87 downto 0) <= \^inferred_gen.icount_out_reg[0]\(87 downto 0); bus2ip_reset <= \^bus2ip_reset\; pwm0 <= \^pwm0\; COUNTER_0_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module port map ( D_1 => D_1, E(0) => TIMER_CONTROL_I_n_24, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\, \INFERRED_GEN.icount_out_reg[31]\(52 downto 0) => \^inferred_gen.icount_out_reg[0]\(84 downto 32), Q(0) => TIMER_CONTROL_I_n_3, S(0) => TIMER_CONTROL_I_n_27, \TCSR0_GENERATE[27].TCSR0_FF_I\ => TIMER_CONTROL_I_n_28, counter_TC(0) => counter_TC(0), generateOutPre0_reg => COUNTER_0_I_n_64, load_Counter_Reg(0) => load_Counter_Reg(0), read_Mux_In(10) => read_Mux_In(85), read_Mux_In(9) => read_Mux_In(86), read_Mux_In(8) => read_Mux_In(87), read_Mux_In(7) => read_Mux_In(88), read_Mux_In(6) => read_Mux_In(89), read_Mux_In(5) => read_Mux_In(90), read_Mux_In(4) => read_Mux_In(91), read_Mux_In(3) => read_Mux_In(92), read_Mux_In(2) => read_Mux_In(93), read_Mux_In(1) => read_Mux_In(94), read_Mux_In(0) => read_Mux_In(95), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_aresetn_0 => \^bus2ip_reset\ ); \GEN_SECOND_TIMER.COUNTER_1_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 port map ( D_2 => D_2, E(0) => TIMER_CONTROL_I_n_25, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\, \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\, \INFERRED_GEN.icount_out_reg[0]\ => \INFERRED_GEN.icount_out_reg[0]_0\, \INFERRED_GEN.icount_out_reg[10]\ => \INFERRED_GEN.icount_out_reg[10]\, \INFERRED_GEN.icount_out_reg[11]\ => \INFERRED_GEN.icount_out_reg[11]\, \INFERRED_GEN.icount_out_reg[12]\ => \INFERRED_GEN.icount_out_reg[12]\, \INFERRED_GEN.icount_out_reg[13]\ => \INFERRED_GEN.icount_out_reg[13]\, \INFERRED_GEN.icount_out_reg[14]\ => \INFERRED_GEN.icount_out_reg[14]\, \INFERRED_GEN.icount_out_reg[15]\ => \INFERRED_GEN.icount_out_reg[15]\, \INFERRED_GEN.icount_out_reg[16]\ => \INFERRED_GEN.icount_out_reg[16]\, \INFERRED_GEN.icount_out_reg[17]\ => \INFERRED_GEN.icount_out_reg[17]\, \INFERRED_GEN.icount_out_reg[18]\ => \INFERRED_GEN.icount_out_reg[18]\, \INFERRED_GEN.icount_out_reg[19]\ => \INFERRED_GEN.icount_out_reg[19]\, \INFERRED_GEN.icount_out_reg[1]\ => \INFERRED_GEN.icount_out_reg[1]\, \INFERRED_GEN.icount_out_reg[20]\ => \INFERRED_GEN.icount_out_reg[20]\, \INFERRED_GEN.icount_out_reg[21]\ => \INFERRED_GEN.icount_out_reg[21]\, \INFERRED_GEN.icount_out_reg[22]\ => \INFERRED_GEN.icount_out_reg[22]\, \INFERRED_GEN.icount_out_reg[23]\ => \INFERRED_GEN.icount_out_reg[23]\, \INFERRED_GEN.icount_out_reg[24]\ => \INFERRED_GEN.icount_out_reg[24]\, \INFERRED_GEN.icount_out_reg[25]\ => \INFERRED_GEN.icount_out_reg[25]\, \INFERRED_GEN.icount_out_reg[26]\ => \INFERRED_GEN.icount_out_reg[26]\, \INFERRED_GEN.icount_out_reg[27]\ => \INFERRED_GEN.icount_out_reg[27]\, \INFERRED_GEN.icount_out_reg[28]\ => \INFERRED_GEN.icount_out_reg[28]\, \INFERRED_GEN.icount_out_reg[29]\ => \INFERRED_GEN.icount_out_reg[29]\, \INFERRED_GEN.icount_out_reg[2]\ => \INFERRED_GEN.icount_out_reg[2]\, \INFERRED_GEN.icount_out_reg[30]\ => \INFERRED_GEN.icount_out_reg[30]\, \INFERRED_GEN.icount_out_reg[31]\ => \^bus2ip_reset\, \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(63 downto 32), \INFERRED_GEN.icount_out_reg[3]\ => \INFERRED_GEN.icount_out_reg[3]\, \INFERRED_GEN.icount_out_reg[4]\ => \INFERRED_GEN.icount_out_reg[4]\, \INFERRED_GEN.icount_out_reg[5]\ => \INFERRED_GEN.icount_out_reg[5]\, \INFERRED_GEN.icount_out_reg[6]\ => \INFERRED_GEN.icount_out_reg[6]\, \INFERRED_GEN.icount_out_reg[7]\ => \INFERRED_GEN.icount_out_reg[7]\, \INFERRED_GEN.icount_out_reg[8]\ => \INFERRED_GEN.icount_out_reg[8]\, \INFERRED_GEN.icount_out_reg[9]\ => \INFERRED_GEN.icount_out_reg[9]\, Q(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(31 downto 0), S(0) => TIMER_CONTROL_I_n_30, \TCSR0_GENERATE[20].TCSR0_FF_I\ => TIMER_CONTROL_I_n_29, counter_TC(0) => counter_TC(1), \counter_TC_Reg_reg[1]\(0) => TIMER_CONTROL_I_n_4, generateOutPre1_reg => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\, load_Counter_Reg(0) => load_Counter_Reg(1), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, \s_axi_rdata_i_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\, \s_axi_rdata_i_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\, \s_axi_rdata_i_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\, \s_axi_rdata_i_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\, \s_axi_rdata_i_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\, \s_axi_rdata_i_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\, \s_axi_rdata_i_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\, \s_axi_rdata_i_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\, \s_axi_rdata_i_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\, \s_axi_rdata_i_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\, \s_axi_rdata_i_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\, \s_axi_rdata_i_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\, \s_axi_rdata_i_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\, \s_axi_rdata_i_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\, \s_axi_rdata_i_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\, \s_axi_rdata_i_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\, \s_axi_rdata_i_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\, \s_axi_rdata_i_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\, \s_axi_rdata_i_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\, \s_axi_rdata_i_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\, \s_axi_rdata_i_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\, \s_axi_rdata_i_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\, \s_axi_rdata_i_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\, \s_axi_rdata_i_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\, \s_axi_rdata_i_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\, \s_axi_rdata_i_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\, \s_axi_rdata_i_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\, \s_axi_rdata_i_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\, \s_axi_rdata_i_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\, \s_axi_rdata_i_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\, \s_axi_rdata_i_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\, \s_axi_rdata_i_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\ ); PWM_FF_I: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => '1', D => TIMER_CONTROL_I_n_26, Q => \^pwm0\, R => R ); READ_MUX_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f port map ( Bus_RNW_reg_reg => Bus_RNW_reg_reg, Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg_0, Bus_RNW_reg_reg_1 => Bus_RNW_reg_reg_1, Bus_RNW_reg_reg_10 => Bus_RNW_reg_reg_10, Bus_RNW_reg_reg_11 => Bus_RNW_reg_reg_11, Bus_RNW_reg_reg_12 => Bus_RNW_reg_reg_12, Bus_RNW_reg_reg_13 => Bus_RNW_reg_reg_13, Bus_RNW_reg_reg_14 => Bus_RNW_reg_reg_14, Bus_RNW_reg_reg_15 => Bus_RNW_reg_reg_15, Bus_RNW_reg_reg_16 => Bus_RNW_reg_reg_16, Bus_RNW_reg_reg_17 => Bus_RNW_reg_reg_17, Bus_RNW_reg_reg_18 => Bus_RNW_reg_reg_18, Bus_RNW_reg_reg_2 => Bus_RNW_reg_reg_2, Bus_RNW_reg_reg_3 => Bus_RNW_reg_reg_3, Bus_RNW_reg_reg_4 => Bus_RNW_reg_reg_4, Bus_RNW_reg_reg_5 => Bus_RNW_reg_reg_5, Bus_RNW_reg_reg_6 => Bus_RNW_reg_reg_6, Bus_RNW_reg_reg_7 => Bus_RNW_reg_reg_7, Bus_RNW_reg_reg_8 => Bus_RNW_reg_reg_8, Bus_RNW_reg_reg_9 => Bus_RNW_reg_reg_9, D(31 downto 0) => D(31 downto 0), \INFERRED_GEN.icount_out_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\, \INFERRED_GEN.icount_out_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\, \INFERRED_GEN.icount_out_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\, \INFERRED_GEN.icount_out_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\, \INFERRED_GEN.icount_out_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\, \INFERRED_GEN.icount_out_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\, \INFERRED_GEN.icount_out_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\, \INFERRED_GEN.icount_out_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\, \INFERRED_GEN.icount_out_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\, \INFERRED_GEN.icount_out_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\, \INFERRED_GEN.icount_out_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\, \INFERRED_GEN.icount_out_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\, \INFERRED_GEN.icount_out_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\, \INFERRED_GEN.icount_out_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\, \INFERRED_GEN.icount_out_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\, \INFERRED_GEN.icount_out_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\, \INFERRED_GEN.icount_out_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\, \INFERRED_GEN.icount_out_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\, \INFERRED_GEN.icount_out_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\, \INFERRED_GEN.icount_out_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\, \INFERRED_GEN.icount_out_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\, \INFERRED_GEN.icount_out_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\, \INFERRED_GEN.icount_out_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\, \INFERRED_GEN.icount_out_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\, \INFERRED_GEN.icount_out_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\, \INFERRED_GEN.icount_out_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\, \INFERRED_GEN.icount_out_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\, \INFERRED_GEN.icount_out_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\, \INFERRED_GEN.icount_out_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\, \INFERRED_GEN.icount_out_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\, \INFERRED_GEN.icount_out_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\, \INFERRED_GEN.icount_out_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\, \LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\, \LOAD_REG_GEN[21].LOAD_REG_I\ => TIMER_CONTROL_I_n_22, \LOAD_REG_GEN[22].LOAD_REG_I\ => TIMER_CONTROL_I_n_21, \LOAD_REG_GEN[23].LOAD_REG_I\ => TIMER_CONTROL_I_n_20, \LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_19, \LOAD_REG_GEN[25].LOAD_REG_I\ => TIMER_CONTROL_I_n_18, \LOAD_REG_GEN[26].LOAD_REG_I\ => TIMER_CONTROL_I_n_17, \LOAD_REG_GEN[27].LOAD_REG_I\ => TIMER_CONTROL_I_n_16, \LOAD_REG_GEN[28].LOAD_REG_I\ => TIMER_CONTROL_I_n_15, \LOAD_REG_GEN[29].LOAD_REG_I\ => TIMER_CONTROL_I_n_14, \LOAD_REG_GEN[30].LOAD_REG_I\ => TIMER_CONTROL_I_n_13, \LOAD_REG_GEN[31].LOAD_REG_I\ => TIMER_CONTROL_I_n_12 ); TIMER_CONTROL_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control port map ( Bus_RNW_reg => Bus_RNW_reg, D_0 => D_0, E(0) => TIMER_CONTROL_I_n_24, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\, \INFERRED_GEN.icount_out_reg[0]\ => \^inferred_gen.icount_out_reg[0]\(87), \INFERRED_GEN.icount_out_reg[0]_0\(0) => TIMER_CONTROL_I_n_25, \INFERRED_GEN.icount_out_reg[1]\(1) => \^inferred_gen.icount_out_reg[0]\(33), \INFERRED_GEN.icount_out_reg[1]\(0) => \^inferred_gen.icount_out_reg[0]\(1), \INFERRED_GEN.icount_out_reg[32]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\, \INFERRED_GEN.icount_out_reg[32]_0\ => COUNTER_0_I_n_64, \INFERRED_GEN.icount_out_reg[4]\(0) => TIMER_CONTROL_I_n_30, \LOAD_REG_GEN[21].LOAD_REG_I\(10) => read_Mux_In(85), \LOAD_REG_GEN[21].LOAD_REG_I\(9) => read_Mux_In(86), \LOAD_REG_GEN[21].LOAD_REG_I\(8) => read_Mux_In(87), \LOAD_REG_GEN[21].LOAD_REG_I\(7) => read_Mux_In(88), \LOAD_REG_GEN[21].LOAD_REG_I\(6) => read_Mux_In(89), \LOAD_REG_GEN[21].LOAD_REG_I\(5) => read_Mux_In(90), \LOAD_REG_GEN[21].LOAD_REG_I\(4) => read_Mux_In(91), \LOAD_REG_GEN[21].LOAD_REG_I\(3) => read_Mux_In(92), \LOAD_REG_GEN[21].LOAD_REG_I\(2) => read_Mux_In(93), \LOAD_REG_GEN[21].LOAD_REG_I\(1) => read_Mux_In(94), \LOAD_REG_GEN[21].LOAD_REG_I\(0) => read_Mux_In(95), \LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_28, \LOAD_REG_GEN[24].LOAD_REG_I_0\ => TIMER_CONTROL_I_n_29, PWM_FF_I => TIMER_CONTROL_I_n_26, Q(1) => TIMER_CONTROL_I_n_3, Q(0) => TIMER_CONTROL_I_n_4, R => R, S(0) => TIMER_CONTROL_I_n_27, SR(0) => \^bus2ip_reset\, \TCSR0_GENERATE[24].TCSR0_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(86), \TCSR0_GENERATE[24].TCSR0_FF_I_1\ => \TCSR0_GENERATE[24].TCSR0_FF_I\, \TCSR1_GENERATE[23].TCSR1_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(85), \TCSR1_GENERATE[24].TCSR1_FF_I_0\ => \TCSR1_GENERATE[24].TCSR1_FF_I\, bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0), capturetrig0 => capturetrig0, capturetrig1 => capturetrig1, counter_TC(0 to 1) => counter_TC(0 to 1), freeze => freeze, generateout0 => generateout0, generateout1 => generateout1, interrupt => interrupt, load_Counter_Reg(0 to 1) => load_Counter_Reg(0 to 1), pair0_Select => pair0_Select, pwm0 => \^pwm0\, read_done1 => read_done1, s_axi_aclk => s_axi_aclk, \s_axi_rdata_i_reg[0]\ => TIMER_CONTROL_I_n_12, \s_axi_rdata_i_reg[10]\ => TIMER_CONTROL_I_n_22, \s_axi_rdata_i_reg[1]\ => TIMER_CONTROL_I_n_13, \s_axi_rdata_i_reg[2]\ => TIMER_CONTROL_I_n_14, \s_axi_rdata_i_reg[3]\ => TIMER_CONTROL_I_n_15, \s_axi_rdata_i_reg[4]\ => TIMER_CONTROL_I_n_16, \s_axi_rdata_i_reg[5]\ => TIMER_CONTROL_I_n_17, \s_axi_rdata_i_reg[6]\ => TIMER_CONTROL_I_n_18, \s_axi_rdata_i_reg[7]\ => TIMER_CONTROL_I_n_19, \s_axi_rdata_i_reg[8]\ => TIMER_CONTROL_I_n_20, \s_axi_rdata_i_reg[9]\ => TIMER_CONTROL_I_n_21, s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is port ( \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC; Bus_RNW_reg : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; \s_axi_rdata_i_reg[12]\ : out STD_LOGIC; \s_axi_rdata_i_reg[13]\ : out STD_LOGIC; \s_axi_rdata_i_reg[14]\ : out STD_LOGIC; \s_axi_rdata_i_reg[15]\ : out STD_LOGIC; \s_axi_rdata_i_reg[16]\ : out STD_LOGIC; \s_axi_rdata_i_reg[17]\ : out STD_LOGIC; \s_axi_rdata_i_reg[18]\ : out STD_LOGIC; \s_axi_rdata_i_reg[19]\ : out STD_LOGIC; \s_axi_rdata_i_reg[20]\ : out STD_LOGIC; \s_axi_rdata_i_reg[21]\ : out STD_LOGIC; \s_axi_rdata_i_reg[22]\ : out STD_LOGIC; \s_axi_rdata_i_reg[23]\ : out STD_LOGIC; \s_axi_rdata_i_reg[24]\ : out STD_LOGIC; \s_axi_rdata_i_reg[25]\ : out STD_LOGIC; \s_axi_rdata_i_reg[26]\ : out STD_LOGIC; \s_axi_rdata_i_reg[27]\ : out STD_LOGIC; \s_axi_rdata_i_reg[28]\ : out STD_LOGIC; \s_axi_rdata_i_reg[29]\ : out STD_LOGIC; \s_axi_rdata_i_reg[30]\ : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC; pair0_Select : out STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; \s_axi_rdata_i_reg[11]\ : out STD_LOGIC; \TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC; \TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC; \LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC; D_0 : out STD_LOGIC; \bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 ); \LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC; \LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC; D_1 : out STD_LOGIC; s_axi_rvalid_i_reg : out STD_LOGIC; s_axi_rvalid_i_reg_0 : out STD_LOGIC; s_axi_rvalid_i_reg_1 : out STD_LOGIC; \TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC; \TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC; \s_axi_rdata_i_reg[10]\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]\ : out STD_LOGIC; \s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC; READ_DONE0_I : out STD_LOGIC; READ_DONE1_I : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); bus2ip_reset : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 ); s_axi_aresetn : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); D_2 : in STD_LOGIC; read_done1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is begin I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment port map ( D(31 downto 0) => D(31 downto 0), D_0 => D_0, D_1 => D_1, D_2 => D_2, \LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\, \LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\, \LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\, \LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\, \LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\, \LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\, \LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\, \LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\, \LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\, \LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\, \LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\, \LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\, \LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\, \LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\, \LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\, \LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\, \LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\, \LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\, \LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\, \LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\, \LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\, \LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\, \LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\, \LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\, \LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\, \LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\, \LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\, \LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\, \LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\, \LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\, \LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\, \LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\, \LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\, \LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\, \LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\, \LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\, \LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\, \LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\, \LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\, \LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\, \LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\, \LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\, \LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\, \LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\, \LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\, \LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\, \LOAD_REG_GEN[31].LOAD_REG_I\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I\, \LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\, \LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\, \LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\, \LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\, \LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\, \LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\, \LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\, \LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\, \LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\, \LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\, \LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\, \LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\, \LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\, \LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\, \LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\, READ_DONE0_I => READ_DONE0_I, READ_DONE1_I => READ_DONE1_I, \TCSR0_GENERATE[23].TCSR0_FF_I\ => Bus_RNW_reg, \TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I\, \TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\, \TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\, \TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\, bus2ip_reset => bus2ip_reset, bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0), pair0_Select => pair0_Select, read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0), read_done1 => read_done1, s_axi_aclk => s_axi_aclk, s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), \s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]\, \s_axi_rdata_i_reg[0]_1\ => \s_axi_rdata_i_reg[0]_0\, \s_axi_rdata_i_reg[10]_0\ => \s_axi_rdata_i_reg[10]\, \s_axi_rdata_i_reg[11]_0\ => \s_axi_rdata_i_reg[11]\, \s_axi_rdata_i_reg[12]_0\ => \s_axi_rdata_i_reg[12]\, \s_axi_rdata_i_reg[13]_0\ => \s_axi_rdata_i_reg[13]\, \s_axi_rdata_i_reg[14]_0\ => \s_axi_rdata_i_reg[14]\, \s_axi_rdata_i_reg[15]_0\ => \s_axi_rdata_i_reg[15]\, \s_axi_rdata_i_reg[16]_0\ => \s_axi_rdata_i_reg[16]\, \s_axi_rdata_i_reg[17]_0\ => \s_axi_rdata_i_reg[17]\, \s_axi_rdata_i_reg[18]_0\ => \s_axi_rdata_i_reg[18]\, \s_axi_rdata_i_reg[19]_0\ => \s_axi_rdata_i_reg[19]\, \s_axi_rdata_i_reg[20]_0\ => \s_axi_rdata_i_reg[20]\, \s_axi_rdata_i_reg[21]_0\ => \s_axi_rdata_i_reg[21]\, \s_axi_rdata_i_reg[22]_0\ => \s_axi_rdata_i_reg[22]\, \s_axi_rdata_i_reg[23]_0\ => \s_axi_rdata_i_reg[23]\, \s_axi_rdata_i_reg[24]_0\ => \s_axi_rdata_i_reg[24]\, \s_axi_rdata_i_reg[25]_0\ => \s_axi_rdata_i_reg[25]\, \s_axi_rdata_i_reg[26]_0\ => \s_axi_rdata_i_reg[26]\, \s_axi_rdata_i_reg[27]_0\ => \s_axi_rdata_i_reg[27]\, \s_axi_rdata_i_reg[28]_0\ => \s_axi_rdata_i_reg[28]\, \s_axi_rdata_i_reg[29]_0\ => \s_axi_rdata_i_reg[29]\, \s_axi_rdata_i_reg[30]_0\ => \s_axi_rdata_i_reg[30]\, \s_axi_rdata_i_reg[31]_0\ => \s_axi_rdata_i_reg[31]\, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg, s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_0, s_axi_rvalid_i_reg_2 => s_axi_rvalid_i_reg_1, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => s_axi_wready, s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer is port ( capturetrig0 : in STD_LOGIC; capturetrig1 : in STD_LOGIC; generateout0 : out STD_LOGIC; generateout1 : out STD_LOGIC; pwm0 : out STD_LOGIC; interrupt : out STD_LOGIC; freeze : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC ); attribute C_COUNT_WIDTH : integer; attribute C_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 32; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "zynq"; attribute C_GEN0_ASSERT : string; attribute C_GEN0_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1"; attribute C_GEN1_ASSERT : string; attribute C_GEN1_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1"; attribute C_ONE_TIMER_ONLY : integer; attribute C_ONE_TIMER_ONLY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 5; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 32; attribute C_TRIG0_ASSERT : string; attribute C_TRIG0_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1"; attribute C_TRIG1_ASSERT : string; attribute C_TRIG1_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer is signal \<const0>\ : STD_LOGIC; signal AXI4_LITE_I_n_10 : STD_LOGIC; signal AXI4_LITE_I_n_100 : STD_LOGIC; signal AXI4_LITE_I_n_101 : STD_LOGIC; signal AXI4_LITE_I_n_102 : STD_LOGIC; signal AXI4_LITE_I_n_103 : STD_LOGIC; signal AXI4_LITE_I_n_104 : STD_LOGIC; signal AXI4_LITE_I_n_105 : STD_LOGIC; signal AXI4_LITE_I_n_106 : STD_LOGIC; signal AXI4_LITE_I_n_11 : STD_LOGIC; signal AXI4_LITE_I_n_12 : STD_LOGIC; signal AXI4_LITE_I_n_13 : STD_LOGIC; signal AXI4_LITE_I_n_14 : STD_LOGIC; signal AXI4_LITE_I_n_15 : STD_LOGIC; signal AXI4_LITE_I_n_16 : STD_LOGIC; signal AXI4_LITE_I_n_17 : STD_LOGIC; signal AXI4_LITE_I_n_18 : STD_LOGIC; signal AXI4_LITE_I_n_19 : STD_LOGIC; signal AXI4_LITE_I_n_20 : STD_LOGIC; signal AXI4_LITE_I_n_21 : STD_LOGIC; signal AXI4_LITE_I_n_22 : STD_LOGIC; signal AXI4_LITE_I_n_23 : STD_LOGIC; signal AXI4_LITE_I_n_27 : STD_LOGIC; signal AXI4_LITE_I_n_28 : STD_LOGIC; signal AXI4_LITE_I_n_29 : STD_LOGIC; signal AXI4_LITE_I_n_30 : STD_LOGIC; signal AXI4_LITE_I_n_31 : STD_LOGIC; signal AXI4_LITE_I_n_32 : STD_LOGIC; signal AXI4_LITE_I_n_33 : STD_LOGIC; signal AXI4_LITE_I_n_34 : STD_LOGIC; signal AXI4_LITE_I_n_35 : STD_LOGIC; signal AXI4_LITE_I_n_36 : STD_LOGIC; signal AXI4_LITE_I_n_37 : STD_LOGIC; signal AXI4_LITE_I_n_38 : STD_LOGIC; signal AXI4_LITE_I_n_39 : STD_LOGIC; signal AXI4_LITE_I_n_4 : STD_LOGIC; signal AXI4_LITE_I_n_40 : STD_LOGIC; signal AXI4_LITE_I_n_41 : STD_LOGIC; signal AXI4_LITE_I_n_42 : STD_LOGIC; signal AXI4_LITE_I_n_43 : STD_LOGIC; signal AXI4_LITE_I_n_44 : STD_LOGIC; signal AXI4_LITE_I_n_45 : STD_LOGIC; signal AXI4_LITE_I_n_46 : STD_LOGIC; signal AXI4_LITE_I_n_47 : STD_LOGIC; signal AXI4_LITE_I_n_48 : STD_LOGIC; signal AXI4_LITE_I_n_49 : STD_LOGIC; signal AXI4_LITE_I_n_5 : STD_LOGIC; signal AXI4_LITE_I_n_50 : STD_LOGIC; signal AXI4_LITE_I_n_51 : STD_LOGIC; signal AXI4_LITE_I_n_52 : STD_LOGIC; signal AXI4_LITE_I_n_53 : STD_LOGIC; signal AXI4_LITE_I_n_54 : STD_LOGIC; signal AXI4_LITE_I_n_55 : STD_LOGIC; signal AXI4_LITE_I_n_56 : STD_LOGIC; signal AXI4_LITE_I_n_57 : STD_LOGIC; signal AXI4_LITE_I_n_58 : STD_LOGIC; signal AXI4_LITE_I_n_59 : STD_LOGIC; signal AXI4_LITE_I_n_6 : STD_LOGIC; signal AXI4_LITE_I_n_60 : STD_LOGIC; signal AXI4_LITE_I_n_65 : STD_LOGIC; signal AXI4_LITE_I_n_66 : STD_LOGIC; signal AXI4_LITE_I_n_67 : STD_LOGIC; signal AXI4_LITE_I_n_68 : STD_LOGIC; signal AXI4_LITE_I_n_69 : STD_LOGIC; signal AXI4_LITE_I_n_7 : STD_LOGIC; signal AXI4_LITE_I_n_70 : STD_LOGIC; signal AXI4_LITE_I_n_71 : STD_LOGIC; signal AXI4_LITE_I_n_72 : STD_LOGIC; signal AXI4_LITE_I_n_73 : STD_LOGIC; signal AXI4_LITE_I_n_74 : STD_LOGIC; signal AXI4_LITE_I_n_75 : STD_LOGIC; signal AXI4_LITE_I_n_76 : STD_LOGIC; signal AXI4_LITE_I_n_77 : STD_LOGIC; signal AXI4_LITE_I_n_78 : STD_LOGIC; signal AXI4_LITE_I_n_79 : STD_LOGIC; signal AXI4_LITE_I_n_8 : STD_LOGIC; signal AXI4_LITE_I_n_80 : STD_LOGIC; signal AXI4_LITE_I_n_81 : STD_LOGIC; signal AXI4_LITE_I_n_82 : STD_LOGIC; signal AXI4_LITE_I_n_83 : STD_LOGIC; signal AXI4_LITE_I_n_84 : STD_LOGIC; signal AXI4_LITE_I_n_85 : STD_LOGIC; signal AXI4_LITE_I_n_86 : STD_LOGIC; signal AXI4_LITE_I_n_87 : STD_LOGIC; signal AXI4_LITE_I_n_88 : STD_LOGIC; signal AXI4_LITE_I_n_89 : STD_LOGIC; signal AXI4_LITE_I_n_9 : STD_LOGIC; signal AXI4_LITE_I_n_90 : STD_LOGIC; signal AXI4_LITE_I_n_91 : STD_LOGIC; signal AXI4_LITE_I_n_92 : STD_LOGIC; signal AXI4_LITE_I_n_93 : STD_LOGIC; signal AXI4_LITE_I_n_94 : STD_LOGIC; signal AXI4_LITE_I_n_95 : STD_LOGIC; signal AXI4_LITE_I_n_97 : STD_LOGIC; signal AXI4_LITE_I_n_98 : STD_LOGIC; signal AXI4_LITE_I_n_99 : STD_LOGIC; signal \COUNTER_0_I/D\ : STD_LOGIC; signal \GEN_SECOND_TIMER.COUNTER_1_I/D\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC; signal \TIMER_CONTROL_I/D\ : STD_LOGIC; signal \TIMER_CONTROL_I/pair0_Select\ : STD_LOGIC; signal \TIMER_CONTROL_I/read_done1\ : STD_LOGIC; signal bus2ip_reset : STD_LOGIC; signal bus2ip_wrce : STD_LOGIC_VECTOR ( 0 to 4 ); signal \bus2ip_wrce__0\ : STD_LOGIC_VECTOR ( 5 to 5 ); signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 ); signal read_Mux_In : STD_LOGIC_VECTOR ( 20 to 191 ); signal \^s_axi_wready\ : STD_LOGIC; begin s_axi_awready <= \^s_axi_wready\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_wready <= \^s_axi_wready\; AXI4_LITE_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif port map ( Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, D(31) => ip2bus_data(0), D(30) => ip2bus_data(1), D(29) => ip2bus_data(2), D(28) => ip2bus_data(3), D(27) => ip2bus_data(4), D(26) => ip2bus_data(5), D(25) => ip2bus_data(6), D(24) => ip2bus_data(7), D(23) => ip2bus_data(8), D(22) => ip2bus_data(9), D(21) => ip2bus_data(10), D(20) => ip2bus_data(11), D(19) => ip2bus_data(12), D(18) => ip2bus_data(13), D(17) => ip2bus_data(14), D(16) => ip2bus_data(15), D(15) => ip2bus_data(16), D(14) => ip2bus_data(17), D(13) => ip2bus_data(18), D(12) => ip2bus_data(19), D(11) => ip2bus_data(20), D(10) => ip2bus_data(21), D(9) => ip2bus_data(22), D(8) => ip2bus_data(23), D(7) => ip2bus_data(24), D(6) => ip2bus_data(25), D(5) => ip2bus_data(26), D(4) => ip2bus_data(27), D(3) => ip2bus_data(28), D(2) => ip2bus_data(29), D(1) => ip2bus_data(30), D(0) => ip2bus_data(31), D_0 => \GEN_SECOND_TIMER.COUNTER_1_I/D\, D_1 => \COUNTER_0_I/D\, D_2 => \TIMER_CONTROL_I/D\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \LOAD_REG_GEN[10].LOAD_REG_I\ => AXI4_LITE_I_n_51, \LOAD_REG_GEN[10].LOAD_REG_I_0\ => AXI4_LITE_I_n_86, \LOAD_REG_GEN[11].LOAD_REG_I\ => AXI4_LITE_I_n_50, \LOAD_REG_GEN[11].LOAD_REG_I_0\ => AXI4_LITE_I_n_85, \LOAD_REG_GEN[12].LOAD_REG_I\ => AXI4_LITE_I_n_49, \LOAD_REG_GEN[12].LOAD_REG_I_0\ => AXI4_LITE_I_n_84, \LOAD_REG_GEN[13].LOAD_REG_I\ => AXI4_LITE_I_n_48, \LOAD_REG_GEN[13].LOAD_REG_I_0\ => AXI4_LITE_I_n_83, \LOAD_REG_GEN[14].LOAD_REG_I\ => AXI4_LITE_I_n_47, \LOAD_REG_GEN[14].LOAD_REG_I_0\ => AXI4_LITE_I_n_82, \LOAD_REG_GEN[15].LOAD_REG_I\ => AXI4_LITE_I_n_46, \LOAD_REG_GEN[15].LOAD_REG_I_0\ => AXI4_LITE_I_n_81, \LOAD_REG_GEN[16].LOAD_REG_I\ => AXI4_LITE_I_n_45, \LOAD_REG_GEN[16].LOAD_REG_I_0\ => AXI4_LITE_I_n_80, \LOAD_REG_GEN[17].LOAD_REG_I\ => AXI4_LITE_I_n_44, \LOAD_REG_GEN[17].LOAD_REG_I_0\ => AXI4_LITE_I_n_79, \LOAD_REG_GEN[18].LOAD_REG_I\ => AXI4_LITE_I_n_43, \LOAD_REG_GEN[18].LOAD_REG_I_0\ => AXI4_LITE_I_n_78, \LOAD_REG_GEN[19].LOAD_REG_I\ => AXI4_LITE_I_n_42, \LOAD_REG_GEN[19].LOAD_REG_I_0\ => AXI4_LITE_I_n_77, \LOAD_REG_GEN[1].LOAD_REG_I\ => AXI4_LITE_I_n_60, \LOAD_REG_GEN[1].LOAD_REG_I_0\ => AXI4_LITE_I_n_95, \LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_41, \LOAD_REG_GEN[20].LOAD_REG_I_0\ => AXI4_LITE_I_n_76, \LOAD_REG_GEN[21].LOAD_REG_I\ => AXI4_LITE_I_n_40, \LOAD_REG_GEN[21].LOAD_REG_I_0\ => AXI4_LITE_I_n_75, \LOAD_REG_GEN[22].LOAD_REG_I\ => AXI4_LITE_I_n_39, \LOAD_REG_GEN[22].LOAD_REG_I_0\ => AXI4_LITE_I_n_74, \LOAD_REG_GEN[23].LOAD_REG_I\ => AXI4_LITE_I_n_38, \LOAD_REG_GEN[23].LOAD_REG_I_0\ => AXI4_LITE_I_n_73, \LOAD_REG_GEN[24].LOAD_REG_I\ => AXI4_LITE_I_n_37, \LOAD_REG_GEN[24].LOAD_REG_I_0\ => AXI4_LITE_I_n_72, \LOAD_REG_GEN[25].LOAD_REG_I\ => AXI4_LITE_I_n_36, \LOAD_REG_GEN[25].LOAD_REG_I_0\ => AXI4_LITE_I_n_71, \LOAD_REG_GEN[26].LOAD_REG_I\ => AXI4_LITE_I_n_35, \LOAD_REG_GEN[26].LOAD_REG_I_0\ => AXI4_LITE_I_n_70, \LOAD_REG_GEN[27].LOAD_REG_I\ => AXI4_LITE_I_n_34, \LOAD_REG_GEN[27].LOAD_REG_I_0\ => AXI4_LITE_I_n_69, \LOAD_REG_GEN[28].LOAD_REG_I\ => AXI4_LITE_I_n_33, \LOAD_REG_GEN[28].LOAD_REG_I_0\ => AXI4_LITE_I_n_68, \LOAD_REG_GEN[29].LOAD_REG_I\ => AXI4_LITE_I_n_32, \LOAD_REG_GEN[29].LOAD_REG_I_0\ => AXI4_LITE_I_n_67, \LOAD_REG_GEN[2].LOAD_REG_I\ => AXI4_LITE_I_n_59, \LOAD_REG_GEN[2].LOAD_REG_I_0\ => AXI4_LITE_I_n_94, \LOAD_REG_GEN[30].LOAD_REG_I\ => AXI4_LITE_I_n_31, \LOAD_REG_GEN[30].LOAD_REG_I_0\ => AXI4_LITE_I_n_66, \LOAD_REG_GEN[31].LOAD_REG_I\ => AXI4_LITE_I_n_30, \LOAD_REG_GEN[31].LOAD_REG_I_0\ => AXI4_LITE_I_n_65, \LOAD_REG_GEN[3].LOAD_REG_I\ => AXI4_LITE_I_n_58, \LOAD_REG_GEN[3].LOAD_REG_I_0\ => AXI4_LITE_I_n_93, \LOAD_REG_GEN[4].LOAD_REG_I\ => AXI4_LITE_I_n_57, \LOAD_REG_GEN[4].LOAD_REG_I_0\ => AXI4_LITE_I_n_92, \LOAD_REG_GEN[5].LOAD_REG_I\ => AXI4_LITE_I_n_56, \LOAD_REG_GEN[5].LOAD_REG_I_0\ => AXI4_LITE_I_n_91, \LOAD_REG_GEN[6].LOAD_REG_I\ => AXI4_LITE_I_n_55, \LOAD_REG_GEN[6].LOAD_REG_I_0\ => AXI4_LITE_I_n_90, \LOAD_REG_GEN[7].LOAD_REG_I\ => AXI4_LITE_I_n_54, \LOAD_REG_GEN[7].LOAD_REG_I_0\ => AXI4_LITE_I_n_89, \LOAD_REG_GEN[8].LOAD_REG_I\ => AXI4_LITE_I_n_53, \LOAD_REG_GEN[8].LOAD_REG_I_0\ => AXI4_LITE_I_n_88, \LOAD_REG_GEN[9].LOAD_REG_I\ => AXI4_LITE_I_n_52, \LOAD_REG_GEN[9].LOAD_REG_I_0\ => AXI4_LITE_I_n_87, READ_DONE0_I => AXI4_LITE_I_n_105, READ_DONE1_I => AXI4_LITE_I_n_106, \TCSR0_GENERATE[23].TCSR0_FF_I\ => AXI4_LITE_I_n_100, \TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28, \TCSR1_GENERATE[23].TCSR1_FF_I\ => AXI4_LITE_I_n_101, \TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29, bus2ip_reset => bus2ip_reset, bus2ip_wrce(1) => bus2ip_wrce(0), bus2ip_wrce(0) => bus2ip_wrce(4), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5), pair0_Select => \TIMER_CONTROL_I/pair0_Select\, read_Mux_In(87) => read_Mux_In(20), read_Mux_In(86) => read_Mux_In(24), read_Mux_In(85) => read_Mux_In(56), read_Mux_In(84) => read_Mux_In(64), read_Mux_In(83) => read_Mux_In(65), read_Mux_In(82) => read_Mux_In(66), read_Mux_In(81) => read_Mux_In(67), read_Mux_In(80) => read_Mux_In(68), read_Mux_In(79) => read_Mux_In(69), read_Mux_In(78) => read_Mux_In(70), read_Mux_In(77) => read_Mux_In(71), read_Mux_In(76) => read_Mux_In(72), read_Mux_In(75) => read_Mux_In(73), read_Mux_In(74) => read_Mux_In(74), read_Mux_In(73) => read_Mux_In(75), read_Mux_In(72) => read_Mux_In(76), read_Mux_In(71) => read_Mux_In(77), read_Mux_In(70) => read_Mux_In(78), read_Mux_In(69) => read_Mux_In(79), read_Mux_In(68) => read_Mux_In(80), read_Mux_In(67) => read_Mux_In(81), read_Mux_In(66) => read_Mux_In(82), read_Mux_In(65) => read_Mux_In(83), read_Mux_In(64) => read_Mux_In(84), read_Mux_In(63) => read_Mux_In(128), read_Mux_In(62) => read_Mux_In(129), read_Mux_In(61) => read_Mux_In(130), read_Mux_In(60) => read_Mux_In(131), read_Mux_In(59) => read_Mux_In(132), read_Mux_In(58) => read_Mux_In(133), read_Mux_In(57) => read_Mux_In(134), read_Mux_In(56) => read_Mux_In(135), read_Mux_In(55) => read_Mux_In(136), read_Mux_In(54) => read_Mux_In(137), read_Mux_In(53) => read_Mux_In(138), read_Mux_In(52) => read_Mux_In(139), read_Mux_In(51) => read_Mux_In(140), read_Mux_In(50) => read_Mux_In(141), read_Mux_In(49) => read_Mux_In(142), read_Mux_In(48) => read_Mux_In(143), read_Mux_In(47) => read_Mux_In(144), read_Mux_In(46) => read_Mux_In(145), read_Mux_In(45) => read_Mux_In(146), read_Mux_In(44) => read_Mux_In(147), read_Mux_In(43) => read_Mux_In(148), read_Mux_In(42) => read_Mux_In(149), read_Mux_In(41) => read_Mux_In(150), read_Mux_In(40) => read_Mux_In(151), read_Mux_In(39) => read_Mux_In(152), read_Mux_In(38) => read_Mux_In(153), read_Mux_In(37) => read_Mux_In(154), read_Mux_In(36) => read_Mux_In(155), read_Mux_In(35) => read_Mux_In(156), read_Mux_In(34) => read_Mux_In(157), read_Mux_In(33) => read_Mux_In(158), read_Mux_In(32) => read_Mux_In(159), read_Mux_In(31) => read_Mux_In(160), read_Mux_In(30) => read_Mux_In(161), read_Mux_In(29) => read_Mux_In(162), read_Mux_In(28) => read_Mux_In(163), read_Mux_In(27) => read_Mux_In(164), read_Mux_In(26) => read_Mux_In(165), read_Mux_In(25) => read_Mux_In(166), read_Mux_In(24) => read_Mux_In(167), read_Mux_In(23) => read_Mux_In(168), read_Mux_In(22) => read_Mux_In(169), read_Mux_In(21) => read_Mux_In(170), read_Mux_In(20) => read_Mux_In(171), read_Mux_In(19) => read_Mux_In(172), read_Mux_In(18) => read_Mux_In(173), read_Mux_In(17) => read_Mux_In(174), read_Mux_In(16) => read_Mux_In(175), read_Mux_In(15) => read_Mux_In(176), read_Mux_In(14) => read_Mux_In(177), read_Mux_In(13) => read_Mux_In(178), read_Mux_In(12) => read_Mux_In(179), read_Mux_In(11) => read_Mux_In(180), read_Mux_In(10) => read_Mux_In(181), read_Mux_In(9) => read_Mux_In(182), read_Mux_In(8) => read_Mux_In(183), read_Mux_In(7) => read_Mux_In(184), read_Mux_In(6) => read_Mux_In(185), read_Mux_In(5) => read_Mux_In(186), read_Mux_In(4) => read_Mux_In(187), read_Mux_In(3) => read_Mux_In(188), read_Mux_In(2) => read_Mux_In(189), read_Mux_In(1) => read_Mux_In(190), read_Mux_In(0) => read_Mux_In(191), read_done1 => \TIMER_CONTROL_I/read_done1\, s_axi_aclk => s_axi_aclk, s_axi_araddr(2 downto 0) => s_axi_araddr(4 downto 2), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(2 downto 0) => s_axi_awaddr(4 downto 2), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), \s_axi_rdata_i_reg[0]\ => AXI4_LITE_I_n_103, \s_axi_rdata_i_reg[0]_0\ => AXI4_LITE_I_n_104, \s_axi_rdata_i_reg[10]\ => AXI4_LITE_I_n_102, \s_axi_rdata_i_reg[11]\ => AXI4_LITE_I_n_27, \s_axi_rdata_i_reg[12]\ => AXI4_LITE_I_n_4, \s_axi_rdata_i_reg[13]\ => AXI4_LITE_I_n_5, \s_axi_rdata_i_reg[14]\ => AXI4_LITE_I_n_6, \s_axi_rdata_i_reg[15]\ => AXI4_LITE_I_n_7, \s_axi_rdata_i_reg[16]\ => AXI4_LITE_I_n_8, \s_axi_rdata_i_reg[17]\ => AXI4_LITE_I_n_9, \s_axi_rdata_i_reg[18]\ => AXI4_LITE_I_n_10, \s_axi_rdata_i_reg[19]\ => AXI4_LITE_I_n_11, \s_axi_rdata_i_reg[20]\ => AXI4_LITE_I_n_12, \s_axi_rdata_i_reg[21]\ => AXI4_LITE_I_n_13, \s_axi_rdata_i_reg[22]\ => AXI4_LITE_I_n_14, \s_axi_rdata_i_reg[23]\ => AXI4_LITE_I_n_15, \s_axi_rdata_i_reg[24]\ => AXI4_LITE_I_n_16, \s_axi_rdata_i_reg[25]\ => AXI4_LITE_I_n_17, \s_axi_rdata_i_reg[26]\ => AXI4_LITE_I_n_18, \s_axi_rdata_i_reg[27]\ => AXI4_LITE_I_n_19, \s_axi_rdata_i_reg[28]\ => AXI4_LITE_I_n_20, \s_axi_rdata_i_reg[29]\ => AXI4_LITE_I_n_21, \s_axi_rdata_i_reg[30]\ => AXI4_LITE_I_n_22, \s_axi_rdata_i_reg[31]\ => AXI4_LITE_I_n_23, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_rvalid_i_reg => AXI4_LITE_I_n_97, s_axi_rvalid_i_reg_0 => AXI4_LITE_I_n_98, s_axi_rvalid_i_reg_1 => AXI4_LITE_I_n_99, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => \^s_axi_wready\, s_axi_wvalid => s_axi_wvalid ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); TC_CORE_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core port map ( Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, Bus_RNW_reg_reg => AXI4_LITE_I_n_23, Bus_RNW_reg_reg_0 => AXI4_LITE_I_n_22, Bus_RNW_reg_reg_1 => AXI4_LITE_I_n_21, Bus_RNW_reg_reg_10 => AXI4_LITE_I_n_12, Bus_RNW_reg_reg_11 => AXI4_LITE_I_n_11, Bus_RNW_reg_reg_12 => AXI4_LITE_I_n_10, Bus_RNW_reg_reg_13 => AXI4_LITE_I_n_9, Bus_RNW_reg_reg_14 => AXI4_LITE_I_n_8, Bus_RNW_reg_reg_15 => AXI4_LITE_I_n_7, Bus_RNW_reg_reg_16 => AXI4_LITE_I_n_6, Bus_RNW_reg_reg_17 => AXI4_LITE_I_n_5, Bus_RNW_reg_reg_18 => AXI4_LITE_I_n_4, Bus_RNW_reg_reg_2 => AXI4_LITE_I_n_20, Bus_RNW_reg_reg_3 => AXI4_LITE_I_n_19, Bus_RNW_reg_reg_4 => AXI4_LITE_I_n_18, Bus_RNW_reg_reg_5 => AXI4_LITE_I_n_17, Bus_RNW_reg_reg_6 => AXI4_LITE_I_n_16, Bus_RNW_reg_reg_7 => AXI4_LITE_I_n_15, Bus_RNW_reg_reg_8 => AXI4_LITE_I_n_14, Bus_RNW_reg_reg_9 => AXI4_LITE_I_n_13, D(31) => ip2bus_data(0), D(30) => ip2bus_data(1), D(29) => ip2bus_data(2), D(28) => ip2bus_data(3), D(27) => ip2bus_data(4), D(26) => ip2bus_data(5), D(25) => ip2bus_data(6), D(24) => ip2bus_data(7), D(23) => ip2bus_data(8), D(22) => ip2bus_data(9), D(21) => ip2bus_data(10), D(20) => ip2bus_data(11), D(19) => ip2bus_data(12), D(18) => ip2bus_data(13), D(17) => ip2bus_data(14), D(16) => ip2bus_data(15), D(15) => ip2bus_data(16), D(14) => ip2bus_data(17), D(13) => ip2bus_data(18), D(12) => ip2bus_data(19), D(11) => ip2bus_data(20), D(10) => ip2bus_data(21), D(9) => ip2bus_data(22), D(8) => ip2bus_data(23), D(7) => ip2bus_data(24), D(6) => ip2bus_data(25), D(5) => ip2bus_data(26), D(4) => ip2bus_data(27), D(3) => ip2bus_data(28), D(2) => ip2bus_data(29), D(1) => ip2bus_data(30), D(0) => ip2bus_data(31), D_0 => \TIMER_CONTROL_I/D\, D_1 => \COUNTER_0_I/D\, D_2 => \GEN_SECOND_TIMER.COUNTER_1_I/D\, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI4_LITE_I_n_100, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => AXI4_LITE_I_n_102, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI4_LITE_I_n_95, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => AXI4_LITE_I_n_94, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => AXI4_LITE_I_n_93, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => AXI4_LITE_I_n_84, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => AXI4_LITE_I_n_83, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => AXI4_LITE_I_n_82, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => AXI4_LITE_I_n_81, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => AXI4_LITE_I_n_80, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => AXI4_LITE_I_n_79, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => AXI4_LITE_I_n_78, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => AXI4_LITE_I_n_77, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => AXI4_LITE_I_n_76, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => AXI4_LITE_I_n_75, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => AXI4_LITE_I_n_92, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => AXI4_LITE_I_n_74, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => AXI4_LITE_I_n_73, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => AXI4_LITE_I_n_72, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => AXI4_LITE_I_n_71, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => AXI4_LITE_I_n_70, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => AXI4_LITE_I_n_69, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => AXI4_LITE_I_n_68, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => AXI4_LITE_I_n_67, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => AXI4_LITE_I_n_66, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => AXI4_LITE_I_n_65, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => AXI4_LITE_I_n_91, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ => AXI4_LITE_I_n_105, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ => AXI4_LITE_I_n_97, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => AXI4_LITE_I_n_90, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => AXI4_LITE_I_n_89, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => AXI4_LITE_I_n_88, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => AXI4_LITE_I_n_87, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => AXI4_LITE_I_n_86, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => AXI4_LITE_I_n_85, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => AXI4_LITE_I_n_99, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI4_LITE_I_n_101, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => AXI4_LITE_I_n_98, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => AXI4_LITE_I_n_106, \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ => AXI4_LITE_I_n_103, \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => AXI4_LITE_I_n_104, \INFERRED_GEN.icount_out_reg[0]\(87) => read_Mux_In(20), \INFERRED_GEN.icount_out_reg[0]\(86) => read_Mux_In(24), \INFERRED_GEN.icount_out_reg[0]\(85) => read_Mux_In(56), \INFERRED_GEN.icount_out_reg[0]\(84) => read_Mux_In(64), \INFERRED_GEN.icount_out_reg[0]\(83) => read_Mux_In(65), \INFERRED_GEN.icount_out_reg[0]\(82) => read_Mux_In(66), \INFERRED_GEN.icount_out_reg[0]\(81) => read_Mux_In(67), \INFERRED_GEN.icount_out_reg[0]\(80) => read_Mux_In(68), \INFERRED_GEN.icount_out_reg[0]\(79) => read_Mux_In(69), \INFERRED_GEN.icount_out_reg[0]\(78) => read_Mux_In(70), \INFERRED_GEN.icount_out_reg[0]\(77) => read_Mux_In(71), \INFERRED_GEN.icount_out_reg[0]\(76) => read_Mux_In(72), \INFERRED_GEN.icount_out_reg[0]\(75) => read_Mux_In(73), \INFERRED_GEN.icount_out_reg[0]\(74) => read_Mux_In(74), \INFERRED_GEN.icount_out_reg[0]\(73) => read_Mux_In(75), \INFERRED_GEN.icount_out_reg[0]\(72) => read_Mux_In(76), \INFERRED_GEN.icount_out_reg[0]\(71) => read_Mux_In(77), \INFERRED_GEN.icount_out_reg[0]\(70) => read_Mux_In(78), \INFERRED_GEN.icount_out_reg[0]\(69) => read_Mux_In(79), \INFERRED_GEN.icount_out_reg[0]\(68) => read_Mux_In(80), \INFERRED_GEN.icount_out_reg[0]\(67) => read_Mux_In(81), \INFERRED_GEN.icount_out_reg[0]\(66) => read_Mux_In(82), \INFERRED_GEN.icount_out_reg[0]\(65) => read_Mux_In(83), \INFERRED_GEN.icount_out_reg[0]\(64) => read_Mux_In(84), \INFERRED_GEN.icount_out_reg[0]\(63) => read_Mux_In(128), \INFERRED_GEN.icount_out_reg[0]\(62) => read_Mux_In(129), \INFERRED_GEN.icount_out_reg[0]\(61) => read_Mux_In(130), \INFERRED_GEN.icount_out_reg[0]\(60) => read_Mux_In(131), \INFERRED_GEN.icount_out_reg[0]\(59) => read_Mux_In(132), \INFERRED_GEN.icount_out_reg[0]\(58) => read_Mux_In(133), \INFERRED_GEN.icount_out_reg[0]\(57) => read_Mux_In(134), \INFERRED_GEN.icount_out_reg[0]\(56) => read_Mux_In(135), \INFERRED_GEN.icount_out_reg[0]\(55) => read_Mux_In(136), \INFERRED_GEN.icount_out_reg[0]\(54) => read_Mux_In(137), \INFERRED_GEN.icount_out_reg[0]\(53) => read_Mux_In(138), \INFERRED_GEN.icount_out_reg[0]\(52) => read_Mux_In(139), \INFERRED_GEN.icount_out_reg[0]\(51) => read_Mux_In(140), \INFERRED_GEN.icount_out_reg[0]\(50) => read_Mux_In(141), \INFERRED_GEN.icount_out_reg[0]\(49) => read_Mux_In(142), \INFERRED_GEN.icount_out_reg[0]\(48) => read_Mux_In(143), \INFERRED_GEN.icount_out_reg[0]\(47) => read_Mux_In(144), \INFERRED_GEN.icount_out_reg[0]\(46) => read_Mux_In(145), \INFERRED_GEN.icount_out_reg[0]\(45) => read_Mux_In(146), \INFERRED_GEN.icount_out_reg[0]\(44) => read_Mux_In(147), \INFERRED_GEN.icount_out_reg[0]\(43) => read_Mux_In(148), \INFERRED_GEN.icount_out_reg[0]\(42) => read_Mux_In(149), \INFERRED_GEN.icount_out_reg[0]\(41) => read_Mux_In(150), \INFERRED_GEN.icount_out_reg[0]\(40) => read_Mux_In(151), \INFERRED_GEN.icount_out_reg[0]\(39) => read_Mux_In(152), \INFERRED_GEN.icount_out_reg[0]\(38) => read_Mux_In(153), \INFERRED_GEN.icount_out_reg[0]\(37) => read_Mux_In(154), \INFERRED_GEN.icount_out_reg[0]\(36) => read_Mux_In(155), \INFERRED_GEN.icount_out_reg[0]\(35) => read_Mux_In(156), \INFERRED_GEN.icount_out_reg[0]\(34) => read_Mux_In(157), \INFERRED_GEN.icount_out_reg[0]\(33) => read_Mux_In(158), \INFERRED_GEN.icount_out_reg[0]\(32) => read_Mux_In(159), \INFERRED_GEN.icount_out_reg[0]\(31) => read_Mux_In(160), \INFERRED_GEN.icount_out_reg[0]\(30) => read_Mux_In(161), \INFERRED_GEN.icount_out_reg[0]\(29) => read_Mux_In(162), \INFERRED_GEN.icount_out_reg[0]\(28) => read_Mux_In(163), \INFERRED_GEN.icount_out_reg[0]\(27) => read_Mux_In(164), \INFERRED_GEN.icount_out_reg[0]\(26) => read_Mux_In(165), \INFERRED_GEN.icount_out_reg[0]\(25) => read_Mux_In(166), \INFERRED_GEN.icount_out_reg[0]\(24) => read_Mux_In(167), \INFERRED_GEN.icount_out_reg[0]\(23) => read_Mux_In(168), \INFERRED_GEN.icount_out_reg[0]\(22) => read_Mux_In(169), \INFERRED_GEN.icount_out_reg[0]\(21) => read_Mux_In(170), \INFERRED_GEN.icount_out_reg[0]\(20) => read_Mux_In(171), \INFERRED_GEN.icount_out_reg[0]\(19) => read_Mux_In(172), \INFERRED_GEN.icount_out_reg[0]\(18) => read_Mux_In(173), \INFERRED_GEN.icount_out_reg[0]\(17) => read_Mux_In(174), \INFERRED_GEN.icount_out_reg[0]\(16) => read_Mux_In(175), \INFERRED_GEN.icount_out_reg[0]\(15) => read_Mux_In(176), \INFERRED_GEN.icount_out_reg[0]\(14) => read_Mux_In(177), \INFERRED_GEN.icount_out_reg[0]\(13) => read_Mux_In(178), \INFERRED_GEN.icount_out_reg[0]\(12) => read_Mux_In(179), \INFERRED_GEN.icount_out_reg[0]\(11) => read_Mux_In(180), \INFERRED_GEN.icount_out_reg[0]\(10) => read_Mux_In(181), \INFERRED_GEN.icount_out_reg[0]\(9) => read_Mux_In(182), \INFERRED_GEN.icount_out_reg[0]\(8) => read_Mux_In(183), \INFERRED_GEN.icount_out_reg[0]\(7) => read_Mux_In(184), \INFERRED_GEN.icount_out_reg[0]\(6) => read_Mux_In(185), \INFERRED_GEN.icount_out_reg[0]\(5) => read_Mux_In(186), \INFERRED_GEN.icount_out_reg[0]\(4) => read_Mux_In(187), \INFERRED_GEN.icount_out_reg[0]\(3) => read_Mux_In(188), \INFERRED_GEN.icount_out_reg[0]\(2) => read_Mux_In(189), \INFERRED_GEN.icount_out_reg[0]\(1) => read_Mux_In(190), \INFERRED_GEN.icount_out_reg[0]\(0) => read_Mux_In(191), \INFERRED_GEN.icount_out_reg[0]_0\ => AXI4_LITE_I_n_30, \INFERRED_GEN.icount_out_reg[10]\ => AXI4_LITE_I_n_40, \INFERRED_GEN.icount_out_reg[11]\ => AXI4_LITE_I_n_41, \INFERRED_GEN.icount_out_reg[12]\ => AXI4_LITE_I_n_42, \INFERRED_GEN.icount_out_reg[13]\ => AXI4_LITE_I_n_43, \INFERRED_GEN.icount_out_reg[14]\ => AXI4_LITE_I_n_44, \INFERRED_GEN.icount_out_reg[15]\ => AXI4_LITE_I_n_45, \INFERRED_GEN.icount_out_reg[16]\ => AXI4_LITE_I_n_46, \INFERRED_GEN.icount_out_reg[17]\ => AXI4_LITE_I_n_47, \INFERRED_GEN.icount_out_reg[18]\ => AXI4_LITE_I_n_48, \INFERRED_GEN.icount_out_reg[19]\ => AXI4_LITE_I_n_49, \INFERRED_GEN.icount_out_reg[1]\ => AXI4_LITE_I_n_31, \INFERRED_GEN.icount_out_reg[20]\ => AXI4_LITE_I_n_50, \INFERRED_GEN.icount_out_reg[21]\ => AXI4_LITE_I_n_51, \INFERRED_GEN.icount_out_reg[22]\ => AXI4_LITE_I_n_52, \INFERRED_GEN.icount_out_reg[23]\ => AXI4_LITE_I_n_53, \INFERRED_GEN.icount_out_reg[24]\ => AXI4_LITE_I_n_54, \INFERRED_GEN.icount_out_reg[25]\ => AXI4_LITE_I_n_55, \INFERRED_GEN.icount_out_reg[26]\ => AXI4_LITE_I_n_56, \INFERRED_GEN.icount_out_reg[27]\ => AXI4_LITE_I_n_57, \INFERRED_GEN.icount_out_reg[28]\ => AXI4_LITE_I_n_58, \INFERRED_GEN.icount_out_reg[29]\ => AXI4_LITE_I_n_59, \INFERRED_GEN.icount_out_reg[2]\ => AXI4_LITE_I_n_32, \INFERRED_GEN.icount_out_reg[30]\ => AXI4_LITE_I_n_60, \INFERRED_GEN.icount_out_reg[3]\ => AXI4_LITE_I_n_33, \INFERRED_GEN.icount_out_reg[4]\ => AXI4_LITE_I_n_34, \INFERRED_GEN.icount_out_reg[5]\ => AXI4_LITE_I_n_35, \INFERRED_GEN.icount_out_reg[6]\ => AXI4_LITE_I_n_36, \INFERRED_GEN.icount_out_reg[7]\ => AXI4_LITE_I_n_37, \INFERRED_GEN.icount_out_reg[8]\ => AXI4_LITE_I_n_38, \INFERRED_GEN.icount_out_reg[9]\ => AXI4_LITE_I_n_39, \LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_27, \TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28, \TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29, bus2ip_reset => bus2ip_reset, bus2ip_wrce(1) => bus2ip_wrce(0), bus2ip_wrce(0) => bus2ip_wrce(4), \bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5), capturetrig0 => capturetrig0, capturetrig1 => capturetrig1, freeze => freeze, generateout0 => generateout0, generateout1 => generateout1, interrupt => interrupt, pair0_Select => \TIMER_CONTROL_I/pair0_Select\, pwm0 => pwm0, read_done1 => \TIMER_CONTROL_I/read_done1\, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_wdata(9 downto 7) => s_axi_wdata(11 downto 9), s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( capturetrig0 : in STD_LOGIC; capturetrig1 : in STD_LOGIC; generateout0 : out STD_LOGIC; generateout1 : out STD_LOGIC; pwm0 : out STD_LOGIC; interrupt : out STD_LOGIC; freeze : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_timer_0_1,axi_timer,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_timer,Vivado 2017.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute C_COUNT_WIDTH : integer; attribute C_COUNT_WIDTH of U0 : label is 32; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_GEN0_ASSERT : string; attribute C_GEN0_ASSERT of U0 : label is "1'b1"; attribute C_GEN1_ASSERT : string; attribute C_GEN1_ASSERT of U0 : label is "1'b1"; attribute C_ONE_TIMER_ONLY : integer; attribute C_ONE_TIMER_ONLY of U0 : label is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of U0 : label is 5; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of U0 : label is 32; attribute C_TRIG0_ASSERT : string; attribute C_TRIG0_ASSERT of U0 : label is "1'b1"; attribute C_TRIG1_ASSERT : string; attribute C_TRIG1_ASSERT of U0 : label is "1'b1"; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer port map ( capturetrig0 => capturetrig0, capturetrig1 => capturetrig1, freeze => freeze, generateout0 => generateout0, generateout1 => generateout1, interrupt => interrupt, pwm0 => pwm0, s_axi_aclk => s_axi_aclk, s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0), s_axi_awready => s_axi_awready, s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;

mit

2f62324d5ad71bfb50a950bf2523b48c

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/gaisler/arith/arith.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Package: arith -- File: arith.vhd -- Author: Jiri Gaisler, Gaisler Research -- Description: Declaration of mul/div components ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package arith is type div32_in_type is record y : std_logic_vector(32 downto 0); -- Y (MSB divident) op1 : std_logic_vector(32 downto 0); -- operand 1 (LSB divident) op2 : std_logic_vector(32 downto 0); -- operand 2 (divisor) flush : std_logic; signed : std_logic; start : std_logic; end record; type div32_out_type is record ready : std_logic; nready : std_logic; icc : std_logic_vector(3 downto 0); -- ICC result : std_logic_vector(31 downto 0); -- div result end record; type mul32_in_type is record op1 : std_logic_vector(32 downto 0); -- operand 1 op2 : std_logic_vector(32 downto 0); -- operand 2 flush : std_logic; signed : std_logic; start : std_logic; mac : std_logic; acc : std_logic_vector(39 downto 0); --y : std_logic_vector(7 downto 0); -- Y (MSB MAC register) --asr18 : std_logic_vector(31 downto 0); -- LSB MAC register end record; type mul32_out_type is record ready : std_logic; nready : std_logic; icc : std_logic_vector(3 downto 0); -- ICC result : std_logic_vector(63 downto 0); -- mul result end record; component div32 generic (scantest : integer := 0); port ( rst : in std_ulogic; clk : in std_ulogic; holdn : in std_ulogic; divi : in div32_in_type; divo : out div32_out_type; testen : in std_ulogic := '0'; testrst : in std_ulogic := '1' ); end component; component mul32 generic ( tech : integer := 0; multype : integer := 0; pipe : integer := 0; mac : integer := 0; arch : integer range 0 to 3 := 0; scantest: integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; holdn : in std_ulogic; muli : in mul32_in_type; mulo : out mul32_out_type; testen : in std_ulogic := '0'; testrst : in std_ulogic := '1' ); end component; function smult ( a, b : in std_logic_vector) return std_logic_vector; function umult ( a, b : in std_logic_vector) return std_logic_vector; end; package body arith is function smult ( a, b : in std_logic_vector) return std_logic_vector is variable sa : signed (a'length-1 downto 0); variable sb : signed (b'length-1 downto 0); variable sc : signed ((a'length + b'length) -1 downto 0); variable res : std_logic_vector ((a'length + b'length) -1 downto 0); begin sa := signed(a); sb := signed(b); -- pragma translate_off if is_x(a) or is_x(b) then sc := (others => 'X'); else -- pragma translate_on sc := sa * sb; -- pragma translate_off end if; -- pragma translate_on res := std_logic_vector(sc); return(res); end; function umult ( a, b : in std_logic_vector) return std_logic_vector is variable sa : unsigned (a'length-1 downto 0); variable sb : unsigned (b'length-1 downto 0); variable sc : unsigned ((a'length + b'length) -1 downto 0); variable res : std_logic_vector ((a'length + b'length) -1 downto 0); begin sa := unsigned(a); sb := unsigned(b); -- pragma translate_off if is_x(a) or is_x(b) then sc := (others => 'X'); else -- pragma translate_on sc := sa * sb; -- pragma translate_off end if; -- pragma translate_on res := std_logic_vector(sc); return(res); end; end;

gpl-2.0

fb247c73ec731b5eff8af0da1747a16d

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_0/synth/zynq_design_1_axi_bram_ctrl_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0 -- IP Revision: 11 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_bram_ctrl_v4_0_11; USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl; ENTITY zynq_design_1_axi_bram_ctrl_0_0 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rst_b : OUT STD_LOGIC; bram_clk_b : OUT STD_LOGIC; bram_en_b : OUT STD_LOGIC; bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END zynq_design_1_axi_bram_ctrl_0_0; ARCHITECTURE zynq_design_1_axi_bram_ctrl_0_0_arch OF zynq_design_1_axi_bram_ctrl_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_bram_ctrl IS GENERIC ( C_BRAM_INST_MODE : STRING; C_MEMORY_DEPTH : INTEGER; C_BRAM_ADDR_WIDTH : INTEGER; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_S_AXI_ID_WIDTH : INTEGER; C_S_AXI_PROTOCOL : STRING; C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER; C_SINGLE_PORT_BRAM : INTEGER; C_FAMILY : STRING; C_SELECT_XPM : INTEGER; C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER; C_ECC : INTEGER; C_ECC_TYPE : INTEGER; C_FAULT_INJECT : INTEGER; C_ECC_ONOFF_RESET_VALUE : INTEGER ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; ecc_interrupt : OUT STD_LOGIC; ecc_ue : OUT STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_ctrl_awvalid : IN STD_LOGIC; s_axi_ctrl_awready : OUT STD_LOGIC; s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wvalid : IN STD_LOGIC; s_axi_ctrl_wready : OUT STD_LOGIC; s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_bvalid : OUT STD_LOGIC; s_axi_ctrl_bready : IN STD_LOGIC; s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_arvalid : IN STD_LOGIC; s_axi_ctrl_arready : OUT STD_LOGIC; s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_rvalid : OUT STD_LOGIC; s_axi_ctrl_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rst_b : OUT STD_LOGIC; bram_clk_b : OUT STD_LOGIC; bram_en_b : OUT STD_LOGIC; bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_bram_ctrl; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2017.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_design_1_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "zynq_design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "zynq_design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=16384,C_BRAM_ADDR_WIDTH=14,C_S_AXI_ADDR_WIDTH=16,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=12,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=0,C_FAMILY=zynq,C_SELECT_XPM=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=3" & "2,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST"; ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST"; ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN"; ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE"; ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN"; ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; BEGIN U0 : axi_bram_ctrl GENERIC MAP ( C_BRAM_INST_MODE => "EXTERNAL", C_MEMORY_DEPTH => 16384, C_BRAM_ADDR_WIDTH => 14, C_S_AXI_ADDR_WIDTH => 16, C_S_AXI_DATA_WIDTH => 32, C_S_AXI_ID_WIDTH => 12, C_S_AXI_PROTOCOL => "AXI4", C_S_AXI_SUPPORTS_NARROW_BURST => 0, C_SINGLE_PORT_BRAM => 0, C_FAMILY => "zynq", C_SELECT_XPM => 0, C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32, C_ECC => 0, C_ECC_TYPE => 0, C_FAULT_INJECT => 0, C_ECC_ONOFF_RESET_VALUE => 0 ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awid => s_axi_awid, s_axi_awaddr => s_axi_awaddr, s_axi_awlen => s_axi_awlen, s_axi_awsize => s_axi_awsize, s_axi_awburst => s_axi_awburst, s_axi_awlock => s_axi_awlock, s_axi_awcache => s_axi_awcache, s_axi_awprot => s_axi_awprot, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wlast => s_axi_wlast, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bid => s_axi_bid, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_arid => s_axi_arid, s_axi_araddr => s_axi_araddr, s_axi_arlen => s_axi_arlen, s_axi_arsize => s_axi_arsize, s_axi_arburst => s_axi_arburst, s_axi_arlock => s_axi_arlock, s_axi_arcache => s_axi_arcache, s_axi_arprot => s_axi_arprot, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rid => s_axi_rid, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rlast => s_axi_rlast, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, s_axi_ctrl_awvalid => '0', s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wvalid => '0', s_axi_ctrl_bready => '0', s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_arvalid => '0', s_axi_ctrl_rready => '0', bram_rst_a => bram_rst_a, bram_clk_a => bram_clk_a, bram_en_a => bram_en_a, bram_we_a => bram_we_a, bram_addr_a => bram_addr_a, bram_wrdata_a => bram_wrdata_a, bram_rddata_a => bram_rddata_a, bram_rst_b => bram_rst_b, bram_clk_b => bram_clk_b, bram_en_b => bram_en_b, bram_we_b => bram_we_b, bram_addr_b => bram_addr_b, bram_wrdata_b => bram_wrdata_b, bram_rddata_b => bram_rddata_b ); END zynq_design_1_axi_bram_ctrl_0_0_arch;

mit

d38a12e6f70793ce896d027eb6e0b553

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/gaisler/i2c/i2cslv.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- -- Entity: i2cslv -- File: i2cslv.vhd -- Author: Jan Andersson - Gaisler Research -- [email protected] -- -- Description: Simple I2C-slave with AMBA APB interface -- -- Documentation of generics: -- -- [hardaddr] -- If this generic is set to 1 the core uses i2caddr as the hard coded address. -- If hardaddr is set to 0 the core's address can be changed via the SLVADDR -- register. -- -- [tenbit] -- Support for ten bit addresses. -- -- [i2caddr] -- The slave's (initial) i2c address. -- -- [oepol] -- Output enable polarity -- -- [filter] -- Length of filters used on SCL and SDA -- -- The slave has four different modes operation. The mode is defined by the -- value of the bits RMODE and TMODE. -- RMODE TMODE I2CSLAVE Mode -- 0 0 0 -- 0 1 1 -- 1 0 2 -- 1 1 3 -- -- RMODE 0: -- The slave accepts one byte and NAKs all other transfers until software has -- acknowledged the received byte. -- RMODE 1: -- The slave accepts one byte and keeps SCL low until software has acknowledged -- the received byte -- TMODE 0: -- The slave transmits the same byte to all if the master requests more than -- one byte in the transfer. The slave then NAKs all read requests unless the -- Transmit Always Valid (TAV) bit in the control register is set. -- TMODE 1: -- The slave transmits one byte and then keeps SCL low until software has -- acknowledged that the byte has been transmitted. library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.i2c.all; library grlib; use grlib.amba.all; use grlib.devices.all; use grlib.stdlib.all; entity i2cslv is generic ( -- APB generics pindex : integer := 0; -- slave bus index paddr : integer := 0; pmask : integer := 16#fff#; pirq : integer := 0; -- interrupt index -- I2C configuration hardaddr : integer range 0 to 1 := 0; -- See description above tenbit : integer range 0 to 1 := 0; i2caddr : integer range 0 to 1023 := 0; oepol : integer range 0 to 1 := 0; filter : integer range 2 to 512 := 2 ); port ( rstn : in std_ulogic; clk : in std_ulogic; -- APB signals apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; -- I2C signals i2ci : in i2c_in_type; i2co : out i2c_out_type ); end entity i2cslv; architecture rtl of i2cslv is ----------------------------------------------------------------------------- -- Constants ----------------------------------------------------------------------------- -- Core version constant I2CSLV_REV : integer := 0; -- AMBA PnP constant PCONFIG : apb_config_type := ( 0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CSLV, 0, I2CSLV_REV, pirq), 1 => apb_iobar(paddr, pmask)); -- Register addresses constant SLV_ADDR : std_logic_vector(7 downto 2) := "000000"; constant CTRL_ADDR : std_logic_vector(7 downto 2) := "000001"; constant STS_ADDR : std_logic_vector(7 downto 2) := "000010"; constant MSK_ADDR : std_logic_vector(7 downto 2) := "000011"; constant RD_ADDR : std_logic_vector(7 downto 2) := "000100"; constant TD_ADDR : std_logic_vector(7 downto 2) := "000101"; -- Core configuration constant TENBIT_SUPPORT : integer := tenbit; constant I2CADDRLEN : integer := 7 + tenbit*3; constant HARDCADDR : integer := hardaddr; constant I2CSLVADDR : std_logic_vector((I2CADDRLEN-1) downto 0) := conv_std_logic_vector(i2caddr, I2CADDRLEN); -- Misc constants constant I2C_READ : std_ulogic := '1'; -- R/Wn bit constant I2C_WRITE : std_ulogic := '0'; constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1); constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL; constant I2C_ACK : std_ulogic := '0'; constant TENBIT_ADDR_START : std_logic_vector(4 downto 0) := "11110"; ----------------------------------------------------------------------------- -- Types ----------------------------------------------------------------------------- type ctrl_reg_type is record -- Control register rmode : std_ulogic; -- Receive mode tmode : std_ulogic; -- Transmit mode tv : std_ulogic; -- Transmit valid tav : std_ulogic; -- Transmit always valid en : std_ulogic; -- Enable end record; type sts_reg_type is record -- Status/Mask registers rec : std_ulogic; -- Received byte tra : std_ulogic; -- Transmitted byte nak : std_ulogic; -- NAK'd address end record; type slvaddr_reg_type is record -- Slave address register tba : std_ulogic; -- 10-bit address slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0); end record; type i2cslv_reg_bank is record -- APB registers slvaddr : slvaddr_reg_type; ctrl : ctrl_reg_type; sts : sts_reg_type; msk : sts_reg_type; receive : std_logic_vector(7 downto 0); transmit : std_logic_vector(7 downto 0); end record; type i2c_in_array is array (filter downto 0) of i2c_in_type; type slv_state_type is (idle, checkaddr, check10bitaddr, sclhold, movebyte, handshake); type i2cslv_reg_type is record slvstate : slv_state_type; -- reg : i2cslv_reg_bank; irq : std_ulogic; -- Transfer phase active : boolean; addr : boolean; transmit : boolean; receive : boolean; -- Shift register sreg : std_logic_vector(7 downto 0); cnt : std_logic_vector(2 downto 0); -- Synchronizers for inputs SCL and SDA scl : std_ulogic; sda : std_ulogic; i2ci : i2c_in_array; -- Output enables scloen : std_ulogic; sdaoen : std_ulogic; end record; ----------------------------------------------------------------------------- -- Subprograms ----------------------------------------------------------------------------- -- purpose: Compares the first byte of a received address with the slave's -- address. The tba input determines if the slave is using a ten bit address. function compaddr1stb ( ibyte : std_logic_vector(7 downto 0); -- I2C byte sr : slvaddr_reg_type) -- slave address register return boolean is variable correct : std_logic_vector(7 downto 1); begin -- compaddr1stb if sr.tba = '1' then correct(7 downto 3) := TENBIT_ADDR_START; correct(2 downto 1):= sr.slvaddr((I2CADDRLEN-1) downto (I2CADDRLEN-2)); else correct(7 downto 1) := sr.slvaddr(6 downto 0); end if; return ibyte(7 downto 1) = correct(7 downto 1); end compaddr1stb; -- purpose: Compares the 2nd byte of a ten bit address with the slave address function compaddr2ndb ( ibyte : std_logic_vector(7 downto 0); -- I2C byte slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0)) -- slave address return boolean is begin -- compaddr2ndb return ibyte((I2CADDRLEN-3) downto 0) = slvaddr((I2CADDRLEN-3) downto 0); end compaddr2ndb; ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- -- Register interface signal r, rin : i2cslv_reg_type; begin comb: process (r, rstn, apbi, i2ci) variable v : i2cslv_reg_type; variable irq : std_logic_vector((NAHBIRQ-1) downto 0); variable apbaddr : std_logic_vector(5 downto 0); variable apbout : std_logic_vector(31 downto 0); variable sclfilt : std_logic_vector(filter-1 downto 0); variable sdafilt : std_logic_vector(filter-1 downto 0); variable tba : boolean; begin -- process comb v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq; apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0'); v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0); tba := false; --------------------------------------------------------------------------- -- APB register interface --------------------------------------------------------------------------- -- read registers if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then case apbaddr is when SLV_ADDR => apbout(31) := r.reg.slvaddr.tba; apbout((I2CADDRLEN-1) downto 0) := r.reg.slvaddr.slvaddr; when CTRL_ADDR => apbout(4 downto 0) := r.reg.ctrl.rmode & r.reg.ctrl.tmode & r.reg.ctrl.tv & r.reg.ctrl.tav & r.reg.ctrl.en; when STS_ADDR => apbout(2 downto 0) := r.reg.sts.rec & r.reg.sts.tra & r.reg.sts.nak; when MSK_ADDR => apbout(2 downto 0) := r.reg.msk.rec & r.reg.msk.tra & r.reg.msk.nak; when RD_ADDR => v.reg.sts.rec := '0'; apbout(7 downto 0) := r.reg.receive; when TD_ADDR => apbout(7 downto 0) := r.reg.transmit; when others => null; end case; end if; -- write registers if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then case apbaddr is when SLV_ADDR => if HARDCADDR = 0 then if TENBIT_SUPPORT = 1 then v.reg.slvaddr.tba := apbi.pwdata(31); end if; v.reg.slvaddr.slvaddr := apbi.pwdata((I2CADDRLEN-1) downto 0); end if; when CTRL_ADDR => v.reg.ctrl.rmode := apbi.pwdata(4); v.reg.ctrl.tmode := apbi.pwdata(3); v.reg.ctrl.tv := apbi.pwdata(2); v.reg.ctrl.tav := apbi.pwdata(1); v.reg.ctrl.en := apbi.pwdata(0); when STS_ADDR => v.reg.sts.tra := r.reg.sts.tra and not apbi.pwdata(1); v.reg.sts.nak := r.reg.sts.nak and not apbi.pwdata(0); when MSK_ADDR => v.reg.msk.rec := apbi.pwdata(2); v.reg.msk.tra := apbi.pwdata(1); v.reg.msk.nak := apbi.pwdata(0); when TD_ADDR => v.reg.transmit := apbi.pwdata(7 downto 0); when others => null; end case; end if; ---------------------------------------------------------------------------- -- Bus filtering ---------------------------------------------------------------------------- for i in 0 to filter-1 loop sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda; end loop; -- i if andv(sclfilt) = '1' then v.scl := '1'; end if; if orv(sclfilt) = '0' then v.scl := '0'; end if; if andv(sdafilt) = '1' then v.sda := '1'; end if; if orv(sdafilt) = '0' then v.sda := '0'; end if; --------------------------------------------------------------------------- -- I2C slave control FSM --------------------------------------------------------------------------- case r.slvstate is when idle => -- Release bus if (r.scl and not v.scl) = '1' then v.sdaoen := I2C_HIZ; end if; when checkaddr => tba := r.reg.slvaddr.tba = '1'; if compaddr1stb(r.sreg, r.reg.slvaddr) then if r.sreg(0) = I2C_READ then if (not tba or (tba and r.active)) then if r.reg.ctrl.tv = '1' then -- Transmit data v.transmit := true; v.slvstate := handshake; else -- No data to transmit, NAK if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then v.irq := '1'; end if; v.reg.sts.nak := '1'; v.slvstate := idle; end if; else -- Ten bit address with R/Wn = 1 and slave not previously -- addressed. v.slvstate := idle; end if; else v.receive := not tba; v.slvstate := handshake; end if; else -- Slave address did not match v.active := false; v.slvstate := idle; end if; v.sreg := r.reg.transmit; when check10bitaddr => if compaddr2ndb(r.sreg, r.reg.slvaddr.slvaddr) then -- Slave has been addressed with a matching 10 bit address -- If we receive a repeated start condition, matching address -- and R/Wn = 1 we will transmit data. Without start condition we -- will receive data. v.addr := true; v.active := true; v.receive := true; v.slvstate := handshake; else v.slvstate := idle; end if; when sclhold => -- This state is used when the device has been addressed to see if SCL -- should be kept low until the receive register is free or the -- transmit register is filled. It is also used when a data byte has -- been transmitted or received to SCL low until software acknowledges -- the transfer. if (r.scl and not v.scl) = '1' then v.scloen := I2C_LOW; v.sdaoen := I2C_HIZ; end if; if ((r.receive and (not r.reg.sts.rec or not r.reg.ctrl.rmode) = '1') or (r.transmit and (r.reg.ctrl.tv or not r.reg.ctrl.tmode) = '1')) then v.slvstate := movebyte; v.scloen := I2C_HIZ; -- Falling edge that should be detected in movebyte may have passed if r.transmit and v.scl = '0' then v.sdaoen := r.sreg(7) xor OEPOL_LEVEL; end if; end if; v.sreg := r.reg.transmit; when movebyte => if (r.scl and not v.scl) = '1' then if r.transmit then v.sdaoen := r.sreg(7) xor OEPOL_LEVEL; else v.sdaoen := I2C_HIZ; end if; end if; if (not r.scl and v.scl) = '1' then v.sreg := r.sreg(6 downto 0) & r.sda; if r.cnt = "111" then if r.addr then v.slvstate := checkaddr; elsif r.receive nor r.transmit then v.slvstate := check10bitaddr; else v.slvstate := handshake; end if; v.cnt := (others => '0'); else v.cnt := r.cnt + 1; end if; end if; when handshake => -- Falling edge if (r.scl and not v.scl) = '1' then if r.addr then v.sdaoen := I2C_LOW; elsif r.receive then -- Receive, send ACK/NAK -- Acknowledge byte if core has room in receive register -- This code assumes that the core's receive register is free if we are -- in RMODE 1. This should always be the case unless software has -- reconfigured the core during operation. if r.reg.sts.rec = '0' then v.sdaoen := I2C_LOW; v.reg.receive := r.sreg; if r.reg.msk.rec = '1' then v.irq := '1'; end if; v.reg.sts.rec := '1'; else -- NAK the byte, the master must abort the transfer v.sdaoen := I2C_HIZ; v.slvstate := idle; end if; else -- Transmit, release bus v.sdaoen := I2C_HIZ; -- Byte transmitted, unset TV unless TAV is set. v.reg.ctrl.tv := r.reg.ctrl.tav; -- Set status bit and check if interrupt should be generated if (not v.reg.sts.tra and r.reg.msk.tra) = '1' then v.irq := '1'; end if; v.reg.sts.tra := '1'; end if; if not r.addr and r.receive and v.sdaoen = I2C_HIZ then if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then v.irq := '1'; end if; v.reg.sts.nak := '1'; end if; end if; -- Risinge edge if (not r.scl and v.scl) = '1' then if r.addr then v.slvstate := movebyte; else if r.receive then -- RMODE 0: Be ready to accept one more byte which will be NAK'd if -- software has not read the receive register -- RMODE 1: Keep SCL low until software has acknowledged received byte if r.reg.ctrl.rmode = '0' then v.slvstate := movebyte; else v.slvstate := sclhold; end if; else -- Transmit, check ACK/NAK from master -- If the master NAKs the transmitted byte the transfer has ended and -- we should wait for the master's next action. If the master ACKs the -- byte the core will act depending on tmode: -- TMODE 0: -- If the master ACKs the byte we must continue to transmit and will -- transmit the same byte on all requests. -- TMODE 1: -- IF the master ACKs the byte we will keep SCL low until software has -- put new transmit data into the transmit register. if r.sda = I2C_ACK then if r.reg.ctrl.tmode = '0' then v.slvstate := movebyte; else v.slvstate := sclhold; end if; else v.slvstate := idle; end if; end if; end if; v.addr := false; v.sreg := r.reg.transmit; end if; end case; if r.reg.ctrl.en = '1' then -- STOP condition if (r.scl and v.scl and not r.sda and v.sda) = '1' then v.active := false; v.slvstate := idle; end if; -- START or repeated START condition if (r.scl and v.scl and r.sda and not v.sda) = '1' then v.slvstate := movebyte; v.cnt := (others => '0'); v.addr := true; v.transmit := false; v.receive := false; end if; end if; ---------------------------------------------------------------------------- -- Reset and idle operation ---------------------------------------------------------------------------- if rstn = '0' then v.slvstate := idle; v.reg.slvaddr.slvaddr := I2CSLVADDR; if TENBIT_SUPPORT = 1 then v.reg.slvaddr.tba := '1'; else v.reg.slvaddr.tba := '0'; end if; v.reg.ctrl.en := '0'; v.reg.sts := ('0', '0', '0'); v.scl := '0'; v.active := false; v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ; end if; ---------------------------------------------------------------------------- -- Signal assignments ---------------------------------------------------------------------------- -- Update registers rin <= v; -- Update outputs apbo.prdata <= apbout; apbo.pirq <= irq; apbo.pconfig <= PCONFIG; apbo.pindex <= pindex; i2co.scl <= '0'; i2co.scloen <= r.scloen; i2co.sda <= '0'; i2co.sdaoen <= r.sdaoen; i2co.enable <= r.reg.ctrl.en; end process comb; reg: process (clk) begin -- process reg if rising_edge(clk) then r <= rin; end if; end process reg; -- Boot message -- pragma translate_off bootmsg : report_version generic map ( "i2cslv" & tost(pindex) & ": I2C slave rev " & tost(I2CSLV_REV) & ", irq " & tost(pirq)); -- pragma translate_on end architecture rtl;

gpl-2.0

14f796ab26737beaddf634fab2a98795

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep3c25/leon3mp.vhd

------------------------------------------------------------------------------ -- LEON3 Demonstration design -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.memctrl.all; use gaisler.ddrpkg.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.jtag.all; library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; ncpu : integer := CFG_NCPU; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; freq : integer := 50000 -- frequency of main clock (used for PLLs) ); port ( resetn : in std_ulogic; clk : in std_ulogic; errorn : out std_ulogic; -- flash/ssram bus address : out std_logic_vector(25 downto 1); data : inout std_logic_vector(31 downto 0); romsn : out std_ulogic; oen : out std_logic; writen : out std_logic; rstoutn : out std_ulogic; ssram_cen : out std_logic; ssram_wen : out std_logic; ssram_bw : out std_logic_vector (0 to 3); ssram_oen : out std_ulogic; ssram_clk : out std_ulogic; ssram_adscn : out std_ulogic; -- ssram_adsp_n : out std_ulogic; -- ssram_adv_n : out std_ulogic; -- pragma translate_off iosn : out std_ulogic; -- pragma translate_on ddr_clk : out std_logic; ddr_clkn : out std_logic; ddr_cke : out std_logic; ddr_csb : out std_logic; ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (12 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data -- debug support unit dsubren : in std_ulogic; dsuact : out std_ulogic; -- console/debug UART rxd1 : in std_logic; txd1 : out std_logic; gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port ); end; architecture rtl of leon3mp is constant blength : integer := 12; constant fifodepth : integer := 8; constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG; signal vcc, gnd : std_logic_vector(7 downto 0); signal memi, smemi : memory_in_type; signal memo, smemo : memory_out_type; signal wpo : wprot_out_type; signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic; signal ddr_clkv : std_logic_vector(2 downto 0); signal ddr_clkbv : std_logic_vector(2 downto 0); signal ddr_ckev : std_logic_vector(1 downto 0); signal ddr_csbv : std_logic_vector(1 downto 0); signal ddr_adl : std_logic_vector (13 downto 0); signal clklock, lock, clkml, rst, ndsuact : std_ulogic; signal tck, tckn, tms, tdi, tdo : std_ulogic; signal ddrclk, ddrrst : std_ulogic; -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; -- attribute syn_keep of clkml : signal is true; -- attribute syn_preserve of clkml : signal is true; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal clkm, rstn, ssram_clkl : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal u1i, dui : uart_in_type; signal u1o, duo : uart_out_type; signal irqi : irq_in_vector(0 to NCPU-1); signal irqo : irq_out_vector(0 to NCPU-1); signal dbgi : l3_debug_in_vector(0 to NCPU-1); signal dbgo : l3_debug_out_vector(0 to NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal gpti : gptimer_in_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; constant IOAEN : integer := 1; constant BOARD_FREQ : integer := 50000; -- input frequency in KHz constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz signal lclk, lclkout : std_ulogic; signal dsubre : std_ulogic; begin ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0'; clklock <= cgo.clklock and lock; clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk); clkgen0 : clkgen -- clock generator using toplevel generic 'freq' generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV, sdramen => 1, freq => freq) port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open, clk2x => open, sdclk => ssram_clkl, pciclk => open, cgi => cgi, cgo => cgo); ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (ssram_clk, ssram_clkl); rst0 : rstgen -- reset generator port map (resetn, clkm, clklock, rstn); rstoutn <= resetn; ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN, nahbm => maxahbm, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- l3 : if CFG_LEON3 = 1 generate cpu : for i in 0 to NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); end generate; end generate; nodsu : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0 : ahbuart -- Debug UART generic map (hindex => NCPU, pindex => 4, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU)); dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd); dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd); end generate; nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1, sden => 0, ram16 => 1) port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo); end generate; memi.brdyn <= '1'; memi.bexcn <= '1'; memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01"; ssr0 : if CFG_SSCTRL = 1 generate ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0, iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP, bus16 => CFG_SSCTRLP16) port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo); end generate; mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads apbo(0) <= apb_none; ahbso(0) <= ahbs_none; roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0)); end generate; mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads addr_pad : outpadv generic map (width => 25, tech => padtech) port map (address, memo.address(25 downto 1)); roms_pad : outpad generic map (tech => padtech) port map (romsn, memo.romsn(0)); oen_pad : outpad generic map (tech => padtech) port map (oen, memo.oen); wri_pad : outpad generic map (tech => padtech) port map (writen, memo.writen); -- pragma translate_off iosn_pad : outpad generic map (tech => padtech) port map (iosn, memo.iosn); -- pragma translate_on -- ssram_adv_n_pad : outpad generic map (tech => padtech) -- port map (ssram_adv_n, vcc(0)); -- ssram_adsp_n_pad : outpad generic map (tech => padtech) -- port map (ssram_adsp_n, gnd(0)); ssram_adscn_pad : outpad generic map (tech => padtech) port map (ssram_adscn, gnd(0)); ssrams_pad : outpad generic map ( tech => padtech) port map (ssram_cen, memo.ramsn(0)); ssram_oen_pad : outpad generic map (tech => padtech) port map (ssram_oen, memo.oen); ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech) port map (ssram_bw, memo.wrn); ssram_wri_pad : outpad generic map (tech => padtech) port map (ssram_wen, memo.writen); data_pad : iopadvv generic map (tech => padtech, width => 32) port map (data(31 downto 0), memo.data(31 downto 0), memo.vbdrive, memi.data(31 downto 0)); end generate; ddrsp0 : if (CFG_DDRSP /= 0) generate ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech, hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1, pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000, col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1) port map ( resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3), ddr_clkv, ddr_clkbv, open, gnd(0), ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq); ddr_ad <= ddr_adl(12 downto 0); ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0); ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0); end generate; ddrsp1 : if (CFG_DDRSP = 0) generate ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1'; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.ctsn <= '0'; u1i.extclk <= '0'; upads : if CFG_AHB_UART = 0 generate u1i.rxd <= rxd1; txd1 <= u1o.txd; end generate; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit grgpio0: grgpio generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH) port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5), gpioi => gpioi, gpioo => gpioo); pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate gpioi.din(i) <= gpio(i); end generate; end generate; ----------------------------------------------------------------------- --- AHB ROM ---------------------------------------------------------- ----------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(6)); end generate; nobpromgen : if CFG_AHBROMEN = 0 generate ahbso(6) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ahbramgen : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE) port map (rstn, clkm, ahbsi, ahbso(7)); end generate; nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate ahbmo(i) <= ahbm_none; end generate; -- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate; -- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate; -- invert signal for input via a key dsubre <= not dsubren; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 Altera EP3C25 SSRAM/DDR Demonstration design", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on end;

gpl-2.0

9933416715f5a756b34e28b1a3a3e727

dsaves/dsaves-hdl

crypto/aes_256/aes_256_core.vhdl

--MIT License -- --Copyright (c) 2017 Danny Savory -- --Permission is hereby granted, free of charge, to any person obtaining a copy --of this software and associated documentation files (the "Software"), to deal --in the Software without restriction, including without limitation the rights --to use, copy, modify, merge, publish, distribute, sublicense, and/or sell --copies of the Software, and to permit persons to whom the Software is --furnished to do so, subject to the following conditions: -- --The above copyright notice and this permission notice shall be included in all --copies or substantial portions of the Software. -- --THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR --IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, --FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE --AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER --LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, --OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE --SOFTWARE. -- ############################################################################ -- The official specifications of the SHA-256 algorithm can be found here: -- http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.aes_256_pkg.all; entity aes_256_core is generic( RST_ASSERT : std_logic := '1'; --reset assertion value CLK_ASSERT : std_logic := '1'; --clock assertion value BLOCK_SIZE : natural := 128 --AES block size is 128 bits ); port( clk : in std_logic; rst : in std_logic; data_in : in std_logic_vector(BLOCK_SIZE-1 downto 0); data_out : out std_logic_vector(BLOCK_SIZE-1 downto 0) ); end entity; architecture aes_256_core_ARCH of aes_256_core is constant KEY_SIZE : natural := 256; -- AES-256 has a 256-bit key size type AES_STATE is (RESET, IDLE, SUB_BYTES, SHIFT_ROWS, MIX_COLUMNS, ADD_ROUND_KEY, FINISHED); signal CURRENT_STATE, NEXT_STATE : AES_STATE; begin --CURRENT_STATE ASSIGNMENT process(clk, rst) begin if(rst=RST_ASSERT) then CURRENT_STATE <= RESET; elsif(clk'event and clk=CLK_ASSERT) then CURRENT_STATE <= NEXT_STATE; end if; end process; --TODO: fix dummy output data_out <= (others => '0'); end architecture;

mit

4baec47827be416287e6f7ed8c9e2d6d

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ac701/config.vhd

----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench configuration -- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------ library techmap; use techmap.gencomp.all; package config is -- Technology and synthesis options constant CFG_FABTECH : integer := artix7; constant CFG_MEMTECH : integer := artix7; constant CFG_PADTECH : integer := artix7; constant CFG_NOASYNC : integer := 0; constant CFG_SCAN : integer := 0; -- Clock generator constant CFG_CLKTECH : integer := artix7; constant CFG_CLKMUL : integer := (4); constant CFG_CLKDIV : integer := (8); constant CFG_OCLKDIV : integer := 1; constant CFG_OCLKBDIV : integer := 0; constant CFG_OCLKCDIV : integer := 0; constant CFG_PCIDLL : integer := 0; constant CFG_PCISYSCLK: integer := 0; constant CFG_CLK_NOFB : integer := 0; -- LEON3 processor core constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); constant CFG_V8 : integer := 2 + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 1; constant CFG_SVT : integer := 1; constant CFG_RSTADDR : integer := 16#00000#; constant CFG_LDDEL : integer := (1); constant CFG_NOTAG : integer := 0; constant CFG_NWP : integer := (2); constant CFG_PWD : integer := 1*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; constant CFG_ISETS : integer := 2; constant CFG_ISETSZ : integer := 4; constant CFG_ILINE : integer := 4; constant CFG_IREPL : integer := 2; constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; constant CFG_ILRAMSZ : integer := 1; constant CFG_DCEN : integer := 1; constant CFG_DSETS : integer := 2; constant CFG_DSETSZ : integer := 4; constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; constant CFG_DLRAMSZ : integer := 1; constant CFG_MMUEN : integer := 1; constant CFG_ITLBNUM : integer := 8; constant CFG_DTLBNUM : integer := 8; constant CFG_TLB_TYPE : integer := 0 + 1*2; constant CFG_TLB_REP : integer := 0; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 1; constant CFG_ITBSZ : integer := 4; constant CFG_ATBSZ : integer := 4; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; constant CFG_RF_ERRINJ : integer := 0; constant CFG_CACHE_FT_EN : integer := 0; constant CFG_CACHE_ERRINJ : integer := 0; constant CFG_LEON3_NETLIST: integer := 0; constant CFG_DISAS : integer := 0 + 0; constant CFG_PCLOW : integer := 2; -- AMBA settings constant CFG_DEFMST : integer := (0); constant CFG_RROBIN : integer := 1; constant CFG_SPLIT : integer := 0; constant CFG_FPNPEN : integer := 1; constant CFG_AHBIO : integer := 16#FFF#; constant CFG_APBADDR : integer := 16#800#; constant CFG_AHB_MON : integer := 0; constant CFG_AHB_MONERR : integer := 0; constant CFG_AHB_MONWAR : integer := 0; constant CFG_AHB_DTRACE : integer := 0; -- DSU UART constant CFG_AHB_UART : integer := 1; -- JTAG based DSU interface constant CFG_AHB_JTAG : integer := 1; -- Ethernet DSU constant CFG_DSU_ETH : integer := 0 + 0 + 0; constant CFG_ETH_BUF : integer := 1; constant CFG_ETH_IPM : integer := 16#C0A8#; constant CFG_ETH_IPL : integer := 16#0033#; constant CFG_ETH_ENM : integer := 16#020000#; constant CFG_ETH_ENL : integer := 16#000009#; -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 1; constant CFG_MCTRL_RAM8BIT : integer := 1; constant CFG_MCTRL_RAM16BIT : integer := 1; constant CFG_MCTRL_5CS : integer := 0; constant CFG_MCTRL_SDEN : integer := 0; constant CFG_MCTRL_SEPBUS : integer := 0; constant CFG_MCTRL_INVCLK : integer := 0; constant CFG_MCTRL_SD64 : integer := 0; constant CFG_MCTRL_PAGE : integer := 0 + 0; -- Xilinx MIG constant CFG_MIG_DDR2 : integer := 0; constant CFG_MIG_RANKS : integer := 1; constant CFG_MIG_COLBITS : integer := 10; constant CFG_MIG_ROWBITS : integer := 13; constant CFG_MIG_BANKBITS: integer := 2; constant CFG_MIG_HMASK : integer := 16#F00#; -- Xilinx MIG Series 7 constant CFG_MIG_SERIES7 : integer := 1; constant CFG_MIG_SERIES7_MODEL : integer := 0; -- AHB status register constant CFG_AHBSTAT : integer := 0; constant CFG_AHBSTATN : integer := 1; -- AHB ROM constant CFG_AHBROMEN : integer := 0; constant CFG_AHBROPIP : integer := 0; constant CFG_AHBRODDR : integer := 16#000#; constant CFG_ROMADDR : integer := 16#000#; constant CFG_ROMMASK : integer := 16#E00# + 16#000#; -- AHB RAM constant CFG_AHBRAMEN : integer := 1; constant CFG_AHBRSZ : integer := 4; constant CFG_AHBRADDR : integer := 16#A00#; constant CFG_AHBRPIPE : integer := 0; -- Gaisler Ethernet core constant CFG_GRETH : integer := 0; constant CFG_GRETH1G : integer := 0; constant CFG_ETH_FIFO : integer := 8; constant CFG_GRETH_FT : integer := 0; constant CFG_GRETH_EDCLFT : integer := 0; -- UART 1 constant CFG_UART1_ENABLE : integer := 1; constant CFG_UART1_FIFO : integer := 32; -- LEON3 interrupt controller constant CFG_IRQ3_ENABLE : integer := 1; constant CFG_IRQ3_NSEC : integer := 0; -- Modular timer constant CFG_GPT_ENABLE : integer := 1; constant CFG_GPT_NTIM : integer := (2); constant CFG_GPT_SW : integer := (8); constant CFG_GPT_TW : integer := (32); constant CFG_GPT_IRQ : integer := (8); constant CFG_GPT_SEPIRQ : integer := 1; constant CFG_GPT_WDOGEN : integer := 0; constant CFG_GPT_WDOG : integer := 16#0#; -- GPIO port constant CFG_GRGPIO_ENABLE : integer := 1; constant CFG_GRGPIO_IMASK : integer := 16#0000#; constant CFG_GRGPIO_WIDTH : integer := (7); -- I2C master constant CFG_I2C_ENABLE : integer := 1; -- VGA and PS2/ interface constant CFG_KBD_ENABLE : integer := 0; constant CFG_VGA_ENABLE : integer := 0; constant CFG_SVGA_ENABLE : integer := 0; -- SPI memory controller constant CFG_SPIMCTRL : integer := 1; constant CFG_SPIMCTRL_SDCARD : integer := 0; constant CFG_SPIMCTRL_READCMD : integer := 16#0B#; constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0; constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0; constant CFG_SPIMCTRL_SCALER : integer := (1); constant CFG_SPIMCTRL_ASCALER : integer := (8); constant CFG_SPIMCTRL_PWRUPCNT : integer := (0); constant CFG_SPIMCTRL_OFFSET : integer := 16#0#; -- SPI controller constant CFG_SPICTRL_ENABLE : integer := 0; constant CFG_SPICTRL_NUM : integer := 1; constant CFG_SPICTRL_SLVS : integer := 1; constant CFG_SPICTRL_FIFO : integer := 1; constant CFG_SPICTRL_SLVREG : integer := 0; constant CFG_SPICTRL_ODMODE : integer := 0; constant CFG_SPICTRL_AM : integer := 0; constant CFG_SPICTRL_ASEL : integer := 0; constant CFG_SPICTRL_TWEN : integer := 0; constant CFG_SPICTRL_MAXWLEN : integer := 0; constant CFG_SPICTRL_SYNCRAM : integer := 0; constant CFG_SPICTRL_FT : integer := 0; -- GRLIB debugging constant CFG_DUART : integer := 0; end;

gpl-2.0

41f6e7fe717cfef807a4bdbdec14db81

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-altera-de2-ep2c35/clkgen_de2.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library techmap; use techmap.gencomp.all; library altera_mf; -- pragma translate_off use altera_mf.altpll; -- pragma translate_on entity clkgen_de2 is generic ( clk_mul : integer := 1; clk_div : integer := 1; clk_freq : integer := 25000; clk2xen : integer := 0; sdramen : integer := 0 ); port ( inclk0 : in std_ulogic; c0 : out std_ulogic; c0_2x : out std_ulogic; e0 : out std_ulogic; locked : out std_ulogic ); end; architecture rtl of clkgen_de2 is component altpll generic ( intended_device_family : string := "Stratix" ; operation_mode : string := "NORMAL" ; compensate_clock : string := "CLK0" ; inclk0_input_frequency : positive; width_clock : positive := 6; clk0_multiply_by : positive := 1; clk0_divide_by : positive := 1; clk1_multiply_by : positive := 1; clk1_divide_by : positive := 1; clk2_multiply_by : positive := 1; clk2_divide_by : positive := 1 ); port ( inclk : in std_logic_vector(1 downto 0); clk : out std_logic_vector(width_clock-1 downto 0); locked : out std_logic ); end component; signal clkout : std_logic_vector (5 downto 0); signal inclk : std_logic_vector (1 downto 0); constant clk_period : integer := 1000000000/clk_freq; constant CLK_MUL2X : integer := clk_mul * 2; begin inclk <= '0' & inclk0; c0 <= clkout(0); c0_2x <= clkout(1); sden : if sdramen = 1 generate altpll0 : altpll generic map ( intended_device_family => "Cyclone II", operation_mode => "ZERO_DELAY_BUFFER", compensate_clock => "CLK2", inclk0_input_frequency => clk_period, clk0_multiply_by => clk_mul, clk0_divide_by => clk_div, clk1_multiply_by => 5, clk1_divide_by => 10, clk2_multiply_by => clk_mul, clk2_divide_by => clk_div) port map (inclk => inclk, clk => clkout, locked => locked); e0 <= clkout(2); end generate; nosd : if sdramen = 0 generate altpll0 : altpll generic map ( intended_device_family => "Cyclone II", operation_mode => "NORMAL", inclk0_input_frequency => clk_period, clk0_multiply_by => clk_mul, clk0_divide_by => clk_div, clk1_multiply_by => 5, clk1_divide_by => 10) port map (inclk => inclk, clk => clkout, locked => locked); e0 <= '0'; end generate; end;

gpl-2.0

9c64dd6c0bf23f529cb8e81144b9c976

a4a881d4/ringbus4xilinx

src/cbus/CMaster.vhd

--------------------------------------------------------------------------------------------------- -- -- Title : Control Bus Master -- Design : Ring Bus -- Author : Zhao Ming -- Company : a4a881d4 -- --------------------------------------------------------------------------------------------------- -- -- File : CMaster.vhd -- Generated : 2013/9/13 -- From : -- By : -- --------------------------------------------------------------------------------------------------- -- -- Description : Control bus master -- -- Rev: 3.1 -- --------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library work; use work.rb_config.all; use work.contr_config.all; entity CMaster is generic( Bwidth : natural := 16; POS : natural := 0; MyBusID : natural := 0 ); port( -- system clk : in STD_LOGIC; rst : in STD_LOGIC; -- send to bus tx: out std_logic_vector(Bwidth-1 downto 0); Req : out std_logic; tx_sop : in std_logic; en : in std_logic; -- read from bus rx_sop : in std_logic; rx: in std_logic_vector(Bwidth-1 downto 0); -- Local Bus CS : in std_logic; addr : in std_logic_vector(3 downto 0); Din : in STD_LOGIC_VECTOR(7 downto 0); Dout : out STD_LOGIC_VECTOR(7 downto 0); cpuClk : in std_logic; wr : in std_logic; rd : in std_logic -- ); end CMaster; architecture behave of CMaster is signal addr_cpu : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0'); signal word3_cpu : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0'); signal cs_wr : std_logic := '0'; signal inCommand : std_logic_vector( command_end downto command_start ) := (others => '0'); signal inDBUSID : std_logic_vector( dbusid_end downto dbusid_start ) := (others => '0'); signal inAddr : std_logic_vector( daddr_end downto daddr_start ) := (others => '0'); signal inTag, returnTag, rdTag : std_logic_vector( len_length-1 downto 0 ) := ( others=>'0' ); signal TagState : std_logic_vector( 2**len_length-1 downto 0 ) := ( others=>'0' ); signal req_cpu : std_logic := '0'; signal tstate,rstate : natural := 0; signal busy_i : std_logic := '0'; signal tagen : std_logic := '0'; signal TagData : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0'); component AAI generic( width : natural := 32; Baddr : std_logic_vector( 3 downto 0 ) := "0000" ); port( -- system signal rst : in STD_LOGIC; -- CPU bus CS : in std_logic; addr : in std_logic_vector( 3 downto 0 ); Din : in std_logic_vector( 7 downto 0 ); cpuClk : in std_logic; Q : out std_logic_vector( width-1 downto 0 ) ); end component; component blockdram generic( depth: integer := 256; Dwidth: integer := 8; Awidth: integer := 8 ); port( addra: IN std_logic_VECTOR(Awidth-1 downto 0); clka: IN std_logic; addrb: IN std_logic_VECTOR(Awidth-1 downto 0); clkb: IN std_logic; dia: IN std_logic_VECTOR(Dwidth-1 downto 0); wea: IN std_logic; reb: IN std_logic; dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0') ); end component; begin cs_wr <= cs and wr; ADDR_AAI:AAI generic map( width => Bwidth, Baddr => reg_Control_ADDR ) port map( rst => rst, CS => cs_wr, addr => addr, Din => Din, cpuClk => cpuClk, Q => addr_cpu ); DATA_AAI:AAI generic map( width => Bwidth, Baddr => reg_Control_DATA ) port map( rst => rst, CS => cs_wr, addr => addr, Din => Din, cpuClk => cpuClk, Q => word3_cpu ); tagmem:blockdram generic map( depth => 2**len_length, Dwidth => Bwidth, Awidth => len_length ) port map( addra => returnTag, clka => clk, addrb => rdTag, clkb => clk, dia => rx, wea => tagen, reb => '1', dob => TagData ); cpuwriteP:process( cpuClk, rst, tstate ) begin if rst='1' then inAddr<=( others=>'0' ); inDBUSID<=( others=>'0' ); inCommand<=( others=>'0' ); inTag<=( others=>'0' ); rdTag<=( others=>'0' ); elsif rising_edge(cpuClk) then if cs_wr='1' then case addr is when reg_Control_BADDR => inAddr<=Din( addr_length-1 downto 0 ); when reg_Control_BID => inDBUSID<=Din( busid_length-1 downto 0 ); when reg_Control_Tag => inTag<=Din( len_length-1 downto 0 ); when reg_Control_rdTag => rdTag<=Din( len_length-1 downto 0 ); when reg_Control_Command => inCommand<=Din( command_length-1 downto 0 ); when others => null; end case; end if; end if; if tstate=state_loading then req_cpu<='0'; elsif rising_edge(cpuClk) then if cs_wr='1' and addr=reg_Control_START then req_cpu<='1'; end if; end if; end process; TagStateP:process(clk,rst) begin if rst='1' then TagState<=( others=>'0' ); elsif rising_edge(clk) then if tstate=state_ADDR and inCommand=command_read then TagState(conv_integer(inTag))<='1'; end if; if tagen='1' then TagState(conv_integer(returnTag))<='0'; end if; end if; end process; FSMT:process(clk,rst) begin if rst='1' then tstate<=state_IDLE; req<='0'; busy_i<='0'; tx <= zeros( Bwidth-1 downto 0 ); elsif rising_edge(clk) then case tstate is when state_IDLE => if req_cpu='1' then tstate<=state_LOADING; busy_i<='1'; else busy_i<='0'; end if; req<='0'; when state_LOADING => tx( command_end downto command_start )<=inCommand; tx( dbusid_end downto dbusid_start )<=inDBUSID; tx( daddr_end downto daddr_start )<=inAddr; tx( len_end downto len_start ) <= zeros(len_end downto len_start)+2; req<='1'; tstate<=state_SENDING; when state_SENDING => if en='1' and tx_sop='1' then tx<=addr_cpu; tstate<=state_ADDR; req<='0'; end if; when state_ADDR => if inCommand=command_write then tx<=word3_cpu; else tx( command_end downto command_start )<=command_complete; tx( dbusid_end downto dbusid_start )<=zeros( dbusid_end downto dbusid_start )+MyBusID; tx( daddr_end downto daddr_start )<=zeros( daddr_end downto daddr_start )+POS; tx( len_end downto len_start )<=inTag; end if; tstate<=state_IDLE; busy_i<='0'; when others => req<='0'; tstate<=state_IDLE; end case; end if; end process; FSMR:process(clk,rst) begin if rst='1' then rstate<=state_IDLE; returnTag<=( others=>'0' ); tagen<='0'; elsif rising_edge(clk) then case rstate is when state_IDLE => if rx_sop='1' and rx( command_end downto command_start )=command_complete then rstate<=state_ADDR; tagen<='0'; end if; tagen<='0'; when state_ADDR => returnTag<=rx( len_end downto len_start ); tagen<='1'; rstate<=state_IDLE; when others => rstate<=state_IDLE; end case; end if; end process; rdP:process(rd,addr,cs,rdTag) begin if rd='1' and cs='1' then case addr is when reg_Control_Busy => Dout(0)<=busy_i; Dout( 7 downto 1 )<=(others=>'Z'); when reg_Control_TagState => Dout(0)<=TagState(conv_integer(rdTag)); Dout( 7 downto 1 )<=(others=>'Z'); when reg_Control_TagData => Dout<=TagData( 7 downto 0 ); when others => Dout<=(others=>'Z'); end case; end if; end process; end behave;

gpl-2.0

5c660123aaa14c8eab7c7f3cd4679e5d

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/6ad8981a62bd9ad5/ip_design_auto_pc_0_sim_netlist.vhdl

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 19:51:15 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_auto_pc_0_sim_netlist.vhdl -- Design : ip_design_auto_pc_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd is port ( next_pending_r_reg_0 : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); \m_axi_awaddr[11]\ : out STD_LOGIC; \m_axi_awaddr[3]\ : out STD_LOGIC; \m_axi_awaddr[2]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_rep\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd is signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal next_pending_r_i_5_n_0 : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair122"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair122"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_1\ : label is "soft_lutpair118"; begin \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(9 downto 0) <= \^axaddr_incr_reg[11]_0\(9 downto 0); \axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\; \axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_7\, O => p_1_in(0) ); \axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(10), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_5\, O => p_1_in(10) ); \axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \state_reg[1]_rep\, O => \axaddr_incr[11]_i_1_n_0\ ); \axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(11), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_4\, O => p_1_in(11) ); \axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_6\, O => p_1_in(1) ); \axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_5\, O => p_1_in(2) ); \axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_4\, O => p_1_in(3) ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"0009" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \state_reg[1]_rep\, I2 => \m_payload_i_reg[46]\(4), I3 => \m_payload_i_reg[46]\(5), O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_incr_reg_n_0_[3]\, I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(4), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[2]\, I1 => \m_payload_i_reg[46]\(4), I2 => \m_payload_i_reg[46]\(5), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(1), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(4), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(4), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"9AAA" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \state_reg[1]_rep\, I2 => \m_payload_i_reg[46]\(4), I3 => \m_payload_i_reg[46]\(5), O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"0A9A" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \state_reg[1]_rep\, I2 => \m_payload_i_reg[46]\(5), I3 => \m_payload_i_reg[46]\(4), O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"009A" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \state_reg[1]_rep\, I2 => \m_payload_i_reg[46]\(4), I3 => \m_payload_i_reg[46]\(5), O => S(1) ); \axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(4), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_7\, O => p_1_in(4) ); \axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(5), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_6\, O => p_1_in(5) ); \axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(6), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_5\, O => p_1_in(6) ); \axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(7), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_4\, O => p_1_in(7) ); \axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(8), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_7\, O => p_1_in(8) ); \axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(9), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_6\, O => p_1_in(9) ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(0), Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(10), Q => \^axaddr_incr_reg[11]_0\(8), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(11), Q => \^axaddr_incr_reg[11]_0\(9), R => '0' ); \axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4_n_4\, O(2) => \axaddr_incr_reg[11]_i_4_n_5\, O(1) => \axaddr_incr_reg[11]_i_4_n_6\, O(0) => \axaddr_incr_reg[11]_i_4_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(9 downto 6) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(1), Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(2), Q => \axaddr_incr_reg_n_0_[2]\, R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(3), Q => \axaddr_incr_reg_n_0_[3]\, R => '0' ); \axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3_n_3\, CYINIT => '0', DI(3) => \axaddr_incr_reg_n_0_[3]\, DI(2) => \axaddr_incr_reg_n_0_[2]\, DI(1 downto 0) => \^axaddr_incr_reg[11]_0\(1 downto 0), O(3) => \axaddr_incr_reg[3]_i_3_n_4\, O(2) => \axaddr_incr_reg[3]_i_3_n_5\, O(1) => \axaddr_incr_reg[3]_i_3_n_6\, O(0) => \axaddr_incr_reg[3]_i_3_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(4), Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(5), Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(6), Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(7), Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3_n_4\, O(2) => \axaddr_incr_reg[7]_i_3_n_5\, O(1) => \axaddr_incr_reg[7]_i_3_n_6\, O(0) => \axaddr_incr_reg[7]_i_3_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(5 downto 2) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(8), Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => p_1_in(9), Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"44444F4444444444" ) port map ( I0 => \axlen_cnt_reg_n_0_[0]\, I1 => \^axlen_cnt_reg[0]_0\, I2 => Q(1), I3 => si_rs_awvalid, I4 => Q(0), I5 => \m_payload_i_reg[46]\(7), O => \axlen_cnt[0]_i_1__1_n_0\ ); \axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(8), I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[1]_i_1_n_0\ ); \axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F8F8F88F88888888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(9), I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[2]_i_1_n_0\ ); \axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA90000FFFFFFFF" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^axlen_cnt_reg[0]_0\, I5 => \m_payload_i_reg[47]\, O => \axlen_cnt[3]_i_2__0_n_0\ ); \axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[4]_i_1_n_0\ ); \axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[4]\, I5 => \axlen_cnt_reg_n_0_[3]\, O => \axlen_cnt[5]_i_1_n_0\ ); \axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[6]_i_1_n_0\ ); \axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt_reg_n_0_[6]\, I3 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[7]_i_2_n_0\ ); \axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[0]\, O => \axlen_cnt[7]_i_3_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[0]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[4]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[5]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[6]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[7]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[0]_rep\ ); \m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \m_payload_i_reg[46]\(6), O => \m_axi_awaddr[11]\ ); \m_axi_awaddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[2]\, I2 => \m_payload_i_reg[46]\(6), I3 => \m_payload_i_reg[46]\(2), O => \m_axi_awaddr[2]\ ); \m_axi_awaddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[3]\, I2 => \m_payload_i_reg[46]\(6), I3 => \m_payload_i_reg[46]\(3), O => \m_axi_awaddr[3]\ ); \next_pending_r_i_4__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[7]\, I4 => next_pending_r_i_5_n_0, O => \^axlen_cnt_reg[0]_0\ ); next_pending_r_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[4]\, I3 => \axlen_cnt_reg_n_0_[3]\, O => next_pending_r_i_5_n_0 ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => incr_next_pending, Q => next_pending_r_reg_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 is port ( incr_next_pending : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); \m_axi_araddr[11]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \m_payload_i_reg[44]\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); si_rs_arvalid : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_14_b2s_incr_cmd"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 is signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC; signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2__1_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC; signal next_pending_r_i_4_n_0 : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__2\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \next_pending_r_i_2__1\ : label is "soft_lutpair6"; begin Q(11 downto 0) <= \^q\(11 downto 0); \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\; incr_next_pending <= \^incr_next_pending\; \axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_7\, O => \axaddr_incr[0]_i_1__0_n_0\ ); \axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_5\, O => \axaddr_incr[10]_i_1__0_n_0\ ); \axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_4\, O => \axaddr_incr[11]_i_2__0_n_0\ ); \axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_6\, O => \axaddr_incr[1]_i_1__0_n_0\ ); \axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_5\, O => \axaddr_incr[2]_i_1__0_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"0202010202020202" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \m_payload_i_reg[46]\(4), I2 => \m_payload_i_reg[46]\(5), I3 => m_axi_arready, I4 => \state_reg[1]_0\(1), I5 => \state_reg[1]_0\(0), O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^q\(3), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(4), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^q\(2), I1 => \m_payload_i_reg[46]\(4), I2 => \m_payload_i_reg[46]\(5), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^q\(1), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(4), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^q\(0), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(4), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_4\, O => \axaddr_incr[3]_i_1__0_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAA6AAAAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \m_payload_i_reg[46]\(4), I2 => \m_payload_i_reg[46]\(5), I3 => m_axi_arready, I4 => \state_reg[1]_0\(1), I5 => \state_reg[1]_0\(0), O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"2A2A262A2A2A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(4), I3 => m_axi_arready, I4 => \state_reg[1]_0\(1), I5 => \state_reg[1]_0\(0), O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"0A0A060A0A0A0A0A" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \m_payload_i_reg[46]\(4), I2 => \m_payload_i_reg[46]\(5), I3 => m_axi_arready, I4 => \state_reg[1]_0\(1), I5 => \state_reg[1]_0\(0), O => S(1) ); \axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_7\, O => \axaddr_incr[4]_i_1__0_n_0\ ); \axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_6\, O => \axaddr_incr[5]_i_1__0_n_0\ ); \axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_5\, O => \axaddr_incr[6]_i_1__0_n_0\ ); \axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_4\, O => \axaddr_incr[7]_i_1__0_n_0\ ); \axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_7\, O => \axaddr_incr[8]_i_1__0_n_0\ ); \axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_6\, O => \axaddr_incr[9]_i_1__0_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[0]_i_1__0_n_0\, Q => \^q\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[10]_i_1__0_n_0\, Q => \^q\(10), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[11]_i_2__0_n_0\, Q => \^q\(11), R => '0' ); \axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\, O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\, O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\, O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\, S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[1]_i_1__0_n_0\, Q => \^q\(1), R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[2]_i_1__0_n_0\, Q => \^q\(2), R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[3]_i_1__0_n_0\, Q => \^q\(3), R => '0' ); \axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => \^q\(3 downto 0), O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[4]_i_1__0_n_0\, Q => \^q\(4), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[5]_i_1__0_n_0\, Q => \^q\(5), R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[6]_i_1__0_n_0\, Q => \^q\(6), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[7]_i_1__0_n_0\, Q => \^q\(7), R => '0' ); \axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\, S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[8]_i_1__0_n_0\, Q => \^q\(8), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[9]_i_1__0_n_0\, Q => \^q\(9), R => '0' ); \axlen_cnt[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20FF2020" ) port map ( I0 => si_rs_arvalid, I1 => \state_reg[0]_rep\, I2 => \m_payload_i_reg[46]\(7), I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[0]_i_1_n_0\ ); \axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(8), I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[1]_i_1__1_n_0\ ); \axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"F8F8F88F88888888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(9), I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[2]_i_1__1_n_0\ ); \axlen_cnt[3]_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA90000FFFFFFFF" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^axlen_cnt_reg[0]_0\, I5 => \m_payload_i_reg[47]\, O => \axlen_cnt[3]_i_2__1_n_0\ ); \axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[7]\, I4 => next_pending_r_i_4_n_0, O => \^axlen_cnt_reg[0]_0\ ); \axlen_cnt[4]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[3]\, O => \axlen_cnt[4]_i_1__2_n_0\ ); \axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[3]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[4]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[5]_i_1__0_n_0\ ); \axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"A6" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt[7]_i_3__0_n_0\, I2 => \axlen_cnt_reg_n_0_[5]\, O => \axlen_cnt[6]_i_1__0_n_0\ ); \axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt_reg_n_0_[6]\, I3 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[7]_i_2__0_n_0\ ); \axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[1]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[0]\, O => \axlen_cnt[7]_i_3__0_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_2__1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[4]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[1]\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[5]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[1]\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[6]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[1]\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[7]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[1]\ ); \m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \m_payload_i_reg[46]\(6), O => \m_axi_araddr[11]\ ); \next_pending_r_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF505C" ) port map ( I0 => \next_pending_r_i_2__1_n_0\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => E(0), I4 => \m_payload_i_reg[44]\, O => \^incr_next_pending\ ); \next_pending_r_i_2__1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => next_pending_r_i_4_n_0, I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, O => \next_pending_r_i_2__1_n_0\ ); next_pending_r_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[4]\, I3 => \axlen_cnt_reg_n_0_[1]\, O => next_pending_r_i_4_n_0 ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^incr_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); D : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[0]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axburst_eq0_reg : out STD_LOGIC; wrap_next_pending : out STD_LOGIC; sel_first_i : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; r_push_r_reg : out STD_LOGIC; \axlen_cnt_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; \axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; \m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \axlen_cnt_reg[6]\ : in STD_LOGIC; s_axburst_eq1_reg_0 : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[35]\ : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[35]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[44]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC; incr_next_pending : in STD_LOGIC; \m_payload_i_reg[44]_0\ : in STD_LOGIC; \axlen_cnt_reg[3]\ : in STD_LOGIC; next_pending_r_reg : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^m_payload_i_reg[0]\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^r_push_r_reg\ : STD_LOGIC; signal \^sel_first_i\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[0]\ : STD_LOGIC; signal \^wrap_next_pending\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \state[1]_i_1__0\ : label is "soft_lutpair1"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair2"; begin E(0) <= \^e\(0); Q(1 downto 0) <= \^q\(1 downto 0); \axaddr_offset_r_reg[0]\(0) <= \^axaddr_offset_r_reg[0]\(0); \m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\; \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; r_push_r_reg <= \^r_push_r_reg\; sel_first_i <= \^sel_first_i\; \wrap_cnt_r_reg[0]\ <= \^wrap_cnt_r_reg[0]\; wrap_next_pending <= \^wrap_next_pending\; \wrap_second_len_r_reg[3]\(1 downto 0) <= \^wrap_second_len_r_reg[3]\(1 downto 0); \axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AEAA" ) port map ( I0 => sel_first, I1 => \^m_payload_i_reg[0]_0\, I2 => \^m_payload_i_reg[0]\, I3 => m_axi_arready, O => \axaddr_incr_reg[0]\(0) ); \axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]\(0), I1 => \m_payload_i_reg[44]\(1), I2 => \^q\(0), I3 => si_rs_arvalid, I4 => \^q\(1), I5 => \m_payload_i_reg[3]\, O => \^axaddr_offset_r_reg[0]\(0) ); \axlen_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0E02" ) port map ( I0 => si_rs_arvalid, I1 => \^q\(0), I2 => \^q\(1), I3 => m_axi_arready, O => \axlen_cnt_reg[4]\(0) ); \axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00002320" ) port map ( I0 => m_axi_arready, I1 => \^q\(1), I2 => \^q\(0), I3 => si_rs_arvalid, I4 => \axlen_cnt_reg[6]\, O => \axlen_cnt_reg[7]\ ); m_axi_arvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, O => m_axi_arvalid ); \m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"8F" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, O => \m_payload_i_reg[0]_1\(0) ); \m_valid_i_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF70FFFF" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => m_valid_i0 ); \next_pending_r_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFABEEAA" ) port map ( I0 => \m_payload_i_reg[44]_0\, I1 => \^r_push_r_reg\, I2 => \^e\(0), I3 => \axlen_cnt_reg[3]\, I4 => next_pending_r_reg, O => \^wrap_next_pending\ ); r_push_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"20" ) port map ( I0 => m_axi_arready, I1 => \^m_payload_i_reg[0]\, I2 => \^m_payload_i_reg[0]_0\, O => \^r_push_r_reg\ ); \s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => \^wrap_next_pending\, I1 => \m_payload_i_reg[44]\(0), I2 => \^sel_first_i\, I3 => incr_next_pending, O => s_axburst_eq0_reg ); \s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"ABA8" ) port map ( I0 => \^wrap_next_pending\, I1 => \m_payload_i_reg[44]\(0), I2 => \^sel_first_i\, I3 => incr_next_pending, O => s_axburst_eq1_reg ); \sel_first_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first_reg_1, I2 => \^q\(1), I3 => si_rs_arvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first, I2 => \^q\(1), I3 => si_rs_arvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first_reg_2, I2 => \^m_payload_i_reg[0]\, I3 => si_rs_arvalid, I4 => \^q\(0), I5 => areset_d1, O => \^sel_first_i\ ); \state[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000770000FFFFF0" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => m_axi_arready, I2 => si_rs_arvalid, I3 => \^q\(0), I4 => \^q\(1), I5 => \cnt_read_reg[1]_rep__0\, O => next_state(0) ); \state[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0FC00040" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => m_axi_arready, I2 => \^m_payload_i_reg[0]_0\, I3 => \^m_payload_i_reg[0]\, I4 => \cnt_read_reg[1]_rep__0\, O => next_state(1) ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => next_state(0), Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => next_state(0), Q => \^m_payload_i_reg[0]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => next_state(1), Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => next_state(1), Q => \^m_payload_i_reg[0]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => si_rs_arvalid, I2 => \^m_payload_i_reg[0]_0\, O => \^e\(0) ); \wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[3]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \^wrap_cnt_r_reg[0]\, I5 => \^axaddr_offset_r_reg[0]\(0), O => D(0) ); \wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \wrap_second_len_r_reg[2]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \^e\(0), I3 => \^wrap_cnt_r_reg[0]\, I4 => \^axaddr_offset_r_reg[0]\(0), I5 => \wrap_second_len_r_reg[2]\(0), O => D(1) ); \wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A6AA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[2]\(0), I2 => \wrap_cnt_r[3]_i_2__0_n_0\, I3 => \wrap_second_len_r_reg[2]\(1), O => D(2) ); \wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"D1D1D1D1D1D1DFD1" ) port map ( I0 => \wrap_second_len_r_reg[3]_0\(0), I1 => \^e\(0), I2 => \^axaddr_offset_r_reg[0]\(0), I3 => \m_payload_i_reg[35]\, I4 => \m_payload_i_reg[47]\(1), I5 => \m_payload_i_reg[47]\(0), O => \wrap_cnt_r[3]_i_2__0_n_0\ ); \wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[3]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \^wrap_cnt_r_reg[0]\, I5 => \^axaddr_offset_r_reg[0]\(0), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000004000404" ) port map ( I0 => \^axaddr_offset_r_reg[0]\(0), I1 => \m_payload_i_reg[35]\, I2 => \m_payload_i_reg[35]_0\, I3 => \^e\(0), I4 => \axaddr_offset_r_reg[3]\(1), I5 => \m_payload_i_reg[47]\(0), O => \^wrap_cnt_r_reg[0]\ ); \wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FB00FFFFFB00FB00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\(0), I1 => \m_payload_i_reg[35]\, I2 => \m_payload_i_reg[47]\(0), I3 => \m_payload_i_reg[35]_0\, I4 => \^e\(0), I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo is port ( \cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; bvalid_i_reg : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); bresp_push : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); b_push : in STD_LOGIC; shandshake_r : in STD_LOGIC; areset_d1 : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; si_rs_bready : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); mhandshake_r : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo is signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC; signal \^bresp_push\ : STD_LOGIC; signal bvalid_i_i_2_n_0 : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \bresp_cnt[7]_i_5\ : label is "soft_lutpair127"; attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair128"; attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair128"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "; attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_3\ : label is "soft_lutpair127"; attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "; attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "; attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "; attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "; attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "; attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "; attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "; attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "; attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "; attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "; attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "; attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "; attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "; attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "; begin bresp_push <= \^bresp_push\; \cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\; \cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\; \bresp_cnt[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAABAAAA" ) port map ( I0 => areset_d1, I1 => \bresp_cnt[7]_i_3_n_0\, I2 => \bresp_cnt[7]_i_4_n_0\, I3 => \bresp_cnt[7]_i_5_n_0\, I4 => \bresp_cnt[7]_i_6_n_0\, O => SR(0) ); \bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"22F2FFFF22F222F2" ) port map ( I0 => \memory_reg[3][1]_srl4_n_0\, I1 => \bresp_cnt_reg[7]\(1), I2 => \bresp_cnt_reg[7]\(3), I3 => \memory_reg[3][3]_srl4_n_0\, I4 => \bresp_cnt_reg[7]\(0), I5 => \memory_reg[3][0]_srl4_n_0\, O => \bresp_cnt[7]_i_3_n_0\ ); \bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAEFFAE" ) port map ( I0 => \bresp_cnt_reg[7]\(4), I1 => \bresp_cnt_reg[7]\(1), I2 => \memory_reg[3][1]_srl4_n_0\, I3 => \bresp_cnt_reg[7]\(0), I4 => \memory_reg[3][0]_srl4_n_0\, O => \bresp_cnt[7]_i_4_n_0\ ); \bresp_cnt[7]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"EAFFEAEA" ) port map ( I0 => \bresp_cnt_reg[7]\(6), I1 => \^cnt_read_reg[0]_rep__0_0\, I2 => \^cnt_read_reg[1]_rep__0_0\, I3 => \bresp_cnt_reg[7]\(3), I4 => \memory_reg[3][3]_srl4_n_0\, O => \bresp_cnt[7]_i_5_n_0\ ); \bresp_cnt[7]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"00004004" ) port map ( I0 => \bresp_cnt_reg[7]\(5), I1 => mhandshake_r, I2 => \bresp_cnt_reg[7]\(2), I3 => \memory_reg[3][2]_srl4_n_0\, I4 => \bresp_cnt_reg[7]\(7), O => \bresp_cnt[7]_i_6_n_0\ ); bvalid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0444" ) port map ( I0 => areset_d1, I1 => bvalid_i_i_2_n_0, I2 => si_rs_bvalid, I3 => si_rs_bready, O => bvalid_i_reg ); bvalid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00070707" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => \^cnt_read_reg[1]_rep__0_0\, I2 => shandshake_r, I3 => Q(0), I4 => Q(1), I5 => si_rs_bvalid, O => bvalid_i_i_2_n_0 ); \cnt_read[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^bresp_push\, I1 => Q(0), I2 => shandshake_r, O => D(0) ); \cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, O => \cnt_read[0]_i_1__0_n_0\ ); \cnt_read[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"E718" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, I3 => \^cnt_read_reg[1]_rep__0_0\, O => \cnt_read[1]_i_1_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \^cnt_read_reg[0]_rep__0_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \^cnt_read_reg[1]_rep__0_0\, S => areset_d1 ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(0), Q => \memory_reg[3][0]_srl4_n_0\ ); \memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000004100" ) port map ( I0 => \bresp_cnt_reg[7]\(7), I1 => \memory_reg[3][2]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(2), I3 => mhandshake_r, I4 => \bresp_cnt_reg[7]\(5), I5 => \memory_reg[3][0]_srl4_i_2__0_n_0\, O => \^bresp_push\ ); \memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFEFFFFFFFEFFFE" ) port map ( I0 => \bresp_cnt[7]_i_3_n_0\, I1 => \bresp_cnt[7]_i_4_n_0\, I2 => \bresp_cnt_reg[7]\(6), I3 => \memory_reg[3][0]_srl4_i_3_n_0\, I4 => \bresp_cnt_reg[7]\(3), I5 => \memory_reg[3][3]_srl4_n_0\, O => \memory_reg[3][0]_srl4_i_2__0_n_0\ ); \memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => \^cnt_read_reg[1]_rep__0_0\, O => \memory_reg[3][0]_srl4_i_3_n_0\ ); \memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(6), Q => \out\(2) ); \memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(7), Q => \out\(3) ); \memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(8), Q => \out\(4) ); \memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(9), Q => \out\(5) ); \memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(10), Q => \out\(6) ); \memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(11), Q => \out\(7) ); \memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(12), Q => \out\(8) ); \memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(13), Q => \out\(9) ); \memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(14), Q => \out\(10) ); \memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(15), Q => \out\(11) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(1), Q => \memory_reg[3][1]_srl4_n_0\ ); \memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(2), Q => \memory_reg[3][2]_srl4_n_0\ ); \memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(3), Q => \memory_reg[3][3]_srl4_n_0\ ); \memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(4), Q => \out\(0) ); \memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(5), Q => \out\(1) ); \state[0]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, O => \state_reg[0]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ is port ( mhandshake : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bready : out STD_LOGIC; \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; mhandshake_r : in STD_LOGIC; shandshake_r : in STD_LOGIC; sel : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair129"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair129"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "; begin Q(1 downto 0) <= \^q\(1 downto 0); \cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9AA6" ) port map ( I0 => \^q\(1), I1 => shandshake_r, I2 => \^q\(0), I3 => sel, O => \cnt_read[1]_i_1__0_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => D(0), Q => \^q\(0), S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__0_n_0\, Q => \^q\(1), S => areset_d1 ); m_axi_bready_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => mhandshake_r, O => m_axi_bready ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[1]\(0) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[1]\(1) ); mhandshake_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => m_axi_bvalid, I1 => mhandshake_r, I2 => \^q\(1), I3 => \^q\(0), O => mhandshake ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ is port ( \cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC; wr_en0 : out STD_LOGIC; \cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); s_ready_i_reg : in STD_LOGIC; si_rs_rready : in STD_LOGIC; \cnt_read_reg[3]_rep__0_0\ : in STD_LOGIC; s_ready_i_reg_0 : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal \^wr_en0\ : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair18"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]"; attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair15"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "; attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "; attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "; attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "; attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "; attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "; attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "; attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "; attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "; attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "; attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "; attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "; attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "; attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "; attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "; attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "; attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "; attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "; attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "; attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair15"; begin \cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\; \cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\; \cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\; wr_en0 <= \^wr_en0\; \cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cnt_read_reg[0]_rep__2_n_0\, I1 => s_ready_i_reg, I2 => \^wr_en0\, O => \cnt_read[0]_i_1__1_n_0\ ); \cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => \cnt_read_reg[1]_rep__2_n_0\, I1 => \cnt_read_reg[0]_rep__2_n_0\, I2 => \^wr_en0\, I3 => s_ready_i_reg, O => \cnt_read[1]_i_1__2_n_0\ ); \cnt_read[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"A6AAAA9A" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \^wr_en0\, I2 => s_ready_i_reg, I3 => \cnt_read_reg[0]_rep__2_n_0\, I4 => \cnt_read_reg[1]_rep__2_n_0\, O => \cnt_read[2]_i_1_n_0\ ); \cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAA96AAAAAAA" ) port map ( I0 => \^cnt_read_reg[3]_rep__2_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[0]_rep__2_n_0\, I3 => \cnt_read_reg[2]_rep__2_n_0\, I4 => \^wr_en0\, I5 => s_ready_i_reg, O => \cnt_read[3]_i_1__0_n_0\ ); \cnt_read[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA55AA6A6AAA6AAA" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_0\, I1 => \cnt_read[4]_i_2__0_n_0\, I2 => \cnt_read[4]_i_3_n_0\, I3 => s_ready_i_reg_0, I4 => \^cnt_read_reg[4]_rep__2_1\, I5 => \^cnt_read_reg[3]_rep__2_0\, O => \cnt_read[4]_i_1_n_0\ ); \cnt_read[4]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => \cnt_read_reg[0]_rep__2_n_0\, I1 => si_rs_rready, I2 => \cnt_read_reg[3]_rep__0_0\, I3 => \^wr_en0\, O => \cnt_read[4]_i_2__0_n_0\ ); \cnt_read[4]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cnt_read_reg[1]_rep__2_n_0\, I1 => \cnt_read_reg[2]_rep__2_n_0\, O => \cnt_read[4]_i_3_n_0\ ); \cnt_read[4]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[0]_rep__2_n_0\, I2 => \cnt_read_reg[1]_rep__2_n_0\, O => \^cnt_read_reg[4]_rep__2_1\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \^cnt_read_reg[3]_rep__2_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \^cnt_read_reg[4]_rep__2_0\, S => areset_d1 ); m_axi_rready_INST_0: unisim.vcomponents.LUT5 generic map( INIT => X"F77F777F" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_0\, I1 => \^cnt_read_reg[3]_rep__2_0\, I2 => \cnt_read_reg[2]_rep__2_n_0\, I3 => \cnt_read_reg[1]_rep__2_n_0\, I4 => \cnt_read_reg[0]_rep__2_n_0\, O => m_axi_rready ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(0), Q => \out\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA2A2AAA2A2A2AAA" ) port map ( I0 => m_axi_rvalid, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[3]_rep__2_0\, I3 => \cnt_read_reg[2]_rep__2_n_0\, I4 => \cnt_read_reg[1]_rep__2_n_0\, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \^wr_en0\ ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(10), Q => \out\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(11), Q => \out\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(12), Q => \out\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(13), Q => \out\(13), Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(14), Q => \out\(14), Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(15), Q => \out\(15), Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(16), Q => \out\(16), Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(17), Q => \out\(17), Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(18), Q => \out\(18), Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(19), Q => \out\(19), Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(1), Q => \out\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(20), Q => \out\(20), Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(21), Q => \out\(21), Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(22), Q => \out\(22), Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(23), Q => \out\(23), Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(24), Q => \out\(24), Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => \^wr_en0\, CLK => aclk, D => \in\(25), Q => \out\(25), Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => \^wr_en0\, CLK => aclk, D => \in\(26), Q => \out\(26), Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => \^wr_en0\, CLK => aclk, D => \in\(27), Q => \out\(27), Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => \^wr_en0\, CLK => aclk, D => \in\(28), Q => \out\(28), Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => \^wr_en0\, CLK => aclk, D => \in\(29), Q => \out\(29), Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(2), Q => \out\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => \^wr_en0\, CLK => aclk, D => \in\(30), Q => \out\(30), Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => \^wr_en0\, CLK => aclk, D => \in\(31), Q => \out\(31), Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => \^wr_en0\, CLK => aclk, D => \in\(32), Q => \out\(32), Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => \^wr_en0\, CLK => aclk, D => \in\(33), Q => \out\(33), Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(3), Q => \out\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(4), Q => \out\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(5), Q => \out\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(6), Q => \out\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(7), Q => \out\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(8), Q => \out\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => \^wr_en0\, CLK => aclk, D => \in\(9), Q => \out\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"7C000000" ) port map ( I0 => \cnt_read_reg[0]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[2]_rep__2_n_0\, I3 => \^cnt_read_reg[3]_rep__2_0\, I4 => \^cnt_read_reg[4]_rep__2_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2\ : out STD_LOGIC; \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); si_rs_rready : in STD_LOGIC; r_push_r : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; \cnt_read_reg[0]_rep__2\ : in STD_LOGIC; wr_en0 : in STD_LOGIC; \cnt_read_reg[3]_rep__2\ : in STD_LOGIC; \cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC; \cnt_read_reg[2]_rep__2\ : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal m_valid_i_i_3_n_0 : STD_LOGIC; signal \^m_valid_i_reg\ : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair19"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "; begin m_valid_i_reg <= \^m_valid_i_reg\; \cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cnt_read_reg[0]_rep__1_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, O => \cnt_read[0]_i_1__2_n_0\ ); \cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"E718" ) port map ( I0 => \cnt_read_reg[0]_rep__1_n_0\, I1 => r_push_r, I2 => s_ready_i_reg, I3 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[1]_i_1__1_n_0\ ); \cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FE7F0180" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__0_n_0\, I2 => r_push_r, I3 => s_ready_i_reg, I4 => \cnt_read_reg[2]_rep__0_n_0\, O => \cnt_read[2]_i_1__0_n_0\ ); \cnt_read[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"DFFFFFFB20000004" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[0]_rep__0_n_0\, I4 => \cnt_read_reg[2]_rep__0_n_0\, I5 => \cnt_read_reg[3]_rep__0_n_0\, O => \cnt_read[3]_i_1_n_0\ ); \cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9AAA9AAA9AAA9AA6" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read[4]_i_2_n_0\, I2 => \cnt_read_reg[2]_rep__0_n_0\, I3 => \cnt_read_reg[3]_rep__0_n_0\, I4 => \cnt_read[4]_i_3__0_n_0\, I5 => \cnt_read_reg[0]_rep__0_n_0\, O => \cnt_read[4]_i_1__0_n_0\ ); \cnt_read[4]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"5DFFFFFF" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => si_rs_rready, I2 => \^m_valid_i_reg\, I3 => r_push_r, I4 => \cnt_read_reg[0]_rep__1_n_0\, O => \cnt_read[4]_i_2_n_0\ ); \cnt_read[4]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => \^m_valid_i_reg\, I2 => si_rs_rready, I3 => r_push_r, O => \cnt_read[4]_i_3__0_n_0\ ); \cnt_read[4]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"4F" ) port map ( I0 => \^m_valid_i_reg\, I1 => si_rs_rready, I2 => wr_en0, O => \cnt_read_reg[4]_rep__2\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); m_valid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FF08080808080808" ) port map ( I0 => \cnt_read_reg[3]_rep__0_n_0\, I1 => \cnt_read_reg[4]_rep__0_n_0\, I2 => m_valid_i_i_3_n_0, I3 => \cnt_read_reg[3]_rep__2\, I4 => \cnt_read_reg[4]_rep__2_0\, I5 => \cnt_read_reg[2]_rep__2\, O => \^m_valid_i_reg\ ); m_valid_i_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \cnt_read_reg[0]_rep__1_n_0\, I1 => \cnt_read_reg[2]_rep__0_n_0\, I2 => \cnt_read_reg[1]_rep__0_n_0\, O => m_valid_i_i_3_n_0 ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[46]\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(10), Q => \skid_buffer_reg[46]\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(11), Q => \skid_buffer_reg[46]\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(12), Q => \skid_buffer_reg[46]\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[46]\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(2), Q => \skid_buffer_reg[46]\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(3), Q => \skid_buffer_reg[46]\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(4), Q => \skid_buffer_reg[46]\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(5), Q => \skid_buffer_reg[46]\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(6), Q => \skid_buffer_reg[46]\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(7), Q => \skid_buffer_reg[46]\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(8), Q => \skid_buffer_reg[46]\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(9), Q => \skid_buffer_reg[46]\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"BEAAAAAAFEAAAAAA" ) port map ( I0 => \cnt_read_reg[0]_rep__2\, I1 => \cnt_read_reg[1]_rep__0_n_0\, I2 => \cnt_read_reg[2]_rep__0_n_0\, I3 => \cnt_read_reg[4]_rep__0_n_0\, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[0]_rep__0_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axlen_cnt_reg[0]\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[7]\ : out STD_LOGIC; s_axburst_eq0_reg : out STD_LOGIC; wrap_next_pending : out STD_LOGIC; sel_first_i : out STD_LOGIC; incr_next_pending : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; si_rs_awvalid : in STD_LOGIC; \axlen_cnt_reg[6]\ : in STD_LOGIC; \m_payload_i_reg[39]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC; next_pending_r_reg : in STD_LOGIC; next_pending_r_reg_0 : in STD_LOGIC; \axlen_cnt_reg[1]\ : in STD_LOGIC; sel_first : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first_0 : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; s_axburst_eq1_reg_0 : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; \cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^axlen_cnt_reg[0]\ : STD_LOGIC; signal \^b_push\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^sel_first_i\ : STD_LOGIC; signal \state_reg[0]_rep_n_0\ : STD_LOGIC; signal \state_reg[1]_rep_n_0\ : STD_LOGIC; signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^wrap_next_pending\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair115"; attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair115"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair114"; begin Q(1 downto 0) <= \^q\(1 downto 0); \axlen_cnt_reg[0]\ <= \^axlen_cnt_reg[0]\; b_push <= \^b_push\; incr_next_pending <= \^incr_next_pending\; sel_first_i <= \^sel_first_i\; \wrap_boundary_axaddr_r_reg[0]\(0) <= \^wrap_boundary_axaddr_r_reg[0]\(0); wrap_next_pending <= \^wrap_next_pending\; \axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"04FF" ) port map ( I0 => \^q\(0), I1 => si_rs_awvalid, I2 => \^q\(1), I3 => \^axlen_cnt_reg[0]\, O => E(0) ); \axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"000004FF" ) port map ( I0 => \state_reg[0]_rep_n_0\, I1 => si_rs_awvalid, I2 => \state_reg[1]_rep_n_0\, I3 => \^axlen_cnt_reg[0]\, I4 => \axlen_cnt_reg[6]\, O => \axlen_cnt_reg[7]\ ); m_axi_awvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \state_reg[0]_rep_n_0\, I1 => \state_reg[1]_rep_n_0\, O => m_axi_awvalid ); \m_payload_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^b_push\, I1 => si_rs_awvalid, O => \m_payload_i_reg[0]\(0) ); \memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CFCF000045000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[0]_rep__0\, I2 => \cnt_read_reg[1]_rep__0_0\, I3 => m_axi_awready, I4 => \state_reg[0]_rep_n_0\, I5 => \state_reg[1]_rep_n_0\, O => \^b_push\ ); next_pending_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\, I1 => \^wrap_boundary_axaddr_r_reg[0]\(0), I2 => next_pending_r_reg, I3 => \^axlen_cnt_reg[0]\, I4 => \axlen_cnt_reg[6]\, O => \^incr_next_pending\ ); \next_pending_r_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B888B8BB" ) port map ( I0 => \m_payload_i_reg[46]\, I1 => \^wrap_boundary_axaddr_r_reg[0]\(0), I2 => next_pending_r_reg_0, I3 => \^axlen_cnt_reg[0]\, I4 => \axlen_cnt_reg[1]\, O => \^wrap_next_pending\ ); next_pending_r_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"5555DD551515DD15" ) port map ( I0 => \state_reg[1]_rep_n_0\, I1 => \state_reg[0]_rep_n_0\, I2 => m_axi_awready, I3 => \cnt_read_reg[1]_rep__0_0\, I4 => \cnt_read_reg[0]_rep__0\, I5 => s_axburst_eq1_reg_0, O => \^axlen_cnt_reg[0]\ ); s_axburst_eq0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => \^wrap_next_pending\, I1 => \m_payload_i_reg[39]\(0), I2 => \^sel_first_i\, I3 => \^incr_next_pending\, O => s_axburst_eq0_reg ); s_axburst_eq1_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"ABA8" ) port map ( I0 => \^wrap_next_pending\, I1 => \m_payload_i_reg[39]\(0), I2 => \^sel_first_i\, I3 => \^incr_next_pending\, O => s_axburst_eq1_reg ); sel_first_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF88888F88" ) port map ( I0 => \^axlen_cnt_reg[0]\, I1 => sel_first, I2 => \state_reg[1]_rep_n_0\, I3 => si_rs_awvalid, I4 => \state_reg[0]_rep_n_0\, I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF88888F88" ) port map ( I0 => \^axlen_cnt_reg[0]\, I1 => sel_first_0, I2 => \state_reg[1]_rep_n_0\, I3 => si_rs_awvalid, I4 => \state_reg[0]_rep_n_0\, I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF88888F88" ) port map ( I0 => \^axlen_cnt_reg[0]\, I1 => sel_first_reg_1, I2 => \state_reg[1]_rep_n_0\, I3 => si_rs_awvalid, I4 => \state_reg[0]_rep_n_0\, I5 => areset_d1, O => \^sel_first_i\ ); \state[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AEFE0E0EFEFE5E5E" ) port map ( I0 => \state_reg[1]_rep_n_0\, I1 => si_rs_awvalid, I2 => \state_reg[0]_rep_n_0\, I3 => s_axburst_eq1_reg_0, I4 => \cnt_read_reg[1]_rep__0\, I5 => m_axi_awready, O => next_state(0) ); \state[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"2E220E0000000000" ) port map ( I0 => m_axi_awready, I1 => \state_reg[1]_rep_n_0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => \cnt_read_reg[1]_rep__0_0\, I4 => s_axburst_eq1_reg_0, I5 => \state_reg[0]_rep_n_0\, O => next_state(1) ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => next_state(0), Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => next_state(0), Q => \state_reg[0]_rep_n_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => next_state(1), Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => next_state(1), Q => \state_reg[1]_rep_n_0\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \state_reg[1]_rep_n_0\, I1 => si_rs_awvalid, I2 => \state_reg[0]_rep_n_0\, O => \^wrap_boundary_axaddr_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd is port ( next_pending_r_reg_0 : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; next_pending_r_reg_1 : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); wrap_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 17 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); sel_first_reg_3 : in STD_LOGIC; sel_first_reg_4 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd is signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair126"; attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair126"; begin sel_first_reg_0 <= \^sel_first_reg_0\; \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(0), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(0), O => \axaddr_wrap[0]_i_1_n_0\ ); \axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(10), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(10), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(10), O => \axaddr_wrap[10]_i_1_n_0\ ); \axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(11), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(11), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(11), O => \axaddr_wrap[11]_i_1_n_0\ ); \axaddr_wrap[11]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFF6" ) port map ( I0 => wrap_cnt_r(3), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axaddr_wrap[11]_i_4_n_0\, I3 => \axlen_cnt_reg_n_0_[4]\, O => \axaddr_wrap[11]_i_3_n_0\ ); \axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => wrap_cnt_r(0), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => wrap_cnt_r(1), I4 => \axlen_cnt_reg_n_0_[2]\, I5 => wrap_cnt_r(2), O => \axaddr_wrap[11]_i_4_n_0\ ); \axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(1), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(1), O => \axaddr_wrap[1]_i_1_n_0\ ); \axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(2), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(2), O => \axaddr_wrap[2]_i_1_n_0\ ); \axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(3), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(3), O => \axaddr_wrap[3]_i_1_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => axaddr_wrap(3), I1 => \m_payload_i_reg[46]\(13), I2 => \m_payload_i_reg[46]\(12), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(2), I1 => \m_payload_i_reg[46]\(12), I2 => \m_payload_i_reg[46]\(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(1), I1 => \m_payload_i_reg[46]\(13), I2 => \m_payload_i_reg[46]\(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => axaddr_wrap(0), I1 => \m_payload_i_reg[46]\(13), I2 => \m_payload_i_reg[46]\(12), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(4), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(4), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(4), O => \axaddr_wrap[4]_i_1_n_0\ ); \axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(5), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(5), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(5), O => \axaddr_wrap[5]_i_1_n_0\ ); \axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(6), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(6), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(6), O => \axaddr_wrap[6]_i_1_n_0\ ); \axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(7), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(7), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(7), O => \axaddr_wrap[7]_i_1_n_0\ ); \axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(8), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(8), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(8), O => \axaddr_wrap[8]_i_1_n_0\ ); \axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \m_payload_i_reg[46]\(9), I1 => \state_reg[1]_rep\, I2 => axaddr_wrap0(9), I3 => \axaddr_wrap[11]_i_3_n_0\, I4 => wrap_boundary_axaddr_r(9), O => \axaddr_wrap[9]_i_1_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[0]_i_1_n_0\, Q => axaddr_wrap(0), R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[10]_i_1_n_0\, Q => axaddr_wrap(10), R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[11]_i_1_n_0\, Q => axaddr_wrap(11), R => '0' ); \axaddr_wrap_reg[11]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(11 downto 8), S(3 downto 0) => axaddr_wrap(11 downto 8) ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[1]_i_1_n_0\, Q => axaddr_wrap(1), R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[2]_i_1_n_0\, Q => axaddr_wrap(2), R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[3]_i_1_n_0\, Q => axaddr_wrap(3), R => '0' ); \axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => axaddr_wrap(3 downto 0), O(3 downto 0) => axaddr_wrap0(3 downto 0), S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[4]_i_1_n_0\, Q => axaddr_wrap(4), R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[5]_i_1_n_0\, Q => axaddr_wrap(5), R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[6]_i_1_n_0\, Q => axaddr_wrap(6), R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[7]_i_1_n_0\, Q => axaddr_wrap(7), R => '0' ); \axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(7 downto 4), S(3 downto 0) => axaddr_wrap(7 downto 4) ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[8]_i_1_n_0\, Q => axaddr_wrap(8), R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[9]_i_1_n_0\, Q => axaddr_wrap(9), R => '0' ); \axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"44444F4444444444" ) port map ( I0 => \axlen_cnt_reg_n_0_[0]\, I1 => \axlen_cnt[3]_i_2_n_0\, I2 => Q(1), I3 => si_rs_awvalid, I4 => Q(0), I5 => \m_payload_i_reg[46]\(15), O => \axlen_cnt[0]_i_1__2_n_0\ ); \axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(16), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt[3]_i_2_n_0\, O => \axlen_cnt[1]_i_1__0_n_0\ ); \axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"F8F8F88F88888888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(17), I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \axlen_cnt[3]_i_2_n_0\, O => \axlen_cnt[2]_i_1__0_n_0\ ); \axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA90000FFFFFFFF" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt[3]_i_2_n_0\, I5 => \m_payload_i_reg[47]\, O => \axlen_cnt[3]_i_1__1_n_0\ ); \axlen_cnt[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"55555554" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[4]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[3]_i_2_n_0\ ); \axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"4444444444444440" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[3]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[4]_i_1__0_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[0]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[4]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => '0' ); \m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(0), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_awaddr(0) ); \m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(10), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(8), O => m_axi_awaddr(10) ); \m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(11), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(9), O => m_axi_awaddr(11) ); \m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(1), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(1), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_awaddr(1) ); \m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \^sel_first_reg_0\, I2 => axaddr_wrap(2), I3 => \m_payload_i_reg[46]\(14), I4 => sel_first_reg_4, O => m_axi_awaddr(2) ); \m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \^sel_first_reg_0\, I2 => axaddr_wrap(3), I3 => \m_payload_i_reg[46]\(14), I4 => sel_first_reg_3, O => m_axi_awaddr(3) ); \m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(4), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_awaddr(4) ); \m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(5), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(5), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_awaddr(5) ); \m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(6), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_awaddr(6) ); \m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(7), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_awaddr(7) ); \m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(8), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_awaddr(8) ); \m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(9), I2 => \m_payload_i_reg[46]\(14), I3 => \m_payload_i_reg[46]\(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_awaddr(9) ); \next_pending_r_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[1]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[4]\, I3 => \axlen_cnt_reg_n_0_[3]\, O => next_pending_r_reg_1 ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_next_pending, Q => next_pending_r_reg_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => wrap_boundary_axaddr_r(0), R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[46]\(10), Q => wrap_boundary_axaddr_r(10), R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[46]\(11), Q => wrap_boundary_axaddr_r(11), R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => wrap_boundary_axaddr_r(1), R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => wrap_boundary_axaddr_r(2), R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => wrap_boundary_axaddr_r(3), R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => wrap_boundary_axaddr_r(4), R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => wrap_boundary_axaddr_r(5), R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => wrap_boundary_axaddr_r(6), R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[46]\(7), Q => wrap_boundary_axaddr_r(7), R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[46]\(8), Q => wrap_boundary_axaddr_r(8), R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[46]\(9), Q => wrap_boundary_axaddr_r(9), R => '0' ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => wrap_cnt_r(0), R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => wrap_cnt_r(1), R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => wrap_cnt_r(2), R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(3), Q => wrap_cnt_r(3), R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 is port ( next_pending_r_reg_0 : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); wrap_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 17 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); si_rs_arvalid : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \m_payload_i_reg[35]\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_14_b2s_wrap_cmd"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 is signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1__1_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_cnt_r[1]_i_1_n_0\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); begin \axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\; sel_first_reg_0 <= \^sel_first_reg_0\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[3]_i_2__0_n_7\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[0]\, I3 => \state_reg[1]_rep\, I4 => Q(0), O => \axaddr_wrap[0]_i_1__0_n_0\ ); \axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[11]_i_2__0_n_5\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[10]\, I3 => \state_reg[1]_rep\, I4 => Q(10), O => \axaddr_wrap[10]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[11]_i_2__0_n_4\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[11]\, I3 => \state_reg[1]_rep\, I4 => Q(11), O => \axaddr_wrap[11]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFF6" ) port map ( I0 => \wrap_cnt_r_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axaddr_wrap[11]_i_4__0_n_0\, I3 => \axlen_cnt_reg_n_0_[4]\, O => \axaddr_wrap[11]_i_3__0_n_0\ ); \axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => \wrap_cnt_r_reg_n_0_[0]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \wrap_cnt_r_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \wrap_cnt_r_reg_n_0_[1]\, O => \axaddr_wrap[11]_i_4__0_n_0\ ); \axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[3]_i_2__0_n_6\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[1]\, I3 => \state_reg[1]_rep\, I4 => Q(1), O => \axaddr_wrap[1]_i_1__0_n_0\ ); \axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[3]_i_2__0_n_5\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[2]\, I3 => \state_reg[1]_rep\, I4 => Q(2), O => \axaddr_wrap[2]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[3]_i_2__0_n_4\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[3]\, I3 => \state_reg[1]_rep\, I4 => Q(3), O => \axaddr_wrap[3]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[3]\, I1 => Q(13), I2 => Q(12), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[2]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[1]\, I1 => Q(13), I2 => Q(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \axaddr_wrap_reg_n_0_[0]\, I1 => Q(13), I2 => Q(12), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[7]_i_2__0_n_7\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[4]\, I3 => \state_reg[1]_rep\, I4 => Q(4), O => \axaddr_wrap[4]_i_1__0_n_0\ ); \axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[7]_i_2__0_n_6\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[5]\, I3 => \state_reg[1]_rep\, I4 => Q(5), O => \axaddr_wrap[5]_i_1__0_n_0\ ); \axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[7]_i_2__0_n_5\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[6]\, I3 => \state_reg[1]_rep\, I4 => Q(6), O => \axaddr_wrap[6]_i_1__0_n_0\ ); \axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[7]_i_2__0_n_4\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[7]\, I3 => \state_reg[1]_rep\, I4 => Q(7), O => \axaddr_wrap[7]_i_1__0_n_0\ ); \axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[11]_i_2__0_n_7\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[8]\, I3 => \state_reg[1]_rep\, I4 => Q(8), O => \axaddr_wrap[8]_i_1__0_n_0\ ); \axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \axaddr_wrap_reg[11]_i_2__0_n_6\, I1 => \axaddr_wrap[11]_i_3__0_n_0\, I2 => \wrap_boundary_axaddr_r_reg_n_0_[9]\, I3 => \state_reg[1]_rep\, I4 => Q(9), O => \axaddr_wrap[9]_i_1__0_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[0]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[0]\, R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[10]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[10]\, R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[11]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[11]\, R => '0' ); \axaddr_wrap_reg[11]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[11]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[11]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[11]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[11]_i_2__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[11]\, S(2) => \axaddr_wrap_reg_n_0_[10]\, S(1) => \axaddr_wrap_reg_n_0_[9]\, S(0) => \axaddr_wrap_reg_n_0_[8]\ ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[1]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[1]\, R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[2]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[2]\, R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[3]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[3]\, R => '0' ); \axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \axaddr_wrap_reg_n_0_[3]\, DI(2) => \axaddr_wrap_reg_n_0_[2]\, DI(1) => \axaddr_wrap_reg_n_0_[1]\, DI(0) => \axaddr_wrap_reg_n_0_[0]\, O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\, S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[4]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[4]\, R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[5]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[5]\, R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[6]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[6]\, R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[7]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[7]\, R => '0' ); \axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[7]\, S(2) => \axaddr_wrap_reg_n_0_[6]\, S(1) => \axaddr_wrap_reg_n_0_[5]\, S(0) => \axaddr_wrap_reg_n_0_[4]\ ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[8]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[8]\, R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[9]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[9]\, R => '0' ); \axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"20FF2020" ) port map ( I0 => si_rs_arvalid, I1 => \state_reg[0]_rep\, I2 => Q(15), I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[0]_i_1__0_n_0\ ); \axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => Q(16), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[1]_i_1__2_n_0\ ); \axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"F8F8F88F88888888" ) port map ( I0 => E(0), I1 => Q(17), I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[2]_i_1__2_n_0\ ); \axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA90000FFFFFFFF" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, I5 => \m_payload_i_reg[47]\, O => \axlen_cnt[3]_i_1__2_n_0\ ); \axlen_cnt[3]_i_2__2\: unisim.vcomponents.LUT5 generic map( INIT => X"55555554" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[4]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[1]\, O => \^axlen_cnt_reg[0]_0\ ); \axlen_cnt[4]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"4444444444444440" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[3]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[4]_i_1__1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[4]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => '0' ); \m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[0]\, I2 => Q(14), I3 => Q(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_araddr(0) ); \m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[10]\, I2 => Q(14), I3 => Q(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(10), O => m_axi_araddr(10) ); \m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[11]\, I2 => Q(14), I3 => Q(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(11), O => m_axi_araddr(11) ); \m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[1]\, I2 => Q(14), I3 => Q(1), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_araddr(1) ); \m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[2]\, I2 => Q(14), I3 => Q(2), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_araddr(2) ); \m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[3]\, I2 => Q(14), I3 => Q(3), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_araddr(3) ); \m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[4]\, I2 => Q(14), I3 => Q(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_araddr(4) ); \m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[5]\, I2 => Q(14), I3 => Q(5), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_araddr(5) ); \m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[6]\, I2 => Q(14), I3 => Q(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_araddr(6) ); \m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[7]\, I2 => Q(14), I3 => Q(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_araddr(7) ); \m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[8]\, I2 => Q(14), I3 => Q(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(8), O => m_axi_araddr(8) ); \m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[9]\, I2 => Q(14), I3 => Q(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(9), O => m_axi_araddr(9) ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_next_pending, Q => next_pending_r_reg_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\, R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(10), Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\, R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(11), Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\, R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\, R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\, R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\, R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\, R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\, R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\, R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(7), Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\, R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(8), Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\, R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(9), Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\, R => '0' ); \wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"313D020E" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_1\, I3 => \m_payload_i_reg[35]\, I4 => \^wrap_second_len_r_reg[3]_0\(1), O => \wrap_cnt_r[1]_i_1_n_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => \wrap_cnt_r_reg_n_0_[0]\, R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_cnt_r[1]_i_1_n_0\, Q => \wrap_cnt_r_reg_n_0_[1]\, R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => \wrap_cnt_r_reg_n_0_[2]\, R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => \wrap_cnt_r_reg_n_0_[3]\, R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice is port ( s_axi_arready : out STD_LOGIC; s_ready_i_reg_0 : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); Q : out STD_LOGIC_VECTOR ( 53 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[1]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \axaddr_offset_r_reg[0]\ : out STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; aclk : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; \aresetn_d_reg[0]_0\ : in STD_LOGIC; \m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \state_reg[1]_rep_0\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); \state_reg[1]_rep_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice is signal \^q\ : STD_LOGIC_VECTOR ( 53 downto 0 ); signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_3_n_0\ : STD_LOGIC; signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 to 3 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_3\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21"; begin Q(53 downto 0) <= \^q\(53 downto 0); \axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\; \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_arready <= \^s_axi_arready\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \aresetn_d_reg[0]_0\, Q => \^m_valid_i_reg_0\, R => '0' ); \axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(36), I2 => \^q\(35), O => \axaddr_incr[3]_i_4__0_n_0\ ); \axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5__0_n_0\ ); \axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(36), I2 => \^q\(35), O => \axaddr_incr[3]_i_6__0_n_0\ ); \axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => O(3 downto 0), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4__0_n_0\, DI(1) => \axaddr_incr[3]_i_5__0_n_0\, DI(0) => \axaddr_incr[3]_i_6__0_n_0\, O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0) ); \axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(35), I3 => \^q\(2), I4 => \^q\(36), I5 => \^q\(0), O => \axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^axaddr_offset_r_reg[1]\, O => \^axaddr_offset_r_reg[3]\(0) ); \axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"1FDF00001FDFFFFF" ) port map ( I0 => \axaddr_offset_r[1]_i_3_n_0\, I1 => \^q\(35), I2 => \^q\(40), I3 => \axaddr_offset_r[2]_i_3__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]_0\(0), O => \^axaddr_offset_r_reg[1]\ ); \axaddr_offset_r[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(3), I1 => \^q\(36), I2 => \^q\(1), O => \axaddr_offset_r[1]_i_3_n_0\ ); \axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AC00FFFFAC000000" ) port map ( I0 => \axaddr_offset_r[2]_i_2__0_n_0\, I1 => \axaddr_offset_r[2]_i_3__0_n_0\, I2 => \^q\(35), I3 => \^q\(41), I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]_0\(1), O => \^axaddr_offset_r_reg[3]\(1) ); \axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(3), O => \axaddr_offset_r[2]_i_2__0_n_0\ ); \axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(36), I2 => \^q\(2), O => \axaddr_offset_r[2]_i_3__0_n_0\ ); \axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => si_rs_arlen(3), I1 => \axaddr_offset_r[3]_i_2__0_n_0\, I2 => \state_reg[1]_rep_0\, I3 => \^s_ready_i_reg_0\, I4 => \state_reg[0]_rep\, I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^axaddr_offset_r_reg[3]\(2) ); \axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => \^q\(35), I3 => \^q\(5), I4 => \^q\(36), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => si_rs_arlen(3), I1 => \state_reg[0]_rep\, I2 => \^s_ready_i_reg_0\, I3 => \state_reg[1]_rep_0\, O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__0_n_0\ ); \m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__0_n_0\ ); \m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__0_n_0\ ); \m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(12), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__0_n_0\ ); \m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(13), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__1_n_0\ ); \m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(14), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__0_n_0\ ); \m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(15), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__0_n_0\ ); \m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(16), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__0_n_0\ ); \m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(17), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__0_n_0\ ); \m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(18), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__0_n_0\ ); \m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(19), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__0_n_0\ ); \m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__0_n_0\ ); \m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(20), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__0_n_0\ ); \m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(21), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__0_n_0\ ); \m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(22), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__0_n_0\ ); \m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(23), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__0_n_0\ ); \m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(24), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__0_n_0\ ); \m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(25), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__0_n_0\ ); \m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(26), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__0_n_0\ ); \m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(27), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__0_n_0\ ); \m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(28), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__0_n_0\ ); \m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(29), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__0_n_0\ ); \m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__0_n_0\ ); \m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(30), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__0_n_0\ ); \m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(31), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_2__0_n_0\ ); \m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__0_n_0\ ); \m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__0_n_0\ ); \m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__0_n_0\ ); \m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__0_n_0\ ); \m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__0_n_0\ ); \m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__0_n_0\ ); \m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__0_n_0\ ); \m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__0_n_0\ ); \m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__0_n_0\ ); \m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__0_n_0\ ); \m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_1__1_n_0\ ); \m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[47]\, O => \m_payload_i[47]_i_1__0_n_0\ ); \m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__0_n_0\ ); \m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[50]\, O => \m_payload_i[50]_i_1__0_n_0\ ); \m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[51]\, O => \m_payload_i[51]_i_1__0_n_0\ ); \m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[52]\, O => \m_payload_i[52]_i_1__0_n_0\ ); \m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[53]\, O => \m_payload_i[53]_i_1__0_n_0\ ); \m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[54]\, O => \m_payload_i[54]_i_1__0_n_0\ ); \m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[55]\, O => \m_payload_i[55]_i_1__0_n_0\ ); \m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[56]\, O => \m_payload_i[56]_i_1__0_n_0\ ); \m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[57]\, O => \m_payload_i[57]_i_1__0_n_0\ ); \m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[58]\, O => \m_payload_i[58]_i_1__0_n_0\ ); \m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[59]\, O => \m_payload_i[59]_i_1__0_n_0\ ); \m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__0_n_0\ ); \m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[60]\, O => \m_payload_i[60]_i_1__0_n_0\ ); \m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[61]\, O => \m_payload_i[61]_i_1__0_n_0\ ); \m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__0_n_0\ ); \m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__0_n_0\ ); \m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__0_n_0\ ); \m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__0_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[0]_i_1__0_n_0\, Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[10]_i_1__0_n_0\, Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[11]_i_1__0_n_0\, Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[12]_i_1__0_n_0\, Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[13]_i_1__1_n_0\, Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[14]_i_1__0_n_0\, Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[15]_i_1__0_n_0\, Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[16]_i_1__0_n_0\, Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[17]_i_1__0_n_0\, Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[18]_i_1__0_n_0\, Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[19]_i_1__0_n_0\, Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[1]_i_1__0_n_0\, Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[20]_i_1__0_n_0\, Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[21]_i_1__0_n_0\, Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[22]_i_1__0_n_0\, Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[23]_i_1__0_n_0\, Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[24]_i_1__0_n_0\, Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[25]_i_1__0_n_0\, Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[26]_i_1__0_n_0\, Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[27]_i_1__0_n_0\, Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[28]_i_1__0_n_0\, Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[29]_i_1__0_n_0\, Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[2]_i_1__0_n_0\, Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[30]_i_1__0_n_0\, Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[31]_i_2__0_n_0\, Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[32]_i_1__0_n_0\, Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[33]_i_1__0_n_0\, Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[34]_i_1__0_n_0\, Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[35]_i_1__0_n_0\, Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[36]_i_1__0_n_0\, Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[38]_i_1__0_n_0\, Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[39]_i_1__0_n_0\, Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[3]_i_1__0_n_0\, Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[44]_i_1__0_n_0\, Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[45]_i_1__0_n_0\, Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[46]_i_1__1_n_0\, Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[47]_i_1__0_n_0\, Q => si_rs_arlen(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[4]_i_1__0_n_0\, Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[50]_i_1__0_n_0\, Q => \^q\(42), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[51]_i_1__0_n_0\, Q => \^q\(43), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[52]_i_1__0_n_0\, Q => \^q\(44), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[53]_i_1__0_n_0\, Q => \^q\(45), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[54]_i_1__0_n_0\, Q => \^q\(46), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[55]_i_1__0_n_0\, Q => \^q\(47), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[56]_i_1__0_n_0\, Q => \^q\(48), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[57]_i_1__0_n_0\, Q => \^q\(49), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[58]_i_1__0_n_0\, Q => \^q\(50), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[59]_i_1__0_n_0\, Q => \^q\(51), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[5]_i_1__0_n_0\, Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[60]_i_1__0_n_0\, Q => \^q\(52), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[61]_i_1__0_n_0\, Q => \^q\(53), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[6]_i_1__0_n_0\, Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[7]_i_1__0_n_0\, Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[8]_i_1__0_n_0\, Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[1]_rep_1\(0), D => \m_payload_i[9]_i_1__0_n_0\, Q => \^q\(9), R => '0' ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^s_ready_i_reg_0\, R => \^m_valid_i_reg_0\ ); \next_pending_r_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(39), I2 => si_rs_arlen(3), I3 => \^q\(40), I4 => \^q\(41), O => next_pending_r_reg ); \s_ready_i_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F444FFFF" ) port map ( I0 => s_axi_arvalid, I1 => \^s_axi_arready\, I2 => \state_reg[1]_rep_0\, I3 => \state_reg[0]_rep\, I4 => \^s_ready_i_reg_0\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_arready\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8888082AAAAA082A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(40), I3 => \^q\(41), I4 => \^q\(36), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => si_rs_arlen(3), O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"002AA02A0A2AAA2A" ) port map ( I0 => \^q\(4), I1 => si_rs_arlen(3), I2 => \^q\(35), I3 => \^q\(36), I4 => \^q\(40), I5 => \^q\(41), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => si_rs_arlen(3), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(36), I2 => \^q\(35), I3 => si_rs_arlen(3), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0EF0FFFF0EF00000" ) port map ( I0 => \^axaddr_offset_r_reg[3]\(1), I1 => \^axaddr_offset_r_reg[3]\(2), I2 => axaddr_offset_0(0), I3 => \^axaddr_offset_r_reg[1]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[2]_0\(0), O => \wrap_second_len_r_reg[2]\(0) ); \wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA4AFFFFAA4A0000" ) port map ( I0 => \^axaddr_offset_r_reg[3]\(1), I1 => \^axaddr_offset_r_reg[3]\(2), I2 => \^axaddr_offset_r_reg[1]\, I3 => axaddr_offset_0(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[2]_0\(1), O => \wrap_second_len_r_reg[2]\(1) ); \wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EEE222E2" ) port map ( I0 => \axaddr_offset_r[2]_i_2__0_n_0\, I1 => \^q\(35), I2 => \^q\(4), I3 => \^q\(36), I4 => \^q\(6), I5 => \^axlen_cnt_reg[3]\, O => \wrap_second_len_r_reg[3]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0 is port ( s_axi_awready : out STD_LOGIC; s_ready_i_reg_0 : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[1]\ : out STD_LOGIC; axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); wrap_second_len : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[1]\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axlen_cnt_reg[3]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[1]_inv\ : out STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[1]_inv_0\ : in STD_LOGIC; aresetn : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0 : entity is "axi_register_slice_v2_1_14_axic_register_slice"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0 is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC; signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[0]_i_3_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC; signal \axaddr_offset_r[2]_i_4_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC; signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC; signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC; signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC; signal \wrap_second_len_r[0]_i_5_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_offset_r[0]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_4\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_2\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_5\ : label is "soft_lutpair53"; begin Q(54 downto 0) <= \^q\(54 downto 0); \axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\; \axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_awready <= \^s_axi_awready\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; wrap_second_len(2 downto 0) <= \^wrap_second_len\(2 downto 0); \wrap_second_len_r_reg[1]\ <= \^wrap_second_len_r_reg[1]\; \aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, I1 => aresetn, O => \aresetn_d_reg[1]_inv\ ); \aresetn_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn, Q => \aresetn_d_reg_n_0_[0]\, R => '0' ); \axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(36), I2 => \^q\(35), O => \axaddr_incr[3]_i_4_n_0\ ); \axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5_n_0\ ); \axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(36), I2 => \^q\(35), O => \axaddr_incr[3]_i_6_n_0\ ); \axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(11 downto 8), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4_n_0\, DI(1) => \axaddr_incr[3]_i_5_n_0\, DI(0) => \axaddr_incr[3]_i_6_n_0\, O(3 downto 0) => axaddr_incr(3 downto 0), S(3 downto 0) => S(3 downto 0) ); \axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(7 downto 4), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \axaddr_offset_r[0]_i_2_n_0\, O => axaddr_offset(0) ); \axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00000700FFFFF7FF" ) port map ( I0 => \^q\(39), I1 => \axaddr_offset_r[0]_i_3_n_0\, I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(0), O => \axaddr_offset_r[0]_i_2_n_0\ ); \axaddr_offset_r[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(35), I3 => \^q\(2), I4 => \^q\(36), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_3_n_0\ ); \axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \^q\(40), I1 => \axaddr_offset_r[1]_i_2__0_n_0\, I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(1), O => \^axaddr_offset_r_reg[1]\ ); \axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(2), I2 => \^q\(35), I3 => \^q\(3), I4 => \^q\(36), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2__0_n_0\ ); \axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \axaddr_offset_r[2]_i_2_n_0\, O => axaddr_offset(1) ); \axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"03FFF3FF55555555" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(2), I1 => \axaddr_offset_r[2]_i_3_n_0\, I2 => \^q\(35), I3 => \^q\(41), I4 => \axaddr_offset_r[2]_i_4_n_0\, I5 => \state_reg[1]_rep\, O => \axaddr_offset_r[2]_i_2_n_0\ ); \axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(36), I2 => \^q\(2), O => \axaddr_offset_r[2]_i_3_n_0\ ); \axaddr_offset_r[2]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(3), O => \axaddr_offset_r[2]_i_4_n_0\ ); \axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \^q\(42), I1 => \axaddr_offset_r[3]_i_2_n_0\, I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(3), O => \^axaddr_offset_r_reg[3]\ ); \axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => \^q\(35), I3 => \^q\(5), I4 => \^q\(36), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2_n_0\ ); \axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[0]\, O => skid_buffer(0) ); \m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(12), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(13), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(14), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(15), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(16), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(17), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(18), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(19), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); \m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[1]\, O => skid_buffer(1) ); \m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(20), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(21), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(22), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(23), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(24), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(25), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(26), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(27), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(28), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(29), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); \m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(30), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(31), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i[47]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[47]\, O => skid_buffer(47) ); \m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[50]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[50]\, O => skid_buffer(50) ); \m_payload_i[51]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[51]\, O => skid_buffer(51) ); \m_payload_i[52]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[52]\, O => skid_buffer(52) ); \m_payload_i[53]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[53]\, O => skid_buffer(53) ); \m_payload_i[54]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[54]\, O => skid_buffer(54) ); \m_payload_i[55]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[55]\, O => skid_buffer(55) ); \m_payload_i[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[56]\, O => skid_buffer(56) ); \m_payload_i[57]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[57]\, O => skid_buffer(57) ); \m_payload_i[58]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[58]\, O => skid_buffer(58) ); \m_payload_i[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[59]\, O => skid_buffer(59) ); \m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[60]\, O => skid_buffer(60) ); \m_payload_i[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[61]\, O => skid_buffer(61) ); \m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(0), Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(10), Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(11), Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(12), Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(13), Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(14), Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(15), Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(16), Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(17), Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(18), Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(19), Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(1), Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(20), Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(21), Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(22), Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(23), Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(24), Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(25), Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(26), Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(27), Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(28), Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(29), Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(2), Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(30), Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(31), Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(32), Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(33), Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(34), Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(35), Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(36), Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(38), Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(39), Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(3), Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(44), Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(45), Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(46), Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(47), Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(4), Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(50), Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(51), Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(52), Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(53), Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(54), Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(55), Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(56), Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(57), Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(58), Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(59), Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(5), Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(60), Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(61), Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(6), Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(7), Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(8), Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(9), Q => \^q\(9), R => '0' ); m_valid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => b_push, I1 => \^m_valid_i_reg_0\, I2 => s_axi_awvalid, I3 => \^s_axi_awready\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^m_valid_i_reg_0\, R => \aresetn_d_reg[1]_inv_0\ ); next_pending_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \^q\(41), I1 => \^q\(40), I2 => \^q\(42), I3 => \^q\(39), O => next_pending_r_reg ); \s_ready_i_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, O => \^s_ready_i_reg_0\ ); s_ready_i_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_awvalid, I1 => \^s_axi_awready\, I2 => b_push, I3 => \^m_valid_i_reg_0\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_awready\, R => \^s_ready_i_reg_0\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A0A002A2AAAA02A2" ) port map ( I0 => \^q\(2), I1 => \^q\(41), I2 => \^q\(35), I3 => \^q\(40), I4 => \^q\(36), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"002A0A2AA02AAA2A" ) port map ( I0 => \^q\(4), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), I4 => \^q\(41), I5 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(36), I2 => \^q\(35), I3 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"DDDDD8DDAAAAA8AA" ) port map ( I0 => \wrap_second_len_r[0]_i_2_n_0\, I1 => \wrap_second_len_r[0]_i_3_n_0\, I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \wrap_second_len_r_reg[3]\(0), O => D(0) ); \wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \^wrap_second_len_r_reg[1]\, I1 => \wrap_cnt_r[3]_i_2_n_0\, O => D(1) ); \wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^wrap_second_len\(1), I1 => \wrap_cnt_r[3]_i_2_n_0\, I2 => \^wrap_second_len_r_reg[1]\, O => D(2) ); \wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"A6AA" ) port map ( I0 => \^wrap_second_len\(2), I1 => \^wrap_second_len_r_reg[1]\, I2 => \wrap_cnt_r[3]_i_2_n_0\, I3 => \^wrap_second_len\(1), O => D(3) ); \wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAABAAA" ) port map ( I0 => \wrap_cnt_r[3]_i_3_n_0\, I1 => \^axaddr_offset_r_reg[1]\, I2 => \axaddr_offset_r[0]_i_2_n_0\, I3 => \axaddr_offset_r[2]_i_2_n_0\, I4 => \^axaddr_offset_r_reg[3]\, O => \wrap_cnt_r[3]_i_2_n_0\ ); \wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"00000800FFFFF8FF" ) port map ( I0 => \^q\(39), I1 => \axaddr_offset_r[0]_i_3_n_0\, I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \wrap_second_len_r_reg[3]\(0), O => \wrap_cnt_r[3]_i_3_n_0\ ); \wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000CCCCCACC" ) port map ( I0 => \wrap_second_len_r[0]_i_2_n_0\, I1 => \wrap_second_len_r_reg[3]\(0), I2 => \state_reg[1]\(0), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(1), I5 => \wrap_second_len_r[0]_i_3_n_0\, O => \^wrap_second_len\(0) ); \wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFF2FFFFFF" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(3), I1 => \state_reg[1]_rep\, I2 => \wrap_second_len_r[3]_i_2_n_0\, I3 => \axaddr_offset_r[2]_i_2_n_0\, I4 => \axaddr_offset_r[0]_i_2_n_0\, I5 => \^axaddr_offset_r_reg[1]\, O => \wrap_second_len_r[0]_i_2_n_0\ ); \wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFE200E2" ) port map ( I0 => \^q\(0), I1 => \^q\(36), I2 => \^q\(2), I3 => \^q\(35), I4 => \wrap_second_len_r[0]_i_4_n_0\, I5 => \wrap_second_len_r[0]_i_5_n_0\, O => \wrap_second_len_r[0]_i_3_n_0\ ); \wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(3), I1 => \^q\(36), I2 => \^q\(1), O => \wrap_second_len_r[0]_i_4_n_0\ ); \wrap_second_len_r[0]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(39), I1 => \state_reg[1]\(0), I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]\(1), O => \wrap_second_len_r[0]_i_5_n_0\ ); \wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"2EE22E222EE22EE2" ) port map ( I0 => \wrap_second_len_r_reg[3]\(1), I1 => \state_reg[1]_rep\, I2 => \axaddr_offset_r[0]_i_2_n_0\, I3 => \^axaddr_offset_r_reg[1]\, I4 => \^axaddr_offset_r_reg[3]\, I5 => \axaddr_offset_r[2]_i_2_n_0\, O => \^wrap_second_len_r_reg[1]\ ); \wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"08F3FFFF08F30000" ) port map ( I0 => \^axaddr_offset_r_reg[3]\, I1 => \axaddr_offset_r[0]_i_2_n_0\, I2 => \^axaddr_offset_r_reg[1]\, I3 => \axaddr_offset_r[2]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]\(2), O => \^wrap_second_len\(1) ); \wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"BF00FFFFBF00BF00" ) port map ( I0 => \^axaddr_offset_r_reg[1]\, I1 => \axaddr_offset_r[0]_i_2_n_0\, I2 => \axaddr_offset_r[2]_i_2_n_0\, I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]\(3), O => \^wrap_second_len\(2) ); \wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EEE222E2" ) port map ( I0 => \axaddr_offset_r[2]_i_4_n_0\, I1 => \^q\(35), I2 => \^q\(4), I3 => \^q\(36), I4 => \^q\(6), I5 => \^axlen_cnt_reg[3]\, O => \wrap_second_len_r[3]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ is port ( s_axi_bvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; shandshake : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_14_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ is signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair82"; attribute SOFT_HLUTNM of shandshake_r_i_1 : label is "soft_lutpair82"; begin s_axi_bvalid <= \^s_axi_bvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__1_n_0\ ); \m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__1_n_0\ ); \m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__1_n_0\ ); \m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__1_n_0\ ); \m_payload_i[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, O => p_1_in ); \m_payload_i[13]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_2_n_0\ ); \m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__1_n_0\ ); \m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__1_n_0\ ); \m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__1_n_0\ ); \m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__1_n_0\ ); \m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__1_n_0\ ); \m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__1_n_0\ ); \m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__1_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__1_n_0\, Q => \s_axi_bid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__1_n_0\, Q => \s_axi_bid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__1_n_0\, Q => \s_axi_bid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__1_n_0\, Q => \s_axi_bid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_2_n_0\, Q => \s_axi_bid[11]\(13), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__1_n_0\, Q => \s_axi_bid[11]\(1), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__1_n_0\, Q => \s_axi_bid[11]\(2), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__1_n_0\, Q => \s_axi_bid[11]\(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__1_n_0\, Q => \s_axi_bid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__1_n_0\, Q => \s_axi_bid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__1_n_0\, Q => \s_axi_bid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__1_n_0\, Q => \s_axi_bid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__1_n_0\, Q => \s_axi_bid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__1_n_0\, Q => \s_axi_bid[11]\(9), R => '0' ); \m_valid_i_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => si_rs_bvalid, I3 => \^skid_buffer_reg[0]_0\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^s_axi_bvalid\, R => \aresetn_d_reg[1]_inv\ ); s_ready_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => si_rs_bvalid, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_bready, I3 => \^s_axi_bvalid\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); shandshake_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^skid_buffer_reg[0]_0\, I1 => si_rs_bvalid, O => shandshake ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(8), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(9), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(10), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(11), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(0), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(1), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(2), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(3), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(4), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(5), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(6), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(7), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ is port ( s_axi_rvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \cnt_read_reg[0]_rep__1\ : out STD_LOGIC; \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; \cnt_read_reg[3]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_14_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ is signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC; signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \m_valid_i_i_1__2\ : label is "soft_lutpair90"; begin s_axi_rvalid <= \^s_axi_rvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \cnt_read[3]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^skid_buffer_reg[0]_0\, I1 => \cnt_read_reg[3]_rep__0\, O => \cnt_read_reg[0]_rep__1\ ); \m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__2_n_0\ ); \m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__2_n_0\ ); \m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__2_n_0\ ); \m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__2_n_0\ ); \m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(13), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__2_n_0\ ); \m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(14), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__1_n_0\ ); \m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(15), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__1_n_0\ ); \m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(16), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__1_n_0\ ); \m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(17), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__1_n_0\ ); \m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(18), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__1_n_0\ ); \m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(19), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__1_n_0\ ); \m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__2_n_0\ ); \m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(20), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__1_n_0\ ); \m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(21), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__1_n_0\ ); \m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(22), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__1_n_0\ ); \m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(23), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__1_n_0\ ); \m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(24), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__1_n_0\ ); \m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(25), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__1_n_0\ ); \m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(26), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__1_n_0\ ); \m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(27), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__1_n_0\ ); \m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(28), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__1_n_0\ ); \m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(29), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__2_n_0\ ); \m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(30), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__1_n_0\ ); \m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(31), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_1__1_n_0\ ); \m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(32), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__1_n_0\ ); \m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(33), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__1_n_0\ ); \m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__1_n_0\ ); \m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__1_n_0\ ); \m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__1_n_0\ ); \m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[37]\, O => \m_payload_i[37]_i_1_n_0\ ); \m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__1_n_0\ ); \m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__2_n_0\ ); \m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[40]\, O => \m_payload_i[40]_i_1_n_0\ ); \m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[41]\, O => \m_payload_i[41]_i_1_n_0\ ); \m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[42]\, O => \m_payload_i[42]_i_1_n_0\ ); \m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[43]\, O => \m_payload_i[43]_i_1_n_0\ ); \m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__1_n_0\ ); \m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__1_n_0\ ); \m_payload_i[46]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, O => p_1_in ); \m_payload_i[46]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_2_n_0\ ); \m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__2_n_0\ ); \m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__2_n_0\ ); \m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__2_n_0\ ); \m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__2_n_0\ ); \m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__2_n_0\ ); \m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__2_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__2_n_0\, Q => \s_axi_rid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__2_n_0\, Q => \s_axi_rid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__2_n_0\, Q => \s_axi_rid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__2_n_0\, Q => \s_axi_rid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_1__2_n_0\, Q => \s_axi_rid[11]\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[14]_i_1__1_n_0\, Q => \s_axi_rid[11]\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[15]_i_1__1_n_0\, Q => \s_axi_rid[11]\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[16]_i_1__1_n_0\, Q => \s_axi_rid[11]\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[17]_i_1__1_n_0\, Q => \s_axi_rid[11]\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[18]_i_1__1_n_0\, Q => \s_axi_rid[11]\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[19]_i_1__1_n_0\, Q => \s_axi_rid[11]\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__2_n_0\, Q => \s_axi_rid[11]\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[20]_i_1__1_n_0\, Q => \s_axi_rid[11]\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[21]_i_1__1_n_0\, Q => \s_axi_rid[11]\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[22]_i_1__1_n_0\, Q => \s_axi_rid[11]\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[23]_i_1__1_n_0\, Q => \s_axi_rid[11]\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[24]_i_1__1_n_0\, Q => \s_axi_rid[11]\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[25]_i_1__1_n_0\, Q => \s_axi_rid[11]\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[26]_i_1__1_n_0\, Q => \s_axi_rid[11]\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[27]_i_1__1_n_0\, Q => \s_axi_rid[11]\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[28]_i_1__1_n_0\, Q => \s_axi_rid[11]\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[29]_i_1__1_n_0\, Q => \s_axi_rid[11]\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__2_n_0\, Q => \s_axi_rid[11]\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[30]_i_1__1_n_0\, Q => \s_axi_rid[11]\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[31]_i_1__1_n_0\, Q => \s_axi_rid[11]\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[32]_i_1__1_n_0\, Q => \s_axi_rid[11]\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[33]_i_1__1_n_0\, Q => \s_axi_rid[11]\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[34]_i_1__1_n_0\, Q => \s_axi_rid[11]\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[35]_i_1__1_n_0\, Q => \s_axi_rid[11]\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[36]_i_1__1_n_0\, Q => \s_axi_rid[11]\(36), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[37]_i_1_n_0\, Q => \s_axi_rid[11]\(37), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[38]_i_1__1_n_0\, Q => \s_axi_rid[11]\(38), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[39]_i_1__1_n_0\, Q => \s_axi_rid[11]\(39), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__2_n_0\, Q => \s_axi_rid[11]\(3), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[40]_i_1_n_0\, Q => \s_axi_rid[11]\(40), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[41]_i_1_n_0\, Q => \s_axi_rid[11]\(41), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[42]_i_1_n_0\, Q => \s_axi_rid[11]\(42), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[43]_i_1_n_0\, Q => \s_axi_rid[11]\(43), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[44]_i_1__1_n_0\, Q => \s_axi_rid[11]\(44), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[45]_i_1__1_n_0\, Q => \s_axi_rid[11]\(45), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[46]_i_2_n_0\, Q => \s_axi_rid[11]\(46), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__2_n_0\, Q => \s_axi_rid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__2_n_0\, Q => \s_axi_rid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__2_n_0\, Q => \s_axi_rid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__2_n_0\, Q => \s_axi_rid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__2_n_0\, Q => \s_axi_rid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__2_n_0\, Q => \s_axi_rid[11]\(9), R => '0' ); \m_valid_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"4FFF" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => \^skid_buffer_reg[0]_0\, I3 => \cnt_read_reg[3]_rep__0\, O => \m_valid_i_i_1__2_n_0\ ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_valid_i_i_1__2_n_0\, Q => \^s_axi_rvalid\, R => \aresetn_d_reg[1]_inv\ ); \s_ready_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"F8FF" ) port map ( I0 => \^skid_buffer_reg[0]_0\, I1 => \cnt_read_reg[3]_rep__0\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \s_ready_i_i_1__2_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__2_n_0\, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(32), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(33), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(0), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(1), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(2), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(3), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(4), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(5), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(6), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(7), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(8), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(9), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(10), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(11), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(12), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel is port ( si_rs_bvalid : out STD_LOGIC; \cnt_read_reg[0]_rep__0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); areset_d1 : in STD_LOGIC; shandshake : in STD_LOGIC; aclk : in STD_LOGIC; b_push : in STD_LOGIC; si_rs_bready : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel is signal bid_fifo_0_n_3 : STD_LOGIC; signal bid_fifo_0_n_5 : STD_LOGIC; signal \bresp_cnt[7]_i_7_n_0\ : STD_LOGIC; signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal bresp_push : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal mhandshake : STD_LOGIC; signal mhandshake_r : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s_bresp_acc0 : STD_LOGIC; signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC; signal shandshake_r : STD_LOGIC; signal \^si_rs_bvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair132"; attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair132"; attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair130"; attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair130"; attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair131"; attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair131"; begin si_rs_bvalid <= \^si_rs_bvalid\; bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo port map ( D(0) => bid_fifo_0_n_5, Q(1 downto 0) => cnt_read(1 downto 0), SR(0) => s_bresp_acc0, aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0), bresp_push => bresp_push, bvalid_i_reg => bid_fifo_0_n_3, \cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\, \in\(15 downto 0) => \in\(15 downto 0), mhandshake_r => mhandshake_r, \out\(11 downto 0) => \out\(11 downto 0), shandshake_r => shandshake_r, si_rs_bready => si_rs_bready, si_rs_bvalid => \^si_rs_bvalid\, \state_reg[0]_rep\ => \state_reg[0]_rep\ ); \bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \bresp_cnt_reg__0\(0), O => p_0_in(0) ); \bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(0), I1 => \bresp_cnt_reg__0\(1), O => p_0_in(1) ); \bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(2), I1 => \bresp_cnt_reg__0\(1), I2 => \bresp_cnt_reg__0\(0), O => p_0_in(2) ); \bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \bresp_cnt_reg__0\(3), I1 => \bresp_cnt_reg__0\(0), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(2), O => p_0_in(3) ); \bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(4), I1 => \bresp_cnt_reg__0\(2), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(3), O => p_0_in(4) ); \bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(1), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => p_0_in(5) ); \bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(6), I1 => \bresp_cnt[7]_i_7_n_0\, O => p_0_in(6) ); \bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(7), I1 => \bresp_cnt[7]_i_7_n_0\, I2 => \bresp_cnt_reg__0\(6), O => p_0_in(7) ); \bresp_cnt[7]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(1), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => \bresp_cnt[7]_i_7_n_0\ ); \bresp_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(0), Q => \bresp_cnt_reg__0\(0), R => s_bresp_acc0 ); \bresp_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(1), Q => \bresp_cnt_reg__0\(1), R => s_bresp_acc0 ); \bresp_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(2), Q => \bresp_cnt_reg__0\(2), R => s_bresp_acc0 ); \bresp_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(3), Q => \bresp_cnt_reg__0\(3), R => s_bresp_acc0 ); \bresp_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(4), Q => \bresp_cnt_reg__0\(4), R => s_bresp_acc0 ); \bresp_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(5), Q => \bresp_cnt_reg__0\(5), R => s_bresp_acc0 ); \bresp_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(6), Q => \bresp_cnt_reg__0\(6), R => s_bresp_acc0 ); \bresp_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(7), Q => \bresp_cnt_reg__0\(7), R => s_bresp_acc0 ); bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ port map ( D(0) => bid_fifo_0_n_5, Q(1 downto 0) => cnt_read(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(1) => \s_bresp_acc_reg_n_0_[1]\, \in\(0) => \s_bresp_acc_reg_n_0_[0]\, m_axi_bready => m_axi_bready, m_axi_bvalid => m_axi_bvalid, mhandshake => mhandshake, mhandshake_r => mhandshake_r, sel => bresp_push, shandshake_r => shandshake_r, \skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0) ); bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => bid_fifo_0_n_3, Q => \^si_rs_bvalid\, R => '0' ); mhandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => mhandshake, Q => mhandshake_r, R => areset_d1 ); \s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EACECCCC" ) port map ( I0 => m_axi_bresp(0), I1 => \s_bresp_acc_reg_n_0_[0]\, I2 => \s_bresp_acc_reg_n_0_[1]\, I3 => m_axi_bresp(1), I4 => mhandshake, I5 => s_bresp_acc0, O => \s_bresp_acc[0]_i_1_n_0\ ); \s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00EA" ) port map ( I0 => \s_bresp_acc_reg_n_0_[1]\, I1 => m_axi_bresp(1), I2 => mhandshake, I3 => s_bresp_acc0, O => \s_bresp_acc[1]_i_1_n_0\ ); \s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[0]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[0]\, R => '0' ); \s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[1]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[1]\, R => '0' ); shandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => shandshake, Q => shandshake_r, R => areset_d1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator is port ( next_pending_r_reg : out STD_LOGIC; next_pending_r_reg_0 : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_0 : out STD_LOGIC; sel_first : out STD_LOGIC; \axlen_cnt_reg[0]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; next_pending_r_reg_1 : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; wrap_next_pending : in STD_LOGIC; sel_first_i : in STD_LOGIC; \m_payload_i_reg[39]\ : in STD_LOGIC; \m_payload_i_reg[39]_0\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 18 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_rep\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_3 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; begin incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd port map ( E(0) => E(0), Q(1 downto 0) => Q(1 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[0]_0\ => sel_first_0, \axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_3, \axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_10, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_11, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_12, \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, incr_next_pending => incr_next_pending, \m_axi_awaddr[11]\ => incr_cmd_0_n_13, \m_axi_awaddr[2]\ => incr_cmd_0_n_15, \m_axi_awaddr[3]\ => incr_cmd_0_n_14, \m_payload_i_reg[46]\(9 downto 7) => \m_payload_i_reg[46]\(18 downto 16), \m_payload_i_reg[46]\(6 downto 4) => \m_payload_i_reg[46]\(14 downto 12), \m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[46]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, next_pending_r_reg_0 => next_pending_r_reg, sel_first_reg_0 => sel_first_reg_1, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]_rep\ => \state_reg[1]_rep\ ); \memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => \m_payload_i_reg[46]\(15), I2 => s_axburst_eq0, O => \state_reg[0]_rep\ ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]\, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]_0\, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), Q(1 downto 0) => Q(1 downto 0), aclk => aclk, \axaddr_incr_reg[11]\(9) => incr_cmd_0_n_3, \axaddr_incr_reg[11]\(8) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_10, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_11, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_12, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[46]\(17 downto 14) => \m_payload_i_reg[46]\(18 downto 15), \m_payload_i_reg[46]\(13 downto 0) => \m_payload_i_reg[46]\(13 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), next_pending_r_reg_0 => next_pending_r_reg_0, next_pending_r_reg_1 => next_pending_r_reg_1, sel_first_reg_0 => sel_first, sel_first_reg_1 => sel_first_reg_2, sel_first_reg_2 => incr_cmd_0_n_13, sel_first_reg_3 => incr_cmd_0_n_14, sel_first_reg_4 => incr_cmd_0_n_15, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[1]_rep\ => \state_reg[1]_rep\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0), \wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 is port ( incr_next_pending : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first : out STD_LOGIC; sel_first_reg_1 : out STD_LOGIC; \axlen_cnt_reg[0]\ : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; r_rlast : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; wrap_next_pending : in STD_LOGIC; sel_first_i : in STD_LOGIC; \m_payload_i_reg[39]\ : in STD_LOGIC; \m_payload_i_reg[39]_0\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; sel_first_reg_3 : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \m_payload_i_reg[44]\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); si_rs_arvalid : in STD_LOGIC; \state_reg[0]_rep_0\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \m_payload_i_reg[35]\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_14_b2s_cmd_translator"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_3 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair14"; begin incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 port map ( E(0) => E(0), O(3 downto 0) => O(3 downto 0), Q(11) => incr_cmd_0_n_3, Q(10) => incr_cmd_0_n_4, Q(9) => incr_cmd_0_n_5, Q(8) => incr_cmd_0_n_6, Q(7) => incr_cmd_0_n_7, Q(6) => incr_cmd_0_n_8, Q(5) => incr_cmd_0_n_9, Q(4) => incr_cmd_0_n_10, Q(3) => incr_cmd_0_n_11, Q(2) => incr_cmd_0_n_12, Q(1) => incr_cmd_0_n_13, Q(0) => incr_cmd_0_n_14, S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_incr_reg[0]_0\ => sel_first, \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, incr_next_pending => incr_next_pending, \m_axi_araddr[11]\ => incr_cmd_0_n_15, m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[44]\ => \m_payload_i_reg[44]\, \m_payload_i_reg[46]\(9 downto 7) => Q(18 downto 16), \m_payload_i_reg[46]\(6 downto 4) => Q(14 downto 12), \m_payload_i_reg[46]\(3 downto 0) => Q(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), sel_first_reg_0 => sel_first_reg_2, sel_first_reg_1(0) => sel_first_reg_4(0), si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\ => \state_reg[1]\, \state_reg[1]_0\(1 downto 0) => \state_reg[1]_0\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); r_rlast_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => s_axburst_eq0, I1 => Q(15), I2 => s_axburst_eq1, O => r_rlast ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]\, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]_0\, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); \state[1]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => Q(15), I2 => s_axburst_eq0, O => \state_reg[0]_rep\ ); wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), Q(17 downto 14) => Q(18 downto 15), Q(13 downto 0) => Q(13 downto 0), aclk => aclk, \axaddr_incr_reg[11]\(11) => incr_cmd_0_n_3, \axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]_0\, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_payload_i_reg[35]\ => \m_payload_i_reg[35]\, \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), next_pending_r_reg_0 => next_pending_r_reg, sel_first_reg_0 => sel_first_reg_1, sel_first_reg_1 => sel_first_reg_3, sel_first_reg_2 => incr_cmd_0_n_15, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]_rep\ => \state_reg[1]_rep\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); r_push : in STD_LOGIC; aclk : in STD_LOGIC; r_rlast : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel is signal \^m_valid_i_reg\ : STD_LOGIC; signal r_push_r : STD_LOGIC; signal rd_data_fifo_0_n_0 : STD_LOGIC; signal rd_data_fifo_0_n_2 : STD_LOGIC; signal rd_data_fifo_0_n_3 : STD_LOGIC; signal rd_data_fifo_0_n_5 : STD_LOGIC; signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 ); signal transaction_fifo_0_n_2 : STD_LOGIC; signal wr_en0 : STD_LOGIC; begin m_valid_i_reg <= \^m_valid_i_reg\; \r_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => trans_in(1), R => '0' ); \r_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(10), Q => trans_in(11), R => '0' ); \r_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(11), Q => trans_in(12), R => '0' ); \r_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => trans_in(2), R => '0' ); \r_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => trans_in(3), R => '0' ); \r_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => trans_in(4), R => '0' ); \r_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(4), Q => trans_in(5), R => '0' ); \r_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(5), Q => trans_in(6), R => '0' ); \r_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(6), Q => trans_in(7), R => '0' ); \r_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(7), Q => trans_in(8), R => '0' ); \r_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(8), Q => trans_in(9), R => '0' ); \r_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(9), Q => trans_in(10), R => '0' ); r_push_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => r_push, Q => r_push_r, R => '0' ); r_rlast_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => r_rlast, Q => trans_in(0), R => '0' ); rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[3]_rep__0_0\ => \^m_valid_i_reg\, \cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2, \cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, \out\(33 downto 0) => \out\(33 downto 0), s_ready_i_reg => s_ready_i_reg, s_ready_i_reg_0 => transaction_fifo_0_n_2, si_rs_rready => si_rs_rready, \state_reg[1]_rep\ => rd_data_fifo_0_n_5, wr_en0 => wr_en0 ); transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5, \cnt_read_reg[2]_rep__2\ => rd_data_fifo_0_n_3, \cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_2, \cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2, \in\(12 downto 0) => trans_in(12 downto 0), m_valid_i_reg => \^m_valid_i_reg\, r_push_r => r_push_r, s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, wr_en0 => wr_en0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice is port ( s_axi_awready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; si_rs_awvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; si_rs_bready : out STD_LOGIC; si_rs_arvalid : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; si_rs_rready : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 3 downto 0 ); wrap_second_len : out STD_LOGIC_VECTOR ( 3 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 53 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); axaddr_offset : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axlen_cnt_reg[3]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; shandshake : out STD_LOGIC; \wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[1]\ : out STD_LOGIC; next_pending_r_reg_0 : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC; \axlen_cnt_reg[3]_0\ : out STD_LOGIC; \cnt_read_reg[0]_rep__1\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \axaddr_offset_r_reg[0]\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); aclk : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; aresetn : in STD_LOGIC; \cnt_read_reg[3]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_rep_0\ : in STD_LOGIC; \wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \state_reg[1]_rep_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_rep_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice is signal \gen_simple_ar.ar_pipe_n_2\ : STD_LOGIC; signal \gen_simple_aw.aw_pipe_n_1\ : STD_LOGIC; signal \gen_simple_aw.aw_pipe_n_91\ : STD_LOGIC; begin \gen_simple_ar.ar_pipe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice port map ( O(3 downto 0) => O(3 downto 0), Q(53 downto 0) => \s_arid_r_reg[11]\(53 downto 0), aclk => aclk, \aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\, \aresetn_d_reg[0]_0\ => \gen_simple_aw.aw_pipe_n_91\, \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), \axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), axaddr_offset_0(0) => axaddr_offset_0(0), \axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]\, \axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]\, \axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0), \axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0), \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\, \m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), m_valid_i0 => m_valid_i0, m_valid_i_reg_0 => \gen_simple_ar.ar_pipe_n_2\, next_pending_r_reg => next_pending_r_reg_0, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_arvalid => s_axi_arvalid, s_ready_i_reg_0 => si_rs_arvalid, \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]_rep\ => \state_reg[1]_rep_0\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_1\, \state_reg[1]_rep_1\(0) => \state_reg[1]_rep_2\(0), \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0), \wrap_second_len_r_reg[2]\(1 downto 0) => \wrap_second_len_r_reg[2]\(1 downto 0), \wrap_second_len_r_reg[2]_0\(1 downto 0) => \wrap_second_len_r_reg[2]_0\(1 downto 0), \wrap_second_len_r_reg[3]\ => \wrap_second_len_r_reg[3]\ ); \gen_simple_aw.aw_pipe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0 port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), Q(54 downto 0) => Q(54 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, aresetn => aresetn, \aresetn_d_reg[1]_inv\ => \gen_simple_aw.aw_pipe_n_91\, \aresetn_d_reg[1]_inv_0\ => \gen_simple_ar.ar_pipe_n_2\, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(1) => axaddr_offset(2), axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[1]\ => axaddr_offset(1), \axaddr_offset_r_reg[3]\ => axaddr_offset(3), \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0), \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\, b_push => b_push, m_valid_i_reg_0 => si_rs_awvalid, next_pending_r_reg => next_pending_r_reg, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, s_ready_i_reg_0 => \gen_simple_aw.aw_pipe_n_1\, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0), wrap_second_len(2 downto 1) => wrap_second_len(3 downto 2), wrap_second_len(0) => wrap_second_len(0), \wrap_second_len_r_reg[1]\ => wrap_second_len(1), \wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0) ); \gen_simple_b.b_pipe\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \gen_simple_ar.ar_pipe_n_2\, \out\(11 downto 0) => \out\(11 downto 0), \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0), shandshake => shandshake, si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[0]_0\ => si_rs_bready ); \gen_simple_r.r_pipe\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \gen_simple_ar.ar_pipe_n_2\, \cnt_read_reg[0]_rep__1\ => \cnt_read_reg[0]_rep__1\, \cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\, \cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0), r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0), \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \skid_buffer_reg[0]_0\ => si_rs_rready ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); axaddr_offset : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); r_push : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; r_rlast : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 30 downto 0 ); D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[35]\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[35]_0\ : in STD_LOGIC; \m_payload_i_reg[3]\ : in STD_LOGIC; \m_payload_i_reg[44]\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel is signal ar_cmd_fsm_0_n_0 : STD_LOGIC; signal ar_cmd_fsm_0_n_11 : STD_LOGIC; signal ar_cmd_fsm_0_n_14 : STD_LOGIC; signal ar_cmd_fsm_0_n_16 : STD_LOGIC; signal ar_cmd_fsm_0_n_17 : STD_LOGIC; signal ar_cmd_fsm_0_n_18 : STD_LOGIC; signal ar_cmd_fsm_0_n_21 : STD_LOGIC; signal ar_cmd_fsm_0_n_3 : STD_LOGIC; signal ar_cmd_fsm_0_n_4 : STD_LOGIC; signal ar_cmd_fsm_0_n_5 : STD_LOGIC; signal ar_cmd_fsm_0_n_6 : STD_LOGIC; signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_1 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_4 : STD_LOGIC; signal cmd_translator_0_n_5 : STD_LOGIC; signal cmd_translator_0_n_6 : STD_LOGIC; signal cmd_translator_0_n_8 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \^r_push\ : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal wrap_next_pending : STD_LOGIC; begin axaddr_offset(0) <= \^axaddr_offset\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; r_push <= \^r_push\; \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm port map ( D(2) => ar_cmd_fsm_0_n_3, D(1) => ar_cmd_fsm_0_n_4, D(0) => ar_cmd_fsm_0_n_5, E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(1 downto 0) => state(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_21, \axaddr_offset_r_reg[0]\(0) => \^axaddr_offset\(0), \axaddr_offset_r_reg[3]\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0), \axlen_cnt_reg[3]\ => cmd_translator_0_n_6, \axlen_cnt_reg[4]\(0) => ar_cmd_fsm_0_n_16, \axlen_cnt_reg[6]\ => cmd_translator_0_n_5, \axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0, \cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\, incr_next_pending => incr_next_pending, m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \m_payload_i_reg[0]\, \m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\, \m_payload_i_reg[0]_1\(0) => E(0), \m_payload_i_reg[35]\ => \m_payload_i_reg[35]\, \m_payload_i_reg[35]_0\ => \m_payload_i_reg[35]_0\, \m_payload_i_reg[3]\ => \m_payload_i_reg[3]\, \m_payload_i_reg[44]\(1 downto 0) => Q(16 downto 15), \m_payload_i_reg[44]_0\ => \m_payload_i_reg[44]\, \m_payload_i_reg[47]\(1 downto 0) => \m_payload_i_reg[47]_0\(2 downto 1), m_valid_i0 => m_valid_i0, next_pending_r_reg => cmd_translator_0_n_1, r_push_r_reg => \^r_push\, s_axburst_eq0_reg => ar_cmd_fsm_0_n_11, s_axburst_eq1_reg => ar_cmd_fsm_0_n_14, s_axburst_eq1_reg_0 => cmd_translator_0_n_8, s_axi_arvalid => s_axi_arvalid, s_ready_i_reg => s_ready_i_reg, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => ar_cmd_fsm_0_n_17, sel_first_reg_0 => ar_cmd_fsm_0_n_18, sel_first_reg_1 => cmd_translator_0_n_4, sel_first_reg_2 => cmd_translator_0_n_2, si_rs_arvalid => si_rs_arvalid, \wrap_cnt_r_reg[0]\ => ar_cmd_fsm_0_n_6, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[2]\(1 downto 0) => D(1 downto 0), \wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len\(3), \wrap_second_len_r_reg[3]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[3]_0\(1) => \wrap_cmd_0/wrap_second_len_r\(3), \wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(0) ); cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 port map ( D(3 downto 1) => \m_payload_i_reg[47]_0\(2 downto 0), D(0) => \^axaddr_offset\(0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, O(3 downto 0) => O(3 downto 0), Q(18 downto 0) => Q(18 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_offset_r_reg[3]\(3 downto 1) => \^axaddr_offset_r_reg[3]\(2 downto 0), \axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0), \axaddr_offset_r_reg[3]_0\ => ar_cmd_fsm_0_n_6, \axlen_cnt_reg[0]\ => cmd_translator_0_n_5, \axlen_cnt_reg[0]_0\ => cmd_translator_0_n_6, incr_next_pending => incr_next_pending, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, \m_payload_i_reg[35]\ => \m_payload_i_reg[35]\, \m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_11, \m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_14, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0), \m_payload_i_reg[44]\ => \m_payload_i_reg[44]\, \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => ar_cmd_fsm_0_n_16, next_pending_r_reg => cmd_translator_0_n_1, r_rlast => r_rlast, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_2, sel_first_reg_1 => cmd_translator_0_n_4, sel_first_reg_2 => ar_cmd_fsm_0_n_18, sel_first_reg_3 => ar_cmd_fsm_0_n_17, sel_first_reg_4(0) => ar_cmd_fsm_0_n_21, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => cmd_translator_0_n_8, \state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\, \state_reg[1]\ => ar_cmd_fsm_0_n_0, \state_reg[1]_0\(1 downto 0) => state(1 downto 0), \state_reg[1]_rep\ => \^r_push\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]\(3) => \wrap_cmd_0/wrap_second_len_r\(3), \wrap_second_len_r_reg[3]\(2 downto 1) => \wrap_second_len_r_reg[2]\(1 downto 0), \wrap_second_len_r_reg[3]\(0) => \wrap_cmd_0/wrap_second_len_r\(0), \wrap_second_len_r_reg[3]_0\(3) => \wrap_cmd_0/wrap_second_len\(3), \wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0), \wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[3]_1\(2) => ar_cmd_fsm_0_n_3, \wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_4, \wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_5 ); \s_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(19), Q => \r_arid_r_reg[11]\(0), R => '0' ); \s_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \r_arid_r_reg[11]\(10), R => '0' ); \s_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \r_arid_r_reg[11]\(11), R => '0' ); \s_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \r_arid_r_reg[11]\(1), R => '0' ); \s_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \r_arid_r_reg[11]\(2), R => '0' ); \s_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \r_arid_r_reg[11]\(3), R => '0' ); \s_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \r_arid_r_reg[11]\(4), R => '0' ); \s_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \r_arid_r_reg[11]\(5), R => '0' ); \s_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \r_arid_r_reg[11]\(6), R => '0' ); \s_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \r_arid_r_reg[11]\(7), R => '0' ); \s_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \r_arid_r_reg[11]\(8), R => '0' ); \s_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \r_arid_r_reg[11]\(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; si_rs_awvalid : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \m_payload_i_reg[61]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; \cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal aw_cmd_fsm_0_n_0 : STD_LOGIC; signal aw_cmd_fsm_0_n_10 : STD_LOGIC; signal aw_cmd_fsm_0_n_11 : STD_LOGIC; signal aw_cmd_fsm_0_n_12 : STD_LOGIC; signal aw_cmd_fsm_0_n_3 : STD_LOGIC; signal aw_cmd_fsm_0_n_5 : STD_LOGIC; signal aw_cmd_fsm_0_n_6 : STD_LOGIC; signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_1 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_5 : STD_LOGIC; signal cmd_translator_0_n_6 : STD_LOGIC; signal cmd_translator_0_n_7 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal sel_first : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC; signal wrap_next_pending : STD_LOGIC; begin Q(1 downto 0) <= \^q\(1 downto 0); \wrap_boundary_axaddr_r_reg[0]\ <= \^wrap_boundary_axaddr_r_reg[0]\; aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm port map ( E(0) => aw_cmd_fsm_0_n_0, Q(1 downto 0) => \^q\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \axlen_cnt_reg[0]\ => aw_cmd_fsm_0_n_3, \axlen_cnt_reg[1]\ => cmd_translator_0_n_7, \axlen_cnt_reg[6]\ => cmd_translator_0_n_5, \axlen_cnt_reg[7]\ => aw_cmd_fsm_0_n_5, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\, \cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0_0\, incr_next_pending => incr_next_pending, m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[0]\(0) => E(0), \m_payload_i_reg[39]\(0) => \m_payload_i_reg[61]\(15), \m_payload_i_reg[46]\ => \m_payload_i_reg[46]\, next_pending_r_reg => cmd_translator_0_n_0, next_pending_r_reg_0 => cmd_translator_0_n_1, s_axburst_eq0_reg => aw_cmd_fsm_0_n_6, s_axburst_eq1_reg => aw_cmd_fsm_0_n_10, s_axburst_eq1_reg_0 => cmd_translator_0_n_6, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => aw_cmd_fsm_0_n_11, sel_first_reg_0 => aw_cmd_fsm_0_n_12, sel_first_reg_1 => cmd_translator_0_n_2, si_rs_awvalid => si_rs_awvalid, \wrap_boundary_axaddr_r_reg[0]\(0) => \^wrap_boundary_axaddr_r_reg[0]\, wrap_next_pending => wrap_next_pending ); cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator port map ( D(3 downto 0) => D(3 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[0]\, Q(1 downto 0) => \^q\(1 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_offset_r_reg[3]\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axlen_cnt_reg[0]\ => cmd_translator_0_n_5, incr_next_pending => incr_next_pending, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_6, \m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_10, \m_payload_i_reg[46]\(18 downto 0) => \m_payload_i_reg[61]\(18 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), next_pending_r_reg => cmd_translator_0_n_0, next_pending_r_reg_0 => cmd_translator_0_n_1, next_pending_r_reg_1 => cmd_translator_0_n_7, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_2, sel_first_reg_1 => aw_cmd_fsm_0_n_12, sel_first_reg_2 => aw_cmd_fsm_0_n_11, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => aw_cmd_fsm_0_n_0, \state_reg[0]_rep\ => cmd_translator_0_n_6, \state_reg[0]_rep_0\ => aw_cmd_fsm_0_n_5, \state_reg[1]_rep\ => aw_cmd_fsm_0_n_3, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0) ); \s_awid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(20), Q => \in\(4), R => '0' ); \s_awid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(30), Q => \in\(14), R => '0' ); \s_awid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(31), Q => \in\(15), R => '0' ); \s_awid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(21), Q => \in\(5), R => '0' ); \s_awid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(22), Q => \in\(6), R => '0' ); \s_awid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(23), Q => \in\(7), R => '0' ); \s_awid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(24), Q => \in\(8), R => '0' ); \s_awid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(25), Q => \in\(9), R => '0' ); \s_awid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(26), Q => \in\(10), R => '0' ); \s_awid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(27), Q => \in\(11), R => '0' ); \s_awid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(28), Q => \in\(12), R => '0' ); \s_awid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(29), Q => \in\(13), R => '0' ); \s_awlen_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(16), Q => \in\(0), R => '0' ); \s_awlen_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(17), Q => \in\(1), R => '0' ); \s_awlen_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(18), Q => \in\(2), R => '0' ); \s_awlen_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[61]\(19), Q => \in\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s is port ( s_axi_rvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_arready : out STD_LOGIC; \m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_bvalid : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_axi_rready : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_arready : in STD_LOGIC; s_axi_rready : in STD_LOGIC; aclk : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awready : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; aresetn : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s is signal \RD.ar_channel_0_n_0\ : STD_LOGIC; signal \RD.ar_channel_0_n_38\ : STD_LOGIC; signal \RD.ar_channel_0_n_39\ : STD_LOGIC; signal \RD.ar_channel_0_n_40\ : STD_LOGIC; signal \RD.ar_channel_0_n_41\ : STD_LOGIC; signal \RD.ar_channel_0_n_8\ : STD_LOGIC; signal \RD.ar_channel_0_n_9\ : STD_LOGIC; signal \RD.r_channel_0_n_0\ : STD_LOGIC; signal \RD.r_channel_0_n_1\ : STD_LOGIC; signal SI_REG_n_10 : STD_LOGIC; signal SI_REG_n_103 : STD_LOGIC; signal SI_REG_n_141 : STD_LOGIC; signal SI_REG_n_142 : STD_LOGIC; signal SI_REG_n_143 : STD_LOGIC; signal SI_REG_n_144 : STD_LOGIC; signal SI_REG_n_145 : STD_LOGIC; signal SI_REG_n_146 : STD_LOGIC; signal SI_REG_n_147 : STD_LOGIC; signal SI_REG_n_148 : STD_LOGIC; signal SI_REG_n_153 : STD_LOGIC; signal SI_REG_n_154 : STD_LOGIC; signal SI_REG_n_161 : STD_LOGIC; signal SI_REG_n_162 : STD_LOGIC; signal SI_REG_n_163 : STD_LOGIC; signal SI_REG_n_164 : STD_LOGIC; signal SI_REG_n_165 : STD_LOGIC; signal SI_REG_n_166 : STD_LOGIC; signal SI_REG_n_167 : STD_LOGIC; signal SI_REG_n_168 : STD_LOGIC; signal SI_REG_n_169 : STD_LOGIC; signal SI_REG_n_170 : STD_LOGIC; signal SI_REG_n_171 : STD_LOGIC; signal SI_REG_n_172 : STD_LOGIC; signal SI_REG_n_173 : STD_LOGIC; signal SI_REG_n_174 : STD_LOGIC; signal SI_REG_n_175 : STD_LOGIC; signal SI_REG_n_176 : STD_LOGIC; signal SI_REG_n_177 : STD_LOGIC; signal SI_REG_n_178 : STD_LOGIC; signal SI_REG_n_179 : STD_LOGIC; signal SI_REG_n_180 : STD_LOGIC; signal SI_REG_n_45 : STD_LOGIC; signal SI_REG_n_83 : STD_LOGIC; signal SI_REG_n_84 : STD_LOGIC; signal SI_REG_n_85 : STD_LOGIC; signal SI_REG_n_86 : STD_LOGIC; signal \WR.aw_channel_0_n_2\ : STD_LOGIC; signal \WR.aw_channel_0_n_42\ : STD_LOGIC; signal \WR.aw_channel_0_n_43\ : STD_LOGIC; signal \WR.aw_channel_0_n_44\ : STD_LOGIC; signal \WR.aw_channel_0_n_45\ : STD_LOGIC; signal \WR.b_channel_0_n_1\ : STD_LOGIC; signal \WR.b_channel_0_n_2\ : STD_LOGIC; signal \WR.b_channel_0_n_3\ : STD_LOGIC; signal areset_d1 : STD_LOGIC; signal areset_d1_i_1_n_0 : STD_LOGIC; signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal b_push : STD_LOGIC; signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 2 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \gen_simple_ar.ar_pipe/m_valid_i0\ : STD_LOGIC; signal \gen_simple_ar.ar_pipe/p_1_in\ : STD_LOGIC; signal \gen_simple_aw.aw_pipe/p_1_in\ : STD_LOGIC; signal r_push : STD_LOGIC; signal r_rlast : STD_LOGIC; signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal shandshake : STD_LOGIC; signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_arlen : STD_LOGIC_VECTOR ( 2 downto 0 ); signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_arvalid : STD_LOGIC; signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_awvalid : STD_LOGIC; signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_bready : STD_LOGIC; signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_bvalid : STD_LOGIC; signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_rlast : STD_LOGIC; signal si_rs_rready : STD_LOGIC; signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); begin s_axi_arready <= \^s_axi_arready\; \RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel port map ( D(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1), E(0) => \gen_simple_ar.ar_pipe/p_1_in\, O(3) => SI_REG_n_145, O(2) => SI_REG_n_146, O(1) => SI_REG_n_147, O(0) => SI_REG_n_148, Q(30 downto 19) => s_arid(11 downto 0), Q(18 downto 16) => si_rs_arlen(2 downto 0), Q(15) => si_rs_arburst(1), Q(14) => SI_REG_n_103, Q(13 downto 12) => si_rs_arsize(1 downto 0), Q(11 downto 0) => si_rs_araddr(11 downto 0), S(3) => \RD.ar_channel_0_n_38\, S(2) => \RD.ar_channel_0_n_39\, S(1) => \RD.ar_channel_0_n_40\, S(0) => \RD.ar_channel_0_n_41\, aclk => aclk, areset_d1 => areset_d1, axaddr_offset(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0), \axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1), \cnt_read_reg[1]_rep__0\ => \RD.r_channel_0_n_1\, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \RD.ar_channel_0_n_8\, \m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_9\, \m_payload_i_reg[35]\ => SI_REG_n_161, \m_payload_i_reg[35]_0\ => SI_REG_n_163, \m_payload_i_reg[3]\ => SI_REG_n_173, \m_payload_i_reg[3]_0\(3) => SI_REG_n_83, \m_payload_i_reg[3]_0\(2) => SI_REG_n_84, \m_payload_i_reg[3]_0\(1) => SI_REG_n_85, \m_payload_i_reg[3]_0\(0) => SI_REG_n_86, \m_payload_i_reg[44]\ => SI_REG_n_162, \m_payload_i_reg[47]\ => SI_REG_n_164, \m_payload_i_reg[47]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1), \m_payload_i_reg[6]\(6) => SI_REG_n_166, \m_payload_i_reg[6]\(5) => SI_REG_n_167, \m_payload_i_reg[6]\(4) => SI_REG_n_168, \m_payload_i_reg[6]\(3) => SI_REG_n_169, \m_payload_i_reg[6]\(2) => SI_REG_n_170, \m_payload_i_reg[6]\(1) => SI_REG_n_171, \m_payload_i_reg[6]\(0) => SI_REG_n_172, \m_payload_i_reg[7]\(3) => SI_REG_n_141, \m_payload_i_reg[7]\(2) => SI_REG_n_142, \m_payload_i_reg[7]\(1) => SI_REG_n_143, \m_payload_i_reg[7]\(0) => SI_REG_n_144, m_valid_i0 => \gen_simple_ar.ar_pipe/m_valid_i0\, \r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0), r_push => r_push, r_rlast => r_rlast, s_axi_arvalid => s_axi_arvalid, s_ready_i_reg => \^s_axi_arready\, si_rs_arvalid => si_rs_arvalid, \wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\, \wrap_second_len_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 1) ); \RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel port map ( D(11 downto 0) => s_arid_r(11 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, m_valid_i_reg => \RD.r_channel_0_n_0\, \out\(33 downto 32) => si_rs_rresp(1 downto 0), \out\(31 downto 0) => si_rs_rdata(31 downto 0), r_push => r_push, r_rlast => r_rlast, s_ready_i_reg => SI_REG_n_165, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0), \skid_buffer_reg[46]\(0) => si_rs_rlast, \state_reg[1]_rep\ => \RD.r_channel_0_n_1\ ); SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice port map ( D(3 downto 2) => wrap_cnt(3 downto 2), D(1) => SI_REG_n_10, D(0) => wrap_cnt(0), E(0) => \gen_simple_aw.aw_pipe/p_1_in\, O(3) => SI_REG_n_145, O(2) => SI_REG_n_146, O(1) => SI_REG_n_147, O(0) => SI_REG_n_148, Q(54 downto 43) => s_awid(11 downto 0), Q(42 downto 39) => si_rs_awlen(3 downto 0), Q(38) => si_rs_awburst(1), Q(37) => SI_REG_n_45, Q(36 downto 35) => si_rs_awsize(1 downto 0), Q(34 downto 12) => Q(22 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_42\, S(2) => \WR.aw_channel_0_n_43\, S(1) => \WR.aw_channel_0_n_44\, S(0) => \WR.aw_channel_0_n_45\, aclk => aclk, aresetn => aresetn, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[3]\(3) => SI_REG_n_83, \axaddr_incr_reg[3]\(2) => SI_REG_n_84, \axaddr_incr_reg[3]\(1) => SI_REG_n_85, \axaddr_incr_reg[3]\(0) => SI_REG_n_86, \axaddr_incr_reg[7]\(3) => SI_REG_n_141, \axaddr_incr_reg[7]\(2) => SI_REG_n_142, \axaddr_incr_reg[7]\(1) => SI_REG_n_143, \axaddr_incr_reg[7]\(0) => SI_REG_n_144, axaddr_offset(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0), axaddr_offset_0(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0), \axaddr_offset_r_reg[0]\ => SI_REG_n_173, \axaddr_offset_r_reg[1]\ => SI_REG_n_161, \axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1), \axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0), \axaddr_offset_r_reg[3]_1\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1), \axlen_cnt_reg[3]\ => SI_REG_n_153, \axlen_cnt_reg[3]_0\ => SI_REG_n_164, b_push => b_push, \cnt_read_reg[0]_rep__1\ => SI_REG_n_165, \cnt_read_reg[3]_rep__0\ => \RD.r_channel_0_n_0\, \cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0), \cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0), \m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_38\, \m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_39\, \m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_40\, \m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_41\, m_valid_i0 => \gen_simple_ar.ar_pipe/m_valid_i0\, next_pending_r_reg => SI_REG_n_154, next_pending_r_reg_0 => SI_REG_n_162, \out\(11 downto 0) => si_rs_bid(11 downto 0), r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0), r_push_r_reg(0) => si_rs_rlast, \s_arid_r_reg[11]\(53 downto 42) => s_arid(11 downto 0), \s_arid_r_reg[11]\(41 downto 39) => si_rs_arlen(2 downto 0), \s_arid_r_reg[11]\(38) => si_rs_arburst(1), \s_arid_r_reg[11]\(37) => SI_REG_n_103, \s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0), \s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0), \s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => \^s_axi_arready\, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0), shandshake => shandshake, si_rs_arvalid => si_rs_arvalid, si_rs_awvalid => si_rs_awvalid, si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, si_rs_rready => si_rs_rready, \state_reg[0]_rep\ => \RD.ar_channel_0_n_9\, \state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_rep\ => \WR.aw_channel_0_n_2\, \state_reg[1]_rep_0\ => \RD.ar_channel_0_n_0\, \state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\, \state_reg[1]_rep_2\(0) => \gen_simple_ar.ar_pipe/p_1_in\, \wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_166, \wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_167, \wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_168, \wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_169, \wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_170, \wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_171, \wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_172, \wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_174, \wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_175, \wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_176, \wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_177, \wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_178, \wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_179, \wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_180, wrap_second_len(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0), \wrap_second_len_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1), \wrap_second_len_r_reg[2]_0\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 1), \wrap_second_len_r_reg[3]\ => SI_REG_n_163, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0) ); \WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel port map ( D(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0), E(0) => \gen_simple_aw.aw_pipe/p_1_in\, Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), S(3) => \WR.aw_channel_0_n_42\, S(2) => \WR.aw_channel_0_n_43\, S(1) => \WR.aw_channel_0_n_44\, S(0) => \WR.aw_channel_0_n_45\, aclk => aclk, areset_d1 => areset_d1, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_offset_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0), b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_3\, \cnt_read_reg[1]_rep__0_0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[46]\ => SI_REG_n_154, \m_payload_i_reg[47]\ => SI_REG_n_153, \m_payload_i_reg[61]\(31 downto 20) => s_awid(11 downto 0), \m_payload_i_reg[61]\(19 downto 16) => si_rs_awlen(3 downto 0), \m_payload_i_reg[61]\(15) => si_rs_awburst(1), \m_payload_i_reg[61]\(14) => SI_REG_n_45, \m_payload_i_reg[61]\(13 downto 12) => si_rs_awsize(1 downto 0), \m_payload_i_reg[61]\(11 downto 0) => si_rs_awaddr(11 downto 0), \m_payload_i_reg[6]\(6) => SI_REG_n_174, \m_payload_i_reg[6]\(5) => SI_REG_n_175, \m_payload_i_reg[6]\(4) => SI_REG_n_176, \m_payload_i_reg[6]\(3) => SI_REG_n_177, \m_payload_i_reg[6]\(2) => SI_REG_n_178, \m_payload_i_reg[6]\(1) => SI_REG_n_179, \m_payload_i_reg[6]\(0) => SI_REG_n_180, si_rs_awvalid => si_rs_awvalid, \wrap_boundary_axaddr_r_reg[0]\ => \WR.aw_channel_0_n_2\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 2) => wrap_cnt(3 downto 2), \wrap_second_len_r_reg[3]_1\(1) => SI_REG_n_10, \wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0) ); \WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel port map ( aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, \out\(11 downto 0) => si_rs_bid(11 downto 0), shandshake => shandshake, si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0), \state_reg[0]_rep\ => \WR.b_channel_0_n_3\ ); areset_d1_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aresetn, O => areset_d1_i_1_n_0 ); areset_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => areset_d1_i_1_n_0, Q => areset_d1, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute P_AXI4 : integer; attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0; attribute P_AXILITE : integer; attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2; attribute P_DECERR : string; attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b11"; attribute P_INCR : string; attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1; attribute P_SLVERR : string; attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b10"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal \^m_axi_wready\ : STD_LOGIC; signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_wvalid\ : STD_LOGIC; begin \^m_axi_wready\ <= m_axi_wready; \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); \^s_axi_wvalid\ <= s_axi_wvalid; m_axi_arburst(1) <= \<const0>\; m_axi_arburst(0) <= \<const1>\; m_axi_arcache(3) <= \<const0>\; m_axi_arcache(2) <= \<const0>\; m_axi_arcache(1) <= \<const0>\; m_axi_arcache(0) <= \<const0>\; m_axi_arid(11) <= \<const0>\; m_axi_arid(10) <= \<const0>\; m_axi_arid(9) <= \<const0>\; m_axi_arid(8) <= \<const0>\; m_axi_arid(7) <= \<const0>\; m_axi_arid(6) <= \<const0>\; m_axi_arid(5) <= \<const0>\; m_axi_arid(4) <= \<const0>\; m_axi_arid(3) <= \<const0>\; m_axi_arid(2) <= \<const0>\; m_axi_arid(1) <= \<const0>\; m_axi_arid(0) <= \<const0>\; m_axi_arlen(7) <= \<const0>\; m_axi_arlen(6) <= \<const0>\; m_axi_arlen(5) <= \<const0>\; m_axi_arlen(4) <= \<const0>\; m_axi_arlen(3) <= \<const0>\; m_axi_arlen(2) <= \<const0>\; m_axi_arlen(1) <= \<const0>\; m_axi_arlen(0) <= \<const0>\; m_axi_arlock(0) <= \<const0>\; m_axi_arqos(3) <= \<const0>\; m_axi_arqos(2) <= \<const0>\; m_axi_arqos(1) <= \<const0>\; m_axi_arqos(0) <= \<const0>\; m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(2) <= \<const0>\; m_axi_arsize(1) <= \<const1>\; m_axi_arsize(0) <= \<const0>\; m_axi_aruser(0) <= \<const0>\; m_axi_awburst(1) <= \<const0>\; m_axi_awburst(0) <= \<const1>\; m_axi_awcache(3) <= \<const0>\; m_axi_awcache(2) <= \<const0>\; m_axi_awcache(1) <= \<const0>\; m_axi_awcache(0) <= \<const0>\; m_axi_awid(11) <= \<const0>\; m_axi_awid(10) <= \<const0>\; m_axi_awid(9) <= \<const0>\; m_axi_awid(8) <= \<const0>\; m_axi_awid(7) <= \<const0>\; m_axi_awid(6) <= \<const0>\; m_axi_awid(5) <= \<const0>\; m_axi_awid(4) <= \<const0>\; m_axi_awid(3) <= \<const0>\; m_axi_awid(2) <= \<const0>\; m_axi_awid(1) <= \<const0>\; m_axi_awid(0) <= \<const0>\; m_axi_awlen(7) <= \<const0>\; m_axi_awlen(6) <= \<const0>\; m_axi_awlen(5) <= \<const0>\; m_axi_awlen(4) <= \<const0>\; m_axi_awlen(3) <= \<const0>\; m_axi_awlen(2) <= \<const0>\; m_axi_awlen(1) <= \<const0>\; m_axi_awlen(0) <= \<const0>\; m_axi_awlock(0) <= \<const0>\; m_axi_awqos(3) <= \<const0>\; m_axi_awqos(2) <= \<const0>\; m_axi_awqos(1) <= \<const0>\; m_axi_awqos(0) <= \<const0>\; m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(2) <= \<const0>\; m_axi_awsize(1) <= \<const1>\; m_axi_awsize(0) <= \<const0>\; m_axi_awuser(0) <= \<const0>\; m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); m_axi_wid(11) <= \<const0>\; m_axi_wid(10) <= \<const0>\; m_axi_wid(9) <= \<const0>\; m_axi_wid(8) <= \<const0>\; m_axi_wid(7) <= \<const0>\; m_axi_wid(6) <= \<const0>\; m_axi_wid(5) <= \<const0>\; m_axi_wid(4) <= \<const0>\; m_axi_wid(3) <= \<const0>\; m_axi_wid(2) <= \<const0>\; m_axi_wid(1) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast <= \<const1>\; m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); m_axi_wuser(0) <= \<const0>\; m_axi_wvalid <= \^s_axi_wvalid\; s_axi_buser(0) <= \<const0>\; s_axi_ruser(0) <= \<const0>\; s_axi_wready <= \^m_axi_wready\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s port map ( Q(22 downto 20) => m_axi_awprot(2 downto 0), Q(19 downto 0) => m_axi_awaddr(31 downto 12), aclk => aclk, aresetn => aresetn, \in\(33 downto 32) => m_axi_rresp(1 downto 0), \in\(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0), \m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0), \s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0), \s_axi_rid[11]\(34) => s_axi_rlast, \s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0), \s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of inst : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of inst : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of inst : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of inst : label is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of inst : label is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of inst : label is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of inst : label is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of inst : label is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of inst : label is 2; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; attribute P_AXI4 of inst : label is 0; attribute P_AXILITE : integer; attribute P_AXILITE of inst : label is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of inst : label is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of inst : label is 2; attribute P_DECERR : string; attribute P_DECERR of inst : label is "2'b11"; attribute P_INCR : string; attribute P_INCR of inst : label is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of inst : label is 1; attribute P_SLVERR : string; attribute P_SLVERR of inst : label is "2'b10"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN"; attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST"; attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY"; attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID"; attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY"; attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID"; attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY"; attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID"; attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY"; attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID"; attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY"; attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID"; attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR"; attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT"; attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR"; attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT"; attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP"; attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA"; attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP"; attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA"; attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB"; attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID"; attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS"; attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID"; attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS"; attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID"; attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID"; attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID"; attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter port map ( aclk => aclk, aresetn => aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0), m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => m_axi_arready, m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0), m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => m_axi_awready, m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => m_axi_awvalid, m_axi_bid(11 downto 0) => B"000000000000", m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_buser(0) => '0', m_axi_bvalid => m_axi_bvalid, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => B"000000000000", m_axi_rlast => '1', m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_ruser(0) => '0', m_axi_rvalid => m_axi_rvalid, m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0), m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED, m_axi_wready => m_axi_wready, m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), s_axi_awready => s_axi_awready, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', s_axi_awvalid => s_axi_awvalid, s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wuser(0) => '0', s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;

mit

ff0310c2b12f61b1120df388a413f37f

khaledhassan/vhdl-examples

decoder/decoder_tb.vhd

-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net> -- This software is distributed under the terms of the MIT License shown below. -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to -- deal in the Software without restriction, including without limitation the -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -- sell copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -- IN THE SOFTWARE. -- Testbench for binary to one-hot decoder. library ieee; use ieee.std_logic_1164.all; entity decoder_tb is end decoder_tb; architecture TB of decoder_tb is constant SELBITS : positive := 2; signal en : std_logic; signal sel : std_logic_vector(SELBITS-1 downto 0); signal hot : std_logic_vector(2**SELBITS-1 downto 0); begin -- Instantiate the unit under test (UUT) UUT : entity work.decoder generic map ( SELBITS => 2 ) port map ( sel => sel, en => en, hot => hot ); -- Stimulus process process begin en <= '1'; sel <= "00"; wait for 10 ns; sel <= "01"; wait for 10 ns; sel <= "10"; wait for 10 ns; sel <= "11"; wait for 10 ns; en <= '0'; wait for 10 ns; sel <= "00"; wait for 10 ns; wait; end process; end TB;

mit

28313462c896147f4042a973c8fc51de

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de0-nano/sdctrl16.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: sdctrl16 -- File: sdctrl16.vhd -- Author: Jiri Gaisler - Gaisler Research -- Modified by: Daniel Bengtsson & Richard Fång -- Description: 16- and 32-bit SDRAM memory controller. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library gaisler; use grlib.devices.all; use gaisler.memctrl.all; entity sdctrl16 is generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#f00#; ioaddr : integer := 16#000#; iomask : integer := 16#fff#; wprot : integer := 0; invclk : integer := 0; fast : integer := 0; pwron : integer := 0; sdbits : integer := 16; oepol : integer := 0; pageburst : integer := 0; mobile : integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; sdi : in sdctrl_in_type; sdo : out sdctrl_out_type ); end; architecture rtl of sdctrl16 is constant WPROTEN : boolean := wprot = 1; constant SDINVCLK : boolean := invclk = 1; constant BUS16 : boolean := (sdbits = 16); constant BUS32 : boolean := (sdbits = 32); constant BUS64 : boolean := (sdbits = 64); constant REVISION : integer := 1; constant PM_PD : std_logic_vector(2 downto 0) := "001"; constant PM_SR : std_logic_vector(2 downto 0) := "010"; constant PM_DPD : std_logic_vector(2 downto 0) := "101"; constant std_rammask: Std_Logic_Vector(31 downto 20) := Conv_Std_Logic_Vector(hmask, 12); constant hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0), 4 => ahb_membar(haddr, '1', '1', hmask), 5 => ahb_iobar(ioaddr, iomask), others => zero32); type mcycletype is (midle, active, leadout); type sdcycletype is (act1, act2, act3, act3_16, rd1, rd2, rd3, rd4, rd4_16, rd5, rd6, rd7, rd8, wr1, wr1_16, wr2, wr3, wr4, wr5, sidle, sref, pd, dpd); type icycletype is (iidle, pre, ref, lmode, emode, finish); -- sdram configuration register type sdram_cfg_type is record command : std_logic_vector(2 downto 0); csize : std_logic_vector(1 downto 0); bsize : std_logic_vector(2 downto 0); casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles trfc : std_logic_vector(2 downto 0); trp : std_ulogic; -- precharge to activate: 2/3 clock cycles refresh : std_logic_vector(14 downto 0); renable : std_ulogic; pageburst : std_ulogic; mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update) tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update) pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update) pmode : std_logic_vector(2 downto 0); -- Power-Saving mode txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing cke : std_ulogic; -- Clock enable end record; -- local registers type reg_type is record hready : std_ulogic; hsel : std_ulogic; bdrive : std_ulogic; nbdrive : std_ulogic; burst : std_ulogic; wprothit : std_ulogic; hio : std_ulogic; startsd : std_ulogic; lhw : std_ulogic; --Lower halfword mstate : mcycletype; sdstate : sdcycletype; cmstate : mcycletype; istate : icycletype; icnt : std_logic_vector(2 downto 0); haddr : std_logic_vector(31 downto 0); hrdata : std_logic_vector((sdbits-1)+((16/sdbits)*16) downto 0); hwdata : std_logic_vector(31 downto 0); hwrite : std_ulogic; htrans : std_logic_vector(1 downto 0); hresp : std_logic_vector(1 downto 0); size : std_logic_vector(1 downto 0); cfg : sdram_cfg_type; trfc : std_logic_vector(3 downto 0); refresh : std_logic_vector(14 downto 0); sdcsn : std_logic_vector(1 downto 0); sdwen : std_ulogic; rasn : std_ulogic; casn : std_ulogic; dqm : std_logic_vector(7 downto 0); address : std_logic_vector(16 downto 2); -- memory address bsel : std_ulogic; idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref end record; signal r, ri : reg_type; signal rbdrive, ribdrive : std_logic_vector(31 downto 0); attribute syn_preserve : boolean; attribute syn_preserve of rbdrive : signal is true; begin ctrl : process(rst, ahbsi, r, sdi, rbdrive) variable v : reg_type; -- local variables for registers variable startsd : std_ulogic; variable dataout : std_logic_vector(31 downto 0); -- data from memory variable regsd : std_logic_vector(31 downto 0); -- data from registers variable dqm : std_logic_vector(7 downto 0); variable raddr : std_logic_vector(12 downto 0); variable adec : std_ulogic; variable rams : std_logic_vector(1 downto 0); variable ba : std_logic_vector(1 downto 0); variable haddr : std_logic_vector(31 downto 0); variable dout : std_logic_vector(31 downto 0); variable hsize : std_logic_vector(1 downto 0); variable hwrite : std_ulogic; variable htrans : std_logic_vector(1 downto 0); variable hready : std_ulogic; variable vbdrive : std_logic_vector(31 downto 0); variable bdrive : std_ulogic; variable lline : std_logic_vector(2 downto 0); variable lineburst : boolean; variable haddr_tmp : std_logic_vector(31 downto 0); variable arefresh : std_logic; variable hwdata : std_logic_vector(31 downto 0); begin -- Variable default settings to avoid latches v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0'; if BUS16 then if (r.lhw = '1') then --muxes read data to correct part of the register. v.hrdata(sdbits-1 downto 0) := sdi.data(sdbits-1 downto 0); else v.hrdata((sdbits*2)-1 downto sdbits) := sdi.data(sdbits-1 downto 0); end if; else v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32); v.hrdata(31 downto 0) := sdi.data(31 downto 0); end if; hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata; lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel; if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then lineburst := true; else lineburst := false; end if; if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite; v.htrans := ahbsi.htrans; if ahbsi.htrans(1) = '1' then v.hio := ahbsi.hmbsel(1); v.hsel := '1'; v.hready := v.hio; end if; v.haddr := ahbsi.haddr; -- addr must be masked since address range can be smaller than -- total banksize. this can result in wrong chip select being -- asserted for i in 31 downto 20 loop v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i); end loop; end if; if (r.hsel = '1') and (ahbsi.hready = '0') then haddr := r.haddr; hsize := r.size; htrans := r.htrans; hwrite := r.hwrite; else haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0); htrans := ahbsi.htrans; hwrite := ahbsi.hwrite; -- addr must be masked since address range can be smaller than -- total banksize. this can result in wrong chip select being -- asserted for i in 31 downto 20 loop haddr(i) := ahbsi.haddr(i) and not std_rammask(i); end loop; end if; if fast = 1 then haddr := r.haddr; end if; if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if; -- main state if BUS16 then case r.size is when "00" => --bytesize case r.haddr(0) is when '0' => dqm := "11111101"; when others => dqm := "11111110"; end case; when others => dqm := "11111100"; --halfword, word end case; else case r.size is when "00" => case r.haddr(1 downto 0) is when "00" => dqm := "11110111"; when "01" => dqm := "11111011"; when "10" => dqm := "11111101"; when others => dqm := "11111110"; end case; when "01" => if r.haddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if; when others => dqm := "11110000"; end case; end if; -- -- case r.size is -- when "00" => -- case r.haddr(1 downto 0) is -- when "00" => dqm := "11111101"; lhw := '0'; --lhv := r.haddr(1) -- when "01" => dqm := "11111110"; lhw := '0'; -- when "10" => dqm := "11111101"; lhw := '1'; -- when others => dqm := "11111110"; lhw := '1'; -- end case; -- when "01" => -- dqm := "11111100"; -- if r.haddr(1) = '0' then -- lhw := '0'; -- else -- lhw := '1'; -- end if; -- when others => dqm := "11111100"; --remember when word: lhw first 0 then 1 -- end case; -- if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if; -- main FSM case r.mstate is when midle => if ((v.hsel and htrans(1) and not v.hio) = '1') then if (r.sdstate = sidle) and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0') then if fast = 0 then startsd := '1'; else v.startsd := '1'; end if; v.mstate := active; elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd)) and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0') then v.startsd := '1'; if r.sdstate = dpd then -- Error response when on Deep Power-Down mode v.hresp := HRESP_ERROR; else v.mstate := active; end if; end if; end if; when others => null; end case; startsd := startsd or r.startsd; -- generate row and column address size if BUS16 then case r.cfg.csize is when "00" => raddr := haddr(21 downto 9);-- case to check for bursting over row limit, since 1 row is 512 byte. when "01" => raddr := haddr(22 downto 10); when "10" => raddr := haddr(23 downto 11); when others => if r.cfg.bsize = "110" then raddr := haddr(25 downto 13); --tänk else raddr := haddr(24 downto 12); end if; end case; else case r.cfg.csize is when "00" => raddr := haddr(22 downto 10); when "01" => raddr := haddr(23 downto 11); when "10" => raddr := haddr(24 downto 12); when others => if r.cfg.bsize = "111" then raddr := haddr(26 downto 14); else raddr := haddr(25 downto 13); end if; end case; end if; -- generate bank address -- if BUS16 then --011 -- ba := genmux(r.cfg.bsize, haddr(26 downto 19)) & -- genmux(r.cfg.bsize, haddr(25 downto 18)); -- else ba := genmux(r.cfg.bsize, haddr(28 downto 21)) & genmux(r.cfg.bsize, haddr(27 downto 20)); -- end if; -- generate chip select if BUS64 then adec := genmux(r.cfg.bsize, haddr(30 downto 23)); v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22)); else adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0'; end if; -- elsif BUS32 then -- adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0'; -- else -- adec := genmux(r.cfg.bsize, haddr(27 downto 20)); v.bsel := '0'; -- end if; rams := adec & not adec; -- sdram access FSM if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if; if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if; case r.sdstate is when sidle => if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then -- if BUS16 then -- v.address(16 downto 2) := '0' & ba & raddr(11 downto 0); --since 1 bit lower row => tot adress field 14 bits -- else v.address(16 downto 2) := ba & raddr; -- ba(16-15) & raddr(14-2) (2+13= 15 bits) -- end if; v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1; v.startsd := '0'; elsif (r.idlecnt = "0000") and (r.cfg.command = "000") and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then case r.cfg.pmode is when PM_SR => v.cfg.cke := '0'; v.sdstate := sref; v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS) when PM_PD => v.cfg.cke := '0'; v.sdstate := pd; when PM_DPD => v.cfg.cke := '0'; v.sdstate := dpd; v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1'; when others => end case; end if; when act1 => v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; if r.cfg.casdel = '1' then v.sdstate := act2; else v.sdstate := act3; if not BUS16 then -- needs if, otherwise it might clock in incorrect write data to state act3_16 v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1); end if; end if; if WPROTEN then v.wprothit := sdi.wprot; if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if; end if; when act2 => v.sdstate := act3; if not BUS16 then v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1); end if; if WPROTEN and (r.wprothit = '1') then v.hresp := HRESP_ERROR; v.hready := '0'; end if; when act3 => v.casn := '0'; if BUS16 then --HW adress needed to memory v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits -- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits v.lhw := r.haddr(1); -- 14-2 = 12 colummn bits => 13 downto 2 else v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2); end if; v.dqm := dqm; v.burst := r.hready; -- ?? if r.hwrite = '1' then if BUS16 then --16 bit if r.size(1) = '1' then --word v.hready := ahbsi.htrans(0) and ahbsi.htrans(1); --delayed this check 1 state to keep write data correct in act3_16 v.burst := ahbsi.htrans(0) and ahbsi.htrans(1); v.sdstate := act3_16; -- goto state for second part of word transfer -- v.lhw := '0'; --write MSB 16 bits to AMBA adress that ends with 00 else --halfword or byte v.sdstate := act3_16; v.hready := '1'; end if; else --32 bit or 64 v.sdstate := wr1; if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if; end if; v.sdwen := '0'; v.bdrive := '0'; --write if WPROTEN and (r.wprothit = '1') then v.hresp := HRESP_ERROR; v.hready := '1'; if BUS16 then v.sdstate := act3_16; else v.sdstate := wr1; end if; v.sdwen := '1'; v.bdrive := '1'; v.casn := '1'; --skip write, remember hready high in next state end if; else v.sdstate := rd1; end if; when act3_16 => --handle 16 bit and WORD write v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 2) & '1'; -- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 2) & '1'; v.lhw := '1'; if (r.hready and r.burst) = '1' and not (WPROTEN and (r.wprothit = '1')) then v.hready := '0'; --kolla på transfertyp nonseq om vi vill delaya nedankoll. if( ahbsi.htrans = "11" and not ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) and not ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00") ) then v.sdstate := wr1_16; end if; elsif r.burst = '1' or (r.hready and not r.burst) = '1' then --terminate burst or single write v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1'; v.dqm := (others => '1'); else -- complete single write v.hready := '1'; v.sdstate := act3_16; --gick till wr1 förut end if; when wr1_16 => v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1); -- v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1); v.lhw := r.haddr(1); v.sdstate := act3_16; v.hready := '1'; when wr1 => v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2); if (((r.burst and r.hready) = '1') and (r.htrans = "11")) and not (WPROTEN and (r.wprothit = '1')) then v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready; if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh v.hready := '0'; end if; else v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1'; v.dqm := (others => '1'); end if; when wr2 => if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if; v.sdstate := wr3; when wr3 => if (r.cfg.trp = '1') then v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; else v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle; v.idlecnt := (others => '1'); end if; when wr4 => v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; if (r.cfg.trp = '1') then v.sdstate := wr5; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if; when wr5 => v.sdstate := sidle; v.idlecnt := (others => '1'); when rd1 => --first read applied to sdram v.casn := '1'; v.sdstate := rd7; --nop if not BUS16 then --starting adress cannot be XXXX...111 since we have word burst in this case. and lowest bit always 0. if lineburst and (ahbsi.htrans = "11") then if r.haddr(4 downto 2) = "111" then v.address(9 downto 5) := r.address(9 downto 5) + 1; --adds only within 1KB limit. v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; end if; when rd7 => v.casn := '1'; --nop if BUS16 then if r.cfg.casdel = '1' then --casdel3 v.sdstate := rd2; if lineburst and (ahbsi.htrans = "11") then if r.haddr(3 downto 1) = "110" then v.address(10 downto 5) := r.address(10 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; else --casdel2 v.sdstate := rd3; if ahbsi.htrans /= "11" then if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if; elsif lineburst then if r.haddr(3 downto 1) = "110" then v.address(10 downto 5) := r.address(10 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; end if; else -- 32 bit or larger if r.cfg.casdel = '1' then --casdel3 v.sdstate := rd2; if lineburst and (ahbsi.htrans = "11") then if r.haddr(4 downto 2) = "110" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; else --casdel2 v.sdstate := rd3; if ahbsi.htrans /= "11" then if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if; --precharge elsif lineburst then if r.haddr(4 downto 2) = "110" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; end if; end if; when rd2 => v.casn := '1'; v.sdstate := rd3; if BUS16 then if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM --note that DQM always has 2 cycle delay before blocking data. So NP if we fetch second HW end if; else if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM elsif lineburst then if r.haddr(4 downto 2) = "101" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; end if; when rd3 => --first read data from sdram output v.lhw := r.haddr(1); v.casn := '1'; --if read before cas makes nop else if pre => no difference if BUS16 then --note if read is for halfwor or byte we dont want to read a second time but exit. --if the read is a word we need to change LHW to one since the next read should be muxed in next cylcle. -- if r.size(1) = '1' then --word v.hready := not r.size(1) -- v.sdstate := rd4_16; v.hready := '0'; --hready low since just first part of a word -- v.lhw := '1'; -- read low 16 next state -- else --HW or byte -- v.sdstate := rd4_16; v.hready := '1'; -- end if; v.sdstate := rd4_16; v.lhw := not r.lhw; --r.lhw is 0 for word, we should invert for next half of word.For HW or Byte v.lhw does not matter. v.hready := not r.size(1); --if word transfer the r.size(1) is 1 and hready goes low.If HW or byte r.size(1)=0 => hready=1 if r.sdwen = '0' then v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP) elsif lineburst and ((ahbsi.htrans = "11") and (r.cfg.casdel = '1')) then --only enter if cl3 if r.haddr(3 downto 1) = "100" then v.address(10 downto 5) := r.address(10 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; else --32 bit or larger v.sdstate := rd4; v.hready := '1'; if r.sdwen = '0' then v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP) elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; end if; when rd4_16 => --enter as word (r.hready is still 0) else 1. If hready one next transfer sampled into v. --v.hready := '1'; v.hready := not r.hready;-- if Byte or HW exit with hready low. If word flip bit, makes correct exit with hready low. v.lhw := not r.lhw; --r.lhw is one the first time we enter (taking care of second part of word) v.casn := '1'; --quit on: Single transfer CL 2/3 (prcharge if CL 2 and timer was not 0) if (ahbsi.htrans /= "11" and (r.hready = '1')) or ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00" and r.hready = '1') or --probably dont have to check hready 1 since if 0 adresses equal. ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100") and (r.hready = '1')) then --quit on: ST W/HW/BYTE OR --v.hready := '0'; --if Byte or HW exit with hready low, if ST word exit with high. v.dqm := (others => '1'); if r.sdcsn /= "11" then --not prechargeing v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; --precharge else--exit if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if; end if; elsif lineburst then --NOTE: r.casn = 1 makes sure its the first halfword of a word that is checked (hready low) if r.cfg.casdel = '0' then if (r.haddr(3 downto 1) = "100") and (r.casn = '1') then --lline = 011 if casdel =1, 100 if casdel= 0 v.address(10 downto 5) := r.address(10 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; else if (r.haddr(3 downto 1) = "010") and (r.hready = '1') then --lline = 011 if casdel =1, 100 if casdel= 0 v.address(10 downto 5) := r.address(10 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; end if; when rd4 => v.hready := '1'; v.casn := '1'; if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh then v.hready := '0'; v.dqm := (others => '1'); if (r.sdcsn /= "11") then v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; else if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if; end if; elsif lineburst then if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; when rd5 => if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if; v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1'); v.casn := '1'; when rd6 => v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1'); v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; when sref => if (startsd = '1' and (r.hio = '0')) or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then if r.trfc = "0000" then -- Minimum duration (= tRAS) v.cfg.cke := '1'; v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1'; end if; if r.cfg.cke = '1' then if (r.idlecnt = "0000") then -- tXSR ns with NOP v.sdstate := sidle; v.idlecnt := (others => '1'); v.sref_tmpcom := r.cfg.command; v.cfg.command := "100"; end if; else v.idlecnt := r.cfg.txsr; end if; end if; when pd => if (startsd = '1' and (r.hio = '0')) or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then v.cfg.cke := '1'; v.sdstate := sidle; v.idlecnt := (others => '1'); end if; when dpd => v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1'; v.cfg.renable := '0'; if (startsd = '1' and r.hio = '0') then v.hready := '1'; -- ack all accesses with Error response v.startsd := '0'; v.hresp := HRESP_ERROR; elsif r.cfg.pmode /= PM_DPD then v.cfg.cke := '1'; if r.cfg.cke = '1' then v.sdstate := sidle; v.idlecnt := (others => '1'); v.cfg.renable := '1'; end if; end if; when others => v.sdstate := sidle; v.idlecnt := (others => '1'); end case; -- sdram commands case r.cmstate is when midle => if r.sdstate = sidle then case r.cfg.command is when "010" => -- precharge v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0'; v.address(12) := '1'; v.cmstate := active; when "100" => -- auto-refresh v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.cmstate := active; when "110" => -- Lodad Mode Reg v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.sdwen := '0'; v.cmstate := active; if lineburst then v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011"; else v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111"; end if; when "111" => -- Load Ext-Mode Reg v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.sdwen := '0'; v.cmstate := active; v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0); when others => null; end case; end if; when active => v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1'; v.sdwen := '1'; --v.cfg.command := "000"; v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000"; v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; when leadout => if r.trfc = "0000" then v.cmstate := midle; end if; end case; -- sdram init case r.istate is when iidle => v.cfg.cke := '1'; if r.cfg.renable = '1' and r.cfg.cke = '1' then v.cfg.command := "010"; v.istate := pre; end if; when pre => if r.cfg.command = "000" then v.cfg.command := "100"; v.istate := ref; v.icnt := "111"; end if; when ref => if r.cfg.command = "000" then v.cfg.command := "100"; v.icnt := r.icnt - 1; if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if; end if; when lmode => if r.cfg.command = "000" then if r.cfg.mobileen = "11" then v.cfg.command := "111"; v.istate := emode; else v.istate := finish; end if; end if; when emode => if r.cfg.command = "000" then v.istate := finish; end if; when others => if r.cfg.renable = '0' and r.sdstate /= dpd then v.istate := iidle; end if; end case; if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then if ahbsi.htrans(1) = '0' then v.hready := '1'; end if; end if; if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if; -- second part of main fsm case r.mstate is when active => if v.hready = '1' then v.mstate := midle; end if; when others => null; end case; -- sdram refresh counter -- pragma translate_off if not is_x(r.cfg.refresh) then -- pragma translate_on if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then v.refresh := r.refresh - 1; if (v.refresh(14) and not r.refresh(14)) = '1' then v.refresh := r.cfg.refresh; v.cfg.command := "100"; arefresh := '1'; end if; end if; -- pragma translate_off end if; -- pragma translate_on -- AHB register access -- if writing to IO space config regs. Just mapping write data to all config values in config reg if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then if r.haddr(3 downto 2) = "00" then if pageburst = 2 then v.cfg.pageburst := hwdata(17); end if; v.cfg.command := hwdata(20 downto 18); v.cfg.csize := hwdata(22 downto 21); v.cfg.bsize := hwdata(25 downto 23); v.cfg.casdel := hwdata(26); v.cfg.trfc := hwdata(29 downto 27); v.cfg.trp := hwdata(30); v.cfg.renable := hwdata(31); v.cfg.refresh := hwdata(14 downto 0); v.refresh := (others => '0'); elsif r.haddr(3 downto 2) = "01" then if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if; if r.cfg.pmode = "000" then v.cfg.cke := hwdata(30); end if; if r.cfg.mobileen(1) = '1' then v.cfg.txsr := hwdata(23 downto 20); v.cfg.pmode := hwdata(18 downto 16); v.cfg.ds(3 downto 2) := hwdata( 6 downto 5); v.cfg.tcsr(3 downto 2) := hwdata( 4 downto 3); v.cfg.pasr(5 downto 3) := hwdata( 2 downto 0); end if; end if; end if; -- Disable CS and DPD when Mobile SDR is Disabled if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if; -- Update EMR when ds, tcsr or pasr change if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2); end if; if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2); end if; if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3); end if; end if; regsd := (others => '0'); --reads out config registers (r/w does not matter) according to manual depending on address, notice generic determines data width. if r.haddr(3 downto 2) = "00" then regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc & r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command; if not lineburst then regsd(17) := '1'; end if; regsd(16) := r.cfg.mobileen(1); if BUS64 then regsd(15) := '1'; end if; regsd(14 downto 0) := r.cfg.refresh; elsif r.haddr(3 downto 2) = "01" then regsd(31) := r.cfg.mobileen(0); regsd(30) := r.cfg.cke; regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0); end if; if (r.hsel and r.hio) = '1' then dout := regsd; else if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32); else dout := r.hrdata(31 downto 0); end if; end if; v.nbdrive := not v.bdrive; if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive); else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if; -- reset if rst = '0' then v.sdstate := sidle; v.mstate := midle; v.istate := iidle; v.cmstate := midle; v.hsel := '0'; v.cfg.command := "000"; v.cfg.csize := "10"; v.cfg.bsize := "000"; v.cfg.casdel := '1'; v.cfg.trfc := "111"; if pwron = 1 then v.cfg.renable := '1'; else v.cfg.renable := '0'; end if; v.cfg.trp := '1'; v.dqm := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1'; v.hready := '1'; v.bsel := '0'; v.startsd := '0'; if (pageburst = 2) then v.cfg.pageburst := '0'; end if; if mobile >= 2 then v.cfg.mobileen := "11"; elsif mobile = 1 then v.cfg.mobileen := "10"; else v.cfg.mobileen := "00"; end if; v.cfg.txsr := (others => '1'); v.cfg.pmode := (others => '0'); v.cfg.ds := (others => '0'); v.cfg.tcsr := (others => '0'); v.cfg.pasr := (others => '0'); if mobile >= 2 then v.cfg.cke := '0'; else v.cfg.cke := '1'; end if; v.sref_tmpcom := "000"; v.idlecnt := (others => '1'); end if; ri <= v; ribdrive <= vbdrive; ahbso.hready <= r.hready; ahbso.hresp <= r.hresp; ahbso.hrdata <= ahbdrivedata(dout); end process; --sdo.sdcke <= (others => '1'); sdo.sdcke <= (others => r.cfg.cke); ahbso.hconfig <= hconfig; ahbso.hirq <= (others => '0'); ahbso.hindex <= hindex; ahbso.hsplit <= (others => '0'); -- Quick hack to get rid of undriven signal warnings. Check this for future -- merge with main sdctrl. drivehack : block begin sdo.qdrive <= '0'; sdo.nbdrive <= '0'; sdo.ce <= '0'; sdo.moben <= '0'; sdo.cal_rst <= '0'; sdo.oct <= '0'; sdo.xsdcsn <= (others => '1'); sdo.data(127 downto 16) <= (others => '0'); sdo.cb <= (others => '0'); sdo.ba <= (others => '0'); sdo.sdck <= (others => '0'); sdo.cal_en <= (others => '0'); sdo.cal_inc <= (others => '0'); sdo.cal_pll <= (others => '0'); sdo.odt <= (others => '0'); sdo.conf <= (others => '0'); sdo.vcbdrive <= (others => '0'); sdo.dqs_gate <= '0'; sdo.cbdqm <= (others => '0'); sdo.cbcal_en <= (others => '0'); sdo.cbcal_inc <= (others => '0'); sdo.read_pend <= (others => '0'); sdo.regwdata <= (others => '0'); sdo.regwrite <= (others => '0'); end block drivehack; regs : process(clk, rst) begin if rising_edge(clk) then r <= ri; rbdrive <= ribdrive; if rst = '0' then r.icnt <= (others => '0'); end if; end if; if (rst = '0') then r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0'; if oepol = 0 then rbdrive <= (others => '1'); else rbdrive <= (others => '0'); end if; end if; end process; rgen : if not SDINVCLK generate sdo.address <= r.address; sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive; sdo.vbdrive <= zero32 & rbdrive; sdo.sdcsn <= r.sdcsn; sdo.sdwen <= r.sdwen; sdo.dqm <= "11111111" & r.dqm; sdo.rasn <= r.rasn; sdo.casn <= r.casn; mux16_wrdata : if BUS16 generate --mux data depending on Low/High HW sdo.data(15 downto 0) <= r.hwdata(15 downto 0) when r.lhw = '1' else r.hwdata(31 downto 16); end generate; wrdata : if not BUS16 generate drivebus: for i in 0 to sdbits/64 generate sdo.data(31+32*i downto 32*i) <= r.hwdata; end generate; end generate; end generate; ngen : if SDINVCLK generate nregs : process(clk, rst) begin if falling_edge(clk) then sdo.address <= r.address; if oepol = 1 then sdo.bdrive <= r.nbdrive; else sdo.bdrive <= r.bdrive; end if; sdo.vbdrive <= zero32 & rbdrive; sdo.sdcsn <= r.sdcsn; sdo.sdwen <= r.sdwen; sdo.dqm <= "11111111" & r.dqm; sdo.rasn <= r.rasn; sdo.casn <= r.casn; if BUS16 then --mux data depending on Low/High HW if (r.lhw ='1') then sdo.data(15 downto 0) <= r.hwdata(15 downto 0); else sdo.data(15 downto 0) <= r.hwdata(31 downto 16); end if; end if; if not BUS16 then for i in 0 to sdbits/64 loop sdo.data(31+32*i downto 32*i) <= r.hwdata; end loop; end if; end if; if rst = '0' then sdo.sdcsn <= (others => '1'); end if; end process; end generate; -- pragma translate_off bootmsg : report_version generic map ("sdctrl16" & tost(hindex) & ": PC133 SDRAM controller rev " & tost(REVISION)); -- pragma translate_on end;

gpl-2.0

af47f1dc5c585620166813b12c451426

kloboves/sicxe

vhdl/sicxe_core.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity sicxe_core is Port ( clock_i : in std_logic; reset_i : in std_logic; enable_i : in std_logic; error_o : out std_logic; -- memory memory_read_o : out std_logic; memory_write_o : out std_logic; memory_address_o : out std_logic_vector(19 downto 0); memory_data_in_i : in std_logic_vector(7 downto 0); memory_data_out_o : out std_logic_vector(7 downto 0); memory_done_i : in std_logic; -- device ports port_id_o : out std_logic_vector(7 downto 0); port_in_i : in std_logic_vector(7 downto 0); port_out_o : out std_logic_vector(7 downto 0); port_read_strobe_o : out std_logic; port_write_strobe_o : out std_logic; -- interrupt interrupt_i : in std_logic; interrupt_acknowledge_o : out std_logic; interrupt_enabled_o : out std_logic ); end sicxe_core; architecture behavioral of sicxe_core is -- opcodes constant OPCODE_LONG_EINT : std_logic_vector := "11111000"; constant OPCODE_LONG_DINT : std_logic_vector := "11111001"; constant OPCODE_LONG_RINT : std_logic_vector := "11111010"; constant OPCODE_LONG_CLEAR : std_logic_vector := "10110100"; constant OPCODE_LONG_RMO : std_logic_vector := "10101100"; constant OPCODE_LONG_ADDR : std_logic_vector := "10010000"; constant OPCODE_LONG_SUBR : std_logic_vector := "10010100"; constant OPCODE_LONG_MULR : std_logic_vector := "10011000"; constant OPCODE_LONG_SHIFTL : std_logic_vector := "10100100"; constant OPCODE_LONG_SHIFTR : std_logic_vector := "10101000"; constant OPCODE_LONG_COMPR : std_logic_vector := "10100000"; constant OPCODE_LONG_TIXR : std_logic_vector := "10111000"; constant OPCODE_LONG_ANDR : std_logic_vector := "11110100"; constant OPCODE_LONG_ORR : std_logic_vector := "11110101"; constant OPCODE_LONG_XORR : std_logic_vector := "11110110"; constant OPCODE_LONG_NOT : std_logic_vector := "11110111"; constant OPCODE_SHORT_ADD : std_logic_vector := "000110"; constant OPCODE_SHORT_SUB : std_logic_vector := "000111"; constant OPCODE_SHORT_MUL : std_logic_vector := "001000"; constant OPCODE_SHORT_AND : std_logic_vector := "010000"; constant OPCODE_SHORT_OR : std_logic_vector := "010001"; constant OPCODE_SHORT_COMP : std_logic_vector := "001010"; constant OPCODE_SHORT_TIX : std_logic_vector := "001011"; constant OPCODE_SHORT_J : std_logic_vector := "001111"; constant OPCODE_SHORT_JEQ : std_logic_vector := "001100"; constant OPCODE_SHORT_JGT : std_logic_vector := "001101"; constant OPCODE_SHORT_JLT : std_logic_vector := "001110"; constant OPCODE_SHORT_JSUB : std_logic_vector := "010010"; constant OPCODE_SHORT_RSUB : std_logic_vector := "010011"; constant OPCODE_SHORT_LDCH : std_logic_vector := "010100"; constant OPCODE_SHORT_LDA : std_logic_vector := "000000"; constant OPCODE_SHORT_LDB : std_logic_vector := "011010"; constant OPCODE_SHORT_LDL : std_logic_vector := "000010"; constant OPCODE_SHORT_LDS : std_logic_vector := "011011"; constant OPCODE_SHORT_LDT : std_logic_vector := "011101"; constant OPCODE_SHORT_LDX : std_logic_vector := "000001"; constant OPCODE_SHORT_STCH : std_logic_vector := "010101"; constant OPCODE_SHORT_STSW : std_logic_vector := "111010"; constant OPCODE_SHORT_STA : std_logic_vector := "000011"; constant OPCODE_SHORT_STB : std_logic_vector := "011110"; constant OPCODE_SHORT_STL : std_logic_vector := "000101"; constant OPCODE_SHORT_STS : std_logic_vector := "011111"; constant OPCODE_SHORT_STT : std_logic_vector := "100001"; constant OPCODE_SHORT_STX : std_logic_vector := "000100"; constant OPCODE_SHORT_TD : std_logic_vector := "111000"; constant OPCODE_SHORT_RD : std_logic_vector := "110110"; constant OPCODE_SHORT_WD : std_logic_vector := "110111"; constant OPCODE_SHORT_XOR : std_logic_vector := "111100"; constant OPCODE_SHORT_STIL : std_logic_vector := "111111"; -- ALU type alu_operation_type is (ALU_ZERO, ALU_PASS1, ALU_PASS2, ALU_ADD, ALU_SUB, ALU_MUL, ALU_AND, ALU_OR, ALU_XOR, ALU_NOT, ALU_SHIFTL, ALU_SHIFTR); signal alu_operation : alu_operation_type; signal alu_operand1 : std_logic_vector(23 downto 0); signal alu_operand2 : std_logic_vector(23 downto 0); signal alu_shift_bits : std_logic_vector(3 downto 0); signal alu_result : std_logic_vector(23 downto 0); signal alu_compare_result_left : std_logic_vector(1 downto 0); signal alu_compare_result_right : std_logic_vector(1 downto 0); -- general registers signal reg_general_a : std_logic_vector(23 downto 0); signal reg_general_x : std_logic_vector(23 downto 0); signal reg_general_l : std_logic_vector(23 downto 0); signal reg_general_b : std_logic_vector(23 downto 0); signal reg_general_s : std_logic_vector(23 downto 0); signal reg_general_t : std_logic_vector(23 downto 0); signal reg_general_write : std_logic; signal reg_general_select : std_logic_vector(3 downto 0); signal reg_general_select_write : std_logic; type select_general_type is (SELECT_GENERAL_A, SELECT_GENERAL_X, SELECT_GENERAL_L, SELECT_GENERAL_R1, SELECT_GENERAL_R2, SELECT_GENERAL_LOAD_INSN); signal select_general : select_general_type; -- operand registers signal reg_operand1 : std_logic_vector(23 downto 0); signal reg_operand2 : std_logic_vector(23 downto 0); signal reg_operand3 : std_logic_vector(23 downto 0); signal reg_operand1_write : std_logic; signal reg_operand2_write : std_logic; signal reg_operand3_write : std_logic; -- result register signal reg_result : std_logic_vector(23 downto 0); signal reg_result_write : std_logic; -- special registers signal reg_special_target : std_logic_vector(23 downto 0); signal reg_special_pc : std_logic_vector(19 downto 0); signal reg_special_il : std_logic_vector(19 downto 0); signal reg_special_cc : std_logic_vector(1 downto 0); signal reg_special_icc : std_logic_vector(1 downto 0); signal reg_special_target_write : std_logic; signal reg_special_pc_write : std_logic; signal reg_special_pc_write_cond : std_logic; signal reg_special_il_write : std_logic; signal reg_special_cc_clear : std_logic; signal reg_special_cc_write_left : std_logic; signal reg_special_cc_write_right : std_logic; signal reg_special_cc_save : std_logic; signal reg_special_cc_restore : std_logic; -- conditional PC write signal reg_special_pc_write_cond_lt : std_logic; signal reg_special_pc_write_cond_eq : std_logic; signal reg_special_pc_write_cond_gt : std_logic; -- interrupt enable register signal reg_interrupt : std_logic; signal reg_interrupt_next : std_logic; signal interrupt_disable : std_logic; signal interrupt_enable : std_logic; signal interrupt_move : std_logic; -- memory data register signal reg_memory_data : std_logic_vector(23 downto 0); signal reg_memory_data_write_result : std_logic; signal reg_memory_data_write_mem : std_logic_vector(2 downto 0); -- device data register signal reg_device_data : std_logic_vector(7 downto 0); signal reg_device_data_write_result : std_logic; signal reg_device_data_write_dev : std_logic; -- instruction register signal reg_instruction : std_logic_vector(31 downto 0); signal reg_instruction_write : std_logic_vector(3 downto 0); signal insn_opcode : std_logic_vector(7 downto 0); signal insn_flag_n : std_logic; signal insn_flag_i : std_logic; signal insn_flag_x : std_logic; signal insn_flag_b : std_logic; signal insn_flag_p : std_logic; signal insn_flag_e : std_logic; signal insn_r1 : std_logic_vector(3 downto 0); signal insn_r2 : std_logic_vector(3 downto 0); signal insn_operand_f3_usgn : std_logic_vector(23 downto 0); signal insn_operand_f3_sgn : std_logic_vector(23 downto 0); signal insn_operand_f4_usgn : std_logic_vector(23 downto 0); signal insn_operand_sic : std_logic_vector(23 downto 0); signal insn_r1_valid : std_logic; signal insn_r2_valid : std_logic; -- operand select type select_op1_type is (SELECT_OP1_ROP1, SELECT_OP1_X, SELECT_OP1_TARGET, SELECT_OP1_PC, SELECT_OP1_IL, SELECT_OP1_MEM, SELECT_OP1_MEM_BYTE, SELECT_OP1_DEV, SELECT_OP1_F3USGN, SELECT_OP1_F3SGN, SELECT_OP1_F4USGN, SELECT_OP1_SIC); signal select_op1 : select_op1_type; type select_op2_type is (SELECT_OP2_CONE, SELECT_OP2_CIV, SELECT_OP2_ROP2, SELECT_OP2_ROP3, SELECT_OP2_A, SELECT_OP2_X, SELECT_OP2_B, SELECT_OP2_L, SELECT_OP2_PC, SELECT_OP2_SW); signal select_op2 : select_op2_type; -- memory address select type select_addr_type is (SELECT_ADDR_PC, SELECT_ADDR_TARGET); signal select_addr : select_addr_type; -- memory out data select type select_mem_type is (SELECT_MEM_BYTE0, SELECT_MEM_BYTE1, SELECT_MEM_BYTE2); signal select_mem : select_mem_type; -- control unit FSM type ctl_state_type is (CTL_ERROR, CTL_DISABLED, CTL_INSN0, CTL_DECODE0, CTL_F1_EINT, CTL_F1_DINT, CTL_F1_RINT, CTL_F2_INSN1, CTL_F2_DECODE1, CTL_F2_ALU0, CTL_F2_ALU1, CTL_F2_COMP, CTL_F2_TIX0, CTL_F2_TIX1, CTL_F2_TIX2, CTL_F34_INSN1, CTL_F34_INSN2, CTL_F34_INSN3, CTL_F34_DECODE1, CTL_F34_DECODE2, CTL_F34_INDEXED, CTL_F34_INDIRECT0, CTL_F34_INDIRECT1, CTL_F34_INDIRECT2, CTL_F34_INDIRECT3, CTL_F34_RSUB, CTL_F34B_LOAD0, CTL_F34B_LOAD1, CTL_F34B_DECODE3, CTL_F34B_WD0, CTL_F34B_WD1, CTL_F34B_WD2, CTL_F34B_TD, CTL_F34B_RD0, CTL_F34B_RD1, CTL_F34B_RD2, CTL_F34B_RD3, CTL_F34B_LDCH0, CTL_F34B_LDCH1, CTL_F34B_STSW, CTL_F34B_STCH, CTL_F34W_STR0, CTL_F34W_STR1, CTL_F34W_STIL, CTL_F34_STORE0, CTL_F34_STORE1, CTL_F34_STORE2, CTL_F34_JUMP, CTL_F34_JSUB0, CTL_F34_JSUB1, CTL_F34W_LOAD0, CTL_F34W_LOAD1, CTL_F34W_LOAD2, CTL_F34W_LOAD3, CTL_F34W_DECODE3, CTL_F34W_LDR0, CTL_F34W_LDR1, CTL_F34W_COMP, CTL_F34W_TIX0, CTL_F34W_TIX1, CTL_F34W_TIX2, CTL_F34W_ALU0, CTL_F34W_ALU1, CTL_INT0, CTL_INT1, CTL_INT2, CTL_INT3, CTL_INT4, CTL_INT5); signal ctl_state : ctl_state_type; signal ctl_next_state : ctl_state_type; begin -- ALU alu_proc : process(alu_operation, alu_operand1, alu_operand2, alu_shift_bits) begin alu_result <= (others => '0'); case (alu_operation) is when ALU_ZERO => alu_result <= (others => '0'); when ALU_PASS1 => alu_result <= alu_operand1; when ALU_PASS2 => alu_result <= alu_operand2; when ALU_ADD => alu_result <= std_logic_vector(signed(alu_operand2) + signed(alu_operand1)); when ALU_SUB => alu_result <= std_logic_vector(signed(alu_operand2) - signed(alu_operand1)); when ALU_MUL => alu_result <= std_logic_vector( resize(signed(alu_operand2) * signed(alu_operand1), 24)); when ALU_AND => alu_result <= std_logic_vector(signed(alu_operand2) and signed(alu_operand1)); when ALU_OR => alu_result <= std_logic_vector(signed(alu_operand2) or signed(alu_operand1)); when ALU_XOR => alu_result <= std_logic_vector(signed(alu_operand2) xor signed(alu_operand1)); when ALU_NOT => alu_result <= std_logic_vector(not signed(alu_operand1)); when ALU_SHIFTL => alu_result <= std_logic_vector( signed(alu_operand1) sll to_integer(unsigned(alu_shift_bits))); when ALU_SHIFTR => alu_result <= std_logic_vector(shift_right(signed(alu_operand1), to_integer(unsigned(alu_shift_bits)))); when others => end case; end process; alu_compare_proc : process(alu_operand1, alu_operand2) begin if (signed(alu_operand1) < signed(alu_operand2)) then alu_compare_result_left <= "00"; alu_compare_result_right <= "10"; elsif (signed(alu_operand1) = signed(alu_operand2)) then alu_compare_result_left <= "01"; alu_compare_result_right <= "01"; else alu_compare_result_left <= "10"; alu_compare_result_right <= "00"; end if; end process; -- general registers reg_general_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_general_a <= (others => '0'); reg_general_x <= (others => '0'); reg_general_l <= (others => '0'); reg_general_b <= (others => '0'); reg_general_s <= (others => '0'); reg_general_t <= (others => '0'); else reg_general_a <= reg_general_a; reg_general_x <= reg_general_x; reg_general_l <= reg_general_l; reg_general_b <= reg_general_b; reg_general_s <= reg_general_s; reg_general_t <= reg_general_t; if (reg_general_write = '1') then case (reg_general_select) is when x"0" => reg_general_a <= reg_result; when x"1" => reg_general_x <= reg_result; when x"2" => reg_general_l <= reg_result; when x"3" => reg_general_b <= reg_result; when x"4" => reg_general_s <= reg_result; when x"5" => reg_general_t <= reg_result; when others => end case; end if; end if; end if; end process; reg_general_select_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_general_select <= x"0"; else reg_general_select <= reg_general_select; if (reg_general_select_write = '1') then case (select_general) is when SELECT_GENERAL_A => reg_general_select <= x"0"; when SELECT_GENERAL_X => reg_general_select <= x"1"; when SELECT_GENERAL_L => reg_general_select <= x"2"; when SELECT_GENERAL_R1 => reg_general_select <= insn_r1; when SELECT_GENERAL_R2 => reg_general_select <= insn_r2; when SELECT_GENERAL_LOAD_INSN => case (insn_opcode(7 downto 2)) is when OPCODE_SHORT_LDA => reg_general_select <= x"0"; when OPCODE_SHORT_LDX => reg_general_select <= x"1"; when OPCODE_SHORT_LDL => reg_general_select <= x"2"; when OPCODE_SHORT_LDB => reg_general_select <= x"3"; when OPCODE_SHORT_LDS => reg_general_select <= x"4"; when OPCODE_SHORT_LDT => reg_general_select <= x"5"; when others => reg_general_select <= x"0"; end case; when others => end case; end if; end if; end if; end process; -- special registers reg_special_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_special_target <= (others => '0'); reg_special_pc <= (others => '0'); reg_special_il <= (others => '0'); reg_special_cc <= (others => '0'); reg_special_icc <= (others => '0'); else reg_special_target <= reg_special_target; reg_special_pc <= reg_special_pc; reg_special_il <= reg_special_il; reg_special_cc <= reg_special_cc; reg_special_icc <= reg_special_icc; if (reg_special_target_write = '1') then reg_special_target <= alu_result; end if; if (reg_special_pc_write = '1' or reg_special_pc_write_cond = '1') then reg_special_pc <= alu_result(19 downto 0); end if; if (reg_special_il_write = '1') then reg_special_il <= alu_result(19 downto 0); end if; if (reg_special_cc_clear = '1') then reg_special_cc <= (others => '0'); elsif (reg_special_cc_write_left = '1') then reg_special_cc <= alu_compare_result_left; elsif (reg_special_cc_write_right = '1') then reg_special_cc <= alu_compare_result_right; elsif (reg_special_cc_restore = '1') then reg_special_cc <= reg_special_icc; end if; if (reg_special_cc_save = '1') then reg_special_icc <= reg_special_cc; end if; end if; end if; end process; -- conditional PC write reg_special_pc_write_cond_proc : process(reg_special_cc, reg_special_pc_write_cond_lt, reg_special_pc_write_cond_eq, reg_special_pc_write_cond_gt) begin reg_special_pc_write_cond <= '0'; case (reg_special_cc) is when "00" => reg_special_pc_write_cond <= reg_special_pc_write_cond_lt; when "01" => reg_special_pc_write_cond <= reg_special_pc_write_cond_eq; when "10" => reg_special_pc_write_cond <= reg_special_pc_write_cond_gt; when others => end case; end process; -- operand registers reg_operand_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_operand1 <= (others => '0'); reg_operand2 <= (others => '0'); reg_operand3 <= (others => '0'); else reg_operand1 <= reg_operand1; reg_operand2 <= reg_operand2; reg_operand3 <= reg_operand3; if (reg_operand1_write = '1') then case (insn_r1) is when x"0" => reg_operand1 <= reg_general_a; when x"1" => reg_operand1 <= reg_general_x; when x"2" => reg_operand1 <= reg_general_l; when x"3" => reg_operand1 <= reg_general_b; when x"4" => reg_operand1 <= reg_general_s; when x"5" => reg_operand1 <= reg_general_t; when others => end case; end if; if (reg_operand2_write = '1') then case (insn_r2) is when x"0" => reg_operand2 <= reg_general_a; when x"1" => reg_operand2 <= reg_general_x; when x"2" => reg_operand2 <= reg_general_l; when x"3" => reg_operand2 <= reg_general_b; when x"4" => reg_operand2 <= reg_general_s; when x"5" => reg_operand2 <= reg_general_t; when others => end case; end if; if (reg_operand3_write = '1') then case (insn_opcode(7 downto 2)) is when OPCODE_SHORT_STA => reg_operand3 <= reg_general_a; when OPCODE_SHORT_STX => reg_operand3 <= reg_general_x; when OPCODE_SHORT_STL => reg_operand3 <= reg_general_l; when OPCODE_SHORT_STB => reg_operand3 <= reg_general_b; when OPCODE_SHORT_STS => reg_operand3 <= reg_general_s; when OPCODE_SHORT_STT => reg_operand3 <= reg_general_t; when others => end case; end if; end if; end if; end process; -- result register reg_result_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_result <= (others => '0'); else if (reg_result_write = '1') then reg_result <= alu_result; else reg_result <= reg_result; end if; end if; end if; end process; -- interrupt enable register reg_interrupt_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_interrupt <= '0'; reg_interrupt_next <= '0'; else if (interrupt_disable = '1') then reg_interrupt <= '0'; reg_interrupt_next <= '0'; else if (interrupt_move = '1') then reg_interrupt <= reg_interrupt_next; else reg_interrupt <= reg_interrupt; end if; if (interrupt_enable = '1') then reg_interrupt_next <= '1'; else reg_interrupt_next <= reg_interrupt_next; end if; end if; end if; end if; end process; -- memory data register reg_memory_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_memory_data <= (others => '0'); else if (reg_memory_data_write_result = '1') then reg_memory_data <= alu_result; else reg_memory_data <= reg_memory_data; if (reg_memory_data_write_mem(0) = '1') then reg_memory_data(7 downto 0) <= memory_data_in_i; end if; if (reg_memory_data_write_mem(1) = '1') then reg_memory_data(15 downto 8) <= memory_data_in_i; end if; if (reg_memory_data_write_mem(2) = '1') then reg_memory_data(23 downto 16) <= memory_data_in_i; end if; end if; end if; end if; end process; -- device data register reg_device_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_device_data <= (others => '0'); else if (reg_device_data_write_result = '1') then reg_device_data <= alu_result(7 downto 0); elsif (reg_device_data_write_dev = '1') then reg_device_data <= port_in_i; else reg_device_data <= reg_device_data; end if; end if; end if; end process; -- instruction register reg_instruction_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_instruction <= (others => '0'); else reg_instruction <= reg_instruction; if (reg_instruction_write(0) = '1') then reg_instruction(7 downto 0) <= memory_data_in_i; end if; if (reg_instruction_write(1) = '1') then reg_instruction(15 downto 8) <= memory_data_in_i; end if; if (reg_instruction_write(2) = '1') then reg_instruction(23 downto 16) <= memory_data_in_i; end if; if (reg_instruction_write(3) = '1') then reg_instruction(31 downto 24) <= memory_data_in_i; end if; end if; end if; end process; insn_opcode <= reg_instruction(31 downto 24); insn_flag_n <= reg_instruction(25); insn_flag_i <= reg_instruction(24); insn_flag_x <= reg_instruction(23); insn_flag_b <= reg_instruction(22); insn_flag_p <= reg_instruction(21); insn_flag_e <= reg_instruction(20); insn_r1 <= reg_instruction(23 downto 20); insn_r2 <= reg_instruction(19 downto 16); insn_operand_f3_usgn <= std_logic_vector( resize(unsigned(reg_instruction(19 downto 8)), 24)); insn_operand_f3_sgn <= std_logic_vector( resize(signed(reg_instruction(19 downto 8)), 24)); insn_operand_f4_usgn <= std_logic_vector( resize(unsigned(reg_instruction(19 downto 0)), 24)); insn_operand_sic <= std_logic_vector( resize(unsigned(reg_instruction(22 downto 8)), 24)); insn_r1_valid_proc : process(insn_r1) begin case (insn_r1) is when x"0" | x"1" | x"2" | x"3" | x"4" | x"5" => insn_r1_valid <= '1'; when others => insn_r1_valid <= '0'; end case; end process; insn_r2_valid_proc : process(insn_r2) begin case (insn_r2) is when x"0" | x"1" | x"2" | x"3" | x"4" | x"5" => insn_r2_valid <= '1'; when others => insn_r2_valid <= '0'; end case; end process; -- operand select select_op1_proc : process(select_op1, reg_operand1, reg_general_x, reg_special_target, reg_special_pc, reg_special_il, reg_memory_data, reg_device_data, insn_operand_f3_usgn, insn_operand_f3_sgn, insn_operand_f4_usgn, insn_operand_sic) begin case (select_op1) is when SELECT_OP1_ROP1 => alu_operand1 <= reg_operand1; when SELECT_OP1_X => alu_operand1 <= reg_general_x; when SELECT_OP1_TARGET => alu_operand1 <= reg_special_target; when SELECT_OP1_PC => alu_operand1 <= "0000" & reg_special_pc; when SELECT_OP1_IL => alu_operand1 <= "0000" & reg_special_il; when SELECT_OP1_MEM => alu_operand1 <= reg_memory_data; when SELECT_OP1_MEM_BYTE => alu_operand1 <= x"0000" & reg_memory_data(7 downto 0); when SELECT_OP1_DEV => alu_operand1 <= x"0000" & reg_device_data; when SELECT_OP1_F3USGN => alu_operand1 <= insn_operand_f3_usgn; when SELECT_OP1_F3SGN => alu_operand1 <= insn_operand_f3_sgn; when SELECT_OP1_F4USGN => alu_operand1 <= insn_operand_f4_usgn; when SELECT_OP1_SIC => alu_operand1 <= insn_operand_sic; when others => alu_operand1 <= (others => '0'); end case; end process; select_op2_proc : process(select_op2, reg_operand2, reg_operand3, reg_general_a, reg_general_x, reg_general_b, reg_general_l, reg_special_pc, reg_interrupt, reg_special_icc, reg_special_cc) begin case (select_op2) is when SELECT_OP2_CONE => alu_operand2 <= x"000001"; when SELECT_OP2_CIV => alu_operand2 <= x"0ffffd"; when SELECT_OP2_ROP2 => alu_operand2 <= reg_operand2; when SELECT_OP2_ROP3 => alu_operand2 <= reg_operand3; when SELECT_OP2_A => alu_operand2 <= reg_general_a; when SELECT_OP2_X => alu_operand2 <= reg_general_x; when SELECT_OP2_B => alu_operand2 <= reg_general_b; when SELECT_OP2_L => alu_operand2 <= reg_general_l; when SELECT_OP2_PC => alu_operand2 <= "0000" & reg_special_pc; when SELECT_OP2_SW => alu_operand2 <= x"0000" & "000" & reg_interrupt & reg_special_icc & reg_special_cc; when others => alu_operand2 <= (others => '0'); end case; end process; -- memory address select select_addr_proc : process(select_addr, reg_special_target, reg_special_pc) begin case (select_addr) is when SELECT_ADDR_PC => memory_address_o <= reg_special_pc; when SELECT_ADDR_TARGET => memory_address_o <= reg_special_target(19 downto 0); when others => memory_address_o <= (others => '0'); end case; end process; -- memory out data select select_mem_proc : process(select_mem, reg_memory_data) begin case (select_mem) is when SELECT_MEM_BYTE0 => memory_data_out_o <= reg_memory_data(7 downto 0); when SELECT_MEM_BYTE1 => memory_data_out_o <= reg_memory_data(15 downto 8); when SELECT_MEM_BYTE2 => memory_data_out_o <= reg_memory_data(23 downto 16); when others => memory_data_out_o <= (others => '0'); end case; end process; -- other connections port_id_o <= reg_special_target(7 downto 0); port_out_o <= reg_device_data; alu_shift_bits <= insn_r2; interrupt_enabled_o <= reg_interrupt; -- control unit FSM ctl_sync_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then ctl_state <= CTL_DISABLED; else ctl_state <= ctl_next_state; end if; end if; end process; ctl_state_proc : process(ctl_state, enable_i, interrupt_i, reg_interrupt, insn_opcode, insn_r1_valid, insn_r2_valid, insn_flag_n, insn_flag_i, insn_flag_x, insn_flag_b, insn_flag_p, insn_flag_e, memory_done_i) begin ctl_next_state <= ctl_state; case (ctl_state) is -- special states when CTL_ERROR => when CTL_DISABLED => if (enable_i = '1') then if (reg_interrupt = '1' and interrupt_i = '1') then ctl_next_state <= CTL_INT0; else ctl_next_state <= CTL_INSN0; end if; end if; -- instruction read & decode when CTL_INSN0 => if (memory_done_i = '1') then ctl_next_state <= CTL_DECODE0; end if; when CTL_DECODE0 => case (insn_opcode) is when OPCODE_LONG_EINT => ctl_next_state <= CTL_F1_EINT; when OPCODE_LONG_DINT => ctl_next_state <= CTL_F1_DINT; when OPCODE_LONG_RINT => ctl_next_state <= CTL_F1_RINT; when OPCODE_LONG_CLEAR | OPCODE_LONG_RMO | OPCODE_LONG_ADDR | OPCODE_LONG_SUBR | OPCODE_LONG_MULR | OPCODE_LONG_SHIFTL | OPCODE_LONG_SHIFTR | OPCODE_LONG_COMPR | OPCODE_LONG_TIXR | OPCODE_LONG_ANDR | OPCODE_LONG_ORR | OPCODE_LONG_XORR | OPCODE_LONG_NOT => ctl_next_state <= CTL_F2_INSN1; when others => case (insn_opcode(7 downto 2)) is when OPCODE_SHORT_ADD | OPCODE_SHORT_SUB |OPCODE_SHORT_MUL | OPCODE_SHORT_AND |OPCODE_SHORT_OR | OPCODE_SHORT_COMP | OPCODE_SHORT_TIX | OPCODE_SHORT_J | OPCODE_SHORT_JEQ | OPCODE_SHORT_JGT | OPCODE_SHORT_JLT | OPCODE_SHORT_JSUB | OPCODE_SHORT_RSUB | OPCODE_SHORT_LDCH | OPCODE_SHORT_LDA | OPCODE_SHORT_LDB | OPCODE_SHORT_LDL | OPCODE_SHORT_LDS | OPCODE_SHORT_LDT | OPCODE_SHORT_LDX | OPCODE_SHORT_STCH | OPCODE_SHORT_STSW | OPCODE_SHORT_STA | OPCODE_SHORT_STB | OPCODE_SHORT_STL | OPCODE_SHORT_STS | OPCODE_SHORT_STT | OPCODE_SHORT_STX | OPCODE_SHORT_TD | OPCODE_SHORT_RD | OPCODE_SHORT_WD | OPCODE_SHORT_XOR | OPCODE_SHORT_STIL => ctl_next_state <= CTL_F34_INSN1; when others => ctl_next_state <= CTL_ERROR; end case; end case; -- format 1 instructions when CTL_F1_EINT | CTL_F1_DINT => if (enable_i = '1') then ctl_next_state <= CTL_INSN0; else ctl_next_state <= CTL_DISABLED; end if; -- format 2 instructions when CTL_F2_INSN1 => if (memory_done_i = '1') then ctl_next_state <= CTL_F2_DECODE1; end if; when CTL_F2_DECODE1 => case (insn_opcode) is when OPCODE_LONG_CLEAR | OPCODE_LONG_NOT | OPCODE_LONG_SHIFTL | OPCODE_LONG_SHIFTR => if (insn_r1_valid = '1') then ctl_next_state <= CTL_F2_ALU0; else ctl_next_state <= CTL_ERROR; end if; when OPCODE_LONG_COMPR => if (insn_r1_valid = '1' and insn_r2_valid = '1') then ctl_next_state <= CTL_F2_COMP; else ctl_next_state <= CTL_ERROR; end if; when OPCODE_LONG_TIXR => if (insn_r1_valid = '1') then ctl_next_state <= CTL_F2_TIX0; else ctl_next_state <= CTL_ERROR; end if; when others => if (insn_r1_valid = '1' and insn_r2_valid = '1') then ctl_next_state <= CTL_F2_ALU0; else ctl_next_state <= CTL_ERROR; end if; end case; when CTL_F2_ALU0 => ctl_next_state <= CTL_F2_ALU1; when CTL_F2_TIX0 => ctl_next_state <= CTL_F2_TIX1; when CTL_F2_TIX1 => ctl_next_state <= CTL_F2_TIX2; -- format S34 instructions when CTL_F34_INSN1 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34_INSN2; end if; when CTL_F34_INSN2 => if (memory_done_i = '1') then if (insn_flag_e = '1') then ctl_next_state <= CTL_F34_INSN3; else ctl_next_state <= CTL_F34_DECODE1; end if; end if; when CTL_F34_INSN3 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34_DECODE1; end if; when CTL_F34_DECODE1 => if (insn_opcode(7 downto 2) = OPCODE_SHORT_RSUB) then ctl_next_state <= CTL_F34_RSUB; else if (insn_flag_n = '0' and insn_flag_i = '0') then -- simple addressing (SIC) if (insn_flag_x = '1') then ctl_next_state <= CTL_F34_INDEXED; else ctl_next_state <= CTL_F34_DECODE2; end if; else if ((insn_flag_b = '1' and insn_flag_p = '1') or (insn_flag_e = '1' and (insn_flag_b = '1' or insn_flag_p = '1'))) then -- invalid addressing ctl_next_state <= CTL_ERROR; else if (insn_flag_n = '1' and insn_flag_i = '1') then -- simple addressing if (insn_flag_x = '1') then ctl_next_state <= CTL_F34_INDEXED; else ctl_next_state <= CTL_F34_DECODE2; end if; else if (insn_flag_x = '1') then -- invalid addressing ctl_next_state <= CTL_ERROR; else if (insn_flag_n = '0' and insn_flag_i = '1') then -- immediate addressing ctl_next_state <= CTL_F34_DECODE2; else -- indirect addressing ctl_next_state <= CTL_F34_INDIRECT0; end if; end if; end if; end if; end if; end if; when CTL_F34_INDEXED => ctl_next_state <= CTL_F34_DECODE2; when CTL_F34_INDIRECT0 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34_INDIRECT1; end if; when CTL_F34_INDIRECT1 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34_INDIRECT2; end if; when CTL_F34_INDIRECT2 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34_INDIRECT3; end if; when CTL_F34_INDIRECT3 => ctl_next_state <= CTL_F34_DECODE2; when CTL_F34_DECODE2 => case (insn_opcode(7 downto 2)) is when OPCODE_SHORT_LDCH | OPCODE_SHORT_TD | OPCODE_SHORT_RD | OPCODE_SHORT_WD => if (insn_flag_n = '0' and insn_flag_i = '1') then ctl_next_state <= CTL_F34B_DECODE3; else ctl_next_state <= CTL_F34B_LOAD0; end if; when OPCODE_SHORT_STSW => if (insn_flag_n = '0' and insn_flag_i = '1') then ctl_next_state <= CTL_ERROR; else ctl_next_state <= CTL_F34B_STSW; end if; when OPCODE_SHORT_STCH => if (insn_flag_n = '0' and insn_flag_i = '1') then ctl_next_state <= CTL_ERROR; else ctl_next_state <= CTL_F34B_STCH; end if; when OPCODE_SHORT_STIL => if (insn_flag_n = '0' and insn_flag_i = '1') then ctl_next_state <= CTL_ERROR; else ctl_next_state <= CTL_F34W_STIL; end if; when OPCODE_SHORT_STA | OPCODE_SHORT_STB | OPCODE_SHORT_STL | OPCODE_SHORT_STS | OPCODE_SHORT_STT | OPCODE_SHORT_STX => if (insn_flag_n = '0' and insn_flag_i = '1') then ctl_next_state <= CTL_ERROR; else ctl_next_state <= CTL_F34W_STR0; end if; when OPCODE_SHORT_J | OPCODE_SHORT_JEQ | OPCODE_SHORT_JGT | OPCODE_SHORT_JLT => ctl_next_state <= CTL_F34_JUMP; when OPCODE_SHORT_JSUB => ctl_next_state <= CTL_F34_JSUB0; when others => if (insn_flag_n = '0' and insn_flag_i = '1') then ctl_next_state <= CTL_F34W_DECODE3; else ctl_next_state <= CTL_F34W_LOAD0; end if; end case; -- format S34 instructions - device operations and load byte when CTL_F34B_LOAD0 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34B_LOAD1; end if; when CTL_F34B_LOAD1 => ctl_next_state <= CTL_F34B_DECODE3; when CTL_F34B_DECODE3 => case (insn_opcode(7 downto 2)) is when OPCODE_SHORT_LDCH => ctl_next_state <= CTL_F34B_LDCH0; when OPCODE_SHORT_TD => ctl_next_state <= CTL_F34B_TD; when OPCODE_SHORT_RD => ctl_next_state <= CTL_F34B_RD0; when OPCODE_SHORT_WD => ctl_next_state <= CTL_F34B_WD0; when others => end case; when CTL_F34B_RD0 => ctl_next_state <= CTL_F34B_RD1; when CTL_F34B_RD1 => ctl_next_state <= CTL_F34B_RD2; when CTL_F34B_RD2 => ctl_next_state <= CTL_F34B_RD3; when CTL_F34B_WD0 => ctl_next_state <= CTL_F34B_WD1; when CTL_F34B_WD1 => ctl_next_state <= CTL_F34B_WD2; when CTL_F34B_LDCH0 => ctl_next_state <= CTL_F34B_LDCH1; -- format S34 instructions - store when CTL_F34B_STSW => ctl_next_state <= CTL_F34_STORE2; when CTL_F34B_STCH => ctl_next_state <= CTL_F34_STORE2; when CTL_F34W_STR0 => ctl_next_state <= CTL_F34W_STR1; when CTL_F34W_STR1 => ctl_next_state <= CTL_F34_STORE0; when CTL_F34W_STIL => ctl_next_state <= CTL_F34_STORE0; when CTL_F34_STORE0 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34_STORE1; end if; when CTL_F34_STORE1 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34_STORE2; end if; when CTL_F34_STORE2 => if (memory_done_i = '1') then if (enable_i = '1') then if (reg_interrupt = '1' and interrupt_i = '1') then ctl_next_state <= CTL_INT0; else ctl_next_state <= CTL_INSN0; end if; else ctl_next_state <= CTL_DISABLED; end if; end if; -- format S34 instructions - jump when CTL_F34_JSUB0 => ctl_next_state <= CTL_F34_JSUB1; -- format S34 instructions - load, ALU and others when CTL_F34W_LOAD0 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34W_LOAD1; end if; when CTL_F34W_LOAD1 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34W_LOAD2; end if; when CTL_F34W_LOAD2 => if (memory_done_i = '1') then ctl_next_state <= CTL_F34W_LOAD3; end if; when CTL_F34W_LOAD3 => ctl_next_state <= CTL_F34W_DECODE3; when CTL_F34W_DECODE3 => case (insn_opcode(7 downto 2)) is when OPCODE_SHORT_LDA | OPCODE_SHORT_LDB | OPCODE_SHORT_LDL | OPCODE_SHORT_LDS | OPCODE_SHORT_LDT | OPCODE_SHORT_LDX => ctl_next_state <= CTL_F34W_LDR0; when OPCODE_SHORT_COMP => ctl_next_state <= CTL_F34W_COMP; when OPCODE_SHORT_TIX => ctl_next_state <= CTL_F34W_TIX0; when OPCODE_SHORT_ADD | OPCODE_SHORT_SUB | OPCODE_SHORT_MUL | OPCODE_SHORT_AND | OPCODE_SHORT_OR | OPCODE_SHORT_XOR => ctl_next_state <= CTL_F34W_ALU0; when others => end case; when CTL_F34W_LDR0 => ctl_next_state <= CTL_F34W_LDR1; when CTL_F34W_TIX0 => ctl_next_state <= CTL_F34W_TIX1; when CTL_F34W_TIX1 => ctl_next_state <= CTL_F34W_TIX2; when CTL_F34W_ALU0 => ctl_next_state <= CTL_F34W_ALU1; -- interrupt cycle when CTL_INT0 => ctl_next_state <= CTL_INT1; when CTL_INT1 => ctl_next_state <= CTL_INT2; when CTL_INT2 => if (memory_done_i = '1') then ctl_next_state <= CTL_INT3; end if; when CTL_INT3 => if (memory_done_i = '1') then ctl_next_state <= CTL_INT4; end if; when CTL_INT4 => if (memory_done_i = '1') then ctl_next_state <= CTL_INT5; end if; when CTL_INT5 => if (enable_i = '1') then ctl_next_state <= CTL_INSN0; else ctl_next_state <= CTL_DISABLED; end if; -- shared logic for last state of many instructions when CTL_F1_RINT | CTL_F2_ALU1 | CTL_F2_COMP | CTL_F2_TIX2 | CTL_F34_RSUB | CTL_F34B_TD | CTL_F34B_RD3 | CTL_F34B_WD2 | CTL_F34B_LDCH1 | CTL_F34_JUMP | CTL_F34_JSUB1 | CTL_F34W_LDR1 | CTL_F34W_COMP | CTL_F34W_TIX2 | CTL_F34W_ALU1 => if (enable_i = '1') then if (reg_interrupt = '1' and interrupt_i = '1') then ctl_next_state <= CTL_INT0; else ctl_next_state <= CTL_INSN0; end if; else ctl_next_state <= CTL_DISABLED; end if; when others => end case; end process; ctl_output_proc : process(ctl_state, insn_opcode, memory_done_i, insn_flag_n, insn_flag_i, insn_flag_x, insn_flag_b, insn_flag_p, insn_flag_e) begin error_o <= '0'; memory_read_o <= '0'; memory_write_o <= '0'; port_read_strobe_o <= '0'; port_write_strobe_o <= '0'; interrupt_acknowledge_o <= '0'; alu_operation <= ALU_ZERO; reg_general_write <= '0'; reg_general_select_write <= '0'; select_general <= SELECT_GENERAL_A; reg_operand1_write <= '0'; reg_operand2_write <= '0'; reg_operand3_write <= '0'; reg_result_write <= '0'; reg_special_target_write <= '0'; reg_special_pc_write <= '0'; reg_special_il_write <= '0'; reg_special_cc_clear <= '0'; reg_special_cc_write_left <= '0'; reg_special_cc_write_right <= '0'; reg_special_cc_save <= '0'; reg_special_cc_restore <= '0'; reg_special_pc_write_cond_lt <= '0'; reg_special_pc_write_cond_eq <= '0'; reg_special_pc_write_cond_gt <= '0'; interrupt_disable <= '0'; interrupt_enable <= '0'; interrupt_move <= '0'; reg_memory_data_write_result <= '0'; reg_memory_data_write_mem <= (others => '0'); reg_device_data_write_result <= '0'; reg_device_data_write_dev <= '0'; reg_instruction_write <= (others => '0'); select_op1 <= SELECT_OP1_ROP1; select_op2 <= SELECT_OP2_CONE; select_addr <= SELECT_ADDR_PC; select_mem <= SELECT_MEM_BYTE0; case (ctl_state) is -- special state when CTL_ERROR => error_o <= '1'; when CTL_DISABLED => -- instruction read & decode when CTL_INSN0 => select_op1 <= SELECT_OP1_PC; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_PC; memory_read_o <= '1'; if (memory_done_i = '1') then reg_instruction_write(3) <= '1'; reg_special_pc_write <= '1'; interrupt_move <= '1'; end if; when CTL_DECODE0 => -- format 1 instructions when CTL_F1_EINT => interrupt_enable <= '1'; when CTL_F1_DINT => interrupt_disable <= '1'; when CTL_F1_RINT => select_op1 <= SELECT_OP1_IL; alu_operation <= ALU_PASS1; reg_special_pc_write <= '1'; reg_special_cc_restore <= '1'; -- format 2 instructions when CTL_F2_INSN1 => select_op1 <= SELECT_OP1_PC; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_PC; memory_read_o <= '1'; if (memory_done_i = '1') then reg_instruction_write(2) <= '1'; reg_special_pc_write <= '1'; end if; when CTL_F2_DECODE1 => reg_operand1_write <= '1'; reg_operand2_write <= '1'; when CTL_F2_ALU0 => select_op1 <= SELECT_OP1_ROP1; select_op2 <= SELECT_OP2_ROP2; reg_result_write <= '1'; reg_general_select_write <= '1'; case (insn_opcode) is when OPCODE_LONG_CLEAR | OPCODE_LONG_NOT | OPCODE_LONG_SHIFTL | OPCODE_LONG_SHIFTR => select_general <= SELECT_GENERAL_R1; when others => select_general <= SELECT_GENERAL_R2; end case; case (insn_opcode) is when OPCODE_LONG_CLEAR => alu_operation <= ALU_ZERO; when OPCODE_LONG_RMO => alu_operation <= ALU_PASS1; when OPCODE_LONG_ADDR => alu_operation <= ALU_ADD; when OPCODE_LONG_SUBR => alu_operation <= ALU_SUB; when OPCODE_LONG_MULR => alu_operation <= ALU_MUL; when OPCODE_LONG_SHIFTL => alu_operation <= ALU_SHIFTL; when OPCODE_LONG_SHIFTR => alu_operation <= ALU_SHIFTR; when OPCODE_LONG_ANDR => alu_operation <= ALU_AND; when OPCODE_LONG_ORR => alu_operation <= ALU_OR; when OPCODE_LONG_XORR => alu_operation <= ALU_XOR; when OPCODE_LONG_NOT => alu_operation <= ALU_NOT; when others => end case; when CTL_F2_ALU1 => reg_general_write <= '1'; when CTL_F2_COMP => select_op1 <= SELECT_OP1_ROP1; select_op2 <= SELECT_OP2_ROP2; reg_special_cc_write_left <= '1'; when CTL_F2_TIX0 => select_op1 <= SELECT_OP1_X; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; reg_result_write <= '1'; reg_general_select_write <= '1'; select_general <= SELECT_GENERAL_X; when CTL_F2_TIX1 => reg_general_write <= '1'; when CTL_F2_TIX2 => select_op1 <= SELECT_OP1_ROP1; select_op2 <= SELECT_OP2_X; reg_special_cc_write_right <= '1'; -- format S34 instructions when CTL_F34_INSN1 => select_op1 <= SELECT_OP1_PC; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_PC; memory_read_o <= '1'; if (memory_done_i = '1') then reg_instruction_write(2) <= '1'; reg_special_pc_write <= '1'; end if; when CTL_F34_INSN2 => select_op1 <= SELECT_OP1_PC; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_PC; memory_read_o <= '1'; if (memory_done_i = '1') then reg_instruction_write(1) <= '1'; reg_special_pc_write <= '1'; end if; when CTL_F34_INSN3 => select_op1 <= SELECT_OP1_PC; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_PC; memory_read_o <= '1'; if (memory_done_i = '1') then reg_instruction_write(0) <= '1'; reg_special_pc_write <= '1'; end if; when CTL_F34_DECODE1 => if (insn_flag_n = '0' and insn_flag_i = '0') then select_op1 <= SELECT_OP1_SIC; else if (insn_flag_e = '1') then select_op1 <= SELECT_OP1_F4USGN; else if (insn_flag_p = '1') then select_op1 <= SELECT_OP1_F3SGN; else select_op1 <= SELECT_OP1_F3USGN; end if; end if; end if; if (insn_flag_b = '1' and insn_flag_p = '0') then select_op2 <= SELECT_OP2_B; alu_operation <= ALU_ADD; elsif (insn_flag_b = '0' and insn_flag_p = '1') then select_op2 <= SELECT_OP2_PC; alu_operation <= ALU_ADD; else alu_operation <= ALU_PASS1; end if; reg_special_target_write <= '1'; when CTL_F34_INDEXED => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_X; alu_operation <= ALU_ADD; reg_special_target_write <= '1'; when CTL_F34_INDIRECT0 => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(2) <= '1'; reg_special_target_write <= '1'; end if; when CTL_F34_INDIRECT1 => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(1) <= '1'; reg_special_target_write <= '1'; end if; when CTL_F34_INDIRECT2 => select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(0) <= '1'; end if; when CTL_F34_INDIRECT3 => select_op1 <= SELECT_OP1_MEM; alu_operation <= ALU_PASS1; reg_special_target_write <= '1'; when CTL_F34_DECODE2 => -- format S34 instructions - rsub when CTL_F34_RSUB => select_op2 <= SELECT_OP2_L; alu_operation <= ALU_PASS2; reg_special_pc_write <= '1'; -- format S34 instructions - device operations and load byte when CTL_F34B_LOAD0 => select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(0) <= '1'; end if; when CTL_F34B_LOAD1 => select_op1 <= SELECT_OP1_MEM_BYTE; alu_operation <= ALU_PASS1; reg_special_target_write <= '1'; when CTL_F34B_DECODE3 => select_general <= SELECT_GENERAL_A; reg_general_select_write <= '1'; when CTL_F34B_TD => reg_special_cc_clear <= '1'; when CTL_F34B_RD0 => when CTL_F34B_RD1 => port_read_strobe_o <= '1'; reg_device_data_write_dev <= '1'; when CTL_F34B_RD2 => select_op1 <= SELECT_OP1_DEV; alu_operation <= ALU_PASS1; reg_result_write <= '1'; when CTL_F34B_RD3 => reg_general_write <= '1'; when CTL_F34B_WD0 => select_op2 <= SELECT_OP2_A; alu_operation <= ALU_PASS2; reg_device_data_write_result <= '1'; when CTL_F34B_WD1 => when CTL_F34B_WD2 => port_write_strobe_o <= '1'; when CTL_F34B_LDCH0 => select_op1 <= SELECT_OP1_TARGET; alu_operation <= ALU_PASS1; reg_result_write <= '1'; when CTL_F34B_LDCH1 => reg_general_write <= '1'; -- format S34 instructions - store when CTL_F34B_STSW => select_op2 <= SELECT_OP2_SW; alu_operation <= ALU_PASS2; reg_memory_data_write_result <= '1'; when CTL_F34B_STCH => select_op2 <= SELECT_OP2_A; alu_operation <= ALU_PASS2; reg_memory_data_write_result <= '1'; when CTL_F34W_STR0 => reg_operand3_write <= '1'; when CTL_F34W_STR1 => select_op2 <= SELECT_OP2_ROP3; alu_operation <= ALU_PASS2; reg_memory_data_write_result <= '1'; when CTL_F34_STORE0 => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_TARGET; select_mem <= SELECT_MEM_BYTE2; memory_write_o <= '1'; if (memory_done_i = '1') then reg_special_target_write <= '1'; end if; when CTL_F34_STORE1 => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_TARGET; select_mem <= SELECT_MEM_BYTE1; memory_write_o <= '1'; if (memory_done_i = '1') then reg_special_target_write <= '1'; end if; when CTL_F34_STORE2 => select_addr <= SELECT_ADDR_TARGET; select_mem <= SELECT_MEM_BYTE0; memory_write_o <= '1'; -- format S34 instructions - jump when CTL_F34_JUMP => select_op1 <= SELECT_OP1_TARGET; alu_operation <= ALU_PASS1; case (insn_opcode(7 downto 2)) is when OPCODE_SHORT_J => reg_special_pc_write <= '1'; when OPCODE_SHORT_JLT => reg_special_pc_write_cond_lt <= '1'; when OPCODE_SHORT_JEQ => reg_special_pc_write_cond_eq <= '1'; when OPCODE_SHORT_JGT => reg_special_pc_write_cond_gt <= '1'; when others => end case; when CTL_F34_JSUB0 => select_general <= SELECT_GENERAL_L; reg_general_select_write <= '1'; select_op1 <= SELECT_OP1_PC; alu_operation <= ALU_PASS1; reg_result_write <= '1'; when CTL_F34_JSUB1 => reg_general_write <= '1'; select_op1 <= SELECT_OP1_TARGET; alu_operation <= ALU_PASS1; reg_special_pc_write <= '1'; -- format S34 instructions - load, ALU and others when CTL_F34W_LOAD0 => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(2) <= '1'; reg_special_target_write <= '1'; end if; when CTL_F34W_LOAD1 => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(1) <= '1'; reg_special_target_write <= '1'; end if; when CTL_F34W_LOAD2 => select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(0) <= '1'; end if; when CTL_F34W_LOAD3 => select_op1 <= SELECT_OP1_MEM; alu_operation <= ALU_PASS1; reg_special_target_write <= '1'; when CTL_F34W_DECODE3 => when CTL_F34W_LDR0 => select_general <= SELECT_GENERAL_LOAD_INSN; reg_general_select_write <= '1'; select_op1 <= SELECT_OP1_TARGET; alu_operation <= ALU_PASS1; reg_result_write <= '1'; when CTL_F34W_LDR1 => reg_general_write <= '1'; when CTL_F34W_COMP => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_A; reg_special_cc_write_right <= '1'; when CTL_F34W_TIX0 => select_op1 <= SELECT_OP1_X; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; reg_result_write <= '1'; reg_general_select_write <= '1'; select_general <= SELECT_GENERAL_X; when CTL_F34W_TIX1 => reg_general_write <= '1'; when CTL_F34W_TIX2 => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_X; reg_special_cc_write_right <= '1'; when CTL_F34W_ALU0 => select_general <= SELECT_GENERAL_A; reg_general_select_write <= '1'; reg_result_write <= '1'; select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_A; case (insn_opcode(7 downto 2)) is when OPCODE_SHORT_ADD => alu_operation <= ALU_ADD; when OPCODE_SHORT_SUB => alu_operation <= ALU_SUB; when OPCODE_SHORT_MUL => alu_operation <= ALU_MUL; when OPCODE_SHORT_AND => alu_operation <= ALU_AND; when OPCODE_SHORT_OR => alu_operation <= ALU_OR; when OPCODE_SHORT_XOR => alu_operation <= ALU_XOR; when others => end case; when CTL_F34W_ALU1 => reg_general_write <= '1'; -- interrupt cycle when CTL_INT0 => interrupt_acknowledge_o <= '1'; interrupt_disable <= '1'; select_op1 <= SELECT_OP1_PC; alu_operation <= ALU_PASS1; reg_special_il_write <= '1'; reg_special_cc_save <= '1'; when CTL_INT1 => select_op2 <= SELECT_OP2_CIV; alu_operation <= ALU_PASS2; reg_special_target_write <= '1'; when CTL_INT2 => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(2) <= '1'; reg_special_target_write <= '1'; end if; when CTL_INT3 => select_op1 <= SELECT_OP1_TARGET; select_op2 <= SELECT_OP2_CONE; alu_operation <= ALU_ADD; select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(1) <= '1'; reg_special_target_write <= '1'; end if; when CTL_INT4 => select_addr <= SELECT_ADDR_TARGET; memory_read_o <= '1'; if (memory_done_i = '1') then reg_memory_data_write_mem(0) <= '1'; end if; when CTL_INT5 => select_op1 <= SELECT_OP1_MEM; alu_operation <= ALU_PASS1; reg_special_pc_write <= '1'; when others => end case; end process; end behavioral;

mit

2f0e60fd136590c8ab474b88d1293b49

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-digilent-nexys4/testbench.vhd

----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; use work.debug.all; use work.config.all; entity testbench is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; clkperiod : integer := 10 -- system clock period ); end; architecture behav of testbench is constant promfile : string := "prom.srec"; -- rom contents constant sdramfile : string := "ram.srec"; -- sdram contents constant lresp : boolean := false; constant ct : integer := clkperiod/2; signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal rstn : std_logic; signal error : std_logic; -- PROM flash signal address : std_logic_vector(26 downto 0):=(others =>'0'); signal data : std_logic_vector(31 downto 0); signal RamCE : std_logic; signal oen : std_ulogic; signal writen : std_ulogic; -- Debug support unit signal dsubre : std_ulogic; -- AHB Uart signal dsurx : std_ulogic; signal dsutx : std_ulogic; -- APB Uart signal urxd : std_ulogic; signal utxd : std_ulogic; -- Ethernet signals signal erx_er : std_ulogic; signal erx_crs : std_ulogic; signal etxdt : std_logic_vector(1 downto 0); -- SVGA signals signal vid_hsync : std_ulogic; signal vid_vsync : std_ulogic; signal vid_r : std_logic_vector(3 downto 0); signal vid_g : std_logic_vector(3 downto 0); signal vid_b : std_logic_vector(3 downto 0); -- Select signal for SPI flash signal spi_sel_n : std_logic; signal spi_clk : std_logic; signal spi_mosi : std_logic; -- Output signals for LEDs signal led : std_logic_vector(15 downto 0); signal brdyn : std_ulogic; signal sw : std_logic_vector(15 downto 0):= (others =>'0'); signal btn : std_logic_vector(4 downto 0):= (others =>'0'); begin -- clock and reset clk <= not clk after ct * 1 ns; rst <= '1', '0' after 100 ns; rstn <= not rst; dsubre <= '0'; urxd <= 'H'; spi_sel_n <= 'H'; spi_clk <= 'L'; d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow) port map ( clk => clk, btnCpuResetn => rstn, -- PROM address => address(22 downto 0), data => data(31 downto 16), RamOE => oen, RamWE => writen, RamCE => RamCE, -- AHB Uart RsRx => dsurx, RsTx => dsutx, -- PHY PhyCrs => erx_crs, PhyRxd => etxdt, PhyRxEr => erx_er, -- Output signals for LEDs led => led, sw => sw, btn => btn ); sram0 : sram generic map (index => 4, abits => 24, fname => sdramfile) port map (address(23 downto 0), data(31 downto 24), RamCE, writen, oen); sram1 : sram generic map (index => 5, abits => 24, fname => sdramfile) port map (address(23 downto 0), data(23 downto 16), RamCE, writen, oen); -- Ethernet model diasbled erx_crs <= '0'; etxdt<= (others =>'0'); erx_er<= '0'; spimem0: if CFG_SPIMCTRL = 1 generate s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile, readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE, dualoutput => 0) port map (spi_clk, spi_mosi, data(24), spi_sel_n); end generate spimem0; led(3) <= 'L'; -- ERROR pull-down error <= not led(3); iuerr : process begin wait for 5 us; assert (to_X01(error) = '1') report "*** IU in error mode, simulation halted ***" severity failure; end process; data <= buskeep(data) after 5 ns; dsucom : process procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is variable w32 : std_logic_vector(31 downto 0); variable c8 : std_logic_vector(7 downto 0); constant txp : time := 160 * 1 ns; begin dsutx <= '1'; wait; wait for 5000 ns; txc(dsutx, 16#55#, txp); -- sync uart txc(dsutx, 16#a0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp); -- -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp); -- -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp); -- -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp); -- -- txc(dsutx, 16#80#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); -- rxi(dsurx, w32, txp, lresp); end; begin dsucfg(dsutx, dsurx); wait; end process; end;

gpl-2.0

8a1b2dc321ebc770d047236f229be4b9

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/grlfpwx.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: grlfpwx -- File: grlfpwx.vhd -- Author: Edvin Catovic - Gaisler Research -- Description: GRFPU LITE / GRFPC wrapper and FP register file ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; library grlib; use grlib.stdlib.all; library gaisler; use gaisler.leon3.all; use gaisler.libleon3.all; use gaisler.libfpu.all; library techmap; use techmap.gencomp.all; use techmap.netcomp.all; entity grlfpwx is generic ( tech : integer := 0; pclow : integer range 0 to 2 := 2; dsu : integer range 0 to 1 := 0; disas : integer range 0 to 2 := 0; pipe : integer := 0; netlist : integer := 0; index : integer := 0); port ( rst : in std_ulogic; -- Reset clk : in std_ulogic; holdn : in std_ulogic; -- pipeline hold cpi : in fpc_in_type; cpo : out fpc_out_type ); end; architecture rtl of grlfpwx is signal rfi1, rfi2 : fp_rf_in_type; signal rfo1, rfo2 : fp_rf_out_type; begin x1 : if true generate grlfpw0 : grlfpw_net generic map (tech, pclow, dsu, disas, pipe) port map ( rst , clk , holdn , cpi.flush , cpi.exack , cpi.a_rs1 , cpi.d.pc , cpi.d.inst , cpi.d.cnt , cpi.d.trap , cpi.d.annul , cpi.d.pv , cpi.a.pc , cpi.a.inst , cpi.a.cnt , cpi.a.trap , cpi.a.annul , cpi.a.pv , cpi.e.pc , cpi.e.inst , cpi.e.cnt , cpi.e.trap , cpi.e.annul , cpi.e.pv , cpi.m.pc , cpi.m.inst , cpi.m.cnt , cpi.m.trap , cpi.m.annul , cpi.m.pv , cpi.x.pc , cpi.x.inst , cpi.x.cnt , cpi.x.trap , cpi.x.annul , cpi.x.pv , cpi.lddata , cpi.dbg.enable , cpi.dbg.write , cpi.dbg.fsr , cpi.dbg.addr , cpi.dbg.data , cpo.data , cpo.exc , cpo.cc , cpo.ccv , cpo.ldlock , cpo.holdn , cpo.dbg.data , rfi1.rd1addr , rfi1.rd2addr , rfi1.wraddr , rfi1.wrdata , rfi1.ren1 , rfi1.ren2 , rfi1.wren , rfi2.rd1addr , rfi2.rd2addr , rfi2.wraddr , rfi2.wrdata , rfi2.ren1 , rfi2.ren2 , rfi2.wren , rfo1.data1 , rfo1.data2 , rfo2.data1 , rfo2.data2 ); end generate; rf1 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16 ) port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2 ); rf2 : regfile_3p_l3 generic map (tech, 4, 32, 1, 16 ) port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2 ); end;

gpl-2.0

bdb58391cd7b5b7495b0033ee9a49068

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-avnet-eval-xc4vlx25/leon3mp.vhd

------------------------------------------------------------------------------ -- LEON3 Demonstration design -- Copyright (C) 2006 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library techmap; use techmap.gencomp.all; use techmap.allclkgen.all; library gaisler; use gaisler.memctrl.all; use gaisler.ddrpkg.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.net.all; use gaisler.jtag.all; library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; ddrfreq : integer := 100000 -- frequency of ddr clock in kHz ); port ( resetn : in std_ulogic; resoutn : out std_logic; clk_100mhz : in std_ulogic; errorn : out std_ulogic; -- prom interface address : out std_logic_vector(21 downto 0); data : inout std_logic_vector(15 downto 0); romsn : out std_ulogic; oen : out std_ulogic; writen : out std_ulogic; romrstn : out std_ulogic; -- pragma translate_off iosn : out std_ulogic; testdata : inout std_logic_vector(15 downto 0); -- pragma translate_on -- ddr memory ddr_clk0 : out std_logic; ddr_clk0b : out std_logic; ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke0 : out std_logic; ddr_cs0b : out std_logic; ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (12 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data -- debug support unit dsuen : in std_ulogic; dsubre : in std_ulogic; dsuact : out std_ulogic; -- UART for serial DCL/console I/O serrx : in std_ulogic; sertx : out std_ulogic; rtsn : out std_ulogic; ctsn : in std_ulogic; led_rx : out std_ulogic; led_tx : out std_ulogic; -- ethernet signals emdio : inout std_logic; -- ethernet PHY interface etx_clk : in std_ulogic; erx_clk : in std_ulogic; erxd : in std_logic_vector(3 downto 0); erx_dv : in std_ulogic; erx_er : in std_ulogic; erx_col : in std_ulogic; erx_crs : in std_ulogic; etxd : out std_logic_vector(3 downto 0); etx_en : out std_ulogic; etx_er : out std_ulogic; emdc : out std_ulogic; erstn : out std_ulogic; -- OLED display signals disp_dcn : out std_ulogic; disp_csn : out std_ulogic; disp_rdn : out std_ulogic; disp_wrn : out std_ulogic; disp_d : inout std_logic_vector(7 downto 0) ); end; architecture rtl of leon3mp is constant blength : integer := 12; constant fifodepth : integer := 8; signal vcc, gnd : std_logic_vector(4 downto 0); signal memi : memory_in_type; signal memo : memory_out_type; signal wpo : wprot_out_type; signal sdi : sdctrl_in_type; signal sdo : sdctrl_out_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal lclk : std_ulogic; signal ddrclk, ddrrst, ddrclkfb : std_ulogic; signal clkm, rstn, clkml, clk2x : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal u1i, dui : uart_in_type; signal u1o, duo : uart_out_type; signal irqi : irq_in_vector(0 to CFG_NCPU-1); signal irqo : irq_out_vector(0 to CFG_NCPU-1); signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal ethi, ethi1, ethi2 : eth_in_type; signal etho, etho1, etho2 : eth_out_type; signal gpti : gptimer_in_type; signal tck, tms, tdi, tdo : std_ulogic; -- signal dsubre : std_logic; signal duart, ldsuen : std_logic; signal rsertx, rserrx, rdsuen : std_logic; signal rstraw : std_logic; signal rstneg : std_logic; signal rxd1 : std_logic; signal txd1 : std_logic; signal lock : std_logic; signal ddr_clk : std_logic_vector(2 downto 0); signal ddr_clkb : std_logic_vector(2 downto 0); signal ddr_cke : std_logic_vector(1 downto 0); signal ddr_csb : std_logic_vector(1 downto 0); signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address attribute keep : boolean; attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute syn_keep of lock : signal is true; attribute syn_keep of clkml : signal is true; attribute syn_preserve of clkml : signal is true; attribute keep of lock : signal is true; attribute keep of clkml : signal is true; attribute keep of clkm : signal is true; constant BOARD_FREQ : integer := 100000; -- input frequency in KHz constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz begin romrstn <= rstn; ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; rstneg <= not resetn; rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw); clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk); clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0) port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1, nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- leon3gen : if CFG_LEON3 = 1 generate cpu : for i in 0 to CFG_NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error); dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); dsui.enable <= '1'; dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); end generate; end generate; nodsu : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0 : ahbuart -- Debug UART generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU)); end generate; nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 ) port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open); end generate; memi.brdyn <= '1'; memi.bexcn <= '1'; memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01"; mg0 : if (CFG_MCTRL_LEON2 = 0) generate apbo(0) <= apb_none; ahbso(0) <= ahbs_none; roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0)); end generate; mgpads : if (CFG_MCTRL_LEON2 /= 0) generate addr_pad : outpadv generic map (width => 22, tech => padtech) port map (address, memo.address(22 downto 1)); roms_pad : outpad generic map (tech => padtech) port map (romsn, memo.romsn(0)); oen_pad : outpad generic map (tech => padtech) port map (oen, memo.oen); wri_pad : outpad generic map (tech => padtech) port map (writen, memo.writen); -- pragma translate_off iosn_pad : outpad generic map (tech => padtech) port map (iosn, memo.iosn); tbdr : for i in 0 to 1 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8), memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8)); end generate; -- pragma translate_on bdr : for i in 0 to 1 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); end generate; end generate; ---------------------------------------------------------------------- --- DDR memory controller ------------------------------------------- ---------------------------------------------------------------------- ddrsp0 : if (CFG_DDRSP /= 0) generate ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech, hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1, pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => -95 -- pragma translate_off * 0 -- disable clock skew during simulation -- pragma translate_on , clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16) port map ( rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4), ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq); ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0); ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0); ddr_ad <= ddr_adl(12 downto 0); end generate; noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit grgpio0: grgpio generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12 --CFG_GRGPIO_WIDTH ) port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); disp_csn_pad : outpad generic map (tech => padtech) port map (disp_csn, gpioo.dout(8)); disp_dcn_pad : outpad generic map (tech => padtech) port map (disp_dcn, gpioo.dout(9)); disp_rdn_pad : outpad generic map (tech => padtech) port map (disp_rdn, gpioo.dout(10)); disp_wrn_pad : outpad generic map (tech => padtech) port map (disp_wrn, gpioo.dout(11)); disp_d_pads : for i in 0 to 7 generate pio_pad : iopad generic map (tech => padtech) port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); end generate; end generate; ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, pindex => 15, paddr => 15, pirq => 12, memtech => memtech, mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO, nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, phyrstadr => 3, giga => CFG_GRETH1G) port map( rst => rstn, clk => clkm, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho); emdio_pad : iopad generic map (tech => padtech) port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i); etxc_pad : inpad generic map (tech => padtech) port map (etx_clk, ethi.tx_clk); erxc_pad : inpad generic map (tech => padtech) port map (erx_clk, ethi.rx_clk); erxd_pad : inpadv generic map (tech => padtech, width => 4) port map (erxd, ethi.rxd(3 downto 0)); erxdv_pad : inpad generic map (tech => padtech) port map (erx_dv, ethi.rx_dv); erxer_pad : inpad generic map (tech => padtech) port map (erx_er, ethi.rx_er); erxco_pad : inpad generic map (tech => padtech) port map (erx_col, ethi.rx_col); erxcr_pad : inpad generic map (tech => padtech) port map (erx_crs, ethi.rx_crs); etxd_pad : outpadv generic map (tech => padtech, width => 4) port map (etxd, etho.txd(3 downto 0)); etxen_pad : outpad generic map (tech => padtech) port map (etx_en, etho.tx_en); etxer_pad : outpad generic map (tech => padtech) port map (etx_er, etho.tx_er); emdc_pad : outpad generic map (tech => padtech) port map (emdc, etho.mdc); erstn_pad : outpad generic map (tech => padtech) port map (erstn, rstn); end generate; ----------------------------------------------------------------------- --- AHB DMA ---------------------------------------------------------- ----------------------------------------------------------------------- -- dma0 : ahbdma -- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH, -- pindex => 12, paddr => 12, dbuf => 32) -- port map (rstn, clkm, apbi, apbo(12), ahbmi, -- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH)); -- -- at0 : ahbtrace -- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#, -- tech => memtech, irq => 0, kbytes => 8) -- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7)); ----------------------------------------------------------------------- --- AHB ROM ---------------------------------------------------------- ----------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(6)); end generate; nobpromgen : if CFG_AHBROMEN = 0 generate ahbso(6) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ahbramgen : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) port map (rstn, clkm, ahbsi, ahbso(3)); end generate; nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate ahbmo(i) <= ahbm_none; end generate; -- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate; -- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate; resoutn <= rstn; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on -- use switch 1 to multiplex DSU UART and UART1 dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen); duart <= rdsuen when CFG_AHB_UART /= 0 else '0'; rxd1 <= txd1 when duart = '1' else rserrx; rsertx <= duo.txd when duart = '1' else txd1; dui.rxd <= rserrx when duart = '1' else '1'; led_rx <= not rserrx; p1 : process(clkm) begin if rising_edge(clkm) then sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen; rtsn <= '0'; led_tx <= not rsertx; end if; end process; end rtl;

gpl-2.0

dee617929cc408f16a1ea9875e649fe2

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/techmap/maps/inpad.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: inpad -- File: inpad.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: input pad with technology wrapper ------------------------------------------------------------------------------ library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; use techmap.allpads.all; entity inpad is generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v; filter : integer := 0; strength : integer := 0); port (pad : in std_ulogic; o : out std_ulogic); end; architecture rtl of inpad is begin gen0 : if has_pads(tech) = 0 generate o <= transport to_X01(pad) -- pragma translate_off after 1 ns -- pragma translate_on ; end generate; xcv : if (is_unisim(tech) = 1) generate x0 : unisim_inpad generic map (level, voltage) port map (pad, o); end generate; axc : if (tech = axcel) or (tech = axdsp) generate x0 : axcel_inpad generic map (level, voltage) port map (pad, o); end generate; pa3 : if (tech = proasic) or (tech = apa3) generate x0 : apa3_inpad generic map (level, voltage, filter) port map (pad, o); end generate; pa3e : if (tech = apa3e) generate x0 : apa3e_inpad generic map (level, voltage, filter) port map (pad, o); end generate; pa3l : if (tech = apa3l) generate x0 : apa3l_inpad generic map (level, voltage, filter) port map (pad, o); end generate; fus : if (tech = actfus) generate x0 : fusion_inpad generic map (level, voltage, filter) port map (pad, o); end generate; atc : if (tech = atc18s) generate x0 : atc18_inpad generic map (level, voltage) port map (pad, o); end generate; atcrh : if (tech = atc18rha) generate x0 : atc18rha_inpad generic map (level, voltage) port map (pad, o); end generate; um : if (tech = umc) generate x0 : umc_inpad generic map (level, voltage, filter) port map (pad, o); end generate; rhu : if (tech = rhumc) generate x0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o); end generate; saed : if (tech = saed32) generate x0 : saed32_inpad generic map (level, voltage, filter) port map (pad, o); end generate; dar : if (tech = dare) generate x0 : dare_inpad generic map (level, voltage, filter) port map (pad, o); end generate; ihp : if (tech = ihp25) generate x0 : ihp25_inpad generic map(level, voltage) port map(pad, o); end generate; ihprh : if (tech = ihp25rh) generate x0 : ihp25rh_inpad generic map(level, voltage) port map(pad, o); end generate; rh18t : if (tech = rhlib18t) generate x0 : rh_lib18t_inpad generic map (voltage, filter) port map(pad, o); end generate; ut025 : if (tech = ut25) generate x0 : ut025crh_inpad generic map (level, voltage, filter) port map(pad, o); end generate; ut13 : if (tech = ut130) generate x0 : ut130hbd_inpad generic map (level, voltage, filter) port map(pad, o); end generate; pereg : if (tech = peregrine) generate x0 : peregrine_inpad generic map (level, voltage, filter, strength) port map(pad, o); end generate; eas : if (tech = easic90) generate x0 : nextreme_inpad generic map (level, voltage) port map (pad, o); end generate; n2x : if (tech = easic45) generate x0 : n2x_inpad generic map (level, voltage) port map (pad, o); end generate; ut90nhbd : if (tech = ut90) generate x0 : ut90nhbd_inpad generic map (level, voltage, filter) port map(pad, o); end generate; end; library techmap; library ieee; use ieee.std_logic_1164.all; use techmap.gencomp.all; entity inpadv is generic (tech : integer := 0; level : integer := 0; voltage : integer := 0; width : integer := 1; filter : integer := 0; strength : integer := 0); port ( pad : in std_logic_vector(width-1 downto 0); o : out std_logic_vector(width-1 downto 0)); end; architecture rtl of inpadv is begin v : for i in width-1 downto 0 generate x0 : inpad generic map (tech, level, voltage, filter, strength) port map (pad(i), o(i)); end generate; end;

gpl-2.0

aee37051f4b553a88e8350838efdabfc

cesar-avalos3/C8VHDL

sources/vhdl/vga_controller.vhd

-- Adapted from Albert Fazakas who adapted from Alec Wyen and Mihaita Nagy -- VGA controller sample demo -- Copyright 2014 Digilent, Inc. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vga_controller is Port ( memRead : in STD_LOGIC_VECTOR (7 downto 0); memWrite : out STD_LOGIC_VECTOR (7 downto 0); memAddress : out STD_LOGIC_VECTOR (11 downto 0); mem_valid : out STD_LOGIC; mem_write : out STD_LOGIC; mem_hold : out STD_LOGIC; mem_done : in STD_LOGIC; active : out STD_LOGIC; clk : in STD_LOGIC; sys_clk : in STD_LOGIC; reset : in STD_LOGIC; sys_reset : in STD_LOGIC; VGA_HS_O : out STD_LOGIC; VGA_VS_O : out STD_LOGIC; VGA_RED_O : out STD_LOGIC_VECTOR (3 downto 0); VGA_GREEN_O : out STD_LOGIC_VECTOR (3 downto 0); VGA_BLUE_O : out STD_LOGIC_VECTOR (3 downto 0) ); end vga_controller; architecture Behavioral of vga_controller is signal requestLine : STD_LOGIC_VECTOR (7 downto 0); signal previousRequestBuffer : STD_LOGIC_VECTOR( 0 downto 0 ); signal requestBuffer : STD_LOGIC_VECTOR( 0 downto 0 ) := "0"; type VBUFF is array( 1 downto 0 ) of STD_LOGIC_VECTOR (63 downto 0); signal vga_VBUFF : VBUFF :=("0000000000000000000000000000000000000000000000000000000000000000", "0000000000000000000000000000000000000000000000000000000000000000"); ------------------------------------------------------------- -- Constants for various VGA Resolutions ------------------------------------------------------------- --***640x480@60Hz***-- constant FRAME_WIDTH : natural := 640; constant FRAME_HEIGHT : natural := 480; constant H_FP : natural := 16; --H front porch width (pixels) constant H_PW : natural := 96; --H sync pulse width (pixels) constant H_MAX : natural := 800; --H total period (pixels) -- constant V_FP : natural := 10; --V front porch width (lines) constant V_PW : natural := 2; --V sync pulse width (lines) constant V_MAX : natural := 525; --V total period (lines) constant H_POL : std_logic := '0'; constant V_POL : std_logic := '0'; ------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------- ------------------------------------------------------------------------- -- VGA Controller specific signals: Counters, Sync, R, G, B ------------------------------------------------------------------------- -- Pixel clock, in this case 25 MHz signal pxl_clk : std_logic := '0'; -- Horizontal and Vertical counters signal h_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0'); signal v_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0'); -- Pipe Horizontal and Vertical Counters signal h_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0'); signal v_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0'); -- Horizontal and Vertical Sync signal h_sync_reg : std_logic := not(H_POL); signal v_sync_reg : std_logic := not(V_POL); -- Pipe Horizontal and Vertical Sync signal h_sync_reg_dly : std_logic := not(H_POL); signal v_sync_reg_dly : std_logic := not(V_POL); -- VGA R, G and B signals coming from the main multiplexers signal vga_red_cmb : std_logic_vector(3 downto 0); signal vga_green_cmb : std_logic_vector(3 downto 0); signal vga_blue_cmb : std_logic_vector(3 downto 0); --The main VGA R, G and B signals, validated by active signal vga_red : std_logic_vector(3 downto 0); signal vga_green : std_logic_vector(3 downto 0); signal vga_blue : std_logic_vector(3 downto 0); signal vga_red_reg : std_logic_vector(3 downto 0); signal vga_green_reg : std_logic_vector(3 downto 0); signal vga_blue_reg : std_logic_vector(3 downto 0); signal tmp_mem_write : std_logic; signal mem_ret_data : std_logic_vector(7 downto 0); signal mhz50 : std_logic := '0'; type state is ( waiting, get0, get1, get2, get3, get4, get5, get6, get7, memA, memB ); signal mem_ret_state, current_state : state; begin mem_write <= tmp_mem_write; process( sys_clk, sys_reset ) begin if( sys_reset = '1' ) then active <= '0'; memWrite <= ( others => '0' ); memAddress <= ( others => '0' ); mem_valid <= '0'; tmp_mem_write <= '0'; mem_hold <= '0'; current_state <= waiting; mem_ret_state <= waiting; elsif ( rising_edge( sys_clk ) ) then current_state <= current_state; case current_state is when waiting => if( previousRequestBuffer /= requestBuffer ) then previousRequestBuffer <= requestBuffer; memAddress <= x"F" & requestLine( 4 downto 0 ) & "000"; tmp_mem_write <= '0'; mem_hold <= '1'; mem_ret_state <= get0; current_state <= memA; end if; when get0 => vga_VBUFF(to_integer( unsigned ( requestBuffer ) ))( 7 downto 0 ) <= mem_ret_data; memAddress <= x"F" & requestLine( 4 downto 0 ) & "001"; mem_ret_state <= get1; current_state <= memA; when get1 => vga_VBUFF(to_integer( unsigned ( requestBuffer ) ))( 15 downto 8 ) <= mem_ret_data; memAddress <= x"F" & requestLine( 4 downto 0 ) & "010"; mem_ret_state <= get2; current_state <= memA; when get2 => vga_VBUFF(to_integer( unsigned ( requestBuffer ) ))( 23 downto 16 ) <= mem_ret_data; memAddress <= x"F" & requestLine( 4 downto 0 ) & "011"; mem_ret_state <= get3; current_state <= memA; when get3 => vga_VBUFF(to_integer( unsigned ( requestBuffer ) ))( 31 downto 24 ) <= mem_ret_data; memAddress <= x"F" & requestLine( 4 downto 0 ) & "100"; mem_ret_state <= get4; current_state <= memA; when get4 => vga_VBUFF(to_integer( unsigned ( requestBuffer ) ))( 39 downto 32 ) <= mem_ret_data; memAddress <= x"F" & requestLine( 4 downto 0 ) & "101"; mem_ret_state <= get5; current_state <= memA; when get5 => vga_VBUFF(to_integer( unsigned ( requestBuffer ) ))( 47 downto 40 ) <= mem_ret_data; memAddress <= x"F" & requestLine( 4 downto 0 ) & "110"; mem_ret_state <= get6; current_state <= memA; when get6 => vga_VBUFF(to_integer( unsigned ( requestBuffer ) ))( 55 downto 48 ) <= mem_ret_data; memAddress <= x"F" & requestLine( 4 downto 0 ) & "111"; mem_ret_state <= get7; current_state <= memA; when get7 => vga_VBUFF(to_integer( unsigned ( requestBuffer ) ))( 63 downto 56 ) <= mem_ret_data; mem_hold <= '0'; current_state <= waiting; when memA => if ( mem_done = '0' ) then mem_valid <= '1'; current_state <= memB; end if; when memB => if( mem_done = '1' ) then if ( tmp_mem_write = '0' ) then mem_ret_data <= memRead; end if; mem_valid <= '0'; current_state <= mem_ret_state; end if; end case; end if; end process; process( clk ) begin if( rising_edge( clk )) then mhz50 <= not mhz50; end if; end process; process( mhz50 ) begin if( rising_edge( mhz50 )) then pxl_clk <= not pxl_clk; end if; end process; --------------------------------------------------------------- -- Generate Horizontal, Vertical counters and the Sync signals --------------------------------------------------------------- -- Horizontal counter process (pxl_clk) begin if (rising_edge(pxl_clk)) then if (h_cntr_reg = (H_MAX - 1)) then h_cntr_reg <= (others =>'0'); else h_cntr_reg <= h_cntr_reg + 1; end if; end if; end process; -- Vertical counter process (pxl_clk) begin if (rising_edge(pxl_clk)) then if ((h_cntr_reg = (H_MAX - 1)) and (v_cntr_reg = (V_MAX - 1))) then v_cntr_reg <= (others =>'0'); elsif (h_cntr_reg = (H_MAX - 1)) then v_cntr_reg <= v_cntr_reg + 1; end if; end if; end process; -- Horizontal sync process (pxl_clk) begin if (rising_edge(pxl_clk)) then if (h_cntr_reg >= (H_FP + FRAME_WIDTH - 1)) and (h_cntr_reg < (H_FP + FRAME_WIDTH + H_PW - 1)) then h_sync_reg <= H_POL; else h_sync_reg <= not(H_POL); end if; end if; end process; -- Vertical sync process (pxl_clk) begin if (rising_edge(pxl_clk)) then if (v_cntr_reg >= (V_FP + FRAME_HEIGHT - 1)) and (v_cntr_reg < (V_FP + FRAME_HEIGHT + V_PW - 1)) then v_sync_reg <= V_POL; else v_sync_reg <= not(V_POL); end if; end if; end process; process( pxl_clk ) variable xspot : std_logic_vector(11 downto 0); variable yspot : std_logic_vector(11 downto 0); variable which_buf : std_logic_vector( 0 downto 0 ); begin which_buf := not requestBuffer; vga_red <= "0000"; vga_blue <= "0000"; vga_green <= "0000"; if( rising_edge(pxl_clk) ) then if ( h_cntr_reg >= (H_FP + 64)) and (h_cntr_reg < (H_FP + FRAME_WIDTH - 64) ) then if( v_cntr_reg >= (V_FP + 112)) and (v_cntr_reg < (V_FP + FRAME_HEIGHT - 112)) then xspot := h_cntr_reg - ( H_FP + 64 ); yspot := v_cntr_reg - ( V_FP + 112 ); if( ( xspot = x"000" ) and ( yspot( 2 downto 0 ) = "000") ) then requestBuffer <= which_buf; which_buf := not which_buf; yspot := "0000000" & yspot( 7 downto 3 ); yspot := yspot + 1; requestLine <= "000" & yspot( 4 downto 0 ); end if; if( vga_VBUFF( to_integer( unsigned ( which_buf ) ))( to_integer( unsigned ( xspot( 11 downto 3 ) ) )) = '1' ) then vga_green <= "1111"; end if; end if; end if; end if; end process; vga_red_cmb <= vga_red; vga_green_cmb <= vga_green; vga_blue_cmb <= vga_blue; -- Register Outputs process (pxl_clk) begin if (rising_edge(pxl_clk)) then v_sync_reg_dly <= v_sync_reg; h_sync_reg_dly <= h_sync_reg; vga_red_reg <= vga_red_cmb; vga_green_reg <= vga_green_cmb; vga_blue_reg <= vga_blue_cmb; end if; end process; -- Assign outputs VGA_HS_O <= h_sync_reg_dly; VGA_VS_O <= v_sync_reg_dly; VGA_RED_O <= vga_red_reg; VGA_GREEN_O <= vga_green_reg; VGA_BLUE_O <= vga_blue_reg; end Behavioral;

mit

4f970cae0a5e9418eeb0603bc5cda607

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/regfile_3p_l3.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: regfile_3p_l3 -- File: regfile_3p_l3.vhd -- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research -- Description: 3-port regfile implemented with two 2-port rams ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; library techmap; use techmap.gencomp.all; use grlib.stdlib.all; entity regfile_3p_l3 is generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; wrfst : integer := 0; numregs : integer := 64; testen : integer := 0); port ( wclk : in std_ulogic; waddr : in std_logic_vector((abits -1) downto 0); wdata : in std_logic_vector((dbits -1) downto 0); we : in std_ulogic; rclk : in std_ulogic; raddr1 : in std_logic_vector((abits -1) downto 0); re1 : in std_ulogic; rdata1 : out std_logic_vector((dbits -1) downto 0); raddr2 : in std_logic_vector((abits -1) downto 0); re2 : in std_ulogic; rdata2 : out std_logic_vector((dbits -1) downto 0); testin : in std_logic_vector(3 downto 0) := "0000"); end; architecture rtl of regfile_3p_l3 is constant rfinfer : boolean := (regfile_3p_infer(tech) = 1); signal wd1, wd2 : std_logic_vector((dbits -1 + 8) downto 0); signal e1, e2 : std_logic_vector((dbits-1) downto 0); signal we1, we2 : std_ulogic; signal vcc, gnd : std_ulogic; signal vgnd : std_logic_vector(dbits-1 downto 0); signal write2, renable2 : std_ulogic; begin vcc <= '1'; gnd <= '0'; vgnd <= (others => '0'); we1 <= we ; we2 <= we ; s0 : if rfinfer generate inf : regfile_3p generic map (0, abits, dbits, wrfst, numregs) port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2); end generate; s1 : if not rfinfer generate rhu : regfile_3p generic map (tech, abits, dbits, wrfst, numregs, testen) port map ( wclk, waddr, wdata, we, rclk, raddr1, re1, rdata1, raddr2, re2, rdata2); end generate; end;

gpl-2.0

e5fe8ba578a1f02783983fb7eb3fcea1

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-jopdesign-ep1c12/testbench.vhd

------------------------------------------------------------------------------ -- LEON3 Demonstration design test bench -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; library micron; use micron.components.all; use work.debug.all; use work.config.all; -- configuration entity testbench is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; ncpu : integer := CFG_NCPU; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; clkperiod : integer := 20; -- system clock period romwidth : integer := 32; -- rom data width (8/32) romdepth : integer := 16; -- rom address depth sramwidth : integer := 32; -- ram data width (8/16/32) sramdepth : integer := 18; -- ram address depth srambanks : integer := 2 -- number of ram banks ); port ( pci_rst : inout std_logic; -- PCI bus pci_clk : in std_logic; pci_gnt : in std_logic; pci_idsel : in std_logic; pci_lock : inout std_logic; pci_ad : inout std_logic_vector(31 downto 0); pci_cbe : inout std_logic_vector(3 downto 0); pci_frame : inout std_logic; pci_irdy : inout std_logic; pci_trdy : inout std_logic; pci_devsel : inout std_logic; pci_stop : inout std_logic; pci_perr : inout std_logic; pci_par : inout std_logic; pci_req : inout std_logic; pci_serr : inout std_logic; pci_host : in std_logic; pci_66 : in std_logic ); end; architecture behav of testbench is constant promfile : string := "prom.srec"; -- rom contents constant sramfile : string := "ram.srec"; -- ram contents constant sdramfile : string := "ram.srec"; -- sdram contents component leon3mp generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW ); port ( resetn : in std_logic; clk : in std_logic; pllref : in std_logic; errorn : out std_logic; address : out std_logic_vector(27 downto 0); data : inout std_logic_vector(31 downto 0); sa : out std_logic_vector(14 downto 0); sd : inout std_logic_vector(63 downto 0); sdclk : out std_logic; sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select sdwen : out std_logic; -- sdram write enable sdrasn : out std_logic; -- sdram ras sdcasn : out std_logic; -- sdram cas sddqm : out std_logic_vector (7 downto 0); -- sdram dqm dsutx : out std_logic; -- DSU tx data dsurx : in std_logic; -- DSU rx data dsuen : in std_logic; dsubre : in std_logic; dsuact : out std_logic; txd1 : out std_logic; -- UART1 tx data rxd1 : in std_logic; -- UART1 rx data txd2 : out std_logic; -- UART1 tx data rxd2 : in std_logic; -- UART1 rx data ramsn : out std_logic_vector (4 downto 0); ramoen : out std_logic_vector (4 downto 0); rwen : out std_logic_vector (3 downto 0); oen : out std_logic; writen : out std_logic; read : out std_logic; iosn : out std_logic; romsn : out std_logic_vector (1 downto 0); gpio : inout std_logic_vector(7 downto 0); -- I/O port emdio : inout std_logic; -- ethernet PHY interface etx_clk : in std_logic; erx_clk : in std_logic; erxd : in std_logic_vector(3 downto 0); erx_dv : in std_logic; erx_er : in std_logic; erx_col : in std_logic; erx_crs : in std_logic; etxd : out std_logic_vector(3 downto 0); etx_en : out std_logic; etx_er : out std_logic; emdc : out std_logic; emddis : out std_logic; epwrdwn : out std_logic; ereset : out std_logic; esleep : out std_logic; epause : out std_logic; pci_rst : inout std_logic; -- PCI bus pci_clk : in std_logic; pci_gnt : in std_logic; pci_idsel : in std_logic; pci_lock : inout std_logic; pci_ad : inout std_logic_vector(31 downto 0); pci_cbe : inout std_logic_vector(3 downto 0); pci_frame : inout std_logic; pci_irdy : inout std_logic; pci_trdy : inout std_logic; pci_devsel : inout std_logic; pci_stop : inout std_logic; pci_perr : inout std_logic; pci_par : inout std_logic; pci_req : inout std_logic; pci_serr : inout std_logic; pci_host : in std_logic; pci_66 : in std_logic; pci_arb_req : in std_logic_vector(0 to 3); pci_arb_gnt : out std_logic_vector(0 to 3); can_txd : out std_logic; can_rxd : in std_logic; can_stb : out std_logic; spw_clk : in std_logic; spw_rxd : in std_logic_vector(0 to 2); spw_rxdn : in std_logic_vector(0 to 2); spw_rxs : in std_logic_vector(0 to 2); spw_rxsn : in std_logic_vector(0 to 2); spw_txd : out std_logic_vector(0 to 2); spw_txdn : out std_logic_vector(0 to 2); spw_txs : out std_logic_vector(0 to 2); spw_txsn : out std_logic_vector(0 to 2) ); end component; signal clk : std_logic := '0'; signal Rst : std_logic := '0'; -- Reset constant ct : integer := clkperiod/2; signal address : std_logic_vector(27 downto 0); signal data : std_logic_vector(31 downto 0); signal ramsn : std_logic_vector(4 downto 0); signal ramoen : std_logic_vector(4 downto 0); signal rwen : std_logic_vector(3 downto 0); signal rwenx : std_logic_vector(3 downto 0); signal romsn : std_logic_vector(1 downto 0); signal iosn : std_logic; signal oen : std_logic; signal read : std_logic; signal writen : std_logic; signal brdyn : std_logic; signal bexcn : std_logic; signal wdog : std_logic; signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic; signal dsurst : std_logic; signal test : std_logic; signal error : std_logic; signal gpio : std_logic_vector(7 downto 0); signal GND : std_logic := '0'; signal VCC : std_logic := '1'; signal NC : std_logic := 'Z'; signal clk2 : std_logic := '1'; signal sdcke : std_logic_vector ( 1 downto 0); -- clk en signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel signal sdwen : std_logic; -- write en signal sdrasn : std_logic; -- row addr stb signal sdcasn : std_logic; -- col addr stb signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask signal sdclk : std_logic; signal plllock : std_logic; signal txd1, rxd1 : std_logic; signal txd2, rxd2 : std_logic; signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0'; signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0'); signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0'); signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used signal gtx_clk : std_logic; signal emddis : std_logic; signal epwrdwn : std_logic; signal ereset : std_logic; signal esleep : std_logic; signal epause : std_logic; constant lresp : boolean := false; signal sa : std_logic_vector(14 downto 0); signal sd : std_logic_vector(63 downto 0); signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3); signal can_txd : std_logic; signal can_rxd : std_logic; signal can_stb : std_logic; signal spw_clk : std_logic := '0'; signal spw_rxd : std_logic_vector(0 to 2) := "000"; signal spw_rxdn : std_logic_vector(0 to 2) := "000"; signal spw_rxs : std_logic_vector(0 to 2) := "000"; signal spw_rxsn : std_logic_vector(0 to 2) := "000"; signal spw_txd : std_logic_vector(0 to 2); signal spw_txdn : std_logic_vector(0 to 2); signal spw_txs : std_logic_vector(0 to 2); signal spw_txsn : std_logic_vector(0 to 2); constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ; constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64; begin -- clock and reset spw_clk <= not spw_clk after 20 ns; spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0); spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0); spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1); spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1); spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2); spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2); clk <= not clk after ct * 1 ns; rst <= dsurst; dsuen <= '1'; dsubre <= '0'; rxd1 <= '1'; can_rxd <= '1'; d3 : leon3mp generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow ) port map (rst, clk, sdclk, error, address(27 downto 0), data, sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2, ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio, emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause, pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par, pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt, can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs, spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn); -- optional sdram sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile) PORT MAP( Dq => data(31 downto 16), Addr => address(14 downto 2), Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(3 downto 2)); u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile) PORT MAP( Dq => data(15 downto 0), Addr => address(14 downto 2), Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(1 downto 0)); u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile) PORT MAP( Dq => data(31 downto 16), Addr => address(14 downto 2), Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(3 downto 2)); u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile) PORT MAP( Dq => data(15 downto 0), Addr => address(14 downto 2), Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(1 downto 0)); end generate; sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile) PORT MAP( Dq => sd(31 downto 16), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(3 downto 2)); u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile) PORT MAP( Dq => sd(15 downto 0), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(1 downto 0)); u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile) PORT MAP( Dq => sd(31 downto 16), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(3 downto 2)); u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile) PORT MAP( Dq => sd(15 downto 0), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(1 downto 0)); sd64 : if (CFG_SD64 /= 0) generate u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile) PORT MAP( Dq => sd(63 downto 48), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(7 downto 6)); u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile) PORT MAP( Dq => sd(47 downto 32), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(5 downto 4)); u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile) PORT MAP( Dq => sd(63 downto 48), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(7 downto 6)); u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile) PORT MAP( Dq => sd(47 downto 32), Addr => sa(12 downto 0), Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0), Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(5 downto 4)); end generate; end generate; prom0 : for i in 0 to (romwidth/8)-1 generate sr0 : sram generic map (index => i, abits => romdepth, fname => promfile) port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0), rwen(i), oen); end generate; sram0 : for i in 0 to (sramwidth/8)-1 generate sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile) port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0), rwen(0), ramoen(0)); end generate; phy0 : if (CFG_GRETH = 1) generate emdio <= 'H'; erxd <= erxdt(3 downto 0); etxdt <= "0000" & etxd; p0: phy generic map(base1000_t_fd => 0, base1000_t_hd => 0) port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk); end generate; error <= 'H'; -- ERROR pull-up iuerr : process begin wait for 2500 ns; if to_x01(error) = '1' then wait on error; end if; assert (to_x01(error) = '1') report "*** IU in error mode, simulation halted ***" severity failure ; end process; data <= buskeep(data), (others => 'H') after 250 ns; sd <= buskeep(sd), (others => 'H') after 250 ns; test0 : grtestmod port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn); dsucom : process procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is variable w32 : std_logic_vector(31 downto 0); variable c8 : std_logic_vector(7 downto 0); constant txp : time := 160 * 1 ns; begin dsutx <= '1'; dsurst <= '0'; wait for 500 ns; dsurst <= '1'; wait; wait for 5000 ns; txc(dsutx, 16#55#, txp); -- sync uart -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp); txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp); txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp); txc(dsutx, 16#80#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); txc(dsutx, 16#a0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); end; begin dsucfg(dsutx, dsurx); wait; end process; end ;

gpl-2.0

19672996f94e541d8d3b3464d11d1324

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/gaisler/uart/apbuart.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: uart -- File: uart.vhd -- Authors: Jiri Gaisler - Gaisler Research -- Marko Isomaki - Gaisler Research -- Description: Asynchronous UART. Implements 8-bit data frame with one stop-bit. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; --use ieee.numeric_std.all; library grlib; use grlib.config_types.all; use grlib.config.all; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library gaisler; use gaisler.uart.all; --pragma translate_off use std.textio.all; --pragma translate_on entity apbuart is generic ( pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; console : integer := 0; pirq : integer := 0; parity : integer := 1; flow : integer := 1; fifosize : integer range 1 to 32 := 1; abits : integer := 8; sbits : integer range 12 to 32 := 12); port ( rst : in std_ulogic; clk : in std_ulogic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; uarti : in uart_in_type; uarto : out uart_out_type); end; architecture rtl of apbuart is constant REVISION : integer := 1; constant pconfig : apb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq), 1 => apb_iobar(paddr, pmask)); type rxfsmtype is (idle, startbit, data, cparity, stopbit); type txfsmtype is (idle, data, cparity, stopbit); type fifo is array (0 to fifosize - 1) of std_logic_vector(7 downto 0); type uartregs is record rxen : std_ulogic; -- receiver enabled txen : std_ulogic; -- transmitter enabled rirqen : std_ulogic; -- receiver irq enable tirqen : std_ulogic; -- transmitter irq enable parsel : std_ulogic; -- parity select paren : std_ulogic; -- parity select flow : std_ulogic; -- flow control enable loopb : std_ulogic; -- loop back mode enable debug : std_ulogic; -- debug mode enable rsempty : std_ulogic; -- receiver shift register empty (internal) tsempty : std_ulogic; -- transmitter shift register empty tsemptyirqen : std_ulogic; -- generate irq when tx shift register is empty break : std_ulogic; -- break detected breakirqen : std_ulogic; -- generate irq when break has been received ovf : std_ulogic; -- receiver overflow parerr : std_ulogic; -- parity error frame : std_ulogic; -- framing error ctsn : std_logic_vector(1 downto 0); -- clear to send rtsn : std_ulogic; -- request to send extclken : std_ulogic; -- use external baud rate clock extclk : std_ulogic; -- rising edge detect register rhold : fifo; rshift : std_logic_vector(7 downto 0); tshift : std_logic_vector(10 downto 0); thold : fifo; irq : std_ulogic; -- tx/rx interrupt (internal) irqpend : std_ulogic; -- pending irq for delayed rx irq delayirqen : std_ulogic; -- enable delayed rx irq tpar : std_ulogic; -- tx data parity (internal) txstate : txfsmtype; txclk : std_logic_vector(2 downto 0); -- tx clock divider txtick : std_ulogic; -- tx clock (internal) rxstate : rxfsmtype; rxclk : std_logic_vector(2 downto 0); -- rx clock divider rxdb : std_logic_vector(1 downto 0); -- rx delay dpar : std_ulogic; -- rx data parity (internal) rxtick : std_ulogic; -- rx clock (internal) tick : std_ulogic; -- rx clock (internal) scaler : std_logic_vector(sbits-1 downto 0); brate : std_logic_vector(sbits-1 downto 0); rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer txd : std_ulogic; -- transmitter data rfifoirqen : std_ulogic; -- receiver fifo interrupt enable tfifoirqen : std_ulogic; -- transmitter fifo interrupt enable irqcnt : std_logic_vector(5 downto 0); -- delay counter for rx irq --fifo counters rwaddr : std_logic_vector(log2x(fifosize) - 1 downto 0); rraddr : std_logic_vector(log2x(fifosize) - 1 downto 0); traddr : std_logic_vector(log2x(fifosize) - 1 downto 0); twaddr : std_logic_vector(log2x(fifosize) - 1 downto 0); rcnt : std_logic_vector(log2x(fifosize) downto 0); tcnt : std_logic_vector(log2x(fifosize) downto 0); end record; constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0'); constant addrzero : std_logic_vector(log2x(fifosize)-1 downto 0) := (others => '0'); constant sbitszero : std_logic_vector(sbits-1 downto 0) := (others => '0'); constant fifozero : fifo := (others => (others => '0')); constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; constant RES : uartregs := (rxen => '0', txen => '0', rirqen => '0', tirqen => '0', parsel => '0', paren => '0', flow => '0', loopb => '0', debug => '0', rsempty => '1', tsempty => '1', tsemptyirqen => '0', break => '0', breakirqen => '0', ovf => '0', parerr => '0', frame => '0', ctsn => (others => '0'), rtsn => '1', extclken => '0', extclk => '0', rhold => fifozero, rshift => (others => '0'), tshift => (others => '1'), thold => fifozero, irq => '0', irqpend => '0', delayirqen => '0', tpar => '0', txstate => idle, txclk => (others => '0'), txtick => '0', rxstate => idle, rxclk => (others => '0'), rxdb => (others => '0'), dpar => '0',rxtick => '0', tick => '0', scaler => sbitszero, brate => sbitszero, rxf => (others => '0'), txd => '0', rfifoirqen => '0', tfifoirqen => '0', irqcnt => (others => '0'), rwaddr => addrzero, rraddr => addrzero, traddr => addrzero, twaddr => addrzero, rcnt => rcntzero, tcnt => rcntzero); signal r, rin : uartregs; begin uartop : process(rst, r, apbi, uarti ) variable rdata : std_logic_vector(31 downto 0); variable scaler : std_logic_vector(sbits-1 downto 0); variable rxclk, txclk : std_logic_vector(2 downto 0); variable rxd, ctsn : std_ulogic; variable irq : std_logic_vector(NAHBIRQ-1 downto 0); variable paddress : std_logic_vector(7 downto 2); variable v : uartregs; variable thalffull : std_ulogic; variable rhalffull : std_ulogic; variable rfull : std_ulogic; variable tfull : std_ulogic; variable dready : std_ulogic; variable thempty : std_ulogic; --pragma translate_off variable L1 : line; variable CH : character; variable FIRST : boolean := true; variable pt : time := 0 ns; --pragma translate_on begin v := r; irq := (others => '0'); irq(pirq) := r.irq; v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0'); v.rxdb(1) := r.rxdb(0); dready := '0'; thempty := '1'; thalffull := '1'; rhalffull := '0'; v.ctsn := r.ctsn(0) & uarti.ctsn; paddress := (others => '0'); paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2); if fifosize = 1 then dready := r.rcnt(0); rfull := dready; tfull := r.tcnt(0); thempty := not tfull; else tfull := r.tcnt(log2x(fifosize)); rfull := r.rcnt(log2x(fifosize)); if (r.rcnt(log2x(fifosize)) or r.rcnt(log2x(fifosize) - 1)) = '1' then rhalffull := '1'; end if; if ((r.tcnt(log2x(fifosize)) or r.tcnt(log2x(fifosize) - 1))) = '1' then thalffull := '0'; end if; if r.rcnt /= rcntzero then dready := '1'; end if; if r.tcnt /= rcntzero then thempty := '0'; end if; end if; -- scaler scaler := r.scaler - 1; if (r.rxen or r.txen) = '1' then v.scaler := scaler; v.tick := scaler(sbits-1) and not r.scaler(sbits-1); if v.tick = '1' then v.scaler := r.brate; end if; end if; -- optional external uart clock v.extclk := uarti.extclk; if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if; -- read/write registers if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then case paddress(7 downto 2) is when "000000" => rdata(7 downto 0) := r.rhold(conv_integer(r.rraddr)); if fifosize = 1 then v.rcnt(0) := '0'; else if r.rcnt /= rcntzero then v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1; end if; end if; when "000001" => if fifosize /= 1 then rdata (26 + log2x(fifosize) downto 26) := r.rcnt; rdata (20 + log2x(fifosize) downto 20) := r.tcnt; rdata (10 downto 7) := rfull & tfull & rhalffull & thalffull; end if; rdata(6 downto 0) := r.frame & r.parerr & r.ovf & r.break & thempty & r.tsempty & dready; --pragma translate_off if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if; --pragma translate_on when "000010" => if fifosize > 1 then rdata(31) := '1'; end if; rdata(14) := r.tsemptyirqen; rdata(13) := r.delayirqen; rdata(12) := r.breakirqen; rdata(11) := r.debug; if fifosize /= 1 then rdata(10 downto 9) := r.rfifoirqen & r.tfifoirqen; end if; rdata(8 downto 0) := r.extclken & r.loopb & r.flow & r.paren & r.parsel & r.tirqen & r.rirqen & r.txen & r.rxen; when "000011" => rdata(sbits-1 downto 0) := r.brate; when "000100" => -- Read TX FIFO. if r.debug = '1' and r.tcnt /= rcntzero then rdata(7 downto 0) := r.thold(conv_integer(r.traddr)); if fifosize = 1 then v.tcnt(0) := '0'; else v.traddr := r.traddr + 1; v.tcnt := r.tcnt - 1; end if; end if; when others => null; end case; end if; if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then case paddress(7 downto 2) is when "000000" => when "000001" => v.frame := apbi.pwdata(6); v.parerr := apbi.pwdata(5); v.ovf := apbi.pwdata(4); v.break := apbi.pwdata(3); when "000010" => v.tsemptyirqen := apbi.pwdata(14); v.delayirqen := apbi.pwdata(13); v.breakirqen := apbi.pwdata(12); v.debug := apbi.pwdata(11); if fifosize /= 1 then v.rfifoirqen := apbi.pwdata(10); v.tfifoirqen := apbi.pwdata(9); end if; v.extclken := apbi.pwdata(8); v.loopb := apbi.pwdata(7); v.flow := apbi.pwdata(6); v.paren := apbi.pwdata(5); v.parsel := apbi.pwdata(4); v.tirqen := apbi.pwdata(3); v.rirqen := apbi.pwdata(2); v.txen := apbi.pwdata(1); v.rxen := apbi.pwdata(0); when "000011" => v.brate := apbi.pwdata(sbits-1 downto 0); v.scaler := apbi.pwdata(sbits-1 downto 0); when "000100" => -- Write RX fifo and generate irq if flow /= 0 then v.rhold(conv_integer(r.rwaddr)) := apbi.pwdata(7 downto 0); if fifosize = 1 then v.rcnt(0) := '1'; else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if; if r.debug = '1' then v.irq := v.irq or r.rirqen; end if; end if; when others => null; end case; end if; -- tx clock txclk := r.txclk + 1; if r.tick = '1' then v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2); end if; -- rx clock rxclk := r.rxclk + 1; if r.tick = '1' then v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2); end if; if (r.rxtick and r.delayirqen) = '1' then v.irqcnt := v.irqcnt + 1; end if; if r.irqcnt(5 downto 4) = "11" then v.irq := v.irq or (r.delayirqen and r.irqpend); -- make sure no tx irqs are lost ! v.irqpend := '0'; end if; -- filter rx data -- v.rxf := r.rxf(6 downto 0) & uarti.rxd; -- if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & -- r.rxf(7)) = r.rxf(6 downto 0)) -- then v.rxdb(0) := r.rxf(7); end if; v.rxf(1 downto 0) := r.rxf(0) & uarti.rxd; -- meta-stability filter if r.tick = '1' then v.rxf(4 downto 2) := r.rxf(3 downto 1); end if; v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or (r.rxf(3) and r.rxf(2)); -- loop-back mode if r.loopb = '1' then v.rxdb(0) := r.tshift(0); ctsn := dready and not r.rsempty; elsif (flow = 1) then ctsn := r.ctsn(1); else ctsn := '0'; end if; rxd := r.rxdb(0); -- transmitter operation case r.txstate is when idle => -- idle state if (r.txtick = '1') then v.tsempty := '1'; end if; if ((not r.debug and r.txen and (not thempty) and r.txtick) and ((not ctsn) or not r.flow)) = '1' then v.txstate := data; v.tpar := r.parsel; v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0'; v.tshift := "10" & r.thold(conv_integer(r.traddr)) & '0'; if fifosize = 1 then v.irq := r.irq or r.tirqen; v.tcnt(0) := '0'; else v.traddr := r.traddr + 1; v.tcnt := r.tcnt - 1; end if; end if; when data => -- transmit data frame if r.txtick = '1' then v.tpar := r.tpar xor r.tshift(1); v.tshift := '1' & r.tshift(10 downto 1); if r.tshift(10 downto 1) = "1111111110" then if r.paren = '1' then v.tshift(0) := r.tpar; v.txstate := cparity; else v.tshift(0) := '1'; v.txstate := stopbit; end if; end if; end if; when cparity => -- transmit parity bit if r.txtick = '1' then v.tshift := '1' & r.tshift(10 downto 1); v.txstate := stopbit; end if; when stopbit => -- transmit stop bit if r.txtick = '1' then v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle; end if; end case; -- writing of tx data register must be done after tx fsm to get correct -- operation of thempty flag if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then case paddress(4 downto 2) is when "000" => if fifosize = 1 then v.thold(0) := apbi.pwdata(7 downto 0); v.tcnt(0) := '1'; else v.thold(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0); if not (tfull = '1') then v.twaddr := r.twaddr + 1; v.tcnt := v.tcnt + 1; end if; end if; --pragma translate_off if CONSOLE = 1 then if first then L1:= new string'(""); first := false; end if; --' if apbi.penable'event then --' CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --' if CH = CR then std.textio.writeline(OUTPUT, L1); elsif CH /= LF then std.textio.write(L1,CH); end if; pt := now; end if; end if; --pragma translate_on when others => null; end case; end if; -- receiver operation case r.rxstate is when idle => -- wait for start bit if ((r.rsempty = '0') and not (rfull = '1')) then v.rsempty := '1'; v.rhold(conv_integer(r.rwaddr)) := r.rshift; if fifosize = 1 then v.rcnt(0) := '1'; else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if; end if; if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100"; if v.rsempty = '0' then v.ovf := '1'; end if; v.rsempty := '0'; v.rxtick := '0'; end if; when startbit => -- check validity of start bit if r.rxtick = '1' then if rxd = '0' then v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data; v.dpar := r.parsel; else v.rxstate := idle; end if; end if; when data => -- receive data frame if r.rxtick = '1' then v.dpar := r.dpar xor rxd; v.rshift := rxd & r.rshift(7 downto 1); if r.rshift(0) = '0' then if r.paren = '1' then v.rxstate := cparity; else v.rxstate := stopbit; v.dpar := '0'; end if; end if; end if; when cparity => -- receive parity bit if r.rxtick = '1' then v.dpar := r.dpar xor rxd; v.rxstate := stopbit; end if; when stopbit => -- receive stop bit if r.rxtick = '1' then if r.delayirqen = '0' then v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost ! end if; if rxd = '1' then if r.delayirqen = '1' then v.irqpend := r.rirqen; v.irqcnt := (others => '0'); end if; v.parerr := r.parerr or r.dpar; v.rsempty := r.dpar; if not (rfull = '1') and (r.dpar = '0') then v.rsempty := '1'; v.rhold(conv_integer(r.rwaddr)) := r.rshift; if fifosize = 1 then v.rcnt(0) := '1'; else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if; end if; else if r.rshift = "00000000" then v.break := '1'; v.irq := v.irq or r.breakirqen; else v.frame := '1'; end if; v.rsempty := '1'; end if; v.rxstate := idle; end if; end case; if r.rxtick = '1' then v.rtsn := (rfull and not r.rsempty) or r.loopb; end if; v.txd := r.tshift(0) or r.loopb or r.debug; if fifosize /= 1 then if thempty = '0' and v.tcnt = rcntzero then v.irq := v.irq or r.tirqen; end if; v.irq := v.irq or (r.tfifoirqen and r.txen and thalffull); v.irq := v.irq or (r.rfifoirqen and r.rxen and rhalffull); if (r.rfifoirqen and r.rxen and rhalffull) = '1' then v.irqpend := '0'; end if; end if; v.irq := v.irq or (r.tsemptyirqen and v.tsempty and not r.tsempty); -- reset operation if (not RESET_ALL) and (rst = '0') then v.frame := RES.frame; v.rsempty := RES.rsempty; v.parerr := RES.parerr; v.ovf := RES.ovf; v.break := RES.break; v.tsempty := RES.tsempty; v.txen := RES.txen; v.rxen := RES.rxen; v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0); v.extclken := RES.extclken; v.rtsn := RES.rtsn; v.flow := RES.flow; v.txclk := RES.txclk; v.rxclk := RES.rxclk; v.rcnt := RES.rcnt; v.tcnt := RES.tcnt; v.rwaddr := RES.rwaddr; v.twaddr := RES.twaddr; v.rraddr := RES.rraddr; v.traddr := RES.traddr; v.irqcnt := RES.irqcnt; v.irqpend := RES.irqpend; end if; -- update registers rin <= v; -- drive outputs uarto.txd <= r.txd; uarto.rtsn <= r.rtsn; uarto.scaler <= (others => '0'); uarto.scaler(sbits-1 downto 0) <= r.scaler; apbo.prdata <= rdata; apbo.pirq <= irq; apbo.pindex <= pindex; uarto.txen <= r.txen; uarto.rxen <= r.rxen; uarto.flow <= '0'; end process; apbo.pconfig <= pconfig; regs : process(clk) begin if rising_edge(clk) then r <= rin; if RESET_ALL and rst = '0' then r <= RES; -- Sync. registers not reset r.ctsn <= rin.ctsn; r.rxf <= rin.rxf; end if; end if; end process; -- pragma translate_off bootmsg : report_version generic map ("apbuart" & tost(pindex) & ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) & ", irq " & tost(pirq) & ", scaler bits " & tost(sbits)); -- pragma translate_on end;

gpl-2.0

c7498eb2d353e21ca88fa50b1e4a3d74

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/spw/wrapper/grspw2_gen.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: grspw2_gen -- File: grspw2_gen.vhd -- Author: Marko Isomaki - Aeroflex Gaisler -- Description: Generic GRSPW2 core ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library spw; use spw.spwcomp.all; entity grspw2_gen is generic( rmap : integer range 0 to 2 := 0; rmapcrc : integer range 0 to 1 := 0; fifosize1 : integer range 4 to 64 := 32; fifosize2 : integer range 16 to 64 := 64; rxunaligned : integer range 0 to 1 := 0; rmapbufs : integer range 2 to 8 := 4; scantest : integer range 0 to 1 := 0; ports : integer range 1 to 2 := 1; dmachan : integer range 1 to 4 := 1; tech : integer; input_type : integer range 0 to 3 := 0; output_type : integer range 0 to 2 := 0; rxtx_sameclk : integer range 0 to 1 := 0; ft : integer range 0 to 2 := 0; techfifo : integer range 0 to 1 := 1; memtech : integer := 0; nodeaddr : integer range 0 to 255 := 254; destkey : integer range 0 to 255 := 0; interruptdist : integer range 0 to 32 := 0; intscalerbits : integer range 0 to 31 := 0; intisrtimerbits : integer range 0 to 31 := 0; intiatimerbits : integer range 0 to 31 := 0; intctimerbits : integer range 0 to 31 := 0; tickinasync : integer range 0 to 1 := 0; pnp : integer range 0 to 2 := 0; pnpvendid : integer range 0 to 16#FFFF# := 0; pnpprodid : integer range 0 to 16#FFFF# := 0; pnpmajorver : integer range 0 to 16#FF# := 0; pnpminorver : integer range 0 to 16#FF# := 0; pnppatch : integer range 0 to 16#FF# := 0; num_txdesc : integer range 64 to 512 := 64; num_rxdesc : integer range 128 to 1024 := 128 ); port( rst : in std_ulogic; clk : in std_ulogic; rxclk0 : in std_ulogic; rxclk1 : in std_ulogic; txclk : in std_ulogic; txclkn : in std_ulogic; --ahb mst in hgrant : in std_ulogic; hready : in std_ulogic; hresp : in std_logic_vector(1 downto 0); hrdata : in std_logic_vector(31 downto 0); --ahb mst out hbusreq : out std_ulogic; hlock : out std_ulogic; htrans : out std_logic_vector(1 downto 0); haddr : out std_logic_vector(31 downto 0); hwrite : out std_ulogic; hsize : out std_logic_vector(2 downto 0); hburst : out std_logic_vector(2 downto 0); hprot : out std_logic_vector(3 downto 0); hwdata : out std_logic_vector(31 downto 0); --apb slv in psel : in std_ulogic; penable : in std_ulogic; paddr : in std_logic_vector(31 downto 0); pwrite : in std_ulogic; pwdata : in std_logic_vector(31 downto 0); --apb slv out prdata : out std_logic_vector(31 downto 0); --spw in d : in std_logic_vector(3 downto 0); dv : in std_logic_vector(3 downto 0); dconnect : in std_logic_vector(3 downto 0); --spw out do : out std_logic_vector(3 downto 0); so : out std_logic_vector(3 downto 0); --time iface tickin : in std_ulogic; tickinraw : in std_ulogic; timein : in std_logic_vector(7 downto 0); tickindone : out std_ulogic; tickout : out std_ulogic; tickoutraw : out std_ulogic; timeout : out std_logic_vector(7 downto 0); --irq irq : out std_logic; --misc clkdiv10 : in std_logic_vector(7 downto 0); linkdis : out std_ulogic; testrst : in std_ulogic := '0'; testen : in std_ulogic := '0'; --rmapen rmapen : in std_ulogic; rmapnodeaddr : in std_logic_vector(7 downto 0); --parallel rx data out rxdav : out std_ulogic; rxdataout : out std_logic_vector(8 downto 0); loopback : out std_ulogic; -- interrupt dist. default values intpreload : in std_logic_vector(30 downto 0); inttreload : in std_logic_vector(30 downto 0); intiareload : in std_logic_vector(30 downto 0); intcreload : in std_logic_vector(30 downto 0); irqtxdefault : in std_logic_vector(4 downto 0); --SpW PnP enable pnpen : in std_ulogic; pnpuvendid : in std_logic_vector(15 downto 0); pnpuprodid : in std_logic_vector(15 downto 0); pnpusn : in std_logic_vector(31 downto 0) ); end entity; architecture rtl of grspw2_gen is constant fabits1 : integer := log2(fifosize1); constant fabits2 : integer := log2(fifosize2); constant rfifo : integer := 5 + log2(rmapbufs); signal rxclki, nrxclki, rxclko : std_logic_vector(1 downto 0); --rx ahb fifo signal rxrenable : std_ulogic; signal rxraddress : std_logic_vector(5 downto 0); signal rxwrite : std_ulogic; signal rxwdata : std_logic_vector(31 downto 0); signal rxwaddress : std_logic_vector(5 downto 0); signal rxrdata : std_logic_vector(31 downto 0); --tx ahb fifo signal txrenable : std_ulogic; signal txraddress : std_logic_vector(5 downto 0); signal txwrite : std_ulogic; signal txwdata : std_logic_vector(31 downto 0); signal txwaddress : std_logic_vector(5 downto 0); signal txrdata : std_logic_vector(31 downto 0); --nchar fifo signal ncrenable : std_ulogic; signal ncraddress : std_logic_vector(5 downto 0); signal ncwrite : std_ulogic; signal ncwdata : std_logic_vector(9 downto 0); signal ncwaddress : std_logic_vector(5 downto 0); signal ncrdata : std_logic_vector(9 downto 0); --rmap buf signal rmrenable : std_ulogic; signal rmrenablex : std_ulogic; signal rmraddress : std_logic_vector(7 downto 0); signal rmwrite : std_ulogic; signal rmwdata : std_logic_vector(7 downto 0); signal rmwaddress : std_logic_vector(7 downto 0); signal rmrdata : std_logic_vector(7 downto 0); --misc signal rxclk, nrxclk: std_logic_vector(ports-1 downto 0); signal testin : std_logic_vector(3 downto 0); attribute syn_netlist_hierarchy : boolean; attribute syn_netlist_hierarchy of rtl : architecture is false; begin testin <= testen & "000"; grspwc0: grspwc2 generic map( rmap => rmap, rmapcrc => rmapcrc, fifosize1 => fifosize1, fifosize2 => fifosize2, rxunaligned => rxunaligned, rmapbufs => rmapbufs, scantest => scantest, ports => ports, dmachan => dmachan, tech => tech, input_type => input_type, output_type => output_type, rxtx_sameclk => rxtx_sameclk, nodeaddr => nodeaddr, destkey => destkey, interruptdist => interruptdist, intscalerbits => intscalerbits, intisrtimerbits => intisrtimerbits, intiatimerbits => intiatimerbits, intctimerbits => intctimerbits, tickinasync => tickinasync, pnp => pnp, pnpvendid => pnpvendid, pnpprodid => pnpprodid, pnpmajorver => pnpmajorver, pnpminorver => pnpminorver, pnppatch => pnppatch, num_txdesc => num_txdesc, num_rxdesc => num_rxdesc) port map( rst => rst, clk => clk, rxclk0 => rxclk0, rxclk1 => rxclk1, txclk => txclk, txclkn => txclkn, --ahb mst in hgrant => hgrant, hready => hready, hresp => hresp, hrdata => hrdata, --ahb mst out hbusreq => hbusreq, hlock => hlock, htrans => htrans, haddr => haddr, hwrite => hwrite, hsize => hsize, hburst => hburst, hprot => hprot, hwdata => hwdata, --apb slv in psel => psel, penable => penable, paddr => paddr, pwrite => pwrite, pwdata => pwdata, --apb slv out prdata => prdata, --spw in d => d, dv => dv, dconnect => dconnect, --spw out do => do, so => so, --time iface tickin => tickin, tickinraw => tickinraw, timein => timein, tickindone => tickindone, tickout => tickout, tickoutraw => tickoutraw, timeout => timeout, --irq irq => irq, --misc clkdiv10 => clkdiv10, --rmapen rmapen => rmapen, rmapnodeaddr => rmapnodeaddr, --rx ahb fifo rxrenable => rxrenable, rxraddress => rxraddress, rxwrite => rxwrite, rxwdata => rxwdata, rxwaddress => rxwaddress, rxrdata => rxrdata, --tx ahb fifo txrenable => txrenable, txraddress => txraddress, txwrite => txwrite, txwdata => txwdata, txwaddress => txwaddress, txrdata => txrdata, --nchar fifo ncrenable => ncrenable, ncraddress => ncraddress, ncwrite => ncwrite, ncwdata => ncwdata, ncwaddress => ncwaddress, ncrdata => ncrdata, --rmap buf rmrenable => rmrenable, rmraddress => rmraddress, rmwrite => rmwrite, rmwdata => rmwdata, rmwaddress => rmwaddress, rmrdata => rmrdata, linkdis => linkdis, testrst => testrst, testen => testen, --parallel rx data out rxdav => rxdav, rxdataout => rxdataout, loopback => loopback, -- interrupt dist. default values intpreload => intpreload, inttreload => inttreload, intiareload => intiareload, intcreload => intcreload, irqtxdefault => irqtxdefault, -- SpW PnP enable pnpen => pnpen, pnpuvendid => pnpuvendid, pnpuprodid => pnpuprodid, pnpusn => pnpusn ); ------------------------------------------------------------------------------ -- FIFOS --------------------------------------------------------------------- ------------------------------------------------------------------------------ nft : if ft = 0 generate --receiver AHB FIFO rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32) port map(clk, rxrenable, rxraddress(fabits1-1 downto 0), rxrdata, clk, rxwrite, rxwaddress(fabits1-1 downto 0), rxwdata, testin); --receiver nchar FIFO rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 10) port map(clk, ncrenable, ncraddress(fabits2-1 downto 0), ncrdata, clk, ncwrite, ncwaddress(fabits2-1 downto 0), ncwdata, testin); --transmitter FIFO tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32) port map(clk, txrenable, txraddress(fabits1-1 downto 0), txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata, testin); --RMAP Buffer rmap_ram : if (rmap /= 0) generate ram0 : syncram_2p generic map(memtech, rfifo, 8) port map(clk, rmrenable, rmraddress(rfifo-1 downto 0), rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0), rmwdata, testin); end generate; end generate; ft1 : if ft /= 0 generate --receiver AHB FIFO rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo) port map(clk, rxrenable, rxraddress(fabits1-1 downto 0), rxrdata, clk, rxwrite, rxwaddress(fabits1-1 downto 0), rxwdata, open, testin); --receiver nchar FIFO rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 10, 0, 0, 2*techfifo) port map(clk, ncrenable, ncraddress(fabits2-1 downto 0), ncrdata, clk, ncwrite, ncwaddress(fabits2-1 downto 0), ncwdata, open, testin); --transmitter FIFO tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo) port map(clk, txrenable, txraddress(fabits1-1 downto 0), txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata, open, testin); --RMAP Buffer rmap_ram : if (rmap /= 0) generate ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2) port map(clk, rmrenable, rmraddress(rfifo-1 downto 0), rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0), rmwdata, open, testin); end generate; end generate; end architecture;

gpl-2.0

2318e9e2de220c8d2a30125cc01f4a37

davidhorrocks/1541UltimateII

fpga/1541/vhdl_source/cpu_part_1541.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mem_bus_pkg.all; entity cpu_part_1541 is generic ( g_tag : std_logic_vector(7 downto 0) := X"02"; g_ram_base : unsigned(27 downto 0) := X"0060000" ); port ( clock : in std_logic; clock_en : in std_logic; reset : in std_logic; -- serial bus pins atn_o : out std_logic; -- open drain atn_i : in std_logic; clk_o : out std_logic; -- open drain clk_i : in std_logic; data_o : out std_logic; -- open drain data_i : in std_logic; -- memory interface mem_req : out t_mem_req; mem_resp : in t_mem_resp; -- trace out cpu_pc : out std_logic_vector(15 downto 0); -- configuration bank_is_ram : in std_logic_vector(7 downto 0); -- drive pins power : in std_logic; drive_address : in std_logic_vector(1 downto 0); motor_on : out std_logic; mode : out std_logic; write_prot_n : in std_logic; step : out std_logic_vector(1 downto 0); soe : out std_logic; rate_ctrl : out std_logic_vector(1 downto 0); byte_ready : in std_logic; sync : in std_logic; track_is_0 : in std_logic; drv_rdata : in std_logic_vector(7 downto 0); drv_wdata : out std_logic_vector(7 downto 0); act_led : out std_logic ); end cpu_part_1541; architecture structural of cpu_part_1541 is signal cpu_write : std_logic; signal cpu_wdata : std_logic_vector(7 downto 0); signal cpu_rdata : std_logic_vector(7 downto 0); signal cpu_addr : std_logic_vector(16 downto 0); signal cpu_irqn : std_logic; signal ext_rdata : std_logic_vector(7 downto 0) := X"00"; signal io_rdata : std_logic_vector(7 downto 0); signal via1_data : std_logic_vector(7 downto 0); signal via2_data : std_logic_vector(7 downto 0); signal ram_en : std_logic; signal via1_wen : std_logic; signal via1_ren : std_logic; signal via2_wen : std_logic; signal via2_ren : std_logic; signal via1_port_a_o : std_logic_vector(7 downto 0); signal via1_port_a_t : std_logic_vector(7 downto 0); signal via1_port_a_i : std_logic_vector(7 downto 0); signal via1_port_b_o : std_logic_vector(7 downto 0); signal via1_port_b_t : std_logic_vector(7 downto 0); signal via1_port_b_i : std_logic_vector(7 downto 0); signal via1_ca1 : std_logic; signal via1_ca2 : std_logic; signal via1_cb1 : std_logic; signal via1_cb2 : std_logic; signal via1_irq : std_logic; signal via2_port_b_o : std_logic_vector(7 downto 0); signal via2_port_b_t : std_logic_vector(7 downto 0); signal via2_port_b_i : std_logic_vector(7 downto 0); signal via2_ca2_o : std_logic; signal via2_ca2_i : std_logic; signal via2_ca2_t : std_logic; signal via2_cb1_o : std_logic; signal via2_cb1_i : std_logic; signal via2_cb1_t : std_logic; signal via2_cb2_o : std_logic; signal via2_cb2_i : std_logic; signal via2_cb2_t : std_logic; signal via2_irq : std_logic; signal bank_is_io : std_logic_vector(7 downto 0); signal io_select : std_logic; signal rdata_mux : std_logic; signal cpu_ready : std_logic; signal need_cycle : unsigned(2 downto 0); signal done_cycle : unsigned(2 downto 0); type t_mem_state is (idle, cpubusy, newcycle, extcycle); signal mem_state : t_mem_state; signal clock_en_d : std_logic; signal clock_en_dd : std_logic; -- "old" style signals signal mem_request : std_logic; signal mem_addr : unsigned(25 downto 0); signal mem_rwn : std_logic; signal mem_rack : std_logic; signal mem_dack : std_logic; signal mem_wdata : std_logic_vector(7 downto 0); begin mem_req.request <= mem_request; mem_req.address <= mem_addr; mem_req.read_writen <= mem_rwn; mem_req.data <= mem_wdata; mem_req.tag <= g_tag; mem_req.size <= "00"; -- 1 byte at a time mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0'; mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0'; cpu: entity work.cpu6502(cycle_exact) port map ( cpu_clk => clock, cpu_reset => reset, cpu_ready => cpu_ready, cpu_write => cpu_write, cpu_wdata => cpu_wdata, cpu_rdata => cpu_rdata, cpu_addr => cpu_addr, cpu_pc => cpu_pc, IRQn => cpu_irqn, -- IRQ interrupt (level sensitive) NMIn => '1', SOn => byte_ready ); via1: entity work.via6522 port map ( clock => clock, clock_en => cpu_ready, reset => reset, addr => cpu_addr(3 downto 0), wen => via1_wen, ren => via1_ren, data_in => cpu_wdata, data_out => via1_data, -- pio -- port_a_o => via1_port_a_o, port_a_t => via1_port_a_t, port_a_i => via1_port_a_i, port_b_o => via1_port_b_o, port_b_t => via1_port_b_t, port_b_i => via1_port_b_i, -- handshake pins ca1_i => via1_ca1, ca2_o => via1_ca2, ca2_i => via1_ca2, ca2_t => open, cb1_o => via1_cb1, cb1_i => via1_cb1, cb1_t => open, cb2_o => via1_cb2, cb2_i => via1_cb2, cb2_t => open, irq => via1_irq ); via2: entity work.via6522 port map ( clock => clock, clock_en => cpu_ready, reset => reset, addr => cpu_addr(3 downto 0), wen => via2_wen, ren => via2_ren, data_in => cpu_wdata, data_out => via2_data, -- pio -- port_a_o => drv_wdata, port_a_t => open, port_a_i => drv_rdata, port_b_o => via2_port_b_o, port_b_t => via2_port_b_t, port_b_i => via2_port_b_i, -- handshake pins ca1_i => byte_ready, ca2_o => via2_ca2_o, ca2_i => via2_ca2_i, ca2_t => via2_ca2_t, cb1_o => via2_cb1_o, cb1_i => via2_cb1_i, cb1_t => via2_cb1_t, cb2_o => via2_cb2_o, cb2_i => via2_cb2_i, cb2_t => via2_cb2_t, irq => via2_irq ); cpu_irqn <= not(via1_irq or via2_irq); -- Fetch ROM byte process(clock) begin if rising_edge(clock) then if clock_en='1' then need_cycle <= need_cycle + 1; end if; bank_is_io <= "0000" & not bank_is_ram(3 downto 1) & '1'; mem_addr(25 downto 16) <= g_ram_base(25 downto 16); clock_en_d <= clock_en; clock_en_dd <= clock_en_d; cpu_ready <= '0'; case mem_state is when idle => if need_cycle /= done_cycle then cpu_ready <= '1'; mem_state <= cpubusy; end if; when cpubusy => mem_state <= newcycle; when newcycle => -- we have a new address now mem_addr(15 downto 0) <= unsigned(cpu_addr(15 downto 0)); io_select <= '0'; if bank_is_io(to_integer(unsigned(cpu_addr(15 downto 13))))='1' then rdata_mux <= '1'; -- io if cpu_addr(12)='0' then -- lower 4K of IO block is possibly RAM mem_request <= '1'; mem_state <= extcycle; mem_addr(14 downto 13) <= "00"; -- cause mirroring else io_select <= '1'; done_cycle <= done_cycle + 1; mem_state <= idle; end if; elsif cpu_write='0' or bank_is_ram(to_integer(unsigned(cpu_addr(15 downto 13))))='1' then -- ram is writeable, rom is not rdata_mux <= '0'; mem_request <= '1'; mem_state <= extcycle; else -- write to rom -> ignore done_cycle <= done_cycle + 1; mem_state <= idle; end if; when extcycle => if mem_rack='1' then mem_request <= '0'; if cpu_write='1' then done_cycle <= done_cycle + 1; mem_state <= idle; end if; end if; if mem_dack='1' and cpu_write='0' then -- only for reads ext_rdata <= mem_resp.data; done_cycle <= done_cycle + 1; mem_state <= idle; end if; when others => null; end case; if reset='1' then rdata_mux <= '0'; io_select <= '0'; cpu_ready <= '0'; mem_request <= '0'; mem_state <= idle; need_cycle <= "000"; done_cycle <= "000"; end if; end if; end process; mem_rwn <= not cpu_write; mem_wdata <= cpu_wdata; -- address decoding and data muxing with cpu_addr(12 downto 10) select io_rdata <= ext_rdata when "000", ext_rdata when "001", via1_data when "110", via2_data when "111", X"FF" when others; cpu_rdata <= io_rdata when rdata_mux='1' else ext_rdata; via1_wen <= '1' when cpu_write='1' and cpu_ready='1' and io_select='1' and cpu_addr(12 downto 10)="110" else '0'; via1_ren <= '1' when cpu_write='0' and cpu_ready='1' and io_select='1' and cpu_addr(12 downto 10)="110" else '0'; via2_wen <= '1' when cpu_write='1' and cpu_ready='1' and io_select='1' and cpu_addr(12 downto 10)="111" else '0'; via2_ren <= '1' when cpu_write='0' and cpu_ready='1' and io_select='1' and cpu_addr(12 downto 10)="111" else '0'; -- correctly attach the VIA pins to the outside world -- pull up when not driven... via1_port_a_i(7 downto 1) <= (others => '1'); via1_port_a_i(0) <= track_is_0; via1_ca1 <= not atn_i; via1_port_b_i(7) <= not atn_i; -- the following bits should read 0 when the jumper is closed (drive select = 0) or when driven low by the VIA itself via1_port_b_i(6) <= drive_address(1); -- drive select via1_port_b_i(5) <= drive_address(0); -- drive select; via1_port_b_i(4) <= '1'; -- atn a - PUP via1_port_b_i(3) <= '1'; -- clock out - PUP via1_port_b_i(2) <= not (clk_i and (not (via1_port_b_o(3) or not via1_port_b_t(3)))); via1_port_b_i(1) <= '1'; -- data out - PUP via1_port_b_i(0) <= not (data_i and (not (via1_port_b_o(1) or not via1_port_b_t(1))) and (not ((via1_port_b_o(4) or not via1_port_b_t(4)) xor (not atn_i)))); --auto_o <= not power or via1_port_b_i(4); data_o <= not power or ((not (via1_port_b_o(1) or not via1_port_b_t(1))) and (not ((via1_port_b_o(4) or not via1_port_b_t(4)) xor (not atn_i)))); clk_o <= not power or (not (via1_port_b_o(3) or not via1_port_b_t(3))); atn_o <= '1'; -- Do the same for VIA 2. Pin levels intead of output register. via2_port_b_i(7) <= sync; via2_port_b_i(6) <= '1'; --Density via2_port_b_i(5) <= '1'; --Density via2_port_b_i(4) <= write_prot_n; via2_port_b_i(3) <= '1'; -- LED via2_port_b_i(2) <= '1'; -- Motor via2_port_b_i(1) <= '1'; -- Step via2_port_b_i(0) <= '1'; -- Step via2_cb1_i <= via2_cb1_o or not via2_cb1_t; via2_cb2_i <= via2_cb2_o or not via2_cb2_t; via2_ca2_i <= via2_ca2_o or not via2_ca2_t; act_led <= not (via2_port_b_o(3) or not via2_port_b_t(3)) or not power; mode <= via2_cb2_i; step(0) <= via2_port_b_o(0) or not via2_port_b_t(0); step(1) <= via2_port_b_o(1) or not via2_port_b_t(1); motor_on <= (via2_port_b_o(2) or not via2_port_b_t(2)) and power; soe <= via2_ca2_i; rate_ctrl(0) <= via2_port_b_o(5) or not via2_port_b_t(5); rate_ctrl(1) <= via2_port_b_o(6) or not via2_port_b_t(6); end structural; -- Original mapping: -- 0000-07FF RAM -- 0800-17FF open -- 1800-1BFF VIA 1 -- 1C00-1CFF VIA 2 -- 2000-27FF RAM -- 2800-37FF open -- 3800-3BFF VIA 1 -- 3C00-3CFF VIA 2 -- 4000-47FF RAM -- 4800-57FF open -- 5800-5BFF VIA 1 -- 5C00-5CFF VIA 2 -- 6000-67FF RAM -- 6800-77FF open -- 7800-7BFF VIA 1 -- 7C00-7CFF VIA 2 -- 8000-BFFF ROM image (mirror) -- C000-FFFF ROM image

gpl-3.0

85d4ba76f3ae3dac5c5545f953eba011

davidhorrocks/1541UltimateII

fpga/6502/vhdl_source/cpu6502.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cpu6502 is port ( cpu_clk : in std_logic; cpu_reset : in std_logic; cpu_ready : in std_logic; cpu_write : out std_logic; cpu_wdata : out std_logic_vector(7 downto 0); cpu_rdata : in std_logic_vector(7 downto 0); cpu_addr : out std_logic_vector(16 downto 0); cpu_pc : out std_logic_vector(15 downto 0); IRQn : in std_logic; -- IRQ interrupt (level sensitive) NMIn : in std_logic; -- NMI interrupt (edge sensitive) SOn : in std_logic -- set Overflow flag ); end cpu6502; architecture cycle_exact of cpu6502 is signal read_write_n : std_logic; begin core: entity work.proc_core generic map ( support_bcd => true ) port map( clock => cpu_clk, clock_en => cpu_ready, reset => cpu_reset, irq_n => IRQn, nmi_n => NMIn, so_n => SOn, pc_out => cpu_pc, addr_out => cpu_addr, data_in => cpu_rdata, data_out => cpu_wdata, read_write_n => read_write_n ); cpu_write <= not read_write_n; end cycle_exact;

gpl-3.0

1c5cb102ec21f3fc433a24505a43d618

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_rst_ps7_0_100M_1/zqynq_lab_1_design_rst_ps7_0_100M_1_sim_netlist.vhdl

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Wed Sep 20 21:09:13 2017 -- Host : EffulgentTome running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top zqynq_lab_1_design_rst_ps7_0_100M_1 -prefix -- zqynq_lab_1_design_rst_ps7_0_100M_1_ zqynq_lab_1_design_rst_ps7_0_100M_0_sim_netlist.vhdl -- Design : zqynq_lab_1_design_rst_ps7_0_100M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_rst_ps7_0_100M_1_cdc_sync is port ( lpf_asr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; aux_reset_in : in STD_LOGIC; lpf_asr : in STD_LOGIC; asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); p_1_in : in STD_LOGIC; p_2_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end zqynq_lab_1_design_rst_ps7_0_100M_1_cdc_sync; architecture STRUCTURE of zqynq_lab_1_design_rst_ps7_0_100M_1_cdc_sync is signal asr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => asr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aux_reset_in, O => asr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_asr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_asr, I1 => asr_lpf(0), I2 => \^scndry_out\, I3 => p_1_in, I4 => p_2_in, O => lpf_asr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_rst_ps7_0_100M_1_cdc_sync_0 is port ( lpf_exr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_exr : in STD_LOGIC; p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_rst_ps7_0_100M_1_cdc_sync_0 : entity is "cdc_sync"; end zqynq_lab_1_design_rst_ps7_0_100M_1_cdc_sync_0; architecture STRUCTURE of zqynq_lab_1_design_rst_ps7_0_100M_1_cdc_sync_0 is signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => mb_debug_sys_rst, I1 => ext_reset_in, O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_exr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_exr, I1 => p_3_out(0), I2 => \^scndry_out\, I3 => p_3_out(1), I4 => p_3_out(2), O => lpf_exr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_rst_ps7_0_100M_1_upcnt_n is port ( Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); seq_clr : in STD_LOGIC; seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end zqynq_lab_1_design_rst_ps7_0_100M_1_upcnt_n; architecture STRUCTURE of zqynq_lab_1_design_rst_ps7_0_100M_1_upcnt_n is signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal clear : STD_LOGIC; signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; begin Q(5 downto 0) <= \^q\(5 downto 0); \q_int[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => q_int0(0) ); \q_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => q_int0(1) ); \q_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => q_int0(2) ); \q_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => q_int0(3) ); \q_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => q_int0(4) ); \q_int[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => seq_clr, O => clear ); \q_int[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => q_int0(5) ); \q_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(0), Q => \^q\(0), R => clear ); \q_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(1), Q => \^q\(1), R => clear ); \q_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(2), Q => \^q\(2), R => clear ); \q_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(3), Q => \^q\(3), R => clear ); \q_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(4), Q => \^q\(4), R => clear ); \q_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(5), Q => \^q\(5), R => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_rst_ps7_0_100M_1_lpf is port ( lpf_int : out STD_LOGIC; slowest_sync_clk : in STD_LOGIC; dcm_locked : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC ); end zqynq_lab_1_design_rst_ps7_0_100M_1_lpf; architecture STRUCTURE of zqynq_lab_1_design_rst_ps7_0_100M_1_lpf is signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; signal Q : STD_LOGIC; signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); signal lpf_asr : STD_LOGIC; signal lpf_exr : STD_LOGIC; signal \lpf_int0__0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC; signal p_3_in1_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; attribute box_type : string; attribute box_type of POR_SRL_I : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; begin \ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.zqynq_lab_1_design_rst_ps7_0_100M_1_cdc_sync port map ( asr_lpf(0) => asr_lpf(0), aux_reset_in => aux_reset_in, lpf_asr => lpf_asr, lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, p_1_in => p_1_in, p_2_in => p_2_in, scndry_out => p_3_in1_in, slowest_sync_clk => slowest_sync_clk ); \ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.zqynq_lab_1_design_rst_ps7_0_100M_1_cdc_sync_0 port map ( ext_reset_in => ext_reset_in, lpf_exr => lpf_exr, lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, mb_debug_sys_rst => mb_debug_sys_rst, p_3_out(2 downto 0) => p_3_out(2 downto 0), scndry_out => p_3_out(3), slowest_sync_clk => slowest_sync_clk ); \AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_in1_in, Q => p_2_in, R => '0' ); \AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_2_in, Q => p_1_in, R => '0' ); \AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_1_in, Q => asr_lpf(0), R => '0' ); \EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(3), Q => p_3_out(2), R => '0' ); \EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => p_3_out(1), R => '0' ); \EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(1), Q => p_3_out(0), R => '0' ); POR_SRL_I: unisim.vcomponents.SRL16E generic map( INIT => X"FFFF" ) port map ( A0 => '1', A1 => '1', A2 => '1', A3 => '1', CE => '1', CLK => slowest_sync_clk, D => '0', Q => Q ); lpf_asr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, Q => lpf_asr, R => '0' ); lpf_exr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, Q => lpf_exr, R => '0' ); lpf_int0: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => Q, I1 => lpf_asr, I2 => dcm_locked, I3 => lpf_exr, O => \lpf_int0__0\ ); lpf_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \lpf_int0__0\, Q => lpf_int, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_rst_ps7_0_100M_1_sequence_psr is port ( Core : out STD_LOGIC; bsr : out STD_LOGIC; pr : out STD_LOGIC; \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC; \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC; lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end zqynq_lab_1_design_rst_ps7_0_100M_1_sequence_psr; architecture STRUCTURE of zqynq_lab_1_design_rst_ps7_0_100M_1_sequence_psr is signal \^core\ : STD_LOGIC; signal Core_i_1_n_0 : STD_LOGIC; signal \^bsr\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; signal bsr_i_1_n_0 : STD_LOGIC; signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; signal from_sys_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^pr\ : STD_LOGIC; signal \pr_dec0__0\ : STD_LOGIC; signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; signal pr_i_1_n_0 : STD_LOGIC; signal seq_clr : STD_LOGIC; signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); signal seq_cnt_en : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; begin Core <= \^core\; bsr <= \^bsr\; pr <= \^pr\; \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^bsr\, O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ ); \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^pr\, O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ ); Core_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^core\, I1 => p_0_in, O => Core_i_1_n_0 ); Core_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Core_i_1_n_0, Q => \^core\, S => lpf_int ); SEQ_COUNTER: entity work.zqynq_lab_1_design_rst_ps7_0_100M_1_upcnt_n port map ( Q(5 downto 0) => seq_cnt(5 downto 0), seq_clr => seq_clr, seq_cnt_en => seq_cnt_en, slowest_sync_clk => slowest_sync_clk ); \bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0804" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt(4), O => p_5_out(0) ); \bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \bsr_dec_reg_n_0_[0]\, O => p_5_out(2) ); \bsr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(0), Q => \bsr_dec_reg_n_0_[0]\, R => '0' ); \bsr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(2), Q => \bsr_dec_reg_n_0_[2]\, R => '0' ); bsr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^bsr\, I1 => \bsr_dec_reg_n_0_[2]\, O => bsr_i_1_n_0 ); bsr_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr_i_1_n_0, Q => \^bsr\, S => lpf_int ); \core_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8040" ) port map ( I0 => seq_cnt(4), I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt_en, O => \core_dec[0]_i_1_n_0\ ); \core_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \core_dec_reg_n_0_[0]\, O => \core_dec[2]_i_1_n_0\ ); \core_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[0]_i_1_n_0\, Q => \core_dec_reg_n_0_[0]\, R => '0' ); \core_dec_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \pr_dec0__0\, Q => \core_dec_reg_n_0_[1]\, R => '0' ); \core_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[2]_i_1_n_0\, Q => p_0_in, R => '0' ); from_sys_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^core\, I1 => seq_cnt_en, O => from_sys_i_1_n_0 ); from_sys_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => from_sys_i_1_n_0, Q => seq_cnt_en, S => lpf_int ); pr_dec0: unisim.vcomponents.LUT4 generic map( INIT => X"0210" ) port map ( I0 => seq_cnt(0), I1 => seq_cnt(1), I2 => seq_cnt(2), I3 => seq_cnt_en, O => \pr_dec0__0\ ); \pr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1080" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(5), I2 => seq_cnt(3), I3 => seq_cnt(4), O => p_3_out(0) ); \pr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \pr_dec_reg_n_0_[0]\, O => p_3_out(2) ); \pr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(0), Q => \pr_dec_reg_n_0_[0]\, R => '0' ); \pr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => \pr_dec_reg_n_0_[2]\, R => '0' ); pr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^pr\, I1 => \pr_dec_reg_n_0_[2]\, O => pr_i_1_n_0 ); pr_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => pr_i_1_n_0, Q => \^pr\, S => lpf_int ); seq_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => '1', Q => seq_clr, R => lpf_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset : entity is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset : entity is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset : entity is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset : entity is 4; attribute C_FAMILY : string; attribute C_FAMILY of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset : entity is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset : entity is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset : entity is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset : entity is 1; end zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset; architecture STRUCTURE of zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset is signal Core : STD_LOGIC; signal SEQ_n_3 : STD_LOGIC; signal SEQ_n_4 : STD_LOGIC; signal bsr : STD_LOGIC; signal lpf_int : STD_LOGIC; signal pr : STD_LOGIC; attribute equivalent_register_removal : string; attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no"; attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no"; attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no"; attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no"; begin \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_3, Q => interconnect_aresetn(0), R => '0' ); \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_4, Q => peripheral_aresetn(0), R => '0' ); \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr, Q => bus_struct_reset(0), R => '0' ); EXT_LPF: entity work.zqynq_lab_1_design_rst_ps7_0_100M_1_lpf port map ( aux_reset_in => aux_reset_in, dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, lpf_int => lpf_int, mb_debug_sys_rst => mb_debug_sys_rst, slowest_sync_clk => slowest_sync_clk ); \PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => pr, Q => peripheral_reset(0), R => '0' ); SEQ: entity work.zqynq_lab_1_design_rst_ps7_0_100M_1_sequence_psr port map ( \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3, \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4, Core => Core, bsr => bsr, lpf_int => lpf_int, pr => pr, slowest_sync_clk => slowest_sync_clk ); mb_reset_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Core, Q => mb_reset, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_rst_ps7_0_100M_1 is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of zqynq_lab_1_design_rst_ps7_0_100M_1 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_rst_ps7_0_100M_1 : entity is "zqynq_lab_1_design_rst_ps7_0_100M_0,proc_sys_reset,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_rst_ps7_0_100M_1 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of zqynq_lab_1_design_rst_ps7_0_100M_1 : entity is "proc_sys_reset,Vivado 2017.2"; end zqynq_lab_1_design_rst_ps7_0_100M_1; architecture STRUCTURE of zqynq_lab_1_design_rst_ps7_0_100M_1 is attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of U0 : label is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of U0 : label is 4; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of U0 : label is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of U0 : label is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of U0 : label is 1; begin U0: entity work.zqynq_lab_1_design_rst_ps7_0_100M_1_proc_sys_reset port map ( aux_reset_in => aux_reset_in, bus_struct_reset(0) => bus_struct_reset(0), dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, interconnect_aresetn(0) => interconnect_aresetn(0), mb_debug_sys_rst => mb_debug_sys_rst, mb_reset => mb_reset, peripheral_aresetn(0) => peripheral_aresetn(0), peripheral_reset(0) => peripheral_reset(0), slowest_sync_clk => slowest_sync_clk ); end STRUCTURE;

mit

18924782f0c6fb386afcc0b9a053cd8c

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ipshared/ffa3/hdl/axi_bram_ctrl_v4_0_rfs.vhd

------------------------------------------------------------------------------- -- SRL_FIFO entity and architecture ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the user’s sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2013 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: srl_fifo.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- srl_fifo.vhd -- ------------------------------------------------------------------------------- -- Author: goran -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- goran 2001-05-11 First Version -- KC 2001-06-20 Added Addr as an output port, for use as an occupancy -- value -- -- DCW 2002-03-12 Structural implementation of synchronous reset for -- Data_Exists DFF (using FDR) -- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims -- -- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR -- component declarations -- -- DET 1/17/2008 v4_00_a -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.all; entity SRL_FIFO is generic ( C_DATA_BITS : natural := 8; C_DEPTH : natural := 16; C_XON : boolean := false ); port ( Clk : in std_logic; Reset : in std_logic; FIFO_Write : in std_logic; Data_In : in std_logic_vector(0 to C_DATA_BITS-1); FIFO_Read : in std_logic; Data_Out : out std_logic_vector(0 to C_DATA_BITS-1); FIFO_Full : out std_logic; Data_Exists : out std_logic; Addr : out std_logic_vector(0 to 3) -- Added Addr as a port ); end entity SRL_FIFO; architecture IMP of SRL_FIFO is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; component SRL16E is -- pragma translate_off generic ( INIT : bit_vector := X"0000" ); -- pragma translate_on port ( CE : in std_logic; D : in std_logic; Clk : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic); end component SRL16E; component LUT4 generic( INIT : bit_vector := X"0000" ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic); end component; component MULT_AND port ( I0 : in std_logic; I1 : in std_logic; LO : out std_logic); end component; component MUXCY_L port ( DI : in std_logic; CI : in std_logic; S : in std_logic; LO : out std_logic); end component; component XORCY port ( LI : in std_logic; CI : in std_logic; O : out std_logic); end component; component FDRE is port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic); end component FDRE; component FDR is port ( Q : out std_logic; C : in std_logic; D : in std_logic; R : in std_logic); end component FDR; signal addr_i : std_logic_vector(0 to 3); signal buffer_Full : std_logic; signal buffer_Empty : std_logic; signal next_Data_Exists : std_logic; signal data_Exists_I : std_logic; signal valid_Write : std_logic; signal hsum_A : std_logic_vector(0 to 3); signal sum_A : std_logic_vector(0 to 3); signal addr_cy : std_logic_vector(0 to 4); begin -- architecture IMP buffer_Full <= '1' when (addr_i = "1111") else '0'; FIFO_Full <= buffer_Full; buffer_Empty <= '1' when (addr_i = "0000") else '0'; next_Data_Exists <= (data_Exists_I and not buffer_Empty) or (buffer_Empty and FIFO_Write) or (data_Exists_I and not FIFO_Read); Data_Exists_DFF : FDR port map ( Q => data_Exists_I, -- [out std_logic] C => Clk, -- [in std_logic] D => next_Data_Exists, -- [in std_logic] R => Reset); -- [in std_logic] Data_Exists <= data_Exists_I; valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full); addr_cy(0) <= valid_Write; Addr_Counters : for I in 0 to 3 generate hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty); MUXCY_L_I : MUXCY_L port map ( DI => addr_i(I), -- [in std_logic] CI => addr_cy(I), -- [in std_logic] S => hsum_A(I), -- [in std_logic] LO => addr_cy(I+1)); -- [out std_logic] XORCY_I : XORCY port map ( LI => hsum_A(I), -- [in std_logic] CI => addr_cy(I), -- [in std_logic] O => sum_A(I)); -- [out std_logic] FDRE_I : FDRE port map ( Q => addr_i(I), -- [out std_logic] C => Clk, -- [in std_logic] CE => data_Exists_I, -- [in std_logic] D => sum_A(I), -- [in std_logic] R => Reset); -- [in std_logic] end generate Addr_Counters; FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate SRL16E_I : SRL16E -- pragma translate_off generic map ( INIT => x"0000") -- pragma translate_on port map ( CE => valid_Write, -- [in std_logic] D => Data_In(I), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => addr_i(0), -- [in std_logic] A1 => addr_i(1), -- [in std_logic] A2 => addr_i(2), -- [in std_logic] A3 => addr_i(3), -- [in std_logic] Q => Data_Out(I)); -- [out std_logic] end generate FIFO_RAM; ------------------------------------------------------------------------------- -- INT_ADDR_PROCESS ------------------------------------------------------------------------------- -- This process assigns the internal address to the output port ------------------------------------------------------------------------------- INT_ADDR_PROCESS:process (addr_i) begin -- process Addr <= addr_i; end process; end architecture IMP; ------------------------------------------------------------------------------- -- axi_bram_ctrl_funcs.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: axi_bram_ctrl_funcs.vhd -- -- Description: Support functions for axi_bram_ctrl library modules. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 2/16/2011 v1.03a -- ~~~~~~ -- Update ECC size on 128-bit data width configuration. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Add MIG functions for Hsiao ECC. -- ^^^^^^ -- JLJ 2/24/2011 v1.03a -- ~~~~~~ -- Add Find_ECC_Size function. -- ^^^^^^ -- JLJ 3/15/2011 v1.03a -- ~~~~~~ -- Add REDUCTION_OR function. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Recode Create_Size_Max with a case statement. -- ^^^^^^ -- JLJ 3/31/2011 v1.03a -- ~~~~~~ -- Add coverage tags. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Remove Family_To_LUT_Size function. -- Remove String_To_Family function. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; package axi_bram_ctrl_funcs is type TARGET_FAMILY_TYPE is ( -- pragma xilinx_rtl_off SPARTAN3, VIRTEX4, VIRTEX5, SPARTAN3E, SPARTAN3A, SPARTAN3AN, SPARTAN3Adsp, SPARTAN6, VIRTEX6, VIRTEX7, KINTEX7, -- pragma xilinx_rtl_on RTL ); -- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE; -- Get the maximum number of inputs to a LUT. -- function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer; function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN; function log2(x : natural) return integer; function Int_ECC_Size (i: integer) return integer; function Find_ECC_Size (i: integer; j: integer) return integer; function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer; function Create_Size_Max (i: integer) return std_logic_vector; function REDUCTION_OR (A: in std_logic_vector) return std_logic; function REDUCTION_XOR (A: in std_logic_vector) return std_logic; function REDUCTION_NOR (A: in std_logic_vector) return std_logic; function BOOLEAN_TO_STD_LOGIC (A: in BOOLEAN) return std_logic; end package axi_bram_ctrl_funcs; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; package body axi_bram_ctrl_funcs is ------------------------------------------------------------------------------- -- Function: Int_ECC_Size -- Purpose: Determine internal size of ECC when enabled. ------------------------------------------------------------------------------- function Int_ECC_Size (i: integer) return integer is begin --coverage off if (i = 32) then return 7; -- 7-bits ECC for 32-bit data -- ECC port size fixed @ 8-bits elsif (i = 64) then return 8; elsif (i = 128) then return 9; -- Hsiao is 9-bits for 128-bit data. else return 0; end if; --coverage on end Int_ECC_Size; ------------------------------------------------------------------------------- -- Function: Find_ECC_Size -- Purpose: Determine external size of ECC signals when enabled. ------------------------------------------------------------------------------- function Find_ECC_Size (i: integer; j: integer) return integer is begin --coverage off if (i = 1) then if (j = 32) then return 8; -- Keep at 8 for port size matchings -- Only 7-bits ECC per 32-bit data elsif (j = 64) then return 8; elsif (j = 128) then return 9; else return 0; end if; else return 0; -- ECC data width = 0 when C_ECC = 0 (disabled) end if; --coverage on end Find_ECC_Size; ------------------------------------------------------------------------------- -- Function: Find_ECC_Full_Bit_Size -- Purpose: Determine external size of ECC signals when enabled in bytes. ------------------------------------------------------------------------------- function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer is begin --coverage off if (i = 1) then if (j = 32) then return 8; elsif (j = 64) then return 8; elsif (j = 128) then return 16; else return 0; end if; else return 0; -- ECC data width = 0 when C_ECC = 0 (disabled) end if; --coverage on end Find_ECC_Full_Bit_Size; ------------------------------------------------------------------------------- -- Function: Create_Size_Max -- Purpose: Create maximum value for AxSIZE based on AXI data bus width. ------------------------------------------------------------------------------- function Create_Size_Max (i: integer) return std_logic_vector is variable size_vector : std_logic_vector (2 downto 0); begin case (i) is when 32 => size_vector := "010"; -- 2h (4 bytes) when 64 => size_vector := "011"; -- 3h (8 bytes) when 128 => size_vector := "100"; -- 4h (16 bytes) when 256 => size_vector := "101"; -- 5h (32 bytes) when 512 => size_vector := "110"; -- 5h (32 bytes) when 1024 => size_vector := "111"; -- 5h (32 bytes) --coverage off when others => size_vector := "000"; -- 0h --coverage on end case; return (size_vector); end function Create_Size_Max; ------------------------------------------------------------------------------- -- Function: REDUCTION_OR -- Purpose: New in v1.03a ------------------------------------------------------------------------------- function REDUCTION_OR (A: in std_logic_vector) return std_logic is variable tmp : std_logic := '0'; begin for i in A'range loop tmp := tmp or A(i); end loop; return tmp; end function REDUCTION_OR; ------------------------------------------------------------------------------- -- Function: REDUCTION_XOR -- Purpose: Derived from MIG v3.7 ecc_gen module for use by Hsiao ECC. -- New in v1.03a ------------------------------------------------------------------------------- function REDUCTION_XOR (A: in std_logic_vector) return std_logic is variable tmp : std_logic := '0'; begin for i in A'range loop tmp := tmp xor A(i); end loop; return tmp; end function REDUCTION_XOR; ------------------------------------------------------------------------------- -- Function: REDUCTION_NOR -- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC. -- New in v1.03a ------------------------------------------------------------------------------- function REDUCTION_NOR (A: in std_logic_vector) return std_logic is variable tmp : std_logic := '0'; begin for i in A'range loop tmp := tmp or A(i); end loop; return not tmp; end function REDUCTION_NOR; ------------------------------------------------------------------------------- -- Function: BOOLEAN_TO_STD_LOGIC -- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC. -- New in v1.03a ------------------------------------------------------------------------------- function BOOLEAN_TO_STD_LOGIC (A : in BOOLEAN) return std_logic is begin if A = true then return '1'; else return '0'; end if; end function BOOLEAN_TO_STD_LOGIC; ------------------------------------------------------------------------------- function LowerCase_Char(char : character) return character is begin --coverage off -- If char is not an upper case letter then return char if char < 'A' or char > 'Z' then return char; end if; -- Otherwise map char to its corresponding lower case character and -- return that case char is when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd'; when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h'; when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l'; when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p'; when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't'; when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x'; when 'Y' => return 'y'; when 'Z' => return 'z'; when others => return char; end case; --coverage on end LowerCase_Char; ------------------------------------------------------------------------------- -- Returns true if case insensitive string comparison determines that -- str1 and str2 are equal function Equal_String ( str1, str2 : STRING ) RETURN BOOLEAN IS CONSTANT len1 : INTEGER := str1'length; CONSTANT len2 : INTEGER := str2'length; VARIABLE equal : BOOLEAN := TRUE; BEGIN --coverage off IF NOT (len1=len2) THEN equal := FALSE; ELSE FOR i IN str1'range LOOP IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN equal := FALSE; END IF; END LOOP; END IF; --coverage on RETURN equal; END Equal_String; ------------------------------------------------------------------------------- -- Remove usage of C_FAMILY. -- Remove usage of String_To_Family function. -- -- -- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is -- begin -- function String_To_Family -- -- --coverage off -- -- if ((Select_RTL) or Equal_String(S, "rtl")) then -- return RTL; -- elsif Equal_String(S, "spartan3") or Equal_String(S, "aspartan3") then -- return SPARTAN3; -- elsif Equal_String(S, "spartan3E") or Equal_String(S, "aspartan3E") then -- return SPARTAN3E; -- elsif Equal_String(S, "spartan3A") or Equal_String(S, "aspartan3A") then -- return SPARTAN3A; -- elsif Equal_String(S, "spartan3AN") then -- return SPARTAN3AN; -- elsif Equal_String(S, "spartan3Adsp") or Equal_String(S, "aspartan3Adsp") then -- return SPARTAN3Adsp; -- elsif Equal_String(S, "spartan6") or Equal_String(S, "spartan6l") or -- Equal_String(S, "qspartan6") or Equal_String(S, "aspartan6") or Equal_String(S, "qspartan6l") then -- return SPARTAN6; -- elsif Equal_String(S, "virtex4") or Equal_String(S, "qvirtex4") -- or Equal_String(S, "qrvirtex4") then -- return VIRTEX4; -- elsif Equal_String(S, "virtex5") or Equal_String(S, "qrvirtex5") then -- return VIRTEX5; -- elsif Equal_String(S, "virtex6") or Equal_String(S, "virtex6l") or Equal_String(S, "qvirtex6") then -- return VIRTEX6; -- elsif Equal_String(S, "virtex7") then -- return VIRTEX7; -- elsif Equal_String(S, "kintex7") then -- return KINTEX7; -- -- --coverage on -- -- else -- -- assert (false) report "No known target family" severity failure; -- return RTL; -- end if; -- -- end function String_To_Family; ------------------------------------------------------------------------------- -- Remove usage of C_FAMILY. -- Remove usage of Family_To_LUT_Size function. -- -- function Family_To_LUT_Size (Family : TARGET_FAMILY_TYPE) return integer is -- begin -- -- --coverage off -- -- if (Family = SPARTAN3) or (Family = SPARTAN3E) or (Family = SPARTAN3A) or -- (Family = SPARTAN3AN) or (Family = SPARTAN3Adsp) or (Family = VIRTEX4) then -- return 4; -- end if; -- -- return 6; -- -- --coverage on -- -- end function Family_To_LUT_Size; ------------------------------------------------------------------------------- -- Function log2 -- returns number of bits needed to encode x choices -- x = 0 returns 0 -- x = 1 returns 0 -- x = 2 returns 1 -- x = 4 returns 2, etc. ------------------------------------------------------------------------------- function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin --coverage off if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val*2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; --coverage on end function log2; ------------------------------------------------------------------------------- end package body axi_bram_ctrl_funcs; ------------------------------------------------------------------------------- -- coregen_comp_defs - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the user’s sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: coregen_comp_defs.vhd -- Version: initial -- Description: -- Component declarations for all black box netlists generated by -- running COREGEN and AXI BRAM CTRL when XST elaborated the client core -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- coregen_comp_defs.vhd ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; PACKAGE coregen_comp_defs IS ------------------------------------------------------------------------------------- -- Start Block Memory Generator Component for blk_mem_gen_v8_3_6 -- Component declaration for blk_mem_gen_v8_3_6 pulled from the blk_mem_gen_v8_3_6.v -- Verilog file used to match paramter order for NCSIM compatibility ------------------------------------------------------------------------------------- component blk_mem_gen_v8_3_6 generic ( ---------------------------------------------------------------------------- -- Generic Declarations ---------------------------------------------------------------------------- --Device Family & Elaboration Directory Parameters: C_FAMILY : STRING := "virtex4"; C_XDEVICEFAMILY : STRING := "virtex4"; -- C_ELABORATION_DIR : STRING := ""; C_INTERFACE_TYPE : INTEGER := 0; C_AXI_TYPE : INTEGER := 1; C_AXI_SLAVE_TYPE : INTEGER := 0; C_HAS_AXI_ID : INTEGER := 0; C_AXI_ID_WIDTH : INTEGER := 4; --General Memory Parameters: C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 9; C_ALGORITHM : INTEGER := 0; C_PRIM_TYPE : INTEGER := 3; --Memory Initialization Parameters: C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := "111111111"; C_RST_TYPE : STRING := "SYNC"; --Port A Parameters: --Reset Parameters: C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := "0"; --Enable Parameters: C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; --Byte Write Enable Parameters: C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; --Write Mode: C_WRITE_MODE_A : STRING := "WRITE_FIRST"; --Data-Addr Width Parameters: C_WRITE_WIDTH_A : INTEGER := 4; C_READ_WIDTH_A : INTEGER := 4; C_WRITE_DEPTH_A : INTEGER := 4096; C_READ_DEPTH_A : INTEGER := 4096; C_ADDRA_WIDTH : INTEGER := 12; --Port B Parameters: --Reset Parameters: C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := "0"; --Enable Parameters: C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; --Byte Write Enable Parameters: C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; --Write Mode: C_WRITE_MODE_B : STRING := "WRITE_FIRST"; --Data-Addr Width Parameters: C_WRITE_WIDTH_B : INTEGER := 4; C_READ_WIDTH_B : INTEGER := 4; C_WRITE_DEPTH_B : INTEGER := 4096; C_READ_DEPTH_B : INTEGER := 4096; C_ADDRB_WIDTH : INTEGER := 12; --Output Registers/ Pipelining Parameters: C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; --Input/Output Registers for SoftECC : C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; --ECC Parameters C_USE_ECC : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; --Simulation Model Parameters: C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 0; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( ---------------------------------------------------------------------------- -- Input and Output Declarations ---------------------------------------------------------------------------- -- Native BMG Input and Output Port Declarations --Port A: CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '0'; REGCEA : IN STD_LOGIC := '0'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); --Port B: CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '0'; REGCEB : IN STD_LOGIC := '0'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); --ECC: INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); -- AXI BMG Input and Output Port Declarations -- AXI Global Signals S_AClk : IN STD_LOGIC := '0'; S_ARESETN : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Write (write side) S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN STD_LOGIC := '0'; S_AXI_AWREADY : OUT STD_LOGIC; S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WLAST : IN STD_LOGIC := '0'; S_AXI_WVALID : IN STD_LOGIC := '0'; S_AXI_WREADY : OUT STD_LOGIC; S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Read (Write side) S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN STD_LOGIC := '0'; S_AXI_ARREADY : OUT STD_LOGIC; S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); S_AXI_RLAST : OUT STD_LOGIC; S_AXI_RVALID : OUT STD_LOGIC; S_AXI_RREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Sideband Signals S_AXI_INJECTSBITERR : IN STD_LOGIC := '0'; S_AXI_INJECTDBITERR : IN STD_LOGIC := '0'; S_AXI_SBITERR : OUT STD_LOGIC; S_AXI_DBITERR : OUT STD_LOGIC; S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END COMPONENT; --blk_mem_gen_v8_3_6 END coregen_comp_defs; ------------------------------------------------------------------------------- -- axi_lite_if.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_lite_if.vhd -- -- Description: Derived AXI-Lite interface module. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity axi_lite_if is generic ( -- AXI4-Lite slave generics -- C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF"; -- C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000"; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_DATA_WIDTH : integer := 32; C_REGADDR_WIDTH : integer := 4; -- Address bits including register offset. C_DWIDTH : integer := 32); -- Width of data bus. port ( LMB_Clk : in std_logic; LMB_Rst : in std_logic; -- AXI4-Lite SLAVE SINGLE INTERFACE S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- lmb_bram_if_cntlr signals RegWr : out std_logic; RegWrData : out std_logic_vector(0 to C_DWIDTH - 1); RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1); RegRdData : in std_logic_vector(0 to C_DWIDTH - 1)); end entity axi_lite_if; library unisim; use unisim.vcomponents.all; architecture IMP of axi_lite_if is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ----------------------------------------------------------------------------- -- Signal declaration ----------------------------------------------------------------------------- signal new_write_access : std_logic; signal new_read_access : std_logic; signal ongoing_write : std_logic; signal ongoing_read : std_logic; signal S_AXI_RVALID_i : std_logic; signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0); begin -- architecture IMP ----------------------------------------------------------------------------- -- Handling the AXI4-Lite bus interface (AR/AW/W) ----------------------------------------------------------------------------- -- Detect new transaction. -- Only allow one access at a time new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID; new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access; -- Acknowledge new transaction. S_AXI_AWREADY <= new_write_access; S_AXI_WREADY <= new_write_access; S_AXI_ARREADY <= new_read_access; -- Store register address and write data Reg: process (LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then RegAddr <= (others => '0'); RegWrData <= (others => '0'); elsif new_write_access = '1' then RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2); RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0); elsif new_read_access = '1' then RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2); end if; end if; end process Reg; -- Handle write access. WriteAccess: process (LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then ongoing_write <= '0'; elsif new_write_access = '1' then ongoing_write <= '1'; elsif ongoing_write = '1' and S_AXI_BREADY = '1' then ongoing_write <= '0'; end if; RegWr <= new_write_access; end if; end process WriteAccess; S_AXI_BVALID <= ongoing_write; S_AXI_BRESP <= (others => '0'); -- Handle read access ReadAccess: process (LMB_Clk) is begin if LMB_Clk'event and LMB_Clk = '1' then if LMB_Rst = '1' then ongoing_read <= '0'; S_AXI_RVALID_i <= '0'; elsif new_read_access = '1' then ongoing_read <= '1'; S_AXI_RVALID_i <= '0'; elsif ongoing_read = '1' then if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then ongoing_read <= '0'; S_AXI_RVALID_i <= '0'; else S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA end if; end if; end if; end process ReadAccess; S_AXI_RVALID <= S_AXI_RVALID_i; S_AXI_RRESP <= (others => '0'); Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate begin S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0'); end generate Not_All_Bits_Are_Used; RegRdData_i <= RegRdData; -- Swap to - downto S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate begin S_AXI_RDATA_FDRE : FDRE port map ( Q => S_AXI_RDATA(I), C => LMB_Clk, CE => ongoing_read, D => RegRdData_i(I), R => LMB_Rst); end generate S_AXI_RDATA_DFF; end architecture IMP; ------------------------------------------------------------------------------- -- checkbit_handler_64.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: checkbit_handler_64.vhd -- -- Description: Generates the ECC checkbits for the input vector of -- 64-bit data widths. -- -- VHDL-Standard: VHDL'93/02 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity checkbit_handler_64 is generic ( C_ENCODE : boolean := true; C_REG : boolean := false; C_USE_LUT6 : boolean := true); port ( Clk : in std_logic; DataIn : in std_logic_vector (63 downto 0); CheckIn : in std_logic_vector (7 downto 0); CheckOut : out std_logic_vector (7 downto 0); Syndrome : out std_logic_vector (7 downto 0); Syndrome_7 : out std_logic_vector (11 downto 0); Syndrome_Chk : in std_logic_vector (0 to 7); Enable_ECC : in std_logic; UE_Q : in std_logic; CE_Q : in std_logic; UE : out std_logic; CE : out std_logic ); end entity checkbit_handler_64; library unisim; use unisim.vcomponents.all; -- library axi_bram_ctrl_v1_02_a; -- use axi_bram_ctrl_v1_02_a.all; architecture IMP of checkbit_handler_64 is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; component XOR18 is generic ( C_USE_LUT6 : boolean); port ( InA : in std_logic_vector(0 to 17); res : out std_logic); end component XOR18; component Parity is generic ( C_USE_LUT6 : boolean; C_SIZE : integer); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Res : out std_logic); end component Parity; -- component ParityEnable -- generic ( -- C_USE_LUT6 : boolean; -- C_SIZE : integer); -- port ( -- InA : in std_logic_vector(0 to C_SIZE - 1); -- Enable : in std_logic; -- Res : out std_logic); -- end component ParityEnable; signal data_chk0 : std_logic_vector(0 to 34); signal data_chk1 : std_logic_vector(0 to 34); signal data_chk2 : std_logic_vector(0 to 34); signal data_chk3 : std_logic_vector(0 to 30); signal data_chk4 : std_logic_vector(0 to 30); signal data_chk5 : std_logic_vector(0 to 30); signal data_chk6 : std_logic_vector(0 to 6); signal data_chk6_xor : std_logic; -- signal data_chk7_a : std_logic_vector(0 to 17); -- signal data_chk7_b : std_logic_vector(0 to 17); -- signal data_chk7_i : std_logic; -- signal data_chk7_xor : std_logic; -- signal data_chk7_i_xor : std_logic; -- signal data_chk7_a_xor : std_logic; -- signal data_chk7_b_xor : std_logic; begin -- architecture IMP -- Add bits for 64-bit ECC -- 0 <= 0 1 3 4 6 8 10 11 13 17 19 21 23 25 26 28 30 -- 32 34 36 38 40 42 44 46 48 50 52 54 56 57 59 61 63 data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) & DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) & DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30) & DataIn(32) & DataIn(34) & DataIn(36) & DataIn(38) & DataIn(40) & DataIn(42) & DataIn(44) & DataIn(46) & DataIn(48) & DataIn(50) & DataIn(52) & DataIn(54) & DataIn(56) & DataIn(57) & DataIn(59) & DataIn(61) & DataIn(63) ; -- 18 + 17 = 35 --------------------------------------------------------------------------- -- 1 <= 0 2 3 5 6 9 10 12 13 16 17 20 21 24 25 27 28 31 -- 32 35 36 39 40 43 44 47 48 51 52 55 56 58 59 62 63 data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) & DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) & DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31) & DataIn(32) & DataIn(35) & DataIn(36) & DataIn(39) & DataIn(40) & DataIn(43) & DataIn(44) & DataIn(47) & DataIn(48) & DataIn(51) & DataIn(52) & DataIn(55) & DataIn(56) & DataIn(58) & DataIn(59) & DataIn(62) & DataIn(63) ; -- 18 + 17 = 35 --------------------------------------------------------------------------- -- 2 <= 1 2 3 7 8 9 10 14 15 16 17 22 23 24 25 29 30 31 -- 32 37 38 39 40 45 46 47 48 53 54 55 56 60 61 62 63 data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31) & DataIn(32) & DataIn(37) & DataIn(38) & DataIn(39) & DataIn(40) & DataIn(45) & DataIn(46) & DataIn(47) & DataIn(48) & DataIn(53) & DataIn(54) & DataIn(55) & DataIn(56) & DataIn(60) & DataIn(61) & DataIn(62) & DataIn(63) ; -- 18 + 17 = 35 --------------------------------------------------------------------------- -- 3 <= 4 5 6 7 8 9 10 18 19 20 21 22 23 24 25 -- 33 34 35 36 37 38 39 40 49 50 51 52 53 54 55 56 data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) & DataIn(38) & DataIn(39) & DataIn(40) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) & DataIn(55) & DataIn(56) ; -- 15 + 16 = 31 --------------------------------------------------------------------------- -- 4 <= 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 -- 41-56 data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(41) & DataIn(42) & DataIn(43) & DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) & DataIn(48) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) & DataIn(55) & DataIn(56) ; -- 15 + 16 = 31 --------------------------------------------------------------------------- -- 5 <= 26 - 31 -- 32 - 56 data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31) & DataIn(32) & DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) & DataIn(38) & DataIn(39) & DataIn(40) & DataIn(41) & DataIn(42) & DataIn(43) & DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) & DataIn(48) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) & DataIn(55) & DataIn(56) ; -- 18 + 13 = 31 --------------------------------------------------------------------------- -- New additional checkbit for 64-bit data -- 6 <= 57 - 63 data_chk6 <= DataIn(57) & DataIn(58) & DataIn(59) & DataIn(60) & DataIn(61) & DataIn(62) & DataIn(63) ; -- Encode bits for writing data Encode_Bits : if (C_ENCODE) generate -- signal data_chk0_i : std_logic_vector(0 to 17); -- signal data_chk0_xor : std_logic; -- signal data_chk0_i_xor : std_logic; -- signal data_chk1_i : std_logic_vector(0 to 17); -- signal data_chk1_xor : std_logic; -- signal data_chk1_i_xor : std_logic; -- signal data_chk2_i : std_logic_vector(0 to 17); -- signal data_chk2_xor : std_logic; -- signal data_chk2_i_xor : std_logic; -- signal data_chk3_i : std_logic_vector(0 to 17); -- signal data_chk3_xor : std_logic; -- signal data_chk3_i_xor : std_logic; -- signal data_chk4_i : std_logic_vector(0 to 17); -- signal data_chk4_xor : std_logic; -- signal data_chk4_i_xor : std_logic; -- signal data_chk5_i : std_logic_vector(0 to 17); -- signal data_chk5_xor : std_logic; -- signal data_chk5_i_xor : std_logic; -- signal data_chk6_i : std_logic; -- signal data_chk0_xor_reg : std_logic; -- signal data_chk0_i_xor_reg : std_logic; -- signal data_chk1_xor_reg : std_logic; -- signal data_chk1_i_xor_reg : std_logic; -- signal data_chk2_xor_reg : std_logic; -- signal data_chk2_i_xor_reg : std_logic; -- signal data_chk3_xor_reg : std_logic; -- signal data_chk3_i_xor_reg : std_logic; -- signal data_chk4_xor_reg : std_logic; -- signal data_chk4_i_xor_reg : std_logic; -- signal data_chk5_xor_reg : std_logic; -- signal data_chk5_i_xor_reg : std_logic; -- signal data_chk6_i_reg : std_logic; -- signal data_chk7_a_xor_reg : std_logic; -- signal data_chk7_b_xor_reg : std_logic; -- Checkbit (0) signal data_chk0_a : std_logic_vector (0 to 5); signal data_chk0_b : std_logic_vector (0 to 5); signal data_chk0_c : std_logic_vector (0 to 5); signal data_chk0_d : std_logic_vector (0 to 5); signal data_chk0_e : std_logic_vector (0 to 5); signal data_chk0_f : std_logic_vector (0 to 4); signal data_chk0_a_xor : std_logic; signal data_chk0_b_xor : std_logic; signal data_chk0_c_xor : std_logic; signal data_chk0_d_xor : std_logic; signal data_chk0_e_xor : std_logic; signal data_chk0_f_xor : std_logic; signal data_chk0_a_xor_reg : std_logic; signal data_chk0_b_xor_reg : std_logic; signal data_chk0_c_xor_reg : std_logic; signal data_chk0_d_xor_reg : std_logic; signal data_chk0_e_xor_reg : std_logic; signal data_chk0_f_xor_reg : std_logic; -- Checkbit (1) signal data_chk1_a : std_logic_vector (0 to 5); signal data_chk1_b : std_logic_vector (0 to 5); signal data_chk1_c : std_logic_vector (0 to 5); signal data_chk1_d : std_logic_vector (0 to 5); signal data_chk1_e : std_logic_vector (0 to 5); signal data_chk1_f : std_logic_vector (0 to 4); signal data_chk1_a_xor : std_logic; signal data_chk1_b_xor : std_logic; signal data_chk1_c_xor : std_logic; signal data_chk1_d_xor : std_logic; signal data_chk1_e_xor : std_logic; signal data_chk1_f_xor : std_logic; signal data_chk1_a_xor_reg : std_logic; signal data_chk1_b_xor_reg : std_logic; signal data_chk1_c_xor_reg : std_logic; signal data_chk1_d_xor_reg : std_logic; signal data_chk1_e_xor_reg : std_logic; signal data_chk1_f_xor_reg : std_logic; -- Checkbit (2) signal data_chk2_a : std_logic_vector (0 to 5); signal data_chk2_b : std_logic_vector (0 to 5); signal data_chk2_c : std_logic_vector (0 to 5); signal data_chk2_d : std_logic_vector (0 to 5); signal data_chk2_e : std_logic_vector (0 to 5); signal data_chk2_f : std_logic_vector (0 to 4); signal data_chk2_a_xor : std_logic; signal data_chk2_b_xor : std_logic; signal data_chk2_c_xor : std_logic; signal data_chk2_d_xor : std_logic; signal data_chk2_e_xor : std_logic; signal data_chk2_f_xor : std_logic; signal data_chk2_a_xor_reg : std_logic; signal data_chk2_b_xor_reg : std_logic; signal data_chk2_c_xor_reg : std_logic; signal data_chk2_d_xor_reg : std_logic; signal data_chk2_e_xor_reg : std_logic; signal data_chk2_f_xor_reg : std_logic; -- Checkbit (3) signal data_chk3_a : std_logic_vector (0 to 5); signal data_chk3_b : std_logic_vector (0 to 5); signal data_chk3_c : std_logic_vector (0 to 5); signal data_chk3_d : std_logic_vector (0 to 5); signal data_chk3_e : std_logic_vector (0 to 5); signal data_chk3_a_xor : std_logic; signal data_chk3_b_xor : std_logic; signal data_chk3_c_xor : std_logic; signal data_chk3_d_xor : std_logic; signal data_chk3_e_xor : std_logic; signal data_chk3_f_xor : std_logic; signal data_chk3_a_xor_reg : std_logic; signal data_chk3_b_xor_reg : std_logic; signal data_chk3_c_xor_reg : std_logic; signal data_chk3_d_xor_reg : std_logic; signal data_chk3_e_xor_reg : std_logic; signal data_chk3_f_xor_reg : std_logic; -- Checkbit (4) signal data_chk4_a : std_logic_vector (0 to 5); signal data_chk4_b : std_logic_vector (0 to 5); signal data_chk4_c : std_logic_vector (0 to 5); signal data_chk4_d : std_logic_vector (0 to 5); signal data_chk4_e : std_logic_vector (0 to 5); signal data_chk4_a_xor : std_logic; signal data_chk4_b_xor : std_logic; signal data_chk4_c_xor : std_logic; signal data_chk4_d_xor : std_logic; signal data_chk4_e_xor : std_logic; signal data_chk4_f_xor : std_logic; signal data_chk4_a_xor_reg : std_logic; signal data_chk4_b_xor_reg : std_logic; signal data_chk4_c_xor_reg : std_logic; signal data_chk4_d_xor_reg : std_logic; signal data_chk4_e_xor_reg : std_logic; signal data_chk4_f_xor_reg : std_logic; -- Checkbit (5) signal data_chk5_a : std_logic_vector (0 to 5); signal data_chk5_b : std_logic_vector (0 to 5); signal data_chk5_c : std_logic_vector (0 to 5); signal data_chk5_d : std_logic_vector (0 to 5); signal data_chk5_e : std_logic_vector (0 to 5); signal data_chk5_a_xor : std_logic; signal data_chk5_b_xor : std_logic; signal data_chk5_c_xor : std_logic; signal data_chk5_d_xor : std_logic; signal data_chk5_e_xor : std_logic; signal data_chk5_f_xor : std_logic; signal data_chk5_a_xor_reg : std_logic; signal data_chk5_b_xor_reg : std_logic; signal data_chk5_c_xor_reg : std_logic; signal data_chk5_d_xor_reg : std_logic; signal data_chk5_e_xor_reg : std_logic; signal data_chk5_f_xor_reg : std_logic; -- Checkbit (6) signal data_chk6_a : std_logic; signal data_chk6_b : std_logic; signal data_chk6_a_reg : std_logic; signal data_chk6_b_reg : std_logic; -- Checkbit (7) signal data_chk7_a : std_logic_vector (0 to 5); signal data_chk7_b : std_logic_vector (0 to 5); signal data_chk7_c : std_logic_vector (0 to 5); signal data_chk7_d : std_logic_vector (0 to 5); signal data_chk7_e : std_logic_vector (0 to 5); signal data_chk7_f : std_logic_vector (0 to 4); signal data_chk7_a_xor : std_logic; signal data_chk7_b_xor : std_logic; signal data_chk7_c_xor : std_logic; signal data_chk7_d_xor : std_logic; signal data_chk7_e_xor : std_logic; signal data_chk7_f_xor : std_logic; signal data_chk7_a_xor_reg : std_logic; signal data_chk7_b_xor_reg : std_logic; signal data_chk7_c_xor_reg : std_logic; signal data_chk7_d_xor_reg : std_logic; signal data_chk7_e_xor_reg : std_logic; signal data_chk7_f_xor_reg : std_logic; begin ----------------------------------------------------------------------------- -- For timing improvements, if check bit XOR logic -- needs to be pipelined. Add register level here -- after 1st LUT level. REG_BITS : if (C_REG) generate begin REG_CHK: process (Clk) begin if (Clk'event and Clk = '1' ) then -- Checkbit (0) -- data_chk0_xor_reg <= data_chk0_xor; -- data_chk0_i_xor_reg <= data_chk0_i_xor; data_chk0_a_xor_reg <= data_chk0_a_xor; data_chk0_b_xor_reg <= data_chk0_b_xor; data_chk0_c_xor_reg <= data_chk0_c_xor; data_chk0_d_xor_reg <= data_chk0_d_xor; data_chk0_e_xor_reg <= data_chk0_e_xor; data_chk0_f_xor_reg <= data_chk0_f_xor; -- Checkbit (1) -- data_chk1_xor_reg <= data_chk1_xor; -- data_chk1_i_xor_reg <= data_chk1_i_xor; data_chk1_a_xor_reg <= data_chk1_a_xor; data_chk1_b_xor_reg <= data_chk1_b_xor; data_chk1_c_xor_reg <= data_chk1_c_xor; data_chk1_d_xor_reg <= data_chk1_d_xor; data_chk1_e_xor_reg <= data_chk1_e_xor; data_chk1_f_xor_reg <= data_chk1_f_xor; -- Checkbit (2) -- data_chk2_xor_reg <= data_chk2_xor; -- data_chk2_i_xor_reg <= data_chk2_i_xor; data_chk2_a_xor_reg <= data_chk2_a_xor; data_chk2_b_xor_reg <= data_chk2_b_xor; data_chk2_c_xor_reg <= data_chk2_c_xor; data_chk2_d_xor_reg <= data_chk2_d_xor; data_chk2_e_xor_reg <= data_chk2_e_xor; data_chk2_f_xor_reg <= data_chk2_f_xor; -- Checkbit (3) -- data_chk3_xor_reg <= data_chk3_xor; -- data_chk3_i_xor_reg <= data_chk3_i_xor; data_chk3_a_xor_reg <= data_chk3_a_xor; data_chk3_b_xor_reg <= data_chk3_b_xor; data_chk3_c_xor_reg <= data_chk3_c_xor; data_chk3_d_xor_reg <= data_chk3_d_xor; data_chk3_e_xor_reg <= data_chk3_e_xor; data_chk3_f_xor_reg <= data_chk3_f_xor; -- Checkbit (4) -- data_chk4_xor_reg <= data_chk4_xor; -- data_chk4_i_xor_reg <= data_chk4_i_xor; data_chk4_a_xor_reg <= data_chk4_a_xor; data_chk4_b_xor_reg <= data_chk4_b_xor; data_chk4_c_xor_reg <= data_chk4_c_xor; data_chk4_d_xor_reg <= data_chk4_d_xor; data_chk4_e_xor_reg <= data_chk4_e_xor; data_chk4_f_xor_reg <= data_chk4_f_xor; -- Checkbit (5) -- data_chk5_xor_reg <= data_chk5_xor; -- data_chk5_i_xor_reg <= data_chk5_i_xor; data_chk5_a_xor_reg <= data_chk5_a_xor; data_chk5_b_xor_reg <= data_chk5_b_xor; data_chk5_c_xor_reg <= data_chk5_c_xor; data_chk5_d_xor_reg <= data_chk5_d_xor; data_chk5_e_xor_reg <= data_chk5_e_xor; data_chk5_f_xor_reg <= data_chk5_f_xor; -- Checkbit (6) -- data_chk6_i_reg <= data_chk6_i; data_chk6_a_reg <= data_chk6_a; data_chk6_b_reg <= data_chk6_b; -- Checkbit (7) -- data_chk7_a_xor_reg <= data_chk7_a_xor; -- data_chk7_b_xor_reg <= data_chk7_b_xor; data_chk7_a_xor_reg <= data_chk7_a_xor; data_chk7_b_xor_reg <= data_chk7_b_xor; data_chk7_c_xor_reg <= data_chk7_c_xor; data_chk7_d_xor_reg <= data_chk7_d_xor; data_chk7_e_xor_reg <= data_chk7_e_xor; data_chk7_f_xor_reg <= data_chk7_f_xor; end if; end process REG_CHK; -- Perform the last XOR after the register stage -- CheckOut(0) <= data_chk0_xor_reg xor data_chk0_i_xor_reg; CheckOut(0) <= data_chk0_a_xor_reg xor data_chk0_b_xor_reg xor data_chk0_c_xor_reg xor data_chk0_d_xor_reg xor data_chk0_e_xor_reg xor data_chk0_f_xor_reg; -- CheckOut(1) <= data_chk1_xor_reg xor data_chk1_i_xor_reg; CheckOut(1) <= data_chk1_a_xor_reg xor data_chk1_b_xor_reg xor data_chk1_c_xor_reg xor data_chk1_d_xor_reg xor data_chk1_e_xor_reg xor data_chk1_f_xor_reg; -- CheckOut(2) <= data_chk2_xor_reg xor data_chk2_i_xor_reg; CheckOut(2) <= data_chk2_a_xor_reg xor data_chk2_b_xor_reg xor data_chk2_c_xor_reg xor data_chk2_d_xor_reg xor data_chk2_e_xor_reg xor data_chk2_f_xor_reg; -- CheckOut(3) <= data_chk3_xor_reg xor data_chk3_i_xor_reg; CheckOut(3) <= data_chk3_a_xor_reg xor data_chk3_b_xor_reg xor data_chk3_c_xor_reg xor data_chk3_d_xor_reg xor data_chk3_e_xor_reg xor data_chk3_f_xor_reg; -- CheckOut(4) <= data_chk4_xor_reg xor data_chk4_i_xor_reg; CheckOut(4) <= data_chk4_a_xor_reg xor data_chk4_b_xor_reg xor data_chk4_c_xor_reg xor data_chk4_d_xor_reg xor data_chk4_e_xor_reg xor data_chk4_f_xor_reg; -- CheckOut(5) <= data_chk5_xor_reg xor data_chk5_i_xor_reg; CheckOut(5) <= data_chk5_a_xor_reg xor data_chk5_b_xor_reg xor data_chk5_c_xor_reg xor data_chk5_d_xor_reg xor data_chk5_e_xor_reg xor data_chk5_f_xor_reg; -- CheckOut(6) <= data_chk6_i_reg; CheckOut(6) <= data_chk6_a_reg xor data_chk6_b_reg; -- CheckOut(7) <= data_chk7_a_xor_reg xor data_chk7_b_xor_reg; CheckOut(7) <= data_chk7_a_xor_reg xor data_chk7_b_xor_reg xor data_chk7_c_xor_reg xor data_chk7_d_xor_reg xor data_chk7_e_xor_reg xor data_chk7_f_xor_reg; end generate REG_BITS; NO_REG_BITS: if (not C_REG) generate begin -- CheckOut(0) <= data_chk0_xor xor data_chk0_i_xor; CheckOut(0) <= data_chk0_a_xor xor data_chk0_b_xor xor data_chk0_c_xor xor data_chk0_d_xor xor data_chk0_e_xor xor data_chk0_f_xor; -- CheckOut(1) <= data_chk1_xor xor data_chk1_i_xor; CheckOut(1) <= data_chk1_a_xor xor data_chk1_b_xor xor data_chk1_c_xor xor data_chk1_d_xor xor data_chk1_e_xor xor data_chk1_f_xor; -- CheckOut(2) <= data_chk2_xor xor data_chk2_i_xor; CheckOut(2) <= data_chk2_a_xor xor data_chk2_b_xor xor data_chk2_c_xor xor data_chk2_d_xor xor data_chk2_e_xor xor data_chk2_f_xor; -- CheckOut(3) <= data_chk3_xor xor data_chk3_i_xor; CheckOut(3) <= data_chk3_a_xor xor data_chk3_b_xor xor data_chk3_c_xor xor data_chk3_d_xor xor data_chk3_e_xor xor data_chk3_f_xor; -- CheckOut(4) <= data_chk4_xor xor data_chk4_i_xor; CheckOut(4) <= data_chk4_a_xor xor data_chk4_b_xor xor data_chk4_c_xor xor data_chk4_d_xor xor data_chk4_e_xor xor data_chk4_f_xor; -- CheckOut(5) <= data_chk5_xor xor data_chk5_i_xor; CheckOut(5) <= data_chk5_a_xor xor data_chk5_b_xor xor data_chk5_c_xor xor data_chk5_d_xor xor data_chk5_e_xor xor data_chk5_f_xor; -- CheckOut(6) <= data_chk6_i; CheckOut(6) <= data_chk6_a xor data_chk6_b; -- CheckOut(7) <= data_chk7_a_xor xor data_chk7_b_xor; CheckOut(7) <= data_chk7_a_xor xor data_chk7_b_xor xor data_chk7_c_xor xor data_chk7_d_xor xor data_chk7_e_xor xor data_chk7_f_xor; end generate NO_REG_BITS; ----------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Checkbit 0 built up using 2x XOR18 ------------------------------------------------------------------------------- -- XOR18_I0_A : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk0 (0 to 17), -- [in std_logic_vector(0 to 17)] -- res => data_chk0_xor); -- [out std_logic] -- -- data_chk0_i <= data_chk0 (18 to 34) & '0'; -- -- XOR18_I0_B : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk0_i, -- [in std_logic_vector(0 to 17)] -- res => data_chk0_i_xor); -- [out std_logic] -- -- -- CheckOut(0) <= data_chk0_xor xor data_chk0_i_xor; -- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG) data_chk0_a <= data_chk0 (0 to 5); data_chk0_b <= data_chk0 (6 to 11); data_chk0_c <= data_chk0 (12 to 17); data_chk0_d <= data_chk0 (18 to 23); data_chk0_e <= data_chk0 (24 to 29); data_chk0_f <= data_chk0 (30 to 34); PARITY_CHK0_A : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk0_a_xor ); -- [out std_logic] PARITY_CHK0_B : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk0_b_xor ); -- [out std_logic] PARITY_CHK0_C : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk0_c_xor ); -- [out std_logic] PARITY_CHK0_D : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk0_d_xor ); -- [out std_logic] PARITY_CHK0_E : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk0_e_xor ); -- [out std_logic] PARITY_CHK0_F : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5) port map ( InA => data_chk0_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk0_f_xor ); -- [out std_logic] ------------------------------------------------------------------------------- -- Checkbit 1 built up using 2x XOR18 ------------------------------------------------------------------------------- -- XOR18_I1_A : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk1 (0 to 17), -- [in std_logic_vector(0 to 17)] -- res => data_chk1_xor); -- [out std_logic] -- -- data_chk1_i <= data_chk1 (18 to 34) & '0'; -- -- XOR18_I1_B : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk1_i, -- [in std_logic_vector(0 to 17)] -- res => data_chk1_i_xor); -- [out std_logic] -- -- -- CheckOut(1) <= data_chk1_xor xor data_chk1_i_xor; -- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG) data_chk1_a <= data_chk1 (0 to 5); data_chk1_b <= data_chk1 (6 to 11); data_chk1_c <= data_chk1 (12 to 17); data_chk1_d <= data_chk1 (18 to 23); data_chk1_e <= data_chk1 (24 to 29); data_chk1_f <= data_chk1 (30 to 34); PARITY_chk1_A : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk1_a_xor ); -- [out std_logic] PARITY_chk1_B : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk1_b_xor ); -- [out std_logic] PARITY_chk1_C : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk1_c_xor ); -- [out std_logic] PARITY_chk1_D : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk1_d_xor ); -- [out std_logic] PARITY_chk1_E : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk1_e_xor ); -- [out std_logic] PARITY_chk1_F : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5) port map ( InA => data_chk1_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk1_f_xor ); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 2 built up using 2x XOR18 ------------------------------------------------------------------------------------------------ -- XOR18_I2_A : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk2 (0 to 17), -- [in std_logic_vector(0 to 17)] -- res => data_chk2_xor); -- [out std_logic] -- -- data_chk2_i <= data_chk2 (18 to 34) & '0'; -- -- XOR18_I2_B : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk2_i, -- [in std_logic_vector(0 to 17)] -- res => data_chk2_i_xor); -- [out std_logic] -- -- -- CheckOut(2) <= data_chk2_xor xor data_chk2_i_xor; -- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG) data_chk2_a <= data_chk2 (0 to 5); data_chk2_b <= data_chk2 (6 to 11); data_chk2_c <= data_chk2 (12 to 17); data_chk2_d <= data_chk2 (18 to 23); data_chk2_e <= data_chk2 (24 to 29); data_chk2_f <= data_chk2 (30 to 34); PARITY_chk2_A : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk2_a_xor ); -- [out std_logic] PARITY_chk2_B : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk2_b_xor ); -- [out std_logic] PARITY_chk2_C : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk2_c_xor ); -- [out std_logic] PARITY_chk2_D : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk2_d_xor ); -- [out std_logic] PARITY_chk2_E : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk2_e_xor ); -- [out std_logic] PARITY_chk2_F : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5) port map ( InA => data_chk2_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk2_f_xor ); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 3 built up using 2x XOR18 ------------------------------------------------------------------------------------------------ -- XOR18_I3_A : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk3 (0 to 17), -- [in std_logic_vector(0 to 17)] -- res => data_chk3_xor); -- [out std_logic] -- -- data_chk3_i <= data_chk3 (18 to 30) & "00000"; -- -- XOR18_I3_B : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk3_i, -- [in std_logic_vector(0 to 17)] -- res => data_chk3_i_xor); -- [out std_logic] -- -- -- CheckOut(3) <= data_chk3_xor xor data_chk3_i_xor; -- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG) data_chk3_a <= data_chk3 (0 to 5); data_chk3_b <= data_chk3 (6 to 11); data_chk3_c <= data_chk3 (12 to 17); data_chk3_d <= data_chk3 (18 to 23); data_chk3_e <= data_chk3 (24 to 29); data_chk3_f_xor <= data_chk3 (30); PARITY_chk3_A : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk3_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk3_a_xor ); -- [out std_logic] PARITY_chk3_B : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk3_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk3_b_xor ); -- [out std_logic] PARITY_chk3_C : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk3_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk3_c_xor ); -- [out std_logic] PARITY_chk3_D : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk3_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk3_d_xor ); -- [out std_logic] PARITY_chk3_E : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk3_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk3_e_xor ); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 4 built up using 2x XOR18 ------------------------------------------------------------------------------------------------ -- XOR18_I4_A : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk4 (0 to 17), -- [in std_logic_vector(0 to 17)] -- res => data_chk4_xor); -- [out std_logic] -- -- data_chk4_i <= data_chk4 (18 to 30) & "00000"; -- -- XOR18_I4_B : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk4_i, -- [in std_logic_vector(0 to 17)] -- res => data_chk4_i_xor); -- [out std_logic] -- -- -- CheckOut(4) <= data_chk4_xor xor data_chk4_i_xor; -- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG) data_chk4_a <= data_chk4 (0 to 5); data_chk4_b <= data_chk4 (6 to 11); data_chk4_c <= data_chk4 (12 to 17); data_chk4_d <= data_chk4 (18 to 23); data_chk4_e <= data_chk4 (24 to 29); data_chk4_f_xor <= data_chk4 (30); PARITY_chk4_A : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk4_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk4_a_xor ); -- [out std_logic] PARITY_chk4_B : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk4_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk4_b_xor ); -- [out std_logic] PARITY_chk4_C : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk4_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk4_c_xor ); -- [out std_logic] PARITY_chk4_D : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk4_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk4_d_xor ); -- [out std_logic] PARITY_chk4_E : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk4_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk4_e_xor ); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 5 built up using 2x XOR18 ------------------------------------------------------------------------------------------------ -- XOR18_I5_A : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk5 (0 to 17), -- [in std_logic_vector(0 to 17)] -- res => data_chk5_xor); -- [out std_logic] -- -- data_chk5_i <= data_chk5 (18 to 30) & "00000"; -- -- XOR18_I5_B : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk5_i, -- [in std_logic_vector(0 to 17)] -- res => data_chk5_i_xor); -- [out std_logic] -- -- -- CheckOut(5) <= data_chk5_xor xor data_chk5_i_xor; -- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG) data_chk5_a <= data_chk5 (0 to 5); data_chk5_b <= data_chk5 (6 to 11); data_chk5_c <= data_chk5 (12 to 17); data_chk5_d <= data_chk5 (18 to 23); data_chk5_e <= data_chk5 (24 to 29); data_chk5_f_xor <= data_chk5 (30); PARITY_chk5_A : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk5_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk5_a_xor ); -- [out std_logic] PARITY_chk5_B : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk5_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk5_b_xor ); -- [out std_logic] PARITY_chk5_C : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk5_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk5_c_xor ); -- [out std_logic] PARITY_chk5_D : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk5_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk5_d_xor ); -- [out std_logic] PARITY_chk5_E : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk5_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk5_e_xor ); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 6 built up from 1 LUT6 + 1 XOR ------------------------------------------------------------------------------------------------ Parity_chk6_I : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6 (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk6_xor); -- [out std_logic] -- data_chk6_i <= data_chk6_xor xor data_chk6(6); -- Push register stage to 1st ECC XOR logic stage (when enabled, C_REG) data_chk6_a <= data_chk6_xor; data_chk6_b <= data_chk6(6); -- CheckOut(6) <= data_chk6_xor xor data_chk6(6); -- CheckOut(6) <= data_chk6_i; -- Overall checkbit -- New checkbit (7) for 64-bit ECC -- 7 <= 0 1 2 4 5 7 10 11 12 14 17 18 21 23 24 26 27 29 -- 32 33 36 38 39 41 44 46 47 50 51 53 56 57 58 60 63 ------------------------------------------------------------------------------------------------ -- Checkbit 6 built up from 2x XOR18 ------------------------------------------------------------------------------------------------ -- data_chk7_a <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) & -- DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) & -- DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29) ; -- -- data_chk7_b <= DataIn(32) & DataIn(33) & DataIn(36) & DataIn(38) & DataIn(39) & -- DataIn(41) & DataIn(44) & DataIn(46) & DataIn(47) & DataIn(50) & -- DataIn(51) & DataIn(53) & DataIn(56) & DataIn(57) & DataIn(58) & -- DataIn(60) & DataIn(63) & '0'; -- -- XOR18_I7_A : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk7_a, -- [in std_logic_vector(0 to 17)] -- res => data_chk7_a_xor); -- [out std_logic] -- -- -- XOR18_I7_B : XOR18 -- generic map ( -- C_USE_LUT6 => C_USE_LUT6) -- [boolean] -- port map ( -- InA => data_chk7_b, -- [in std_logic_vector(0 to 17)] -- res => data_chk7_b_xor); -- [out std_logic] -- Move register stage to earlier in LUT XOR logic when enabled (for C_ENCODE only) -- Break up data_chk7_a & data_chk7_b into the following 6-input LUT XOR combinations. data_chk7_a <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7); data_chk7_b <= DataIn(10) & DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18); data_chk7_c <= DataIn(21) & DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29); data_chk7_d <= DataIn(32) & DataIn(33) & DataIn(36) & DataIn(38) & DataIn(39) & DataIn(41); data_chk7_e <= DataIn(44) & DataIn(46) & DataIn(47) & DataIn(50) & DataIn(51) & DataIn(53); data_chk7_f <= DataIn(56) & DataIn(57) & DataIn(58) & DataIn(60) & DataIn(63); PARITY_CHK7_A : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk7_a_xor ); -- [out std_logic] PARITY_CHK7_B : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk7_b_xor ); -- [out std_logic] PARITY_CHK7_C : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk7_c_xor ); -- [out std_logic] PARITY_CHK7_D : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk7_d_xor ); -- [out std_logic] PARITY_CHK7_E : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk7_e_xor ); -- [out std_logic] PARITY_CHK7_F : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5) port map ( InA => data_chk7_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => data_chk7_f_xor ); -- [out std_logic] -- Merge all data bits -- CheckOut(7) <= data_chk7_xor xor data_chk7_i_xor; -- data_chk7_i <= data_chk7_a_xor xor data_chk7_b_xor; -- CheckOut(7) <= data_chk7_i; end generate Encode_Bits; -------------------------------------------------------------------------------------------------- -- Decode bits to get syndrome and UE/CE signals -------------------------------------------------------------------------------------------------- Decode_Bits : if (not C_ENCODE) generate signal syndrome_i : std_logic_vector(0 to 7) := (others => '0'); -- Unused signal syndrome_int_7 : std_logic; signal chk0_1 : std_logic_vector(0 to 6); signal chk1_1 : std_logic_vector(0 to 6); signal chk2_1 : std_logic_vector(0 to 6); signal data_chk3_i : std_logic_vector(0 to 31); signal chk3_1 : std_logic_vector(0 to 3); signal data_chk4_i : std_logic_vector(0 to 31); signal chk4_1 : std_logic_vector(0 to 3); signal data_chk5_i : std_logic_vector(0 to 31); signal chk5_1 : std_logic_vector(0 to 3); signal data_chk6_i : std_logic_vector(0 to 7); signal data_chk7 : std_logic_vector(0 to 71); signal chk7_1 : std_logic_vector(0 to 11); -- signal syndrome7_a : std_logic; -- signal syndrome7_b : std_logic; signal syndrome_0_to_2 : std_logic_vector(0 to 2); signal syndrome_3_to_6 : std_logic_vector(3 to 6); signal syndrome_3_to_6_multi : std_logic; signal syndrome_3_to_6_zero : std_logic; signal ue_i_0 : std_logic; signal ue_i_1 : std_logic; begin ------------------------------------------------------------------------------------------------ -- Syndrome bit 0 built up from 5 LUT6, 1 LUT5 and 1 7-bit XOR ------------------------------------------------------------------------------------------------ -- chk0_1(3) <= CheckIn(0); chk0_1(6) <= CheckIn(0); -- 64-bit ECC Parity_chk0_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(0)); -- [out std_logic] Parity_chk0_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(1)); -- [out std_logic] Parity_chk0_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(2)); -- [out std_logic] -- Checkbit 0 -- 18-bit for 32-bit data -- 35-bit for 64-bit data Parity_chk0_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(18 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(3)); -- [out std_logic] Parity_chk0_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(24 to 29), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(4)); -- [out std_logic] Parity_chk0_6 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5) port map ( InA => data_chk0(30 to 34), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(5)); -- [out std_logic] -- Parity_chk0_7 : ParityEnable -- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) -- port map ( -- InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)] -- Enable => Enable_ECC, -- [in std_logic] -- Res => syndrome_i(0)); -- [out std_logic] Parity_chk0_7 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(0)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 1 built up from 5 LUT6, 1 LUT5 and 1 7-bit XOR ------------------------------------------------------------------------------------------------ -- chk1_1(3) <= CheckIn(1); chk1_1(6) <= CheckIn(1); -- 64-bit ECC Parity_chk1_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(0)); -- [out std_logic] Parity_chk1_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(1)); -- [out std_logic] Parity_chk1_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(2)); -- [out std_logic] -- Checkbit 1 -- 18-bit for 32-bit data -- 35-bit for 64-bit data Parity_chk1_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(18 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(3)); -- [out std_logic] Parity_chk1_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(24 to 29), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(4)); -- [out std_logic] Parity_chk1_6 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5) port map ( InA => data_chk1(30 to 34), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(5)); -- [out std_logic] -- Parity_chk1_7 : ParityEnable -- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) -- port map ( -- InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)] -- Enable => Enable_ECC, -- [in std_logic] -- Res => syndrome_i(1)); -- [out std_logic] Parity_chk1_7 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(1)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 2 built up from 5 LUT6, 1 LUT5 and 1 7-bit XOR ------------------------------------------------------------------------------------------------ -- chk2_1(3) <= CheckIn(2); chk2_1(6) <= CheckIn(2); -- 64-bit ECC Parity_chk2_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(0)); -- [out std_logic] Parity_chk2_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(1)); -- [out std_logic] Parity_chk2_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(2)); -- [out std_logic] -- Checkbit 2 -- 18-bit for 32-bit data -- 35-bit for 64-bit data Parity_chk2_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(18 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(3)); -- [out std_logic] Parity_chk2_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(24 to 29), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(4)); -- [out std_logic] Parity_chk2_6 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5) port map ( InA => data_chk2(30 to 34), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(5)); -- [out std_logic] -- Parity_chk2_7 : ParityEnable -- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) -- port map ( -- InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)] -- Enable => Enable_ECC, -- [in std_logic] -- Res => syndrome_i(2)); -- [out std_logic] Parity_chk2_7 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(2)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 3 built up from 4 LUT8 and 1 LUT4 ------------------------------------------------------------------------------------------------ data_chk3_i <= data_chk3 & CheckIn(3); Parity_chk3_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(0)); -- [out std_logic] Parity_chk3_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(1)); -- [out std_logic] -- 15-bit for 32-bit ECC -- 31-bit for 64-bit ECC Parity_chk3_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(16 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(2)); -- [out std_logic] Parity_chk3_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(24 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(3)); -- [out std_logic] -- Parity_chk3_5 : ParityEnable -- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) -- port map ( -- InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)] -- Enable => Enable_ECC, -- [in std_logic] -- Res => syndrome_i(3)); -- [out std_logic] Parity_chk3_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(3)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 4 built up from 4 LUT8 and 1 LUT4 ------------------------------------------------------------------------------------------------ data_chk4_i <= data_chk4 & CheckIn(4); -- 15-bit for 32-bit ECC -- 31-bit for 64-bit ECC Parity_chk4_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(0)); -- [out std_logic] Parity_chk4_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(1)); -- [out std_logic] Parity_chk4_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(16 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(2)); -- [out std_logic] Parity_chk4_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(24 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(3)); -- [out std_logic] Parity_chk4_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(4)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 5 built up from 4 LUT8 and 1 LUT4 ------------------------------------------------------------------------------------------------ data_chk5_i <= data_chk5 & CheckIn(5); -- 15-bit for 32-bit ECC -- 31-bit for 64-bit ECC Parity_chk5_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk5_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk5_1(0)); -- [out std_logic] Parity_chk5_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk5_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk5_1(1)); -- [out std_logic] Parity_chk5_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk5_i(16 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk5_1(2)); -- [out std_logic] Parity_chk5_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk5_i(24 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk5_1(3)); -- [out std_logic] Parity_chk5_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk5_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(5)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 6 built up from 1 LUT8 ------------------------------------------------------------------------------------------------ data_chk6_i <= data_chk6 & CheckIn(6); Parity_chk6_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk6_i, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(6)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 7 built up from 3 LUT7 and 8 LUT6 and 1 LUT3 (12 total) + 2 LUT6 + 1 2-bit XOR ------------------------------------------------------------------------------------------------ -- 32-bit ECC uses DataIn(0:31) and Checkin (0 to 6) -- 64-bit ECC will use DataIn(0:63) and Checkin (0 to 7) data_chk7 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31) & DataIn(32) & DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) & DataIn(38) & DataIn(39) & DataIn(40) & DataIn(41) & DataIn(42) & DataIn(43) & DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) & DataIn(48) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) & DataIn(55) & DataIn(56) & DataIn(57) & DataIn(58) & DataIn(59) & DataIn(60) & DataIn(61) & DataIn(62) & DataIn(63) & CheckIn(6) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) & CheckIn(1) & CheckIn(0) & CheckIn(7); Parity_chk7_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(0)); -- [out std_logic] Parity_chk7_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(1)); -- [out std_logic] Parity_chk7_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(2)); -- [out std_logic] Parity_chk7_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk7(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(3)); -- [out std_logic] Parity_chk7_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk7(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(4)); -- [out std_logic] Parity_chk7_6 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk7(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(5)); -- [out std_logic] Parity_chk7_7 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7(39 to 44), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(6)); -- [out std_logic] Parity_chk7_8 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7(45 to 50), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(7)); -- [out std_logic] Parity_chk7_9 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7(51 to 56), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(8)); -- [out std_logic] Parity_chk7_10 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7(57 to 62), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(9)); -- [out std_logic] Parity_chk7_11 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk7(63 to 68), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(10)); -- [out std_logic] Parity_chk7_12 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 3) port map ( InA => data_chk7(69 to 71), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk7_1(11)); -- [out std_logic] -- Unused -- Parity_chk7_13 : Parity -- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) -- port map ( -- InA => chk7_1 (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] -- Res => syndrome7_a); -- [out std_logic] -- -- -- Parity_chk7_14 : Parity -- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) -- port map ( -- InA => chk7_1 (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] -- Res => syndrome7_b); -- [out std_logic] -- Unused syndrome_i(7) <= syndrome7_a xor syndrome7_b; -- Unused syndrome_i (7) <= syndrome7_a; -- syndrome_i (7) is not used here. Final XOR stage is done outside this module with Syndrome_7 vector output. -- Clean up this statement. syndrome_i (7) <= '0'; -- Unused syndrome_int_7 <= syndrome7_a xor syndrome7_b; -- Unused Syndrome_7_b <= syndrome7_b; Syndrome <= syndrome_i; -- Bring out seperate output to do final XOR stage on Syndrome (7) after -- the pipeline stage. Syndrome_7 <= chk7_1 (0 to 11); --------------------------------------------------------------------------- -- With final syndrome registered outside this module for pipeline balancing -- Use registered syndrome to generate any error flags. -- Use input signal, Syndrome_Chk which is the registered Syndrome used to -- correct any single bit errors. syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2); -- syndrome_3_to_6 <= syndrome_i(3) & syndrome_i(4) & syndrome_i(5) & syndrome_i(6); syndrome_3_to_6 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5) & Syndrome_Chk(6); syndrome_3_to_6_zero <= '1' when syndrome_3_to_6 = "0000" else '0'; -- Syndrome bits (3:6) can indicate a double bit error if -- Syndrome (6) = '1' AND any bits of Syndrome(3:5) are equal to a '1'. syndrome_3_to_6_multi <= '1' when (syndrome_3_to_6 = "1111" or -- 15 syndrome_3_to_6 = "1101" or -- 13 syndrome_3_to_6 = "1011" or -- 11 syndrome_3_to_6 = "1001" or -- 9 syndrome_3_to_6 = "0111" or -- 7 syndrome_3_to_6 = "0101" or -- 5 syndrome_3_to_6 = "0011") -- 3 else '0'; -- A single bit error is detectable if -- Syndrome (7) = '1' and a double bit error is not detectable in Syndrome (3:6) -- CE <= Enable_ECC and (syndrome_i(7) or CE_Q) when (syndrome_3_to_6_multi = '0') -- CE <= Enable_ECC and (syndrome_int_7 or CE_Q) when (syndrome_3_to_6_multi = '0') -- CE <= Enable_ECC and (Syndrome_Chk(7) or CE_Q) when (syndrome_3_to_6_multi = '0') -- else CE_Q and Enable_ECC; -- Ensure that CE flag is only asserted for a single clock cycle (and does not keep -- registered output value) CE <= (Enable_ECC and Syndrome_Chk(7)) when (syndrome_3_to_6_multi = '0') else '0'; -- Uncorrectable error if Syndrome(7) = '0' and any other bits are = '1'. -- ue_i_0 <= Enable_ECC when (syndrome_3_to_6_zero = '0') or (syndrome_i(0 to 2) /= "000") -- else UE_Q and Enable_ECC; -- ue_i_0 <= Enable_ECC when (syndrome_3_to_6_zero = '0') or (syndrome_0_to_2 /= "000") -- else UE_Q and Enable_ECC; -- -- ue_i_1 <= Enable_ECC and (syndrome_3_to_6_multi or UE_Q); -- Similar edit from CE flag. Ensure that UE flags are only asserted for a single -- clock cycle. The flags are registered outside this module for detection in -- register module. ue_i_0 <= Enable_ECC when (syndrome_3_to_6_zero = '0') or (syndrome_0_to_2 /= "000") else '0'; ue_i_1 <= Enable_ECC and (syndrome_3_to_6_multi); Use_LUT6: if (C_USE_LUT6) generate UE_MUXF7 : MUXF7 port map ( I0 => ue_i_0, I1 => ue_i_1, -- S => syndrome_i(7), -- S => syndrome_int_7, S => Syndrome_Chk(7), O => UE ); end generate Use_LUT6; Use_RTL: if (not C_USE_LUT6) generate -- bit 6 in 32-bit ECC -- bit 7 in 64-bit ECC -- UE <= ue_i_1 when syndrome_i(7) = '1' else ue_i_0; -- UE <= ue_i_1 when syndrome_int_7 = '1' else ue_i_0; UE <= ue_i_1 when Syndrome_Chk(7) = '1' else ue_i_0; end generate Use_RTL; end generate Decode_Bits; end architecture IMP; ------------------------------------------------------------------------------- -- checkbit_handler.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: checkbit_handler.vhd -- -- Description: Generates the ECC checkbits for the input vector of data bits. -- -- VHDL-Standard: VHDL'93/02 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity checkbit_handler is generic ( C_ENCODE : boolean := true; C_USE_LUT6 : boolean := true ); port ( DataIn : in std_logic_vector(0 to 31); --- changed from 31 downto 0 to 0 to 31 to make it compatabile with LMB Controller's hamming code. CheckIn : in std_logic_vector(0 to 6); CheckOut : out std_logic_vector(0 to 6); Syndrome : out std_logic_vector(0 to 6); Syndrome_4 : out std_logic_vector (0 to 1); Syndrome_6 : out std_logic_vector (0 to 5); Syndrome_Chk : in std_logic_vector (0 to 6); Enable_ECC : in std_logic; UE_Q : in std_logic; CE_Q : in std_logic; UE : out std_logic; CE : out std_logic ); end entity checkbit_handler; library unisim; use unisim.vcomponents.all; architecture IMP of checkbit_handler is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; component XOR18 is generic ( C_USE_LUT6 : boolean); port ( InA : in std_logic_vector(0 to 17); res : out std_logic); end component XOR18; component Parity is generic ( C_USE_LUT6 : boolean; C_SIZE : integer); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Res : out std_logic); end component Parity; signal data_chk0 : std_logic_vector(0 to 17); signal data_chk1 : std_logic_vector(0 to 17); signal data_chk2 : std_logic_vector(0 to 17); signal data_chk3 : std_logic_vector(0 to 14); signal data_chk4 : std_logic_vector(0 to 14); signal data_chk5 : std_logic_vector(0 to 5); begin -- architecture IMP data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) & DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) & DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30); data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) & DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) & DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31); data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31); data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25); data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25); data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31); -- Encode bits for writing data Encode_Bits : if (C_ENCODE) generate signal data_chk3_i : std_logic_vector(0 to 17); signal data_chk4_i : std_logic_vector(0 to 17); signal data_chk6 : std_logic_vector(0 to 17); begin ------------------------------------------------------------------------------------------------ -- Checkbit 0 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I0 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk0, -- [in std_logic_vector(0 to 17)] res => CheckOut(0)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 1 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I1 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk1, -- [in std_logic_vector(0 to 17)] res => CheckOut(1)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 2 built up using XOR18 ------------------------------------------------------------------------------------------------ XOR18_I2 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk2, -- [in std_logic_vector(0 to 17)] res => CheckOut(2)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 3 built up using XOR18 ------------------------------------------------------------------------------------------------ data_chk3_i <= data_chk3 & "000"; XOR18_I3 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk3_i, -- [in std_logic_vector(0 to 17)] res => CheckOut(3)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 4 built up using XOR18 ------------------------------------------------------------------------------------------------ data_chk4_i <= data_chk4 & "000"; XOR18_I4 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk4_i, -- [in std_logic_vector(0 to 17)] res => CheckOut(4)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 5 built up from 1 LUT6 ------------------------------------------------------------------------------------------------ Parity_chk5_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => CheckOut(5)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Checkbit 6 built up from 3 LUT7 and 4 LUT6 ------------------------------------------------------------------------------------------------ data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) & DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29); XOR18_I6 : XOR18 generic map ( C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( InA => data_chk6, -- [in std_logic_vector(0 to 17)] res => CheckOut(6)); -- [out std_logic] end generate Encode_Bits; -------------------------------------------------------------------------------------------------- -- Decode bits to get syndrome and UE/CE signals -------------------------------------------------------------------------------------------------- Decode_Bits : if (not C_ENCODE) generate signal syndrome_i : std_logic_vector(0 to 6) := (others => '0'); signal chk0_1 : std_logic_vector(0 to 3); signal chk1_1 : std_logic_vector(0 to 3); signal chk2_1 : std_logic_vector(0 to 3); signal data_chk3_i : std_logic_vector(0 to 15); signal chk3_1 : std_logic_vector(0 to 1); signal data_chk4_i : std_logic_vector(0 to 15); signal chk4_1 : std_logic_vector(0 to 1); signal data_chk5_i : std_logic_vector(0 to 6); signal data_chk6 : std_logic_vector(0 to 38); signal chk6_1 : std_logic_vector(0 to 5); signal syndrome_0_to_2 : std_logic_vector (0 to 2); signal syndrome_3_to_5 : std_logic_vector (3 to 5); signal syndrome_3_to_5_multi : std_logic; signal syndrome_3_to_5_zero : std_logic; signal ue_i_0 : std_logic; signal ue_i_1 : std_logic; begin ------------------------------------------------------------------------------------------------ -- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk0_1(3) <= CheckIn(0); Parity_chk0_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(0)); -- [out std_logic] Parity_chk0_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(1)); -- [out std_logic] Parity_chk0_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk0_1(2)); -- [out std_logic] Parity_chk0_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(0)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk1_1(3) <= CheckIn(1); Parity_chk1_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(0)); -- [out std_logic] Parity_chk1_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(1)); -- [out std_logic] Parity_chk1_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk1_1(2)); -- [out std_logic] Parity_chk1_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(1)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4 ------------------------------------------------------------------------------------------------ chk2_1(3) <= CheckIn(2); Parity_chk2_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(0)); -- [out std_logic] Parity_chk2_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(1)); -- [out std_logic] Parity_chk2_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk2_1(2)); -- [out std_logic] Parity_chk2_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4) port map ( InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(2)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2 ------------------------------------------------------------------------------------------------ data_chk3_i <= data_chk3 & CheckIn(3); Parity_chk3_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(0)); -- [out std_logic] Parity_chk3_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk3_1(1)); -- [out std_logic] -- For improved timing, remove Enable_ECC signal in this LUT level Parity_chk3_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(3)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2 ------------------------------------------------------------------------------------------------ data_chk4_i <= data_chk4 & CheckIn(4); Parity_chk4_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(0)); -- [out std_logic] Parity_chk4_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8) port map ( InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk4_1(1)); -- [out std_logic] -- Set bit 4 output with default. Real ECC XOR value will be determined post register -- stage. syndrome_i (4) <= '0'; -- For improved timing, move last LUT level XOR to next side of pipeline -- stage in read path. Syndrome_4 <= chk4_1; ------------------------------------------------------------------------------------------------ -- Syndrome bit 5 built up from 1 LUT7 ------------------------------------------------------------------------------------------------ data_chk5_i <= data_chk5 & CheckIn(5); Parity_chk5_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_i(5)); -- [out std_logic] ------------------------------------------------------------------------------------------------ -- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6 ------------------------------------------------------------------------------------------------ data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) & CheckIn(1) & CheckIn(0) & CheckIn(6); Parity_chk6_1 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(0)); -- [out std_logic] Parity_chk6_2 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(1)); -- [out std_logic] Parity_chk6_3 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(2)); -- [out std_logic] Parity_chk6_4 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(3)); -- [out std_logic] Parity_chk6_5 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(4)); -- [out std_logic] Parity_chk6_6 : Parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7) port map ( InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => chk6_1(5)); -- [out std_logic] -- No internal use for MSB of syndrome (it is created after the -- register stage, outside of this block) syndrome_i(6) <= '0'; Syndrome <= syndrome_i; -- (N:0) <= (0:N) -- Bring out seperate output to do final XOR stage on Syndrome (6) after -- the pipeline stage. Syndrome_6 <= chk6_1 (0 to 5); --------------------------------------------------------------------------- -- With final syndrome registered outside this module for pipeline balancing -- Use registered syndrome to generate any error flags. -- Use input signal, Syndrome_Chk which is the registered Syndrome used to -- correct any single bit errors. syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2); syndrome_3_to_5 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5); syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0'; syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or syndrome_3_to_5 = "011" or syndrome_3_to_5 = "101") else '0'; -- Ensure that CE flag is only asserted for a single clock cycle (and does not keep -- registered output value) CE <= (Enable_ECC and Syndrome_Chk(6)) when (syndrome_3_to_5_multi = '0') else '0'; -- Similar edit from CE flag. Ensure that UE flags are only asserted for a single -- clock cycle. The flags are registered outside this module for detection in -- register module. ue_i_0 <= Enable_ECC when (syndrome_3_to_5_zero = '0') or (syndrome_0_to_2 /= "000") else '0'; ue_i_1 <= Enable_ECC and (syndrome_3_to_5_multi); Use_LUT6: if (C_USE_LUT6) generate begin UE_MUXF7 : MUXF7 port map ( I0 => ue_i_0, I1 => ue_i_1, S => Syndrome_Chk(6), O => UE); end generate Use_LUT6; Use_RTL: if (not C_USE_LUT6) generate begin UE <= ue_i_1 when Syndrome_Chk(6) = '1' else ue_i_0; end generate Use_RTL; end generate Decode_Bits; end architecture IMP; ------------------------------------------------------------------------------- -- correct_one_bit_64.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: correct_one_bit_64.vhd -- -- Description: Identifies single bit to correct in 64-bit word of -- data read from memory as indicated by the syndrome input -- vector. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity Correct_One_Bit_64 is generic ( C_USE_LUT6 : boolean := true; Correct_Value : std_logic_vector(0 to 7)); port ( DIn : in std_logic; Syndrome : in std_logic_vector(0 to 7); DCorr : out std_logic); end entity Correct_One_Bit_64; architecture IMP of Correct_One_Bit_64 is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ----------------------------------------------------------------------------- -- Find which bit that has a '1' -- There is always one bit which has a '1' ----------------------------------------------------------------------------- function find_one (Syn : std_logic_vector(0 to 7)) return natural is begin -- function find_one for I in 0 to 7 loop if (Syn(I) = '1') then return I; end if; end loop; -- I return 0; -- Should never reach this statement end function find_one; constant di_index : natural := find_one(Correct_Value); signal corr_sel : std_logic; signal corr_c : std_logic; signal lut_compare : std_logic_vector(0 to 6); signal lut_corr_val : std_logic_vector(0 to 6); begin -- architecture IMP Remove_DI_Index : process (Syndrome) is begin -- process Remove_DI_Index if (di_index = 0) then lut_compare <= Syndrome(1 to 7); lut_corr_val <= Correct_Value(1 to 7); elsif (di_index = 6) then lut_compare <= Syndrome(0 to 6); lut_corr_val <= Correct_Value(0 to 6); else lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 7); lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 7); end if; end process Remove_DI_Index; corr_sel <= '0' when lut_compare = lut_corr_val else '1'; Corr_MUXCY : MUXCY_L port map ( DI => Syndrome(di_index), CI => '0', S => corr_sel, LO => corr_c); Corr_XORCY : XORCY port map ( LI => DIn, CI => corr_c, O => DCorr); end architecture IMP; ------------------------------------------------------------------------------- -- correct_one_bit.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: correct_one_bit.vhd -- -- Description: Identifies single bit to correct in 32-bit word of -- data read from memory as indicated by the syndrome input -- vector. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity Correct_One_Bit is generic ( C_USE_LUT6 : boolean := true; Correct_Value : std_logic_vector(0 to 6)); port ( DIn : in std_logic; Syndrome : in std_logic_vector(0 to 6); DCorr : out std_logic); end entity Correct_One_Bit; architecture IMP of Correct_One_Bit is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ----------------------------------------------------------------------------- -- Find which bit that has a '1' -- There is always one bit which has a '1' ----------------------------------------------------------------------------- function find_one (Syn : std_logic_vector(0 to 6)) return natural is begin -- function find_one for I in 0 to 6 loop if (Syn(I) = '1') then return I; end if; end loop; -- I return 0; -- Should never reach this statement end function find_one; constant di_index : natural := find_one(Correct_Value); signal corr_sel : std_logic; signal corr_c : std_logic; signal lut_compare : std_logic_vector(0 to 5); signal lut_corr_val : std_logic_vector(0 to 5); begin -- architecture IMP Remove_DI_Index : process (Syndrome) is begin -- process Remove_DI_Index if (di_index = 0) then lut_compare <= Syndrome(1 to 6); lut_corr_val <= Correct_Value(1 to 6); elsif (di_index = 6) then lut_compare <= Syndrome(0 to 5); lut_corr_val <= Correct_Value(0 to 5); else lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6); lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6); end if; end process Remove_DI_Index; -- Corr_LUT : LUT6 -- generic map( -- INIT => X"6996966996696996" -- ) -- port map( -- O => corr_sel, -- [out] -- I0 => InA(5), -- [in] -- I1 => InA(4), -- [in] -- I2 => InA(3), -- [in] -- I3 => InA(2), -- [in] -- I4 => InA(1), -- [in] -- I5 => InA(0) -- [in] -- ); corr_sel <= '0' when lut_compare = lut_corr_val else '1'; Corr_MUXCY : MUXCY_L port map ( DI => Syndrome(di_index), CI => '0', S => corr_sel, LO => corr_c); Corr_XORCY : XORCY port map ( LI => DIn, CI => corr_c, O => DCorr); end architecture IMP; ------------------------------------------------------------------------------- -- xor18.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: xor18.vhd -- -- Description: Basic 18-bit input XOR function. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add default on C_USE_LUT6 parameter. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity XOR18 is generic ( C_USE_LUT6 : boolean := FALSE ); port ( InA : in std_logic_vector(0 to 17); res : out std_logic); end entity XOR18; architecture IMP of XOR18 is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; begin -- architecture IMP Using_LUT6: if (C_USE_LUT6) generate signal xor6_1 : std_logic; signal xor6_2 : std_logic; signal xor6_3 : std_logic; signal xor18_c1 : std_logic; signal xor18_c2 : std_logic; begin -- generate Using_LUT6 XOR6_1_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => xor6_1, I0 => InA(17), I1 => InA(16), I2 => InA(15), I3 => InA(14), I4 => InA(13), I5 => InA(12)); XOR_1st_MUXCY : MUXCY_L port map ( DI => '1', CI => '0', S => xor6_1, LO => xor18_c1); XOR6_2_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => xor6_2, I0 => InA(11), I1 => InA(10), I2 => InA(9), I3 => InA(8), I4 => InA(7), I5 => InA(6)); XOR_2nd_MUXCY : MUXCY_L port map ( DI => xor6_1, CI => xor18_c1, S => xor6_2, LO => xor18_c2); XOR6_3_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => xor6_3, I0 => InA(5), I1 => InA(4), I2 => InA(3), I3 => InA(2), I4 => InA(1), I5 => InA(0)); XOR18_XORCY : XORCY port map ( LI => xor6_3, CI => xor18_c2, O => res); end generate Using_LUT6; Not_Using_LUT6: if (not C_USE_LUT6) generate begin -- generate Not_Using_LUT6 res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0); end generate Not_Using_LUT6; end architecture IMP; ------------------------------------------------------------------------------- -- parity.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: parity.vhd -- -- Description: Generate parity optimally for all target architectures. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity Parity is generic ( C_USE_LUT6 : boolean := true; C_SIZE : integer := 6 ); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Res : out std_logic ); end entity Parity; library unisim; use unisim.vcomponents.all; architecture IMP of Parity is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; -- Non-recursive loop implementation function ParityGen (InA : std_logic_vector) return std_logic is variable result : std_logic; begin result := '0'; for I in InA'range loop result := result xor InA(I); end loop; return result; end function ParityGen; begin -- architecture IMP Using_LUT6 : if (C_USE_LUT6) generate -------------------------------------------------------------------------------------------------- -- Single LUT6 -------------------------------------------------------------------------------------------------- Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate signal inA6 : std_logic_vector(0 to 5); begin Assign_InA : process (InA) is begin inA6 <= (others => '0'); inA6(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => Res, I0 => inA6(5), I1 => inA6(4), I2 => inA6(3), I3 => inA6(2), I4 => inA6(1), I5 => inA6(0)); end generate Single_LUT6; -------------------------------------------------------------------------------------------------- -- Two LUT6 and one MUXF7 -------------------------------------------------------------------------------------------------- Use_MUXF7 : if C_SIZE = 7 generate signal inA7 : std_logic_vector(0 to 6); signal result6 : std_logic; signal result6n : std_logic; begin Assign_InA : process (InA) is begin inA7 <= (others => '0'); inA7(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => result6, I0 => inA7(5), I1 => inA7(4), I2 => inA7(3), I3 => inA7(2), I4 => inA7(1), I5 => inA7(0)); XOR6_LUT_N : LUT6 generic map( INIT => X"9669699669969669") port map( O => result6n, I0 => inA7(5), I1 => inA7(4), I2 => inA7(3), I3 => inA7(2), I4 => inA7(1), I5 => inA7(0)); MUXF7_LUT : MUXF7 port map ( O => Res, I0 => result6, I1 => result6n, S => inA7(6)); end generate Use_MUXF7; -------------------------------------------------------------------------------------------------- -- Four LUT6, two MUXF7 and one MUXF8 -------------------------------------------------------------------------------------------------- Use_MUXF8 : if C_SIZE = 8 generate signal inA8 : std_logic_vector(0 to 7); signal result6_1 : std_logic; signal result6_1n : std_logic; signal result6_2 : std_logic; signal result6_2n : std_logic; signal result7_1 : std_logic; signal result7_1n : std_logic; begin Assign_InA : process (InA) is begin inA8 <= (others => '0'); inA8(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT1 : LUT6 generic map( INIT => X"6996966996696996") port map( O => result6_1, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); XOR6_LUT2_N : LUT6 generic map( INIT => X"9669699669969669") port map( O => result6_1n, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); MUXF7_LUT1 : MUXF7 port map ( O => result7_1, I0 => result6_1, I1 => result6_1n, S => inA8(6)); XOR6_LUT3 : LUT6 generic map( INIT => X"6996966996696996") port map( O => result6_2, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); XOR6_LUT4_N : LUT6 generic map( INIT => X"9669699669969669") port map( O => result6_2n, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); MUXF7_LUT2 : MUXF7 port map ( O => result7_1n, I0 => result6_2n, I1 => result6_2, S => inA8(6)); MUXF8_LUT : MUXF8 port map ( O => res, I0 => result7_1, I1 => result7_1n, S => inA8(7)); end generate Use_MUXF8; end generate Using_LUT6; -- Fall-back implementation without LUT6 Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate begin Res <= ParityGen(InA); end generate Not_Using_LUT6; end architecture IMP; ---------------------------------------------------------------------------------------------- -- -- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006 -- Wed Jun 17 2009 01:03:24 -- -- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ecc/ecc_gen.v -- Component name : ecc_gen -- Author : -- Company : -- -- Description : -- -- ---------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; -- Generate the ecc code. Note that the synthesizer should -- generate this as a static logic. Code in this block should -- never run during simulation phase, or directly impact timing. -- -- The code generated is a single correct, double detect code. -- It is the classic Hamming code. Instead, the code is -- optimized for minimal/balanced tree depth and size. See -- Hsiao IBM Technial Journal 1970. -- -- The code is returned as a single bit vector, h_rows. This was -- the only way to "subroutinize" this with the restrictions of -- disallowed include files and that matrices cannot be passed -- in ports. -- -- Factorial and the combos functions are defined. Combos -- simply computes the number of combinations from the set -- size and elements at a time. -- -- The function next_combo computes the next combination in -- lexicographical order given the "current" combination. Its -- output is undefined if given the last combination in the -- lexicographical order. -- -- next_combo is insensitive to the number of elements in the -- combinations. -- -- An H transpose matrix is generated because that's the easiest -- way to do it. The H transpose matrix is generated by taking -- the one at a time combinations, then the 3 at a time, then -- the 5 at a time. The number combinations used is equal to -- the width of the code (CODE_WIDTH). The boundaries between -- the 1, 3 and 5 groups are hardcoded in the for loop. -- -- At the same time the h_rows vector is generated from the -- H transpose matrix. entity ecc_gen is generic ( CODE_WIDTH : integer := 72; ECC_WIDTH : integer := 8; DATA_WIDTH : integer := 64 ); port ( -- Outputs -- function next_combo -- Given a combination, return the next combo in lexicographical -- order. Scans from right to left. Assumes the first combination -- is k ones all of the way to the left. -- -- Upon entry, initialize seen0, trig1, and ones. "seen0" means -- that a zero has been observed while scanning from right to left. -- "trig1" means that a one have been observed _after_ seen0 is set. -- "ones" counts the number of ones observed while scanning the input. -- -- If trig1 is one, just copy the input bit to the output and increment -- to the next bit. Otherwise set the the output bit to zero, if the -- input is a one, increment ones. If the input bit is a one and seen0 -- is true, dump out the accumulated ones. Set seen0 to the complement -- of the input bit. Note that seen0 is not used subsequent to trig1 -- getting set. -- The stuff above leads to excessive XST execution times. For now, hardwire to 72/64 bit. h_rows : out std_logic_vector(CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); end entity ecc_gen; architecture trans of ecc_gen is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of trans : architecture is "yes"; function factorial (ivar: integer) return integer is variable tmp : integer; begin if (ivar = 1) then return 1; else tmp := 1; for i in ivar downto 2 loop tmp := tmp * i; end loop; end if; return tmp; end function factorial; function combos ( n, k: integer) return integer is begin return factorial(n)/(factorial(k)*factorial(n-k)); end function combos; function next_combo (i: std_logic_vector) return std_logic_vector is variable seen0: std_logic; variable trig1: std_logic; variable ones: std_logic_vector (ECC_WIDTH-1 downto 0); variable tmp: std_logic_vector (ECC_WIDTH-1 downto 0); variable tmp_index : integer; begin seen0 := '0'; trig1 := '0'; ones := (others => '0'); for index in ECC_WIDTH -1 downto 0 loop tmp_index := ECC_WIDTH -1 - index; if (trig1 = '1') then tmp(tmp_index) := i(tmp_index); else tmp(tmp_index) := '0'; ones := ones + i(tmp_index); if ((i(tmp_index) = '1') and (seen0 = '1')) then trig1 := '1'; for dump_index in tmp_index-1 downto 0 loop if (dump_index >= (tmp_index- conv_integer(ones)) ) then tmp(dump_index) := '1'; end if; end loop; end if; seen0 := not(i(tmp_index)); end if; end loop; return tmp; end function next_combo; constant COMBOS_3 : integer := combos(ECC_WIDTH, 3); constant COMBOS_5 : integer := combos(ECC_WIDTH, 5); type twoDarray is array (CODE_WIDTH -1 downto 0) of std_logic_vector (ECC_WIDTH-1 downto 0); signal ht_matrix : twoDarray; begin columns: for n in CODE_WIDTH - 1 downto 0 generate column0: if (n = 0) generate ht_matrix(n) <= "111" & conv_std_logic_vector(0,ECC_WIDTH-3); end generate; column_combos3: if ((n = COMBOS_3) and ( n < DATA_WIDTH) ) generate ht_matrix(n) <= "11111" & conv_std_logic_vector(0,ECC_WIDTH-5); end generate; column_combos5: if ((n = COMBOS_3 + COMBOS_5) and ( n < DATA_WIDTH) ) generate ht_matrix(n) <= "1111111" & conv_std_logic_vector(0,ECC_WIDTH-7); end generate; column_datawidth: if (n = DATA_WIDTH) generate ht_matrix(n) <= "1" & conv_std_logic_vector(0,ECC_WIDTH-1); end generate; column_gen: if ( (n /= 0 ) and ((n /= COMBOS_3) or (n > DATA_WIDTH)) and ((n /= COMBOS_3+COMBOS_5) or (n > DATA_WIDTH)) and (n /= DATA_WIDTH) ) generate ht_matrix(n) <= next_combo(ht_matrix(n-1)); end generate; out_assign: for s in ECC_WIDTH-1 downto 0 generate h_rows(s*CODE_WIDTH+n) <= ht_matrix(n)(s); end generate; end generate; --h_row0 <= "100000000100100011101101001101001000110100100010000110100100010000100000"; --h_row1 <= "010000001010010011011010101010100100101010010001000101010010001000010000"; --h_row2 <= "001000001001001010110110010110010010011001001000100011001001000100001000"; --h_row3 <= "000100000111000101110001110001110001000111000100010000111000100010000100"; --h_row4 <= "000010000000111100001111110000001111000000111100001000000111100001000010"; --h_row5 <= "000001001111111100000000001111111111000000000011111000000000011111000001"; --h_row6 <= "000000101111111100000000000000000000111111111111111000000000000000111111"; --h_row7 <= "000000011111111100000000000000000000000000000000000111111111111111111111"; --h_rows <= (h_row7 & h_row6 & h_row5 & h_row4 & h_row3 & h_row2 & h_row1 & h_row0); end architecture trans; ------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI-Lite ECC Register Interface Signals *** -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** Memory Controller Interface Signals *** -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation; ------------------------------------------------------------------------------- -- axi_lite.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_lite.vhd -- -- Description: This file is the top level module for the AXI-Lite -- instantiation of the BRAM controller interface. -- -- Responsible for shared address pipelining between the -- write address (AW) and read address (AR) channels. -- Controls (seperately) the data flows for the write data -- (W), write response (B), and read data (R) channels. -- -- Creates a shared port to BRAM (for all read and write -- transactions) or dual BRAM port utilization based on a -- generic parameter setting. -- -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- ecc_gen.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Update BRAM address mapping to lite_ecc_reg module. Corrected -- signal size for XST detected unused bits in vector. -- Plus minor code cleanup. -- -- Add top level parameter, C_ECC_TYPE for Hsiao ECC algorithm. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Add Hsiao ECC algorithm logic (similar to full_axi module HDL). -- ^^^^^^ -- JLJ 2/24/2011 v1.03a -- ~~~~~~ -- Move REG_RDATA register process out from C_ECC_TYPE generate block -- to C_ECC generate block. -- ^^^^^^ -- JLJ 3/22/2011 v1.03a -- ~~~~~~ -- Add LUT level with reset signal to combinatorial outputs, AWREADY -- and WREADY. This will ensure that the output remains LOW during reset, -- regardless of AWVALID or WVALID input signals. -- ^^^^^^ -- JLJ 3/28/2011 v1.03a -- ~~~~~~ -- Remove combinatorial output paths on AWREADY and WREADY. -- Combine AWREADY and WREADY registers. -- Remove combinatorial output path on ARREADY. Can pre-assert ARREADY -- (but only for non ECC configurations). -- Create 3-bit counter for BVALID response, seperate from AW/W channels. -- -- Delay assertion of WREADY in ECC configurations to minimize register -- resource utilization. -- No pre-assertion of ARREADY in ECC configurations (due to write latency -- with ECC enabled). -- -- ^^^^^^ -- JLJ 3/30/2011 v1.03a -- ~~~~~~ -- Update Sl_CE and Sl_UE flag assertions to a single clock cycle. -- Clean up comments. -- ^^^^^^ -- JLJ 4/19/2011 v1.03a -- ~~~~~~ -- Update BVALID assertion when ECC is enabled to match the implementation -- when C_ECC = 0. Optimize back to back write performance when C_ECC = 1. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Modify FaultInjectClr signal assertion. With BVALID counter, delay -- when fault inject register gets cleared. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Code clean up. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Hard code C_USE_LUT6 constant. -- ^^^^^^ -- JLJ 7/7/2011 v1.03a -- ~~~~~~ -- Fix DV regression failure with reset. -- Hold off BRAM enable output with active reset signal. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.lite_ecc_reg; use work.parity; use work.checkbit_handler; use work.correct_one_bit; use work.ecc_gen; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity axi_lite is generic ( C_S_AXI_PROTOCOL : string := "AXI4LITE"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : integer := 1; -- Enable single port usage of BRAM -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_TYPE : integer := 0; -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; ECC_Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI Write Address Channel Signals (AW) *** AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); AXI_AWVALID : in std_logic; AXI_AWREADY : out std_logic; -- Unused AW AXI-Lite Signals -- AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); -- AXI_AWLEN : in std_logic_vector(7 downto 0); -- AXI_AWSIZE : in std_logic_vector(2 downto 0); -- AXI_AWBURST : in std_logic_vector(1 downto 0); -- AXI_AWLOCK : in std_logic; -- Currently unused -- AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused -- AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused -- *** AXI Write Data Channel Signals (W) *** AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); AXI_WVALID : in std_logic; AXI_WREADY : out std_logic; -- Unused W AXI-Lite Signals -- AXI_WLAST : in std_logic; -- *** AXI Write Data Response Channel Signals (B) *** AXI_BRESP : out std_logic_vector(1 downto 0); AXI_BVALID : out std_logic; AXI_BREADY : in std_logic; -- Unused B AXI-Lite Signals -- AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); -- *** AXI Read Address Channel Signals (AR) *** AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); AXI_ARVALID : in std_logic; AXI_ARREADY : out std_logic; -- *** AXI Read Data Channel Signals (R) *** AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); AXI_RRESP : out std_logic_vector(1 downto 0); AXI_RLAST : out std_logic; AXI_RVALID : out std_logic; AXI_RREADY : in std_logic; -- *** AXI-Lite ECC Register Interface Signals *** -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** BRAM Port A Interface Signals *** -- Note: Clock handled at top level (axi_bram_ctrl module) BRAM_En_A : out std_logic; BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0); BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC -- Note: Remove BRAM_RdData_A port (unused in dual port mode) -- Platgen will keep port open on BRAM block -- *** BRAM Port B Interface Signals *** -- Note: Clock handled at top level (axi_bram_ctrl module) BRAM_En_B : out std_logic; BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0); BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) -- @ port level = 8-bits wide ECC ); end entity axi_lite; ------------------------------------------------------------------------------- architecture implementation of axi_lite is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error -- For future implementation. -- constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response -- constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8); constant C_BRAM_ADDR_ADJUST : integer := C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR; constant C_AXI_DATA_WIDTH_BYTES : integer := C_S_AXI_DATA_WIDTH/8; -- Internal data width based on C_S_AXI_DATA_WIDTH. constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH); -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; -- Remove usage of C_FAMILY. -- All architectures supporting AXI will support a LUT6. -- Hard code this internal constant used in ECC algorithm. -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; constant C_USE_LUT6 : boolean := TRUE; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal axi_aresetn_d1 : std_logic := '0'; signal axi_aresetn_re : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write & Read Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type LITE_SM_TYPE is ( IDLE, SNG_WR_DATA, RD_DATA, RMW_RD_DATA, RMW_MOD_DATA, RMW_WR_DATA ); signal lite_sm_cs, lite_sm_ns : LITE_SM_TYPE; signal axi_arready_cmb : std_logic := '0'; signal axi_arready_reg : std_logic := '0'; signal axi_arready_int : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write Data Channel Signals ------------------------------------------------------------------------------- signal axi_wready_cmb : std_logic := '0'; signal axi_wready_int : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write Response Channel Signals ------------------------------------------------------------------------------- signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_bvalid_int : std_logic := '0'; signal bvalid_cnt_inc : std_logic := '0'; signal bvalid_cnt_inc_d1 : std_logic := '0'; signal bvalid_cnt_dec : std_logic := '0'; signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Read Data Channel Signals ------------------------------------------------------------------------------- signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_rvalid_set : std_logic := '0'; signal axi_rvalid_set_r : std_logic := '0'; signal axi_rvalid_int : std_logic := '0'; signal axi_rlast_set : std_logic := '0'; signal axi_rlast_set_r : std_logic := '0'; signal axi_rlast_int : std_logic := '0'; signal axi_rdata_int : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal axi_rdata_int_corr : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Internal BRAM Signals ------------------------------------------------------------------------------- signal bram_we_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0) := (others => '0'); signal bram_en_a_cmb : std_logic := '0'; signal bram_en_b_cmb : std_logic := '0'; signal bram_en_a_int : std_logic := '0'; signal bram_en_b_int : std_logic := '0'; signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_a_int_q : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port level signal, 8-bits ECC ------------------------------------------------------------------------------- -- Internal ECC Signals ------------------------------------------------------------------------------- signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register signal Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal Sl_CE_i : std_logic := '0'; signal Sl_UE_i : std_logic := '0'; signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal FaultInjectECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal CorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal UnCorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal CE_Q : std_logic := '0'; signal UE_Q : std_logic := '0'; signal Enable_ECC : std_logic := '0'; signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence signal RdModifyWr_Check : std_logic := '0'; -- Read cycle in read modify write sequence signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence signal WrData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal WrData_cmb : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal Active_Wr : std_logic := '0'; signal BRAM_Addr_En : std_logic := '0'; signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- *** AXI-Lite ECC Register Output Signals *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_REGS -- Purpose: Generate default values if ECC registers are disabled (or when -- ECC is disabled). -- Include both AXI-Lite default signal values & internal -- core signal values. --------------------------------------------------------------------------- -- For future implementation. -- GEN_NO_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) or (C_ECC = 0) generate GEN_NO_REGS: if (C_ECC = 0) generate begin AXI_CTRL_AWREADY <= '0'; AXI_CTRL_WREADY <= '0'; AXI_CTRL_BRESP <= (others => '0'); AXI_CTRL_BVALID <= '0'; AXI_CTRL_ARREADY <= '0'; AXI_CTRL_RDATA <= (others => '0'); AXI_CTRL_RRESP <= (others => '0'); AXI_CTRL_RVALID <= '0'; -- No fault injection FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); -- Interrupt only enabled when ECC status/interrupt registers enabled ECC_Interrupt <= '0'; ECC_UE <= '0'; BRAM_Addr_En <= '0'; ----------------------------------------------------------------------- -- Generate: GEN_DIS_ECC -- Purpose: Disable ECC in read path when ECC is disabled in core. ----------------------------------------------------------------------- GEN_DIS_ECC: if C_ECC = 0 generate Enable_ECC <= '0'; end generate GEN_DIS_ECC; -- For future implementation. -- -- ----------------------------------------------------------------------- -- -- Generate: GEN_EN_ECC -- -- Purpose: Enable ECC when C_ECC = 1 and no ECC registers are available. -- -- ECC on/off control register is not accessible (so ECC is always -- -- enabled in this configuraiton). -- ----------------------------------------------------------------------- -- GEN_EN_ECC: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) generate -- Enable_ECC <= '1'; -- ECC ON/OFF register can not be enabled (as no ECC -- -- ECC registers are available. Therefore, ECC -- -- is always enabled. -- end generate GEN_EN_ECC; end generate GEN_NO_REGS; --------------------------------------------------------------------------- -- Generate: GEN_REGS -- Purpose: Generate ECC register module when ECC is enabled and -- ECC registers are enabled. --------------------------------------------------------------------------- -- For future implementation. -- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate GEN_REGS: if (C_ECC = 1) generate begin --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- Description: This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. --------------------------------------------------------------------------- I_LITE_ECC_REG : entity work.lite_ecc_reg generic map ( C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width C_FAULT_INJECT => C_FAULT_INJECT , C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , -- AXI clock S_AXI_AResetn => S_AXI_AResetn , -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock -- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn , Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , AXI_CTRL_AWVALID => AXI_CTRL_AWVALID , AXI_CTRL_AWREADY => AXI_CTRL_AWREADY , AXI_CTRL_AWADDR => AXI_CTRL_AWADDR , AXI_CTRL_WDATA => AXI_CTRL_WDATA , AXI_CTRL_WVALID => AXI_CTRL_WVALID , AXI_CTRL_WREADY => AXI_CTRL_WREADY , AXI_CTRL_BRESP => AXI_CTRL_BRESP , AXI_CTRL_BVALID => AXI_CTRL_BVALID , AXI_CTRL_BREADY => AXI_CTRL_BREADY , AXI_CTRL_ARADDR => AXI_CTRL_ARADDR , AXI_CTRL_ARVALID => AXI_CTRL_ARVALID , AXI_CTRL_ARREADY => AXI_CTRL_ARREADY , AXI_CTRL_RDATA => AXI_CTRL_RDATA , AXI_CTRL_RRESP => AXI_CTRL_RRESP , AXI_CTRL_RVALID => AXI_CTRL_RVALID , AXI_CTRL_RREADY => AXI_CTRL_RREADY , Enable_ECC => Enable_ECC , FaultInjectClr => FaultInjectClr , CE_Failing_We => CE_Failing_We , CE_CounterReg_Inc => CE_Failing_We , Sl_CE => Sl_CE , Sl_UE => Sl_UE , BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_En => BRAM_Addr_En , Active_Wr => Active_Wr , FaultInjectData => FaultInjectData , FaultInjectECC => FaultInjectECC ); FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0'; CE_Failing_We <= '1' when Enable_ECC = '1' and CE_Q = '1' else '0'; Active_Wr <= '1' when (RdModifyWr_Read = '1' or RdModifyWr_Check = '1' or RdModifyWr_Modify = '1' or RdModifyWr_Write = '1') else '0'; ----------------------------------------------------------------------- -- Add register delay on BVALID counter increment -- Used to clear fault inject register. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt_inc_d1 <= '0'; else bvalid_cnt_inc_d1 <= bvalid_cnt_inc; end if; end if; end process REG_BVALID_CNT; ----------------------------------------------------------------------- end generate GEN_REGS; --------------------------------------------------------------------------- -- *** AXI Output Signals *** --------------------------------------------------------------------------- -- AXI Write Address Channel Output Signals -- AXI_AWREADY <= axi_awready_cmb; -- AXI_AWREADY <= '0' when (S_AXI_AResetn = '0') else axi_awready_cmb; -- v1.03a AXI_AWREADY <= axi_wready_int; -- v1.03a -- AXI Write Data Channel Output Signals -- AXI_WREADY <= axi_wready_cmb; -- AXI_WREADY <= '0' when (S_AXI_AResetn = '0') else axi_wready_cmb; -- v1.03a AXI_WREADY <= axi_wready_int; -- v1.03a -- AXI Write Response Channel Output Signals AXI_BRESP <= axi_bresp_int; AXI_BVALID <= axi_bvalid_int; -- AXI Read Address Channel Output Signals -- AXI_ARREADY <= axi_arready_cmb; -- v1.03a AXI_ARREADY <= axi_arready_int; -- v1.03a -- AXI Read Data Channel Output Signals -- AXI_RRESP <= axi_rresp_int; AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int; -- AXI_RDATA <= axi_rdata_int; -- Move assignment of RDATA to generate statements based on C_ECC. AXI_RVALID <= axi_rvalid_int; AXI_RLAST <= axi_rlast_int; ---------------------------------------------------------------------------- -- Need to detect end of reset cycle to assert AWREADY on AXI bus REG_ARESETN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then axi_aresetn_d1 <= S_AXI_AResetn; end if; end process REG_ARESETN; -- Create combinatorial RE detect of S_AXI_AResetn axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0'; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** AXI Write Address Channel Interface *** --------------------------------------------------------------------------- -- Notes: -- No address pipelining for AXI-Lite. -- PDR feedback. -- Remove address register stage to BRAM. -- Rely on registers in AXI Interconnect. --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Generate all valid bits in the address(es) to BRAM. -- If dual port, generate Port B address signal. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin --------------------------------------------------------------------------- -- Generate: GEN_ADDR_SNG_PORT -- Purpose: Generate BRAM address when a single port to BRAM. -- Mux read and write addresses from AXI AW and AR channels. --------------------------------------------------------------------------- GEN_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin -- Read takes priority over AWADDR -- bram_addr_a_int (i) <= AXI_ARADDR (i) when (AXI_ARVALID = '1') else AXI_AWADDR (i); -- ISE should optimize away this mux when connected to the AXI Interconnect -- as the AXI Interconnect duplicates the write or read address on both channels. -- v1.03a -- ARVALID may get asserted while handling ECC read-modify-write. -- With the delay in assertion of AWREADY/WREADY, must add some logic to the -- control on this mux select. bram_addr_a_int (i) <= AXI_ARADDR (i) when ((AXI_ARVALID = '1' and (lite_sm_cs = IDLE or lite_sm_cs = SNG_WR_DATA)) or (lite_sm_cs = RD_DATA)) else AXI_AWADDR (i); end generate GEN_ADDR_SNG_PORT; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_DUAL_PORT -- Purpose: Generate BRAM address when a single port to BRAM. -- Mux read and write addresses from AXI AW and AR channels. --------------------------------------------------------------------------- GEN_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin bram_addr_a_int (i) <= AXI_AWADDR (i); bram_addr_b_int (i) <= AXI_ARADDR (i); end generate GEN_ADDR_DUAL_PORT; end generate GEN_ADDR; --------------------------------------------------------------------------- -- *** AXI Read Address Channel Interface *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_ARREADY -- Purpose: Only pre-assert ARREADY for non ECC designs. -- With ECC, a write requires a read-modify-write and -- will miss the address associated with the ARVALID -- (due to the # of clock cycles). --------------------------------------------------------------------------- GEN_ARREADY: if (C_ECC = 0) generate begin REG_ARREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- ARREADY is asserted until we detect the ARVALID. -- Check for back-to-back ARREADY assertions (add axi_arready_int). if (S_AXI_AResetn = C_RESET_ACTIVE) or (AXI_ARVALID = '1' and axi_arready_int = '1') then axi_arready_int <= '0'; -- Then ARREADY is asserted again when the read operation completes. elsif (axi_aresetn_re = '1') or (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_arready_int <= '1'; else axi_arready_int <= axi_arready_int; end if; end if; end process REG_ARREADY; end generate GEN_ARREADY; --------------------------------------------------------------------------- -- Generate: GEN_ARREADY_ECC -- Purpose: Generate ARREADY from SM logic. ARREADY is not pre-asserted -- as in the non ECC configuration. --------------------------------------------------------------------------- GEN_ARREADY_ECC: if (C_ECC = 1) generate begin axi_arready_int <= axi_arready_reg; end generate GEN_ARREADY_ECC; --------------------------------------------------------------------------- -- *** AXI Write Data Channel Interface *** --------------------------------------------------------------------------- -- No AXI_WLAST --------------------------------------------------------------------------- -- Generate: GEN_WRDATA -- Purpose: Generate BRAM port A write data. For AXI-Lite, pass -- through from AXI bus. If ECC is enabled, merge with fault -- inject vector. -- Write data bits are in lower order bit lanes. -- (31:0) or (63:0) --------------------------------------------------------------------------- GEN_WRDATA: for i in C_S_AXI_DATA_WIDTH-1 downto 0 generate begin --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Generate output write data when ECC is disabled. -- Remove write data path register to BRAM --------------------------------------------------------------------------- GEN_NO_ECC : if C_ECC = 0 generate begin bram_wrdata_a_int (i) <= AXI_WDATA (i); end generate GEN_NO_ECC; --------------------------------------------------------------------------- -- Generate: GEN_W_ECC -- Purpose: Generate output write data when ECC is enable -- (use fault vector). -- (N:0) --------------------------------------------------------------------------- GEN_W_ECC : if C_ECC = 1 generate begin bram_wrdata_a_int (i) <= WrData (i) xor FaultInjectData (i); end generate GEN_W_ECC; end generate GEN_WRDATA; --------------------------------------------------------------------------- -- *** AXI Write Response Channel Interface *** --------------------------------------------------------------------------- -- No BID support (wrap around in Interconnect) -- In AXI-Lite, no WLAST assertion -- Drive constant value out on BRESP -- axi_bresp_int <= RESP_OKAY; axi_bresp_int <= RESP_SLVERR when (C_ECC = 1 and UE_Q = '1') else RESP_OKAY; --------------------------------------------------------------------------- -- Implement BVALID with counter regardless of IP configuration. -- -- BVALID counter to track the # of required BVALID/BREADY handshakes -- needed to occur on the AXI interface. Based on early and seperate -- AWVALID/AWREADY and WVALID/WREADY handshake exchanges. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt <= (others => '0'); -- Ensure we only increment counter wyhen BREADY is not asserted elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1); -- Ensure that we only decrement when SM is not incrementing elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1); else bvalid_cnt <= bvalid_cnt; end if; end if; end process REG_BVALID_CNT; bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt /= "000") else '0'; -- Replace BVALID output register -- Assert BVALID as long as BVALID counter /= zero REG_BVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (bvalid_cnt = "001" and bvalid_cnt_dec = '1') then axi_bvalid_int <= '0'; elsif (bvalid_cnt /= "000") then axi_bvalid_int <= '1'; else axi_bvalid_int <= '0'; end if; end if; end process REG_BVALID; --------------------------------------------------------------------------- -- *** AXI Read Data Channel Interface *** --------------------------------------------------------------------------- -- For reductions on AXI-Lite, drive constant value on RESP axi_rresp_int <= RESP_OKAY; --------------------------------------------------------------------------- -- Generate: GEN_R -- Purpose: Generate AXI R channel outputs when ECC is disabled. -- No register delay on AXI_RVALID and AXI_RLAST. --------------------------------------------------------------------------- GEN_R: if C_ECC = 0 generate begin --------------------------------------------------------------------------- -- AXI_RVALID Output Register -- -- Set AXI_RVALID when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rvalid_int <= '0'; elsif (axi_rvalid_set = '1') then axi_rvalid_int <= '1'; else axi_rvalid_int <= axi_rvalid_int; end if; end if; end process REG_RVALID; --------------------------------------------------------------------------- -- AXI_RLAST Output Register -- -- Set AXI_RLAST when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RLAST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rlast_int <= '0'; elsif (axi_rlast_set = '1') then axi_rlast_int <= '1'; else axi_rlast_int <= axi_rlast_int; end if; end if; end process REG_RLAST; end generate GEN_R; --------------------------------------------------------------------------- -- Generate: GEN_R_ECC -- Purpose: Generate AXI R channel outputs when ECC is enabled. -- Must use registered delayed control signals for RLAST -- and RVALID to align with register inclusion for corrected -- read data in ECC logic. --------------------------------------------------------------------------- GEN_R_ECC: if C_ECC = 1 generate begin --------------------------------------------------------------------------- -- AXI_RVALID Output Register -- -- Set AXI_RVALID when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rvalid_int <= '0'; elsif (axi_rvalid_set_r = '1') then axi_rvalid_int <= '1'; else axi_rvalid_int <= axi_rvalid_int; end if; end if; end process REG_RVALID; --------------------------------------------------------------------------- -- AXI_RLAST Output Register -- -- Set AXI_RLAST when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RLAST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then -- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1' -- May be able to remove from this if clause (and simplify logic) axi_rlast_int <= '0'; elsif (axi_rlast_set_r = '1') then axi_rlast_int <= '1'; else axi_rlast_int <= axi_rlast_int; end if; end if; end process REG_RLAST; end generate GEN_R_ECC; --------------------------------------------------------------------------- -- -- Generate AXI bus read data. No register. Pass through -- read data from BRAM. Determine source on single port -- vs. dual port configuration. -- --------------------------------------------------------------------------- ----------------------------------------------------------------------- -- Generate: RDATA_NO_ECC -- Purpose: Define port A/B from BRAM on AXI_RDATA when ECC disabled. ----------------------------------------------------------------------- RDATA_NO_ECC: if (C_ECC = 0) generate begin AXI_RDATA <= axi_rdata_int; ----------------------------------------------------------------------- -- Generate: GEN_RDATA_SNG_PORT -- Purpose: Source of read data: Port A in single port configuration. ----------------------------------------------------------------------- GEN_RDATA_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A(C_S_AXI_DATA_WIDTH-1 downto 0); end generate GEN_RDATA_SNG_PORT; ----------------------------------------------------------------------- -- Generate: GEN_RDATA_DUAL_PORT -- Purpose: Source of read data: Port B in dual port configuration. ----------------------------------------------------------------------- GEN_RDATA_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0); end generate GEN_RDATA_DUAL_PORT; end generate RDATA_NO_ECC; ----------------------------------------------------------------------- -- Generate: RDATA_W_ECC -- Purpose: Connect AXI_RDATA from ECC module when ECC enabled. ----------------------------------------------------------------------- RDATA_W_ECC: if (C_ECC = 1) generate subtype syndrome_bits is std_logic_vector (0 to 6); type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits; constant correct_data_table : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); begin -- Logic common to either type of ECC encoding/decoding -- Renove bit reversal on AXI_RDATA output. AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr; CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0); -- Remove GEN_RDATA that was doing bit reversal. -- Read back data is registered prior to any single bit error correction. REG_RDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rdata_int <= (others => '0'); else axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1); end if; end if; end process REG_RDATA; --------------------------------------------------------------------------- -- Generate: RDATA_W_HAMMING -- Purpose: Add generate statement for Hamming Code ECC algorithm -- specific logic. --------------------------------------------------------------------------- RDATA_W_HAMMING: if C_ECC_TYPE = 0 generate begin -- Move correct_one_bit logic to output side of AXI_RDATA output register. -- Improves timing by balancing logic on both sides of pipeline stage. -- Utilizing registers in AXI interconnect makes this feasible. --------------------------------------------------------------------------- -- Register ECC syndrome value to correct any single bit errors -- post-register on AXI read data. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_reg <= Syndrome; syndrome_4_reg <= Syndrome_4; syndrome_6_reg <= Syndrome_6; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl -- w/ balanced pipeline stage) before correct_one_bit module. syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3); PARITY_CHK4: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (4) ); -- [out std_logic] syndrome_reg_i (5) <= syndrome_reg (5); PARITY_CHK6: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (6) ); -- [out std_logic] --------------------------------------------------------------------------- -- Generate: GEN_CORR_32 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_32: for i in 0 to C_S_AXI_DATA_WIDTH-1 generate begin --------------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_32 -- Description: Generate ECC bits for checking data read from BRAM. --------------------------------------------------------------------------- CORR_ONE_BIT_32: entity work.correct_one_bit generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table (i)) port map ( DIn => axi_rdata_int (31-i), Syndrome => syndrome_reg_i, DCorr => axi_rdata_int_corr (31-i)); end generate GEN_CORR_32; end generate RDATA_W_HAMMING; -- Hsiao ECC done in seperate generate statement (GEN_HSIAO_ECC) end generate RDATA_W_ECC; --------------------------------------------------------------------------- -- Main AXI-Lite State Machine -- -- Description: Central processing unit for AXI-Lite write and read address -- channel interface handling and handshaking. -- Handles all arbitration between write and read channels -- to utilize single port to BRAM -- -- Outputs: axi_wready_int Registered -- axi_arready_reg Registered (used in ECC configurations) -- bvalid_cnt_inc Combinatorial -- axi_rvalid_set Combinatorial -- axi_rlast_set Combinatorial -- bram_en_a_cmb Combinatorial -- bram_en_b_cmb Combinatorial -- bram_we_a_int Combinatorial -- -- -- LITE_SM_CMB_PROCESS: Combinational process to determine next state. -- LITE_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- LITE_SM_CMB_PROCESS: process ( AXI_AWVALID, AXI_WVALID, AXI_WSTRB, AXI_ARVALID, AXI_RREADY, bvalid_cnt, axi_rvalid_int, lite_sm_cs ) begin -- assign default values for state machine outputs lite_sm_ns <= lite_sm_cs; axi_wready_cmb <= '0'; axi_arready_cmb <= '0'; bvalid_cnt_inc <= '0'; axi_rvalid_set <= '0'; axi_rlast_set <= '0'; bram_en_a_cmb <= '0'; bram_en_b_cmb <= '0'; bram_we_a_int <= (others => '0'); case lite_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- AXI Interconnect will only issue AWVALID OR ARVALID -- at a time. In the case when the core is attached -- to another AXI master IP, arbitrate between read -- and write operation. Read operation will always win. if (AXI_ARVALID = '1') then lite_sm_ns <= RD_DATA; -- Initiate BRAM read transfer -- For single port BRAM, use Port A -- For dual port BRAM, use Port B if (C_SINGLE_PORT_BRAM = 1) then bram_en_a_cmb <= '1'; else bram_en_b_cmb <= '1'; end if; bram_we_a_int <= (others => '0'); -- RVALID to be asserted in next clock cycle -- Only 1 clock cycle latency on reading data from BRAM axi_rvalid_set <= '1'; -- Due to single data beat with AXI-Lite -- Assert RLAST on AXI axi_rlast_set <= '1'; -- Only in ECC configurations -- Must assert ARREADY here (no pre-assertion) if (C_ECC = 1) then axi_arready_cmb <= '1'; end if; -- Write operations are lower priority than reads -- when an AXI master asserted both operations simultaneously. elsif (AXI_AWVALID = '1') and (AXI_WVALID = '1') and (bvalid_cnt /= "111") then -- Initiate BRAM write transfer bram_en_a_cmb <= '1'; -- Always perform a read-modify-write sequence with ECC is enabled. if (C_ECC = 1) then lite_sm_ns <= RMW_RD_DATA; -- Disable Port A write enables bram_we_a_int <= (others => '0'); else -- Non ECC operation or an ECC full 32-bit word write -- Assert acknowledge of data & address on AXI. -- Wait to assert AWREADY and WREADY in ECC designs. axi_wready_cmb <= '1'; -- Increment counter to track # of required BVALID responses. bvalid_cnt_inc <= '1'; lite_sm_ns <= SNG_WR_DATA; bram_we_a_int <= AXI_WSTRB; end if; end if; ------------------------- SNG_WR_DATA State ------------------------- when SNG_WR_DATA => -- With early assertion of ARREADY, the SM -- must be able to accept a read address at any clock cycle. -- Check here for active ARVALID and directly handle read -- and do not proceed back to IDLE (no empty clock cycle in which -- read address may be missed). if (AXI_ARVALID = '1') and (C_ECC = 0) then lite_sm_ns <= RD_DATA; -- Initiate BRAM read transfer -- For single port BRAM, use Port A -- For dual port BRAM, use Port B if (C_SINGLE_PORT_BRAM = 1) then bram_en_a_cmb <= '1'; else bram_en_b_cmb <= '1'; end if; bram_we_a_int <= (others => '0'); -- RVALID to be asserted in next clock cycle -- Only 1 clock cycle latency on reading data from BRAM axi_rvalid_set <= '1'; -- Due to single data beat with AXI-Lite -- Assert RLAST on AXI axi_rlast_set <= '1'; -- Only in ECC configurations -- Must assert ARREADY here (no pre-assertion) -- Pre-assertion of ARREADY is only for non ECC configurations. if (C_ECC = 1) then axi_arready_cmb <= '1'; end if; else lite_sm_ns <= IDLE; end if; ---------------------------- RD_DATA State --------------------------- when RD_DATA => -- Data is presented to AXI bus -- Wait for acknowledgment to process any next transfers -- RVALID may not be asserted as we transition into this state. if (AXI_RREADY = '1') and (axi_rvalid_int = '1') then lite_sm_ns <= IDLE; end if; ------------------------- RMW_RD_DATA State ------------------------- when RMW_RD_DATA => lite_sm_ns <= RMW_MOD_DATA; ------------------------- RMW_MOD_DATA State ------------------------- when RMW_MOD_DATA => lite_sm_ns <= RMW_WR_DATA; -- Hold off on assertion of WREADY and AWREADY until -- here, so no pipeline registers necessary. -- Assert acknowledge of data & address on AXI axi_wready_cmb <= '1'; -- Increment counter to track # of required BVALID responses. -- Able to assert this signal early, then BVALID counter -- will get incremented in the next clock cycle when WREADY -- is asserted. bvalid_cnt_inc <= '1'; ------------------------- RMW_WR_DATA State ------------------------- when RMW_WR_DATA => -- Initiate BRAM write transfer bram_en_a_cmb <= '1'; -- Enable all WEs to BRAM bram_we_a_int <= (others => '1'); -- Complete write operation lite_sm_ns <= IDLE; --coverage off ------------------------------ Default ---------------------------- when others => lite_sm_ns <= IDLE; --coverage on end case; end process LITE_SM_CMB_PROCESS; --------------------------------------------------------------------------- LITE_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then lite_sm_cs <= IDLE; axi_wready_int <= '0'; axi_arready_reg <= '0'; axi_rvalid_set_r <= '0'; axi_rlast_set_r <= '0'; else lite_sm_cs <= lite_sm_ns; axi_wready_int <= axi_wready_cmb; axi_arready_reg <= axi_arready_cmb; axi_rvalid_set_r <= axi_rvalid_set; axi_rlast_set_r <= axi_rlast_set; end if; end if; end process LITE_SM_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** ECC Logic *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_ECC -- Purpose: Generate BRAM ECC write data and check ECC on read operations. -- Create signals to update ECC registers (lite_ecc_reg module interface). -- --------------------------------------------------------------------------- GEN_ECC: if C_ECC = 1 generate constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite) signal WrECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0); -- Specific to BRAM data width signal WrECC_i : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); signal wrdata_i : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); signal AXI_WDATA_Q : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); signal AXI_WSTRB_Q : std_logic_vector ((C_S_AXI_DATA_WIDTH/8 - 1) downto 0); signal bram_din_a_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width signal bram_rddata_in : std_logic_vector (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); subtype syndrome_bits is std_logic_vector (0 to 6); type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits; constant correct_data_table : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); type bool_array is array (natural range 0 to 6) of boolean; constant inverted_bit : bool_array := (false,false,true,false,true,false,false); begin -- Read on Port A -- or any operation on Port B (it will be read only). BRAM_Addr_En <= '1' when (bram_en_a_int = '1' and bram_we_a_int = "00000") or (bram_en_b_int = '1') else '0'; -- BRAM_WE generated from SM -- Remember byte write enables one clock cycle to properly mux bytes to write, -- with read data in read/modify write operation -- Write in Read/Write always 1 cycle after Read REG_RMW_SIGS : process (S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Add reset values if (S_AXI_AResetn = C_RESET_ACTIVE) then RdModifyWr_Check <= '0'; RdModifyWr_Modify <= '0'; RdModifyWr_Write <= '0'; else RdModifyWr_Check <= RdModifyWr_Read; RdModifyWr_Modify <= RdModifyWr_Check; RdModifyWr_Write <= RdModifyWr_Modify; end if; end if; end process REG_RMW_SIGS; -- v1.03a -- Delay assertion of WREADY to minimize registers in core. -- Use SM transition to RMW "read" to assert this signal. RdModifyWr_Read <= '1' when (lite_sm_ns = RMW_RD_DATA) else '0'; -- Remember write data one cycle to be available after read has been completed in a -- read/modify write operation STORE_WRITE_DBUS : process (S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then AXI_WDATA_Q <= (others => '0'); AXI_WSTRB_Q <= (others => '0'); -- v1.03a -- With the delay assertion of WREADY, use WVALID -- to register in WDATA and WSTRB signals. elsif (AXI_WVALID = '1') then AXI_WDATA_Q <= AXI_WDATA; AXI_WSTRB_Q <= AXI_WSTRB; end if; end if; end process STORE_WRITE_DBUS; wrdata_i <= AXI_WDATA_Q when RdModifyWr_Modify = '1' else AXI_WDATA; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_WRDATA_CMB -- Purpose: Replace manual signal assignment for WrData_cmb with -- generate funtion. -- -- Ensure correct byte swapping occurs with -- CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) assignment -- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0). -- -- AXI_WSTRB_Q (C_S_AXI_DATA_WIDTH_BYTES-1 downto 0) matches -- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0). -- ------------------------------------------------------------------------ GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate begin WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= wrdata_i ((((i+1)*8)-1) downto i*8) when (RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1') else CorrectedRdData ( (C_S_AXI_DATA_WIDTH - ((i+1)*8)) to (C_S_AXI_DATA_WIDTH - (i*8) - 1) ); end generate GEN_WRDATA_CMB; REG_WRDATA : process (S_AXI_AClk) is begin -- Remove reset value to minimize resources & improve timing if (S_AXI_AClk'event and S_AXI_AClk = '1') then WrData <= WrData_cmb; end if; end process REG_WRDATA; ------------------------------------------------------------------------ -- New assignment of ECC bits to BRAM write data outside generate -- blocks. Same signal assignment regardless of ECC type. bram_wrdata_a_int (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) <= '0'; bram_wrdata_a_int ((C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH - 1) downto C_S_AXI_DATA_WIDTH) <= WrECC xor FaultInjectECC; ------------------------------------------------------------------------ -- No need to use RdModifyWr_Write in the data path. -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. ------------------------------------------------------------------------ GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate begin --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_WR_32 -- Description: Generate ECC bits for writing into BRAM. -- WrData (N:0) --------------------------------------------------------------------------- CHK_HANDLER_WR_32: entity work.checkbit_handler generic map ( C_ENCODE => true, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( DataIn => WrData, -- [in std_logic_vector(0 to 31)] CheckIn => null7, -- [in std_logic_vector(0 to 6)] CheckOut => WrECC, -- [out std_logic_vector(0 to 6)] Syndrome_4 => open, -- [out std_logic_vector(0 to 1)] Syndrome_6 => open, -- [out std_logic_vector(0 to 5)] Syndrome => open, -- [out std_logic_vector(0 to 6)] Enable_ECC => '1', -- [in std_logic] Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open ); -- [out std_logic] --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_RD_32 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- CHK_HANDLER_RD_32: entity work.checkbit_handler generic map ( C_ENCODE => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( -- DataIn (8:39) -- CheckIn (1:7) -- Bit swapping done at port level on checkbit_handler (31:0) & (6:0) DataIn => bram_din_a_i (C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_S_AXI_DATA_WIDTH), -- [in std_logic_vector(8 to 39)] CheckIn => bram_din_a_i (1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(1 to 7)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)] Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] -- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate -- of AXI RDATA output register logic to use registered syndrome value. end generate GEN_HAMMING_ECC; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. ------------------------------------------------------------------------ GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate constant CODE_WIDTH : integer := C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH; constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; type type_int0 is array (C_S_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0); signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0); signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0); signal ecc_rddata_r : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); signal h_matrix : type_int0; signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0); signal flip_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); begin ---------------------- Hsiao ECC Write Logic ---------------------- -- Instantiate ecc_gen module, generated from MIG ECC_GEN_HSIAO: entity work.ecc_gen generic map ( code_width => CODE_WIDTH, ecc_width => ECC_WIDTH, data_width => C_S_AXI_DATA_WIDTH ) port map ( -- Output h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); -- Merge muxed rd/write data to gen HSIAO_ECC: process (h_rows, WrData) constant DQ_WIDTH : integer := CODE_WIDTH; variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH); begin -- Loop to generate all ECC bits for k in 0 to ECC_WIDTH - 1 loop ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_S_AXI_DATA_WIDTH - 1 downto 0) and h_rows (k * CODE_WIDTH + C_S_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH))); end loop; WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH); end process HSIAO_ECC; ---------------------- Hsiao ECC Read Logic ----------------------- GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate begin syndrome_ns (m) <= REDUCTION_XOR ( bram_rddata_in (CODE_WIDTH-1 downto 0) and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH))); end generate GEN_RD_ECC; -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_r <= syndrome_ns; -- Replicate BRAM read back data register for Hamming ECC ecc_rddata_r <= bram_rddata_in (C_S_AXI_DATA_WIDTH-1 downto 0); end if; end process REG_SYNDROME; -- Reconstruct H-matrix H_COL: for n in 0 to C_S_AXI_DATA_WIDTH - 1 generate begin H_BIT: for p in 0 to ECC_WIDTH - 1 generate begin h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n); end generate H_BIT; end generate H_COL; GEN_FLIP_BIT: for r in 0 to C_S_AXI_DATA_WIDTH - 1 generate begin flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r); end generate GEN_FLIP_BIT; axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0) <= ecc_rddata_r (C_S_AXI_DATA_WIDTH-1 downto 0) xor flip_bits (C_S_AXI_DATA_WIDTH-1 downto 0); Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); end generate GEN_HSIAO_ECC; -- Capture correctable/uncorrectable error from BRAM read. -- Either during RMW of write operation or during BRAM read. CORR_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if RdModifyWr_Modify = '1' or ((Enable_ECC = '1') and (axi_rvalid_int = '1' and AXI_RREADY = '1')) then -- Capture error signals CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CORR_REG; -- Register CE and UE flags to register block. Sl_CE <= CE_Q; Sl_UE <= UE_Q; --------------------------------------------------------------------------- -- Generate: GEN_DIN_A -- Purpose: Generate BRAM read data vector assignment to always be from Port A -- in a single port BRAM configuration. -- Map BRAM_RdData_A (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. --------------------------------------------------------------------------- GEN_DIN_A: if C_SINGLE_PORT_BRAM = 1 generate begin --------------------------------------------------------------------------- -- Generate: GEN_DIN_A_HAMMING -- Purpose: Standard input for Hamming ECC code generation. -- MSB '0' is removed in port mapping to checkbit_handler module. --------------------------------------------------------------------------- GEN_DIN_A_HAMMING: if C_ECC_TYPE = 0 generate begin bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); end generate GEN_DIN_A_HAMMING; --------------------------------------------------------------------------- -- Generate: GEN_DIN_A_HSIAO -- Purpose: For Hsiao ECC implementation configurations. -- Remove MSB '0' on 32-bit implementation with fixed -- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix). --------------------------------------------------------------------------- GEN_DIN_A_HSIAO: if C_ECC_TYPE = 1 generate begin bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0); end generate GEN_DIN_A_HSIAO; end generate GEN_DIN_A; --------------------------------------------------------------------------- -- Generate: GEN_DIN_B -- Purpose: Generate BRAM read data vector assignment in a dual port -- configuration to be either from Port B, or from Port A in a -- read-modify-write sequence. -- Map BRAM_RdData_A/B (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. --------------------------------------------------------------------------- GEN_DIN_B: if C_SINGLE_PORT_BRAM = 0 generate begin --------------------------------------------------------------------------- -- Generate: GEN_DIN_B_HAMMING -- Purpose: Standard input for Hamming ECC code generation. -- MSB '0' is removed in port mapping to checkbit_handler module. --------------------------------------------------------------------------- GEN_DIN_B_HAMMING: if C_ECC_TYPE = 0 generate begin bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (RdModifyWr_Check = '1') else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); end generate GEN_DIN_B_HAMMING; --------------------------------------------------------------------------- -- Generate: GEN_DIN_B_HSIAO -- Purpose: For Hsiao ECC implementation configurations. -- Remove MSB '0' on 32-bit implementation with fixed -- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix). --------------------------------------------------------------------------- GEN_DIN_B_HSIAO: if C_ECC_TYPE = 1 generate begin bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) when (RdModifyWr_Check = '1') else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0); end generate GEN_DIN_B_HSIAO; end generate GEN_DIN_B; -- Map data vector from BRAM to use in correct_one_bit module with -- register syndrome (post AXI RDATA register). UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_S_AXI_DATA_WIDTH-1) when (C_ECC_TYPE = 0) else bram_rddata_in(C_S_AXI_DATA_WIDTH-1 downto 0); end generate GEN_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** BRAM Interface Signals *** --------------------------------------------------------------------------- -- With AXI-LITE no narrow operations are allowed. -- AXI_WSTRB is ignored and all byte lanes are written. bram_en_a_int <= bram_en_a_cmb; -- BRAM_En_A <= bram_en_a_int; -- DV regression failure with reset -- 7/7/11 BRAM_En_A <= '0' when (S_AXI_AResetn = C_RESET_ACTIVE) else bram_en_a_int; ----------------------------------------------------------------------- -- Generate: GEN_BRAM_EN_DUAL_PORT -- Purpose: Only generate Port B BRAM enable signal when -- configured for dual port BRAM. ----------------------------------------------------------------------- GEN_BRAM_EN_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin bram_en_b_int <= bram_en_b_cmb; BRAM_En_B <= bram_en_b_int; end generate GEN_BRAM_EN_DUAL_PORT; ----------------------------------------------------------------------- -- Generate: GEN_BRAM_EN_SNG_PORT -- Purpose: Drive default for unused BRAM Port B in single -- port BRAM configuration. ----------------------------------------------------------------------- GEN_BRAM_EN_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_En_B <= '0'; end generate GEN_BRAM_EN_SNG_PORT; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WE -- Purpose: BRAM WE generate process -- One WE per 8-bits of BRAM data. --------------------------------------------------------------------------- GEN_BRAM_WE: for i in (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH)/8-1 downto 0 generate begin BRAM_WE_A (i) <= bram_we_a_int (i); end generate GEN_BRAM_WE; --------------------------------------------------------------------------- BRAM_Addr_A <= BRAM_Addr_A_i; BRAM_Addr_B <= BRAM_Addr_B_i; --------------------------------------------------------------------------- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr_A_i (i) <= '0'; BRAM_Addr_B_i (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. --------------------------------------------------------------------------- GEN_U_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr_A_i (i) <= bram_addr_a_int (i); ----------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR_DUAL_PORT -- Purpose: Only generate Port B BRAM address when -- configured for dual port BRAM. ----------------------------------------------------------------------- GEN_BRAM_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate begin BRAM_Addr_B_i (i) <= bram_addr_b_int (i); end generate GEN_BRAM_ADDR_DUAL_PORT; ----------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR_SNG_PORT -- Purpose: Drive default for unused BRAM Port B in single -- port BRAM configuration. ----------------------------------------------------------------------- GEN_BRAM_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_Addr_B_i (i) <= '0'; end generate GEN_BRAM_ADDR_SNG_PORT; end generate GEN_U_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WRDATA -- Purpose: Generate BRAM Write Data for Port A. --------------------------------------------------------------------------- -- When C_ECC = 0, C_ECC_WIDTH = 0 (at top level HDL) GEN_BRAM_WRDATA: for i in (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto 0 generate begin BRAM_WrData_A (i) <= bram_wrdata_a_int (i); end generate GEN_BRAM_WRDATA; BRAM_WrData_B <= (others => '0'); BRAM_WE_B <= (others => '0'); --------------------------------------------------------------------------- end architecture implementation; ------------------------------------------------------------------------------- -- sng_port_arb.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: sng_port_arb.vhd -- -- Description: This file is the top level arbiter for full AXI4 mode -- when configured in a single port mode to BRAM. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 4/11/2011 v1.03a -- ~~~~~~ -- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations -- when WREADY is to be a registered output. With a seperate FIFO for BID, -- ensure arbitration does not get more than 8 ahead of BID responses. A -- value of 8 is the max of the BVALID counter. -- ^^^^^^ -- -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------ entity sng_port_arb is generic ( C_S_AXI_ADDR_WIDTH : integer := 32 -- Width of AXI address bus (in bits) ); port ( -- *** AXI Clock and Reset *** S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; -- *** AXI Write Address Channel Signals (AW) *** AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); AXI_AWVALID : in std_logic; AXI_AWREADY : out std_logic := '0'; -- *** AXI Read Address Channel Signals (AR) *** AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); AXI_ARVALID : in std_logic; AXI_ARREADY : out std_logic := '0'; -- *** Write Channel Interface Signals *** Arb2AW_Active : out std_logic := '0'; AW2Arb_Busy : in std_logic; AW2Arb_Active_Clr : in std_logic; AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0); -- *** Read Channel Interface Signals *** Arb2AR_Active : out std_logic := '0'; AR2Arb_Active_Clr : in std_logic ); end entity sng_port_arb; ------------------------------------------------------------------------------- architecture implementation of sng_port_arb is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant ARB_WR : std_logic := '0'; constant ARB_RD : std_logic := '1'; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Write & Read Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type ARB_SM_TYPE is ( IDLE, RD_DATA, WR_DATA ); signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE; signal axi_awready_cmb : std_logic := '0'; signal axi_awready_int : std_logic := '0'; signal axi_arready_cmb : std_logic := '0'; signal axi_arready_int : std_logic := '0'; signal last_arb_won_cmb : std_logic := '0'; signal last_arb_won : std_logic := '0'; signal aw_active_cmb : std_logic := '0'; signal aw_active : std_logic := '0'; signal ar_active_cmb : std_logic := '0'; signal ar_active : std_logic := '0'; ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- *** AXI Output Signals *** --------------------------------------------------------------------------- -- AXI Write Address Channel Output Signals AXI_AWREADY <= axi_awready_int; -- AXI Read Address Channel Output Signals AXI_ARREADY <= axi_arready_int; --------------------------------------------------------------------------- -- *** AXI Write Address Channel Interface *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** AXI Read Address Channel Interface *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** Internal Arbitration Interface *** --------------------------------------------------------------------------- Arb2AW_Active <= aw_active; Arb2AR_Active <= ar_active; --------------------------------------------------------------------------- -- Main Arb State Machine -- -- Description: Main arbitration logic when AXI BRAM controller -- configured in a single port BRAM mode. -- Module is instantiated when C_SINGLE_PORT_BRAM = 1. -- -- Outputs: last_arb_won Registered -- aw_active Registered -- ar_active Registered -- axi_awready_int Registered -- axi_arready_int Registered -- -- -- ARB_SM_CMB_PROCESS: Combinational process to determine next state. -- ARB_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- ARB_SM_CMB_PROCESS: process ( AXI_AWVALID, AXI_ARVALID, AW2Arb_BVALID_Cnt, AW2Arb_Busy, AW2Arb_Active_Clr, AR2Arb_Active_Clr, last_arb_won, aw_active, ar_active, arb_sm_cs ) begin -- assign default values for state machine outputs arb_sm_ns <= arb_sm_cs; axi_awready_cmb <= '0'; axi_arready_cmb <= '0'; last_arb_won_cmb <= last_arb_won; aw_active_cmb <= aw_active; ar_active_cmb <= ar_active; case arb_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Check for valid read operation -- Reads take priority over AW traffic (if both asserted) -- 4/11 -- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then -- 4/11 -- Add BVALID counter to AW arbitration. -- Since this is arbitration to read, no need for BVALID counter. if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and --(AW2Arb_BVALID_Cnt /= "111")) or ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then -- Read wins arbitration arb_sm_ns <= RD_DATA; axi_arready_cmb <= '1'; last_arb_won_cmb <= ARB_RD; ar_active_cmb <= '1'; -- Write operations are lower priority than reads -- when an AXI master asserted both operations simultaneously. -- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and (AW2Arb_BVALID_Cnt /= "111") then -- Write wins arbitration arb_sm_ns <= WR_DATA; axi_awready_cmb <= '1'; last_arb_won_cmb <= ARB_WR; aw_active_cmb <= '1'; end if; ------------------------- WR_DATA State ------------------------- when WR_DATA => -- Wait for write operation to complete if (AW2Arb_Active_Clr = '1') then aw_active_cmb <= '0'; -- Check early for pending read (to save clock cycle -- in transitioning back to IDLE) if (AXI_ARVALID = '1') then -- Read wins arbitration arb_sm_ns <= RD_DATA; axi_arready_cmb <= '1'; last_arb_won_cmb <= ARB_RD; ar_active_cmb <= '1'; -- Note: if timing paths occur b/w wr_chnl data SM -- and here, remove this clause to check for early -- arbitration on a read operation. else arb_sm_ns <= IDLE; end if; end if; ---------------------------- RD_DATA State --------------------------- when RD_DATA => -- Wait for read operation to complete if (AR2Arb_Active_Clr = '1') then ar_active_cmb <= '0'; -- Check early for pending write operation (to save clock cycle -- in transitioning back to IDLE) -- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and (AW2Arb_BVALID_Cnt /= "111") then -- Write wins arbitration arb_sm_ns <= WR_DATA; axi_awready_cmb <= '1'; last_arb_won_cmb <= ARB_WR; aw_active_cmb <= '1'; -- Note: if timing paths occur b/w rd_chnl data SM -- and here, remove this clause to check for early -- arbitration on a write operation. -- Check early for a pending back-to-back read operation elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then -- Read wins arbitration arb_sm_ns <= RD_DATA; axi_arready_cmb <= '1'; last_arb_won_cmb <= ARB_RD; ar_active_cmb <= '1'; else arb_sm_ns <= IDLE; end if; end if; --coverage off ------------------------------ Default ---------------------------- when others => arb_sm_ns <= IDLE; --coverage on end case; end process ARB_SM_CMB_PROCESS; --------------------------------------------------------------------------- ARB_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then arb_sm_cs <= IDLE; last_arb_won <= ARB_WR; aw_active <= '0'; ar_active <= '0'; axi_awready_int <='0'; axi_arready_int <='0'; else arb_sm_cs <= arb_sm_ns; last_arb_won <= last_arb_won_cmb; aw_active <= aw_active_cmb; ar_active <= ar_active_cmb; axi_awready_int <= axi_awready_cmb; axi_arready_int <= axi_arready_cmb; end if; end if; end process ARB_SM_REG_PROCESS; --------------------------------------------------------------------------- end architecture implementation; ------------------------------------------------------------------------------- -- ua_narrow.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: ua_narrow.vhd -- -- Description: Creates a narrow burst count load value when an operation -- is an unaligned narrow WRAP or INCR burst type. Used by -- I_NARROW_CNT module. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 2/4/2011 v1.03a -- ~~~~~~ -- Edit for scalability and support of 512 and 1024-bit data widths. -- ^^^^^^ -- JLJ 2/8/2011 v1.03a -- ~~~~~~ -- Update bit vector usage of address LSB for calculating ua_narrow_load. -- Add axi_bram_ctrl_funcs package inclusion. -- ^^^^^^ -- JLJ 3/1/2011 v1.03a -- ~~~~~~ -- Fix XST handling for DIV functions. Create seperate process when -- divisor is not constant and a power of two. -- ^^^^^^ -- JLJ 3/2/2011 v1.03a -- ~~~~~~ -- Update range of integer signals. -- ^^^^^^ -- JLJ 3/4/2011 v1.03a -- ~~~~~~ -- Remove use of local function, Create_Size_Max. -- ^^^^^^ -- JLJ 3/11/2011 v1.03a -- ~~~~~~ -- Remove C_AXI_DATA_WIDTH generate statments. -- ^^^^^^ -- JLJ 3/14/2011 v1.03a -- ~~~~~~ -- Update ua_narrow_load signal assignment to pass simulations & XST. -- ^^^^^^ -- JLJ 3/15/2011 v1.03a -- ~~~~~~ -- Update multiply function on signal, ua_narrow_wrap_gt_width, -- for timing path improvements. Replace with left shift operation. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. And general code clean-up. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity ua_narrow is generic ( C_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_BRAM_ADDR_ADJUST_FACTOR : integer := 32; -- Adjust BRAM address width based on C_AXI_DATA_WIDTH C_NARROW_BURST_CNT_LEN : integer := 4 -- Size of narrow burst counter ); port ( curr_wrap_burst : in std_logic; curr_incr_burst : in std_logic; bram_addr_ld_en : in std_logic; curr_axlen : in std_logic_vector (7 downto 0) := (others => '0'); curr_axsize : in std_logic_vector (2 downto 0) := (others => '0'); curr_axaddr_lsb : in std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0'); curr_ua_narrow_wrap : out std_logic; curr_ua_narrow_incr : out std_logic; ua_narrow_load : out std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0') ); end entity ua_narrow; ------------------------------------------------------------------------------- architecture implementation of ua_narrow is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; -- AXI Size Constants -- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte -- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes -- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM -- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM -- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM -- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM -- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM -- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM -- Determine max value of ARSIZE based on the AXI data width. -- Use function in axi_bram_ctrl_funcs package. constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH); -- Determine the number of bytes based on the AXI data width. constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8; constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES); -- Use constant to compare when LSB of ADDR is equal to zero. constant axaddr_lsb_zero : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0'); -- 8d = size of AxLEN vector constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8; -- Convert # of data bytes for AXI data bus into an unsigned vector (C_MAX_LSHIFT_SIZE:0). constant C_AXI_DATA_WIDTH_BYTES_UNSIGNED : unsigned (C_MAX_LSHIFT_SIZE downto 0) := to_unsigned (C_AXI_DATA_WIDTH_BYTES, C_MAX_LSHIFT_SIZE+1); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal ua_narrow_wrap_gt_width : std_logic := '0'; signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0'); signal curr_axsize_int : integer := 0; signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0'); signal curr_axlen_unsigned_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d signal bytes_per_addr : integer := 1; -- range 1 to 128 := 1; signal size_plus_lsb : integer range 1 to 256 := 1; signal narrow_addr_offset : integer := 1; ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin -- v1.03a -- Added for narrow INCR bursts with UA addresses -- Check if burst is a) INCR type, -- b) a narrow burst (SIZE = full width of bus) -- c) LSB of address is non zero curr_ua_narrow_incr <= '1' when (curr_incr_burst = '1') and (curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and (curr_axaddr_lsb /= axaddr_lsb_zero) and (bram_addr_ld_en = '1') else '0'; -- v1.03a -- Detect narrow WRAP bursts -- Detect if the operation is a) WRAP type, -- b) a narrow burst (SIZE = full width of bus) -- c) LSB of address is non zero -- d) complete size of WRAP is larger than width of BRAM curr_ua_narrow_wrap <= '1' when (curr_wrap_burst = '1') and (curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and (curr_axaddr_lsb /= axaddr_lsb_zero) and (bram_addr_ld_en = '1') and (ua_narrow_wrap_gt_width = '1') else '0'; --------------------------------------------------------------------------- -- v1.03a -- Check condition if narrow burst wraps within the size of the BRAM width. -- Check if size * length > BRAM width in bytes. -- -- When asserted = '1', means that narrow burst counter is not preloaded early, -- the BRAM burst will be contained within the BRAM data width. curr_axsize_unsigned <= unsigned (curr_axsize); curr_axsize_int <= to_integer (curr_axsize_unsigned); curr_axlen_unsigned <= unsigned (curr_axlen); -- Original logic with multiply function. -- -- ua_narrow_wrap_gt_width <= '0' when (((2**(to_integer (curr_axsize_unsigned))) * -- unsigned (curr_axlen (7 downto 0))) -- < C_AXI_DATA_WIDTH_BYTES) -- else '1'; -- Replace with left shift operation of AxLEN. -- Replace multiply of AxLEN * AxSIZE with a left shift function. LEN_LSHIFT: process (curr_axlen_unsigned, curr_axsize_int) begin for i in C_MAX_LSHIFT_SIZE downto 0 loop if (i >= curr_axsize_int + 8) then curr_axlen_unsigned_lshift (i) <= '0'; elsif (i >= curr_axsize_int) then curr_axlen_unsigned_lshift (i) <= curr_axlen_unsigned (i - curr_axsize_int); else curr_axlen_unsigned_lshift (i) <= '0'; end if; end loop; end process LEN_LSHIFT; -- Final result. ua_narrow_wrap_gt_width <= '0' when (curr_axlen_unsigned_lshift < C_AXI_DATA_WIDTH_BYTES_UNSIGNED) else '1'; --------------------------------------------------------------------------- -- v1.03a -- For narrow burst transfer, provides the number of bytes per address -- XST does not support divisors that are not constants AND powers of two. -- Create process to create a fixed value for divisor. -- Replace this statement: -- bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_axsize_unsigned))); -- With this new process: -- Replace case statement with unsigned signal comparator. DIV_AXSIZE: process (curr_axsize) begin case (curr_axsize) is when "000" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 1; when "001" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 2; when "010" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 4; when "011" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 8; when "100" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 16; when "101" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 32; when "110" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 64; when "111" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 128; -- Max SIZE for 1024-bit AXI bus when others => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES; end case; end process DIV_AXSIZE; -- Original statement. -- XST does not support divisors that are not constants AND powers of two. -- Insert process to perform (size_plus_lsb / size_bytes_int) function in generation of ua_narrow_load. -- -- size_bytes_int <= (2**(to_integer (curr_axsize_unsigned))); -- -- ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr - -- (size_plus_lsb / size_bytes_int), C_NARROW_BURST_CNT_LEN)); -- AxSIZE + LSB of address -- Use all LSB address bit lanes for the narrow transfer based on C_S_AXI_DATA_WIDTH size_plus_lsb <= (2**(to_integer (curr_axsize_unsigned))) + to_integer (unsigned (curr_axaddr_lsb (C_AXI_DATA_WIDTH_BYTES_LOG2-1 downto 0))); -- Process to keep synthesis with divide by constants that are a power of 2. DIV_SIZE_BYTES: process (size_plus_lsb, curr_axsize) begin -- Use unsigned w/ curr_axsize signal case (curr_axsize) is when "000" => narrow_addr_offset <= size_plus_lsb / 1; when "001" => narrow_addr_offset <= size_plus_lsb / 2; when "010" => narrow_addr_offset <= size_plus_lsb / 4; when "011" => narrow_addr_offset <= size_plus_lsb / 8; when "100" => narrow_addr_offset <= size_plus_lsb / 16; when "101" => narrow_addr_offset <= size_plus_lsb / 32; when "110" => narrow_addr_offset <= size_plus_lsb / 64; when "111" => narrow_addr_offset <= size_plus_lsb / 128; -- Max SIZE for 1024-bit AXI bus when others => narrow_addr_offset <= size_plus_lsb; end case; end process DIV_SIZE_BYTES; -- Final new statement. -- Passing in simulation and XST. ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr - narrow_addr_offset, C_NARROW_BURST_CNT_LEN)) when (bytes_per_addr >= narrow_addr_offset) else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN)); --------------------------------------------------------------------------- end architecture implementation; ------------------------------------------------------------------------------- -- wrap_brst.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: wrap_brst.vhd -- -- Description: Create sub module for logic to generate WRAP burst -- address for rd_chnl and wr_chnl. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 2/4/2011 v1.03a -- ~~~~~~ -- Edit for scalability and support of 512 and 1024-bit data widths. -- Add axi_bram_ctrl_funcs package inclusion. -- ^^^^^^ -- JLJ 2/7/2011 v1.03a -- ~~~~~~ -- Remove axi_bram_ctrl_funcs package use. -- ^^^^^^ -- JLJ 3/15/2011 v1.03a -- ~~~~~~ -- Update multiply function on signal, wrap_burst_total_cmb, -- for timing path improvements. Replace with left shift operation. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. And general code clean-up. -- ^^^^^^ -- JLJ 3/24/2011 v1.03a -- ~~~~~~ -- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate -- total WRAP burst size for improved FPGA resource utilization. -- ^^^^^^ -- JLJ 3/30/2011 v1.03a -- ~~~~~~ -- Clean up code. -- Re-code wrap_burst_total_cmb process blocks for each data width -- to improve and catch all false conditions in code coverage analysis. -- ^^^^^^ -- -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity wrap_brst is generic ( C_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_BRAM_ADDR_ADJUST_FACTOR : integer := 32; -- Adjust BRAM address width based on C_AXI_DATA_WIDTH C_AXI_DATA_WIDTH : integer := 32 -- Width of AXI data bus (in bits) ); port ( S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; curr_axlen : in std_logic_vector(7 downto 0) := (others => '0'); curr_axsize : in std_logic_vector(2 downto 0) := (others => '0'); curr_narrow_burst : in std_logic; narrow_bram_addr_inc_re : in std_logic; bram_addr_ld_en : in std_logic; bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); max_wrap_burst_mod : out std_logic := '0' ); end entity wrap_brst; ------------------------------------------------------------------------------- architecture implementation of wrap_brst is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; -- AXI Size Constants constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM -- Determine the number of bytes based on the AXI data width. constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8; constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES); -- 8d = size of AxLEN vector constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8; -- Constants for WRAP size decoding to simplify integer represenation. constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001"; constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010"; constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011"; constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100"; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal max_wrap_burst : std_logic := '0'; signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) := (others => '0'); -- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0'); -- signal curr_axsize_int : integer := 0; -- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0'); -- Holds burst length/size total (based on width of BRAM width) -- Max size = max length of burst (256 beats) -- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes) -- signal wrap_burst_total : integer range 0 to 256 := 1; signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0'); signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0'); -- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0'); -- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- Modify counter size based on size of current write burst operation -- For WRAP burst types, the counter value will roll over when the burst -- boundary is reached. -- Based on AxSIZE and AxLEN -- To minimize muxing on initial load of counter value -- Detect on WRAP burst types, when the max address is reached. -- When the max address is reached, re-load counter with lower -- address value. -- Save initial load address value. REG_INIT_BRAM_ADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then save_init_bram_addr_ld <= (others => '0'); elsif (bram_addr_ld_en = '1') then save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1); else save_init_bram_addr_ld <= save_init_bram_addr_ld; end if; end if; end process REG_INIT_BRAM_ADDR; --------------------------------------------------------------------------- -- v1.03a -- Calculate AXI size (integer) -- curr_axsize_unsigned <= unsigned (curr_axsize); -- curr_axsize_int <= to_integer (curr_axsize_unsigned); -- Calculate AXI length (integer) -- curr_axlen_unsigned <= unsigned (curr_axlen); -- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001"; -- WRAP = size * length (based on BRAM data width in bytes) -- -- Original multiply function: -- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES; -- For XST, modify integer multiply function to improve timing. -- Replace multiply of AxLEN * AxSIZE with a left shift function. -- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int) -- begin -- -- for i in C_MAX_LSHIFT_SIZE downto 0 loop -- -- if (i >= curr_axsize_int + 8) then -- curr_axlen_unsigned_plus1_lshift (i) <= '0'; -- elsif (i >= curr_axsize_int) then -- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int); -- else -- curr_axlen_unsigned_plus1_lshift (i) <= '0'; -- end if; -- -- end loop; -- -- end process LEN_LSHIFT; -- Final signal assignment for XST & timing improvements. -- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES; --------------------------------------------------------------------------- -- v1.03a -- For best FPGA resource implementation, hard code the generation of -- WRAP burst size based on each C_AXI_DATA_WIDTH possibility. --------------------------------------------------------------------------- -- Generate: GEN_32_WRAP_SIZE -- Purpose: These wrap size values only apply to 32-bit BRAM. --------------------------------------------------------------------------- GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate begin WRAP_SIZE_CMB: process (curr_axlen, curr_axsize) begin -- v1.03a -- Attempt to re code this to improve conditional coverage checks. -- Use case statment to replace if/else with no priority enabled. -- Current size of transaction case (curr_axsize (2 downto 0)) is -- 4 bytes (full AXI size) when C_AXI_SIZE_4BYTE => case (curr_axlen (3 downto 0)) is when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 2 bytes (1/2 AXI size) when C_AXI_SIZE_2BYTE => case (curr_axlen (3 downto 0)) is when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 1 byte (1/4 AXI size) when C_AXI_SIZE_1BYTE => case (curr_axlen (3 downto 0)) is when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when others => wrap_burst_total_cmb <= (others => '0'); end case; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- v1.03 Original HDL -- -- -- if ((curr_axlen (3 downto 0) = "0001") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or -- ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_2; -- -- elsif ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_4; -- -- elsif ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_8; -- -- elsif ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_16; -- -- else -- wrap_burst_total_cmb <= (others => '0'); -- end if; end process WRAP_SIZE_CMB; end generate GEN_32_WRAP_SIZE; --------------------------------------------------------------------------- -- Generate: GEN_64_WRAP_SIZE -- Purpose: These wrap size values only apply to 64-bit BRAM. --------------------------------------------------------------------------- GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate begin WRAP_SIZE_CMB: process (curr_axlen, curr_axsize) begin -- v1.03a -- Attempt to re code this to improve conditional coverage checks. -- Use case statment to replace if/else with no priority enabled. -- Current size of transaction case (curr_axsize (2 downto 0)) is -- 8 bytes (full AXI size) when C_AXI_SIZE_8BYTE => case (curr_axlen (3 downto 0)) is when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 4 bytes (1/2 AXI size) when C_AXI_SIZE_4BYTE => case (curr_axlen (3 downto 0)) is when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 2 bytes (1/4 AXI size) when C_AXI_SIZE_2BYTE => case (curr_axlen (3 downto 0)) is when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 1 byte (1/8 AXI size) when C_AXI_SIZE_1BYTE => case (curr_axlen (3 downto 0)) is when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when others => wrap_burst_total_cmb <= (others => '0'); end case; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- v1.03 Original HDL -- -- -- if ((curr_axlen (3 downto 0) = "0001") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or -- ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_2; -- -- elsif ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_4; -- -- elsif ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_8; -- -- elsif ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_16; -- -- else -- wrap_burst_total_cmb <= (others => '0'); -- end if; end process WRAP_SIZE_CMB; end generate GEN_64_WRAP_SIZE; --------------------------------------------------------------------------- -- Generate: GEN_128_WRAP_SIZE -- Purpose: These wrap size values only apply to 128-bit BRAM. --------------------------------------------------------------------------- GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate begin WRAP_SIZE_CMB: process (curr_axlen, curr_axsize) begin -- v1.03a -- Attempt to re code this to improve conditional coverage checks. -- Use case statment to replace if/else with no priority enabled. -- Current size of transaction case (curr_axsize (2 downto 0)) is -- 16 bytes (full AXI size) when C_AXI_SIZE_16BYTE => case (curr_axlen (3 downto 0)) is when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 8 bytes (1/2 AXI size) when C_AXI_SIZE_8BYTE => case (curr_axlen (3 downto 0)) is when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 4 bytes (1/4 AXI size) when C_AXI_SIZE_4BYTE => case (curr_axlen (3 downto 0)) is when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 2 bytes (1/8 AXI size) when C_AXI_SIZE_2BYTE => case (curr_axlen (3 downto 0)) is when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when others => wrap_burst_total_cmb <= (others => '0'); end case; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- v1.03 Original HDL -- -- if ((curr_axlen (3 downto 0) = "0001") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or -- ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_2; -- -- elsif ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_4; -- -- elsif ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_8; -- -- elsif ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_16; -- -- else -- wrap_burst_total_cmb <= (others => '0'); -- end if; end process WRAP_SIZE_CMB; end generate GEN_128_WRAP_SIZE; --------------------------------------------------------------------------- -- Generate: GEN_256_WRAP_SIZE -- Purpose: These wrap size values only apply to 256-bit BRAM. --------------------------------------------------------------------------- GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate begin WRAP_SIZE_CMB: process (curr_axlen, curr_axsize) begin -- v1.03a -- Attempt to re code this to improve conditional coverage checks. -- Use case statment to replace if/else with no priority enabled. -- Current size of transaction case (curr_axsize (2 downto 0)) is -- 32 bytes (full AXI size) when C_AXI_SIZE_32BYTE => case (curr_axlen (3 downto 0)) is when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 16 bytes (1/2 AXI size) when C_AXI_SIZE_16BYTE => case (curr_axlen (3 downto 0)) is when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 8 bytes (1/4 AXI size) when C_AXI_SIZE_8BYTE => case (curr_axlen (3 downto 0)) is when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 4 bytes (1/8 AXI size) when C_AXI_SIZE_4BYTE => case (curr_axlen (3 downto 0)) is when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when others => wrap_burst_total_cmb <= (others => '0'); end case; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- v1.03 Original HDL -- -- if ((curr_axlen (3 downto 0) = "0001") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or -- ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_2; -- -- elsif ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_4; -- -- elsif ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_8; -- -- elsif ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_16; -- -- else -- wrap_burst_total_cmb <= (others => '0'); -- end if; end process WRAP_SIZE_CMB; end generate GEN_256_WRAP_SIZE; --------------------------------------------------------------------------- -- Generate: GEN_512_WRAP_SIZE -- Purpose: These wrap size values only apply to 512-bit BRAM. --------------------------------------------------------------------------- GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate begin WRAP_SIZE_CMB: process (curr_axlen, curr_axsize) begin -- v1.03a -- Attempt to re code this to improve conditional coverage checks. -- Use case statment to replace if/else with no priority enabled. -- Current size of transaction case (curr_axsize (2 downto 0)) is -- 64 bytes (full AXI size) when C_AXI_SIZE_64BYTE => case (curr_axlen (3 downto 0)) is when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 32 bytes (1/2 AXI size) when C_AXI_SIZE_32BYTE => case (curr_axlen (3 downto 0)) is when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 16 bytes (1/4 AXI size) when C_AXI_SIZE_16BYTE => case (curr_axlen (3 downto 0)) is when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 8 bytes (1/8 AXI size) when C_AXI_SIZE_8BYTE => case (curr_axlen (3 downto 0)) is when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when others => wrap_burst_total_cmb <= (others => '0'); end case; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- v1.03 Original HDL -- -- -- if ((curr_axlen (3 downto 0) = "0001") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or -- ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_2; -- -- elsif ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_4; -- -- elsif ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_8; -- -- elsif ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_16; -- -- else -- wrap_burst_total_cmb <= (others => '0'); -- end if; end process WRAP_SIZE_CMB; end generate GEN_512_WRAP_SIZE; --------------------------------------------------------------------------- -- Generate: GEN_1024_WRAP_SIZE -- Purpose: These wrap size values only apply to 1024-bit BRAM. --------------------------------------------------------------------------- GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate begin WRAP_SIZE_CMB: process (curr_axlen, curr_axsize) begin -- v1.03a -- Attempt to re code this to improve conditional coverage checks. -- Use case statment to replace if/else with no priority enabled. -- Current size of transaction case (curr_axsize (2 downto 0)) is -- 128 bytes (full AXI size) when C_AXI_SIZE_128BYTE => case (curr_axlen (3 downto 0)) is when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 64 bytes (1/2 AXI size) when C_AXI_SIZE_64BYTE => case (curr_axlen (3 downto 0)) is when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 32 bytes (1/4 AXI size) when C_AXI_SIZE_32BYTE => case (curr_axlen (3 downto 0)) is when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- 16 bytes (1/8 AXI size) when C_AXI_SIZE_16BYTE => case (curr_axlen (3 downto 0)) is when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2; when others => wrap_burst_total_cmb <= (others => '0'); end case; when others => wrap_burst_total_cmb <= (others => '0'); end case; -- v1.03 Original HDL -- -- -- if ((curr_axlen (3 downto 0) = "0001") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or -- ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_2; -- -- elsif ((curr_axlen (3 downto 0) = "0011") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or -- ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_4; -- -- elsif ((curr_axlen (3 downto 0) = "0111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or -- ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_8; -- -- elsif ((curr_axlen (3 downto 0) = "1111") and -- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then -- -- wrap_burst_total_cmb <= C_WRAP_SIZE_16; -- -- else -- wrap_burst_total_cmb <= (others => '0'); -- end if; end process WRAP_SIZE_CMB; end generate GEN_1024_WRAP_SIZE; --------------------------------------------------------------------------- -- Early decode to determine size of WRAP transfer -- Goal to break up long timing path to generate max_wrap_burst signal. REG_WRAP_TOTAL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then wrap_burst_total <= (others => '0'); elsif (bram_addr_ld_en = '1') then wrap_burst_total <= wrap_burst_total_cmb; else wrap_burst_total <= wrap_burst_total; end if; end if; end process REG_WRAP_TOTAL; --------------------------------------------------------------------------- CHECK_WRAP_MAX : process ( wrap_burst_total, bram_addr_int, save_init_bram_addr_ld ) begin -- Check BRAM address value if max value is reached. -- Max value is based on burst size/length for operation. -- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length. -- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width). case wrap_burst_total is when C_WRAP_SIZE_2 => if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then max_wrap_burst <= '1'; else max_wrap_burst <= '0'; end if; -- Use saved BRAM load value bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1); -- Reset lower order address bits to zero (to wrap address) bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0'; when C_WRAP_SIZE_4 => if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then max_wrap_burst <= '1'; else max_wrap_burst <= '0'; end if; -- Use saved BRAM load value bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <= save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2); -- Reset lower order address bits to zero (to wrap address) bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00"; when C_WRAP_SIZE_8 => if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then max_wrap_burst <= '1'; else max_wrap_burst <= '0'; end if; -- Use saved BRAM load value bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <= save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3); -- Reset lower order address bits to zero (to wrap address) bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000"; when C_WRAP_SIZE_16 => if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then max_wrap_burst <= '1'; else max_wrap_burst <= '0'; end if; -- Use saved BRAM load value bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <= save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4); -- Reset lower order address bits to zero (to wrap address) bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000"; when others => max_wrap_burst <= '0'; bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld; -- Reset lower order address bits to zero (to wrap address) bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0'; end case; end process CHECK_WRAP_MAX; --------------------------------------------------------------------------- -- Move outside of CHECK_WRAP_MAX process. -- Account for narrow burst operations. -- -- Currently max_wrap_burst is getting asserted at the first address beat to BRAM -- that indicates the maximum WRAP burst boundary. Must wait for the completion of the -- narrow wrap burst counter to assert max_wrap_burst. -- -- Indicates when narrow burst address counter hits max (all zeros value) -- narrow_bram_addr_inc_re max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else (max_wrap_burst and narrow_bram_addr_inc_re); --------------------------------------------------------------------------- end architecture implementation; ------------------------------------------------------------------------------- -- rd_chnl.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: rd_chnl.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller read channel interfaces. Controls all -- handshaking and data flow on the AXI read address (AR) -- and read data (R) channels. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/3/2011 v1.03a -- ~~~~~~ -- Edits for scalability and support of 512 and 1024-bit data widths. -- ^^^^^^ -- JLJ 2/14/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter. -- Similar edits as wr_chnl on Hsiao ECC code. -- ^^^^^^ -- JLJ 2/18/2011 v1.03a -- ~~~~~~ -- Update for usage of ecc_gen.vhd module directly from MIG. -- Clean-up XST warnings. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Found issue with ECC decoding on read path. Remove MSB '0' usage -- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits. -- Modify read data signal used in single bit error correction. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Move all MIG functions to package body. -- ^^^^^^ -- JLJ 3/2/2011 v1.03a -- ~~~~~~ -- Fix XST handling for DIV functions. Create seperate process when -- divisor is not constant and a power of two. -- ^^^^^^ -- JLJ 3/15/2011 v1.03a -- ~~~~~~ -- Clean-up unused signal, narrow_addr_inc. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. And general code clean-up. -- ^^^^^^ -- JLJ 4/21/2011 v1.03a -- ~~~~~~ -- Code clean up. -- Add defaults to araddr_pipe_sel & axi_arready_int when in single port mode. -- Remove use of IF_IS_AXI4 constant. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Code clean up. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Hard code C_USE_LUT6 constant. -- ^^^^^^ -- JLJ 5/26/2011 v1.03a -- ~~~~~~ -- With CR # 609695, update else clause for narrow_burst_cnt_ld to -- remove simulation warnings when axi_byte_div_curr_arsize = zero. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.wrap_brst; use work.ua_narrow; use work.checkbit_handler; use work.checkbit_handler_64; use work.correct_one_bit; use work.correct_one_bit_64; use work.ecc_gen; use work.parity; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity rd_chnl is generic ( -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type C_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) C_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_AXI_ID_WIDTH : integer := 4; -- AXI ID vector width C_S_AXI_SUPPORTS_NARROW : integer := 1; -- Support for narrow burst operations C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to "AXI4LITE" to optimize out burst transaction support C_SINGLE_PORT_BRAM : integer := 0; -- Enable single port usage of BRAM C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_ECC_TYPE : integer := 0 -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code ); port ( -- AXI Global Signals S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI Read Address Channel Signals (AR) AXI_ARID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_ARADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0); AXI_ARLEN : in std_logic_vector(7 downto 0); -- Specifies the number of data transfers in the burst -- "0000 0000" 1 data transfer -- "0000 0001" 2 data transfers -- ... -- "1111 1111" 256 data transfers AXI_ARSIZE : in std_logic_vector(2 downto 0); -- Specifies the max number of data bytes to transfer in each data beat -- "000" 1 byte to transfer -- "001" 2 bytes to transfer -- "010" 3 bytes to transfer -- ... AXI_ARBURST : in std_logic_vector(1 downto 0); -- Specifies burst type -- "00" FIXED = Fixed burst address (handled as INCR) -- "01" INCR = Increment burst address -- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary -- "11" Reserved (not checked) AXI_ARLOCK : in std_logic; AXI_ARCACHE : in std_logic_vector(3 downto 0); AXI_ARPROT : in std_logic_vector(2 downto 0); AXI_ARVALID : in std_logic; AXI_ARREADY : out std_logic; -- AXI Read Data Channel Signals (R) AXI_RID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_RDATA : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); AXI_RRESP : out std_logic_vector(1 downto 0); AXI_RLAST : out std_logic; AXI_RVALID : out std_logic; AXI_RREADY : in std_logic; -- ECC Register Interface Signals Enable_ECC : in std_logic; BRAM_Addr_En : out std_logic; CE_Failing_We : out std_logic := '0'; Sl_CE : out std_logic := '0'; Sl_UE : out std_logic := '0'; -- Single Port Arbitration Signals Arb2AR_Active : in std_logic; AR2Arb_Active_Clr : out std_logic := '0'; Sng_BRAM_Addr_Ld_En : out std_logic := '0'; Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); Sng_BRAM_Addr_Inc : out std_logic := '0'; Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- BRAM Read Port Interface Signals BRAM_En : out std_logic; BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0); BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ); end entity rd_chnl; ------------------------------------------------------------------------------- architecture implementation of rd_chnl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error -- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response -- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error -- Set constants for ARLEN equal to a count of one or two beats. constant AXI_ARLEN_ONE : std_logic_vector(7 downto 0) := (others => '0'); constant AXI_ARLEN_TWO : std_logic_vector(7 downto 0) := "00000001"; -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" -- Move to full_axi module -- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8); -- Not used -- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR; -- Determine maximum size for narrow burst length counter -- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits -- resulting in a count 3 downto 0 => so minimum counter width = 2 bits. -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits -- resulting in a count 31 downto 0 => so minimum counter width = 5 bits. constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8); constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); -- Max length burst count AXI4 specification constant C_MAX_BRST_CNT : integer := 256; constant C_BRST_CNT_SIZE : integer := log2 (C_MAX_BRST_CNT); -- When the burst count = 0 constant C_BRST_CNT_ZERO : std_logic_vector(C_BRST_CNT_SIZE-1 downto 0) := (others => '0'); -- Burst count = 1 constant C_BRST_CNT_ONE : std_logic_vector(7 downto 0) := "00000001"; -- Burst count = 2 constant C_BRST_CNT_TWO : std_logic_vector(7 downto 0) := "00000010"; -- Read data mux select constants (for signal rddata_mux_sel) -- '0' selects BRAM -- '1' selects read skid buffer constant C_RDDATA_MUX_BRAM : std_logic := '0'; constant C_RDDATA_MUX_SKID_BUF : std_logic := '1'; -- Determine the number of bytes based on the AXI data width. constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8; -- AXI Burst Types -- AXI Spec 4.4 constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10"; constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01"; constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00"; -- AXI Size Constants -- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte -- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes -- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM -- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM -- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM -- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM -- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM -- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM -- Determine max value of ARSIZE based on the AXI data width. -- Use function in axi_bram_ctrl_funcs package. constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH); -- Internal ECC data width size. constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH); -- For use with ECC functions (to use LUT6 components or let synthesis infer the optimal implementation). -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; -- Remove usage of C_FAMILY. -- All architectures supporting AXI will support a LUT6. -- Hard code this internal constant used in ECC algorithm. constant C_USE_LUT6 : boolean := TRUE; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Read Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type RD_ADDR_SM_TYPE is ( IDLE, LD_ARADDR ); signal rd_addr_sm_cs, rd_addr_sm_ns : RD_ADDR_SM_TYPE; signal ar_active_set : std_logic := '0'; signal ar_active_set_i : std_logic := '0'; signal ar_active_clr : std_logic := '0'; signal ar_active : std_logic := '0'; signal ar_active_d1 : std_logic := '0'; signal ar_active_re : std_logic := '0'; signal axi_araddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal curr_araddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0'); signal araddr_pipe_ld : std_logic := '0'; signal araddr_pipe_ld_i : std_logic := '0'; signal araddr_pipe_sel : std_logic := '0'; -- '0' indicates mux select from AXI -- '1' indicates mux select from AR Addr Register signal axi_araddr_full : std_logic := '0'; signal axi_arready_int : std_logic := '0'; signal axi_early_arready_int : std_logic := '0'; signal axi_aresetn_d1 : std_logic := '0'; signal axi_aresetn_d2 : std_logic := '0'; signal axi_aresetn_d3 : std_logic := '0'; signal axi_aresetn_re : std_logic := '0'; signal axi_aresetn_re_reg : std_logic := '0'; signal no_ar_ack_cmb : std_logic := '0'; signal no_ar_ack : std_logic := '0'; signal pend_rd_op_cmb : std_logic := '0'; signal pend_rd_op : std_logic := '0'; signal axi_arid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_arsize_pipe : std_logic_vector (2 downto 0) := (others => '0'); signal axi_arsize_pipe_4byte : std_logic := '0'; signal axi_arsize_pipe_8byte : std_logic := '0'; signal axi_arsize_pipe_16byte : std_logic := '0'; signal axi_arsize_pipe_32byte : std_logic := '0'; -- v1.03a signal axi_arsize_pipe_max : std_logic := '0'; signal curr_arsize : std_logic_vector (2 downto 0) := (others => '0'); signal curr_arsize_reg : std_logic_vector (2 downto 0) := (others => '0'); signal axi_arlen_pipe : std_logic_vector(7 downto 0) := (others => '0'); signal axi_arlen_pipe_1_or_2 : std_logic := '0'; signal curr_arlen : std_logic_vector(7 downto 0) := (others => '0'); signal curr_arlen_reg : std_logic_vector(7 downto 0) := (others => '0'); signal axi_arburst_pipe : std_logic_vector(1 downto 0) := (others => '0'); signal axi_arburst_pipe_fixed : std_logic := '0'; signal curr_arburst : std_logic_vector(1 downto 0) := (others => '0'); signal curr_wrap_burst : std_logic := '0'; signal curr_wrap_burst_reg : std_logic := '0'; signal max_wrap_burst : std_logic := '0'; signal curr_incr_burst : std_logic := '0'; signal curr_fixed_burst : std_logic := '0'; signal curr_fixed_burst_reg : std_logic := '0'; -- BRAM Address Counter signal bram_addr_ld_en : std_logic := '0'; signal bram_addr_ld_en_i : std_logic := '0'; signal bram_addr_ld_en_mod : std_logic := '0'; signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_inc : std_logic := '0'; signal bram_addr_inc_mod : std_logic := '0'; signal bram_addr_inc_wrap_mod : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Read Data Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type RD_DATA_SM_TYPE is ( IDLE, SNG_ADDR, SEC_ADDR, FULL_PIPE, FULL_THROTTLE, LAST_ADDR, LAST_THROTTLE, LAST_DATA, LAST_DATA_AR_PEND ); signal rd_data_sm_cs, rd_data_sm_ns : RD_DATA_SM_TYPE; signal rd_adv_buf : std_logic := '0'; signal axi_rd_burst : std_logic := '0'; signal axi_rd_burst_two : std_logic := '0'; signal act_rd_burst : std_logic := '0'; signal act_rd_burst_set : std_logic := '0'; signal act_rd_burst_clr : std_logic := '0'; signal act_rd_burst_two : std_logic := '0'; -- Rd Data Buffer/Register signal rd_skid_buf_ld_cmb : std_logic := '0'; signal rd_skid_buf_ld_reg : std_logic := '0'; signal rd_skid_buf_ld : std_logic := '0'; signal rd_skid_buf_ld_imm : std_logic := '0'; signal rd_skid_buf : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal rddata_mux_sel_cmb : std_logic := '0'; signal rddata_mux_sel : std_logic := '0'; signal axi_rdata_en : std_logic := '0'; signal axi_rdata_mux : std_logic_vector (C_AXI_DATA_WIDTH+8*C_ECC-1 downto 0) := (others => '0'); -- Read Burst Counter signal brst_cnt_max : std_logic := '0'; signal brst_cnt_max_d1 : std_logic := '0'; signal brst_cnt_max_re : std_logic := '0'; signal end_brst_rd_clr_cmb : std_logic := '0'; signal end_brst_rd_clr : std_logic := '0'; signal end_brst_rd : std_logic := '0'; signal brst_zero : std_logic := '0'; signal brst_one : std_logic := '0'; signal brst_cnt_ld : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0'); signal brst_cnt_rst : std_logic := '0'; signal brst_cnt_ld_en : std_logic := '0'; signal brst_cnt_ld_en_i : std_logic := '0'; signal brst_cnt_dec : std_logic := '0'; signal brst_cnt : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0'); -- AXI Read Response Signals signal axi_rid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_rid_temp_full : std_logic := '0'; signal axi_rid_temp_full_d1 : std_logic := '0'; signal axi_rid_temp_full_fe : std_logic := '0'; signal axi_rid_temp2 : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_rid_temp2_full : std_logic := '0'; signal axi_b2b_rid_adv : std_logic := '0'; signal axi_rid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_rvalid_clr_ok : std_logic := '0'; signal axi_rvalid_set_cmb : std_logic := '0'; signal axi_rvalid_set : std_logic := '0'; signal axi_rvalid_int : std_logic := '0'; signal axi_rlast_int : std_logic := '0'; signal axi_rlast_set : std_logic := '0'; -- Internal BRAM Signals signal bram_en_cmb : std_logic := '0'; signal bram_en_int : std_logic := '0'; signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- Narrow Burst Signals signal curr_narrow_burst_cmb : std_logic := '0'; signal curr_narrow_burst : std_logic := '0'; signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_addr_rst : std_logic := '0'; signal narrow_addr_ld_en : std_logic := '0'; signal narrow_addr_dec : std_logic := '0'; signal narrow_bram_addr_inc : std_logic := '0'; signal narrow_bram_addr_inc_d1 : std_logic := '0'; signal narrow_bram_addr_inc_re : std_logic := '0'; signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal curr_ua_narrow_wrap : std_logic := '0'; signal curr_ua_narrow_incr : std_logic := '0'; signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); -- State machine type declarations type RLAST_SM_TYPE is ( IDLE, W8_THROTTLE, W8_2ND_LAST_DATA, W8_LAST_DATA, -- W8_LAST_DATA_B2, W8_THROTTLE_B2 ); signal rlast_sm_cs, rlast_sm_ns : RLAST_SM_TYPE; signal last_bram_addr : std_logic := '0'; signal set_last_bram_addr : std_logic := '0'; signal alast_bram_addr : std_logic := '0'; signal rd_b2b_elgible : std_logic := '0'; signal rd_b2b_elgible_no_thr_check : std_logic := '0'; signal throttle_last_data : std_logic := '0'; signal disable_b2b_brst_cmb : std_logic := '0'; signal disable_b2b_brst : std_logic := '0'; signal axi_b2b_brst_cmb : std_logic := '0'; signal axi_b2b_brst : std_logic := '0'; signal do_cmplt_burst_cmb : std_logic := '0'; signal do_cmplt_burst : std_logic := '0'; signal do_cmplt_burst_clr : std_logic := '0'; ------------------------------------------------------------------------------- -- ECC Signals ------------------------------------------------------------------------------- signal UnCorrectedRdData : std_logic_vector (0 to C_AXI_DATA_WIDTH-1) := (others => '0'); -- Move vector from core ECC module to use in AXI RDATA register output signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to ECC @ 32-bit data width signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to ECC @ 64-bit data width signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal Sl_UE_i : std_logic := '0'; signal UE_Q : std_logic := '0'; -- v1.03a -- Hsiao ECC signal syndrome_r : std_logic_vector (C_INT_ECC_WIDTH - 1 downto 0) := (others => '0'); constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH; constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- AXI Read Address Channel Output Signals --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_ARREADY_DUAL -- Purpose: Generate AXI_ARREADY when in dual port mode. --------------------------------------------------------------------------- GEN_ARREADY_DUAL: if C_SINGLE_PORT_BRAM = 0 generate begin -- Ensure ARREADY only gets asserted early when acknowledge recognized -- on AXI read data channel. AXI_ARREADY <= axi_arready_int or (axi_early_arready_int and rd_adv_buf); end generate GEN_ARREADY_DUAL; --------------------------------------------------------------------------- -- Generate: GEN_ARREADY_SNG -- Purpose: Generate AXI_ARREADY when in single port mode. --------------------------------------------------------------------------- GEN_ARREADY_SNG: if C_SINGLE_PORT_BRAM = 1 generate begin -- ARREADY generated by sng_port_arb module AXI_ARREADY <= '0'; axi_arready_int <= '0'; end generate GEN_ARREADY_SNG; --------------------------------------------------------------------------- -- AXI Read Data Channel Output Signals --------------------------------------------------------------------------- -- UE flag is detected is same clock cycle that read data is presented on -- the AXI bus. Must drive SLVERR combinatorially to align with corrupted -- detected data word. AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int; AXI_RVALID <= axi_rvalid_int; AXI_RID <= axi_rid_int; AXI_RLAST <= axi_rlast_int; --------------------------------------------------------------------------- -- -- *** AXI Read Address Channel Interface *** -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_AR_PIPE_SNG -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AR_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate begin -- Unused AW pipeline (set default values) araddr_pipe_ld <= '0'; axi_araddr_pipe <= AXI_ARADDR; axi_arid_pipe <= AXI_ARID; axi_arsize_pipe <= AXI_ARSIZE; axi_arlen_pipe <= AXI_ARLEN; axi_arburst_pipe <= AXI_ARBURST; axi_arlen_pipe_1_or_2 <= '0'; axi_arburst_pipe_fixed <= '0'; axi_araddr_full <= '0'; end generate GEN_AR_PIPE_SNG; --------------------------------------------------------------------------- -- Generate: GEN_AR_PIPE_DUAL -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AR_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate begin ----------------------------------------------------------------------- -- AXI Read Address Buffer/Register -- (mimic behavior of address pipeline for AXI_ARID) ----------------------------------------------------------------------- GEN_ARADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate begin REG_ARADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- No reset condition to save resources/timing if (araddr_pipe_ld = '1') then axi_araddr_pipe (i) <= AXI_ARADDR (i); else axi_araddr_pipe (i) <= axi_araddr_pipe (i); end if; end if; end process REG_ARADDR; end generate GEN_ARADDR; ------------------------------------------------------------------- -- Register ARID -- No reset condition to save resources/timing ------------------------------------------------------------------- REG_ARID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (araddr_pipe_ld = '1') then axi_arid_pipe <= AXI_ARID; else axi_arid_pipe <= axi_arid_pipe; end if; end if; end process REG_ARID; --------------------------------------------------------------------------- -- In parallel to ARADDR pipeline and ARID -- Use same control signals to capture AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST. -- Register AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST -- No reset condition to save resources/timing REG_ARCTRL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (araddr_pipe_ld = '1') then axi_arsize_pipe <= AXI_ARSIZE; axi_arlen_pipe <= AXI_ARLEN; axi_arburst_pipe <= AXI_ARBURST; else axi_arsize_pipe <= axi_arsize_pipe; axi_arlen_pipe <= axi_arlen_pipe; axi_arburst_pipe <= axi_arburst_pipe; end if; end if; end process REG_ARCTRL; --------------------------------------------------------------------------- -- Create signals that indicate value of AXI_ARLEN in pipeline stage -- Used to decode length of burst when BRAM address can be loaded early -- when pipeline is full. -- -- Add early decode of ARBURST in pipeline. -- Copy logic from WR_CHNL module (similar logic). -- Add early decode of ARSIZE = 4 bytes in pipeline. REG_ARLEN_PIPE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- No reset condition to save resources/timing if (araddr_pipe_ld = '1') then -- Create merge to decode ARLEN of ONE or TWO if (AXI_ARLEN = AXI_ARLEN_ONE) or (AXI_ARLEN = AXI_ARLEN_TWO) then axi_arlen_pipe_1_or_2 <= '1'; else axi_arlen_pipe_1_or_2 <= '0'; end if; -- Early decode on value in pipeline of ARBURST if (AXI_ARBURST = C_AXI_BURST_FIXED) then axi_arburst_pipe_fixed <= '1'; else axi_arburst_pipe_fixed <= '0'; end if; else axi_arlen_pipe_1_or_2 <= axi_arlen_pipe_1_or_2; axi_arburst_pipe_fixed <= axi_arburst_pipe_fixed; end if; end if; end process REG_ARLEN_PIPE; --------------------------------------------------------------------------- -- Create full flag for ARADDR pipeline -- Set when read address register is loaded. -- Cleared when read address stored in register is loaded into BRAM -- address counter. REG_RDADDR_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- (bram_addr_ld_en = '1' and araddr_pipe_sel = '1') then (bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and araddr_pipe_ld = '0') then axi_araddr_full <= '0'; elsif (araddr_pipe_ld = '1') then axi_araddr_full <= '1'; else axi_araddr_full <= axi_araddr_full; end if; end if; end process REG_RDADDR_FULL; --------------------------------------------------------------------------- end generate GEN_AR_PIPE_DUAL; --------------------------------------------------------------------------- -- v1.03a -- Add early decode of ARSIZE = max size in pipeline based on AXI data -- bus width (use constant, C_AXI_SIZE_MAX) REG_ARSIZE_PIPE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_arsize_pipe_max <= '0'; elsif (araddr_pipe_ld = '1') then -- Early decode of ARSIZE in pipeline equal to max # of bytes -- based on AXI data bus width if (AXI_ARSIZE = C_AXI_SIZE_MAX) then axi_arsize_pipe_max <= '1'; else axi_arsize_pipe_max <= '0'; end if; else axi_arsize_pipe_max <= axi_arsize_pipe_max; end if; end if; end process REG_ARSIZE_PIPE; --------------------------------------------------------------------------- -- Generate: GE_ARREADY -- Purpose: ARREADY is only created here when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_ARREADY: if (C_SINGLE_PORT_BRAM = 0) generate begin ---------------------------------------------------------------------------- -- AXI_ARREADY Output Register -- Description: Keep AXI_ARREADY output asserted until ARADDR pipeline -- is full. When a full condition is reached, negate -- ARREADY as another AR address can not be accepted. -- Add condition to keep ARReady asserted if loading current --- ARADDR pipeline value into the BRAM address counter. -- Indicated by assertion of bram_addr_ld_en & araddr_pipe_sel. -- ---------------------------------------------------------------------------- REG_ARREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_arready_int <= '0'; -- Detect end of S_AXI_AResetn to assert AWREADY and accept -- new AWADDR values elsif (axi_aresetn_re_reg = '1') or -- Add condition for early ARREADY to keep pipeline full (bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and axi_early_arready_int = '0') then axi_arready_int <= '1'; -- Add conditional check if ARREADY is asserted (with ARVALID) (one clock cycle later) -- when the address pipeline is full. elsif (araddr_pipe_ld = '1') or (AXI_ARVALID = '1' and axi_arready_int = '1' and axi_araddr_full = '1') then axi_arready_int <= '0'; else axi_arready_int <= axi_arready_int; end if; end if; end process REG_ARREADY; ---------------------------------------------------------------------------- REG_EARLY_ARREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_early_arready_int <= '0'; -- Pending ARADDR and ARREADY is not yet asserted to accept -- operation (due to ARADDR being full) elsif (AXI_ARVALID = '1' and axi_arready_int = '0' and axi_araddr_full = '1') and (alast_bram_addr = '1') and -- Add check for elgible back-to-back BRAM load (rd_b2b_elgible = '1') then axi_early_arready_int <= '1'; else axi_early_arready_int <= '0'; end if; end if; end process REG_EARLY_ARREADY; --------------------------------------------------------------------------- -- Need to detect end of reset cycle to assert ARREADY on AXI bus REG_ARESETN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then axi_aresetn_d1 <= S_AXI_AResetn; axi_aresetn_d2 <= axi_aresetn_d1; axi_aresetn_d3 <= axi_aresetn_d2; axi_aresetn_re_reg <= axi_aresetn_re; end if; end process REG_ARESETN; -- Create combinatorial RE detect of S_AXI_AResetn --axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d2 = '0') else '0'; axi_aresetn_re <= '1' when (axi_aresetn_d1 = '1' and axi_aresetn_d2 = '0') else '0'; ---------------------------------------------------------------------------- end generate GEN_ARREADY; --------------------------------------------------------------------------- -- Generate: GEN_DUAL_ADDR_CNT -- Purpose: Instantiate BRAM address counter unique for wr_chnl logic -- only when controller configured in dual port mode. --------------------------------------------------------------------------- GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate begin --------------------------------------------------------------------------- -- Replace I_ADDR_CNT module usage of pf_counter in proc_common library. -- Only need to use lower 12-bits of address due to max AXI burst size -- Since AXI guarantees bursts do not cross 4KB boundary, the counting part -- of I_ADDR_CNT can be reduced to max 4KB. -- -- No reset on bram_addr_int. -- Increment ONLY. REG_ADDR_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (bram_addr_ld_en_mod = '1') then bram_addr_int <= bram_addr_ld; elsif (bram_addr_inc_mod = '1') then bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <= bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12); bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <= std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1); end if; end if; end process REG_ADDR_CNT; --------------------------------------------------------------------------- -- Set defaults to shared address counter -- Only used in single port configurations Sng_BRAM_Addr_Ld_En <= '0'; Sng_BRAM_Addr_Ld <= (others => '0'); Sng_BRAM_Addr_Inc <= '0'; end generate GEN_DUAL_ADDR_CNT; --------------------------------------------------------------------------- -- Generate: GEN_SNG_ADDR_CNT -- Purpose: When configured in single port BRAM mode, address counter -- is shared with rd_chnl module. Assign output signals here -- to counter instantiation at full_axi module level. --------------------------------------------------------------------------- GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate begin Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod; Sng_BRAM_Addr_Ld <= bram_addr_ld; Sng_BRAM_Addr_Inc <= bram_addr_inc_mod; bram_addr_int <= Sng_BRAM_Addr; end generate GEN_SNG_ADDR_CNT; --------------------------------------------------------------------------- -- BRAM address load mux. -- Either load BRAM counter directly from AXI bus or from stored registered value -- Use registered signal to indicate current operation is a WRAP burst -- -- Match bram_addr_ld to what asserts bram_addr_ld_en_mod -- Include bram_addr_inc_mod when asserted to use bram_addr_ld_wrap value -- (otherwise use pipelined or AXI bus value to load BRAM address counter) bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst = '1' and curr_wrap_burst_reg = '1' and bram_addr_inc_wrap_mod = '1') else axi_araddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) when (araddr_pipe_sel = '1') else AXI_ARADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); --------------------------------------------------------------------------- -- On wrap burst max loads (simultaneous BRAM address increment is asserted). -- Ensure that load has higher priority over increment. -- Use registered signal to indicate current operation is a WRAP burst bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or (max_wrap_burst = '1' and curr_wrap_burst_reg = '1' and bram_addr_inc_wrap_mod = '1')) else '0'; -- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal -- logic. No need for the check if the current operation is NOT a fixed AND a wrap -- burst. The transfer will be one or the other. -- Found issue when narrow FIXED length burst is incorrectly -- incrementing BRAM address counter bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0') else narrow_bram_addr_inc_re; ---------------------------------------------------------------------------- -- Narrow bursting -- -- Handle read burst addressing on narrow burst operations -- Intercept BRAM address increment flag, bram_addr_inc and only -- increment address when the number of BRAM reads match the width of the -- AXI data bus. -- For a 32-bit BRAM, byte burst will increment the BRAM address -- after four reads from BRAM. -- For a 256-bit BRAM, a byte burst will increment the BRAM address -- after 32 reads from BRAM. -- Based on current operation being a narrow burst, hold off BRAM -- address increment until narrow burst fits BRAM data width. -- For non narrow burst operations, use bram_addr_inc from data SM. -- -- Add in check that burst type is not FIXED, curr_fixed_burst_reg -- bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else -- narrow_bram_addr_inc_re; -- -- -- Replace w/ below generate statements based on supporting narrow transfers or not. -- Create generate statement around the signal assignment for bram_addr_inc_mod. --------------------------------------------------------------------------- -- Generate: GEN_BRAM_INC_MOD_W_NARROW -- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers -- are supported in design instantiation. --------------------------------------------------------------------------- GEN_BRAM_INC_MOD_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin -- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else (narrow_bram_addr_inc_re and not (curr_fixed_burst_reg)); end generate GEN_BRAM_INC_MOD_W_NARROW; --------------------------------------------------------------------------- -- Generate: GEN_WO_NARROW -- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers -- are not supported in the design instantiation. -- Drive default values for narrow counter and logic when -- narrow operation support is disabled. --------------------------------------------------------------------------- GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate begin -- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg); narrow_addr_rst <= '0'; narrow_burst_cnt_ld_mod <= (others => '0'); narrow_addr_dec <= '0'; narrow_addr_ld_en <= '0'; narrow_bram_addr_inc <= '0'; narrow_bram_addr_inc_d1 <= '0'; narrow_bram_addr_inc_re <= '0'; narrow_addr_int <= (others => '0'); curr_narrow_burst <= '0'; end generate GEN_WO_NARROW; --------------------------------------------------------------------------- -- -- Only instantiate NARROW_CNT and supporting logic when narrow transfers -- are supported and utilized by masters in the AXI system. -- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this. -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NARROW_CNT -- Purpose: Instantiate narrow counter and logic when narrow -- operation support is enabled. --------------------------------------------------------------------------- GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin --------------------------------------------------------------------------- -- -- Generate seperate smaller counter for narrow burst operations -- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library. -- -- Counter size is adjusted based on size of data burst. -- -- For example, 32-bit data width BRAM, minimum narrow width -- burst is 8 bits resulting in a count 3 downto 0. So the -- minimum counter width = 2 bits. -- -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst -- is 8 bits resulting in a count 31 downto 0. So the -- minimum counter width = 5 bits. -- -- Size of counter = C_NARROW_BURST_CNT_LEN -- --------------------------------------------------------------------------- REG_NARROW_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (narrow_addr_rst = '1') then narrow_addr_int <= (others => '0'); -- Load enable elsif (narrow_addr_ld_en = '1') then narrow_addr_int <= narrow_burst_cnt_ld_mod; -- Decrement ONLY (no increment functionality) elsif (narrow_addr_dec = '1') then narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <= std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1); end if; end if; end process REG_NARROW_CNT; --------------------------------------------------------------------------- narrow_addr_rst <= not (S_AXI_AResetn); -- Modify narrow burst count load value based on -- unalignment of AXI address value narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else narrow_burst_cnt_ld_reg; narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0'; narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re; narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and (curr_narrow_burst = '1') -- Ensure that narrow address counter doesn't -- flag max or get loaded to -- reset narrow counter until AXI read data -- bus has acknowledged current -- data on the AXI bus. Use rd_adv_buf signal -- to indicate the non throttle -- condition on the AXI bus. and (bram_addr_inc = '1') else '0'; ---------------------------------------------------------------------------- -- Detect rising edge of narrow_bram_addr_inc REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_bram_addr_inc_d1 <= '0'; else narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc; end if; end if; end process REG_NARROW_BRAM_ADDR_INC; narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and (narrow_bram_addr_inc_d1 = '0') else '0'; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT; ---------------------------------------------------------------------------- -- Specify current ARSIZE signal -- Address pipeline MUX curr_arsize <= axi_arsize_pipe when (araddr_pipe_sel = '1') else AXI_ARSIZE; REG_ARSIZE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_arsize_reg <= (others => '0'); -- Register curr_arsize when bram_addr_ld_en = '1' elsif (bram_addr_ld_en = '1') then curr_arsize_reg <= curr_arsize; else curr_arsize_reg <= curr_arsize_reg; end if; end if; end process REG_ARSIZE; --------------------------------------------------------------------------- -- Generate: GEN_NARROW_EN -- Purpose: Only instantiate logic to determine if current burst -- is a narrow burst when narrow bursting logic is supported. --------------------------------------------------------------------------- GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin ----------------------------------------------------------------------- -- Determine "narrow" burst transfers -- Compare the ARSIZE to the BRAM data width ----------------------------------------------------------------------- -- v1.03a -- Detect if current burst operation is of size /= to the full -- AXI data bus width. If not, then the current operation is a -- "narrow" burst. curr_narrow_burst_cmb <= '1' when (curr_arsize /= C_AXI_SIZE_MAX) else '0'; --------------------------------------------------------------------------- -- Register flag indicating the current operation -- is a narrow read burst NARROW_BURST_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Need to reset this flag at end of narrow burst operation -- Ensure if curr_narrow_burst got set during previous transaction, axi_rlast_set -- doesn't clear the flag (add check for pend_rd_op negated). if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_set = '1' and pend_rd_op = '0' and bram_addr_ld_en = '0') then curr_narrow_burst <= '0'; -- Add check for burst operation using ARLEN value -- Ensure that narrow burst flag does not get set during FIXED burst types elsif (bram_addr_ld_en = '1') and (curr_arlen /= AXI_ARLEN_ONE) and (curr_fixed_burst = '0') then curr_narrow_burst <= curr_narrow_burst_cmb; end if; end if; end process NARROW_BURST_REG; end generate GEN_NARROW_EN; --------------------------------------------------------------------------- -- Generate: GEN_NARROW_CNT_LD -- Purpose: Only instantiate logic to determine narrow burst counter -- load value when narrow bursts are enabled. --------------------------------------------------------------------------- GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate signal curr_arsize_unsigned : unsigned (2 downto 0) := (others => '0'); signal axi_byte_div_curr_arsize : integer := 1; begin -- v1.03a -- Create narrow burst counter load value based on current operation -- "narrow" data width (indicated by value of AWSIZE). curr_arsize_unsigned <= unsigned (curr_arsize); -- XST does not support divisors that are not constants and powers of 2. -- Create process to create a fixed value for divisor. -- Replace this statement: -- narrow_burst_cnt_ld <= std_logic_vector ( -- to_unsigned ( -- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_arsize_unsigned))) ) - 1, -- C_NARROW_BURST_CNT_LEN)); -- -- With this new process and subsequent signal assignment: -- DIV_AWSIZE: process (curr_arsize_unsigned) -- begin -- -- case (to_integer (curr_arsize_unsigned)) is -- when 0 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1; -- when 1 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2; -- when 2 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4; -- when 3 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8; -- when 4 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16; -- when 5 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32; -- when 6 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64; -- when 7 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128; -- --coverage off -- when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES; -- --coverage on -- end case; -- -- end process DIV_AWSIZE; -- w/ CR # 609695 -- With this new process and subsequent signal assignment: DIV_AWSIZE: process (curr_arsize_unsigned) begin case (curr_arsize_unsigned) is when "000" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1; when "001" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2; when "010" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4; when "011" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8; when "100" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16; when "101" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32; when "110" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64; when "111" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128; --coverage off when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES; --coverage on end case; end process DIV_AWSIZE; -- v1.03a -- Replace with new signal assignment. -- For synthesis to support only divisors that are constant and powers of two. -- Updated else clause for simulation warnings w/ CR # 609695 narrow_burst_cnt_ld <= std_logic_vector ( to_unsigned ( (axi_byte_div_curr_arsize) - 1, C_NARROW_BURST_CNT_LEN)) when (axi_byte_div_curr_arsize > 0) else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN)); --------------------------------------------------------------------------- -- Register narrow burst count load indicator REG_NAR_BRST_CNT_LD: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_burst_cnt_ld_reg <= (others => '0'); elsif (bram_addr_ld_en = '1') then narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld; else narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg; end if; end if; end process REG_NAR_BRST_CNT_LD; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT_LD; ---------------------------------------------------------------------------- -- Handling for WRAP burst types -- -- For WRAP burst types, the counter value will roll over when the burst -- boundary is reached. -- Boundary is reached based on ARSIZE and ARLEN. -- -- Goal is to minimize muxing on initial load of counter value. -- On WRAP burst types, detect when the max address is reached. -- When the max address is reached, re-load counter with lower -- address value set to '0'. ---------------------------------------------------------------------------- -- Detect valid WRAP burst types curr_wrap_burst <= '1' when (curr_arburst = C_AXI_BURST_WRAP) else '0'; curr_incr_burst <= '1' when (curr_arburst = C_AXI_BURST_INCR) else '0'; curr_fixed_burst <= '1' when (curr_arburst = C_AXI_BURST_FIXED) else '0'; ---------------------------------------------------------------------------- -- Register curr_wrap_burst & curr_fixed_burst signals when BRAM -- address counter is initially loaded REG_CURR_BRST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_wrap_burst_reg <= '0'; curr_fixed_burst_reg <= '0'; elsif (bram_addr_ld_en = '1') then curr_wrap_burst_reg <= curr_wrap_burst; curr_fixed_burst_reg <= curr_fixed_burst; else curr_wrap_burst_reg <= curr_wrap_burst_reg; curr_fixed_burst_reg <= curr_fixed_burst_reg; end if; end if; end process REG_CURR_BRST; --------------------------------------------------------------------------- -- Instance: I_WRAP_BRST -- -- Description: -- -- Instantiate WRAP_BRST module -- Logic to generate the wrap around value to load into the BRAM address -- counter on WRAP burst transactions. -- WRAP value is based on current ARLEN, ARSIZE (for narrows) and -- data width of BRAM module. -- --------------------------------------------------------------------------- I_WRAP_BRST : entity work.wrap_brst generic map ( C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , curr_axlen => curr_arlen , curr_axsize => curr_arsize , curr_narrow_burst => curr_narrow_burst , narrow_bram_addr_inc_re => narrow_bram_addr_inc_re , bram_addr_ld_en => bram_addr_ld_en , bram_addr_ld => bram_addr_ld , bram_addr_int => bram_addr_int , bram_addr_ld_wrap => bram_addr_ld_wrap , max_wrap_burst_mod => max_wrap_burst ); ---------------------------------------------------------------------------- -- Specify current ARBURST signal -- Input address pipeline MUX curr_arburst <= axi_arburst_pipe when (araddr_pipe_sel = '1') else AXI_ARBURST; ---------------------------------------------------------------------------- -- Specify current AWBURST signal -- Input address pipeline MUX curr_arlen <= axi_arlen_pipe when (araddr_pipe_sel = '1') else AXI_ARLEN; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_UA_NARROW -- Purpose: Only instantiate logic for burst narrow WRAP operations when -- AXI bus protocol is not set for AXI-LITE and narrow -- burst operations are supported. -- --------------------------------------------------------------------------- GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin --------------------------------------------------------------------------- -- -- New logic to detect unaligned address on a narrow WRAP burst transaction. -- If this condition is met, then the narrow burst counter will be -- initially loaded with an offset value corresponding to the unalignment -- in the ARADDR value. -- -- -- Create a sub module for all logic to determine the narrow burst counter -- offset value on unaligned WRAP burst operations. -- -- Module generates the following signals: -- -- => curr_ua_narrow_wrap, to indicate the current -- operation is an unaligned narrow WRAP burst. -- -- => curr_ua_narrow_incr, to load narrow burst counter -- for unaligned INCR burst operations. -- -- => ua_narrow_load, narrow counter load value. -- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0) -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Instance: I_UA_NARROW -- -- Description: -- -- Creates a narrow burst count load value when an operation -- is an unaligned narrow WRAP or INCR burst type. Used by -- I_NARROW_CNT module. -- -- Logic is customized for each C_AXI_DATA_WIDTH. -- --------------------------------------------------------------------------- I_UA_NARROW : entity work.ua_narrow generic map ( C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN ) port map ( curr_wrap_burst => curr_wrap_burst , -- in curr_incr_burst => curr_incr_burst , -- in bram_addr_ld_en => bram_addr_ld_en , -- in curr_axlen => curr_arlen , -- in curr_axsize => curr_arsize , -- in curr_axaddr_lsb => curr_araddr_lsb , -- in curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out curr_ua_narrow_incr => curr_ua_narrow_incr , -- out ua_narrow_load => ua_narrow_load -- out ); -- Use in all C_AXI_DATA_WIDTH generate statements -- Only probe least significant BRAM address bits -- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0. curr_araddr_lsb <= axi_araddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) when (araddr_pipe_sel = '1') else AXI_ARADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0); end generate GEN_UA_NARROW; ---------------------------------------------------------------------------- -- -- New logic to detect if pending operation in ARADDR pipeline is -- elgible for back-to-back no "bubble" performance. And BRAM address -- counter can be loaded upon last BRAM address presented for the current -- operation. -- This condition exists when the ARADDR pipeline is full and the pending -- operation is a burst >= length of two data beats. -- And not a FIXED burst type (must be INCR or WRAP type). -- The DATA SM handles detecting a throttle condition and will void -- the capability to be a back-to-back in performance transaction. -- -- Add check if new operation is a narrow burst (to be loaded into BRAM -- counter) -- Add check for throttling condition on after last BRAM address is -- presented -- ---------------------------------------------------------------------------- -- v1.03a rd_b2b_elgible_no_thr_check <= '1' when (axi_araddr_full = '1') and (axi_arlen_pipe_1_or_2 /= '1') and (axi_arburst_pipe_fixed /= '1') and (disable_b2b_brst = '0') and (axi_arsize_pipe_max = '1') else '0'; rd_b2b_elgible <= '1' when (rd_b2b_elgible_no_thr_check = '1') and (throttle_last_data = '0') else '0'; -- Check if SM is in LAST_THROTTLE state which also indicates we are throttling at -- the last data beat in the read burst. Ensures that the bursts are not implemented -- as back-to-back bursts and RVALID will negate upon recognition of RLAST and RID -- pipeline will be advanced properly. -- Fix timing path on araddr_pipe_sel generated in RDADDR SM -- SM uses rd_b2b_elgible signal which checks throttle condition on -- last data beat to hold off loading new BRAM address counter for next -- back-to-back operation. -- Attempt to modify logic in generation of throttle_last_data signal. throttle_last_data <= '1' when ((brst_zero = '1') and (rd_adv_buf = '0')) or (rd_data_sm_cs = LAST_THROTTLE) else '0'; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_AR_SNG -- Purpose: If single port BRAM configuration, set all AR flags from -- logic generated in sng_port_arb module. -- --------------------------------------------------------------------------- GEN_AR_SNG: if (C_SINGLE_PORT_BRAM = 1) generate begin araddr_pipe_sel <= '0'; -- Unused in single port configuration ar_active <= Arb2AR_Active; bram_addr_ld_en <= ar_active_re; brst_cnt_ld_en <= ar_active_re; AR2Arb_Active_Clr <= axi_rlast_int and AXI_RREADY; -- Rising edge detect of Arb2AR_Active RE_AR_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Clear ar_active_d1 early w/ ar_active -- So back to back ar_active assertions see the new transaction -- and initiate the read transfer. if (S_AXI_AResetn = C_RESET_ACTIVE) or ((axi_rlast_int and AXI_RREADY) = '1') then ar_active_d1 <= '0'; else ar_active_d1 <= ar_active; end if; end if; end process RE_AR_ACT; ar_active_re <= '1' when (ar_active = '1' and ar_active_d1 = '0') else '0'; end generate GEN_AR_SNG; --------------------------------------------------------------------------- -- -- Generate: GEN_AW_DUAL -- Purpose: Generate AW control state machine logic only when AXI4 -- controller is configured for dual port mode. In dual port -- mode, wr_chnl has full access over AW & port A of BRAM. -- --------------------------------------------------------------------------- GEN_AR_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate begin AR2Arb_Active_Clr <= '0'; -- Only used in single port case --------------------------------------------------------------------------- -- RD ADDR State Machine -- -- Description: Central processing unit for AXI write address -- channel interface handling and handshaking. -- -- Outputs: araddr_pipe_ld Not Registered -- araddr_pipe_sel Not Registered -- bram_addr_ld_en Not Registered -- brst_cnt_ld_en Not Registered -- ar_active_set Not Registered -- -- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- RD_ADDR_SM_CMB_PROCESS: process ( AXI_ARVALID, axi_araddr_full, ar_active, no_ar_ack, pend_rd_op, last_bram_addr, rd_b2b_elgible, rd_addr_sm_cs ) begin -- assign default values for state machine outputs rd_addr_sm_ns <= rd_addr_sm_cs; araddr_pipe_ld_i <= '0'; bram_addr_ld_en_i <= '0'; brst_cnt_ld_en_i <= '0'; ar_active_set_i <= '0'; case rd_addr_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Reload BRAM address counter on last BRAM address of current burst -- if a new address is pending in the AR pipeline and is elgible to -- be loaded for subsequent back-to-back performance. if (last_bram_addr = '1' and rd_b2b_elgible = '1') then -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; -- If loading BRAM counter for subsequent operation -- AND ARVALID is pending on the bus, go ahead and respond -- and fill ARADDR pipeline with next operation. -- -- Asserting the signal to load the ARADDR pipeline here -- allows the full bandwidth utilization to BRAM on -- back to back bursts of two data beats. if (AXI_ARVALID = '1') then araddr_pipe_ld_i <= '1'; rd_addr_sm_ns <= LD_ARADDR; else rd_addr_sm_ns <= IDLE; end if; elsif (AXI_ARVALID = '1') then -- If address pipeline is full -- ARReady output is negated -- Remain in this state -- -- Add check for already pending read operation -- in data SM, but waiting on throttle (even though ar_active is -- already set to '0'). if (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then rd_addr_sm_ns <= IDLE; bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; -- Address counter is currently busy else -- Check if ARADDR pipeline is not full and can be loaded if (axi_araddr_full = '0') then rd_addr_sm_ns <= LD_ARADDR; araddr_pipe_ld_i <= '1'; end if; end if; -- ar_active -- Pending operation in pipeline that is waiting -- until current operation is complete (ar_active = '0') elsif (axi_araddr_full = '1') and (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then rd_addr_sm_ns <= IDLE; -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; end if; -- ARVALID ---------------------------- LD_ARADDR State --------------------------- when LD_ARADDR => -- Check here for subsequent BRAM address load when ARADDR pipe is loaded -- in previous clock cycle. -- -- Reload BRAM address counter on last BRAM address of current burst -- if a new address is pending in the AR pipeline and is elgible to -- be loaded for subsequent back-to-back performance. if (last_bram_addr = '1' and rd_b2b_elgible = '1') then -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; brst_cnt_ld_en_i <= '1'; ar_active_set_i <= '1'; -- If loading BRAM counter for subsequent operation -- AND ARVALID is pending on the bus, go ahead and respond -- and fill ARADDR pipeline with next operation. -- -- Asserting the signal to load the ARADDR pipeline here -- allows the full bandwidth utilization to BRAM on -- back to back bursts of two data beats. if (AXI_ARVALID = '1') then araddr_pipe_ld_i <= '1'; rd_addr_sm_ns <= LD_ARADDR; -- Stay in this state another clock cycle else rd_addr_sm_ns <= IDLE; end if; else rd_addr_sm_ns <= IDLE; end if; --coverage off ------------------------------ Default ---------------------------- when others => rd_addr_sm_ns <= IDLE; --coverage on end case; end process RD_ADDR_SM_CMB_PROCESS; --------------------------------------------------------------------------- -- CR # 582705 -- Ensure combinatorial SM output signals do not get set before -- the end of the reset (and ARREAADY can be set). bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d3; brst_cnt_ld_en <= brst_cnt_ld_en_i and axi_aresetn_d3; ar_active_set <= ar_active_set_i and axi_aresetn_d3; araddr_pipe_ld <= araddr_pipe_ld_i and axi_aresetn_d3; RD_ADDR_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- if (S_AXI_AResetn = C_RESET_ACTIVE) then -- CR # 582705 -- Ensure that ar_active does not get asserted (from SM) before -- the end of reset and the ARREADY flag is set. if (axi_aresetn_d3 = C_RESET_ACTIVE) then rd_addr_sm_cs <= IDLE; else rd_addr_sm_cs <= rd_addr_sm_ns; end if; end if; end process RD_ADDR_SM_REG_PROCESS; --------------------------------------------------------------------------- -- Assert araddr_pipe_sel outside of SM logic -- The BRAM address counter will get loaded with value in ARADDR pipeline -- when data is stored in the ARADDR pipeline. araddr_pipe_sel <= '1' when (axi_araddr_full = '1') else '0'; --------------------------------------------------------------------------- -- Register for ar_active REG_AR_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- if (S_AXI_AResetn = C_RESET_ACTIVE) then -- CR # 582705 if (axi_aresetn_d3 = C_RESET_ACTIVE) then ar_active <= '0'; elsif (ar_active_set = '1') then ar_active <= '1'; -- For code coverage closure, ensure priority encoding in if/else clause -- to prevent checking ar_active_set in reset clause. elsif (ar_active_clr = '1') then ar_active <= '0'; else ar_active <= ar_active; end if; end if; end process REG_AR_ACT; end generate GEN_AR_DUAL; --------------------------------------------------------------------------- -- -- REG_BRST_CNT. -- Read Burst Counter. -- No need to decrement burst counter. -- Able to load with fixed burst length value. -- Replace usage of proc_common_v4_0_2 library with direct HDL. -- -- Size of counter = C_BRST_CNT_SIZE -- Max size of burst transfer = 256 data beats -- --------------------------------------------------------------------------- REG_BRST_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (brst_cnt_rst = '1') then brst_cnt <= (others => '0'); -- Load burst counter elsif (brst_cnt_ld_en = '1') then brst_cnt <= brst_cnt_ld; -- Decrement ONLY (no increment functionality) elsif (brst_cnt_dec = '1') then brst_cnt (C_BRST_CNT_SIZE-1 downto 0) <= std_logic_vector (unsigned (brst_cnt (C_BRST_CNT_SIZE-1 downto 0)) - 1); end if; end if; end process REG_BRST_CNT; --------------------------------------------------------------------------- brst_cnt_rst <= not (S_AXI_AResetn); -- Determine burst count load value -- Either load BRAM counter directly from AXI bus or from stored registered value. -- Use mux signal for ARLEN BRST_CNT_LD_PROCESS : process (curr_arlen) variable brst_cnt_ld_int : integer := 0; begin brst_cnt_ld_int := to_integer (unsigned (curr_arlen (7 downto 0))); brst_cnt_ld <= std_logic_vector (to_unsigned (brst_cnt_ld_int, 8)); end process BRST_CNT_LD_PROCESS; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_BRST_MAX_W_NARROW -- Purpose: Generate registered logic for brst_cnt_max when the -- design instantiation supports narrow operations. -- --------------------------------------------------------------------------- GEN_BRST_MAX_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin REG_BRST_MAX: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') -- Added with single port (13.1 release) or (end_brst_rd_clr = '1') then brst_cnt_max <= '0'; -- Replace usage of brst_cnt in this logic. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then -- Hold off assertion of brst_cnt_max on narrow burst transfers -- Must wait until narrow burst count = 0. if (curr_narrow_burst = '1') then if (narrow_bram_addr_inc = '1') then brst_cnt_max <= '1'; end if; else brst_cnt_max <= '1'; end if; else brst_cnt_max <= brst_cnt_max; end if; end if; end process REG_BRST_MAX; end generate GEN_BRST_MAX_W_NARROW; --------------------------------------------------------------------------- -- -- Generate: GEN_BRST_MAX_WO_NARROW -- Purpose: Generate registered logic for brst_cnt_max when the -- design instantiation does not support narrow operations. -- --------------------------------------------------------------------------- GEN_BRST_MAX_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate begin REG_BRST_MAX: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') then brst_cnt_max <= '0'; -- Replace usage of brst_cnt in this logic. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then -- When narrow operations are not supported in the core -- configuration, no check for curr_narrow_burst on assertion. brst_cnt_max <= '1'; else brst_cnt_max <= brst_cnt_max; end if; end if; end process REG_BRST_MAX; end generate GEN_BRST_MAX_WO_NARROW; --------------------------------------------------------------------------- REG_BRST_MAX_D1: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then brst_cnt_max_d1 <= '0'; else brst_cnt_max_d1 <= brst_cnt_max; end if; end if; end process REG_BRST_MAX_D1; brst_cnt_max_re <= '1' when (brst_cnt_max = '1') and (brst_cnt_max_d1 = '0') else '0'; -- Set flag that end of burst is reached -- Need to capture this condition as the burst -- counter may get reloaded for a subsequent read burst REG_END_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- SM may assert clear flag early (in case of narrow bursts) -- Wait until the end_brst_rd flag is asserted to clear the flag. if (S_AXI_AResetn = C_RESET_ACTIVE) or (end_brst_rd_clr = '1' and end_brst_rd = '1') then end_brst_rd <= '0'; elsif (brst_cnt_max_re = '1') then end_brst_rd <= '1'; end if; end if; end process REG_END_BURST; --------------------------------------------------------------------------- -- Create flag that indicates burst counter is reaching ZEROs (max of burst -- length) REG_BURST_ZERO: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or ((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ZERO)) then brst_zero <= '0'; elsif (brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE) then brst_zero <= '1'; else brst_zero <= brst_zero; end if; end if; end process REG_BURST_ZERO; --------------------------------------------------------------------------- -- Create additional flag that indicates burst counter is reaching ONEs -- (near end of burst length). Used to disable back-to-back condition in SM. REG_BURST_ONE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or ((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ONE)) or ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE)) then brst_one <= '0'; elsif ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_TWO)) or ((brst_cnt_ld_en = '1') and (brst_cnt_ld = C_BRST_CNT_ONE)) then brst_one <= '1'; else brst_one <= brst_one; end if; end if; end process REG_BURST_ONE; --------------------------------------------------------------------------- -- Register flags for read burst operation REG_RD_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Clear axi_rd_burst flags when burst count gets to zeros (unless the burst -- counter is getting subsequently loaded for the new burst operation) -- -- Replace usage of brst_cnt in this logic. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_zero = '1' and brst_cnt_ld_en = '0') then axi_rd_burst <= '0'; axi_rd_burst_two <= '0'; elsif (brst_cnt_ld_en = '1') then if (curr_arlen /= AXI_ARLEN_ONE and curr_arlen /= AXI_ARLEN_TWO) then axi_rd_burst <= '1'; else axi_rd_burst <= '0'; end if; if (curr_arlen = AXI_ARLEN_TWO) then axi_rd_burst_two <= '1'; else axi_rd_burst_two <= '0'; end if; else axi_rd_burst <= axi_rd_burst; axi_rd_burst_two <= axi_rd_burst_two; end if; end if; end process REG_RD_BURST; --------------------------------------------------------------------------- -- Seeing issue with axi_rd_burst getting cleared too soon -- on subsquent brst_cnt_ld_en early assertion and pend_rd_op is asserted. -- Create flag for currently active read burst operation -- Gets asserted when burst counter is loaded, but does not -- get cleared until the RD_DATA_SM has completed the read -- burst operation REG_ACT_RD_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (act_rd_burst_clr = '1') then act_rd_burst <= '0'; act_rd_burst_two <= '0'; elsif (act_rd_burst_set = '1') then -- If not loading the burst counter for a B2B operation -- Then act_rd_burst follows axi_rd_burst and -- act_rd_burst_two follows axi_rd_burst_two. -- Get registered value of axi_* signal. if (brst_cnt_ld_en = '0') then act_rd_burst <= axi_rd_burst; act_rd_burst_two <= axi_rd_burst_two; else -- Otherwise, duplicate logic for axi_* signals if burst counter -- is getting loaded. -- For improved code coverage here -- The act_rd_burst_set signal will never get asserted if the burst -- size is less than two data beats. So, the conditional check -- for (curr_arlen /= AXI_ARLEN_ONE) is never evaluated. Removed -- from this if clause. if (curr_arlen /= AXI_ARLEN_TWO) then act_rd_burst <= '1'; else act_rd_burst <= '0'; end if; if (curr_arlen = AXI_ARLEN_TWO) then act_rd_burst_two <= '1'; else act_rd_burst_two <= '0'; end if; -- Note: re-code this if/else clause. end if; else act_rd_burst <= act_rd_burst; act_rd_burst_two <= act_rd_burst_two; end if; end if; end process REG_ACT_RD_BURST; --------------------------------------------------------------------------- rd_adv_buf <= axi_rvalid_int and AXI_RREADY; --------------------------------------------------------------------------- -- RD DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking. -- -- Outputs: Name Type -- -- bram_en_int Registered -- bram_addr_inc Not Registered -- brst_cnt_dec Not Registered -- rddata_mux_sel Registered -- axi_rdata_en Not Registered -- axi_rvalid_set Registered -- -- -- RD_DATA_SM_CMB_PROCESS: Combinational process to determine next state. -- RD_DATA_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- RD_DATA_SM_CMB_PROCESS: process ( bram_addr_ld_en, rd_adv_buf, ar_active, axi_araddr_full, rd_b2b_elgible_no_thr_check, disable_b2b_brst, curr_arlen, axi_rd_burst, axi_rd_burst_two, act_rd_burst, act_rd_burst_two, end_brst_rd, brst_zero, brst_one, axi_b2b_brst, bram_en_int, rddata_mux_sel, end_brst_rd_clr, no_ar_ack, pend_rd_op, axi_rlast_int, rd_data_sm_cs ) begin -- assign default values for state machine outputs rd_data_sm_ns <= rd_data_sm_cs; bram_en_cmb <= bram_en_int; bram_addr_inc <= '0'; brst_cnt_dec <= '0'; rd_skid_buf_ld_cmb <= '0'; rd_skid_buf_ld_imm <= '0'; rddata_mux_sel_cmb <= rddata_mux_sel; -- Change axi_rdata_en generated from SM to be a combinatorial signal -- Can't afford the latency when throttling on the AXI bus. axi_rdata_en <= '0'; axi_rvalid_set_cmb <= '0'; end_brst_rd_clr_cmb <= end_brst_rd_clr; no_ar_ack_cmb <= no_ar_ack; pend_rd_op_cmb <= pend_rd_op; act_rd_burst_set <= '0'; act_rd_burst_clr <= '0'; set_last_bram_addr <= '0'; alast_bram_addr <= '0'; axi_b2b_brst_cmb <= axi_b2b_brst; disable_b2b_brst_cmb <= disable_b2b_brst; ar_active_clr <= '0'; case rd_data_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Initiate BRAM read when address is available in controller -- Indicated by load of BRAM address counter -- Remove use of pend_rd_op signal. -- Never asserted as we transition back to IDLE -- Detected in code coverage if (bram_addr_ld_en = '1') then -- At start of new read, clear end burst signal end_brst_rd_clr_cmb <= '0'; -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Only count addresses & burst length for read -- burst operations -- If currently loading BRAM address counter -- Must check curr_arlen (mux output from pipe or AXI bus) -- to determine length of next operation. -- If ARLEN = 1 data beat, then set last_bram_addr signal -- Otherwise, increment BRAM address counter. if (curr_arlen /= AXI_ARLEN_ONE) then -- Start of new operation, update act_rd_burst and -- act_rd_burst_two signals act_rd_burst_set <= '1'; else -- Set flag for last_bram_addr on transition -- to SNG_ADDR on single operations. set_last_bram_addr <= '1'; end if; -- Go to single active read address state rd_data_sm_ns <= SNG_ADDR; end if; ------------------------- SNG_ADDR State -------------------------- when SNG_ADDR => -- Clear flag once pending read is recognized -- Duplicate logic here in case combinatorial flag was getting -- set as the SM transitioned into this state. if (pend_rd_op = '1') then pend_rd_op_cmb <= '0'; end if; -- At start of new read, clear end burst signal end_brst_rd_clr_cmb <= '0'; -- Reach this state on first BRAM address & enable assertion -- For burst operation, create next BRAM address and keep enable -- asserted -- Note: -- No ability to throttle yet as RVALID has not yet been -- asserted on the AXI bus -- Reset data mux select between skid buffer and BRAM -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- Assert RVALID on AXI when 1st data beat available -- from BRAM axi_rvalid_set_cmb <= '1'; -- Reach this state when BRAM address counter is loaded -- Use axi_rd_burst and axi_rd_burst_two to indicate if -- operation is a single data beat burst. if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then -- Proceed directly to get BRAM read data rd_data_sm_ns <= LAST_ADDR; -- End of active current read address ar_active_clr <= '1'; -- Negate BRAM enable bram_en_cmb <= '0'; -- Load read data skid buffer for BRAM capture -- in next clock cycle rd_skid_buf_ld_cmb <= '1'; -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; -- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM -- address is loaded) and we are waiting for the current read burst to complete. if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; end if; -- Read burst else -- Increment BRAM address counter (2nd data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (2nd data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; rd_data_sm_ns <= SEC_ADDR; -- Load read data skid buffer for BRAM capture -- in next clock cycle rd_skid_buf_ld_cmb <= '1'; -- Start of new operation, update act_rd_burst and -- act_rd_burst_two signals act_rd_burst_set <= '1'; -- If new burst is 2 data beats -- Then disable capability on back-to-back bursts if (axi_rd_burst_two = '1') then -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; else -- Support back-to-back for all other burst lengths disable_b2b_brst_cmb <= '0'; end if; end if; ------------------------- SEC_ADDR State -------------------------- when SEC_ADDR => -- Reach this state when the 2nd incremented address of the burst -- is presented to the BRAM. -- Only reach this state when axi_rd_burst = '1', -- an active read burst. -- Note: -- No ability to throttle yet as RVALID has not yet been -- asserted on the AXI bus -- Enable AXI read data register axi_rdata_en <= '1'; -- Only in dual port mode can the address counter get loaded early if C_SINGLE_PORT_BRAM = 0 then -- If we see the next address get loaded into the BRAM counter -- then set flag for pending operation if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; end if; end if; -- Check here for burst length of two data transfers -- If so, then the SM will NOT hit the condition of a full -- pipeline: -- Operation A) 1st BRAM address data on AXI bus -- Operation B) 2nd BRAm address data read from BRAM -- Operation C) 3rd BRAM address presented to BRAM -- -- Full pipeline condition is hit for any read burst -- length greater than 2 data beats. if (axi_rd_burst_two = '1') then -- No increment of BRAM address -- or decrement of burst counter -- Burst counter should be = zero rd_data_sm_ns <= LAST_ADDR; -- End of active current read address ar_active_clr <= '1'; -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- Negate BRAM enable bram_en_cmb <= '0'; -- Load read data skid buffer for BRAM capture -- in next clock cycle. -- This signal will negate in the next state -- if the data is not accepted on the AXI bus. -- So that no new data from BRAM is registered into the -- read channel controller. rd_skid_buf_ld_cmb <= '1'; else -- Burst length will hit full pipeline condition -- Increment BRAM address counter (3rd data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (3rd data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; rd_data_sm_ns <= FULL_PIPE; -- Assert almost last BRAM address flag -- so that ARVALID logic output can remain registered -- -- Replace usage of brst_cnt with signal, brst_one. if (brst_one = '1') then alast_bram_addr <= '1'; end if; -- Load read data skid buffer for BRAM capture -- in next clock cycle rd_skid_buf_ld_cmb <= '1'; end if; -- ARLEN = "0000 0001" ------------------------- FULL_PIPE State ------------------------- when FULL_PIPE => -- Reach this state when all three data beats in the burst -- are active -- -- Operation A) 1st BRAM address data on AXI bus -- Operation B) 2nd BRAM address data read from BRAM -- Operation C) 3rd BRAM address presented to BRAM -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- With new pipelining capability BRAM address counter may be -- loaded in this state. This only occurs on back-to-back -- bursts (when enabled). -- No flag set for pending operation. -- Modify the if clause here to check for back-to-back burst operations -- If we load the BRAM address in this state for a subsequent burst, then -- this condition indicates a back-to-back burst and no need to assert -- the pending read operation flag. -- Seeing corner case when pend_rd_op needs to be asserted and cleared -- in this state. If the BRAM address counter is loaded early, but -- axi_rlast_set is delayed in getting asserted (all while in this state). -- The signal, curr_narrow_burst can not get cleared. -- Only in dual port mode can the address counter get loaded early if C_SINGLE_PORT_BRAM = 0 then -- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM -- address is loaded) and we are waiting for the current read burst to complete. if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; -- Clear flag once pending read is recognized and -- earlier read data phase is complete. elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then pend_rd_op_cmb <= '0'; end if; end if; -- Check AXI throttling condition -- If AXI bus advances and accepts read data, SM can -- proceed with next data beat of burst. -- If not, then go to FULL_THROTTLE state to wait for -- AXI_RREADY = '1'. if (rd_adv_buf = '1') then -- Assert AXI read data enable for BRAM capture axi_rdata_en <= '1'; -- Load read data skid buffer for BRAM capture in next clock cycle rd_skid_buf_ld_cmb <= '1'; -- Assert almost last BRAM address flag -- so that ARVALID logic output can remain registered -- -- Replace usage of brst_cnt with signal, brst_one. if (brst_one = '1') then alast_bram_addr <= '1'; end if; -- Check burst counter for max -- If max burst count is reached, no new addresses -- presented to BRAM, advance to last capture data states. -- -- For timing, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1' and axi_b2b_brst = '0') then -- Check for elgible pending read operation to support back-to-back performance. -- If so, load BRAM address counter. -- -- Replace rd_b2b_elgible signal check to remove path from -- arlen_pipe through rd_b2b_elgible -- (with data throttle check) if (rd_b2b_elgible_no_thr_check = '1') then rd_data_sm_ns <= FULL_PIPE; -- Set flag to indicate back-to-back read burst -- RVALID will not clear in this case and remain asserted axi_b2b_brst_cmb <= '1'; -- Set flag to update active read burst or -- read burst of two flag act_rd_burst_set <= '1'; -- Otherwise, complete current transaction else -- No increment of BRAM address -- or decrement of burst counter -- Burst counter should be = zero bram_addr_inc <= '0'; brst_cnt_dec <= '0'; rd_data_sm_ns <= LAST_ADDR; -- Negate BRAM enable bram_en_cmb <= '0'; -- End of active current read address ar_active_clr <= '1'; end if; else -- Remain in this state until burst count reaches zero -- Increment BRAM address counter (Nth data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (Nth data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; -- Skid buffer load will remain asserted -- AXI read data register is asserted end if; else -- Throttling condition detected rd_data_sm_ns <= FULL_THROTTLE; -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- Skid buffer gets loaded from BRAM read data in next clock -- cycle ONLY. -- Only on transition to THROTTLE state does skid buffer get loaded. -- Negate load of read data skid buffer for BRAM capture -- in next clock cycle due to detection of Throttle condition rd_skid_buf_ld_cmb <= '0'; -- BRAM address is NOT getting incremented -- (same for burst counter) bram_addr_inc <= '0'; brst_cnt_dec <= '0'; -- If transitioning to throttle state -- Then next register enable assertion of the AXI read data -- output register needs to come from the skid buffer -- Set read data mux select here for SKID_BUFFER data rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; -- Detect if at end of burst read as we transition to FULL_THROTTLE -- If so, negate the BRAM enable even if prior to throttle condition -- on AXI bus. Read skid buffer will hold last beat of data in burst. -- -- For timing purposes, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1') then -- No back to back "non bubble" support when AXI master -- is throttling on current burst. -- Seperate signal throttle_last_data will be asserted outside SM. -- End of burst read, negate BRAM enable bram_en_cmb <= '0'; -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; -- Disable B2B capability if throttling detected when -- burst count is equal to one. -- -- For timing purposes, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_one, indicating the -- brst_cnt to be one when decrement. elsif (brst_one = '1') then -- Assert new flag to disable back-to-back bursts -- due to throttling disable_b2b_brst_cmb <= '1'; -- Throttle, but not end of burst else bram_en_cmb <= '1'; end if; end if; -- rd_adv_buf (RREADY throttle) ------------------------- FULL_THROTTLE State --------------------- when FULL_THROTTLE => -- Reach this state when the AXI bus throttles on the AXI data -- beat read from BRAM (when the read pipeline is fully active) -- Flag disable_b2b_brst_cmb should be asserted as we transition -- to this state. Flag is asserted near the end of a read burst -- to prevent the back-to-back performance pipelining in the BRAM -- address counter. -- Detect if at end of burst read -- If so, negate the BRAM enable even if prior to throttle condition -- on AXI bus. Read skid buffer will hold last beat of data in burst. -- -- For timing, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1') then bram_en_cmb <= '0'; end if; -- Set new flag for pending operation if bram_addr_ld_en is asserted (BRAM -- address is loaded) and we are waiting for the current read burst to complete. if (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; -- Clear flag once pending read is recognized and -- earlier read data phase is complete. elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then pend_rd_op_cmb <= '0'; end if; -- Wait for RREADY to be asserted w/ RVALID on AXI bus if (rd_adv_buf = '1') then -- Ensure read data mux is set for skid buffer data rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; -- Ensure that AXI read data output register is enabled axi_rdata_en <= '1'; -- Must reload skid buffer here from BRAM data -- so if needed can be presented to AXI bus on the following clock cycle rd_skid_buf_ld_imm <= '1'; -- When detecting end of throttle condition -- Check first if burst count is complete -- Check burst counter for max -- If max burst count is reached, no new addresses -- presented to BRAM, advance to last capture data states. -- -- For timing, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_zero, indicating the -- brst_cnt to be zero when decrement. if (brst_zero = '1') or (end_brst_rd = '1') then -- No back-to-back performance when AXI master throttles -- If we reach the end of the burst, proceed to LAST_ADDR state. -- No increment of BRAM address -- or decrement of burst counter -- Burst counter should be = zero bram_addr_inc <= '0'; brst_cnt_dec <= '0'; rd_data_sm_ns <= LAST_ADDR; -- Negate BRAM enable bram_en_cmb <= '0'; -- End of active current read address ar_active_clr <= '1'; -- Not end of current burst w/ throttle condition else -- Go back to FULL_PIPE rd_data_sm_ns <= FULL_PIPE; -- Assert almost last BRAM address flag -- so that ARVALID logic output can remain registered -- -- For timing purposes, replace usage of brst_cnt in this SM. -- Replace with registered signal, brst_one, indicating the -- brst_cnt to be one when decrement. if (brst_one = '1') then alast_bram_addr <= '1'; end if; -- Increment BRAM address counter (Nth data beat) bram_addr_inc <= '1'; -- Decrement BRAM burst counter (Nth data beat) brst_cnt_dec <= '1'; -- Keep BRAM enable asserted bram_en_cmb <= '1'; end if; -- Burst Max else -- Stay in this state -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- Ensure that skid buffer is not getting loaded with -- current read data from BRAM rd_skid_buf_ld_cmb <= '0'; -- BRAM address is NOT getting incremented -- (same for burst counter) bram_addr_inc <= '0'; brst_cnt_dec <= '0'; end if; -- rd_adv_buf (RREADY throttle) ------------------------- LAST_ADDR State ------------------------- when LAST_ADDR => -- Reach this state in the clock cycle following the last address -- presented to the BRAM. Capture the last BRAM data beat in the -- next clock cycle. -- -- Data is presented to AXI bus (if no throttling detected) and -- loaded into the skid buffer. -- If we reach this state after back to back burst transfers -- then clear the flag to ensure that RVALID will clear when RLAST -- is recognized if (axi_b2b_brst = '1') then axi_b2b_brst_cmb <= '0'; end if; -- Clear flag that indicates end of read burst -- Once we reach this state, we have recognized the burst complete. -- -- It is getting asserted too early -- and recognition of the end of the burst is missed when throttling -- on the last two data beats in the read. end_brst_rd_clr_cmb <= '1'; -- Set new flag for pending operation if ar_active is asserted (BRAM -- address has already been loaded) and we are waiting for the current -- read burst to complete. If those two conditions apply, set this flag. -- For dual port, support checking for early writes into BRAM address counter if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then -- Support back-to-backs for single AND dual port modes. -- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then -- if (ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1') then pend_rd_op_cmb <= '1'; end if; -- Load read data skid buffer for BRAM is asserted on transition -- into this state. Only gets negated if done with operation -- as detected in below if clause. -- Check flag for no subsequent operations -- Clear that now, with current operation completing if (no_ar_ack = '1') then no_ar_ack_cmb <= '0'; end if; -- Check for single AXI read operations -- If so, wait for RREADY to be asserted -- Check for burst and bursts of two as seperate signals. if (act_rd_burst = '0') and (act_rd_burst_two = '0') then -- Create rvalid_set to only be asserted for a single clock -- cycle. -- Will get set as transitioning to LAST_ADDR on single read operations -- Only assert RVALID here on single operations -- Enable AXI read data register axi_rdata_en <= '1'; -- Data will not yet be acknowledged on AXI -- in this state. -- Go to wait for last data beat rd_data_sm_ns <= LAST_DATA; -- Set read data mux select for SKID BUF rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; else -- Only check throttling on AXI during read data burst operations -- Check AXI throttling condition -- If AXI bus advances and accepts read data, SM can -- proceed with next data beat. -- If not, then go to LAST_THROTTLE state to wait for -- AXI_RREADY = '1'. if (rd_adv_buf = '1') then -- Assert AXI read data enable for BRAM capture -- in next clock cycle -- Enable AXI read data register axi_rdata_en <= '1'; -- Ensure read data mux is set for BRAM data rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM; -- Burst counter already at zero. Reached this state due to NO -- pending ARADDR in the read address pipeline. However, check -- here for any new read addresses. -- New ARADDR detected and loaded into BRAM address counter -- Add check here for previously loaded BRAM address -- ar_active will be asserted (and qualify that with the -- condition that the read burst is complete, for narrow reads). if (bram_addr_ld_en = '1') then -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Instead of transitioning to SNG_ADDR -- go to wait for last data beat. rd_data_sm_ns <= LAST_DATA_AR_PEND; else -- No pending read address to initiate next read burst -- Go to capture last data beat from BRAM and present on AXI bus. rd_data_sm_ns <= LAST_DATA; end if; -- bram_addr_ld_en (New read burst) else -- Throttling condition detected rd_data_sm_ns <= LAST_THROTTLE; -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- Skid buffer gets loaded from BRAM read data in next clock -- cycle ONLY. -- Only on transition to THROTTLE state does skid buffer get loaded. -- Set read data mux select for SKID BUF rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; end if; -- rd_adv_buf (RREADY throttle) end if; -- AXI read burst ------------------------- LAST_THROTTLE State --------------------- when LAST_THROTTLE => -- Reach this state when the AXI bus throttles on the last data -- beat read from BRAM -- Data to be sourced from read skid buffer -- Add check in LAST_THROTTLE as well as LAST_ADDR -- as we may miss the setting of this flag for a subsequent operation. -- For dual port, support checking for early writes into BRAM address counter if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then -- Support back-to-back for single AND dual port modes. -- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then pend_rd_op_cmb <= '1'; end if; -- Wait for RREADY to be asserted w/ RVALID on AXI bus if (rd_adv_buf = '1') then -- Assert AXI read data enable for BRAM capture axi_rdata_en <= '1'; -- Set read data mux select for SKID BUF rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF; -- No pending read address to initiate next read burst -- Go to capture last data beat from BRAM and present on AXI bus. rd_data_sm_ns <= LAST_DATA; -- Load read data skid buffer for BRAM capture in next clock cycle -- of last data read -- Read Skid buffer already loaded with last data beat from BRAM -- Does not need to be asserted again in this state else -- Stay in this state -- Ensure that AXI read data output register is disabled axi_rdata_en <= '0'; -- Ensure that skid buffer is not getting loaded with -- current read data from BRAM rd_skid_buf_ld_cmb <= '0'; -- BRAM address is NOT getting incremented -- (same for burst counter) bram_addr_inc <= '0'; brst_cnt_dec <= '0'; -- Keep RVALID asserted on AXI -- No need to assert RVALID again end if; -- rd_adv_buf (RREADY throttle) ------------------------- LAST_DATA State ------------------------- when LAST_DATA => -- Reach this state when last BRAM data beat is -- presented on AXI bus. -- For a read burst, RLAST is not asserted until SM reaches -- this state. -- Ok to accept new operation if throttling detected -- during current operation (and flag was previously set -- to disable the back-to-back performance). disable_b2b_brst_cmb <= '0'; -- Stay in this state until RREADY is asserted on AXI bus -- Indicated by assertion of rd_adv_buf if (rd_adv_buf = '1') then -- Last data beat acknowledged on AXI bus -- Check for new read burst or proceed back to IDLE -- New ARADDR detected and loaded into BRAM address counter -- Note: this condition may occur when C_SINGLE_PORT_BRAM = 0 or 1 if (bram_addr_ld_en = '1') or (pend_rd_op = '1') then -- Clear flag once pending read is recognized if (pend_rd_op = '1') then pend_rd_op_cmb <= '0'; end if; -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Only count addresses & burst length for read -- burst operations -- Go to SNG_ADDR state rd_data_sm_ns <= SNG_ADDR; -- If current operation was a burst, clear the active -- burst flag if (act_rd_burst = '1') or (act_rd_burst_two = '1') then act_rd_burst_clr <= '1'; end if; -- If we are loading the BRAM, then we have to view the curr_arlen -- signal to determine if the next operation is a single transfer. -- Or if the BRAM address counter is already loaded (and we reach -- this if clause due to pend_rd_op then the axi_* signals will indicate -- if the next operation is a burst or not. -- If the operation is a single transaction, then set the last_bram_addr -- signal when we reach SNG_ADDR. if (bram_addr_ld_en = '1') then if (curr_arlen = AXI_ARLEN_ONE) then -- Set flag for last_bram_addr on transition -- to SNG_ADDR on single operations. set_last_bram_addr <= '1'; end if; elsif (pend_rd_op = '1') then if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then set_last_bram_addr <= '1'; end if; end if; else -- No pending read address to initiate next read burst. -- Go to IDLE rd_data_sm_ns <= IDLE; -- If current operation was a burst, clear the active -- burst flag if (act_rd_burst = '1') or (act_rd_burst_two = '1') then act_rd_burst_clr <= '1'; end if; end if; else -- Throttling condition detected -- Ensure that AXI read data output register is disabled -- due to throttle condition. axi_rdata_en <= '0'; -- If new ARADDR detected and loaded into BRAM address counter if (bram_addr_ld_en = '1') then -- Initiate BRAM read transfer bram_en_cmb <= '1'; -- Only count addresses & burst length for read -- burst operations -- Instead of transitioning to SNG_ADDR -- to wait for last data beat. rd_data_sm_ns <= LAST_DATA_AR_PEND; -- For singles, block any subsequent loads into BRAM address -- counter from AR SM no_ar_ack_cmb <= '1'; end if; end if; -- rd_adv_buf (RREADY throttle) ------------------------ LAST_DATA_AR_PEND -------------------- when LAST_DATA_AR_PEND => -- Ok to accept new operation if throttling detected -- during current operation (and flag was previously set -- to disable the back-to-back performance). disable_b2b_brst_cmb <= '0'; -- Reach this state when new BRAM address is loaded into -- BRAM address counter -- But waiting for last RREADY/RVALID/RLAST to be asserted -- Once this occurs, continue with pending AR operation if (rd_adv_buf = '1') then -- Go to SNG_ADDR state rd_data_sm_ns <= SNG_ADDR; -- If current operation was a burst, clear the active -- burst flag if (act_rd_burst = '1') or (act_rd_burst_two = '1') then act_rd_burst_clr <= '1'; end if; -- In this state, the BRAM address counter is already loaded, -- the axi_rd_burst and axi_rd_burst_two signals will indicate -- if the next operation is a burst or not. -- If the operation is a single transaction, then set the last_bram_addr -- signal when we reach SNG_ADDR. if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then set_last_bram_addr <= '1'; end if; -- Code coverage tests are reporting that reaching this state -- always when axi_rd_burst = '0' and axi_rd_burst_two = '0', -- so no bursting operations. end if; --coverage off ------------------------------ Default ---------------------------- when others => rd_data_sm_ns <= IDLE; --coverage on end case; end process RD_DATA_SM_CMB_PROCESS; --------------------------------------------------------------------------- RD_DATA_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rd_data_sm_cs <= IDLE; bram_en_int <= '0'; rd_skid_buf_ld_reg <= '0'; rddata_mux_sel <= C_RDDATA_MUX_BRAM; axi_rvalid_set <= '0'; end_brst_rd_clr <= '0'; no_ar_ack <= '0'; pend_rd_op <= '0'; axi_b2b_brst <= '0'; disable_b2b_brst <= '0'; else rd_data_sm_cs <= rd_data_sm_ns; bram_en_int <= bram_en_cmb; rd_skid_buf_ld_reg <= rd_skid_buf_ld_cmb; rddata_mux_sel <= rddata_mux_sel_cmb; axi_rvalid_set <= axi_rvalid_set_cmb; end_brst_rd_clr <= end_brst_rd_clr_cmb; no_ar_ack <= no_ar_ack_cmb; pend_rd_op <= pend_rd_op_cmb; axi_b2b_brst <= axi_b2b_brst_cmb; disable_b2b_brst <= disable_b2b_brst_cmb; end if; end if; end process RD_DATA_SM_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Create seperate registered process for last_bram_addr signal. -- Only asserted for a single clock cycle -- Gets set when the burst counter is loaded with 0's (for a single data beat operation) -- (indicated by set_last_bram_addr from DATA SM) -- or when the burst counter is decrement and the current value = 1 REG_LAST_BRAM_ADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then last_bram_addr <= '0'; -- The signal, set_last_bram_addr, is asserted when the DATA SM transitions to SNG_ADDR -- on a single data beat burst. Can not use condition of loading burst counter -- with the value of 0's (as the burst counter may be loaded during prior single operation -- when waiting on last throttle/data beat, ie. rd_adv_buf not yet asserted). elsif (set_last_bram_addr = '1') or -- On burst operations at the last BRAM address presented to BRAM (brst_cnt_dec = '1' and brst_cnt = C_BRST_CNT_ONE) then last_bram_addr <= '1'; else last_bram_addr <= '0'; end if; end if; end process REG_LAST_BRAM_ADDR; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- *** AXI Read Data Channel Interface *** -- --------------------------------------------------------------------------- rd_skid_buf_ld <= rd_skid_buf_ld_reg or rd_skid_buf_ld_imm; --------------------------------------------------------------------------- -- Generate: GEN_RDATA_NO_ECC -- Purpose: Generation of AXI_RDATA output register without ECC -- logic (C_ECC = 0 parameterization in design) --------------------------------------------------------------------------- GEN_RDATA_NO_ECC: if C_ECC = 0 generate signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); begin --------------------------------------------------------------------------- -- AXI RdData Skid Buffer/Register -- Sized according to size of AXI/BRAM data width --------------------------------------------------------------------------- REG_RD_BUF: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rd_skid_buf <= (others => '0'); -- Add immediate load of read skid buffer -- Occurs in the case when at full throttle and RREADY/RVALID are asserted elsif (rd_skid_buf_ld = '1') then rd_skid_buf <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0); else rd_skid_buf <= rd_skid_buf; end if; end if; end process REG_RD_BUF; -- Rd Data Mux (selects between skid buffer and BRAM read data) -- Select control signal from SM determines register load value axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else rd_skid_buf; --------------------------------------------------------------------------- -- Generate: GEN_RDATA -- Purpose: Generate each bit of AXI_RDATA. --------------------------------------------------------------------------- GEN_RDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate begin REG_RDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Clear output after last data beat accepted by requesting AXI master if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Don't clear RDDATA when a back to back burst is occuring on RLAST & RVALID assertion -- For improved code coverage, can remove the signal, axi_rvalid_int from this if clause. -- It will always be asserted in this case. (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then axi_rdata_int (i) <= '0'; elsif (axi_rdata_en = '1') then axi_rdata_int (i) <= axi_rdata_mux (i); else axi_rdata_int (i) <= axi_rdata_int (i); end if; end if; end process REG_RDATA; end generate GEN_RDATA; -- If C_ECC = 0, direct output assignment to AXI_RDATA AXI_RDATA <= axi_rdata_int; end generate GEN_RDATA_NO_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_RDATA_ECC -- Purpose: Generation of AXI_RDATA output register when ECC -- logic is enabled (C_ECC = 1 parameterization in design) --------------------------------------------------------------------------- GEN_RDATA_ECC: if C_ECC = 1 generate subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- 0:6 for 32-bit ECC -- 0:7 for 64-bit ECC type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits; signal rd_skid_buf_i : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal axi_rdata_int_corr : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); begin -- Remove GEN_RD_BUF that was doing bit reversal. -- Replace with direct register assignments. Sized according to AXI data width. REG_RD_BUF: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rd_skid_buf_i <= (others => '0'); -- Add immediate load of read skid buffer -- Occurs in the case when at full throttle and RREADY/RVALID are asserted elsif (rd_skid_buf_ld = '1') then rd_skid_buf_i (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1); else rd_skid_buf_i <= rd_skid_buf_i; end if; end if; end process REG_RD_BUF; -- Rd Data Mux (selects between skid buffer and BRAM read data) -- Select control signal from SM determines register load value -- axi_rdata_mux holds data + ECC bits. -- Previous mux on input to checkbit_handler logic. -- Removed now (mux inserted after checkbit_handler logic before register stage) -- -- axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else -- rd_skid_buf_i; -- Remove GEN_RDATA that was doing bit reversal. REG_RDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then axi_rdata_int <= (others => '0'); elsif (axi_rdata_en = '1') then -- Track uncorrected data vector with AXI RDATA output pipeline -- Mimic mux logic here (from previous post checkbit XOR logic register) if (rddata_mux_sel = C_RDDATA_MUX_BRAM) then axi_rdata_int (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1); else axi_rdata_int <= rd_skid_buf_i; end if; else axi_rdata_int <= axi_rdata_int; end if; end if; end process REG_RDATA; -- When C_ECC = 1, correct any single bit errors on output read data. -- Post register stage to improve timing on ECC logic data path. -- Use registers in AXI Interconnect IP core. -- Perform bit swapping on output of correct_one_bit -- module (axi_rdata_int_corr signal). -- AXI_RDATA (i) <= axi_rdata_int (i) when (Enable_ECC = '0') -- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i); -- Found in HW debug -- axi_rdata_int is reversed to be returned on AXI bus. -- AXI_RDATA (i) <= axi_rdata_int (C_AXI_DATA_WIDTH-1-i) when (Enable_ECC = '0') -- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i); -- Remove bit reversal on AXI_RDATA output. AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC_CORR -- -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Generate statements to correct BRAM read data -- dependent on ECC type. ------------------------------------------------------------------------ GEN_HAMMING_ECC_CORR: if C_ECC_TYPE = 0 generate begin ------------------------------------------------------------------------ -- Generate: CHK_ECC_32 -- Purpose: Check ECC data unique for 32-bit BRAM. ------------------------------------------------------------------------ CHK_ECC_32: if C_AXI_DATA_WIDTH = 32 generate constant correct_data_table_32 : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC begin --------------------------------------------------------------------------- -- Register ECC syndrome value to correct any single bit errors -- post-register on AXI read data. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then syndrome_reg <= (others => '0'); syndrome_4_reg <= (others => '0'); syndrome_6_reg <= (others => '0'); -- Align register stage of syndrome with AXI read data pipeline elsif (axi_rdata_en = '1') then syndrome_reg <= Syndrome; syndrome_4_reg <= Syndrome_4; syndrome_6_reg <= Syndrome_6; else syndrome_reg <= syndrome_reg; syndrome_4_reg <= syndrome_4_reg; syndrome_6_reg <= syndrome_6_reg; end if; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on specific syndrome bits after pipeline stage before -- correct_one_bit module. syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3); PARITY_CHK4: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (4) ); -- [out std_logic] syndrome_reg_i (5) <= syndrome_reg (5); PARITY_CHK6: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (6) ); -- [out std_logic] --------------------------------------------------------------------------- -- Generate: GEN_CORR_32 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin ----------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_32 -- Description: Correct output read data based on syndrome vector. -- A single error can be corrected by decoding the -- syndrome value. -- Input signal is declared (N:0). -- Output signal is (N:0). -- In order to reuse correct_one_bit module, -- the single data bit correction is done LSB to MSB -- in generate statement loop. ----------------------------------------------------------------------- CORR_ONE_BIT_32: entity work.correct_one_bit generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_32 (i)) port map ( DIn => axi_rdata_int (31-i), -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal) Syndrome => syndrome_reg_i, DCorr => axi_rdata_int_corr (31-i)); -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal) end generate GEN_CORR_32; end generate CHK_ECC_32; ------------------------------------------------------------------------ -- Generate: CHK_ECC_64 -- Purpose: Check ECC data unique for 64-bit BRAM. ------------------------------------------------------------------------ CHK_ECC_64: if C_AXI_DATA_WIDTH = 64 generate constant correct_data_table_64 : correct_data_table_type := ( 0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001", 4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001", 8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001", 12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001", 16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001", 20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001", 24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101", 28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101", 32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101", 36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101", 40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101", 44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101", 48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101", 52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101", 56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011", 60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011" ); signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); -- Specific for 64-bit ECC signal syndrome_7_a : std_logic; signal syndrome_7_b : std_logic; begin --------------------------------------------------------------------------- -- Register ECC syndrome value to correct any single bit errors -- post-register on AXI read data. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Align register stage of syndrome with AXI read data pipeline if (axi_rdata_en = '1') then syndrome_reg <= Syndrome; syndrome_7_reg <= Syndrome_7; else syndrome_reg <= syndrome_reg; syndrome_7_reg <= syndrome_7_reg; end if; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on select syndrome bits after pipeline stage -- before correct_one_bit_64 module. PARITY_CHK7_A: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_7_a ); -- [out std_logic] PARITY_CHK7_B: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_7_b ); -- [out std_logic] -- Do last XOR on Syndrome MSB after pipeline stage before correct_one_bit module -- PASSES: syndrome_reg_i (7) <= syndrome_reg (7) xor syndrome_7_b_reg; syndrome_reg_i (7) <= syndrome_7_a xor syndrome_7_b; syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6); --------------------------------------------------------------------------- -- Generate: GEN_CORR_64 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin ----------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_64 -- Description: Correct output read data based on syndrome vector. -- A single error can be corrected by decoding the -- syndrome value. ----------------------------------------------------------------------- CORR_ONE_BIT_64: entity work.correct_one_bit_64 generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_64 (i)) port map ( DIn => axi_rdata_int (i), Syndrome => syndrome_reg_i, DCorr => axi_rdata_int_corr (i)); end generate GEN_CORR_64; end generate CHK_ECC_64; end generate GEN_HAMMING_ECC_CORR; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC_CORR -- -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. -- Generate statements to correct BRAM read data -- dependent on ECC type. ------------------------------------------------------------------------ GEN_HSIAO_ECC_CORR: if C_ECC_TYPE = 1 generate type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0); signal h_matrix : type_int0; signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); begin -- Reconstruct H-matrix H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate begin H_BIT: for p in 0 to ECC_WIDTH - 1 generate begin h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n); end generate H_BIT; end generate H_COL; -- Based on syndrome value, determine bits to flip in BRAM read data. GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate begin flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r); end generate GEN_FLIP_BIT; ecc_rddata_r <= axi_rdata_int; axi_rdata_int_corr (C_AXI_DATA_WIDTH-1 downto 0) <= -- UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) xor ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor flip_bits (C_AXI_DATA_WIDTH-1 downto 0); end generate GEN_HSIAO_ECC_CORR; end generate GEN_RDATA_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_RID_SNG -- Purpose: Generate RID output pipeline when the core is configured -- in a single port mode. --------------------------------------------------------------------------- GEN_RID_SNG: if (C_SINGLE_PORT_BRAM = 1) generate begin REG_RID_TEMP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp <= (others => '0'); elsif (bram_addr_ld_en = '1') then axi_rid_temp <= AXI_ARID; else axi_rid_temp <= axi_rid_temp; end if; end if; end process REG_RID_TEMP; REG_RID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_rid_int <= (others => '0'); elsif (bram_addr_ld_en = '1') then axi_rid_int <= AXI_ARID; elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then axi_rid_int <= axi_rid_temp; else axi_rid_int <= axi_rid_int; end if; end if; end process REG_RID; -- Advance RID pipeline values axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '1') else '0'; end generate GEN_RID_SNG; --------------------------------------------------------------------------- -- Generate: GEN_RID -- Purpose: Generate RID in dual port mode (with read address pipeline). --------------------------------------------------------------------------- GEN_RID: if (C_SINGLE_PORT_BRAM = 0) generate begin --------------------------------------------------------------------------- -- RID Output Register -- -- Output RID value either comes from pipelined value or directly wrapped -- ARID value. Determined by address pipeline usage. --------------------------------------------------------------------------- -- Create intermediate temporary RID output register REG_RID_TEMP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp <= (others => '0'); -- When BRAM address counter gets loaded -- Set output RID value based on address source elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '0') then -- If BRAM address counter gets loaded directly from -- AXI bus, then save ARID value for wrapping to RID if (araddr_pipe_sel = '0') then axi_rid_temp <= AXI_ARID; else -- Use pipelined AWID value axi_rid_temp <= axi_arid_pipe; end if; -- Add condition to check for temp utilized (temp_full now = '0'), but a -- pending RID is stored in temp2. Must advance the pipeline. elsif ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or (axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then axi_rid_temp <= axi_rid_temp2; else axi_rid_temp <= axi_rid_temp; end if; end if; end process REG_RID_TEMP; -- Create flag that indicates if axi_rid_temp is full REG_RID_TEMP_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rid_temp_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and axi_rid_temp2_full = '0') then axi_rid_temp_full <= '0'; elsif (bram_addr_ld_en = '1') or ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or (axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then axi_rid_temp_full <= '1'; else axi_rid_temp_full <= axi_rid_temp_full; end if; end if; end process REG_RID_TEMP_FULL; -- Create flag to detect falling edge of axi_rid_temp_full flag REG_RID_TEMP_FULL_D1: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp_full_d1 <= '0'; else axi_rid_temp_full_d1 <= axi_rid_temp_full; end if; end if; end process REG_RID_TEMP_FULL_D1; axi_rid_temp_full_fe <= '1' when (axi_rid_temp_full = '0' and axi_rid_temp_full_d1 = '1') else '0'; --------------------------------------------------------------------------- -- Create intermediate temporary RID output register REG_RID_TEMP2: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rid_temp2 <= (others => '0'); -- When BRAM address counter gets loaded -- Set output RID value based on address source elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then -- If BRAM address counter gets loaded directly from -- AXI bus, then save ARID value for wrapping to RID if (araddr_pipe_sel = '0') then axi_rid_temp2 <= AXI_ARID; else -- Use pipelined AWID value axi_rid_temp2 <= axi_arid_pipe; end if; else axi_rid_temp2 <= axi_rid_temp2; end if; end if; end process REG_RID_TEMP2; -- Create flag that indicates if axi_rid_temp2 is full REG_RID_TEMP2_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rid_temp2_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1')) or (axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then axi_rid_temp2_full <= '0'; elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then axi_rid_temp2_full <= '1'; else axi_rid_temp2_full <= axi_rid_temp2_full; end if; end if; end process REG_RID_TEMP2_FULL; --------------------------------------------------------------------------- -- Output RID register is enabeld when RVALID is asserted on the AXI bus -- Clear RID when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. REG_RID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- For improved code coverage, can remove the signal, axi_rvalid_int from statement. (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then axi_rid_int <= (others => '0'); -- Add back to back case to advance RID elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then axi_rid_int <= axi_rid_temp; else axi_rid_int <= axi_rid_int; end if; end if; end process REG_RID; -- Advance RID pipeline values axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '1') else '0'; end generate GEN_RID; --------------------------------------------------------------------------- -- Generate: GEN_RRESP -- Purpose: Create register output unique when ECC is disabled. -- Only possible output value = OKAY response. --------------------------------------------------------------------------- GEN_RRESP: if C_ECC = 0 generate begin ----------------------------------------------------------------------- -- AXI_RRESP Output Register -- -- Set when RVALID is asserted on AXI bus. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking -- sequence and recognized by AXI requesting master. ----------------------------------------------------------------------- REG_RRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted. (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_rresp_int <= (others => '0'); elsif (axi_rvalid_set = '1') then -- AXI BRAM only supports OK response for normal operations -- Exclusive operations not yet supported axi_rresp_int <= RESP_OKAY; else axi_rresp_int <= axi_rresp_int; end if; end if; end process REG_RRESP; end generate GEN_RRESP; --------------------------------------------------------------------------- -- Generate: GEN_RRESP_ECC -- Purpose: Create register output unique when ECC is disabled. -- Only possible output value = OKAY response. --------------------------------------------------------------------------- GEN_RRESP_ECC: if C_ECC = 1 generate begin ----------------------------------------------------------------------- -- AXI_RRESP Output Register -- -- Set when RVALID is asserted on AXI bus. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking -- sequence and recognized by AXI requesting master. ----------------------------------------------------------------------- REG_RRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted. (axi_rlast_int = '1' and AXI_RREADY = '1') then axi_rresp_int <= (others => '0'); elsif (axi_rvalid_set = '1') then -- AXI BRAM only supports OK response for normal operations -- Exclusive operations not yet supported -- For ECC implementation -- Check that an uncorrectable error has not occured. -- If so, then respond with RESP_SLVERR on AXI. -- Ok to use combinatorial signal here. The Sl_UE_i -- flag is generated based on the registered syndrome value. -- if (Sl_UE_i = '1') then -- axi_rresp_int <= RESP_SLVERR; -- else axi_rresp_int <= RESP_OKAY; -- end if; else axi_rresp_int <= axi_rresp_int; end if; end if; end process REG_RRESP; end generate GEN_RRESP_ECC; --------------------------------------------------------------------------- -- AXI_RVALID Output Register -- -- Set AXI_RVALID when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Clear AXI_RVALID at the end of tranfer when able to clear -- (axi_rlast_int = '1' and axi_rvalid_int = '1' and AXI_RREADY = '1' and -- For improved code coverage, remove signal axi_rvalid_int. (axi_rlast_int = '1' and AXI_RREADY = '1' and -- Added axi_rvalid_clr_ok to check if during a back-to-back burst -- and the back-to-back is elgible for streaming performance axi_rvalid_clr_ok = '1') then axi_rvalid_int <= '0'; elsif (axi_rvalid_set = '1') then axi_rvalid_int <= '1'; else axi_rvalid_int <= axi_rvalid_int; end if; end if; end process REG_RVALID; -- Create flag that gets set when we load BRAM address early in a B2B scenario -- This will prevent the RVALID from getting cleared at the end of the current burst -- Otherwise, the RVALID gets cleared after RLAST/RREADY dual assertion REG_RVALID_CLR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_rvalid_clr_ok <= '0'; -- When the new address loaded into the BRAM counter is for a back-to-back operation -- Do not clear the RVALID elsif (rd_b2b_elgible = '1' and bram_addr_ld_en = '1') then axi_rvalid_clr_ok <= '0'; -- Else when we start a new transaction (that is not back-to-back) -- Then enable the RVALID to get cleared upon RLAST/RREADY elsif (bram_addr_ld_en = '1') or (axi_rvalid_clr_ok = '0' and (disable_b2b_brst = '1' or disable_b2b_brst_cmb = '1') and last_bram_addr = '1') or -- Add check for current SM state -- If LAST_ADDR state reached, no longer performing back-to-back -- transfers and keeping data streaming on AXI bus. (rd_data_sm_cs = LAST_ADDR) then axi_rvalid_clr_ok <= '1'; else axi_rvalid_clr_ok <= axi_rvalid_clr_ok; end if; end if; end process REG_RVALID_CLR; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- AXI_RLAST Output Register -- -- Set AXI_RLAST when read data SM indicates. -- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence -- and recognized by AXI requesting master. --------------------------------------------------------------------------- REG_RLAST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- To improve code coverage, remove -- use of axi_rvalid_int (it will always be asserted with RLAST). if (S_AXI_AResetn = C_RESET_ACTIVE) or (axi_rlast_int = '1' and AXI_RREADY = '1' and axi_rlast_set = '0') then axi_rlast_int <= '0'; elsif (axi_rlast_set = '1') then axi_rlast_int <= '1'; else axi_rlast_int <= axi_rlast_int; end if; end if; end process REG_RLAST; --------------------------------------------------------------------------- -- Generate complete flag do_cmplt_burst_cmb <= '1' when (last_bram_addr = '1' and axi_rd_burst = '1' and axi_rd_burst_two = '0') else '0'; -- Register complete flags REG_CMPLT_BURST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (do_cmplt_burst_clr = '1') then do_cmplt_burst <= '0'; elsif (do_cmplt_burst_cmb = '1') then do_cmplt_burst <= '1'; else do_cmplt_burst <= do_cmplt_burst; end if; end if; end process REG_CMPLT_BURST; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- RLAST State Machine -- -- Description: SM to generate axi_rlast_set signal. -- Created based on IR # 555346 to track when RLAST needs -- to be asserted for back to back transfers -- Uses the indication when last BRAM address is presented -- and then counts the handshaking cycles on the AXI bus -- (RVALID and RREADY both asserted). -- Uses rd_adv_buf to perform this operation. -- -- Output: Name Type -- axi_rlast_set Not Registered -- do_cmplt_burst_clr Not Registered -- -- -- RLAST_SM_CMB_PROCESS: Combinational process to determine next state. -- RLAST_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- RLAST_SM_CMB_PROCESS: process ( do_cmplt_burst, last_bram_addr, rd_adv_buf, act_rd_burst, axi_rd_burst, act_rd_burst_two, axi_rd_burst_two, axi_rlast_int, rlast_sm_cs ) begin -- assign default values for state machine outputs rlast_sm_ns <= rlast_sm_cs; axi_rlast_set <= '0'; do_cmplt_burst_clr <= '0'; case rlast_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- If last read address is presented to BRAM if (last_bram_addr = '1') then -- If the operation is a single read operation if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then -- Go to wait for last data beat rlast_sm_ns <= W8_LAST_DATA; -- Else the transaction is a burst else -- Throttle condition on 3rd to last data beat if (rd_adv_buf = '0') then -- If AXI read burst = 2 (only two data beats to capture) if (axi_rd_burst_two = '1' or act_rd_burst_two = '1') then rlast_sm_ns <= W8_THROTTLE_B2; else rlast_sm_ns <= W8_THROTTLE; end if; -- No throttle on 3rd to last data beat else -- Only back-to-back support when burst size is greater -- than two data beats. We will never toggle on a burst > 2 -- when last_bram_addr is asserted (as this is no toggle -- condition) -- Go to wait for 2nd to last data beat rlast_sm_ns <= W8_2ND_LAST_DATA; do_cmplt_burst_clr <= '1'; end if; end if; end if; ------------------------- W8_THROTTLE State ----------------------- when W8_THROTTLE => if (rd_adv_buf = '1') then -- Go to wait for 2nd to last data beat rlast_sm_ns <= W8_2ND_LAST_DATA; -- If do_cmplt_burst flag is set, then clear it if (do_cmplt_burst = '1') then do_cmplt_burst_clr <= '1'; end if; end if; ---------------------- W8_2ND_LAST_DATA State --------------------- when W8_2ND_LAST_DATA => if (rd_adv_buf = '1') then -- Assert RLAST on AXI axi_rlast_set <= '1'; rlast_sm_ns <= W8_LAST_DATA; end if; ------------------------- W8_LAST_DATA State ---------------------- when W8_LAST_DATA => -- If pending single to complete, keep RLAST asserted -- Added to only assert axi_rlast_set for a single clock cycle -- when we enter this state and are here waiting for the -- throttle on the AXI bus. if (axi_rlast_int = '1') then axi_rlast_set <= '0'; else axi_rlast_set <= '1'; end if; -- Wait for last data beat to transition back to IDLE if (rd_adv_buf = '1') then rlast_sm_ns <= IDLE; end if; -------------------------- W8_THROTTLE_B2 ------------------------ when W8_THROTTLE_B2 => -- Wait for last data beat to transition back to IDLE -- and set RLAST if (rd_adv_buf = '1') then rlast_sm_ns <= IDLE; axi_rlast_set <= '1'; end if; --coverage off ------------------------------ Default ---------------------------- when others => rlast_sm_ns <= IDLE; --coverage on end case; end process RLAST_SM_CMB_PROCESS; --------------------------------------------------------------------------- RLAST_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then rlast_sm_cs <= IDLE; else rlast_sm_cs <= rlast_sm_ns; end if; end if; end process RLAST_SM_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** ECC Logic *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_ECC -- Purpose: Generate BRAM ECC write data and check ECC on read operations. -- Create signals to update ECC registers (lite_ecc_reg module interface). -- --------------------------------------------------------------------------- GEN_ECC: if C_ECC = 1 generate signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width signal CE_Q : std_logic := '0'; signal Sl_CE_i : std_logic := '0'; signal bram_en_int_d1 : std_logic := '0'; signal bram_en_int_d2 : std_logic := '0'; begin -- Generate signal to advance BRAM read address pipeline to -- capture address for ECC error conditions (in lite_ecc_reg module). -- BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or -- ((bram_en_int or bram_en_int_reg) and not (axi_rd_burst) and not (axi_rd_burst_two)); BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or rd_adv_buf or ((bram_en_int or bram_en_int_d1 or bram_en_int_d2) and not (axi_rd_burst) and not (axi_rd_burst_two)); -- Enable 2nd & 3rd pipeline stage for BRAM address storage with single read transfers. BRAM_EN_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then bram_en_int_d1 <= bram_en_int; bram_en_int_d2 <= bram_en_int_d1; end if; end process BRAM_EN_REG; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. ------------------------------------------------------------------------ GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate begin ------------------------------------------------------------------------ -- Generate: GEN_ECC_32 -- Purpose: Check ECC data unique for 32-bit BRAM. -- Add extra '0' at MSB of ECC vector for data2mem alignment -- w/ 32-bit BRAM data widths. -- ECC bits are in upper order bits. ------------------------------------------------------------------------ GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate signal bram_din_a_rev : std_logic_vector(31 downto 0) := (others => '0'); -- Specific to BRAM data width signal bram_din_ecc_a_rev : std_logic_vector(6 downto 0) := (others => '0'); -- Specific to BRAM data width begin --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_32 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- -- process (bram_din_a_i) begin -- for k in 0 to 31 loop -- bram_din_a_rev(k) <= bram_din_a_i(39-k); -- end loop; -- for k in 0 to 6 loop -- bram_din_ecc_a_rev(0) <= bram_din_a_i(6-k); -- end loop; -- end process; CHK_HANDLER_32: entity work.checkbit_handler generic map ( C_ENCODE => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( -- In 32-bit BRAM use case: DataIn (8:39) -- CheckIn (1:7) DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)] CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)] --DataIn => bram_din_a_rev, -- [in std_logic_vector(0 to 31)] --CheckIn => bram_din_ecc_a_rev, -- [in std_logic_vector(0 to 6)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)] Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => syndrome_reg_i, -- [out std_logic_vector(0 to 6)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] -- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate -- of AXI RDATA output register logic. end generate GEN_ECC_32; ------------------------------------------------------------------------ -- Generate: GEN_ECC_64 -- Purpose: Check ECC data unique for 64-bit BRAM. -- No extra '0' at MSB of ECC vector for data2mem alignment -- w/ 64-bit BRAM data widths. -- ECC bits are in upper order bits. ------------------------------------------------------------------------ GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_64 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- CHK_HANDLER_64: entity work.checkbit_handler_64 generic map ( C_ENCODE => false, -- [boolean] C_REG => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( Clk => S_AXI_AClk, -- [in std_logic] -- In 64-bit BRAM use case: DataIn (8:71) -- CheckIn (0:7) DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)] CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)] CheckOut => open, -- [out std_logic_vector(0 to 7)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)] Syndrome_7 => Syndrome_7, Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] -- GEN_CORR_64 generate & correct_one_bit instantiation moved to generate -- of AXI RDATA output register logic. end generate GEN_ECC_64; end generate GEN_HAMMING_ECC; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. ------------------------------------------------------------------------ GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; signal syndrome_ns : std_logic_vector (ECC_WIDTH - 1 downto 0) := (others => '0'); begin -- Generate ECC check bits and syndrome values based on -- BRAM read data. -- Generate appropriate single or double bit error flags. -- Instantiate ecc_gen_hsiao module, generated from MIG I_ECC_GEN_HSIAO: entity work.ecc_gen generic map ( code_width => CODE_WIDTH, ecc_width => ECC_WIDTH, data_width => C_AXI_DATA_WIDTH ) port map ( -- Output h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate begin syndrome_ns (m) <= REDUCTION_XOR ( -- bram_din_a_i (0 to CODE_WIDTH-1) BRAM_RdData (CODE_WIDTH-1 downto 0) and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH))); end generate GEN_RD_ECC; -- Insert register stage for syndrome. -- Same as Hamming ECC code. Syndrome value is registered. REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_r <= syndrome_ns; end if; end process REG_SYNDROME; Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not(REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); end generate GEN_HSIAO_ECC; -- Capture correctable/uncorrectable error from BRAM read CORR_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (Enable_ECC = '1') and (axi_rvalid_int = '1' and AXI_RREADY = '1') then -- Capture error flags CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CORR_REG; -- The signal, axi_rdata_en loads the syndrome_reg. -- Use the AXI RVALID/READY signals to capture state of UE and CE. -- Since flag generation uses the registered syndrome value. -- ECC register block gets registered UE or CE conditions to update -- ECC registers/interrupt/flag outputs. Sl_CE <= CE_Q; Sl_UE <= UE_Q; -- CE_Failing_We <= Sl_CE_i and Enable_ECC and axi_rvalid_set; CE_Failing_We <= CE_Q; --------------------------------------------------------------------------- -- Generate BRAM read data vector assignment to always be from Port A -- in a single port BRAM configuration. -- Map BRAM_RdData (Port A) (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. -- -- Port A or Port B sourcing done at full_axi module level --------------------------------------------------------------------------- -- Original design with mux (BRAM vs. Skid Buffer) on input side of checkbit_handler logic. -- Move mux to enable on AXI RDATA register. bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- Map data vector from BRAM to use in correct_one_bit module with -- register syndrome (post AXI RDATA register). UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_AXI_DATA_WIDTH-1); end generate GEN_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Drive default output signals when ECC is diabled. --------------------------------------------------------------------------- GEN_NO_ECC: if C_ECC = 0 generate begin BRAM_Addr_En <= '0'; CE_Failing_We <= '0'; Sl_CE <= '0'; Sl_UE <= '0'; end generate GEN_NO_ECC; --------------------------------------------------------------------------- -- -- *** BRAM Interface Signals *** -- --------------------------------------------------------------------------- BRAM_En <= bram_en_int; --------------------------------------------------------------------------- -- BRAM Address Generate --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. -- --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. -- --------------------------------------------------------------------------- GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr (i) <= bram_addr_int (i); end generate GEN_BRAM_ADDR; --------------------------------------------------------------------------- end architecture implementation; ------------------------------------------------------------------------------- -- wr_chnl.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: wr_chnl.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller write channel interfaces. Controls all -- handshaking and data flow on the AXI write address (AW), -- write data (W) and write response (B) channels. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/3/2011 v1.03a -- ~~~~~~ -- Edits for scalability and support of 512 and 1024-bit data widths. -- ^^^^^^ -- JLJ 2/10/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter. -- ^^^^^^ -- JLJ 2/14/2011 v1.03a -- ~~~~~~ -- Shift Hsiao ECC generate logic so not dependent on C_S_AXI_DATA_WIDTH. -- ^^^^^^ -- JLJ 2/18/2011 v1.03a -- ~~~~~~ -- Update WE size based on 128-bit ECC configuration. -- Update for usage of ecc_gen.vhd module directly from MIG. -- Clean-up XST warnings. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Found issue with ECC decoding on read path. Remove MSB '0' usage -- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Code clean-up. -- Move all MIG functions to package body. -- ^^^^^^ -- JLJ 2/28/2011 v1.03a -- ~~~~~~ -- Fix mapping on BRAM_WE with bram_we_int for 128-bit w/ ECC. -- ^^^^^^ -- JLJ 3/1/2011 v1.03a -- ~~~~~~ -- Fix XST handling for DIV functions. Create seperate process when -- divisor is not constant and a power of two. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. And general code clean-up. -- Fix double clock assertion of CE/UE error flags when asserted -- during the RMW sequence. -- ^^^^^^ -- JLJ 3/23/2011 v1.03a -- ~~~~~~ -- Code clean-up. -- ^^^^^^ -- JLJ 3/30/2011 v1.03a -- ~~~~~~ -- Add code coverage on/off statements. -- ^^^^^^ -- JLJ 4/8/2011 v1.03a -- ~~~~~~ -- Modify back-to-back capability to remove combinatorial loop -- on WREADY to AXI interface. Add internal constant, C_REG_WREADY. -- Update axi_wready_int reset value (ensure it is '0'). -- -- Create new SM for C_REG_WREADY with dual port. Seperate assertion of BVALID -- from WREADY. Create a FIFO to store AWID/BID values. -- Use counter (with max of 8 ID values) to allow WREADY assertions -- to be ahead of BVALID assertions. -- Add sub module, SRL_FIFO. -- ^^^^^^ -- JLJ 4/11/2011 v1.03a -- ~~~~~~ -- Implement similar updates on WREADY for single port & ECC configurations. -- Remove use of signal, axi_wready_sng with constant, C_REG_WREADY. -- -- For single port operation with registered WREADY, provide BVALID counter -- value to arbitration SM, add output signal, AW2Arb_BVALID_Cnt. -- -- Create an additional SM for single port when C_REG_WREADY. -- ^^^^^^ -- JLJ 4/14/2011 v1.03a -- ~~~~~~ -- Remove attempt to create AXI write data pipeline full flag outside of SM -- logic. Add corner case checks for BID FIFO/BVALID counter. -- ^^^^^^ -- JLJ 4/15/2011 v1.03a -- ~~~~~~ -- Clean up all code not related to C_REG_WREADY. -- Goal to remove internal constant, C_REG_WREADY. -- Work on size optimization. Implement signals to represent BVALID -- counter values. -- ^^^^^^ -- JLJ 4/20/2011 v1.03a -- ~~~~~~ -- Code clean up. Remove unused signals. -- Remove additional generate blocks with C_REG_WREADY. -- ^^^^^^ -- JLJ 4/21/2011 v1.03a -- ~~~~~~ -- Code clean up. Remove use of IF_IS_AXI4 constant. -- Create new SM TYPE for each configuration. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Add check in data SM on back-to-back for BVALID counter max. -- Clean up AXI_WREADY generate blocks. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Code clean up. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Hard code C_USE_LUT6 constant. -- ^^^^^^ -- JLJ 5/26/2011 v1.03a -- ~~~~~~ -- Fix CR # 609695. -- Modify usage of WLAST. Ensure that WLAST is qualified with -- WVALID/WREADY assertions. -- -- With CR # 609695, update else clause for narrow_burst_cnt_ld to -- remove simulation warnings when axi_byte_div_curr_awsize = zero. -- -- Catch code clean up with WLAST in data SM for axi_wr_burst_cmb -- signal assertion. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.srl_fifo; use work.wrap_brst; use work.ua_narrow; use work.checkbit_handler; use work.checkbit_handler_64; use work.correct_one_bit; use work.correct_one_bit_64; use work.ecc_gen; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity wr_chnl is generic ( -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type C_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) C_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_SUPPORTS_NARROW : INTEGER := 1; -- Support for narrow burst operations C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to "AXI4LITE" to optimize out burst transaction support C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_ECC_TYPE : integer := 0 -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code ); port ( -- AXI Global Signals S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI Write Address Channel Signals (AW) AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_AWADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0); AXI_AWLEN : in std_logic_vector(7 downto 0); -- Specifies the number of data transfers in the burst -- "0000 0000" 1 data transfer -- "0000 0001" 2 data transfers -- ... -- "1111 1111" 256 data transfers AXI_AWSIZE : in std_logic_vector(2 downto 0); -- Specifies the max number of data bytes to transfer in each data beat -- "000" 1 byte to transfer -- "001" 2 bytes to transfer -- "010" 3 bytes to transfer -- ... AXI_AWBURST : in std_logic_vector(1 downto 0); -- Specifies burst type -- "00" FIXED = Fixed burst address (handled as INCR) -- "01" INCR = Increment burst address -- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary -- "11" Reserved (not checked) AXI_AWLOCK : in std_logic; -- Currently unused AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused AXI_AWVALID : in std_logic; AXI_AWREADY : out std_logic; -- AXI Write Data Channel Signals (W) AXI_WDATA : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); AXI_WSTRB : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0); AXI_WLAST : in std_logic; AXI_WVALID : in std_logic; AXI_WREADY : out std_logic; -- AXI Write Data Response Channel Signals (B) AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_BRESP : out std_logic_vector(1 downto 0); AXI_BVALID : out std_logic; AXI_BREADY : in std_logic; -- ECC Register Interface Signals Enable_ECC : in std_logic; BRAM_Addr_En : out std_logic := '0'; FaultInjectClr : out std_logic := '0'; CE_Failing_We : out std_logic := '0'; Sl_CE : out std_logic := '0'; Sl_UE : out std_logic := '0'; Active_Wr : out std_logic := '0'; FaultInjectData : in std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0); FaultInjectECC : in std_logic_vector (C_ECC_WIDTH-1 downto 0); -- Single Port Arbitration Signals Arb2AW_Active : in std_logic; AW2Arb_Busy : out std_logic := '0'; AW2Arb_Active_Clr : out std_logic := '0'; AW2Arb_BVALID_Cnt : out std_logic_vector (2 downto 0) := (others => '0'); Sng_BRAM_Addr_Rst : out std_logic := '0'; Sng_BRAM_Addr_Ld_En : out std_logic := '0'; Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); Sng_BRAM_Addr_Inc : out std_logic := '0'; Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- BRAM Write Port Interface Signals BRAM_En : out std_logic := '0'; BRAM_WE : out std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); BRAM_WrData : out std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ); end entity wr_chnl; ------------------------------------------------------------------------------- architecture implementation of wr_chnl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error -- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response -- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error -- Set constants for AWLEN equal to a count of one or two beats. constant AXI_AWLEN_ONE : std_logic_vector (7 downto 0) := (others => '0'); constant AXI_AWLEN_TWO : std_logic_vector (7 downto 0) := "00000001"; constant AXI_AWSIZE_ONE : std_logic_vector (2 downto 0) := "001"; -- Determine maximum size for narrow burst length counter -- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits -- resulting in a count 3 downto 0 => so minimum counter width = 2 bits. -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits -- resulting in a count 31 downto 0 => so minimum counter width = 5 bits. constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8); constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); -- AXI Size Constants -- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte -- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes -- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM -- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM -- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM -- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM -- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM -- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM -- Determine max value of ARSIZE based on the AXI data width. -- Use function in axi_bram_ctrl_funcs package. constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH); -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" -- Move to full_axi module -- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8); -- Not used -- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR; constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8; -- AXI Burst Types -- AXI Spec 4.4 constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10"; constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01"; constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00"; -- Internal ECC data width size. constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Write Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type WR_ADDR_SM_TYPE is ( IDLE, LD_AWADDR ); signal wr_addr_sm_cs, wr_addr_sm_ns : WR_ADDR_SM_TYPE; signal aw_active_set : std_logic := '0'; signal aw_active_set_i : std_logic := '0'; signal aw_active_clr : std_logic := '0'; signal delay_aw_active_clr_cmb : std_logic := '0'; signal delay_aw_active_clr : std_logic := '0'; signal aw_active : std_logic := '0'; signal aw_active_d1 : std_logic := '0'; signal aw_active_re : std_logic := '0'; signal axi_awaddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal curr_awaddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0'); signal awaddr_pipe_ld : std_logic := '0'; signal awaddr_pipe_ld_i : std_logic := '0'; signal awaddr_pipe_sel : std_logic := '0'; -- '0' indicates mux select from AXI -- '1' indicates mux select from AW Addr Register signal axi_awaddr_full : std_logic := '0'; signal axi_awid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_awsize_pipe : std_logic_vector(2 downto 0) := (others => '0'); signal curr_awsize : std_logic_vector(2 downto 0) := (others => '0'); signal curr_awsize_reg : std_logic_vector (2 downto 0) := (others => '0'); -- Narrow Burst Signals signal curr_narrow_burst_cmb : std_logic := '0'; signal curr_narrow_burst : std_logic := '0'; signal curr_narrow_burst_en : std_logic := '0'; signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_addr_rst : std_logic := '0'; signal narrow_addr_ld_en : std_logic := '0'; signal narrow_addr_dec : std_logic := '0'; signal axi_awlen_pipe : std_logic_vector(7 downto 0) := (others => '0'); signal axi_awlen_pipe_1_or_2 : std_logic := '0'; signal curr_awlen : std_logic_vector(7 downto 0) := (others => '0'); signal curr_awlen_reg : std_logic_vector(7 downto 0) := (others => '0'); signal curr_awlen_reg_1_or_2 : std_logic := '0'; signal axi_awburst_pipe : std_logic_vector(1 downto 0) := (others => '0'); signal axi_awburst_pipe_fixed : std_logic := '0'; signal curr_awburst : std_logic_vector(1 downto 0) := (others => '0'); signal curr_wrap_burst : std_logic := '0'; signal curr_wrap_burst_reg : std_logic := '0'; signal curr_incr_burst : std_logic := '0'; signal curr_fixed_burst : std_logic := '0'; signal curr_fixed_burst_reg : std_logic := '0'; signal max_wrap_burst_mod : std_logic := '0'; signal axi_awready_int : std_logic := '0'; signal axi_aresetn_d1 : std_logic := '0'; signal axi_aresetn_d2 : std_logic := '0'; signal axi_aresetn_d3 : std_logic := '0'; signal axi_aresetn_re : std_logic := '0'; signal axi_aresetn_re_reg : std_logic := '0'; -- BRAM Address Counter signal bram_addr_ld_en : std_logic := '0'; signal bram_addr_ld_en_i : std_logic := '0'; signal bram_addr_ld_en_mod : std_logic := '0'; signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_inc : std_logic := '0'; signal bram_addr_inc_mod : std_logic := '0'; signal bram_addr_inc_wrap_mod : std_logic := '0'; signal bram_addr_rst : std_logic := '0'; signal bram_addr_rst_cmb : std_logic := '0'; signal narrow_bram_addr_inc : std_logic := '0'; signal narrow_bram_addr_inc_d1 : std_logic := '0'; signal narrow_bram_addr_inc_re : std_logic := '0'; signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal curr_ua_narrow_wrap : std_logic := '0'; signal curr_ua_narrow_incr : std_logic := '0'; signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Write Data Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type WR_DATA_SM_TYPE is ( IDLE, W8_AWADDR, -- W8_BREADY, SNG_WR_DATA, BRST_WR_DATA, -- NEW_BRST_WR_DATA, B2B_W8_WR_DATA --, -- B2B_W8_BRESP, -- W8_BRESP ); signal wr_data_sm_cs, wr_data_sm_ns : WR_DATA_SM_TYPE; type WR_DATA_SNG_SM_TYPE is ( IDLE, SNG_WR_DATA, BRST_WR_DATA ); signal wr_data_sng_sm_cs, wr_data_sng_sm_ns : WR_DATA_SNG_SM_TYPE; type WR_DATA_ECC_SM_TYPE is ( IDLE, RMW_RD_DATA, RMW_CHK_DATA, RMW_MOD_DATA, RMW_WR_DATA ); signal wr_data_ecc_sm_cs, wr_data_ecc_sm_ns : WR_DATA_ECC_SM_TYPE; -- Wr Data Buffer/Register signal wrdata_reg_ld : std_logic := '0'; signal axi_wready_int : std_logic := '0'; signal axi_wready_int_mod : std_logic := '0'; signal axi_wdata_full_cmb : std_logic := '0'; signal axi_wdata_full : std_logic := '0'; signal axi_wdata_empty : std_logic := '0'; signal axi_wdata_full_reg : std_logic := '0'; -- WE Generator Signals signal clr_bram_we_cmb : std_logic := '0'; signal clr_bram_we : std_logic := '0'; signal bram_we_ld : std_logic := '0'; signal axi_wr_burst_cmb : std_logic := '0'; signal axi_wr_burst : std_logic := '0'; signal wr_b2b_elgible : std_logic := '0'; -- CR # 609695 signal last_data_ack : std_logic := '0'; -- CR # 609695 signal last_data_ack_throttle : std_logic := '0'; signal last_data_ack_mod : std_logic := '0'; -- CR # 609695 signal w8_b2b_bresp : std_logic := '0'; signal axi_wlast_d1 : std_logic := '0'; signal axi_wlast_re : std_logic := '0'; -- Single Port Signals -- Write busy flags only used in ECC configuration -- when waiting for BVALID/BREADY handshake signal wr_busy_cmb : std_logic := '0'; signal wr_busy_reg : std_logic := '0'; -- Only used by ECC register module. signal active_wr_cmb : std_logic := '0'; signal active_wr_reg : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write Response Channel Signals ------------------------------------------------------------------------------- signal axi_bid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_bid_temp_full : std_logic := '0'; signal axi_bid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_bvalid_int : std_logic := '0'; signal axi_bvalid_set_cmb : std_logic := '0'; ------------------------------------------------------------------------------- -- Internal BRAM Signals ------------------------------------------------------------------------------- signal reset_bram_we : std_logic := '0'; signal set_bram_we_cmb : std_logic := '0'; signal set_bram_we : std_logic := '0'; signal bram_we_int : std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal bram_en_cmb : std_logic := '0'; signal bram_en_int : std_logic := '0'; signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_wrdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- ECC Signals ------------------------------------------------------------------------------- signal CorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1); signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence signal WrData : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal WrData_cmb : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal UE_Q : std_logic := '0'; ------------------------------------------------------------------------------- -- BVALID Signals ------------------------------------------------------------------------------- signal bvalid_cnt_inc : std_logic := '0'; signal bvalid_cnt_inc_d1 : std_logic := '0'; signal bvalid_cnt_dec : std_logic := '0'; signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0'); signal bvalid_cnt_amax : std_logic := '0'; signal bvalid_cnt_max : std_logic := '0'; signal bvalid_cnt_non_zero : std_logic := '0'; ------------------------------------------------------------------------------- -- BID FIFO Signals ------------------------------------------------------------------------------- signal bid_fifo_rst : std_logic := '0'; signal bid_fifo_ld_en : std_logic := '0'; signal bid_fifo_ld : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal bid_fifo_rd_en : std_logic := '0'; signal bid_fifo_rd : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal bid_fifo_not_empty : std_logic := '0'; signal bid_gets_fifo_load : std_logic := '0'; signal bid_gets_fifo_load_d1 : std_logic := '0'; signal first_fifo_bid : std_logic := '0'; signal b2b_fifo_bid : std_logic := '0'; ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- AXI Write Address Channel Output Signals --------------------------------------------------------------------------- AXI_AWREADY <= axi_awready_int; --------------------------------------------------------------------------- -- AXI Write Data Channel Output Signals --------------------------------------------------------------------------- -- WREADY same signal assertion regardless of ECC or single port configuration. AXI_WREADY <= axi_wready_int_mod; --------------------------------------------------------------------------- -- AXI Write Response Channel Output Signals --------------------------------------------------------------------------- AXI_BRESP <= axi_bresp_int; AXI_BVALID <= axi_bvalid_int; AXI_BID <= axi_bid_int; --------------------------------------------------------------------------- -- *** AXI Write Address Channel Interface *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_AW_PIPE_SNG -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AW_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate begin -- Unused AW pipeline (set default values) awaddr_pipe_ld <= '0'; axi_awaddr_pipe <= AXI_AWADDR; axi_awid_pipe <= AXI_AWID; axi_awsize_pipe <= AXI_AWSIZE; axi_awlen_pipe <= AXI_AWLEN; axi_awburst_pipe <= AXI_AWBURST; axi_awlen_pipe_1_or_2 <= '0'; axi_awburst_pipe_fixed <= '0'; axi_awaddr_full <= '0'; end generate GEN_AW_PIPE_SNG; --------------------------------------------------------------------------- -- Generate: GEN_AW_PIPE_DUAL -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AW_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate begin ----------------------------------------------------------------------- -- -- AXI Write Address Buffer/Register -- (mimic behavior of address pipeline for AXI_AWID) -- ----------------------------------------------------------------------- GEN_AWADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate begin REG_AWADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then axi_awaddr_pipe (i) <= AXI_AWADDR (i); else axi_awaddr_pipe (i) <= axi_awaddr_pipe (i); end if; end if; end process REG_AWADDR; end generate GEN_AWADDR; ----------------------------------------------------------------------- -- Register AWID REG_AWID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then axi_awid_pipe <= AXI_AWID; else axi_awid_pipe <= axi_awid_pipe; end if; end if; end process REG_AWID; --------------------------------------------------------------------------- -- In parallel to AWADDR pipeline and AWID -- Use same control signals to capture AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST. -- Register AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST REG_AWCTRL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then axi_awsize_pipe <= AXI_AWSIZE; axi_awlen_pipe <= AXI_AWLEN; axi_awburst_pipe <= AXI_AWBURST; else axi_awsize_pipe <= axi_awsize_pipe; axi_awlen_pipe <= axi_awlen_pipe; axi_awburst_pipe <= axi_awburst_pipe; end if; end if; end process REG_AWCTRL; --------------------------------------------------------------------------- -- Create signals that indicate value of AXI_AWLEN in pipeline stage -- Used to decode length of burst when BRAM address can be loaded early -- when pipeline is full. -- -- Add early decode of AWBURST in pipeline. REG_AWLEN_PIPE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then -- Create merge to decode AWLEN of ONE or TWO if (AXI_AWLEN = AXI_AWLEN_ONE) or (AXI_AWLEN = AXI_AWLEN_TWO) then axi_awlen_pipe_1_or_2 <= '1'; else axi_awlen_pipe_1_or_2 <= '0'; end if; -- Early decode on value in pipeline of AWBURST if (AXI_AWBURST = C_AXI_BURST_FIXED) then axi_awburst_pipe_fixed <= '1'; else axi_awburst_pipe_fixed <= '0'; end if; else axi_awlen_pipe_1_or_2 <= axi_awlen_pipe_1_or_2; axi_awburst_pipe_fixed <= axi_awburst_pipe_fixed; end if; end if; end process REG_AWLEN_PIPE; --------------------------------------------------------------------------- -- Create full flag for AWADDR pipeline -- Set when write address register is loaded. -- Cleared when write address stored in register is loaded into BRAM -- address counter. REG_WRADDR_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then axi_awaddr_full <= '0'; elsif (awaddr_pipe_ld = '1') then axi_awaddr_full <= '1'; else axi_awaddr_full <= axi_awaddr_full; end if; end if; end process REG_WRADDR_FULL; --------------------------------------------------------------------------- end generate GEN_AW_PIPE_DUAL; --------------------------------------------------------------------------- -- Generate: GEN_DUAL_ADDR_CNT -- Purpose: Instantiate BRAM address counter unique for wr_chnl logic -- only when controller configured in dual port mode. --------------------------------------------------------------------------- GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate begin ---------------------------------------------------------------------------- -- Replace I_ADDR_CNT module usage of pf_counter in proc_common library. -- Only need to use lower 12-bits of address due to max AXI burst size -- Since AXI guarantees bursts do not cross 4KB boundary, the counting part -- of I_ADDR_CNT can be reduced to max 4KB. -- -- Counter size is adjusted based on data width of BRAM. -- For example, 32-bit data width BRAM, BRAM_Addr (1:0) -- are fixed at "00". So, counter increments from -- (C_AXI_ADDR_WIDTH - 1 : C_BRAM_ADDR_ADJUST). ---------------------------------------------------------------------------- I_ADDR_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Reset usage differs from RD CHNL if (bram_addr_rst = '1') then bram_addr_int <= (others => '0'); elsif (bram_addr_ld_en_mod = '1') then bram_addr_int <= bram_addr_ld; elsif (bram_addr_inc_mod = '1') then bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <= bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12); bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <= std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1); end if; end if; end process I_ADDR_CNT; -- Set defaults to shared address counter -- Only used in single port configurations Sng_BRAM_Addr_Rst <= '0'; Sng_BRAM_Addr_Ld_En <= '0'; Sng_BRAM_Addr_Ld <= (others => '0'); Sng_BRAM_Addr_Inc <= '0'; end generate GEN_DUAL_ADDR_CNT; --------------------------------------------------------------------------- -- Generate: GEN_SNG_ADDR_CNT -- Purpose: When configured in single port BRAM mode, address counter -- is shared with rd_chnl module. Assign output signals here -- to counter instantiation at full_axi module level. --------------------------------------------------------------------------- GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate begin Sng_BRAM_Addr_Rst <= bram_addr_rst; Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod; Sng_BRAM_Addr_Ld <= bram_addr_ld; Sng_BRAM_Addr_Inc <= bram_addr_inc_mod; bram_addr_int <= Sng_BRAM_Addr; end generate GEN_SNG_ADDR_CNT; --------------------------------------------------------------------------- -- -- Add BRAM counter reset for @ end of transfer -- -- Create a unique BRAM address reset signal -- If the write transaction is throttling on the AXI bus, then -- the BRAM EN may get negated during the write transfer -- -- Use combinatorial output from SM, bram_addr_rst_cmb, but ensure the -- BRAM address is not reset while loading a new address. bram_addr_rst <= (not (S_AXI_AResetn)) or (bram_addr_rst_cmb and not (bram_addr_ld_en_mod) and not (bram_addr_inc_mod)); --------------------------------------------------------------------------- -- BRAM address counter load mux -- -- Either load BRAM counter directly from AXI bus or from stored registered value -- -- Added bram_addr_ld_wrap for loading on wrap burst types -- Use registered signal to indicate current operation is a WRAP burst -- -- Do not load bram_addr_ld_wrap when bram_addr_ld_en signal is asserted at beginning of write burst -- BRAM address counter load. Due to condition when max_wrap_burst_mod remains asserted, due to BRAM address -- counter not incrementing (at the end of the previous write burst). -- bram_addr_ld <= bram_addr_ld_wrap when -- (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else -- axi_awaddr_pipe (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR) -- when (awaddr_pipe_sel = '1') else -- AXI_AWADDR (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- Replace C_BRAM_ADDR_SIZE w/ C_AXI_ADDR_WIDTH parameter usage bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else axi_awaddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) when (awaddr_pipe_sel = '1') else AXI_AWADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); --------------------------------------------------------------------------- -- On wrap burst max loads (simultaneous BRAM address increment is asserted). -- Ensure that load has higher priority over increment. -- Use registered signal to indicate current operation is a WRAP burst -- bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or -- (max_wrap_burst_mod = '1' and -- curr_wrap_burst_reg = '1' and -- bram_addr_inc_mod = '1')) -- else '0'; -- Use duplicate version of bram_addr_ld_en in effort -- to reduce fanout of signal routed to BRAM address counter bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_inc_wrap_mod = '1')) else '0'; -- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal -- logic. No need for the check if the current operation is NOT a fixed AND a wrap -- burst. The transfer will be one or the other. -- Found issue when narrow FIXED length burst is incorrectly -- incrementing BRAM address counter bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0') else narrow_bram_addr_inc_re; ---------------------------------------------------------------------------- -- Handling for WRAP burst types -- -- For WRAP burst types, the counter value will roll over when the burst -- boundary is reached. -- Boundary is reached based on ARSIZE and ARLEN. -- -- Goal is to minimize muxing on initial load of counter value. -- On WRAP burst types, detect when the max address is reached. -- When the max address is reached, re-load counter with lower -- address value set to '0'. ---------------------------------------------------------------------------- -- Detect valid WRAP burst types curr_wrap_burst <= '1' when (curr_awburst = C_AXI_BURST_WRAP) else '0'; -- Detect INCR & FIXED burst type operations curr_incr_burst <= '1' when (curr_awburst = C_AXI_BURST_INCR) else '0'; curr_fixed_burst <= '1' when (curr_awburst = C_AXI_BURST_FIXED) else '0'; ---------------------------------------------------------------------------- -- Register curr_wrap_burst signal when BRAM address counter is initially -- loaded REG_CURR_WRAP_BRST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Add reset same as BRAM address counter if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then curr_wrap_burst_reg <= '0'; elsif (bram_addr_ld_en = '1') then curr_wrap_burst_reg <= curr_wrap_burst; else curr_wrap_burst_reg <= curr_wrap_burst_reg; end if; end if; end process REG_CURR_WRAP_BRST; ---------------------------------------------------------------------------- -- Register curr_fixed_burst signal when BRAM address counter is initially -- loaded REG_CURR_FIXED_BRST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Add reset same as BRAM address counter if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then curr_fixed_burst_reg <= '0'; elsif (bram_addr_ld_en = '1') then curr_fixed_burst_reg <= curr_fixed_burst; else curr_fixed_burst_reg <= curr_fixed_burst_reg; end if; end if; end process REG_CURR_FIXED_BRST; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Instance: I_WRAP_BRST -- -- Description: -- -- Instantiate WRAP_BRST module -- Logic to generate the wrap around value to load into the BRAM address -- counter on WRAP burst transactions. -- WRAP value is based on current AWLEN, AWSIZE (for narrows) and -- data width of BRAM module. -- --------------------------------------------------------------------------- I_WRAP_BRST : entity work.wrap_brst generic map ( C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , S_AXI_AResetn => S_AXI_AResetn , curr_axlen => curr_awlen , curr_axsize => curr_awsize , curr_narrow_burst => curr_narrow_burst , narrow_bram_addr_inc_re => narrow_bram_addr_inc_re , bram_addr_ld_en => bram_addr_ld_en , bram_addr_ld => bram_addr_ld , bram_addr_int => bram_addr_int , bram_addr_ld_wrap => bram_addr_ld_wrap , max_wrap_burst_mod => max_wrap_burst_mod ); --------------------------------------------------------------------------- -- Generate: GEN_WO_NARROW -- Purpose: Create BRAM address increment signal when narrow bursts -- are disabled. --------------------------------------------------------------------------- GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate begin -- For non narrow burst operations, use bram_addr_inc from data SM. -- Add in check that burst type is not FIXED, curr_fixed_burst_reg bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg); -- The signal, curr_narrow_burst should always be set to '0' when narrow bursts -- are disabled. curr_narrow_burst <= '0'; narrow_bram_addr_inc_re <= '0'; end generate GEN_WO_NARROW; --------------------------------------------------------------------------- -- Only instantiate NARROW_CNT and supporting logic when narrow transfers -- are supported and utilized by masters in the AXI system. -- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this. --------------------------------------------------------------------------- -- Generate: GEN_NARROW_CNT -- Purpose: Instantiate narrow counter and logic when narrow -- operation support is enabled. -- And, only instantiate logic for narrow operations when -- AXI bus protocol is not set for AXI-LITE. --------------------------------------------------------------------------- GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin -- Based on current operation being a narrow burst, hold off BRAM -- address increment until narrow burst fits BRAM data width. -- For non narrow burst operations, use bram_addr_inc from data SM. -- Add in check that burst type is not FIXED, curr_fixed_burst_reg bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') -- else narrow_bram_addr_inc_re; -- Seeing incorrect BRAM address increment on narrow -- fixed length burst operations. -- Add this check for curr_fixed_burst_reg else (narrow_bram_addr_inc_re and not (curr_fixed_burst_reg)); --------------------------------------------------------------------------- -- -- Generate seperate smaller counter for narrow burst operations -- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library. -- -- Counter size is adjusted based on size of data burst. -- -- For example, 32-bit data width BRAM, minimum narrow width -- burst is 8 bits resulting in a count 3 downto 0. So the -- minimum counter width = 2 bits. -- -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst -- is 8 bits resulting in a count 31 downto 0. So the -- minimum counter width = 5 bits. -- -- Size of counter = C_NARROW_BURST_CNT_LEN -- --------------------------------------------------------------------------- I_NARROW_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (narrow_addr_rst = '1') then narrow_addr_int <= (others => '0'); -- Load narrow address counter elsif (narrow_addr_ld_en = '1') then narrow_addr_int <= narrow_burst_cnt_ld_mod; -- Decrement ONLY (no increment functionality) elsif (narrow_addr_dec = '1') then narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <= std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1); end if; end if; end process I_NARROW_CNT; --------------------------------------------------------------------------- narrow_addr_rst <= not (S_AXI_AResetn); -- Narrow burst counter load mux -- Modify narrow burst count load value based on -- unalignment of AXI address value -- Account for INCR burst types at unaligned addresses narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else narrow_burst_cnt_ld_reg; narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0'; narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re; narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and (curr_narrow_burst = '1') -- Ensure that narrow address counter doesn't -- flag max or get loaded to -- reset narrow counter until AXI read data -- bus has acknowledged current -- data on the AXI bus. Use rd_adv_buf signal -- to indicate the non throttle -- condition on the AXI bus. and (bram_addr_inc = '1') else '0'; -- Detect rising edge of narrow_bram_addr_inc REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_bram_addr_inc_d1 <= '0'; else narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc; end if; end if; end process REG_NARROW_BRAM_ADDR_INC; narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and (narrow_bram_addr_inc_d1 = '0') else '0'; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT; --------------------------------------------------------------------------- -- Generate: GEN_AWREADY -- Purpose: AWREADY is only created here when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AWREADY: if (C_SINGLE_PORT_BRAM = 0) generate begin -- v1.03a ---------------------------------------------------------------------------- -- AXI_AWREADY Output Register -- Description: Keep AXI_AWREADY output asserted until AWADDR pipeline -- is full. When a full condition is reached, negate -- AWREADY as another AW address can not be accepted. -- Add condition to keep AWReady asserted if loading current --- AWADDR pipeline value into the BRAM address counter. -- Indicated by assertion of bram_addr_ld_en & awaddr_pipe_sel. -- ---------------------------------------------------------------------------- REG_AWREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_awready_int <= '0'; -- Detect end of S_AXI_AResetn to assert AWREADY and accept -- new AWADDR values elsif (axi_aresetn_re_reg = '1') or (bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then axi_awready_int <= '1'; elsif (awaddr_pipe_ld = '1') then axi_awready_int <= '0'; else axi_awready_int <= axi_awready_int; end if; end if; end process REG_AWREADY; ---------------------------------------------------------------------------- -- Need to detect end of reset cycle to assert AWREADY on AXI bus REG_ARESETN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then axi_aresetn_d1 <= S_AXI_AResetn; axi_aresetn_d2 <= axi_aresetn_d1; axi_aresetn_d3 <= axi_aresetn_d2; axi_aresetn_re_reg <= axi_aresetn_re; end if; end process REG_ARESETN; -- Create combinatorial RE detect of S_AXI_AResetn --axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0'; axi_aresetn_re <= '1' when (axi_aresetn_d1 = '1' and axi_aresetn_d2 = '0') else '0'; end generate GEN_AWREADY; ---------------------------------------------------------------------------- -- Specify current AWSIZE signal -- Address pipeline MUX curr_awsize <= axi_awsize_pipe when (awaddr_pipe_sel = '1') else AXI_AWSIZE; -- Register curr_awsize when bram_addr_ld_en = '1' REG_AWSIZE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_awsize_reg <= (others => '0'); elsif (bram_addr_ld_en = '1') then curr_awsize_reg <= curr_awsize; else curr_awsize_reg <= curr_awsize_reg; end if; end if; end process REG_AWSIZE; --------------------------------------------------------------------------- -- -- Generate: GEN_NARROW_EN -- Purpose: Only instantiate logic to determine if current burst -- is a narrow burst when narrow bursting logic is supported. -- --------------------------------------------------------------------------- GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin ----------------------------------------------------------------------- -- Determine "narrow" burst transfers -- Compare the AWSIZE to the BRAM data width ----------------------------------------------------------------------- -- v1.03a -- Detect if current burst operation is of size /= to the full -- AXI data bus width. If not, then the current operation is a -- "narrow" burst. curr_narrow_burst_cmb <= '1' when (curr_awsize /= C_AXI_SIZE_MAX) else '0'; --------------------------------------------------------------------------- curr_narrow_burst_en <= '1' when (bram_addr_ld_en = '1') and (curr_awlen /= AXI_AWLEN_ONE) and (curr_fixed_burst = '0') else '0'; -- Register flag indicating the current operation -- is a narrow write burst NARROW_BURST_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Need to reset this flag at end of narrow burst operation -- Use handshaking signals on AXI if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Check for back to back narrow burst. If that is the case, then -- do not clear curr_narrow_burst flag. (axi_wlast_re = '1' and curr_narrow_burst_en = '0' -- If ECC is enabled, no clear to curr_narrow_burst when WLAST is asserted -- this causes the BRAM address to incorrectly get asserted on the last -- beat in the burst (due to delay in RMW logic) and C_ECC = 0) then curr_narrow_burst <= '0'; elsif (curr_narrow_burst_en = '1') then curr_narrow_burst <= curr_narrow_burst_cmb; end if; end if; end process NARROW_BURST_REG; --------------------------------------------------------------------------- -- Detect RE of AXI_WLAST -- Only used when narrow bursts are enabled. WLAST_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_wlast_d1 <= '0'; else -- axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod; -- CR # 609695 axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod and AXI_WVALID; end if; end if; end process WLAST_REG; -- axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod) and not (axi_wlast_d1); -- CR # 609695 axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod and AXI_WVALID) and not (axi_wlast_d1); end generate GEN_NARROW_EN; --------------------------------------------------------------------------- -- Generate registered flag that active burst is a "narrow" burst -- and load narrow burst counter --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_NARROW_CNT_LD -- Purpose: Only instantiate logic to determine narrow burst counter -- load value when narrow bursts are enabled. -- --------------------------------------------------------------------------- GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate signal curr_awsize_unsigned : unsigned (2 downto 0) := (others => '0'); signal axi_byte_div_curr_awsize : integer := 1; begin -- v1.03a -- Create narrow burst counter load value based on current operation -- "narrow" data width (indicated by value of AWSIZE). curr_awsize_unsigned <= unsigned (curr_awsize); -- XST does not support divisors that are not constants and powers of 2. -- Create process to create a fixed value for divisor. -- Replace this statement: -- narrow_burst_cnt_ld <= std_logic_vector ( -- to_unsigned ( -- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_awsize_unsigned))) ) - 1, -- C_NARROW_BURST_CNT_LEN)); -- -- With this new process and subsequent signal assignment: -- DIV_AWSIZE: process (curr_awsize_unsigned) -- begin -- -- case (to_integer (curr_awsize_unsigned)) is -- when 0 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1; -- when 1 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2; -- when 2 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4; -- when 3 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8; -- when 4 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16; -- when 5 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32; -- when 6 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64; -- when 7 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128; -- --coverage off -- when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES; -- --coverage on -- end case; -- -- end process DIV_AWSIZE; -- w/ CR # 609695 -- With this new process and subsequent signal assignment: DIV_AWSIZE: process (curr_awsize_unsigned) begin case (curr_awsize_unsigned) is when "000" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1; when "001" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2; when "010" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4; when "011" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8; when "100" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16; when "101" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32; when "110" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64; when "111" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128; --coverage off when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES; --coverage on end case; end process DIV_AWSIZE; --------------------------------------------------------------------------- -- Create narrow burst count load value. -- -- Size is based on [C_NARROW_BURST_CNT_LEN-1 : 0] -- For 32-bit BRAM, C_NARROW_BURST_CNT_LEN = 2. -- For 64-bit BRAM, C_NARROW_BURST_CNT_LEN = 3. -- For 128-bit BRAM, C_NARROW_BURST_CNT_LEN = 4. (etc.) -- -- Signal, narrow_burst_cnt_ld signal is sized according to C_AXI_DATA_WIDTH. -- Updated else clause for simulation warnings w/ CR # 609695 narrow_burst_cnt_ld <= std_logic_vector ( to_unsigned ( (axi_byte_div_curr_awsize) - 1, C_NARROW_BURST_CNT_LEN)) when (axi_byte_div_curr_awsize > 0) else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN)); --------------------------------------------------------------------------- -- Register narrow_burst_cnt_ld REG_NAR_BRST_CNT_LD: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_burst_cnt_ld_reg <= (others => '0'); elsif (bram_addr_ld_en = '1') then narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld; else narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg; end if; end if; end process REG_NAR_BRST_CNT_LD; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT_LD; ---------------------------------------------------------------------------- -- Specify current AWBURST signal -- Input address pipeline MUX curr_awburst <= axi_awburst_pipe when (awaddr_pipe_sel = '1') else AXI_AWBURST; ---------------------------------------------------------------------------- -- Specify current AWBURST signal -- Input address pipeline MUX curr_awlen <= axi_awlen_pipe when (awaddr_pipe_sel = '1') else AXI_AWLEN; -- Duplicate early decode of AWLEN value to use in wr_b2b_elgible logic REG_CURR_AWLEN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_awlen_reg_1_or_2 <= '0'; elsif (bram_addr_ld_en = '1') then -- Create merge to decode AWLEN of ONE or TWO if (curr_awlen = AXI_AWLEN_ONE) or (curr_awlen = AXI_AWLEN_TWO) then curr_awlen_reg_1_or_2 <= '1'; else curr_awlen_reg_1_or_2 <= '0'; end if; else curr_awlen_reg_1_or_2 <= curr_awlen_reg_1_or_2; end if; end if; end process REG_CURR_AWLEN; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_UA_NARROW -- Purpose: Only instantiate logic for burst narrow WRAP operations when -- AXI bus protocol is not set for AXI-LITE and narrow -- burst operations are supported. -- --------------------------------------------------------------------------- GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin --------------------------------------------------------------------------- -- New logic to detect unaligned address on a narrow WRAP burst transaction. -- If this condition is met, then the narrow burst counter will be -- initially loaded with an offset value corresponding to the unalignment -- in the ARADDR value. -- Create a sub module for all logic to determine the narrow burst counter -- offset value on unaligned WRAP burst operations. -- Module generates the following signals: -- -- => curr_ua_narrow_wrap, to indicate the current -- operation is an unaligned narrow WRAP burst. -- -- => curr_ua_narrow_incr, to load narrow burst counter -- for unaligned INCR burst operations. -- -- => ua_narrow_load, narrow counter load value. -- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0) -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Instance: I_UA_NARROW -- -- Description: -- -- Creates a narrow burst count load value when an operation -- is an unaligned narrow WRAP or INCR burst type. Used by -- I_NARROW_CNT module. -- -- Logic is customized for each C_AXI_DATA_WIDTH. --------------------------------------------------------------------------- I_UA_NARROW : entity work.ua_narrow generic map ( C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN ) port map ( curr_wrap_burst => curr_wrap_burst , -- in curr_incr_burst => curr_incr_burst , -- in bram_addr_ld_en => bram_addr_ld_en , -- in curr_axlen => curr_awlen , -- in curr_axsize => curr_awsize , -- in curr_axaddr_lsb => curr_awaddr_lsb , -- in curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out curr_ua_narrow_incr => curr_ua_narrow_incr , -- out ua_narrow_load => ua_narrow_load -- out ); -- Use in all C_AXI_DATA_WIDTH generate statements -- Only probe least significant BRAM address bits -- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0. curr_awaddr_lsb <= axi_awaddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) when (awaddr_pipe_sel = '1') else AXI_AWADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0); end generate GEN_UA_NARROW; --------------------------------------------------------------------------- -- -- Generate: GEN_AW_SNG -- Purpose: If single port BRAM configuration, set all AW flags from -- logic generated in sng_port_arb module. -- --------------------------------------------------------------------------- GEN_AW_SNG: if (C_SINGLE_PORT_BRAM = 1) generate begin aw_active <= Arb2AW_Active; bram_addr_ld_en <= aw_active_re; AW2Arb_Active_Clr <= aw_active_clr; AW2Arb_Busy <= wr_busy_reg; AW2Arb_BVALID_Cnt <= bvalid_cnt; end generate GEN_AW_SNG; -- Rising edge detect of aw_active -- For single port configurations, aw_active = Arb2AW_Active. -- For dual port configurations, aw_active generated in ADDR SM. RE_AW_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then aw_active_d1 <= '0'; else aw_active_d1 <= aw_active; end if; end if; end process RE_AW_ACT; aw_active_re <= '1' when (aw_active = '1' and aw_active_d1 = '0') else '0'; --------------------------------------------------------------------------- -- -- Generate: GEN_AW_DUAL -- Purpose: Generate AW control state machine logic only when AXI4 -- controller is configured for dual port mode. In dual port -- mode, wr_chnl has full access over AW & port A of BRAM. -- --------------------------------------------------------------------------- GEN_AW_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate begin AW2Arb_Active_Clr <= '0'; -- Only used in single port case AW2Arb_Busy <= '0'; -- Only used in single port case AW2Arb_BVALID_Cnt <= (others => '0'); ---------------------------------------------------------------------------- REG_LAST_DATA_ACK: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then last_data_ack_mod <= '0'; else -- last_data_ack_mod <= AXI_WLAST; -- CR # 609695 last_data_ack_mod <= AXI_WLAST and AXI_WVALID and axi_wready_int_mod; end if; end if; end process REG_LAST_DATA_ACK; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- WR ADDR State Machine -- -- Description: Central processing unit for AXI write address -- channel interface handling and handshaking. -- -- Outputs: awaddr_pipe_ld Combinatorial -- awaddr_pipe_sel -- bram_addr_ld_en -- -- -- -- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine. --------------------------------------------------------------------------- WR_ADDR_SM_CMB_PROCESS: process ( AXI_AWVALID, bvalid_cnt_max, axi_awaddr_full, aw_active, wr_b2b_elgible, last_data_ack_mod, wr_addr_sm_cs ) begin -- assign default values for state machine outputs wr_addr_sm_ns <= wr_addr_sm_cs; awaddr_pipe_ld_i <= '0'; bram_addr_ld_en_i <= '0'; aw_active_set_i <= '0'; case wr_addr_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Check for pending operation in address pipeline that may -- be elgible for back-to-back performance to BRAM. -- Prevent loading BRAM address counter if BID FIFO can not -- store the AWID value. Check the BVALID counter. if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then wr_addr_sm_ns <= IDLE; -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; -- Ensure AWVALID is recognized. -- Address pipeline may be loaded, but BRAM counter -- can not be loaded if at max of BID FIFO. elsif (AXI_AWVALID = '1') then -- If address pipeline is full -- AWReady output is negated -- If write address logic is ready for new operation -- Load BRAM address counter and set aw_active = '1' -- If address pipeline is already full to start next operation -- load address counter from pipeline. -- Prevent loading BRAM address counter if BID FIFO can not -- store the AWID value. Check the BVALID counter. -- Remain in this state if (aw_active = '0') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then wr_addr_sm_ns <= IDLE; -- Stay in this state to capture AWVALID if asserted -- in next clock cycle. bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; -- Address counter is currently busy. -- No check on BVALID counter for address pipeline load. -- Only the BRAM address counter is checked for BID FIFO capacity. else -- Check if AWADDR pipeline is not full and can be loaded if (axi_awaddr_full = '0') then wr_addr_sm_ns <= LD_AWADDR; awaddr_pipe_ld_i <= '1'; end if; end if; -- aw_active -- Pending operation in pipeline that is waiting -- until current operation is complete (aw_active = '0') elsif (axi_awaddr_full = '1') and (aw_active = '0') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then wr_addr_sm_ns <= IDLE; -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; end if; -- AWVALID ---------------------------- LD_AWADDR State --------------------------- when LD_AWADDR => wr_addr_sm_ns <= IDLE; if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; end if; --coverage off ------------------------------ Default ---------------------------- when others => wr_addr_sm_ns <= IDLE; --coverage on end case; end process WR_ADDR_SM_CMB_PROCESS; --------------------------------------------------------------------------- -- CR # 582705 -- Ensure combinatorial SM output signals do not get set before -- the end of the reset (and ARREAADY can be set). bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d3; aw_active_set <= aw_active_set_i and axi_aresetn_d3; awaddr_pipe_ld <= awaddr_pipe_ld_i and axi_aresetn_d3; WR_ADDR_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- if (S_AXI_AResetn = C_RESET_ACTIVE) then -- CR # 582705 -- Ensure that ar_active does not get asserted (from SM) before -- the end of reset and the ARREADY flag is set. if (axi_aresetn_d3 = C_RESET_ACTIVE) then wr_addr_sm_cs <= IDLE; else wr_addr_sm_cs <= wr_addr_sm_ns; end if; end if; end process WR_ADDR_SM_REG_PROCESS; --------------------------------------------------------------------------- -- Asserting awaddr_pipe_sel outside of SM logic -- The BRAM address counter will get loaded with value in AWADDR pipeline -- when data is stored in the AWADDR pipeline. awaddr_pipe_sel <= '1' when (axi_awaddr_full = '1') else '0'; --------------------------------------------------------------------------- -- Register for aw_active REG_AW_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- CR # 582705 -- if (S_AXI_AResetn = C_RESET_ACTIVE) then if (axi_aresetn_d3 = C_RESET_ACTIVE) then aw_active <= '0'; elsif (aw_active_set = '1') then aw_active <= '1'; elsif (aw_active_clr = '1') then aw_active <= '0'; else aw_active <= aw_active; end if; end if; end process REG_AW_ACT; --------------------------------------------------------------------------- end generate GEN_AW_DUAL; --------------------------------------------------------------------------- -- *** AXI Write Data Channel Interface *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- AXI WrData Buffer/Register --------------------------------------------------------------------------- GEN_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate begin REG_WRDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (wrdata_reg_ld = '1') then bram_wrdata_int (i) <= AXI_WDATA (i); else bram_wrdata_int (i) <= bram_wrdata_int (i); end if; end if; end process REG_WRDATA; end generate GEN_WRDATA; --------------------------------------------------------------------------- -- Generate: GEN_WR_NO_ECC -- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA -- and AXI_WSTRBs when C_ECC is disabled. --------------------------------------------------------------------------- GEN_WR_NO_ECC: if C_ECC = 0 generate begin --------------------------------------------------------------------------- -- AXI WSTRB Buffer/Register -- Use AXI write data channel data strobe signals to generate BRAM WE. --------------------------------------------------------------------------- REG_BRAM_WE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Ensure we don't clear WE when loading subsequent WSTRB value if (S_AXI_AResetn = C_RESET_ACTIVE) or (clr_bram_we = '1' and bram_we_ld = '0') then bram_we_int <= (others => '0'); elsif (bram_we_ld = '1') then bram_we_int <= AXI_WSTRB; else bram_we_int <= bram_we_int; end if; end if; end process REG_BRAM_WE; ---------------------------------------------------------------------------- -- New logic to detect if pending operation in AWADDR pipeline is -- elgible for back-to-back no "bubble" performance. And BRAM address -- counter can be loaded upon last BRAM address presented for the current -- operation. -- This condition exists when the AWADDR pipeline is full and the pending -- operation is a burst >= length of two data beats. -- And not a FIXED burst type (must be INCR or WRAP type). -- -- Narrow bursts are be neglible -- -- Add check to complete current single and burst of two data bursts -- prior to loading BRAM counter wr_b2b_elgible <= '1' when (axi_awaddr_full = '1') and -- Replace comparator logic here with register signal (pre pipeline stage -- on axi_awlen_pipe value -- Use merge in decode of ONE or TWO (axi_awlen_pipe_1_or_2 /= '1') and (axi_awburst_pipe_fixed /= '1') and -- Use merge in decode of ONE or TWO (curr_awlen_reg_1_or_2 /= '1') else '0'; ---------------------------------------------------------------------------- end generate GEN_WR_NO_ECC; --------------------------------------------------------------------------- -- Generate: GEN_WR_ECC -- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA -- and AXI_WSTRBs when C_ECC is enabled. --------------------------------------------------------------------------- GEN_WR_ECC: if C_ECC = 1 generate begin wr_b2b_elgible <= '0'; --------------------------------------------------------------------------- -- AXI WSTRB Buffer/Register -- Use AXI write data channel data strobe signals to generate BRAM WE. --------------------------------------------------------------------------- REG_BRAM_WE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Ensure we don't clear WE when loading subsequent WSTRB value if (S_AXI_AResetn = C_RESET_ACTIVE) or (reset_bram_we = '1') then bram_we_int <= (others => '0'); elsif (set_bram_we = '1') then bram_we_int <= (others => '1'); else bram_we_int <= bram_we_int; end if; end if; end process REG_BRAM_WE; end generate GEN_WR_ECC; ----------------------------------------------------------------------- -- v1.03a ----------------------------------------------------------------------- -- -- Implement WREADY to be a registered output. Used by all configurations. -- This will disable the back-to-back streamlined WDATA -- for write operations to BRAM. -- ----------------------------------------------------------------------- REG_WREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_wready_int_mod <= '0'; -- Keep AXI WREADY asserted unless write data register is full -- Use combinatorial signal from SM. elsif (axi_wdata_full_cmb = '1') then axi_wready_int_mod <= '0'; else axi_wready_int_mod <= '1'; end if; end if; end process REG_WREADY; --------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- Generate: GEN_WDATA_SM_ECC -- Purpose: Create seperate SM for ECC read-modify-write logic. -- Only used in single port BRAM mode. So, no address -- pipelining. Must use aw_active from arbitration logic -- to determine start of write to BRAM. -- ---------------------------------------------------------------------------- -- Test using same write data SM for single or dual port configuration. -- The difference is the source of aw_active. In a single port configuration, -- the aw_active is coming from the arbiter SM. In a dual port configuration, -- the aw_active is coming from the write address SM in this module. GEN_WDATA_SM_ECC: if C_ECC = 1 generate begin -- Unused in this SM configuration bram_we_ld <= '0'; bram_addr_rst_cmb <= '0'; -- Output only used by ECC register module. Active_Wr <= active_wr_reg; --------------------------------------------------------------------------- -- -- WR DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking when ECC is enabled. SM will handle -- each transaction as a read-modify-write to ensure -- the correct ECC bits are stored in BRAM. -- -- Dedicated to single port BRAM interface. Transaction -- is not initiated until valid AWADDR is arbitration, -- ie. aw_active will be asserted. SM can do early reads -- while waiting for WVALID to be asserted. -- -- Valid AWADDR recieve indicator comes from arbitration -- logic (aw_active will be asserted). -- -- Outputs: Name Type -- -- aw_active_clr Not Registered -- axi_wdata_full_reg Registered -- wrdata_reg_ld Not Registered -- bvalid_cnt_inc Not Registered -- bram_addr_inc Not Registered -- bram_en_int Registered -- reset_bram_we Not Registered -- set_bram_we Not Registered -- -- -- WR_DATA_ECC_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_DATA_ECC_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- WR_DATA_ECC_SM_CMB_PROCESS: process ( AXI_WVALID, AXI_WLAST, aw_active, wr_busy_reg, axi_wdata_full_reg, axi_wr_burst, AXI_BREADY, active_wr_reg, wr_data_ecc_sm_cs ) begin -- Assign default values for state machine outputs wr_data_ecc_sm_ns <= wr_data_ecc_sm_cs; aw_active_clr <= '0'; wr_busy_cmb <= wr_busy_reg; bvalid_cnt_inc <= '0'; wrdata_reg_ld <= '0'; reset_bram_we <= '0'; set_bram_we_cmb <= '0'; bram_en_cmb <= '0'; bram_addr_inc <= '0'; axi_wdata_full_cmb <= axi_wdata_full_reg; axi_wr_burst_cmb <= axi_wr_burst; active_wr_cmb <= active_wr_reg; case wr_data_ecc_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Prior to AWVALID assertion, WVALID may be asserted -- and data accepted into WDATA register. -- Catch this condition and ensure the register full flag is set. -- Check that data pipeline is not already full. if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then wrdata_reg_ld <= '1'; -- Load write data register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data -- w/ CR # 609695 -- -- -- Set flag to check if single or not -- if (AXI_WLAST = '1') then -- axi_wr_burst_cmb <= '0'; -- else -- axi_wr_burst_cmb <= '1'; -- end if; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not end if; -- Check if AWVALID is asserted & wins arbitration if (aw_active = '1') then active_wr_cmb <= '1'; -- Set flag that RMW SM is active -- Controls mux select for BRAM and ECC register module -- (Set to '1' wr_chnl or '0' for rd_chnl control) bram_en_cmb <= '1'; -- Initiate BRAM read transfer reset_bram_we <= '1'; -- Disable Port A write enables -- Will proceed to read-modify-write if we get a -- valid write address early (before WVALID) wr_data_ecc_sm_ns <= RMW_RD_DATA; end if; -- WVALID ------------------------- RMW_RD_DATA State ------------------------- when RMW_RD_DATA => -- Check if data to write is available in data pipeline if (axi_wdata_full_reg = '1') then wr_data_ecc_sm_ns <= RMW_CHK_DATA; -- Else may have address, but not yet data from W channel elsif (AXI_WVALID = '1') then -- Ensure that WDATA pipeline is marked as full, so WREADY negates axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data wrdata_reg_ld <= '1'; -- Load write data register -- w/ CR # 609695 -- -- -- Set flag to check if single or not -- if (AXI_WLAST = '1') then -- axi_wr_burst_cmb <= '0'; -- else -- axi_wr_burst_cmb <= '1'; -- end if; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not wr_data_ecc_sm_ns <= RMW_CHK_DATA; else -- Hold here and wait for write data wr_data_ecc_sm_ns <= RMW_RD_DATA; end if; ------------------------- RMW_CHK_DATA State ------------------------- when RMW_CHK_DATA => -- New state here to add register stage on calculating -- checkbits for read data and then muxing/creating new -- checkbits for write cycle. -- Go immediately to MODIFY stage in RMW sequence wr_data_ecc_sm_ns <= RMW_MOD_DATA; set_bram_we_cmb <= '1'; -- Enable all WEs to BRAM ------------------------- RMW_MOD_DATA State ------------------------- when RMW_MOD_DATA => -- Modify clock cycle in RMW sequence -- Only reach this state after a read AND we have data -- in the write data pipeline to modify and subsequently write to BRAM. bram_en_cmb <= '1'; -- Initiate BRAM write transfer -- Can clear WDATA pipeline full condition flag if (axi_wr_burst = '1') then axi_wdata_full_cmb <= '0'; end if; wr_data_ecc_sm_ns <= RMW_WR_DATA; -- Go to write data to BRAM ------------------------- RMW_WR_DATA State ------------------------- when RMW_WR_DATA => -- Check if last data beat in a burst (or the write is a single) if (axi_wr_burst = '0') then -- Can clear WDATA pipeline full condition flag now that -- write data has gone out to BRAM (for single data transfers) axi_wdata_full_cmb <= '0'; bvalid_cnt_inc <= '1'; -- Set flag to assert BVALID and increment counter wr_data_ecc_sm_ns <= IDLE; -- Go back to IDLE, BVALID assertion is seperate wr_busy_cmb <= '0'; -- Clear flag to arbiter active_wr_cmb <= '0'; -- Clear flag (wr_chnl is done accessing BRAM) -- Used for single port arbitration SM axi_wr_burst_cmb <= '0'; aw_active_clr <= '1'; -- Clear aw_active flag reset_bram_we <= '1'; -- Disable Port A write enables else -- Continue with read-modify-write sequence for write burst -- If next data beat is available on AXI, capture the data if (AXI_WVALID = '1') then wrdata_reg_ld <= '1'; -- Load write data register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data -- w/ CR # 609695 -- -- -- Set flag to check if single or not -- if (AXI_WLAST = '1') then -- axi_wr_burst_cmb <= '0'; -- else -- axi_wr_burst_cmb <= '1'; -- end if; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not end if; -- After write cycle (in RMW) => Increment BRAM address counter bram_addr_inc <= '1'; bram_en_cmb <= '1'; -- Initiate BRAM read transfer reset_bram_we <= '1'; -- Disable Port A write enables -- Will proceed to read-modify-write if we get a -- valid write address early (before WVALID) wr_data_ecc_sm_ns <= RMW_RD_DATA; end if; --coverage off ------------------------------ Default ---------------------------- when others => wr_data_ecc_sm_ns <= IDLE; --coverage on end case; end process WR_DATA_ECC_SM_CMB_PROCESS; --------------------------------------------------------------------------- WR_DATA_ECC_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then wr_data_ecc_sm_cs <= IDLE; bram_en_int <= '0'; axi_wdata_full_reg <= '0'; wr_busy_reg <= '0'; active_wr_reg <= '0'; set_bram_we <= '0'; else wr_data_ecc_sm_cs <= wr_data_ecc_sm_ns; bram_en_int <= bram_en_cmb; axi_wdata_full_reg <= axi_wdata_full_cmb; wr_busy_reg <= wr_busy_cmb; active_wr_reg <= active_wr_cmb; set_bram_we <= set_bram_we_cmb; end if; end if; end process WR_DATA_ECC_SM_REG_PROCESS; --------------------------------------------------------------------------- end generate GEN_WDATA_SM_ECC; -- v1.03a ---------------------------------------------------------------------------- -- -- Generate: GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY -- Purpose: Create seperate SM use case of no ECC (no read-modify-write) -- and single port BRAM configuration (no back to back operations -- are supported). Must wait for aw_active from arbiter to indicate -- control on BRAM interface. -- ---------------------------------------------------------------------------- GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY: if C_ECC = 0 and C_SINGLE_PORT_BRAM = 1 generate begin -- Unused in this SM configuration wr_busy_cmb <= '0'; -- Unused wr_busy_reg <= '0'; -- Unused active_wr_cmb <= '0'; -- Unused active_wr_reg <= '0'; -- Unused Active_Wr <= '0'; -- Unused --------------------------------------------------------------------------- -- -- WR DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking. -- -- Outputs: Name Type -- aw_active_clr Not Registered -- bvalid_cnt_inc Not Registered -- wrdata_reg_ld Not Registered -- bram_we_ld Not Registered -- bram_en_int Registered -- clr_bram_we Registered -- bram_addr_inc Not Registered -- wrdata_reg_ld Not Registered -- -- Note: -- -- On "narrow burst transfers" BRAM address only -- gets incremented at BRAM data width. -- On WRAP bursts, the BRAM address must wrap when -- the max is reached -- -- -- -- WR_DATA_SNG_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_DATA_SNG_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- WR_DATA_SNG_SM_CMB_PROCESS: process ( AXI_WVALID, AXI_WLAST, aw_active, axi_wr_burst, axi_wdata_full_reg, wr_data_sng_sm_cs ) begin -- assign default values for state machine outputs wr_data_sng_sm_ns <= wr_data_sng_sm_cs; aw_active_clr <= '0'; bvalid_cnt_inc <= '0'; axi_wr_burst_cmb <= axi_wr_burst; wrdata_reg_ld <= '0'; bram_we_ld <= '0'; bram_en_cmb <= '0'; clr_bram_we_cmb <= '0'; bram_addr_inc <= '0'; bram_addr_rst_cmb <= '0'; axi_wdata_full_cmb <= axi_wdata_full_reg; case wr_data_sng_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Prior to AWVALID assertion, WVALID may be asserted -- and data accepted into WDATA register. -- Catch this condition and ensure the register full flag is set. -- Check that data pipeline is not already full. -- -- Modify WE pipeline and mux to BRAM -- as well. Since WE may be asserted early (when pipeline is loaded), -- but not yet ready to go out to BRAM. -- -- Only first data beat will be accepted early into data pipeline. -- All remaining beats in a burst will only be accepted upon WVALID. if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not end if; -- Wait for WVALID and aw_active to initiate write transfer if (aw_active = '1' and (AXI_WVALID = '1' or axi_wdata_full_reg = '1')) then -- If operation is a single, then it goes directly out to BRAM -- WDATA register is never marked as FULL in this case. -- If data pipeline is not previously loaded, do so now. if (axi_wdata_full_reg = '0') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register end if; -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- If data goes out to BRAM, mark data register as EMPTY axi_wdata_full_cmb <= '0'; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not -- Check for singles, by checking WLAST assertion w/ WVALID -- Only if write data pipeline is not yet filled, check WLAST -- Otherwise, if pipeline is already full, use registered value of WLAST -- to check for single vs. burst write operation. if (AXI_WLAST = '1' and axi_wdata_full_reg = '0') or (axi_wdata_full_reg = '1' and axi_wr_burst = '0') then -- Single data write wr_data_sng_sm_ns <= SNG_WR_DATA; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; else -- Burst data write wr_data_sng_sm_ns <= BRST_WR_DATA; end if; -- WLAST end if; ------------------------- SNG_WR_DATA State ------------------------- when SNG_WR_DATA => -- If WREADY is registered, then BVALID generation is seperate -- from write data flow. -- Go back to IDLE automatically -- BVALID will get asserted seperately from W channel wr_data_sng_sm_ns <= IDLE; bram_addr_rst_cmb <= '1'; aw_active_clr <= '1'; -- Check for capture of next data beat (WREADY will be asserted) if (AXI_WVALID = '1') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not else axi_wdata_full_cmb <= '0'; -- If no next data, ensure data register is flagged EMPTY. end if; ------------------------- BRST_WR_DATA State ------------------------- when BRST_WR_DATA => -- Reach this state at the 2nd data beat of a burst -- AWADDR is already accepted -- Continue to accept data from AXI write channel -- and wait for assertion of WLAST -- Check that WVALID remains asserted for burst -- If negated, indicates throttling from AXI master if (AXI_WVALID = '1') then -- If WVALID is asserted for the 2nd and remaining -- data beats of the transfer -- Continue w/ BRAM write enable assertion & advance -- write data register -- Write data goes directly out to BRAM. -- WDATA register is never marked as FULL in this case. wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Increment BRAM address counter bram_addr_inc <= '1'; -- Check for last data beat in burst transfer if (AXI_WLAST = '1') then -- Last/single data write wr_data_sng_sm_ns <= SNG_WR_DATA; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; end if; -- WLAST -- Throttling -- Suspend BRAM write & halt write data & WE register load else -- Negate write data register load wrdata_reg_ld <= '0'; -- Negate WE register load bram_we_ld <= '0'; -- Negate write to BRAM bram_en_cmb <= '0'; -- Do not increment BRAM address counter bram_addr_inc <= '0'; end if; -- WVALID --coverage off ------------------------------ Default ---------------------------- when others => wr_data_sng_sm_ns <= IDLE; --coverage on end case; end process WR_DATA_SNG_SM_CMB_PROCESS; --------------------------------------------------------------------------- WR_DATA_SNG_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then wr_data_sng_sm_cs <= IDLE; bram_en_int <= '0'; clr_bram_we <= '0'; axi_wdata_full_reg <= '0'; else wr_data_sng_sm_cs <= wr_data_sng_sm_ns; bram_en_int <= bram_en_cmb; clr_bram_we <= clr_bram_we_cmb; axi_wdata_full_reg <= axi_wdata_full_cmb; end if; end if; end process WR_DATA_SNG_SM_REG_PROCESS; --------------------------------------------------------------------------- end generate GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY; ---------------------------------------------------------------------------- -- -- Generate: GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY -- -- Purpose: Create seperate SM for new logic to register out WREADY -- signal. Behavior for back-to-back operations is different -- than with combinatorial genearted WREADY output to AXI. -- -- New SM design supports seperate WREADY and BVALID responses. -- -- New logic here for axi_bvalid_int output register based -- on counter design of BVALID. -- ---------------------------------------------------------------------------- GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY: if C_ECC = 0 and C_SINGLE_PORT_BRAM = 0 generate begin -- Unused in this SM configuration active_wr_cmb <= '0'; -- Unused active_wr_reg <= '0'; -- Unused Active_Wr <= '0'; -- Unused wr_busy_cmb <= '0'; -- Unused wr_busy_reg <= '0'; -- Unused --------------------------------------------------------------------------- -- -- WR DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking. -- -- Outputs: Name Type -- bvalid_cnt_inc Not Registered -- aw_active_clr Not Registered -- delay_aw_active_clr Registered -- axi_wdata_full_reg Registered -- bram_en_int Registered -- wrdata_reg_ld Not Registered -- bram_we_ld Not Registered -- clr_bram_we Registered -- bram_addr_inc -- -- Note: -- -- On "narrow burst transfers" BRAM address only -- gets incremented at BRAM data width. -- On WRAP bursts, the BRAM address must wrap when -- the max is reached -- -- Add check on BVALID counter max. Check with -- AWVALID assertions (since AWID is connected to AWVALID). -- -- -- WR_DATA_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_DATA_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- WR_DATA_SM_CMB_PROCESS: process ( AXI_WVALID, AXI_WLAST, bvalid_cnt_max, bvalid_cnt_amax, aw_active, delay_aw_active_clr, AXI_AWVALID, axi_awready_int, bram_addr_ld_en, axi_awaddr_full, awaddr_pipe_sel, axi_wr_burst, axi_wdata_full_reg, wr_b2b_elgible, wr_data_sm_cs ) begin -- assign default values for state machine outputs wr_data_sm_ns <= wr_data_sm_cs; aw_active_clr <= '0'; delay_aw_active_clr_cmb <= delay_aw_active_clr; bvalid_cnt_inc <= '0'; axi_wr_burst_cmb <= axi_wr_burst; wrdata_reg_ld <= '0'; bram_we_ld <= '0'; bram_en_cmb <= '0'; clr_bram_we_cmb <= '0'; bram_addr_inc <= '0'; bram_addr_rst_cmb <= '0'; axi_wdata_full_cmb <= axi_wdata_full_reg; case wr_data_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Check valid write data on AXI write data channel if (AXI_WVALID = '1') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register -- Add condition to check for simultaneous assertion -- of AWVALID and AWREADY if ((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Check for singles, by checking WLAST assertion w/ WVALID if (AXI_WLAST = '1') then -- Single data write wr_data_sm_ns <= SNG_WR_DATA; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- Set flag to delay clear of AW active flag delay_aw_active_clr_cmb <= '1'; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; axi_wr_burst_cmb <= '0'; else -- Burst data write wr_data_sm_ns <= BRST_WR_DATA; axi_wr_burst_cmb <= '1'; end if; -- WLAST else -- AWADDR not yet received -- Go to wait for write address wr_data_sm_ns <= W8_AWADDR; -- Set flag that AXI write data pipe is full -- and can not accept any more data beats -- WREADY on AXI will negate in this condition. axi_wdata_full_cmb <= '1'; -- Set flag for single/burst write operation -- when AWADDR is not yet received if (AXI_WLAST = '1') then axi_wr_burst_cmb <= '0'; else axi_wr_burst_cmb <= '1'; end if; -- WLAST end if; -- aw_active end if; -- WVALID ------------------------- W8_AWADDR State ------------------------- when W8_AWADDR => -- As we transition into this state, the write data pipeline -- is already filled. axi_wdata_full_reg should be = '1'. -- Disable any additional loads into write data register -- Default value in SM is applied. -- Wait for write address to be acknowledged if (((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) or -- Detect load of BRAM address counter from value stored in pipeline. -- No need to wait until aw_active is asserted or address is captured from AXI bus. -- As BRAM address is loaded from pipe and ready to be presented to BRAM. -- Assert BRAM WE. (bram_addr_ld_en = '1' and axi_awaddr_full = '1' and awaddr_pipe_sel = '1')) and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Negate write data full condition axi_wdata_full_cmb <= '0'; -- Check if single or burst operation if (axi_wr_burst = '1') then wr_data_sm_ns <= BRST_WR_DATA; else wr_data_sm_ns <= SNG_WR_DATA; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; delay_aw_active_clr_cmb <= '1'; end if; else -- Set flag that AXI write data pipe is full -- and can not accept any more data beats -- WREADY on AXI will negate in this condition. axi_wdata_full_cmb <= '1'; end if; ------------------------- SNG_WR_DATA State ------------------------- when SNG_WR_DATA => -- No need to check for BVALID assertion here. -- Move here under if clause on write response channel -- acknowledging completion of write data. -- If aw_active was not cleared prior to this state, then -- clear the flag now. if (delay_aw_active_clr = '1') then delay_aw_active_clr_cmb <= '0'; aw_active_clr <= '1'; end if; -- Add check here if while writing single data beat to BRAM, -- a new AXI data beat is received (prior to the AWVALID assertion). -- Ensure here that full flag is asserted for data pipeline state. -- Check valid write data on AXI write data channel if (AXI_WVALID = '1') then -- Load write data register wrdata_reg_ld <= '1'; -- Must also load WE register bram_we_ld <= '1'; -- Set flag that AXI write data pipe is full -- and can not accept any more data beats -- WREADY on AXI will negate in this condition. -- Ensure that axi_wdata_full_reg is asserted -- to prevent early captures on next data burst (or single data -- transfer) -- This ensures that the data beats do not get skipped. axi_wdata_full_cmb <= '1'; -- AWADDR not yet received -- Go to wait for write address wr_data_sm_ns <= W8_AWADDR; -- Accept no more new write data after this first data beat -- Pipeline is already full in this state. No need to assert -- no_wdata_accept flag to '1'. -- Set flag for single/burst write operation -- when AWADDR is not yet received if (AXI_WLAST = '1') then axi_wr_burst_cmb <= '0'; else axi_wr_burst_cmb <= '1'; end if; -- WLAST else -- No subsequent pending operation -- Return to IDLE wr_data_sm_ns <= IDLE; bram_addr_rst_cmb <= '1'; end if; ------------------------- BRST_WR_DATA State ------------------------- when BRST_WR_DATA => -- Reach this state at the 2nd data beat of a burst -- AWADDR is already accepted -- Continue to accept data from AXI write channel -- and wait for assertion of WLAST -- Check that WVALID remains asserted for burst -- If negated, indicates throttling from AXI master if (AXI_WVALID = '1') then -- If WVALID is asserted for the 2nd and remaining -- data beats of the transfer -- Continue w/ BRAM write enable assertion & advance -- write data register wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register bram_en_cmb <= '1'; -- Initiate BRAM write transfer bram_addr_inc <= '1'; -- Increment BRAM address counter -- Check for last data beat in burst transfer if (AXI_WLAST = '1') then -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- The elgible signal will not be asserted for a subsequent -- single data beat operation. Next operation is a burst. -- And the AWADDR is loaded in the address pipeline. -- Only if BVALID counter can handle next transfer, -- proceed with back-to-back. Otherwise, go to IDLE -- (after last data write). if (wr_b2b_elgible = '1' and bvalid_cnt_amax = '0') then -- Go to next operation and handle as a -- back-to-back burst. No empty clock cycles. -- Go to handle new burst for back to back condition wr_data_sm_ns <= B2B_W8_WR_DATA; axi_wr_burst_cmb <= '1'; -- No pending subsequent transfer (burst > 2 data beats) -- to process else -- Last/single data write wr_data_sm_ns <= SNG_WR_DATA; -- Be sure to clear aw_active flag at end of write burst -- But delay when the flag is cleared delay_aw_active_clr_cmb <= '1'; end if; end if; -- WLAST -- Throttling -- Suspend BRAM write & halt write data & WE register load else wrdata_reg_ld <= '0'; -- Negate write data register load bram_we_ld <= '0'; -- Negate WE register load bram_en_cmb <= '0'; -- Negate write to BRAM bram_addr_inc <= '0'; -- Do not increment BRAM address counter end if; -- WVALID ------------------------- B2B_W8_WR_DATA -------------------------- when B2B_W8_WR_DATA => -- Reach this state upon a back-to-back condition -- when BVALID/BREADY handshake is received, -- but WVALID is not yet asserted for subsequent transfer. -- Check valid write data on AXI write data channel if (AXI_WVALID = '1') then -- Load write data register wrdata_reg_ld <= '1'; -- Load WE register bram_we_ld <= '1'; -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Burst data write wr_data_sm_ns <= BRST_WR_DATA; axi_wr_burst_cmb <= '1'; -- Make modification to last_data_ack_mod signal -- so that it is asserted when this state is reached -- and the BRAM address counter gets loaded. -- WVALID not yet asserted else wrdata_reg_ld <= '0'; -- Negate write data register load bram_we_ld <= '0'; -- Negate WE register load bram_en_cmb <= '0'; -- Negate write to BRAM bram_addr_inc <= '0'; -- Do not increment BRAM address counter end if; --coverage off ------------------------------ Default ---------------------------- when others => wr_data_sm_ns <= IDLE; --coverage on end case; end process WR_DATA_SM_CMB_PROCESS; --------------------------------------------------------------------------- WR_DATA_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then wr_data_sm_cs <= IDLE; bram_en_int <= '0'; clr_bram_we <= '0'; delay_aw_active_clr <= '0'; axi_wdata_full_reg <= '0'; else wr_data_sm_cs <= wr_data_sm_ns; bram_en_int <= bram_en_cmb; clr_bram_we <= clr_bram_we_cmb; delay_aw_active_clr <= delay_aw_active_clr_cmb; axi_wdata_full_reg <= axi_wdata_full_cmb; end if; end if; end process WR_DATA_SM_REG_PROCESS; --------------------------------------------------------------------------- end generate GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY; --------------------------------------------------------------------------- WR_BURST_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_wr_burst <= '0'; else axi_wr_burst <= axi_wr_burst_cmb; end if; end if; end process WR_BURST_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** AXI Write Response Channel Interface *** --------------------------------------------------------------------------- -- v1.03a --------------------------------------------------------------------------- -- -- -- New FIFO storage for BID, so AWID can be stored in -- a FIFO and B response is seperated from W response. -- -- Use registered WREADY & BID FIFO in single port configuration. -- --------------------------------------------------------------------------- -- Instantiate FIFO to store BID values to be asserted back on B channel. -- Only 8 entries deep, BVALID counter only allows W channel to be 8 ahead of -- B channel. -- -- If AWID is a single bit wide, sythesis optimizes the module, srl_fifo, -- to a single SRL16E library module. BID_FIFO: entity work.srl_fifo generic map ( C_DATA_BITS => C_AXI_ID_WIDTH, C_DEPTH => 8 ) port map ( Clk => S_AXI_AClk, Reset => bid_fifo_rst, FIFO_Write => bid_fifo_ld_en, Data_In => bid_fifo_ld, FIFO_Read => bid_fifo_rd_en, Data_Out => bid_fifo_rd, FIFO_Full => open, Data_Exists => bid_fifo_not_empty, Addr => open ); bid_fifo_rst <= not (S_AXI_AResetn); bid_fifo_ld_en <= bram_addr_ld_en; bid_fifo_ld <= AXI_AWID when (awaddr_pipe_sel = '0') else axi_awid_pipe; -- Read from FIFO when BVALID is to be asserted on bus, or in a back-to-back assertion -- when a BID value is available in the FIFO. bid_fifo_rd_en <= bid_fifo_not_empty and -- Only read if data is available. ((bid_gets_fifo_load_d1) or -- a) Do the FIFO read in the clock cycle -- following the BID value directly -- aserted on the B channel (from AWID or pipeline). (first_fifo_bid) or -- b) Read from FIFO when BID is previously stored -- but BVALID is not yet asserted on AXI. (bvalid_cnt_dec)); -- c) Or read when next BID value is to be updated -- on B channel (and exists waiting in FIFO). -- 1) Special case (1st load in FIFO) (and single clock cycle turnaround needed on BID, from AWID). -- If loading the FIFO and BVALID is to be asserted in the next clock cycle -- Then capture this condition to read from FIFO in the subsequent clock cycle -- (and clear the BID value stored in the FIFO). bid_gets_fifo_load <= '1' when (bid_fifo_ld_en = '1') and (first_fifo_bid = '1' or b2b_fifo_bid = '1') else '0'; first_fifo_bid <= '1' when ((bvalid_cnt_inc = '1') and (bvalid_cnt_non_zero = '0')) else '0'; -- 2) An additional special case. -- When write data register is loaded for single (bvalid_cnt = "001", due to WLAST/WVALID) -- But, AWID not yet received (FIFO is still empty). -- If BID FIFO is still empty with the BVALID counter decrement, but simultaneously -- is increment (same condition as first_fifo_bid). b2b_fifo_bid <= '1' when (bvalid_cnt_inc = '1' and bvalid_cnt_dec = '1' and bvalid_cnt = "001" and bid_fifo_not_empty = '0') else '0'; -- Output BID register to B AXI channel REG_BID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_bid_int <= (others => '0'); -- If loading the FIFO and BVALID is to be asserted in the next clock cycle -- Then output the AWID or pipelined value (the same BID that gets loaded into FIFO). elsif (bid_gets_fifo_load = '1') then axi_bid_int <= bid_fifo_ld; -- If new value read from FIFO then ensure that value is updated on AXI. elsif (bid_fifo_rd_en = '1') then axi_bid_int <= bid_fifo_rd; else axi_bid_int <= axi_bid_int; end if; end if; end process REG_BID; -- Capture condition of BID output updated while the FIFO is also -- getting updated. Read FIFO in the subsequent clock cycle to -- clear the value stored in the FIFO. REG_BID_LD: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then bid_gets_fifo_load_d1 <= '0'; else bid_gets_fifo_load_d1 <= bid_gets_fifo_load; end if; end if; end process REG_BID_LD; --------------------------------------------------------------------------- -- AXI_BRESP Output Register --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_BRESP -- Purpose: Generate BRESP output signal when ECC is disabled. -- Only allowable output is RESP_OKAY. --------------------------------------------------------------------------- GEN_BRESP: if C_ECC = 0 generate begin REG_BRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_bresp_int <= (others => '0'); -- elsif (AXI_WLAST = '1') then -- CR # 609695 elsif ((AXI_WLAST and AXI_WVALID and axi_wready_int_mod) = '1') then -- AXI BRAM only supports OK response for normal operations -- Exclusive operations not yet supported axi_bresp_int <= RESP_OKAY; else axi_bresp_int <= axi_bresp_int; end if; end if; end process REG_BRESP; end generate GEN_BRESP; --------------------------------------------------------------------------- -- Generate: GEN_BRESP_ECC -- Purpose: Generate BRESP output signal when ECC is enabled -- If no ECC error condition is detected during the RMW -- sequence, then output will be RESP_OKAY. When an -- uncorrectable error is detected, the output will RESP_SLVERR. --------------------------------------------------------------------------- GEN_BRESP_ECC: if C_ECC = 1 generate signal UE_Q_reg : std_logic := '0'; begin REG_BRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_bresp_int <= (others => '0'); elsif (bvalid_cnt_inc_d1 = '1') then --coverage off -- Exclusive operations not yet supported -- If no ECC errors occur, respond with OK if (UE_Q = '1') or (UE_Q_reg = '1') then axi_bresp_int <= RESP_SLVERR; --coverage on else axi_bresp_int <= RESP_OKAY; end if; else axi_bresp_int <= axi_bresp_int; end if; end if; end process REG_BRESP; -- Check if any error conditions occured during the write operation. -- Capture condition for each write transfer. REG_UE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Clear at end of current write (and ensure the flag is cleared -- at the beginning of a write transfer) if (S_AXI_AResetn = C_RESET_ACTIVE) or (aw_active_re = '1') or (AXI_BREADY = '1' and axi_bvalid_int = '1') then UE_Q_reg <= '0'; --coverage off elsif (UE_Q = '1') then UE_Q_reg <= '1'; --coverage on else UE_Q_reg <= UE_Q_reg; end if; end if; end process REG_UE; end generate GEN_BRESP_ECC; -- v1.03a --------------------------------------------------------------------------- -- Instantiate BVALID counter outside of specific SM generate block. --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- BVALID counter to track the # of required BVALID/BREADY handshakes -- needed to occur on the AXI interface. Based on early and seperate -- AWVALID/AWREADY and WVALID/WREADY handshake exchanges. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt <= (others => '0'); -- Ensure we only increment counter wyhen BREADY is not asserted elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1); -- Ensure that we only decrement when SM is not incrementing elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1); else bvalid_cnt <= bvalid_cnt; end if; end if; end process REG_BVALID_CNT; bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt_non_zero = '1') else '0'; bvalid_cnt_non_zero <= '1' when (bvalid_cnt /= "000") else '0'; bvalid_cnt_amax <= '1' when (bvalid_cnt = "110") else '0'; bvalid_cnt_max <= '1' when (bvalid_cnt = "111") else '0'; -- Replace BVALID output register -- Assert BVALID as long as BVALID counter /= zero REG_BVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Ensure that if we are also incrementing BVALID counter, the BVALID stays asserted. (bvalid_cnt = "001" and bvalid_cnt_dec = '1' and bvalid_cnt_inc = '0') then axi_bvalid_int <= '0'; elsif (bvalid_cnt_non_zero = '1') or (bvalid_cnt_inc = '1') then axi_bvalid_int <= '1'; else axi_bvalid_int <= '0'; end if; end if; end process REG_BVALID; --------------------------------------------------------------------------- -- *** ECC Logic *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_ECC -- Purpose: Generate BRAM ECC write data and check ECC on read operations. -- Create signals to update ECC registers (lite_ecc_reg module interface). -- --------------------------------------------------------------------------- GEN_ECC: if C_ECC = 1 generate constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite) constant null8 : std_logic_vector(0 to 7) := "00000000"; -- Specific to 64-bit data width -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; -- Remove usage of C_FAMILY. -- All architectures supporting AXI will support a LUT6. -- Hard code this internal constant used in ECC algorithm. constant C_USE_LUT6 : boolean := TRUE; signal RdECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Temp signal WrECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal WrECC_i : std_logic_vector(C_ECC_WIDTH-1 downto 0) := (others => '0'); signal AXI_WSTRB_Q : std_logic_vector((C_AXI_DATA_WIDTH/8 - 1) downto 0) := (others => '0'); signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to 64-bit ECC signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence signal RdModifyWr_Read_i : std_logic := '0'; signal RdModifyWr_Check : std_logic := '0'; signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width signal UnCorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1) := (others => '0'); signal CE_Q : std_logic := '0'; signal Sl_CE_i : std_logic := '0'; signal Sl_UE_i : std_logic := '0'; subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- 0:6 for 32-bit ECC -- 0:7 for 64-bit ECC type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits; type bool_array is array (natural range 0 to 6) of boolean; constant inverted_bit : bool_array := (false,false,true,false,true,false,false); -- v1.03a constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH; constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0); begin -- Generate signal to advance BRAM read address pipeline to -- capture address for ECC error conditions (in lite_ecc_reg module). BRAM_Addr_En <= RdModifyWr_Read; -- v1.03a RdModifyWr_Read <= '1' when (wr_data_ecc_sm_cs = RMW_RD_DATA) else '0'; RdModifyWr_Modify <= '1' when (wr_data_ecc_sm_cs = RMW_MOD_DATA) else '0'; RdModifyWr_Write <= '1' when (wr_data_ecc_sm_cs = RMW_WR_DATA) else '0'; ----------------------------------------------------------------------- -- Remember write data one cycle to be available after read has been completed in a -- read/modify write operation. -- Save WSTRBs here in this register REG_WSTRB : process (S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then AXI_WSTRB_Q <= (others => '0'); elsif (wrdata_reg_ld = '1') then AXI_WSTRB_Q <= AXI_WSTRB; end if; end if; end process REG_WSTRB; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_WRDATA_CMB -- Purpose: Replace manual signal assignment for WrData_cmb with -- generate funtion. -- -- Ensure correct byte swapping occurs with -- CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) assignment -- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0). -- -- AXI_WSTRB_Q (C_AXI_DATA_WIDTH_BYTES-1 downto 0) matches -- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0). -- ------------------------------------------------------------------------ GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate begin WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= bram_wrdata_int ((((i+1)*8)-1) downto i*8) when (RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1') else CorrectedRdData ( (C_AXI_DATA_WIDTH - ((i+1)*8)) to (C_AXI_DATA_WIDTH - (i*8) - 1) ); end generate GEN_WRDATA_CMB; REG_WRDATA : process (S_AXI_AClk) is begin -- Remove reset value to minimize resources & improve timing if (S_AXI_AClk'event and S_AXI_AClk = '1') then WrData <= WrData_cmb; end if; end process REG_WRDATA; ------------------------------------------------------------------------ -- New assignment of ECC bits to BRAM write data outside generate -- blocks. Same signal assignment regardless of ECC type. BRAM_WrData ((C_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto C_AXI_DATA_WIDTH) <= WrECC_i xor FaultInjectECC; ------------------------------------------------------------------------ -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. ------------------------------------------------------------------------ GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0); signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0); signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0); signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); signal h_matrix : type_int0; signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); begin ---------------------- Hsiao ECC Write Logic ---------------------- -- Instantiate ecc_gen_hsiao module, generated from MIG ECC_GEN_HSIAO: entity work.ecc_gen generic map ( code_width => CODE_WIDTH, ecc_width => ECC_WIDTH, data_width => C_AXI_DATA_WIDTH ) port map ( -- Output h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); -- Merge muxed rd/write data to gen HSIAO_ECC: process (h_rows, WrData) constant DQ_WIDTH : integer := CODE_WIDTH; variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_AXI_DATA_WIDTH); begin -- Loop to generate all ECC bits for k in 0 to ECC_WIDTH - 1 loop ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_AXI_DATA_WIDTH - 1 downto 0) and h_rows (k * CODE_WIDTH + C_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH))); end loop; WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_AXI_DATA_WIDTH); end process HSIAO_ECC; ----------------------------------------------------------------------- -- Generate: GEN_ECC_32 -- Purpose: For 32-bit ECC implementations, assign unused -- MSB of ECC output to BRAM with '0'. ----------------------------------------------------------------------- GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate begin -- Account for 32-bit and MSB '0' of ECC bits WrECC_i <= '0' & WrECC; end generate GEN_ECC_32; ----------------------------------------------------------------------- -- Generate: GEN_ECC_N -- Purpose: For all non 32-bit ECC implementations, assign ECC -- bits for BRAM output. ----------------------------------------------------------------------- GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate begin WrECC_i <= WrECC; end generate GEN_ECC_N; ---------------------- Hsiao ECC Read Logic ----------------------- GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate begin syndrome_ns (m) <= REDUCTION_XOR ( BRAM_RdData (CODE_WIDTH-1 downto 0) and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH))); end generate GEN_RD_ECC; -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_r <= syndrome_ns; end if; end process REG_SYNDROME; ecc_rddata_r <= UnCorrectedRdData; -- Reconstruct H-matrix H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate begin H_BIT: for p in 0 to ECC_WIDTH - 1 generate begin h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n); end generate H_BIT; end generate H_COL; GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate begin flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r); end generate GEN_FLIP_BIT; CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor flip_bits (C_AXI_DATA_WIDTH-1 downto 0); Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); end generate GEN_HSIAO_ECC; ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. ------------------------------------------------------------------------ GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate begin ----------------------------------------------------------------- -- Generate: GEN_ECC_32 -- Purpose: Assign ECC out data vector (N:0) unique for 32-bit BRAM. -- Add extra '0' at MSB of ECC vector for data2mem alignment -- w/ 32-bit BRAM data widths. -- ECC bits are in upper order bits. ----------------------------------------------------------------- GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate constant correct_data_table_32 : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC begin --------------------- Hamming 32-bit ECC Write Logic ------------------ ------------------------------------------------------------------------- -- Instance: CHK_HANDLER_WR_32 -- Description: Generate ECC bits for writing into BRAM. -- WrData (N:0) ------------------------------------------------------------------------- CHK_HANDLER_WR_32: entity work.checkbit_handler generic map ( C_ENCODE => true, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( DataIn => WrData, -- [in std_logic_vector(0 to 31)] CheckIn => null7, -- [in std_logic_vector(0 to 6)] CheckOut => WrECC, -- [out std_logic_vector(0 to 6)] Syndrome => open, -- [out std_logic_vector(0 to 6)] Syndrome_4 => open, -- [out std_logic_vector(0 to 1)] Syndrome_6 => open, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)] Enable_ECC => '1', -- [in std_logic] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open ); -- [out std_logic] -- v1.03a -- Account for 32-bit and MSB '0' of ECC bits WrECC_i <= '0' & WrECC; --------------------- Hamming 32-bit ECC Read Logic ------------------- -------------------------------------------------------------------------- -- Instance: CHK_HANDLER_RD_32 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) -------------------------------------------------------------------------- CHK_HANDLER_RD_32: entity work.checkbit_handler generic map ( C_ENCODE => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( -- DataIn (8:39) -- CheckIn (1:7) DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)] CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)] Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] --------------------------------------------------------------------------- -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_reg <= Syndrome; syndrome_4_reg <= Syndrome_4; syndrome_6_reg <= Syndrome_6; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl -- w/ balanced pipeline stage) before correct_one_bit module. syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3); PARITY_CHK4: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (4) ); -- [out std_logic] syndrome_reg_i (5) <= syndrome_reg (5); PARITY_CHK6: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (6) ); -- [out std_logic] --------------------------------------------------------------------------- -- Generate: GEN_CORR_32 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin --------------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_32 -- Description: Generate ECC bits for checking data read from BRAM. --------------------------------------------------------------------------- CORR_ONE_BIT_32: entity work.correct_one_bit generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_32 (i)) port map ( DIn => UnCorrectedRdData (i), Syndrome => syndrome_reg_i, DCorr => CorrectedRdData (i)); end generate GEN_CORR_32; end generate GEN_ECC_32; ----------------------------------------------------------------- -- Generate: GEN_ECC_64 -- Purpose: Assign ECC out data vector (N:0) unique for 64-bit BRAM. -- No extra '0' at MSB of ECC vector for data2mem alignment -- w/ 64-bit BRAM data widths. -- ECC bits are in upper order bits. ----------------------------------------------------------------- GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate constant correct_data_table_64 : correct_data_table_type := ( 0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001", 4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001", 8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001", 12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001", 16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001", 20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001", 24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101", 28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101", 32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101", 36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101", 40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101", 44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101", 48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101", 52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101", 56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011", 60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011" ); signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); signal syndrome7_a : std_logic := '0'; signal syndrome7_b : std_logic := '0'; begin --------------------- Hamming 64-bit ECC Write Logic ------------------ --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_WR_64 -- Description: Generate ECC bits for writing into BRAM when configured -- as 64-bit wide BRAM. -- WrData (N:0) -- Enable C_REG on encode path. --------------------------------------------------------------------------- CHK_HANDLER_WR_64: entity work.checkbit_handler_64 generic map ( C_ENCODE => true, -- [boolean] C_REG => true, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( Clk => S_AXI_AClk, -- [in std_logic] DataIn => WrData_cmb, -- [in std_logic_vector(0 to 63)] CheckIn => null8, -- [in std_logic_vector(0 to 7)] CheckOut => WrECC, -- [out std_logic_vector(0 to 7)] Syndrome => open, -- [out std_logic_vector(0 to 7)] Syndrome_7 => open, -- [out std_logic_vector(0 to 11)] Syndrome_Chk => null8, -- [in std_logic_vector(0 to 7)] Enable_ECC => '1', -- [in std_logic] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open ); -- [out std_logic] -- Note: (7:0) Old bit lane assignment -- BRAM_WrData ((C_ECC_WIDTH - 1) downto 0) -- v1.02a -- WrECC is assigned to BRAM_WrData (71:64) -- v1.03a -- BRAM_WrData (71:64) assignment done outside of this -- ECC type generate block. WrECC_i <= WrECC; --------------------- Hamming 64-bit ECC Read Logic ------------------- --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_RD_64 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- CHK_HANDLER_RD_64: entity work.checkbit_handler_64 generic map ( C_ENCODE => false, -- [boolean] C_REG => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( Clk => S_AXI_AClk, -- [in std_logic] -- DataIn (8:71) -- CheckIn (0:7) DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)] CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)] CheckOut => open, -- [out std_logic_vector(0 to 7)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)] Syndrome_7 => Syndrome_7, -- [out std_logic_vector(0 to 11)] Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] --------------------------------------------------------------------------- -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_reg <= Syndrome; syndrome_7_reg <= Syndrome_7; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Move final XOR to registered side of syndrome bits. -- Do last XOR on select syndrome bits after pipeline stage -- before correct_one_bit_64 module. syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6); PARITY_CHK7_A: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome7_a ); -- [out std_logic] PARITY_CHK7_B: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome7_b ); -- [out std_logic] syndrome_reg_i (7) <= syndrome7_a xor syndrome7_b; --------------------------------------------------------------------------- -- Generate: GEN_CORRECT_DATA -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin --------------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_64 -- Description: Generate ECC bits for checking data read from BRAM. --------------------------------------------------------------------------- CORR_ONE_BIT_64: entity work.correct_one_bit_64 generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_64 (i)) port map ( DIn => UnCorrectedRdData (i), Syndrome => syndrome_reg_i, DCorr => CorrectedRdData (i)); end generate GEN_CORR_64; end generate GEN_ECC_64; end generate GEN_HAMMING_ECC; -- Remember correctable/uncorrectable error from BRAM read CORR_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if RdModifyWr_Modify = '1' then -- Capture error signals CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CORR_REG; -- ECC register block gets registered UE or CE conditions to update -- ECC registers/interrupt/flag outputs. Sl_CE <= CE_Q; Sl_UE <= UE_Q; CE_Failing_We <= CE_Q; FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0'; ----------------------------------------------------------------------- -- Add register delay on BVALID counter increment -- Used to clear fault inject register. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt_inc_d1 <= '0'; else bvalid_cnt_inc_d1 <= bvalid_cnt_inc; end if; end if; end process REG_BVALID_CNT; ----------------------------------------------------------------------- -- Map BRAM_RdData (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- Generate: GEN_ECC_32 -- Purpose: For 32-bit ECC implementations, account for -- extra bit in read data mapping on registered value. ----------------------------------------------------------------------- GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate begin -- Insert register stage for read data to correct REG_CHK_DATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH); end if; end process REG_CHK_DATA; end generate GEN_ECC_32; ----------------------------------------------------------------------- -- Generate: GEN_ECC_N -- Purpose: For all non 32-bit ECC implementations, assign ECC -- bits for BRAM output. ----------------------------------------------------------------------- GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate begin -- Insert register stage for read data to correct REG_CHK_DATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1); end if; end process REG_CHK_DATA; end generate GEN_ECC_N; end generate GEN_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Drive default output signals when ECC is diabled. --------------------------------------------------------------------------- GEN_NO_ECC: if C_ECC = 0 generate begin BRAM_Addr_En <= '0'; FaultInjectClr <= '0'; CE_Failing_We <= '0'; Sl_CE <= '0'; Sl_UE <= '0'; end generate GEN_NO_ECC; --------------------------------------------------------------------------- -- *** BRAM Interface Signals *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WE -- Purpose: BRAM WE generate process -- One WE per 8-bits of BRAM data. --------------------------------------------------------------------------- GEN_BRAM_WE: for i in C_AXI_DATA_WIDTH/8 + (C_ECC*(1+(C_AXI_DATA_WIDTH/128))) - 1 downto 0 generate begin BRAM_WE (i) <= bram_we_int (i); end generate GEN_BRAM_WE; --------------------------------------------------------------------------- BRAM_En <= bram_en_int; --------------------------------------------------------------------------- -- BRAM Address Generate --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. -- --------------------------------------------------------------------------- GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr (i) <= bram_addr_int (i); end generate GEN_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WRDATA -- Purpose: Generate BRAM Write Data. --------------------------------------------------------------------------- GEN_BRAM_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate begin -- Check if ECC is enabled -- If so, XOR the fault injection vector with the data -- (post-pipeline) to avoid any timing issues on the data vector -- from AXI. ----------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Generate output write data when ECC is disabled. ----------------------------------------------------------------------- GEN_NO_ECC : if C_ECC = 0 generate begin BRAM_WrData (i) <= bram_wrdata_int (i); end generate GEN_NO_ECC; ----------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Generate output write data when ECC is enable -- (use fault vector) -- (N:0) -- for 32-bit (31:0) WrData while (ECC = [39:32]) ----------------------------------------------------------------------- GEN_W_ECC : if C_ECC = 1 generate begin BRAM_WrData (i) <= WrData (i) xor FaultInjectData (i); end generate GEN_W_ECC; end generate GEN_BRAM_WRDATA; --------------------------------------------------------------------------- end architecture implementation; ------------------------------------------------------------------------------- -- full_axi.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: full_axi.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller when configured in a full AXI4 mode. -- The rd_chnl and wr_chnl modules are instantiated. -- The ECC AXI-Lite register module is instantiated, if enabled. -- When single port BRAM mode is selected, the arbitration logic -- is instantiated (and connected to each wr_chnl & rd_chnl). -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen_hsiao.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen_hsiao.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/15/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter and mappings on instantiated modules. -- ^^^^^^ -- JLJ 2/18/2011 v1.03a -- ~~~~~~ -- Update WE & BRAM data sizes based on 128-bit ECC configuration. -- Plus XST clean-up. -- ^^^^^^ -- JLJ 3/31/2011 v1.03a -- ~~~~~~ -- Add coverage tags. -- ^^^^^^ -- JLJ 4/11/2011 v1.03a -- ~~~~~~ -- Add signal, AW2Arb_BVALID_Cnt, between wr_chnl and sng_port_arb modules. -- ^^^^^^ -- JLJ 4/20/2011 v1.03a -- ~~~~~~ -- Add default values for Arb2AW_Active & Arb2AR_Active when dual port mode. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_bram_ctrl_funcs.all; use work.lite_ecc_reg; use work.sng_port_arb; use work.wr_chnl; use work.rd_chnl; ------------------------------------------------------------------------------ entity full_axi is generic ( -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1; -- Support for narrow burst operations C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_ECC_TYPE : integer := 0; -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; ECC_Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- AXI Write Address Channel Signals (AW) S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWLEN : in std_logic_vector(7 downto 0); S_AXI_AWSIZE : in std_logic_vector(2 downto 0); S_AXI_AWBURST : in std_logic_vector(1 downto 0); S_AXI_AWLOCK : in std_logic; S_AXI_AWCACHE : in std_logic_vector(3 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; -- AXI Write Data Channel Signals (W) S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); S_AXI_WLAST : in std_logic; S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; -- AXI Write Data Response Channel Signals (B) S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; -- AXI Read Address Channel Signals (AR) S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARLEN : in std_logic_vector(7 downto 0); S_AXI_ARSIZE : in std_logic_vector(2 downto 0); S_AXI_ARBURST : in std_logic_vector(1 downto 0); S_AXI_ARLOCK : in std_logic; S_AXI_ARCACHE : in std_logic_vector(3 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; -- AXI Read Data Channel Signals (R) S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RLAST : out std_logic; S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- AXI-Lite ECC Register Interface Signals -- AXI-Lite Clock and Reset -- TBD -- S_AXI_CTRL_ACLK : in std_logic; -- S_AXI_CTRL_ARESETN : in std_logic; -- AXI-Lite Write Address Channel Signals (AW) S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic; -- BRAM Interface Signals (Port A) BRAM_En_A : out std_logic; BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- BRAM Interface Signals (Port B) BRAM_En_B : out std_logic; BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) ); end entity full_axi; ------------------------------------------------------------------------------- architecture implementation of full_axi is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH); -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- -- Internal AXI Signals signal S_AXI_AWREADY_i : std_logic := '0'; signal S_AXI_ARREADY_i : std_logic := '0'; -- Internal BRAM Signals signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal BRAM_En_A_i : std_logic := '0'; signal BRAM_En_B_i : std_logic := '0'; signal BRAM_WE_A_i : std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal BRAM_RdData_i : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); -- Internal ECC Signals signal Enable_ECC : std_logic := '0'; signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal Wr_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers --signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers --signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register signal Wr_Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Wr_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal Rd_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers signal Rd_Sl_CE : std_logic := '0'; -- Correctable Error Flag signal Rd_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal FaultInjectECC : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal FaultInjectECC_i : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal Active_Wr : std_logic := '0'; signal BRAM_Addr_En : std_logic := '0'; signal Wr_BRAM_Addr_En : std_logic := '0'; signal Rd_BRAM_Addr_En : std_logic := '0'; -- Internal Arbitration Signals signal Arb2AW_Active : std_logic := '0'; signal AW2Arb_Busy : std_logic := '0'; signal AW2Arb_Active_Clr : std_logic := '0'; signal AW2Arb_BVALID_Cnt : std_logic_vector (2 downto 0) := (others => '0'); signal Arb2AR_Active : std_logic := '0'; signal AR2Arb_Active_Clr : std_logic := '0'; signal WrChnl_BRAM_Addr_Rst : std_logic := '0'; signal WrChnl_BRAM_Addr_Ld_En : std_logic := '0'; signal WrChnl_BRAM_Addr_Inc : std_logic := '0'; signal WrChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal RdChnl_BRAM_Addr_Ld_En : std_logic := '0'; signal RdChnl_BRAM_Addr_Inc : std_logic := '0'; signal RdChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- *** BRAM Output Signals *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: ADDR_SNG_PORT -- Purpose: OR the BRAM_Addr outputs from each wr_chnl & rd_chnl -- Only one write or read will be active at a time. -- Ensure that ecah channel address is driven to '0' when not in use. --------------------------------------------------------------------------- ADDR_SNG_PORT: if C_SINGLE_PORT_BRAM = 1 generate signal sng_bram_addr_rst : std_logic := '0'; signal sng_bram_addr_ld_en : std_logic := '0'; signal sng_bram_addr_ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal sng_bram_addr_inc : std_logic := '0'; begin -- BRAM_Addr_A <= BRAM_Addr_A_i or BRAM_Addr_B_i; -- BRAM_Addr_A <= BRAM_Addr_A_i when (Arb2AW_Active = '1') else BRAM_Addr_B_i; -- BRAM_Addr_A <= BRAM_Addr_A_i when (Active_Wr = '1') else BRAM_Addr_B_i; -- Insert mux on address counter control signals sng_bram_addr_rst <= WrChnl_BRAM_Addr_Rst; sng_bram_addr_ld_en <= WrChnl_BRAM_Addr_Ld_En or RdChnl_BRAM_Addr_Ld_En; sng_bram_addr_ld <= RdChnl_BRAM_Addr_Ld when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Ld; sng_bram_addr_inc <= RdChnl_BRAM_Addr_Inc when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Inc; I_ADDR_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (sng_bram_addr_rst = '1') then bram_addr_int <= (others => '0'); elsif (sng_bram_addr_ld_en = '1') then bram_addr_int <= sng_bram_addr_ld; elsif (sng_bram_addr_inc = '1') then bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12) <= bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12); bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <= std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1); end if; end if; end process I_ADDR_CNT; BRAM_Addr_B <= (others => '0'); BRAM_En_A <= BRAM_En_A_i or BRAM_En_B_i; -- BRAM_En_A <= BRAM_En_A_i when (Arb2AW_Active = '1') else BRAM_En_B_i; BRAM_En_B <= '0'; BRAM_RdData_i <= BRAM_RdData_A; -- Assign read data port A BRAM_WE_A <= BRAM_WE_A_i when (Arb2AW_Active = '1') else (others => '0'); -- v1.03a -- Early register on WrData and WSTRB in wr_chnl. (Previous value was always cleared). --------------------------------------------------------------------------- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr_A (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. --------------------------------------------------------------------------- GEN_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr_A (i) <= bram_addr_int (i); end generate GEN_BRAM_ADDR; end generate ADDR_SNG_PORT; --------------------------------------------------------------------------- -- Generate: ADDR_DUAL_PORT -- Purpose: Assign each BRAM address when in a dual port controller -- configuration. --------------------------------------------------------------------------- ADDR_DUAL_PORT: if C_SINGLE_PORT_BRAM = 0 generate begin BRAM_Addr_A <= BRAM_Addr_A_i; BRAM_Addr_B <= BRAM_Addr_B_i; BRAM_En_A <= BRAM_En_A_i; BRAM_En_B <= BRAM_En_B_i; BRAM_WE_A <= BRAM_WE_A_i; BRAM_RdData_i <= BRAM_RdData_B; -- Assign read data port B end generate ADDR_DUAL_PORT; BRAM_WrData_B <= (others => '0'); BRAM_WE_B <= (others => '0'); --------------------------------------------------------------------------- -- *** AXI-Lite ECC Register Output Signals *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_REGS -- Purpose: Generate default values if ECC registers are disabled (or when -- ECC is disabled). -- Include both AXI-Lite default signal values & internal -- core signal values. --------------------------------------------------------------------------- GEN_NO_REGS: if (C_ECC = 0) generate begin S_AXI_CTRL_AWREADY <= '0'; S_AXI_CTRL_WREADY <= '0'; S_AXI_CTRL_BRESP <= (others => '0'); S_AXI_CTRL_BVALID <= '0'; S_AXI_CTRL_ARREADY <= '0'; S_AXI_CTRL_RDATA <= (others => '0'); S_AXI_CTRL_RRESP <= (others => '0'); S_AXI_CTRL_RVALID <= '0'; -- No fault injection FaultInjectData <= (others => '0'); FaultInjectECC <= (others => '0'); -- Interrupt only enabled when ECC status/interrupt registers enabled ECC_Interrupt <= '0'; ECC_UE <= '0'; Enable_ECC <= '0'; end generate GEN_NO_REGS; --------------------------------------------------------------------------- -- Generate: GEN_REGS -- Purpose: Generate ECC register module when ECC is enabled and -- ECC registers are enabled. --------------------------------------------------------------------------- -- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate -- For future implementation. GEN_REGS: if (C_ECC = 1) generate begin --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- Description: This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. --------------------------------------------------------------------------- I_LITE_ECC_REG : entity work.lite_ecc_reg generic map ( C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width C_FAULT_INJECT => C_FAULT_INJECT , C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , -- AXI clock S_AXI_AResetn => S_AXI_AResetn , -- TBD -- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock -- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn , Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , -- Add AXI-Lite ECC Register Ports AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , Enable_ECC => Enable_ECC , FaultInjectClr => FaultInjectClr , CE_Failing_We => CE_Failing_We , CE_CounterReg_Inc => CE_Failing_We , Sl_CE => Sl_CE , Sl_UE => Sl_UE , BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a BRAM_Addr_En => BRAM_Addr_En , Active_Wr => Active_Wr , -- BRAM_RdData_A => BRAM_RdData_A (C_S_AXI_DATA_WIDTH-1 downto 0) , -- BRAM_RdData_B => BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0) , FaultInjectData => FaultInjectData , FaultInjectECC => FaultInjectECC_i ); BRAM_Addr_En <= Wr_BRAM_Addr_En or Rd_BRAM_Addr_En; -- v1.03a -- Add coverage tags for Wr_CE_Failing_We. -- No testing on forcing errors with RMW and AXI write transfers. --coverage off CE_Failing_We <= Wr_CE_Failing_We or Rd_CE_Failing_We; Sl_CE <= Wr_Sl_CE or Rd_Sl_CE; Sl_UE <= Wr_Sl_UE or Rd_Sl_UE; --coverage on ------------------------------------------------------------------- -- Generate: GEN_32 -- Purpose: Add MSB '0' on ECC vector as only 7-bits wide in 32-bit. ------------------------------------------------------------------- GEN_32: if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectECC <= '0' & FaultInjectECC_i; end generate GEN_32; ------------------------------------------------------------------- -- Generate: GEN_NON_32 -- Purpose: Data widths match at 8-bits for ECC on 64-bit data. -- And 9-bits for 128-bit data. ------------------------------------------------------------------- GEN_NON_32: if C_S_AXI_DATA_WIDTH /= 32 generate begin FaultInjectECC <= FaultInjectECC_i; end generate GEN_NON_32; end generate GEN_REGS; --------------------------------------------------------------------------- -- Generate: GEN_ARB -- Purpose: Generate arbitration module when AXI4 is configured in -- single port mode. --------------------------------------------------------------------------- GEN_ARB: if (C_SINGLE_PORT_BRAM = 1) generate begin --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- Description: This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. --------------------------------------------------------------------------- I_SNG_PORT : entity work.sng_port_arb generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , -- AXI clock S_AXI_AResetn => S_AXI_AResetn , AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_AWVALID => S_AXI_AWVALID , AXI_AWREADY => S_AXI_AWREADY , AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_ARVALID => S_AXI_ARVALID , AXI_ARREADY => S_AXI_ARREADY , Arb2AW_Active => Arb2AW_Active , AW2Arb_Busy => AW2Arb_Busy , AW2Arb_Active_Clr => AW2Arb_Active_Clr , AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt , Arb2AR_Active => Arb2AR_Active , AR2Arb_Active_Clr => AR2Arb_Active_Clr ); end generate GEN_ARB; --------------------------------------------------------------------------- -- Generate: GEN_DUAL -- Purpose: Dual mode. AWREADY and ARREADY are generated from each -- wr_chnl and rd_chnl module. --------------------------------------------------------------------------- GEN_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate begin S_AXI_AWREADY <= S_AXI_AWREADY_i; S_AXI_ARREADY <= S_AXI_ARREADY_i; Arb2AW_Active <= '0'; Arb2AR_Active <= '0'; end generate GEN_DUAL; --------------------------------------------------------------------------- -- Instance: I_WR_CHNL -- -- Description: -- BRAM controller write channel logic. Controls AXI bus handshaking and -- data flow on the write address (AW), write data (W) and -- write response (B) channels. -- -- BRAM signals are marked as output from Wr Chnl for future implementation -- of merging Wr/Rd channel outputs to a single port of the BRAM module. -- --------------------------------------------------------------------------- I_WR_CHNL : entity work.wr_chnl generic map ( -- C_FAMILY => C_FAMILY , C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_ECC => C_ECC , C_ECC_WIDTH => C_ECC_WIDTH , C_ECC_TYPE => C_ECC_TYPE -- v1.03a ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , AXI_AWID => S_AXI_AWID , AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_AWLEN => S_AXI_AWLEN , AXI_AWSIZE => S_AXI_AWSIZE , AXI_AWBURST => S_AXI_AWBURST , AXI_AWLOCK => S_AXI_AWLOCK , AXI_AWCACHE => S_AXI_AWCACHE , AXI_AWPROT => S_AXI_AWPROT , AXI_AWVALID => S_AXI_AWVALID , AXI_AWREADY => S_AXI_AWREADY_i , AXI_WDATA => S_AXI_WDATA , AXI_WSTRB => S_AXI_WSTRB , AXI_WLAST => S_AXI_WLAST , AXI_WVALID => S_AXI_WVALID , AXI_WREADY => S_AXI_WREADY , AXI_BID => S_AXI_BID , AXI_BRESP => S_AXI_BRESP , AXI_BVALID => S_AXI_BVALID , AXI_BREADY => S_AXI_BREADY , -- Arb Ports Arb2AW_Active => Arb2AW_Active , AW2Arb_Busy => AW2Arb_Busy , AW2Arb_Active_Clr => AW2Arb_Active_Clr , AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt , Sng_BRAM_Addr_Rst => WrChnl_BRAM_Addr_Rst , Sng_BRAM_Addr_Ld_En => WrChnl_BRAM_Addr_Ld_En , Sng_BRAM_Addr_Ld => WrChnl_BRAM_Addr_Ld , Sng_BRAM_Addr_Inc => WrChnl_BRAM_Addr_Inc , Sng_BRAM_Addr => bram_addr_int , -- ECC Ports Enable_ECC => Enable_ECC , BRAM_Addr_En => Wr_BRAM_Addr_En , FaultInjectClr => FaultInjectClr , CE_Failing_We => Wr_CE_Failing_We , Sl_CE => Wr_Sl_CE , Sl_UE => Wr_Sl_UE , Active_Wr => Active_Wr , FaultInjectData => FaultInjectData , FaultInjectECC => FaultInjectECC , BRAM_En => BRAM_En_A_i , -- BRAM_WE => BRAM_WE_A , -- 4/13 BRAM_WE => BRAM_WE_A_i , BRAM_WrData => BRAM_WrData_A , BRAM_RdData => BRAM_RdData_A , BRAM_Addr => BRAM_Addr_A_i ); --------------------------------------------------------------------------- -- Instance: I_RD_CHNL -- -- Description: -- BRAM controller read channel logic. Controls all handshaking and data -- flow on read address (AR) and read data (R) AXI channels. -- -- BRAM signals are marked as Rd Chnl signals for future implementation -- of merging Rd/Wr BRAM signals to a single BRAM port. -- --------------------------------------------------------------------------- I_RD_CHNL : entity work.rd_chnl generic map ( -- C_FAMILY => C_FAMILY , C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_ECC => C_ECC , C_ECC_WIDTH => C_ECC_WIDTH , C_ECC_TYPE => C_ECC_TYPE -- v1.03a ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , AXI_ARID => S_AXI_ARID , AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0), AXI_ARLEN => S_AXI_ARLEN , AXI_ARSIZE => S_AXI_ARSIZE , AXI_ARBURST => S_AXI_ARBURST , AXI_ARLOCK => S_AXI_ARLOCK , AXI_ARCACHE => S_AXI_ARCACHE , AXI_ARPROT => S_AXI_ARPROT , AXI_ARVALID => S_AXI_ARVALID , AXI_ARREADY => S_AXI_ARREADY_i , AXI_RID => S_AXI_RID , AXI_RDATA => S_AXI_RDATA , AXI_RRESP => S_AXI_RRESP , AXI_RLAST => S_AXI_RLAST , AXI_RVALID => S_AXI_RVALID , AXI_RREADY => S_AXI_RREADY , -- Arb Ports Arb2AR_Active => Arb2AR_Active , AR2Arb_Active_Clr => AR2Arb_Active_Clr , Sng_BRAM_Addr_Ld_En => RdChnl_BRAM_Addr_Ld_En , Sng_BRAM_Addr_Ld => RdChnl_BRAM_Addr_Ld , Sng_BRAM_Addr_Inc => RdChnl_BRAM_Addr_Inc , Sng_BRAM_Addr => bram_addr_int , -- ECC Ports Enable_ECC => Enable_ECC , BRAM_Addr_En => Rd_BRAM_Addr_En , CE_Failing_We => Rd_CE_Failing_We , Sl_CE => Rd_Sl_CE , Sl_UE => Rd_Sl_UE , BRAM_En => BRAM_En_B_i , BRAM_Addr => BRAM_Addr_B_i , BRAM_RdData => BRAM_RdData_i ); end architecture implementation; ------------------------------------------------------------------------------- -- axi_bram_ctrl_top.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_bram_ctrl_top.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller IP core. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl_top.vhd (v4_0) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- ecc_gen.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/9/2011 v1.03a -- ~~~~~~ -- Update Create_Size_Default function to support 512 & 1024-bit BRAM. -- Replace usage of Create_Size_Default function. -- ^^^^^^ -- JLJ 2/15/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter on full_axi module. -- Update ECC signal sizes for 128-bit support. -- ^^^^^^ -- JLJ 2/16/2011 v1.03a -- ~~~~~~ -- Update WE size based on 128-bit ECC configuration. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Add C_ECC_TYPE top level parameter on axi_lite module. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Set C_ECC_TYPE = 1 for Hsiao DV regressions. -- ^^^^^^ -- JLJ 2/24/2011 v1.03a -- ~~~~~~ -- Move Find_ECC_Size function to package. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove C_FAMILY from top level. -- Remove C_FAMILY in axi_lite sub module. -- ^^^^^^ -- JLJ 6/23/2011 v1.03a -- ~~~~~~ -- Migrate 9-bit ECC to 16-bit ECC for 128-bit BRAM data width. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; library work; use work.axi_lite; use work.full_axi; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity axi_bram_ctrl_top is generic ( -- AXI Parameters C_BRAM_ADDR_WIDTH : integer := 12; -- Width of AXI address bus (in bits) C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1; -- Support for narrow burst operations C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_TYPE : integer := 1; C_FAULT_INJECT : integer := 0; -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE : integer := 1 -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) -- Reserved parameters for future implementations. -- C_ENABLE_AXI_CTRL_REG_IF : integer := 1; -- By default the ECC AXI-Lite register interface is enabled -- C_CE_FAILING_REGISTERS : integer := 1; -- Enable CE (correctable error) failing registers -- C_UE_FAILING_REGISTERS : integer := 1; -- Enable UE (uncorrectable error) failing registers -- C_ECC_STATUS_REGISTERS : integer := 1; -- Enable ECC status registers -- C_ECC_ONOFF_REGISTER : integer := 1; -- Enable ECC on/off control register -- C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; ECC_Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- AXI Write Address Channel Signals (AW) S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWLEN : in std_logic_vector(7 downto 0); S_AXI_AWSIZE : in std_logic_vector(2 downto 0); S_AXI_AWBURST : in std_logic_vector(1 downto 0); S_AXI_AWLOCK : in std_logic; S_AXI_AWCACHE : in std_logic_vector(3 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; -- AXI Write Data Channel Signals (W) S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); S_AXI_WLAST : in std_logic; S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; -- AXI Write Data Response Channel Signals (B) S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; -- AXI Read Address Channel Signals (AR) S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARLEN : in std_logic_vector(7 downto 0); S_AXI_ARSIZE : in std_logic_vector(2 downto 0); S_AXI_ARBURST : in std_logic_vector(1 downto 0); S_AXI_ARLOCK : in std_logic; S_AXI_ARCACHE : in std_logic_vector(3 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; -- AXI Read Data Channel Signals (R) S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RLAST : out std_logic; S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- AXI-Lite ECC Register Interface Signals -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_ACLK : in std_logic; -- S_AXI_CTRL_ARESETN : in std_logic; -- AXI-Lite Write Address Channel Signals (AW) S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic; -- BRAM Interface Signals (Port A) BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_En_A : out std_logic; BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- BRAM Interface Signals (Port B) BRAM_Rst_B : out std_logic; BRAM_Clk_B : out std_logic; BRAM_En_B : out std_logic; BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) ); end entity axi_bram_ctrl_top; ------------------------------------------------------------------------------- architecture implementation of axi_bram_ctrl_top is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Model behavior of AXI Interconnect in simulation for wrapping of ID values. constant C_SIM_ONLY : std_logic := '1'; -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; -- Create top level constant to assign fixed value to ARSIZE and AWSIZE -- when narrow bursting is parameterized out of the IP core instantiation. -- constant AXI_FIXED_SIZE_WO_NARROW : std_logic_vector (2 downto 0) := Create_Size_Default; -- v1.03a constant AXI_FIXED_SIZE_WO_NARROW : integer := log2 (C_S_AXI_DATA_WIDTH/8); -- Only instantiate logic based on C_S_AXI_PROTOCOL. constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Determine external ECC width. -- Use function defined in axi_bram_ctrl_funcs package. constant C_ECC_WIDTH : integer := Find_ECC_Size (C_ECC, C_S_AXI_DATA_WIDTH); constant C_ECC_FULL_BIT_WIDTH : integer := Find_ECC_Full_Bit_Size (C_ECC, C_S_AXI_DATA_WIDTH); -- Set internal parameters for ECC register enabling when C_ECC = 1 constant C_ENABLE_AXI_CTRL_REG_IF_I : integer := C_ECC; constant C_CE_FAILING_REGISTERS_I : integer := C_ECC; constant C_UE_FAILING_REGISTERS_I : integer := 0; -- Remove all UE registers -- Catastrophic error indicated with ECC_UE & Interrupt flags. constant C_ECC_STATUS_REGISTERS_I : integer := C_ECC; constant C_ECC_ONOFF_REGISTER_I : integer := C_ECC; constant C_CE_COUNTER_WIDTH : integer := 8 * C_ECC; -- Counter only sized when C_ECC = 1. -- Selects CE counter width/threshold to assert ECC_Interrupt -- Hard coded at 8-bits to capture and count up to 256 correctable errors. --constant C_ECC_TYPE : integer := 1; -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- -- Internal BRAM Signals -- Port A signal bram_en_a_int : std_logic := '0'; signal bram_we_a_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0'); signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); signal bram_rddata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port B signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_en_b_int : std_logic := '0'; signal bram_we_b_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0'); signal bram_wrdata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); signal bram_rddata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); signal axi_awsize_int : std_logic_vector(2 downto 0) := (others => '0'); signal axi_arsize_int : std_logic_vector(2 downto 0) := (others => '0'); signal S_AXI_ARREADY_int : std_logic := '0'; signal S_AXI_AWREADY_int : std_logic := '0'; signal S_AXI_RID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal S_AXI_BID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin -- *** BRAM Port A Output Signals *** BRAM_Rst_A <= not (S_AXI_ARESETN); BRAM_Clk_A <= S_AXI_ACLK; BRAM_En_A <= bram_en_a_int; BRAM_WE_A ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_a_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0); BRAM_Addr_A <= bram_addr_a_int; bram_rddata_a_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)); BRAM_WrData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH-1 downto 0); -- Added for 13.3 -- Drive unused upper ECC bits to '0' -- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case. GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate begin BRAM_WrData_A ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0'); BRAM_WrData_A ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0); end generate GEN_128_ECC_WR; GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate begin BRAM_WrData_A ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0); end generate GEN_ECC_WR; -- *** BRAM Port B Output Signals *** GEN_PORT_B: if (C_SINGLE_PORT_BRAM = 0) generate begin BRAM_Rst_B <= not (S_AXI_ARESETN); BRAM_WE_B ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_b_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0); BRAM_Addr_B <= bram_addr_b_int; BRAM_En_B <= bram_en_b_int; bram_rddata_b_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)); BRAM_WrData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH-1 downto 0); -- 13.3 -- BRAM_WrData_B <= bram_wrdata_b_int; -- Added for 13.3 -- Drive unused upper ECC bits to '0' -- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case. GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate begin BRAM_WrData_B ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0'); BRAM_WrData_B ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0); end generate GEN_128_ECC_WR; GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate begin BRAM_WrData_B ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0); end generate GEN_ECC_WR; end generate GEN_PORT_B; GEN_NO_PORT_B: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_Rst_B <= '0'; BRAM_WE_B <= (others => '0'); BRAM_WrData_B <= (others => '0'); BRAM_Addr_B <= (others => '0'); BRAM_En_B <= '0'; end generate GEN_NO_PORT_B; --------------------------------------------------------------------------- -- -- Generate: GEN_BRAM_CLK_B -- Purpose: Only drive BRAM_Clk_B when dual port BRAM is enabled. -- --------------------------------------------------------------------------- GEN_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 0) generate begin BRAM_Clk_B <= S_AXI_ACLK; end generate GEN_BRAM_CLK_B; --------------------------------------------------------------------------- -- -- Generate: GEN_NO_BRAM_CLK_B -- Purpose: Drive default value for BRAM_Clk_B when single port -- BRAM is enabled and no clock is necessary on the inactive -- BRAM port. -- --------------------------------------------------------------------------- GEN_NO_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_Clk_B <= '0'; end generate GEN_NO_BRAM_CLK_B; --------------------------------------------------------------------------- -- Generate top level ARSIZE and AWSIZE signals for rd_chnl and wr_chnl -- respectively, based on design parameter setting of generic, -- C_S_AXI_SUPPORTS_NARROW_BURST. --------------------------------------------------------------------------- -- -- Generate: GEN_W_NARROW -- Purpose: Create internal AWSIZE and ARSIZE signal for write and -- read channel modules based on top level AXI signal inputs. -- --------------------------------------------------------------------------- GEN_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 1) and (IF_IS_AXI4) generate begin axi_awsize_int <= S_AXI_AWSIZE; axi_arsize_int <= S_AXI_ARSIZE; end generate GEN_W_NARROW; --------------------------------------------------------------------------- -- -- Generate: GEN_WO_NARROW -- Purpose: Create internal AWSIZE and ARSIZE signal for write and -- read channel modules based on hard coded -- value that indicates all AXI transfers will be equal in -- size to the AXI data bus. -- --------------------------------------------------------------------------- GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 0) or (IF_IS_AXI4LITE) generate begin -- axi_awsize_int <= AXI_FIXED_SIZE_WO_NARROW; -- When AXI-LITE (no narrow transfers supported) -- axi_arsize_int <= AXI_FIXED_SIZE_WO_NARROW; -- v1.03a axi_awsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3)); axi_arsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3)); end generate GEN_WO_NARROW; S_AXI_ARREADY <= S_AXI_ARREADY_int; S_AXI_AWREADY <= S_AXI_AWREADY_int; --------------------------------------------------------------------------- -- -- Generate: GEN_AXI_LITE -- Purpose: Create internal signals for lower level write and read -- channel modules to discard unused AXI signals when the -- AXI protocol is set up for AXI-LITE. -- --------------------------------------------------------------------------- GEN_AXI4LITE: if (IF_IS_AXI4LITE) generate begin -- For simulation purposes ONLY -- AXI Interconnect handles this in real system topologies. S_AXI_BID <= S_AXI_BID_int; S_AXI_RID <= S_AXI_RID_int; ----------------------------------------------------------------------- -- -- Generate: GEN_SIM_ONLY -- Purpose: Mimic behavior of AXI Interconnect in simulation. -- In real hardware system, AXI Interconnect stores and -- wraps value of ARID to RID and AWID to BID. -- ----------------------------------------------------------------------- GEN_SIM_ONLY: if (C_SIM_ONLY = '1') generate begin ------------------------------------------------------------------- -- Must register and wrap the AWID signal REG_BID: process (S_AXI_ACLK) begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if (S_AXI_ARESETN = C_RESET_ACTIVE) then S_AXI_BID_int <= (others => '0'); elsif (S_AXI_AWVALID = '1') and (S_AXI_AWREADY_int = '1') then S_AXI_BID_int <= S_AXI_AWID; else S_AXI_BID_int <= S_AXI_BID_int; end if; end if; end process REG_BID; ------------------------------------------------------------------- -- Must register and wrap the ARID signal REG_RID: process (S_AXI_ACLK) begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if (S_AXI_ARESETN = C_RESET_ACTIVE) then S_AXI_RID_int <= (others => '0'); elsif (S_AXI_ARVALID = '1') and (S_AXI_ARREADY_int = '1') then S_AXI_RID_int <= S_AXI_ARID; else S_AXI_RID_int <= S_AXI_RID_int; end if; end if; end process REG_RID; ------------------------------------------------------------------- end generate GEN_SIM_ONLY; --------------------------------------------------------------------------- -- -- Generate: GEN_HW -- Purpose: Drive default values of RID and BID. In real system -- these are left unconnected and AXI Interconnect is -- responsible for values. -- --------------------------------------------------------------------------- GEN_HW: if (C_SIM_ONLY = '0') generate begin S_AXI_BID_int <= (others => '0'); S_AXI_RID_int <= (others => '0'); end generate GEN_HW; --------------------------------------------------------------------------- -- Instance: I_AXI_LITE -- -- Description: -- This module is for the AXI-Lite -- instantiation of the BRAM controller interface. -- -- Responsible for shared address pipelining between the -- write address (AW) and read address (AR) channels. -- Controls (seperately) the data flows for the write data -- (W), write response (B), and read data (R) channels. -- -- Creates a shared port to BRAM (for all read and write -- transactions) or dual BRAM port utilization based on a -- generic parameter setting. -- -- Instantiates ECC register block if enabled and -- generates ECC logic, when enabled. -- -- --------------------------------------------------------------------------- I_AXI_LITE : entity work.axi_lite generic map ( C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , -- C_FAMILY => C_FAMILY , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC => C_ECC , C_ECC_TYPE => C_ECC_TYPE , -- v1.03a C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths) C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC C_FAULT_INJECT => C_FAULT_INJECT , C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , ECC_Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , AXI_AWADDR => S_AXI_AWADDR , AXI_AWVALID => S_AXI_AWVALID , AXI_AWREADY => S_AXI_AWREADY_int , AXI_WDATA => S_AXI_WDATA , AXI_WSTRB => S_AXI_WSTRB , AXI_WVALID => S_AXI_WVALID , AXI_WREADY => S_AXI_WREADY , AXI_BRESP => S_AXI_BRESP , AXI_BVALID => S_AXI_BVALID , AXI_BREADY => S_AXI_BREADY , AXI_ARADDR => S_AXI_ARADDR , AXI_ARVALID => S_AXI_ARVALID , AXI_ARREADY => S_AXI_ARREADY_int , AXI_RDATA => S_AXI_RDATA , AXI_RRESP => S_AXI_RRESP , AXI_RLAST => S_AXI_RLAST , AXI_RVALID => S_AXI_RVALID , AXI_RREADY => S_AXI_RREADY , -- Add AXI-Lite ECC Register Ports -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK , -- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN , AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , BRAM_En_A => bram_en_a_int , BRAM_WE_A => bram_we_a_int , BRAM_Addr_A => bram_addr_a_int , BRAM_WrData_A => bram_wrdata_a_int , BRAM_RdData_A => bram_rddata_a_int , BRAM_En_B => bram_en_b_int , BRAM_WE_B => bram_we_b_int , BRAM_Addr_B => bram_addr_b_int , BRAM_WrData_B => bram_wrdata_b_int , BRAM_RdData_B => bram_rddata_b_int ); end generate GEN_AXI4LITE; --------------------------------------------------------------------------- -- -- Generate: GEN_AXI -- Purpose: Only create internal signals for lower level write and read -- channel modules to assign AXI signals when the -- AXI protocol is set up for non AXI-LITE IF connections. -- For AXI4, all AXI signals are assigned to lower level modules. -- -- For AXI-Lite connections, generate statement above will -- create default values on these signals (assigned here). -- --------------------------------------------------------------------------- GEN_AXI4: if (IF_IS_AXI4) generate begin --------------------------------------------------------------------------- -- Instance: I_FULL_AXI -- -- Description: -- Full AXI BRAM controller logic. -- Instantiates wr_chnl and rd_chnl modules. -- If enabled, ECC register interface is included. -- --------------------------------------------------------------------------- I_FULL_AXI : entity work.full_axi generic map ( C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC => C_ECC , C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths) C_ECC_TYPE => C_ECC_TYPE , -- v1.03a C_FAULT_INJECT => C_FAULT_INJECT , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , ECC_Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , S_AXI_AWID => S_AXI_AWID , S_AXI_AWADDR => S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH-1 downto 0), S_AXI_AWLEN => S_AXI_AWLEN , S_AXI_AWSIZE => axi_awsize_int , S_AXI_AWBURST => S_AXI_AWBURST , S_AXI_AWLOCK => S_AXI_AWLOCK , S_AXI_AWCACHE => S_AXI_AWCACHE , S_AXI_AWPROT => S_AXI_AWPROT , S_AXI_AWVALID => S_AXI_AWVALID , S_AXI_AWREADY => S_AXI_AWREADY_int , S_AXI_WDATA => S_AXI_WDATA , S_AXI_WSTRB => S_AXI_WSTRB , S_AXI_WLAST => S_AXI_WLAST , S_AXI_WVALID => S_AXI_WVALID , S_AXI_WREADY => S_AXI_WREADY , S_AXI_BID => S_AXI_BID , S_AXI_BRESP => S_AXI_BRESP , S_AXI_BVALID => S_AXI_BVALID , S_AXI_BREADY => S_AXI_BREADY , S_AXI_ARID => S_AXI_ARID , S_AXI_ARADDR => S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH-1 downto 0), S_AXI_ARLEN => S_AXI_ARLEN , S_AXI_ARSIZE => axi_arsize_int , S_AXI_ARBURST => S_AXI_ARBURST , S_AXI_ARLOCK => S_AXI_ARLOCK , S_AXI_ARCACHE => S_AXI_ARCACHE , S_AXI_ARPROT => S_AXI_ARPROT , S_AXI_ARVALID => S_AXI_ARVALID , S_AXI_ARREADY => S_AXI_ARREADY_int , S_AXI_RID => S_AXI_RID , S_AXI_RDATA => S_AXI_RDATA , S_AXI_RRESP => S_AXI_RRESP , S_AXI_RLAST => S_AXI_RLAST , S_AXI_RVALID => S_AXI_RVALID , S_AXI_RREADY => S_AXI_RREADY , -- Add AXI-Lite ECC Register Ports -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK , -- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN , S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , BRAM_En_A => bram_en_a_int , BRAM_WE_A => bram_we_a_int , BRAM_WrData_A => bram_wrdata_a_int , BRAM_Addr_A => bram_addr_a_int , BRAM_RdData_A => bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) , BRAM_En_B => bram_en_b_int , BRAM_WE_B => bram_we_b_int , BRAM_Addr_B => bram_addr_b_int , BRAM_WrData_B => bram_wrdata_b_int , BRAM_RdData_B => bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ); -- v1.02a -- Seperate instantiations for wr_chnl and rd_chnl moved to -- full_axi module. end generate GEN_AXI4; end architecture implementation; ------------------------------------------------------------------------------- -- axi_bram_ctrl.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_bram_ctrl_wrapper.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller IP core. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v4_0) -- | -- |--axi_bram_ctrl_top.vhd -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- ecc_gen.vhd -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; Library xpm; use xpm.vcomponents.all; library work; use work.axi_bram_ctrl_top; use work.axi_bram_ctrl_funcs.all; --use work.coregen_comp_defs.all; library blk_mem_gen_v8_3_6; use blk_mem_gen_v8_3_6.all; ------------------------------------------------------------------------------ entity axi_bram_ctrl is generic ( C_BRAM_INST_MODE : string := "EXTERNAL"; -- external ; internal --determines whether the bmg is external or internal to axi bram ctrl wrapper C_MEMORY_DEPTH : integer := 4096; --Memory depth specified by the user C_BRAM_ADDR_WIDTH : integer := 12; -- Width of AXI address bus (in bits) C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1; -- Support for narrow burst operations C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM C_FAMILY : string := "virtex7"; -- Specify the target architecture type C_SELECT_XPM : integer := 1; -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_TYPE : integer := 1; C_FAULT_INJECT : integer := 0; -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE : integer := 1 -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) ); port ( -- AXI Interface Signals -- AXI Clock and Reset s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; ecc_interrupt : out std_logic := '0'; ecc_ue : out std_logic := '0'; -- axi write address channel Signals (AW) s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic; s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; -- axi write data channel Signals (W) s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); s_axi_wlast : in std_logic; s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; -- axi write data response Channel Signals (B) s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; -- axi read address channel Signals (AR) s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic; s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; -- axi read data channel Signals (R) s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- axi-lite ecc register Interface Signals -- axi-lite clock and Reset -- note: axi-lite control IF and AXI IF share the same clock. -- s_axi_ctrl_aclk : in std_logic; -- s_axi_ctrl_aresetn : in std_logic; -- axi-lite write address Channel Signals (AW) s_axi_ctrl_awvalid : in std_logic; s_axi_ctrl_awready : out std_logic; s_axi_ctrl_awaddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- axi-lite write data Channel Signals (W) s_axi_ctrl_wdata : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); s_axi_ctrl_wvalid : in std_logic; s_axi_ctrl_wready : out std_logic; -- axi-lite write data Response Channel Signals (B) s_axi_ctrl_bresp : out std_logic_vector(1 downto 0); s_axi_ctrl_bvalid : out std_logic; s_axi_ctrl_bready : in std_logic; -- axi-lite read address Channel Signals (AR) s_axi_ctrl_araddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); s_axi_ctrl_arvalid : in std_logic; s_axi_ctrl_arready : out std_logic; -- axi-lite read data Channel Signals (R) s_axi_ctrl_rdata : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); s_axi_ctrl_rresp : out std_logic_vector(1 downto 0); s_axi_ctrl_rvalid : out std_logic; s_axi_ctrl_rready : in std_logic; -- bram interface signals (Port A) bram_rst_a : out std_logic; bram_clk_a : out std_logic; bram_en_a : out std_logic; bram_we_a : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_addr_a : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); bram_wrdata_a : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_rddata_a : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- bram interface signals (Port B) bram_rst_b : out std_logic; bram_clk_b : out std_logic; bram_en_b : out std_logic; bram_we_b : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_addr_b : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); bram_wrdata_b : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); bram_rddata_b : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) ); end entity axi_bram_ctrl; ------------------------------------------------------------------------------- architecture implementation of axi_bram_ctrl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; component xpm_memory_tdpram generic ( MEMORY_SIZE : integer := 4096*32; MEMORY_PRIMITIVE : string := "auto"; CLOCKING_MODE : string := "common_clock"; ECC_MODE : string := "no_ecc"; MEMORY_INIT_FILE : string := "none"; MEMORY_INIT_PARAM : string := ""; WAKEUP_TIME : string := "disable_sleep"; MESSAGE_CONTROL : integer := 0; WRITE_DATA_WIDTH_A : integer := 32; READ_DATA_WIDTH_A : integer := 32; BYTE_WRITE_WIDTH_A : integer := 8; ADDR_WIDTH_A : integer := 12; READ_RESET_VALUE_A : string := "0"; READ_LATENCY_A : integer := 1; WRITE_MODE_A : string := "read_first"; WRITE_DATA_WIDTH_B : integer := 32; READ_DATA_WIDTH_B : integer := 32; BYTE_WRITE_WIDTH_B : integer := 8; ADDR_WIDTH_B : integer := 12; READ_RESET_VALUE_B : string := "0"; READ_LATENCY_B : integer := 1; WRITE_MODE_B : string := "read_first" ); port ( -- Common module ports sleep : in std_logic; -- Port A module ports clka : in std_logic; rsta : in std_logic; ena : in std_logic; regcea : in std_logic; wea : in std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); -- (WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A)-1:0] -- addra : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); addra : in std_logic_vector (C_BRAM_ADDR_WIDTH-1 downto 0) := (others => '0'); dina : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); -- [WRITE_DATA_WIDTH_A-1:0] injectsbiterra : in std_logic; injectdbiterra : in std_logic; douta : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- [READ_DATA_WIDTH_A-1:0] sbiterra : out std_logic; dbiterra : out std_logic; -- Port B module ports clkb : in std_logic; rstb : in std_logic; enb : in std_logic; regceb : in std_logic; web : in std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); -- addrb : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); -- [ADDR_WIDTH_B-1:0] addrb : in std_logic_vector (C_BRAM_ADDR_WIDTH-1 downto 0) := (others => '0'); -- [ADDR_WIDTH_B-1:0] dinb : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); injectsbiterrb : in std_logic; injectdbiterrb : in std_logic; doutb : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- [READ_DATA_WIDTH_B-1:0] sbiterrb : out std_logic; dbiterrb : out std_logic ); end component; ------------------------------------------------------------------------------ -- FUNCTION: if_then_else -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------------------------------------------------- -- FUNCTION : log2roundup --------------------------------------------------------------------------- FUNCTION log2roundup (data_value : integer) RETURN integer IS VARIABLE width : integer := 0; VARIABLE cnt : integer := 1; CONSTANT lower_limit : integer := 1; CONSTANT upper_limit : integer := 8; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Only instantiate logic based on C_S_AXI_PROTOCOL. -- Determine external ECC width. -- Use function defined in axi_bram_ctrl_funcs package. -- Set internal parameters for ECC register enabling when C_ECC = 1 -- Catastrophic error indicated with ECC_UE & Interrupt flags. -- Counter only sized when C_ECC = 1. -- Selects CE counter width/threshold to assert ECC_Interrupt -- Hard coded at 8-bits to capture and count up to 256 correctable errors. -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code constant GND : std_logic := '0'; constant VCC : std_logic := '1'; constant ZERO1 : std_logic_vector(0 downto 0) := (others => '0'); constant ZERO2 : std_logic_vector(1 downto 0) := (others => '0'); constant ZERO3 : std_logic_vector(2 downto 0) := (others => '0'); constant ZERO4 : std_logic_vector(3 downto 0) := (others => '0'); constant ZERO8 : std_logic_vector(7 downto 0) := (others => '0'); constant WSTRB_ZERO : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); constant ZERO16 : std_logic_vector(15 downto 0) := (others => '0'); constant ZERO32 : std_logic_vector(31 downto 0) := (others => '0'); constant ZERO64 : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); CONSTANT MEM_TYPE : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,2); CONSTANT BWE_B : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,1); CONSTANT BMG_ADDR_WIDTH : INTEGER := log2roundup(C_MEMORY_DEPTH) + log2roundup(C_S_AXI_DATA_WIDTH/8) ; ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal clka_bram_clka_i : std_logic := '0'; signal rsta_bram_rsta_i : std_logic := '0'; signal ena_bram_ena_i : std_logic := '0'; signal REGCEA : std_logic := '0'; signal wea_bram_wea_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal addra_bram_addra_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal dina_bram_dina_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal douta_bram_douta_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); signal clkb_bram_clkb_i : std_logic := '0'; signal rstb_bram_rstb_i : std_logic := '0'; signal enb_bram_enb_i : std_logic := '0'; signal REGCEB : std_logic := '0'; signal web_bram_web_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal addrb_bram_addrb_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal dinb_bram_dinb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal doutb_bram_doutb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); ----------------------------------------------------------------------- -- Architecture Body ----------------------------------------------------------------------- begin gint_inst: IF (C_BRAM_INST_MODE = "INTERNAL" ) GENERATE constant c_addrb_width : INTEGER := log2roundup(C_MEMORY_DEPTH); constant C_WEA_WIDTH_I : INTEGER := (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ; constant C_WRITE_WIDTH_A_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ; constant C_READ_WIDTH_A_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))); constant C_ADDRA_WIDTH_I : INTEGER := log2roundup(C_MEMORY_DEPTH); constant C_WEB_WIDTH_I : INTEGER := (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))); constant C_WRITE_WIDTH_B_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))); constant C_READ_WIDTH_B_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))); signal s_axi_rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal s_axi_dbiterr_bmg_int : STD_LOGIC; signal s_axi_sbiterr_bmg_int : STD_LOGIC; signal s_axi_rvalid_bmg_int : STD_LOGIC; signal s_axi_rlast_bmg_int : STD_LOGIC; signal s_axi_rresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0); signal s_axi_rdata_bmg_int : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); signal s_axi_rid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0); signal s_axi_arready_bmg_int : STD_LOGIC; signal s_axi_bvalid_bmg_int : STD_LOGIC; signal s_axi_bresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0); signal s_axi_bid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0); signal s_axi_wready_bmg_int : STD_LOGIC; signal s_axi_awready_bmg_int : STD_LOGIC; signal rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal dbiterr_bmg_int : STD_LOGIC; signal sbiterr_bmg_int : STD_LOGIC; begin xpm_spram_mem_gen : if ((C_SELECT_XPM = 1) and (MEM_TYPE = 0)) generate xpm_memory_spram_inst : xpm_memory_spram generic map ( -- Common module generics MEMORY_SIZE => (C_WRITE_WIDTH_A_I*C_MEMORY_DEPTH), --positive integer MEMORY_PRIMITIVE => "block", ---"auto", --string; "auto", "distributed", "block" or "ultra" ; MEMORY_INIT_FILE => "none", --string; "none" or "<filename>.mem" MEMORY_INIT_PARAM => "", --string; USE_MEM_INIT => 1, --integer; 0,1 WAKEUP_TIME => "disable_sleep",--string; "disable_sleep" or "use_sleep_pin" MESSAGE_CONTROL => 0, --integer; 0,1 ECC_MODE => "no_ecc", --string; "no_ecc", "encode_only", "decode_only" or "both_encode_and_decode" AUTO_SLEEP_TIME => 0, --Do not Change -- Port A module generics WRITE_DATA_WIDTH_A => C_WRITE_WIDTH_A_I, --positive integer READ_DATA_WIDTH_A => C_READ_WIDTH_A_I, --positive integer BYTE_WRITE_WIDTH_A => 8, --integer; 8, 9, or WRITE_DATA_WIDTH_A value ADDR_WIDTH_A => C_ADDRA_WIDTH_I, --positive integer READ_RESET_VALUE_A => "0", --string READ_LATENCY_A => 1, --non-negative integer WRITE_MODE_A => "write_first" ---"read_first" --string; "write_first", "read_first", "no_change" ) port map ( -- Common module ports sleep => GND, ---'0', -- Port A module ports clka => clka_bram_clka_i, ----clka, rsta => rsta_bram_rsta_i, ----rsta, ena => ena_bram_ena_i, ----ena, regcea => GND, ---regcea, wea => wea_bram_wea_i, ----wea, addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)), ----addra, dina => dina_bram_dina_i, ----dina, injectsbiterra => GND, ---'0', injectdbiterra => GND, ---'0', douta => douta_bram_douta_i, ---douta, sbiterra => open, dbiterra => open ); end generate xpm_spram_mem_gen; xpm_tdpram_mem_gen : if ((C_SELECT_XPM = 1) and (MEM_TYPE = 2)) generate xpm_memory_inst: xpm_memory_tdpram generic map ( MEMORY_SIZE => C_WRITE_WIDTH_A_I*C_MEMORY_DEPTH, MEMORY_PRIMITIVE => "blockram", CLOCKING_MODE => "common_clock", ECC_MODE => "no_ecc", MEMORY_INIT_FILE => "none", MEMORY_INIT_PARAM => "", WAKEUP_TIME => "disable_sleep", MESSAGE_CONTROL => 0, WRITE_DATA_WIDTH_A => C_WRITE_WIDTH_A_I, READ_DATA_WIDTH_A => C_READ_WIDTH_A_I, BYTE_WRITE_WIDTH_A => 8, ADDR_WIDTH_A => C_ADDRA_WIDTH_I, READ_RESET_VALUE_A => "0", READ_LATENCY_A => 1, WRITE_MODE_A => "write_first", --write_first WRITE_DATA_WIDTH_B => C_WRITE_WIDTH_B_I, READ_DATA_WIDTH_B => C_READ_WIDTH_B_I, BYTE_WRITE_WIDTH_B => 8, ADDR_WIDTH_B => C_ADDRB_WIDTH, READ_RESET_VALUE_B => "0", READ_LATENCY_B => 1, WRITE_MODE_B => "write_first" ) port map ( -- Common module ports sleep => GND, -- Port A module ports clka => clka_bram_clka_i, rsta => rsta_bram_rsta_i, ena => ena_bram_ena_i, regcea => GND, wea => wea_bram_wea_i, addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)), dina => dina_bram_dina_i, injectsbiterra => GND, injectdbiterra => GND, douta => douta_bram_douta_i, sbiterra => open, dbiterra => open, -- Port B module ports clkb => clkb_bram_clkb_i, rstb => rstb_bram_rstb_i, enb => enb_bram_enb_i, regceb => GND, web => web_bram_web_i, addrb => addrb_bram_addrb_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)), dinb => dinb_bram_dinb_i, injectsbiterrb => GND, injectdbiterrb => GND, doutb => doutb_bram_doutb_i, sbiterrb => open, dbiterrb => open ); end generate xpm_tdpram_mem_gen; blk_mem_gen : if (C_SELECT_XPM = 0) generate bmgv81_inst : entity blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6 GENERIC MAP( ---------------------------------------------------------------------------- -- Generic Declarations ---------------------------------------------------------------------------- --Device Family & Elaboration Directory Parameters: C_FAMILY => C_FAMILY, C_XDEVICEFAMILY => C_FAMILY, ---- C_ELABORATION_DIR => "NULL" , C_INTERFACE_TYPE => 0 , --General Memory Parameters: ----- C_ENABLE_32BIT_ADDRESS => 0 , C_MEM_TYPE => MEM_TYPE , C_BYTE_SIZE => 8 , C_ALGORITHM => 1 , C_PRIM_TYPE => 1 , --Memory Initialization Parameters: C_LOAD_INIT_FILE => 0 , C_INIT_FILE_NAME => "no_coe_file_loaded" , C_USE_DEFAULT_DATA => 0 , C_DEFAULT_DATA => "NULL" , --Port A Parameters: --Reset Parameters: C_HAS_RSTA => 0 , --Enable Parameters: C_HAS_ENA => 1 , C_HAS_REGCEA => 0 , --Byte Write Enable Parameters: C_USE_BYTE_WEA => 1 , C_WEA_WIDTH => C_WEA_WIDTH_I, --(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) , --Write Mode: C_WRITE_MODE_A => "WRITE_FIRST" , --Data-Addr Width Parameters: C_WRITE_WIDTH_A => C_WRITE_WIDTH_A_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) , C_READ_WIDTH_A => C_READ_WIDTH_A_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) , C_WRITE_DEPTH_A => C_MEMORY_DEPTH , C_READ_DEPTH_A => C_MEMORY_DEPTH , C_ADDRA_WIDTH => C_ADDRA_WIDTH_I,--log2roundup(C_MEMORY_DEPTH) , --Port B Parameters: --Reset Parameters: C_HAS_RSTB => 0 , --Enable Parameters: C_HAS_ENB => 1 , C_HAS_REGCEB => 0 , --Byte Write Enable Parameters: C_USE_BYTE_WEB => BWE_B , C_WEB_WIDTH => C_WEB_WIDTH_I,--(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) , --Write Mode: C_WRITE_MODE_B => "WRITE_FIRST" , --Data-Addr Width Parameters: C_WRITE_WIDTH_B => C_WRITE_WIDTH_B_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) , C_READ_WIDTH_B => C_READ_WIDTH_B_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) , C_WRITE_DEPTH_B => C_MEMORY_DEPTH , C_READ_DEPTH_B => C_MEMORY_DEPTH , C_ADDRB_WIDTH => C_ADDRB_WIDTH,--log2roundup(C_MEMORY_DEPTH) , --Output Registers/ Pipelining Parameters: C_HAS_MEM_OUTPUT_REGS_A => 0 , C_HAS_MEM_OUTPUT_REGS_B => 0 , C_HAS_MUX_OUTPUT_REGS_A => 0 , C_HAS_MUX_OUTPUT_REGS_B => 0 , C_MUX_PIPELINE_STAGES => 0 , --Input/Output Registers for SoftECC : C_HAS_SOFTECC_INPUT_REGS_A => 0 , C_HAS_SOFTECC_OUTPUT_REGS_B=> 0 , --ECC Parameters C_USE_ECC => 0 , C_USE_SOFTECC => 0 , C_HAS_INJECTERR => 0 , C_EN_ECC_PIPE => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, --Simulation Model Parameters: C_SIM_COLLISION_CHECK => "NONE" , C_COMMON_CLK => 1 , C_DISABLE_WARN_BHV_COLL => 1 , C_DISABLE_WARN_BHV_RANGE => 1 ) PORT MAP( ---------------------------------------------------------------------------- -- Input and Output Declarations ---------------------------------------------------------------------------- -- Native BMG Input and Output Port Declarations --Port A: clka => clka_bram_clka_i , rsta => rsta_bram_rsta_i , ena => ena_bram_ena_i , regcea => GND , wea => wea_bram_wea_i , addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , --addra => addra_bram_addra_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , dina => dina_bram_dina_i , douta => douta_bram_douta_i , --port b: clkb => clkb_bram_clkb_i , rstb => rstb_bram_rstb_i , enb => enb_bram_enb_i , regceb => GND , web => web_bram_web_i , addrb => addrb_bram_addrb_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , --addrb => addrb_bram_addrb_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) , dinb => dinb_bram_dinb_i , doutb => doutb_bram_doutb_i , --ecc: injectsbiterr => GND , injectdbiterr => GND , sbiterr => sbiterr_bmg_int, dbiterr => dbiterr_bmg_int, rdaddrecc => rdaddrecc_bmg_int, eccpipece => GND, sleep => GND, deepsleep => GND, shutdown => GND, -- axi bmg input and output Port Declarations -- axi global signals s_aclk => GND , s_aresetn => GND , -- axi full/lite slave write (write side) s_axi_awid => ZERO4 , s_axi_awaddr => ZERO32 , s_axi_awlen => ZERO8 , s_axi_awsize => ZERO3 , s_axi_awburst => ZERO2 , s_axi_awvalid => GND , s_axi_awready => s_axi_awready_bmg_int, s_axi_wdata => ZERO64 , s_axi_wstrb => WSTRB_ZERO, s_axi_wlast => GND , s_axi_wvalid => GND , s_axi_wready => s_axi_wready_bmg_int, s_axi_bid => s_axi_bid_bmg_int, s_axi_bresp => s_axi_bresp_bmg_int, s_axi_bvalid => s_axi_bvalid_bmg_int, s_axi_bready => GND , -- axi full/lite slave read (Write side) s_axi_arid => ZERO4, s_axi_araddr => "00000000000000000000000000000000", s_axi_arlen => "00000000", s_axi_arsize => "000", s_axi_arburst => "00", s_axi_arvalid => '0', s_axi_arready => s_axi_arready_bmg_int, s_axi_rid => s_axi_rid_bmg_int, s_axi_rdata => s_axi_rdata_bmg_int, s_axi_rresp => s_axi_rresp_bmg_int, s_axi_rlast => s_axi_rlast_bmg_int, s_axi_rvalid => s_axi_rvalid_bmg_int, s_axi_rready => GND , -- axi full/lite sideband Signals s_axi_injectsbiterr => GND , s_axi_injectdbiterr => GND , s_axi_sbiterr => s_axi_sbiterr_bmg_int, s_axi_dbiterr => s_axi_dbiterr_bmg_int, s_axi_rdaddrecc => s_axi_rdaddrecc_bmg_int ); end generate blk_mem_gen; abcv4_0_int_inst : entity work.axi_bram_ctrl_top generic map( -- AXI Parameters C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , -- AXI ID vector width C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST , -- Support for narrow burst operations C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , -- Enable single port usage of BRAM -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC => C_ECC , -- Enables or disables ECC functionality C_ECC_TYPE => C_ECC_TYPE , C_FAULT_INJECT => C_FAULT_INJECT , -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) ) port map( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK => S_AXI_ACLK , S_AXI_ARESETN => S_AXI_ARESETN , ECC_Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , -- AXI Write Address Channel Signals (AW) S_AXI_AWID => S_AXI_AWID , S_AXI_AWADDR => S_AXI_AWADDR , S_AXI_AWLEN => S_AXI_AWLEN , S_AXI_AWSIZE => S_AXI_AWSIZE , S_AXI_AWBURST => S_AXI_AWBURST , S_AXI_AWLOCK => S_AXI_AWLOCK , S_AXI_AWCACHE => S_AXI_AWCACHE , S_AXI_AWPROT => S_AXI_AWPROT , S_AXI_AWVALID => S_AXI_AWVALID , S_AXI_AWREADY => S_AXI_AWREADY , -- AXI Write Data Channel Signals (W) S_AXI_WDATA => S_AXI_WDATA , S_AXI_WSTRB => S_AXI_WSTRB , S_AXI_WLAST => S_AXI_WLAST , S_AXI_WVALID => S_AXI_WVALID , S_AXI_WREADY => S_AXI_WREADY , -- AXI Write Data Response Channel Signals (B) S_AXI_BID => S_AXI_BID , S_AXI_BRESP => S_AXI_BRESP , S_AXI_BVALID => S_AXI_BVALID , S_AXI_BREADY => S_AXI_BREADY , -- AXI Read Address Channel Signals (AR) S_AXI_ARID => S_AXI_ARID , S_AXI_ARADDR => S_AXI_ARADDR , S_AXI_ARLEN => S_AXI_ARLEN , S_AXI_ARSIZE => S_AXI_ARSIZE , S_AXI_ARBURST => S_AXI_ARBURST , S_AXI_ARLOCK => S_AXI_ARLOCK , S_AXI_ARCACHE => S_AXI_ARCACHE , S_AXI_ARPROT => S_AXI_ARPROT , S_AXI_ARVALID => S_AXI_ARVALID , S_AXI_ARREADY => S_AXI_ARREADY , -- AXI Read Data Channel Signals (R) S_AXI_RID => S_AXI_RID , S_AXI_RDATA => S_AXI_RDATA , S_AXI_RRESP => S_AXI_RRESP , S_AXI_RLAST => S_AXI_RLAST , S_AXI_RVALID => S_AXI_RVALID , S_AXI_RREADY => S_AXI_RREADY , -- AXI-Lite ECC Register Interface Signals -- AXI-Lite Write Address Channel Signals (AW) S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , -- AXI-Lite Write Data Channel Signals (W) S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , -- AXI-Lite Write Data Response Channel Signals (B) S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , -- AXI-Lite Read Address Channel Signals (AR) S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , -- AXI-Lite Read Data Channel Signals (R) S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , -- BRAM Interface Signals (Port A) BRAM_Rst_A => rsta_bram_rsta_i , BRAM_Clk_A => clka_bram_clka_i , BRAM_En_A => ena_bram_ena_i , BRAM_WE_A => wea_bram_wea_i , BRAM_Addr_A => addra_bram_addra_i, BRAM_WrData_A => dina_bram_dina_i , BRAM_RdData_A => douta_bram_douta_i , -- BRAM Interface Signals (Port B) BRAM_Rst_B => rstb_bram_rstb_i , BRAM_Clk_B => clkb_bram_clkb_i , BRAM_En_B => enb_bram_enb_i , BRAM_WE_B => web_bram_web_i , BRAM_Addr_B => addrb_bram_addrb_i , BRAM_WrData_B => dinb_bram_dinb_i , BRAM_RdData_B => doutb_bram_doutb_i ); -- The following signals are driven 0's to remove the synthesis warnings bram_rst_a <= '0'; bram_clk_a <= '0'; bram_en_a <= '0'; bram_we_a <= (others => '0'); bram_addr_a <= (others => '0'); bram_wrdata_a <= (others => '0'); bram_rst_b <= '0'; bram_clk_b <= '0'; bram_en_b <= '0'; bram_we_b <= (others => '0'); bram_addr_b <= (others => '0'); bram_wrdata_b <= (others => '0'); END GENERATE gint_inst; -- End of internal bram instance gext_inst: IF (C_BRAM_INST_MODE = "EXTERNAL" ) GENERATE abcv4_0_ext_inst : entity work.axi_bram_ctrl_top generic map( -- AXI Parameters C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , -- AXI ID vector width C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST , -- Support for narrow burst operations C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , -- Enable single port usage of BRAM -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC => C_ECC , -- Enables or disables ECC functionality C_ECC_TYPE => C_ECC_TYPE , C_FAULT_INJECT => C_FAULT_INJECT , -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) ) port map( -- AXI Interface Signals -- AXI Clock and Reset s_axi_aclk => s_axi_aclk , s_axi_aresetn => s_axi_aresetn , ecc_interrupt => ecc_interrupt , ecc_ue => ecc_ue , -- axi write address channel signals (aw) s_axi_awid => s_axi_awid , s_axi_awaddr => s_axi_awaddr , s_axi_awlen => s_axi_awlen , s_axi_awsize => s_axi_awsize , s_axi_awburst => s_axi_awburst , s_axi_awlock => s_axi_awlock , s_axi_awcache => s_axi_awcache , s_axi_awprot => s_axi_awprot , s_axi_awvalid => s_axi_awvalid , s_axi_awready => s_axi_awready , -- axi write data channel signals (w) s_axi_wdata => s_axi_wdata , s_axi_wstrb => s_axi_wstrb , s_axi_wlast => s_axi_wlast , s_axi_wvalid => s_axi_wvalid , s_axi_wready => s_axi_wready , -- axi write data response channel signals (b) s_axi_bid => s_axi_bid , s_axi_bresp => s_axi_bresp , s_axi_bvalid => s_axi_bvalid , s_axi_bready => s_axi_bready , -- axi read address channel signals (ar) s_axi_arid => s_axi_arid , s_axi_araddr => s_axi_araddr , s_axi_arlen => s_axi_arlen , s_axi_arsize => s_axi_arsize , s_axi_arburst => s_axi_arburst , s_axi_arlock => s_axi_arlock , s_axi_arcache => s_axi_arcache , s_axi_arprot => s_axi_arprot , s_axi_arvalid => s_axi_arvalid , s_axi_arready => s_axi_arready , -- axi read data channel signals (r) s_axi_rid => s_axi_rid , s_axi_rdata => s_axi_rdata , s_axi_rresp => s_axi_rresp , s_axi_rlast => s_axi_rlast , s_axi_rvalid => s_axi_rvalid , s_axi_rready => s_axi_rready , -- axi-lite ecc register interface signals -- axi-lite write address channel signals (aw) s_axi_ctrl_awvalid => s_axi_ctrl_awvalid , s_axi_ctrl_awready => s_axi_ctrl_awready , s_axi_ctrl_awaddr => s_axi_ctrl_awaddr , -- axi-lite write data channel signals (w) s_axi_ctrl_wdata => s_axi_ctrl_wdata , s_axi_ctrl_wvalid => s_axi_ctrl_wvalid , s_axi_ctrl_wready => s_axi_ctrl_wready , -- axi-lite write data response channel signals (b) s_axi_ctrl_bresp => s_axi_ctrl_bresp , s_axi_ctrl_bvalid => s_axi_ctrl_bvalid , s_axi_ctrl_bready => s_axi_ctrl_bready , -- axi-lite read address channel signals (ar) s_axi_ctrl_araddr => s_axi_ctrl_araddr , s_axi_ctrl_arvalid => s_axi_ctrl_arvalid , s_axi_ctrl_arready => s_axi_ctrl_arready , -- axi-lite read data channel signals (r) s_axi_ctrl_rdata => s_axi_ctrl_rdata , s_axi_ctrl_rresp => s_axi_ctrl_rresp , s_axi_ctrl_rvalid => s_axi_ctrl_rvalid , s_axi_ctrl_rready => s_axi_ctrl_rready , -- bram interface signals (port a) bram_rst_a => bram_rst_a , bram_clk_a => bram_clk_a , bram_en_a => bram_en_a , bram_we_a => bram_we_a , bram_addr_a => bram_addr_a , bram_wrdata_a => bram_wrdata_a , bram_rddata_a => bram_rddata_a , -- bram interface signals (port b) bram_rst_b => bram_rst_b , bram_clk_b => bram_clk_b , bram_en_b => bram_en_b , bram_we_b => bram_we_b , bram_addr_b => bram_addr_b , bram_wrdata_b => bram_wrdata_b , bram_rddata_b => bram_rddata_b ); END GENERATE gext_inst; -- End of internal bram instance end architecture implementation;

mit

55dc1649f0e358f861871ff293f86dd5

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml50x/testbench.vhd

----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; library micron; use micron.components.all; library cypress; use cypress.components.all; use work.debug.all; use work.config.all; -- configuration entity testbench is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; ncpu : integer := CFG_NCPU; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; clkperiod : integer := 10; -- system clock period romwidth : integer := 32; -- rom data width (8/32) romdepth : integer := 16; -- rom address depth sramwidth : integer := 32; -- ram data width (8/16/32) sramdepth : integer := 18; -- ram address depth srambanks : integer := 2 -- number of ram banks ); end; architecture behav of testbench is constant promfile : string := "prom.srec"; -- rom contents constant sramfile : string := "ram.srec"; -- ram contents constant sdramfile : string := "ram.srec"; -- sdram contents signal sys_clk : std_logic := '0'; signal sys_rst_in : std_logic := '0'; -- Reset constant ct : integer := clkperiod/2; signal bus_error : std_logic_vector (1 downto 0); signal sram_flash_addr : std_logic_vector(23 downto 0); signal address : std_logic_vector(24 downto 0); signal sram_flash_data, data : std_logic_vector(31 downto 0); signal sram_cen : std_logic; signal sram_bw : std_logic_vector (3 downto 0); signal sram_oen : std_ulogic; signal flash_oen : std_ulogic; signal sram_flash_we_n : std_ulogic; signal flash_cen : std_logic; signal flash_adv_n : std_logic; signal sram_clk : std_ulogic; signal sram_clk_fb : std_ulogic; signal sram_mode : std_ulogic; signal sram_adv_ld_n : std_ulogic; signal iosn : std_ulogic; signal ddr_clk : std_logic_vector(1 downto 0); signal ddr_clkb : std_logic_vector(1 downto 0); signal ddr_cke : std_logic_vector(1 downto 0); signal ddr_csb : std_logic_vector(1 downto 0); signal ddr_odt : std_logic_vector(1 downto 0); signal ddr_web : std_ulogic; -- ddr write enable signal ddr_rasb : std_ulogic; -- ddr ras signal ddr_casb : std_ulogic; -- ddr cas signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm signal ddr_dqsp : std_logic_vector (7 downto 0); -- ddr dqs signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address signal ddr_ba : std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data signal ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data signal txd1 : std_ulogic; -- UART1 tx data signal rxd1 : std_ulogic; -- UART1 rx data signal txd2 : std_ulogic; -- UART2 tx data signal rxd2 : std_ulogic; -- UART2 rx data signal gpio : std_logic_vector(12 downto 0); -- I/O port signal led : std_logic_vector(12 downto 0); -- I/O port signal phy_mii_data: std_logic; -- ethernet PHY interface signal phy_tx_clk : std_ulogic; signal phy_rx_clk : std_ulogic; signal phy_rx_data : std_logic_vector(7 downto 0); signal phy_dv : std_ulogic; signal phy_rx_er : std_ulogic; signal phy_col : std_ulogic; signal phy_crs : std_ulogic; signal phy_tx_data : std_logic_vector(7 downto 0); signal phy_tx_en : std_ulogic; signal phy_tx_er : std_ulogic; signal phy_mii_clk : std_ulogic; signal phy_rst_n : std_ulogic; signal phy_int : std_ulogic := '0'; signal phy_gtx_clk : std_ulogic; signal ps2_keyb_clk: std_logic; signal ps2_keyb_data: std_logic; signal ps2_mouse_clk: std_logic; signal ps2_mouse_data: std_logic; signal usb_csn, usb_rstn : std_logic; signal iic_scl_main, iic_sda_main : std_logic; signal iic_scl_video, iic_sda_video : std_logic; signal tft_lcd_data : std_logic_vector(11 downto 0); signal tft_lcd_clk_p : std_logic; signal tft_lcd_clk_n : std_logic; signal tft_lcd_hsync : std_logic; signal tft_lcd_vsync : std_logic; signal tft_lcd_de : std_logic; signal tft_lcd_reset_b : std_logic; signal sysace_mpa : std_logic_vector(6 downto 0); signal sysace_mpce : std_ulogic; signal sysace_mpirq : std_ulogic; signal sysace_mpoe : std_ulogic; signal sysace_mpwe : std_ulogic; signal sysace_d : std_logic_vector(15 downto 0); --pcie-- signal cor_sys_reset_n : std_logic := '1'; signal ep_sys_clk_p : std_logic; signal ep_sys_clk_n : std_logic; signal rp_sys_clk : std_logic; signal cor_pci_exp_txn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0'); signal cor_pci_exp_txp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0'); signal cor_pci_exp_rxn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0'); signal cor_pci_exp_rxp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0'); --pcie end-- signal GND : std_ulogic := '0'; signal VCC : std_ulogic := '1'; signal NC : std_ulogic := 'Z'; signal clk_200_p : std_ulogic := '0'; signal clk_200_n : std_ulogic := '1'; signal clk_33 : std_ulogic := '0'; constant lresp : boolean := false; begin -- clock and reset sys_clk <= not sys_clk after ct * 1 ns; sys_rst_in <= '0', '1' after 200 ns; clk_200_p <= not clk_200_p after 2.5 ns; clk_200_n <= not clk_200_n after 2.5 ns; clk_33 <= not clk_33 after 15 ns; rxd1 <= 'H'; gpio(11) <= 'L'; sram_clk_fb <= sram_clk; ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H'; ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H'; iic_scl_main <= 'H'; iic_sda_main <= 'H'; iic_scl_video <= 'H'; iic_sda_video <= 'H'; sysace_d <= (others => 'H'); sysace_mpirq <= 'L'; cpu : entity work.leon3mp generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow ) port map ( sys_rst_in, sys_clk, clk_200_p, clk_200_n, clk_33, sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_oen, sram_flash_we_n, flash_cen, flash_oen, flash_adv_n,sram_clk, sram_clk_fb, sram_mode, sram_adv_ld_n, iosn, ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, txd1, rxd1, txd2, rxd2, gpio, led, bus_error, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_int, ps2_keyb_clk, ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, usb_csn, usb_rstn, iic_scl_main, iic_sda_main, iic_scl_video, iic_sda_video, tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync, tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b, sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe, sysace_mpwe, sysace_d, cor_pci_exp_txp, cor_pci_exp_txn, cor_pci_exp_rxp, cor_pci_exp_rxn, ep_sys_clk_p, ep_sys_clk_n, cor_sys_reset_n ); ddr0 : ddr2ram generic map(width => 64, abits => 13, babits =>2, colbits => 10, rowbits => 13, implbanks => 1, fname => sdramfile, speedbin=>1, density => 2, lddelay => 100 us * CFG_MIG_DDR2) port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0), odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2, dqs => ddr_dqsp, dqsn =>ddr_dqsn); nodqdel : if (CFG_MIG_DDR2 = 1) generate ddr2delay : delay_wire generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 0.0) port map(a => ddr_dq, b => ddr_dq2); end generate; dqdel : if (CFG_MIG_DDR2 = 0) generate ddr2delay : delay_wire generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 5.5) port map(a => ddr_dq, b => ddr_dq2); end generate; sram01 : for i in 0 to 1 generate sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile) port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(15-i*8 downto 8-i*8), sram_cen, sram_bw(i+2), sram_oen); end generate; sram23 : for i in 2 to 3 generate sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile) port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(47-i*8 downto 40-i*8), sram_cen, sram_bw(i-2), sram_oen); end generate; prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile) port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(15 downto 0), gnd, gnd, flash_cen, sram_flash_we_n, flash_oen); phy_mii_data <= 'H'; p0: phy generic map (address => 7) port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk); i0: i2c_slave_model port map (iic_scl_main, iic_sda_main); iuerr : process begin wait for 5000 ns; if to_x01(bus_error(0)) = '0' then wait on bus_error; end if; assert (to_x01(bus_error(0)) = '0') report "*** IU in error mode, simulation halted ***" severity failure ; end process; data <= sram_flash_data(15 downto 0) & sram_flash_data(31 downto 16); address <= sram_flash_addr & '0'; test0 : grtestmod port map ( sys_rst_in, sys_clk, bus_error(0), sram_flash_addr(20 downto 1), data, iosn, flash_oen, sram_bw(0), open); sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns; -- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns; data <= buskeep(data), (others => 'H') after 250 ns; end ;

gpl-2.0

32f49552efef717ffe022503d6ae40a8

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/b73b442e1fb83bed/ip_design_nco_0_0_sim_netlist.vhdl

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 18:54:10 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_nco_0_0_sim_netlist.vhdl -- Design : ip_design_nco_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi is port ( s_axi_AXILiteS_RVALID : out STD_LOGIC; ap_rst_n_inv : out STD_LOGIC; s_axi_AXILiteS_ARREADY : out STD_LOGIC; O : out STD_LOGIC_VECTOR ( 3 downto 0 ); \temp_V_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \temp_V_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \temp_V_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); sel : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_AXILiteS_AWREADY : out STD_LOGIC; s_axi_AXILiteS_WREADY : out STD_LOGIC; s_axi_AXILiteS_BVALID : out STD_LOGIC; ap_clk : in STD_LOGIC; s_axi_AXILiteS_ARVALID : in STD_LOGIC; s_axi_AXILiteS_RREADY : in STD_LOGIC; s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 1 downto 0 ); \out\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); temp_V_reg : in STD_LOGIC_VECTOR ( 15 downto 0 ); ap_rst_n : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 ); s_axi_AXILiteS_AWVALID : in STD_LOGIC; s_axi_AXILiteS_WVALID : in STD_LOGIC; s_axi_AXILiteS_BREADY : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi is signal \^ap_rst_n_inv\ : STD_LOGIC; signal ar_hs : STD_LOGIC; signal int_sine_sample_V_ap_vld : STD_LOGIC; signal int_sine_sample_V_ap_vld_i_1_n_0 : STD_LOGIC; signal int_sine_sample_V_ap_vld_i_2_n_0 : STD_LOGIC; signal \int_step_size_V[0]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[10]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[11]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[12]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[13]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[14]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[15]_i_2_n_0\ : STD_LOGIC; signal \int_step_size_V[15]_i_3_n_0\ : STD_LOGIC; signal \int_step_size_V[1]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[2]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[3]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[4]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[5]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[6]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[7]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[8]_i_1_n_0\ : STD_LOGIC; signal \int_step_size_V[9]_i_1_n_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal q0_reg_0_i_10_n_0 : STD_LOGIC; signal q0_reg_0_i_11_n_0 : STD_LOGIC; signal q0_reg_0_i_12_n_0 : STD_LOGIC; signal q0_reg_0_i_12_n_1 : STD_LOGIC; signal q0_reg_0_i_12_n_2 : STD_LOGIC; signal q0_reg_0_i_12_n_3 : STD_LOGIC; signal q0_reg_0_i_13_n_0 : STD_LOGIC; signal q0_reg_0_i_14_n_0 : STD_LOGIC; signal q0_reg_0_i_15_n_0 : STD_LOGIC; signal q0_reg_0_i_16_n_0 : STD_LOGIC; signal q0_reg_0_i_17_n_0 : STD_LOGIC; signal q0_reg_0_i_18_n_0 : STD_LOGIC; signal q0_reg_0_i_19_n_0 : STD_LOGIC; signal q0_reg_0_i_1_n_1 : STD_LOGIC; signal q0_reg_0_i_1_n_2 : STD_LOGIC; signal q0_reg_0_i_1_n_3 : STD_LOGIC; signal q0_reg_0_i_20_n_0 : STD_LOGIC; signal q0_reg_0_i_2_n_0 : STD_LOGIC; signal q0_reg_0_i_2_n_1 : STD_LOGIC; signal q0_reg_0_i_2_n_2 : STD_LOGIC; signal q0_reg_0_i_2_n_3 : STD_LOGIC; signal q0_reg_0_i_3_n_0 : STD_LOGIC; signal q0_reg_0_i_3_n_1 : STD_LOGIC; signal q0_reg_0_i_3_n_2 : STD_LOGIC; signal q0_reg_0_i_3_n_3 : STD_LOGIC; signal q0_reg_0_i_4_n_0 : STD_LOGIC; signal q0_reg_0_i_5_n_0 : STD_LOGIC; signal q0_reg_0_i_6_n_0 : STD_LOGIC; signal q0_reg_0_i_7_n_0 : STD_LOGIC; signal q0_reg_0_i_8_n_0 : STD_LOGIC; signal q0_reg_0_i_9_n_0 : STD_LOGIC; signal \rdata[0]_i_1_n_0\ : STD_LOGIC; signal \rdata[0]_i_2_n_0\ : STD_LOGIC; signal \rdata[10]_i_1_n_0\ : STD_LOGIC; signal \rdata[11]_i_1_n_0\ : STD_LOGIC; signal \rdata[12]_i_1_n_0\ : STD_LOGIC; signal \rdata[13]_i_1_n_0\ : STD_LOGIC; signal \rdata[14]_i_1_n_0\ : STD_LOGIC; signal \rdata[15]_i_1_n_0\ : STD_LOGIC; signal \rdata[15]_i_3_n_0\ : STD_LOGIC; signal \rdata[1]_i_1_n_0\ : STD_LOGIC; signal \rdata[2]_i_1_n_0\ : STD_LOGIC; signal \rdata[3]_i_1_n_0\ : STD_LOGIC; signal \rdata[4]_i_1_n_0\ : STD_LOGIC; signal \rdata[5]_i_1_n_0\ : STD_LOGIC; signal \rdata[6]_i_1_n_0\ : STD_LOGIC; signal \rdata[7]_i_1_n_0\ : STD_LOGIC; signal \rdata[8]_i_1_n_0\ : STD_LOGIC; signal \rdata[9]_i_1_n_0\ : STD_LOGIC; signal \rstate[0]_i_2_n_0\ : STD_LOGIC; signal \^s_axi_axilites_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \^s_axi_axilites_rvalid\ : STD_LOGIC; signal step_size_V : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \temp_V[0]_i_2_n_0\ : STD_LOGIC; signal \temp_V[0]_i_3_n_0\ : STD_LOGIC; signal \temp_V[0]_i_4_n_0\ : STD_LOGIC; signal \temp_V[0]_i_5_n_0\ : STD_LOGIC; signal \temp_V[12]_i_2_n_0\ : STD_LOGIC; signal \temp_V[12]_i_3_n_0\ : STD_LOGIC; signal \temp_V[12]_i_4_n_0\ : STD_LOGIC; signal \temp_V[12]_i_5_n_0\ : STD_LOGIC; signal \temp_V[4]_i_2_n_0\ : STD_LOGIC; signal \temp_V[4]_i_3_n_0\ : STD_LOGIC; signal \temp_V[4]_i_4_n_0\ : STD_LOGIC; signal \temp_V[4]_i_5_n_0\ : STD_LOGIC; signal \temp_V[8]_i_2_n_0\ : STD_LOGIC; signal \temp_V[8]_i_3_n_0\ : STD_LOGIC; signal \temp_V[8]_i_4_n_0\ : STD_LOGIC; signal \temp_V[8]_i_5_n_0\ : STD_LOGIC; signal \temp_V_reg[0]_i_1_n_0\ : STD_LOGIC; signal \temp_V_reg[0]_i_1_n_1\ : STD_LOGIC; signal \temp_V_reg[0]_i_1_n_2\ : STD_LOGIC; signal \temp_V_reg[0]_i_1_n_3\ : STD_LOGIC; signal \temp_V_reg[12]_i_1_n_1\ : STD_LOGIC; signal \temp_V_reg[12]_i_1_n_2\ : STD_LOGIC; signal \temp_V_reg[12]_i_1_n_3\ : STD_LOGIC; signal \temp_V_reg[4]_i_1_n_0\ : STD_LOGIC; signal \temp_V_reg[4]_i_1_n_1\ : STD_LOGIC; signal \temp_V_reg[4]_i_1_n_2\ : STD_LOGIC; signal \temp_V_reg[4]_i_1_n_3\ : STD_LOGIC; signal \temp_V_reg[8]_i_1_n_0\ : STD_LOGIC; signal \temp_V_reg[8]_i_1_n_1\ : STD_LOGIC; signal \temp_V_reg[8]_i_1_n_2\ : STD_LOGIC; signal \temp_V_reg[8]_i_1_n_3\ : STD_LOGIC; signal waddr : STD_LOGIC; signal \waddr_reg_n_0_[0]\ : STD_LOGIC; signal \waddr_reg_n_0_[1]\ : STD_LOGIC; signal \waddr_reg_n_0_[2]\ : STD_LOGIC; signal \waddr_reg_n_0_[3]\ : STD_LOGIC; signal \waddr_reg_n_0_[4]\ : STD_LOGIC; signal wstate : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \wstate[0]_i_1_n_0\ : STD_LOGIC; signal \wstate[1]_i_1_n_0\ : STD_LOGIC; signal NLW_q0_reg_0_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 ); signal NLW_q0_reg_0_i_12_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_temp_V_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \int_step_size_V[0]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_step_size_V[10]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_step_size_V[11]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \int_step_size_V[12]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_step_size_V[13]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \int_step_size_V[14]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_step_size_V[15]_i_2\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \int_step_size_V[15]_i_3\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \int_step_size_V[1]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \int_step_size_V[2]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_step_size_V[3]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \int_step_size_V[4]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_step_size_V[5]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \int_step_size_V[6]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_step_size_V[7]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \int_step_size_V[8]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \int_step_size_V[9]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \rdata[10]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \rdata[11]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \rdata[12]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \rdata[13]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \rdata[14]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \rdata[15]_i_3\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \rdata[2]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \rdata[3]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \rdata[4]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \rdata[5]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \rdata[6]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \rdata[7]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \rdata[8]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \rdata[9]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \rstate[0]_i_2\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of s_axi_AXILiteS_ARREADY_INST_0 : label is "soft_lutpair10"; attribute SOFT_HLUTNM of s_axi_AXILiteS_AWREADY_INST_0 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of s_axi_AXILiteS_BVALID_INST_0 : label is "soft_lutpair18"; attribute SOFT_HLUTNM of s_axi_AXILiteS_WREADY_INST_0 : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \wstate[0]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \wstate[1]_i_1\ : label is "soft_lutpair1"; begin ap_rst_n_inv <= \^ap_rst_n_inv\; s_axi_AXILiteS_RDATA(15 downto 0) <= \^s_axi_axilites_rdata\(15 downto 0); s_axi_AXILiteS_RVALID <= \^s_axi_axilites_rvalid\; int_sine_sample_V_ap_vld_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFEFFFFFAAAAAAAA" ) port map ( I0 => Q(0), I1 => int_sine_sample_V_ap_vld_i_2_n_0, I2 => ar_hs, I3 => s_axi_AXILiteS_ARADDR(3), I4 => s_axi_AXILiteS_ARADDR(2), I5 => int_sine_sample_V_ap_vld, O => int_sine_sample_V_ap_vld_i_1_n_0 ); int_sine_sample_V_ap_vld_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"FB" ) port map ( I0 => s_axi_AXILiteS_ARADDR(1), I1 => s_axi_AXILiteS_ARADDR(4), I2 => s_axi_AXILiteS_ARADDR(0), O => int_sine_sample_V_ap_vld_i_2_n_0 ); int_sine_sample_V_ap_vld_reg: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => int_sine_sample_V_ap_vld_i_1_n_0, Q => int_sine_sample_V_ap_vld, R => \^ap_rst_n_inv\ ); \int_step_size_V[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(0), I1 => s_axi_AXILiteS_WSTRB(0), I2 => step_size_V(0), O => \int_step_size_V[0]_i_1_n_0\ ); \int_step_size_V[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(10), I1 => s_axi_AXILiteS_WSTRB(1), I2 => step_size_V(10), O => \int_step_size_V[10]_i_1_n_0\ ); \int_step_size_V[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(11), I1 => s_axi_AXILiteS_WSTRB(1), I2 => step_size_V(11), O => \int_step_size_V[11]_i_1_n_0\ ); \int_step_size_V[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(12), I1 => s_axi_AXILiteS_WSTRB(1), I2 => step_size_V(12), O => \int_step_size_V[12]_i_1_n_0\ ); \int_step_size_V[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(13), I1 => s_axi_AXILiteS_WSTRB(1), I2 => step_size_V(13), O => \int_step_size_V[13]_i_1_n_0\ ); \int_step_size_V[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(14), I1 => s_axi_AXILiteS_WSTRB(1), I2 => step_size_V(14), O => \int_step_size_V[14]_i_1_n_0\ ); \int_step_size_V[15]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \waddr_reg_n_0_[0]\, I1 => \waddr_reg_n_0_[2]\, I2 => \waddr_reg_n_0_[1]\, I3 => \int_step_size_V[15]_i_3_n_0\, O => p_0_in ); \int_step_size_V[15]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(15), I1 => s_axi_AXILiteS_WSTRB(1), I2 => step_size_V(15), O => \int_step_size_V[15]_i_2_n_0\ ); \int_step_size_V[15]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF7FFF" ) port map ( I0 => \waddr_reg_n_0_[4]\, I1 => \waddr_reg_n_0_[3]\, I2 => s_axi_AXILiteS_WVALID, I3 => wstate(0), I4 => wstate(1), O => \int_step_size_V[15]_i_3_n_0\ ); \int_step_size_V[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(1), I1 => s_axi_AXILiteS_WSTRB(0), I2 => step_size_V(1), O => \int_step_size_V[1]_i_1_n_0\ ); \int_step_size_V[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(2), I1 => s_axi_AXILiteS_WSTRB(0), I2 => step_size_V(2), O => \int_step_size_V[2]_i_1_n_0\ ); \int_step_size_V[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(3), I1 => s_axi_AXILiteS_WSTRB(0), I2 => step_size_V(3), O => \int_step_size_V[3]_i_1_n_0\ ); \int_step_size_V[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(4), I1 => s_axi_AXILiteS_WSTRB(0), I2 => step_size_V(4), O => \int_step_size_V[4]_i_1_n_0\ ); \int_step_size_V[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(5), I1 => s_axi_AXILiteS_WSTRB(0), I2 => step_size_V(5), O => \int_step_size_V[5]_i_1_n_0\ ); \int_step_size_V[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(6), I1 => s_axi_AXILiteS_WSTRB(0), I2 => step_size_V(6), O => \int_step_size_V[6]_i_1_n_0\ ); \int_step_size_V[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(7), I1 => s_axi_AXILiteS_WSTRB(0), I2 => step_size_V(7), O => \int_step_size_V[7]_i_1_n_0\ ); \int_step_size_V[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(8), I1 => s_axi_AXILiteS_WSTRB(1), I2 => step_size_V(8), O => \int_step_size_V[8]_i_1_n_0\ ); \int_step_size_V[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_AXILiteS_WDATA(9), I1 => s_axi_AXILiteS_WSTRB(1), I2 => step_size_V(9), O => \int_step_size_V[9]_i_1_n_0\ ); \int_step_size_V_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[0]_i_1_n_0\, Q => step_size_V(0), R => '0' ); \int_step_size_V_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[10]_i_1_n_0\, Q => step_size_V(10), R => '0' ); \int_step_size_V_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[11]_i_1_n_0\, Q => step_size_V(11), R => '0' ); \int_step_size_V_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[12]_i_1_n_0\, Q => step_size_V(12), R => '0' ); \int_step_size_V_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[13]_i_1_n_0\, Q => step_size_V(13), R => '0' ); \int_step_size_V_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[14]_i_1_n_0\, Q => step_size_V(14), R => '0' ); \int_step_size_V_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[15]_i_2_n_0\, Q => step_size_V(15), R => '0' ); \int_step_size_V_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[1]_i_1_n_0\, Q => step_size_V(1), R => '0' ); \int_step_size_V_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[2]_i_1_n_0\, Q => step_size_V(2), R => '0' ); \int_step_size_V_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[3]_i_1_n_0\, Q => step_size_V(3), R => '0' ); \int_step_size_V_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[4]_i_1_n_0\, Q => step_size_V(4), R => '0' ); \int_step_size_V_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[5]_i_1_n_0\, Q => step_size_V(5), R => '0' ); \int_step_size_V_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[6]_i_1_n_0\, Q => step_size_V(6), R => '0' ); \int_step_size_V_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[7]_i_1_n_0\, Q => step_size_V(7), R => '0' ); \int_step_size_V_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[8]_i_1_n_0\, Q => step_size_V(8), R => '0' ); \int_step_size_V_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => p_0_in, D => \int_step_size_V[9]_i_1_n_0\, Q => step_size_V(9), R => '0' ); q0_reg_0_i_1: unisim.vcomponents.CARRY4 port map ( CI => q0_reg_0_i_2_n_0, CO(3) => NLW_q0_reg_0_i_1_CO_UNCONNECTED(3), CO(2) => q0_reg_0_i_1_n_1, CO(1) => q0_reg_0_i_1_n_2, CO(0) => q0_reg_0_i_1_n_3, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => temp_V_reg(14 downto 12), O(3 downto 0) => sel(11 downto 8), S(3) => q0_reg_0_i_4_n_0, S(2) => q0_reg_0_i_5_n_0, S(1) => q0_reg_0_i_6_n_0, S(0) => q0_reg_0_i_7_n_0 ); q0_reg_0_i_10: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(9), I1 => step_size_V(9), O => q0_reg_0_i_10_n_0 ); q0_reg_0_i_11: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(8), I1 => step_size_V(8), O => q0_reg_0_i_11_n_0 ); q0_reg_0_i_12: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => q0_reg_0_i_12_n_0, CO(2) => q0_reg_0_i_12_n_1, CO(1) => q0_reg_0_i_12_n_2, CO(0) => q0_reg_0_i_12_n_3, CYINIT => '0', DI(3 downto 0) => temp_V_reg(3 downto 0), O(3 downto 0) => NLW_q0_reg_0_i_12_O_UNCONNECTED(3 downto 0), S(3) => q0_reg_0_i_17_n_0, S(2) => q0_reg_0_i_18_n_0, S(1) => q0_reg_0_i_19_n_0, S(0) => q0_reg_0_i_20_n_0 ); q0_reg_0_i_13: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(7), I1 => step_size_V(7), O => q0_reg_0_i_13_n_0 ); q0_reg_0_i_14: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(6), I1 => step_size_V(6), O => q0_reg_0_i_14_n_0 ); q0_reg_0_i_15: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(5), I1 => step_size_V(5), O => q0_reg_0_i_15_n_0 ); q0_reg_0_i_16: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(4), I1 => step_size_V(4), O => q0_reg_0_i_16_n_0 ); q0_reg_0_i_17: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(3), I1 => step_size_V(3), O => q0_reg_0_i_17_n_0 ); q0_reg_0_i_18: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(2), I1 => step_size_V(2), O => q0_reg_0_i_18_n_0 ); q0_reg_0_i_19: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(1), I1 => step_size_V(1), O => q0_reg_0_i_19_n_0 ); q0_reg_0_i_2: unisim.vcomponents.CARRY4 port map ( CI => q0_reg_0_i_3_n_0, CO(3) => q0_reg_0_i_2_n_0, CO(2) => q0_reg_0_i_2_n_1, CO(1) => q0_reg_0_i_2_n_2, CO(0) => q0_reg_0_i_2_n_3, CYINIT => '0', DI(3 downto 0) => temp_V_reg(11 downto 8), O(3 downto 0) => sel(7 downto 4), S(3) => q0_reg_0_i_8_n_0, S(2) => q0_reg_0_i_9_n_0, S(1) => q0_reg_0_i_10_n_0, S(0) => q0_reg_0_i_11_n_0 ); q0_reg_0_i_20: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(0), I1 => step_size_V(0), O => q0_reg_0_i_20_n_0 ); q0_reg_0_i_3: unisim.vcomponents.CARRY4 port map ( CI => q0_reg_0_i_12_n_0, CO(3) => q0_reg_0_i_3_n_0, CO(2) => q0_reg_0_i_3_n_1, CO(1) => q0_reg_0_i_3_n_2, CO(0) => q0_reg_0_i_3_n_3, CYINIT => '0', DI(3 downto 0) => temp_V_reg(7 downto 4), O(3 downto 0) => sel(3 downto 0), S(3) => q0_reg_0_i_13_n_0, S(2) => q0_reg_0_i_14_n_0, S(1) => q0_reg_0_i_15_n_0, S(0) => q0_reg_0_i_16_n_0 ); q0_reg_0_i_4: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(15), I1 => step_size_V(15), O => q0_reg_0_i_4_n_0 ); q0_reg_0_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(14), I1 => step_size_V(14), O => q0_reg_0_i_5_n_0 ); q0_reg_0_i_6: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(13), I1 => step_size_V(13), O => q0_reg_0_i_6_n_0 ); q0_reg_0_i_7: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(12), I1 => step_size_V(12), O => q0_reg_0_i_7_n_0 ); q0_reg_0_i_8: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(11), I1 => step_size_V(11), O => q0_reg_0_i_8_n_0 ); q0_reg_0_i_9: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(10), I1 => step_size_V(10), O => q0_reg_0_i_9_n_0 ); \rdata[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0020FFFF00200000" ) port map ( I0 => \rdata[0]_i_2_n_0\, I1 => s_axi_AXILiteS_ARADDR(0), I2 => s_axi_AXILiteS_ARADDR(4), I3 => s_axi_AXILiteS_ARADDR(1), I4 => ar_hs, I5 => \^s_axi_axilites_rdata\(0), O => \rdata[0]_i_1_n_0\ ); \rdata[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"30BB3088" ) port map ( I0 => step_size_V(0), I1 => s_axi_AXILiteS_ARADDR(3), I2 => int_sine_sample_V_ap_vld, I3 => s_axi_AXILiteS_ARADDR(2), I4 => \out\(0), O => \rdata[0]_i_2_n_0\ ); \rdata[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(10), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(10), O => \rdata[10]_i_1_n_0\ ); \rdata[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(11), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(11), O => \rdata[11]_i_1_n_0\ ); \rdata[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(12), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(12), O => \rdata[12]_i_1_n_0\ ); \rdata[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(13), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(13), O => \rdata[13]_i_1_n_0\ ); \rdata[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(14), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(14), O => \rdata[14]_i_1_n_0\ ); \rdata[15]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFB00000000" ) port map ( I0 => s_axi_AXILiteS_ARADDR(1), I1 => s_axi_AXILiteS_ARADDR(4), I2 => s_axi_AXILiteS_ARADDR(0), I3 => s_axi_AXILiteS_ARADDR(2), I4 => \^s_axi_axilites_rvalid\, I5 => s_axi_AXILiteS_ARVALID, O => \rdata[15]_i_1_n_0\ ); \rdata[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s_axi_AXILiteS_ARVALID, I1 => \^s_axi_axilites_rvalid\, O => ar_hs ); \rdata[15]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(15), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(15), O => \rdata[15]_i_3_n_0\ ); \rdata[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(1), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(1), O => \rdata[1]_i_1_n_0\ ); \rdata[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(2), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(2), O => \rdata[2]_i_1_n_0\ ); \rdata[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(3), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(3), O => \rdata[3]_i_1_n_0\ ); \rdata[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(4), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(4), O => \rdata[4]_i_1_n_0\ ); \rdata[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(5), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(5), O => \rdata[5]_i_1_n_0\ ); \rdata[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(6), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(6), O => \rdata[6]_i_1_n_0\ ); \rdata[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(7), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(7), O => \rdata[7]_i_1_n_0\ ); \rdata[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(8), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(8), O => \rdata[8]_i_1_n_0\ ); \rdata[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => step_size_V(9), I1 => s_axi_AXILiteS_ARADDR(3), I2 => \out\(9), O => \rdata[9]_i_1_n_0\ ); \rdata_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rdata[0]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(0), R => '0' ); \rdata_reg[10]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[10]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(10), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[11]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[11]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(11), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[12]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[12]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(12), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[13]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[13]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(13), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[14]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[14]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(14), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[15]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[15]_i_3_n_0\, Q => \^s_axi_axilites_rdata\(15), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[1]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(1), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[2]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(2), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[3]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(3), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[4]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(4), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[5]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[5]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(5), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[6]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[6]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(6), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[7]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[7]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(7), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[8]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[8]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(8), R => \rdata[15]_i_1_n_0\ ); \rdata_reg[9]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => ar_hs, D => \rdata[9]_i_1_n_0\, Q => \^s_axi_axilites_rdata\(9), R => \rdata[15]_i_1_n_0\ ); \rstate[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ap_rst_n, O => \^ap_rst_n_inv\ ); \rstate[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"3A" ) port map ( I0 => s_axi_AXILiteS_ARVALID, I1 => s_axi_AXILiteS_RREADY, I2 => \^s_axi_axilites_rvalid\, O => \rstate[0]_i_2_n_0\ ); \rstate_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \rstate[0]_i_2_n_0\, Q => \^s_axi_axilites_rvalid\, R => \^ap_rst_n_inv\ ); s_axi_AXILiteS_ARREADY_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^s_axi_axilites_rvalid\, O => s_axi_AXILiteS_ARREADY ); s_axi_AXILiteS_AWREADY_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => wstate(1), I1 => wstate(0), O => s_axi_AXILiteS_AWREADY ); s_axi_AXILiteS_BVALID_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => wstate(1), I1 => wstate(0), O => s_axi_AXILiteS_BVALID ); s_axi_AXILiteS_WREADY_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => wstate(0), I1 => wstate(1), O => s_axi_AXILiteS_WREADY ); \temp_V[0]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(3), I1 => temp_V_reg(3), O => \temp_V[0]_i_2_n_0\ ); \temp_V[0]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(2), I1 => temp_V_reg(2), O => \temp_V[0]_i_3_n_0\ ); \temp_V[0]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(1), I1 => temp_V_reg(1), O => \temp_V[0]_i_4_n_0\ ); \temp_V[0]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(0), I1 => temp_V_reg(0), O => \temp_V[0]_i_5_n_0\ ); \temp_V[12]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => temp_V_reg(15), I1 => step_size_V(15), O => \temp_V[12]_i_2_n_0\ ); \temp_V[12]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(14), I1 => temp_V_reg(14), O => \temp_V[12]_i_3_n_0\ ); \temp_V[12]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(13), I1 => temp_V_reg(13), O => \temp_V[12]_i_4_n_0\ ); \temp_V[12]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(12), I1 => temp_V_reg(12), O => \temp_V[12]_i_5_n_0\ ); \temp_V[4]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(7), I1 => temp_V_reg(7), O => \temp_V[4]_i_2_n_0\ ); \temp_V[4]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(6), I1 => temp_V_reg(6), O => \temp_V[4]_i_3_n_0\ ); \temp_V[4]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(5), I1 => temp_V_reg(5), O => \temp_V[4]_i_4_n_0\ ); \temp_V[4]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(4), I1 => temp_V_reg(4), O => \temp_V[4]_i_5_n_0\ ); \temp_V[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(11), I1 => temp_V_reg(11), O => \temp_V[8]_i_2_n_0\ ); \temp_V[8]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(10), I1 => temp_V_reg(10), O => \temp_V[8]_i_3_n_0\ ); \temp_V[8]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(9), I1 => temp_V_reg(9), O => \temp_V[8]_i_4_n_0\ ); \temp_V[8]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => step_size_V(8), I1 => temp_V_reg(8), O => \temp_V[8]_i_5_n_0\ ); \temp_V_reg[0]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \temp_V_reg[0]_i_1_n_0\, CO(2) => \temp_V_reg[0]_i_1_n_1\, CO(1) => \temp_V_reg[0]_i_1_n_2\, CO(0) => \temp_V_reg[0]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => step_size_V(3 downto 0), O(3 downto 0) => O(3 downto 0), S(3) => \temp_V[0]_i_2_n_0\, S(2) => \temp_V[0]_i_3_n_0\, S(1) => \temp_V[0]_i_4_n_0\, S(0) => \temp_V[0]_i_5_n_0\ ); \temp_V_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \temp_V_reg[8]_i_1_n_0\, CO(3) => \NLW_temp_V_reg[12]_i_1_CO_UNCONNECTED\(3), CO(2) => \temp_V_reg[12]_i_1_n_1\, CO(1) => \temp_V_reg[12]_i_1_n_2\, CO(0) => \temp_V_reg[12]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 0) => step_size_V(14 downto 12), O(3 downto 0) => \temp_V_reg[15]\(3 downto 0), S(3) => \temp_V[12]_i_2_n_0\, S(2) => \temp_V[12]_i_3_n_0\, S(1) => \temp_V[12]_i_4_n_0\, S(0) => \temp_V[12]_i_5_n_0\ ); \temp_V_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \temp_V_reg[0]_i_1_n_0\, CO(3) => \temp_V_reg[4]_i_1_n_0\, CO(2) => \temp_V_reg[4]_i_1_n_1\, CO(1) => \temp_V_reg[4]_i_1_n_2\, CO(0) => \temp_V_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => step_size_V(7 downto 4), O(3 downto 0) => \temp_V_reg[7]\(3 downto 0), S(3) => \temp_V[4]_i_2_n_0\, S(2) => \temp_V[4]_i_3_n_0\, S(1) => \temp_V[4]_i_4_n_0\, S(0) => \temp_V[4]_i_5_n_0\ ); \temp_V_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \temp_V_reg[4]_i_1_n_0\, CO(3) => \temp_V_reg[8]_i_1_n_0\, CO(2) => \temp_V_reg[8]_i_1_n_1\, CO(1) => \temp_V_reg[8]_i_1_n_2\, CO(0) => \temp_V_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => step_size_V(11 downto 8), O(3 downto 0) => \temp_V_reg[11]\(3 downto 0), S(3) => \temp_V[8]_i_2_n_0\, S(2) => \temp_V[8]_i_3_n_0\, S(1) => \temp_V[8]_i_4_n_0\, S(0) => \temp_V[8]_i_5_n_0\ ); \waddr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => s_axi_AXILiteS_AWVALID, I1 => wstate(0), I2 => wstate(1), O => waddr ); \waddr_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_AXILiteS_AWADDR(0), Q => \waddr_reg_n_0_[0]\, R => '0' ); \waddr_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_AXILiteS_AWADDR(1), Q => \waddr_reg_n_0_[1]\, R => '0' ); \waddr_reg[2]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_AXILiteS_AWADDR(2), Q => \waddr_reg_n_0_[2]\, R => '0' ); \waddr_reg[3]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_AXILiteS_AWADDR(3), Q => \waddr_reg_n_0_[3]\, R => '0' ); \waddr_reg[4]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => waddr, D => s_axi_AXILiteS_AWADDR(4), Q => \waddr_reg_n_0_[4]\, R => '0' ); \wstate[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0454" ) port map ( I0 => wstate(1), I1 => s_axi_AXILiteS_AWVALID, I2 => wstate(0), I3 => s_axi_AXILiteS_WVALID, O => \wstate[0]_i_1_n_0\ ); \wstate[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0838" ) port map ( I0 => s_axi_AXILiteS_WVALID, I1 => wstate(0), I2 => wstate(1), I3 => s_axi_AXILiteS_BREADY, O => \wstate[1]_i_1_n_0\ ); \wstate_reg[0]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \wstate[0]_i_1_n_0\, Q => wstate(0), R => \^ap_rst_n_inv\ ); \wstate_reg[1]\: unisim.vcomponents.FDRE port map ( C => ap_clk, CE => '1', D => \wstate[1]_i_1_n_0\, Q => wstate(1), R => \^ap_rst_n_inv\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom is port ( \out\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); ap_clk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); sel : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom is signal NLW_q0_reg_0_CASCADEOUTA_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_0_CASCADEOUTB_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_0_DBITERR_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_0_INJECTDBITERR_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_0_INJECTSBITERR_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_0_SBITERR_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_0_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 8 ); signal NLW_q0_reg_0_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_q0_reg_0_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 ); signal NLW_q0_reg_0_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_q0_reg_0_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_q0_reg_0_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); signal NLW_q0_reg_1_CASCADEOUTA_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_1_CASCADEOUTB_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_1_DBITERR_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_1_INJECTDBITERR_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_1_INJECTSBITERR_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_1_SBITERR_UNCONNECTED : STD_LOGIC; signal NLW_q0_reg_1_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 7 ); signal NLW_q0_reg_1_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_q0_reg_1_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_q0_reg_1_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_q0_reg_1_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_q0_reg_1_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of q0_reg_0 : label is "p1_d8"; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of q0_reg_0 : label is ""; attribute RTL_RAM_BITS : integer; attribute RTL_RAM_BITS of q0_reg_0 : label is 65536; attribute RTL_RAM_NAME : string; attribute RTL_RAM_NAME of q0_reg_0 : label is "sine_lut_V_U/nco_sine_lut_V_rom_U/q0"; attribute bram_addr_begin : integer; attribute bram_addr_begin of q0_reg_0 : label is 0; attribute bram_addr_end : integer; attribute bram_addr_end of q0_reg_0 : label is 4095; attribute bram_slice_begin : integer; attribute bram_slice_begin of q0_reg_0 : label is 0; attribute bram_slice_end : integer; attribute bram_slice_end of q0_reg_0 : label is 8; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of q0_reg_1 : label is "p0_d7"; attribute METHODOLOGY_DRC_VIOS of q0_reg_1 : label is ""; attribute RTL_RAM_BITS of q0_reg_1 : label is 65536; attribute RTL_RAM_NAME of q0_reg_1 : label is "sine_lut_V_U/nco_sine_lut_V_rom_U/q0"; attribute bram_addr_begin of q0_reg_1 : label is 0; attribute bram_addr_end of q0_reg_1 : label is 4095; attribute bram_slice_begin of q0_reg_1 : label is 9; attribute bram_slice_end of q0_reg_1 : label is 15; begin q0_reg_0: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"07FF001FFC00FFE003FF001FF800FFC007FE007FF003FF003FF801FF801FF800", INITP_01 => X"E0007FFE0007FFC001FFF0007FFC003FFC003FFC003FFC007FF800FFF001FFC0", INITP_02 => X"E000000FFFFFE000007FFFF800007FFFE00007FFFC0001FFFE0001FFFC0007FF", INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000001FFFFFFFFF00000001FFFFFF", INITP_04 => X"FFFFFF00000001FFFFFFFFF000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFE", INITP_05 => X"FFC0007FFF0000FFFF00007FFFC0000FFFFC00003FFFFC00000FFFFFE000000F", INITP_06 => X"07FF001FFE003FFC007FF8007FF8007FF8007FFC001FFF0007FFC000FFFC000F", INITP_07 => X"003FF003FF003FF801FF801FFC00FFC007FE003FF001FF800FFE007FF001FFC0", INITP_08 => X"F800FFE003FF001FFC00FFE007FF003FF801FF800FFC00FFC007FE007FE007FE", INITP_09 => X"1FFF8001FFF8003FFE000FFF8003FFC003FFC003FFC003FF8007FF000FFE003F", INITP_0A => X"1FFFFFF000001FFFFF800007FFFF80001FFFF80003FFFE0001FFFE0003FFF800", INITP_0B => X"00000000000000000000000000001FFFFFFFFFFFE000000000FFFFFFFE000000", INITP_0C => X"000000FFFFFFFE000000000FFFFFFFFFFFF00000000000000000000000000000", INITP_0D => X"003FFF8000FFFF0000FFFF80003FFFF00003FFFFC00003FFFFF000001FFFFFF0", INITP_0E => X"F800FFE001FFC003FF8007FF8007FF8007FF8003FFE000FFF8003FFF0003FFF0", INITP_0F => X"FFC00FFC00FFC007FE007FE003FF003FF801FFC00FFE007FF001FF800FFE003F", INIT_00 => X"0AF1D8BFA68D745B41280FF6DDC4AB92785F462D14FBE2C9AF967D644B321900", INIT_01 => X"2C13FAE1C8AF967D644B321900E7CEB59C836A51371E05ECD3BAA1886F563D23", INIT_02 => X"4B321900E7CEB59C846B52392007EED5BCA38A71583F260DF4DBC2A990775E45", INIT_03 => X"634B321901E8CFB69E856C543B2209F1D8BFA68D755C432A11F9E0C7AE957C64", INIT_04 => X"745C432B12FAE2C9B19880674F361E05EDD4BCA38B7259412810F7DEC6AD957C", INIT_05 => X"7B634B331B03EBD3BBA28A725A422A11F9E1C9B09880684F371F06EED6BDA58C", INIT_06 => X"776048301901E9D1BAA28A725A432B13FBE3CBB39B836C543C240CF4DCC4AC94", INIT_07 => X"664F382009F2DAC3AC947D664E371F08F1D9C2AA937B644C341D05EED6BEA78F", INIT_08 => X"462F1802EBD4BDA68F79624B341D06EFD8C1AA937C654E372008F1DAC3AC957D", INIT_09 => X"15FEE8D2BCA68F79634C362009F3DCC6AF99836C553F2812FBE5CEB7A18A735D", INIT_0A => X"D1BBA6907B654F39240EF8E2CDB7A18B755F49341E08F2DCC6B099836D57412B", INIT_0B => X"79644F3A2510FBE6D1BCA7927D67523D2812FDE8D2BDA8927D68523D2712FCE7", INIT_0C => X"0BF7E3CFBAA6927D6954402C1703EEDAC5B09C87735E4934200BF6E1CDB8A38E", INIT_0D => X"86725F4B382411FDEAD6C2AF9B87735F4C382410FCE8D4C0AC9884705C48341F", INIT_0E => X"E8D5C2B09D8A7765523F2C1906F3E0CDBAA794816E5A4734210EFAE7D4C0AD99", INIT_0F => X"2F1D0BF9E8D6C4B2A08E7C6A574533210FFCEAD8C6B3A18E7C6A574532200DFA", INIT_10 => X"5A4938281605F4E3D2C1B09F8D7C6B5A4837251403F1E0CEBCAB998876645241", INIT_11 => X"69594938281808F8E8D8C7B7A796867665554434231302F1E1D0BFAF9E8D7C6B", INIT_12 => X"58493A2B1C0DFEEEDFD0C1B1A293837464554536261607F7E7D8C8B8A8988879", INIT_13 => X"281A0CFEF0E2D4C6B7A99B8C7E706153443627190AFBEDDECFC1B2A394857667", INIT_14 => X"D8CBBEB1A496897C6F6254473A2C1F1204F7E9DCCEC0B3A597897C6E60524436", INIT_15 => X"65594D4135291D1105F9EDE0D4C8BBAFA3968A7D7164574B3E3125180BFEF1E5", INIT_16 => X"D0C5BAAFA4998E83786D62574C41352A1F1308FDF1E6DACFC3B7ACA094897D71", INIT_17 => X"170D03FAF0E6DCD2C8BEB4AAA0968C82786D63594F443A2F251A1005FBF0E5DA", INIT_18 => X"39312820170E06FDF4EBE2DAD1C8BFB6ADA39A91887F756C635950473D342A20", INIT_19 => X"372F282119120A02FBF3ECE4DCD4CCC5BDB5ADA59D958C847C746C635B534A42", INIT_1A => X"0E0802FCF5EFE9E2DCD6CFC9C2BBB5AEA7A19A938C857E777069625B544D453E", INIT_1B => X"C0BBB6B1ACA7A19C97928C87827C77716C66615B55504A443E38332D27211B14", INIT_1C => X"4A47433F3B37332F2B27231F1B17130E0A0601FDF8F4EFEBE6E1DDD8D3CECAC5", INIT_1D => X"AEACA9A6A4A19E9C999693908D8A8784817E7B7874716E6A6764605D5955524E", INIT_1E => X"EBE9E8E7E5E4E2E1DFDEDCDAD8D7D5D3D1CFCDCBC9C7C5C3C1BFBCBAB8B5B3B1", INIT_1F => X"FFFFFFFFFFFFFFFEFEFEFDFDFCFCFBFBFAF9F9F8F7F6F5F4F3F2F1F0EFEEEDEC", INIT_20 => X"EDEEEFF0F1F2F3F4F5F6F7F8F9F9FAFBFBFCFCFDFDFEFEFEFFFFFFFFFFFFFF00", INIT_21 => X"B3B5B8BABCBFC1C3C5C7C9CBCDCFD1D3D5D7D8DADCDEDFE1E2E4E5E7E8E9EBEC", INIT_22 => X"5255595D6064676A6E7174787B7E8184878A8D909396999C9EA1A4A6A9ACAEB1", INIT_23 => X"CACED3D8DDE1E6EBEFF4F8FD01060A0E13171B1F23272B2F33373B3F43474A4E", INIT_24 => X"1B21272D33383E444A50555B61666C71777C82878C92979CA1A7ACB1B6BBC0C5", INIT_25 => X"454D545B626970777E858C939AA1A7AEB5BBC2C9CFD6DCE2E9EFF5FC02080E14", INIT_26 => X"4A535B636C747C848C959DA5ADB5BDC5CCD4DCE4ECF3FB020A121921282F373E", INIT_27 => X"2A343D475059636C757F88919AA3ADB6BFC8D1DAE2EBF4FD060E172028313942", INIT_28 => X"E5F0FB05101A252F3A444F59636D78828C96A0AAB4BEC8D2DCE6F0FA030D1720", INIT_29 => X"7D8994A0ACB7C3CFDAE6F1FD08131F2A35414C57626D78838E99A4AFBAC5D0DA", INIT_2A => X"F1FE0B1825313E4B5764717D8A96A3AFBBC8D4E0EDF905111D2935414D596571", INIT_2B => X"4452606E7C8997A5B3C0CEDCE9F704121F2C3A4754626F7C8996A4B1BECBD8E5", INIT_2C => X"768594A3B2C1CFDEEDFB0A192736445361707E8C9BA9B7C6D4E2F0FE0C1A2836", INIT_2D => X"8898A8B8C8D8E7F707162636455564748393A2B1C1D0DFEEFE0D1C2B3A495867", INIT_2E => X"7C8D9EAFBFD0E1F102132334445565768696A7B7C7D8E8F80818283849596979", INIT_2F => X"5264768899ABBCCEE0F103142537485A6B7C8D9FB0C1D2E3F405162838495A6B", INIT_30 => X"0D203245576A7C8EA1B3C6D8EAFC0F213345576A7C8EA0B2C4D6E8F90B1D2F41", INIT_31 => X"ADC0D4E7FA0E2134475A6E8194A7BACDE0F306192C3F5265778A9DB0C2D5E8FA", INIT_32 => X"34485C708498ACC0D4E8FC1024384C5F73879BAFC2D6EAFD1124384B5F728699", INIT_33 => X"A3B8CDE1F60B2034495E73879CB0C5DAEE03172C4054697D92A6BACFE3F70B1F", INIT_34 => X"FC12273D52687D92A8BDD2E8FD12283D52677D92A7BCD1E6FB10253A4F64798E", INIT_35 => X"41576D8399B0C6DCF2081E34495F758BA1B7CDE2F80E24394F657B90A6BBD1E7", INIT_36 => X"738AA1B7CEE5FB12283F556C8399AFC6DCF30920364C63798FA6BCD2E8FE152B", INIT_37 => X"95ACC3DAF10820374E657C93AAC1D8EF061D344B62798FA6BDD4EB02182F465D", INIT_38 => X"A7BED6EE051D344C647B93AAC2D9F1081F374E667D94ACC3DAF20920384F667D", INIT_39 => X"ACC4DCF40C243C546C839BB3CBE3FB132B435A728AA2BAD1E90119304860778F", INIT_3A => X"A5BDD6EE061F374F688098B0C9E1F9112A425A728AA2BBD3EB031B334B637B94", INIT_3B => X"95ADC6DEF710284159728BA3BCD4ED051E364F678098B1C9E2FA122B435C748C", INIT_3C => X"7C95AEC7E0F9112A435C758DA6BFD8F109223B546C859EB6CFE80119324B637C", INIT_3D => X"5E7790A9C2DBF40D263F58718AA3BCD5EE072039526B849CB5CEE70019324B64", INIT_3E => X"3D566F88A1BAD3EC051E37516A839CB5CEE70019324B647D96AFC8E1FA132C45", INIT_3F => X"19324B647D96AFC9E2FB142D465F7892ABC4DDF60F28415B748DA6BFD8F10A23", INIT_40 => X"F50E274059728BA4BED7F009223B546D87A0B9D2EB041D365069829BB4CDE600", INIT_41 => X"D3EC051E375069829BB4CDE6FF18314A637C95AEC8E1FA132C455E7790A9C2DC", INIT_42 => X"B4CDE6FF18314A637B94ADC6DFF8112A435C758EA7C0D9F20B243D566F88A1BA", INIT_43 => X"9CB4CDE6FE173049617A93ABC4DDF60E274059728AA3BCD5EE061F38516A839B", INIT_44 => X"8BA3BCD4ED051D364E677F98B0C9E1FA122B435C748DA6BED7EF082139526A83", INIT_45 => X"849CB4CCE4FC142C445D758DA5BDD5EE061E364F677F97B0C8E0F91129425A73", INIT_46 => X"889FB7CFE6FE162E455D758DA5BCD4EC041C344C647C93ABC3DBF30B233B536B", INIT_47 => X"99B0C7DFF60D253C536B8299B1C8E0F70E263D556C849BB3CBE2FA1129415870", INIT_48 => X"B9D0E7FD142B425970869DB4CBE2F910273E556C839AB1C8DFF70E253C536A82", INIT_49 => X"EA01172D435970869CB3C9DFF60C233950667C93AAC0D7ED041A31485E758CA2", INIT_4A => X"2E44596F849AB0C6DBF1071D32485E748AA0B6CBE1F70D23394F667C92A8BED4", INIT_4B => X"869BB0C5DAEF04192E43586D8298ADC2D7ED02172D42576D8297ADC2D8ED0318", INIT_4C => X"F4081C3045596D8296ABBFD3E8FC11253A4F63788CA1B6CBDFF4091E32475C71", INIT_4D => X"798DA0B4C7DBEE0215293D5064788CA0B3C7DBEF03172B3F53677B8FA3B7CBE0", INIT_4E => X"172A3D4F6275889AADC0D3E6F90C1F3245586B7E91A5B8CBDEF105182B3F5266", INIT_4F => X"D0E2F40617293B4D5F718395A8BACCDEF0031527394C5E718395A8BACDDFF205", INIT_50 => X"A5B6C7D7E9FA0B1C2D3E4F60728394A5B7C8DAEBFC0E1F3143546677899BADBE", INIT_51 => X"96A6B6C7D7E7F70717273848586979899AAABBCBDCECFD0E1E2F405061728394", INIT_52 => X"A7B6C5D4E3F20111202F3E4E5D6C7C8B9BAABAC9D9E9F8081827374757677786", INIT_53 => X"D7E5F3010F1D2B3948566473818F9EACBBC9D8E6F5041221303E4D5C6B7A8998", INIT_54 => X"2734414E5B697683909DABB8C5D3E0EDFB081623313F4C5A687683919FADBBC9", INIT_55 => X"9AA6B2BECAD6E2EEFA06121F2B3744505C6975828E9BA8B4C1CEDAE7F4010E1A", INIT_56 => X"2F3A45505B66717C87929DA8B3BECAD5E0ECF7020E1925303C48535F6B76828E", INIT_57 => X"E8F2FC050F19232D37414B555F69737D87929CA6B0BBC5D0DAE5EFFA040F1A25", INIT_58 => X"C6CED7DFE8F1F9020B141D252E374049525C656E77808A939CA6AFB8C2CBD5DF", INIT_59 => X"C8D0D7DEE6EDF5FD040C131B232B333A424A525A626A737B838B939CA4ACB5BD", INIT_5A => X"F1F7FD030A10161D232930363D444A51585E656C737A81888F969DA4ABB2BAC1", INIT_5B => X"3F44494E53585E63686D73787D83888E93999EA4AAAFB5BBC1C7CCD2D8DEE4EB", INIT_5C => X"B5B8BCC0C4C8CCD0D4D8DCE0E4E8ECF1F5F9FE02070B1014191E22272C31353A", INIT_5D => X"515356595B5E616366696C6F7275787B7E8184878B8E9195989B9FA2A6AAADB1", INIT_5E => X"141617181A1B1D1E2021232527282A2C2E30323436383A3C3E404345474A4C4E", INIT_5F => X"000000000000000101010202030304040506060708090A0B0C0D0E0F10111213", INIT_60 => X"1211100F0E0D0C0B0A0908070606050404030302020101010000000000000000", INIT_61 => X"4C4A474543403E3C3A38363432302E2C2A2827252321201E1D1B1A1817161413", INIT_62 => X"ADAAA6A29F9B9895918E8B8784817E7B7875726F6C696663615E5B595653514E", INIT_63 => X"35312C27221E1914100B0702FEF9F5F1ECE8E4E0DCD8D4D0CCC8C4C0BCB8B5B1", INIT_64 => X"E4DED8D2CCC7C1BBB5AFAAA49E99938E88837D78736D68635E58534E49443F3A", INIT_65 => X"BAB2ABA49D968F88817A736C655E58514A443D363029231D16100A03FDF7F1EB", INIT_66 => X"B5ACA49C938B837B736A625A524A423A332B231B130C04FDF5EDE6DED7D0C8C1", INIT_67 => X"D5CBC2B8AFA69C938A80776E655C524940372E251D140B02F9F1E8DFD7CEC6BD", INIT_68 => X"1A0F04FAEFE5DAD0C5BBB0A69C92877D73695F554B41372D23190F05FCF2E8DF", INIT_69 => X"82766B5F53483C3025190E02F7ECE0D5CABEB3A89D92877C71665B50453A2F25", INIT_6A => X"0E01F4E7DACEC1B4A89B8E8275695C5044372B1F1206FAEEE2D6CABEB2A69A8E", INIT_6B => X"BBAD9F918376685A4C3F31231608FBEDE0D3C5B8AB9D908376695B4E4134271A", INIT_6C => X"897A6B5C4D3E30211204F5E6D8C9BBAC9E8F8173645648392B1D0F01F3E5D7C9", INIT_6D => X"7767574737271808F8E9D9C9BAAA9B8B7C6C5D4E3E2F201101F2E3D4C5B6A798", INIT_6E => X"83726150402F1E0EFDECDCCBBBAA9A897969584838271707F7E7D7C7B6A69686", INIT_6F => X"AD9B8977665443311F0EFCEBDAC8B7A5948372604F3E2D1C0BFAE9D7C7B6A594", INIT_70 => X"F2DFCDBAA89583715E4C39271503F0DECCBAA89583715F4D3B291706F4E2D0BE", INIT_71 => X"523F2B1805F1DECBB8A5917E6B5845321F0CF9E6D3C0AD9A8875624F3D2A1705", INIT_72 => X"CBB7A38F7B67533F2B1703EFDBC7B3A08C7864503D291502EEDBC7B4A08D7966", INIT_73 => X"5C47321E09F4DFCBB6A18C78634F3A2511FCE8D3BFAB96826D5945301C08F4E0", INIT_74 => X"03EDD8C2AD97826D57422D1702EDD7C2AD98826D58432E1904EFDAC5B09B8671", INIT_75 => X"BEA8927C664F39230DF7E1CBB6A08A745E48321D07F1DBC6B09A846F59442E18", INIT_76 => X"8C755E48311A04EDD7C0AA937C665039230CF6DFC9B39C867059432D1701EAD4", INIT_77 => X"6A533C250EF7DFC8B19A836C553E2710F9E2CBB49D867059422B14FDE7D0B9A2", INIT_78 => X"58412911FAE2CBB39B846C553D260EF7E0C8B199826B533C250DF6DFC7B09982", INIT_79 => X"533B230BF3DBC3AB937C644C341C04ECD4BCA58D755D452E16FEE6CFB79F8870", INIT_7A => X"5A422911F9E0C8B0977F674F361E06EED5BDA58D755D442C14FCE4CCB49C846B", INIT_7B => X"6A52392108EFD7BEA68D745C432B12FAE1C9B0987F674E361D05EDD4BCA38B73", INIT_7C => X"836A51381F06EED5BCA38A725940270EF6DDC4AB937A61493017FEE6CDB49C83", INIT_7D => X"A1886F563D240BF2D9C0A78E755C432A11F8DFC6AD947B634A3118FFE6CDB49B", INIT_7E => X"C2A990775E452C13FAE1C8AE957C634A3118FFE6CDB49B826950371E05ECD3BA", INIT_7F => X"E6CDB49B826950361D04EBD2B9A0876D543B2209F0D7BEA48B725940270EF5DC", INIT_A => X"000000000", INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => sel(11 downto 0), ADDRARDADDR(2 downto 0) => B"000", ADDRBWRADDR(15 downto 0) => B"1111111111111111", CASCADEINA => '1', CASCADEINB => '0', CASCADEOUTA => NLW_q0_reg_0_CASCADEOUTA_UNCONNECTED, CASCADEOUTB => NLW_q0_reg_0_CASCADEOUTB_UNCONNECTED, CLKARDCLK => ap_clk, CLKBWRCLK => '0', DBITERR => NLW_q0_reg_0_DBITERR_UNCONNECTED, DIADI(31 downto 0) => B"00000000000000000000000011111111", DIBDI(31 downto 0) => B"11111111111111111111111111111111", DIPADIP(3 downto 0) => B"0001", DIPBDIP(3 downto 0) => B"1111", DOADO(31 downto 8) => NLW_q0_reg_0_DOADO_UNCONNECTED(31 downto 8), DOADO(7 downto 0) => \out\(7 downto 0), DOBDO(31 downto 0) => NLW_q0_reg_0_DOBDO_UNCONNECTED(31 downto 0), DOPADOP(3 downto 1) => NLW_q0_reg_0_DOPADOP_UNCONNECTED(3 downto 1), DOPADOP(0) => \out\(8), DOPBDOP(3 downto 0) => NLW_q0_reg_0_DOPBDOP_UNCONNECTED(3 downto 0), ECCPARITY(7 downto 0) => NLW_q0_reg_0_ECCPARITY_UNCONNECTED(7 downto 0), ENARDEN => Q(0), ENBWREN => '0', INJECTDBITERR => NLW_q0_reg_0_INJECTDBITERR_UNCONNECTED, INJECTSBITERR => NLW_q0_reg_0_INJECTSBITERR_UNCONNECTED, RDADDRECC(8 downto 0) => NLW_q0_reg_0_RDADDRECC_UNCONNECTED(8 downto 0), REGCEAREGCE => Q(1), REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => SR(0), RSTREGB => '0', SBITERR => NLW_q0_reg_0_SBITERR_UNCONNECTED, WEA(3 downto 0) => B"0000", WEBWE(7 downto 0) => B"00000000" ); q0_reg_1: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0101010101010101010101000000000000000000000000000000000000000000", INIT_01 => X"0303020202020202020202020202020202020202020202010101010101010101", INIT_02 => X"0404040404040404040404040404030303030303030303030303030303030303", INIT_03 => X"0606060606050505050505050505050505050505050505050504040404040404", INIT_04 => X"0707070707070707070707070707070706060606060606060606060606060606", INIT_05 => X"0909090909090808080808080808080808080808080808080808080707070707", INIT_06 => X"0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A09090909090909090909090909090909", INIT_07 => X"0C0C0C0C0C0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0A0A0A0A0A", INIT_08 => X"0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C", INIT_09 => X"0F0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0D0D0D0D0D0D0D0D", INIT_0A => X"101010101010101010100F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F", INIT_0B => X"1111111111111111111111111111111111111010101010101010101010101010", INIT_0C => X"1312121212121212121212121212121212121212121212121212111111111111", INIT_0D => X"1414141414141413131313131313131313131313131313131313131313131313", INIT_0E => X"1515151515151515151515151514141414141414141414141414141414141414", INIT_0F => X"1616161616161616161616161616161616151515151515151515151515151515", INIT_10 => X"1717171717171717171717171717171717171717171616161616161616161616", INIT_11 => X"1818181818181818181818181818181818181818181818171717171717171717", INIT_12 => X"1919191919191919191919191919191919191919191919181818181818181818", INIT_13 => X"1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1919191919191919191919", INIT_14 => X"1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A", INIT_15 => X"1C1C1C1C1C1C1C1C1C1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B", INIT_16 => X"1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C", INIT_17 => X"1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1C1C1C1C", INIT_18 => X"1E1E1E1E1E1E1E1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D", INIT_19 => X"1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E", INIT_1A => X"1F1F1F1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E", INIT_1B => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F", INIT_1C => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F", INIT_1D => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F", INIT_1E => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F", INIT_1F => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F", INIT_20 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F20", INIT_21 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F", INIT_22 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F", INIT_23 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F", INIT_24 => X"1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F1F", INIT_25 => X"1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1F1F1F1F", INIT_26 => X"1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E1E", INIT_27 => X"1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1E1E1E1E1E1E1E1E", INIT_28 => X"1C1C1C1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D", INIT_29 => X"1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C1C", INIT_2A => X"1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1C1C1C1C1C1C1C1C1C1C", INIT_2B => X"1A1A1A1A1A1A1A1A1A1A1A1A1A1A1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B", INIT_2C => X"191919191919191919191A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A1A", INIT_2D => X"1818181818181818191919191919191919191919191919191919191919191919", INIT_2E => X"1717171717171717181818181818181818181818181818181818181818181818", INIT_2F => X"1616161616161616161617171717171717171717171717171717171717171717", INIT_30 => X"1515151515151515151515151515161616161616161616161616161616161616", INIT_31 => X"1414141414141414141414141414141414141515151515151515151515151515", INIT_32 => X"1313131313131313131313131313131313131313131313131414141414141414", INIT_33 => X"1111111111121212121212121212121212121212121212121212121212121313", INIT_34 => X"1010101010101010101010101011111111111111111111111111111111111111", INIT_35 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1010101010101010101010", INIT_36 => X"0D0D0D0D0D0D0D0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0F0F", INIT_37 => X"0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0C0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D", INIT_38 => X"0A0A0A0A0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0B0C0C0C0C0C0C", INIT_39 => X"0909090909090909090909090909090A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A", INIT_3A => X"0707070708080808080808080808080808080808080808080809090909090909", INIT_3B => X"0606060606060606060606060606060707070707070707070707070707070707", INIT_3C => X"0404040404040505050505050505050505050505050505050505060606060606", INIT_3D => X"0303030303030303030303030303030303040404040404040404040404040404", INIT_3E => X"0101010101010101020202020202020202020202020202020202020202030303", INIT_3F => X"0000000000000000000000000000000000000000010101010101010101010101", INIT_40 => X"7E7E7E7E7E7E7E7E7E7E7E7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F00", INIT_41 => X"7C7C7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7E7E7E7E7E7E7E7E7E", INIT_42 => X"7B7B7B7B7B7B7B7B7B7B7B7B7B7B7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C", INIT_43 => X"79797979797A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7B7B7B7B7B7B7B", INIT_44 => X"7878787878787878787878787878787879797979797979797979797979797979", INIT_45 => X"7676767676767777777777777777777777777777777777777777777878787878", INIT_46 => X"7575757575757575757575757575757576767676767676767676767676767676", INIT_47 => X"7373737373747474747474747474747474747474747474747474747575757575", INIT_48 => X"7272727272727272727272727272727373737373737373737373737373737373", INIT_49 => X"7071717171717171717171717171717171717171717171717272727272727272", INIT_4A => X"6F6F6F6F6F6F6F6F6F6F70707070707070707070707070707070707070707070", INIT_4B => X"6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6F6F6F6F6F6F6F6F6F6F6F6F6F6F", INIT_4C => X"6C6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6E6E6E6E6E6E", INIT_4D => X"6B6B6B6B6B6B6B6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C", INIT_4E => X"6A6A6A6A6A6A6A6A6A6A6A6A6A6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B", INIT_4F => X"69696969696969696969696969696969696A6A6A6A6A6A6A6A6A6A6A6A6A6A6A", INIT_50 => X"6868686868686868686868686868686868686868686969696969696969696969", INIT_51 => X"6767676767676767676767676767676767676767676767686868686868686868", INIT_52 => X"6666666666666666666666666666666666666666666666676767676767676767", INIT_53 => X"6565656565656565656565656565656565656565656666666666666666666666", INIT_54 => X"6464646464646464646464646464646464656565656565656565656565656565", INIT_55 => X"6363636363636363636464646464646464646464646464646464646464646464", INIT_56 => X"6363636363636363636363636363636363636363636363636363636363636363", INIT_57 => X"6262626262626262626262626262626262626262626262626262626263636363", INIT_58 => X"6161616161616162626262626262626262626262626262626262626262626262", INIT_59 => X"6161616161616161616161616161616161616161616161616161616161616161", INIT_5A => X"6060606161616161616161616161616161616161616161616161616161616161", INIT_5B => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_5C => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_5D => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_5E => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_5F => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_60 => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_61 => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_62 => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_63 => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_64 => X"6060606060606060606060606060606060606060606060606060606060606060", INIT_65 => X"6161616161616161616161616161616161616161616161616161616160606060", INIT_66 => X"6161616161616161616161616161616161616161616161616161616161616161", INIT_67 => X"6262626262626262626262626262626262626262626262626161616161616161", INIT_68 => X"6363636262626262626262626262626262626262626262626262626262626262", INIT_69 => X"6363636363636363636363636363636363636363636363636363636363636363", INIT_6A => X"6464646464646464646464646464646464646464646463636363636363636363", INIT_6B => X"6565656565656565656565656565646464646464646464646464646464646464", INIT_6C => X"6666666666666666666665656565656565656565656565656565656565656565", INIT_6D => X"6767676767676767666666666666666666666666666666666666666666666666", INIT_6E => X"6868686868686868676767676767676767676767676767676767676767676767", INIT_6F => X"6969696969696969696968686868686868686868686868686868686868686868", INIT_70 => X"6A6A6A6A6A6A6A6A6A6A6A6A6A6A696969696969696969696969696969696969", INIT_71 => X"6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6B6A6A6A6A6A6A6A6A6A6A6A6A6A6A", INIT_72 => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6B6B6B6B6B6B6B6B", INIT_73 => X"6E6E6E6E6E6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6D6C6C", INIT_74 => X"6F6F6F6F6F6F6F6F6F6F6F6F6F6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E6E", INIT_75 => X"7070707070707070707070707070707070707070706F6F6F6F6F6F6F6F6F6F6F", INIT_76 => X"7272727272727271717171717171717171717171717171717171717171717070", INIT_77 => X"7373737373737373737373737373737372727272727272727272727272727272", INIT_78 => X"7575757574747474747474747474747474747474747474747474737373737373", INIT_79 => X"7676767676767676767676767676767575757575757575757575757575757575", INIT_7A => X"7878787877777777777777777777777777777777777777777776767676767676", INIT_7B => X"7979797979797979797979797979797878787878787878787878787878787878", INIT_7C => X"7B7B7B7B7B7B7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A7A797979797979", INIT_7D => X"7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7C7B7B7B7B7B7B7B7B7B7B7B7B7B7B7B", INIT_7E => X"7E7E7E7E7E7E7E7E7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7D7C7C7C", INIT_7F => X"7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7F7E7E7E7E7E7E7E7E7E7E7E7E", INIT_A => X"000000000", INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 9, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => sel(11 downto 0), ADDRARDADDR(2 downto 0) => B"000", ADDRBWRADDR(15 downto 0) => B"1111111111111111", CASCADEINA => '1', CASCADEINB => '0', CASCADEOUTA => NLW_q0_reg_1_CASCADEOUTA_UNCONNECTED, CASCADEOUTB => NLW_q0_reg_1_CASCADEOUTB_UNCONNECTED, CLKARDCLK => ap_clk, CLKBWRCLK => '0', DBITERR => NLW_q0_reg_1_DBITERR_UNCONNECTED, DIADI(31 downto 0) => B"00000000000000000000000001111111", DIBDI(31 downto 0) => B"11111111111111111111111111111111", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"1111", DOADO(31 downto 7) => NLW_q0_reg_1_DOADO_UNCONNECTED(31 downto 7), DOADO(6 downto 0) => \out\(15 downto 9), DOBDO(31 downto 0) => NLW_q0_reg_1_DOBDO_UNCONNECTED(31 downto 0), DOPADOP(3 downto 0) => NLW_q0_reg_1_DOPADOP_UNCONNECTED(3 downto 0), DOPBDOP(3 downto 0) => NLW_q0_reg_1_DOPBDOP_UNCONNECTED(3 downto 0), ECCPARITY(7 downto 0) => NLW_q0_reg_1_ECCPARITY_UNCONNECTED(7 downto 0), ENARDEN => Q(0), ENBWREN => '0', INJECTDBITERR => NLW_q0_reg_1_INJECTDBITERR_UNCONNECTED, INJECTSBITERR => NLW_q0_reg_1_INJECTSBITERR_UNCONNECTED, RDADDRECC(8 downto 0) => NLW_q0_reg_1_RDADDRECC_UNCONNECTED(8 downto 0), REGCEAREGCE => Q(1), REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => SR(0), RSTREGB => '0', SBITERR => NLW_q0_reg_1_SBITERR_UNCONNECTED, WEA(3 downto 0) => B"0000", WEBWE(7 downto 0) => B"00000000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V is port ( \out\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); ap_clk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); sel : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V is begin nco_sine_lut_V_rom_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V_rom port map ( Q(1 downto 0) => Q(1 downto 0), SR(0) => SR(0), ap_clk => ap_clk, \out\(15 downto 0) => \out\(15 downto 0), sel(11 downto 0) => sel(11 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco is port ( s_axi_AXILiteS_AWVALID : in STD_LOGIC; s_axi_AXILiteS_AWREADY : out STD_LOGIC; s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_AXILiteS_WVALID : in STD_LOGIC; s_axi_AXILiteS_WREADY : out STD_LOGIC; s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_AXILiteS_ARVALID : in STD_LOGIC; s_axi_AXILiteS_ARREADY : out STD_LOGIC; s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_AXILiteS_RVALID : out STD_LOGIC; s_axi_AXILiteS_RREADY : in STD_LOGIC; s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_AXILiteS_BVALID : out STD_LOGIC; s_axi_AXILiteS_BREADY : in STD_LOGIC; s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC ); attribute C_S_AXI_AXILITES_ADDR_WIDTH : integer; attribute C_S_AXI_AXILITES_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 6; attribute C_S_AXI_AXILITES_DATA_WIDTH : integer; attribute C_S_AXI_AXILITES_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 32; attribute C_S_AXI_AXILITES_WSTRB_WIDTH : integer; attribute C_S_AXI_AXILITES_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 4; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 32; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 4; attribute ap_ST_st1_fsm_0 : string; attribute ap_ST_st1_fsm_0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "2'b01"; attribute ap_ST_st2_fsm_1 : string; attribute ap_ST_st2_fsm_1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "2'b10"; attribute ap_const_int64_8 : integer; attribute ap_const_int64_8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 8; attribute ap_const_logic_0 : string; attribute ap_const_logic_0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "1'b0"; attribute ap_const_logic_1 : string; attribute ap_const_logic_1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "1'b1"; attribute ap_const_lv1_1 : string; attribute ap_const_lv1_1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "1'b1"; attribute ap_const_lv32_0 : integer; attribute ap_const_lv32_0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 0; attribute ap_const_lv32_1 : integer; attribute ap_const_lv32_1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 1; attribute ap_const_lv32_4 : integer; attribute ap_const_lv32_4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 4; attribute ap_const_lv32_F : integer; attribute ap_const_lv32_F of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is 15; attribute ap_true : string; attribute ap_true of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "1'b1"; attribute hls_module : string; attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco is signal \<const0>\ : STD_LOGIC; signal ap_NS_fsm : STD_LOGIC_VECTOR ( 1 to 1 ); signal ap_rst_n_inv : STD_LOGIC; signal ap_sig_bdd_66 : STD_LOGIC; signal ap_sig_bdd_79 : STD_LOGIC; signal int_sine_sample_V : STD_LOGIC_VECTOR ( 15 downto 0 ); signal nco_AXILiteS_s_axi_U_n_10 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_11 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_12 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_13 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_14 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_15 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_16 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_17 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_18 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_3 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_4 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_5 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_6 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_7 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_8 : STD_LOGIC; signal nco_AXILiteS_s_axi_U_n_9 : STD_LOGIC; signal \^s_axi_axilites_rdata\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal sel : STD_LOGIC_VECTOR ( 11 downto 0 ); signal temp_V_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute FSM_ENCODING : string; attribute FSM_ENCODING of \ap_CS_fsm_reg[0]\ : label is "none"; attribute FSM_ENCODING of \ap_CS_fsm_reg[1]\ : label is "none"; begin s_axi_AXILiteS_BRESP(1) <= \<const0>\; s_axi_AXILiteS_BRESP(0) <= \<const0>\; s_axi_AXILiteS_RDATA(31) <= \<const0>\; s_axi_AXILiteS_RDATA(30) <= \<const0>\; s_axi_AXILiteS_RDATA(29) <= \<const0>\; s_axi_AXILiteS_RDATA(28) <= \<const0>\; s_axi_AXILiteS_RDATA(27) <= \<const0>\; s_axi_AXILiteS_RDATA(26) <= \<const0>\; s_axi_AXILiteS_RDATA(25) <= \<const0>\; s_axi_AXILiteS_RDATA(24) <= \<const0>\; s_axi_AXILiteS_RDATA(23) <= \<const0>\; s_axi_AXILiteS_RDATA(22) <= \<const0>\; s_axi_AXILiteS_RDATA(21) <= \<const0>\; s_axi_AXILiteS_RDATA(20) <= \<const0>\; s_axi_AXILiteS_RDATA(19) <= \<const0>\; s_axi_AXILiteS_RDATA(18) <= \<const0>\; s_axi_AXILiteS_RDATA(17) <= \<const0>\; s_axi_AXILiteS_RDATA(16) <= \<const0>\; s_axi_AXILiteS_RDATA(15 downto 0) <= \^s_axi_axilites_rdata\(15 downto 0); s_axi_AXILiteS_RRESP(1) <= \<const0>\; s_axi_AXILiteS_RRESP(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \ap_CS_fsm[1]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ap_sig_bdd_79, O => ap_NS_fsm(1) ); \ap_CS_fsm_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => ap_clk, CE => '1', D => ap_sig_bdd_79, Q => ap_sig_bdd_66, S => ap_rst_n_inv ); \ap_CS_fsm_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => '1', D => ap_NS_fsm(1), Q => ap_sig_bdd_79, R => ap_rst_n_inv ); nco_AXILiteS_s_axi_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_AXILiteS_s_axi port map ( O(3) => nco_AXILiteS_s_axi_U_n_3, O(2) => nco_AXILiteS_s_axi_U_n_4, O(1) => nco_AXILiteS_s_axi_U_n_5, O(0) => nco_AXILiteS_s_axi_U_n_6, Q(0) => ap_sig_bdd_79, ap_clk => ap_clk, ap_rst_n => ap_rst_n, ap_rst_n_inv => ap_rst_n_inv, \out\(15 downto 0) => int_sine_sample_V(15 downto 0), s_axi_AXILiteS_ARADDR(4 downto 0) => s_axi_AXILiteS_ARADDR(4 downto 0), s_axi_AXILiteS_ARREADY => s_axi_AXILiteS_ARREADY, s_axi_AXILiteS_ARVALID => s_axi_AXILiteS_ARVALID, s_axi_AXILiteS_AWADDR(4 downto 0) => s_axi_AXILiteS_AWADDR(4 downto 0), s_axi_AXILiteS_AWREADY => s_axi_AXILiteS_AWREADY, s_axi_AXILiteS_AWVALID => s_axi_AXILiteS_AWVALID, s_axi_AXILiteS_BREADY => s_axi_AXILiteS_BREADY, s_axi_AXILiteS_BVALID => s_axi_AXILiteS_BVALID, s_axi_AXILiteS_RDATA(15 downto 0) => \^s_axi_axilites_rdata\(15 downto 0), s_axi_AXILiteS_RREADY => s_axi_AXILiteS_RREADY, s_axi_AXILiteS_RVALID => s_axi_AXILiteS_RVALID, s_axi_AXILiteS_WDATA(15 downto 0) => s_axi_AXILiteS_WDATA(15 downto 0), s_axi_AXILiteS_WREADY => s_axi_AXILiteS_WREADY, s_axi_AXILiteS_WSTRB(1 downto 0) => s_axi_AXILiteS_WSTRB(1 downto 0), s_axi_AXILiteS_WVALID => s_axi_AXILiteS_WVALID, sel(11 downto 0) => sel(11 downto 0), temp_V_reg(15 downto 0) => temp_V_reg(15 downto 0), \temp_V_reg[11]\(3) => nco_AXILiteS_s_axi_U_n_11, \temp_V_reg[11]\(2) => nco_AXILiteS_s_axi_U_n_12, \temp_V_reg[11]\(1) => nco_AXILiteS_s_axi_U_n_13, \temp_V_reg[11]\(0) => nco_AXILiteS_s_axi_U_n_14, \temp_V_reg[15]\(3) => nco_AXILiteS_s_axi_U_n_15, \temp_V_reg[15]\(2) => nco_AXILiteS_s_axi_U_n_16, \temp_V_reg[15]\(1) => nco_AXILiteS_s_axi_U_n_17, \temp_V_reg[15]\(0) => nco_AXILiteS_s_axi_U_n_18, \temp_V_reg[7]\(3) => nco_AXILiteS_s_axi_U_n_7, \temp_V_reg[7]\(2) => nco_AXILiteS_s_axi_U_n_8, \temp_V_reg[7]\(1) => nco_AXILiteS_s_axi_U_n_9, \temp_V_reg[7]\(0) => nco_AXILiteS_s_axi_U_n_10 ); sine_lut_V_U: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco_sine_lut_V port map ( Q(1) => ap_sig_bdd_79, Q(0) => ap_sig_bdd_66, SR(0) => ap_rst_n_inv, ap_clk => ap_clk, \out\(15 downto 0) => int_sine_sample_V(15 downto 0), sel(11 downto 0) => sel(11 downto 0) ); \temp_V_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_6, Q => temp_V_reg(0), R => '0' ); \temp_V_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_12, Q => temp_V_reg(10), R => '0' ); \temp_V_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_11, Q => temp_V_reg(11), R => '0' ); \temp_V_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_18, Q => temp_V_reg(12), R => '0' ); \temp_V_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_17, Q => temp_V_reg(13), R => '0' ); \temp_V_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_16, Q => temp_V_reg(14), R => '0' ); \temp_V_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_15, Q => temp_V_reg(15), R => '0' ); \temp_V_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_5, Q => temp_V_reg(1), R => '0' ); \temp_V_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_4, Q => temp_V_reg(2), R => '0' ); \temp_V_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_3, Q => temp_V_reg(3), R => '0' ); \temp_V_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_10, Q => temp_V_reg(4), R => '0' ); \temp_V_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_9, Q => temp_V_reg(5), R => '0' ); \temp_V_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_8, Q => temp_V_reg(6), R => '0' ); \temp_V_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_7, Q => temp_V_reg(7), R => '0' ); \temp_V_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_14, Q => temp_V_reg(8), R => '0' ); \temp_V_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ap_clk, CE => ap_sig_bdd_66, D => nco_AXILiteS_s_axi_U_n_13, Q => temp_V_reg(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_AXILiteS_AWVALID : in STD_LOGIC; s_axi_AXILiteS_AWREADY : out STD_LOGIC; s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_AXILiteS_WVALID : in STD_LOGIC; s_axi_AXILiteS_WREADY : out STD_LOGIC; s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_AXILiteS_BVALID : out STD_LOGIC; s_axi_AXILiteS_BREADY : in STD_LOGIC; s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 ); s_axi_AXILiteS_ARVALID : in STD_LOGIC; s_axi_AXILiteS_ARREADY : out STD_LOGIC; s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_AXILiteS_RVALID : out STD_LOGIC; s_axi_AXILiteS_RREADY : in STD_LOGIC; ap_clk : in STD_LOGIC; ap_rst_n : in STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_nco_0_0,nco,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "nco,Vivado 2017.3"; attribute hls_module : string; attribute hls_module of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute C_S_AXI_AXILITES_ADDR_WIDTH : integer; attribute C_S_AXI_AXILITES_ADDR_WIDTH of inst : label is 6; attribute C_S_AXI_AXILITES_DATA_WIDTH : integer; attribute C_S_AXI_AXILITES_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_AXILITES_WSTRB_WIDTH : integer; attribute C_S_AXI_AXILITES_WSTRB_WIDTH of inst : label is 4; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of inst : label is 32; attribute C_S_AXI_WSTRB_WIDTH : integer; attribute C_S_AXI_WSTRB_WIDTH of inst : label is 4; attribute ap_ST_st1_fsm_0 : string; attribute ap_ST_st1_fsm_0 of inst : label is "2'b01"; attribute ap_ST_st2_fsm_1 : string; attribute ap_ST_st2_fsm_1 of inst : label is "2'b10"; attribute ap_const_int64_8 : integer; attribute ap_const_int64_8 of inst : label is 8; attribute ap_const_logic_0 : string; attribute ap_const_logic_0 of inst : label is "1'b0"; attribute ap_const_logic_1 : string; attribute ap_const_logic_1 of inst : label is "1'b1"; attribute ap_const_lv1_1 : string; attribute ap_const_lv1_1 of inst : label is "1'b1"; attribute ap_const_lv32_0 : integer; attribute ap_const_lv32_0 of inst : label is 0; attribute ap_const_lv32_1 : integer; attribute ap_const_lv32_1 of inst : label is 1; attribute ap_const_lv32_4 : integer; attribute ap_const_lv32_4 of inst : label is 4; attribute ap_const_lv32_F : integer; attribute ap_const_lv32_F of inst : label is 15; attribute ap_true : string; attribute ap_true of inst : label is "1'b1"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of ap_clk : signal is "xilinx.com:signal:clock:1.0 ap_clk CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of ap_clk : signal is "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_AXILiteS, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of ap_rst_n : signal is "xilinx.com:signal:reset:1.0 ap_rst_n RST"; attribute X_INTERFACE_PARAMETER of ap_rst_n : signal is "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARREADY"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARVALID"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWREADY"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWVALID"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BREADY"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BVALID"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_AXILiteS_RREADY : signal is "XIL_INTERFACENAME s_axi_AXILiteS, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RVALID"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WREADY"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WVALID"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARADDR"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWADDR"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BRESP"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RDATA"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RRESP"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WDATA"; attribute X_INTERFACE_INFO of s_axi_AXILiteS_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WSTRB"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_nco port map ( ap_clk => ap_clk, ap_rst_n => ap_rst_n, s_axi_AXILiteS_ARADDR(5 downto 0) => s_axi_AXILiteS_ARADDR(5 downto 0), s_axi_AXILiteS_ARREADY => s_axi_AXILiteS_ARREADY, s_axi_AXILiteS_ARVALID => s_axi_AXILiteS_ARVALID, s_axi_AXILiteS_AWADDR(5 downto 0) => s_axi_AXILiteS_AWADDR(5 downto 0), s_axi_AXILiteS_AWREADY => s_axi_AXILiteS_AWREADY, s_axi_AXILiteS_AWVALID => s_axi_AXILiteS_AWVALID, s_axi_AXILiteS_BREADY => s_axi_AXILiteS_BREADY, s_axi_AXILiteS_BRESP(1 downto 0) => s_axi_AXILiteS_BRESP(1 downto 0), s_axi_AXILiteS_BVALID => s_axi_AXILiteS_BVALID, s_axi_AXILiteS_RDATA(31 downto 0) => s_axi_AXILiteS_RDATA(31 downto 0), s_axi_AXILiteS_RREADY => s_axi_AXILiteS_RREADY, s_axi_AXILiteS_RRESP(1 downto 0) => s_axi_AXILiteS_RRESP(1 downto 0), s_axi_AXILiteS_RVALID => s_axi_AXILiteS_RVALID, s_axi_AXILiteS_WDATA(31 downto 0) => s_axi_AXILiteS_WDATA(31 downto 0), s_axi_AXILiteS_WREADY => s_axi_AXILiteS_WREADY, s_axi_AXILiteS_WSTRB(3 downto 0) => s_axi_AXILiteS_WSTRB(3 downto 0), s_axi_AXILiteS_WVALID => s_axi_AXILiteS_WVALID ); end STRUCTURE;

mit

3870fc438da17d357a53a0d956840945

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-nuhorizons-3s1500/leon3mp.vhd

----------------------------------------------------------------------------- -- LEON3 Demonstration design -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.memctrl.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.can.all; use gaisler.net.all; use gaisler.jtag.all; library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW ); port ( pb_sw : in std_logic_vector (4 downto 1); -- push buttons pll_clk : in std_ulogic; -- PLL clock led : out std_logic_vector(8 downto 1); flash_a : out std_logic_vector(20 downto 0); flash_d : inout std_logic_vector(15 downto 0); sdram_a : out std_logic_vector(11 downto 0); sdram_d : inout std_logic_vector(31 downto 0); sdram_ba : out std_logic_vector(3 downto 0); sdram_dqm : out std_logic_vector(3 downto 0); sdram_clk : inout std_ulogic; sdram_cke : out std_ulogic; -- sdram clock enable sdram_csn : out std_ulogic; -- sdram chip select sdram_wen : out std_ulogic; -- sdram write enable sdram_rasn : out std_ulogic; -- sdram ras sdram_casn : out std_ulogic; -- sdram cas uart1_txd : out std_ulogic; uart1_rxd : in std_ulogic; uart1_rts : out std_ulogic; uart1_cts : in std_ulogic; uart2_txd : out std_ulogic; uart2_rxd : in std_ulogic; uart2_rts : out std_ulogic; uart2_cts : in std_ulogic; flash_oen : out std_ulogic; flash_wen : out std_ulogic; flash_cen : out std_ulogic; flash_byte : out std_ulogic; flash_ready : in std_ulogic; flash_rpn : out std_ulogic; flash_wpn : out std_ulogic; phy_mii_data: inout std_logic; -- ethernet PHY interface phy_tx_clk : in std_ulogic; phy_rx_clk : in std_ulogic; phy_rx_data : in std_logic_vector(3 downto 0); phy_dv : in std_ulogic; phy_rx_er : in std_ulogic; phy_col : in std_ulogic; phy_crs : in std_ulogic; phy_tx_data : out std_logic_vector(3 downto 0); phy_tx_en : out std_ulogic; phy_mii_clk : out std_ulogic; phy_100 : in std_ulogic; -- 100 Mbit indicator phy_rst_n : out std_ulogic; gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- lcd_data : inout std_logic_vector(7 downto 0); -- lcd_rs : out std_ulogic; -- lcd_rw : out std_ulogic; -- lcd_en : out std_ulogic; -- lcd_backl : out std_ulogic; can_txd : out std_ulogic; can_rxd : in std_ulogic; smsc_addr : out std_logic_vector(14 downto 0); smsc_data : inout std_logic_vector(31 downto 0); smsc_nbe : out std_logic_vector(3 downto 0); smsc_resetn : out std_ulogic; smsc_ardy : in std_ulogic; -- smsc_intr : in std_ulogic; smsc_nldev : in std_ulogic; smsc_nrd : out std_ulogic; smsc_nwr : out std_ulogic; smsc_ncs : out std_ulogic; smsc_aen : out std_ulogic; smsc_lclk : out std_ulogic; smsc_wnr : out std_ulogic; smsc_rdyrtn : out std_ulogic; smsc_cycle : out std_ulogic; smsc_nads : out std_ulogic ); end; architecture rtl of leon3mp is signal vcc, gnd : std_logic_vector(7 downto 0); signal wpo : wprot_out_type; signal sdi : sdctrl_in_type; signal sdo : sdram_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal clkm, rstn, rstraw, pciclk, sdclkl : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal u1i, u2i, dui : uart_in_type; signal u1o, u2o, duo : uart_out_type; signal irqi : irq_in_vector(0 to CFG_NCPU-1); signal irqo : irq_out_vector(0 to CFG_NCPU-1); signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal ethi, ethi1, ethi2 : eth_in_type; signal etho, etho1, etho2 : eth_out_type; signal gpti : gptimer_in_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; signal can_lrx, can_ltx : std_ulogic; signal lclk, pci_lclk, sdfb : std_ulogic; signal tck, tms, tdi, tdo : std_ulogic; signal resetn : std_ulogic; signal pbsw : std_logic_vector(4 downto 1); signal ledo : std_logic_vector(8 downto 1); signal memi : memory_in_type; signal memo : memory_out_type; --for smc lan chip signal s_eth_aen : std_logic; signal s_eth_readn : std_logic; signal s_eth_writen: std_logic; signal s_eth_nbe : std_logic_vector(3 downto 0); signal s_eth_din : std_logic_vector(31 downto 0); constant ahbmmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+ CFG_GRETH; constant BOARD_FREQ : integer := 50000; -- board frequency in KHz constant CPU_FREQ : integer := (BOARD_FREQ*CFG_CLKMUL)/CFG_CLKDIV; -- cpu frequency in KHz begin ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); sdram_clk_pad : skew_outpad generic map (tech => padtech, slew => 1, strength => 24, skew => -60) port map (sdram_clk, sdclkl, rstn); cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; resetn <= pbsw(4); ledo(2) <= not cgo.clklock; ledo(3) <= pbsw(3); clk_pad : clkpad generic map (tech => padtech) port map (pll_clk, lclk); clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ) port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo); rst0 : rstgen -- reset generator port map (resetn, clkm, cgo.clklock, rstn, rstraw); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, nahbm => ahbmmax, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- l3 : if CFG_LEON3 = 1 generate cpu : for i in 0 to CFG_NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; ledo(8) <= dbgo(0).error; dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; dsui.break <= pbsw(1); ledo(1) <= not dsuo.active; end generate; end generate; nodcom : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0: ahbuart -- Debug UART generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); dui.rxd <= u2i.rxd; u2o.txd <= duo.txd; u2o.rtsn <= gnd(0); end generate; nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- PROM/SDRAM Memory controller ------------------------------------ ---------------------------------------------------------------------- memi.brdyn <= '1'; memi.bexcn <= '1'; memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00" when CFG_MCTRL_RAM16BIT = 0 else "01"; mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller sr1 : entity work.smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0, srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64) port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo, s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe, s_eth_din); addr_pad : outpadv generic map (width => 21, tech => padtech) port map (flash_a(20 downto 0), memo.address(21 downto 1)); roms_pad : outpad generic map (tech => padtech) port map (flash_cen, memo.romsn(0)); oen_pad : outpad generic map (tech => padtech) port map (flash_oen, memo.oen); wri_pad : outpad generic map (tech => padtech) port map (flash_wen, memo.writen); rom8 : if CFG_MCTRL_RAM16BIT = 0 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (flash_d(7 downto 0), memo.data(31 downto 24), memo.bdrive(0), memi.data(31 downto 24)); data15_pad : iopad generic map (tech => padtech) port map (flash_d(15), memo.address(0), gnd(0), open); end generate; rom16 : if CFG_MCTRL_RAM16BIT = 1 generate data_pad : iopadv generic map (tech => padtech, width => 16) port map (flash_d(15 downto 0), memo.data(31 downto 16), memo.bdrive(0), memi.data(31 downto 16)); end generate; sa_pad : outpadv generic map (width => 12, tech => padtech) port map (sdram_a, memo.sa(11 downto 0)); sba1_pad : outpadv generic map (width => 2, tech => padtech) port map (sdram_ba(1 downto 0), memo.sa(14 downto 13)); sba2_pad : outpadv generic map (width => 2, tech => padtech) port map (sdram_ba(3 downto 2), memo.sa(14 downto 13)); bdr : for i in 0 to 3 generate sd_pad : iopadv generic map (tech => padtech, width => 8) port map (sdram_d(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8)); end generate; sdcke_pad : outpad generic map (tech => padtech) port map (sdram_cke, sdo.sdcke(0)); sdwen_pad : outpad generic map (tech => padtech) port map (sdram_wen, sdo.sdwen); sdcsn_pad : outpad generic map (tech => padtech) port map (sdram_csn, sdo.sdcsn(0)); sdras_pad : outpad generic map (tech => padtech) port map (sdram_rasn, sdo.rasn); sdcas_pad : outpad generic map (tech => padtech) port map (sdram_casn, sdo.casn); sddqm_pad : outpadv generic map (width => 4, tech => padtech) port map (sdram_dqm, sdo.dqm(3 downto 0)); end generate; nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller sdcke_pad : outpad generic map (tech => padtech) port map (sdram_cke, gnd(0)); sdcsn_pad : outpad generic map (tech => padtech) port map (sdram_csn, vcc(0)); end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom generic map (hindex => 4, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(4)); end generate; nobpromgen : if CFG_AHBROMEN = 0 generate ahbso(4) <= ahbs_none; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.extclk <= '0'; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd); ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd); ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts, u1i.ctsn); ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts, u1o.rtsn); ua2 : if (CFG_UART2_ENABLE /= 0) and (CFG_AHB_UART = 0) generate uart2 : apbuart -- UART 2 generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) port map (rstn, clkm, apbi, apbo(9), u2i, u2o); u2i.extclk <= '0'; end generate; noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate; ua2rx_pad : inpad generic map (tech => padtech) port map (uart2_rxd, u2i.rxd); ua2tx_pad : outpad generic map (tech => padtech) port map (uart2_txd, u2o.txd); ua2cts_pad : inpad generic map (tech => padtech) port map (uart2_cts, u2i.ctsn); ua2rts_pad : outpad generic map (tech => padtech) port map (uart2_rts, u2o.rtsn); irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit grgpio0: grgpio generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH) port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5), gpioi => gpioi, gpioo => gpioo); pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate pio_pad : iopad generic map (tech => padtech) port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); end generate; end generate; ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, pindex => 15, paddr => 15, pirq => 12, memtech => memtech, mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO, nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL) port map( rst => rstn, clk => clkm, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho); end generate; ethpads : if CFG_GRETH = 0 generate -- no eth etho <= eth_out_none; end generate; emdio_pad : iopad generic map (tech => padtech) port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i); etxc_pad : clkpad generic map (tech => padtech, arch => 0) port map (phy_tx_clk, ethi.tx_clk); erxc_pad : clkpad generic map (tech => padtech, arch => 0) port map (phy_rx_clk, ethi.rx_clk); erxd_pad : inpadv generic map (tech => padtech, width => 4) port map (phy_rx_data, ethi.rxd(3 downto 0)); erxdv_pad : inpad generic map (tech => padtech) port map (phy_dv, ethi.rx_dv); erxer_pad : inpad generic map (tech => padtech) port map (phy_rx_er, ethi.rx_er); erxco_pad : inpad generic map (tech => padtech) port map (phy_col, ethi.rx_col); erxcr_pad : inpad generic map (tech => padtech) port map (phy_crs, ethi.rx_crs); etxd_pad : outpadv generic map (tech => padtech, width => 4) port map (phy_tx_data, etho.txd(3 downto 0)); etxen_pad : outpad generic map (tech => padtech) port map ( phy_tx_en, etho.tx_en); emdc_pad : outpad generic map (tech => padtech) port map (phy_mii_clk, etho.mdc); ereset_pad : outpad generic map (tech => padtech) port map (phy_rst_n, rstn); ----------------------------------------------------------------------- --- CAN -------------------------------------------------------------- ----------------------------------------------------------------------- can0 : if CFG_CAN = 1 generate can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO, iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech) port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx ); end generate; ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate; can_loopback : if CFG_CANLOOP = 1 generate can_lrx <= can_ltx; end generate; can_pads : if CFG_CANLOOP = 0 generate can_tx_pad : outpad generic map (tech => padtech) port map (can_txd, can_ltx); can_rx_pad : inpad generic map (tech => padtech) port map (can_rxd, can_lrx); end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ocram : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE) port map ( rstn, clkm, ahbsi, ahbso(7)); end generate; nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- I/O interface --------------------------------------------------- ----------------------------------------------------------------------- pb_sw_pad : inpadv generic map (width => 4, tech => padtech) port map (pb_sw, pbsw); led_pad : outpadv generic map (width => 8, tech => padtech) port map (led, ledo); rom8 : if CFG_MCTRL_RAM16BIT = 0 generate byte_pad : outpad generic map (tech => padtech) port map (flash_byte, gnd(0)); end generate; rom16 : if CFG_MCTRL_RAM16BIT = 1 generate byte_pad : outpad generic map (tech => padtech) port map (flash_byte, vcc(0)); end generate; rpn_pad : outpad generic map (tech => padtech) port map (flash_rpn, rstn); wpn_pad : outpad generic map (tech => padtech) port map (flash_wpn, vcc(0)); ready_pad : inpad generic map (tech => padtech) port map (flash_ready, open); smsc_data_pads : for i in 0 to 3 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (smsc_data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), s_eth_din(31-i*8 downto 24-i*8)); end generate; smsc_addr_pad : outpadv generic map (tech => padtech, width => 15) port map (smsc_addr, memo.address(15 downto 1)); smsc_nbe_pad : outpadv generic map (tech => padtech, width => 4) port map (smsc_nbe, s_eth_nbe); smsc_reset_pad : outpad generic map (tech => padtech) port map (smsc_resetn, rstn); smsc_nrd_pad : outpad generic map (tech => padtech) port map (smsc_nrd, s_eth_readn); smsc_nwr_pad : outpad generic map (tech => padtech) port map (smsc_nwr, s_eth_writen); smsc_ncs_pad : outpad generic map (tech => padtech) port map (smsc_ncs, memo.iosn); smsc_aen_pad : outpad generic map (tech => padtech) port map (smsc_aen, s_eth_aen); smsc_lclk_pad : outpad generic map (tech => padtech) port map (smsc_lclk, vcc(0)); smsc_wnr_pad : outpad generic map (tech => padtech) port map (smsc_wnr, vcc(0)); smsc_rdyrtn_pad : outpad generic map (tech => padtech) port map (smsc_rdyrtn, vcc(0)); smsc_cycle_pad : outpad generic map (tech => padtech) port map (smsc_cycle, vcc(0)); smsc_nads_pad : outpad generic map (tech => padtech) port map (smsc_nads, gnd(0)); -- lcd_data_pad : iopadv generic map (width => 8, tech => padtech) -- port map (lcd_data, nuo.lcd_data, nuo.lcd_ben, nui.lcd_data); -- lcd_rs_pad : outpad generic map (tech => padtech) -- port map (lcd_rs, nuo.lcd_rs); -- lcd_rw_pad : outpad generic map (tech => padtech) -- port map (lcd_rw, nuo.lcd_rw ); -- lcd_en_pad : outpad generic map (tech => padtech) -- port map (lcd_en, nuo.lcd_en); -- lcd_backl_pad : outpad generic map (tech => padtech) -- port map (lcd_backl, nuo.lcd_backl); ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- -- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate -- ahbmo(i) <= ahbm_none; -- end generate; -- nap0 : for i in 11 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate; apbo(6) <= apb_none; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 Demonstration design for Nuhorizon SP3 board", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on end;

gpl-2.0

82534e427c101219128cca26e15dd65e

VerkhovtsovPavel/BSUIR_Labs

Labs/POCP/POCP-6/src/RAM_Ham.vhd

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity RAM_Ham is generic( m: integer := 2; n: integer := 4 ); port ( CLK: in std_logic; WR: in std_logic; AB: in std_logic_vector (m-1 downto 0); DB: inout std_logic_vector (n-1 downto 0); ER: out std_logic ); end RAM_Ham; architecture Beh of RAM_Ham is subtype word is std_logic_vector (n+2 downto 0); type tram is array (0 to 2**m - 1) of word; signal sRAM: tram; signal addrreg: integer range 0 to 2**m - 1; signal buf: std_logic_vector (n-1 downto 0); Begin addrreg <= CONV_INTEGER(AB); WRP: process (WR, CLK, addrreg, DB) variable r1, r2, r3: std_logic; begin if WR = '0' then if rising_edge(CLK) then r1 := DB(0) xor DB(1) xor DB(2); r2 := DB(1) xor DB(2) xor DB(3); r3 := DB(0) xor DB(1) xor DB(3); sRAM(addrreg) <= r3 & r2 & r1 & DB; end if; end if; end process; RDP: process(WR, sRAM, addrreg) variable s1, s2, s3 : std_logic; begin if WR = '1' then s1 := sRAM(addrreg)(0) xor sRAM(addrreg)(1) xor sRAM(addrreg)(2) xor sRAM(addrreg)(n); s2 := sRAM(addrreg)(1) xor sRAM(addrreg)(2) xor sRAM(addrreg)(3) xor sRAM(addrreg)(n + 1); s3 := sRAM(addrreg)(0) xor sRAM(addrreg)(1) xor sRAM(addrreg)(3) xor sRAM(addrreg)(n + 2); ER <= s1 or s2 or s3; DB <= sRAM (addrreg)(n-1 downto 0); else DB <= (others => 'Z'); end if; end process; end Beh;

mit

4e4907beaf72280925e65fe35d526aaa

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/33befe9f7af11a93/led_controller_design_led_controller_0_0_sim_netlist.vhdl

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 15:44:51 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_led_controller_0_0_sim_netlist.vhdl -- Design : led_controller_design_led_controller_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI is port ( S_AXI_ARREADY : out STD_LOGIC; S_AXI_AWREADY : out STD_LOGIC; S_AXI_WREADY : out STD_LOGIC; LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_rvalid : out STD_LOGIC; s00_axi_bvalid : out STD_LOGIC; s00_axi_arvalid : in STD_LOGIC; s00_axi_aclk : in STD_LOGIC; s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_awvalid : in STD_LOGIC; s00_axi_wvalid : in STD_LOGIC; s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_aresetn : in STD_LOGIC; s00_axi_bready : in STD_LOGIC; s00_axi_rready : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI is signal \^leds_out\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; signal aw_en_i_1_n_0 : STD_LOGIC; signal aw_en_reg_n_0 : STD_LOGIC; signal axi_araddr : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \axi_araddr[2]_i_1_n_0\ : STD_LOGIC; signal \axi_araddr[3]_i_1_n_0\ : STD_LOGIC; signal axi_arready_i_1_n_0 : STD_LOGIC; signal \axi_awaddr[2]_i_1_n_0\ : STD_LOGIC; signal \axi_awaddr[3]_i_1_n_0\ : STD_LOGIC; signal axi_awready0 : STD_LOGIC; signal axi_bvalid_i_1_n_0 : STD_LOGIC; signal axi_rvalid_i_1_n_0 : STD_LOGIC; signal axi_wready0 : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 ); signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 7 ); signal reg_data_out : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s00_axi_bvalid\ : STD_LOGIC; signal \^s00_axi_rvalid\ : STD_LOGIC; signal slv_reg0 : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \slv_reg0[7]_i_1_n_0\ : STD_LOGIC; signal slv_reg1 : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \slv_reg1[15]_i_1_n_0\ : STD_LOGIC; signal \slv_reg1[23]_i_1_n_0\ : STD_LOGIC; signal \slv_reg1[31]_i_1_n_0\ : STD_LOGIC; signal \slv_reg1[7]_i_1_n_0\ : STD_LOGIC; signal slv_reg2 : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \slv_reg2[15]_i_1_n_0\ : STD_LOGIC; signal \slv_reg2[23]_i_1_n_0\ : STD_LOGIC; signal \slv_reg2[31]_i_1_n_0\ : STD_LOGIC; signal \slv_reg2[7]_i_1_n_0\ : STD_LOGIC; signal slv_reg3 : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \slv_reg3[15]_i_1_n_0\ : STD_LOGIC; signal \slv_reg3[23]_i_1_n_0\ : STD_LOGIC; signal \slv_reg3[31]_i_1_n_0\ : STD_LOGIC; signal \slv_reg3[7]_i_1_n_0\ : STD_LOGIC; signal \slv_reg_rden__0\ : STD_LOGIC; signal \slv_reg_wren__0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axi_araddr[3]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of axi_arready_i_1 : label is "soft_lutpair1"; attribute SOFT_HLUTNM of axi_wready_i_1 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \slv_reg0[7]_i_3\ : label is "soft_lutpair0"; begin LEDs_out(7 downto 0) <= \^leds_out\(7 downto 0); S_AXI_ARREADY <= \^s_axi_arready\; S_AXI_AWREADY <= \^s_axi_awready\; S_AXI_WREADY <= \^s_axi_wready\; s00_axi_bvalid <= \^s00_axi_bvalid\; s00_axi_rvalid <= \^s00_axi_rvalid\; aw_en_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"F7FFC4CCC4CCC4CC" ) port map ( I0 => s00_axi_wvalid, I1 => aw_en_reg_n_0, I2 => \^s_axi_awready\, I3 => s00_axi_awvalid, I4 => s00_axi_bready, I5 => \^s00_axi_bvalid\, O => aw_en_i_1_n_0 ); aw_en_reg: unisim.vcomponents.FDSE port map ( C => s00_axi_aclk, CE => '1', D => aw_en_i_1_n_0, Q => aw_en_reg_n_0, S => \slv_reg0[7]_i_1_n_0\ ); \axi_araddr[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s00_axi_araddr(0), I1 => s00_axi_arvalid, I2 => \^s_axi_arready\, I3 => axi_araddr(2), O => \axi_araddr[2]_i_1_n_0\ ); \axi_araddr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s00_axi_araddr(1), I1 => s00_axi_arvalid, I2 => \^s_axi_arready\, I3 => axi_araddr(3), O => \axi_araddr[3]_i_1_n_0\ ); \axi_araddr_reg[2]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => '1', D => \axi_araddr[2]_i_1_n_0\, Q => axi_araddr(2), R => \slv_reg0[7]_i_1_n_0\ ); \axi_araddr_reg[3]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => '1', D => \axi_araddr[3]_i_1_n_0\, Q => axi_araddr(3), R => \slv_reg0[7]_i_1_n_0\ ); axi_arready_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s00_axi_arvalid, I1 => \^s_axi_arready\, O => axi_arready_i_1_n_0 ); axi_arready_reg: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => '1', D => axi_arready_i_1_n_0, Q => \^s_axi_arready\, R => \slv_reg0[7]_i_1_n_0\ ); \axi_awaddr[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF08000000" ) port map ( I0 => s00_axi_awaddr(0), I1 => s00_axi_awvalid, I2 => \^s_axi_awready\, I3 => aw_en_reg_n_0, I4 => s00_axi_wvalid, I5 => p_0_in(0), O => \axi_awaddr[2]_i_1_n_0\ ); \axi_awaddr[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFFFFFF08000000" ) port map ( I0 => s00_axi_awaddr(1), I1 => s00_axi_awvalid, I2 => \^s_axi_awready\, I3 => aw_en_reg_n_0, I4 => s00_axi_wvalid, I5 => p_0_in(1), O => \axi_awaddr[3]_i_1_n_0\ ); \axi_awaddr_reg[2]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => '1', D => \axi_awaddr[2]_i_1_n_0\, Q => p_0_in(0), R => \slv_reg0[7]_i_1_n_0\ ); \axi_awaddr_reg[3]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => '1', D => \axi_awaddr[3]_i_1_n_0\, Q => p_0_in(1), R => \slv_reg0[7]_i_1_n_0\ ); axi_awready_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => s00_axi_awvalid, I1 => \^s_axi_awready\, I2 => aw_en_reg_n_0, I3 => s00_axi_wvalid, O => axi_awready0 ); axi_awready_reg: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => '1', D => axi_awready0, Q => \^s_axi_awready\, R => \slv_reg0[7]_i_1_n_0\ ); axi_bvalid_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFF80008000" ) port map ( I0 => \^s_axi_wready\, I1 => \^s_axi_awready\, I2 => s00_axi_awvalid, I3 => s00_axi_wvalid, I4 => s00_axi_bready, I5 => \^s00_axi_bvalid\, O => axi_bvalid_i_1_n_0 ); axi_bvalid_reg: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => '1', D => axi_bvalid_i_1_n_0, Q => \^s00_axi_bvalid\, R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(0), I1 => \^leds_out\(0), I2 => slv_reg3(0), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(0), O => reg_data_out(0) ); \axi_rdata[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(10), I1 => slv_reg0(10), I2 => slv_reg3(10), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(10), O => reg_data_out(10) ); \axi_rdata[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(11), I1 => slv_reg0(11), I2 => slv_reg3(11), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(11), O => reg_data_out(11) ); \axi_rdata[12]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(12), I1 => slv_reg0(12), I2 => slv_reg3(12), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(12), O => reg_data_out(12) ); \axi_rdata[13]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(13), I1 => slv_reg0(13), I2 => slv_reg3(13), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(13), O => reg_data_out(13) ); \axi_rdata[14]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(14), I1 => slv_reg0(14), I2 => slv_reg3(14), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(14), O => reg_data_out(14) ); \axi_rdata[15]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(15), I1 => slv_reg0(15), I2 => slv_reg3(15), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(15), O => reg_data_out(15) ); \axi_rdata[16]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(16), I1 => slv_reg0(16), I2 => slv_reg3(16), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(16), O => reg_data_out(16) ); \axi_rdata[17]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(17), I1 => slv_reg0(17), I2 => slv_reg3(17), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(17), O => reg_data_out(17) ); \axi_rdata[18]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(18), I1 => slv_reg0(18), I2 => slv_reg3(18), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(18), O => reg_data_out(18) ); \axi_rdata[19]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(19), I1 => slv_reg0(19), I2 => slv_reg3(19), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(19), O => reg_data_out(19) ); \axi_rdata[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(1), I1 => \^leds_out\(1), I2 => slv_reg3(1), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(1), O => reg_data_out(1) ); \axi_rdata[20]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(20), I1 => slv_reg0(20), I2 => slv_reg3(20), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(20), O => reg_data_out(20) ); \axi_rdata[21]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(21), I1 => slv_reg0(21), I2 => slv_reg3(21), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(21), O => reg_data_out(21) ); \axi_rdata[22]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(22), I1 => slv_reg0(22), I2 => slv_reg3(22), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(22), O => reg_data_out(22) ); \axi_rdata[23]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(23), I1 => slv_reg0(23), I2 => slv_reg3(23), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(23), O => reg_data_out(23) ); \axi_rdata[24]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(24), I1 => slv_reg0(24), I2 => slv_reg3(24), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(24), O => reg_data_out(24) ); \axi_rdata[25]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(25), I1 => slv_reg0(25), I2 => slv_reg3(25), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(25), O => reg_data_out(25) ); \axi_rdata[26]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(26), I1 => slv_reg0(26), I2 => slv_reg3(26), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(26), O => reg_data_out(26) ); \axi_rdata[27]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(27), I1 => slv_reg0(27), I2 => slv_reg3(27), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(27), O => reg_data_out(27) ); \axi_rdata[28]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(28), I1 => slv_reg0(28), I2 => slv_reg3(28), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(28), O => reg_data_out(28) ); \axi_rdata[29]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(29), I1 => slv_reg0(29), I2 => slv_reg3(29), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(29), O => reg_data_out(29) ); \axi_rdata[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(2), I1 => \^leds_out\(2), I2 => slv_reg3(2), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(2), O => reg_data_out(2) ); \axi_rdata[30]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(30), I1 => slv_reg0(30), I2 => slv_reg3(30), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(30), O => reg_data_out(30) ); \axi_rdata[31]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(31), I1 => slv_reg0(31), I2 => slv_reg3(31), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(31), O => reg_data_out(31) ); \axi_rdata[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(3), I1 => \^leds_out\(3), I2 => slv_reg3(3), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(3), O => reg_data_out(3) ); \axi_rdata[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(4), I1 => \^leds_out\(4), I2 => slv_reg3(4), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(4), O => reg_data_out(4) ); \axi_rdata[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(5), I1 => \^leds_out\(5), I2 => slv_reg3(5), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(5), O => reg_data_out(5) ); \axi_rdata[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(6), I1 => \^leds_out\(6), I2 => slv_reg3(6), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(6), O => reg_data_out(6) ); \axi_rdata[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(7), I1 => \^leds_out\(7), I2 => slv_reg3(7), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(7), O => reg_data_out(7) ); \axi_rdata[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(8), I1 => slv_reg0(8), I2 => slv_reg3(8), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(8), O => reg_data_out(8) ); \axi_rdata[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0AAFFCCF0AA00CC" ) port map ( I0 => slv_reg1(9), I1 => slv_reg0(9), I2 => slv_reg3(9), I3 => axi_araddr(3), I4 => axi_araddr(2), I5 => slv_reg2(9), O => reg_data_out(9) ); \axi_rdata_reg[0]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(0), Q => s00_axi_rdata(0), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[10]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(10), Q => s00_axi_rdata(10), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[11]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(11), Q => s00_axi_rdata(11), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[12]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(12), Q => s00_axi_rdata(12), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[13]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(13), Q => s00_axi_rdata(13), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[14]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(14), Q => s00_axi_rdata(14), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[15]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(15), Q => s00_axi_rdata(15), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[16]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(16), Q => s00_axi_rdata(16), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[17]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(17), Q => s00_axi_rdata(17), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[18]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(18), Q => s00_axi_rdata(18), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[19]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(19), Q => s00_axi_rdata(19), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[1]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(1), Q => s00_axi_rdata(1), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[20]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(20), Q => s00_axi_rdata(20), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[21]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(21), Q => s00_axi_rdata(21), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[22]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(22), Q => s00_axi_rdata(22), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[23]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(23), Q => s00_axi_rdata(23), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[24]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(24), Q => s00_axi_rdata(24), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[25]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(25), Q => s00_axi_rdata(25), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[26]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(26), Q => s00_axi_rdata(26), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[27]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(27), Q => s00_axi_rdata(27), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[28]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(28), Q => s00_axi_rdata(28), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[29]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(29), Q => s00_axi_rdata(29), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[2]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(2), Q => s00_axi_rdata(2), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[30]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(30), Q => s00_axi_rdata(30), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[31]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(31), Q => s00_axi_rdata(31), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[3]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(3), Q => s00_axi_rdata(3), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[4]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(4), Q => s00_axi_rdata(4), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[5]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(5), Q => s00_axi_rdata(5), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[6]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(6), Q => s00_axi_rdata(6), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[7]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(7), Q => s00_axi_rdata(7), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[8]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(8), Q => s00_axi_rdata(8), R => \slv_reg0[7]_i_1_n_0\ ); \axi_rdata_reg[9]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg_rden__0\, D => reg_data_out(9), Q => s00_axi_rdata(9), R => \slv_reg0[7]_i_1_n_0\ ); axi_rvalid_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"08F8" ) port map ( I0 => \^s_axi_arready\, I1 => s00_axi_arvalid, I2 => \^s00_axi_rvalid\, I3 => s00_axi_rready, O => axi_rvalid_i_1_n_0 ); axi_rvalid_reg: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => '1', D => axi_rvalid_i_1_n_0, Q => \^s00_axi_rvalid\, R => \slv_reg0[7]_i_1_n_0\ ); axi_wready_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => \^s_axi_wready\, I1 => s00_axi_wvalid, I2 => s00_axi_awvalid, I3 => aw_en_reg_n_0, O => axi_wready0 ); axi_wready_reg: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => '1', D => axi_wready0, Q => \^s_axi_wready\, R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0[15]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0200" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => p_0_in(0), I3 => s00_axi_wstrb(1), O => p_1_in(15) ); \slv_reg0[23]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0200" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => p_0_in(0), I3 => s00_axi_wstrb(2), O => p_1_in(23) ); \slv_reg0[31]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0200" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => p_0_in(0), I3 => s00_axi_wstrb(3), O => p_1_in(31) ); \slv_reg0[7]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => s00_axi_aresetn, O => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0200" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => p_0_in(0), I3 => s00_axi_wstrb(0), O => p_1_in(7) ); \slv_reg0[7]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \^s_axi_wready\, I1 => \^s_axi_awready\, I2 => s00_axi_awvalid, I3 => s00_axi_wvalid, O => \slv_reg_wren__0\ ); \slv_reg0_reg[0]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(7), D => s00_axi_wdata(0), Q => \^leds_out\(0), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[10]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(15), D => s00_axi_wdata(10), Q => slv_reg0(10), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[11]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(15), D => s00_axi_wdata(11), Q => slv_reg0(11), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[12]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(15), D => s00_axi_wdata(12), Q => slv_reg0(12), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[13]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(15), D => s00_axi_wdata(13), Q => slv_reg0(13), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[14]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(15), D => s00_axi_wdata(14), Q => slv_reg0(14), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[15]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(15), D => s00_axi_wdata(15), Q => slv_reg0(15), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[16]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(23), D => s00_axi_wdata(16), Q => slv_reg0(16), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[17]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(23), D => s00_axi_wdata(17), Q => slv_reg0(17), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[18]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(23), D => s00_axi_wdata(18), Q => slv_reg0(18), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[19]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(23), D => s00_axi_wdata(19), Q => slv_reg0(19), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[1]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(7), D => s00_axi_wdata(1), Q => \^leds_out\(1), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[20]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(23), D => s00_axi_wdata(20), Q => slv_reg0(20), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[21]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(23), D => s00_axi_wdata(21), Q => slv_reg0(21), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[22]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(23), D => s00_axi_wdata(22), Q => slv_reg0(22), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[23]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(23), D => s00_axi_wdata(23), Q => slv_reg0(23), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[24]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(31), D => s00_axi_wdata(24), Q => slv_reg0(24), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[25]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(31), D => s00_axi_wdata(25), Q => slv_reg0(25), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[26]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(31), D => s00_axi_wdata(26), Q => slv_reg0(26), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[27]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(31), D => s00_axi_wdata(27), Q => slv_reg0(27), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[28]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(31), D => s00_axi_wdata(28), Q => slv_reg0(28), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[29]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(31), D => s00_axi_wdata(29), Q => slv_reg0(29), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[2]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(7), D => s00_axi_wdata(2), Q => \^leds_out\(2), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[30]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(31), D => s00_axi_wdata(30), Q => slv_reg0(30), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[31]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(31), D => s00_axi_wdata(31), Q => slv_reg0(31), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[3]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(7), D => s00_axi_wdata(3), Q => \^leds_out\(3), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[4]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(7), D => s00_axi_wdata(4), Q => \^leds_out\(4), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[5]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(7), D => s00_axi_wdata(5), Q => \^leds_out\(5), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[6]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(7), D => s00_axi_wdata(6), Q => \^leds_out\(6), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[7]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(7), D => s00_axi_wdata(7), Q => \^leds_out\(7), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[8]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(15), D => s00_axi_wdata(8), Q => slv_reg0(8), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg0_reg[9]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => p_1_in(15), D => s00_axi_wdata(9), Q => slv_reg0(9), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1[15]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => s00_axi_wstrb(1), I3 => p_0_in(0), O => \slv_reg1[15]_i_1_n_0\ ); \slv_reg1[23]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => s00_axi_wstrb(2), I3 => p_0_in(0), O => \slv_reg1[23]_i_1_n_0\ ); \slv_reg1[31]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => s00_axi_wstrb(3), I3 => p_0_in(0), O => \slv_reg1[31]_i_1_n_0\ ); \slv_reg1[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => s00_axi_wstrb(0), I3 => p_0_in(0), O => \slv_reg1[7]_i_1_n_0\ ); \slv_reg1_reg[0]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[7]_i_1_n_0\, D => s00_axi_wdata(0), Q => slv_reg1(0), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[10]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[15]_i_1_n_0\, D => s00_axi_wdata(10), Q => slv_reg1(10), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[11]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[15]_i_1_n_0\, D => s00_axi_wdata(11), Q => slv_reg1(11), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[12]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[15]_i_1_n_0\, D => s00_axi_wdata(12), Q => slv_reg1(12), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[13]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[15]_i_1_n_0\, D => s00_axi_wdata(13), Q => slv_reg1(13), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[14]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[15]_i_1_n_0\, D => s00_axi_wdata(14), Q => slv_reg1(14), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[15]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[15]_i_1_n_0\, D => s00_axi_wdata(15), Q => slv_reg1(15), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[16]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[23]_i_1_n_0\, D => s00_axi_wdata(16), Q => slv_reg1(16), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[17]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[23]_i_1_n_0\, D => s00_axi_wdata(17), Q => slv_reg1(17), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[18]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[23]_i_1_n_0\, D => s00_axi_wdata(18), Q => slv_reg1(18), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[19]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[23]_i_1_n_0\, D => s00_axi_wdata(19), Q => slv_reg1(19), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[1]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[7]_i_1_n_0\, D => s00_axi_wdata(1), Q => slv_reg1(1), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[20]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[23]_i_1_n_0\, D => s00_axi_wdata(20), Q => slv_reg1(20), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[21]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[23]_i_1_n_0\, D => s00_axi_wdata(21), Q => slv_reg1(21), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[22]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[23]_i_1_n_0\, D => s00_axi_wdata(22), Q => slv_reg1(22), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[23]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[23]_i_1_n_0\, D => s00_axi_wdata(23), Q => slv_reg1(23), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[24]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[31]_i_1_n_0\, D => s00_axi_wdata(24), Q => slv_reg1(24), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[25]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[31]_i_1_n_0\, D => s00_axi_wdata(25), Q => slv_reg1(25), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[26]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[31]_i_1_n_0\, D => s00_axi_wdata(26), Q => slv_reg1(26), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[27]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[31]_i_1_n_0\, D => s00_axi_wdata(27), Q => slv_reg1(27), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[28]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[31]_i_1_n_0\, D => s00_axi_wdata(28), Q => slv_reg1(28), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[29]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[31]_i_1_n_0\, D => s00_axi_wdata(29), Q => slv_reg1(29), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[2]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[7]_i_1_n_0\, D => s00_axi_wdata(2), Q => slv_reg1(2), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[30]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[31]_i_1_n_0\, D => s00_axi_wdata(30), Q => slv_reg1(30), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[31]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[31]_i_1_n_0\, D => s00_axi_wdata(31), Q => slv_reg1(31), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[3]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[7]_i_1_n_0\, D => s00_axi_wdata(3), Q => slv_reg1(3), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[4]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[7]_i_1_n_0\, D => s00_axi_wdata(4), Q => slv_reg1(4), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[5]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[7]_i_1_n_0\, D => s00_axi_wdata(5), Q => slv_reg1(5), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[6]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[7]_i_1_n_0\, D => s00_axi_wdata(6), Q => slv_reg1(6), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[7]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[7]_i_1_n_0\, D => s00_axi_wdata(7), Q => slv_reg1(7), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[8]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[15]_i_1_n_0\, D => s00_axi_wdata(8), Q => slv_reg1(8), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg1_reg[9]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg1[15]_i_1_n_0\, D => s00_axi_wdata(9), Q => slv_reg1(9), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2[15]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => s00_axi_wstrb(1), I3 => p_0_in(0), O => \slv_reg2[15]_i_1_n_0\ ); \slv_reg2[23]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => s00_axi_wstrb(2), I3 => p_0_in(0), O => \slv_reg2[23]_i_1_n_0\ ); \slv_reg2[31]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => s00_axi_wstrb(3), I3 => p_0_in(0), O => \slv_reg2[31]_i_1_n_0\ ); \slv_reg2[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \slv_reg_wren__0\, I1 => p_0_in(1), I2 => s00_axi_wstrb(0), I3 => p_0_in(0), O => \slv_reg2[7]_i_1_n_0\ ); \slv_reg2_reg[0]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[7]_i_1_n_0\, D => s00_axi_wdata(0), Q => slv_reg2(0), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[10]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[15]_i_1_n_0\, D => s00_axi_wdata(10), Q => slv_reg2(10), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[11]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[15]_i_1_n_0\, D => s00_axi_wdata(11), Q => slv_reg2(11), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[12]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[15]_i_1_n_0\, D => s00_axi_wdata(12), Q => slv_reg2(12), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[13]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[15]_i_1_n_0\, D => s00_axi_wdata(13), Q => slv_reg2(13), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[14]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[15]_i_1_n_0\, D => s00_axi_wdata(14), Q => slv_reg2(14), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[15]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[15]_i_1_n_0\, D => s00_axi_wdata(15), Q => slv_reg2(15), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[16]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[23]_i_1_n_0\, D => s00_axi_wdata(16), Q => slv_reg2(16), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[17]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[23]_i_1_n_0\, D => s00_axi_wdata(17), Q => slv_reg2(17), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[18]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[23]_i_1_n_0\, D => s00_axi_wdata(18), Q => slv_reg2(18), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[19]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[23]_i_1_n_0\, D => s00_axi_wdata(19), Q => slv_reg2(19), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[1]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[7]_i_1_n_0\, D => s00_axi_wdata(1), Q => slv_reg2(1), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[20]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[23]_i_1_n_0\, D => s00_axi_wdata(20), Q => slv_reg2(20), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[21]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[23]_i_1_n_0\, D => s00_axi_wdata(21), Q => slv_reg2(21), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[22]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[23]_i_1_n_0\, D => s00_axi_wdata(22), Q => slv_reg2(22), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[23]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[23]_i_1_n_0\, D => s00_axi_wdata(23), Q => slv_reg2(23), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[24]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[31]_i_1_n_0\, D => s00_axi_wdata(24), Q => slv_reg2(24), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[25]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[31]_i_1_n_0\, D => s00_axi_wdata(25), Q => slv_reg2(25), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[26]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[31]_i_1_n_0\, D => s00_axi_wdata(26), Q => slv_reg2(26), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[27]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[31]_i_1_n_0\, D => s00_axi_wdata(27), Q => slv_reg2(27), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[28]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[31]_i_1_n_0\, D => s00_axi_wdata(28), Q => slv_reg2(28), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[29]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[31]_i_1_n_0\, D => s00_axi_wdata(29), Q => slv_reg2(29), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[2]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[7]_i_1_n_0\, D => s00_axi_wdata(2), Q => slv_reg2(2), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[30]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[31]_i_1_n_0\, D => s00_axi_wdata(30), Q => slv_reg2(30), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[31]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[31]_i_1_n_0\, D => s00_axi_wdata(31), Q => slv_reg2(31), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[3]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[7]_i_1_n_0\, D => s00_axi_wdata(3), Q => slv_reg2(3), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[4]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[7]_i_1_n_0\, D => s00_axi_wdata(4), Q => slv_reg2(4), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[5]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[7]_i_1_n_0\, D => s00_axi_wdata(5), Q => slv_reg2(5), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[6]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[7]_i_1_n_0\, D => s00_axi_wdata(6), Q => slv_reg2(6), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[7]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[7]_i_1_n_0\, D => s00_axi_wdata(7), Q => slv_reg2(7), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[8]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[15]_i_1_n_0\, D => s00_axi_wdata(8), Q => slv_reg2(8), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg2_reg[9]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg2[15]_i_1_n_0\, D => s00_axi_wdata(9), Q => slv_reg2(9), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3[15]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \slv_reg_wren__0\, I1 => s00_axi_wstrb(1), I2 => p_0_in(0), I3 => p_0_in(1), O => \slv_reg3[15]_i_1_n_0\ ); \slv_reg3[23]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \slv_reg_wren__0\, I1 => s00_axi_wstrb(2), I2 => p_0_in(0), I3 => p_0_in(1), O => \slv_reg3[23]_i_1_n_0\ ); \slv_reg3[31]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \slv_reg_wren__0\, I1 => s00_axi_wstrb(3), I2 => p_0_in(0), I3 => p_0_in(1), O => \slv_reg3[31]_i_1_n_0\ ); \slv_reg3[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \slv_reg_wren__0\, I1 => s00_axi_wstrb(0), I2 => p_0_in(0), I3 => p_0_in(1), O => \slv_reg3[7]_i_1_n_0\ ); \slv_reg3_reg[0]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[7]_i_1_n_0\, D => s00_axi_wdata(0), Q => slv_reg3(0), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[10]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[15]_i_1_n_0\, D => s00_axi_wdata(10), Q => slv_reg3(10), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[11]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[15]_i_1_n_0\, D => s00_axi_wdata(11), Q => slv_reg3(11), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[12]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[15]_i_1_n_0\, D => s00_axi_wdata(12), Q => slv_reg3(12), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[13]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[15]_i_1_n_0\, D => s00_axi_wdata(13), Q => slv_reg3(13), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[14]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[15]_i_1_n_0\, D => s00_axi_wdata(14), Q => slv_reg3(14), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[15]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[15]_i_1_n_0\, D => s00_axi_wdata(15), Q => slv_reg3(15), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[16]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[23]_i_1_n_0\, D => s00_axi_wdata(16), Q => slv_reg3(16), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[17]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[23]_i_1_n_0\, D => s00_axi_wdata(17), Q => slv_reg3(17), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[18]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[23]_i_1_n_0\, D => s00_axi_wdata(18), Q => slv_reg3(18), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[19]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[23]_i_1_n_0\, D => s00_axi_wdata(19), Q => slv_reg3(19), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[1]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[7]_i_1_n_0\, D => s00_axi_wdata(1), Q => slv_reg3(1), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[20]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[23]_i_1_n_0\, D => s00_axi_wdata(20), Q => slv_reg3(20), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[21]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[23]_i_1_n_0\, D => s00_axi_wdata(21), Q => slv_reg3(21), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[22]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[23]_i_1_n_0\, D => s00_axi_wdata(22), Q => slv_reg3(22), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[23]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[23]_i_1_n_0\, D => s00_axi_wdata(23), Q => slv_reg3(23), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[24]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[31]_i_1_n_0\, D => s00_axi_wdata(24), Q => slv_reg3(24), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[25]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[31]_i_1_n_0\, D => s00_axi_wdata(25), Q => slv_reg3(25), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[26]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[31]_i_1_n_0\, D => s00_axi_wdata(26), Q => slv_reg3(26), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[27]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[31]_i_1_n_0\, D => s00_axi_wdata(27), Q => slv_reg3(27), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[28]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[31]_i_1_n_0\, D => s00_axi_wdata(28), Q => slv_reg3(28), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[29]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[31]_i_1_n_0\, D => s00_axi_wdata(29), Q => slv_reg3(29), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[2]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[7]_i_1_n_0\, D => s00_axi_wdata(2), Q => slv_reg3(2), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[30]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[31]_i_1_n_0\, D => s00_axi_wdata(30), Q => slv_reg3(30), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[31]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[31]_i_1_n_0\, D => s00_axi_wdata(31), Q => slv_reg3(31), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[3]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[7]_i_1_n_0\, D => s00_axi_wdata(3), Q => slv_reg3(3), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[4]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[7]_i_1_n_0\, D => s00_axi_wdata(4), Q => slv_reg3(4), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[5]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[7]_i_1_n_0\, D => s00_axi_wdata(5), Q => slv_reg3(5), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[6]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[7]_i_1_n_0\, D => s00_axi_wdata(6), Q => slv_reg3(6), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[7]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[7]_i_1_n_0\, D => s00_axi_wdata(7), Q => slv_reg3(7), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[8]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[15]_i_1_n_0\, D => s00_axi_wdata(8), Q => slv_reg3(8), R => \slv_reg0[7]_i_1_n_0\ ); \slv_reg3_reg[9]\: unisim.vcomponents.FDRE port map ( C => s00_axi_aclk, CE => \slv_reg3[15]_i_1_n_0\, D => s00_axi_wdata(9), Q => slv_reg3(9), R => \slv_reg0[7]_i_1_n_0\ ); slv_reg_rden: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^s00_axi_rvalid\, I1 => s00_axi_arvalid, I2 => \^s_axi_arready\, O => \slv_reg_rden__0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 is port ( S_AXI_ARREADY : out STD_LOGIC; S_AXI_AWREADY : out STD_LOGIC; S_AXI_WREADY : out STD_LOGIC; LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_rvalid : out STD_LOGIC; s00_axi_bvalid : out STD_LOGIC; s00_axi_arvalid : in STD_LOGIC; s00_axi_aclk : in STD_LOGIC; s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_awvalid : in STD_LOGIC; s00_axi_wvalid : in STD_LOGIC; s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_aresetn : in STD_LOGIC; s00_axi_bready : in STD_LOGIC; s00_axi_rready : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 is begin led_controller_v1_0_S00_AXI_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI port map ( LEDs_out(7 downto 0) => LEDs_out(7 downto 0), S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WREADY => S_AXI_WREADY, s00_axi_aclk => s00_axi_aclk, s00_axi_araddr(1 downto 0) => s00_axi_araddr(1 downto 0), s00_axi_aresetn => s00_axi_aresetn, s00_axi_arvalid => s00_axi_arvalid, s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(1 downto 0), s00_axi_awvalid => s00_axi_awvalid, s00_axi_bready => s00_axi_bready, s00_axi_bvalid => s00_axi_bvalid, s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0), s00_axi_rready => s00_axi_rready, s00_axi_rvalid => s00_axi_rvalid, s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0), s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0), s00_axi_wvalid => s00_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_awvalid : in STD_LOGIC; s00_axi_awready : out STD_LOGIC; s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_wvalid : in STD_LOGIC; s00_axi_wready : out STD_LOGIC; s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_bvalid : out STD_LOGIC; s00_axi_bready : in STD_LOGIC; s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_arvalid : in STD_LOGIC; s00_axi_arready : out STD_LOGIC; s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_rvalid : out STD_LOGIC; s00_axi_rready : in STD_LOGIC; s00_axi_aclk : in STD_LOGIC; s00_axi_aresetn : in STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_design_led_controller_0_0,led_controller_v1_0,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_v1_0,Vivado 2017.3"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal \<const0>\ : STD_LOGIC; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of s00_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of s00_axi_aclk : signal is "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of s00_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S00_AXI_RST RST"; attribute X_INTERFACE_PARAMETER of s00_axi_aresetn : signal is "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW"; attribute X_INTERFACE_INFO of s00_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"; attribute X_INTERFACE_INFO of s00_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"; attribute X_INTERFACE_INFO of s00_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"; attribute X_INTERFACE_INFO of s00_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"; attribute X_INTERFACE_INFO of s00_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY"; attribute X_INTERFACE_INFO of s00_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID"; attribute X_INTERFACE_INFO of s00_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY"; attribute X_INTERFACE_PARAMETER of s00_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s00_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID"; attribute X_INTERFACE_INFO of s00_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY"; attribute X_INTERFACE_INFO of s00_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID"; attribute X_INTERFACE_INFO of s00_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"; attribute X_INTERFACE_INFO of s00_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"; attribute X_INTERFACE_INFO of s00_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"; attribute X_INTERFACE_INFO of s00_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"; attribute X_INTERFACE_INFO of s00_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP"; attribute X_INTERFACE_INFO of s00_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA"; attribute X_INTERFACE_INFO of s00_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP"; attribute X_INTERFACE_INFO of s00_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA"; attribute X_INTERFACE_INFO of s00_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"; begin s00_axi_bresp(1) <= \<const0>\; s00_axi_bresp(0) <= \<const0>\; s00_axi_rresp(1) <= \<const0>\; s00_axi_rresp(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 port map ( LEDs_out(7 downto 0) => LEDs_out(7 downto 0), S_AXI_ARREADY => s00_axi_arready, S_AXI_AWREADY => s00_axi_awready, S_AXI_WREADY => s00_axi_wready, s00_axi_aclk => s00_axi_aclk, s00_axi_araddr(1 downto 0) => s00_axi_araddr(3 downto 2), s00_axi_aresetn => s00_axi_aresetn, s00_axi_arvalid => s00_axi_arvalid, s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(3 downto 2), s00_axi_awvalid => s00_axi_awvalid, s00_axi_bready => s00_axi_bready, s00_axi_bvalid => s00_axi_bvalid, s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0), s00_axi_rready => s00_axi_rready, s00_axi_rvalid => s00_axi_rvalid, s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0), s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0), s00_axi_wvalid => s00_axi_wvalid ); end STRUCTURE;

mit

ea2bdc6d80d1efe1ee78e0d30cd09257

offox/offox-fpga-projects

digital-watch/clock_60hz.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity clk60Hz is Port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; clk_out: out STD_LOGIC ); end clk60Hz; architecture Behavioral of clk60Hz is signal temporal: STD_LOGIC; signal counter : integer range 0 to 833333 := 0; begin frequency_divider: process (reset, clk_in) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk_in) then if (counter = 833333) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; clk_out <= temporal; end Behavioral;

gpl-2.0

3f44f46dc903753f6599f1981d0b3481

dawsonjon/FPGA-TX

fpga_tx/bsp_components/serdes_model.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity serdes is port( clk : in std_logic; rst : in std_logic; input_0 : in std_logic; input_1 : in std_logic; input_2 : in std_logic; input_3 : in std_logic; input_4 : in std_logic; input_5 : in std_logic; input_6 : in std_logic; input_7 : in std_logic; output : out std_logic ); end entity serdes; architecture rtl of serdes is begin process begin while True loop wait until rising_edge(clk); output <= input_0; wait for 1.25 ns; output <= input_1; wait for 1.25 ns; output <= input_2; wait for 1.25 ns; output <= input_3; wait for 1.25 ns; output <= input_4; wait for 1.25 ns; output <= input_5; wait for 1.25 ns; output <= input_6; wait for 1.25 ns; output <= input_7; wait for 1.25 ns; end loop; wait; end process; end rtl;

mit

a63ad9bc4397f1769e1055b7ccd7410a

eamadio/fpgaMSP430

fmsp430/misc/fmsp_clock_gate.vhd

------------------------------------------------------------------------------ --! Copyright (C) 2009 , Olivier Girard -- --! Redistribution and use in source and binary forms, with or without --! modification, are permitted provided that the following conditions --! are met: --! * Redistributions of source code must retain the above copyright --! notice, this list of conditions and the following disclaimer. --! * Redistributions in binary form must reproduce the above copyright --! notice, this list of conditions and the following disclaimer in the --! documentation and/or other materials provided with the distribution. --! * Neither the name of the authors nor the names of its contributors --! may be used to endorse or promote products derived from this software --! without specific prior written permission. -- --! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE --! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE --! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE --! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, --! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF --! THE POSSIBILITY OF SUCH DAMAGE -- ------------------------------------------------------------------------------ -- --! @file fmsp_clock_gate.vhd --! --! @brief fpgaMSP430 Generic clock gate cell -- --! @author Olivier Girard, [email protected] --! @author Emmanuel Amadio, [email protected] (VHDL Rewrite) -- ------------------------------------------------------------------------------ --! @version 1 --! @date: 2017-04-21 ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH- entity fmsp_clock_gate is port ( --! INPUTs clk : in std_logic; --! Clock enable : in std_logic; --! Clock enable scan_enable : in std_logic; --! Scan enable (active during scan shifting) --! OUTPUTs gclk : out std_logic --! Gated clock ); end entity fmsp_clock_gate; architecture RTL of fmsp_clock_gate is signal enable_in : std_logic; signal enable_latch : std_logic; begin --============================================================================= --! CLOCK GATE: LATCH + AND --============================================================================= --! Enable clock gate during scan shift --! (the gate itself is checked with the scan capture cycle) enable_in <= enable or scan_enable; --! LATCH the enable signal LATCH_REG : process(clk,enable_in) begin if (not(clk) = '1') then enable_latch <= enable_in; end if; end process LATCH_REG; --! AND gate gclk <= clk and enable_latch; end RTL; --! fmsp_clock_gate

bsd-3-clause

f24575990184e4d5351ad7e023f2ccc9

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_zed_audio_ctrl_0_0/ip_design_zed_audio_ctrl_0_0_sim_netlist.vhdl

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 19:49:32 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode funcsim -- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_zed_audio_ctrl_0_0/ip_design_zed_audio_ctrl_0_0_sim_netlist.vhdl -- Design : ip_design_zed_audio_ctrl_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ip_design_zed_audio_ctrl_0_0_address_decoder is port ( \DataTx_R_reg[0]\ : out STD_LOGIC; \DataTx_R_reg[0]_0\ : out STD_LOGIC; \DataTx_R_reg[0]_1\ : out STD_LOGIC; \DataTx_R_reg[0]_2\ : out STD_LOGIC; \DataTx_R_reg[0]_3\ : out STD_LOGIC; \DataTx_R_reg[0]_4\ : out STD_LOGIC; data_rdy_bit_reg : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_AWREADY : out STD_LOGIC; S_AXI_ARREADY : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); data_rdy_bit_reg_0 : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rvalid_i_reg : out STD_LOGIC; s_axi_bvalid_i_reg : out STD_LOGIC; S_AXI_ACLK : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ARVALID : in STD_LOGIC; s_axi_bvalid_i_reg_0 : in STD_LOGIC; \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_WVALID_0 : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC; S_AXI_ARESETN : in STD_LOGIC; S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_AWVALID : in STD_LOGIC; S_AXI_WVALID : in STD_LOGIC; data_rdy_bit : in STD_LOGIC; \DataTx_R_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 ); \DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC; S_AXI_RREADY : in STD_LOGIC; s_axi_rvalid_i_reg_0 : in STD_LOGIC; S_AXI_BREADY : in STD_LOGIC; s_axi_bvalid_i_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_address_decoder : entity is "address_decoder"; end ip_design_zed_audio_ctrl_0_0_address_decoder; architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_address_decoder is signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC; signal \^datatx_r_reg[0]\ : STD_LOGIC; signal \^datatx_r_reg[0]_0\ : STD_LOGIC; signal \^datatx_r_reg[0]_1\ : STD_LOGIC; signal \^datatx_r_reg[0]_2\ : STD_LOGIC; signal \^datatx_r_reg[0]_3\ : STD_LOGIC; signal \^datatx_r_reg[0]_4\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\ : STD_LOGIC; signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\ : STD_LOGIC; signal S_AXI_ARREADY_INST_0_i_1_n_0 : STD_LOGIC; signal ce_expnd_i_0 : STD_LOGIC; signal ce_expnd_i_1 : STD_LOGIC; signal ce_expnd_i_2 : STD_LOGIC; signal ce_expnd_i_3 : STD_LOGIC; signal ce_expnd_i_4 : STD_LOGIC; signal cs_ce_clr : STD_LOGIC; signal s_axi_bvalid_i0 : STD_LOGIC; signal \s_axi_rdata_i[0]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[0]_i_3_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[0]_i_4_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[10]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[11]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[12]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[13]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[14]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[15]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[16]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[17]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[18]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[19]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[1]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[20]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[21]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[22]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[23]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[23]_i_3_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[23]_i_4_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[2]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[3]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[4]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[5]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[6]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[7]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[8]_i_2_n_0\ : STD_LOGIC; signal \s_axi_rdata_i[9]_i_2_n_0\ : STD_LOGIC; signal s_axi_rvalid_i0 : STD_LOGIC; signal start : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of S_AXI_ARREADY_INST_0 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of S_AXI_AWREADY_INST_0 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of data_rdy_bit_i_2 : label is "soft_lutpair1"; attribute SOFT_HLUTNM of s_axi_bvalid_i_i_2 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_4\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_3\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of s_axi_rvalid_i_i_2 : label is "soft_lutpair0"; begin \DataTx_R_reg[0]\ <= \^datatx_r_reg[0]\; \DataTx_R_reg[0]_0\ <= \^datatx_r_reg[0]_0\; \DataTx_R_reg[0]_1\ <= \^datatx_r_reg[0]_1\; \DataTx_R_reg[0]_2\ <= \^datatx_r_reg[0]_2\; \DataTx_R_reg[0]_3\ <= \^datatx_r_reg[0]_3\; \DataTx_R_reg[0]_4\ <= \^datatx_r_reg[0]_4\; Bus_RNW_reg_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FEFFFFFF02020202" ) port map ( I0 => S_AXI_ARVALID, I1 => Q(0), I2 => Q(1), I3 => S_AXI_AWVALID, I4 => S_AXI_WVALID, I5 => \^datatx_r_reg[0]_4\, O => Bus_RNW_reg_i_1_n_0 ); Bus_RNW_reg_reg: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => '1', D => Bus_RNW_reg_i_1_n_0, Q => \^datatx_r_reg[0]_4\, R => '0' ); \DataTx_L[31]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000004" ) port map ( I0 => \^datatx_r_reg[0]_0\, I1 => \^datatx_r_reg[0]_1\, I2 => \^datatx_r_reg[0]_4\, I3 => \^datatx_r_reg[0]_2\, I4 => \^datatx_r_reg[0]_3\, I5 => \^datatx_r_reg[0]\, O => \DataTx_L_reg[0]\(0) ); \DataTx_R[31]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000004" ) port map ( I0 => \^datatx_r_reg[0]_1\, I1 => \^datatx_r_reg[0]_0\, I2 => \^datatx_r_reg[0]_4\, I3 => \^datatx_r_reg[0]_2\, I4 => \^datatx_r_reg[0]_3\, I5 => \^datatx_r_reg[0]\, O => E(0) ); \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"020202020202FF02" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\, I1 => S_AXI_ARADDR(0), I2 => S_AXI_ARADDR(1), I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\, I4 => S_AXI_AWADDR(0), I5 => S_AXI_AWADDR(1), O => ce_expnd_i_4 ); \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => start, D => ce_expnd_i_4, Q => \^datatx_r_reg[0]_3\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"08080808FF080808" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\, I1 => S_AXI_ARADDR(0), I2 => S_AXI_ARADDR(1), I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\, I4 => S_AXI_AWADDR(0), I5 => S_AXI_AWADDR(1), O => ce_expnd_i_3 ); \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => start, D => ce_expnd_i_3, Q => \^datatx_r_reg[0]_2\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"08080808FF080808" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\, I1 => S_AXI_ARADDR(1), I2 => S_AXI_ARADDR(0), I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\, I4 => S_AXI_AWADDR(1), I5 => S_AXI_AWADDR(0), O => ce_expnd_i_2 ); \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => start, D => ce_expnd_i_2, Q => \^datatx_r_reg[0]_1\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF80808080808080" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\, I1 => S_AXI_ARADDR(0), I2 => S_AXI_ARADDR(1), I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\, I4 => S_AXI_AWADDR(0), I5 => S_AXI_AWADDR(1), O => ce_expnd_i_1 ); \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => S_AXI_ARVALID, I1 => Q(0), I2 => Q(1), I3 => S_AXI_ARADDR(2), O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\ ); \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000040" ) port map ( I0 => S_AXI_ARVALID, I1 => S_AXI_WVALID, I2 => S_AXI_AWVALID, I3 => Q(1), I4 => Q(0), I5 => S_AXI_AWADDR(2), O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\ ); \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => start, D => ce_expnd_i_1, Q => \^datatx_r_reg[0]_0\, R => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"FD" ) port map ( I0 => S_AXI_ARESETN, I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), I2 => S_AXI_ARREADY_INST_0_i_1_n_0, O => cs_ce_clr ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"03020202" ) port map ( I0 => S_AXI_ARVALID, I1 => Q(0), I2 => Q(1), I3 => S_AXI_AWVALID, I4 => S_AXI_WVALID, O => start ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAEAA" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\, I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\, I2 => S_AXI_AWADDR(1), I3 => S_AXI_AWADDR(2), I4 => S_AXI_AWADDR(0), O => ce_expnd_i_0 ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000400" ) port map ( I0 => S_AXI_ARADDR(0), I1 => S_AXI_ARADDR(2), I2 => S_AXI_ARADDR(1), I3 => S_AXI_ARVALID, I4 => Q(0), I5 => Q(1), O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\ ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"00001000" ) port map ( I0 => Q(0), I1 => Q(1), I2 => S_AXI_AWVALID, I3 => S_AXI_WVALID, I4 => S_AXI_ARVALID, O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\ ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => start, D => ce_expnd_i_0, Q => \^datatx_r_reg[0]\, R => cs_ce_clr ); S_AXI_ARREADY_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"F8" ) port map ( I0 => \^datatx_r_reg[0]_4\, I1 => S_AXI_ARREADY_INST_0_i_1_n_0, I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), O => S_AXI_ARREADY ); S_AXI_ARREADY_INST_0_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \^datatx_r_reg[0]\, I1 => \^datatx_r_reg[0]_3\, I2 => \^datatx_r_reg[0]_2\, I3 => \^datatx_r_reg[0]_0\, I4 => \^datatx_r_reg[0]_1\, O => S_AXI_ARREADY_INST_0_i_1_n_0 ); S_AXI_AWREADY_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"F4" ) port map ( I0 => \^datatx_r_reg[0]_4\, I1 => S_AXI_ARREADY_INST_0_i_1_n_0, I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), O => S_AXI_AWREADY ); data_rdy_bit_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \^datatx_r_reg[0]\, I1 => \^datatx_r_reg[0]_3\, I2 => \^datatx_r_reg[0]_2\, I3 => \^datatx_r_reg[0]_4\, O => data_rdy_bit_reg_0 ); data_rdy_bit_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFEFFFF" ) port map ( I0 => \^datatx_r_reg[0]_3\, I1 => \^datatx_r_reg[0]_2\, I2 => \^datatx_r_reg[0]_1\, I3 => \^datatx_r_reg[0]_0\, I4 => \^datatx_r_reg[0]\, I5 => \^datatx_r_reg[0]_4\, O => data_rdy_bit_reg ); s_axi_bvalid_i_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"BA" ) port map ( I0 => s_axi_bvalid_i0, I1 => S_AXI_BREADY, I2 => s_axi_bvalid_i_reg_1, O => s_axi_bvalid_i_reg ); s_axi_bvalid_i_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"0000AE00" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), I1 => S_AXI_ARREADY_INST_0_i_1_n_0, I2 => \^datatx_r_reg[0]_4\, I3 => Q(1), I4 => Q(0), O => s_axi_bvalid_i0 ); \s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFAAEAAAEAAAEAAA" ) port map ( I0 => \s_axi_rdata_i[0]_i_2_n_0\, I1 => data_rdy_bit, I2 => \^datatx_r_reg[0]\, I3 => \s_axi_rdata_i[0]_i_3_n_0\, I4 => \^datatx_r_reg[0]_0\, I5 => \DataTx_R_reg[31]\(0), O => \s_axi_rdata_i_reg[31]\(0) ); \s_axi_rdata_i[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF888F888F888" ) port map ( I0 => \s_axi_rdata_i[0]_i_4_n_0\, I1 => \DataTx_L_reg[31]\(0), I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(0), I4 => \DataRx_L_reg[23]\(0), I5 => \s_axi_rdata_i[23]_i_2_n_0\, O => \s_axi_rdata_i[0]_i_2_n_0\ ); \s_axi_rdata_i[0]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^datatx_r_reg[0]_4\, I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, O => \s_axi_rdata_i[0]_i_3_n_0\ ); \s_axi_rdata_i[0]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I1 => \^datatx_r_reg[0]_4\, I2 => \^datatx_r_reg[0]_1\, O => \s_axi_rdata_i[0]_i_4_n_0\ ); \s_axi_rdata_i[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(10), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(10), I4 => \s_axi_rdata_i[10]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(10) ); \s_axi_rdata_i[10]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(10), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(10), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[10]_i_2_n_0\ ); \s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(11), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(11), I4 => \s_axi_rdata_i[11]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(11) ); \s_axi_rdata_i[11]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(11), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(11), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[11]_i_2_n_0\ ); \s_axi_rdata_i[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(12), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(12), I4 => \s_axi_rdata_i[12]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(12) ); \s_axi_rdata_i[12]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(12), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(12), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[12]_i_2_n_0\ ); \s_axi_rdata_i[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(13), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(13), I4 => \s_axi_rdata_i[13]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(13) ); \s_axi_rdata_i[13]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(13), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(13), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[13]_i_2_n_0\ ); \s_axi_rdata_i[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(14), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(14), I4 => \s_axi_rdata_i[14]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(14) ); \s_axi_rdata_i[14]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(14), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(14), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[14]_i_2_n_0\ ); \s_axi_rdata_i[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(15), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(15), I4 => \s_axi_rdata_i[15]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(15) ); \s_axi_rdata_i[15]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(15), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(15), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[15]_i_2_n_0\ ); \s_axi_rdata_i[16]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(16), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(16), I4 => \s_axi_rdata_i[16]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(16) ); \s_axi_rdata_i[16]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(16), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(16), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[16]_i_2_n_0\ ); \s_axi_rdata_i[17]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(17), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(17), I4 => \s_axi_rdata_i[17]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(17) ); \s_axi_rdata_i[17]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(17), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(17), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[17]_i_2_n_0\ ); \s_axi_rdata_i[18]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(18), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(18), I4 => \s_axi_rdata_i[18]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(18) ); \s_axi_rdata_i[18]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(18), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(18), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[18]_i_2_n_0\ ); \s_axi_rdata_i[19]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(19), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(19), I4 => \s_axi_rdata_i[19]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(19) ); \s_axi_rdata_i[19]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(19), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(19), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[19]_i_2_n_0\ ); \s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(1), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(1), I4 => \s_axi_rdata_i[1]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(1) ); \s_axi_rdata_i[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(1), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(1), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[1]_i_2_n_0\ ); \s_axi_rdata_i[20]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(20), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(20), I4 => \s_axi_rdata_i[20]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(20) ); \s_axi_rdata_i[20]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(20), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(20), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[20]_i_2_n_0\ ); \s_axi_rdata_i[21]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(21), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(21), I4 => \s_axi_rdata_i[21]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(21) ); \s_axi_rdata_i[21]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(21), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(21), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[21]_i_2_n_0\ ); \s_axi_rdata_i[22]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(22), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(22), I4 => \s_axi_rdata_i[22]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(22) ); \s_axi_rdata_i[22]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(22), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(22), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[22]_i_2_n_0\ ); \s_axi_rdata_i[23]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(23), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(23), I4 => \s_axi_rdata_i[23]_i_4_n_0\, O => \s_axi_rdata_i_reg[31]\(23) ); \s_axi_rdata_i[23]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I1 => \^datatx_r_reg[0]_4\, I2 => \^datatx_r_reg[0]_3\, O => \s_axi_rdata_i[23]_i_2_n_0\ ); \s_axi_rdata_i[23]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I1 => \^datatx_r_reg[0]_4\, I2 => \^datatx_r_reg[0]_2\, O => \s_axi_rdata_i[23]_i_3_n_0\ ); \s_axi_rdata_i[23]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(23), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(23), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[23]_i_4_n_0\ ); \s_axi_rdata_i[24]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(24), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(24), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i_reg[31]\(24) ); \s_axi_rdata_i[25]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(25), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(25), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i_reg[31]\(25) ); \s_axi_rdata_i[26]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(26), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(26), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i_reg[31]\(26) ); \s_axi_rdata_i[27]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(27), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(27), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i_reg[31]\(27) ); \s_axi_rdata_i[28]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(28), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(28), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i_reg[31]\(28) ); \s_axi_rdata_i[29]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(29), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(29), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i_reg[31]\(29) ); \s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(2), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(2), I4 => \s_axi_rdata_i[2]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(2) ); \s_axi_rdata_i[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(2), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(2), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[2]_i_2_n_0\ ); \s_axi_rdata_i[30]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(30), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(30), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i_reg[31]\(30) ); \s_axi_rdata_i[31]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(31), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(31), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i_reg[31]\(31) ); \s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(3), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(3), I4 => \s_axi_rdata_i[3]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(3) ); \s_axi_rdata_i[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(3), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(3), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[3]_i_2_n_0\ ); \s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(4), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(4), I4 => \s_axi_rdata_i[4]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(4) ); \s_axi_rdata_i[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(4), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(4), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[4]_i_2_n_0\ ); \s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(5), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(5), I4 => \s_axi_rdata_i[5]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(5) ); \s_axi_rdata_i[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(5), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(5), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[5]_i_2_n_0\ ); \s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(6), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(6), I4 => \s_axi_rdata_i[6]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(6) ); \s_axi_rdata_i[6]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(6), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(6), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[6]_i_2_n_0\ ); \s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(7), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(7), I4 => \s_axi_rdata_i[7]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(7) ); \s_axi_rdata_i[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(7), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(7), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[7]_i_2_n_0\ ); \s_axi_rdata_i[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(8), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(8), I4 => \s_axi_rdata_i[8]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(8) ); \s_axi_rdata_i[8]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(8), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(8), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[8]_i_2_n_0\ ); \s_axi_rdata_i[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF888" ) port map ( I0 => \DataRx_L_reg[23]\(9), I1 => \s_axi_rdata_i[23]_i_2_n_0\, I2 => \s_axi_rdata_i[23]_i_3_n_0\, I3 => \DataRx_R_reg[23]\(9), I4 => \s_axi_rdata_i[9]_i_2_n_0\, O => \s_axi_rdata_i_reg[31]\(9) ); \s_axi_rdata_i[9]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"F800000088000000" ) port map ( I0 => \DataTx_L_reg[31]\(9), I1 => \^datatx_r_reg[0]_1\, I2 => \DataTx_R_reg[31]\(9), I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\, I4 => \^datatx_r_reg[0]_4\, I5 => \^datatx_r_reg[0]_0\, O => \s_axi_rdata_i[9]_i_2_n_0\ ); s_axi_rvalid_i_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"BA" ) port map ( I0 => s_axi_rvalid_i0, I1 => S_AXI_RREADY, I2 => s_axi_rvalid_i_reg_0, O => s_axi_rvalid_i_reg ); s_axi_rvalid_i_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"0000EA00" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), I1 => S_AXI_ARREADY_INST_0_i_1_n_0, I2 => \^datatx_r_reg[0]_4\, I3 => Q(0), I4 => Q(1), O => s_axi_rvalid_i0 ); \state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FFF4" ) port map ( I0 => Q(1), I1 => S_AXI_ARVALID, I2 => s_axi_bvalid_i0, I3 => s_axi_bvalid_i_reg_0, O => D(0) ); \state[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF4454" ) port map ( I0 => Q(0), I1 => Q(1), I2 => S_AXI_WVALID_0, I3 => S_AXI_ARVALID, I4 => \state_reg[1]\, I5 => s_axi_rvalid_i0, O => D(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ip_design_zed_audio_ctrl_0_0_iis_deser is port ( lrclk_d1 : out STD_LOGIC; sclk_d1 : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \rdata_reg_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \bit_cntr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); sdata_reg_reg : out STD_LOGIC; \FSM_onehot_iis_state_reg[0]\ : out STD_LOGIC; data_rdy_bit_reg : out STD_LOGIC; \FSM_onehot_iis_state_reg[0]_0\ : out STD_LOGIC; \DataRx_L_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); \DataRx_R_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACLK : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); data_rdy_bit : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC; S_AXI_ARESETN : in STD_LOGIC; SDATA_I : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_iis_deser : entity is "iis_deser"; end ip_design_zed_audio_ctrl_0_0_iis_deser; architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_iis_deser is signal \^datarx_l_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 ); signal \^datarx_r_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 ); signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \FSM_sequential_iis_state[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_iis_state[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_iis_state[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_iis_state[2]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_iis_state[2]_i_3_n_0\ : STD_LOGIC; signal \FSM_sequential_iis_state[2]_i_4_n_0\ : STD_LOGIC; signal \bit_cntr[4]_i_1_n_0\ : STD_LOGIC; signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal bit_rdy : STD_LOGIC; signal data_rdy_bit_i_4_n_0 : STD_LOGIC; signal eqOp : STD_LOGIC; signal iis_state : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of iis_state : signal is "yes"; signal ldata_reg : STD_LOGIC; signal ldata_reg0 : STD_LOGIC; signal \^lrclk_d1\ : STD_LOGIC; signal \plusOp__1\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal rdata_reg0 : STD_LOGIC; signal \^sclk_d1\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \DataRx_L[23]_i_2\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_5\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \FSM_sequential_iis_state[2]_i_4\ : label is "soft_lutpair8"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[0]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110"; attribute KEEP : string; attribute KEEP of \FSM_sequential_iis_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[1]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110"; attribute KEEP of \FSM_sequential_iis_state_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[2]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110"; attribute KEEP of \FSM_sequential_iis_state_reg[2]\ : label is "yes"; attribute SOFT_HLUTNM of \bit_cntr[0]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \bit_cntr[1]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \bit_cntr[2]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \bit_cntr[3]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \bit_cntr[4]_i_2__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \bit_cntr[4]_i_3\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of sdata_reg_i_2 : label is "soft_lutpair10"; begin \DataRx_L_reg[23]\(23 downto 0) <= \^datarx_l_reg[23]\(23 downto 0); \DataRx_R_reg[23]\(23 downto 0) <= \^datarx_r_reg[23]\(23 downto 0); E(0) <= \^e\(0); lrclk_d1 <= \^lrclk_d1\; sclk_d1 <= \^sclk_d1\; \DataRx_L[23]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => eqOp, I1 => iis_state(2), I2 => iis_state(1), I3 => iis_state(0), O => \^e\(0) ); \DataRx_L[23]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00000020" ) port map ( I0 => \bit_cntr_reg__0\(3), I1 => \bit_cntr_reg__0\(0), I2 => \bit_cntr_reg__0\(4), I3 => \bit_cntr_reg__0\(1), I4 => \bit_cntr_reg__0\(2), O => eqOp ); \FSM_onehot_iis_state[4]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^lrclk_d1\, I1 => Q(1), I2 => \out\(1), O => \FSM_onehot_iis_state_reg[0]_0\ ); \FSM_onehot_iis_state[4]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"DF" ) port map ( I0 => \^lrclk_d1\, I1 => Q(1), I2 => \out\(0), O => \FSM_onehot_iis_state_reg[0]\ ); \FSM_sequential_iis_state[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"75777F7745444044" ) port map ( I0 => iis_state(0), I1 => \FSM_sequential_iis_state[2]_i_2_n_0\, I2 => iis_state(1), I3 => iis_state(2), I4 => \FSM_sequential_iis_state[2]_i_3_n_0\, I5 => iis_state(0), O => \FSM_sequential_iis_state[0]_i_1_n_0\ ); \FSM_sequential_iis_state[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"3A7B3F7B0A480048" ) port map ( I0 => iis_state(0), I1 => \FSM_sequential_iis_state[2]_i_2_n_0\, I2 => iis_state(1), I3 => iis_state(2), I4 => \FSM_sequential_iis_state[2]_i_3_n_0\, I5 => iis_state(1), O => \FSM_sequential_iis_state[1]_i_1_n_0\ ); \FSM_sequential_iis_state[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"3FB33FB30F800080" ) port map ( I0 => iis_state(0), I1 => \FSM_sequential_iis_state[2]_i_2_n_0\, I2 => iis_state(1), I3 => iis_state(2), I4 => \FSM_sequential_iis_state[2]_i_3_n_0\, I5 => iis_state(2), O => \FSM_sequential_iis_state[2]_i_1_n_0\ ); \FSM_sequential_iis_state[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFA33FF000A330F" ) port map ( I0 => bit_rdy, I1 => \FSM_sequential_iis_state[2]_i_4_n_0\, I2 => iis_state(2), I3 => iis_state(0), I4 => iis_state(1), I5 => eqOp, O => \FSM_sequential_iis_state[2]_i_2_n_0\ ); \FSM_sequential_iis_state[2]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"22A222A2EEAE22A2" ) port map ( I0 => bit_rdy, I1 => iis_state(2), I2 => iis_state(0), I3 => iis_state(1), I4 => Q(1), I5 => \^lrclk_d1\, O => \FSM_sequential_iis_state[2]_i_3_n_0\ ); \FSM_sequential_iis_state[2]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => Q(1), I1 => \^lrclk_d1\, O => \FSM_sequential_iis_state[2]_i_4_n_0\ ); \FSM_sequential_iis_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \FSM_sequential_iis_state[0]_i_1_n_0\, Q => iis_state(0), R => '0' ); \FSM_sequential_iis_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \FSM_sequential_iis_state[1]_i_1_n_0\, Q => iis_state(1), R => '0' ); \FSM_sequential_iis_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \FSM_sequential_iis_state[2]_i_1_n_0\, Q => iis_state(2), R => '0' ); \bit_cntr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \bit_cntr_reg__0\(0), O => \plusOp__1\(0) ); \bit_cntr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bit_cntr_reg__0\(0), I1 => \bit_cntr_reg__0\(1), O => \plusOp__1\(1) ); \bit_cntr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \bit_cntr_reg__0\(1), I1 => \bit_cntr_reg__0\(0), I2 => \bit_cntr_reg__0\(2), O => \plusOp__1\(2) ); \bit_cntr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6CCC" ) port map ( I0 => \bit_cntr_reg__0\(1), I1 => \bit_cntr_reg__0\(3), I2 => \bit_cntr_reg__0\(0), I3 => \bit_cntr_reg__0\(2), O => \plusOp__1\(3) ); \bit_cntr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"D7" ) port map ( I0 => iis_state(1), I1 => iis_state(0), I2 => iis_state(2), O => \bit_cntr[4]_i_1_n_0\ ); \bit_cntr[4]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => Q(0), I1 => \^sclk_d1\, O => bit_rdy ); \bit_cntr[4]_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^sclk_d1\, I1 => Q(0), O => \bit_cntr_reg[4]_0\(0) ); \bit_cntr[4]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"78F0F0F0" ) port map ( I0 => \bit_cntr_reg__0\(3), I1 => \bit_cntr_reg__0\(2), I2 => \bit_cntr_reg__0\(4), I3 => \bit_cntr_reg__0\(1), I4 => \bit_cntr_reg__0\(0), O => \plusOp__1\(4) ); \bit_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => bit_rdy, D => \plusOp__1\(0), Q => \bit_cntr_reg__0\(0), R => \bit_cntr[4]_i_1_n_0\ ); \bit_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => bit_rdy, D => \plusOp__1\(1), Q => \bit_cntr_reg__0\(1), R => \bit_cntr[4]_i_1_n_0\ ); \bit_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => bit_rdy, D => \plusOp__1\(2), Q => \bit_cntr_reg__0\(2), R => \bit_cntr[4]_i_1_n_0\ ); \bit_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => bit_rdy, D => \plusOp__1\(3), Q => \bit_cntr_reg__0\(3), R => \bit_cntr[4]_i_1_n_0\ ); \bit_cntr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => bit_rdy, D => \plusOp__1\(4), Q => \bit_cntr_reg__0\(4), R => \bit_cntr[4]_i_1_n_0\ ); data_rdy_bit_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"CC00EA0000000000" ) port map ( I0 => data_rdy_bit, I1 => \^e\(0), I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\, I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\, I4 => data_rdy_bit_i_4_n_0, I5 => S_AXI_ARESETN, O => data_rdy_bit_reg ); data_rdy_bit_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000090000000" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, I2 => eqOp, I3 => iis_state(2), I4 => iis_state(1), I5 => iis_state(0), O => data_rdy_bit_i_4_n_0 ); \ldata_reg[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => iis_state(1), I1 => iis_state(0), I2 => iis_state(2), O => ldata_reg ); \ldata_reg[23]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00004000" ) port map ( I0 => iis_state(2), I1 => iis_state(0), I2 => iis_state(1), I3 => Q(0), I4 => \^sclk_d1\, O => ldata_reg0 ); \ldata_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => SDATA_I, Q => \^datarx_l_reg[23]\(0), R => ldata_reg ); \ldata_reg_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(9), Q => \^datarx_l_reg[23]\(10), R => ldata_reg ); \ldata_reg_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(10), Q => \^datarx_l_reg[23]\(11), R => ldata_reg ); \ldata_reg_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(11), Q => \^datarx_l_reg[23]\(12), R => ldata_reg ); \ldata_reg_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(12), Q => \^datarx_l_reg[23]\(13), R => ldata_reg ); \ldata_reg_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(13), Q => \^datarx_l_reg[23]\(14), R => ldata_reg ); \ldata_reg_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(14), Q => \^datarx_l_reg[23]\(15), R => ldata_reg ); \ldata_reg_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(15), Q => \^datarx_l_reg[23]\(16), R => ldata_reg ); \ldata_reg_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(16), Q => \^datarx_l_reg[23]\(17), R => ldata_reg ); \ldata_reg_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(17), Q => \^datarx_l_reg[23]\(18), R => ldata_reg ); \ldata_reg_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(18), Q => \^datarx_l_reg[23]\(19), R => ldata_reg ); \ldata_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(0), Q => \^datarx_l_reg[23]\(1), R => ldata_reg ); \ldata_reg_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(19), Q => \^datarx_l_reg[23]\(20), R => ldata_reg ); \ldata_reg_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(20), Q => \^datarx_l_reg[23]\(21), R => ldata_reg ); \ldata_reg_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(21), Q => \^datarx_l_reg[23]\(22), R => ldata_reg ); \ldata_reg_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(22), Q => \^datarx_l_reg[23]\(23), R => ldata_reg ); \ldata_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(1), Q => \^datarx_l_reg[23]\(2), R => ldata_reg ); \ldata_reg_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(2), Q => \^datarx_l_reg[23]\(3), R => ldata_reg ); \ldata_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(3), Q => \^datarx_l_reg[23]\(4), R => ldata_reg ); \ldata_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(4), Q => \^datarx_l_reg[23]\(5), R => ldata_reg ); \ldata_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(5), Q => \^datarx_l_reg[23]\(6), R => ldata_reg ); \ldata_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(6), Q => \^datarx_l_reg[23]\(7), R => ldata_reg ); \ldata_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(7), Q => \^datarx_l_reg[23]\(8), R => ldata_reg ); \ldata_reg_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => ldata_reg0, D => \^datarx_l_reg[23]\(8), Q => \^datarx_l_reg[23]\(9), R => ldata_reg ); lrclk_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => Q(1), Q => \^lrclk_d1\, R => '0' ); \rdata_reg[23]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00004000" ) port map ( I0 => iis_state(0), I1 => iis_state(1), I2 => iis_state(2), I3 => Q(0), I4 => \^sclk_d1\, O => rdata_reg0 ); \rdata_reg[23]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"4040FF4040404040" ) port map ( I0 => Q(0), I1 => \^sclk_d1\, I2 => \out\(2), I3 => \out\(0), I4 => Q(1), I5 => \^lrclk_d1\, O => \rdata_reg_reg[23]_0\(0) ); \rdata_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => SDATA_I, Q => \^datarx_r_reg[23]\(0), R => ldata_reg ); \rdata_reg_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(9), Q => \^datarx_r_reg[23]\(10), R => ldata_reg ); \rdata_reg_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(10), Q => \^datarx_r_reg[23]\(11), R => ldata_reg ); \rdata_reg_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(11), Q => \^datarx_r_reg[23]\(12), R => ldata_reg ); \rdata_reg_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(12), Q => \^datarx_r_reg[23]\(13), R => ldata_reg ); \rdata_reg_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(13), Q => \^datarx_r_reg[23]\(14), R => ldata_reg ); \rdata_reg_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(14), Q => \^datarx_r_reg[23]\(15), R => ldata_reg ); \rdata_reg_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(15), Q => \^datarx_r_reg[23]\(16), R => ldata_reg ); \rdata_reg_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(16), Q => \^datarx_r_reg[23]\(17), R => ldata_reg ); \rdata_reg_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(17), Q => \^datarx_r_reg[23]\(18), R => ldata_reg ); \rdata_reg_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(18), Q => \^datarx_r_reg[23]\(19), R => ldata_reg ); \rdata_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(0), Q => \^datarx_r_reg[23]\(1), R => ldata_reg ); \rdata_reg_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(19), Q => \^datarx_r_reg[23]\(20), R => ldata_reg ); \rdata_reg_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(20), Q => \^datarx_r_reg[23]\(21), R => ldata_reg ); \rdata_reg_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(21), Q => \^datarx_r_reg[23]\(22), R => ldata_reg ); \rdata_reg_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(22), Q => \^datarx_r_reg[23]\(23), R => ldata_reg ); \rdata_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(1), Q => \^datarx_r_reg[23]\(2), R => ldata_reg ); \rdata_reg_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(2), Q => \^datarx_r_reg[23]\(3), R => ldata_reg ); \rdata_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(3), Q => \^datarx_r_reg[23]\(4), R => ldata_reg ); \rdata_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(4), Q => \^datarx_r_reg[23]\(5), R => ldata_reg ); \rdata_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(5), Q => \^datarx_r_reg[23]\(6), R => ldata_reg ); \rdata_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(6), Q => \^datarx_r_reg[23]\(7), R => ldata_reg ); \rdata_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(7), Q => \^datarx_r_reg[23]\(8), R => ldata_reg ); \rdata_reg_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => rdata_reg0, D => \^datarx_r_reg[23]\(8), Q => \^datarx_r_reg[23]\(9), R => ldata_reg ); sclk_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => Q(0), Q => \^sclk_d1\, R => '0' ); sdata_reg_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => Q(0), I1 => \^sclk_d1\, O => sdata_reg_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ip_design_zed_audio_ctrl_0_0_iis_ser is port ( SDATA_O : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACLK : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); sclk_d1 : in STD_LOGIC; lrclk_d1 : in STD_LOGIC; \DataTx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 ); \DataTx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 ); \clk_cntr_reg[4]\ : in STD_LOGIC; lrclk_d1_reg : in STD_LOGIC; lrclk_d1_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); sclk_d1_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_iis_ser : entity is "iis_ser"; end ip_design_zed_audio_ctrl_0_0_iis_ser; architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_iis_ser is signal \FSM_onehot_iis_state[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_iis_state[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_iis_state[3]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_iis_state[4]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_iis_state[4]_i_2_n_0\ : STD_LOGIC; signal \^sdata_o\ : STD_LOGIC; signal \bit_cntr[4]_i_1__0_n_0\ : STD_LOGIC; signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal eqOp : STD_LOGIC; signal ldata_reg : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of ldata_reg : signal is "yes"; signal \ldata_reg[0]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[10]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[11]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[12]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[13]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[14]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[15]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[16]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[17]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[18]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[19]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[1]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[20]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[21]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[22]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[23]_i_1__0_n_0\ : STD_LOGIC; signal \ldata_reg[23]_i_2__0_n_0\ : STD_LOGIC; signal \ldata_reg[2]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[3]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[4]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[5]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[6]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[7]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[8]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg[9]_i_1_n_0\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[0]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[10]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[11]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[12]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[13]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[14]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[15]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[16]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[17]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[18]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[19]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[1]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[20]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[21]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[22]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[2]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[3]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[4]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[5]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[6]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[7]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[8]\ : STD_LOGIC; signal \ldata_reg_reg_n_0_[9]\ : STD_LOGIC; signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP of \^out\ : signal is "yes"; signal p_0_in2_in : STD_LOGIC; attribute RTL_KEEP of p_0_in2_in : signal is "yes"; signal p_1_in : STD_LOGIC_VECTOR ( 23 downto 0 ); signal p_2_in : STD_LOGIC; signal \plusOp__2\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \rdata_reg_reg_n_0_[0]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[10]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[11]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[12]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[13]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[14]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[15]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[16]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[17]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[18]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[19]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[1]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[20]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[21]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[22]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[23]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[2]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[3]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[4]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[5]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[6]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[7]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[8]\ : STD_LOGIC; signal \rdata_reg_reg_n_0_[9]\ : STD_LOGIC; signal sdata_reg_i_1_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_4\ : label is "soft_lutpair11"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[0]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000"; attribute KEEP : string; attribute KEEP of \FSM_onehot_iis_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[1]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000"; attribute KEEP of \FSM_onehot_iis_state_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[2]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000"; attribute KEEP of \FSM_onehot_iis_state_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[3]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000"; attribute KEEP of \FSM_onehot_iis_state_reg[3]\ : label is "yes"; attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[4]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000"; attribute KEEP of \FSM_onehot_iis_state_reg[4]\ : label is "yes"; attribute SOFT_HLUTNM of \bit_cntr[0]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \bit_cntr[1]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \bit_cntr[2]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \bit_cntr[3]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \bit_cntr[4]_i_3__0\ : label is "soft_lutpair11"; begin SDATA_O <= \^sdata_o\; \out\(2 downto 0) <= \^out\(2 downto 0); \FSM_onehot_iis_state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAABA" ) port map ( I0 => ldata_reg, I1 => p_0_in2_in, I2 => \^out\(2), I3 => \^out\(1), I4 => \^out\(0), O => \FSM_onehot_iis_state[1]_i_1_n_0\ ); \FSM_onehot_iis_state[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0ACA" ) port map ( I0 => p_0_in2_in, I1 => \^out\(0), I2 => \FSM_onehot_iis_state[4]_i_1_n_0\, I3 => ldata_reg, O => \FSM_onehot_iis_state[2]_i_1_n_0\ ); \FSM_onehot_iis_state[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => p_0_in2_in, I1 => ldata_reg, I2 => \^out\(0), O => \FSM_onehot_iis_state[3]_i_1_n_0\ ); \FSM_onehot_iis_state[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFEEFFFFFEEEFFFF" ) port map ( I0 => ldata_reg, I1 => lrclk_d1_reg, I2 => \^out\(2), I3 => eqOp, I4 => lrclk_d1_reg_0, I5 => p_0_in2_in, O => \FSM_onehot_iis_state[4]_i_1_n_0\ ); \FSM_onehot_iis_state[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0010" ) port map ( I0 => ldata_reg, I1 => p_0_in2_in, I2 => \^out\(1), I3 => \^out\(0), O => \FSM_onehot_iis_state[4]_i_2_n_0\ ); \FSM_onehot_iis_state[4]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"02000000" ) port map ( I0 => \bit_cntr_reg__0\(0), I1 => \bit_cntr_reg__0\(1), I2 => \bit_cntr_reg__0\(2), I3 => \bit_cntr_reg__0\(4), I4 => \bit_cntr_reg__0\(3), O => eqOp ); \FSM_onehot_iis_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => S_AXI_ACLK, CE => \FSM_onehot_iis_state[4]_i_1_n_0\, D => '0', Q => ldata_reg, R => '0' ); \FSM_onehot_iis_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \FSM_onehot_iis_state[4]_i_1_n_0\, D => \FSM_onehot_iis_state[1]_i_1_n_0\, Q => \^out\(0), R => '0' ); \FSM_onehot_iis_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \FSM_onehot_iis_state[2]_i_1_n_0\, Q => p_0_in2_in, R => '0' ); \FSM_onehot_iis_state_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \FSM_onehot_iis_state[4]_i_1_n_0\, D => \FSM_onehot_iis_state[3]_i_1_n_0\, Q => \^out\(1), R => '0' ); \FSM_onehot_iis_state_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \FSM_onehot_iis_state[4]_i_1_n_0\, D => \FSM_onehot_iis_state[4]_i_2_n_0\, Q => \^out\(2), R => '0' ); \bit_cntr[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \bit_cntr_reg__0\(0), O => \plusOp__2\(0) ); \bit_cntr[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bit_cntr_reg__0\(0), I1 => \bit_cntr_reg__0\(1), O => \plusOp__2\(1) ); \bit_cntr[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \bit_cntr_reg__0\(1), I1 => \bit_cntr_reg__0\(0), I2 => \bit_cntr_reg__0\(2), O => \plusOp__2\(2) ); \bit_cntr[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \bit_cntr_reg__0\(2), I1 => \bit_cntr_reg__0\(0), I2 => \bit_cntr_reg__0\(1), I3 => \bit_cntr_reg__0\(3), O => \plusOp__2\(3) ); \bit_cntr[4]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^out\(2), I1 => p_0_in2_in, O => \bit_cntr[4]_i_1__0_n_0\ ); \bit_cntr[4]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \bit_cntr_reg__0\(3), I1 => \bit_cntr_reg__0\(1), I2 => \bit_cntr_reg__0\(0), I3 => \bit_cntr_reg__0\(2), I4 => \bit_cntr_reg__0\(4), O => \plusOp__2\(4) ); \bit_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => sclk_d1_reg(0), D => \plusOp__2\(0), Q => \bit_cntr_reg__0\(0), R => \bit_cntr[4]_i_1__0_n_0\ ); \bit_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => sclk_d1_reg(0), D => \plusOp__2\(1), Q => \bit_cntr_reg__0\(1), R => \bit_cntr[4]_i_1__0_n_0\ ); \bit_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => sclk_d1_reg(0), D => \plusOp__2\(2), Q => \bit_cntr_reg__0\(2), R => \bit_cntr[4]_i_1__0_n_0\ ); \bit_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => sclk_d1_reg(0), D => \plusOp__2\(3), Q => \bit_cntr_reg__0\(3), R => \bit_cntr[4]_i_1__0_n_0\ ); \bit_cntr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => sclk_d1_reg(0), D => \plusOp__2\(4), Q => \bit_cntr_reg__0\(4), R => \bit_cntr[4]_i_1__0_n_0\ ); \ldata_reg[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => \DataTx_L_reg[23]\(0), I1 => \^out\(0), I2 => Q(1), I3 => lrclk_d1, O => \ldata_reg[0]_i_1_n_0\ ); \ldata_reg[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[9]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(10), O => \ldata_reg[10]_i_1_n_0\ ); \ldata_reg[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[10]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(11), O => \ldata_reg[11]_i_1_n_0\ ); \ldata_reg[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[11]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(12), O => \ldata_reg[12]_i_1_n_0\ ); \ldata_reg[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[12]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(13), O => \ldata_reg[13]_i_1_n_0\ ); \ldata_reg[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[13]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(14), O => \ldata_reg[14]_i_1_n_0\ ); \ldata_reg[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[14]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(15), O => \ldata_reg[15]_i_1_n_0\ ); \ldata_reg[16]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[15]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(16), O => \ldata_reg[16]_i_1_n_0\ ); \ldata_reg[17]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[16]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(17), O => \ldata_reg[17]_i_1_n_0\ ); \ldata_reg[18]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[17]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(18), O => \ldata_reg[18]_i_1_n_0\ ); \ldata_reg[19]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[18]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(19), O => \ldata_reg[19]_i_1_n_0\ ); \ldata_reg[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[0]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(1), O => \ldata_reg[1]_i_1_n_0\ ); \ldata_reg[20]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[19]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(20), O => \ldata_reg[20]_i_1_n_0\ ); \ldata_reg[21]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[20]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(21), O => \ldata_reg[21]_i_1_n_0\ ); \ldata_reg[22]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[21]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(22), O => \ldata_reg[22]_i_1_n_0\ ); \ldata_reg[23]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"2020FF2020202020" ) port map ( I0 => p_0_in2_in, I1 => Q(0), I2 => sclk_d1, I3 => \^out\(0), I4 => Q(1), I5 => lrclk_d1, O => \ldata_reg[23]_i_1__0_n_0\ ); \ldata_reg[23]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[22]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(23), O => \ldata_reg[23]_i_2__0_n_0\ ); \ldata_reg[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[1]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(2), O => \ldata_reg[2]_i_1_n_0\ ); \ldata_reg[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[2]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(3), O => \ldata_reg[3]_i_1_n_0\ ); \ldata_reg[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[3]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(4), O => \ldata_reg[4]_i_1_n_0\ ); \ldata_reg[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[4]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(5), O => \ldata_reg[5]_i_1_n_0\ ); \ldata_reg[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[5]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(6), O => \ldata_reg[6]_i_1_n_0\ ); \ldata_reg[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[6]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(7), O => \ldata_reg[7]_i_1_n_0\ ); \ldata_reg[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[7]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(8), O => \ldata_reg[8]_i_1_n_0\ ); \ldata_reg[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \ldata_reg_reg_n_0_[8]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_L_reg[23]\(9), O => \ldata_reg[9]_i_1_n_0\ ); \ldata_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[0]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[0]\, R => ldata_reg ); \ldata_reg_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[10]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[10]\, R => ldata_reg ); \ldata_reg_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[11]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[11]\, R => ldata_reg ); \ldata_reg_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[12]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[12]\, R => ldata_reg ); \ldata_reg_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[13]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[13]\, R => ldata_reg ); \ldata_reg_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[14]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[14]\, R => ldata_reg ); \ldata_reg_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[15]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[15]\, R => ldata_reg ); \ldata_reg_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[16]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[16]\, R => ldata_reg ); \ldata_reg_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[17]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[17]\, R => ldata_reg ); \ldata_reg_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[18]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[18]\, R => ldata_reg ); \ldata_reg_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[19]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[19]\, R => ldata_reg ); \ldata_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[1]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[1]\, R => ldata_reg ); \ldata_reg_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[20]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[20]\, R => ldata_reg ); \ldata_reg_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[21]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[21]\, R => ldata_reg ); \ldata_reg_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[22]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[22]\, R => ldata_reg ); \ldata_reg_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[23]_i_2__0_n_0\, Q => p_2_in, R => ldata_reg ); \ldata_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[2]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[2]\, R => ldata_reg ); \ldata_reg_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[3]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[3]\, R => ldata_reg ); \ldata_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[4]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[4]\, R => ldata_reg ); \ldata_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[5]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[5]\, R => ldata_reg ); \ldata_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[6]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[6]\, R => ldata_reg ); \ldata_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[7]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[7]\, R => ldata_reg ); \ldata_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[8]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[8]\, R => ldata_reg ); \ldata_reg_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \ldata_reg[23]_i_1__0_n_0\, D => \ldata_reg[9]_i_1_n_0\, Q => \ldata_reg_reg_n_0_[9]\, R => ldata_reg ); \rdata_reg[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => \DataTx_R_reg[23]\(0), I1 => \^out\(0), I2 => Q(1), I3 => lrclk_d1, O => p_1_in(0) ); \rdata_reg[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[9]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(10), O => p_1_in(10) ); \rdata_reg[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[10]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(11), O => p_1_in(11) ); \rdata_reg[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[11]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(12), O => p_1_in(12) ); \rdata_reg[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[12]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(13), O => p_1_in(13) ); \rdata_reg[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[13]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(14), O => p_1_in(14) ); \rdata_reg[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[14]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(15), O => p_1_in(15) ); \rdata_reg[16]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[15]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(16), O => p_1_in(16) ); \rdata_reg[17]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[16]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(17), O => p_1_in(17) ); \rdata_reg[18]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[17]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(18), O => p_1_in(18) ); \rdata_reg[19]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[18]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(19), O => p_1_in(19) ); \rdata_reg[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[0]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(1), O => p_1_in(1) ); \rdata_reg[20]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[19]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(20), O => p_1_in(20) ); \rdata_reg[21]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[20]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(21), O => p_1_in(21) ); \rdata_reg[22]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[21]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(22), O => p_1_in(22) ); \rdata_reg[23]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[22]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(23), O => p_1_in(23) ); \rdata_reg[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[1]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(2), O => p_1_in(2) ); \rdata_reg[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[2]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(3), O => p_1_in(3) ); \rdata_reg[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[3]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(4), O => p_1_in(4) ); \rdata_reg[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[4]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(5), O => p_1_in(5) ); \rdata_reg[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[5]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(6), O => p_1_in(6) ); \rdata_reg[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[6]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(7), O => p_1_in(7) ); \rdata_reg[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[7]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(8), O => p_1_in(8) ); \rdata_reg[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AEAAA2AA" ) port map ( I0 => \rdata_reg_reg_n_0_[8]\, I1 => lrclk_d1, I2 => Q(1), I3 => \^out\(0), I4 => \DataTx_R_reg[23]\(9), O => p_1_in(9) ); \rdata_reg_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(0), Q => \rdata_reg_reg_n_0_[0]\, R => ldata_reg ); \rdata_reg_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(10), Q => \rdata_reg_reg_n_0_[10]\, R => ldata_reg ); \rdata_reg_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(11), Q => \rdata_reg_reg_n_0_[11]\, R => ldata_reg ); \rdata_reg_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(12), Q => \rdata_reg_reg_n_0_[12]\, R => ldata_reg ); \rdata_reg_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(13), Q => \rdata_reg_reg_n_0_[13]\, R => ldata_reg ); \rdata_reg_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(14), Q => \rdata_reg_reg_n_0_[14]\, R => ldata_reg ); \rdata_reg_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(15), Q => \rdata_reg_reg_n_0_[15]\, R => ldata_reg ); \rdata_reg_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(16), Q => \rdata_reg_reg_n_0_[16]\, R => ldata_reg ); \rdata_reg_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(17), Q => \rdata_reg_reg_n_0_[17]\, R => ldata_reg ); \rdata_reg_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(18), Q => \rdata_reg_reg_n_0_[18]\, R => ldata_reg ); \rdata_reg_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(19), Q => \rdata_reg_reg_n_0_[19]\, R => ldata_reg ); \rdata_reg_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(1), Q => \rdata_reg_reg_n_0_[1]\, R => ldata_reg ); \rdata_reg_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(20), Q => \rdata_reg_reg_n_0_[20]\, R => ldata_reg ); \rdata_reg_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(21), Q => \rdata_reg_reg_n_0_[21]\, R => ldata_reg ); \rdata_reg_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(22), Q => \rdata_reg_reg_n_0_[22]\, R => ldata_reg ); \rdata_reg_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(23), Q => \rdata_reg_reg_n_0_[23]\, R => ldata_reg ); \rdata_reg_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(2), Q => \rdata_reg_reg_n_0_[2]\, R => ldata_reg ); \rdata_reg_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(3), Q => \rdata_reg_reg_n_0_[3]\, R => ldata_reg ); \rdata_reg_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(4), Q => \rdata_reg_reg_n_0_[4]\, R => ldata_reg ); \rdata_reg_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(5), Q => \rdata_reg_reg_n_0_[5]\, R => ldata_reg ); \rdata_reg_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(6), Q => \rdata_reg_reg_n_0_[6]\, R => ldata_reg ); \rdata_reg_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(7), Q => \rdata_reg_reg_n_0_[7]\, R => ldata_reg ); \rdata_reg_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(8), Q => \rdata_reg_reg_n_0_[8]\, R => ldata_reg ); \rdata_reg_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => p_1_in(9), Q => \rdata_reg_reg_n_0_[9]\, R => ldata_reg ); sdata_reg_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFCCAF0000CCA0" ) port map ( I0 => \rdata_reg_reg_n_0_[23]\, I1 => p_2_in, I2 => \^out\(2), I3 => p_0_in2_in, I4 => \clk_cntr_reg[4]\, I5 => \^sdata_o\, O => sdata_reg_i_1_n_0 ); sdata_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => sdata_reg_i_1_n_0, Q => \^sdata_o\, R => ldata_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ip_design_zed_audio_ctrl_0_0_slave_attachment is port ( \DataTx_R_reg[0]\ : out STD_LOGIC; \DataTx_R_reg[0]_0\ : out STD_LOGIC; \DataTx_R_reg[0]_1\ : out STD_LOGIC; \DataTx_R_reg[0]_2\ : out STD_LOGIC; \DataTx_R_reg[0]_3\ : out STD_LOGIC; \DataTx_R_reg[0]_4\ : out STD_LOGIC; S_AXI_RVALID : out STD_LOGIC; S_AXI_BVALID : out STD_LOGIC; data_rdy_bit_reg : out STD_LOGIC; S_AXI_AWREADY : out STD_LOGIC; S_AXI_ARREADY : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); data_rdy_bit_reg_0 : out STD_LOGIC; S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACLK : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_ARVALID : in STD_LOGIC; S_AXI_ARESETN : in STD_LOGIC; S_AXI_BREADY : in STD_LOGIC; S_AXI_RREADY : in STD_LOGIC; S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_AWVALID : in STD_LOGIC; S_AXI_WVALID : in STD_LOGIC; data_rdy_bit : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); \DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 ); \DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_slave_attachment : entity is "slave_attachment"; end ip_design_zed_audio_ctrl_0_0_slave_attachment; architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_slave_attachment is signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\ : STD_LOGIC; signal IP2Bus_Data : STD_LOGIC_VECTOR ( 31 downto 0 ); signal I_DECODER_n_46 : STD_LOGIC; signal I_DECODER_n_47 : STD_LOGIC; signal I_DECODER_n_7 : STD_LOGIC; signal I_DECODER_n_8 : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal p_2_out : STD_LOGIC; signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 ); signal rst : STD_LOGIC; signal s_axi_rdata_i : STD_LOGIC; signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \state[0]_i_2_n_0\ : STD_LOGIC; signal \state[1]_i_2_n_0\ : STD_LOGIC; signal \state[1]_i_3_n_0\ : STD_LOGIC; signal timeout : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair4"; begin S_AXI_BVALID <= \^s_axi_bvalid\; S_AXI_RVALID <= \^s_axi_rvalid\; \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\, O => plusOp(0) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\, I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\, O => plusOp(1) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\, I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\, I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\, O => plusOp(2) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => state(1), I1 => state(0), O => p_2_out ); \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\, I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\, I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\, I3 => timeout, O => plusOp(3) ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => '1', D => plusOp(0), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\, R => p_2_out ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => '1', D => plusOp(1), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\, R => p_2_out ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => '1', D => plusOp(2), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\, R => p_2_out ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => '1', D => plusOp(3), Q => timeout, R => p_2_out ); I_DECODER: entity work.ip_design_zed_audio_ctrl_0_0_address_decoder port map ( D(1) => I_DECODER_n_7, D(0) => I_DECODER_n_8, \DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0), \DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0), \DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0), \DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0), \DataTx_R_reg[0]\ => \DataTx_R_reg[0]\, \DataTx_R_reg[0]_0\ => \DataTx_R_reg[0]_0\, \DataTx_R_reg[0]_1\ => \DataTx_R_reg[0]_1\, \DataTx_R_reg[0]_2\ => \DataTx_R_reg[0]_2\, \DataTx_R_reg[0]_3\ => \DataTx_R_reg[0]_3\, \DataTx_R_reg[0]_4\ => \DataTx_R_reg[0]_4\, \DataTx_R_reg[31]\(31 downto 0) => Q(31 downto 0), E(0) => E(0), \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\, \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0) => timeout, Q(1 downto 0) => state(1 downto 0), S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0), S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0), S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_RREADY => S_AXI_RREADY, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WVALID_0 => \state[1]_i_2_n_0\, data_rdy_bit => data_rdy_bit, data_rdy_bit_reg => data_rdy_bit_reg, data_rdy_bit_reg_0 => data_rdy_bit_reg_0, s_axi_bvalid_i_reg => I_DECODER_n_47, s_axi_bvalid_i_reg_0 => \state[0]_i_2_n_0\, s_axi_bvalid_i_reg_1 => \^s_axi_bvalid\, \s_axi_rdata_i_reg[31]\(31 downto 0) => IP2Bus_Data(31 downto 0), s_axi_rvalid_i_reg => I_DECODER_n_46, s_axi_rvalid_i_reg_0 => \^s_axi_rvalid\, \state_reg[1]\ => \state[1]_i_3_n_0\ ); rst_reg: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => '1', D => SR(0), Q => rst, R => '0' ); s_axi_bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => I_DECODER_n_47, Q => \^s_axi_bvalid\, R => rst ); \s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => state(0), I1 => state(1), O => s_axi_rdata_i ); \s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(0), Q => S_AXI_RDATA(0), R => rst ); \s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(10), Q => S_AXI_RDATA(10), R => rst ); \s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(11), Q => S_AXI_RDATA(11), R => rst ); \s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(12), Q => S_AXI_RDATA(12), R => rst ); \s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(13), Q => S_AXI_RDATA(13), R => rst ); \s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(14), Q => S_AXI_RDATA(14), R => rst ); \s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(15), Q => S_AXI_RDATA(15), R => rst ); \s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(16), Q => S_AXI_RDATA(16), R => rst ); \s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(17), Q => S_AXI_RDATA(17), R => rst ); \s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(18), Q => S_AXI_RDATA(18), R => rst ); \s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(19), Q => S_AXI_RDATA(19), R => rst ); \s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(1), Q => S_AXI_RDATA(1), R => rst ); \s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(20), Q => S_AXI_RDATA(20), R => rst ); \s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(21), Q => S_AXI_RDATA(21), R => rst ); \s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(22), Q => S_AXI_RDATA(22), R => rst ); \s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(23), Q => S_AXI_RDATA(23), R => rst ); \s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(24), Q => S_AXI_RDATA(24), R => rst ); \s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(25), Q => S_AXI_RDATA(25), R => rst ); \s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(26), Q => S_AXI_RDATA(26), R => rst ); \s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(27), Q => S_AXI_RDATA(27), R => rst ); \s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(28), Q => S_AXI_RDATA(28), R => rst ); \s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(29), Q => S_AXI_RDATA(29), R => rst ); \s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(2), Q => S_AXI_RDATA(2), R => rst ); \s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(30), Q => S_AXI_RDATA(30), R => rst ); \s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(31), Q => S_AXI_RDATA(31), R => rst ); \s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(3), Q => S_AXI_RDATA(3), R => rst ); \s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(4), Q => S_AXI_RDATA(4), R => rst ); \s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(5), Q => S_AXI_RDATA(5), R => rst ); \s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(6), Q => S_AXI_RDATA(6), R => rst ); \s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(7), Q => S_AXI_RDATA(7), R => rst ); \s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(8), Q => S_AXI_RDATA(8), R => rst ); \s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => s_axi_rdata_i, D => IP2Bus_Data(9), Q => S_AXI_RDATA(9), R => rst ); s_axi_rvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => I_DECODER_n_46, Q => \^s_axi_rvalid\, R => rst ); \state[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"07770000FFFF0000" ) port map ( I0 => \^s_axi_bvalid\, I1 => S_AXI_BREADY, I2 => S_AXI_RREADY, I3 => \^s_axi_rvalid\, I4 => state(0), I5 => state(1), O => \state[0]_i_2_n_0\ ); \state[1]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => S_AXI_AWVALID, I1 => S_AXI_WVALID, O => \state[1]_i_2_n_0\ ); \state[1]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"002A2A2A" ) port map ( I0 => state(1), I1 => \^s_axi_rvalid\, I2 => S_AXI_RREADY, I3 => S_AXI_BREADY, I4 => \^s_axi_bvalid\, O => \state[1]_i_3_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => '1', D => I_DECODER_n_8, Q => state(0), R => rst ); \state_reg[1]\: unisim.vcomponents.FDRE port map ( C => S_AXI_ACLK, CE => '1', D => I_DECODER_n_7, Q => state(1), R => rst ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ip_design_zed_audio_ctrl_0_0_user_logic is port ( \s_axi_rdata_i_reg[24]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); data_rdy_bit : out STD_LOGIC; SDATA_O : out STD_LOGIC; \s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); \s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); SR : out STD_LOGIC_VECTOR ( 0 to 0 ); \s_axi_rdata_i_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); \s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC_VECTOR ( 23 downto 0 ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : in STD_LOGIC; Bus_RNW_reg : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC; S_AXI_ACLK : in STD_LOGIC; S_AXI_ARESETN : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC; SDATA_I : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_user_logic : entity is "user_logic"; end ip_design_zed_audio_ctrl_0_0_user_logic; architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_user_logic is signal Inst_iis_deser_n_3 : STD_LOGIC; signal Inst_iis_deser_n_33 : STD_LOGIC; signal Inst_iis_deser_n_34 : STD_LOGIC; signal Inst_iis_deser_n_35 : STD_LOGIC; signal Inst_iis_deser_n_36 : STD_LOGIC; signal Inst_iis_deser_n_37 : STD_LOGIC; signal Inst_iis_deser_n_38 : STD_LOGIC; signal Inst_iis_deser_n_39 : STD_LOGIC; signal Inst_iis_deser_n_40 : STD_LOGIC; signal Inst_iis_deser_n_41 : STD_LOGIC; signal Inst_iis_deser_n_42 : STD_LOGIC; signal Inst_iis_deser_n_43 : STD_LOGIC; signal Inst_iis_deser_n_44 : STD_LOGIC; signal Inst_iis_deser_n_45 : STD_LOGIC; signal Inst_iis_deser_n_46 : STD_LOGIC; signal Inst_iis_deser_n_47 : STD_LOGIC; signal Inst_iis_deser_n_48 : STD_LOGIC; signal Inst_iis_deser_n_49 : STD_LOGIC; signal Inst_iis_deser_n_5 : STD_LOGIC; signal Inst_iis_deser_n_50 : STD_LOGIC; signal Inst_iis_deser_n_51 : STD_LOGIC; signal Inst_iis_deser_n_52 : STD_LOGIC; signal Inst_iis_deser_n_53 : STD_LOGIC; signal Inst_iis_deser_n_54 : STD_LOGIC; signal Inst_iis_deser_n_55 : STD_LOGIC; signal Inst_iis_deser_n_56 : STD_LOGIC; signal Inst_iis_deser_n_6 : STD_LOGIC; signal Inst_iis_deser_n_7 : STD_LOGIC; signal Inst_iis_deser_n_8 : STD_LOGIC; signal Inst_iis_ser_n_1 : STD_LOGIC; signal Inst_iis_ser_n_2 : STD_LOGIC; signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \clk_cntr[10]_i_2_n_0\ : STD_LOGIC; signal \clk_cntr_reg_n_0_[0]\ : STD_LOGIC; signal \clk_cntr_reg_n_0_[1]\ : STD_LOGIC; signal \clk_cntr_reg_n_0_[2]\ : STD_LOGIC; signal \clk_cntr_reg_n_0_[3]\ : STD_LOGIC; signal \clk_cntr_reg_n_0_[5]\ : STD_LOGIC; signal \clk_cntr_reg_n_0_[6]\ : STD_LOGIC; signal \clk_cntr_reg_n_0_[7]\ : STD_LOGIC; signal \clk_cntr_reg_n_0_[8]\ : STD_LOGIC; signal \clk_cntr_reg_n_0_[9]\ : STD_LOGIC; signal data_rdy : STD_LOGIC; signal \^data_rdy_bit\ : STD_LOGIC; signal ldata_reg : STD_LOGIC_VECTOR ( 23 downto 0 ); signal lrclk_d1 : STD_LOGIC; signal p_0_in4_in : STD_LOGIC; signal \plusOp__0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); signal \^s_axi_rdata_i_reg[31]\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_rdata_i_reg[31]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal sclk_d1 : STD_LOGIC; signal write_bit : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \clk_cntr[1]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \clk_cntr[2]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \clk_cntr[3]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \clk_cntr[4]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \clk_cntr[6]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \clk_cntr[7]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \clk_cntr[8]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \clk_cntr[9]_i_1\ : label is "soft_lutpair15"; begin Q(1 downto 0) <= \^q\(1 downto 0); SR(0) <= \^sr\(0); data_rdy_bit <= \^data_rdy_bit\; \s_axi_rdata_i_reg[31]\(31 downto 0) <= \^s_axi_rdata_i_reg[31]\(31 downto 0); \s_axi_rdata_i_reg[31]_0\(31 downto 0) <= \^s_axi_rdata_i_reg[31]_0\(31 downto 0); \DataRx_L_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(0), Q => \s_axi_rdata_i_reg[23]\(0), R => '0' ); \DataRx_L_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(10), Q => \s_axi_rdata_i_reg[23]\(10), R => '0' ); \DataRx_L_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(11), Q => \s_axi_rdata_i_reg[23]\(11), R => '0' ); \DataRx_L_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(12), Q => \s_axi_rdata_i_reg[23]\(12), R => '0' ); \DataRx_L_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(13), Q => \s_axi_rdata_i_reg[23]\(13), R => '0' ); \DataRx_L_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(14), Q => \s_axi_rdata_i_reg[23]\(14), R => '0' ); \DataRx_L_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(15), Q => \s_axi_rdata_i_reg[23]\(15), R => '0' ); \DataRx_L_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(16), Q => \s_axi_rdata_i_reg[23]\(16), R => '0' ); \DataRx_L_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(17), Q => \s_axi_rdata_i_reg[23]\(17), R => '0' ); \DataRx_L_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(18), Q => \s_axi_rdata_i_reg[23]\(18), R => '0' ); \DataRx_L_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(19), Q => \s_axi_rdata_i_reg[23]\(19), R => '0' ); \DataRx_L_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(1), Q => \s_axi_rdata_i_reg[23]\(1), R => '0' ); \DataRx_L_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(20), Q => \s_axi_rdata_i_reg[23]\(20), R => '0' ); \DataRx_L_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(21), Q => \s_axi_rdata_i_reg[23]\(21), R => '0' ); \DataRx_L_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(22), Q => \s_axi_rdata_i_reg[23]\(22), R => '0' ); \DataRx_L_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(23), Q => \s_axi_rdata_i_reg[23]\(23), R => '0' ); \DataRx_L_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(2), Q => \s_axi_rdata_i_reg[23]\(2), R => '0' ); \DataRx_L_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(3), Q => \s_axi_rdata_i_reg[23]\(3), R => '0' ); \DataRx_L_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(4), Q => \s_axi_rdata_i_reg[23]\(4), R => '0' ); \DataRx_L_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(5), Q => \s_axi_rdata_i_reg[23]\(5), R => '0' ); \DataRx_L_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(6), Q => \s_axi_rdata_i_reg[23]\(6), R => '0' ); \DataRx_L_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(7), Q => \s_axi_rdata_i_reg[23]\(7), R => '0' ); \DataRx_L_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(8), Q => \s_axi_rdata_i_reg[23]\(8), R => '0' ); \DataRx_L_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => ldata_reg(9), Q => \s_axi_rdata_i_reg[23]\(9), R => '0' ); \DataRx_R_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_56, Q => \s_axi_rdata_i_reg[23]_0\(0), R => '0' ); \DataRx_R_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_46, Q => \s_axi_rdata_i_reg[23]_0\(10), R => '0' ); \DataRx_R_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_45, Q => \s_axi_rdata_i_reg[23]_0\(11), R => '0' ); \DataRx_R_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_44, Q => \s_axi_rdata_i_reg[23]_0\(12), R => '0' ); \DataRx_R_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_43, Q => \s_axi_rdata_i_reg[23]_0\(13), R => '0' ); \DataRx_R_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_42, Q => \s_axi_rdata_i_reg[23]_0\(14), R => '0' ); \DataRx_R_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_41, Q => \s_axi_rdata_i_reg[23]_0\(15), R => '0' ); \DataRx_R_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_40, Q => \s_axi_rdata_i_reg[23]_0\(16), R => '0' ); \DataRx_R_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_39, Q => \s_axi_rdata_i_reg[23]_0\(17), R => '0' ); \DataRx_R_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_38, Q => \s_axi_rdata_i_reg[23]_0\(18), R => '0' ); \DataRx_R_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_37, Q => \s_axi_rdata_i_reg[23]_0\(19), R => '0' ); \DataRx_R_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_55, Q => \s_axi_rdata_i_reg[23]_0\(1), R => '0' ); \DataRx_R_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_36, Q => \s_axi_rdata_i_reg[23]_0\(20), R => '0' ); \DataRx_R_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_35, Q => \s_axi_rdata_i_reg[23]_0\(21), R => '0' ); \DataRx_R_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_34, Q => \s_axi_rdata_i_reg[23]_0\(22), R => '0' ); \DataRx_R_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_33, Q => \s_axi_rdata_i_reg[23]_0\(23), R => '0' ); \DataRx_R_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_54, Q => \s_axi_rdata_i_reg[23]_0\(2), R => '0' ); \DataRx_R_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_53, Q => \s_axi_rdata_i_reg[23]_0\(3), R => '0' ); \DataRx_R_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_52, Q => \s_axi_rdata_i_reg[23]_0\(4), R => '0' ); \DataRx_R_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_51, Q => \s_axi_rdata_i_reg[23]_0\(5), R => '0' ); \DataRx_R_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_50, Q => \s_axi_rdata_i_reg[23]_0\(6), R => '0' ); \DataRx_R_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_49, Q => \s_axi_rdata_i_reg[23]_0\(7), R => '0' ); \DataRx_R_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_48, Q => \s_axi_rdata_i_reg[23]_0\(8), R => '0' ); \DataRx_R_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => data_rdy, D => Inst_iis_deser_n_47, Q => \s_axi_rdata_i_reg[23]_0\(9), R => '0' ); \DataTx_L_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(0), Q => \^s_axi_rdata_i_reg[31]\(0), R => \^sr\(0) ); \DataTx_L_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(10), Q => \^s_axi_rdata_i_reg[31]\(10), R => \^sr\(0) ); \DataTx_L_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(11), Q => \^s_axi_rdata_i_reg[31]\(11), R => \^sr\(0) ); \DataTx_L_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(12), Q => \^s_axi_rdata_i_reg[31]\(12), R => \^sr\(0) ); \DataTx_L_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(13), Q => \^s_axi_rdata_i_reg[31]\(13), R => \^sr\(0) ); \DataTx_L_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(14), Q => \^s_axi_rdata_i_reg[31]\(14), R => \^sr\(0) ); \DataTx_L_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(15), Q => \^s_axi_rdata_i_reg[31]\(15), R => \^sr\(0) ); \DataTx_L_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(16), Q => \^s_axi_rdata_i_reg[31]\(16), R => \^sr\(0) ); \DataTx_L_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(17), Q => \^s_axi_rdata_i_reg[31]\(17), R => \^sr\(0) ); \DataTx_L_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(18), Q => \^s_axi_rdata_i_reg[31]\(18), R => \^sr\(0) ); \DataTx_L_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(19), Q => \^s_axi_rdata_i_reg[31]\(19), R => \^sr\(0) ); \DataTx_L_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(1), Q => \^s_axi_rdata_i_reg[31]\(1), R => \^sr\(0) ); \DataTx_L_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(20), Q => \^s_axi_rdata_i_reg[31]\(20), R => \^sr\(0) ); \DataTx_L_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(21), Q => \^s_axi_rdata_i_reg[31]\(21), R => \^sr\(0) ); \DataTx_L_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(22), Q => \^s_axi_rdata_i_reg[31]\(22), R => \^sr\(0) ); \DataTx_L_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(23), Q => \^s_axi_rdata_i_reg[31]\(23), R => \^sr\(0) ); \DataTx_L_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(24), Q => \^s_axi_rdata_i_reg[31]\(24), R => \^sr\(0) ); \DataTx_L_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(25), Q => \^s_axi_rdata_i_reg[31]\(25), R => \^sr\(0) ); \DataTx_L_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(26), Q => \^s_axi_rdata_i_reg[31]\(26), R => \^sr\(0) ); \DataTx_L_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(27), Q => \^s_axi_rdata_i_reg[31]\(27), R => \^sr\(0) ); \DataTx_L_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(28), Q => \^s_axi_rdata_i_reg[31]\(28), R => \^sr\(0) ); \DataTx_L_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(29), Q => \^s_axi_rdata_i_reg[31]\(29), R => \^sr\(0) ); \DataTx_L_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(2), Q => \^s_axi_rdata_i_reg[31]\(2), R => \^sr\(0) ); \DataTx_L_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(30), Q => \^s_axi_rdata_i_reg[31]\(30), R => \^sr\(0) ); \DataTx_L_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(31), Q => \^s_axi_rdata_i_reg[31]\(31), R => \^sr\(0) ); \DataTx_L_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(3), Q => \^s_axi_rdata_i_reg[31]\(3), R => \^sr\(0) ); \DataTx_L_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(4), Q => \^s_axi_rdata_i_reg[31]\(4), R => \^sr\(0) ); \DataTx_L_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(5), Q => \^s_axi_rdata_i_reg[31]\(5), R => \^sr\(0) ); \DataTx_L_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(6), Q => \^s_axi_rdata_i_reg[31]\(6), R => \^sr\(0) ); \DataTx_L_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(7), Q => \^s_axi_rdata_i_reg[31]\(7), R => \^sr\(0) ); \DataTx_L_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(8), Q => \^s_axi_rdata_i_reg[31]\(8), R => \^sr\(0) ); \DataTx_L_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => E(0), D => S_AXI_WDATA(9), Q => \^s_axi_rdata_i_reg[31]\(9), R => \^sr\(0) ); \DataTx_R_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(0), Q => \^s_axi_rdata_i_reg[31]_0\(0), R => \^sr\(0) ); \DataTx_R_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(10), Q => \^s_axi_rdata_i_reg[31]_0\(10), R => \^sr\(0) ); \DataTx_R_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(11), Q => \^s_axi_rdata_i_reg[31]_0\(11), R => \^sr\(0) ); \DataTx_R_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(12), Q => \^s_axi_rdata_i_reg[31]_0\(12), R => \^sr\(0) ); \DataTx_R_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(13), Q => \^s_axi_rdata_i_reg[31]_0\(13), R => \^sr\(0) ); \DataTx_R_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(14), Q => \^s_axi_rdata_i_reg[31]_0\(14), R => \^sr\(0) ); \DataTx_R_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(15), Q => \^s_axi_rdata_i_reg[31]_0\(15), R => \^sr\(0) ); \DataTx_R_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(16), Q => \^s_axi_rdata_i_reg[31]_0\(16), R => \^sr\(0) ); \DataTx_R_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(17), Q => \^s_axi_rdata_i_reg[31]_0\(17), R => \^sr\(0) ); \DataTx_R_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(18), Q => \^s_axi_rdata_i_reg[31]_0\(18), R => \^sr\(0) ); \DataTx_R_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(19), Q => \^s_axi_rdata_i_reg[31]_0\(19), R => \^sr\(0) ); \DataTx_R_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(1), Q => \^s_axi_rdata_i_reg[31]_0\(1), R => \^sr\(0) ); \DataTx_R_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(20), Q => \^s_axi_rdata_i_reg[31]_0\(20), R => \^sr\(0) ); \DataTx_R_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(21), Q => \^s_axi_rdata_i_reg[31]_0\(21), R => \^sr\(0) ); \DataTx_R_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(22), Q => \^s_axi_rdata_i_reg[31]_0\(22), R => \^sr\(0) ); \DataTx_R_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(23), Q => \^s_axi_rdata_i_reg[31]_0\(23), R => \^sr\(0) ); \DataTx_R_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(24), Q => \^s_axi_rdata_i_reg[31]_0\(24), R => \^sr\(0) ); \DataTx_R_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(25), Q => \^s_axi_rdata_i_reg[31]_0\(25), R => \^sr\(0) ); \DataTx_R_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(26), Q => \^s_axi_rdata_i_reg[31]_0\(26), R => \^sr\(0) ); \DataTx_R_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(27), Q => \^s_axi_rdata_i_reg[31]_0\(27), R => \^sr\(0) ); \DataTx_R_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(28), Q => \^s_axi_rdata_i_reg[31]_0\(28), R => \^sr\(0) ); \DataTx_R_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(29), Q => \^s_axi_rdata_i_reg[31]_0\(29), R => \^sr\(0) ); \DataTx_R_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(2), Q => \^s_axi_rdata_i_reg[31]_0\(2), R => \^sr\(0) ); \DataTx_R_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(30), Q => \^s_axi_rdata_i_reg[31]_0\(30), R => \^sr\(0) ); \DataTx_R_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(31), Q => \^s_axi_rdata_i_reg[31]_0\(31), R => \^sr\(0) ); \DataTx_R_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(3), Q => \^s_axi_rdata_i_reg[31]_0\(3), R => \^sr\(0) ); \DataTx_R_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(4), Q => \^s_axi_rdata_i_reg[31]_0\(4), R => \^sr\(0) ); \DataTx_R_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(5), Q => \^s_axi_rdata_i_reg[31]_0\(5), R => \^sr\(0) ); \DataTx_R_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(6), Q => \^s_axi_rdata_i_reg[31]_0\(6), R => \^sr\(0) ); \DataTx_R_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(7), Q => \^s_axi_rdata_i_reg[31]_0\(7), R => \^sr\(0) ); \DataTx_R_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(8), Q => \^s_axi_rdata_i_reg[31]_0\(8), R => \^sr\(0) ); \DataTx_R_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0), D => S_AXI_WDATA(9), Q => \^s_axi_rdata_i_reg[31]_0\(9), R => \^sr\(0) ); Inst_iis_deser: entity work.ip_design_zed_audio_ctrl_0_0_iis_deser port map ( \DataRx_L_reg[23]\(23 downto 0) => ldata_reg(23 downto 0), \DataRx_R_reg[23]\(23) => Inst_iis_deser_n_33, \DataRx_R_reg[23]\(22) => Inst_iis_deser_n_34, \DataRx_R_reg[23]\(21) => Inst_iis_deser_n_35, \DataRx_R_reg[23]\(20) => Inst_iis_deser_n_36, \DataRx_R_reg[23]\(19) => Inst_iis_deser_n_37, \DataRx_R_reg[23]\(18) => Inst_iis_deser_n_38, \DataRx_R_reg[23]\(17) => Inst_iis_deser_n_39, \DataRx_R_reg[23]\(16) => Inst_iis_deser_n_40, \DataRx_R_reg[23]\(15) => Inst_iis_deser_n_41, \DataRx_R_reg[23]\(14) => Inst_iis_deser_n_42, \DataRx_R_reg[23]\(13) => Inst_iis_deser_n_43, \DataRx_R_reg[23]\(12) => Inst_iis_deser_n_44, \DataRx_R_reg[23]\(11) => Inst_iis_deser_n_45, \DataRx_R_reg[23]\(10) => Inst_iis_deser_n_46, \DataRx_R_reg[23]\(9) => Inst_iis_deser_n_47, \DataRx_R_reg[23]\(8) => Inst_iis_deser_n_48, \DataRx_R_reg[23]\(7) => Inst_iis_deser_n_49, \DataRx_R_reg[23]\(6) => Inst_iis_deser_n_50, \DataRx_R_reg[23]\(5) => Inst_iis_deser_n_51, \DataRx_R_reg[23]\(4) => Inst_iis_deser_n_52, \DataRx_R_reg[23]\(3) => Inst_iis_deser_n_53, \DataRx_R_reg[23]\(2) => Inst_iis_deser_n_54, \DataRx_R_reg[23]\(1) => Inst_iis_deser_n_55, \DataRx_R_reg[23]\(0) => Inst_iis_deser_n_56, E(0) => data_rdy, \FSM_onehot_iis_state_reg[0]\ => Inst_iis_deser_n_6, \FSM_onehot_iis_state_reg[0]_0\ => Inst_iis_deser_n_8, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\, Q(1 downto 0) => \^q\(1 downto 0), SDATA_I => SDATA_I, S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, \bit_cntr_reg[4]_0\(0) => write_bit, data_rdy_bit => \^data_rdy_bit\, data_rdy_bit_reg => Inst_iis_deser_n_7, lrclk_d1 => lrclk_d1, \out\(2) => Inst_iis_ser_n_1, \out\(1) => Inst_iis_ser_n_2, \out\(0) => p_0_in4_in, \rdata_reg_reg[23]_0\(0) => Inst_iis_deser_n_3, sclk_d1 => sclk_d1, sdata_reg_reg => Inst_iis_deser_n_5 ); Inst_iis_ser: entity work.ip_design_zed_audio_ctrl_0_0_iis_ser port map ( \DataTx_L_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]\(23 downto 0), \DataTx_R_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]_0\(23 downto 0), E(0) => Inst_iis_deser_n_3, Q(1 downto 0) => \^q\(1 downto 0), SDATA_O => SDATA_O, S_AXI_ACLK => S_AXI_ACLK, \clk_cntr_reg[4]\ => Inst_iis_deser_n_5, lrclk_d1 => lrclk_d1, lrclk_d1_reg => Inst_iis_deser_n_8, lrclk_d1_reg_0 => Inst_iis_deser_n_6, \out\(2) => Inst_iis_ser_n_1, \out\(1) => Inst_iis_ser_n_2, \out\(0) => p_0_in4_in, sclk_d1 => sclk_d1, sclk_d1_reg(0) => write_bit ); \clk_cntr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \clk_cntr_reg_n_0_[0]\, O => \plusOp__0\(0) ); \clk_cntr[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F7FFFFFF08000000" ) port map ( I0 => \clk_cntr_reg_n_0_[9]\, I1 => \clk_cntr_reg_n_0_[7]\, I2 => \clk_cntr[10]_i_2_n_0\, I3 => \clk_cntr_reg_n_0_[6]\, I4 => \clk_cntr_reg_n_0_[8]\, I5 => \^q\(1), O => \plusOp__0\(10) ); \clk_cntr[10]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \^q\(0), I1 => \clk_cntr_reg_n_0_[2]\, I2 => \clk_cntr_reg_n_0_[0]\, I3 => \clk_cntr_reg_n_0_[1]\, I4 => \clk_cntr_reg_n_0_[3]\, I5 => \clk_cntr_reg_n_0_[5]\, O => \clk_cntr[10]_i_2_n_0\ ); \clk_cntr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \clk_cntr_reg_n_0_[0]\, I1 => \clk_cntr_reg_n_0_[1]\, O => \plusOp__0\(1) ); \clk_cntr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \clk_cntr_reg_n_0_[1]\, I1 => \clk_cntr_reg_n_0_[0]\, I2 => \clk_cntr_reg_n_0_[2]\, O => \plusOp__0\(2) ); \clk_cntr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \clk_cntr_reg_n_0_[2]\, I1 => \clk_cntr_reg_n_0_[0]\, I2 => \clk_cntr_reg_n_0_[1]\, I3 => \clk_cntr_reg_n_0_[3]\, O => \plusOp__0\(3) ); \clk_cntr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \clk_cntr_reg_n_0_[3]\, I1 => \clk_cntr_reg_n_0_[1]\, I2 => \clk_cntr_reg_n_0_[0]\, I3 => \clk_cntr_reg_n_0_[2]\, I4 => \^q\(0), O => \plusOp__0\(4) ); \clk_cntr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(0), I1 => \clk_cntr_reg_n_0_[2]\, I2 => \clk_cntr_reg_n_0_[0]\, I3 => \clk_cntr_reg_n_0_[1]\, I4 => \clk_cntr_reg_n_0_[3]\, I5 => \clk_cntr_reg_n_0_[5]\, O => \plusOp__0\(5) ); \clk_cntr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \clk_cntr[10]_i_2_n_0\, I1 => \clk_cntr_reg_n_0_[6]\, O => \plusOp__0\(6) ); \clk_cntr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => \clk_cntr_reg_n_0_[6]\, I1 => \clk_cntr[10]_i_2_n_0\, I2 => \clk_cntr_reg_n_0_[7]\, O => \plusOp__0\(7) ); \clk_cntr[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"DF20" ) port map ( I0 => \clk_cntr_reg_n_0_[7]\, I1 => \clk_cntr[10]_i_2_n_0\, I2 => \clk_cntr_reg_n_0_[6]\, I3 => \clk_cntr_reg_n_0_[8]\, O => \plusOp__0\(8) ); \clk_cntr[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FF0800" ) port map ( I0 => \clk_cntr_reg_n_0_[8]\, I1 => \clk_cntr_reg_n_0_[6]\, I2 => \clk_cntr[10]_i_2_n_0\, I3 => \clk_cntr_reg_n_0_[7]\, I4 => \clk_cntr_reg_n_0_[9]\, O => \plusOp__0\(9) ); \clk_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(0), Q => \clk_cntr_reg_n_0_[0]\, R => '0' ); \clk_cntr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(10), Q => \^q\(1), R => '0' ); \clk_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(1), Q => \clk_cntr_reg_n_0_[1]\, R => '0' ); \clk_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(2), Q => \clk_cntr_reg_n_0_[2]\, R => '0' ); \clk_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(3), Q => \clk_cntr_reg_n_0_[3]\, R => '0' ); \clk_cntr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(4), Q => \^q\(0), R => '0' ); \clk_cntr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(5), Q => \clk_cntr_reg_n_0_[5]\, R => '0' ); \clk_cntr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(6), Q => \clk_cntr_reg_n_0_[6]\, R => '0' ); \clk_cntr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(7), Q => \clk_cntr_reg_n_0_[7]\, R => '0' ); \clk_cntr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(8), Q => \clk_cntr_reg_n_0_[8]\, R => '0' ); \clk_cntr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => \plusOp__0\(9), Q => \clk_cntr_reg_n_0_[9]\, R => '0' ); data_rdy_bit_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => S_AXI_ACLK, CE => '1', D => Inst_iis_deser_n_7, Q => \^data_rdy_bit\, R => '0' ); rst_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => S_AXI_ARESETN, O => \^sr\(0) ); slv_ip2bus_data: unisim.vcomponents.LUT6 generic map( INIT => X"0000000400040448" ) port map ( I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, I1 => Bus_RNW_reg, I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, I5 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, O => \s_axi_rdata_i_reg[24]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ip_design_zed_audio_ctrl_0_0_axi_lite_ipif is port ( \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC; \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC; Bus_RNW_reg : out STD_LOGIC; S_AXI_RVALID : out STD_LOGIC; S_AXI_BVALID : out STD_LOGIC; data_rdy_bit_reg : out STD_LOGIC; S_AXI_AWREADY : out STD_LOGIC; S_AXI_ARREADY : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); data_rdy_bit_reg_0 : out STD_LOGIC; S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACLK : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); S_AXI_ARVALID : in STD_LOGIC; S_AXI_ARESETN : in STD_LOGIC; S_AXI_BREADY : in STD_LOGIC; S_AXI_RREADY : in STD_LOGIC; S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_AWVALID : in STD_LOGIC; S_AXI_WVALID : in STD_LOGIC; data_rdy_bit : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); \DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 ); \DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 ); \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_axi_lite_ipif : entity is "axi_lite_ipif"; end ip_design_zed_audio_ctrl_0_0_axi_lite_ipif; architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_axi_lite_ipif is begin I_SLAVE_ATTACHMENT: entity work.ip_design_zed_audio_ctrl_0_0_slave_attachment port map ( \DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0), \DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0), \DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0), \DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0), \DataTx_R_reg[0]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, \DataTx_R_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, \DataTx_R_reg[0]_1\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, \DataTx_R_reg[0]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \DataTx_R_reg[0]_3\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, \DataTx_R_reg[0]_4\ => Bus_RNW_reg, E(0) => E(0), \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\, Q(31 downto 0) => Q(31 downto 0), SR(0) => SR(0), S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0), S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0), S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_BVALID => S_AXI_BVALID, S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0), S_AXI_RREADY => S_AXI_RREADY, S_AXI_RVALID => S_AXI_RVALID, S_AXI_WVALID => S_AXI_WVALID, data_rdy_bit => data_rdy_bit, data_rdy_bit_reg => data_rdy_bit_reg, data_rdy_bit_reg_0 => data_rdy_bit_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ip_design_zed_audio_ctrl_0_0_i2s_ctrl is port ( \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_AWREADY : out STD_LOGIC; S_AXI_ARREADY : out STD_LOGIC; S_AXI_BVALID : out STD_LOGIC; S_AXI_RVALID : out STD_LOGIC; SDATA_O : out STD_LOGIC; S_AXI_ACLK : in STD_LOGIC; SDATA_I : in STD_LOGIC; S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ARVALID : in STD_LOGIC; S_AXI_ARESETN : in STD_LOGIC; S_AXI_BREADY : in STD_LOGIC; S_AXI_RREADY : in STD_LOGIC; S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_AWVALID : in STD_LOGIC; S_AXI_WVALID : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ip_design_zed_audio_ctrl_0_0_i2s_ctrl : entity is "i2s_ctrl"; end ip_design_zed_audio_ctrl_0_0_i2s_ctrl; architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0_i2s_ctrl is signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC; signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC; signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC; signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC; signal DataRx_L : STD_LOGIC_VECTOR ( 23 downto 0 ); signal DataRx_R : STD_LOGIC_VECTOR ( 23 downto 0 ); signal DataTx_L : STD_LOGIC_VECTOR ( 31 downto 0 ); signal DataTx_R : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC; signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC; signal USER_LOGIC_I_n_0 : STD_LOGIC; signal USER_LOGIC_I_n_69 : STD_LOGIC; signal data_rdy_bit : STD_LOGIC; begin AXI_LITE_IPIF_I: entity work.ip_design_zed_audio_ctrl_0_0_axi_lite_ipif port map ( Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, \DataRx_L_reg[23]\(23 downto 0) => DataRx_L(23 downto 0), \DataRx_R_reg[23]\(23 downto 0) => DataRx_R(23 downto 0), \DataTx_L_reg[0]\(0) => AXI_LITE_IPIF_I_n_12, \DataTx_L_reg[31]\(31 downto 0) => DataTx_L(31 downto 0), E(0) => AXI_LITE_IPIF_I_n_11, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => USER_LOGIC_I_n_0, Q(31 downto 0) => DataTx_R(31 downto 0), SR(0) => USER_LOGIC_I_n_69, S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0), S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0), S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_BVALID => S_AXI_BVALID, S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0), S_AXI_RREADY => S_AXI_RREADY, S_AXI_RVALID => S_AXI_RVALID, S_AXI_WVALID => S_AXI_WVALID, data_rdy_bit => data_rdy_bit, data_rdy_bit_reg => AXI_LITE_IPIF_I_n_8, data_rdy_bit_reg_0 => AXI_LITE_IPIF_I_n_13 ); USER_LOGIC_I: entity work.ip_design_zed_audio_ctrl_0_0_user_logic port map ( Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\, E(0) => AXI_LITE_IPIF_I_n_12, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_8, \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0) => AXI_LITE_IPIF_I_n_11, \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\, \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI_LITE_IPIF_I_n_13, Q(1 downto 0) => \out\(1 downto 0), SDATA_I => SDATA_I, SDATA_O => SDATA_O, SR(0) => USER_LOGIC_I_n_69, S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0), data_rdy_bit => data_rdy_bit, \s_axi_rdata_i_reg[23]\(23 downto 0) => DataRx_L(23 downto 0), \s_axi_rdata_i_reg[23]_0\(23 downto 0) => DataRx_R(23 downto 0), \s_axi_rdata_i_reg[24]\ => USER_LOGIC_I_n_0, \s_axi_rdata_i_reg[31]\(31 downto 0) => DataTx_L(31 downto 0), \s_axi_rdata_i_reg[31]_0\(31 downto 0) => DataTx_R(31 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ip_design_zed_audio_ctrl_0_0 is port ( BCLK : out STD_LOGIC; LRCLK : out STD_LOGIC; SDATA_I : in STD_LOGIC; SDATA_O : out STD_LOGIC; S_AXI_ACLK : in STD_LOGIC; S_AXI_ARESETN : in STD_LOGIC; S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_AWVALID : in STD_LOGIC; S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_WVALID : in STD_LOGIC; S_AXI_BREADY : in STD_LOGIC; S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ARVALID : in STD_LOGIC; S_AXI_RREADY : in STD_LOGIC; S_AXI_ARREADY : out STD_LOGIC; S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_RVALID : out STD_LOGIC; S_AXI_WREADY : out STD_LOGIC; S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_BVALID : out STD_LOGIC; S_AXI_AWREADY : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of ip_design_zed_audio_ctrl_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of ip_design_zed_audio_ctrl_0_0 : entity is "ip_design_zed_audio_ctrl_0_0,i2s_ctrl,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of ip_design_zed_audio_ctrl_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of ip_design_zed_audio_ctrl_0_0 : entity is "i2s_ctrl,Vivado 2017.3"; end ip_design_zed_audio_ctrl_0_0; architecture STRUCTURE of ip_design_zed_audio_ctrl_0_0 is signal \<const0>\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; attribute max_fanout : string; attribute max_fanout of S_AXI_ACLK : signal is "10000"; attribute sigis : string; attribute sigis of S_AXI_ACLK : signal is "Clk"; attribute x_interface_info : string; attribute x_interface_info of S_AXI_ACLK : signal is "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK"; attribute x_interface_parameter : string; attribute x_interface_parameter of S_AXI_ACLK : signal is "XIL_INTERFACENAME S_AXI_signal_clock, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0"; attribute max_fanout of S_AXI_ARESETN : signal is "10000"; attribute sigis of S_AXI_ARESETN : signal is "Rst"; attribute x_interface_info of S_AXI_ARESETN : signal is "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST"; attribute x_interface_parameter of S_AXI_ARESETN : signal is "XIL_INTERFACENAME S_AXI_signal_reset, POLARITY ACTIVE_LOW"; attribute x_interface_info of S_AXI_ARREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; attribute x_interface_info of S_AXI_ARVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; attribute x_interface_info of S_AXI_AWREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; attribute x_interface_info of S_AXI_AWVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; attribute x_interface_info of S_AXI_BREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; attribute x_interface_info of S_AXI_BVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; attribute x_interface_info of S_AXI_RREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; attribute x_interface_info of S_AXI_RVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; attribute x_interface_info of S_AXI_WREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; attribute x_interface_info of S_AXI_WVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; attribute x_interface_info of S_AXI_ARADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; attribute x_interface_info of S_AXI_AWADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; attribute x_interface_parameter of S_AXI_AWADDR : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute x_interface_info of S_AXI_BRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; attribute x_interface_info of S_AXI_RDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; attribute x_interface_info of S_AXI_RRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; attribute x_interface_info of S_AXI_WDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; attribute x_interface_info of S_AXI_WSTRB : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; begin S_AXI_AWREADY <= \^s_axi_awready\; S_AXI_BRESP(1) <= \<const0>\; S_AXI_BRESP(0) <= \<const0>\; S_AXI_RRESP(1) <= \<const0>\; S_AXI_RRESP(0) <= \<const0>\; S_AXI_WREADY <= \^s_axi_awready\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); U0: entity work.ip_design_zed_audio_ctrl_0_0_i2s_ctrl port map ( SDATA_I => SDATA_I, SDATA_O => SDATA_O, S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(4 downto 2), S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(4 downto 2), S_AXI_AWREADY => \^s_axi_awready\, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_BVALID => S_AXI_BVALID, S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0), S_AXI_RREADY => S_AXI_RREADY, S_AXI_RVALID => S_AXI_RVALID, S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0), S_AXI_WVALID => S_AXI_WVALID, \out\(1) => LRCLK, \out\(0) => BCLK ); end STRUCTURE;

mit

79f13398dc16e6e2bd6cf31efc538487

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/8a4f3f63fe715aee/zynq_design_1_xbar_0_sim_netlist.vhdl

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Tue Sep 19 00:30:15 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_xbar_0_sim_netlist.vhdl -- Design : zynq_design_1_xbar_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter is port ( \s_axi_arready[0]\ : out STD_LOGIC; aa_mi_arvalid : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_rlast_i0 : out STD_LOGIC; \m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ : out STD_LOGIC; \gen_no_arbiter.m_target_hot_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); aresetn_d_reg : in STD_LOGIC; aclk : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); r_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 ); \gen_axi.read_cnt_reg[5]\ : in STD_LOGIC; p_15_in : in STD_LOGIC; mi_arready_2 : in STD_LOGIC; \gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); \chosen_reg[0]\ : in STD_LOGIC; \gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC; st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); \s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 ); \s_axi_araddr[30]\ : in STD_LOGIC; \s_axi_araddr[28]\ : in STD_LOGIC; \s_axi_araddr[25]\ : in STD_LOGIC; \m_payload_i_reg[34]\ : in STD_LOGIC; m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[34]_0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_valid_i_reg : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 0 to 0 ); m_valid_i : in STD_LOGIC; aresetn_d : in STD_LOGIC; aresetn_d_reg_0 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter is signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^aa_mi_arvalid\ : STD_LOGIC; signal \^gen_axi.s_axi_rid_i_reg[11]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gen_axi.s_axi_rlast_i_i_6_n_0\ : STD_LOGIC; signal \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC; signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC; signal \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC; signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC; signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC; signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC; signal \^gen_no_arbiter.m_target_hot_i_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC; signal \^gen_no_arbiter.m_valid_i_reg_0\ : STD_LOGIC; signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 ); signal \^s_axi_arready[0]\ : STD_LOGIC; signal s_ready_i2 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_5\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_3\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[16]_i_2\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[1]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair6"; begin aa_mi_arvalid <= \^aa_mi_arvalid\; \gen_axi.s_axi_rid_i_reg[11]\(0) <= \^gen_axi.s_axi_rid_i_reg[11]\(0); \gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) <= \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0); \gen_no_arbiter.m_valid_i_reg_0\ <= \^gen_no_arbiter.m_valid_i_reg_0\; \m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0); \s_axi_arready[0]\ <= \^s_axi_arready[0]\; \gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \^aa_mi_arvalid\, I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0), I2 => mi_arready_2, I3 => p_15_in, O => E(0) ); \gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"444444444444444F" ) port map ( I0 => \gen_axi.read_cnt_reg[5]\, I1 => p_15_in, I2 => \gen_axi.s_axi_rlast_i_i_6_n_0\, I3 => \^m_axi_arqos[7]\(44), I4 => \^m_axi_arqos[7]\(45), I5 => \^m_axi_arqos[7]\(47), O => s_axi_rlast_i0 ); \gen_axi.s_axi_rlast_i_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \^m_axi_arqos[7]\(49), I1 => p_15_in, I2 => \^m_axi_arqos[7]\(48), I3 => \^m_axi_arqos[7]\(46), I4 => \^m_axi_arqos[7]\(51), I5 => \^m_axi_arqos[7]\(50), O => \gen_axi.s_axi_rlast_i_i_6_n_0\ ); \gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => r_issuing_cnt(0), I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\, I2 => r_issuing_cnt(1), O => D(0) ); \gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7E81" ) port map ( I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\, I1 => r_issuing_cnt(0), I2 => r_issuing_cnt(1), I3 => r_issuing_cnt(2), O => D(1) ); \gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6666666666666662" ) port map ( I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\, I1 => \m_payload_i_reg[34]\, I2 => r_issuing_cnt(0), I3 => r_issuing_cnt(1), I4 => r_issuing_cnt(2), I5 => r_issuing_cnt(3), O => \gen_master_slots[0].r_issuing_cnt_reg[0]\(0) ); \gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAA9" ) port map ( I0 => r_issuing_cnt(3), I1 => r_issuing_cnt(2), I2 => r_issuing_cnt(1), I3 => r_issuing_cnt(0), I4 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\, O => D(2) ); \gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => m_axi_arready(0), I1 => aa_mi_artarget_hot(0), I2 => \^aa_mi_arvalid\, O => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\ ); \gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \^aa_mi_arvalid\, I1 => aa_mi_artarget_hot(0), I2 => m_axi_arready(0), I3 => \m_payload_i_reg[34]\, O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ ); \gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7E81" ) port map ( I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\, I1 => r_issuing_cnt(4), I2 => r_issuing_cnt(5), I3 => r_issuing_cnt(6), O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1) ); \gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6666666666666662" ) port map ( I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\, I1 => \m_payload_i_reg[34]_0\, I2 => r_issuing_cnt(4), I3 => r_issuing_cnt(5), I4 => r_issuing_cnt(6), I5 => r_issuing_cnt(7), O => \gen_master_slots[1].r_issuing_cnt_reg[8]\(0) ); \gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAA9" ) port map ( I0 => r_issuing_cnt(7), I1 => r_issuing_cnt(6), I2 => r_issuing_cnt(5), I3 => r_issuing_cnt(4), I4 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\, O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2) ); \gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => m_axi_arready(1), I1 => aa_mi_artarget_hot(1), I2 => \^aa_mi_arvalid\, O => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\ ); \gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0080808080808080" ) port map ( I0 => \^aa_mi_arvalid\, I1 => aa_mi_artarget_hot(1), I2 => m_axi_arready(1), I3 => s_axi_rready(0), I4 => m_valid_i_reg, I5 => Q(0), O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ ); \gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => r_issuing_cnt(4), I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\, I2 => r_issuing_cnt(5), O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0) ); \gen_master_slots[2].r_issuing_cnt[16]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => mi_arready_2, I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0), I2 => \^aa_mi_arvalid\, O => \^gen_no_arbiter.m_valid_i_reg_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => st_aa_artarget_hot(0), I1 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0), O => \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ ); \gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^aa_mi_arvalid\, O => s_ready_i2 ); \gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(0), Q => \^m_axi_arqos[7]\(0), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(10), Q => \^m_axi_arqos[7]\(10), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(11), Q => \^m_axi_arqos[7]\(11), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(12), Q => \^m_axi_arqos[7]\(12), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(13), Q => \^m_axi_arqos[7]\(13), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(14), Q => \^m_axi_arqos[7]\(14), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(15), Q => \^m_axi_arqos[7]\(15), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(16), Q => \^m_axi_arqos[7]\(16), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(17), Q => \^m_axi_arqos[7]\(17), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(18), Q => \^m_axi_arqos[7]\(18), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(19), Q => \^m_axi_arqos[7]\(19), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(1), Q => \^m_axi_arqos[7]\(1), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(20), Q => \^m_axi_arqos[7]\(20), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(21), Q => \^m_axi_arqos[7]\(21), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(22), Q => \^m_axi_arqos[7]\(22), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(23), Q => \^m_axi_arqos[7]\(23), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(24), Q => \^m_axi_arqos[7]\(24), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(25), Q => \^m_axi_arqos[7]\(25), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(26), Q => \^m_axi_arqos[7]\(26), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(27), Q => \^m_axi_arqos[7]\(27), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(28), Q => \^m_axi_arqos[7]\(28), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(29), Q => \^m_axi_arqos[7]\(29), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(2), Q => \^m_axi_arqos[7]\(2), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(30), Q => \^m_axi_arqos[7]\(30), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(31), Q => \^m_axi_arqos[7]\(31), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(32), Q => \^m_axi_arqos[7]\(32), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(33), Q => \^m_axi_arqos[7]\(33), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(34), Q => \^m_axi_arqos[7]\(34), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(35), Q => \^m_axi_arqos[7]\(35), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(36), Q => \^m_axi_arqos[7]\(36), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(37), Q => \^m_axi_arqos[7]\(37), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(38), Q => \^m_axi_arqos[7]\(38), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(39), Q => \^m_axi_arqos[7]\(39), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(3), Q => \^m_axi_arqos[7]\(3), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(40), Q => \^m_axi_arqos[7]\(40), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(41), Q => \^m_axi_arqos[7]\(41), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(42), Q => \^m_axi_arqos[7]\(42), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(43), Q => \^m_axi_arqos[7]\(43), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(44), Q => \^m_axi_arqos[7]\(44), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(45), Q => \^m_axi_arqos[7]\(45), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(46), Q => \^m_axi_arqos[7]\(46), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(47), Q => \^m_axi_arqos[7]\(47), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(48), Q => \^m_axi_arqos[7]\(48), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(49), Q => \^m_axi_arqos[7]\(49), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(4), Q => \^m_axi_arqos[7]\(4), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(50), Q => \^m_axi_arqos[7]\(50), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(51), Q => \^m_axi_arqos[7]\(51), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(52), Q => \^m_axi_arqos[7]\(52), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(53), Q => \^m_axi_arqos[7]\(53), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(54), Q => \^m_axi_arqos[7]\(54), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(55), Q => \^m_axi_arqos[7]\(55), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(56), Q => \^m_axi_arqos[7]\(56), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(57), Q => \^m_axi_arqos[7]\(57), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(58), Q => \^m_axi_arqos[7]\(58), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(5), Q => \^m_axi_arqos[7]\(5), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(59), Q => \^m_axi_arqos[7]\(59), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(60), Q => \^m_axi_arqos[7]\(60), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(61), Q => \^m_axi_arqos[7]\(61), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(62), Q => \^m_axi_arqos[7]\(62), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(63), Q => \^m_axi_arqos[7]\(63), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(64), Q => \^m_axi_arqos[7]\(64), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(6), Q => \^m_axi_arqos[7]\(6), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(65), Q => \^m_axi_arqos[7]\(65), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(66), Q => \^m_axi_arqos[7]\(66), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(67), Q => \^m_axi_arqos[7]\(67), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(68), Q => \^m_axi_arqos[7]\(68), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(7), Q => \^m_axi_arqos[7]\(7), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(8), Q => \^m_axi_arqos[7]\(8), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_arqos[3]\(9), Q => \^m_axi_arqos[7]\(9), R => SR(0) ); \gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BF80" ) port map ( I0 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0), I1 => m_valid_i, I2 => aresetn_d, I3 => aa_mi_artarget_hot(0), O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ ); \gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00000080" ) port map ( I0 => \s_axi_arqos[3]\(33), I1 => \s_axi_arqos[3]\(36), I2 => \s_axi_araddr[30]\, I3 => \s_axi_araddr[28]\, I4 => \s_axi_araddr[25]\, O => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) ); \gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BF80" ) port map ( I0 => st_aa_artarget_hot(0), I1 => m_valid_i, I2 => aresetn_d, I3 => aa_mi_artarget_hot(1), O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ ); \gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\, Q => aa_mi_artarget_hot(0), R => '0' ); \gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\, Q => aa_mi_artarget_hot(1), R => '0' ); \gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => aresetn_d_reg_0, Q => \^gen_axi.s_axi_rid_i_reg[11]\(0), R => '0' ); \gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF0000002A" ) port map ( I0 => \^aa_mi_arvalid\, I1 => aa_mi_artarget_hot(0), I2 => m_axi_arready(0), I3 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\, I4 => \^gen_no_arbiter.m_valid_i_reg_0\, I5 => m_valid_i, O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\ ); \gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\, Q => \^aa_mi_arvalid\, R => SR(0) ); \gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFEFFFEFFFEFFFFF" ) port map ( I0 => \gen_master_slots[2].r_issuing_cnt_reg[16]\, I1 => \^aa_mi_arvalid\, I2 => s_axi_arvalid(0), I3 => \^s_axi_arready[0]\, I4 => \chosen_reg[0]\, I5 => \gen_multi_thread.accept_cnt_reg[3]\, O => \gen_no_arbiter.s_ready_i_reg[0]_0\ ); \gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn_d_reg, Q => \^s_axi_arready[0]\, R => '0' ); \m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^aa_mi_arvalid\, I1 => aa_mi_artarget_hot(0), O => m_axi_arvalid(0) ); \m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^aa_mi_arvalid\, I1 => aa_mi_artarget_hot(1), O => m_axi_arvalid(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 is port ( ss_aa_awready : out STD_LOGIC; aa_sa_awvalid : out STD_LOGIC; \m_ready_d_reg[0]\ : out STD_LOGIC; \m_ready_d_reg[1]\ : out STD_LOGIC; aa_mi_awtarget_hot : out STD_LOGIC_VECTOR ( 2 downto 0 ); D : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_master_slots[1].w_issuing_cnt_reg[9]\ : out STD_LOGIC; \gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); st_aa_awtarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.m_target_hot_i_reg[2]_0\ : out STD_LOGIC; \m_ready_d_reg[1]_0\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 68 downto 0 ); aresetn_d_reg : in STD_LOGIC; aclk : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 ); aresetn_d : in STD_LOGIC; w_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 ); \chosen_reg[1]\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 ); \chosen_reg[0]\ : in STD_LOGIC; mi_awready_2 : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC; s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); \s_axi_awaddr[26]\ : in STD_LOGIC; \s_axi_awaddr[20]\ : in STD_LOGIC; \s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 ); m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); m_valid_i : in STD_LOGIC; st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 ); aresetn_d_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 is signal \^aa_mi_awtarget_hot\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^aa_sa_awvalid\ : STD_LOGIC; signal \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC; signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC; signal \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC; signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC; signal \^gen_master_slots[1].w_issuing_cnt_reg[9]\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\ : STD_LOGIC; signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC; signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC; signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC; signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC; signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC; signal \^m_ready_d_reg[1]\ : STD_LOGIC; signal s_ready_i2 : STD_LOGIC; signal \^ss_aa_awready\ : STD_LOGIC; signal \^st_aa_awtarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_5\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[9]_i_2\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_2\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \m_ready_d[1]_i_4\ : label is "soft_lutpair12"; begin aa_mi_awtarget_hot(2 downto 0) <= \^aa_mi_awtarget_hot\(2 downto 0); aa_sa_awvalid <= \^aa_sa_awvalid\; \gen_master_slots[1].w_issuing_cnt_reg[9]\ <= \^gen_master_slots[1].w_issuing_cnt_reg[9]\; \m_ready_d_reg[1]\ <= \^m_ready_d_reg[1]\; ss_aa_awready <= \^ss_aa_awready\; st_aa_awtarget_hot(0) <= \^st_aa_awtarget_hot\(0); \gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => m_ready_d(1), I1 => \^aa_sa_awvalid\, I2 => \^aa_mi_awtarget_hot\(2), I3 => mi_awready_2, O => \gen_master_slots[2].w_issuing_cnt_reg[16]\ ); \gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAA95555555" ) port map ( I0 => w_issuing_cnt(0), I1 => \chosen_reg[0]\, I2 => m_axi_awready(0), I3 => \^aa_mi_awtarget_hot\(0), I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\, I5 => w_issuing_cnt(1), O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0) ); \gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7E81" ) port map ( I0 => w_issuing_cnt(0), I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\, I2 => w_issuing_cnt(1), I3 => w_issuing_cnt(2), O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1) ); \gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA55555554" ) port map ( I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\, I1 => w_issuing_cnt(3), I2 => w_issuing_cnt(0), I3 => w_issuing_cnt(2), I4 => w_issuing_cnt(1), I5 => \chosen_reg[0]\, O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0) ); \gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAA9" ) port map ( I0 => w_issuing_cnt(3), I1 => w_issuing_cnt(0), I2 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\, I3 => w_issuing_cnt(1), I4 => w_issuing_cnt(2), O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2) ); \gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => m_ready_d(1), I1 => \^aa_sa_awvalid\, I2 => \^aa_mi_awtarget_hot\(0), I3 => m_axi_awready(0), O => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\ ); \gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"00008000" ) port map ( I0 => \chosen_reg[0]\, I1 => m_axi_awready(0), I2 => \^aa_mi_awtarget_hot\(0), I3 => \^aa_sa_awvalid\, I4 => m_ready_d(1), O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ ); \gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7E81" ) port map ( I0 => w_issuing_cnt(4), I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\, I2 => w_issuing_cnt(5), I3 => w_issuing_cnt(6), O => D(1) ); \gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA55555554" ) port map ( I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\, I1 => w_issuing_cnt(7), I2 => w_issuing_cnt(4), I3 => w_issuing_cnt(6), I4 => w_issuing_cnt(5), I5 => \chosen_reg[1]\, O => E(0) ); \gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAA9" ) port map ( I0 => w_issuing_cnt(7), I1 => w_issuing_cnt(4), I2 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\, I3 => w_issuing_cnt(5), I4 => w_issuing_cnt(6), O => D(2) ); \gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => m_ready_d(1), I1 => \^aa_sa_awvalid\, I2 => \^aa_mi_awtarget_hot\(1), I3 => m_axi_awready(1), O => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\ ); \gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000070000000" ) port map ( I0 => m_valid_i_reg, I1 => s_axi_bready(0), I2 => m_axi_awready(1), I3 => \^aa_mi_awtarget_hot\(1), I4 => \^aa_sa_awvalid\, I5 => m_ready_d(1), O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ ); \gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAA95555555" ) port map ( I0 => w_issuing_cnt(4), I1 => \chosen_reg[1]\, I2 => m_axi_awready(1), I3 => \^aa_mi_awtarget_hot\(1), I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\, I5 => w_issuing_cnt(5), O => D(0) ); \gen_master_slots[1].w_issuing_cnt[9]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^aa_sa_awvalid\, I1 => m_ready_d(1), O => \^gen_master_slots[1].w_issuing_cnt_reg[9]\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"10000000" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\, I1 => \s_axi_awaddr[26]\, I2 => \s_axi_awaddr[20]\, I3 => \s_axi_awqos[3]\(33), I4 => \s_axi_awqos[3]\(36), O => \^st_aa_awtarget_hot\(0) ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \s_axi_awqos[3]\(35), I1 => \s_axi_awqos[3]\(31), I2 => \s_axi_awqos[3]\(28), I3 => \s_axi_awqos[3]\(39), O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\ ); \gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^aa_sa_awvalid\, O => s_ready_i2 ); \gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(0), Q => Q(0), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(10), Q => Q(10), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(11), Q => Q(11), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(12), Q => Q(12), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(13), Q => Q(13), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(14), Q => Q(14), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(15), Q => Q(15), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(16), Q => Q(16), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(17), Q => Q(17), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(18), Q => Q(18), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(19), Q => Q(19), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(1), Q => Q(1), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(20), Q => Q(20), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(21), Q => Q(21), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(22), Q => Q(22), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(23), Q => Q(23), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(24), Q => Q(24), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(25), Q => Q(25), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(26), Q => Q(26), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(27), Q => Q(27), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(28), Q => Q(28), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(29), Q => Q(29), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(2), Q => Q(2), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(30), Q => Q(30), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(31), Q => Q(31), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(32), Q => Q(32), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(33), Q => Q(33), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(34), Q => Q(34), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(35), Q => Q(35), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(36), Q => Q(36), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(37), Q => Q(37), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(38), Q => Q(38), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(39), Q => Q(39), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(3), Q => Q(3), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(40), Q => Q(40), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(41), Q => Q(41), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(42), Q => Q(42), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(43), Q => Q(43), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(44), Q => Q(44), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(45), Q => Q(45), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(46), Q => Q(46), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(47), Q => Q(47), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(48), Q => Q(48), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(49), Q => Q(49), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(4), Q => Q(4), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(50), Q => Q(50), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(51), Q => Q(51), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(52), Q => Q(52), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(53), Q => Q(53), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(54), Q => Q(54), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(55), Q => Q(55), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(56), Q => Q(56), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(57), Q => Q(57), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(58), Q => Q(58), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(5), Q => Q(5), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(59), Q => Q(59), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(60), Q => Q(60), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(61), Q => Q(61), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(62), Q => Q(62), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(63), Q => Q(63), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(64), Q => Q(64), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(6), Q => Q(6), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(65), Q => Q(65), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(66), Q => Q(66), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(67), Q => Q(67), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(68), Q => Q(68), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(7), Q => Q(7), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(8), Q => Q(8), R => SR(0) ); \gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => s_ready_i2, D => \s_axi_awqos[3]\(9), Q => Q(9), R => SR(0) ); \gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BF80" ) port map ( I0 => \^st_aa_awtarget_hot\(0), I1 => m_valid_i, I2 => aresetn_d, I3 => \^aa_mi_awtarget_hot\(0), O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ ); \gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BF80" ) port map ( I0 => st_aa_awtarget_enc(0), I1 => m_valid_i, I2 => aresetn_d, I3 => \^aa_mi_awtarget_hot\(1), O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ ); \gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\, Q => \^aa_mi_awtarget_hot\(0), R => '0' ); \gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\, Q => \^aa_mi_awtarget_hot\(1), R => '0' ); \gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => aresetn_d_reg_0, Q => \^aa_mi_awtarget_hot\(2), R => '0' ); \gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"F2" ) port map ( I0 => \^aa_sa_awvalid\, I1 => \gen_no_arbiter.m_valid_i_i_2_n_0\, I2 => m_valid_i, O => \gen_no_arbiter.m_valid_i_i_1_n_0\ ); \gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FFFE" ) port map ( I0 => \^aa_mi_awtarget_hot\(0), I1 => \^aa_mi_awtarget_hot\(1), I2 => \^aa_mi_awtarget_hot\(2), I3 => m_ready_d(0), I4 => \^m_ready_d_reg[1]\, O => \gen_no_arbiter.m_valid_i_i_2_n_0\ ); \gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \gen_no_arbiter.m_valid_i_i_1_n_0\, Q => \^aa_sa_awvalid\, R => SR(0) ); \gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^ss_aa_awready\, I1 => m_ready_d_0(0), O => \gen_no_arbiter.m_target_hot_i_reg[2]_0\ ); \gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn_d_reg, Q => \^ss_aa_awready\, R => '0' ); \m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"20" ) port map ( I0 => \^aa_mi_awtarget_hot\(0), I1 => m_ready_d(1), I2 => \^aa_sa_awvalid\, O => m_axi_awvalid(0) ); \m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"20" ) port map ( I0 => \^aa_mi_awtarget_hot\(1), I1 => m_ready_d(1), I2 => \^aa_sa_awvalid\, O => m_axi_awvalid(1) ); \m_ready_d[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"55555554FFFFFFFF" ) port map ( I0 => \^m_ready_d_reg[1]\, I1 => m_ready_d(0), I2 => \^aa_mi_awtarget_hot\(2), I3 => \^aa_mi_awtarget_hot\(1), I4 => \^aa_mi_awtarget_hot\(0), I5 => aresetn_d, O => \m_ready_d_reg[0]\ ); \m_ready_d[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => m_ready_d(0), I1 => \^aa_mi_awtarget_hot\(2), I2 => \^aa_mi_awtarget_hot\(1), I3 => \^aa_mi_awtarget_hot\(0), O => \m_ready_d_reg[1]_0\ ); \m_ready_d[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000777" ) port map ( I0 => m_axi_awready(1), I1 => \^aa_mi_awtarget_hot\(1), I2 => mi_awready_2, I3 => \^aa_mi_awtarget_hot\(2), I4 => \m_ready_d[1]_i_4_n_0\, I5 => m_ready_d(1), O => \^m_ready_d_reg[1]\ ); \m_ready_d[1]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => m_axi_awready(0), I1 => \^aa_mi_awtarget_hot\(0), O => \m_ready_d[1]_i_4_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp is port ( \gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC; m_valid_i : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC; \chosen_reg[0]_0\ : out STD_LOGIC; \gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); \chosen_reg[1]_0\ : out STD_LOGIC; \gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC; \gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : out STD_LOGIC; aresetn_d : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_ready_d_reg[1]\ : in STD_LOGIC; p_80_out : in STD_LOGIC; s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); \s_axi_awaddr[26]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ : in STD_LOGIC; \gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC; \gen_master_slots[2].w_issuing_cnt_reg[16]_1\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_ready_d_reg[1]_0\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC; \m_ready_d_reg[1]_1\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_ready_d_reg[1]_2\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); cmd_push_3 : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_ready_d_reg[1]_3\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_ready_d_reg[1]_4\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); cmd_push_0 : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC; aa_sa_awvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC; p_38_out : in STD_LOGIC; p_60_out : in STD_LOGIC; w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 ); \m_ready_d_reg[1]_5\ : in STD_LOGIC; aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp is signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \chosen[0]_i_1__0_n_0\ : STD_LOGIC; signal \chosen[1]_i_1__0_n_0\ : STD_LOGIC; signal \chosen[2]_i_1__0_n_0\ : STD_LOGIC; signal \^chosen_reg[0]_0\ : STD_LOGIC; signal \^chosen_reg[1]_0\ : STD_LOGIC; signal \^gen_master_slots[0].w_issuing_cnt_reg[1]\ : STD_LOGIC; signal \^gen_master_slots[2].w_issuing_cnt_reg[16]\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC; signal \last_rr_hot[0]_i_1_n_0\ : STD_LOGIC; signal \last_rr_hot[1]_i_1_n_0\ : STD_LOGIC; signal \last_rr_hot[2]_i_1_n_0\ : STD_LOGIC; signal \last_rr_hot[2]_i_6_n_0\ : STD_LOGIC; signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC; signal \^m_valid_i\ : STD_LOGIC; signal need_arbitration : STD_LOGIC; signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_3_in : STD_LOGIC; signal p_4_in : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \chosen[0]_i_1__0\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \chosen[2]_i_1__0\ : label is "soft_lutpair112"; attribute use_clock_enable : string; attribute use_clock_enable of \chosen_reg[0]\ : label is "yes"; attribute use_clock_enable of \chosen_reg[1]\ : label is "yes"; attribute use_clock_enable of \chosen_reg[2]\ : label is "yes"; attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \last_rr_hot[2]_i_6\ : label is "soft_lutpair111"; begin SR(0) <= \^sr\(0); \chosen_reg[0]_0\ <= \^chosen_reg[0]_0\; \chosen_reg[1]_0\ <= \^chosen_reg[1]_0\; \gen_master_slots[0].w_issuing_cnt_reg[1]\ <= \^gen_master_slots[0].w_issuing_cnt_reg[1]\; \gen_master_slots[2].w_issuing_cnt_reg[16]\ <= \^gen_master_slots[2].w_issuing_cnt_reg[16]\; m_valid_i <= \^m_valid_i\; \chosen[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => next_rr_hot(0), I1 => need_arbitration, I2 => \^chosen_reg[0]_0\, O => \chosen[0]_i_1__0_n_0\ ); \chosen[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => next_rr_hot(1), I1 => need_arbitration, I2 => \^chosen_reg[1]_0\, O => \chosen[1]_i_1__0_n_0\ ); \chosen[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => next_rr_hot(2), I1 => need_arbitration, I2 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\, O => \chosen[2]_i_1__0_n_0\ ); \chosen_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \chosen[0]_i_1__0_n_0\, Q => \^chosen_reg[0]_0\, R => \^sr\(0) ); \chosen_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \chosen[1]_i_1__0_n_0\, Q => \^chosen_reg[1]_0\, R => \^sr\(0) ); \chosen_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \chosen[2]_i_1__0_n_0\, Q => \^gen_master_slots[2].w_issuing_cnt_reg[16]\, R => \^sr\(0) ); \gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \^chosen_reg[0]_0\, I1 => p_80_out, I2 => s_axi_bready(0), O => \^gen_master_slots[0].w_issuing_cnt_reg[1]\ ); \gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => s_axi_bready(0), I1 => \^chosen_reg[1]_0\, I2 => p_60_out, O => \gen_master_slots[1].w_issuing_cnt_reg[8]\ ); \gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"807F7F00" ) port map ( I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\, I1 => p_38_out, I2 => s_axi_bready(0), I3 => \m_ready_d_reg[1]_5\, I4 => w_issuing_cnt(4), O => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\ ); \gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"A956" ) port map ( I0 => Q(0), I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I2 => \m_ready_d_reg[1]\, I3 => Q(1), O => D(0) ); \gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFF1100E" ) port map ( I0 => \m_ready_d_reg[1]\, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I2 => Q(0), I3 => Q(1), I4 => Q(2), O => D(1) ); \gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFE00000000FFFF" ) port map ( I0 => Q(3), I1 => Q(0), I2 => Q(1), I3 => Q(2), I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I5 => \m_ready_d_reg[1]\, O => \gen_multi_thread.accept_cnt_reg[3]\(0) ); \gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AAAAAAAA999A" ) port map ( I0 => Q(3), I1 => Q(0), I2 => \m_ready_d_reg[1]\, I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I4 => Q(1), I5 => Q(2), O => D(2) ); \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9AAA" ) port map ( I0 => cmd_push_0, I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\, I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0), I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"5955" ) port map ( I0 => \m_ready_d_reg[1]_4\, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\, I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0), O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"5955" ) port map ( I0 => \m_ready_d_reg[1]_3\, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\, I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0), O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9AAA" ) port map ( I0 => cmd_push_3, I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\, I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0), I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"5955" ) port map ( I0 => \m_ready_d_reg[1]_2\, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\, I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0), O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"5955" ) port map ( I0 => \m_ready_d_reg[1]_1\, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\, I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0), O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9555" ) port map ( I0 => \m_ready_d_reg[1]_0\, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0), I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\, O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"5955" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I2 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\, I3 => CO(0), O => E(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"00AAAA80AA80AA80" ) port map ( I0 => s_axi_bready(0), I1 => \^chosen_reg[0]_0\, I2 => p_80_out, I3 => m_valid_i_reg, I4 => p_38_out, I5 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\, O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\ ); \gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aresetn_d, O => \^sr\(0) ); \gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"1FFF1000" ) port map ( I0 => \s_axi_awaddr[26]\(0), I1 => st_aa_awtarget_hot(0), I2 => \^m_valid_i\, I3 => aresetn_d, I4 => aa_mi_awtarget_hot(0), O => \gen_no_arbiter.m_target_hot_i_reg[2]\ ); \gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^m_valid_i\, I1 => aresetn_d, O => \gen_no_arbiter.s_ready_i_reg[0]\ ); \gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"000000000000F022" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\, I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\, I3 => \s_axi_awaddr[26]\(0), I4 => \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\, I5 => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\, O => \^m_valid_i\ ); \gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFF40FFFF" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\, I1 => Q(3), I2 => \gen_multi_thread.accept_cnt_reg[0]\, I3 => aa_sa_awvalid, I4 => s_axi_awvalid(0), I5 => \gen_no_arbiter.s_ready_i_reg[0]_0\, O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT5 generic map( INIT => X"00020000" ) port map ( I0 => \^gen_master_slots[0].w_issuing_cnt_reg[1]\, I1 => w_issuing_cnt(2), I2 => w_issuing_cnt(1), I3 => w_issuing_cnt(0), I4 => w_issuing_cnt(3), O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"EFAAEFEFEFAAEAEA" ) port map ( I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\, I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\, I2 => st_aa_awtarget_hot(0), I3 => \gen_master_slots[1].w_issuing_cnt_reg[10]\, I4 => \s_axi_awaddr[26]\(0), I5 => \gen_master_slots[2].w_issuing_cnt_reg[16]_1\, O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ ); \last_rr_hot[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF57AA00" ) port map ( I0 => need_arbitration, I1 => next_rr_hot(2), I2 => next_rr_hot(1), I3 => next_rr_hot(0), I4 => \last_rr_hot_reg_n_0_[0]\, O => \last_rr_hot[0]_i_1_n_0\ ); \last_rr_hot[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F5F7A0A0" ) port map ( I0 => need_arbitration, I1 => next_rr_hot(2), I2 => next_rr_hot(1), I3 => next_rr_hot(0), I4 => p_3_in, O => \last_rr_hot[1]_i_1_n_0\ ); \last_rr_hot[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"DDDF8888" ) port map ( I0 => need_arbitration, I1 => next_rr_hot(2), I2 => next_rr_hot(1), I3 => next_rr_hot(0), I4 => p_4_in, O => \last_rr_hot[2]_i_1_n_0\ ); \last_rr_hot[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFEE00000FEE" ) port map ( I0 => p_60_out, I1 => p_38_out, I2 => \^chosen_reg[0]_0\, I3 => p_80_out, I4 => \last_rr_hot[2]_i_6_n_0\, I5 => s_axi_bready(0), O => need_arbitration ); \last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA20222020" ) port map ( I0 => p_38_out, I1 => p_60_out, I2 => \last_rr_hot_reg_n_0_[0]\, I3 => p_80_out, I4 => p_4_in, I5 => p_3_in, O => next_rr_hot(2) ); \last_rr_hot[2]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA0A0A0008" ) port map ( I0 => p_60_out, I1 => p_3_in, I2 => p_80_out, I3 => p_38_out, I4 => p_4_in, I5 => \last_rr_hot_reg_n_0_[0]\, O => next_rr_hot(1) ); \last_rr_hot[2]_i_5__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8A8A8A8A88888A88" ) port map ( I0 => p_80_out, I1 => p_4_in, I2 => p_38_out, I3 => \last_rr_hot_reg_n_0_[0]\, I4 => p_60_out, I5 => p_3_in, O => next_rr_hot(0) ); \last_rr_hot[2]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"F888" ) port map ( I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\, I1 => p_38_out, I2 => \^chosen_reg[1]_0\, I3 => p_60_out, O => \last_rr_hot[2]_i_6_n_0\ ); \last_rr_hot_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \last_rr_hot[0]_i_1_n_0\, Q => \last_rr_hot_reg_n_0_[0]\, R => \^sr\(0) ); \last_rr_hot_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \last_rr_hot[1]_i_1_n_0\, Q => p_3_in, R => \^sr\(0) ); \last_rr_hot_reg[2]\: unisim.vcomponents.FDSE port map ( C => aclk, CE => '1', D => \last_rr_hot[2]_i_1_n_0\, Q => p_4_in, S => \^sr\(0) ); \s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF888F888F888" ) port map ( I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\, I1 => p_38_out, I2 => \^chosen_reg[1]_0\, I3 => p_60_out, I4 => p_80_out, I5 => \^chosen_reg[0]_0\, O => s_axi_bvalid(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_5 is port ( D : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.accept_cnt_reg[2]\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[0]_0\ : out STD_LOGIC; s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); \chosen_reg[1]_0\ : out STD_LOGIC; \m_payload_i_reg[34]\ : out STD_LOGIC; s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 ); \m_payload_i_reg[34]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); \gen_no_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC; cmd_push_3 : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC; CO : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ : in STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]_2\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.s_ready_i_reg[0]_3\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ : in STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]_4\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.s_ready_i_reg[0]_5\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); cmd_push_0 : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); p_74_out : in STD_LOGIC; s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); p_54_out : in STD_LOGIC; p_32_out : in STD_LOGIC; \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); \m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_5 : entity is "axi_crossbar_v2_1_14_arbiter_resp"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_5; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_5 is signal \chosen[0]_i_1_n_0\ : STD_LOGIC; signal \chosen[1]_i_1_n_0\ : STD_LOGIC; signal \chosen[2]_i_1_n_0\ : STD_LOGIC; signal \^chosen_reg[1]_0\ : STD_LOGIC; signal \^gen_multi_thread.accept_cnt_reg[2]\ : STD_LOGIC; signal \i__carry_i_10_n_0\ : STD_LOGIC; signal \i__carry_i_11_n_0\ : STD_LOGIC; signal \i__carry_i_12_n_0\ : STD_LOGIC; signal \i__carry_i_13_n_0\ : STD_LOGIC; signal \i__carry_i_14_n_0\ : STD_LOGIC; signal \i__carry_i_15_n_0\ : STD_LOGIC; signal \i__carry_i_16_n_0\ : STD_LOGIC; signal \i__carry_i_5_n_0\ : STD_LOGIC; signal \i__carry_i_6_n_0\ : STD_LOGIC; signal \i__carry_i_7_n_0\ : STD_LOGIC; signal \i__carry_i_8_n_0\ : STD_LOGIC; signal \i__carry_i_9_n_0\ : STD_LOGIC; signal \last_rr_hot[0]_i_1__0_n_0\ : STD_LOGIC; signal \last_rr_hot[1]_i_1__0_n_0\ : STD_LOGIC; signal \last_rr_hot[2]_i_1__0_n_0\ : STD_LOGIC; signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \^m_payload_i_reg[34]\ : STD_LOGIC; signal need_arbitration : STD_LOGIC; signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_3_in : STD_LOGIC; signal p_4_in : STD_LOGIC; signal \s_axi_rid[11]_INST_0_i_1_n_0\ : STD_LOGIC; signal \s_axi_rid[11]_INST_0_i_2_n_0\ : STD_LOGIC; signal \s_axi_rid[11]_INST_0_i_3_n_0\ : STD_LOGIC; signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \chosen[0]_i_1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \chosen[2]_i_1\ : label is "soft_lutpair79"; attribute use_clock_enable : string; attribute use_clock_enable of \chosen_reg[0]\ : label is "yes"; attribute use_clock_enable of \chosen_reg[1]\ : label is "yes"; attribute use_clock_enable of \chosen_reg[2]\ : label is "yes"; attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_2\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_3\ : label is "soft_lutpair78"; begin \chosen_reg[1]_0\ <= \^chosen_reg[1]_0\; \gen_multi_thread.accept_cnt_reg[2]\ <= \^gen_multi_thread.accept_cnt_reg[2]\; \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; \m_payload_i_reg[34]\ <= \^m_payload_i_reg[34]\; s_axi_rlast(0) <= \^s_axi_rlast\(0); \chosen[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => next_rr_hot(0), I1 => need_arbitration, I2 => \^m_payload_i_reg[0]_0\, O => \chosen[0]_i_1_n_0\ ); \chosen[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => next_rr_hot(1), I1 => need_arbitration, I2 => \^chosen_reg[1]_0\, O => \chosen[1]_i_1_n_0\ ); \chosen[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => next_rr_hot(2), I1 => need_arbitration, I2 => \^m_payload_i_reg[34]\, O => \chosen[2]_i_1_n_0\ ); \chosen_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \chosen[0]_i_1_n_0\, Q => \^m_payload_i_reg[0]_0\, R => SR(0) ); \chosen_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \chosen[1]_i_1_n_0\, Q => \^chosen_reg[1]_0\, R => SR(0) ); \chosen_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \chosen[2]_i_1_n_0\, Q => \^m_payload_i_reg[34]\, R => SR(0) ); \gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A659" ) port map ( I0 => Q(0), I1 => \gen_no_arbiter.s_ready_i_reg[0]\, I2 => \^gen_multi_thread.accept_cnt_reg[2]\, I3 => Q(1), O => D(0) ); \gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"BFF4400B" ) port map ( I0 => \^gen_multi_thread.accept_cnt_reg[2]\, I1 => \gen_no_arbiter.s_ready_i_reg[0]\, I2 => Q(0), I3 => Q(1), I4 => Q(2), O => D(1) ); \gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFFFFFE0000" ) port map ( I0 => Q(3), I1 => Q(0), I2 => Q(1), I3 => Q(2), I4 => \^gen_multi_thread.accept_cnt_reg[2]\, I5 => \gen_no_arbiter.s_ready_i_reg[0]\, O => \gen_multi_thread.accept_cnt_reg[3]\(0) ); \gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A6AAAAAAAAAA9A99" ) port map ( I0 => Q(3), I1 => Q(0), I2 => \^gen_multi_thread.accept_cnt_reg[2]\, I3 => \gen_no_arbiter.s_ready_i_reg[0]\, I4 => Q(1), I5 => Q(2), O => D(2) ); \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9AAA" ) port map ( I0 => cmd_push_0, I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\, I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0), I3 => \^gen_multi_thread.accept_cnt_reg[2]\, O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"5955" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_5\, I1 => \^gen_multi_thread.accept_cnt_reg[2]\, I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\, I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0), O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"5955" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_4\, I1 => \^gen_multi_thread.accept_cnt_reg[2]\, I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\, I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0), O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9AAA" ) port map ( I0 => cmd_push_3, I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\, I2 => CO(0), I3 => \^gen_multi_thread.accept_cnt_reg[2]\, O => E(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9555" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_3\, I1 => \^gen_multi_thread.accept_cnt_reg[2]\, I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0), I3 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\, O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"5955" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_2\, I1 => \^gen_multi_thread.accept_cnt_reg[2]\, I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\, I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0), O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9555" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I1 => \^gen_multi_thread.accept_cnt_reg[2]\, I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0), I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\, O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9555" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\, I1 => \^gen_multi_thread.accept_cnt_reg[2]\, I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0), I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\, O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"A8880000" ) port map ( I0 => \^s_axi_rlast\(0), I1 => \s_axi_rid[11]_INST_0_i_1_n_0\, I2 => \^m_payload_i_reg[0]_0\, I3 => p_74_out, I4 => s_axi_rready(0), O => \^gen_multi_thread.accept_cnt_reg[2]\ ); \i__carry_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_2_n_0\, I1 => \m_payload_i_reg[46]_1\(9), I2 => \m_payload_i_reg[46]_0\(22), I3 => \s_axi_rid[11]_INST_0_i_3_n_0\, I4 => \m_payload_i_reg[46]\(22), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_10_n_0\ ); \i__carry_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_2_n_0\, I1 => \m_payload_i_reg[46]_1\(5), I2 => \m_payload_i_reg[46]_0\(18), I3 => \s_axi_rid[11]_INST_0_i_3_n_0\, I4 => \m_payload_i_reg[46]\(18), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_11_n_0\ ); \i__carry_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(17), I2 => \m_payload_i_reg[46]_1\(4), I3 => \s_axi_rid[11]_INST_0_i_2_n_0\, I4 => \m_payload_i_reg[46]_0\(17), I5 => \s_axi_rid[11]_INST_0_i_3_n_0\, O => \i__carry_i_12_n_0\ ); \i__carry_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_3_n_0\, I1 => \m_payload_i_reg[46]_0\(19), I2 => \m_payload_i_reg[46]_1\(6), I3 => \s_axi_rid[11]_INST_0_i_2_n_0\, I4 => \m_payload_i_reg[46]\(19), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_13_n_0\ ); \i__carry_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_2_n_0\, I1 => \m_payload_i_reg[46]_1\(2), I2 => \m_payload_i_reg[46]_0\(15), I3 => \s_axi_rid[11]_INST_0_i_3_n_0\, I4 => \m_payload_i_reg[46]\(15), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_14_n_0\ ); \i__carry_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_3_n_0\, I1 => \m_payload_i_reg[46]_0\(14), I2 => \m_payload_i_reg[46]_1\(1), I3 => \s_axi_rid[11]_INST_0_i_2_n_0\, I4 => \m_payload_i_reg[46]\(14), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_15_n_0\ ); \i__carry_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_2_n_0\, I1 => \m_payload_i_reg[46]_1\(3), I2 => \m_payload_i_reg[46]_0\(16), I3 => \s_axi_rid[11]_INST_0_i_3_n_0\, I4 => \m_payload_i_reg[46]\(16), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_16_n_0\ ); \i__carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10), I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9), I3 => \i__carry_i_6_n_0\, I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11), I5 => \i__carry_i_7_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3) ); \i__carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_8_n_0\, I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7), I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6), I3 => \i__carry_i_9_n_0\, I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8), I5 => \i__carry_i_10_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2) ); \i__carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_11_n_0\, I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4), I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3), I3 => \i__carry_i_12_n_0\, I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5), I5 => \i__carry_i_13_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1) ); \i__carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_14_n_0\, I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1), I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0), I3 => \i__carry_i_15_n_0\, I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2), I5 => \i__carry_i_16_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) ); \i__carry_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_2_n_0\, I1 => \m_payload_i_reg[46]_1\(11), I2 => \m_payload_i_reg[46]\(24), I3 => \s_axi_rid[11]_INST_0_i_1_n_0\, I4 => \m_payload_i_reg[46]_0\(24), I5 => \s_axi_rid[11]_INST_0_i_3_n_0\, O => \i__carry_i_5_n_0\ ); \i__carry_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_3_n_0\, I1 => \m_payload_i_reg[46]_0\(23), I2 => \m_payload_i_reg[46]_1\(10), I3 => \s_axi_rid[11]_INST_0_i_2_n_0\, I4 => \m_payload_i_reg[46]\(23), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_6_n_0\ ); \i__carry_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_3_n_0\, I1 => \m_payload_i_reg[46]_0\(25), I2 => \m_payload_i_reg[46]_1\(12), I3 => \s_axi_rid[11]_INST_0_i_2_n_0\, I4 => \m_payload_i_reg[46]\(25), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_7_n_0\ ); \i__carry_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_2_n_0\, I1 => \m_payload_i_reg[46]_1\(8), I2 => \m_payload_i_reg[46]_0\(21), I3 => \s_axi_rid[11]_INST_0_i_3_n_0\, I4 => \m_payload_i_reg[46]\(21), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_8_n_0\ ); \i__carry_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"BB0BBB0B0000BB0B" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_2_n_0\, I1 => \m_payload_i_reg[46]_1\(7), I2 => \m_payload_i_reg[46]_0\(20), I3 => \s_axi_rid[11]_INST_0_i_3_n_0\, I4 => \m_payload_i_reg[46]\(20), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => \i__carry_i_9_n_0\ ); \last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FF57AA00" ) port map ( I0 => need_arbitration, I1 => next_rr_hot(2), I2 => next_rr_hot(1), I3 => next_rr_hot(0), I4 => \last_rr_hot_reg_n_0_[0]\, O => \last_rr_hot[0]_i_1__0_n_0\ ); \last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F5F7A0A0" ) port map ( I0 => need_arbitration, I1 => next_rr_hot(2), I2 => next_rr_hot(1), I3 => next_rr_hot(0), I4 => p_3_in, O => \last_rr_hot[1]_i_1__0_n_0\ ); \last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"DDDF8888" ) port map ( I0 => need_arbitration, I1 => next_rr_hot(2), I2 => next_rr_hot(1), I3 => next_rr_hot(0), I4 => p_4_in, O => \last_rr_hot[2]_i_1__0_n_0\ ); \last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"ABBBABBBABBBAB88" ) port map ( I0 => s_axi_rready(0), I1 => \s_axi_rid[11]_INST_0_i_1_n_0\, I2 => \^m_payload_i_reg[0]_0\, I3 => p_74_out, I4 => p_54_out, I5 => p_32_out, O => need_arbitration ); \last_rr_hot[2]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA20222020" ) port map ( I0 => p_32_out, I1 => p_54_out, I2 => \last_rr_hot_reg_n_0_[0]\, I3 => p_74_out, I4 => p_4_in, I5 => p_3_in, O => next_rr_hot(2) ); \last_rr_hot[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA0A0A0008" ) port map ( I0 => p_54_out, I1 => p_3_in, I2 => p_74_out, I3 => p_32_out, I4 => p_4_in, I5 => \last_rr_hot_reg_n_0_[0]\, O => next_rr_hot(1) ); \last_rr_hot[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"8A8A8A8A88888A88" ) port map ( I0 => p_74_out, I1 => p_4_in, I2 => p_32_out, I3 => \last_rr_hot_reg_n_0_[0]\, I4 => p_54_out, I5 => p_3_in, O => next_rr_hot(0) ); \last_rr_hot_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \last_rr_hot[0]_i_1__0_n_0\, Q => \last_rr_hot_reg_n_0_[0]\, R => SR(0) ); \last_rr_hot_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \last_rr_hot[1]_i_1__0_n_0\, Q => p_3_in, R => SR(0) ); \last_rr_hot_reg[2]\: unisim.vcomponents.FDSE port map ( C => aclk, CE => '1', D => \last_rr_hot[2]_i_1__0_n_0\, Q => p_4_in, S => SR(0) ); \m_payload_i[46]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B3" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => p_74_out, I2 => s_axi_rready(0), O => \m_payload_i_reg[0]\(0) ); \m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"8F" ) port map ( I0 => s_axi_rready(0), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, O => \m_payload_i_reg[34]_0\(0) ); \p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10), I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9), I3 => \i__carry_i_6_n_0\, I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11), I5 => \i__carry_i_7_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) ); \p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_8_n_0\, I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7), I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6), I3 => \i__carry_i_9_n_0\, I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8), I5 => \i__carry_i_10_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) ); \p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_11_n_0\, I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4), I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3), I3 => \i__carry_i_12_n_0\, I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5), I5 => \i__carry_i_13_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) ); \p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_14_n_0\, I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1), I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0), I3 => \i__carry_i_15_n_0\, I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2), I5 => \i__carry_i_16_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) ); \p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9), I3 => \i__carry_i_6_n_0\, I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11), I5 => \i__carry_i_7_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) ); \p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_8_n_0\, I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6), I3 => \i__carry_i_9_n_0\, I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8), I5 => \i__carry_i_10_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) ); \p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_11_n_0\, I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3), I3 => \i__carry_i_12_n_0\, I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5), I5 => \i__carry_i_13_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) ); \p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_14_n_0\, I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0), I3 => \i__carry_i_15_n_0\, I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2), I5 => \i__carry_i_16_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) ); \p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10), I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9), I3 => \i__carry_i_6_n_0\, I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11), I5 => \i__carry_i_7_n_0\, O => S(3) ); \p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_8_n_0\, I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7), I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6), I3 => \i__carry_i_9_n_0\, I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8), I5 => \i__carry_i_10_n_0\, O => S(2) ); \p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_11_n_0\, I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4), I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3), I3 => \i__carry_i_12_n_0\, I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5), I5 => \i__carry_i_13_n_0\, O => S(1) ); \p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_14_n_0\, I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1), I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0), I3 => \i__carry_i_15_n_0\, I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2), I5 => \i__carry_i_16_n_0\, O => S(0) ); \p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10), I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9), I3 => \i__carry_i_6_n_0\, I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11), I5 => \i__carry_i_7_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) ); \p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_8_n_0\, I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7), I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6), I3 => \i__carry_i_9_n_0\, I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8), I5 => \i__carry_i_10_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) ); \p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_11_n_0\, I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4), I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3), I3 => \i__carry_i_12_n_0\, I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5), I5 => \i__carry_i_13_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) ); \p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_14_n_0\, I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1), I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0), I3 => \i__carry_i_15_n_0\, I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2), I5 => \i__carry_i_16_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) ); \p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10), I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9), I3 => \i__carry_i_6_n_0\, I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11), I5 => \i__carry_i_7_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) ); \p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_8_n_0\, I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7), I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6), I3 => \i__carry_i_9_n_0\, I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8), I5 => \i__carry_i_10_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) ); \p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_11_n_0\, I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4), I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3), I3 => \i__carry_i_12_n_0\, I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5), I5 => \i__carry_i_13_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) ); \p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_14_n_0\, I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1), I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0), I3 => \i__carry_i_15_n_0\, I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2), I5 => \i__carry_i_16_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) ); \p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10), I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9), I3 => \i__carry_i_6_n_0\, I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11), I5 => \i__carry_i_7_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) ); \p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_8_n_0\, I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7), I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6), I3 => \i__carry_i_9_n_0\, I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8), I5 => \i__carry_i_10_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) ); \p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_11_n_0\, I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4), I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3), I3 => \i__carry_i_12_n_0\, I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5), I5 => \i__carry_i_13_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) ); \p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_14_n_0\, I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1), I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0), I3 => \i__carry_i_15_n_0\, I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2), I5 => \i__carry_i_16_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) ); \p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10), I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9), I3 => \i__carry_i_6_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11), I5 => \i__carry_i_7_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3) ); \p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_8_n_0\, I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7), I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6), I3 => \i__carry_i_9_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8), I5 => \i__carry_i_10_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2) ); \p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_11_n_0\, I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4), I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3), I3 => \i__carry_i_12_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5), I5 => \i__carry_i_13_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1) ); \p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \i__carry_i_14_n_0\, I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1), I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0), I3 => \i__carry_i_15_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2), I5 => \i__carry_i_16_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) ); \s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(0), O => s_axi_rdata(0) ); \s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(5), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(5), O => s_axi_rdata(5) ); \s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(6), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(6), O => s_axi_rdata(6) ); \s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(7), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(7), O => s_axi_rdata(7) ); \s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(8), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(8), O => s_axi_rdata(8) ); \s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(9), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(9), O => s_axi_rdata(9) ); \s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(10), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(10), O => s_axi_rdata(10) ); \s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(11), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(11), O => s_axi_rdata(11) ); \s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(1), O => s_axi_rdata(1) ); \s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(2), O => s_axi_rdata(2) ); \s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(3), O => s_axi_rdata(3) ); \s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3F2A2A2A002A2A2A" ) port map ( I0 => \m_payload_i_reg[46]\(4), I1 => \^m_payload_i_reg[34]\, I2 => p_32_out, I3 => \^chosen_reg[1]_0\, I4 => p_54_out, I5 => \m_payload_i_reg[46]_0\(4), O => s_axi_rdata(4) ); \s_axi_rid[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(14), I2 => \s_axi_rid[11]_INST_0_i_2_n_0\, I3 => \m_payload_i_reg[46]_1\(1), I4 => \m_payload_i_reg[46]_0\(14), I5 => \s_axi_rid[11]_INST_0_i_3_n_0\, O => s_axi_rid(0) ); \s_axi_rid[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_3_n_0\, I1 => \m_payload_i_reg[46]_0\(24), I2 => \s_axi_rid[11]_INST_0_i_1_n_0\, I3 => \m_payload_i_reg[46]\(24), I4 => \m_payload_i_reg[46]_1\(11), I5 => \s_axi_rid[11]_INST_0_i_2_n_0\, O => s_axi_rid(10) ); \s_axi_rid[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(25), I2 => \s_axi_rid[11]_INST_0_i_2_n_0\, I3 => \m_payload_i_reg[46]_1\(12), I4 => \m_payload_i_reg[46]_0\(25), I5 => \s_axi_rid[11]_INST_0_i_3_n_0\, O => s_axi_rid(11) ); \s_axi_rid[11]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F888" ) port map ( I0 => \^m_payload_i_reg[34]\, I1 => p_32_out, I2 => \^chosen_reg[1]_0\, I3 => p_54_out, O => \s_axi_rid[11]_INST_0_i_1_n_0\ ); \s_axi_rid[11]_INST_0_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8FFF" ) port map ( I0 => \^chosen_reg[1]_0\, I1 => p_54_out, I2 => \^m_payload_i_reg[34]\, I3 => p_32_out, O => \s_axi_rid[11]_INST_0_i_2_n_0\ ); \s_axi_rid[11]_INST_0_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"8FFF" ) port map ( I0 => \^m_payload_i_reg[34]\, I1 => p_32_out, I2 => \^chosen_reg[1]_0\, I3 => p_54_out, O => \s_axi_rid[11]_INST_0_i_3_n_0\ ); \s_axi_rid[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(15), I2 => \s_axi_rid[11]_INST_0_i_3_n_0\, I3 => \m_payload_i_reg[46]_0\(15), I4 => \m_payload_i_reg[46]_1\(2), I5 => \s_axi_rid[11]_INST_0_i_2_n_0\, O => s_axi_rid(1) ); \s_axi_rid[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(16), I2 => \s_axi_rid[11]_INST_0_i_3_n_0\, I3 => \m_payload_i_reg[46]_0\(16), I4 => \m_payload_i_reg[46]_1\(3), I5 => \s_axi_rid[11]_INST_0_i_2_n_0\, O => s_axi_rid(2) ); \s_axi_rid[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_3_n_0\, I1 => \m_payload_i_reg[46]_0\(17), I2 => \s_axi_rid[11]_INST_0_i_2_n_0\, I3 => \m_payload_i_reg[46]_1\(4), I4 => \m_payload_i_reg[46]\(17), I5 => \s_axi_rid[11]_INST_0_i_1_n_0\, O => s_axi_rid(3) ); \s_axi_rid[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(18), I2 => \s_axi_rid[11]_INST_0_i_3_n_0\, I3 => \m_payload_i_reg[46]_0\(18), I4 => \m_payload_i_reg[46]_1\(5), I5 => \s_axi_rid[11]_INST_0_i_2_n_0\, O => s_axi_rid(4) ); \s_axi_rid[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(19), I2 => \s_axi_rid[11]_INST_0_i_2_n_0\, I3 => \m_payload_i_reg[46]_1\(6), I4 => \m_payload_i_reg[46]_0\(19), I5 => \s_axi_rid[11]_INST_0_i_3_n_0\, O => s_axi_rid(5) ); \s_axi_rid[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(20), I2 => \s_axi_rid[11]_INST_0_i_3_n_0\, I3 => \m_payload_i_reg[46]_0\(20), I4 => \m_payload_i_reg[46]_1\(7), I5 => \s_axi_rid[11]_INST_0_i_2_n_0\, O => s_axi_rid(6) ); \s_axi_rid[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(21), I2 => \s_axi_rid[11]_INST_0_i_3_n_0\, I3 => \m_payload_i_reg[46]_0\(21), I4 => \m_payload_i_reg[46]_1\(8), I5 => \s_axi_rid[11]_INST_0_i_2_n_0\, O => s_axi_rid(7) ); \s_axi_rid[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(22), I2 => \s_axi_rid[11]_INST_0_i_3_n_0\, I3 => \m_payload_i_reg[46]_0\(22), I4 => \m_payload_i_reg[46]_1\(9), I5 => \s_axi_rid[11]_INST_0_i_2_n_0\, O => s_axi_rid(8) ); \s_axi_rid[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"4F444F44FFFF4F44" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_1_n_0\, I1 => \m_payload_i_reg[46]\(23), I2 => \s_axi_rid[11]_INST_0_i_2_n_0\, I3 => \m_payload_i_reg[46]_1\(10), I4 => \m_payload_i_reg[46]_0\(23), I5 => \s_axi_rid[11]_INST_0_i_3_n_0\, O => s_axi_rid(9) ); \s_axi_rlast[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"44F444F4FFFF44F4" ) port map ( I0 => \s_axi_rid[11]_INST_0_i_2_n_0\, I1 => \m_payload_i_reg[46]_1\(0), I2 => \m_payload_i_reg[46]\(13), I3 => \s_axi_rid[11]_INST_0_i_1_n_0\, I4 => \m_payload_i_reg[46]_0\(13), I5 => \s_axi_rid[11]_INST_0_i_3_n_0\, O => \^s_axi_rlast\(0) ); \s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3FEAEAEA00EAEAEA" ) port map ( I0 => \m_payload_i_reg[46]\(12), I1 => p_32_out, I2 => \^m_payload_i_reg[34]\, I3 => p_54_out, I4 => \^chosen_reg[1]_0\, I5 => \m_payload_i_reg[46]_0\(12), O => s_axi_rresp(0) ); \s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF888F888F888" ) port map ( I0 => p_54_out, I1 => \^chosen_reg[1]_0\, I2 => p_32_out, I3 => \^m_payload_i_reg[34]\, I4 => \^m_payload_i_reg[0]_0\, I5 => p_74_out, O => s_axi_rvalid(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is port ( mi_awready_2 : out STD_LOGIC; p_14_in : out STD_LOGIC; p_21_in : out STD_LOGIC; p_15_in : out STD_LOGIC; p_17_in : out STD_LOGIC; \gen_axi.write_cs_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); mi_arready_2 : out STD_LOGIC; \gen_axi.s_axi_arready_i_reg_0\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 11 downto 0 ); \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); aclk : in STD_LOGIC; aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); aa_sa_awvalid : in STD_LOGIC; m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.m_target_hot_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); aa_mi_arvalid : in STD_LOGIC; mi_rready_2 : in STD_LOGIC; \gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 ); \gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC; mi_bready_2 : in STD_LOGIC; \m_ready_d_reg[1]\ : in STD_LOGIC; \storage_data1_reg[0]\ : in STD_LOGIC; s_axi_rlast_i0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); aresetn_d : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC; signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC; signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 ); signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC; signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC; signal \^gen_axi.s_axi_arready_i_reg_0\ : STD_LOGIC; signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC; signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC; signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC; signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC; signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC; signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC; signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC; signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC; signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC; signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC; signal \^gen_axi.write_cs_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^mi_arready_2\ : STD_LOGIC; signal \^mi_awready_2\ : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \^p_14_in\ : STD_LOGIC; signal \^p_15_in\ : STD_LOGIC; signal \^p_17_in\ : STD_LOGIC; signal \^p_21_in\ : STD_LOGIC; signal write_cs : STD_LOGIC_VECTOR ( 0 to 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_3\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_2\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_4\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_5\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair15"; begin \gen_axi.s_axi_arready_i_reg_0\ <= \^gen_axi.s_axi_arready_i_reg_0\; \gen_axi.write_cs_reg[1]_0\(0) <= \^gen_axi.write_cs_reg[1]_0\(0); mi_arready_2 <= \^mi_arready_2\; mi_awready_2 <= \^mi_awready_2\; p_14_in <= \^p_14_in\; p_15_in <= \^p_15_in\; p_17_in <= \^p_17_in\; p_21_in <= \^p_21_in\; \gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"74" ) port map ( I0 => \gen_axi.read_cnt_reg\(0), I1 => \^p_15_in\, I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12), O => p_0_in(0) ); \gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"9F90" ) port map ( I0 => \gen_axi.read_cnt_reg\(0), I1 => \gen_axi.read_cnt_reg__0\(1), I2 => \^p_15_in\, I3 => \gen_no_arbiter.m_mesg_i_reg[51]\(13), O => p_0_in(1) ); \gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"A9FFA900" ) port map ( I0 => \gen_axi.read_cnt_reg__0\(2), I1 => \gen_axi.read_cnt_reg__0\(1), I2 => \gen_axi.read_cnt_reg\(0), I3 => \^p_15_in\, I4 => \gen_no_arbiter.m_mesg_i_reg[51]\(14), O => p_0_in(2) ); \gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA9FFFFAAA90000" ) port map ( I0 => \gen_axi.read_cnt_reg__0\(3), I1 => \gen_axi.read_cnt_reg__0\(2), I2 => \gen_axi.read_cnt_reg\(0), I3 => \gen_axi.read_cnt_reg__0\(1), I4 => \^p_15_in\, I5 => \gen_no_arbiter.m_mesg_i_reg[51]\(15), O => p_0_in(3) ); \gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FACAFAFACACACACA" ) port map ( I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16), I1 => \gen_axi.read_cnt[7]_i_3_n_0\, I2 => \^p_15_in\, I3 => \gen_axi.read_cnt_reg__0\(3), I4 => \gen_axi.read_cnt[4]_i_2_n_0\, I5 => \gen_axi.read_cnt_reg__0\(4), O => p_0_in(4) ); \gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => \gen_axi.read_cnt_reg__0\(1), I1 => \gen_axi.read_cnt_reg\(0), I2 => \gen_axi.read_cnt_reg__0\(2), O => \gen_axi.read_cnt[4]_i_2_n_0\ ); \gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"3CAA" ) port map ( I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17), I1 => \gen_axi.read_cnt[7]_i_3_n_0\, I2 => \gen_axi.read_cnt_reg__0\(5), I3 => \^p_15_in\, O => p_0_in(5) ); \gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EE2E22E2" ) port map ( I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18), I1 => \^p_15_in\, I2 => \gen_axi.read_cnt[7]_i_3_n_0\, I3 => \gen_axi.read_cnt_reg__0\(5), I4 => \gen_axi.read_cnt_reg__0\(6), O => p_0_in(6) ); \gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00800080FF800080" ) port map ( I0 => \^mi_arready_2\, I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0), I2 => aa_mi_arvalid, I3 => \^p_15_in\, I4 => mi_rready_2, I5 => \^gen_axi.s_axi_arready_i_reg_0\, O => \gen_axi.read_cnt[7]_i_1_n_0\ ); \gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"B8B8B8B8B8B874B8" ) port map ( I0 => \gen_axi.read_cnt_reg__0\(7), I1 => \^p_15_in\, I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(19), I3 => \gen_axi.read_cnt[7]_i_3_n_0\, I4 => \gen_axi.read_cnt_reg__0\(5), I5 => \gen_axi.read_cnt_reg__0\(6), O => p_0_in(7) ); \gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \gen_axi.read_cnt_reg\(0), I1 => \gen_axi.read_cnt_reg__0\(2), I2 => \gen_axi.read_cnt_reg__0\(1), I3 => \gen_axi.read_cnt_reg__0\(4), I4 => \gen_axi.read_cnt_reg__0\(3), O => \gen_axi.read_cnt[7]_i_3_n_0\ ); \gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.read_cnt[7]_i_1_n_0\, D => p_0_in(0), Q => \gen_axi.read_cnt_reg\(0), R => SR(0) ); \gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.read_cnt[7]_i_1_n_0\, D => p_0_in(1), Q => \gen_axi.read_cnt_reg__0\(1), R => SR(0) ); \gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.read_cnt[7]_i_1_n_0\, D => p_0_in(2), Q => \gen_axi.read_cnt_reg__0\(2), R => SR(0) ); \gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.read_cnt[7]_i_1_n_0\, D => p_0_in(3), Q => \gen_axi.read_cnt_reg__0\(3), R => SR(0) ); \gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.read_cnt[7]_i_1_n_0\, D => p_0_in(4), Q => \gen_axi.read_cnt_reg__0\(4), R => SR(0) ); \gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.read_cnt[7]_i_1_n_0\, D => p_0_in(5), Q => \gen_axi.read_cnt_reg__0\(5), R => SR(0) ); \gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.read_cnt[7]_i_1_n_0\, D => p_0_in(6), Q => \gen_axi.read_cnt_reg__0\(6), R => SR(0) ); \gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.read_cnt[7]_i_1_n_0\, D => p_0_in(7), Q => \gen_axi.read_cnt_reg__0\(7), R => SR(0) ); \gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0080FF80FF80FF80" ) port map ( I0 => \^mi_arready_2\, I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0), I2 => aa_mi_arvalid, I3 => \^p_15_in\, I4 => mi_rready_2, I5 => \^gen_axi.s_axi_arready_i_reg_0\, O => \gen_axi.read_cs[0]_i_1_n_0\ ); \gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \gen_axi.read_cs[0]_i_1_n_0\, Q => \^p_15_in\, R => SR(0) ); \gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FBBB0000" ) port map ( I0 => \^mi_arready_2\, I1 => \^p_15_in\, I2 => mi_rready_2, I3 => \^gen_axi.s_axi_arready_i_reg_0\, I4 => aresetn_d, I5 => E(0), O => \gen_axi.s_axi_arready_i_i_1_n_0\ ); \gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \gen_axi.read_cnt[7]_i_3_n_0\, I1 => \gen_axi.read_cnt_reg__0\(5), I2 => \gen_axi.read_cnt_reg__0\(6), I3 => \gen_axi.read_cnt_reg__0\(7), O => \^gen_axi.s_axi_arready_i_reg_0\ ); \gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \gen_axi.s_axi_arready_i_i_1_n_0\, Q => \^mi_arready_2\, R => '0' ); \gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF7F70F000F0F" ) port map ( I0 => \gen_no_arbiter.m_valid_i_reg\, I1 => aa_mi_awtarget_hot(0), I2 => write_cs(0), I3 => mi_bready_2, I4 => \^gen_axi.write_cs_reg[1]_0\(0), I5 => \^mi_awready_2\, O => \gen_axi.s_axi_awready_i_i_1_n_0\ ); \gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \gen_axi.s_axi_awready_i_i_1_n_0\, Q => \^mi_awready_2\, R => SR(0) ); \gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000010000000" ) port map ( I0 => write_cs(0), I1 => \^gen_axi.write_cs_reg[1]_0\(0), I2 => \^mi_awready_2\, I3 => aa_mi_awtarget_hot(0), I4 => aa_sa_awvalid, I5 => m_ready_d(0), O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\ ); \gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(0), Q => Q(0), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(10), Q => Q(10), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(11), Q => Q(11), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(1), Q => Q(1), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(2), Q => Q(2), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(3), Q => Q(3), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(4), Q => Q(4), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(5), Q => Q(5), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(6), Q => Q(6), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(7), Q => Q(7), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(8), Q => Q(8), R => SR(0) ); \gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, D => \gen_no_arbiter.m_mesg_i_reg[11]\(9), Q => Q(9), R => SR(0) ); \gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EFFFA888" ) port map ( I0 => \storage_data1_reg[0]\, I1 => write_cs(0), I2 => \^gen_axi.write_cs_reg[1]_0\(0), I3 => mi_bready_2, I4 => \^p_21_in\, O => \gen_axi.s_axi_bvalid_i_i_1_n_0\ ); \gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \gen_axi.s_axi_bvalid_i_i_1_n_0\, Q => \^p_21_in\, R => SR(0) ); \gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(0), Q => \skid_buffer_reg[46]\(0), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(10), Q => \skid_buffer_reg[46]\(10), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(11), Q => \skid_buffer_reg[46]\(11), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(1), Q => \skid_buffer_reg[46]\(1), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(2), Q => \skid_buffer_reg[46]\(2), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(3), Q => \skid_buffer_reg[46]\(3), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(4), Q => \skid_buffer_reg[46]\(4), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(5), Q => \skid_buffer_reg[46]\(5), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(6), Q => \skid_buffer_reg[46]\(6), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(7), Q => \skid_buffer_reg[46]\(7), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(8), Q => \skid_buffer_reg[46]\(8), R => SR(0) ); \gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \gen_no_arbiter.m_mesg_i_reg[51]\(9), Q => \skid_buffer_reg[46]\(9), R => SR(0) ); \gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"BBBBBBBA8888888A" ) port map ( I0 => s_axi_rlast_i0, I1 => E(0), I2 => \gen_axi.s_axi_rlast_i_i_3_n_0\, I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\, I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\, I5 => \^p_17_in\, O => \gen_axi.s_axi_rlast_i_i_1_n_0\ ); \gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => \gen_axi.read_cnt_reg__0\(7), I1 => \gen_axi.read_cnt_reg__0\(6), I2 => \gen_axi.read_cnt_reg__0\(5), O => \gen_axi.s_axi_rlast_i_i_3_n_0\ ); \gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \^p_15_in\, I1 => mi_rready_2, O => \gen_axi.s_axi_rlast_i_i_4_n_0\ ); \gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \gen_axi.read_cnt_reg__0\(3), I1 => \gen_axi.read_cnt_reg__0\(4), I2 => \gen_axi.read_cnt_reg__0\(1), I3 => \gen_axi.read_cnt_reg__0\(2), O => \gen_axi.s_axi_rlast_i_i_5_n_0\ ); \gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_axi.s_axi_rlast_i_i_1_n_0\, Q => \^p_17_in\, R => SR(0) ); \gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0FFF0202" ) port map ( I0 => \m_ready_d_reg[1]\, I1 => \^gen_axi.write_cs_reg[1]_0\(0), I2 => write_cs(0), I3 => \storage_data1_reg[0]\, I4 => \^p_14_in\, O => \gen_axi.s_axi_wready_i_i_1_n_0\ ); \gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \gen_axi.s_axi_wready_i_i_1_n_0\, Q => \^p_14_in\, R => SR(0) ); \gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0252" ) port map ( I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, I1 => \^gen_axi.write_cs_reg[1]_0\(0), I2 => write_cs(0), I3 => \storage_data1_reg[0]\, O => \gen_axi.write_cs[0]_i_1_n_0\ ); \gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF10FA10" ) port map ( I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\, I1 => mi_bready_2, I2 => \^gen_axi.write_cs_reg[1]_0\(0), I3 => write_cs(0), I4 => \storage_data1_reg[0]\, O => \gen_axi.write_cs[1]_i_1_n_0\ ); \gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_axi.write_cs[0]_i_1_n_0\, Q => write_cs(0), R => SR(0) ); \gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_axi.write_cs[1]_i_1_n_0\, Q => \^gen_axi.write_cs_reg[1]_0\(0), R => SR(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is port ( s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 ); \gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC; ss_wr_awvalid : out STD_LOGIC; ss_aa_awready : in STD_LOGIC; ss_wr_awready : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); aresetn_d : in STD_LOGIC; aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC; signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\ : label is "soft_lutpair141"; attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair141"; begin m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0); \FSM_onehot_state[3]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s_axi_awvalid(0), I1 => \^m_ready_d\(1), O => ss_wr_awvalid ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"111F" ) port map ( I0 => \^m_ready_d\(1), I1 => ss_wr_awready, I2 => \^m_ready_d\(0), I3 => ss_aa_awready, O => \gen_multi_thread.accept_cnt_reg[3]\ ); \m_ready_d[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0302030000000000" ) port map ( I0 => s_axi_awvalid(0), I1 => \^m_ready_d\(1), I2 => ss_wr_awready, I3 => \^m_ready_d\(0), I4 => ss_aa_awready, I5 => aresetn_d, O => \m_ready_d[0]_i_1_n_0\ ); \m_ready_d[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000000EC00000000" ) port map ( I0 => s_axi_awvalid(0), I1 => \^m_ready_d\(1), I2 => ss_wr_awready, I3 => \^m_ready_d\(0), I4 => ss_aa_awready, I5 => aresetn_d, O => \m_ready_d[1]_i_1_n_0\ ); \m_ready_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_ready_d[0]_i_1_n_0\, Q => \^m_ready_d\(0), R => '0' ); \m_ready_d_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_ready_d[1]_i_1_n_0\, Q => \^m_ready_d\(1), R => '0' ); \s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"EEE0" ) port map ( I0 => ss_aa_awready, I1 => \^m_ready_d\(0), I2 => ss_wr_awready, I3 => \^m_ready_d\(1), O => s_axi_awready(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_3 is port ( m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 ); aa_sa_awvalid : in STD_LOGIC; aresetn_d : in STD_LOGIC; \m_ready_d_reg[0]_0\ : in STD_LOGIC; \gen_no_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC; aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_ready_d_reg[0]_1\ : in STD_LOGIC; aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_3 : entity is "axi_crossbar_v2_1_14_splitter"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_3; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_3 is signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC; signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC; begin m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0); \m_ready_d[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EEEEEEEC" ) port map ( I0 => aa_sa_awvalid, I1 => \^m_ready_d\(0), I2 => aa_mi_awtarget_hot(2), I3 => aa_mi_awtarget_hot(1), I4 => aa_mi_awtarget_hot(0), I5 => \m_ready_d_reg[0]_1\, O => \m_ready_d[0]_i_1_n_0\ ); \m_ready_d[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000000E0" ) port map ( I0 => aa_sa_awvalid, I1 => \^m_ready_d\(1), I2 => aresetn_d, I3 => \m_ready_d_reg[0]_0\, I4 => \gen_no_arbiter.m_target_hot_i_reg[1]\, O => \m_ready_d[1]_i_1_n_0\ ); \m_ready_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_ready_d[0]_i_1_n_0\, Q => \^m_ready_d\(0), R => '0' ); \m_ready_d_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_ready_d[1]_i_1_n_0\, Q => \^m_ready_d\(1), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is port ( \storage_data1_reg[0]\ : out STD_LOGIC; push : in STD_LOGIC; st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 ); fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC; attribute BOX_TYPE : string; attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE"; attribute srl_bus_name : string; attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls "; attribute srl_name : string; attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst "; begin \gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 3) => B"00", A(2 downto 0) => fifoaddr(2 downto 0), CE => push, CLK => aclk, D => st_aa_awtarget_enc(0), Q => \storage_data1_reg[0]\, Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is port ( push : out STD_LOGIC; \storage_data1_reg[1]\ : out STD_LOGIC; s_ready_i_reg : out STD_LOGIC; \gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ); fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); aclk : in STD_LOGIC; st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 ); st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); out0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); load_s1 : in STD_LOGIC; \storage_data1_reg[1]_0\ : in STD_LOGIC; s_ready_i_reg_0 : in STD_LOGIC; m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_avalid : in STD_LOGIC; m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 ); p_14_in : in STD_LOGIC; \storage_data1_reg[0]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is signal \FSM_onehot_state[3]_i_6_n_0\ : STD_LOGIC; signal \^gen_rep[0].fifoaddr_reg[0]\ : STD_LOGIC; signal p_2_out : STD_LOGIC; signal \^push\ : STD_LOGIC; signal \^s_ready_i_reg\ : STD_LOGIC; signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC; attribute BOX_TYPE : string; attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE"; attribute srl_bus_name : string; attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls "; attribute srl_name : string; attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst "; begin \gen_rep[0].fifoaddr_reg[0]\ <= \^gen_rep[0].fifoaddr_reg[0]\; push <= \^push\; s_ready_i_reg <= \^s_ready_i_reg\; \FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => \FSM_onehot_state[3]_i_6_n_0\, I1 => s_axi_wlast(0), I2 => s_axi_wvalid(0), I3 => m_avalid, O => \^gen_rep[0].fifoaddr_reg[0]\ ); \FSM_onehot_state[3]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"F035FF35" ) port map ( I0 => m_axi_wready(0), I1 => p_14_in, I2 => \storage_data1_reg[1]_0\, I3 => \storage_data1_reg[0]\, I4 => m_axi_wready(1), O => \FSM_onehot_state[3]_i_6_n_0\ ); \gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 3) => B"00", A(2 downto 0) => fifoaddr(2 downto 0), CE => \^push\, CLK => aclk, D => D(0), Q => p_2_out, Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ ); \gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^s_ready_i_reg\, O => \^push\ ); \gen_primitive_shifter.gen_srls[0].srl_inst_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0DFFFFFFDDFFFF" ) port map ( I0 => out0(1), I1 => \^gen_rep[0].fifoaddr_reg[0]\, I2 => s_ready_i_reg_0, I3 => m_ready_d(0), I4 => s_axi_awvalid(0), I5 => out0(0), O => \^s_ready_i_reg\ ); \storage_data1[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F011FFFFF0110000" ) port map ( I0 => st_aa_awtarget_enc(0), I1 => st_aa_awtarget_hot(0), I2 => p_2_out, I3 => out0(0), I4 => load_s1, I5 => \storage_data1_reg[1]_0\, O => \storage_data1_reg[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is port ( \m_payload_i_reg[2]_0\ : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; mi_bready_2 : out STD_LOGIC; s_ready_i_reg_0 : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC; \gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); aclk : in STD_LOGIC; p_1_in : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; p_21_in : in STD_LOGIC; chosen : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 ); m_valid_i_reg_1 : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 ); D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\ : STD_LOGIC; signal \^m_payload_i_reg[2]_0\ : STD_LOGIC; signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^mi_bready_2\ : STD_LOGIC; signal \s_axi_bid[6]_INST_0_i_1_n_0\ : STD_LOGIC; signal \s_axi_bid[7]_INST_0_i_1_n_0\ : STD_LOGIC; signal \s_axi_bid[8]_INST_0_i_1_n_0\ : STD_LOGIC; signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal st_mr_bid : STD_LOGIC_VECTOR ( 35 downto 24 ); begin \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\; \m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; mi_bready_2 <= \^mi_bready_2\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \aresetn_d_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \aresetn_d_reg[0]\, Q => \^s_ready_i_reg_0\, R => '0' ); \gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => w_issuing_cnt(0), I1 => s_axi_bready(0), I2 => \^m_payload_i_reg[2]_0\, I3 => chosen(0), O => \gen_no_arbiter.m_target_hot_i_reg[2]\ ); \i__carry_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \s_axi_bid[7]_INST_0_i_1_n_0\, I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(1), I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(0), I3 => \s_axi_bid[6]_INST_0_i_1_n_0\, I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2), I5 => \s_axi_bid[8]_INST_0_i_1_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) ); \m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^m_payload_i_reg[2]_0\, O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\ ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(8), Q => st_mr_bid(32), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(9), Q => st_mr_bid(33), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(10), Q => Q(4), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(11), Q => st_mr_bid(35), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(0), Q => st_mr_bid(24), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(1), Q => Q(0), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(2), Q => Q(1), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(3), Q => Q(2), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(4), Q => st_mr_bid(28), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(5), Q => Q(3), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(6), Q => st_mr_bid(30), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\, D => D(7), Q => st_mr_bid(31), R => '0' ); \m_valid_i_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"8BBBBBBB" ) port map ( I0 => p_21_in, I1 => \^mi_bready_2\, I2 => s_axi_bready(0), I3 => \^m_payload_i_reg[2]_0\, I4 => chosen(0), O => \m_valid_i_i_1__1_n_0\ ); \m_valid_i_i_1__5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^s_ready_i_reg_0\, O => \^m_valid_i_reg_0\ ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_valid_i_i_1__1_n_0\, Q => \^m_payload_i_reg[2]_0\, R => \^m_valid_i_reg_0\ ); p_10_out_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \s_axi_bid[7]_INST_0_i_1_n_0\, I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(1), I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(0), I3 => \s_axi_bid[6]_INST_0_i_1_n_0\, I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2), I5 => \s_axi_bid[8]_INST_0_i_1_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) ); p_12_out_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \s_axi_bid[7]_INST_0_i_1_n_0\, I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(1), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(0), I3 => \s_axi_bid[6]_INST_0_i_1_n_0\, I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2), I5 => \s_axi_bid[8]_INST_0_i_1_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) ); p_14_out_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \s_axi_bid[7]_INST_0_i_1_n_0\, I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(1), I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(0), I3 => \s_axi_bid[6]_INST_0_i_1_n_0\, I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2), I5 => \s_axi_bid[8]_INST_0_i_1_n_0\, O => S(0) ); p_2_out_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \s_axi_bid[7]_INST_0_i_1_n_0\, I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(1), I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(0), I3 => \s_axi_bid[6]_INST_0_i_1_n_0\, I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2), I5 => \s_axi_bid[8]_INST_0_i_1_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) ); p_4_out_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \s_axi_bid[7]_INST_0_i_1_n_0\, I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(1), I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(0), I3 => \s_axi_bid[6]_INST_0_i_1_n_0\, I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2), I5 => \s_axi_bid[8]_INST_0_i_1_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) ); p_6_out_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \s_axi_bid[7]_INST_0_i_1_n_0\, I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(1), I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(0), I3 => \s_axi_bid[6]_INST_0_i_1_n_0\, I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2), I5 => \s_axi_bid[8]_INST_0_i_1_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) ); p_8_out_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \s_axi_bid[7]_INST_0_i_1_n_0\, I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(1), I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(0), I3 => \s_axi_bid[6]_INST_0_i_1_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2), I5 => \s_axi_bid[8]_INST_0_i_1_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) ); \s_axi_bid[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\, O => s_axi_bid(0) ); \s_axi_bid[0]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0003555FFFF3555" ) port map ( I0 => \m_payload_i_reg[13]_0\(0), I1 => st_mr_bid(24), I2 => \^m_payload_i_reg[2]_0\, I3 => chosen(0), I4 => m_valid_i_reg_1, I5 => \m_payload_i_reg[13]_0\(7), O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ ); \s_axi_bid[11]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\, O => s_axi_bid(6) ); \s_axi_bid[11]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0003555FFFF3555" ) port map ( I0 => \m_payload_i_reg[13]_0\(6), I1 => st_mr_bid(35), I2 => \^m_payload_i_reg[2]_0\, I3 => chosen(0), I4 => m_valid_i_reg_1, I5 => \m_payload_i_reg[13]_0\(13), O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ ); \s_axi_bid[4]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\, O => s_axi_bid(1) ); \s_axi_bid[4]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0003555FFFF3555" ) port map ( I0 => \m_payload_i_reg[13]_0\(1), I1 => st_mr_bid(28), I2 => \^m_payload_i_reg[2]_0\, I3 => chosen(0), I4 => m_valid_i_reg_1, I5 => \m_payload_i_reg[13]_0\(8), O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ ); \s_axi_bid[6]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \s_axi_bid[6]_INST_0_i_1_n_0\, O => s_axi_bid(2) ); \s_axi_bid[6]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0003555FFFF3555" ) port map ( I0 => \m_payload_i_reg[13]_0\(2), I1 => st_mr_bid(30), I2 => \^m_payload_i_reg[2]_0\, I3 => chosen(0), I4 => m_valid_i_reg_1, I5 => \m_payload_i_reg[13]_0\(9), O => \s_axi_bid[6]_INST_0_i_1_n_0\ ); \s_axi_bid[7]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \s_axi_bid[7]_INST_0_i_1_n_0\, O => s_axi_bid(3) ); \s_axi_bid[7]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0003555FFFF3555" ) port map ( I0 => \m_payload_i_reg[13]_0\(3), I1 => st_mr_bid(31), I2 => \^m_payload_i_reg[2]_0\, I3 => chosen(0), I4 => m_valid_i_reg_1, I5 => \m_payload_i_reg[13]_0\(10), O => \s_axi_bid[7]_INST_0_i_1_n_0\ ); \s_axi_bid[8]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \s_axi_bid[8]_INST_0_i_1_n_0\, O => s_axi_bid(4) ); \s_axi_bid[8]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F5303030F53F3F3F" ) port map ( I0 => st_mr_bid(32), I1 => \m_payload_i_reg[13]_0\(11), I2 => m_valid_i_reg_1, I3 => \^m_payload_i_reg[2]_0\, I4 => chosen(0), I5 => \m_payload_i_reg[13]_0\(4), O => \s_axi_bid[8]_INST_0_i_1_n_0\ ); \s_axi_bid[9]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\, O => s_axi_bid(5) ); \s_axi_bid[9]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0003555FFFF3555" ) port map ( I0 => \m_payload_i_reg[13]_0\(5), I1 => st_mr_bid(33), I2 => \^m_payload_i_reg[2]_0\, I3 => chosen(0), I4 => m_valid_i_reg_1, I5 => \m_payload_i_reg[13]_0\(12), O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ ); \s_ready_i_i_1__5\: unisim.vcomponents.LUT5 generic map( INIT => X"B111FFFF" ) port map ( I0 => \^m_payload_i_reg[2]_0\, I1 => p_21_in, I2 => chosen(0), I3 => s_axi_bready(0), I4 => \^s_ready_i_reg_0\, O => \s_ready_i_i_1__5_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__5_n_0\, Q => \^mi_bready_2\, R => p_1_in ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is port ( \m_payload_i_reg[0]_0\ : out STD_LOGIC; m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); p_1_in : out STD_LOGIC; \gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC; \gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); \aresetn_d_reg[1]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[1]_0\ : in STD_LOGIC; aclk : in STD_LOGIC; aresetn : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen : in STD_LOGIC_VECTOR ( 1 downto 0 ); \aresetn_d_reg[1]_1\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); p_38_out : in STD_LOGIC; \m_payload_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); D : in STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ : entity is "axi_register_slice_v2_1_13_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is signal \^gen_multi_thread.accept_cnt_reg[3]\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC; signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 ); signal \^p_1_in\ : STD_LOGIC; signal \s_ready_i_i_2__0_n_0\ : STD_LOGIC; signal st_mr_bid : STD_LOGIC_VECTOR ( 22 downto 13 ); signal st_mr_bmesg : STD_LOGIC_VECTOR ( 4 downto 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \s_axi_bid[11]_INST_0_i_2\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \s_ready_i_i_2__0\ : label is "soft_lutpair44"; begin \gen_multi_thread.accept_cnt_reg[3]\ <= \^gen_multi_thread.accept_cnt_reg[3]\; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\; m_axi_bready(0) <= \^m_axi_bready\(0); \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; p_1_in <= \^p_1_in\; \aresetn_d[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => p_0_in(1), I1 => aresetn, O => \aresetn_d_reg[1]\ ); \aresetn_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn, Q => p_0_in(1), R => '0' ); \gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000700000000" ) port map ( I0 => \^gen_multi_thread.accept_cnt_reg[3]\, I1 => s_axi_bready(0), I2 => Q(2), I3 => Q(1), I4 => Q(0), I5 => Q(3), O => \gen_no_arbiter.m_target_hot_i_reg[2]\ ); \m_payload_i[13]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^m_payload_i_reg[0]_0\, O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(0), Q => st_mr_bmesg(3), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(10), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(4), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(11), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(5), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(12), Q => st_mr_bid(22), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(13), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(1), Q => st_mr_bmesg(4), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(2), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(0), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(3), Q => st_mr_bid(13), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(4), Q => st_mr_bid(14), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(5), Q => st_mr_bid(15), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(6), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(1), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(7), Q => st_mr_bid(17), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(8), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(2), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\, D => D(9), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(3), R => '0' ); \m_valid_i_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8BBBBBBB" ) port map ( I0 => m_axi_bvalid(0), I1 => \^m_axi_bready\(0), I2 => s_axi_bready(0), I3 => chosen(0), I4 => \^m_payload_i_reg[0]_0\, O => \m_valid_i_i_1__0_n_0\ ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_valid_i_i_1__0_n_0\, Q => \^m_payload_i_reg[0]_0\, R => \aresetn_d_reg[1]_0\ ); \s_axi_bid[10]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\, O => s_axi_bid(4) ); \s_axi_bid[10]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0353535FF353535" ) port map ( I0 => \m_payload_i_reg[12]_0\(4), I1 => st_mr_bid(22), I2 => \^gen_multi_thread.accept_cnt_reg[3]\, I3 => p_38_out, I4 => chosen(1), I5 => \m_payload_i_reg[12]_0\(9), O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ ); \s_axi_bid[11]_INST_0_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => chosen(0), O => \^gen_multi_thread.accept_cnt_reg[3]\ ); \s_axi_bid[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\, O => s_axi_bid(0) ); \s_axi_bid[1]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0353535FF353535" ) port map ( I0 => \m_payload_i_reg[12]_0\(0), I1 => st_mr_bid(13), I2 => \^gen_multi_thread.accept_cnt_reg[3]\, I3 => p_38_out, I4 => chosen(1), I5 => \m_payload_i_reg[12]_0\(5), O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ ); \s_axi_bid[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\, O => s_axi_bid(1) ); \s_axi_bid[2]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0535353FF535353" ) port map ( I0 => st_mr_bid(14), I1 => \m_payload_i_reg[12]_0\(1), I2 => \^gen_multi_thread.accept_cnt_reg[3]\, I3 => p_38_out, I4 => chosen(1), I5 => \m_payload_i_reg[12]_0\(6), O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ ); \s_axi_bid[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\, O => s_axi_bid(2) ); \s_axi_bid[3]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0535353FF535353" ) port map ( I0 => st_mr_bid(15), I1 => \m_payload_i_reg[12]_0\(2), I2 => \^gen_multi_thread.accept_cnt_reg[3]\, I3 => p_38_out, I4 => chosen(1), I5 => \m_payload_i_reg[12]_0\(7), O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ ); \s_axi_bid[5]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\, O => s_axi_bid(3) ); \s_axi_bid[5]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0353535FF353535" ) port map ( I0 => \m_payload_i_reg[12]_0\(3), I1 => st_mr_bid(17), I2 => \^gen_multi_thread.accept_cnt_reg[3]\, I3 => p_38_out, I4 => chosen(1), I5 => \m_payload_i_reg[12]_0\(8), O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ ); \s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"3FBFBFBF3F808080" ) port map ( I0 => st_mr_bmesg(3), I1 => chosen(0), I2 => \^m_payload_i_reg[0]_0\, I3 => chosen(1), I4 => p_38_out, I5 => \m_payload_i_reg[1]_0\(0), O => s_axi_bresp(0) ); \s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"0CCCFAAAFAAAFAAA" ) port map ( I0 => \m_payload_i_reg[1]_0\(1), I1 => st_mr_bmesg(4), I2 => chosen(1), I3 => p_38_out, I4 => \^m_payload_i_reg[0]_0\, I5 => chosen(0), O => s_axi_bresp(1) ); \s_ready_i_i_1__3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => p_0_in(1), O => \^p_1_in\ ); \s_ready_i_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B111FFFF" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => m_axi_bvalid(0), I2 => s_axi_bready(0), I3 => chosen(0), I4 => \aresetn_d_reg[1]_1\, O => \s_ready_i_i_2__0_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_2__0_n_0\, Q => \^m_axi_bready\(0), R => \^p_1_in\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is port ( \m_payload_i_reg[0]_0\ : out STD_LOGIC; m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \aresetn_d_reg[1]\ : in STD_LOGIC; aclk : in STD_LOGIC; p_1_in : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); \aresetn_d_reg[1]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ : entity is "axi_register_slice_v2_1_13_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal m_valid_i_i_2_n_0 : STD_LOGIC; signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC; begin m_axi_bready(0) <= \^m_axi_bready\(0); \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; \m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^m_payload_i_reg[0]_0\, O => \m_payload_i[13]_i_1__1_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(0), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(10), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(11), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(12), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(13), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(1), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(2), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(3), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(4), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(5), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(6), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(7), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(8), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \m_payload_i[13]_i_1__1_n_0\, D => D(9), Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(9), R => '0' ); m_valid_i_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"8BBBBBBB" ) port map ( I0 => m_axi_bvalid(0), I1 => \^m_axi_bready\(0), I2 => chosen(0), I3 => \^m_payload_i_reg[0]_0\, I4 => s_axi_bready(0), O => m_valid_i_i_2_n_0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i_i_2_n_0, Q => \^m_payload_i_reg[0]_0\, R => \aresetn_d_reg[1]\ ); \s_ready_i_i_1__4\: unisim.vcomponents.LUT5 generic map( INIT => X"B111FFFF" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => m_axi_bvalid(0), I2 => chosen(0), I3 => s_axi_bready(0), I4 => \aresetn_d_reg[1]_0\, O => \s_ready_i_i_1__4_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__4_n_0\, Q => \^m_axi_bready\(0), R => p_1_in ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is port ( m_valid_i_reg_0 : out STD_LOGIC; \skid_buffer_reg[34]_0\ : out STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); \gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC; \aresetn_d_reg[1]\ : in STD_LOGIC; aclk : in STD_LOGIC; p_1_in : in STD_LOGIC; r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 ); st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 ); \gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC; \gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC; p_15_in : in STD_LOGIC; s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); p_17_in : in STD_LOGIC; \gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 ); signal \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 ); signal \^skid_buffer_reg[34]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair69"; begin \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0); m_valid_i_reg_0 <= \^m_valid_i_reg_0\; \skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\; \gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"955555552AAAAAAA" ) port map ( I0 => \gen_axi.s_axi_arready_i_reg\, I1 => s_axi_rready(0), I2 => chosen_0(0), I3 => \^m_valid_i_reg_0\, I4 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0), I5 => r_issuing_cnt(0), O => \gen_master_slots[2].r_issuing_cnt_reg[16]\ ); \gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0FF2020000F202" ) port map ( I0 => r_issuing_cnt(0), I1 => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\, I2 => st_aa_artarget_hot(0), I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\, I4 => st_aa_artarget_hot(1), I5 => \gen_master_slots[1].r_issuing_cnt_reg[8]\, O => \gen_no_arbiter.s_ready_i_reg[0]\ ); \gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0), I1 => \^m_valid_i_reg_0\, I2 => chosen_0(0), I3 => s_axi_rready(0), O => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\ ); \m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => p_17_in, I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(0), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(1), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(2), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[37]\, O => skid_buffer(37) ); \m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(3), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(4), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(5), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[40]\, O => skid_buffer(40) ); \m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(6), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[41]\, O => skid_buffer(41) ); \m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(7), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[42]\, O => skid_buffer(42) ); \m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(8), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[43]\, O => skid_buffer(43) ); \m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(9), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(10), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \gen_axi.s_axi_rid_i_reg[11]\(11), I1 => \^skid_buffer_reg[34]_0\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(34), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(35), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(36), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(37), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(38), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(39), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(40), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(41), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(42), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(43), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(44), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(45), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(46), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12), R => '0' ); \m_valid_i_i_1__4\: unisim.vcomponents.LUT5 generic map( INIT => X"FF70FFFF" ) port map ( I0 => s_axi_rready(0), I1 => chosen_0(0), I2 => \^m_valid_i_reg_0\, I3 => p_15_in, I4 => \^skid_buffer_reg[34]_0\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^m_valid_i_reg_0\, R => \aresetn_d_reg[1]\ ); \s_ready_i_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"F444FFFF" ) port map ( I0 => p_15_in, I1 => \^skid_buffer_reg[34]_0\, I2 => s_axi_rready(0), I3 => chosen_0(0), I4 => \^m_valid_i_reg_0\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^skid_buffer_reg[34]_0\, R => p_1_in ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => p_17_in, Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(2), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(3), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(4), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(5), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(6), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(7), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(8), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(9), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(10), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[34]_0\, D => \gen_axi.s_axi_rid_i_reg[11]\(11), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is port ( s_ready_i_reg_0 : out STD_LOGIC; \m_axi_rready[1]\ : out STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC; \gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); \gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC; \aresetn_d_reg[1]\ : in STD_LOGIC; aclk : in STD_LOGIC; p_1_in : in STD_LOGIC; s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[32]_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 ); p_32_out : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ : entity is "axi_register_slice_v2_1_13_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is signal \^gen_master_slots[1].r_issuing_cnt_reg[8]\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 25 downto 0 ); signal \^m_axi_rready[1]\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal p_1_in_0 : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal st_mr_rmesg : STD_LOGIC_VECTOR ( 68 downto 35 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_6\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__3\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_valid_i_i_1__3\ : label is "soft_lutpair45"; begin \gen_master_slots[1].r_issuing_cnt_reg[8]\ <= \^gen_master_slots[1].r_issuing_cnt_reg[8]\; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0); \m_axi_rready[1]\ <= \^m_axi_rready[1]\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13), I1 => \^s_ready_i_reg_0\, I2 => chosen_0(0), I3 => s_axi_rready(0), O => \^gen_master_slots[1].r_issuing_cnt_reg[8]\ ); \gen_master_slots[1].r_issuing_cnt[11]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^s_ready_i_reg_0\, I1 => chosen_0(0), O => \gen_master_slots[1].r_issuing_cnt_reg[11]\ ); \gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000100" ) port map ( I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(0), I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(1), I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(2), I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3), I4 => \^gen_master_slots[1].r_issuing_cnt_reg[8]\, O => \gen_no_arbiter.s_ready_i_reg[0]\ ); \m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(0), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[0]\, O => skid_buffer(0) ); \m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(10), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(11), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(12), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(13), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(14), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(15), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(16), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(17), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(18), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(19), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); \m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(1), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[1]\, O => skid_buffer(1) ); \m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(20), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(21), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(22), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(23), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(24), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(25), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(26), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(27), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(28), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(29), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(2), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); \m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(30), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(31), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rresp(0), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rresp(1), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rlast(0), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(0), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(1), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(2), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[37]\, O => skid_buffer(37) ); \m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(3), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(4), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(3), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(5), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[40]\, O => skid_buffer(40) ); \m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(6), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[41]\, O => skid_buffer(41) ); \m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(7), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[42]\, O => skid_buffer(42) ); \m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(8), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[43]\, O => skid_buffer(43) ); \m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(9), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(10), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"D5" ) port map ( I0 => \^s_ready_i_reg_0\, I1 => s_axi_rready(0), I2 => chosen_0(0), O => p_1_in_0 ); \m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(11), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(4), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(5), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(6), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(7), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(8), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(9), I1 => \^m_axi_rready[1]\, I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(0), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(10), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(11), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(12), Q => st_mr_rmesg(50), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(13), Q => st_mr_rmesg(51), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(14), Q => st_mr_rmesg(52), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(15), Q => st_mr_rmesg(53), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(16), Q => st_mr_rmesg(54), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(17), Q => st_mr_rmesg(55), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(18), Q => st_mr_rmesg(56), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(19), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(1), Q => st_mr_rmesg(39), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(20), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(21), Q => st_mr_rmesg(59), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(22), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(23), Q => st_mr_rmesg(61), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(24), Q => st_mr_rmesg(62), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(25), Q => st_mr_rmesg(63), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(26), Q => st_mr_rmesg(64), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(27), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(28), Q => st_mr_rmesg(66), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(29), Q => st_mr_rmesg(67), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(2), Q => st_mr_rmesg(40), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(30), Q => st_mr_rmesg(68), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(31), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(32), Q => st_mr_rmesg(35), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(33), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(34), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(35), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(36), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(37), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(38), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(39), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(3), Q => st_mr_rmesg(41), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(40), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(41), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(42), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(43), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(44), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(45), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(46), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(4), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(5), Q => st_mr_rmesg(43), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(6), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(7), Q => st_mr_rmesg(45), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(8), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in_0, D => skid_buffer(9), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4), R => '0' ); \m_valid_i_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"FF2AFFFF" ) port map ( I0 => \^s_ready_i_reg_0\, I1 => s_axi_rready(0), I2 => chosen_0(0), I3 => m_axi_rvalid(0), I4 => \^m_axi_rready[1]\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^s_ready_i_reg_0\, R => \aresetn_d_reg[1]\ ); \s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(50), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(5), O => s_axi_rdata(5) ); \s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(51), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(6), O => s_axi_rdata(6) ); \s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(52), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(7), O => s_axi_rdata(7) ); \s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(53), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(8), O => s_axi_rdata(8) ); \s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(54), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(9), O => s_axi_rdata(9) ); \s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(55), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(10), O => s_axi_rdata(10) ); \s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(56), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(11), O => s_axi_rdata(11) ); \s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(39), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(0), O => s_axi_rdata(0) ); \s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(59), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(12), O => s_axi_rdata(12) ); \s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(61), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(13), O => s_axi_rdata(13) ); \s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(62), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(14), O => s_axi_rdata(14) ); \s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(63), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(15), O => s_axi_rdata(15) ); \s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(64), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(16), O => s_axi_rdata(16) ); \s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(66), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(17), O => s_axi_rdata(17) ); \s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(67), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(18), O => s_axi_rdata(18) ); \s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(40), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(1), O => s_axi_rdata(1) ); \s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(68), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(19), O => s_axi_rdata(19) ); \s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(41), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(2), O => s_axi_rdata(2) ); \s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(43), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(3), O => s_axi_rdata(3) ); \s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"2A3F3F3F2A000000" ) port map ( I0 => st_mr_rmesg(45), I1 => chosen_0(1), I2 => p_32_out, I3 => chosen_0(0), I4 => \^s_ready_i_reg_0\, I5 => \m_payload_i_reg[32]_0\(4), O => s_axi_rdata(4) ); \s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"0FFFACCCACCCACCC" ) port map ( I0 => st_mr_rmesg(35), I1 => \m_payload_i_reg[32]_0\(20), I2 => \^s_ready_i_reg_0\, I3 => chosen_0(0), I4 => p_32_out, I5 => chosen_0(1), O => s_axi_rresp(0) ); \s_ready_i_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FF4F4F4F" ) port map ( I0 => m_axi_rvalid(0), I1 => \^m_axi_rready[1]\, I2 => \^s_ready_i_reg_0\, I3 => s_axi_rready(0), I4 => chosen_0(0), O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^m_axi_rready[1]\, R => p_1_in ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rresp(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rresp(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rlast(0), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(2), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(3), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(4), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(5), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(6), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(7), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(8), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(9), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(10), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rid(11), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[1]\, D => m_axi_rdata(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is port ( m_valid_i_reg_0 : out STD_LOGIC; \m_axi_rready[0]\ : out STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC; \gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); \aresetn_d_reg[1]\ : in STD_LOGIC; aclk : in STD_LOGIC; p_1_in : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is signal \^gen_master_slots[0].r_issuing_cnt_reg[0]\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 ); signal \^m_axi_rready[0]\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair39"; begin \gen_master_slots[0].r_issuing_cnt_reg[0]\ <= \^gen_master_slots[0].r_issuing_cnt_reg[0]\; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0); \m_axi_rready[0]\ <= \^m_axi_rready[0]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; \gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34), I1 => s_axi_rready(0), I2 => \^m_valid_i_reg_0\, I3 => chosen_0(0), O => \^gen_master_slots[0].r_issuing_cnt_reg[0]\ ); \gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000100" ) port map ( I0 => Q(0), I1 => Q(1), I2 => Q(2), I3 => Q(3), I4 => \^gen_master_slots[0].r_issuing_cnt_reg[0]\, O => \gen_no_arbiter.s_ready_i_reg[0]\ ); \m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(0), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[0]\, O => skid_buffer(0) ); \m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(10), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(11), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(12), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(13), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(14), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(15), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(16), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(17), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(18), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(19), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); \m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(1), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[1]\, O => skid_buffer(1) ); \m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(20), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(21), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(22), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(23), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(24), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(25), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(26), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(27), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(28), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(29), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(2), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); \m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(30), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(31), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rresp(0), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rresp(1), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rlast(0), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(0), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(1), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(2), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[37]\, O => skid_buffer(37) ); \m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(3), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(4), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(3), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(5), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[40]\, O => skid_buffer(40) ); \m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(6), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[41]\, O => skid_buffer(41) ); \m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(7), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[42]\, O => skid_buffer(42) ); \m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(8), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[43]\, O => skid_buffer(43) ); \m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(9), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(10), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rid(11), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(4), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(5), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(6), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(7), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(8), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => m_axi_rdata(9), I1 => \^m_axi_rready[0]\, I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(0), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(10), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(11), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(12), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(13), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(14), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(15), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(16), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(17), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(18), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(19), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(1), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(20), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(21), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(22), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(23), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(24), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(25), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(26), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(27), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(28), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(29), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(2), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(30), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(31), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(32), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(33), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(34), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(35), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(36), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(37), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(38), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(39), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(3), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(40), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(41), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(42), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(43), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(44), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(45), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(46), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(4), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(5), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(6), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(7), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(8), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(9), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9), R => '0' ); \m_valid_i_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"FF4CFFFF" ) port map ( I0 => chosen_0(0), I1 => \^m_valid_i_reg_0\, I2 => s_axi_rready(0), I3 => m_axi_rvalid(0), I4 => \^m_axi_rready[0]\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^m_valid_i_reg_0\, R => \aresetn_d_reg[1]\ ); s_ready_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"F4FF44FF" ) port map ( I0 => m_axi_rvalid(0), I1 => \^m_axi_rready[0]\, I2 => chosen_0(0), I3 => \^m_valid_i_reg_0\, I4 => s_axi_rready(0), O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^m_axi_rready[0]\, R => p_1_in ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rresp(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rresp(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rlast(0), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(2), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(3), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(4), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(5), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(6), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(7), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(8), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(9), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(10), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rid(11), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^m_axi_rready[0]\, D => m_axi_rdata(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor is port ( \gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC; m_valid_i : out STD_LOGIC; \gen_multi_thread.accept_cnt_reg[2]_0\ : out STD_LOGIC; \gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC; st_aa_artarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : out STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); chosen : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 ); \m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); aresetn_d : in STD_LOGIC; \s_axi_araddr[25]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC; \s_axi_araddr[25]_0\ : in STD_LOGIC; \gen_no_arbiter.m_target_hot_i_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC; \s_axi_araddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 ); p_74_out : in STD_LOGIC; s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); p_54_out : in STD_LOGIC; p_32_out : in STD_LOGIC; \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); \m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 ); \m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); aclk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor is signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 ); signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 ); signal aid_match_00 : STD_LOGIC; signal aid_match_00_carry_i_1_n_0 : STD_LOGIC; signal aid_match_00_carry_i_2_n_0 : STD_LOGIC; signal aid_match_00_carry_i_3_n_0 : STD_LOGIC; signal aid_match_00_carry_i_4_n_0 : STD_LOGIC; signal aid_match_00_carry_n_1 : STD_LOGIC; signal aid_match_00_carry_n_2 : STD_LOGIC; signal aid_match_00_carry_n_3 : STD_LOGIC; signal aid_match_10 : STD_LOGIC; signal aid_match_10_carry_i_1_n_0 : STD_LOGIC; signal aid_match_10_carry_i_2_n_0 : STD_LOGIC; signal aid_match_10_carry_i_3_n_0 : STD_LOGIC; signal aid_match_10_carry_i_4_n_0 : STD_LOGIC; signal aid_match_10_carry_n_1 : STD_LOGIC; signal aid_match_10_carry_n_2 : STD_LOGIC; signal aid_match_10_carry_n_3 : STD_LOGIC; signal aid_match_20 : STD_LOGIC; signal aid_match_20_carry_i_1_n_0 : STD_LOGIC; signal aid_match_20_carry_i_2_n_0 : STD_LOGIC; signal aid_match_20_carry_i_3_n_0 : STD_LOGIC; signal aid_match_20_carry_i_4_n_0 : STD_LOGIC; signal aid_match_20_carry_n_1 : STD_LOGIC; signal aid_match_20_carry_n_2 : STD_LOGIC; signal aid_match_20_carry_n_3 : STD_LOGIC; signal aid_match_30 : STD_LOGIC; signal aid_match_30_carry_i_1_n_0 : STD_LOGIC; signal aid_match_30_carry_i_2_n_0 : STD_LOGIC; signal aid_match_30_carry_i_3_n_0 : STD_LOGIC; signal aid_match_30_carry_i_4_n_0 : STD_LOGIC; signal aid_match_30_carry_n_1 : STD_LOGIC; signal aid_match_30_carry_n_2 : STD_LOGIC; signal aid_match_30_carry_n_3 : STD_LOGIC; signal aid_match_40 : STD_LOGIC; signal aid_match_40_carry_i_1_n_0 : STD_LOGIC; signal aid_match_40_carry_i_2_n_0 : STD_LOGIC; signal aid_match_40_carry_i_3_n_0 : STD_LOGIC; signal aid_match_40_carry_i_4_n_0 : STD_LOGIC; signal aid_match_40_carry_n_1 : STD_LOGIC; signal aid_match_40_carry_n_2 : STD_LOGIC; signal aid_match_40_carry_n_3 : STD_LOGIC; signal aid_match_50 : STD_LOGIC; signal aid_match_50_carry_i_1_n_0 : STD_LOGIC; signal aid_match_50_carry_i_2_n_0 : STD_LOGIC; signal aid_match_50_carry_i_3_n_0 : STD_LOGIC; signal aid_match_50_carry_i_4_n_0 : STD_LOGIC; signal aid_match_50_carry_n_1 : STD_LOGIC; signal aid_match_50_carry_n_2 : STD_LOGIC; signal aid_match_50_carry_n_3 : STD_LOGIC; signal aid_match_60 : STD_LOGIC; signal aid_match_60_carry_i_1_n_0 : STD_LOGIC; signal aid_match_60_carry_i_2_n_0 : STD_LOGIC; signal aid_match_60_carry_i_3_n_0 : STD_LOGIC; signal aid_match_60_carry_i_4_n_0 : STD_LOGIC; signal aid_match_60_carry_n_1 : STD_LOGIC; signal aid_match_60_carry_n_2 : STD_LOGIC; signal aid_match_60_carry_n_3 : STD_LOGIC; signal aid_match_70 : STD_LOGIC; signal aid_match_70_carry_i_1_n_0 : STD_LOGIC; signal aid_match_70_carry_i_2_n_0 : STD_LOGIC; signal aid_match_70_carry_i_3_n_0 : STD_LOGIC; signal aid_match_70_carry_i_4_n_0 : STD_LOGIC; signal aid_match_70_carry_n_1 : STD_LOGIC; signal aid_match_70_carry_n_2 : STD_LOGIC; signal aid_match_70_carry_n_3 : STD_LOGIC; signal cmd_push_0 : STD_LOGIC; signal cmd_push_1 : STD_LOGIC; signal cmd_push_2 : STD_LOGIC; signal cmd_push_3 : STD_LOGIC; signal cmd_push_4 : STD_LOGIC; signal cmd_push_5 : STD_LOGIC; signal cmd_push_6 : STD_LOGIC; signal cmd_push_7 : STD_LOGIC; signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \gen_multi_thread.arbiter_resp_inst_n_0\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_1\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_20\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_21\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_22\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_23\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_24\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_25\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_26\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_27\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_28\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_29\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_30\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_31\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_32\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_33\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_34\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_35\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_36\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_37\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_38\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_39\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_40\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_41\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_42\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_43\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_44\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_45\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_46\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_47\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_48\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_49\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_5\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_50\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_51\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_6\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_7\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_8\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_13_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC; signal \^m_valid_i\ : STD_LOGIC; signal p_0_out : STD_LOGIC; signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC; signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC; signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC; signal p_10_out : STD_LOGIC; signal p_10_out_carry_n_1 : STD_LOGIC; signal p_10_out_carry_n_2 : STD_LOGIC; signal p_10_out_carry_n_3 : STD_LOGIC; signal p_12_out : STD_LOGIC; signal p_12_out_carry_n_1 : STD_LOGIC; signal p_12_out_carry_n_2 : STD_LOGIC; signal p_12_out_carry_n_3 : STD_LOGIC; signal p_14_out : STD_LOGIC; signal p_14_out_carry_n_1 : STD_LOGIC; signal p_14_out_carry_n_2 : STD_LOGIC; signal p_14_out_carry_n_3 : STD_LOGIC; signal p_2_out : STD_LOGIC; signal p_2_out_carry_n_1 : STD_LOGIC; signal p_2_out_carry_n_2 : STD_LOGIC; signal p_2_out_carry_n_3 : STD_LOGIC; signal p_4_out : STD_LOGIC; signal p_4_out_carry_n_1 : STD_LOGIC; signal p_4_out_carry_n_2 : STD_LOGIC; signal p_4_out_carry_n_3 : STD_LOGIC; signal p_6_out : STD_LOGIC; signal p_6_out_carry_n_1 : STD_LOGIC; signal p_6_out_carry_n_2 : STD_LOGIC; signal p_6_out_carry_n_3 : STD_LOGIC; signal p_8_out : STD_LOGIC; signal p_8_out_carry_n_1 : STD_LOGIC; signal p_8_out_carry_n_2 : STD_LOGIC; signal p_8_out_carry_n_3 : STD_LOGIC; signal \^st_aa_artarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1__0\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1__0\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_24__0\ : label is "soft_lutpair99"; begin \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\; \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\; \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\; m_valid_i <= \^m_valid_i\; st_aa_artarget_hot(0) <= \^st_aa_artarget_hot\(0); aid_match_00_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_00, CO(2) => aid_match_00_carry_n_1, CO(1) => aid_match_00_carry_n_2, CO(0) => aid_match_00_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0), S(3) => aid_match_00_carry_i_1_n_0, S(2) => aid_match_00_carry_i_2_n_0, S(1) => aid_match_00_carry_i_3_n_0, S(0) => aid_match_00_carry_i_4_n_0 ); aid_match_00_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9), I1 => \s_axi_araddr[31]\(9), I2 => \s_axi_araddr[31]\(10), I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10), I4 => \s_axi_araddr[31]\(11), I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11), O => aid_match_00_carry_i_1_n_0 ); aid_match_00_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7), I1 => \s_axi_araddr[31]\(7), I2 => \s_axi_araddr[31]\(8), I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8), I4 => \s_axi_araddr[31]\(6), I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6), O => aid_match_00_carry_i_2_n_0 ); aid_match_00_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3), I1 => \s_axi_araddr[31]\(3), I2 => \s_axi_araddr[31]\(4), I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4), I4 => \s_axi_araddr[31]\(5), I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5), O => aid_match_00_carry_i_3_n_0 ); aid_match_00_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0), I1 => \s_axi_araddr[31]\(0), I2 => \s_axi_araddr[31]\(2), I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2), I4 => \s_axi_araddr[31]\(1), I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1), O => aid_match_00_carry_i_4_n_0 ); aid_match_10_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_10, CO(2) => aid_match_10_carry_n_1, CO(1) => aid_match_10_carry_n_2, CO(0) => aid_match_10_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0), S(3) => aid_match_10_carry_i_1_n_0, S(2) => aid_match_10_carry_i_2_n_0, S(1) => aid_match_10_carry_i_3_n_0, S(0) => aid_match_10_carry_i_4_n_0 ); aid_match_10_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \s_axi_araddr[31]\(10), I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9), I3 => \s_axi_araddr[31]\(9), I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11), I5 => \s_axi_araddr[31]\(11), O => aid_match_10_carry_i_1_n_0 ); aid_match_10_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \s_axi_araddr[31]\(7), I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8), I3 => \s_axi_araddr[31]\(8), I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6), I5 => \s_axi_araddr[31]\(6), O => aid_match_10_carry_i_2_n_0 ); aid_match_10_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \s_axi_araddr[31]\(3), I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5), I3 => \s_axi_araddr[31]\(5), I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4), I5 => \s_axi_araddr[31]\(4), O => aid_match_10_carry_i_3_n_0 ); aid_match_10_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \s_axi_araddr[31]\(0), I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2), I3 => \s_axi_araddr[31]\(2), I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1), I5 => \s_axi_araddr[31]\(1), O => aid_match_10_carry_i_4_n_0 ); aid_match_20_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_20, CO(2) => aid_match_20_carry_n_1, CO(1) => aid_match_20_carry_n_2, CO(0) => aid_match_20_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0), S(3) => aid_match_20_carry_i_1_n_0, S(2) => aid_match_20_carry_i_2_n_0, S(1) => aid_match_20_carry_i_3_n_0, S(0) => aid_match_20_carry_i_4_n_0 ); aid_match_20_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9), I1 => \s_axi_araddr[31]\(9), I2 => \s_axi_araddr[31]\(10), I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10), I4 => \s_axi_araddr[31]\(11), I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11), O => aid_match_20_carry_i_1_n_0 ); aid_match_20_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7), I1 => \s_axi_araddr[31]\(7), I2 => \s_axi_araddr[31]\(8), I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8), I4 => \s_axi_araddr[31]\(6), I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6), O => aid_match_20_carry_i_2_n_0 ); aid_match_20_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3), I1 => \s_axi_araddr[31]\(3), I2 => \s_axi_araddr[31]\(5), I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5), I4 => \s_axi_araddr[31]\(4), I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4), O => aid_match_20_carry_i_3_n_0 ); aid_match_20_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1), I1 => \s_axi_araddr[31]\(1), I2 => \s_axi_araddr[31]\(2), I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2), I4 => \s_axi_araddr[31]\(0), I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0), O => aid_match_20_carry_i_4_n_0 ); aid_match_30_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_30, CO(2) => aid_match_30_carry_n_1, CO(1) => aid_match_30_carry_n_2, CO(0) => aid_match_30_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0), S(3) => aid_match_30_carry_i_1_n_0, S(2) => aid_match_30_carry_i_2_n_0, S(1) => aid_match_30_carry_i_3_n_0, S(0) => aid_match_30_carry_i_4_n_0 ); aid_match_30_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10), I1 => \s_axi_araddr[31]\(10), I2 => \s_axi_araddr[31]\(11), I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11), I4 => \s_axi_araddr[31]\(9), I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9), O => aid_match_30_carry_i_1_n_0 ); aid_match_30_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6), I1 => \s_axi_araddr[31]\(6), I2 => \s_axi_araddr[31]\(8), I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8), I4 => \s_axi_araddr[31]\(7), I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7), O => aid_match_30_carry_i_2_n_0 ); aid_match_30_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3), I1 => \s_axi_araddr[31]\(3), I2 => \s_axi_araddr[31]\(5), I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5), I4 => \s_axi_araddr[31]\(4), I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4), O => aid_match_30_carry_i_3_n_0 ); aid_match_30_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0), I1 => \s_axi_araddr[31]\(0), I2 => \s_axi_araddr[31]\(2), I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2), I4 => \s_axi_araddr[31]\(1), I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1), O => aid_match_30_carry_i_4_n_0 ); aid_match_40_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_40, CO(2) => aid_match_40_carry_n_1, CO(1) => aid_match_40_carry_n_2, CO(0) => aid_match_40_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0), S(3) => aid_match_40_carry_i_1_n_0, S(2) => aid_match_40_carry_i_2_n_0, S(1) => aid_match_40_carry_i_3_n_0, S(0) => aid_match_40_carry_i_4_n_0 ); aid_match_40_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9), I1 => \s_axi_araddr[31]\(9), I2 => \s_axi_araddr[31]\(10), I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10), I4 => \s_axi_araddr[31]\(11), I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11), O => aid_match_40_carry_i_1_n_0 ); aid_match_40_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6), I1 => \s_axi_araddr[31]\(6), I2 => \s_axi_araddr[31]\(7), I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7), I4 => \s_axi_araddr[31]\(8), I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8), O => aid_match_40_carry_i_2_n_0 ); aid_match_40_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \s_axi_araddr[31]\(5), I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5), I2 => \s_axi_araddr[31]\(3), I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3), I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4), I5 => \s_axi_araddr[31]\(4), O => aid_match_40_carry_i_3_n_0 ); aid_match_40_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1), I1 => \s_axi_araddr[31]\(1), I2 => \s_axi_araddr[31]\(0), I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0), I4 => \s_axi_araddr[31]\(2), I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2), O => aid_match_40_carry_i_4_n_0 ); aid_match_50_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_50, CO(2) => aid_match_50_carry_n_1, CO(1) => aid_match_50_carry_n_2, CO(0) => aid_match_50_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0), S(3) => aid_match_50_carry_i_1_n_0, S(2) => aid_match_50_carry_i_2_n_0, S(1) => aid_match_50_carry_i_3_n_0, S(0) => aid_match_50_carry_i_4_n_0 ); aid_match_50_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9), I1 => \s_axi_araddr[31]\(9), I2 => \s_axi_araddr[31]\(10), I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10), I4 => \s_axi_araddr[31]\(11), I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11), O => aid_match_50_carry_i_1_n_0 ); aid_match_50_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6), I1 => \s_axi_araddr[31]\(6), I2 => \s_axi_araddr[31]\(7), I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7), I4 => \s_axi_araddr[31]\(8), I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8), O => aid_match_50_carry_i_2_n_0 ); aid_match_50_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3), I1 => \s_axi_araddr[31]\(3), I2 => \s_axi_araddr[31]\(4), I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4), I4 => \s_axi_araddr[31]\(5), I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5), O => aid_match_50_carry_i_3_n_0 ); aid_match_50_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1), I1 => \s_axi_araddr[31]\(1), I2 => \s_axi_araddr[31]\(0), I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0), I4 => \s_axi_araddr[31]\(2), I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2), O => aid_match_50_carry_i_4_n_0 ); aid_match_60_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_60, CO(2) => aid_match_60_carry_n_1, CO(1) => aid_match_60_carry_n_2, CO(0) => aid_match_60_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0), S(3) => aid_match_60_carry_i_1_n_0, S(2) => aid_match_60_carry_i_2_n_0, S(1) => aid_match_60_carry_i_3_n_0, S(0) => aid_match_60_carry_i_4_n_0 ); aid_match_60_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9), I1 => \s_axi_araddr[31]\(9), I2 => \s_axi_araddr[31]\(11), I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11), I4 => \s_axi_araddr[31]\(10), I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10), O => aid_match_60_carry_i_1_n_0 ); aid_match_60_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6), I1 => \s_axi_araddr[31]\(6), I2 => \s_axi_araddr[31]\(8), I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8), I4 => \s_axi_araddr[31]\(7), I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7), O => aid_match_60_carry_i_2_n_0 ); aid_match_60_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3), I1 => \s_axi_araddr[31]\(3), I2 => \s_axi_araddr[31]\(5), I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5), I4 => \s_axi_araddr[31]\(4), I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4), O => aid_match_60_carry_i_3_n_0 ); aid_match_60_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0), I1 => \s_axi_araddr[31]\(0), I2 => \s_axi_araddr[31]\(1), I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1), I4 => \s_axi_araddr[31]\(2), I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2), O => aid_match_60_carry_i_4_n_0 ); aid_match_70_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_70, CO(2) => aid_match_70_carry_n_1, CO(1) => aid_match_70_carry_n_2, CO(0) => aid_match_70_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0), S(3) => aid_match_70_carry_i_1_n_0, S(2) => aid_match_70_carry_i_2_n_0, S(1) => aid_match_70_carry_i_3_n_0, S(0) => aid_match_70_carry_i_4_n_0 ); aid_match_70_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10), I1 => \s_axi_araddr[31]\(10), I2 => \s_axi_araddr[31]\(9), I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9), I4 => \s_axi_araddr[31]\(11), I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11), O => aid_match_70_carry_i_1_n_0 ); aid_match_70_carry_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6), I1 => \s_axi_araddr[31]\(6), I2 => \s_axi_araddr[31]\(7), I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7), I4 => \s_axi_araddr[31]\(8), I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8), O => aid_match_70_carry_i_2_n_0 ); aid_match_70_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3), I1 => \s_axi_araddr[31]\(3), I2 => \s_axi_araddr[31]\(4), I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4), I4 => \s_axi_araddr[31]\(5), I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5), O => aid_match_70_carry_i_3_n_0 ); aid_match_70_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1), I1 => \s_axi_araddr[31]\(1), I2 => \s_axi_araddr[31]\(0), I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0), I4 => \s_axi_araddr[31]\(2), I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2), O => aid_match_70_carry_i_4_n_0 ); \gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.accept_cnt_reg__0\(0), O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ ); \gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_12\, D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\, Q => \gen_multi_thread.accept_cnt_reg__0\(0), R => SR(0) ); \gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_12\, D => \gen_multi_thread.arbiter_resp_inst_n_2\, Q => \gen_multi_thread.accept_cnt_reg__0\(1), R => SR(0) ); \gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_12\, D => \gen_multi_thread.arbiter_resp_inst_n_1\, Q => \gen_multi_thread.accept_cnt_reg__0\(2), R => SR(0) ); \gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_12\, D => \gen_multi_thread.arbiter_resp_inst_n_0\, Q => \gen_multi_thread.accept_cnt_reg__0\(3), R => SR(0) ); \gen_multi_thread.arbiter_resp_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_5 port map ( CO(0) => p_8_out, D(2) => \gen_multi_thread.arbiter_resp_inst_n_0\, D(1) => \gen_multi_thread.arbiter_resp_inst_n_1\, D(0) => \gen_multi_thread.arbiter_resp_inst_n_2\, E(0) => \gen_multi_thread.arbiter_resp_inst_n_4\, Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0), S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\, S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\, S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\, S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\, SR(0) => SR(0), aclk => aclk, \chosen_reg[1]_0\ => chosen(1), cmd_push_0 => cmd_push_0, cmd_push_3 => cmd_push_3, \gen_multi_thread.accept_cnt_reg[2]\ => \gen_multi_thread.accept_cnt_reg[2]_0\, \gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\, \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out, \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0), \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\, \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_24\, \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_25\, \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_26\, \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_27\, \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\, \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out, \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0), \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\, \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_9\, \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_28\, \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_29\, \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_30\, \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_31\, \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out, \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0), \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\, \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3) => \gen_multi_thread.arbiter_resp_inst_n_32\, \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2) => \gen_multi_thread.arbiter_resp_inst_n_33\, \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1) => \gen_multi_thread.arbiter_resp_inst_n_34\, \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_35\, \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0), \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_8\, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_36\, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_37\, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_38\, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_39\, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\, \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out, \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0), \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\, \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_7\, \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_40\, \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_41\, \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_42\, \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_43\, \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out, \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0), \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_6\, \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_44\, \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_45\, \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_46\, \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_47\, \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\, \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out, \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.arbiter_resp_inst_n_5\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_48\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_49\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_50\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_51\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\, \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out, \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0), \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]_1\, \gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\, \gen_no_arbiter.s_ready_i_reg[0]_1\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\, \gen_no_arbiter.s_ready_i_reg[0]_2\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\, \gen_no_arbiter.s_ready_i_reg[0]_3\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\, \gen_no_arbiter.s_ready_i_reg[0]_4\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\, \gen_no_arbiter.s_ready_i_reg[0]_5\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\, \m_payload_i_reg[0]\(0) => E(0), \m_payload_i_reg[0]_0\ => chosen(0), \m_payload_i_reg[34]\ => chosen(2), \m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]\(0), \m_payload_i_reg[46]\(25 downto 0) => \m_payload_i_reg[46]\(25 downto 0), \m_payload_i_reg[46]_0\(25 downto 0) => \m_payload_i_reg[46]_0\(25 downto 0), \m_payload_i_reg[46]_1\(12 downto 0) => \m_payload_i_reg[46]_1\(12 downto 0), p_32_out => p_32_out, p_54_out => p_54_out, p_74_out => p_74_out, s_axi_rdata(11 downto 0) => s_axi_rdata(11 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast(0) => s_axi_rlast(0), s_axi_rready(0) => s_axi_rready(0), s_axi_rresp(0) => s_axi_rresp(0), s_axi_rvalid(0) => s_axi_rvalid(0) ); \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(0), O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => cmd_push_0, I1 => active_cnt(0), I2 => active_cnt(1), O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"6AA9" ) port map ( I0 => active_cnt(2), I1 => active_cnt(0), I2 => active_cnt(1), I3 => cmd_push_0, O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAA9" ) port map ( I0 => active_cnt(3), I1 => active_cnt(2), I2 => cmd_push_0, I3 => active_cnt(1), I4 => active_cnt(0), O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_11\, D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\, Q => active_cnt(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_11\, D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\, Q => active_cnt(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_11\, D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\, Q => active_cnt(2), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_11\, D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\, Q => active_cnt(3), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(6), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(7), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(8), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_araddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000F0088888888" ) port map ( I0 => aid_match_00, I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\, I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\, O => cmd_push_0 ); \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAA8FFFFFFFF" ) port map ( I0 => aid_match_30, I1 => active_cnt(24), I2 => active_cnt(25), I3 => active_cnt(27), I4 => active_cnt(26), I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\, O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \^st_aa_artarget_hot\(0), Q => active_target(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\, Q => active_target(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(10), I1 => active_cnt(8), I2 => active_cnt(9), I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(11), I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\, I2 => active_cnt(9), I3 => active_cnt(8), I4 => active_cnt(10), O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF55FF55CF55FF55" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\, I1 => active_cnt(10), I2 => active_cnt(11), I3 => active_cnt(9), I4 => active_cnt(8), O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(8), O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\, I1 => active_cnt(8), I2 => active_cnt(9), O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_10\, D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\, Q => active_cnt(10), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_10\, D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\, Q => active_cnt(11), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_10\, D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\, Q => active_cnt(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_10\, D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\, Q => active_cnt(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(6), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(7), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(8), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_araddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"3B080808" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\, I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\, I3 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I4 => aid_match_10, O => cmd_push_1 ); \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\, I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(8), I1 => active_cnt(9), I2 => active_cnt(11), I3 => active_cnt(10), O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(0), I1 => active_cnt(1), I2 => active_cnt(3), I3 => active_cnt(2), O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \^st_aa_artarget_hot\(0), Q => active_target(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\, Q => active_target(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(16), O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\, I1 => active_cnt(16), I2 => active_cnt(17), O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(18), I1 => active_cnt(16), I2 => active_cnt(17), I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(19), I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\, I2 => active_cnt(17), I3 => active_cnt(16), I4 => active_cnt(18), O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(16), I1 => active_cnt(17), I2 => active_cnt(19), I3 => active_cnt(18), O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_9\, D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\, Q => active_cnt(16), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_9\, D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\, Q => active_cnt(17), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_9\, D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\, Q => active_cnt(18), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_9\, D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\, Q => active_cnt(19), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(6), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(7), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(8), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_araddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\, O => cmd_push_2 ); \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF77FF77F077FF77" ) port map ( I0 => aid_match_20, I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\, I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF0001" ) port map ( I0 => active_cnt(10), I1 => active_cnt(11), I2 => active_cnt(9), I3 => active_cnt(8), I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \^st_aa_artarget_hot\(0), Q => active_target(16), R => SR(0) ); \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\, Q => active_target(17), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(24), O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => cmd_push_3, I1 => active_cnt(24), I2 => active_cnt(25), O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"6AA9" ) port map ( I0 => active_cnt(26), I1 => active_cnt(24), I2 => active_cnt(25), I3 => cmd_push_3, O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAA9" ) port map ( I0 => active_cnt(27), I1 => active_cnt(26), I2 => cmd_push_3, I3 => active_cnt(25), I4 => active_cnt(24), O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(24), I1 => active_cnt(25), I2 => active_cnt(27), I3 => active_cnt(26), O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_4\, D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\, Q => active_cnt(24), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_4\, D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\, Q => active_cnt(25), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_4\, D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\, Q => active_cnt(26), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_4\, D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\, Q => active_cnt(27), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(6), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(7), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(8), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_araddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFF" ) port map ( I0 => active_cnt(2), I1 => active_cnt(3), I2 => active_cnt(1), I3 => active_cnt(0), I4 => aid_match_00, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"55555557" ) port map ( I0 => aid_match_60, I1 => active_cnt(49), I2 => active_cnt(48), I3 => active_cnt(50), I4 => active_cnt(51), O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFF" ) port map ( I0 => active_cnt(18), I1 => active_cnt(19), I2 => active_cnt(17), I3 => active_cnt(16), I4 => aid_match_20, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0A0A0A0A3A0A0A0A" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\, O => cmd_push_3 ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\, I1 => active_cnt(26), I2 => active_cnt(27), I3 => active_cnt(25), I4 => active_cnt(24), O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFF" ) port map ( I0 => active_cnt(26), I1 => active_cnt(27), I2 => active_cnt(25), I3 => active_cnt(24), I4 => aid_match_30, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFF" ) port map ( I0 => active_cnt(10), I1 => active_cnt(11), I2 => active_cnt(9), I3 => active_cnt(8), I4 => aid_match_10, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55555557" ) port map ( I0 => aid_match_70, I1 => active_cnt(57), I2 => active_cnt(56), I3 => active_cnt(58), I4 => active_cnt(59), O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\, I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF0001" ) port map ( I0 => active_cnt(18), I1 => active_cnt(19), I2 => active_cnt(17), I3 => active_cnt(16), I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\, I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55555557" ) port map ( I0 => aid_match_40, I1 => active_cnt(33), I2 => active_cnt(32), I3 => active_cnt(34), I4 => active_cnt(35), O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFF" ) port map ( I0 => active_cnt(42), I1 => active_cnt(43), I2 => active_cnt(41), I3 => active_cnt(40), I4 => aid_match_50, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \^st_aa_artarget_hot\(0), Q => active_target(24), R => SR(0) ); \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\, Q => active_target(25), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(32), O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\, I1 => active_cnt(32), I2 => active_cnt(33), O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(34), I1 => active_cnt(32), I2 => active_cnt(33), I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(35), I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\, I2 => active_cnt(33), I3 => active_cnt(32), I4 => active_cnt(34), O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => active_cnt(35), I1 => active_cnt(34), I2 => active_cnt(32), I3 => active_cnt(33), O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_8\, D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\, Q => active_cnt(32), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_8\, D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\, Q => active_cnt(33), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_8\, D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\, Q => active_cnt(34), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_8\, D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\, Q => active_cnt(35), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(6), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(7), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(8), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_araddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\, O => cmd_push_4 ); \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"5545FFFFFFEFFFFF" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\, I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\, I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\, I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\, I4 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I5 => aid_match_40, O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF0001" ) port map ( I0 => active_cnt(26), I1 => active_cnt(27), I2 => active_cnt(25), I3 => active_cnt(24), I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\, I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \^st_aa_artarget_hot\(0), Q => active_target(32), R => SR(0) ); \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\, Q => active_target(33), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(40), O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\, I1 => active_cnt(40), I2 => active_cnt(41), O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(42), I1 => active_cnt(40), I2 => active_cnt(41), I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(43), I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\, I2 => active_cnt(41), I3 => active_cnt(40), I4 => active_cnt(42), O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(40), I1 => active_cnt(41), I2 => active_cnt(43), I3 => active_cnt(42), O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_7\, D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\, Q => active_cnt(40), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_7\, D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\, Q => active_cnt(41), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_7\, D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\, Q => active_cnt(42), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_7\, D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\, Q => active_cnt(43), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(6), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(7), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(8), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_araddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\, O => cmd_push_5 ); \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF77FF77F077FF77" ) port map ( I0 => aid_match_50, I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\, I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\, I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAABFFFFFFFF" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\, I1 => active_cnt(24), I2 => active_cnt(25), I3 => active_cnt(27), I4 => active_cnt(26), I5 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\, I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \^st_aa_artarget_hot\(0), Q => active_target(40), R => SR(0) ); \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\, Q => active_target(41), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(48), O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\, I1 => active_cnt(48), I2 => active_cnt(49), O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(50), I1 => active_cnt(48), I2 => active_cnt(49), I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(51), I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\, I2 => active_cnt(49), I3 => active_cnt(48), I4 => active_cnt(50), O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => active_cnt(51), I1 => active_cnt(50), I2 => active_cnt(48), I3 => active_cnt(49), O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_6\, D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\, Q => active_cnt(48), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_6\, D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\, Q => active_cnt(49), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_6\, D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\, Q => active_cnt(50), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_6\, D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\, Q => active_cnt(51), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(6), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(7), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(8), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_araddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\, O => cmd_push_6 ); \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"5555555545555555" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\, I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAA800000000" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I1 => active_cnt(51), I2 => active_cnt(50), I3 => active_cnt(48), I4 => active_cnt(49), I5 => aid_match_60, O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\, I1 => active_cnt(51), I2 => active_cnt(50), I3 => active_cnt(48), I4 => active_cnt(49), I5 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \^st_aa_artarget_hot\(0), Q => active_target(48), R => SR(0) ); \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\, Q => active_target(49), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(56), O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\, I1 => active_cnt(56), I2 => active_cnt(57), O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(58), I1 => active_cnt(56), I2 => active_cnt(57), I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(59), I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\, I2 => active_cnt(57), I3 => active_cnt(56), I4 => active_cnt(58), O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => active_cnt(59), I1 => active_cnt(58), I2 => active_cnt(56), I3 => active_cnt(57), O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_5\, D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\, Q => active_cnt(56), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_5\, D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\, Q => active_cnt(57), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_5\, D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\, Q => active_cnt(58), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_5\, D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\, Q => active_cnt(59), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(6), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(7), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(8), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_araddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000010" ) port map ( I0 => \s_axi_araddr[31]\(17), I1 => \s_axi_araddr[31]\(20), I2 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\, I3 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\, I4 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\, O => \^st_aa_artarget_hot\(0) ); \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100000000" ) port map ( I0 => \s_axi_araddr[31]\(13), I1 => \s_axi_araddr[31]\(22), I2 => \s_axi_araddr[31]\(15), I3 => \s_axi_araddr[31]\(12), I4 => \s_axi_araddr[31]\(14), I5 => \s_axi_araddr[31]\(26), O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \s_axi_araddr[31]\(25), I1 => \s_axi_araddr[31]\(27), I2 => \s_axi_araddr[31]\(23), I3 => \s_axi_araddr[31]\(24), O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ ); \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \s_axi_araddr[31]\(18), I1 => \s_axi_araddr[31]\(19), I2 => \s_axi_araddr[31]\(16), I3 => \s_axi_araddr[31]\(21), O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\, O => cmd_push_7 ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \s_axi_araddr[25]_0\, O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF5555CFFF5555" ) port map ( I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\, I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\, I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \^st_aa_artarget_hot\(0), Q => active_target(56), R => SR(0) ); \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\, Q => active_target(57), R => SR(0) ); \gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F40" ) port map ( I0 => \s_axi_araddr[25]_0\, I1 => \^m_valid_i\, I2 => aresetn_d, I3 => \gen_no_arbiter.m_target_hot_i_reg[2]_0\(0), O => \gen_no_arbiter.m_target_hot_i_reg[2]\ ); \gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5 generic map( INIT => X"DDDDFFFD" ) port map ( I0 => aid_match_30, I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\, I2 => \s_axi_araddr[25]\(0), I3 => active_target(25), I4 => active_target(24), O => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"88880008" ) port map ( I0 => aid_match_60, I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\, I2 => \s_axi_araddr[25]\(0), I3 => active_target(49), I4 => active_target(48), O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5 generic map( INIT => X"22220002" ) port map ( I0 => aid_match_50, I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\, I2 => \s_axi_araddr[25]\(0), I3 => active_target(41), I4 => active_target(40), O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"40FF404040404040" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\, I1 => aid_match_10, I2 => active_target(8), I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\, I4 => aid_match_00, I5 => active_target(0), O => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0404040404FF0404" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\, I1 => aid_match_50, I2 => active_target(40), I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\, I4 => aid_match_10, I5 => active_target(8), O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT6 generic map( INIT => X"1010101010FF1010" ) port map ( I0 => active_target(16), I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\, I2 => aid_match_20, I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\, I4 => aid_match_30, I5 => active_target(24), O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAAAAAA8" ) port map ( I0 => aid_match_00, I1 => active_cnt(0), I2 => active_cnt(1), I3 => active_cnt(3), I4 => active_cnt(2), I5 => active_target(0), O => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT6 generic map( INIT => X"08080808FF080808" ) port map ( I0 => aid_match_60, I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\, I2 => active_target(48), I3 => aid_match_40, I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\, I5 => active_target(32), O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000F1000000" ) port map ( I0 => active_target(33), I1 => \s_axi_araddr[25]\(0), I2 => active_target(32), I3 => aid_match_40, I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\, I5 => \^st_aa_artarget_hot\(0), O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT6 generic map( INIT => X"80FF808080808080" ) port map ( I0 => aid_match_60, I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\, I2 => active_target(49), I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\, I4 => aid_match_20, I5 => active_target(17), O => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^m_valid_i\, I1 => aresetn_d, O => \gen_no_arbiter.s_ready_i_reg[0]\ ); \gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7F007F7F7F7F7F7F" ) port map ( I0 => active_target(33), I1 => aid_match_40, I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\, I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\, I4 => aid_match_50, I5 => active_target(41), O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT6 generic map( INIT => X"80FF808080808080" ) port map ( I0 => aid_match_70, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\, I2 => active_target(57), I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\, I4 => aid_match_30, I5 => active_target(25), O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT6 generic map( INIT => X"40FF404040404040" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\, I1 => aid_match_10, I2 => active_target(9), I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\, I4 => aid_match_00, I5 => active_target(1), O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => \gen_multi_thread.accept_cnt_reg__0\(3), I1 => \gen_multi_thread.accept_cnt_reg__0\(2), I2 => \gen_multi_thread.accept_cnt_reg__0\(1), I3 => \gen_multi_thread.accept_cnt_reg__0\(0), O => \gen_no_arbiter.s_ready_i_reg[0]_0\ ); \gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000000002F2" ) port map ( I0 => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\, I1 => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\, I2 => \^st_aa_artarget_hot\(0), I3 => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\, I4 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\, I5 => \gen_no_arbiter.m_valid_i_reg\, O => \^m_valid_i\ ); \gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000E00" ) port map ( I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\, I1 => \s_axi_araddr[25]\(0), I2 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\, I3 => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\, I4 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\, I5 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF0000111F" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\, I1 => active_target(9), I2 => active_target(1), I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\, I4 => \s_axi_araddr[25]\(0), I5 => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFEEEF" ) port map ( I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\, I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\, I3 => active_target(56), I4 => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\, I5 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFEFAAAAAAAA" ) port map ( I0 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\, I1 => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\, I2 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\, I3 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\, I4 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\, I5 => \s_axi_araddr[25]_0\, O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"F7F7F700F7F7F7F7" ) port map ( I0 => aid_match_70, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\, I2 => active_target(57), I3 => active_target(17), I4 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\, I5 => aid_match_20, O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"80FF808080808080" ) port map ( I0 => aid_match_70, I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\, I2 => active_target(56), I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\, I4 => aid_match_20, I5 => active_target(16), O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ ); \p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_0_out, CO(2) => \p_0_out_inferred__9/i__carry_n_1\, CO(1) => \p_0_out_inferred__9/i__carry_n_2\, CO(0) => \p_0_out_inferred__9/i__carry_n_3\, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0), S(3) => \gen_multi_thread.arbiter_resp_inst_n_48\, S(2) => \gen_multi_thread.arbiter_resp_inst_n_49\, S(1) => \gen_multi_thread.arbiter_resp_inst_n_50\, S(0) => \gen_multi_thread.arbiter_resp_inst_n_51\ ); p_10_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_10_out, CO(2) => p_10_out_carry_n_1, CO(1) => p_10_out_carry_n_2, CO(0) => p_10_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0), S(3) => \gen_multi_thread.arbiter_resp_inst_n_28\, S(2) => \gen_multi_thread.arbiter_resp_inst_n_29\, S(1) => \gen_multi_thread.arbiter_resp_inst_n_30\, S(0) => \gen_multi_thread.arbiter_resp_inst_n_31\ ); p_12_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_12_out, CO(2) => p_12_out_carry_n_1, CO(1) => p_12_out_carry_n_2, CO(0) => p_12_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0), S(3) => \gen_multi_thread.arbiter_resp_inst_n_24\, S(2) => \gen_multi_thread.arbiter_resp_inst_n_25\, S(1) => \gen_multi_thread.arbiter_resp_inst_n_26\, S(0) => \gen_multi_thread.arbiter_resp_inst_n_27\ ); p_14_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_14_out, CO(2) => p_14_out_carry_n_1, CO(1) => p_14_out_carry_n_2, CO(0) => p_14_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0), S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\, S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\, S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\, S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\ ); p_2_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_2_out, CO(2) => p_2_out_carry_n_1, CO(1) => p_2_out_carry_n_2, CO(0) => p_2_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0), S(3) => \gen_multi_thread.arbiter_resp_inst_n_44\, S(2) => \gen_multi_thread.arbiter_resp_inst_n_45\, S(1) => \gen_multi_thread.arbiter_resp_inst_n_46\, S(0) => \gen_multi_thread.arbiter_resp_inst_n_47\ ); p_4_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_4_out, CO(2) => p_4_out_carry_n_1, CO(1) => p_4_out_carry_n_2, CO(0) => p_4_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0), S(3) => \gen_multi_thread.arbiter_resp_inst_n_40\, S(2) => \gen_multi_thread.arbiter_resp_inst_n_41\, S(1) => \gen_multi_thread.arbiter_resp_inst_n_42\, S(0) => \gen_multi_thread.arbiter_resp_inst_n_43\ ); p_6_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_6_out, CO(2) => p_6_out_carry_n_1, CO(1) => p_6_out_carry_n_2, CO(0) => p_6_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0), S(3) => \gen_multi_thread.arbiter_resp_inst_n_36\, S(2) => \gen_multi_thread.arbiter_resp_inst_n_37\, S(1) => \gen_multi_thread.arbiter_resp_inst_n_38\, S(0) => \gen_multi_thread.arbiter_resp_inst_n_39\ ); p_8_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_8_out, CO(2) => p_8_out_carry_n_1, CO(1) => p_8_out_carry_n_2, CO(0) => p_8_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0), S(3) => \gen_multi_thread.arbiter_resp_inst_n_32\, S(2) => \gen_multi_thread.arbiter_resp_inst_n_33\, S(1) => \gen_multi_thread.arbiter_resp_inst_n_34\, S(0) => \gen_multi_thread.arbiter_resp_inst_n_35\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is port ( \gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC; m_valid_i : out STD_LOGIC; \gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC; chosen : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC; st_aa_awtarget_enc : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); SR : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC; \gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); S : in STD_LOGIC_VECTOR ( 0 to 0 ); aresetn_d : in STD_LOGIC; st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_ready_d_reg[1]\ : in STD_LOGIC; p_80_out : in STD_LOGIC; s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC; \gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : in STD_LOGIC; \s_axi_awaddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC; \m_payload_i_reg[2]\ : in STD_LOGIC; \m_payload_i_reg[4]\ : in STD_LOGIC; \m_payload_i_reg[6]\ : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; \m_payload_i_reg[7]\ : in STD_LOGIC; \m_payload_i_reg[12]\ : in STD_LOGIC; \m_payload_i_reg[11]\ : in STD_LOGIC; \m_payload_i_reg[13]\ : in STD_LOGIC; aa_sa_awvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC; p_38_out : in STD_LOGIC; p_60_out : in STD_LOGIC; w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 ); \m_ready_d_reg[1]_0\ : in STD_LOGIC; aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 ); signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 ); signal aid_match_00 : STD_LOGIC; signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC; signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC; signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC; signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC; signal aid_match_00_carry_n_1 : STD_LOGIC; signal aid_match_00_carry_n_2 : STD_LOGIC; signal aid_match_00_carry_n_3 : STD_LOGIC; signal aid_match_10 : STD_LOGIC; signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC; signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC; signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC; signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC; signal aid_match_10_carry_n_1 : STD_LOGIC; signal aid_match_10_carry_n_2 : STD_LOGIC; signal aid_match_10_carry_n_3 : STD_LOGIC; signal aid_match_20 : STD_LOGIC; signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC; signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC; signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC; signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC; signal aid_match_20_carry_n_1 : STD_LOGIC; signal aid_match_20_carry_n_2 : STD_LOGIC; signal aid_match_20_carry_n_3 : STD_LOGIC; signal aid_match_30 : STD_LOGIC; signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC; signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC; signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC; signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC; signal aid_match_30_carry_n_1 : STD_LOGIC; signal aid_match_30_carry_n_2 : STD_LOGIC; signal aid_match_30_carry_n_3 : STD_LOGIC; signal aid_match_40 : STD_LOGIC; signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC; signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC; signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC; signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC; signal aid_match_40_carry_n_1 : STD_LOGIC; signal aid_match_40_carry_n_2 : STD_LOGIC; signal aid_match_40_carry_n_3 : STD_LOGIC; signal aid_match_50 : STD_LOGIC; signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC; signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC; signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC; signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC; signal aid_match_50_carry_n_1 : STD_LOGIC; signal aid_match_50_carry_n_2 : STD_LOGIC; signal aid_match_50_carry_n_3 : STD_LOGIC; signal aid_match_60 : STD_LOGIC; signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC; signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC; signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC; signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC; signal aid_match_60_carry_n_1 : STD_LOGIC; signal aid_match_60_carry_n_2 : STD_LOGIC; signal aid_match_60_carry_n_3 : STD_LOGIC; signal aid_match_70 : STD_LOGIC; signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC; signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC; signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC; signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC; signal aid_match_70_carry_n_1 : STD_LOGIC; signal aid_match_70_carry_n_2 : STD_LOGIC; signal aid_match_70_carry_n_3 : STD_LOGIC; signal cmd_push_0 : STD_LOGIC; signal cmd_push_1 : STD_LOGIC; signal cmd_push_2 : STD_LOGIC; signal cmd_push_3 : STD_LOGIC; signal cmd_push_4 : STD_LOGIC; signal cmd_push_5 : STD_LOGIC; signal cmd_push_6 : STD_LOGIC; signal cmd_push_7 : STD_LOGIC; signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_13\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_14\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_15\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_16\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_17\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_3\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\ : STD_LOGIC; signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : STD_LOGIC; signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_10_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_16_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_19_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC; signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC; signal \i__carry_i_1_n_0\ : STD_LOGIC; signal \i__carry_i_3_n_0\ : STD_LOGIC; signal \i__carry_i_4_n_0\ : STD_LOGIC; signal p_0_out : STD_LOGIC; signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC; signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC; signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC; signal p_10_out : STD_LOGIC; signal p_10_out_carry_i_1_n_0 : STD_LOGIC; signal p_10_out_carry_i_3_n_0 : STD_LOGIC; signal p_10_out_carry_i_4_n_0 : STD_LOGIC; signal p_10_out_carry_n_1 : STD_LOGIC; signal p_10_out_carry_n_2 : STD_LOGIC; signal p_10_out_carry_n_3 : STD_LOGIC; signal p_12_out : STD_LOGIC; signal p_12_out_carry_i_1_n_0 : STD_LOGIC; signal p_12_out_carry_i_3_n_0 : STD_LOGIC; signal p_12_out_carry_i_4_n_0 : STD_LOGIC; signal p_12_out_carry_n_1 : STD_LOGIC; signal p_12_out_carry_n_2 : STD_LOGIC; signal p_12_out_carry_n_3 : STD_LOGIC; signal p_14_out : STD_LOGIC; signal p_14_out_carry_i_1_n_0 : STD_LOGIC; signal p_14_out_carry_i_3_n_0 : STD_LOGIC; signal p_14_out_carry_i_4_n_0 : STD_LOGIC; signal p_14_out_carry_n_1 : STD_LOGIC; signal p_14_out_carry_n_2 : STD_LOGIC; signal p_14_out_carry_n_3 : STD_LOGIC; signal p_2_out : STD_LOGIC; signal p_2_out_carry_i_1_n_0 : STD_LOGIC; signal p_2_out_carry_i_3_n_0 : STD_LOGIC; signal p_2_out_carry_i_4_n_0 : STD_LOGIC; signal p_2_out_carry_n_1 : STD_LOGIC; signal p_2_out_carry_n_2 : STD_LOGIC; signal p_2_out_carry_n_3 : STD_LOGIC; signal p_4_out : STD_LOGIC; signal p_4_out_carry_i_1_n_0 : STD_LOGIC; signal p_4_out_carry_i_3_n_0 : STD_LOGIC; signal p_4_out_carry_i_4_n_0 : STD_LOGIC; signal p_4_out_carry_n_1 : STD_LOGIC; signal p_4_out_carry_n_2 : STD_LOGIC; signal p_4_out_carry_n_3 : STD_LOGIC; signal p_6_out : STD_LOGIC; signal p_6_out_carry_i_1_n_0 : STD_LOGIC; signal p_6_out_carry_i_3_n_0 : STD_LOGIC; signal p_6_out_carry_i_4_n_0 : STD_LOGIC; signal p_6_out_carry_n_1 : STD_LOGIC; signal p_6_out_carry_n_2 : STD_LOGIC; signal p_6_out_carry_n_3 : STD_LOGIC; signal p_8_out : STD_LOGIC; signal p_8_out_carry_i_1_n_0 : STD_LOGIC; signal p_8_out_carry_i_3_n_0 : STD_LOGIC; signal p_8_out_carry_i_4_n_0 : STD_LOGIC; signal p_8_out_carry_n_1 : STD_LOGIC; signal p_8_out_carry_n_2 : STD_LOGIC; signal p_8_out_carry_n_3 : STD_LOGIC; signal \^st_aa_awtarget_enc\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair136"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair138"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair138"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair122"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair122"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair126"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair126"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair129"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\ : label is "soft_lutpair132"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair135"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair135"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\ : label is "soft_lutpair128"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\ : label is "soft_lutpair129"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair130"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\ : label is "soft_lutpair132"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\ : label is "soft_lutpair128"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair127"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\ : label is "soft_lutpair127"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\ : label is "soft_lutpair130"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair133"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair133"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair134"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair134"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair137"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair137"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair131"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair131"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_12\ : label is "soft_lutpair139"; attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair139"; attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28\ : label is "soft_lutpair136"; attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_8__0\ : label is "soft_lutpair140"; attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_9__0\ : label is "soft_lutpair140"; begin D(0) <= \^d\(0); Q(2 downto 0) <= \^q\(2 downto 0); SR(0) <= \^sr\(0); \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0); \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0); \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\; \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\; st_aa_awtarget_enc(0) <= \^st_aa_awtarget_enc\(0); aid_match_00_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_00, CO(2) => aid_match_00_carry_n_1, CO(1) => aid_match_00_carry_n_2, CO(0) => aid_match_00_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0), S(3) => \aid_match_00_carry_i_1__0_n_0\, S(2) => \aid_match_00_carry_i_2__0_n_0\, S(1) => \aid_match_00_carry_i_3__0_n_0\, S(0) => \aid_match_00_carry_i_4__0_n_0\ ); \aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9), I1 => \s_axi_awaddr[31]\(9), I2 => \s_axi_awaddr[31]\(11), I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11), I4 => \s_axi_awaddr[31]\(10), I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10), O => \aid_match_00_carry_i_1__0_n_0\ ); \aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^q\(0), I1 => \s_axi_awaddr[31]\(6), I2 => \s_axi_awaddr[31]\(7), I3 => \^q\(1), I4 => \s_axi_awaddr[31]\(8), I5 => \^q\(2), O => \aid_match_00_carry_i_2__0_n_0\ ); \aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4), I1 => \s_axi_awaddr[31]\(4), I2 => \s_axi_awaddr[31]\(3), I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3), I4 => \s_axi_awaddr[31]\(5), I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5), O => \aid_match_00_carry_i_3__0_n_0\ ); \aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0), I1 => \s_axi_awaddr[31]\(0), I2 => \s_axi_awaddr[31]\(2), I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2), I4 => \s_axi_awaddr[31]\(1), I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1), O => \aid_match_00_carry_i_4__0_n_0\ ); aid_match_10_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_10, CO(2) => aid_match_10_carry_n_1, CO(1) => aid_match_10_carry_n_2, CO(0) => aid_match_10_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0), S(3) => \aid_match_10_carry_i_1__0_n_0\, S(2) => \aid_match_10_carry_i_2__0_n_0\, S(1) => \aid_match_10_carry_i_3__0_n_0\, S(0) => \aid_match_10_carry_i_4__0_n_0\ ); \aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \s_axi_awaddr[31]\(9), I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10), I3 => \s_axi_awaddr[31]\(10), I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11), I5 => \s_axi_awaddr[31]\(11), O => \aid_match_10_carry_i_1__0_n_0\ ); \aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \s_axi_awaddr[31]\(6), I1 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0), I2 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2), I3 => \s_axi_awaddr[31]\(8), I4 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1), I5 => \s_axi_awaddr[31]\(7), O => \aid_match_10_carry_i_2__0_n_0\ ); \aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \s_axi_awaddr[31]\(3), I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4), I3 => \s_axi_awaddr[31]\(4), I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5), I5 => \s_axi_awaddr[31]\(5), O => \aid_match_10_carry_i_3__0_n_0\ ); \aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \s_axi_awaddr[31]\(0), I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2), I3 => \s_axi_awaddr[31]\(2), I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1), I5 => \s_axi_awaddr[31]\(1), O => \aid_match_10_carry_i_4__0_n_0\ ); aid_match_20_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_20, CO(2) => aid_match_20_carry_n_1, CO(1) => aid_match_20_carry_n_2, CO(0) => aid_match_20_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0), S(3) => \aid_match_20_carry_i_1__0_n_0\, S(2) => \aid_match_20_carry_i_2__0_n_0\, S(1) => \aid_match_20_carry_i_3__0_n_0\, S(0) => \aid_match_20_carry_i_4__0_n_0\ ); \aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9), I1 => \s_axi_awaddr[31]\(9), I2 => \s_axi_awaddr[31]\(10), I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10), I4 => \s_axi_awaddr[31]\(11), I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11), O => \aid_match_20_carry_i_1__0_n_0\ ); \aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1), I1 => \s_axi_awaddr[31]\(7), I2 => \s_axi_awaddr[31]\(8), I3 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2), I4 => \s_axi_awaddr[31]\(6), I5 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0), O => \aid_match_20_carry_i_2__0_n_0\ ); \aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4), I1 => \s_axi_awaddr[31]\(4), I2 => \s_axi_awaddr[31]\(5), I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5), I4 => \s_axi_awaddr[31]\(3), I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3), O => \aid_match_20_carry_i_3__0_n_0\ ); \aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1), I1 => \s_axi_awaddr[31]\(1), I2 => \s_axi_awaddr[31]\(0), I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0), I4 => \s_axi_awaddr[31]\(2), I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2), O => \aid_match_20_carry_i_4__0_n_0\ ); aid_match_30_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_30, CO(2) => aid_match_30_carry_n_1, CO(1) => aid_match_30_carry_n_2, CO(0) => aid_match_30_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0), S(3) => \aid_match_30_carry_i_1__0_n_0\, S(2) => \aid_match_30_carry_i_2__0_n_0\, S(1) => \aid_match_30_carry_i_3__0_n_0\, S(0) => \aid_match_30_carry_i_4__0_n_0\ ); \aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10), I1 => \s_axi_awaddr[31]\(10), I2 => \s_axi_awaddr[31]\(11), I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11), I4 => \s_axi_awaddr[31]\(9), I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9), O => \aid_match_30_carry_i_1__0_n_0\ ); \aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0), I1 => \s_axi_awaddr[31]\(6), I2 => \s_axi_awaddr[31]\(7), I3 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1), I4 => \s_axi_awaddr[31]\(8), I5 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2), O => \aid_match_30_carry_i_2__0_n_0\ ); \aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3), I1 => \s_axi_awaddr[31]\(3), I2 => \s_axi_awaddr[31]\(5), I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5), I4 => \s_axi_awaddr[31]\(4), I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4), O => \aid_match_30_carry_i_3__0_n_0\ ); \aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1), I1 => \s_axi_awaddr[31]\(1), I2 => \s_axi_awaddr[31]\(2), I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2), I4 => \s_axi_awaddr[31]\(0), I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0), O => \aid_match_30_carry_i_4__0_n_0\ ); aid_match_40_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_40, CO(2) => aid_match_40_carry_n_1, CO(1) => aid_match_40_carry_n_2, CO(0) => aid_match_40_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0), S(3) => \aid_match_40_carry_i_1__0_n_0\, S(2) => \aid_match_40_carry_i_2__0_n_0\, S(1) => \aid_match_40_carry_i_3__0_n_0\, S(0) => \aid_match_40_carry_i_4__0_n_0\ ); \aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9), I1 => \s_axi_awaddr[31]\(9), I2 => \s_axi_awaddr[31]\(10), I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10), I4 => \s_axi_awaddr[31]\(11), I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11), O => \aid_match_40_carry_i_1__0_n_0\ ); \aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1), I1 => \s_axi_awaddr[31]\(7), I2 => \s_axi_awaddr[31]\(6), I3 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0), I4 => \s_axi_awaddr[31]\(8), I5 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2), O => \aid_match_40_carry_i_2__0_n_0\ ); \aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4), I1 => \s_axi_awaddr[31]\(4), I2 => \s_axi_awaddr[31]\(3), I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3), I4 => \s_axi_awaddr[31]\(5), I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5), O => \aid_match_40_carry_i_3__0_n_0\ ); \aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1), I1 => \s_axi_awaddr[31]\(1), I2 => \s_axi_awaddr[31]\(2), I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2), I4 => \s_axi_awaddr[31]\(0), I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0), O => \aid_match_40_carry_i_4__0_n_0\ ); aid_match_50_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_50, CO(2) => aid_match_50_carry_n_1, CO(1) => aid_match_50_carry_n_2, CO(0) => aid_match_50_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0), S(3) => \aid_match_50_carry_i_1__0_n_0\, S(2) => \aid_match_50_carry_i_2__0_n_0\, S(1) => \aid_match_50_carry_i_3__0_n_0\, S(0) => \aid_match_50_carry_i_4__0_n_0\ ); \aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10), I1 => \s_axi_awaddr[31]\(10), I2 => \s_axi_awaddr[31]\(9), I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9), I4 => \s_axi_awaddr[31]\(11), I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11), O => \aid_match_50_carry_i_1__0_n_0\ ); \aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1), I1 => \s_axi_awaddr[31]\(7), I2 => \s_axi_awaddr[31]\(8), I3 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2), I4 => \s_axi_awaddr[31]\(6), I5 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0), O => \aid_match_50_carry_i_2__0_n_0\ ); \aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4), I1 => \s_axi_awaddr[31]\(4), I2 => \s_axi_awaddr[31]\(5), I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5), I4 => \s_axi_awaddr[31]\(3), I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3), O => \aid_match_50_carry_i_3__0_n_0\ ); \aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0), I1 => \s_axi_awaddr[31]\(0), I2 => \s_axi_awaddr[31]\(1), I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1), I4 => \s_axi_awaddr[31]\(2), I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2), O => \aid_match_50_carry_i_4__0_n_0\ ); aid_match_60_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_60, CO(2) => aid_match_60_carry_n_1, CO(1) => aid_match_60_carry_n_2, CO(0) => aid_match_60_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0), S(3) => \aid_match_60_carry_i_1__0_n_0\, S(2) => \aid_match_60_carry_i_2__0_n_0\, S(1) => \aid_match_60_carry_i_3__0_n_0\, S(0) => \aid_match_60_carry_i_4__0_n_0\ ); \aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9), I1 => \s_axi_awaddr[31]\(9), I2 => \s_axi_awaddr[31]\(11), I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11), I4 => \s_axi_awaddr[31]\(10), I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10), O => \aid_match_60_carry_i_1__0_n_0\ ); \aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0), I1 => \s_axi_awaddr[31]\(6), I2 => \s_axi_awaddr[31]\(8), I3 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2), I4 => \s_axi_awaddr[31]\(7), I5 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1), O => \aid_match_60_carry_i_2__0_n_0\ ); \aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3), I1 => \s_axi_awaddr[31]\(3), I2 => \s_axi_awaddr[31]\(5), I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5), I4 => \s_axi_awaddr[31]\(4), I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4), O => \aid_match_60_carry_i_3__0_n_0\ ); \aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0), I1 => \s_axi_awaddr[31]\(0), I2 => \s_axi_awaddr[31]\(1), I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1), I4 => \s_axi_awaddr[31]\(2), I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2), O => \aid_match_60_carry_i_4__0_n_0\ ); aid_match_70_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => aid_match_70, CO(2) => aid_match_70_carry_n_1, CO(1) => aid_match_70_carry_n_2, CO(0) => aid_match_70_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0), S(3) => \aid_match_70_carry_i_1__0_n_0\, S(2) => \aid_match_70_carry_i_2__0_n_0\, S(1) => \aid_match_70_carry_i_3__0_n_0\, S(0) => \aid_match_70_carry_i_4__0_n_0\ ); \aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9), I1 => \s_axi_awaddr[31]\(9), I2 => \s_axi_awaddr[31]\(10), I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10), I4 => \s_axi_awaddr[31]\(11), I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11), O => \aid_match_70_carry_i_1__0_n_0\ ); \aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1), I1 => \s_axi_awaddr[31]\(7), I2 => \s_axi_awaddr[31]\(6), I3 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0), I4 => \s_axi_awaddr[31]\(8), I5 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2), O => \aid_match_70_carry_i_2__0_n_0\ ); \aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4), I1 => \s_axi_awaddr[31]\(4), I2 => \s_axi_awaddr[31]\(5), I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5), I4 => \s_axi_awaddr[31]\(3), I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3), O => \aid_match_70_carry_i_3__0_n_0\ ); \aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"9009000000009009" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1), I1 => \s_axi_awaddr[31]\(1), I2 => \s_axi_awaddr[31]\(2), I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2), I4 => \s_axi_awaddr[31]\(0), I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0), O => \aid_match_70_carry_i_4__0_n_0\ ); \gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.accept_cnt_reg\(0), O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\ ); \gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_17\, D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\, Q => \gen_multi_thread.accept_cnt_reg\(0), R => \^sr\(0) ); \gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_17\, D => \gen_multi_thread.arbiter_resp_inst_n_4\, Q => \gen_multi_thread.accept_cnt_reg\(1), R => \^sr\(0) ); \gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_17\, D => \gen_multi_thread.arbiter_resp_inst_n_3\, Q => \gen_multi_thread.accept_cnt_reg\(2), R => \^sr\(0) ); \gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_17\, D => \gen_multi_thread.arbiter_resp_inst_n_2\, Q => \gen_multi_thread.accept_cnt_reg\(3), R => \^sr\(0) ); \gen_multi_thread.arbiter_resp_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp port map ( CO(0) => p_0_out, D(2) => \gen_multi_thread.arbiter_resp_inst_n_2\, D(1) => \gen_multi_thread.arbiter_resp_inst_n_3\, D(0) => \gen_multi_thread.arbiter_resp_inst_n_4\, E(0) => \gen_multi_thread.arbiter_resp_inst_n_9\, Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0), SR(0) => \^sr\(0), aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(0), aa_sa_awvalid => aa_sa_awvalid, aclk => aclk, aresetn_d => aresetn_d, \chosen_reg[0]_0\ => chosen(0), \chosen_reg[1]_0\ => chosen(1), cmd_push_0 => cmd_push_0, cmd_push_3 => cmd_push_3, \gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_master_slots[0].w_issuing_cnt_reg[1]\, \gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].w_issuing_cnt_reg[10]\, \gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_master_slots[1].w_issuing_cnt_reg[8]\, \gen_master_slots[2].w_issuing_cnt_reg[16]\ => chosen(2), \gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].w_issuing_cnt_reg[16]\, \gen_master_slots[2].w_issuing_cnt_reg[16]_1\ => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\, \gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\, \gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_17\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_16\, \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out, \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_15\, \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\, \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out, \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\, \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_14\, \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out, \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\, \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\, \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_13\, \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\, \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out, \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\, \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\, \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out, \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\, \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\, \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out, \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\, \gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\, \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\, \gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\, \m_ready_d_reg[1]\ => \m_ready_d_reg[1]\, \m_ready_d_reg[1]_0\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\, \m_ready_d_reg[1]_1\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\, \m_ready_d_reg[1]_2\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\, \m_ready_d_reg[1]_3\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\, \m_ready_d_reg[1]_4\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\, \m_ready_d_reg[1]_5\ => \m_ready_d_reg[1]_0\, m_valid_i => m_valid_i, m_valid_i_reg => m_valid_i_reg, p_38_out => p_38_out, p_60_out => p_60_out, p_80_out => p_80_out, \s_axi_awaddr[26]\(0) => \^st_aa_awtarget_enc\(0), s_axi_awvalid(0) => s_axi_awvalid(0), s_axi_bready(0) => s_axi_bready(0), s_axi_bvalid(0) => s_axi_bvalid(0), st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0), w_issuing_cnt(4 downto 0) => w_issuing_cnt(4 downto 0) ); \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(0), O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => cmd_push_0, I1 => active_cnt(0), I2 => active_cnt(1), O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AA9" ) port map ( I0 => active_cnt(2), I1 => active_cnt(0), I2 => active_cnt(1), I3 => cmd_push_0, O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAA9" ) port map ( I0 => active_cnt(3), I1 => active_cnt(2), I2 => cmd_push_0, I3 => active_cnt(1), I4 => active_cnt(0), O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_16\, D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\, Q => active_cnt(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_16\, D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\, Q => active_cnt(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_16\, D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\, Q => active_cnt(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_16\, D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\, Q => active_cnt(3), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(6), Q => \^q\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(7), Q => \^q\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(8), Q => \^q\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \s_axi_awaddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0500050035300500" ) port map ( I0 => \m_ready_d_reg[1]\, I1 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\, I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\, I3 => aid_match_00, I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\, O => cmd_push_0 ); \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => aid_match_40, I1 => active_cnt(34), I2 => active_cnt(35), I3 => active_cnt(33), I4 => active_cnt(32), O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFF" ) port map ( I0 => active_cnt(42), I1 => active_cnt(43), I2 => active_cnt(41), I3 => active_cnt(40), I4 => aid_match_50, O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \^st_aa_awtarget_enc\(0), Q => active_target(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_0, D => \^d\(0), Q => active_target(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(10), I1 => active_cnt(8), I2 => active_cnt(9), I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(11), I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\, I2 => active_cnt(9), I3 => active_cnt(8), I4 => active_cnt(10), O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFBBFFBBF0BBFFBB" ) port map ( I0 => \m_ready_d_reg[1]\, I1 => aid_match_10, I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\, I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(8), O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\, I1 => active_cnt(8), I2 => active_cnt(9), O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_15\, D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\, Q => active_cnt(10), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_15\, D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\, Q => active_cnt(11), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_15\, D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\, Q => active_cnt(8), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_15\, D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\, Q => active_cnt(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(6), Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(7), Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(8), Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \s_axi_awaddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"08083B08" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\, I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\, I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\, I3 => aid_match_10, I4 => \m_ready_d_reg[1]\, O => cmd_push_1 ); \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0010" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\, I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\, I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\, O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(8), I1 => active_cnt(9), I2 => active_cnt(11), I3 => active_cnt(10), O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(0), I1 => active_cnt(1), I2 => active_cnt(3), I3 => active_cnt(2), O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\ ); \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \^st_aa_awtarget_enc\(0), Q => active_target(8), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_1, D => \^d\(0), Q => active_target(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(16), O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\, I1 => active_cnt(16), I2 => active_cnt(17), O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(18), I1 => active_cnt(16), I2 => active_cnt(17), I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(19), I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\, I2 => active_cnt(17), I3 => active_cnt(16), I4 => active_cnt(18), O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(16), I1 => active_cnt(17), I2 => active_cnt(19), I3 => active_cnt(18), O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_14\, D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\, Q => active_cnt(16), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_14\, D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\, Q => active_cnt(17), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_14\, D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\, Q => active_cnt(18), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_14\, D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\, Q => active_cnt(19), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(6), Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(7), Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(8), Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \s_axi_awaddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\, O => cmd_push_2 ); \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFDDFFDDF0DDFFDD" ) port map ( I0 => aid_match_20, I1 => \m_ready_d_reg[1]\, I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\, I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF0001" ) port map ( I0 => active_cnt(10), I1 => active_cnt(11), I2 => active_cnt(9), I3 => active_cnt(8), I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\, O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \^st_aa_awtarget_enc\(0), Q => active_target(16), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_2, D => \^d\(0), Q => active_target(17), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(24), O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => cmd_push_3, I1 => active_cnt(24), I2 => active_cnt(25), O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AA9" ) port map ( I0 => active_cnt(26), I1 => active_cnt(24), I2 => active_cnt(25), I3 => cmd_push_3, O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAA9" ) port map ( I0 => active_cnt(27), I1 => active_cnt(26), I2 => cmd_push_3, I3 => active_cnt(25), I4 => active_cnt(24), O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_13\, D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\, Q => active_cnt(24), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_13\, D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\, Q => active_cnt(25), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_13\, D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\, Q => active_cnt(26), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_13\, D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\, Q => active_cnt(27), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(6), Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(7), Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(8), Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \s_axi_awaddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"004400440F440044" ) port map ( I0 => \m_ready_d_reg[1]\, I1 => aid_match_30, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\, O => cmd_push_3 ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF0001" ) port map ( I0 => active_cnt(18), I1 => active_cnt(19), I2 => active_cnt(17), I3 => active_cnt(16), I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\, I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(24), I1 => active_cnt(25), I2 => active_cnt(27), I3 => active_cnt(26), O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\, I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\, I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFEFFF" ) port map ( I0 => \m_ready_d_reg[1]\, I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\, I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\, I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFF" ) port map ( I0 => active_cnt(18), I1 => active_cnt(19), I2 => active_cnt(17), I3 => active_cnt(16), I4 => aid_match_20, O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => aid_match_10, I1 => active_cnt(10), I2 => active_cnt(11), I3 => active_cnt(9), I4 => active_cnt(8), O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => aid_match_30, I1 => active_cnt(26), I2 => active_cnt(27), I3 => active_cnt(25), I4 => active_cnt(24), O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\ ); \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \^st_aa_awtarget_enc\(0), Q => active_target(24), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_3, D => \^d\(0), Q => active_target(25), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(32), O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\, I1 => active_cnt(32), I2 => active_cnt(33), O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(34), I1 => active_cnt(32), I2 => active_cnt(33), I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(35), I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\, I2 => active_cnt(33), I3 => active_cnt(32), I4 => active_cnt(34), O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(32), I1 => active_cnt(33), I2 => active_cnt(35), I3 => active_cnt(34), O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_12\, D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\, Q => active_cnt(32), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_12\, D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\, Q => active_cnt(33), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_12\, D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\, Q => active_cnt(34), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_12\, D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\, Q => active_cnt(35), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(6), Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(7), Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(8), Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \s_axi_awaddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\, O => cmd_push_4 ); \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFAFAFAFAFACAFAF" ) port map ( I0 => \m_ready_d_reg[1]\, I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\, I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\, I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\, I1 => active_cnt(34), I2 => active_cnt(35), I3 => active_cnt(33), I4 => active_cnt(32), O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => aid_match_00, I1 => active_cnt(2), I2 => active_cnt(3), I3 => active_cnt(1), I4 => active_cnt(0), O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF0001" ) port map ( I0 => active_cnt(26), I1 => active_cnt(27), I2 => active_cnt(25), I3 => active_cnt(24), I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\, O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\ ); \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \^st_aa_awtarget_enc\(0), Q => active_target(32), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_4, D => \^d\(0), Q => active_target(33), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(40), O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\, I1 => active_cnt(40), I2 => active_cnt(41), O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(42), I1 => active_cnt(40), I2 => active_cnt(41), I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(43), I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\, I2 => active_cnt(41), I3 => active_cnt(40), I4 => active_cnt(42), O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(40), I1 => active_cnt(41), I2 => active_cnt(43), I3 => active_cnt(42), O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_11\, D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\, Q => active_cnt(40), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_11\, D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\, Q => active_cnt(41), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_11\, D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\, Q => active_cnt(42), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_11\, D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\, Q => active_cnt(43), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(6), Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(7), Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(8), Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \s_axi_awaddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\, O => cmd_push_5 ); \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FAFAFFFFFACAFFCF" ) port map ( I0 => \m_ready_d_reg[1]\, I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\, I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\, I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\, I4 => aid_match_50, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\, O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \^st_aa_awtarget_enc\(0), Q => active_target(40), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_5, D => \^d\(0), Q => active_target(41), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(48), O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\, I1 => active_cnt(48), I2 => active_cnt(49), O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(50), I1 => active_cnt(48), I2 => active_cnt(49), I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(51), I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\, I2 => active_cnt(49), I3 => active_cnt(48), I4 => active_cnt(50), O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => active_cnt(51), I1 => active_cnt(50), I2 => active_cnt(48), I3 => active_cnt(49), O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_10\, D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\, Q => active_cnt(48), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_10\, D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\, Q => active_cnt(49), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_10\, D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\, Q => active_cnt(50), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_10\, D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\, Q => active_cnt(51), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(6), Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(7), Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(8), Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \s_axi_awaddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\, O => cmd_push_6 ); \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEEEEE0EEEE" ) port map ( I0 => \m_ready_d_reg[1]\, I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\, I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\, I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\, I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"55555557" ) port map ( I0 => aid_match_60, I1 => active_cnt(49), I2 => active_cnt(48), I3 => active_cnt(50), I4 => active_cnt(51), O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\, I2 => active_cnt(51), I3 => active_cnt(50), I4 => active_cnt(48), I5 => active_cnt(49), O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFE0000" ) port map ( I0 => active_cnt(32), I1 => active_cnt(33), I2 => active_cnt(35), I3 => active_cnt(34), I4 => aid_match_40, I5 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\, O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\ ); \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \^st_aa_awtarget_enc\(0), Q => active_target(48), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_6, D => \^d\(0), Q => active_target(49), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active_cnt(56), O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\, I1 => active_cnt(56), I2 => active_cnt(57), O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"A96A" ) port map ( I0 => active_cnt(58), I1 => active_cnt(56), I2 => active_cnt(57), I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => active_cnt(59), I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\, I2 => active_cnt(57), I3 => active_cnt(56), I4 => active_cnt(58), O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => active_cnt(56), I1 => active_cnt(57), I2 => active_cnt(59), I3 => active_cnt(58), O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_9\, D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\, Q => active_cnt(56), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_9\, D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\, Q => active_cnt(57), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_9\, D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\, Q => active_cnt(58), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \gen_multi_thread.arbiter_resp_inst_n_9\, D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\, Q => active_cnt(59), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(0), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(1), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(2), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(3), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(4), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(5), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(6), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(7), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(8), Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(9), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(10), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \s_axi_awaddr[31]\(11), Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\, I1 => \s_axi_awaddr[31]\(17), I2 => \s_axi_awaddr[31]\(20), O => \^st_aa_awtarget_enc\(0) ); \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\, I1 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\, I2 => \s_axi_awaddr[31]\(19), I3 => \s_axi_awaddr[31]\(15), I4 => \s_axi_awaddr[31]\(12), I5 => \s_axi_awaddr[31]\(23), O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\, O => cmd_push_7 ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \s_axi_awaddr[31]\(14), I1 => \s_axi_awaddr[31]\(25), I2 => \s_axi_awaddr[31]\(21), I3 => \s_axi_awaddr[31]\(22), O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000100" ) port map ( I0 => \s_axi_awaddr[31]\(24), I1 => \s_axi_awaddr[31]\(27), I2 => \s_axi_awaddr[31]\(13), I3 => \s_axi_awaddr[31]\(26), I4 => \s_axi_awaddr[31]\(18), I5 => \s_axi_awaddr[31]\(16), O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^st_aa_awtarget_enc\(0), I1 => st_aa_awtarget_hot(0), O => \^d\(0) ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF0000FFEF" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\, I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\, I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\, I4 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\, I5 => \m_ready_d_reg[1]\, O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF0001" ) port map ( I0 => active_cnt(34), I1 => active_cnt(35), I2 => active_cnt(33), I3 => active_cnt(32), I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFD" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\, I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\, I2 => active_cnt(58), I3 => active_cnt(59), I4 => active_cnt(57), I5 => active_cnt(56), O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"EFFF" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\, I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\, I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\, O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => aid_match_70, I1 => active_cnt(58), I2 => active_cnt(59), I3 => active_cnt(57), I4 => active_cnt(56), O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\ ); \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \^st_aa_awtarget_enc\(0), Q => active_target(56), R => \^sr\(0) ); \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => cmd_push_7, D => \^d\(0), Q => active_target(57), R => \^sr\(0) ); \gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"0000F100" ) port map ( I0 => active_target(41), I1 => st_aa_awtarget_hot(0), I2 => active_target(40), I3 => aid_match_50, I4 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5 generic map( INIT => X"22220002" ) port map ( I0 => aid_match_20, I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\, I2 => active_target(17), I3 => st_aa_awtarget_hot(0), I4 => active_target(16), O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"54" ) port map ( I0 => active_target(56), I1 => st_aa_awtarget_hot(0), I2 => active_target(57), O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT3 generic map( INIT => X"54" ) port map ( I0 => active_target(8), I1 => st_aa_awtarget_hot(0), I2 => active_target(9), O => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"44440004" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\, I1 => aid_match_00, I2 => active_target(1), I3 => st_aa_awtarget_hot(0), I4 => active_target(0), O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"44440004" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\, I1 => aid_match_30, I2 => active_target(25), I3 => st_aa_awtarget_hot(0), I4 => active_target(24), O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"0404040404FF0404" ) port map ( I0 => active_target(32), I1 => aid_match_40, I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\, I3 => active_target(8), I4 => aid_match_10, I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFB00FBFB" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\, I1 => aid_match_50, I2 => active_target(40), I3 => active_target(24), I4 => aid_match_30, I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT6 generic map( INIT => X"0404040404FF0404" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\, I1 => aid_match_20, I2 => active_target(16), I3 => active_target(0), I4 => aid_match_00, I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFFE0000" ) port map ( I0 => active_cnt(56), I1 => active_cnt(57), I2 => active_cnt(59), I3 => active_cnt(58), I4 => aid_match_70, I5 => active_target(56), O => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT6 generic map( INIT => X"4040FF4040404040" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\, I1 => aid_match_20, I2 => active_target(17), I3 => aid_match_00, I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\, I5 => active_target(1), O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT6 generic map( INIT => X"2020FF2020202020" ) port map ( I0 => aid_match_40, I1 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\, I2 => active_target(33), I3 => aid_match_70, I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\, I5 => active_target(57), O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT6 generic map( INIT => X"DFDF00DFDFDFDFDF" ) port map ( I0 => active_target(41), I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\, I2 => aid_match_50, I3 => aid_match_10, I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\, I5 => active_target(9), O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT6 generic map( INIT => X"8080FF8080808080" ) port map ( I0 => aid_match_60, I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\, I2 => active_target(49), I3 => aid_match_30, I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\, I5 => active_target(25), O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => \gen_multi_thread.accept_cnt_reg\(0), I1 => \gen_multi_thread.accept_cnt_reg\(1), I2 => \gen_multi_thread.accept_cnt_reg\(2), O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"000000000000DDD0" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\, I1 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\, I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\, I3 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\, I4 => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\, I5 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF22F2" ) port map ( I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\, I1 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\, I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\, I3 => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\, I4 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\, I5 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000004040400" ) port map ( I0 => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\, I1 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\, I2 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\, I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\, I4 => active_target(48), I5 => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEEEEE0EEEE" ) port map ( I0 => st_aa_awtarget_hot(0), I1 => \^st_aa_awtarget_enc\(0), I2 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\, I3 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\, I4 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\, I5 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\, O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT3 generic map( INIT => X"54" ) port map ( I0 => active_target(32), I1 => st_aa_awtarget_hot(0), I2 => active_target(33), O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ ); \gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT3 generic map( INIT => X"54" ) port map ( I0 => active_target(48), I1 => st_aa_awtarget_hot(0), I2 => active_target(49), O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ ); \i__carry_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[12]\, I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10), I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9), I3 => \m_payload_i_reg[11]\, I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11), I5 => \m_payload_i_reg[13]\, O => \i__carry_i_1_n_0\ ); \i__carry_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[6]\, I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4), I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3), I3 => \m_payload_i_reg[5]\, I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5), I5 => \m_payload_i_reg[7]\, O => \i__carry_i_3_n_0\ ); \i__carry_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[3]\, I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1), I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0), I3 => \m_payload_i_reg[2]\, I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2), I5 => \m_payload_i_reg[4]\, O => \i__carry_i_4_n_0\ ); \p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_0_out, CO(2) => \p_0_out_inferred__9/i__carry_n_1\, CO(1) => \p_0_out_inferred__9/i__carry_n_2\, CO(0) => \p_0_out_inferred__9/i__carry_n_3\, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0), S(3) => \i__carry_i_1_n_0\, S(2) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0), S(1) => \i__carry_i_3_n_0\, S(0) => \i__carry_i_4_n_0\ ); p_10_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_10_out, CO(2) => p_10_out_carry_n_1, CO(1) => p_10_out_carry_n_2, CO(0) => p_10_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0), S(3) => p_10_out_carry_i_1_n_0, S(2) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0), S(1) => p_10_out_carry_i_3_n_0, S(0) => p_10_out_carry_i_4_n_0 ); p_10_out_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[12]\, I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10), I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9), I3 => \m_payload_i_reg[11]\, I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11), I5 => \m_payload_i_reg[13]\, O => p_10_out_carry_i_1_n_0 ); p_10_out_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[6]\, I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4), I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3), I3 => \m_payload_i_reg[5]\, I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5), I5 => \m_payload_i_reg[7]\, O => p_10_out_carry_i_3_n_0 ); p_10_out_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[3]\, I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1), I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0), I3 => \m_payload_i_reg[2]\, I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2), I5 => \m_payload_i_reg[4]\, O => p_10_out_carry_i_4_n_0 ); p_12_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_12_out, CO(2) => p_12_out_carry_n_1, CO(1) => p_12_out_carry_n_2, CO(0) => p_12_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0), S(3) => p_12_out_carry_i_1_n_0, S(2) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0), S(1) => p_12_out_carry_i_3_n_0, S(0) => p_12_out_carry_i_4_n_0 ); p_12_out_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[12]\, I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9), I3 => \m_payload_i_reg[11]\, I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11), I5 => \m_payload_i_reg[13]\, O => p_12_out_carry_i_1_n_0 ); p_12_out_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[6]\, I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3), I3 => \m_payload_i_reg[5]\, I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5), I5 => \m_payload_i_reg[7]\, O => p_12_out_carry_i_3_n_0 ); p_12_out_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[3]\, I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1), I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0), I3 => \m_payload_i_reg[2]\, I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2), I5 => \m_payload_i_reg[4]\, O => p_12_out_carry_i_4_n_0 ); p_14_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_14_out, CO(2) => p_14_out_carry_n_1, CO(1) => p_14_out_carry_n_2, CO(0) => p_14_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0), S(3) => p_14_out_carry_i_1_n_0, S(2) => S(0), S(1) => p_14_out_carry_i_3_n_0, S(0) => p_14_out_carry_i_4_n_0 ); p_14_out_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[12]\, I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10), I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9), I3 => \m_payload_i_reg[11]\, I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11), I5 => \m_payload_i_reg[13]\, O => p_14_out_carry_i_1_n_0 ); p_14_out_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[6]\, I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4), I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3), I3 => \m_payload_i_reg[5]\, I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5), I5 => \m_payload_i_reg[7]\, O => p_14_out_carry_i_3_n_0 ); p_14_out_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[3]\, I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1), I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0), I3 => \m_payload_i_reg[2]\, I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2), I5 => \m_payload_i_reg[4]\, O => p_14_out_carry_i_4_n_0 ); p_2_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_2_out, CO(2) => p_2_out_carry_n_1, CO(1) => p_2_out_carry_n_2, CO(0) => p_2_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0), S(3) => p_2_out_carry_i_1_n_0, S(2) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0), S(1) => p_2_out_carry_i_3_n_0, S(0) => p_2_out_carry_i_4_n_0 ); p_2_out_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[12]\, I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10), I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9), I3 => \m_payload_i_reg[11]\, I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11), I5 => \m_payload_i_reg[13]\, O => p_2_out_carry_i_1_n_0 ); p_2_out_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[6]\, I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4), I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3), I3 => \m_payload_i_reg[5]\, I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5), I5 => \m_payload_i_reg[7]\, O => p_2_out_carry_i_3_n_0 ); p_2_out_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[3]\, I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1), I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0), I3 => \m_payload_i_reg[2]\, I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2), I5 => \m_payload_i_reg[4]\, O => p_2_out_carry_i_4_n_0 ); p_4_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_4_out, CO(2) => p_4_out_carry_n_1, CO(1) => p_4_out_carry_n_2, CO(0) => p_4_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0), S(3) => p_4_out_carry_i_1_n_0, S(2) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0), S(1) => p_4_out_carry_i_3_n_0, S(0) => p_4_out_carry_i_4_n_0 ); p_4_out_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[12]\, I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10), I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9), I3 => \m_payload_i_reg[11]\, I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11), I5 => \m_payload_i_reg[13]\, O => p_4_out_carry_i_1_n_0 ); p_4_out_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[6]\, I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4), I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3), I3 => \m_payload_i_reg[5]\, I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5), I5 => \m_payload_i_reg[7]\, O => p_4_out_carry_i_3_n_0 ); p_4_out_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[3]\, I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1), I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0), I3 => \m_payload_i_reg[2]\, I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2), I5 => \m_payload_i_reg[4]\, O => p_4_out_carry_i_4_n_0 ); p_6_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_6_out, CO(2) => p_6_out_carry_n_1, CO(1) => p_6_out_carry_n_2, CO(0) => p_6_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0), S(3) => p_6_out_carry_i_1_n_0, S(2) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0), S(1) => p_6_out_carry_i_3_n_0, S(0) => p_6_out_carry_i_4_n_0 ); p_6_out_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[12]\, I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10), I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9), I3 => \m_payload_i_reg[11]\, I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11), I5 => \m_payload_i_reg[13]\, O => p_6_out_carry_i_1_n_0 ); p_6_out_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[6]\, I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4), I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3), I3 => \m_payload_i_reg[5]\, I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5), I5 => \m_payload_i_reg[7]\, O => p_6_out_carry_i_3_n_0 ); p_6_out_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[3]\, I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1), I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0), I3 => \m_payload_i_reg[2]\, I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2), I5 => \m_payload_i_reg[4]\, O => p_6_out_carry_i_4_n_0 ); p_8_out_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => p_8_out, CO(2) => p_8_out_carry_n_1, CO(1) => p_8_out_carry_n_2, CO(0) => p_8_out_carry_n_3, CYINIT => '1', DI(3 downto 0) => B"0000", O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0), S(3) => p_8_out_carry_i_1_n_0, S(2) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0), S(1) => p_8_out_carry_i_3_n_0, S(0) => p_8_out_carry_i_4_n_0 ); p_8_out_carry_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[12]\, I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10), I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9), I3 => \m_payload_i_reg[11]\, I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11), I5 => \m_payload_i_reg[13]\, O => p_8_out_carry_i_1_n_0 ); p_8_out_carry_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[6]\, I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4), I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3), I3 => \m_payload_i_reg[5]\, I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5), I5 => \m_payload_i_reg[7]\, O => p_8_out_carry_i_3_n_0 ); p_8_out_carry_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000066006600000" ) port map ( I0 => \m_payload_i_reg[3]\, I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1), I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0), I3 => \m_payload_i_reg[2]\, I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2), I5 => \m_payload_i_reg[4]\, O => p_8_out_carry_i_4_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is port ( s_ready_i_reg_0 : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); \gen_axi.write_cs_reg[1]\ : out STD_LOGIC; s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 ); aclk : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 ); p_14_in : in STD_LOGIC; ss_wr_awvalid : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is signal \/FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC; signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC; signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC; signal \/FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes"; signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC; attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes"; signal areset_d1 : STD_LOGIC; signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC; signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC; signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC; signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC; signal \gen_srls[0].gen_rep[1].srl_nx1_n_1\ : STD_LOGIC; signal \gen_srls[0].gen_rep[1].srl_nx1_n_2\ : STD_LOGIC; signal \gen_srls[0].gen_rep[1].srl_nx1_n_3\ : STD_LOGIC; signal load_s1 : STD_LOGIC; signal m_avalid : STD_LOGIC; signal m_valid_i : STD_LOGIC; signal m_valid_i_i_1_n_0 : STD_LOGIC; signal p_0_in5_out : STD_LOGIC; signal p_0_in8_in : STD_LOGIC; attribute RTL_KEEP of p_0_in8_in : signal is "yes"; signal p_9_in : STD_LOGIC; attribute RTL_KEEP of p_9_in : signal is "yes"; signal push : STD_LOGIC; signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; signal s_ready_i_i_2_n_0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal \storage_data1[0]_i_1_n_0\ : STD_LOGIC; signal \storage_data1_reg_n_0_[0]\ : STD_LOGIC; signal \storage_data1_reg_n_0_[1]\ : STD_LOGIC; attribute KEEP : string; attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes"; attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes"; attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes"; attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes"; attribute syn_keep : string; attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1"; attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1"; attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair142"; attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair142"; begin s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \/FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"40440000" ) port map ( I0 => p_9_in, I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I2 => m_ready_d(0), I3 => s_axi_awvalid(0), I4 => p_0_in8_in, O => \/FSM_onehot_state[0]_i_1_n_0\ ); \/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20202F20" ) port map ( I0 => s_axi_awvalid(0), I1 => m_ready_d(0), I2 => p_9_in, I3 => p_0_in5_out, I4 => p_0_in8_in, O => \/FSM_onehot_state[1]_i_1_n_0\ ); \/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B0B0B0BF" ) port map ( I0 => m_ready_d(0), I1 => s_axi_awvalid(0), I2 => p_9_in, I3 => p_0_in5_out, I4 => p_0_in8_in, O => \/FSM_onehot_state[2]_i_1_n_0\ ); \/FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00002A22" ) port map ( I0 => p_0_in8_in, I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I2 => m_ready_d(0), I3 => s_axi_awvalid(0), I4 => p_9_in, O => \/FSM_onehot_state[3]_i_2_n_0\ ); \FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF488F488F488" ) port map ( I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I1 => p_0_in8_in, I2 => p_9_in, I3 => ss_wr_awvalid, I4 => \FSM_onehot_state_reg_n_0_[3]\, I5 => p_0_in5_out, O => m_valid_i ); \FSM_onehot_state[3]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000010000000" ) port map ( I0 => fifoaddr(1), I1 => fifoaddr(0), I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\, I3 => \FSM_onehot_state_reg_n_0_[3]\, I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I5 => fifoaddr(2), O => p_0_in5_out ); \FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => m_valid_i, D => \/FSM_onehot_state[0]_i_1_n_0\, Q => p_9_in, S => areset_d1 ); \FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => m_valid_i, D => \/FSM_onehot_state[1]_i_1_n_0\, Q => p_0_in8_in, R => areset_d1 ); \FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => m_valid_i, D => \/FSM_onehot_state[2]_i_1_n_0\, Q => \FSM_onehot_state_reg_n_0_[2]\, R => areset_d1 ); \FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => m_valid_i, D => \/FSM_onehot_state[3]_i_2_n_0\, Q => \FSM_onehot_state_reg_n_0_[3]\, R => areset_d1 ); areset_d1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => SR(0), Q => areset_d1, R => '0' ); \gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0400000000000000" ) port map ( I0 => \storage_data1_reg_n_0_[0]\, I1 => \storage_data1_reg_n_0_[1]\, I2 => \gen_axi.write_cs_reg[1]_0\(0), I3 => s_axi_wlast(0), I4 => s_axi_wvalid(0), I5 => m_avalid, O => \gen_axi.write_cs_reg[1]\ ); \gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"C133DDFF3ECC2200" ) port map ( I0 => p_0_in8_in, I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I2 => \^s_ready_i_reg_0\, I3 => ss_wr_awvalid, I4 => \FSM_onehot_state_reg_n_0_[3]\, I5 => fifoaddr(0), O => \gen_rep[0].fifoaddr[0]_i_1_n_0\ ); \gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"BFD5402A" ) port map ( I0 => fifoaddr(0), I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I2 => \FSM_onehot_state_reg_n_0_[3]\, I3 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\, I4 => fifoaddr(1), O => \gen_rep[0].fifoaddr[1]_i_1_n_0\ ); \gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"EFFFF77710000888" ) port map ( I0 => fifoaddr(0), I1 => fifoaddr(1), I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I3 => \FSM_onehot_state_reg_n_0_[3]\, I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\, I5 => fifoaddr(2), O => \gen_rep[0].fifoaddr[2]_i_1_n_0\ ); \gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE port map ( C => aclk, CE => '1', D => \gen_rep[0].fifoaddr[0]_i_1_n_0\, Q => fifoaddr(0), S => SR(0) ); \gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE port map ( C => aclk, CE => '1', D => \gen_rep[0].fifoaddr[1]_i_1_n_0\, Q => fifoaddr(1), S => SR(0) ); \gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE port map ( C => aclk, CE => '1', D => \gen_rep[0].fifoaddr[2]_i_1_n_0\, Q => fifoaddr(2), S => SR(0) ); \gen_srls[0].gen_rep[0].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ port map ( aclk => aclk, fifoaddr(2 downto 0) => fifoaddr(2 downto 0), push => push, st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0), \storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\ ); \gen_srls[0].gen_rep[1].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ port map ( D(0) => D(0), aclk => aclk, fifoaddr(2 downto 0) => fifoaddr(2 downto 0), \gen_rep[0].fifoaddr_reg[0]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, load_s1 => load_s1, m_avalid => m_avalid, m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0), m_ready_d(0) => m_ready_d(0), out0(1) => p_0_in8_in, out0(0) => \FSM_onehot_state_reg_n_0_[3]\, p_14_in => p_14_in, push => push, s_axi_awvalid(0) => s_axi_awvalid(0), s_axi_wlast(0) => s_axi_wlast(0), s_axi_wvalid(0) => s_axi_wvalid(0), s_ready_i_reg => \gen_srls[0].gen_rep[1].srl_nx1_n_2\, s_ready_i_reg_0 => \^s_ready_i_reg_0\, st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0), st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0), \storage_data1_reg[0]\ => \storage_data1_reg_n_0_[0]\, \storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_1\, \storage_data1_reg[1]_0\ => \storage_data1_reg_n_0_[1]\ ); \m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => \storage_data1_reg_n_0_[0]\, I1 => \storage_data1_reg_n_0_[1]\, I2 => m_avalid, I3 => s_axi_wvalid(0), O => m_axi_wvalid(0) ); \m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => \storage_data1_reg_n_0_[0]\, I1 => \storage_data1_reg_n_0_[1]\, I2 => m_avalid, I3 => s_axi_wvalid(0), O => m_axi_wvalid(1) ); m_valid_i_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF400F400F400" ) port map ( I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I1 => p_0_in8_in, I2 => p_9_in, I3 => ss_wr_awvalid, I4 => \FSM_onehot_state_reg_n_0_[3]\, I5 => p_0_in5_out, O => m_valid_i_i_1_n_0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => m_valid_i, D => m_valid_i_i_1_n_0, Q => m_avalid, R => areset_d1 ); \s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"0A8A008A0A800080" ) port map ( I0 => m_avalid, I1 => m_axi_wready(1), I2 => \storage_data1_reg_n_0_[0]\, I3 => \storage_data1_reg_n_0_[1]\, I4 => p_14_in, I5 => m_axi_wready(0), O => s_axi_wready(0) ); \s_ready_i_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FEFFFFFFAAAAAAAA" ) port map ( I0 => s_ready_i_i_2_n_0, I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\, I2 => fifoaddr(0), I3 => fifoaddr(1), I4 => fifoaddr(2), I5 => \^s_ready_i_reg_0\, O => \s_ready_i_i_1__2_n_0\ ); s_ready_i_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"EA" ) port map ( I0 => areset_d1, I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I2 => \FSM_onehot_state_reg_n_0_[3]\, O => s_ready_i_i_2_n_0 ); s_ready_i_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__2_n_0\, Q => \^s_ready_i_reg_0\, R => SR(0) ); \storage_data1[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \gen_srls[0].gen_rep[0].srl_nx1_n_0\, I1 => \FSM_onehot_state_reg_n_0_[3]\, I2 => st_aa_awtarget_enc(0), I3 => load_s1, I4 => \storage_data1_reg_n_0_[0]\, O => \storage_data1[0]_i_1_n_0\ ); \storage_data1[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"88888888FFC88888" ) port map ( I0 => \FSM_onehot_state_reg_n_0_[3]\, I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\, I2 => p_0_in8_in, I3 => p_9_in, I4 => s_axi_awvalid(0), I5 => m_ready_d(0), O => load_s1 ); \storage_data1_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \storage_data1[0]_i_1_n_0\, Q => \storage_data1_reg_n_0_[0]\, R => '0' ); \storage_data1_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_srls[0].gen_rep[1].srl_nx1_n_1\, Q => \storage_data1_reg_n_0_[1]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is port ( p_80_out : out STD_LOGIC; m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); p_74_out : out STD_LOGIC; \m_axi_rready[0]\ : out STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC; \gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \aresetn_d_reg[1]\ : in STD_LOGIC; aclk : in STD_LOGIC; p_1_in : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); \aresetn_d_reg[1]_0\ : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); D : in STD_LOGIC_VECTOR ( 13 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is begin b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ port map ( D(13 downto 0) => D(13 downto 0), aclk => aclk, \aresetn_d_reg[1]\ => \aresetn_d_reg[1]\, \aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\, chosen(0) => chosen(0), \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0), m_axi_bready(0) => m_axi_bready(0), m_axi_bvalid(0) => m_axi_bvalid(0), \m_payload_i_reg[0]_0\ => p_80_out, p_1_in => p_1_in, s_axi_bready(0) => s_axi_bready(0) ); r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ port map ( E(0) => E(0), Q(3 downto 0) => Q(3 downto 0), aclk => aclk, \aresetn_d_reg[1]\ => \aresetn_d_reg[1]\, chosen_0(0) => chosen_0(0), \gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0), \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0), m_axi_rlast(0) => m_axi_rlast(0), \m_axi_rready[0]\ => \m_axi_rready[0]\, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_rvalid(0) => m_axi_rvalid(0), m_valid_i_reg_0 => p_74_out, p_1_in => p_1_in, s_axi_rready(0) => s_axi_rready(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 is port ( p_60_out : out STD_LOGIC; m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); p_1_in : out STD_LOGIC; p_54_out : out STD_LOGIC; \m_axi_rready[1]\ : out STD_LOGIC; \gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC; \gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); \gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC; \gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 ); \gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC; \aresetn_d_reg[1]\ : out STD_LOGIC; \aresetn_d_reg[1]_0\ : in STD_LOGIC; aclk : in STD_LOGIC; aresetn : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen : in STD_LOGIC_VECTOR ( 1 downto 0 ); \aresetn_d_reg[1]_1\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[12]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); p_38_out : in STD_LOGIC; \m_payload_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[32]\ : in STD_LOGIC_VECTOR ( 20 downto 0 ); p_32_out : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); D : in STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 is signal \^p_1_in\ : STD_LOGIC; begin p_1_in <= \^p_1_in\; b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ port map ( D(13 downto 0) => D(13 downto 0), Q(3 downto 0) => Q(3 downto 0), aclk => aclk, aresetn => aresetn, \aresetn_d_reg[1]\ => \aresetn_d_reg[1]\, \aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\, \aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\, chosen(1 downto 0) => chosen(1 downto 0), \gen_multi_thread.accept_cnt_reg[3]\ => \gen_multi_thread.accept_cnt_reg[3]\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6 downto 0), \gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\, m_axi_bready(0) => m_axi_bready(0), m_axi_bvalid(0) => m_axi_bvalid(0), \m_payload_i_reg[0]_0\ => p_60_out, \m_payload_i_reg[12]_0\(9 downto 0) => \m_payload_i_reg[12]\(9 downto 0), \m_payload_i_reg[1]_0\(1 downto 0) => \m_payload_i_reg[1]\(1 downto 0), p_1_in => \^p_1_in\, p_38_out => p_38_out, s_axi_bid(4 downto 0) => s_axi_bid(4 downto 0), s_axi_bready(0) => s_axi_bready(0), s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0) ); r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ port map ( aclk => aclk, \aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\, chosen_0(1 downto 0) => chosen_0(1 downto 0), \gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].r_issuing_cnt_reg[11]\, \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0), \gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0), \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0), m_axi_rlast(0) => m_axi_rlast(0), \m_axi_rready[1]\ => \m_axi_rready[1]\, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_rvalid(0) => m_axi_rvalid(0), \m_payload_i_reg[32]_0\(20 downto 0) => \m_payload_i_reg[32]\(20 downto 0), p_1_in => \^p_1_in\, p_32_out => p_32_out, s_axi_rdata(19 downto 0) => s_axi_rdata(19 downto 0), s_axi_rready(0) => s_axi_rready(0), s_axi_rresp(0) => s_axi_rresp(0), s_ready_i_reg_0 => p_54_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 is port ( p_38_out : out STD_LOGIC; m_valid_i_reg : out STD_LOGIC; mi_bready_2 : out STD_LOGIC; p_32_out : out STD_LOGIC; mi_rready_2 : out STD_LOGIC; s_ready_i_reg : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC; \gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC; \gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC; \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); \gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC; aclk : in STD_LOGIC; p_1_in : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; p_21_in : in STD_LOGIC; chosen : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[13]\ : in STD_LOGIC_VECTOR ( 13 downto 0 ); m_valid_i_reg_0 : in STD_LOGIC; \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 ); r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 ); st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 ); \gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC; \gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC; p_15_in : in STD_LOGIC; s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); p_17_in : in STD_LOGIC; \gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 11 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 is signal \^m_valid_i_reg\ : STD_LOGIC; begin m_valid_i_reg <= \^m_valid_i_reg\; b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ port map ( D(11 downto 0) => D(11 downto 0), Q(4 downto 0) => Q(4 downto 0), S(0) => S(0), aclk => aclk, \aresetn_d_reg[0]\ => \aresetn_d_reg[0]\, chosen(0) => chosen(0), \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\, \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0), \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0), \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0), \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0), \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0), \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0), \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0), \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0), \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0), \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0), \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0), \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0), \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0), \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0), \gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\, \m_payload_i_reg[13]_0\(13 downto 0) => \m_payload_i_reg[13]\(13 downto 0), \m_payload_i_reg[2]_0\ => p_38_out, m_valid_i_reg_0 => \^m_valid_i_reg\, m_valid_i_reg_1 => m_valid_i_reg_0, mi_bready_2 => mi_bready_2, p_1_in => p_1_in, p_21_in => p_21_in, s_axi_bid(6 downto 0) => s_axi_bid(6 downto 0), s_axi_bready(0) => s_axi_bready(0), s_ready_i_reg_0 => s_ready_i_reg, w_issuing_cnt(0) => w_issuing_cnt(0) ); r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ port map ( E(0) => E(0), aclk => aclk, \aresetn_d_reg[1]\ => \^m_valid_i_reg\, chosen_0(0) => chosen_0(0), \gen_axi.s_axi_arready_i_reg\ => \gen_axi.s_axi_arready_i_reg\, \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0), \gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\, \gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\, \gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 0), \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\, m_valid_i_reg_0 => p_32_out, p_15_in => p_15_in, p_17_in => p_17_in, p_1_in => p_1_in, r_issuing_cnt(0) => r_issuing_cnt(0), s_axi_rready(0) => s_axi_rready(0), \skid_buffer_reg[34]_0\ => mi_rready_2, st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router is port ( ss_wr_awready : out STD_LOGIC; m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); \gen_axi.write_cs_reg[1]\ : out STD_LOGIC; s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 ); aclk : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 ); m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); \gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 ); p_14_in : in STD_LOGIC; ss_wr_awvalid : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router is begin wrouter_aw_fifo: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo port map ( D(0) => D(0), SR(0) => SR(0), aclk => aclk, \gen_axi.write_cs_reg[1]\ => \gen_axi.write_cs_reg[1]\, \gen_axi.write_cs_reg[1]_0\(0) => \gen_axi.write_cs_reg[1]_0\(0), m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0), m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0), m_ready_d(0) => m_ready_d(0), p_14_in => p_14_in, s_axi_awvalid(0) => s_axi_awvalid(0), s_axi_wlast(0) => s_axi_wlast(0), s_axi_wready(0) => s_axi_wready(0), s_axi_wvalid(0) => s_axi_wvalid(0), s_ready_i_reg_0 => ss_wr_awready, ss_wr_awvalid => ss_wr_awvalid, st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0), st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar is port ( S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 ); Q : out STD_LOGIC_VECTOR ( 68 downto 0 ); \m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 ); m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_RREADY : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); aclk : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); aresetn : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 56 downto 0 ); \s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 56 downto 0 ); s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar is signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 2 to 2 ); signal aa_mi_arvalid : STD_LOGIC; signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 2 downto 0 ); signal aa_sa_awvalid : STD_LOGIC; signal addr_arbiter_ar_n_2 : STD_LOGIC; signal addr_arbiter_ar_n_3 : STD_LOGIC; signal addr_arbiter_ar_n_4 : STD_LOGIC; signal addr_arbiter_ar_n_5 : STD_LOGIC; signal addr_arbiter_ar_n_6 : STD_LOGIC; signal addr_arbiter_ar_n_7 : STD_LOGIC; signal addr_arbiter_ar_n_80 : STD_LOGIC; signal addr_arbiter_ar_n_81 : STD_LOGIC; signal addr_arbiter_ar_n_82 : STD_LOGIC; signal addr_arbiter_ar_n_84 : STD_LOGIC; signal addr_arbiter_ar_n_85 : STD_LOGIC; signal addr_arbiter_aw_n_10 : STD_LOGIC; signal addr_arbiter_aw_n_11 : STD_LOGIC; signal addr_arbiter_aw_n_12 : STD_LOGIC; signal addr_arbiter_aw_n_13 : STD_LOGIC; signal addr_arbiter_aw_n_14 : STD_LOGIC; signal addr_arbiter_aw_n_15 : STD_LOGIC; signal addr_arbiter_aw_n_16 : STD_LOGIC; signal addr_arbiter_aw_n_2 : STD_LOGIC; signal addr_arbiter_aw_n_20 : STD_LOGIC; signal addr_arbiter_aw_n_21 : STD_LOGIC; signal addr_arbiter_aw_n_3 : STD_LOGIC; signal addr_arbiter_aw_n_7 : STD_LOGIC; signal addr_arbiter_aw_n_8 : STD_LOGIC; signal addr_arbiter_aw_n_9 : STD_LOGIC; signal aresetn_d : STD_LOGIC; signal \gen_decerr_slave.decerr_slave_inst_n_7\ : STD_LOGIC; signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC; signal \gen_master_slots[0].reg_slice_mi_n_5\ : STD_LOGIC; signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_12\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_20\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_21\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_22\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_23\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_26\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_27\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_5\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_6\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_75\ : STD_LOGIC; signal \gen_master_slots[1].reg_slice_mi_n_76\ : STD_LOGIC; signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_1\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_13\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_19\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_20\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_21\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_22\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_23\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_24\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_25\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_26\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_27\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_28\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_29\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_30\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_31\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_45\ : STD_LOGIC; signal \gen_master_slots[2].reg_slice_mi_n_5\ : STD_LOGIC; signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_multi_thread.arbiter_resp_inst/chosen_1\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 ); signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 ); signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 ); signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 ); signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 ); signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 ); signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 ); signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 ); signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\ : STD_LOGIC; signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\ : STD_LOGIC; signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 ); signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m_ready_d_3 : STD_LOGIC_VECTOR ( 1 downto 0 ); signal m_valid_i : STD_LOGIC; signal m_valid_i_2 : STD_LOGIC; signal mi_arready_2 : STD_LOGIC; signal mi_awready_2 : STD_LOGIC; signal mi_bready_2 : STD_LOGIC; signal mi_rready_2 : STD_LOGIC; signal p_14_in : STD_LOGIC; signal p_15_in : STD_LOGIC; signal p_17_in : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_20_in : STD_LOGIC_VECTOR ( 11 downto 0 ); signal p_21_in : STD_LOGIC; signal p_24_in : STD_LOGIC_VECTOR ( 11 downto 0 ); signal p_32_out : STD_LOGIC; signal p_34_out : STD_LOGIC; signal p_38_out : STD_LOGIC; signal p_54_out : STD_LOGIC; signal p_56_out : STD_LOGIC; signal p_60_out : STD_LOGIC; signal p_74_out : STD_LOGIC; signal p_76_out : STD_LOGIC; signal p_80_out : STD_LOGIC; signal r_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 ); signal \r_pipe/p_1_in\ : STD_LOGIC; signal \r_pipe/p_1_in_0\ : STD_LOGIC; signal reset : STD_LOGIC; signal s_axi_rlast_i0 : STD_LOGIC; signal s_axi_rvalid_i : STD_LOGIC; signal ss_aa_awready : STD_LOGIC; signal ss_wr_awready : STD_LOGIC; signal ss_wr_awvalid : STD_LOGIC; signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 ); signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 0 to 0 ); signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 ); signal st_mr_bid : STD_LOGIC_VECTOR ( 34 downto 0 ); signal st_mr_bmesg : STD_LOGIC_VECTOR ( 1 downto 0 ); signal st_mr_rid : STD_LOGIC_VECTOR ( 35 downto 0 ); signal st_mr_rmesg : STD_LOGIC_VECTOR ( 69 downto 0 ); signal w_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 ); signal write_cs : STD_LOGIC_VECTOR ( 1 to 1 ); begin Q(68 downto 0) <= \^q\(68 downto 0); S_AXI_ARREADY(0) <= \^s_axi_arready\(0); \m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0); addr_arbiter_ar: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter port map ( D(2) => addr_arbiter_ar_n_2, D(1) => addr_arbiter_ar_n_3, D(0) => addr_arbiter_ar_n_4, E(0) => s_axi_rvalid_i, Q(0) => p_56_out, SR(0) => reset, aa_mi_arvalid => aa_mi_arvalid, aclk => aclk, aresetn_d => aresetn_d, aresetn_d_reg => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\, aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\, \chosen_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\, \gen_axi.read_cnt_reg[5]\ => \gen_decerr_slave.decerr_slave_inst_n_7\, \gen_axi.s_axi_rid_i_reg[11]\(0) => aa_mi_artarget_hot(2), \gen_master_slots[0].r_issuing_cnt_reg[0]\(0) => addr_arbiter_ar_n_84, \gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_5, \gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_6, \gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_7, \gen_master_slots[1].r_issuing_cnt_reg[8]\(0) => addr_arbiter_ar_n_85, \gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_31\, \gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\, \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ => addr_arbiter_ar_n_82, \gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) => st_aa_artarget_hot(0), \gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_ar_n_80, \gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_ar_n_81, \m_axi_arqos[7]\(68 downto 0) => \^m_axi_arqos[7]\(68 downto 0), m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0), m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0), \m_payload_i_reg[34]\ => \gen_master_slots[0].reg_slice_mi_n_5\, \m_payload_i_reg[34]_0\ => \gen_master_slots[1].reg_slice_mi_n_27\, m_valid_i => m_valid_i, m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_75\, mi_arready_2 => mi_arready_2, p_15_in => p_15_in, r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8), r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0), \s_axi_araddr[25]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\, \s_axi_araddr[28]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\, \s_axi_araddr[30]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\, \s_axi_arqos[3]\(68 downto 12) => \s_axi_arqos[3]\(56 downto 0), \s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0), \s_axi_arready[0]\ => \^s_axi_arready\(0), s_axi_arvalid(0) => s_axi_arvalid(0), s_axi_rlast_i0 => s_axi_rlast_i0, s_axi_rready(0) => s_axi_rready(0), st_aa_artarget_hot(0) => st_aa_artarget_hot(1) ); addr_arbiter_aw: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 port map ( D(2) => addr_arbiter_aw_n_7, D(1) => addr_arbiter_aw_n_8, D(0) => addr_arbiter_aw_n_9, E(0) => addr_arbiter_aw_n_15, Q(68 downto 0) => \^q\(68 downto 0), SR(0) => reset, aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0), aa_sa_awvalid => aa_sa_awvalid, aclk => aclk, aresetn_d => aresetn_d, aresetn_d_reg => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\, aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\, \chosen_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\, \chosen_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\, \gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => addr_arbiter_aw_n_16, \gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => addr_arbiter_aw_n_11, \gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => addr_arbiter_aw_n_12, \gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => addr_arbiter_aw_n_13, \gen_master_slots[1].w_issuing_cnt_reg[9]\ => addr_arbiter_aw_n_10, \gen_master_slots[2].w_issuing_cnt_reg[16]\ => addr_arbiter_aw_n_14, \gen_no_arbiter.m_target_hot_i_reg[2]_0\ => addr_arbiter_aw_n_20, m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0), m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0), m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0), m_ready_d_0(0) => m_ready_d(0), \m_ready_d_reg[0]\ => addr_arbiter_aw_n_2, \m_ready_d_reg[1]\ => addr_arbiter_aw_n_3, \m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_21, m_valid_i => m_valid_i_2, m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\, mi_awready_2 => mi_awready_2, \s_axi_awaddr[20]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\, \s_axi_awaddr[26]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\, \s_axi_awqos[3]\(68 downto 12) => D(56 downto 0), \s_axi_awqos[3]\(11 downto 0) => s_axi_awid(11 downto 0), s_axi_bready(0) => s_axi_bready(0), ss_aa_awready => ss_aa_awready, st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0), st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0), w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8), w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0) ); aresetn_d_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn, Q => aresetn_d, R => '0' ); \gen_decerr_slave.decerr_slave_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave port map ( E(0) => s_axi_rvalid_i, Q(11 downto 0) => p_24_in(11 downto 0), SR(0) => reset, aa_mi_arvalid => aa_mi_arvalid, aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2), aa_sa_awvalid => aa_sa_awvalid, aclk => aclk, aresetn_d => aresetn_d, \gen_axi.s_axi_arready_i_reg_0\ => \gen_decerr_slave.decerr_slave_inst_n_7\, \gen_axi.write_cs_reg[1]_0\(0) => write_cs(1), \gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0), \gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[7]\(51 downto 44), \gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[7]\(11 downto 0), \gen_no_arbiter.m_target_hot_i_reg[2]\(0) => aa_mi_artarget_hot(2), \gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_aw_n_10, m_ready_d(0) => m_ready_d_3(1), \m_ready_d_reg[1]\ => addr_arbiter_aw_n_14, mi_arready_2 => mi_arready_2, mi_awready_2 => mi_awready_2, mi_bready_2 => mi_bready_2, mi_rready_2 => mi_rready_2, p_14_in => p_14_in, p_15_in => p_15_in, p_17_in => p_17_in, p_21_in => p_21_in, s_axi_rlast_i0 => s_axi_rlast_i0, \skid_buffer_reg[46]\(11 downto 0) => p_20_in(11 downto 0), \storage_data1_reg[0]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\ ); \gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => r_issuing_cnt(0), O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ ); \gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_ar_n_84, D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\, Q => r_issuing_cnt(0), R => reset ); \gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_ar_n_84, D => addr_arbiter_ar_n_4, Q => r_issuing_cnt(1), R => reset ); \gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_ar_n_84, D => addr_arbiter_ar_n_3, Q => r_issuing_cnt(2), R => reset ); \gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_ar_n_84, D => addr_arbiter_ar_n_2, Q => r_issuing_cnt(3), R => reset ); \gen_master_slots[0].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice port map ( D(13 downto 2) => m_axi_bid(11 downto 0), D(1 downto 0) => m_axi_bresp(1 downto 0), E(0) => \r_pipe/p_1_in_0\, Q(3 downto 0) => r_issuing_cnt(3 downto 0), aclk => aclk, \aresetn_d_reg[1]\ => \gen_master_slots[2].reg_slice_mi_n_1\, \aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_5\, chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(0), chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0), \gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_5\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 2) => st_mr_bid(11 downto 0), \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1 downto 0) => st_mr_bmesg(1 downto 0), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_76_out, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3), \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\, m_axi_bready(0) => m_axi_bready(0), m_axi_bvalid(0) => m_axi_bvalid(0), m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0), m_axi_rlast(0) => m_axi_rlast(0), \m_axi_rready[0]\ => M_AXI_RREADY(0), m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_rvalid(0) => m_axi_rvalid(0), p_1_in => p_1_in, p_74_out => p_74_out, p_80_out => p_80_out, s_axi_bready(0) => s_axi_bready(0), s_axi_rready(0) => s_axi_rready(0) ); \gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => w_issuing_cnt(0), O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ ); \gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_aw_n_16, D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\, Q => w_issuing_cnt(0), R => reset ); \gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_aw_n_16, D => addr_arbiter_aw_n_13, Q => w_issuing_cnt(1), R => reset ); \gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_aw_n_16, D => addr_arbiter_aw_n_12, Q => w_issuing_cnt(2), R => reset ); \gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_aw_n_16, D => addr_arbiter_aw_n_11, Q => w_issuing_cnt(3), R => reset ); \gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => r_issuing_cnt(8), O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ ); \gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_ar_n_85, D => addr_arbiter_ar_n_6, Q => r_issuing_cnt(10), R => reset ); \gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_ar_n_85, D => addr_arbiter_ar_n_5, Q => r_issuing_cnt(11), R => reset ); \gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_ar_n_85, D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\, Q => r_issuing_cnt(8), R => reset ); \gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_ar_n_85, D => addr_arbiter_ar_n_7, Q => r_issuing_cnt(9), R => reset ); \gen_master_slots[1].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 port map ( D(13 downto 2) => m_axi_bid(23 downto 12), D(1 downto 0) => m_axi_bresp(3 downto 2), Q(3 downto 0) => w_issuing_cnt(11 downto 8), aclk => aclk, aresetn => aresetn, \aresetn_d_reg[1]\ => \gen_master_slots[1].reg_slice_mi_n_76\, \aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_1\, \aresetn_d_reg[1]_1\ => \gen_master_slots[2].reg_slice_mi_n_5\, chosen(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 1), chosen_0(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 1), \gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].reg_slice_mi_n_75\, \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => r_issuing_cnt(11 downto 8), \gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_27\, \gen_multi_thread.accept_cnt_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_6\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_12\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6) => st_mr_bid(23), \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(5 downto 2) => st_mr_bid(21 downto 18), \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(1) => st_mr_bid(16), \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(0) => st_mr_bid(12), \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[1].reg_slice_mi_n_20\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[1].reg_slice_mi_n_21\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_master_slots[1].reg_slice_mi_n_22\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ => \gen_master_slots[1].reg_slice_mi_n_23\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 14) => st_mr_rid(23 downto 12), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13) => p_56_out, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12) => st_mr_rmesg(36), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11) => st_mr_rmesg(69), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10) => st_mr_rmesg(65), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9) => st_mr_rmesg(60), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8 downto 7) => st_mr_rmesg(58 downto 57), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6 downto 3) => st_mr_rmesg(49 downto 46), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2) => st_mr_rmesg(44), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1) => st_mr_rmesg(42), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => st_mr_rmesg(38), \gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_5\, \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_26\, m_axi_bready(0) => m_axi_bready(1), m_axi_bvalid(0) => m_axi_bvalid(1), m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32), m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12), m_axi_rlast(0) => m_axi_rlast(1), \m_axi_rready[1]\ => M_AXI_RREADY(1), m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2), m_axi_rvalid(0) => m_axi_rvalid(1), \m_payload_i_reg[12]\(9) => st_mr_bid(34), \m_payload_i_reg[12]\(8) => st_mr_bid(29), \m_payload_i_reg[12]\(7 downto 5) => st_mr_bid(27 downto 25), \m_payload_i_reg[12]\(4) => st_mr_bid(10), \m_payload_i_reg[12]\(3) => st_mr_bid(5), \m_payload_i_reg[12]\(2 downto 0) => st_mr_bid(3 downto 1), \m_payload_i_reg[1]\(1 downto 0) => st_mr_bmesg(1 downto 0), \m_payload_i_reg[32]\(20) => st_mr_rmesg(0), \m_payload_i_reg[32]\(19 downto 17) => st_mr_rmesg(33 downto 31), \m_payload_i_reg[32]\(16 downto 13) => st_mr_rmesg(29 downto 26), \m_payload_i_reg[32]\(12) => st_mr_rmesg(24), \m_payload_i_reg[32]\(11 downto 5) => st_mr_rmesg(21 downto 15), \m_payload_i_reg[32]\(4) => st_mr_rmesg(10), \m_payload_i_reg[32]\(3) => st_mr_rmesg(8), \m_payload_i_reg[32]\(2 downto 0) => st_mr_rmesg(6 downto 4), p_1_in => p_1_in, p_32_out => p_32_out, p_38_out => p_38_out, p_54_out => p_54_out, p_60_out => p_60_out, s_axi_bid(4) => s_axi_bid(10), s_axi_bid(3) => s_axi_bid(5), s_axi_bid(2 downto 0) => s_axi_bid(3 downto 1), s_axi_bready(0) => s_axi_bready(0), s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_rdata(19 downto 17) => s_axi_rdata(30 downto 28), s_axi_rdata(16 downto 13) => s_axi_rdata(26 downto 23), s_axi_rdata(12) => s_axi_rdata(21), s_axi_rdata(11 downto 5) => s_axi_rdata(18 downto 12), s_axi_rdata(4) => s_axi_rdata(7), s_axi_rdata(3) => s_axi_rdata(5), s_axi_rdata(2 downto 0) => s_axi_rdata(3 downto 1), s_axi_rready(0) => s_axi_rready(0), s_axi_rresp(0) => s_axi_rresp(0) ); \gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => w_issuing_cnt(8), O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ ); \gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_aw_n_15, D => addr_arbiter_aw_n_8, Q => w_issuing_cnt(10), R => reset ); \gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_aw_n_15, D => addr_arbiter_aw_n_7, Q => w_issuing_cnt(11), R => reset ); \gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_aw_n_15, D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\, Q => w_issuing_cnt(8), R => reset ); \gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => addr_arbiter_aw_n_15, D => addr_arbiter_aw_n_9, Q => w_issuing_cnt(9), R => reset ); \gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_master_slots[2].reg_slice_mi_n_45\, Q => r_issuing_cnt(16), R => reset ); \gen_master_slots[2].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 port map ( D(11 downto 0) => p_24_in(11 downto 0), E(0) => \r_pipe/p_1_in\, Q(4) => st_mr_bid(34), Q(3) => st_mr_bid(29), Q(2 downto 0) => st_mr_bid(27 downto 25), S(0) => \gen_master_slots[2].reg_slice_mi_n_20\, aclk => aclk, \aresetn_d_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_76\, chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2), chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2), \gen_axi.s_axi_arready_i_reg\ => addr_arbiter_ar_n_80, \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_20_in(11 downto 0), \gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\, \gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_26\, \gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_45\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_master_slots[2].reg_slice_mi_n_19\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[2].reg_slice_mi_n_28\, \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[2].reg_slice_mi_n_29\, \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_master_slots[2].reg_slice_mi_n_21\, \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_master_slots[2].reg_slice_mi_n_22\, \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_master_slots[2].reg_slice_mi_n_23\, \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_master_slots[2].reg_slice_mi_n_24\, \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_master_slots[2].reg_slice_mi_n_25\, \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_master_slots[2].reg_slice_mi_n_26\, \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_master_slots[2].reg_slice_mi_n_27\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 1) => st_mr_rid(35 downto 24), \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => p_34_out, \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6), \gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_30\, \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_31\, \m_payload_i_reg[13]\(13) => st_mr_bid(23), \m_payload_i_reg[13]\(12 downto 9) => st_mr_bid(21 downto 18), \m_payload_i_reg[13]\(8) => st_mr_bid(16), \m_payload_i_reg[13]\(7 downto 6) => st_mr_bid(12 downto 11), \m_payload_i_reg[13]\(5 downto 2) => st_mr_bid(9 downto 6), \m_payload_i_reg[13]\(1) => st_mr_bid(4), \m_payload_i_reg[13]\(0) => st_mr_bid(0), m_valid_i_reg => \gen_master_slots[2].reg_slice_mi_n_1\, m_valid_i_reg_0 => \gen_master_slots[1].reg_slice_mi_n_6\, mi_bready_2 => mi_bready_2, mi_rready_2 => mi_rready_2, p_15_in => p_15_in, p_17_in => p_17_in, p_1_in => p_1_in, p_21_in => p_21_in, p_32_out => p_32_out, p_38_out => p_38_out, r_issuing_cnt(0) => r_issuing_cnt(16), s_axi_bid(6) => s_axi_bid(11), s_axi_bid(5 downto 2) => s_axi_bid(9 downto 6), s_axi_bid(1) => s_axi_bid(4), s_axi_bid(0) => s_axi_bid(0), s_axi_bready(0) => s_axi_bready(0), s_axi_rready(0) => s_axi_rready(0), s_ready_i_reg => \gen_master_slots[2].reg_slice_mi_n_5\, st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0), w_issuing_cnt(0) => w_issuing_cnt(16) ); \gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\, Q => w_issuing_cnt(16), R => reset ); \gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor port map ( E(0) => \r_pipe/p_1_in_0\, SR(0) => reset, aclk => aclk, aresetn_d => aresetn_d, chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 0), \gen_multi_thread.accept_cnt_reg[2]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\, \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\, \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\, \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\, \gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\, \gen_no_arbiter.m_target_hot_i_reg[2]_0\(0) => aa_mi_artarget_hot(2), \gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_ar_n_81, \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\, \gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\, \gen_no_arbiter.s_ready_i_reg[0]_1\ => \^s_axi_arready\(0), \m_payload_i_reg[34]\(0) => \r_pipe/p_1_in\, \m_payload_i_reg[46]\(25 downto 14) => st_mr_rid(11 downto 0), \m_payload_i_reg[46]\(13) => p_76_out, \m_payload_i_reg[46]\(12) => st_mr_rmesg(1), \m_payload_i_reg[46]\(11) => st_mr_rmesg(34), \m_payload_i_reg[46]\(10) => st_mr_rmesg(30), \m_payload_i_reg[46]\(9) => st_mr_rmesg(25), \m_payload_i_reg[46]\(8 downto 7) => st_mr_rmesg(23 downto 22), \m_payload_i_reg[46]\(6 downto 3) => st_mr_rmesg(14 downto 11), \m_payload_i_reg[46]\(2) => st_mr_rmesg(9), \m_payload_i_reg[46]\(1) => st_mr_rmesg(7), \m_payload_i_reg[46]\(0) => st_mr_rmesg(3), \m_payload_i_reg[46]_0\(25 downto 14) => st_mr_rid(23 downto 12), \m_payload_i_reg[46]_0\(13) => p_56_out, \m_payload_i_reg[46]_0\(12) => st_mr_rmesg(36), \m_payload_i_reg[46]_0\(11) => st_mr_rmesg(69), \m_payload_i_reg[46]_0\(10) => st_mr_rmesg(65), \m_payload_i_reg[46]_0\(9) => st_mr_rmesg(60), \m_payload_i_reg[46]_0\(8 downto 7) => st_mr_rmesg(58 downto 57), \m_payload_i_reg[46]_0\(6 downto 3) => st_mr_rmesg(49 downto 46), \m_payload_i_reg[46]_0\(2) => st_mr_rmesg(44), \m_payload_i_reg[46]_0\(1) => st_mr_rmesg(42), \m_payload_i_reg[46]_0\(0) => st_mr_rmesg(38), \m_payload_i_reg[46]_1\(12 downto 1) => st_mr_rid(35 downto 24), \m_payload_i_reg[46]_1\(0) => p_34_out, m_valid_i => m_valid_i, p_32_out => p_32_out, p_54_out => p_54_out, p_74_out => p_74_out, \s_axi_araddr[25]\(0) => st_aa_artarget_hot(0), \s_axi_araddr[25]_0\ => addr_arbiter_ar_n_82, \s_axi_araddr[31]\(27 downto 12) => \s_axi_arqos[3]\(31 downto 16), \s_axi_araddr[31]\(11 downto 0) => s_axi_arid(11 downto 0), s_axi_rdata(11) => s_axi_rdata(31), s_axi_rdata(10) => s_axi_rdata(27), s_axi_rdata(9) => s_axi_rdata(22), s_axi_rdata(8 downto 7) => s_axi_rdata(20 downto 19), s_axi_rdata(6 downto 3) => s_axi_rdata(11 downto 8), s_axi_rdata(2) => s_axi_rdata(6), s_axi_rdata(1) => s_axi_rdata(4), s_axi_rdata(0) => s_axi_rdata(0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast(0) => s_axi_rlast(0), s_axi_rready(0) => s_axi_rready(0), s_axi_rresp(0) => s_axi_rresp(1), s_axi_rvalid(0) => s_axi_rvalid(0), st_aa_artarget_hot(0) => st_aa_artarget_hot(1) ); \gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ port map ( D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\, Q(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6), S(0) => \gen_master_slots[2].reg_slice_mi_n_20\, SR(0) => reset, aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2), aa_sa_awvalid => aa_sa_awvalid, aclk => aclk, aresetn_d => aresetn_d, chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 0), \gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\, \gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].reg_slice_mi_n_5\, \gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\, \gen_master_slots[2].w_issuing_cnt_reg[16]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\, \gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].reg_slice_mi_n_30\, \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_21\, \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_22\, \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_23\, \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_24\, \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_25\, \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_26\, \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6), \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_27\, \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\, \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\, \gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\, \gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\, \gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_20, \m_payload_i_reg[11]\ => \gen_master_slots[2].reg_slice_mi_n_28\, \m_payload_i_reg[12]\ => \gen_master_slots[1].reg_slice_mi_n_23\, \m_payload_i_reg[13]\ => \gen_master_slots[2].reg_slice_mi_n_29\, \m_payload_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\, \m_payload_i_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_12\, \m_payload_i_reg[4]\ => \gen_master_slots[1].reg_slice_mi_n_20\, \m_payload_i_reg[5]\ => \gen_master_slots[1].reg_slice_mi_n_21\, \m_payload_i_reg[6]\ => \gen_master_slots[2].reg_slice_mi_n_19\, \m_payload_i_reg[7]\ => \gen_master_slots[1].reg_slice_mi_n_22\, \m_ready_d_reg[1]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\, \m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_14, m_valid_i => m_valid_i_2, m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\, p_38_out => p_38_out, p_60_out => p_60_out, p_80_out => p_80_out, \s_axi_awaddr[31]\(27 downto 12) => D(31 downto 16), \s_axi_awaddr[31]\(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awvalid(0) => s_axi_awvalid(0), s_axi_bready(0) => s_axi_bready(0), s_axi_bvalid(0) => s_axi_bvalid(0), st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0), st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0), w_issuing_cnt(4) => w_issuing_cnt(16), w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0) ); \gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter port map ( aclk => aclk, aresetn_d => aresetn_d, \gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\, m_ready_d(1 downto 0) => m_ready_d(1 downto 0), s_axi_awready(0) => s_axi_awready(0), s_axi_awvalid(0) => s_axi_awvalid(0), ss_aa_awready => ss_aa_awready, ss_wr_awready => ss_wr_awready, ss_wr_awvalid => ss_wr_awvalid ); \gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router port map ( D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\, SR(0) => reset, aclk => aclk, \gen_axi.write_cs_reg[1]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\, \gen_axi.write_cs_reg[1]_0\(0) => write_cs(1), m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0), m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0), m_ready_d(0) => m_ready_d(1), p_14_in => p_14_in, s_axi_awvalid(0) => s_axi_awvalid(0), s_axi_wlast(0) => s_axi_wlast(0), s_axi_wready(0) => s_axi_wready(0), s_axi_wvalid(0) => s_axi_wvalid(0), ss_wr_awready => ss_wr_awready, ss_wr_awvalid => ss_wr_awvalid, st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0), st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0) ); splitter_aw_mi: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_3 port map ( aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0), aa_sa_awvalid => aa_sa_awvalid, aclk => aclk, aresetn_d => aresetn_d, \gen_no_arbiter.m_target_hot_i_reg[1]\ => addr_arbiter_aw_n_3, m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0), \m_ready_d_reg[0]_0\ => addr_arbiter_aw_n_21, \m_ready_d_reg[0]_1\ => addr_arbiter_aw_n_2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_wid : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_wuser : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_ruser : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12; attribute C_AXI_PROTOCOL : integer; attribute C_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute C_CONNECTIVITY_MODE : integer; attribute C_CONNECTIVITY_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute C_DEBUG : integer; attribute C_DEBUG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq"; attribute C_M_AXI_ADDR_WIDTH : string; attribute C_M_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000001000000000000000000000000000000010000"; attribute C_M_AXI_BASE_ADDR : string; attribute C_M_AXI_BASE_ADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000"; attribute C_M_AXI_READ_CONNECTIVITY : string; attribute C_M_AXI_READ_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111"; attribute C_M_AXI_READ_ISSUING : string; attribute C_M_AXI_READ_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000"; attribute C_M_AXI_SECURE : string; attribute C_M_AXI_SECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000"; attribute C_M_AXI_WRITE_CONNECTIVITY : string; attribute C_M_AXI_WRITE_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111"; attribute C_M_AXI_WRITE_ISSUING : string; attribute C_M_AXI_WRITE_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000"; attribute C_NUM_ADDR_RANGES : integer; attribute C_NUM_ADDR_RANGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute C_NUM_MASTER_SLOTS : integer; attribute C_NUM_MASTER_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 2; attribute C_NUM_SLAVE_SLOTS : integer; attribute C_NUM_SLAVE_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute C_R_REGISTER : integer; attribute C_R_REGISTER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0; attribute C_S_AXI_ARB_PRIORITY : integer; attribute C_S_AXI_ARB_PRIORITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0; attribute C_S_AXI_BASE_ID : integer; attribute C_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0; attribute C_S_AXI_READ_ACCEPTANCE : integer; attribute C_S_AXI_READ_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8; attribute C_S_AXI_SINGLE_THREAD : integer; attribute C_S_AXI_SINGLE_THREAD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0; attribute C_S_AXI_THREAD_ID_WIDTH : integer; attribute C_S_AXI_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12; attribute C_S_AXI_WRITE_ACCEPTANCE : integer; attribute C_S_AXI_WRITE_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes"; attribute P_ADDR_DECODE : integer; attribute P_ADDR_DECODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute P_AXI3 : integer; attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute P_AXI4 : integer; attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0; attribute P_AXILITE : integer; attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010"; attribute P_FAMILY : string; attribute P_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq"; attribute P_INCR : string; attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01"; attribute P_LEN : integer; attribute P_LEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8; attribute P_LOCK : integer; attribute P_LOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute P_M_AXI_ERR_MODE : string; attribute P_M_AXI_ERR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000"; attribute P_M_AXI_SUPPORTS_READ : string; attribute P_M_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11"; attribute P_M_AXI_SUPPORTS_WRITE : string; attribute P_M_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11"; attribute P_ONES : string; attribute P_ONES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111"; attribute P_RANGE_CHECK : integer; attribute P_RANGE_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1; attribute P_S_AXI_BASE_ID : string; attribute P_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000"; attribute P_S_AXI_HIGH_ID : string; attribute P_S_AXI_HIGH_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111"; attribute P_S_AXI_SUPPORTS_READ : string; attribute P_S_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1"; attribute P_S_AXI_SUPPORTS_WRITE : string; attribute P_S_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is signal \<const0>\ : STD_LOGIC; signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 63 downto 32 ); signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 7 downto 4 ); signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 1 to 1 ); signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 5 downto 3 ); signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 7 downto 4 ); signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 5 downto 3 ); signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 63 downto 32 ); signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 7 downto 4 ); signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 1 to 1 ); signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 5 downto 3 ); signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 7 downto 4 ); signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 5 downto 3 ); signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wlast\(0) <= s_axi_wlast(0); \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(63 downto 32); m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(63 downto 32); m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(3 downto 2); m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(3 downto 2); m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(7 downto 4); m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(7 downto 4); m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0); m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0); m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0); m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0); m_axi_arlock(1) <= \^m_axi_arlock\(1); m_axi_arlock(0) <= \^m_axi_arlock\(1); m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(5 downto 3); m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(5 downto 3); m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(7 downto 4); m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(7 downto 4); m_axi_arregion(7) <= \<const0>\; m_axi_arregion(6) <= \<const0>\; m_axi_arregion(5) <= \<const0>\; m_axi_arregion(4) <= \<const0>\; m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(5 downto 3); m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(5 downto 3); m_axi_aruser(1) <= \<const0>\; m_axi_aruser(0) <= \<const0>\; m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(63 downto 32); m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(63 downto 32); m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(3 downto 2); m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(3 downto 2); m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(7 downto 4); m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(7 downto 4); m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0); m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0); m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(15 downto 8); m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(15 downto 8); m_axi_awlock(1) <= \^m_axi_awlock\(1); m_axi_awlock(0) <= \^m_axi_awlock\(1); m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(5 downto 3); m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(5 downto 3); m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(7 downto 4); m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(7 downto 4); m_axi_awregion(7) <= \<const0>\; m_axi_awregion(6) <= \<const0>\; m_axi_awregion(5) <= \<const0>\; m_axi_awregion(4) <= \<const0>\; m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(5 downto 3); m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(5 downto 3); m_axi_awuser(1) <= \<const0>\; m_axi_awuser(0) <= \<const0>\; m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0); m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); m_axi_wid(23) <= \<const0>\; m_axi_wid(22) <= \<const0>\; m_axi_wid(21) <= \<const0>\; m_axi_wid(20) <= \<const0>\; m_axi_wid(19) <= \<const0>\; m_axi_wid(18) <= \<const0>\; m_axi_wid(17) <= \<const0>\; m_axi_wid(16) <= \<const0>\; m_axi_wid(15) <= \<const0>\; m_axi_wid(14) <= \<const0>\; m_axi_wid(13) <= \<const0>\; m_axi_wid(12) <= \<const0>\; m_axi_wid(11) <= \<const0>\; m_axi_wid(10) <= \<const0>\; m_axi_wid(9) <= \<const0>\; m_axi_wid(8) <= \<const0>\; m_axi_wid(7) <= \<const0>\; m_axi_wid(6) <= \<const0>\; m_axi_wid(5) <= \<const0>\; m_axi_wid(4) <= \<const0>\; m_axi_wid(3) <= \<const0>\; m_axi_wid(2) <= \<const0>\; m_axi_wid(1) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast(1) <= \^s_axi_wlast\(0); m_axi_wlast(0) <= \^s_axi_wlast\(0); m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0); m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); m_axi_wuser(1) <= \<const0>\; m_axi_wuser(0) <= \<const0>\; s_axi_buser(0) <= \<const0>\; s_axi_ruser(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \gen_samd.crossbar_samd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar port map ( D(56 downto 53) => s_axi_awqos(3 downto 0), D(52 downto 49) => s_axi_awcache(3 downto 0), D(48 downto 47) => s_axi_awburst(1 downto 0), D(46 downto 44) => s_axi_awprot(2 downto 0), D(43) => s_axi_awlock(0), D(42 downto 40) => s_axi_awsize(2 downto 0), D(39 downto 32) => s_axi_awlen(7 downto 0), D(31 downto 0) => s_axi_awaddr(31 downto 0), M_AXI_RREADY(1 downto 0) => m_axi_rready(1 downto 0), Q(68 downto 65) => \^m_axi_awqos\(7 downto 4), Q(64 downto 61) => \^m_axi_awcache\(7 downto 4), Q(60 downto 59) => \^m_axi_awburst\(3 downto 2), Q(58 downto 56) => \^m_axi_awprot\(5 downto 3), Q(55) => \^m_axi_awlock\(1), Q(54 downto 52) => \^m_axi_awsize\(5 downto 3), Q(51 downto 44) => \^m_axi_awlen\(15 downto 8), Q(43 downto 12) => \^m_axi_awaddr\(63 downto 32), Q(11 downto 0) => \^m_axi_awid\(11 downto 0), S_AXI_ARREADY(0) => s_axi_arready(0), aclk => aclk, aresetn => aresetn, \m_axi_arqos[7]\(68 downto 65) => \^m_axi_arqos\(7 downto 4), \m_axi_arqos[7]\(64 downto 61) => \^m_axi_arcache\(7 downto 4), \m_axi_arqos[7]\(60 downto 59) => \^m_axi_arburst\(3 downto 2), \m_axi_arqos[7]\(58 downto 56) => \^m_axi_arprot\(5 downto 3), \m_axi_arqos[7]\(55) => \^m_axi_arlock\(1), \m_axi_arqos[7]\(54 downto 52) => \^m_axi_arsize\(5 downto 3), \m_axi_arqos[7]\(51 downto 44) => \^m_axi_arlen\(7 downto 0), \m_axi_arqos[7]\(43 downto 12) => \^m_axi_araddr\(63 downto 32), \m_axi_arqos[7]\(11 downto 0) => \^m_axi_arid\(11 downto 0), m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0), m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0), m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0), m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0), m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0), m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0), m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0), m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0), m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0), m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0), m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0), m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0), m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0), m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0), m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), \s_axi_arqos[3]\(56 downto 53) => s_axi_arqos(3 downto 0), \s_axi_arqos[3]\(52 downto 49) => s_axi_arcache(3 downto 0), \s_axi_arqos[3]\(48 downto 47) => s_axi_arburst(1 downto 0), \s_axi_arqos[3]\(46 downto 44) => s_axi_arprot(2 downto 0), \s_axi_arqos[3]\(43) => s_axi_arlock(0), \s_axi_arqos[3]\(42 downto 40) => s_axi_arsize(2 downto 0), \s_axi_arqos[3]\(39 downto 32) => s_axi_arlen(7 downto 0), \s_axi_arqos[3]\(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arvalid(0) => s_axi_arvalid(0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awready(0) => s_axi_awready(0), s_axi_awvalid(0) => s_axi_awvalid(0), s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready(0) => s_axi_bready(0), s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bvalid(0) => s_axi_bvalid(0), s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast(0) => s_axi_rlast(0), s_axi_rready(0) => s_axi_rready(0), s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_rvalid(0) => s_axi_rvalid(0), s_axi_wlast(0) => \^s_axi_wlast\(0), s_axi_wready(0) => s_axi_wready(0), s_axi_wvalid(0) => s_axi_wvalid(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of inst : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of inst : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of inst : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 12; attribute C_AXI_PROTOCOL : integer; attribute C_AXI_PROTOCOL of inst : label is 0; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of inst : label is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_CONNECTIVITY_MODE : integer; attribute C_CONNECTIVITY_MODE of inst : label is 1; attribute C_DEBUG : integer; attribute C_DEBUG of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_M_AXI_ADDR_WIDTH : string; attribute C_M_AXI_ADDR_WIDTH of inst : label is "64'b0000000000000000000000000001000000000000000000000000000000010000"; attribute C_M_AXI_BASE_ADDR : string; attribute C_M_AXI_BASE_ADDR of inst : label is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000"; attribute C_M_AXI_READ_CONNECTIVITY : string; attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111"; attribute C_M_AXI_READ_ISSUING : string; attribute C_M_AXI_READ_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000"; attribute C_M_AXI_SECURE : string; attribute C_M_AXI_SECURE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000"; attribute C_M_AXI_WRITE_CONNECTIVITY : string; attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111"; attribute C_M_AXI_WRITE_ISSUING : string; attribute C_M_AXI_WRITE_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000"; attribute C_NUM_ADDR_RANGES : integer; attribute C_NUM_ADDR_RANGES of inst : label is 1; attribute C_NUM_MASTER_SLOTS : integer; attribute C_NUM_MASTER_SLOTS of inst : label is 2; attribute C_NUM_SLAVE_SLOTS : integer; attribute C_NUM_SLAVE_SLOTS of inst : label is 1; attribute C_R_REGISTER : integer; attribute C_R_REGISTER of inst : label is 0; attribute C_S_AXI_ARB_PRIORITY : integer; attribute C_S_AXI_ARB_PRIORITY of inst : label is 0; attribute C_S_AXI_BASE_ID : integer; attribute C_S_AXI_BASE_ID of inst : label is 0; attribute C_S_AXI_READ_ACCEPTANCE : integer; attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8; attribute C_S_AXI_SINGLE_THREAD : integer; attribute C_S_AXI_SINGLE_THREAD of inst : label is 0; attribute C_S_AXI_THREAD_ID_WIDTH : integer; attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12; attribute C_S_AXI_WRITE_ACCEPTANCE : integer; attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_ADDR_DECODE : integer; attribute P_ADDR_DECODE of inst : label is 1; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; attribute P_AXI4 of inst : label is 0; attribute P_AXILITE : integer; attribute P_AXILITE of inst : label is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of inst : label is "3'b010"; attribute P_FAMILY : string; attribute P_FAMILY of inst : label is "zynq"; attribute P_INCR : string; attribute P_INCR of inst : label is "2'b01"; attribute P_LEN : integer; attribute P_LEN of inst : label is 8; attribute P_LOCK : integer; attribute P_LOCK of inst : label is 1; attribute P_M_AXI_ERR_MODE : string; attribute P_M_AXI_ERR_MODE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000"; attribute P_M_AXI_SUPPORTS_READ : string; attribute P_M_AXI_SUPPORTS_READ of inst : label is "2'b11"; attribute P_M_AXI_SUPPORTS_WRITE : string; attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "2'b11"; attribute P_ONES : string; attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111"; attribute P_RANGE_CHECK : integer; attribute P_RANGE_CHECK of inst : label is 1; attribute P_S_AXI_BASE_ID : string; attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000"; attribute P_S_AXI_HIGH_ID : string; attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111"; attribute P_S_AXI_SUPPORTS_READ : string; attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1"; attribute P_S_AXI_SUPPORTS_WRITE : string; attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar port map ( aclk => aclk, aresetn => aresetn, m_axi_araddr(63 downto 0) => m_axi_araddr(63 downto 0), m_axi_arburst(3 downto 0) => m_axi_arburst(3 downto 0), m_axi_arcache(7 downto 0) => m_axi_arcache(7 downto 0), m_axi_arid(23 downto 0) => m_axi_arid(23 downto 0), m_axi_arlen(15 downto 0) => m_axi_arlen(15 downto 0), m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0), m_axi_arprot(5 downto 0) => m_axi_arprot(5 downto 0), m_axi_arqos(7 downto 0) => m_axi_arqos(7 downto 0), m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0), m_axi_arregion(7 downto 0) => m_axi_arregion(7 downto 0), m_axi_arsize(5 downto 0) => m_axi_arsize(5 downto 0), m_axi_aruser(1 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(1 downto 0), m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0), m_axi_awaddr(63 downto 0) => m_axi_awaddr(63 downto 0), m_axi_awburst(3 downto 0) => m_axi_awburst(3 downto 0), m_axi_awcache(7 downto 0) => m_axi_awcache(7 downto 0), m_axi_awid(23 downto 0) => m_axi_awid(23 downto 0), m_axi_awlen(15 downto 0) => m_axi_awlen(15 downto 0), m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0), m_axi_awprot(5 downto 0) => m_axi_awprot(5 downto 0), m_axi_awqos(7 downto 0) => m_axi_awqos(7 downto 0), m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0), m_axi_awregion(7 downto 0) => m_axi_awregion(7 downto 0), m_axi_awsize(5 downto 0) => m_axi_awsize(5 downto 0), m_axi_awuser(1 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(1 downto 0), m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0), m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0), m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0), m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0), m_axi_buser(1 downto 0) => B"00", m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0), m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0), m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0), m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0), m_axi_rready(1 downto 0) => m_axi_rready(1 downto 0), m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0), m_axi_ruser(1 downto 0) => B"00", m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0), m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0), m_axi_wid(23 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(23 downto 0), m_axi_wlast(1 downto 0) => m_axi_wlast(1 downto 0), m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0), m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0), m_axi_wuser(1 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1 downto 0), m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arlock(0) => s_axi_arlock(0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready(0) => s_axi_arready(0), s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid(0) => s_axi_arvalid(0), s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), s_axi_awlock(0) => s_axi_awlock(0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), s_axi_awready(0) => s_axi_awready(0), s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', s_axi_awvalid(0) => s_axi_awvalid(0), s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready(0) => s_axi_bready(0), s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), s_axi_bvalid(0) => s_axi_bvalid(0), s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast(0) => s_axi_rlast(0), s_axi_rready(0) => s_axi_rready(0), s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid(0) => s_axi_rvalid(0), s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wid(11 downto 0) => B"000000000000", s_axi_wlast(0) => s_axi_wlast(0), s_axi_wready(0) => s_axi_wready(0), s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wuser(0) => '0', s_axi_wvalid(0) => s_axi_wvalid(0) ); end STRUCTURE;

mit

2991a55964944d7c45fefed1654f01b3

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/gaisler/sim/pwm_check.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- -- Entity: pwm_check -- File: pwm_check.vhd -- Author: Jonas Ekergarn - Aeroflex Gaisler (parts are copied from -- grtestmod.vhd) -- Description: Simulation unit that examines the PWMs generated by the GRPWM -- when software/leon3/grpwm.c is run. Note that pwm_check -- requires that the system includes an I/O memory interface -- and that grtestmod.vhd is instantiated in the system testbench. -- If the subtests in software/leon3/grpwm.c is modified then the -- configuration below and the procedure verify_subtest must be -- changed as well. ------------------------------------------------------------------------------- -- pragma translate_off library ieee, grlib, gaisler; use ieee.std_logic_1164.all; use std.textio.all; use grlib.stdlib.all; use grlib.stdio.all; use grlib.devices.all; use gaisler.sim.all; entity pwm_check is port ( clk : in std_ulogic; address : in std_logic_vector(21 downto 2); data : inout std_logic_vector(31 downto 0); iosn : in std_ulogic; oen : in std_ulogic; writen : in std_ulogic; pwm : in std_logic_vector(15 downto 0) ); end; architecture sim of pwm_check is signal ior, iow : std_ulogic; signal addr : std_logic_vector(21 downto 2); signal ldata : std_logic_vector(31 downto 0); signal pwmh : std_logic_vector(1 downto 0); signal pwmh0 : integer := 0; signal pwmh1 : integer := 1; ----------------------------------------------------------------------------- -- Configuration of the PWMs that should be verified ----------------------------------------------------------------------------- -- Number of "useful" words in the waveform ram. The core will read address -- 0 - (STX_WRAMSIZE-1). constant ST3_WRAMSIZE : integer := 32; constant ST4_WRAMSIZE : integer := 32; -- Number of periods to verify for each subtest. Verification of the very -- first period after PWM is started is skipped because there is no way of -- knowing exactly when it starts. It is assumed that the first period is -- correct. If it isn't then the verification of the other periods will fail -- as well. constant ST1_NPER : integer := 10; constant ST2_NPER : integer := 10; constant ST3_NPER : integer := 2*ST3_WRAMSIZE; constant ST4_NPER : integer := 2*ST4_WRAMSIZE; type st1_vector is array (0 to ST1_NPER) of integer; type st2_vector is array (0 to ST2_NPER) of integer; type st3_vector is array (0 to ST3_NPER) of integer; type st4_vector is array (0 to ST4_NPER) of integer; type st1_array is array (0 to 7) of st1_vector; type st2_array is array (0 to 7) of st2_vector; type st3_array is array (0 to 7) of st3_vector; type st4_array is array (0 to 7) of st4_vector; type wram_type is array (0 to 8191) of integer; -- Polarity for each PWM in the different subtests constant ST1_POL : std_logic_vector(7 downto 0) := (others=>'1'); constant ST2_POL : std_logic_vector(7 downto 0) := (others=>'1'); constant ST3_POL : std_logic_vector(7 downto 0) := (others=>'1'); constant ST4_POL : std_logic_vector(7 downto 0) := (others=>'1'); -- Period, compare, and dead band values for each pwm period in subtest 1, -- in clock cycles constant ST1_PER : st1_array := ( 0 => (others=>200), 1 => (others=>201), 2 => (others=>202), 3 => (others=>203), 4 => (others=>204), 5 => (others=>205), 6 => (others=>206), 7 => (others=>207)); constant ST1_COMPA : st1_array := ( 0 => (others=>100), 1 => (others=>101), 2 => (others=>102), 3 => (others=>103), 4 => (others=>104), 5 => (others=>105), 6 => (others=>106), 7 => (others=>107)); constant ST1_DB : st1_array := ( 0 => (others=>10), 1 => (others=>11), 2 => (others=>12), 3 => (others=>13), 4 => (others=>14), 5 => (others=>15), 6 => (others=>16), 7 => (others=>17)); -- Period, compare, and dead band values for each pwm period in subtest 2, -- in clock cycles constant ST2_PER : st2_array := ( 0 => (others=>200), 1 => (others=>202), 2 => (others=>204), 3 => (others=>206), 4 => (others=>208), 5 => (others=>210), 6 => (others=>212), 7 => (others=>214)); constant ST2_COMPA : st2_array := ( 0 => (others=>50), 1 => (others=>51), 2 => (others=>52), 3 => (others=>53), 4 => (others=>54), 5 => (others=>55), 6 => (others=>56), 7 => (others=>57)); constant ST2_DB : st2_array := ( 0 => (others=>10), 1 => (others=>11), 2 => (others=>12), 3 => (others=>13), 4 => (others=>14), 5 => (others=>15), 6 => (others=>16), 7 => (others=>17)); -- Period, compare, and dead band values for each pwm period in subtest 3, -- in clock cycles. (Only the PWM with the highest index is active during -- subtest 3, but since we here don't know how many PWM outputs there are, -- all get the same value) constant ST3_WRAM : wram_type := ( 32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55, 56,57,58,59,60,61,62,63, others=>0); constant ST3_PER : st3_array := ( 0 => (others=>200), 1 => (others=>200), 2 => (others=>200), 3 => (others=>200), 4 => (others=>200), 5 => (others=>200), 6 => (others=>200), 7 => (others=>200)); constant ST3_DB : st3_array := ( 0 => (others=>10), 1 => (others=>10), 2 => (others=>10), 3 => (others=>10), 4 => (others=>10), 5 => (others=>10), 6 => (others=>10), 7 => (others=>10)); -- Period, compare, and dead band values for each pwm period in subtest 4, -- in clock cycles. (Only the PWM with the highest index is active during -- subtest 4, but since we here don't know how many PWM outputs there are, -- all get the same value) constant ST4_WRAM : wram_type := ( 32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55, 56,57,58,59,60,61,62,63, others=>0); constant ST4_PER : st4_array := ( 0 => (others=>200), 1 => (others=>200), 2 => (others=>200), 3 => (others=>200), 4 => (others=>200), 5 => (others=>200), 6 => (others=>200), 7 => (others=>200)); constant ST4_DB : st4_array := ( 0 => (others=>10), 1 => (others=>10), 2 => (others=>10), 3 => (others=>10), 4 => (others=>10), 5 => (others=>10), 6 => (others=>10), 7 => (others=>10)); type pwm_int_array is array (0 to 7) of integer; type pwm_bool_array is array (0 to 7) of boolean; procedure verify_subtest ( constant subtest : in integer; constant npwm : in integer range 1 to 8; signal clk : in std_ulogic; signal pwm : in std_logic_vector(15 downto 0); signal pwmh : in std_logic_vector(1 downto 0)) is variable cnt : pwm_int_array := (others=>0); variable cnt2 : pwm_int_array := (others=>0); variable pcnt : pwm_int_array := (others=>0); variable parta : pwm_bool_array := (others=>false); variable partb : pwm_bool_array := (others=>false); variable partc : pwm_bool_array := (others=>false); variable partd : pwm_bool_array := (others=>false); variable done : pwm_bool_array := (others=>false); variable ST2_COMPB : st2_array; variable ST4_COMPB : st4_array; variable addr : integer; variable il, ih : integer; begin case subtest is when 1 => ------------------------------------------------------------------------- -- Subtest 1: npwm assymmetric PWM pairs are generated, all with -- different periods, compare values, and dead band values. Verify -- periods, compare matches, and dead band times. ------------------------------------------------------------------------- for i in 0 to 7 loop if npwm < i+1 then done(i) := true; end if; -- no dead band time is inserted in the very first pwm period after -- startup parta(i) := true; end loop; while not(done(0) and done(1) and done(2) and done(3) and done(4) and done(5) and done(6) and done(7)) loop wait until rising_edge(clk); for i in 0 to npwm-1 loop cnt(i) := cnt(i)+1; end loop; wait until (pwm'event or falling_edge(clk)); if clk = '1' then for i in 0 to npwm-1 loop if (not done(i)) then if (not parta(i)) then -- pwm is in time period between period start and when paired -- output goes active (after dead band time) if pwm(2*i+1) = ST1_POL(i) then parta(i) := true; if pcnt(i) /= 0 then if cnt(i) /= ST1_DB(i)(pcnt(i)) then Print("ERROR: Wrong dead band (1) detected for pwm " & tost(i+1) & " in period = " & tost(pcnt(i)) & ". Is " & tost(cnt(i)) & ", should be " & tost(ST1_DB(i)(pcnt(i)))); end if; end if; end if; elsif (not partb(i)) then -- pwm is in time period between paired output going active and -- paired output going inactive if pwm(2*i+1) = (not ST1_POL(i)) then partb(i) := true; if pcnt(i) /= 0 then if cnt(i) /= ST1_COMPA(i)(pcnt(i)) then Print("ERROR: Wrong compare match detected for pwm " & tost(i+1) & " in period = " & tost(pcnt(i)) & ". Is " & tost(cnt(i)) & ", should be " & tost(ST1_COMPA(i)(pcnt(i)))); end if; if ST1_DB(i)(pcnt(i)) = 0 then partc(i) := true; if pwm(2*i) /= ST1_POL(i) then Print("ERROR: Both outputs did not switch simultaneously" & " even though dead band time was zero"); end if; end if; end if; end if; elsif (not partc(i)) then -- pwm is in time period between paired output going inactive and -- output going active (after dead band time) if pwm(2*i) = ST1_POL(i) then partc(i) := true; if pcnt(i) /= 0 then if cnt(i) /= (ST1_COMPA(i)(pcnt(i)) + ST1_DB(i)(pcnt(i))) then Print("ERROR: Wrong dead band (2) time detected for pwm " & tost(i+1) & " in period = " & tost(pcnt(i)) & ". Is " & tost(cnt(i)-ST1_COMPA(i)(pcnt(i))) & ", should be " & tost(ST1_DB(i)(pcnt(i)))); end if; end if; end if; else -- pwm is in time period between output going active and period end -- (output going inactive) if pwm(2*i) = (not ST1_POL(i)) then parta(i) := false; partb(i) := false; partc(i) := false; if pcnt(i) /= 0 then if cnt(i) /= ST1_PER(i)(pcnt(i)) then Print("ERROR: Wrong PWM period detected for pwm " & tost(i+1) & " in period = " & tost(pcnt(i)) & ". Is " & tost(cnt(i)) & ", should be " & tost(ST1_PER(i)(pcnt(i)))); end if; end if; if pcnt(i) = ST1_NPER then done(i) := true; end if; pcnt(i) := pcnt(i)+1; cnt(i) := 0; if pcnt(i) < ST1_NPER then if ST1_DB(i)(pcnt(i)) = 0 then parta(i) := true; if pwm(2*i+1) /= ST1_POL(i) then Print("ERROR: Both outputs did not switch simultaneously" & " even though dead band time was zero"); end if; end if; end if; end if; end if; end if; end loop; end if; end loop; when 2 => ------------------------------------------------------------------------- -- Subtest 2: npwm symmetric PWM pairs are generated, all with -- different periods, compare values, and dead band values. Verify -- periods, compare matches, and dead band times ------------------------------------------------------------------------- for i in 0 to 7 loop for j in 0 to ST2_NPER loop ST2_COMPB(i)(j) := ST2_PER(i)(j)-ST2_COMPA(i)(j); end loop; if npwm < i+1 then done(i) := true; end if; end loop; while not(done(0) and done(1) and done(2) and done(3) and done(4) and done(5) and done(6) and done(7)) loop wait until rising_edge(clk); for i in 0 to npwm-1 loop cnt(i) := cnt(i)+1; cnt2(i) := cnt2(i)+1; end loop; wait until (pwm'event or falling_edge(clk)); if clk = '1' then for i in 0 to npwm-1 loop if (not done(i)) then if (not parta(i)) then -- pwm is in time period between period start and when paired -- output goes inactive if pwm(2*i+1) = (not ST2_POL(i)) then parta(i) := true; if pcnt(i) /= 0 then if cnt(i) /= ST2_COMPA(i)(pcnt(i)) then Print("ERROR: Wrong compare match 1 detected for pwm " & tost(i+1) & " in period = " & tost(pcnt(i)) & ". Is " & tost(cnt(i)) & ", should be " & tost(ST2_COMPA(i)(pcnt(i)))); end if; if ST2_DB(i)(pcnt(i)) = 0 then partb(i) := true; if pwm(2*i) /= ST2_POL(i) then Print("ERROR: Both outputs did not switch simultaneously" & " even though dead band time was zero"); end if; end if; end if; end if; elsif (not partb(i)) then -- pwm is in time period between paired output going inactive and -- output going active (after dead band time) if pwm(2*i) = ST2_POL(i) then partb(i) := true; if pcnt(i) /= 0 then if cnt(i) /= (ST2_COMPA(i)(pcnt(i)) + ST2_DB(i)(pcnt(i))) then Print("ERROR: Wrong dead band (1) time detected for pwm " & tost(i+1) & " in period = " & tost(pcnt(i)) & ". Is " & tost(cnt(i)-ST2_COMPA(i)(pcnt(i))) & ", should be " & tost(ST2_DB(i)(pcnt(i)))); end if; end if; end if; elsif (not partc(i)) then -- pwm is in time period between output going active and -- output going inactive if pwm(2*i) = (not ST2_POL(i)) then partc(i) := true; if pcnt(i) /= 0 then if cnt(i) /= ST2_COMPB(i)(pcnt(i)) then Print("ERROR: Wrong compare match (2) detected for pwm " & tost(i+1) & " in period = " & tost(pcnt(i)) & ". Is " & tost(cnt(i)) & ", should be " & tost(ST2_COMPB(i)(pcnt(i)))); end if; if ST2_DB(i)(pcnt(i)) = 0 then partd(i) := true; if pwm(2*i+1) /= ST2_POL(i) then Print("ERROR: Both outputs did not switch simultaneously" & " even though dead band time was zero"); end if; end if; else if ST2_DB(i)(0) = 0 then cnt2(i) := 0; partd(i) := true; end if; end if; end if; elsif (not partd(i)) then -- pwm is in time period between output going inactive and -- paired output going active (after dead band time) if pwm(2*i+1) = ST2_POL(i) then partd(i) := true; if pcnt(i) /= 0 then if cnt(i) /= (ST2_COMPB(i)(pcnt(i)) + ST2_DB(i)(pcnt(i))) then Print("ERROR: Wrong dead band (2) time detected for pwm " & tost(i+1) & " in period = " & tost(pcnt(i)) & ". Is " & tost(cnt(i)-ST2_COMPB(i)(pcnt(i))) & ", should be " & tost(ST2_DB(i)(pcnt(i)))); end if; else cnt2(i) := 0; end if; end if; end if; end if; end loop; end if; for i in 0 to npwm-1 loop if (not done(i)) then if partd(i) then -- pwm is in time period between paired output going active -- and period end if pcnt(i) /= 0 then if cnt(i) = ST2_PER(i)(pcnt(i)) then parta(i) := false; partb(i) := false; partc(i) := false; partd(i) := false; pcnt(i) := pcnt(i)+1; cnt(i) := 0; end if; else if (cnt2(i)+ST2_COMPB(i)(0)+ST2_DB(i)(0)) = ST2_PER(i)(0) then parta(i) := false; partb(i) := false; partc(i) := false; partd(i) := false; pcnt(i) := pcnt(i)+1; cnt(i) := 0; end if; end if; if pcnt(i) = ST2_NPER then done(i) := true; end if; end if; end if; end loop; end loop; when 3 => ------------------------------------------------------------------------- -- Subtest 3: One asymmetric waveform PWM is generated. Verify period, -- compare matches and dead band time ------------------------------------------------------------------------- parta(npwm-1) := true; while not done(npwm-1) loop wait until rising_edge(clk); cnt(npwm-1) := cnt(npwm-1)+1; wait until (pwmh'event or falling_edge(clk)); if clk = '1' then addr := pcnt(npwm-1) - (pcnt(npwm-1)/ST3_WRAMSIZE)*ST3_WRAMSIZE; if (not parta(npwm-1)) then -- pwm is in time period between period start and when paired -- output goes active (after dead band time) if pwmh(1) = ST3_POL(npwm-1) then parta(npwm-1) := true; if pcnt(npwm-1) /= 0 then if cnt(npwm-1) /= ST3_DB(npwm-1)(pcnt(npwm-1)) then Print("ERROR: Wrong dead band (1) detected for pwm " & tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) & ". Is " & tost(cnt(npwm-1)) & ", should be " & tost(ST3_DB(npwm-1)(pcnt(npwm-1)))); end if; end if; end if; elsif (not partb(npwm-1)) then -- pwm is in time period between paired output going active and -- paired output going inactive if pwmh(1) = (not ST3_POL(npwm-1)) then partb(npwm-1) := true; if pcnt(npwm-1) /= 0 then if cnt(npwm-1) /= ST3_WRAM(addr) then Print("ERROR: Wrong compare match detected for pwm " & tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) & ". Is " & tost(cnt(npwm-1)) & ", should be " & tost(ST3_WRAM(addr))); end if; if ST3_DB(npwm-1)(pcnt(npwm-1)) = 0 then partc(npwm-1) := true; if pwmh(0) /= ST3_POL(npwm-1) then Print("ERROR: Both outputs did not switch simultaneously" & " even though dead band time was zero"); end if; end if; end if; end if; elsif (not partc(npwm-1)) then -- pwm is in time period between paired output going inactive and -- output going active (after dead band time) if pwmh(0) = ST3_POL(npwm-1) then partc(npwm-1) := true; if pcnt(npwm-1) /= 0 then if cnt(npwm-1) /= (ST3_WRAM(addr) + ST3_DB(npwm-1)(pcnt(npwm-1))) then Print("ERROR: Wrong dead band (2) time detected for pwm " & tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) & ". Is " & tost(cnt(npwm-1)-ST3_WRAM(addr)) & ", should be " & tost(ST3_DB(npwm-1)(pcnt(npwm-1)))); end if; end if; end if; else -- pwm is in time period between output going active and period end -- (output going inactive) if pwmh(0) = (not ST3_POL(npwm-1)) then parta(npwm-1) := false; partb(npwm-1) := false; partc(npwm-1) := false; if pcnt(npwm-1) /= 0 then if cnt(npwm-1) /= ST3_PER(npwm-1)(pcnt(npwm-1)) then Print("ERROR: Wrong PWM period detected for pwm " & tost((npwm-1)+1) & " in period = " & tost(pcnt(npwm-1)) & ". Is " & tost(cnt(npwm-1)) & ", should be " & tost(ST3_PER(npwm-1)(pcnt(npwm-1)))); end if; end if; if pcnt(npwm-1) = ST3_NPER then done(npwm-1) := true; end if; pcnt(npwm-1) := pcnt(npwm-1)+1; cnt(npwm-1) := 0; if pcnt(npwm-1) < ST3_NPER then if ST3_DB(npwm-1)(pcnt(npwm-1)) = 0 then parta(npwm-1) := true; if pwmh(1) /= ST3_POL(npwm-1) then Print("ERROR: Both outputs did not switch simultaneously" & " even though dead band time was zero"); end if; end if; end if; end if; end if; end if; end loop; when 4 => ------------------------------------------------------------------------- -- Subtest 4: One symmetric waveform PWM is generated. Verify period, -- compare matches, and dead band time ------------------------------------------------------------------------- for j in 0 to ST4_NPER loop addr := j - (j/ST4_WRAMSIZE)*ST4_WRAMSIZE; ST4_COMPB(npwm-1)(j) := ST4_PER(npwm-1)(j)-ST4_WRAM(addr); end loop; while not done(npwm-1) loop wait until rising_edge(clk); cnt(npwm-1) := cnt(npwm-1)+1; cnt2(npwm-1) := cnt2(npwm-1)+1; wait until (pwmh'event or falling_edge(clk)); if clk = '1' then addr := pcnt(npwm-1) - (pcnt(npwm-1)/ST4_WRAMSIZE)*ST4_WRAMSIZE; if (not parta(npwm-1)) then -- pwm is in time period between period start and when paired -- output goes inactive if pwmh(1) = (not ST4_POL(npwm-1)) then parta(npwm-1) := true; if pcnt(npwm-1) /= 0 then if cnt(npwm-1) /= ST4_WRAM(addr) then Print("ERROR: Wrong compare match 1 detected for pwm " & tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) & ". Is " & tost(cnt(npwm-1)) & ", should be " & tost(ST4_WRAM(addr))); end if; if ST4_DB(npwm-1)(pcnt(npwm-1)) = 0 then partb(npwm-1) := true; if pwmh(0) /= ST4_POL(npwm-1) then Print("ERROR: Both outputs did not switch simultaneously" & " even though dead band time was zero"); end if; end if; end if; end if; elsif (not partb(npwm-1)) then -- pwm is in time period between paired output going inactive and -- output going active (after dead band time) if pwmh(0) = ST4_POL(npwm-1) then partb(npwm-1) := true; if pcnt(npwm-1) /= 0 then if cnt(npwm-1) /= (ST4_WRAM(addr) + ST4_DB(npwm-1)(pcnt(npwm-1))) then Print("ERROR: Wrong dead band (1) time detected for pwm " & tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) & ". Is " & tost(cnt(npwm-1)-ST4_WRAM(addr)) & ", should be " & tost(ST4_DB(npwm-1)(pcnt(npwm-1)))); end if; end if; end if; elsif (not partc(npwm-1)) then -- pwm is in time period between output going active and -- output going inactive if pwmh(0) = (not ST4_POL(npwm-1)) then partc(npwm-1) := true; if pcnt(npwm-1) /= 0 then if cnt(npwm-1) /= ST4_COMPB(npwm-1)(pcnt(npwm-1)) then Print("ERROR: Wrong compare match (2) detected for pwm " & tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) & ". Is " & tost(cnt(npwm-1)) & ", should be " & tost(ST4_COMPB(npwm-1)(pcnt(npwm-1)))); end if; if ST4_DB(npwm-1)(pcnt(npwm-1)) = 0 then partd(npwm-1) := true; if pwmh(1) /= ST4_POL(npwm-1) then Print("ERROR: Both outputs did not switch simultaneously" & " even though dead band time was zero"); end if; end if; else if ST4_DB(npwm-1)(0) = 0 then cnt2(npwm-1) := 0; partd(npwm-1) := true; end if; end if; end if; elsif (not partd(npwm-1)) then -- pwm is in time period between output going inactive and -- paired output going active (after dead band time) if pwmh(1) = ST4_POL(npwm-1) then partd(npwm-1) := true; if pcnt(npwm-1) /= 0 then if cnt(npwm-1) /= (ST4_COMPB(npwm-1)(pcnt(npwm-1)) + ST4_DB(npwm-1)(pcnt(npwm-1))) then Print("ERROR: Wrong dead band (2) time detected for pwm " & tost(npwm-1+1) & " in period = " & tost(pcnt(npwm-1)) & ". Is " & tost(cnt(npwm-1)-ST4_COMPB(npwm-1)(pcnt(npwm-1))) & ", should be " & tost(ST4_DB(npwm-1)(pcnt(npwm-1)))); end if; else cnt2(npwm-1) := 0; end if; end if; end if; end if; if partd(npwm-1) then -- pwm is in time period between paired output going active -- and period end if pcnt(npwm-1) /= 0 then if cnt(npwm-1) = ST4_PER(npwm-1)(pcnt(npwm-1)) then parta(npwm-1) := false; partb(npwm-1) := false; partc(npwm-1) := false; partd(npwm-1) := false; pcnt(npwm-1) := pcnt(npwm-1)+1; cnt(npwm-1) := 0; end if; else if (cnt2(npwm-1)+ST4_COMPB(npwm-1)(0)+ST4_DB(npwm-1)(0)) = ST4_PER(npwm-1)(0) then parta(npwm-1) := false; partb(npwm-1) := false; partc(npwm-1) := false; partd(npwm-1) := false; pcnt(npwm-1) := pcnt(npwm-1)+1; cnt(npwm-1) := 0; end if; end if; if pcnt(npwm-1) = ST4_NPER then done(npwm-1) := true; end if; end if; end loop; when others => null; end case; end verify_subtest; begin ior <= iosn or oen; iow <= iosn or writen; data <= (others => 'Z'); addr <= to_X01(address) when rising_edge(clk) else addr; ldata <= to_X01(data) when rising_edge(clk) else ldata; pwmh <= pwm(pwmh1 downto pwmh0); process variable vid, did, subtest : integer; variable npwm : integer := 8; begin pwmh0 <= 2*(npwm-1); pwmh1 <= 2*(npwm-1)+1; wait until ((rising_edge(ior) nor falling_edge(ior)) and rising_edge(iow)); case addr(7 downto 2) is when "000000" => vid := conv_integer(ldata(31 downto 24)); did := conv_integer(ldata(23 downto 12)); when "000010" => subtest := conv_integer(ldata(7 downto 0)); if vid = VENDOR_GAISLER and did = GAISLER_PWM then if subtest > 246 then -- set npwm npwm := 255 - subtest; else verify_subtest(subtest, npwm, clk, pwm, pwmh); end if; end if; when others => end case; end process; end sim; -- pragma translate_on

gpl-2.0

f041c856a20c0733de9e6b79594f3d4b

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/ip_repo/ac.uk_user_lms_pcore_1.0/hdl/vhdl/lms_pcore_cop.vhd

-- ------------------------------------------------------------- -- -- File Name: hdl_prj\hdlsrc\lms\lms_pcore_cop.vhd -- Created: 2015-06-19 16:39:46 -- -- Generated by MATLAB 8.5 and HDL Coder 3.6 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: lms_pcore_cop -- Source Path: lms_pcore/lms_pcore_cop -- Hierarchy Level: 1 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY lms_pcore_cop IS PORT( clk : IN std_logic; reset : IN std_logic; in_strobe : IN std_logic; -- ufix1 cop_enable : IN std_logic; -- ufix1 out_ready : OUT std_logic; -- ufix1 dut_enable : OUT std_logic; -- ufix1 reg_strobe : OUT std_logic -- ufix1 ); END lms_pcore_cop; ARCHITECTURE rtl OF lms_pcore_cop IS -- Signals SIGNAL enb : std_logic; SIGNAL cp_controller_cpstate : unsigned(7 DOWNTO 0); -- uint8 SIGNAL cp_controller_clkcnt : std_logic; -- ufix1 SIGNAL cp_controller_cpstate_next : unsigned(7 DOWNTO 0); -- uint8 SIGNAL cp_controller_clkcnt_next : std_logic; -- ufix1 BEGIN enb <= cop_enable; cp_controller_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN cp_controller_cpstate <= to_unsigned(16#00#, 8); cp_controller_clkcnt <= '0'; ELSIF clk'EVENT AND clk = '1' THEN IF enb = '1' THEN cp_controller_cpstate <= cp_controller_cpstate_next; cp_controller_clkcnt <= cp_controller_clkcnt_next; END IF; END IF; END PROCESS cp_controller_process; cp_controller_output : PROCESS (cp_controller_cpstate, cp_controller_clkcnt, in_strobe) VARIABLE clkcnt_temp : std_logic; VARIABLE add_cast : unsigned(1 DOWNTO 0); VARIABLE add_temp : unsigned(1 DOWNTO 0); BEGIN cp_controller_cpstate_next <= cp_controller_cpstate; CASE cp_controller_cpstate IS WHEN "00000000" => out_ready <= '1'; dut_enable <= '0'; reg_strobe <= '0'; clkcnt_temp := '0'; IF in_strobe /= '0' THEN cp_controller_cpstate_next <= to_unsigned(16#01#, 8); ELSE cp_controller_cpstate_next <= to_unsigned(16#00#, 8); END IF; WHEN "00000001" => out_ready <= '0'; dut_enable <= '1'; reg_strobe <= '0'; add_cast := '0' & cp_controller_clkcnt; add_temp := add_cast + to_unsigned(16#1#, 2); clkcnt_temp := add_temp(0); IF clkcnt_temp = '1' THEN cp_controller_cpstate_next <= to_unsigned(16#02#, 8); ELSE cp_controller_cpstate_next <= to_unsigned(16#01#, 8); END IF; WHEN "00000010" => out_ready <= '0'; dut_enable <= '0'; reg_strobe <= '1'; clkcnt_temp := '0'; cp_controller_cpstate_next <= to_unsigned(16#00#, 8); WHEN OTHERS => out_ready <= '0'; dut_enable <= '0'; reg_strobe <= '0'; clkcnt_temp := '0'; cp_controller_cpstate_next <= to_unsigned(16#00#, 8); END CASE; cp_controller_clkcnt_next <= clkcnt_temp; END PROCESS cp_controller_output; END rtl;

mit

01d5c29e2180efb5ef30a1a4ea48c3ae

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ddrphy_wrap.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: ddr_phy -- File: ddr_phy.vhd -- Author: Jiri Gaisler, Gaisler Research -- Description: Wrapper entities for techmap ddrphy/ddr2phy ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.ddrpkg.all; ------------------------------------------------------------------ -- DDR1 PHY wrapper ------------------------------------------------------- ------------------------------------------------------------------ entity ddrphy_wrap is generic (tech : integer := virtex2; MHz : integer := 100; rstdelay : integer := 200; dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2; rskew : integer :=0; mobile : integer := 0; scantest : integer := 0; phyiconf : integer := 0); port ( rst : in std_ulogic; clk : in std_logic; -- input clock clkout : out std_ulogic; -- system clock clkoutret : in std_ulogic; clkread : out std_ulogic; -- read clock lock : out std_ulogic; -- DCM locked ddr_clk : out std_logic_vector(2 downto 0); ddr_clkb : out std_logic_vector(2 downto 0); ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke : out std_logic_vector(1 downto 0); ddr_csb : out std_logic_vector(1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (13 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data sdi : out ddrctrl_in_type; sdo : in ddrctrl_out_type; testen : in std_ulogic; testrst : in std_ulogic; scanen : in std_ulogic; testoen : in std_ulogic); end; architecture rtl of ddrphy_wrap is begin ddr_phy0 : ddrphy generic map (tech => tech, MHz => MHz, rstdelay => rstdelay -- reduce 200 us start-up delay during simulation -- pragma translate_off / 200 -- pragma translate_on , dbits => dbits, clk_mul => clk_mul, clk_div => clk_div, rskew => rskew, mobile => mobile, scantest => scantest, phyiconf => phyiconf) port map ( rst, clk, clkout, clkoutret, clkread, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, sdo.address(13 downto 0), sdo.ba(1 downto 0), sdi.data(dbits*2-1 downto 0), sdo.data(dbits*2-1 downto 0), sdo.dqm(dbits/4-1 downto 0), sdo.bdrive, sdo.bdrive, sdo.qdrive, sdo.rasn, sdo.casn, sdo.sdwen, sdo.sdcsn, sdo.sdcke, sdo.sdck(2 downto 0), sdo.moben, sdi.datavalid, testen, testrst, scanen, testoen); drvdata : if dbits < 64 generate sdi.data(127 downto dbits*2) <= (others => '0'); end generate; sdi.cb <= (others => '0'); sdi.regrdata <= (others => '0'); sdi.writereq <= '0'; end; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.ddrpkg.all; ------------------------------------------------------------------ -- DDR1 PHY with checkbits merged on data bus -------------------- ------------------------------------------------------------------ entity ddrphy_wrap_cbd is generic (tech : integer := virtex2; MHz : integer := 100; rstdelay : integer := 200; dbits : integer := 16; chkbits: integer := 0; padbits : integer := 0; clk_mul : integer := 2 ; clk_div : integer := 2; rskew : integer :=0; mobile : integer := 0; abits: integer := 14; nclk: integer := 3; ncs: integer := 2; scantest: integer := 0; phyiconf : integer := 0); port ( rst : in std_ulogic; clk : in std_logic; -- input clock clkout : out std_ulogic; -- system clock clkoutret : in std_ulogic; -- system clock return clkread : out std_ulogic; lock : out std_ulogic; -- DCM locked ddr_clk : out std_logic_vector(nclk-1 downto 0); ddr_clkb : out std_logic_vector(nclk-1 downto 0); ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke : out std_logic_vector(ncs-1 downto 0); ddr_csb : out std_logic_vector(ncs-1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data sdi : out ddrctrl_in_type; sdo : in ddrctrl_out_type; testen : in std_ulogic; testrst : in std_ulogic; scanen : in std_ulogic; testoen : in std_ulogic); end; architecture rtl of ddrphy_wrap_cbd is function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(2*ow-1 downto 0); constant iw: integer := x'length/2; begin r := (others => '0'); if iw <= ow then r(iw+ow-1 downto ow) := x(2*iw-1 downto iw); r(iw-1 downto 0) := x(iw-1 downto 0); else r := x(iw+ow-1 downto iw) & x(ow-1 downto 0); end if; return r; end; function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(ow-1 downto 0); constant iw: integer := x'length; variable xd : std_logic_vector(iw-1 downto 0); begin r := (others => '0'); xd := x; if iw >= ow then r := xd(ow-1 downto 0); else r(iw-1 downto 0) := xd; end if; return r; end; function ddrmerge(a,b: std_logic_vector) return std_logic_vector is constant aw: integer := a'length/2; constant bw: integer := b'length/2; begin return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0); end; signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0); signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0); signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0); signal odt,csn,cke: std_logic_vector(ncs-1 downto 0); signal sdck: std_logic_vector(nclk-1 downto 0); begin -- Merge checkbit and data buses comb: process(sdo,dqin) variable dq: std_logic_vector(2*dbits-1 downto 0); variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0); variable cb: std_logic_vector(dbits-1 downto 0); variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0 variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0); variable dm: std_logic_vector(dbits/4-1 downto 0); variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0); variable cbdm: std_logic_vector(dbits/8-1 downto 0); variable cbdmpad: std_logic_vector(chkbits/4 downto 0); variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0); variable vcsn,vcke: std_logic_vector(ncs-1 downto 0); variable vsdck: std_logic_vector(nclk-1 downto 0); begin dq := sdo.data(2*dbits-1 downto 0); dqpad := ddr_widthconv(dq, dbits+padbits ); if chkbits > 0 then cb := sdo.cb(dbits-1 downto 0); cbpad := '0' & ddr_widthconv(cb, chkbits); dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad); else dqcb := dqpad; end if; dqout <= dqcb; dqcb := dqin; if chkbits > 0 then cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) & dqin(chkbits+dbits+padbits-1 downto dbits+padbits); cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2); else cb := (others => '0'); end if; dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) & dqcb(dbits-1 downto 0); sdi.cb(dbits-1 downto 0) <= cb; sdi.data(2*dbits-1 downto 0) <= dq; if sdi.cb'length > dbits then sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0'); end if; if sdi.data'length > 2*dbits then sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0'); end if; dm := sdo.dqm(dbits/4-1 downto 0); dmpad := ddr_widthconv(dm, (dbits+padbits)/8); if chkbits > 0 then cbdm := sdo.cbdqm(dbits/8-1 downto 0); cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8); dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad); else dqcbdm := dmpad; end if; dqm <= dqcbdm; cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) & sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 ); cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) & sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 ); vcsn := (others => '1'); for x in 0 to ncs-1 loop if x<2 then vcsn(x) := sdo.sdcsn(x); end if; vcke(x) := sdo.sdcke(x mod 2); end loop; for x in 0 to nclk-1 loop vsdck(x) := sdo.sdck(x mod 2); end loop; csn <= vcsn; cke <= vcke; sdck <= vsdck; end process; -- Phy instantiation ddr_phy0 : ddrphy generic map (tech => tech, MHz => MHz, rstdelay => rstdelay -- reduce 200 us start-up delay during simulation -- pragma translate_off / 200 -- pragma translate_on , dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div, rskew => rskew, mobile => mobile, abits => abits, nclk => nclk, ncs => ncs, scantest => scantest, phyiconf => phyiconf) port map ( rst, clk, clkout, clkoutret, clkread, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, sdo.address(abits-1 downto 0), sdo.ba(1 downto 0), dqin, dqout, dqm, sdo.bdrive, sdo.bdrive, sdo.qdrive, sdo.rasn, sdo.casn, sdo.sdwen, csn, cke, sdck, sdo.moben,sdi.datavalid, testen,testrst,scanen,testoen); sdi.regrdata <= (others => '0'); sdi.writereq <= '0'; end; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.ddrpkg.all; ------------------------------------------------------------------ -- DDR1 PHY with checkbits merged on data bus, pads not in phy -- ------------------------------------------------------------------ entity ddrphy_wrap_cbd_wo_pads is generic (tech : integer := virtex2; MHz : integer := 100; rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0; clk_mul : integer := 2 ; clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0; abits : integer := 14; nclk : integer := 3; ncs : integer := 2; chkbits : integer := 0; scantest : integer := 0; phyiconf : integer := 0); port ( rst : in std_ulogic; clk : in std_logic; -- input clock clkout : out std_ulogic; -- system clock clkoutret : in std_ulogic; -- system clock return lock : out std_ulogic; -- DCM locked ddr_clk : out std_logic_vector(nclk-1 downto 0); ddr_clkb : out std_logic_vector(nclk-1 downto 0); ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke : out std_logic_vector(ncs-1 downto 0); ddr_csb : out std_logic_vector(ncs-1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); sdi : out ddrctrl_in_type; sdo : in ddrctrl_out_type; testen : in std_ulogic; testrst : in std_ulogic; scanen : in std_ulogic; testoen : in std_ulogic); end; architecture rtl of ddrphy_wrap_cbd_wo_pads is function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(2*ow-1 downto 0); constant iw: integer := x'length/2; begin r := (others => '0'); if iw <= ow then r(iw+ow-1 downto ow) := x(2*iw-1 downto iw); r(iw-1 downto 0) := x(iw-1 downto 0); else r := x(iw+ow-1 downto iw) & x(ow-1 downto 0); end if; return r; end; function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(ow-1 downto 0); constant iw: integer := x'length; variable xd : std_logic_vector(iw-1 downto 0); begin r := (others => '0'); xd := x; if iw >= ow then r := xd(ow-1 downto 0); else r(iw-1 downto 0) := xd; end if; return r; end; function ddrmerge(a,b: std_logic_vector) return std_logic_vector is constant aw: integer := a'length/2; constant bw: integer := b'length/2; begin return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0); end; signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0); signal odt,csn,cke: std_logic_vector(ncs-1 downto 0); signal sdck: std_logic_vector(nclk-1 downto 0); signal gnd : std_logic_vector(chkbits*2-1 downto 0); begin gnd <= (others => '0'); -- Merge checkbit and data buses comb: process(sdo,dqin) variable dq: std_logic_vector(2*dbits-1 downto 0); variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0); variable cb: std_logic_vector(dbits-1 downto 0); variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0 variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0); variable dm: std_logic_vector(dbits/4-1 downto 0); variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0); variable cbdm: std_logic_vector(dbits/8-1 downto 0); variable cbdmpad: std_logic_vector(chkbits/4 downto 0); variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0); variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0); variable vsdck: std_logic_vector(nclk-1 downto 0); begin dq := sdo.data(2*dbits-1 downto 0); dqpad := ddr_widthconv(dq, dbits+padbits ); if chkbits > 0 then cb := sdo.cb(dbits-1 downto 0); cbpad := '0' & ddr_widthconv(cb, chkbits); dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad); else dqcb := dqpad; end if; dqout <= dqcb; dqcb := dqin; if chkbits > 0 then cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) & dqin(chkbits+dbits+padbits-1 downto dbits+padbits); cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2); else cb := (others => '0'); end if; dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) & dqcb(dbits-1 downto 0); sdi.cb(dbits-1 downto 0) <= cb; sdi.data(2*dbits-1 downto 0) <= dq; if sdi.cb'length > dbits then sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0'); end if; if sdi.data'length > 2*dbits then sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0'); end if; dm := sdo.dqm(dbits/4-1 downto 0); dmpad := ddr_widthconv(dm, (dbits+padbits)/8); if chkbits > 0 then cbdm := sdo.cbdqm(dbits/8-1 downto 0); cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8); dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad); else dqcbdm := dmpad; end if; dqm <= dqcbdm; vcsn := (others => '1'); for x in 0 to ncs-1 loop if x<2 then vcsn(x) := sdo.sdcsn(x); end if; vodt(x) := sdo.odt(x mod 2); vcke(x) := sdo.sdcke(x mod 2); end loop; for x in 0 to nclk-1 loop vsdck(x) := sdo.sdck(x mod 2); end loop; csn <= vcsn; cke <= vcke; sdck <= vsdck; end process; -- Phy instantiation ddr_phy0 : ddrphy_wo_pads generic map ( tech => tech, MHz => MHz, rstdelay => rstdelay -- reduce 200 us start-up delay during simulation -- pragma translate_off / 200 -- pragma translate_on , dbits => dbits+padbits+chkbits, clk_mul => clk_mul, clk_div => clk_div, rskew => rskew, abits => abits, nclk => nclk, ncs => ncs, mobile => mobile, scantest => scantest, phyiconf => phyiconf) port map ( rst => rst, clk => clk, clkout => clkout, clkoutret => clkoutret, lock => lock, ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_clk_fb_out => ddr_clk_fb_out, ddr_clk_fb => ddr_clk_fb, ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb, ddr_dm => ddr_dm, ddr_dqs_in => ddr_dqs_in, ddr_dqs_out => ddr_dqs_out, ddr_dqs_oen => ddr_dqs_oen, ddr_ad => ddr_ad, ddr_ba => ddr_ba, ddr_dq_in => ddr_dq_in, ddr_dq_out => ddr_dq_out, ddr_dq_oen => ddr_dq_oen, addr => sdo.address(abits-1 downto 0), ba => sdo.ba(1 downto 0), dqin => dqin, dqout => dqout, dm => dqm, oen => sdo.bdrive, dqs => sdo.bdrive, dqsoen => sdo.qdrive, rasn => sdo.rasn, casn => sdo.casn, wen => sdo.sdwen, csn => csn, cke => cke, ck => sdck, moben => sdo.moben, dqvalid => sdi.datavalid, testen => testen, testrst => testrst, scanen => scanen, testoen => testoen ); sdi.regrdata <= (others => '0'); sdi.writereq <= '0'; end; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.ddrpkg.all; ------------------------------------------------------------------ -- DDR2 PHY wrapper ----------------------------------------------- ------------------------------------------------------------------ ------------------------------------------------------------------------------- -- There are three variants of the PHY wrapper depending on pads/checkbits: -- 1. ddr2phy_wrap: -- This provides pads and outputs checkbits on separate vectors -- 2. ddr2phy_wrap_cbd: -- This provides pads and merges checkbits+data on same vector -- 3. ddr2phy_wrap_cbd_wo_pads: -- This does not provide pads and merges checkbits+data on same vectors -- -- Variants (1),(3) can not be used when ddr2phy_builtin_pads(tech)=1 ------------------------------------------------------------------------------- entity ddr2phy_wrap is generic (tech : integer := virtex2; MHz : integer := 100; rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0; clk_mul : integer := 2 ; clk_div : integer := 2; ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0; ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0; ddelayb6 : integer := 0; ddelayb7 : integer := 0; cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0; cbdelayb3 : integer := 0; numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0; rskew : integer := 0; eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0; abits : integer := 14; nclk : integer := 3; ncs : integer := 2; cben : integer := 0; chkbits : integer := 8; ctrl2en : integer := 0; resync : integer := 0; custombits: integer := 8; scantest : integer := 0); port ( rst : in std_ulogic; clk : in std_logic; -- input clock clkref200 : in std_logic; -- input 200MHz clock clkout : out std_ulogic; -- system clock clkoutret : in std_ulogic; -- system clock return clkresync : in std_ulogic; -- resync clock (if resync/=0) lock : out std_ulogic; -- DCM locked ddr_clk : out std_logic_vector(nclk-1 downto 0); ddr_clkb : out std_logic_vector(nclk-1 downto 0); ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke : out std_logic_vector(ncs-1 downto 0); ddr_csb : out std_logic_vector(ncs-1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address ddr_dq : inout std_logic_vector ((dbits+padbits)-1 downto 0); -- ddr data ddr_odt : out std_logic_vector(ncs-1 downto 0); ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0); ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0); ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0); ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0); ddr_web2 : out std_ulogic; -- ddr write enable ddr_rasb2 : out std_ulogic; -- ddr ras ddr_casb2 : out std_ulogic; -- ddr cas ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address sdi : out ddrctrl_in_type; sdo : in ddrctrl_out_type; customclk : in std_ulogic; customdin : in std_logic_vector(custombits-1 downto 0); customdout : out std_logic_vector(custombits-1 downto 0); testen : in std_ulogic; testrst : in std_ulogic; scanen : in std_ulogic; testoen : in std_ulogic ); end; architecture rtl of ddr2phy_wrap is signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0); signal lddr_clk_fb_out,lddr_clk_fb: std_ulogic; signal lddr_cke,lddr_csb,lddr_odt: std_logic_vector(ncs-1 downto 0); signal lddr_web,lddr_rasb,lddr_casb: std_ulogic; signal lddr_dm,lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector((dbits+padbits+chkbits)/8-1 downto 0); signal lddr_ad: std_logic_vector(abits-1 downto 0); signal lddr_ba: std_logic_vector(1+eightbanks downto 0); signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits+padbits+chkbits-1 downto 0); begin -- Instantiate PHY without pads via other wrapper w0: ddr2phy_wrap_cbd_wo_pads generic map (tech,MHz,rstdelay,dbits,padbits,clk_mul,clk_div, ddelayb0,ddelayb1,ddelayb2,ddelayb3,ddelayb4,ddelayb5,ddelayb6,ddelayb7, cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3, numidelctrl,norefclk,odten,rskew, eightbanks,dqsse,abits,nclk,ncs,chkbits,resync,custombits,scantest) port map ( rst,clk,clkref200,clkout,clkoutret,clkresync,lock, lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb, lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm, lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen, lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen, lddr_odt, sdi,sdo,customclk,customdin,customdout,testen,testrst,scanen,testoen); -- Instantiate pads for control signals and data bus p0: ddr2pads generic map (tech,dbits+padbits,eightbanks,dqsse,abits,nclk,ncs,ctrl2en) port map ( ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb, ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb, ddr_dm,ddr_dqs,ddr_dqsn,ddr_ad,ddr_ba,ddr_dq,ddr_odt, ddr_web2,ddr_rasb2,ddr_casb2,ddr_ad2,ddr_ba2, lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb, lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb, lddr_dm(dbits/8+padbits/8-1 downto 0), lddr_dqs_in(dbits/8+padbits/8-1 downto 0), lddr_dqs_out(dbits/8+padbits/8-1 downto 0), lddr_dqs_oen(dbits/8+padbits/8-1 downto 0), lddr_ad,lddr_ba, lddr_dq_in(dbits+padbits-1 downto 0), lddr_dq_out(dbits+padbits-1 downto 0), lddr_dq_oen(dbits+padbits-1 downto 0), lddr_odt); -- Instantiate pads for checkbit bus cbdqpad: iopadvv generic map (tech => tech, slew => 1, level => sstl18_ii, width => chkbits) port map (pad => ddr_cbdq, i => lddr_dq_out(dbits+padbits+chkbits-1 downto dbits+padbits), en => lddr_dq_oen(dbits+padbits+chkbits-1 downto dbits+padbits), o => lddr_dq_in(dbits+padbits+chkbits-1 downto dbits+padbits)); cbdqmpad: outpadv generic map (tech => tech, slew => 1, level => sstl18_i, width => chkbits/8) port map (pad => ddr_cbdm, i => lddr_dm(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8)); cbdqspad: iopad_dsvv generic map (tech => tech, slew => 1, level => sstl18_ii, width => chkbits/8) port map (padp => ddr_cbdqs, padn => ddr_cbdqsn, i => lddr_dqs_out(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8), en => lddr_dqs_oen(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8), o => lddr_dqs_in(dbits/8+padbits/8+chkbits/8-1 downto dbits/8+padbits/8)); end; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.ddrpkg.all; ------------------------------------------------------------------ -- DDR2 PHY with checkbits merged on data bus -------------------- ------------------------------------------------------------------ entity ddr2phy_wrap_cbd is generic (tech : integer := virtex2; MHz : integer := 100; rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0; clk_mul : integer := 2 ; clk_div : integer := 2; ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0; ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0; ddelayb6 : integer := 0; ddelayb7 : integer := 0; cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0; cbdelayb3 : integer := 0; numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0; rskew : integer := 0; eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0; abits : integer := 14; nclk : integer := 3; ncs : integer := 2; chkbits : integer := 0; ctrl2en : integer := 0; resync : integer := 0; custombits: integer := 8; extraio : integer := 0; scantest : integer := 0); port ( rst : in std_ulogic; clk : in std_logic; -- input clock clkref200 : in std_logic; -- input 200MHz clock clkout : out std_ulogic; -- system clock clkoutret : in std_ulogic; -- system clock return clkresync : in std_ulogic; lock : out std_ulogic; -- DCM locked ddr_clk : out std_logic_vector(nclk-1 downto 0); ddr_clkb : out std_logic_vector(nclk-1 downto 0); ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke : out std_logic_vector(ncs-1 downto 0); ddr_csb : out std_logic_vector(ncs-1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (extraio+(dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data ddr_odt : out std_logic_vector(ncs-1 downto 0); ddr_web2 : out std_ulogic; -- ddr write enable ddr_rasb2 : out std_ulogic; -- ddr ras ddr_casb2 : out std_ulogic; -- ddr cas ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address sdi : out ddrctrl_in_type; sdo : in ddrctrl_out_type; customclk : in std_ulogic; customdin : in std_logic_vector(custombits-1 downto 0); customdout : out std_logic_vector(custombits-1 downto 0); testen : in std_ulogic; testrst : in std_ulogic; scanen : in std_ulogic; testoen : in std_ulogic); end; architecture rtl of ddr2phy_wrap_cbd is function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(2*ow-1 downto 0); constant iw: integer := x'length/2; begin r := (others => '0'); if iw <= ow then r(iw+ow-1 downto ow) := x(2*iw-1 downto iw); r(iw-1 downto 0) := x(iw-1 downto 0); else r := x(iw+ow-1 downto iw) & x(ow-1 downto 0); end if; return r; end; function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(ow-1 downto 0); constant iw: integer := x'length; variable xd : std_logic_vector(iw-1 downto 0); begin r := (others => '0'); xd := x; if iw >= ow then r := xd(ow-1 downto 0); else r(iw-1 downto 0) := xd; end if; return r; end; function ddrmerge(a,b: std_logic_vector) return std_logic_vector is constant aw: integer := a'length/2; constant bw: integer := b'length/2; begin return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0); end; type int_array is array (natural range <>) of integer; constant delays: int_array(0 to 7) := (ddelayb0,ddelayb1,ddelayb2,ddelayb3, ddelayb4,ddelayb5,ddelayb6,ddelayb7); constant cbdelays: int_array(0 to 11) := (cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,0,0,0,0,0,0,0,0); constant cbddelays: int_array(0 to 11) := delays(0 to (dbits+padbits)/8-1) & cbdelays(0 to 11-(dbits+padbits)/8); signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0); signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0); signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0); signal odt,csn,cke: std_logic_vector(ncs-1 downto 0); begin -- Merge checkbit and data buses comb: process(sdo,dqin) variable dq: std_logic_vector(2*dbits-1 downto 0); variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0); variable cb: std_logic_vector(dbits-1 downto 0); variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0 variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0); variable dm: std_logic_vector(dbits/4-1 downto 0); variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0); variable cbdm: std_logic_vector(dbits/8-1 downto 0); variable cbdmpad: std_logic_vector(chkbits/4 downto 0); variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0); variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0); begin dq := sdo.data(2*dbits-1 downto 0); dqpad := ddr_widthconv(dq, dbits+padbits ); if chkbits > 0 then cb := sdo.cb(dbits-1 downto 0); cbpad := '0' & ddr_widthconv(cb, chkbits); dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad); else dqcb := dqpad; end if; dqout <= dqcb; dqcb := dqin; if chkbits > 0 then cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) & dqin(chkbits+dbits+padbits-1 downto dbits+padbits); cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2); else cb := (others => '0'); end if; dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) & dqcb(dbits-1 downto 0); sdi.cb(dbits-1 downto 0) <= cb; sdi.data(2*dbits-1 downto 0) <= dq; if sdi.cb'length > dbits then sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0'); end if; if sdi.data'length > 2*dbits then sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0'); end if; dm := sdo.dqm(dbits/4-1 downto 0); dmpad := ddr_widthconv(dm, (dbits+padbits)/8); if chkbits > 0 then cbdm := sdo.cbdqm(dbits/8-1 downto 0); cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8); dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad); else dqcbdm := dmpad; end if; dqm <= dqcbdm; cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) & sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 ); cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) & sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 ); vcsn := (others => '1'); for x in 0 to ncs-1 loop if x<2 then vcsn(x) := sdo.sdcsn(x); end if; vodt(x) := sdo.odt(x mod 2); vcke(x) := sdo.sdcke(x mod 2); end loop; csn <= vcsn; odt <= vodt; cke <= vcke; end process; -- Phy instantiation ddr_phy0 : ddr2phy generic map (tech => tech, MHz => MHz, rstdelay => rstdelay -- reduce 200 us start-up delay during simulation -- pragma translate_off / 200 -- pragma translate_on , dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div, ddelayb0 => cbddelays(0), ddelayb1 => cbddelays(1), ddelayb2 => cbddelays(2), ddelayb3 => cbddelays(3), ddelayb4 => cbddelays(4), ddelayb5 => cbddelays(5), ddelayb6 => cbddelays(6), ddelayb7 => cbddelays(7), ddelayb8 => cbddelays(8), ddelayb9 => cbddelays(9), ddelayb10 => cbddelays(10), ddelayb11 => cbddelays(11), numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew, eightbanks => eightbanks, dqsse => dqsse, abits => abits, nclk => nclk, ncs => ncs, ctrl2en => ctrl2en, resync => resync, custombits => custombits, extraio => extraio, scantest => scantest) port map ( rst, clk, clkref200, clkout, clkoutret, clkresync, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt, sdo.address(abits-1 downto 0), sdo.ba, dqin, dqout, dqm, sdo.bdrive, sdo.nbdrive, sdo.bdrive, sdo.qdrive, sdo.rasn, sdo.casn, sdo.sdwen, csn, cke, cal_en, cal_inc, sdo.cal_pll, sdo.cal_rst, odt, sdo.oct, sdo.read_pend, sdo.regwdata, sdo.regwrite, sdi.regrdata, sdi.datavalid, customclk, customdin, customdout, ddr_web2, ddr_rasb2, ddr_casb2, ddr_ad2, ddr_ba2, testen, testrst, scanen, testoen ); sdi.writereq <= '0'; end; library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.ddrpkg.all; ------------------------------------------------------------------ -- DDR2 PHY with checkbits merged on data bus, pads not in phy -- ------------------------------------------------------------------ entity ddr2phy_wrap_cbd_wo_pads is generic (tech : integer := virtex2; MHz : integer := 100; rstdelay : integer := 200; dbits : integer := 16; padbits : integer := 0; clk_mul : integer := 2 ; clk_div : integer := 2; ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0; ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0; ddelayb6 : integer := 0; ddelayb7 : integer := 0; cbdelayb0 : integer := 0; cbdelayb1: integer := 0; cbdelayb2: integer := 0; cbdelayb3 : integer := 0; numidelctrl : integer := 4; norefclk : integer := 0; odten : integer := 0; rskew : integer := 0; eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0; abits : integer := 14; nclk : integer := 3; ncs : integer := 2; chkbits : integer := 0; resync : integer := 0; custombits: integer := 8; scantest : integer := 0); port ( rst : in std_ulogic; clk : in std_logic; -- input clock clkref200 : in std_logic; -- input 200MHz clock clkout : out std_ulogic; -- system clock clkoutret : in std_ulogic; -- system clock return clkresync : in std_ulogic; lock : out std_ulogic; -- DCM locked ddr_clk : out std_logic_vector(nclk-1 downto 0); ddr_clkb : out std_logic_vector(nclk-1 downto 0); ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke : out std_logic_vector(ncs-1 downto 0); ddr_csb : out std_logic_vector(ncs-1 downto 0); ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data ddr_odt : out std_logic_vector(ncs-1 downto 0); sdi : out ddrctrl_in_type; sdo : in ddrctrl_out_type; customclk : in std_ulogic; customdin : in std_logic_vector(custombits-1 downto 0); customdout : out std_logic_vector(custombits-1 downto 0); testen : in std_ulogic; testrst : in std_ulogic; scanen : in std_ulogic; testoen : in std_ulogic); end; architecture rtl of ddr2phy_wrap_cbd_wo_pads is function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(2*ow-1 downto 0); constant iw: integer := x'length/2; begin r := (others => '0'); if iw <= ow then r(iw+ow-1 downto ow) := x(2*iw-1 downto iw); r(iw-1 downto 0) := x(iw-1 downto 0); else r := x(iw+ow-1 downto iw) & x(ow-1 downto 0); end if; return r; end; function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(ow-1 downto 0); constant iw: integer := x'length; variable xd : std_logic_vector(iw-1 downto 0); begin r := (others => '0'); xd := x; if iw >= ow then r := xd(ow-1 downto 0); else r(iw-1 downto 0) := xd; end if; return r; end; function ddrmerge(a,b: std_logic_vector) return std_logic_vector is constant aw: integer := a'length/2; constant bw: integer := b'length/2; begin return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0); end; type int_array is array (natural range <>) of integer; constant delays: int_array(0 to 7) := (ddelayb0,ddelayb1,ddelayb2,ddelayb3, ddelayb4,ddelayb5,ddelayb6,ddelayb7); constant cbdelays: int_array(0 to 11) := (cbdelayb0,cbdelayb1,cbdelayb2,cbdelayb3,0,0,0,0,0,0,0,0); constant cbddelays: int_array(0 to 11) := delays(0 to (dbits+padbits)/8-1) & cbdelays(0 to 11-(dbits+padbits)/8); signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0); signal cal_en: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0); signal cal_inc: std_logic_vector((chkbits+dbits+padbits)/8-1 downto 0); signal odt,csn,cke: std_logic_vector(ncs-1 downto 0); signal gnd : std_logic_vector(chkbits*2-1 downto 0); begin gnd <= (others => '0'); -- Merge checkbit and data buses comb: process(sdo,dqin) variable dq: std_logic_vector(2*dbits-1 downto 0); variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0); variable cb: std_logic_vector(dbits-1 downto 0); variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0 variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0); variable dm: std_logic_vector(dbits/4-1 downto 0); variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0); variable cbdm: std_logic_vector(dbits/8-1 downto 0); variable cbdmpad: std_logic_vector(chkbits/4 downto 0); variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0); variable vcsn,vodt,vcke: std_logic_vector(ncs-1 downto 0); begin dq := sdo.data(2*dbits-1 downto 0); dqpad := ddr_widthconv(dq, dbits+padbits ); if chkbits > 0 then cb := sdo.cb(dbits-1 downto 0); cbpad := '0' & ddr_widthconv(cb, chkbits); dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad); else dqcb := dqpad; end if; dqout <= dqcb; dqcb := dqin; if chkbits > 0 then cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) & dqin(chkbits+dbits+padbits-1 downto dbits+padbits); cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2); else cb := (others => '0'); end if; dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) & dqcb(dbits-1 downto 0); sdi.cb(dbits-1 downto 0) <= cb; sdi.data(2*dbits-1 downto 0) <= dq; if sdi.cb'length > dbits then sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0'); end if; if sdi.data'length > 2*dbits then sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0'); end if; dm := sdo.dqm(dbits/4-1 downto 0); dmpad := ddr_widthconv(dm, (dbits+padbits)/8); if chkbits > 0 then cbdm := sdo.cbdqm(dbits/8-1 downto 0); cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8); dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad); else dqcbdm := dmpad; end if; dqm <= dqcbdm; cal_en <= sdr_widthconv(sdo.cbcal_en (dbits/16-1 downto 0) & sdo.cal_en (dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 ); cal_inc <= sdr_widthconv(sdo.cbcal_inc(dbits/16-1 downto 0) & sdo.cal_inc(dbits/8-1 downto 0), (dbits+padbits+chkbits)/8 ); vcsn := (others => '1'); for x in 0 to ncs-1 loop if x<2 then vcsn(x) := sdo.sdcsn(x); end if; vodt(x) := sdo.odt(x mod 2); vcke(x) := sdo.sdcke(x mod 2); end loop; csn <= vcsn; odt <= vodt; cke <= vcke; end process; -- Phy instantiation ddr_phy0 : ddr2phy_wo_pads generic map (tech => tech, MHz => MHz, rstdelay => rstdelay -- reduce 200 us start-up delay during simulation -- pragma translate_off / 200 -- pragma translate_on , dbits => dbits+padbits+chkbits,clk_mul => clk_mul, clk_div => clk_div, ddelayb0 => cbddelays(0), ddelayb1 => cbddelays(1), ddelayb2 => cbddelays(2), ddelayb3 => cbddelays(3), ddelayb4 => cbddelays(4), ddelayb5 => cbddelays(5), ddelayb6 => cbddelays(6), ddelayb7 => cbddelays(7), ddelayb8 => cbddelays(8), ddelayb9 => cbddelays(9), ddelayb10 => cbddelays(10), ddelayb11 => cbddelays(11), numidelctrl => numidelctrl, norefclk => norefclk, rskew => rskew, eightbanks => eightbanks, dqsse => dqsse, abits => abits, nclk => nclk, ncs => ncs, resync => resync, custombits => custombits, scantest => scantest) port map ( rst => rst, clk => clk, clkref => clkref200, clkout => clkout, clkoutret => clkoutret, clkresync => clkresync, lock => lock, ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_clk_fb_out => ddr_clk_fb_out, ddr_clk_fb => ddr_clk_fb, ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb, ddr_dm => ddr_dm, ddr_dqs_in => ddr_dqs_in, ddr_dqs_out => ddr_dqs_out, ddr_dqs_oen => ddr_dqs_oen, ddr_ad => ddr_ad, ddr_ba => ddr_ba, ddr_dq_in => ddr_dq_in, ddr_dq_out => ddr_dq_out, ddr_dq_oen => ddr_dq_oen, ddr_odt => ddr_odt, addr => sdo.address(abits-1 downto 0), ba => sdo.ba, dqin => dqin, dqout => dqout, dm => dqm, oen => sdo.bdrive, noen => sdo.nbdrive, dqs => sdo.bdrive, dqsoen => sdo.qdrive, rasn => sdo.rasn, casn => sdo.casn, wen => sdo.sdwen, csn => csn, cke => cke, cal_en => cal_en, cal_inc => cal_inc, cal_pll => sdo.cal_pll, cal_rst => sdo.cal_rst, odt => odt, oct => sdo.oct, read_pend => sdo.read_pend, regwdata => sdo.regwdata, regwrite => sdo.regwrite, regrdata => sdi.regrdata, dqin_valid => sdi.datavalid, customclk => customclk, customdin => customdin, customdout => customdout, testen => testen, testrst => testrst, scanen => scanen, testoen => testoen ); sdi.writereq <= '0'; end; ------------------------------------------------------------------ -- LPDDR2/LPDDR3 PHY with checkbits merged on data bus, no pads -- ------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.ddrpkg.all; entity lpddr2phy_wrap_cbd_wo_pads is generic (tech : integer := virtex2; dbits : integer := 16; nclk : integer := 3; ncs : integer := 2; chkbits : integer := 0; padbits : integer := 0; scantest : integer := 0); port ( rst : in std_ulogic; clkin : in std_ulogic; -- input clock clkin2 : in std_ulogic; -- input clock clkout : out std_ulogic; -- system clock clkoutret : in std_ulogic; -- system clock return clkout2 : out std_ulogic; -- system clock lock : out std_ulogic; -- DCM locked ddr_clk : out std_logic_vector(nclk-1 downto 0); ddr_clkb : out std_logic_vector(nclk-1 downto 0); ddr_cke : out std_logic_vector(ncs-1 downto 0); ddr_csb : out std_logic_vector(ncs-1 downto 0); ddr_ca : out std_logic_vector(9 downto 0); -- ddr cmd/addr ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); sdi : out ddrctrl_in_type; sdo : in ddrctrl_out_type; testen : in std_ulogic; testrst : in std_ulogic; scanen : in std_ulogic; testoen : in std_ulogic); end; architecture rtl of lpddr2phy_wrap_cbd_wo_pads is function ddr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(2*ow-1 downto 0); constant iw: integer := x'length/2; begin r := (others => '0'); if iw <= ow then r(iw+ow-1 downto ow) := x(2*iw-1 downto iw); r(iw-1 downto 0) := x(iw-1 downto 0); else r := x(iw+ow-1 downto iw) & x(ow-1 downto 0); end if; return r; end; function sdr_widthconv(x: std_logic_vector; ow: integer) return std_logic_vector is variable r: std_logic_vector(ow-1 downto 0); constant iw: integer := x'length; variable xd : std_logic_vector(iw-1 downto 0); begin r := (others => '0'); xd := x; if iw >= ow then r := xd(ow-1 downto 0); else r(iw-1 downto 0) := xd; end if; return r; end; function ddrmerge(a,b: std_logic_vector) return std_logic_vector is constant aw: integer := a'length/2; constant bw: integer := b'length/2; begin return a(2*aw-1 downto aw) & b(2*bw-1 downto bw) & a(aw-1 downto 0) & b(bw-1 downto 0); end; signal dqin: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqout: std_logic_vector(2*(chkbits+dbits+padbits)-1 downto 0); signal dqm: std_logic_vector((chkbits+dbits+padbits)/4-1 downto 0); signal odt,csn,cke: std_logic_vector(ncs-1 downto 0); signal sdck: std_logic_vector(nclk-1 downto 0); signal gnd : std_logic_vector(chkbits*2-1 downto 0); begin gnd <= (others => '0'); -- Merge checkbit and data buses comb: process(sdo,dqin) variable dq: std_logic_vector(2*dbits-1 downto 0); variable dqpad: std_logic_vector(2*(dbits+padbits)-1 downto 0); variable cb: std_logic_vector(dbits-1 downto 0); variable cbpad: std_logic_vector(2*chkbits downto 0); -- Extra bit to handle chkbits=0 variable dqcb: std_logic_vector(2*(dbits+padbits+chkbits)-1 downto 0); variable dm: std_logic_vector(dbits/4-1 downto 0); variable dmpad: std_logic_vector((dbits+padbits)/4-1 downto 0); variable cbdm: std_logic_vector(dbits/8-1 downto 0); variable cbdmpad: std_logic_vector(chkbits/4 downto 0); variable dqcbdm: std_logic_vector((dbits+padbits+chkbits)/4-1 downto 0); variable vcsn,vcke: std_logic_vector(ncs-1 downto 0); variable vsdck: std_logic_vector(nclk-1 downto 0); begin dq := sdo.data(2*dbits-1 downto 0); dqpad := ddr_widthconv(dq, dbits+padbits ); if chkbits > 0 then cb := sdo.cb(dbits-1 downto 0); cbpad := '0' & ddr_widthconv(cb, chkbits); dqcb := ddrmerge(cbpad(2*chkbits-1 downto 0), dqpad); else dqcb := dqpad; end if; dqout <= dqcb; dqcb := dqin; if chkbits > 0 then cbpad := '0' & dqin(2*(chkbits+dbits+padbits)-1 downto 2*(dbits+padbits)+chkbits) & dqin(chkbits+dbits+padbits-1 downto dbits+padbits); cb := ddr_widthconv(cbpad(2*chkbits-1 downto 0), dbits/2); else cb := (others => '0'); end if; dq := dqcb(2*dbits+chkbits+padbits-1 downto dbits+chkbits+padbits) & dqcb(dbits-1 downto 0); sdi.cb(dbits-1 downto 0) <= cb; sdi.data(2*dbits-1 downto 0) <= dq; if sdi.cb'length > dbits then sdi.cb(sdi.cb'length-1 downto dbits) <= (others => '0'); end if; if sdi.data'length > 2*dbits then sdi.data(sdi.data'length-1 downto 2*dbits) <= (others => '0'); end if; dm := sdo.dqm(dbits/4-1 downto 0); dmpad := ddr_widthconv(dm, (dbits+padbits)/8); if chkbits > 0 then cbdm := sdo.cbdqm(dbits/8-1 downto 0); cbdmpad := '0' & ddr_widthconv(cbdm(dbits/8-1 downto 0), chkbits/8); dqcbdm := ddrmerge(cbdmpad(chkbits/4-1 downto 0), dmpad); else dqcbdm := dmpad; end if; dqm <= dqcbdm; vcsn := (others => '1'); for x in 0 to ncs-1 loop if x<2 then vcsn(x) := sdo.sdcsn(x); end if; vcke(x) := sdo.sdcke(x mod 2); end loop; for x in 0 to nclk-1 loop vsdck(x) := sdo.sdck(x mod 2); end loop; csn <= vcsn; cke <= vcke; sdck <= vsdck; end process; -- Phy instantiation ddr_phy0 : lpddr2phy_wo_pads generic map ( tech => tech, dbits => dbits+padbits+chkbits, nclk => nclk, ncs => ncs, clkratio => 1, scantest => scantest) port map ( rst => rst, clkin => clkin, clkin2 => clkin2, clkout => clkout, clkoutret => clkoutret, clkout2 => clkout2, lock => lock, ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_ca => ddr_ca, ddr_dm => ddr_dm, ddr_dqs_in => ddr_dqs_in, ddr_dqs_out => ddr_dqs_out, ddr_dqs_oen => ddr_dqs_oen, ddr_dq_in => ddr_dq_in, ddr_dq_out => ddr_dq_out, ddr_dq_oen => ddr_dq_oen, ca => sdo.ca, cke => cke, csn => csn, dqin => dqin, dqout => dqout, dm => dqm, ckstop => sdo.sdck(0), boot => sdo.boot, wrpend => sdo.wrpend, rdpend => sdo.read_pend, wrreq(0) => sdi.writereq, rdvalid(0) => sdi.datavalid, refcal => '0', refcalwu => '0', refcaldone => open, phycmd => "00000000", phycmden => '0', phycmdin => x"00000000", phycmdout => open, testen => '0', testrst => '1', scanen => '0', testoen => '0' ); sdi.regrdata <= (others => '0'); end;

gpl-2.0

588f57feecb92a0f62dbf795a2b2a1c1

schmr/grlib

grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/mmu_cache.vhd

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: mmu_cache -- File: mmu_cache.vhd -- Author: Jiri Gaisler -- Description: Cache controllers and AHB interface ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.libiu.all; use gaisler.libcache.all; use gaisler.libleon3.all; use gaisler.mmuconfig.all; use gaisler.mmuiface.all; use gaisler.libmmu.all; entity mmu_cache is generic ( hindex : integer := 0; memtech : integer range 0 to NTECH := 0; dsu : integer range 0 to 1 := 0; icen : integer range 0 to 1 := 0; irepl : integer range 0 to 3 := 0; isets : integer range 1 to 4 := 1; ilinesize : integer range 4 to 8 := 4; isetsize : integer range 1 to 256 := 1; isetlock : integer range 0 to 1 := 0; dcen : integer range 0 to 1 := 0; drepl : integer range 0 to 3 := 0; dsets : integer range 1 to 4 := 1; dlinesize : integer range 4 to 8 := 4; dsetsize : integer range 1 to 256 := 1; dsetlock : integer range 0 to 1 := 0; dsnoop : integer range 0 to 6 := 0; ilram : integer range 0 to 1 := 0; ilramsize : integer range 1 to 512 := 1; ilramstart : integer range 0 to 255 := 16#8e#; dlram : integer range 0 to 1 := 0; dlramsize : integer range 1 to 512 := 1; dlramstart : integer range 0 to 255 := 16#8f#; itlbnum : integer range 2 to 64 := 8; dtlbnum : integer range 2 to 64 := 8; tlb_type : integer range 0 to 3 := 1; tlb_rep : integer range 0 to 1 := 0; cached : integer := 0; clk2x : integer := 0; scantest : integer := 0; mmupgsz : integer range 0 to 5 := 0; smp : integer := 0; mmuen : integer range 0 to 1 := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; ici : in icache_in_type; ico : out icache_out_type; dci : in dcache_in_type; dco : out dcache_out_type; ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type; ahbsi : in ahb_slv_in_type; ahbso : in ahb_slv_out_vector; crami : out cram_in_type; cramo : in cram_out_type; fpuholdn : in std_ulogic; hclk, sclk : in std_ulogic; hclken : in std_ulogic ); end; architecture rtl of mmu_cache is signal icol : icache_out_type; signal dcol : dcache_out_type; signal mcii : memory_ic_in_type; signal mcio : memory_ic_out_type; signal mcdi : memory_dc_in_type; signal mcdo : memory_dc_out_type; signal mcmmi : memory_mm_in_type; signal mcmmo : memory_mm_out_type; signal mmudci : mmudc_in_type; signal mmudco : mmudc_out_type; signal mmuici : mmuic_in_type; signal mmuico : mmuic_out_type; signal ahbsi2 : ahb_slv_in_type; signal ahbi2 : ahb_mst_in_type; signal ahbo2 : ahb_mst_out_type; signal gndv: std_logic_vector(1 downto 0); begin gndv <= (others => '0'); icache0 : mmu_icache generic map (icen, irepl, isets, ilinesize, isetsize, isetlock, ilram, ilramsize, ilramstart, mmuen) port map (rst, clk, ici, icol, dci, dcol, mcii, mcio, crami.icramin, cramo.icramo, fpuholdn, mmudci, mmuici, mmuico); dcache0 : mmu_dcache generic map (dsu, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop, dlram, dlramsize, dlramstart, ilram, ilramstart, itlbnum, dtlbnum, tlb_type, memtech, cached, mmupgsz, smp, mmuen) port map (rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2, crami.dcramin, cramo.dcramo, fpuholdn, mmudci, mmudco, sclk, ahbso); -- AMBA AHB interface a0 : mmu_acache generic map (hindex, ilinesize, cached, clk2x, scantest ) port map (rst, sclk, mcii, mcio, mcdi, mcdo, mcmmi, mcmmo, ahbi2, ahbo2, ahbso, hclken); -- MMU mmugen : if mmuen = 1 generate m0 : mmu generic map (memtech, itlbnum, dtlbnum, tlb_type, tlb_rep, mmupgsz, 1) port map (rst, clk, mmudci, mmudco, mmuici, mmuico, mcmmo, mcmmi, gndv(0), gndv(1 downto 0), open); end generate; nommu : if mmuen = 0 generate mcmmi <= mci_zero; mmudco <= mmudco_zero; mmuico <= mmuico_zero; end generate; ico <= icol; dco <= dcol; clk2xgen: if clk2x /= 0 generate sync0 : clk2xsync generic map (hindex, clk2x) port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2, mcii, mcdi, mcdo, mcmmi.req, mcmmo.grant, hclken); end generate; noclk2x : if clk2x = 0 generate ahbsi2 <= ahbsi; ahbi2 <= ahbi; ahbo <= ahbo2; end generate; end;

gpl-2.0

0eef2c0a2d8970be5bc995b091fb7a87

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-gr-cpci-xc2v6000/leon3mp.vhd

----------------------------------------------------------------------------- -- LEON3 Demonstration design -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib, techmap; use grlib.amba.all; use grlib.stdlib.all; use techmap.gencomp.all; library gaisler; use gaisler.memctrl.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.can.all; use gaisler.pci.all; use gaisler.net.all; use gaisler.jtag.all; use gaisler.spacewire.all; library esa; use esa.memoryctrl.all; use esa.pcicomp.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW ); port ( resetn : in std_logic; clk : in std_logic; pllref : in std_logic; errorn : out std_logic; address : out std_logic_vector(27 downto 0); data : inout std_logic_vector(31 downto 0); sa : out std_logic_vector(14 downto 0); sd : inout std_logic_vector(63 downto 0); sdclk : out std_logic; sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select sdwen : out std_logic; -- sdram write enable sdrasn : out std_logic; -- sdram ras sdcasn : out std_logic; -- sdram cas sddqm : out std_logic_vector (7 downto 0); -- sdram dqm dsutx : out std_logic; -- DSU tx data dsurx : in std_logic; -- DSU rx data dsuen : in std_logic; dsubre : in std_logic; dsuact : out std_logic; txd1 : out std_logic; -- UART1 tx data rxd1 : in std_logic; -- UART1 rx data txd2 : out std_logic; -- UART2 tx data rxd2 : in std_logic; -- UART2 rx data ramsn : out std_logic_vector (4 downto 0); ramoen : out std_logic_vector (4 downto 0); rwen : out std_logic_vector (3 downto 0); oen : out std_logic; writen : out std_logic; read : out std_logic; iosn : out std_logic; romsn : out std_logic_vector (1 downto 0); gpio : inout std_logic_vector(7 downto 0); -- I/O port emdio : inout std_logic; -- ethernet PHY interface etx_clk : in std_logic; erx_clk : in std_logic; erxd : in std_logic_vector(3 downto 0); erx_dv : in std_logic; erx_er : in std_logic; erx_col : in std_logic; erx_crs : in std_logic; etxd : out std_logic_vector(3 downto 0); etx_en : out std_logic; etx_er : out std_logic; emdc : out std_logic; pci_rst : inout std_logic; -- PCI bus pci_clk : in std_logic; pci_gnt : in std_logic; pci_idsel : in std_logic; pci_lock : inout std_logic; pci_ad : inout std_logic_vector(31 downto 0); pci_cbe : inout std_logic_vector(3 downto 0); pci_frame : inout std_logic; pci_irdy : inout std_logic; pci_trdy : inout std_logic; pci_devsel : inout std_logic; pci_stop : inout std_logic; pci_perr : inout std_logic; pci_par : inout std_logic; pci_req : inout std_logic; pci_serr : inout std_logic; pci_host : in std_logic; pci_66 : in std_logic; pci_arb_req : in std_logic_vector(0 to 3); pci_arb_gnt : out std_logic_vector(0 to 3); can_txd : out std_logic_vector(0 to 1); can_rxd : in std_logic_vector(0 to 1); can_stb : out std_logic_vector(0 to 1); spw_rxd : in std_logic_vector(0 to 2); spw_rxdn : in std_logic_vector(0 to 2); spw_rxs : in std_logic_vector(0 to 2); spw_rxsn : in std_logic_vector(0 to 2); spw_txd : out std_logic_vector(0 to 2); spw_txdn : out std_logic_vector(0 to 2); spw_txs : out std_logic_vector(0 to 2); spw_txsn : out std_logic_vector(0 to 2) ); end; architecture rtl of leon3mp is constant blength : integer := 12; constant fifodepth : integer := 8; constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI); constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp; signal vcc, gnd : std_logic_vector(4 downto 0); signal memi : memory_in_type; signal memo : memory_out_type; signal wpo : wprot_out_type; signal sdi : sdctrl_in_type; signal sdo : sdram_out_type; signal sdo2, sdo3 : sdctrl_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal u1i, u2i, dui : uart_in_type; signal u1o, u2o, duo : uart_out_type; signal irqi : irq_in_vector(0 to CFG_NCPU-1); signal irqo : irq_out_vector(0 to CFG_NCPU-1); signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal pcii : pci_in_type; signal pcio : pci_out_type; signal ethi, ethi1, ethi2 : eth_in_type; signal etho, etho1, etho2 : eth_out_type; signal gpti : gptimer_in_type; signal can_lrx, can_ltx : std_logic; signal lclk, pci_lclk : std_logic; signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3); signal tck, tms, tdi, tdo : std_logic; signal spwi : grspw_in_type_vector(0 to 2); signal spwo : grspw_out_type_vector(0 to 2); signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1); signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1); signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1); signal spw_rxtxclk : std_ulogic; signal spw_rxclkn : std_ulogic; signal fpi : grfpu_in_vector_type; signal fpo : grfpu_out_vector_type; constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz constant IOAEN : integer := CFG_SDCTRL+CFG_CAN+CFG_PCI; begin ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref); clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk); pci_clk_pad : clkpad generic map (tech => padtech, level => pci33) port map (pci_clk, pci_lclk); clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN, CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, CFG_SPW_EN) port map (lclk, pci_lclk, clkm, open, spw_lclk, sdclkl, pciclk, cgi, cgo); sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl); rst0 : rstgen -- reset generator port map (resetn, clkm, cgo.clklock, rstn, rstraw); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN, nahbm => maxahbm, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- l3 : if CFG_LEON3 = 1 generate nosh : if CFG_GRFPUSH = 0 generate cpu : for i in 0 to CFG_NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; end generate; sh : if CFG_GRFPUSH = 1 generate cpu : for i in 0 to CFG_NCPU-1 generate u0 : leon3sh -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i)); end generate; grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech) port map (clkm, rstn, fpi, fpo); end generate; errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error); dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); end generate; end generate; nodsu : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0: ahbuart -- Debug UART generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd); dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd); end generate; -- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- mg1 : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS, romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#, rmw => CFG_SRCTRL_RMW) port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3); apbo(0) <= apb_none; end generate; sd1 : if CFG_SDCTRL = 1 generate sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#, ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK, sdbits => 32 + 32*CFG_SDCTRL_SD64) port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2); sa_pad : outpadv generic map (width => 15, tech => padtech) port map (sa, sdo2.address); sd_pad : iopadv generic map (width => 32, tech => padtech) port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0)); sd2 : if CFG_SDCTRL_SD64 = 1 generate sd_pad2 : iopadv generic map (width => 32) port map (sd(63 downto 32), sdo2.data(63 downto 32), sdo2.bdrive, sdi.data(63 downto 32)); end generate; sdcke_pad : outpadv generic map (width =>2, tech => padtech) port map (sdcke, sdo2.sdcke); sdwen_pad : outpad generic map (tech => padtech) port map (sdwen, sdo2.sdwen); sdcsn_pad : outpadv generic map (width =>2, tech => padtech) port map (sdcsn, sdo2.sdcsn); sdras_pad : outpad generic map (tech => padtech) port map (sdrasn, sdo2.rasn); sdcas_pad : outpad generic map (tech => padtech) port map (sdcasn, sdo2.casn); sddqm_pad : outpadv generic map (width =>8, tech => padtech) port map (sddqm, sdo2.dqm(7 downto 0)); end generate; -- sdsn : if (CFG_SDEN = 0) or (CFG_MEMC = 2) generate ahbso(3) <= ahbs_none; end generate; mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0, srbanks => 2, sden => CFG_MCTRL_SDEN, invclk => CFG_INVCLK, sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64) port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller sd2 : if CFG_MCTRL_SEPBUS = 1 generate sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa); bdr : for i in 0 to 3 generate sd_pad : iopadv generic map (tech => padtech, width => 8) port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8)); sd2 : if CFG_MCTRL_SD64 = 1 generate sd_pad2 : iopadv generic map (tech => padtech, width => 8) port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32)); end generate; end generate; end generate; sdwen_pad : outpad generic map (tech => padtech) port map (sdwen, sdo.sdwen); sdras_pad : outpad generic map (tech => padtech) port map (sdrasn, sdo.rasn); sdcas_pad : outpad generic map (tech => padtech) port map (sdcasn, sdo.casn); sddqm_pad : outpadv generic map (width =>8, tech => padtech) port map (sddqm, sdo.dqm); sdcke_pad : outpadv generic map (width =>2, tech => padtech) port map (sdcke, sdo.sdcke); sdcsn_pad : outpadv generic map (width =>2, tech => padtech) port map (sdcsn, sdo.sdcsn); end generate; end generate; nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller sdcke_pad : outpadv generic map (width =>2, tech => padtech) port map (sdcke, vcc(1 downto 0)); sdcsn_pad : outpadv generic map (width =>2, tech => padtech) port map (sdcsn, vcc(1 downto 0)); end generate; memi.brdyn <= '1'; memi.bexcn <= '1'; memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; mg0 : if (CFG_SRCTRL + CFG_MCTRL_LEON2) = 0 generate -- No PROM/SRAM controller apbo(0) <= apb_none; ahbso(0) <= ahbs_none; rams_pad : outpadv generic map (width => 5, tech => padtech) port map (ramsn, vcc); roms_pad : outpadv generic map (width => 2, tech => padtech) port map (romsn, vcc(1 downto 0)); end generate; mgpads : if (CFG_SRCTRL + CFG_MCTRL_LEON2) /= 0 generate -- prom/sram pads addr_pad : outpadv generic map (width => 28, tech => padtech) port map (address, memo.address(27 downto 0)); rams_pad : outpadv generic map (width => 5, tech => padtech) port map (ramsn, memo.ramsn(4 downto 0)); roms_pad : outpadv generic map (width => 2, tech => padtech) port map (romsn, memo.romsn(1 downto 0)); oen_pad : outpad generic map (tech => padtech) port map (oen, memo.oen); rwen_pad : outpadv generic map (width => 4, tech => padtech) port map (rwen, memo.wrn); roen_pad : outpadv generic map (width => 5, tech => padtech) port map (ramoen, memo.ramoen(4 downto 0)); wri_pad : outpad generic map (tech => padtech) port map (writen, memo.writen); read_pad : outpad generic map (tech => padtech) port map (read, memo.read); iosn_pad : outpad generic map (tech => padtech) port map (iosn, memo.iosn); bdr : for i in 0 to 3 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); end generate; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.extclk <= '0'; j2u : if CFG_AHB_UART = 0 generate dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, u1i.rxd); dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, u1o.txd); end generate; j1u : if CFG_AHB_UART = 1 generate rxd_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd); txd_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd); end generate; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; ua2 : if CFG_UART2_ENABLE /= 0 generate uart2 : apbuart -- UART 2 generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) port map (rstn, clkm, apbi, apbo(9), u2i, u2o); u2i.extclk <= '0'; rxd_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd); txd_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd); end generate; noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate; -- apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; -- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; ----------------------------------------------------------------------- --- PCI ------------------------------------------------------------ ----------------------------------------------------------------------- pp : if CFG_PCI /= 0 generate pci_gr0 : if CFG_PCI = 1 generate -- simple target-only pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, device_id => CFG_PCIDID, vendor_id => CFG_PCIVID) port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG)); end generate; pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, ioaddr => 16#400#, nsync => 2, hostrst => 1) port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); end generate; pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1, dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#, nsync => 2, hostrst => 1) port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1), apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4)); end generate; pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)), memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#) port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8)); end generate; pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter pciarb0 : pciarb generic map (pindex => 10, paddr => 10, apb_en => CFG_PCI_ARBAPB) port map ( clk => pciclk, rst_n => pcii.rst, req_n => pci_arb_req_n, frame_n => pcii.frame, gnt_n => pci_arb_gnt_n, pclk => clkm, prst_n => rstn, apbi => apbi, apbo => apbo(10) ); pgnt_pad : outpadv generic map (tech => padtech, width => 4) port map (pci_arb_gnt, pci_arb_gnt_n); preq_pad : inpadv generic map (tech => padtech, width => 4) port map (pci_arb_req, pci_arb_req_n); end generate; pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio ); end generate; -- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate; -- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate; -- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate; -- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate; -- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate; ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG, pindex => 15, paddr => 15, pirq => 6, memtech => memtech, mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO, nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL) port map( rst => rstn, clk => clkm, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho); emdio_pad : iopad generic map (tech => padtech) port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i); etxc_pad : inpad generic map (tech => padtech) port map (etx_clk, ethi.tx_clk); erxc_pad : inpad generic map (tech => padtech) port map (erx_clk, ethi.rx_clk); erxd_pad : inpadv generic map (tech => padtech, width => 4) port map (erxd, ethi.rxd(3 downto 0)); erxdv_pad : inpad generic map (tech => padtech) port map (erx_dv, ethi.rx_dv); erxer_pad : inpad generic map (tech => padtech) port map (erx_er, ethi.rx_er); erxco_pad : inpad generic map (tech => padtech) port map (erx_col, ethi.rx_col); erxcr_pad : inpad generic map (tech => padtech) port map (erx_crs, ethi.rx_crs); etxd_pad : outpadv generic map (tech => padtech, width => 4) port map (etxd, etho.txd(3 downto 0)); etxen_pad : outpad generic map (tech => padtech) port map ( etx_en, etho.tx_en); etxer_pad : outpad generic map (tech => padtech) port map (etx_er, etho.tx_er); emdc_pad : outpad generic map (tech => padtech) port map (emdc, etho.mdc); end generate; ----------------------------------------------------------------------- --- CAN -------------------------------------------------------------- ----------------------------------------------------------------------- can0 : if CFG_CAN = 1 generate can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO, iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech) port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx ); end generate; -- ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate; can_stb(0) <= '0'; -- no standby can_loopback : if CFG_CANLOOP = 1 generate can_lrx <= can_ltx; end generate; can_pads : if CFG_CANLOOP = 0 generate can_tx_pad : outpad generic map (tech => padtech) port map (can_txd(0), can_ltx); can_rx_pad : inpad generic map (tech => padtech) port map (can_rxd(0), can_lrx); end generate; ----------------------------------------------------------------------- --- SPACEWIRE ------------------------------------------------------- ----------------------------------------------------------------------- spw : if CFG_SPW_EN > 0 generate spw_rxtxclk <= spw_lclk; spw_rxclkn <= not spw_rxtxclk; swloop : for i in 0 to CFG_SPW_NUM-1 generate -- GRSPW2 PHY spw2_input : if CFG_SPW_GRSPW = 2 generate spw_phy0 : grspw2_phy generic map( scantest => 0, tech => fabtech, input_type => CFG_SPW_INPUT) port map( rstn => rstn, rxclki => spw_rxtxclk, rxclkin => spw_rxclkn, nrxclki => spw_rxtxclk, di => dtmp(i), si => stmp(i), do => spwi(i).d(1 downto 0), dov => spwi(i).dv(1 downto 0), dconnect => spwi(i).dconnect(1 downto 0), rxclko => spw_rxclk(i)); spwi(i).nd <= (others => '0'); -- Only used in GRSPW spwi(i).dv(3 downto 2) <= "00"; -- For second port end generate spw2_input; -- GRSPW PHY spw1_input: if CFG_SPW_GRSPW = 1 generate spw_phy0 : grspw_phy generic map( tech => fabtech, rxclkbuftype => 1, scantest => 0) port map( rxrst => spwo(i).rxrst, di => dtmp(i), si => stmp(i), rxclko => spw_rxclk(i), do => spwi(i).d(0), ndo => spwi(i).nd(4 downto 0), dconnect => spwi(i).dconnect(1 downto 0)); spwi(i).d(1) <= '0'; spwi(i).dv <= (others => '0'); -- Only used in GRSPW2 spwi(i).nd(9 downto 5) <= "00000"; -- For second port end generate spw1_input; spwi(i).d(3 downto 2) <= "00"; -- For second port spwi(i).dconnect(3 downto 2) <= "00"; -- For second port spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY sw0 : grspwm generic map(tech => fabtech, hindex => maxahbmsp+i, pindex => 10+i, paddr => 10+i, pirq => 10+i, sysfreq => cpu_freq, nsync => 1, rmap => CFG_SPW_RMAP, rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1, rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, netlist => CFG_SPW_NETLIST, ports => 1, dmachan => CFG_SPW_DMACHAN, memtech => memtech, spwcore => CFG_SPW_GRSPW, input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT, rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL) port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk, ahbmi, ahbmo(maxahbmsp+i), apbi, apbo(10+i), spwi(i), spwo(i)); spwi(i).tickin <= '0'; spwi(i).rmapen <= '0'; spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ*2/10000-1, 8); spwi(i).dcrstval <= (others => '0'); spwi(i).timerrstval <= (others => '0'); spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v) port map (spw_rxd(i), spw_rxdn(i), dtmp(i)); spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v) port map (spw_rxs(i), spw_rxsn(i), stmp(i)); spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v) port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0)); spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v) port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0)); end generate; end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ocram : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE) port map ( rstn, clkm, ahbsi, ahbso(7)); end generate; -- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- -- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate -- ahbmo(i) <= ahbm_none; -- end generate; -- nam2 : if CFG_PCI > 1 generate -- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none; -- end generate; -- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate; -- apbo(6) <= apb_none; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 GR-CPCI-XC2V6000 Demonstration design", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on end;

gpl-2.0

d6b93be873eab750705a101783f6370e

MarkBlanco/FPGA_Sandbox

RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution2/syn/vhdl/fir_shift_reg.vhd

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fir_shift_reg_ram is generic( mem_type : string := "distributed"; dwidth : integer := 32; awidth : integer := 4; mem_size : integer := 11 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; d0 : in std_logic_vector(dwidth-1 downto 0); we0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of fir_shift_reg_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array := (others=>(others=>'0')); attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "select_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then if (we0 = '1') then ram(CONV_INTEGER(addr0_tmp)) := d0; end if; q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity fir_shift_reg is generic ( DataWidth : INTEGER := 32; AddressRange : INTEGER := 11; AddressWidth : INTEGER := 4); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of fir_shift_reg is component fir_shift_reg_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR; we0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR); end component; begin fir_shift_reg_ram_U : component fir_shift_reg_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, d0 => d0, we0 => we0, q0 => q0); end architecture;

mit

cc3ab486e770bea4ba38eaa91c209401

VerkhovtsovPavel/BSUIR_Labs

Labs/POCP/POCP-6/src/TB/RegFile_T.vhd

library ieee; use ieee.std_logic_1164.all; entity RegFile_T is end RegFile_T; architecture Beh of RegFile_T is component RegFile generic ( -- èíèöèàëèçàöèÿ ðåãèñòðà ïëþñ ðàçðÿäíîé øèíû äàííûõ INITREG: std_logic_vector := "0000"; -- ðàçðÿäíîñòü øèíû àäðåñà a: integer := 2); port ( -- ñèãíàë èíèöèàëèçàöèè ðåãèñòðîâ INIT: in std_logic; -- øèíà äàííûõ äëÿ çàïèñè WDP: in std_logic_vector(INITREG'range); -- øèíà àäðåñà äëÿ çàïèñè WA: in std_logic_vector(a-1 downto 0); -- øèíà àäðåñà äëÿ ÷òåíèÿ RA: in std_logic_vector(a-1 downto 0); -- ñèãíàë ðàçðåøåíèÿ çàïèñè WE: in std_logic; -- ïðî÷èòàííûå äàííûå RDP: out std_logic_vector(INITREG'range)); end component; signal init: std_logic := '0'; signal wdp: std_logic_vector(3 downto 0):= "0000"; signal wa: std_logic_vector(1 downto 0) := "00"; signal ra: std_logic_vector(1 downto 0) := "00"; signal we: std_logic := '0'; signal rdp: std_logic_vector(3 downto 0) := "0000"; constant WAIT_Period: time := 10 ns; begin ufile: RegFile port map ( init => init, wdp => wdp, wa => wa, ra => ra, we => we, rdp => rdp ); main: process begin wait for wait_period; init <= '1'; wait for wait_period / 2; init <= '0'; wdp <= "1100"; wa <= "00"; we <= '1'; wait for wait_period / 2; we <= '0'; wdp <= "1010"; wa <= "01"; wait for wait_period / 2; we <= '1'; wait for wait_period / 2; we <= '0'; wait for wait_period / 2; ra <= "00"; wait for wait_period; ra <= "01"; wait; end process; end Beh; configuration config of RegFile_T is for Beh for ufile : RegFile use entity work.regfile(Beh); end for; end for; end config;

mit

a8f324f8ed545aadd0ba0de0f8a3dde4

MarkBlanco/FPGA_Sandbox

RecComp/Lab2/CNN_Optimization/CNN_Optimization2/solution1/syn/vhdl/convolve_kernel.vhd

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity convolve_kernel is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufw_EN_A : OUT STD_LOGIC; bufw_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0); bufw_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufw_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0); bufw_Clk_A : OUT STD_LOGIC; bufw_Rst_A : OUT STD_LOGIC; bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufi_EN_A : OUT STD_LOGIC; bufi_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0); bufi_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufi_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0); bufi_Clk_A : OUT STD_LOGIC; bufi_Rst_A : OUT STD_LOGIC; bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufo_EN_A : OUT STD_LOGIC; bufo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0); bufo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0); bufo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0); bufo_Clk_A : OUT STD_LOGIC; bufo_Rst_A : OUT STD_LOGIC ); end; architecture behav of convolve_kernel is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "convolve_kernel,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=38509,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=5,HLS_SYN_FF=1433,HLS_SYN_LUT=1252}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000001"; constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000010"; constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000100"; constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000001000"; constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000010000"; constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000100000"; constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000001000000"; constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000010000000"; constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000100000000"; constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000001000000000"; constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000010000000000"; constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000100000000000"; constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000001000000000000"; constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000010000000000000"; constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000100000000000000"; constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000001000000000000000"; constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000010000000000000000"; constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000100000000000000000"; constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (29 downto 0) := "000000000001000000000000000000"; constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (29 downto 0) := "000000000010000000000000000000"; constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (29 downto 0) := "000000000100000000000000000000"; constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (29 downto 0) := "000000001000000000000000000000"; constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (29 downto 0) := "000000010000000000000000000000"; constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (29 downto 0) := "000000100000000000000000000000"; constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (29 downto 0) := "000001000000000000000000000000"; constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (29 downto 0) := "000010000000000000000000000000"; constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (29 downto 0) := "000100000000000000000000000000"; constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (29 downto 0) := "001000000000000000000000000000"; constant ap_ST_fsm_state29 : STD_LOGIC_VECTOR (29 downto 0) := "010000000000000000000000000000"; constant ap_ST_fsm_state30 : STD_LOGIC_VECTOR (29 downto 0) := "100000000000000000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111"; constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010"; constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101"; constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001"; constant ap_const_boolean_1 : BOOLEAN := true; signal ap_CS_fsm : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal to_b_V_fu_201_p2 : STD_LOGIC_VECTOR (1 downto 0); signal to_b_V_reg_479 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none"; signal tmp_16_cast_fu_229_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_16_cast_reg_484 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_fu_195_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ti_b_V_fu_239_p2 : STD_LOGIC_VECTOR (1 downto 0); signal ti_b_V_reg_493 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state3 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none"; signal tmp_4_fu_249_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_4_reg_498 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_2_fu_233_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_16_fu_266_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_16_reg_504 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_11_fu_286_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_11_reg_509 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state4 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none"; signal tmp_21_cast_fu_292_p1 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_21_cast_reg_514 : STD_LOGIC_VECTOR (6 downto 0); signal row_b_V_fu_301_p2 : STD_LOGIC_VECTOR (1 downto 0); signal row_b_V_reg_522 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state5 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none"; signal tmp_17_fu_311_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_17_reg_527 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_5_fu_295_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_fu_321_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_19_reg_533 : STD_LOGIC_VECTOR (5 downto 0); signal ap_CS_fsm_state6 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none"; signal tmp_7_cast_fu_326_p1 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_7_cast_reg_538 : STD_LOGIC_VECTOR (2 downto 0); signal col_b_V_fu_336_p2 : STD_LOGIC_VECTOR (1 downto 0); signal col_b_V_reg_546 : STD_LOGIC_VECTOR (1 downto 0); signal ap_CS_fsm_state7 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none"; signal bufo_addr_reg_551 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_8_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_cast_fu_356_p1 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_cast_reg_556 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state9 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none"; signal i_V_fu_366_p2 : STD_LOGIC_VECTOR (2 downto 0); signal i_V_reg_569 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state10 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none"; signal tmp_22_fu_381_p1 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_22_reg_574 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_3_fu_360_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_fu_385_p1 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_23_reg_579 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_9_fu_389_p2 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_9_reg_584 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_24_fu_401_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_24_reg_589 : STD_LOGIC_VECTOR (8 downto 0); signal ap_CS_fsm_state11 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none"; signal tmp_25_fu_409_p2 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_25_reg_594 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_26_fu_414_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_26_reg_599 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_27_fu_428_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_27_reg_604 : STD_LOGIC_VECTOR (8 downto 0); signal ap_CS_fsm_state12 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none"; signal j_V_fu_440_p2 : STD_LOGIC_VECTOR (2 downto 0); signal j_V_reg_612 : STD_LOGIC_VECTOR (2 downto 0); signal ap_CS_fsm_state13 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none"; signal tmp_28_fu_450_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_28_reg_617 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_10_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_12_fu_455_p2 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_12_reg_622 : STD_LOGIC_VECTOR (2 downto 0); signal tmp_29_fu_463_p2 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_29_reg_627 : STD_LOGIC_VECTOR (8 downto 0); signal ap_CS_fsm_state14 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none"; signal ap_CS_fsm_state15 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none"; signal bufw_load_reg_642 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state16 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none"; signal bufi_load_reg_647 : STD_LOGIC_VECTOR (31 downto 0); signal grp_fu_191_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_13_reg_652 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state21 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state21 : signal is "none"; signal grp_fu_186_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state30 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state30 : signal is "none"; signal p_s_reg_95 : STD_LOGIC_VECTOR (1 downto 0); signal p_1_reg_106 : STD_LOGIC_VECTOR (1 downto 0); signal p_2_reg_117 : STD_LOGIC_VECTOR (1 downto 0); signal p_3_reg_129 : STD_LOGIC_VECTOR (1 downto 0); signal p_4_reg_141 : STD_LOGIC_VECTOR (2 downto 0); signal temp1_reg_152 : STD_LOGIC_VECTOR (31 downto 0); signal p_5_reg_162 : STD_LOGIC_VECTOR (2 downto 0); signal temp_1_reg_173 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_25_cast_fu_351_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_32_cast_fu_468_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_33_cast_fu_472_p1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state8 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none"; signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state22 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state22 : signal is "none"; signal ap_CS_fsm_state17 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none"; signal tmp_s_fu_211_p3 : STD_LOGIC_VECTOR (3 downto 0); signal p_shl_cast_fu_219_p1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_1_cast_fu_207_p1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_1_fu_223_p2 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_4_cast_fu_245_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_15_fu_254_p3 : STD_LOGIC_VECTOR (4 downto 0); signal p_shl1_cast_fu_262_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_7_fu_275_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_17_cast_fu_272_p1 : STD_LOGIC_VECTOR (31 downto 0); signal p_shl2_fu_282_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_7_cast8_fu_307_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_18_fu_316_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_cast7_fu_342_p1 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_20_fu_346_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp_6_fu_372_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_21_fu_376_p2 : STD_LOGIC_VECTOR (31 downto 0); signal p_shl5_cast_fu_394_p3 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_9_cast_cast_fu_406_p1 : STD_LOGIC_VECTOR (6 downto 0); signal p_shl4_cast_fu_421_p3 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_29_cast_fu_418_p1 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_11_cast_fu_446_p1 : STD_LOGIC_VECTOR (8 downto 0); signal tmp_12_cast_cast_fu_460_p1 : STD_LOGIC_VECTOR (8 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (29 downto 0); component convolve_kernel_fbkb IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; component convolve_kernel_fcud IS generic ( ID : INTEGER; NUM_STAGE : INTEGER; din0_WIDTH : INTEGER; din1_WIDTH : INTEGER; dout_WIDTH : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; din0 : IN STD_LOGIC_VECTOR (31 downto 0); din1 : IN STD_LOGIC_VECTOR (31 downto 0); ce : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (31 downto 0) ); end component; begin convolve_kernel_fbkb_U0 : component convolve_kernel_fbkb generic map ( ID => 1, NUM_STAGE => 9, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => temp_1_reg_173, din1 => tmp_13_reg_652, ce => ap_const_logic_1, dout => grp_fu_186_p2); convolve_kernel_fcud_U1 : component convolve_kernel_fcud generic map ( ID => 1, NUM_STAGE => 5, din0_WIDTH => 32, din1_WIDTH => 32, dout_WIDTH => 32) port map ( clk => ap_clk, reset => ap_rst, din0 => bufw_load_reg_642, din1 => bufi_load_reg_647, ce => ap_const_logic_1, dout => grp_fu_191_p2); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; p_1_reg_106_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_5_fu_295_p2 = ap_const_lv1_1))) then p_1_reg_106 <= ti_b_V_reg_493; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_0))) then p_1_reg_106 <= ap_const_lv2_0; end if; end if; end process; p_2_reg_117_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_8_fu_330_p2 = ap_const_lv1_1))) then p_2_reg_117 <= row_b_V_reg_522; elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then p_2_reg_117 <= ap_const_lv2_0; end if; end if; end process; p_3_reg_129_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state10) and (tmp_3_fu_360_p2 = ap_const_lv1_1))) then p_3_reg_129 <= col_b_V_reg_546; elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then p_3_reg_129 <= ap_const_lv2_0; end if; end if; end process; p_4_reg_141_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then p_4_reg_141 <= i_V_reg_569; elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then p_4_reg_141 <= ap_const_lv3_0; end if; end if; end process; p_5_reg_162_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state30)) then p_5_reg_162 <= j_V_reg_612; elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then p_5_reg_162 <= ap_const_lv3_0; end if; end if; end process; p_s_reg_95_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_2_fu_233_p2 = ap_const_lv1_1))) then p_s_reg_95 <= to_b_V_reg_479; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then p_s_reg_95 <= ap_const_lv2_0; end if; end if; end process; temp1_reg_152_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then temp1_reg_152 <= temp_1_reg_173; elsif ((ap_const_logic_1 = ap_CS_fsm_state9)) then temp1_reg_152 <= bufo_Dout_A; end if; end if; end process; temp_1_reg_173_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state30)) then temp_1_reg_173 <= grp_fu_186_p2; elsif ((ap_const_logic_1 = ap_CS_fsm_state12)) then temp_1_reg_173 <= temp1_reg_152; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state16)) then bufi_load_reg_647 <= bufi_Dout_A; bufw_load_reg_642 <= bufw_Dout_A; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_0 = tmp_8_fu_330_p2))) then bufo_addr_reg_551 <= tmp_25_cast_fu_351_p1(5 - 1 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state7)) then col_b_V_reg_546 <= col_b_V_fu_336_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state10)) then i_V_reg_569 <= i_V_fu_366_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state13)) then j_V_reg_612 <= j_V_fu_440_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state5)) then row_b_V_reg_522 <= row_b_V_fu_301_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state3)) then ti_b_V_reg_493 <= ti_b_V_fu_239_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state4)) then tmp_11_reg_509 <= tmp_11_fu_286_p2; tmp_21_cast_reg_514 <= tmp_21_cast_fu_292_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = tmp_10_fu_434_p2))) then tmp_12_reg_622 <= tmp_12_fu_455_p2; tmp_28_reg_617 <= tmp_28_fu_450_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state21)) then tmp_13_reg_652 <= grp_fu_191_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_0))) then tmp_16_cast_reg_484 <= tmp_16_cast_fu_229_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = tmp_2_fu_233_p2))) then tmp_16_reg_504 <= tmp_16_fu_266_p2; tmp_4_reg_498 <= tmp_4_fu_249_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_5_fu_295_p2))) then tmp_17_reg_527 <= tmp_17_fu_311_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state6)) then tmp_19_reg_533 <= tmp_19_fu_321_p2; tmp_7_cast_reg_538(1 downto 0) <= tmp_7_cast_fu_326_p1(1 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state10) and (ap_const_lv1_0 = tmp_3_fu_360_p2))) then tmp_22_reg_574 <= tmp_22_fu_381_p1; tmp_23_reg_579 <= tmp_23_fu_385_p1; tmp_9_reg_584 <= tmp_9_fu_389_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state11)) then tmp_24_reg_589 <= tmp_24_fu_401_p2; tmp_25_reg_594 <= tmp_25_fu_409_p2; tmp_26_reg_599 <= tmp_26_fu_414_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state12)) then tmp_27_reg_604 <= tmp_27_fu_428_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state14)) then tmp_29_reg_627 <= tmp_29_fu_463_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state9)) then tmp_cast_reg_556(1 downto 0) <= tmp_cast_fu_356_p1(1 downto 0); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state2)) then to_b_V_reg_479 <= to_b_V_fu_201_p2; end if; end if; end process; tmp_7_cast_reg_538(2) <= '0'; tmp_cast_reg_556(2) <= '0'; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, tmp_fu_195_p2, ap_CS_fsm_state3, tmp_2_fu_233_p2, ap_CS_fsm_state5, tmp_5_fu_295_p2, ap_CS_fsm_state7, tmp_8_fu_330_p2, ap_CS_fsm_state10, tmp_3_fu_360_p2, ap_CS_fsm_state13, tmp_10_fu_434_p2) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_state2 => if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state1; else ap_NS_fsm <= ap_ST_fsm_state3; end if; when ap_ST_fsm_state3 => if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_2_fu_233_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state4; end if; when ap_ST_fsm_state4 => ap_NS_fsm <= ap_ST_fsm_state5; when ap_ST_fsm_state5 => if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_5_fu_295_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state3; else ap_NS_fsm <= ap_ST_fsm_state6; end if; when ap_ST_fsm_state6 => ap_NS_fsm <= ap_ST_fsm_state7; when ap_ST_fsm_state7 => if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_8_fu_330_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state5; else ap_NS_fsm <= ap_ST_fsm_state8; end if; when ap_ST_fsm_state8 => ap_NS_fsm <= ap_ST_fsm_state9; when ap_ST_fsm_state9 => ap_NS_fsm <= ap_ST_fsm_state10; when ap_ST_fsm_state10 => if (((ap_const_logic_1 = ap_CS_fsm_state10) and (tmp_3_fu_360_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state7; else ap_NS_fsm <= ap_ST_fsm_state11; end if; when ap_ST_fsm_state11 => ap_NS_fsm <= ap_ST_fsm_state12; when ap_ST_fsm_state12 => ap_NS_fsm <= ap_ST_fsm_state13; when ap_ST_fsm_state13 => if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then ap_NS_fsm <= ap_ST_fsm_state10; else ap_NS_fsm <= ap_ST_fsm_state14; end if; when ap_ST_fsm_state14 => ap_NS_fsm <= ap_ST_fsm_state15; when ap_ST_fsm_state15 => ap_NS_fsm <= ap_ST_fsm_state16; when ap_ST_fsm_state16 => ap_NS_fsm <= ap_ST_fsm_state17; when ap_ST_fsm_state17 => ap_NS_fsm <= ap_ST_fsm_state18; when ap_ST_fsm_state18 => ap_NS_fsm <= ap_ST_fsm_state19; when ap_ST_fsm_state19 => ap_NS_fsm <= ap_ST_fsm_state20; when ap_ST_fsm_state20 => ap_NS_fsm <= ap_ST_fsm_state21; when ap_ST_fsm_state21 => ap_NS_fsm <= ap_ST_fsm_state22; when ap_ST_fsm_state22 => ap_NS_fsm <= ap_ST_fsm_state23; when ap_ST_fsm_state23 => ap_NS_fsm <= ap_ST_fsm_state24; when ap_ST_fsm_state24 => ap_NS_fsm <= ap_ST_fsm_state25; when ap_ST_fsm_state25 => ap_NS_fsm <= ap_ST_fsm_state26; when ap_ST_fsm_state26 => ap_NS_fsm <= ap_ST_fsm_state27; when ap_ST_fsm_state27 => ap_NS_fsm <= ap_ST_fsm_state28; when ap_ST_fsm_state28 => ap_NS_fsm <= ap_ST_fsm_state29; when ap_ST_fsm_state29 => ap_NS_fsm <= ap_ST_fsm_state30; when ap_ST_fsm_state30 => ap_NS_fsm <= ap_ST_fsm_state13; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end case; end process; ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_CS_fsm_state10 <= ap_CS_fsm(9); ap_CS_fsm_state11 <= ap_CS_fsm(10); ap_CS_fsm_state12 <= ap_CS_fsm(11); ap_CS_fsm_state13 <= ap_CS_fsm(12); ap_CS_fsm_state14 <= ap_CS_fsm(13); ap_CS_fsm_state15 <= ap_CS_fsm(14); ap_CS_fsm_state16 <= ap_CS_fsm(15); ap_CS_fsm_state17 <= ap_CS_fsm(16); ap_CS_fsm_state2 <= ap_CS_fsm(1); ap_CS_fsm_state21 <= ap_CS_fsm(20); ap_CS_fsm_state22 <= ap_CS_fsm(21); ap_CS_fsm_state3 <= ap_CS_fsm(2); ap_CS_fsm_state30 <= ap_CS_fsm(29); ap_CS_fsm_state4 <= ap_CS_fsm(3); ap_CS_fsm_state5 <= ap_CS_fsm(4); ap_CS_fsm_state6 <= ap_CS_fsm(5); ap_CS_fsm_state7 <= ap_CS_fsm(6); ap_CS_fsm_state8 <= ap_CS_fsm(7); ap_CS_fsm_state9 <= ap_CS_fsm(8); ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_195_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_1))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_195_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_195_p2 = ap_const_lv1_1))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; bufi_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_33_cast_fu_472_p1),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0))))); bufi_Clk_A <= ap_clk; bufi_Din_A <= ap_const_lv32_0; bufi_EN_A_assign_proc : process(ap_CS_fsm_state15) begin if ((ap_const_logic_1 = ap_CS_fsm_state15)) then bufi_EN_A <= ap_const_logic_1; else bufi_EN_A <= ap_const_logic_0; end if; end process; bufi_Rst_A <= ap_rst; bufi_WEN_A <= ap_const_lv4_0; bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0))))); bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_551),32)); bufo_Clk_A <= ap_clk; bufo_Din_A <= temp_1_reg_173; bufo_EN_A_assign_proc : process(ap_CS_fsm_state13, ap_CS_fsm_state8) begin if (((ap_const_logic_1 = ap_CS_fsm_state13) or (ap_const_logic_1 = ap_CS_fsm_state8))) then bufo_EN_A <= ap_const_logic_1; else bufo_EN_A <= ap_const_logic_0; end if; end process; bufo_Rst_A <= ap_rst; bufo_WEN_A_assign_proc : process(ap_CS_fsm_state13, tmp_10_fu_434_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state13) and (tmp_10_fu_434_p2 = ap_const_lv1_1))) then bufo_WEN_A <= ap_const_lv4_F; else bufo_WEN_A <= ap_const_lv4_0; end if; end process; bufw_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_32_cast_fu_468_p1),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0))))); bufw_Clk_A <= ap_clk; bufw_Din_A <= ap_const_lv32_0; bufw_EN_A_assign_proc : process(ap_CS_fsm_state15) begin if ((ap_const_logic_1 = ap_CS_fsm_state15)) then bufw_EN_A <= ap_const_logic_1; else bufw_EN_A <= ap_const_logic_0; end if; end process; bufw_Rst_A <= ap_rst; bufw_WEN_A <= ap_const_lv4_0; col_b_V_fu_336_p2 <= std_logic_vector(unsigned(p_3_reg_129) + unsigned(ap_const_lv2_1)); i_V_fu_366_p2 <= std_logic_vector(unsigned(p_4_reg_141) + unsigned(ap_const_lv3_1)); j_V_fu_440_p2 <= std_logic_vector(unsigned(p_5_reg_162) + unsigned(ap_const_lv3_1)); p_shl1_cast_fu_262_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_15_fu_254_p3),6)); p_shl2_fu_282_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_7_fu_275_p3),32)); p_shl4_cast_fu_421_p3 <= (tmp_26_reg_599 & ap_const_lv3_0); p_shl5_cast_fu_394_p3 <= (tmp_23_reg_579 & ap_const_lv2_0); p_shl_cast_fu_219_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_fu_211_p3),5)); row_b_V_fu_301_p2 <= std_logic_vector(unsigned(p_2_reg_117) + unsigned(ap_const_lv2_1)); ti_b_V_fu_239_p2 <= std_logic_vector(unsigned(p_1_reg_106) + unsigned(ap_const_lv2_1)); tmp_10_fu_434_p2 <= "1" when (p_5_reg_162 = ap_const_lv3_5) else "0"; tmp_11_cast_fu_446_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_5_reg_162),9)); tmp_11_fu_286_p2 <= std_logic_vector(signed(tmp_17_cast_fu_272_p1) + signed(p_shl2_fu_282_p1)); tmp_12_cast_cast_fu_460_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_reg_622),9)); tmp_12_fu_455_p2 <= std_logic_vector(unsigned(tmp_cast_reg_556) + unsigned(p_5_reg_162)); tmp_15_fu_254_p3 <= (p_1_reg_106 & ap_const_lv3_0); tmp_16_cast_fu_229_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_1_fu_223_p2),6)); tmp_16_fu_266_p2 <= std_logic_vector(unsigned(p_shl1_cast_fu_262_p1) - unsigned(tmp_4_cast_fu_245_p1)); tmp_17_cast_fu_272_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_4_reg_498),32)); tmp_17_fu_311_p2 <= std_logic_vector(unsigned(tmp_7_cast8_fu_307_p1) + unsigned(tmp_16_cast_reg_484)); tmp_18_fu_316_p2 <= std_logic_vector(shift_left(unsigned(tmp_17_reg_527),to_integer(unsigned('0' & ap_const_lv6_2(6-1 downto 0))))); tmp_19_fu_321_p2 <= std_logic_vector(unsigned(tmp_18_fu_316_p2) - unsigned(tmp_17_reg_527)); tmp_1_cast_fu_207_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_s_reg_95),5)); tmp_1_fu_223_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_219_p1) - unsigned(tmp_1_cast_fu_207_p1)); tmp_20_fu_346_p2 <= std_logic_vector(unsigned(tmp_19_reg_533) + unsigned(tmp_cast7_fu_342_p1)); tmp_21_cast_fu_292_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_16_reg_504),7)); tmp_21_fu_376_p2 <= std_logic_vector(unsigned(tmp_6_fu_372_p1) + unsigned(tmp_11_reg_509)); tmp_22_fu_381_p1 <= tmp_21_fu_376_p2(9 - 1 downto 0); tmp_23_fu_385_p1 <= tmp_21_fu_376_p2(7 - 1 downto 0); tmp_24_fu_401_p2 <= std_logic_vector(unsigned(p_shl5_cast_fu_394_p3) + unsigned(tmp_22_reg_574)); tmp_25_cast_fu_351_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_20_fu_346_p2),32)); tmp_25_fu_409_p2 <= std_logic_vector(unsigned(tmp_9_cast_cast_fu_406_p1) + unsigned(tmp_21_cast_reg_514)); tmp_26_fu_414_p1 <= tmp_25_fu_409_p2(6 - 1 downto 0); tmp_27_fu_428_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_421_p3) - unsigned(tmp_29_cast_fu_418_p1)); tmp_28_fu_450_p2 <= std_logic_vector(unsigned(tmp_24_reg_589) + unsigned(tmp_11_cast_fu_446_p1)); tmp_29_cast_fu_418_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_25_reg_594),9)); tmp_29_fu_463_p2 <= std_logic_vector(unsigned(tmp_27_reg_604) + unsigned(tmp_12_cast_cast_fu_460_p1)); tmp_2_fu_233_p2 <= "1" when (p_1_reg_106 = ap_const_lv2_3) else "0"; tmp_32_cast_fu_468_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_28_reg_617),32)); tmp_33_cast_fu_472_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_29_reg_627),32)); tmp_3_fu_360_p2 <= "1" when (p_4_reg_141 = ap_const_lv3_5) else "0"; tmp_4_cast_fu_245_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_1_reg_106),6)); tmp_4_fu_249_p2 <= std_logic_vector(signed(tmp_16_cast_reg_484) + signed(tmp_4_cast_fu_245_p1)); tmp_5_fu_295_p2 <= "1" when (p_2_reg_117 = ap_const_lv2_3) else "0"; tmp_6_fu_372_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_4_reg_141),32)); tmp_7_cast8_fu_307_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_2_reg_117),6)); tmp_7_cast_fu_326_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_2_reg_117),3)); tmp_7_fu_275_p3 <= (tmp_4_reg_498 & ap_const_lv2_0); tmp_8_fu_330_p2 <= "1" when (p_3_reg_129 = ap_const_lv2_3) else "0"; tmp_9_cast_cast_fu_406_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_584),7)); tmp_9_fu_389_p2 <= std_logic_vector(unsigned(p_4_reg_141) + unsigned(tmp_7_cast_reg_538)); tmp_cast7_fu_342_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_3_reg_129),6)); tmp_cast_fu_356_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_3_reg_129),3)); tmp_fu_195_p2 <= "1" when (p_s_reg_95 = ap_const_lv2_3) else "0"; tmp_s_fu_211_p3 <= (p_s_reg_95 & ap_const_lv2_0); to_b_V_fu_201_p2 <= std_logic_vector(unsigned(p_s_reg_95) + unsigned(ap_const_lv2_1)); end behav;

mit

dee910dd1aa72a4ec5a37a7d88c3060b

JimLewis/OSVVM

CoveragePkg.vhd

-- -- File Name: CoveragePkg.vhd -- Design Unit Name: CoveragePkg -- Revision: STANDARD VERSION -- -- Maintainer: Jim Lewis email: [email protected] -- Contributor(s): -- Jim Lewis SynthWorks -- Matthias Alles Creonic. Inspired GetMinBinVal, GetMinPoint, GetCov -- Jerry Kaczynski Aldec. Inspired GetBin function -- Sebastian Dunst Inspired GetBinName function -- ... Aldec Worked on VendorCov functional coverage interface -- -- Package Defines -- Functional coverage modeling utilities and data structure -- -- Developed by/for: -- SynthWorks Design Inc. -- VHDL Training Classes -- 11898 SW 128th Ave. Tigard, Or 97223 -- http://www.SynthWorks.com -- -- Revision History: For more details, see CoveragePkg_release_notes.pdf -- Date Version Description -- 06/2010: 0.1 Initial revision -- 09/2010 Release in SynthWorks' VHDL Testbenches and Verification classes -- 02/2011: 1.0 Changed CoverBinType to facilitage long term support of cross coverage -- 02/2011: 1.1 Added GetMinCov, GetMaxCov, CountCovHoles, GetCovHole -- 04/2011: 2.0 Added protected type based data structure: CovPType -- 06/2011: 2.1 Removed signal based coverage modeling -- 07/2011: 2.2 Added randomization with coverage goals (AtLeast), weight, and percentage thresholds -- 11/2011: 2.2a Changed constants ALL_RANGE, ZERO_BIN, and ONE_BIN to have a 1 index -- 12/2011: 2.2b Fixed minor inconsistencies on interface declarations. -- 01/2012: 2.3 Added Function GetBin from Jerry K. Made write for RangeArrayType visible -- 01/2012: 2.4 Added Merging of bins -- 04/2013: 2013.04 Thresholding, CovTarget, Merging off by default, -- 5/2013 2013.05 Release with updated RandomPkg. Minimal changes. -- 1/2014 2014.01 Merging of Cov Models, LastIndex -- 7/2014 2014.07 Bin Naming (for requirements tracking), WriteBin with Pass/Fail, GenBin[integer_vector] -- 12/2014 2014.07a Fix memory leak in deallocate. Removed initialied pointers which can lead to leaks. -- 01/2015 2015.01 Use AlertLogPkg to count assertions and filter log messages -- 06/2015 2015.06 AddCross[CovMatrix?Type], Mirroring for WriteBin -- 01/2016 2016.01 Fixes for pure functions. Added bounds checking on ICover -- 03/2016 2016.03 Added GetBinName(Index) to retrieve a bin's name -- 11/2016 2016.11 Added VendorCovApiPkg and calls to bind it in. -- 05/2017 2017.05 Updated WriteBin name printing -- ClearCov (deprecates SetCovZero) -- 04/2018 2018.04 Updated PercentCov calculation so AtLeast of <= 0 is correct -- String' Fix for GHDL -- Removed Deprecated procedure Increment - see TbUtilPkg as it moved there -- 01/2020 2020.01 Updated Licenses to Apache -- 05/2020 2020.05 Updated LastIndex to also be set during ICover. -- Updated deallocate to set all variables to their initial value -- Added GetInc{Index, BinVal, Point} -- Added GetNext{Index, BinVal, Point}[(Mode => {RANDOM|INCREMENT|MIN})] -- Added NextPointModeType = (RANDOM, INCREMENT, MODE_MINIMUM) -- Added SetNextPointMode[(Mode => {RANDOM|INCREMENT|MODE_MINIMUM}) -- Added to_std_logic(integer), to_boolean(integer) + vector forms -- RandCov{Point|BinVal} is deprecated, renamed to GetRand{Point|BinVal} -- 05/2020 2020.07 Adjusted NextPointModeType: Changed MIN to MODE_MINIMUM. -- The preferred MINIMUM will not work in some tools -- Added GetNext{Index, BinVal, Point}[(Mode => {RANDOM|INCREMENT|MODE_MINIMUM})] -- Added NextPointModeType = (RANDOM, INCREMENT, MODE_MINIMUM) -- Added SetNextPointMode[(Mode => {RANDOM|INCREMENT|MODE_MINIMUM}) -- -- -- Development Notes: -- The coverage procedures are named ICover to avoid conflicts with -- future language changes which may add cover as a keyword -- Procedure WriteBin writes each CovBin on a separate line, as such -- it was inappropriate to overload either textio write or to_string -- In the notes VHDL-2008 notes refers to -- composites with unconstrained elements -- -- -- This file is part of OSVVM. -- -- Copyright (c) 2010 - 2020 by SynthWorks Design Inc. -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- https://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use ieee.math_real.all ; use std.textio.all ; -- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002 -- library ieee_proposed ; -- remove with VHDL-2008 -- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008 use work.TextUtilPkg.all ; use work.TranscriptPkg.all ; use work.AlertLogPkg.all ; use work.RandomBasePkg.all ; use work.RandomPkg.all ; use work.NamePkg.all ; use work.MessagePkg.all ; use work.OsvvmGlobalPkg.all ; use work.VendorCovApiPkg.all ; package CoveragePkg is -- CovPType allocates bins that are multiples of MIN_NUM_BINS constant MIN_NUM_BINS : integer := 2**7 ; -- power of 2 type RangeType is record min : integer ; max : integer ; end record ; type RangeArrayType is array (integer range <>) of RangeType ; constant ALL_RANGE : RangeArrayType := (1=>(Integer'left, Integer'right)) ; procedure write ( file f : text ; BinVal : RangeArrayType ) ; procedure write ( variable buf : inout line ; constant BinVal : in RangeArrayType) ; -- CovBinBaseType.action values. -- Note that coverage counting depends on these values constant COV_COUNT : integer := 1 ; constant COV_IGNORE : integer := 0 ; constant COV_ILLEGAL : integer := -1 ; -- type OsvvmOptionsType is (OPT_DEFAULT, FALSE, TRUE) ; alias CovOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ; constant COV_OPT_INIT_PARM_DETECT : CovOptionsType := work.OsvvmGlobalPkg.OPT_INIT_PARM_DETECT ; -- For backward compatibility. Don't add to other packages. alias DISABLED is work.OsvvmGlobalPkg.DISABLED [return work.OsvvmGlobalPkg.OsvvmOptionsType ]; alias ENABLED is work.OsvvmGlobalPkg.ENABLED [return work.OsvvmGlobalPkg.OsvvmOptionsType ]; -- Deprecated -- Used for easy manual entry. Order: min, max, action -- Intentionally did not use a record to allow other input -- formats in the future with VHDL-2008 unconstrained arrays -- of unconstrained elements -- type CovBinManualType is array (natural range <>) of integer_vector(0 to 2) ; type CovBinBaseType is record BinVal : RangeArrayType(1 to 1) ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; end record ; type CovBinType is array (natural range <>) of CovBinBaseType ; constant ALL_BIN : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ; constant ALL_COUNT : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ; constant ALL_ILLEGAL : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_ILLEGAL, Count => 0, AtLeast => 0, Weight => 0 )) ; constant ALL_IGNORE : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_IGNORE, Count => 0, AtLeast => 0, Weight => 0 )) ; constant ZERO_BIN : CovBinType := (0 => ( BinVal => (1=>(0,0)), Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ; constant ONE_BIN : CovBinType := (0 => ( BinVal => (1=>(1,1)), Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ; constant NULL_BIN : CovBinType(work.RandomPkg.NULL_RANGE_TYPE) := (others => ( BinVal => ALL_RANGE, Action => integer'high, Count => 0, AtLeast => integer'high, Weight => integer'high )) ; type NextPointModeType is (RANDOM, INCREMENT, MODE_MINIMUM) ; type CountModeType is (COUNT_FIRST, COUNT_ALL) ; type IllegalModeType is (ILLEGAL_ON, ILLEGAL_FAILURE, ILLEGAL_OFF) ; type WeightModeType is (AT_LEAST, WEIGHT, REMAIN, REMAIN_EXP, REMAIN_SCALED, REMAIN_WEIGHT ) ; -- In VHDL-2008 CovMatrix?BaseType and CovMatrix?Type will be subsumed -- by CovBinBaseType and CovBinType with RangeArrayType as an unconstrained array. type CovMatrix2BaseType is record BinVal : RangeArrayType(1 to 2) ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; end record ; type CovMatrix2Type is array (natural range <>) of CovMatrix2BaseType ; type CovMatrix3BaseType is record BinVal : RangeArrayType(1 to 3) ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; end record ; type CovMatrix3Type is array (natural range <>) of CovMatrix3BaseType ; type CovMatrix4BaseType is record BinVal : RangeArrayType(1 to 4) ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; end record ; type CovMatrix4Type is array (natural range <>) of CovMatrix4BaseType ; type CovMatrix5BaseType is record BinVal : RangeArrayType(1 to 5) ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; end record ; type CovMatrix5Type is array (natural range <>) of CovMatrix5BaseType ; type CovMatrix6BaseType is record BinVal : RangeArrayType(1 to 6) ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; end record ; type CovMatrix6Type is array (natural range <>) of CovMatrix6BaseType ; type CovMatrix7BaseType is record BinVal : RangeArrayType(1 to 7) ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; end record ; type CovMatrix7Type is array (natural range <>) of CovMatrix7BaseType ; type CovMatrix8BaseType is record BinVal : RangeArrayType(1 to 8) ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; end record ; type CovMatrix8Type is array (natural range <>) of CovMatrix8BaseType ; type CovMatrix9BaseType is record BinVal : RangeArrayType(1 to 9) ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; end record ; type CovMatrix9Type is array (natural range <>) of CovMatrix9BaseType ; ------------------------------------------------------------ VendorCov -- VendorCov Conversion for Vendor supported functional coverage modeling function ToVendorCovBinVal (BinVal : RangeArrayType) return VendorCovRangeArrayType ; ------------------------------------------------------------ function ToMinPoint (A : RangeArrayType) return integer ; function ToMinPoint (A : RangeArrayType) return integer_vector ; -- BinVal to Minimum Point ------------------------------------------------------------ procedure ToRandPoint( -- BinVal to Random Point -- better as a function, however, inout not supported on functions ------------------------------------------------------------ variable RV : inout RandomPType ; constant BinVal : in RangeArrayType ; variable result : out integer ) ; ------------------------------------------------------------ procedure ToRandPoint( -- BinVal to Random Point ------------------------------------------------------------ variable RV : inout RandomPType ; constant BinVal : in RangeArrayType ; variable result : out integer_vector ) ; ------------------------------------------------------------------------------------------ -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ------------------------------------------------------------------------------------------ type CovPType is protected procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) ; procedure FileCloseWriteBin ; procedure SetAlertLogID (A : AlertLogIDType) ; procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ; impure function GetAlertLogID return AlertLogIDType ; -- procedure FileOpenWriteCovDb (FileName : string; OpenKind : File_Open_Kind ) ; -- procedure FileCloseWriteCovDb ; procedure SetNextPointMode (A : NextPointModeType) ; procedure SetIllegalMode (A : IllegalModeType) ; procedure SetWeightMode (A : WeightModeType; Scale : real := 1.0) ; procedure SetName (Name : String) ; impure function SetName (Name : String) return string ; impure function GetName return String ; impure function GetCovModelName return String ; procedure SetMessage (Message : String) ; procedure DeallocateName ; -- clear name procedure DeallocateMessage ; -- clear message procedure SetThresholding(A : boolean := TRUE ) ; -- 2.5 procedure SetCovThreshold (Percent : real) ; procedure SetCovTarget (Percent : real) ; -- 2.5 impure function GetCovTarget return real ; -- 2.5 procedure SetMerging(A : boolean := TRUE ) ; -- 2.5 procedure SetCountMode (A : CountModeType) ; procedure InitSeed (S : string ) ; impure function InitSeed (S : string ) return string ; procedure InitSeed (I : integer ) ; procedure SetSeed (RandomSeedIn : RandomSeedType ) ; impure function GetSeed return RandomSeedType ; ------------------------------------------------------------ procedure SetReportOptions ( WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; procedure SetBinSize (NewNumBins : integer) ; ------------------------------------------------------------ procedure AddBins ( ------------------------------------------------------------ Name : String ; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) ; procedure AddBins ( Name : String ; AtLeast : integer ; CovBin : CovBinType ) ; procedure AddBins ( Name : String ; CovBin : CovBinType) ; procedure AddBins ( AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) ; procedure AddBins ( AtLeast : integer ; CovBin : CovBinType ) ; procedure AddBins ( CovBin : CovBinType ) ; ------------------------------------------------------------ procedure AddCross( ------------------------------------------------------------ Name : string ; AtLeast : integer ; Weight : integer ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) ; ------------------------------------------------------------ procedure AddCross( Name : string ; AtLeast : integer ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) ; ------------------------------------------------------------ procedure AddCross( Name : string ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) ; ------------------------------------------------------------ procedure AddCross( AtLeast : integer ; Weight : integer ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) ; ------------------------------------------------------------ procedure AddCross( AtLeast : integer ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) ; ------------------------------------------------------------ procedure AddCross( Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) ; procedure Deallocate ; procedure ICoverLast ; procedure ICover( CovPoint : integer) ; procedure ICover( CovPoint : integer_vector) ; procedure ClearCov ; procedure SetCovZero ; impure function IsInitialized return boolean ; impure function GetMinCov return real ; -- PercentCov impure function GetMinCount return integer ; -- Count impure function GetMaxCov return real ; -- PercentCov impure function GetMaxCount return integer ; -- Count impure function CountCovHoles ( PercentCov : real ) return integer ; impure function CountCovHoles return integer ; impure function IsCovered return boolean ; impure function IsCovered ( PercentCov : real ) return boolean ; impure function GetCov ( PercentCov : real ) return real ; impure function GetCov return real ; -- PercentCov of entire model/all bins impure function GetItemCount return integer ; impure function GetTotalCovGoal ( PercentCov : real ) return integer ; impure function GetTotalCovGoal return integer ; -- Return Index impure function GetNumBins return integer ; impure function GetLastIndex return integer ; impure function GetRandIndex return integer ; impure function GetRandIndex ( CovTargetPercent : real ) return integer ; impure function GetIncIndex return integer ; impure function GetMinIndex return integer ; impure function GetMaxIndex return integer ; impure function GetNextIndex return integer ; impure function GetNextIndex(Mode : NextPointModeType) return integer ; -- Return BinVal impure function GetBinVal ( BinIndex : integer ) return RangeArrayType ; impure function GetLastBinVal return RangeArrayType ; impure function GetRandBinVal return RangeArrayType ; impure function GetRandBinVal ( PercentCov : real ) return RangeArrayType ; impure function GetIncBinVal return RangeArrayType ; impure function GetMinBinVal return RangeArrayType ; impure function GetMaxBinVal return RangeArrayType ; impure function GetNextBinVal return RangeArrayType ; impure function GetNextBinVal(Mode : NextPointModeType) return RangeArrayType ; impure function GetHoleBinVal ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ; impure function GetHoleBinVal ( PercentCov : real ) return RangeArrayType ; impure function GetHoleBinVal ( ReqHoleNum : integer := 1 ) return RangeArrayType ; -- RandCovBinVal is deprecated, renamed to GetRandBinVal impure function RandCovBinVal return RangeArrayType ; impure function RandCovBinVal ( PercentCov : real ) return RangeArrayType ; -- deprecated, see GetRandBinVal -- Return Points impure function GetPoint ( BinIndex : integer ) return integer ; impure function GetPoint ( BinIndex : integer ) return integer_vector ; impure function GetRandPoint return integer ; impure function GetRandPoint ( PercentCov : real ) return integer ; impure function GetRandPoint return integer_vector ; impure function GetRandPoint ( PercentCov : real ) return integer_vector ; impure function GetIncPoint return integer ; impure function GetIncPoint return integer_vector ; impure function GetMinPoint return integer ; impure function GetMinPoint return integer_vector ; impure function GetMaxPoint return integer ; impure function GetMaxPoint return integer_vector ; impure function GetNextPoint return integer ; impure function GetNextPoint return integer_vector ; impure function GetNextPoint(Mode : NextPointModeType) return integer ; impure function GetNextPoint(Mode : NextPointModeType) return integer_vector ; -- RandCovPoint is deprecated, renamed to GetRandPoint impure function RandCovPoint return integer ; impure function RandCovPoint ( PercentCov : real ) return integer ; impure function RandCovPoint return integer_vector ; impure function RandCovPoint ( PercentCov : real ) return integer_vector ; -- GetBin returns an internal value of the coverage data structure -- The return value may change as the package evolves -- Use it only for debugging. -- GetBinInfo is a for development only. impure function GetBinInfo ( BinIndex : integer ) return CovBinBaseType ; impure function GetBinValLength return integer ; impure function GetBin ( BinIndex : integer ) return CovBinBaseType ; impure function GetBin ( BinIndex : integer ) return CovMatrix2BaseType ; impure function GetBin ( BinIndex : integer ) return CovMatrix3BaseType ; impure function GetBin ( BinIndex : integer ) return CovMatrix4BaseType ; impure function GetBin ( BinIndex : integer ) return CovMatrix5BaseType ; impure function GetBin ( BinIndex : integer ) return CovMatrix6BaseType ; impure function GetBin ( BinIndex : integer ) return CovMatrix7BaseType ; impure function GetBin ( BinIndex : integer ) return CovMatrix8BaseType ; impure function GetBin ( BinIndex : integer ) return CovMatrix9BaseType ; impure function GetBinName ( BinIndex : integer; DefaultName : string := "" ) return string ; ------------------------------------------------------------ procedure WriteBin ( WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; ------------------------------------------------------------ procedure WriteBin ( -- With LogLevel LogLevel : LogType ; WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; ------------------------------------------------------------ procedure WriteBin ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ; WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; ------------------------------------------------------------ procedure WriteBin ( -- With LogLevel LogLevel : LogType ; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ; WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; procedure WriteCovHoles ( LogLevel : LogType := ALWAYS ) ; procedure WriteCovHoles ( PercentCov : real ) ; procedure WriteCovHoles ( LogLevel : LogType ; PercentCov : real ) ; procedure WriteCovHoles ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ; procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ; procedure WriteCovHoles ( FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ; procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ; procedure DumpBin (LogLevel : LogType := DEBUG) ; -- Development only procedure ReadCovDb (FileName : string; Merge : boolean := FALSE) ; procedure WriteCovDb (FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ; impure function GetErrorCount return integer ; -- These support usage of cross coverage constants -- Also support the older AddBins(GenCross(...)) methodology -- which has been replaced by AddCross procedure AddCross (CovBin : CovMatrix2Type ; Name : String := "") ; procedure AddCross (CovBin : CovMatrix3Type ; Name : String := "") ; procedure AddCross (CovBin : CovMatrix4Type ; Name : String := "") ; procedure AddCross (CovBin : CovMatrix5Type ; Name : String := "") ; procedure AddCross (CovBin : CovMatrix6Type ; Name : String := "") ; procedure AddCross (CovBin : CovMatrix7Type ; Name : String := "") ; procedure AddCross (CovBin : CovMatrix8Type ; Name : String := "") ; procedure AddCross (CovBin : CovMatrix9Type ; Name : String := "") ; ------------------------------------------------------------ -- Remaining are Deprecated -- -- Deprecated. Replaced by SetName with multi-line support procedure SetItemName (ItemNameIn : String) ; -- deprecated -- Deprecated. Consistency across packages impure function CovBinErrCnt return integer ; -- Deprecated. Due to name changes to promote greater consistency -- Maintained for backward compatibility. -- RandCovHole replaced by RandCovBinVal impure function RandCovHole ( PercentCov : real ) return RangeArrayType ; -- Deprecated impure function RandCovHole return RangeArrayType ; -- Deprecated -- GetCovHole replaced by GetHoleBinVal impure function GetCovHole ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ; impure function GetCovHole ( PercentCov : real ) return RangeArrayType ; impure function GetCovHole ( ReqHoleNum : integer := 1 ) return RangeArrayType ; -- Deprecated/ Subsumed by versions with PercentCov Parameter -- Maintained for backward compatibility only and -- may be removed in the future. impure function GetMinCov return integer ; impure function GetMaxCov return integer ; impure function CountCovHoles ( AtLeast : integer ) return integer ; impure function IsCovered ( AtLeast : integer ) return boolean ; impure function RandCovBinVal ( AtLeast : integer ) return RangeArrayType ; impure function RandCovHole ( AtLeast : integer ) return RangeArrayType ; -- Deprecated impure function RandCovPoint (AtLeast : integer ) return integer ; impure function RandCovPoint (AtLeast : integer ) return integer_vector ; impure function GetHoleBinVal ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType ; impure function GetCovHole ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType ; procedure WriteCovHoles ( AtLeast : integer ) ; procedure WriteCovHoles ( LogLevel : LogType ; AtLeast : integer ) ; procedure WriteCovHoles ( FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) ; procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) ; -- Replaced by a more appropriately named AddCross procedure AddBins (CovBin : CovMatrix2Type ; Name : String := "") ; procedure AddBins (CovBin : CovMatrix3Type ; Name : String := "") ; procedure AddBins (CovBin : CovMatrix4Type ; Name : String := "") ; procedure AddBins (CovBin : CovMatrix5Type ; Name : String := "") ; procedure AddBins (CovBin : CovMatrix6Type ; Name : String := "") ; procedure AddBins (CovBin : CovMatrix7Type ; Name : String := "") ; procedure AddBins (CovBin : CovMatrix8Type ; Name : String := "") ; procedure AddBins (CovBin : CovMatrix9Type ; Name : String := "") ; end protected CovPType ; ------------------------------------------------------------------------------------------ -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ------------------------------------------------------------------------------------------ ------------------------------------------------------------ -- Experimental. Intended primarily for development. procedure CompareBins ( ------------------------------------------------------------ variable Bin1 : inout CovPType ; variable Bin2 : inout CovPType ; variable ErrorCount : inout integer ) ; ------------------------------------------------------------ -- Experimental. Intended primarily for development. procedure CompareBins ( ------------------------------------------------------------ variable Bin1 : inout CovPType ; variable Bin2 : inout CovPType ) ; -- -- Support for AddBins and AddCross -- ------------------------------------------------------------ function GenBin( ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Min, Max : integer ; NumBin : integer ) return CovBinType ; -- Each item in range in a separate CovBin function GenBin(AtLeast : integer ; Min, Max, NumBin : integer ) return CovBinType ; function GenBin(Min, Max, NumBin : integer ) return CovBinType ; function GenBin(Min, Max : integer) return CovBinType ; function GenBin(A : integer) return CovBinType ; ------------------------------------------------------------ function GenBin( ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; A : integer_vector ) return CovBinType ; function GenBin ( AtLeast : integer ; A : integer_vector ) return CovBinType ; function GenBin ( A : integer_vector ) return CovBinType ; ------------------------------------------------------------ function IllegalBin ( Min, Max, NumBin : integer ) return CovBinType ; ------------------------------------------------------------ -- All items in range in a single CovBin function IllegalBin ( Min, Max : integer ) return CovBinType ; function IllegalBin ( A : integer ) return CovBinType ; -- IgnoreBin should never have an AtLeast parameter ------------------------------------------------------------ function IgnoreBin (Min, Max, NumBin : integer) return CovBinType ; ------------------------------------------------------------ function IgnoreBin (Min, Max : integer) return CovBinType ; -- All items in range in a single CovBin function IgnoreBin (A : integer) return CovBinType ; -- With VHDL-2008, there will be one GenCross that returns CovBinType -- and has inputs initialized to NULL_BIN - see AddCross ------------------------------------------------------------ function GenCross( -- 2 -- Cross existing bins -- Use AddCross for adding values directly to coverage database -- Use GenCross for constants ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2 : CovBinType ) return CovMatrix2Type ; function GenCross(AtLeast : integer ; Bin1, Bin2 : CovBinType) return CovMatrix2Type ; function GenCross(Bin1, Bin2 : CovBinType) return CovMatrix2Type ; ------------------------------------------------------------ function GenCross( -- 3 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type ; function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type ; function GenCross( Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type ; ------------------------------------------------------------ function GenCross( -- 4 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type ; function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type ; function GenCross( Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type ; ------------------------------------------------------------ function GenCross( -- 5 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type ; function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type ; function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type ; ------------------------------------------------------------ function GenCross( -- 6 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type ; function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type ; function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type ; ------------------------------------------------------------ function GenCross( -- 7 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type ; function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type ; function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type ; ------------------------------------------------------------ function GenCross( -- 8 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type ; function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type ; function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type ; ------------------------------------------------------------ function GenCross( -- 9 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type ; function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type ; function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type ; ------------------------------------------------------------ -- Utilities. Remove if added to std.standard function to_integer ( B : boolean ) return integer ; function to_boolean ( I : integer ) return boolean ; function to_integer ( SL : std_logic ) return integer ; function to_std_logic ( I : integer ) return std_logic ; function to_integer_vector ( BV : boolean_vector ) return integer_vector ; function to_boolean_vector ( IV : integer_vector ) return boolean_vector ; function to_integer_vector ( SLV : std_logic_vector ) return integer_vector ; function to_std_logic_vector ( IV : integer_vector ) return std_logic_vector ; alias to_slv is to_std_logic_vector[integer_vector return std_logic_vector] ; ------------------------------------------------------------ ------------------------------------------------------------ -- Deprecated: These are not part of the coverage model -- procedure increment( signal Count : inout integer ) ; -- procedure increment( signal Count : inout integer ; enable : boolean ) ; -- procedure increment( signal Count : inout integer ; enable : std_ulogic ) ; end package CoveragePkg ; --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// package body CoveragePkg is ------------------------------------------------------------ function inside ( -- package local ------------------------------------------------------------ CovPoint : integer_vector ; BinVal : RangeArrayType ) return boolean is alias iCovPoint : integer_vector(BinVal'range) is CovPoint ; begin for i in BinVal'range loop if not (iCovPoint(i) >= BinVal(i).min and iCovPoint(i) <= BinVal(i).max) then return FALSE ; end if ; end loop ; return TRUE ; end function inside ; ------------------------------------------------------------ function inside ( -- package local, used by InsertBin -- True when BinVal1 is inside BinVal2 ------------------------------------------------------------ BinVal1 : RangeArrayType ; BinVal2 : RangeArrayType ) return boolean is alias iBinVal2 : RangeArrayType(BinVal1'range) is BinVal2 ; begin for i in BinVal1'range loop if not (BinVal1(i).min >= iBinVal2(i).min and BinVal1(i).max <= iBinVal2(i).max) then return FALSE ; end if ; end loop ; return TRUE ; end function inside ; ------------------------------------------------------------ procedure write ( variable buf : inout line ; CovPoint : integer_vector ) is -- package local. called by ICover ------------------------------------------------------------ alias iCovPoint : integer_vector(1 to CovPoint'length) is CovPoint ; begin write(buf, "(" & integer'image(iCovPoint(1)) ) ; for i in 2 to iCovPoint'right loop write(buf, "," & integer'image(iCovPoint(i)) ) ; end loop ; swrite(buf, ")") ; end procedure write ; ------------------------------------------------------------ procedure write ( file f : text ; BinVal : RangeArrayType ) is -- called by WriteBin and WriteCovHoles ------------------------------------------------------------ begin for i in BinVal'range loop if BinVal(i).min = BinVal(i).max then write(f, "(" & integer'image(BinVal(i).min) & ") " ) ; elsif (BinVal(i).min = integer'left) and (BinVal(i).max = integer'right) then write(f, "(ALL) " ) ; else write(f, "(" & integer'image(BinVal(i).min) & " to " & integer'image(BinVal(i).max) & ") " ) ; end if ; end loop ; end procedure write ; ------------------------------------------------------------ procedure write ( -- called by WriteBin and WriteCovHoles ------------------------------------------------------------ variable buf : inout line ; constant BinVal : in RangeArrayType ) is ------------------------------------------------------------ begin for i in BinVal'range loop if BinVal(i).min = BinVal(i).max then write(buf, "(" & integer'image(BinVal(i).min) & ") " ) ; elsif (BinVal(i).min = integer'left) and (BinVal(i).max = integer'right) then swrite(buf, "(ALL) " ) ; else write(buf, "(" & integer'image(BinVal(i).min) & " to " & integer'image(BinVal(i).max) & ") " ) ; end if ; end loop ; end procedure write ; ------------------------------------------------------------ procedure WriteBinVal ( -- package local for now ------------------------------------------------------------ variable buf : inout line ; constant BinVal : in RangeArrayType ) is begin for i in BinVal'range loop write(buf, BinVal(i).min) ; write(buf, ' ') ; write(buf, BinVal(i).max) ; write(buf, ' ') ; end loop ; end procedure WriteBinVal ; ------------------------------------------------------------ -- package local for now procedure read ( -- if public, also create one that does not use valid flag ------------------------------------------------------------ variable buf : inout line ; variable BinVal : out RangeArrayType ; variable Valid : out boolean ) is variable ReadValid : boolean ; begin for i in BinVal'range loop read(buf, BinVal(i).min, ReadValid) ; exit when not ReadValid ; read(buf, BinVal(i).max, ReadValid) ; exit when not ReadValid ; end loop ; Valid := ReadValid ; end procedure read ; ------------------------------------------------------------ function CalcPercentCov( Count : integer ; AtLeast : integer ) return real is -- package local, called by MergeBin, InsertBin, ClearCov, ReadCovDbDatabase ------------------------------------------------------------ variable PercentCov : real ; begin if AtLeast > 0 then return real(Count)*100.0/real(AtLeast) ; elsif AtLeast = 0 then return 100.0 ; else return real'right ; end if ; end function CalcPercentCov ; -- ------------------------------------------------------------ function BinLengths ( -- package local, used by AddCross, GenCross -- ------------------------------------------------------------ Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) return integer_vector is variable result : integer_vector(1 to 20) := (others => 0 ) ; variable i : integer := result'left ; variable Len : integer ; begin loop case i is when 1 => Len := Bin1'length ; when 2 => Len := Bin2'length ; when 3 => Len := Bin3'length ; when 4 => Len := Bin4'length ; when 5 => Len := Bin5'length ; when 6 => Len := Bin6'length ; when 7 => Len := Bin7'length ; when 8 => Len := Bin8'length ; when 9 => Len := Bin9'length ; when 10 => Len := Bin10'length ; when 11 => Len := Bin11'length ; when 12 => Len := Bin12'length ; when 13 => Len := Bin13'length ; when 14 => Len := Bin14'length ; when 15 => Len := Bin15'length ; when 16 => Len := Bin16'length ; when 17 => Len := Bin17'length ; when 18 => Len := Bin18'length ; when 19 => Len := Bin19'length ; when 20 => Len := Bin20'length ; when others => Len := 0 ; end case ; result(i) := Len ; exit when Len = 0 ; i := i + 1 ; exit when i = 21 ; end loop ; return result(1 to (i-1)) ; end function BinLengths ; -- ------------------------------------------------------------ function CalcNumCrossBins ( BinLens : integer_vector ) return integer is -- package local, used by AddCross -- ------------------------------------------------------------ variable result : integer := 1 ; begin for i in BinLens'range loop result := result * BinLens(i) ; end loop ; return result ; end function CalcNumCrossBins ; -- ------------------------------------------------------------ procedure IncBinIndex ( -- package local, used by AddCross -- ------------------------------------------------------------ variable BinIndex : inout integer_vector ; constant BinLens : in integer_vector ) is alias aBinIndex : integer_vector(1 to BinIndex'length) is BinIndex ; alias aBinLens : integer_vector(aBinIndex'range) is BinLens ; begin -- increment right most one, then if overflow, increment next -- assumes bins numbered from 1 to N. - assured by ConcatenateBins for i in aBinIndex'reverse_range loop aBinIndex(i) := aBinIndex(i) + 1 ; exit when aBinIndex(i) <= aBinLens(i) ; aBinIndex(i) := 1 ; end loop ; end procedure IncBinIndex ; -- ------------------------------------------------------------ function ConcatenateBins ( -- package local, used by AddCross and GenCross -- ------------------------------------------------------------ BinIndex : integer_vector ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) return CovBinType is alias aBin1 : CovBinType (1 to Bin1'length) is Bin1 ; alias aBin2 : CovBinType (1 to Bin2'length) is Bin2 ; alias aBin3 : CovBinType (1 to Bin3'length) is Bin3 ; alias aBin4 : CovBinType (1 to Bin4'length) is Bin4 ; alias aBin5 : CovBinType (1 to Bin5'length) is Bin5 ; alias aBin6 : CovBinType (1 to Bin6'length) is Bin6 ; alias aBin7 : CovBinType (1 to Bin7'length) is Bin7 ; alias aBin8 : CovBinType (1 to Bin8'length) is Bin8 ; alias aBin9 : CovBinType (1 to Bin9'length) is Bin9 ; alias aBin10 : CovBinType (1 to Bin10'length) is Bin10 ; alias aBin11 : CovBinType (1 to Bin11'length) is Bin11 ; alias aBin12 : CovBinType (1 to Bin12'length) is Bin12 ; alias aBin13 : CovBinType (1 to Bin13'length) is Bin13 ; alias aBin14 : CovBinType (1 to Bin14'length) is Bin14 ; alias aBin15 : CovBinType (1 to Bin15'length) is Bin15 ; alias aBin16 : CovBinType (1 to Bin16'length) is Bin16 ; alias aBin17 : CovBinType (1 to Bin17'length) is Bin17 ; alias aBin18 : CovBinType (1 to Bin18'length) is Bin18 ; alias aBin19 : CovBinType (1 to Bin19'length) is Bin19 ; alias aBin20 : CovBinType (1 to Bin20'length) is Bin20 ; alias aBinIndex : integer_vector(1 to BinIndex'length) is BinIndex ; variable result : CovBinType(aBinIndex'range) ; begin for i in aBinIndex'range loop case i is when 1 => result(i) := aBin1(aBinIndex(i)) ; when 2 => result(i) := aBin2(aBinIndex(i)) ; when 3 => result(i) := aBin3(aBinIndex(i)) ; when 4 => result(i) := aBin4(aBinIndex(i)) ; when 5 => result(i) := aBin5(aBinIndex(i)) ; when 6 => result(i) := aBin6(aBinIndex(i)) ; when 7 => result(i) := aBin7(aBinIndex(i)) ; when 8 => result(i) := aBin8(aBinIndex(i)) ; when 9 => result(i) := aBin9(aBinIndex(i)) ; when 10 => result(i) := aBin10(aBinIndex(i)) ; when 11 => result(i) := aBin11(aBinIndex(i)) ; when 12 => result(i) := aBin12(aBinIndex(i)) ; when 13 => result(i) := aBin13(aBinIndex(i)) ; when 14 => result(i) := aBin14(aBinIndex(i)) ; when 15 => result(i) := aBin15(aBinIndex(i)) ; when 16 => result(i) := aBin16(aBinIndex(i)) ; when 17 => result(i) := aBin17(aBinIndex(i)) ; when 18 => result(i) := aBin18(aBinIndex(i)) ; when 19 => result(i) := aBin19(aBinIndex(i)) ; when 20 => result(i) := aBin20(aBinIndex(i)) ; when others => -- pure functions cannot use alert and/or print report "CoveragePkg.AddCross: More than 20 bins not supported" severity FAILURE ; end case ; end loop ; return result ; end function ConcatenateBins ; ------------------------------------------------------------ function MergeState( CrossBins : CovBinType) return integer is -- package local, Used by AddCross, GenCross ------------------------------------------------------------ variable resultState : integer ; begin resultState := COV_COUNT ; for i in CrossBins'range loop if CrossBins(i).action = COV_ILLEGAL then return COV_ILLEGAL ; end if ; if CrossBins(i).action = COV_IGNORE then resultState := COV_IGNORE ; end if ; end loop ; return resultState ; end function MergeState ; ------------------------------------------------------------ function MergeBinVal( CrossBins : CovBinType) return RangeArrayType is -- package local, Used by AddCross, GenCross ------------------------------------------------------------ alias aCrossBins : CovBinType(1 to CrossBins'length) is CrossBins ; variable BinVal : RangeArrayType(aCrossBins'range) ; begin for i in aCrossBins'range loop BinVal(i to i) := aCrossBins(i).BinVal ; end loop ; return BinVal ; end function MergeBinVal ; ------------------------------------------------------------ function MergeAtLeast( -- package local, Used by AddCross, GenCross ------------------------------------------------------------ Action : in integer ; AtLeast : in integer ; CrossBins : in CovBinType ) return integer is variable Result : integer := AtLeast ; begin if Action /= COV_COUNT then return 0 ; end if ; for i in CrossBins'range loop if CrossBins(i).Action = Action then Result := maximum (Result, CrossBins(i).AtLeast) ; end if ; end loop ; return result ; end function MergeAtLeast ; ------------------------------------------------------------ function MergeWeight( -- package local, Used by AddCross, GenCross ------------------------------------------------------------ Action : in integer ; Weight : in integer ; CrossBins : in CovBinType ) return integer is variable Result : integer := Weight ; begin if Action /= COV_COUNT then return 0 ; end if ; for i in CrossBins'range loop if CrossBins(i).Action = Action then Result := maximum (Result, CrossBins(i).Weight) ; end if ; end loop ; return result ; end function MergeWeight ; ------------------------------------------------------------ VendorCov -- VendorCov Conversion for Vendor supported functional coverage modeling function ToVendorCovBinVal (BinVal : RangeArrayType) return VendorCovRangeArrayType is ------------------------------------------------------------ variable VendorCovBinVal : VendorCovRangeArrayType(BinVal'range); begin -- VendorCov for ArrIdx in BinVal'LEFT to BinVal'RIGHT loop -- VendorCov VendorCovBinVal(ArrIdx) := (min => BinVal(ArrIdx).min, -- VendorCov max => BinVal(ArrIdx).max) ; -- VendorCov end loop; -- VendorCov return VendorCovBinVal ; end function ToVendorCovBinVal ; ------------------------------------------------------------ function ToMinPoint (A : RangeArrayType) return integer is -- Used in testing ------------------------------------------------------------ begin return A(A'left).min ; end function ToMinPoint ; ------------------------------------------------------------ function ToMinPoint (A : RangeArrayType) return integer_vector is -- Used in testing ------------------------------------------------------------ variable result : integer_vector(A'range) ; begin for i in A'range loop result(i) := A(i).min ; end loop ; return result ; end function ToMinPoint ; ------------------------------------------------------------ procedure ToRandPoint( ------------------------------------------------------------ variable RV : inout RandomPType ; constant BinVal : in RangeArrayType ; variable result : out integer ) is begin result := RV.RandInt(BinVal(BinVal'left).min, BinVal(BinVal'left).max) ; end procedure ToRandPoint ; ------------------------------------------------------------ procedure ToRandPoint( ------------------------------------------------------------ variable RV : inout RandomPType ; constant BinVal : in RangeArrayType ; variable result : out integer_vector ) is variable VectorVal : integer_vector(BinVal'range) ; begin for i in BinVal'range loop VectorVal(i) := RV.RandInt(BinVal(i).min, BinVal(i).max) ; end loop ; result := VectorVal ; end procedure ToRandPoint ; ------------------------------------------------------------ -- Local. Get first word from a string function GetWord (Message : string) return string is ------------------------------------------------------------ alias aMessage : string( 1 to Message'length) is Message ; begin for i in aMessage'range loop if aMessage(i) = ' ' or aMessage(i) = HT then return aMessage(1 to i-1) ; end if ; end loop ; return aMessage ; end function GetWord ; ------------------------------------------------------------ -- Local -- long term move to MessagePkg? Used by WriteCovDb procedure WriteMessage ( file f : text ; variable Message : inout MessagePType ) is ------------------------------------------------------------ variable buf : line ; begin for i in 1 to Message.GetCount loop write(buf, string'(Message.Get(i))) ; writeline(f, buf) ; end loop ; end procedure WriteMessage ; ------------------------------------------------------------------------------------------ -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ------------------------------------------------------------------------------------------ type CovPType is protected body -- Name Data Structure variable CovNameVar : NamePType ; variable CovMessageVar : MessagePType ; -- Handle into Vendor Data Structure -- VendorCov variable VendorCovHandleVar : VendorCovHandleType := 0 ; -- VendorCov -- CoverageBin Data Structures type RangeArrayPtrType is access RangeArrayType ; type CovBinBaseTempType is record BinVal : RangeArrayPtrType ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; PercentCov : real ; --! OrderCount : integer ; Name : line ; end record CovBinBaseTempType ; type CovBinTempType is array (natural range <>) of CovBinBaseTempType ; type CovBinPtrType is access CovBinTempType ; variable CovBinPtr : CovBinPtrType ; variable NumBins : integer := 0 ; variable BinValLength : integer := 1 ; --! variable OrderCount : integer := 0 ; -- for statistics variable ItemCount : integer := 0 ; -- Count of randomizations variable LastIndex : integer := 1 ; -- Index of last Stimulus Gen or Coverage Collection variable LastStimGenIndex : integer := 1 ; -- Index of last stimulus gen -- Internal Modes and Names variable NextPointModeVar : NextPointModeType := RANDOM ; variable IllegalMode : IllegalModeType := ILLEGAL_ON ; variable IllegalModeLevel : AlertType := ERROR ; variable WeightMode : WeightModeType := AT_LEAST ; variable WeightScale : real := 1.0 ; variable ThresholdingEnable : boolean := FALSE ; -- thresholding disabled by default variable CovThreshold : real := 45.0 ; variable CovTarget : real := 100.0 ; variable MergingEnable : boolean := FALSE ; -- merging disabled by default variable CountMode : CountModeType := COUNT_FIRST ; -- Randomization Variable variable RV : RandomPType ; variable RvSeedInit : boolean := FALSE ; file WriteBinFile : text ; variable WriteBinFileInit : boolean := FALSE ; variable UsingLocalFile : boolean := FALSE ; variable AlertLogIDVar : AlertLogIDType := OSVVM_ALERTLOG_ID ; -- file WriteCovDbFile : text ; -- variable WriteCovDbFileInit : boolean := FALSE ; -- Local WriteBin and WriteCovHoles formatting settings, defaults determined by CoverageGlobals variable WritePassFailVar : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; variable WriteBinInfoVar : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; variable WriteCountVar : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; variable WriteAnyIllegalVar : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; variable WritePrefixVar : NamePType ; variable PassNameVar : NamePType ; variable FailNameVar : NamePType ; ------------------------------------------------------------ procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) is ------------------------------------------------------------ begin WriteBinFileInit := TRUE ; file_open( WriteBinFile , FileName , OpenKind ); end procedure FileOpenWriteBin ; ------------------------------------------------------------ procedure FileCloseWriteBin is ------------------------------------------------------------ begin WriteBinFileInit := FALSE ; file_close( WriteBinFile) ; end procedure FileCloseWriteBin ; ------------------------------------------------------------ procedure SetAlertLogID (A : AlertLogIDType) is ------------------------------------------------------------ begin AlertLogIDVar := A ; end procedure SetAlertLogID ; ------------------------------------------------------------ procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is ------------------------------------------------------------ begin AlertLogIDVar := GetAlertLogID(Name, ParentID, CreateHierarchy) ; if not RvSeedInit then -- Init seed if not initialized RV.InitSeed(Name) ; RvSeedInit := TRUE ; end if ; end procedure SetAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogID return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogIDVar ; end function GetAlertLogID ; -- ------------------------------------------------------------ -- procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is -- ------------------------------------------------------------ -- begin -- WriteCovDbFileInit := TRUE ; -- file_open( WriteCovDbFile , FileName , OpenKind ); -- end procedure FileOpenWriteCovDb ; -- -- ------------------------------------------------------------ -- procedure FileCloseWriteCovDb is -- ------------------------------------------------------------ -- begin -- WriteCovDbFileInit := FALSE ; -- file_close( WriteCovDbFile ); -- end procedure FileCloseWriteCovDb ; ------------------------------------------------------------ procedure SetName (Name : String) is ------------------------------------------------------------ begin CovNameVar.Set(Name) ; -- Update if name updated after model created -- VendorCov if IsInitialized then -- VendorCov VendorCovSetName(VendorCovHandleVar, Name) ; -- VendorCov end if ; -- VendorCov if not RvSeedInit then -- Init seed if not initialized RV.InitSeed(Name) ; RvSeedInit := TRUE ; end if ; end procedure SetName ; ------------------------------------------------------------ impure function SetName (Name : String) return string is ------------------------------------------------------------ begin SetName(Name) ; -- call procedure above return Name ; end function SetName ; ------------------------------------------------------------ impure function GetName return String is ------------------------------------------------------------ begin return CovNameVar.Get("") ; end function GetName ; ------------------------------------------------------------ impure function GetCovModelName return String is ------------------------------------------------------------ begin if CovNameVar.IsSet then -- return Name if set return CovNameVar.Get ; elsif AlertLogIDVar /= OSVVM_ALERTLOG_ID then -- otherwise return AlertLogName if it is set return GetAlertLogName(AlertLogIDVar) ; elsif CovMessageVar.IsSet then -- otherwise Get the first word of the Message if it is set return GetWord(string'(CovMessageVar.Get(1))) ; else return "" ; end if ; end function GetCovModelName ; ------------------------------------------------------------ impure function GetNamePlus(prefix, suffix : string) return String is ------------------------------------------------------------ begin if CovNameVar.IsSet then -- return Name if set return prefix & CovNameVar.Get & suffix ; elsif AlertLogIDVar = OSVVM_ALERTLOG_ID and CovMessageVar.IsSet then -- If AlertLogID not set, then use Message return prefix & GetWord(string'(CovMessageVar.Get(1))) & suffix ; else return "" ; end if ; end function GetNamePlus ; ------------------------------------------------------------ procedure SetMessage (Message : String) is ------------------------------------------------------------ begin CovMessageVar.Set(Message) ; -- VendorCov update if name updated after model created if IsInitialized then -- VendorCov -- Refine this? If CovNameVar or AlertLogIDName is set, -- VendorCov -- it may be set to the same name again. -- VendorCov VendorCovSetName(VendorCovHandleVar, GetCovModelName) ; -- VendorCov end if ; -- VendorCov if not RvSeedInit then -- Init seed if not initialized RV.InitSeed(Message) ; RvSeedInit := TRUE ; end if ; end procedure SetMessage ; ------------------------------------------------------------ procedure SetNextPointMode (A : NextPointModeType) is ------------------------------------------------------------ begin NextPointModeVar := A ; end procedure SetNextPointMode ; ------------------------------------------------------------ procedure SetIllegalMode (A : IllegalModeType) is ------------------------------------------------------------ begin IllegalMode := A ; if IllegalMode = ILLEGAL_FAILURE then IllegalModeLevel := FAILURE ; else IllegalModeLevel := ERROR ; end if ; end procedure SetIllegalMode ; ------------------------------------------------------------ procedure SetWeightMode (A : WeightModeType; Scale : real := 1.0) is ------------------------------------------------------------ variable buf : line ; begin WeightMode := A ; WeightScale := Scale ; if (WeightMode = REMAIN_EXP) and (WeightScale > 2.0) then Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.SetWeightMode:" & " WeightScale > 2.0 and large Counts can cause RandCovPoint to fail due to integer values out of range", WARNING) ; end if ; if (WeightScale < 1.0) and (WeightMode = REMAIN_WEIGHT or WeightMode = REMAIN_SCALED) then Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.SetWeightMode:" & " WeightScale must be > 1.0 when WeightMode = REMAIN_WEIGHT or WeightMode = REMAIN_SCALED", FAILURE) ; WeightScale := 1.0 ; end if; if WeightScale <= 0.0 then Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.SetWeightMode:" & " WeightScale must be > 0.0", FAILURE) ; WeightScale := 1.0 ; end if; end procedure SetWeightMode ; ------------------------------------------------------------ -- pt local for now -- file formal parameter not allowed with a public method procedure WriteBinName ( file f : text ; S : string ; Prefix : string := "%% " ) is ------------------------------------------------------------ variable MessageCount : integer ; variable MessageIndex : integer := 1 ; variable buf : line ; begin MessageCount := CovMessageVar.GetCount ; if MessageCount = 0 then write(buf, Prefix & S & GetCovModelName) ; -- Print name when no message writeline(f, buf) ; else if CovNameVar.IsSet then -- Print Name if set write(buf, Prefix & S & CovNameVar.Get) ; elsif AlertLogIDVar /= OSVVM_ALERTLOG_ID then -- otherwise Print AlertLogName if it is set write(buf, Prefix & S & string'(GetAlertLogName(AlertLogIDVar)) ) ; else -- otherwise print the first line of the message MessageIndex := 2 ; write(buf, Prefix & S & string'(CovMessageVar.Get(1))) ; end if ; writeline(f, buf) ; for i in MessageIndex to MessageCount loop write(buf, Prefix & string'(CovMessageVar.Get(i))) ; writeline(f, buf) ; end loop ; end if ; end procedure WriteBinName ; ------------------------------------------------------------ procedure DeallocateMessage is ------------------------------------------------------------ begin CovMessageVar.Deallocate ; end procedure DeallocateMessage ; ------------------------------------------------------------ procedure DeallocateName is ------------------------------------------------------------ begin CovNameVar.Clear ; end procedure DeallocateName ; ------------------------------------------------------------ procedure SetThresholding (A : boolean := TRUE ) is ------------------------------------------------------------ begin ThresholdingEnable := A ; end procedure SetThresholding ; ------------------------------------------------------------ procedure SetCovThreshold (Percent : real) is ------------------------------------------------------------ begin ThresholdingEnable := TRUE ; if Percent >= 0.0 then CovThreshold := Percent + 0.0001 ; -- used in less than else CovThreshold := 0.0001 ; -- used in less than Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.SetCovThreshold:" & " Invalid Threshold Value " & real'image(Percent), FAILURE) ; end if ; end procedure SetCovThreshold ; ------------------------------------------------------------ procedure SetCovTarget (Percent : real) is ------------------------------------------------------------ begin CovTarget := Percent ; end procedure SetCovTarget ; ------------------------------------------------------------ impure function GetCovTarget return real is ------------------------------------------------------------ begin return CovTarget ; end function GetCovTarget ; ------------------------------------------------------------ procedure SetMerging (A : boolean := TRUE ) is ------------------------------------------------------------ begin MergingEnable := A ; end procedure SetMerging ; ------------------------------------------------------------ procedure SetCountMode (A : CountModeType) is ------------------------------------------------------------ begin CountMode := A ; end procedure SetCountMode ; ------------------------------------------------------------ procedure InitSeed (S : string ) is ------------------------------------------------------------ begin RV.InitSeed(S) ; RvSeedInit := TRUE ; end procedure InitSeed ; ------------------------------------------------------------ impure function InitSeed (S : string ) return string is ------------------------------------------------------------ begin RV.InitSeed(S) ; RvSeedInit := TRUE ; return S ; end function InitSeed ; ------------------------------------------------------------ procedure InitSeed (I : integer ) is ------------------------------------------------------------ begin RV.InitSeed(I) ; RvSeedInit := TRUE ; end procedure InitSeed ; ------------------------------------------------------------ procedure SetSeed (RandomSeedIn : RandomSeedType ) is ------------------------------------------------------------ begin RV.SetSeed(RandomSeedIn) ; RvSeedInit := TRUE ; end procedure SetSeed ; ------------------------------------------------------------ impure function GetSeed return RandomSeedType is ------------------------------------------------------------ begin return RV.GetSeed ; end function GetSeed ; ------------------------------------------------------------ procedure SetReportOptions ( ------------------------------------------------------------ WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is begin if WritePassFail /= COV_OPT_INIT_PARM_DETECT then WritePassFailVar := WritePassFail ; end if ; if WriteBinInfo /= COV_OPT_INIT_PARM_DETECT then WriteBinInfoVar := WriteBinInfo ; end if ; if WriteCount /= COV_OPT_INIT_PARM_DETECT then WriteCountVar := WriteCount ; end if ; if WriteAnyIllegal /= COV_OPT_INIT_PARM_DETECT then WriteAnyIllegalVar := WriteAnyIllegal ; end if ; if WritePrefix /= OSVVM_STRING_INIT_PARM_DETECT then WritePrefixVar.Set(WritePrefix) ; end if ; if PassName /= OSVVM_STRING_INIT_PARM_DETECT then PassNameVar.Set(PassName) ; end if ; if FailName /= OSVVM_STRING_INIT_PARM_DETECT then FailNameVar.Set(FailName) ; end if ; end procedure SetReportOptions ; ------------------------------------------------------------ procedure SetBinSize (NewNumBins : integer) is -- Sets a CovBin to a particular size -- Use for small bins to save space or large bins to -- suppress the resize and copy as a CovBin autosizes. ------------------------------------------------------------ variable oldCovBinPtr : CovBinPtrType ; begin if CovBinPtr = NULL then CovBinPtr := new CovBinTempType(1 to NewNumBins) ; elsif NewNumBins > CovBinPtr'length then -- make message bigger oldCovBinPtr := CovBinPtr ; CovBinPtr := new CovBinTempType(1 to NewNumBins) ; CovBinPtr.all(1 to NumBins) := oldCovBinPtr.all(1 to NumBins) ; deallocate(oldCovBinPtr) ; end if ; end procedure SetBinSize ; ------------------------------------------------------------ -- pt local procedure CheckBinValLength( CurBinValLength : integer ; Caller : string ) is begin if NumBins = 0 then BinValLength := CurBinValLength ; -- number of points in cross else AlertIf(AlertLogIDVar, BinValLength /= CurBinValLength, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg." & Caller & ":" & " Cross coverage bins of different dimensions prohibited", FAILURE) ; end if; end procedure CheckBinValLength ; ------------------------------------------------------------ -- pt local impure function NormalizeNumBins( ReqNumBins : integer ) return integer is variable NormNumBins : integer := MIN_NUM_BINS ; begin while NormNumBins < ReqNumBins loop NormNumBins := NormNumBins + MIN_NUM_BINS ; end loop ; return NormNumBins ; end function NormalizeNumBins ; ------------------------------------------------------------ -- pt local procedure GrowBins (ReqNumBins : integer) is variable oldCovBinPtr : CovBinPtrType ; variable NewNumBins : integer ; begin NewNumBins := NumBins + ReqNumBins ; if CovBinPtr = NULL then CovBinPtr := new CovBinTempType(1 to NormalizeNumBins(NewNumBins)) ; elsif NewNumBins > CovBinPtr'length then -- make message bigger oldCovBinPtr := CovBinPtr ; CovBinPtr := new CovBinTempType(1 to NormalizeNumBins(NewNumBins)) ; CovBinPtr.all(1 to NumBins) := oldCovBinPtr.all(1 to NumBins) ; deallocate(oldCovBinPtr) ; end if ; end procedure GrowBins ; ------------------------------------------------------------ -- pt local, called by InsertBin -- Finds index of bin if it is inside an existing bins procedure FindBinInside( BinVal : RangeArrayType ; Position : out integer ; FoundInside : out boolean ) is begin Position := NumBins + 1 ; FoundInside := FALSE ; FindLoop : for i in NumBins downto 1 loop -- skip this CovBin if CovPoint is not in it next FindLoop when not inside(BinVal, CovBinPtr(i).BinVal.all) ; Position := i ; FoundInside := TRUE ; exit ; end loop ; end procedure FindBinInside ; ------------------------------------------------------------ -- pt local -- Inserts values into a new bin. -- Called by InsertBin procedure InsertNewBin( BinVal : RangeArrayType ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; Name : string ; PercentCov : real ) is begin if (not IsInitialized) then -- VendorCov if (BinVal'length > 1) then -- Cross Bin -- VendorCov VendorCovHandleVar := VendorCovCrossCreate(GetCovModelName) ; -- VendorCov else -- VendorCov VendorCovHandleVar := VendorCovPointCreate(GetCovModelName); -- VendorCov end if; -- VendorCov end if; -- VendorCov VendorCovBinAdd(VendorCovHandleVar, ToVendorCovBinVal(BinVal), Action, AtLeast, Name) ; -- VendorCov NumBins := NumBins + 1 ; CovBinPtr.all(NumBins).BinVal := new RangeArrayType'(BinVal) ; CovBinPtr.all(NumBins).Action := Action ; CovBinPtr.all(NumBins).Count := Count ; CovBinPtr.all(NumBins).AtLeast := AtLeast ; CovBinPtr.all(NumBins).Weight := Weight ; CovBinPtr.all(NumBins).Name := new String'(Name) ; CovBinPtr.all(NumBins).PercentCov := PercentCov ; --! CovBinPtr.all(NumBins).OrderCount := 0 ; --- Metrics for evaluating randomization order Temp end procedure InsertNewBin ; ------------------------------------------------------------ -- pt local -- Inserts values into a new bin. -- Called by InsertBin procedure MergeBin ( Position : Natural ; Count : integer ; AtLeast : integer ; Weight : integer ) is begin CovBinPtr.all(Position).Count := CovBinPtr.all(Position).Count + Count ; CovBinPtr.all(Position).AtLeast := CovBinPtr.all(Position).AtLeast + AtLeast ; CovBinPtr.all(Position).Weight := CovBinPtr.all(Position).Weight + Weight ; CovBinPtr.all(Position).PercentCov := CalcPercentCov( Count => CovBinPtr.all(Position).Count, AtLeast => CovBinPtr.all(Position).AtLeast ) ; end procedure MergeBin ; ------------------------------------------------------------ -- pt local -- All insertion comes here -- Enforces the general insertion use model: -- Earlier bins supercede later bins - except with COUNT_ALL -- Add Illegal and Ignore bins first to remove regions of larger count bins -- Later ignore bins can be used to miss an illegal catch-all -- Add Illegal bins last as a catch-all to find things that missed other bins procedure InsertBin( BinVal : RangeArrayType ; Action : integer ; Count : integer ; AtLeast : integer ; Weight : integer ; Name : string ) is variable Position : integer ; variable FoundInside : boolean ; variable PercentCov : real ; begin PercentCov := CalcPercentCov(Count => Count, AtLeast => AtLeast) ; if not MergingEnable then InsertNewBin(BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ; else -- handle merging -- future optimization, FindBinInside only checks against Ignore and Illegal bins FindBinInside(BinVal, Position, FoundInside) ; if not FoundInside then InsertNewBin(BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ; elsif Action = COV_COUNT then -- when check only ignore and illegal bins, only action is to drop if CovBinPtr.all(Position).Action /= COV_COUNT then null ; -- drop count bin when it is inside a Illegal or Ignore bin elsif CovBinPtr.all(Position).BinVal.all = BinVal and CovBinPtr.all(Position).Name.all = Name then -- Bins match, so merge the count values MergeBin (Position, Count, AtLeast, Weight) ; else -- Bins overlap, but do not match, insert new bin InsertNewBin(BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ; end if; elsif Action = COV_IGNORE then -- when check only ignore and illegal bins, only action is to report error if CovBinPtr.all(Position).Action = COV_COUNT then InsertNewBin(BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ; else Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.InsertBin (AddBins/AddCross):" & " ignore bin dropped. It is a subset of prior bin", ERROR) ; end if; elsif Action = COV_ILLEGAL then -- when check only ignore and illegal bins, only action is to report error if CovBinPtr.all(Position).Action = COV_COUNT then InsertNewBin(BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ; else Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.InsertBin (AddBins/AddCross):" & " illegal bin dropped. It is a subset of prior bin", ERROR) ; end if; end if ; end if ; -- merging enabled end procedure InsertBin ; ------------------------------------------------------------ procedure AddBins ( ------------------------------------------------------------ Name : String ; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) is variable calcAtLeast : integer ; variable calcWeight : integer ; begin CheckBinValLength( 1, "AddBins") ; GrowBins(CovBin'length) ; for i in CovBin'range loop if CovBin(i).Action = COV_COUNT then calcAtLeast := maximum(AtLeast, CovBin(i).AtLeast) ; calcWeight := maximum(Weight, CovBin(i).Weight) ; else calcAtLeast := 0 ; calcWeight := 0 ; end if ; InsertBin( BinVal => CovBin(i).BinVal, Action => CovBin(i).Action, Count => CovBin(i).Count, AtLeast => calcAtLeast, Weight => calcWeight, Name => Name ) ; end loop ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins ( Name : String ; AtLeast : integer ; CovBin : CovBinType ) is ------------------------------------------------------------ begin AddBins(Name, AtLeast, 0, CovBin) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins (Name : String ; CovBin : CovBinType) is ------------------------------------------------------------ begin AddBins(Name, 0, 0, CovBin) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins ( AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) is ------------------------------------------------------------ begin AddBins("", AtLeast, Weight, CovBin) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins ( AtLeast : integer ; CovBin : CovBinType ) is ------------------------------------------------------------ begin AddBins("", AtLeast, 0, CovBin) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins ( CovBin : CovBinType ) is ------------------------------------------------------------ begin AddBins("", 0, 0, CovBin) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddCross( ------------------------------------------------------------ Name : string ; AtLeast : integer ; Weight : integer ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) is constant BIN_LENS : integer_vector := BinLengths( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 ) ; constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ; variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ; variable CrossBins : CovBinType(BinIndex'range) ; variable calcAction, calcCount, calcAtLeast, calcWeight : integer ; variable calcBinVal : RangeArrayType(BinIndex'range) ; begin CheckBinValLength( BIN_LENS'length, "AddCross") ; GrowBins(NUM_NEW_BINS) ; calcCount := 0 ; for MatrixIndex in 1 to NUM_NEW_BINS loop CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 ) ; calcAction := MergeState(CrossBins) ; calcBinVal := MergeBinVal(CrossBins) ; calcAtLeast := MergeAtLeast( calcAction, AtLeast, CrossBins) ; calcWeight := MergeWeight ( calcAction, Weight, CrossBins) ; InsertBin(calcBinVal, calcAction, calcCount, calcAtLeast, calcWeight, Name) ; IncBinIndex( BinIndex, BIN_LENS) ; -- increment right most one, then if overflow, increment next end loop ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross( ------------------------------------------------------------ Name : string ; AtLeast : integer ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) is begin AddCross(Name, AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 ) ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross( ------------------------------------------------------------ Name : string ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) is begin AddCross(Name, 0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 ) ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross( ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) is begin AddCross("", AtLeast, Weight, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 ) ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross( ------------------------------------------------------------ AtLeast : integer ; Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) is begin AddCross("", AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 ) ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross( ------------------------------------------------------------ Bin1, Bin2 : CovBinType ; Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN ) is begin AddCross("", 0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 ) ; end procedure AddCross ; ------------------------------------------------------------ procedure Deallocate is ------------------------------------------------------------ begin for i in 1 to NumBins loop deallocate(CovBinPtr(i).BinVal) ; deallocate(CovBinPtr(i).Name) ; end loop ; deallocate(CovBinPtr) ; DeallocateName ; DeallocateMessage ; -- Restore internal variables to their default values VendorCovHandleVar := 0 ; NumBins := 0 ; BinValLength := 1 ; --! OrderCount := 0 ; ItemCount := 0 ; LastIndex := 1 ; LastStimGenIndex := 1 ; NextPointModeVar := RANDOM ; IllegalMode := ILLEGAL_ON ; IllegalModeLevel := ERROR ; WeightMode := AT_LEAST ; WeightScale := 1.0 ; ThresholdingEnable := FALSE ; CovThreshold := 45.0 ; CovTarget := 100.0 ; MergingEnable := FALSE ; CountMode := COUNT_FIRST ; RvSeedInit := FALSE ; AlertLogIDVar := OSVVM_ALERTLOG_ID ; -- RvSeedInit := FALSE ; WritePassFailVar := COV_OPT_INIT_PARM_DETECT ; WriteBinInfoVar := COV_OPT_INIT_PARM_DETECT ; WriteCountVar := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegalVar := COV_OPT_INIT_PARM_DETECT ; WritePrefixVar.deallocate ; PassNameVar.deallocate ; FailNameVar.deallocate ; end procedure deallocate ; ------------------------------------------------------------ -- Local procedure ICoverIndex( Index : integer ; CovPoint : integer_vector ) is ------------------------------------------------------------ variable buf : line ; begin -- Update Count, PercentCov CovBinPtr(Index).Count := CovBinPtr(Index).Count + CovBinPtr(Index).action ; VendorCovBinInc(VendorCovHandleVar, Index); -- VendorCov CovBinPtr(Index).PercentCov := CalcPercentCov( Count => CovBinPtr.all(Index).Count, AtLeast => CovBinPtr.all(Index).AtLeast ) ; --! -- OrderCount handling - Statistics --! OrderCount := OrderCount + 1 ; --! CovBinPtr(Index).OrderCount := OrderCount + CovBinPtr(Index).OrderCount ; if CovBinPtr(Index).action = COV_ILLEGAL then if IllegalMode /= ILLEGAL_OFF then if CovPoint = NULL_INTV then alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ICoverLast:" & " Value randomized is in an illegal bin.", IllegalModeLevel) ; else write(buf, CovPoint) ; alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ICover:" & " Value " & buf.all & " is in an illegal bin.", IllegalModeLevel) ; deallocate(buf) ; end if ; else IncAlertCount(AlertLogIDVar, ERROR) ; -- silent alert. end if ; end if ; end procedure ICoverIndex ; ------------------------------------------------------------ procedure ICoverLast is ------------------------------------------------------------ begin ICoverIndex(LastStimGenIndex, NULL_INTV) ; end procedure ICoverLast ; ------------------------------------------------------------ procedure ICover ( CovPoint : integer) is ------------------------------------------------------------ begin ICover((1=> CovPoint)) ; end procedure ICover ; ------------------------------------------------------------ procedure ICover( CovPoint : integer_vector) is ------------------------------------------------------------ begin if CovPoint'length /= BinValLength then Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg." & " ICover: CovPoint length = " & to_string(CovPoint'length) & " does not match Coverage Bin dimensions = " & to_string(BinValLength), FAILURE) ; -- Search LastStimGenIndex first. Important it is not LastIndex seen by ICover below. -- If find an object in a sentinal bin - only looks in sentinal bin after that point elsif CountMode = COUNT_FIRST and inside(CovPoint, CovBinPtr(LastStimGenIndex).BinVal.all) then ICoverIndex(LastStimGenIndex, CovPoint) ; else CovLoop : for i in 1 to NumBins loop -- skip this CovBin if CovPoint is not in it next CovLoop when not inside(CovPoint, CovBinPtr(i).BinVal.all) ; -- Mark Covered LastIndex := i ; -- Mark found index ICoverIndex(i, CovPoint) ; exit CovLoop when CountMode = COUNT_FIRST ; -- only find first one end loop CovLoop ; end if ; end procedure ICover ; ------------------------------------------------------------ procedure ClearCov is ------------------------------------------------------------ begin for i in 1 to NumBins loop CovBinPtr(i).Count := 0 ; CovBinPtr(i).PercentCov := CalcPercentCov( Count => CovBinPtr.all(i).Count, AtLeast => CovBinPtr.all(i).AtLeast ) ; --! CovBinPtr(i).OrderCount := 0 ; end loop ; --! OrderCount := 0 ; end procedure ClearCov ; ------------------------------------------------------------ -- deprecated procedure SetCovZero is ------------------------------------------------------------ begin ClearCov ; end procedure SetCovZero ; ------------------------------------------------------------ impure function IsInitialized return boolean is ------------------------------------------------------------ begin return NumBins > 0 ; end function IsInitialized ; ------------------------------------------------------------ impure function GetMinCov return real is ------------------------------------------------------------ variable MinCov : real := real'right ; -- big number begin CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < MinCov then MinCov := CovBinPtr(i).PercentCov ; end if ; end loop CovLoop ; return MinCov ; end function GetMinCov ; ------------------------------------------------------------ impure function GetMinCount return integer is ------------------------------------------------------------ variable MinCount : integer := integer'right ; -- big number begin CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < MinCount then MinCount := CovBinPtr(i).Count ; end if ; end loop CovLoop ; return MinCount ; end function GetMinCount ; ------------------------------------------------------------ impure function GetMaxCov return real is ------------------------------------------------------------ variable MaxCov : real := 0.0 ; begin CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov > MaxCov then MaxCov := CovBinPtr(i).PercentCov ; end if ; end loop CovLoop ; return MaxCov ; end function GetMaxCov ; ------------------------------------------------------------ impure function GetMaxCount return integer is ------------------------------------------------------------ variable MaxCount : integer := 0 ; begin CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count > MaxCount then MaxCount := CovBinPtr(i).Count ; end if ; end loop CovLoop ; return MaxCount ; end function GetMaxCount ; ------------------------------------------------------------ impure function CountCovHoles ( PercentCov : real ) return integer is ------------------------------------------------------------ variable HoleCount : integer := 0 ; begin CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < PercentCov then HoleCount := HoleCount + 1 ; end if ; end loop CovLoop ; return HoleCount ; end function CountCovHoles ; ------------------------------------------------------------ impure function CountCovHoles return integer is ------------------------------------------------------------ begin return CountCovHoles(CovTarget) ; end function CountCovHoles ; ------------------------------------------------------------ impure function IsCovered ( PercentCov : real ) return boolean is ------------------------------------------------------------ begin -- AlertIf(NumBins < 1, OSVVM_ALERTLOG_ID, "CoveragePkg.IsCovered: Empty Coverage Model", failure) ; return CountCovHoles(PercentCov) = 0 ; end function IsCovered ; ------------------------------------------------------------ impure function IsCovered return boolean is ------------------------------------------------------------ begin -- AlertIf(NumBins < 1, OSVVM_ALERTLOG_ID, "CoveragePkg.IsCovered: Empty Coverage Model", failure) ; return CountCovHoles(CovTarget) = 0 ; end function IsCovered ; ------------------------------------------------------------ impure function GetCov ( PercentCov : real ) return real is ------------------------------------------------------------ variable TotalCovGoal, TotalCovCount, ScaledCovGoal : integer := 0 ; begin BinLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT then ScaledCovGoal := integer(ceil(PercentCov * real(CovBinPtr(i).AtLeast)/100.0)) ; TotalCovGoal := TotalCovGoal + ScaledCovGoal ; if CovBinPtr(i).Count <= ScaledCovGoal then TotalCovCount := TotalCovCount + CovBinPtr(i).Count ; else -- do not count the extra values that exceed their cov goal TotalCovCount := TotalCovCount + ScaledCovGoal ; end if ; end if ; end loop BinLoop ; return 100.0 * real(TotalCovCount) / real(TotalCovGoal) ; end function GetCov ; ------------------------------------------------------------ impure function GetCov return real is ------------------------------------------------------------ variable TotalCovGoal, TotalCovCount : integer := 0 ; begin return GetCov( CovTarget ) ; end function GetCov ; ------------------------------------------------------------ impure function GetItemCount return integer is ------------------------------------------------------------ begin return ItemCount ; end function GetItemCount ; ------------------------------------------------------------ impure function GetTotalCovGoal ( PercentCov : real ) return integer is ------------------------------------------------------------ variable TotalCovGoal, ScaledCovGoal : integer := 0 ; begin BinLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT then ScaledCovGoal := integer(ceil(PercentCov * real(CovBinPtr(i).AtLeast)/100.0)) ; TotalCovGoal := TotalCovGoal + ScaledCovGoal ; end if ; end loop BinLoop ; return TotalCovGoal ; end function GetTotalCovGoal ; ------------------------------------------------------------ impure function GetTotalCovGoal return integer is ------------------------------------------------------------ begin return GetTotalCovGoal(CovTarget) ; end function GetTotalCovGoal ; -- Return Index Values ------------------------------------------------------------ impure function GetNumBins return integer is ------------------------------------------------------------ begin return NumBins ; end function GetNumBins ; ------------------------------------------------------------ impure function GetLastIndex return integer is ------------------------------------------------------------ begin return LastIndex ; end function GetLastIndex ; ------------------------------------------------------------ impure function CalcWeight ( BinIndex : integer ; MaxCovPercent : real ) return integer is -- pt local ------------------------------------------------------------ begin case WeightMode is when AT_LEAST => -- AtLeast return CovBinPtr(BinIndex).AtLeast ; when WEIGHT => -- Weight return CovBinPtr(BinIndex).Weight ; when REMAIN => -- (Adjust * AtLeast) - Count --?? simpler integer( Ceil (MaxCovPercent - CovBinPtr(BinIndex).PercentCov)) * CovBinPtr(BinIndex).AtLeast return integer( Ceil( MaxCovPercent * real(CovBinPtr(BinIndex).AtLeast)/100.0)) - CovBinPtr(BinIndex).Count ; when REMAIN_EXP => -- Weight * (REMAIN **WeightScale) -- Experimental may be removed -- CAUTION: for large numbers and/or WeightScale > 2.0, result can be > 2**31 (max integer value) -- both Weight and WeightScale default to 1 return CovBinPtr(BinIndex).Weight * integer( Ceil ( ( (MaxCovPercent * real(CovBinPtr(BinIndex).AtLeast)/100.0) - real(CovBinPtr(BinIndex).Count) ) ** WeightScale ) ); when REMAIN_SCALED => -- (WeightScale * Adjust * AtLeast) - Count -- Experimental may be removed -- Biases remainder toward AT_LEAST value. -- WeightScale must be > 1.0 return integer( Ceil( WeightScale * MaxCovPercent * real(CovBinPtr(BinIndex).AtLeast)/100.0)) - CovBinPtr(BinIndex).Count ; when REMAIN_WEIGHT => -- Weight * ((WeightScale * Adjust * AtLeast) - Count) -- Experimental may be removed -- WeightScale must be > 1.0 return CovBinPtr(BinIndex).Weight * ( integer( Ceil( WeightScale * MaxCovPercent * real(CovBinPtr(BinIndex).AtLeast)/100.0)) - CovBinPtr(BinIndex).Count) ; end case ; end function CalcWeight ; ------------------------------------------------------------ impure function GetRandIndex ( CovTargetPercent : real ) return integer is ------------------------------------------------------------ variable WeightVec : integer_vector(0 to NumBins-1) ; -- Prep for change to DistInt variable MaxCovPercent : real ; variable MinCovPercent : real ; begin ItemCount := ItemCount + 1 ; MinCovPercent := GetMinCov ; if ThresholdingEnable then MaxCovPercent := MinCovPercent + CovThreshold ; if MinCovPercent < CovTargetPercent then -- Clip at CovTargetPercent until reach CovTargetPercent MaxCovPercent := minimum(MaxCovPercent, CovTargetPercent); end if ; else if MinCovPercent < CovTargetPercent then MaxCovPercent := CovTargetPercent ; else -- Done, Enable all bins MaxCovPercent := GetMaxCov + 1.0 ; -- MaxCovPercent := real'right ; -- weight scale issues end if ; end if ; CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < MaxCovPercent then -- Calculate Weight based on WeightMode -- Scale to current percentage goal: MaxCov which can be < or > 100.0 WeightVec(i-1) := CalcWeight(i, MaxCovPercent) ; else WeightVec(i-1) := 0 ; end if ; end loop CovLoop ; -- DistInt returns integer range 0 to Numbins-1 -- Caution: DistInt can fail when sum(WeightVec) > 2**31 -- See notes in CalcWeight for REMAIN_EXP LastStimGenIndex := 1 + RV.DistInt( WeightVec ) ; -- return range 1 to NumBins LastIndex := LastStimGenIndex ; return LastStimGenIndex ; end function GetRandIndex ; ------------------------------------------------------------ impure function GetRandIndex return integer is ------------------------------------------------------------ begin return GetRandIndex(CovTarget) ; end function GetRandIndex ; ------------------------------------------------------------ impure function GetIncIndex return integer is ------------------------------------------------------------ variable CurIndex : integer ; begin CurIndex := LastStimGenIndex ; LastStimGenIndex := (LastStimGenIndex mod NumBins) + 1 ; LastIndex := LastStimGenIndex ; return CurIndex ; end function GetIncIndex ; ------------------------------------------------------------ impure function GetMinIndex return integer is ------------------------------------------------------------ variable MinCov : real := real'right ; -- big number begin CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < MinCov then MinCov := CovBinPtr(i).PercentCov ; LastStimGenIndex := i ; end if ; end loop CovLoop ; LastIndex := LastStimGenIndex ; return LastStimGenIndex ; end function GetMinIndex ; ------------------------------------------------------------ impure function GetMaxIndex return integer is ------------------------------------------------------------ variable MaxCov : real := -1.0 ; begin CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov > MaxCov then MaxCov := CovBinPtr(i).PercentCov ; LastStimGenIndex := i ; end if ; end loop CovLoop ; LastIndex := LastStimGenIndex ; return LastStimGenIndex ; end function GetMaxIndex ; ------------------------------------------------------------ impure function GetNextIndex (Mode : NextPointModeType) return integer is ------------------------------------------------------------ begin case Mode is when RANDOM => return GetRandIndex ; when INCREMENT => return GetIncIndex ; when others => return GetMinIndex ; end case ; end function GetNextIndex; ------------------------------------------------------------ impure function GetNextIndex return integer is ------------------------------------------------------------ begin return GetNextIndex(NextPointModeVar) ; end function GetNextIndex ; -- Return BinVals ------------------------------------------------------------ impure function GetBinVal ( BinIndex : integer ) return RangeArrayType is ------------------------------------------------------------ begin return CovBinPtr( BinIndex ).BinVal.all ; end function GetBinVal ; ------------------------------------------------------------ impure function GetLastBinVal return RangeArrayType is ------------------------------------------------------------ begin return CovBinPtr( LastIndex ).BinVal.all ; end function GetLastBinVal ; ------------------------------------------------------------ impure function GetRandBinVal ( PercentCov : real ) return RangeArrayType is ------------------------------------------------------------ begin return CovBinPtr( GetRandIndex(PercentCov) ).BinVal.all ; -- GetBinVal end function GetRandBinVal ; ------------------------------------------------------------ impure function GetRandBinVal return RangeArrayType is ------------------------------------------------------------ begin -- use global coverage target return CovBinPtr( GetRandIndex( CovTarget ) ).BinVal.all ; -- GetBinVal end function GetRandBinVal ; ------------------------------------------------------------ impure function GetIncBinVal return RangeArrayType is ------------------------------------------------------------ begin return GetBinVal( GetIncIndex ) ; end function GetIncBinVal ; ------------------------------------------------------------ impure function GetMinBinVal return RangeArrayType is ------------------------------------------------------------ begin -- use global coverage target return GetBinVal( GetMinIndex ) ; end function GetMinBinVal ; ------------------------------------------------------------ impure function GetMaxBinVal return RangeArrayType is ------------------------------------------------------------ begin -- use global coverage target return GetBinVal( GetMaxIndex ) ; end function GetMaxBinVal ; ------------------------------------------------------------ impure function GetNextBinVal (Mode : NextPointModeType) return RangeArrayType is ------------------------------------------------------------ begin return GetBinVal(GetNextIndex(Mode)) ; end function GetNextBinVal; ------------------------------------------------------------ impure function GetNextBinVal return RangeArrayType is ------------------------------------------------------------ begin return GetBinVal(GetNextIndex(NextPointModeVar)) ; end function GetNextBinVal ; ------------------------------------------------------------ -- deprecated, see GetRandBinVal impure function RandCovBinVal ( PercentCov : real ) return RangeArrayType is ------------------------------------------------------------ begin return CovBinPtr( GetRandIndex(PercentCov) ).BinVal.all ; -- GetBinVal end function RandCovBinVal ; ------------------------------------------------------------ -- deprecated, see GetRandBinVal impure function RandCovBinVal return RangeArrayType is ------------------------------------------------------------ begin -- use global coverage target return CovBinPtr( GetRandIndex( CovTarget ) ).BinVal.all ; -- GetBinVal end function RandCovBinVal ; ------------------------------------------------------------ impure function GetHoleBinVal ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is ------------------------------------------------------------ variable HoleCount : integer := 0 ; variable buf : line ; begin CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < PercentCov then HoleCount := HoleCount + 1 ; if HoleCount = ReqHoleNum then return CovBinPtr(i).BinVal.all ; end if ; end if ; end loop CovLoop ; Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.GetHoleBinVal:" & " did not find a coverage hole. HoleCount = " & integer'image(HoleCount) & " ReqHoleNum = " & integer'image(ReqHoleNum), ERROR ) ; return CovBinPtr(NumBins).BinVal.all ; end function GetHoleBinVal ; ------------------------------------------------------------ impure function GetHoleBinVal ( PercentCov : real ) return RangeArrayType is ------------------------------------------------------------ begin return GetHoleBinVal(1, PercentCov) ; end function GetHoleBinVal ; ------------------------------------------------------------ impure function GetHoleBinVal ( ReqHoleNum : integer := 1 ) return RangeArrayType is ------------------------------------------------------------ begin return GetHoleBinVal(ReqHoleNum, CovTarget) ; end function GetHoleBinVal ; -- Return Points ------------------------------------------------------------ impure function ToRandPoint( BinVal : RangeArrayType ) return integer is -- pt local ------------------------------------------------------------ begin return RV.RandInt(BinVal(BinVal'left).min, BinVal(BinVal'left).max) ; end function ToRandPoint ; ------------------------------------------------------------ impure function ToRandPoint( BinVal : RangeArrayType ) return integer_vector is -- pt local ------------------------------------------------------------ variable CovPoint : integer_vector(BinVal'range) ; variable normCovPoint : integer_vector(1 to BinVal'length) ; begin for i in BinVal'range loop CovPoint(i) := RV.RandInt(BinVal(i).min, BinVal(i).max) ; end loop ; normCovPoint := CovPoint ; return normCovPoint ; end function ToRandPoint ; ------------------------------------------------------------ impure function GetPoint ( BinIndex : integer ) return integer is ------------------------------------------------------------ begin return ToRandPoint(GetBinVal(BinIndex)) ; end function GetPoint ; ------------------------------------------------------------ impure function GetPoint ( BinIndex : integer ) return integer_vector is ------------------------------------------------------------ begin return ToRandPoint(GetBinVal(BinIndex)) ; end function GetPoint ; ------------------------------------------------------------ impure function GetRandPoint return integer is ------------------------------------------------------------ begin return ToRandPoint(GetRandBinVal(CovTarget)) ; end function GetRandPoint ; ------------------------------------------------------------ impure function GetRandPoint ( PercentCov : real ) return integer is ------------------------------------------------------------ begin return ToRandPoint(GetRandBinVal(PercentCov)) ; end function GetRandPoint ; ------------------------------------------------------------ impure function GetRandPoint return integer_vector is ------------------------------------------------------------ begin return ToRandPoint(GetRandBinVal(CovTarget)) ; end function GetRandPoint ; ------------------------------------------------------------ impure function GetRandPoint ( PercentCov : real ) return integer_vector is ------------------------------------------------------------ begin return ToRandPoint(GetRandBinVal(PercentCov)) ; end function GetRandPoint ; ------------------------------------------------------------ impure function GetIncPoint return integer is ------------------------------------------------------------ begin return GetPoint(GetIncIndex) ; end function GetIncPoint ; ------------------------------------------------------------ impure function GetIncPoint return integer_vector is ------------------------------------------------------------ begin return GetPoint(GetIncIndex) ; end function GetIncPoint ; ------------------------------------------------------------ impure function GetMinPoint return integer is ------------------------------------------------------------ begin return ToRandPoint(GetBinVal( GetMinIndex )) ; end function GetMinPoint ; ------------------------------------------------------------ impure function GetMinPoint return integer_vector is ------------------------------------------------------------ begin return ToRandPoint(GetBinVal( GetMinIndex )) ; end function GetMinPoint ; ------------------------------------------------------------ impure function GetMaxPoint return integer is ------------------------------------------------------------ begin return ToRandPoint(GetBinVal( GetMaxIndex )) ; end function GetMaxPoint ; ------------------------------------------------------------ impure function GetMaxPoint return integer_vector is ------------------------------------------------------------ begin return ToRandPoint(GetBinVal( GetMaxIndex )) ; end function GetMaxPoint ; ------------------------------------------------------------ impure function GetNextPoint (Mode : NextPointModeType) return integer is ------------------------------------------------------------ begin return GetPoint(GetNextIndex(Mode)) ; end function GetNextPoint; ------------------------------------------------------------ impure function GetNextPoint (Mode : NextPointModeType) return integer_vector is ------------------------------------------------------------ begin return GetPoint(GetNextIndex(Mode)) ; end function GetNextPoint; ------------------------------------------------------------ impure function GetNextPoint return integer is ------------------------------------------------------------ begin return GetPoint(GetNextIndex(NextPointModeVar)) ; end function GetNextPoint ; ------------------------------------------------------------ impure function GetNextPoint return integer_vector is ------------------------------------------------------------ begin return GetPoint(GetNextIndex(NextPointModeVar)) ; end function GetNextPoint ; ------------------------------------------------------------ -- deprecated, see GetRandPoint impure function RandCovPoint return integer is ------------------------------------------------------------ begin return ToRandPoint(GetRandBinVal(CovTarget)) ; end function RandCovPoint ; ------------------------------------------------------------ -- deprecated, see GetRandPoint impure function RandCovPoint ( PercentCov : real ) return integer is ------------------------------------------------------------ begin return ToRandPoint(GetRandBinVal(PercentCov)) ; end function RandCovPoint ; ------------------------------------------------------------ -- deprecated, see GetRandPoint impure function RandCovPoint return integer_vector is ------------------------------------------------------------ begin return ToRandPoint(GetRandBinVal(CovTarget)) ; end function RandCovPoint ; ------------------------------------------------------------ -- deprecated, see GetRandPoint impure function RandCovPoint ( PercentCov : real ) return integer_vector is ------------------------------------------------------------ begin return ToRandPoint(GetRandBinVal(PercentCov)) ; end function RandCovPoint ; -- ------------------------------------------------------------ -- Intended as a stand in until we get a more general GetBin impure function GetBinInfo ( BinIndex : integer ) return CovBinBaseType is -- ------------------------------------------------------------ variable result : CovBinBaseType ; begin result.BinVal := ALL_RANGE; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBinInfo ; -- ------------------------------------------------------------ -- Intended as a stand in until we get a more general GetBin impure function GetBinValLength return integer is -- ------------------------------------------------------------ begin return BinValLength ; end function GetBinValLength ; -- Eventually the multiple GetBin functions will be replaced by a -- a single GetBin that returns CovBinBaseType with BinVal as an -- unconstrained element -- ------------------------------------------------------------ impure function GetBin ( BinIndex : integer ) return CovBinBaseType is -- ------------------------------------------------------------ variable result : CovBinBaseType ; begin result.BinVal := CovBinPtr(BinIndex).BinVal.all; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBin ; -- ------------------------------------------------------------ impure function GetBin ( BinIndex : integer ) return CovMatrix2BaseType is -- ------------------------------------------------------------ variable result : CovMatrix2BaseType ; begin result.BinVal := CovBinPtr(BinIndex).BinVal.all; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBin ; -- ------------------------------------------------------------ impure function GetBin ( BinIndex : integer ) return CovMatrix3BaseType is -- ------------------------------------------------------------ variable result : CovMatrix3BaseType ; begin result.BinVal := CovBinPtr(BinIndex).BinVal.all; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBin ; -- ------------------------------------------------------------ impure function GetBin ( BinIndex : integer ) return CovMatrix4BaseType is -- ------------------------------------------------------------ variable result : CovMatrix4BaseType ; begin result.BinVal := CovBinPtr(BinIndex).BinVal.all; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBin ; -- ------------------------------------------------------------ impure function GetBin ( BinIndex : integer ) return CovMatrix5BaseType is -- ------------------------------------------------------------ variable result : CovMatrix5BaseType ; begin result.BinVal := CovBinPtr(BinIndex).BinVal.all; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBin ; -- ------------------------------------------------------------ impure function GetBin ( BinIndex : integer ) return CovMatrix6BaseType is -- ------------------------------------------------------------ variable result : CovMatrix6BaseType ; begin result.BinVal := CovBinPtr(BinIndex).BinVal.all; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBin ; -- ------------------------------------------------------------ impure function GetBin ( BinIndex : integer ) return CovMatrix7BaseType is -- ------------------------------------------------------------ variable result : CovMatrix7BaseType ; begin result.BinVal := CovBinPtr(BinIndex).BinVal.all; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBin ; -- ------------------------------------------------------------ impure function GetBin ( BinIndex : integer ) return CovMatrix8BaseType is -- ------------------------------------------------------------ variable result : CovMatrix8BaseType ; begin result.BinVal := CovBinPtr(BinIndex).BinVal.all; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBin ; -- ------------------------------------------------------------ impure function GetBin ( BinIndex : integer ) return CovMatrix9BaseType is -- ------------------------------------------------------------ variable result : CovMatrix9BaseType ; begin result.BinVal := CovBinPtr(BinIndex).BinVal.all; result.Action := CovBinPtr(BinIndex).Action; result.Count := CovBinPtr(BinIndex).Count; result.AtLeast := CovBinPtr(BinIndex).AtLeast; result.Weight := CovBinPtr(BinIndex).Weight; return result ; end function GetBin ; -- ------------------------------------------------------------ impure function GetBinName ( BinIndex : integer; DefaultName : string := "" ) return string is -- ------------------------------------------------------------ begin if CovBinPtr(BinIndex).Name.all /= "" then return CovBinPtr(BinIndex).Name.all ; else return DefaultName ; end if; end function GetBinName; ------------------------------------------------------------ -- pt local for now -- file formal parameter not allowed with method procedure WriteBin ( file f : text ; WritePassFail : CovOptionsType ; WriteBinInfo : CovOptionsType ; WriteCount : CovOptionsType ; WriteAnyIllegal : CovOptionsType ; WritePrefix : string ; PassName : string ; FailName : string ) is ------------------------------------------------------------ variable buf : line ; begin if NumBins < 1 then if WriteBinFileInit or UsingLocalFile then swrite(buf, WritePrefix & " " & FailName & " ") ; swrite(buf, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.WriteBin: Coverage model is empty. Nothing to print.") ; writeline(f, buf) ; end if ; Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.WriteBin:" & " Coverage model is empty. Nothing to print.", FAILURE) ; return ; end if ; -- Models with Bins WriteBinName(f, "WriteBin: ", WritePrefix) ; for i in 1 to NumBins loop -- CovBinPtr.all'range if CovBinPtr(i).action = COV_COUNT or (CovBinPtr(i).action = COV_ILLEGAL and IsEnabled(WriteAnyIllegal)) or CovBinPtr(i).count < 0 -- Illegal bin with errors then -- WriteBin Info swrite(buf, WritePrefix) ; if CovBinPtr(i).Name.all /= "" then swrite(buf, CovBinPtr(i).Name.all & " ") ; end if ; if IsEnabled(WritePassFail) then -- For illegal bins, AtLeast = 0 and count is negative. if CovBinPtr(i).count >= CovBinPtr(i).AtLeast then swrite(buf, PassName & ' ') ; else swrite(buf, FailName & ' ') ; end if ; end if ; if IsEnabled(WriteBinInfo) then if CovBinPtr(i).action = COV_COUNT then swrite(buf, "Bin:") ; else swrite(buf, "Illegal Bin:") ; end if; write(buf, CovBinPtr(i).BinVal.all) ; end if ; if IsEnabled(WriteCount) then write(buf, " Count = " & integer'image(abs(CovBinPtr(i).count))) ; write(buf, " AtLeast = " & integer'image(CovBinPtr(i).AtLeast)) ; if WeightMode = WEIGHT or WeightMode = REMAIN_WEIGHT then -- Print Weight only when it is used write(buf, " Weight = " & integer'image(CovBinPtr(i).Weight)) ; end if ; end if ; writeline(f, buf) ; end if ; end loop ; swrite(buf, "") ; writeline(f, buf) ; end procedure WriteBin ; ------------------------------------------------------------ procedure WriteBin ( ------------------------------------------------------------ WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is constant rWritePassFail : CovOptionsType := ResolveCovWritePassFail(WritePassFail, WritePassFailVar) ; constant rWriteBinInfo : CovOptionsType := ResolveCovWriteBinInfo(WriteBinInfo, WriteBinInfoVar ) ; constant rWriteCount : CovOptionsType := ResolveCovWriteCount(WriteCount, WriteCountVar ) ; constant rWriteAnyIllegal : CovOptionsType := ResolveCovWriteAnyIllegal(WriteAnyIllegal, WriteAnyIllegalVar) ; constant rWritePrefix : string := ResolveOsvvmWritePrefix(WritePrefix, WritePrefixVar.GetOpt) ; constant rPassName : string := ResolveOsvvmPassName(PassName, PassNameVar.GetOpt ) ; constant rFailName : string := ResolveOsvvmFailName(FailName, FailNameVar.GetOpt ) ; begin if WriteBinFileInit then -- Write to Local WriteBinFile - Deprecated, recommend use TranscriptFile instead WriteBin ( f => WriteBinFile, WritePassFail => rWritePassFail, WriteBinInfo => rWriteBinInfo, WriteCount => rWriteCount, WriteAnyIllegal => rWriteAnyIllegal, WritePrefix => rWritePrefix, PassName => rPassName, FailName => rFailName ) ; elsif IsTranscriptEnabled then -- Write to TranscriptFile WriteBin ( f => TranscriptFile, WritePassFail => rWritePassFail, WriteBinInfo => rWriteBinInfo, WriteCount => rWriteCount, WriteAnyIllegal => rWriteAnyIllegal, WritePrefix => rWritePrefix, PassName => rPassName, FailName => rFailName ) ; if IsTranscriptMirrored then -- Mirrored to OUTPUT WriteBin ( f => OUTPUT, WritePassFail => rWritePassFail, WriteBinInfo => rWriteBinInfo, WriteCount => rWriteCount, WriteAnyIllegal => rWriteAnyIllegal, WritePrefix => rWritePrefix, PassName => rPassName, FailName => rFailName ) ; end if ; else -- Default Write to OUTPUT WriteBin ( f => OUTPUT, WritePassFail => rWritePassFail, WriteBinInfo => rWriteBinInfo, WriteCount => rWriteCount, WriteAnyIllegal => rWriteAnyIllegal, WritePrefix => rWritePrefix, PassName => rPassName, FailName => rFailName ) ; end if ; end procedure WriteBin ; ------------------------------------------------------------ procedure WriteBin ( -- With LogLevel ------------------------------------------------------------ LogLevel : LogType ; WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is begin if IsLogEnabled(AlertLogIDVar, LogLevel) then WriteBin ( WritePassFail => WritePassFail, WriteBinInfo => WriteBinInfo, WriteCount => WriteCount, WriteAnyIllegal => WriteAnyIllegal, WritePrefix => WritePrefix, PassName => PassName, FailName => FailName ) ; end if ; end procedure WriteBin ; -- With LogLevel ------------------------------------------------------------ procedure WriteBin ( ------------------------------------------------------------ FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ; WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is file LocalWriteBinFile : text open OpenKind is FileName ; constant rWritePassFail : CovOptionsType := ResolveCovWritePassFail(WritePassFail, WritePassFailVar) ; constant rWriteBinInfo : CovOptionsType := ResolveCovWriteBinInfo(WriteBinInfo, WriteBinInfoVar ) ; constant rWriteCount : CovOptionsType := ResolveCovWriteCount(WriteCount, WriteCountVar ) ; constant rWriteAnyIllegal : CovOptionsType := ResolveCovWriteAnyIllegal(WriteAnyIllegal, WriteAnyIllegalVar) ; constant rWritePrefix : string := ResolveOsvvmWritePrefix(WritePrefix, WritePrefixVar.GetOpt) ; constant rPassName : string := ResolveOsvvmPassName(PassName, PassNameVar.GetOpt ) ; constant rFailName : string := ResolveOsvvmFailName(FailName, FailNameVar.GetOpt ) ; begin UsingLocalFile := TRUE ; WriteBin ( f => LocalWriteBinFile, WritePassFail => rWritePassFail, WriteBinInfo => rWriteBinInfo, WriteCount => rWriteCount, WriteAnyIllegal => rWriteAnyIllegal, WritePrefix => rWritePrefix, PassName => rPassName, FailName => rFailName ); UsingLocalFile := FALSE ; end procedure WriteBin ; ------------------------------------------------------------ procedure WriteBin ( -- With LogLevel ------------------------------------------------------------ LogLevel : LogType ; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ; WritePassFail : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteBinInfo : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteCount : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WriteAnyIllegal : CovOptionsType := COV_OPT_INIT_PARM_DETECT ; WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is begin if IsLogEnabled(AlertLogIDVar, LogLevel) then UsingLocalFile := TRUE ; WriteBin ( FileName => FileName, OpenKind => OpenKind, WritePassFail => WritePassFail, WriteBinInfo => WriteBinInfo, WriteCount => WriteCount, WriteAnyIllegal => WriteAnyIllegal, WritePrefix => WritePrefix, PassName => PassName, FailName => FailName ) ; UsingLocalFile := FALSE ; end if ; end procedure WriteBin ; -- With LogLevel ------------------------------------------------------------ -- Development only -- pt local for now -- file formal parameter not allowed with method procedure DumpBin ( file f : text ) is ------------------------------------------------------------ variable buf : line ; begin WriteBinName(f, "DumpBin: ") ; -- if NumBins < 1 then -- Write(f, "%%FATAL, Coverage Model is empty. Nothing to print." & LF ) ; -- end if ; for i in 1 to NumBins loop -- CovBinPtr.all'range swrite(buf, "%% ") ; if CovBinPtr(i).Name.all /= "" then swrite(buf, CovBinPtr(i).Name.all & " ") ; end if ; swrite(buf, "Bin:") ; write(buf, CovBinPtr(i).BinVal.all) ; case CovBinPtr(i).action is when COV_COUNT => swrite(buf, " Count = ") ; when COV_IGNORE => swrite(buf, " Ignore = ") ; when COV_ILLEGAL => swrite(buf, " Illegal = ") ; when others => swrite(buf, " BOGUS BOGUS BOGUS = ") ; end case ; write(buf, CovBinPtr(i).count) ; -- write(f, " Count = " & integer'image(CovBinPtr(i).count)) ; write(buf, " AtLeast = " & integer'image(CovBinPtr(i).AtLeast)) ; write(buf, " Weight = " & integer'image(CovBinPtr(i).Weight)) ; --! write(buf, " OrderCount = " & integer'image(CovBinPtr(i).OrderCount)) ; --! if CovBinPtr(i).count > 0 then --! write(buf, " Normalized OrderCount = " & integer'image(CovBinPtr(i).OrderCount/CovBinPtr(i).count)) ; --! end if ; writeline(f, buf) ; end loop ; swrite(buf, "") ; writeline(f,buf) ; end procedure DumpBin ; ------------------------------------------------------------ procedure DumpBin (LogLevel : LogType := DEBUG) is ------------------------------------------------------------ begin if IsLogEnabled(AlertLogIDVar, LogLevel) then if WriteBinFileInit then -- Write to Local WriteBinFile - Deprecated, recommend use TranscriptFile instead DumpBin(WriteBinFile) ; elsif IsTranscriptEnabled then -- Write to TranscriptFile DumpBin(TranscriptFile) ; if IsTranscriptMirrored then -- Mirrored to OUTPUT DumpBin(OUTPUT) ; end if ; else -- Default Write to OUTPUT DumpBin(OUTPUT) ; end if ; end if ; end procedure DumpBin ; ------------------------------------------------------------ -- pt local procedure WriteCovHoles ( file f : text; PercentCov : real := 100.0 ) is ------------------------------------------------------------ variable buf : line ; begin if NumBins < 1 then if WriteBinFileInit or UsingLocalFile then -- Duplicate Alert in specified file swrite(buf, "%% Alert FAILURE " & GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" & " coverage model empty. Nothing to print.") ; writeline(f, buf) ; end if ; Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" & " coverage model empty. Nothing to print.", FAILURE) ; return ; end if ; -- Models with Bins WriteBinName(f, "WriteCovHoles: ") ; CovLoop : for i in 1 to NumBins loop if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).PercentCov < PercentCov then swrite(buf, "%% ") ; if CovBinPtr(i).Name.all /= "" then swrite(buf, CovBinPtr(i).Name.all & " ") ; end if ; swrite(buf, "Bin:") ; write(buf, CovBinPtr(i).BinVal.all) ; write(buf, " Count = " & integer'image(CovBinPtr(i).Count)) ; write(buf, " AtLeast = " & integer'image(CovBinPtr(i).AtLeast)) ; if WeightMode = WEIGHT or WeightMode = REMAIN_WEIGHT then -- Print Weight only when it is used write(buf, " Weight = " & integer'image(CovBinPtr(i).Weight)) ; end if ; writeline(f, buf) ; end if ; end loop CovLoop ; swrite(buf, "") ; writeline(f, buf) ; end procedure WriteCovHoles ; ------------------------------------------------------------ procedure WriteCovHoles ( PercentCov : real ) is ------------------------------------------------------------ begin if WriteBinFileInit then -- Write to Local WriteBinFile - Deprecated, recommend use TranscriptFile instead WriteCovHoles(WriteBinFile, PercentCov) ; elsif IsTranscriptEnabled then -- Write to TranscriptFile WriteCovHoles(TranscriptFile, PercentCov) ; if IsTranscriptMirrored then -- Mirrored to OUTPUT WriteCovHoles(OUTPUT, PercentCov) ; end if ; else -- Default Write to OUTPUT WriteCovHoles(OUTPUT, PercentCov) ; end if; end procedure WriteCovHoles ; ------------------------------------------------------------ procedure WriteCovHoles ( LogLevel : LogType := ALWAYS ) is ------------------------------------------------------------ begin if IsLogEnabled(AlertLogIDVar, LogLevel) then WriteCovHoles(CovTarget) ; end if; end procedure WriteCovHoles ; ------------------------------------------------------------ procedure WriteCovHoles ( LogLevel : LogType ; PercentCov : real ) is ------------------------------------------------------------ begin if IsLogEnabled(AlertLogIDVar, LogLevel) then WriteCovHoles(PercentCov) ; end if; end procedure WriteCovHoles ; ------------------------------------------------------------ procedure WriteCovHoles ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is ------------------------------------------------------------ file CovHoleFile : text open OpenKind is FileName ; begin UsingLocalFile := TRUE ; WriteCovHoles(CovHoleFile, CovTarget) ; UsingLocalFile := FALSE ; end procedure WriteCovHoles ; ------------------------------------------------------------ procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is ------------------------------------------------------------ begin if IsLogEnabled(AlertLogIDVar, LogLevel) then WriteCovHoles(FileName, OpenKind) ; end if; end procedure WriteCovHoles ; ------------------------------------------------------------ procedure WriteCovHoles ( FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is ------------------------------------------------------------ file CovHoleFile : text open OpenKind is FileName ; begin UsingLocalFile := TRUE ; WriteCovHoles(CovHoleFile, PercentCov) ; UsingLocalFile := FALSE ; end procedure WriteCovHoles ; ------------------------------------------------------------ procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is ------------------------------------------------------------ begin if IsLogEnabled(AlertLogIDVar, LogLevel) then WriteCovHoles(FileName, PercentCov, OpenKind) ; end if; end procedure WriteCovHoles ; ------------------------------------------------------------ -- pt local impure function FindExactBin ( -- find an exact match to a bin wrt BinVal, Action, AtLeast, Weight, and Name ------------------------------------------------------------ Merge : boolean ; BinVal : RangeArrayType ; Action : integer ; AtLeast : integer ; Weight : integer ; Name : string ) return integer is begin if Merge then for i in 1 to NumBins loop if (BinVal = CovBinPtr(i).BinVal.all) and (Action = CovBinPtr(i).Action) and (AtLeast = CovBinPtr(i).AtLeast) and (Weight = CovBinPtr(i).Weight) and (Name = CovBinPtr(i).Name.all) then return i ; end if; end loop ; end if ; return 0 ; end function FindExactBin ; ------------------------------------------------------------ -- pt local procedure read ( ------------------------------------------------------------ buf : inout line ; NamePtr : inout line ; NameLength : in integer ; ReadValid : out boolean ) is variable Name : string(1 to NameLength) ; begin if NameLength > 0 then read(buf, Name, ReadValid) ; NamePtr := new string'(Name) ; else ReadValid := TRUE ; NamePtr := new string'("") ; end if ; end procedure read ; ------------------------------------------------------------ -- pt local procedure ReadCovVars (file CovDbFile : text; Good : out boolean ) is ------------------------------------------------------------ variable buf : line ; variable Empty : boolean ; variable MultiLineComment : boolean := FALSE ; variable ReadValid : boolean ; variable GoodLoop1 : boolean ; variable iSeed : RandomSeedType ; variable iIllegalMode : integer ; variable iWeightMode : integer ; variable iWeightScale : real ; variable iCovThreshold : real ; variable iCountMode : integer ; variable iNumberOfMessages : integer ; variable iThresholdingEnable : boolean ; variable iCovTarget : real ; variable iMergingEnable : boolean ; begin -- ReadLoop0 : while not EndFile(CovDbFile) loop ReadLoop0 : loop -- allows emulation of "return when" -- ReadLine to Get Coverage Model Name, skip blank and comment lines, fails when file empty exit when AlertIf(AlertLogIDVar, EndFile(CovDbFile), GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: No Coverage Data to read", FAILURE) ; ReadLine(CovDbFile, buf) ; EmptyOrCommentLine(buf, Empty, MultiLineComment) ; next when Empty ; if buf.all /= "Coverage_Model_Not_Named" then SetName(buf.all) ; end if ; exit ReadLoop0 ; end loop ReadLoop0 ; -- ReadLoop1 : while not EndFile(CovDbFile) loop ReadLoop1 : loop -- ReadLine to Get Variables, skip blank and comment lines, fails when file empty exit when AlertIf(AlertLogIDVar, EndFile(CovDbFile), GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Coverage DB File Incomplete", FAILURE) ; ReadLine(CovDbFile, buf) ; EmptyOrCommentLine(buf, Empty, MultiLineComment) ; next when Empty ; read(buf, iSeed, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading Seed", FAILURE) ; RV.SetSeed( iSeed ) ; RvSeedInit := TRUE ; read(buf, iCovThreshold, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading CovThreshold", FAILURE) ; CovThreshold := iCovThreshold ; read(buf, iIllegalMode, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading IllegalMode", FAILURE) ; SetIllegalMode(IllegalModeType'val( iIllegalMode )) ; read(buf, iWeightMode, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading WeightMode", FAILURE) ; WeightMode := WeightModeType'val( iWeightMode ) ; read(buf, iWeightScale, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading WeightScale", FAILURE) ; WeightScale := iWeightScale ; read(buf, iCountMode, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading CountMode", FAILURE) ; CountMode := CountModeType'val( iCountMode ) ; read(buf, iThresholdingEnable, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading CountMode", FAILURE) ; ThresholdingEnable := iThresholdingEnable ; read(buf, iCovTarget, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading CountMode", FAILURE) ; CovTarget := iCovTarget ; read(buf, iMergingEnable, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading CountMode", FAILURE) ; MergingEnable := iMergingEnable ; exit ReadLoop1 ; end loop ReadLoop1 ; GoodLoop1 := ReadValid ; -- ReadLoop2 : while not EndFile(CovDbFile) loop ReadLoop2 : while ReadValid loop -- ReadLine to Coverage Model Header WriteBin Message, skip blank and comment lines, fails when file empty exit when AlertIf(AlertLogIDVar, EndFile(CovDbFile), GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Coverage DB File Incomplete", FAILURE) ; ReadLine(CovDbFile, buf) ; EmptyOrCommentLine(buf, Empty, MultiLineComment) ; next when Empty ; read(buf, iNumberOfMessages, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading NumberOfMessages", FAILURE) ; for i in 1 to iNumberOfMessages loop exit when AlertIf(AlertLogIDVar, EndFile(CovDbFile), GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: End of File while reading Messages", FAILURE) ; ReadLine(CovDbFile, buf) ; SetMessage(buf.all) ; end loop ; exit ReadLoop2 ; end loop ReadLoop2 ; Good := ReadValid and GoodLoop1 ; end procedure ReadCovVars ; ------------------------------------------------------------ -- pt local procedure ReadCovDbInfo ( ------------------------------------------------------------ File CovDbFile : text ; variable NumRangeItems : out integer ; variable NumLines : out integer ; variable Good : out boolean ) is variable buf : line ; variable ReadValid : boolean ; variable Empty : boolean ; variable MultiLineComment : boolean := FALSE ; begin ReadLoop : loop -- ReadLine to RangeItems NumLines, skip blank and comment lines, fails when file empty exit when AlertIf(AlertLogIDVar, EndFile(CovDbFile), GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Coverage DB File Incomplete", FAILURE) ; ReadLine(CovDbFile, buf) ; EmptyOrCommentLine(buf, Empty, MultiLineComment) ; next when Empty ; read(buf, NumRangeItems, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading NumRangeItems", FAILURE) ; read(buf, NumLines, ReadValid) ; exit when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading NumLines", FAILURE) ; exit ; end loop ReadLoop ; Good := ReadValid ; end procedure ReadCovDbInfo ; ------------------------------------------------------------ -- pt local procedure ReadCovDbDataBase ( ------------------------------------------------------------ File CovDbFile : text ; constant NumRangeItems : in integer ; constant NumLines : in integer ; constant Merge : in boolean ; variable Good : out boolean ) is variable buf : line ; variable Empty : boolean ; variable MultiLineComment : boolean := FALSE ; variable ReadValid : boolean ; -- Format: Action Count min1 max1 min2 max2 .... variable Action : integer ; variable Count : integer ; variable BinVal : RangeArrayType(1 to NumRangeItems) ; variable index : integer ; variable AtLeast : integer ; variable Weight : integer ; variable PercentCov : real ; variable NameLength : integer ; variable SkipBlank : character ; variable NamePtr : line ; begin GrowBins(NumLines) ; ReadLoop : for i in 1 to NumLines loop GetValidLineLoop: loop exit ReadLoop when AlertIf(AlertLogIDVar, EndFile(CovDbFile), GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Did not read specified number of lines", FAILURE) ; ReadLine(CovDbFile, buf) ; EmptyOrCommentLine(buf, Empty, MultiLineComment) ; next GetValidLineLoop when Empty ; -- replace with EmptyLine(buf) exit GetValidLineLoop ; end loop ; read(buf, Action, ReadValid) ; exit ReadLoop when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading Action", FAILURE) ; read(buf, Count, ReadValid) ; exit ReadLoop when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading Count", FAILURE) ; read(buf, AtLeast, ReadValid) ; exit ReadLoop when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading AtLeast", FAILURE) ; read(buf, Weight, ReadValid) ; exit ReadLoop when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading Weight", FAILURE) ; read(buf, PercentCov, ReadValid) ; exit ReadLoop when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading PercentCov", FAILURE) ; read(buf, BinVal, ReadValid) ; exit ReadLoop when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading BinVal", FAILURE) ; read(buf, NameLength, ReadValid) ; exit ReadLoop when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading Bin Name Length", FAILURE) ; read(buf, SkipBlank, ReadValid) ; exit ReadLoop when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading Bin Name Length", FAILURE) ; read(buf, NamePtr, NameLength, ReadValid) ; exit ReadLoop when AlertIfNot(AlertLogIDVar, ReadValid, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.ReadCovDb: Failed while reading Bin Name", FAILURE) ; index := FindExactBin(Merge, BinVal, Action, AtLeast, Weight, NamePtr.all) ; if index > 0 then -- Bin is an exact match so only merge the count values CovBinPtr(index).Count := CovBinPtr(index).Count + Count ; CovBinPtr(index).PercentCov := CalcPercentCov( Count => CovBinPtr.all(index).Count, AtLeast => CovBinPtr.all(index).AtLeast ) ; else InsertNewBin(BinVal, Action, Count, AtLeast, Weight, NamePtr.all, PercentCov) ; end if ; deallocate(NamePtr) ; end loop ReadLoop ; Good := ReadValid ; end ReadCovDbDataBase ; ------------------------------------------------------------ -- pt local procedure ReadCovDb (File CovDbFile : text; Merge : boolean := FALSE) is ------------------------------------------------------------ -- Format: Action Count min1 max1 min2 max2 -- file CovDbFile : text open READ_MODE is FileName ; variable NumRangeItems : integer ; variable NumLines : integer ; variable ReadValid : boolean ; begin if not Merge then Deallocate ; -- remove any old bins end if ; ReadLoop : loop -- Read coverage private variables to the file ReadCovVars(CovDbFile, ReadValid) ; exit when not ReadValid ; -- Get Coverage dimensions and number of items in file. ReadCovDbInfo(CovDbFile, NumRangeItems, NumLines, ReadValid) ; exit when not ReadValid ; -- Read the file ReadCovDbDataBase(CovDbFile, NumRangeItems, NumLines, Merge, ReadValid) ; exit ; end loop ReadLoop ; end ReadCovDb ; ------------------------------------------------------------ procedure ReadCovDb (FileName : string; Merge : boolean := FALSE) is ------------------------------------------------------------ -- Format: Action Count min1 max1 min2 max2 file CovDbFile : text open READ_MODE is FileName ; begin ReadCovDb(CovDbFile, Merge) ; end procedure ReadCovDb ; ------------------------------------------------------------ -- pt local procedure WriteCovDbVars (file CovDbFile : text ) is ------------------------------------------------------------ variable buf : line ; begin -- write coverage private variables to the file swrite(buf, CovNameVar.Get("Coverage_Model_Not_Named")) ; writeline(CovDbFile, buf) ; write(buf, RV.GetSeed ) ; write(buf, ' ') ; write(buf, CovThreshold, RIGHT, 0, 5) ; write(buf, ' ') ; write(buf, IllegalModeType'pos(IllegalMode)) ; write(buf, ' ') ; write(buf, WeightModeType'pos(WeightMode)) ; write(buf, ' ') ; write(buf, WeightScale, RIGHT, 0, 6) ; write(buf, ' ') ; write(buf, CountModeType'pos(CountMode)) ; write(buf, ' ') ; write(buf, ThresholdingEnable) ; -- boolean write(buf, ' ') ; write(buf, CovTarget, RIGHT, 0, 6) ; -- Real write(buf, ' ') ; write(buf, MergingEnable) ; -- boolean write(buf, ' ') ; writeline(CovDbFile, buf) ; write(buf, CovMessageVar.GetCount ) ; writeline(CovDbFile, buf) ; WriteMessage(CovDbFile, CovMessageVar) ; end procedure WriteCovDbVars ; ------------------------------------------------------------ -- pt local procedure WriteCovDb (file CovDbFile : text ) is ------------------------------------------------------------ -- Format: Action Count min1 max1 min2 max2 variable buf : line ; begin -- write Cover variables to the file WriteCovDbVars( CovDbFile ) ; -- write NumRangeItems, NumLines write(buf, CovBinPtr(1).BinVal'length) ; write(buf, ' ') ; write(buf, NumBins) ; write(buf, ' ') ; writeline(CovDbFile, buf) ; -- write coverage to a file writeloop : for LineCount in 1 to NumBins loop write(buf, CovBinPtr(LineCount).Action) ; write(buf, ' ') ; write(buf, CovBinPtr(LineCount).Count) ; write(buf, ' ') ; write(buf, CovBinPtr(LineCount).AtLeast) ; write(buf, ' ') ; write(buf, CovBinPtr(LineCount).Weight) ; write(buf, ' ') ; write(buf, CovBinPtr(LineCount).PercentCov, RIGHT, 0, 4) ; write(buf, ' ') ; WriteBinVal(buf, CovBinPtr(LineCount).BinVal.all) ; write(buf, ' ') ; write(buf, CovBinPtr(LineCount).Name'length) ; write(buf, ' ') ; write(buf, CovBinPtr(LineCount).Name.all) ; writeline(CovDbFile, buf) ; end loop WriteLoop ; end procedure WriteCovDb ; ------------------------------------------------------------ procedure WriteCovDb (FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is ------------------------------------------------------------ -- Format: Action Count min1 max1 min2 max2 file CovDbFile : text open OpenKind is FileName ; begin if NumBins >= 1 then WriteCovDb(CovDbFile) ; else Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovDb: no bins defined ", FAILURE) ; end if ; end procedure WriteCovDb ; -- ------------------------------------------------------------ -- procedure WriteCovDb is -- ------------------------------------------------------------ -- begin -- if WriteCovDbFileInit then -- WriteCovDb(WriteCovDbFile) ; -- else -- report "CoveragePkg: WriteCovDb file not specified" severity failure ; -- end if ; -- end procedure WriteCovDb ; ------------------------------------------------------------ impure function GetErrorCount return integer is ------------------------------------------------------------ variable ErrorCnt : integer := 0 ; begin if NumBins < 1 then return 1 ; -- return error if model empty else for i in 1 to NumBins loop if CovBinPtr(i).count < 0 then -- illegal CovBin ErrorCnt := ErrorCnt + CovBinPtr(i).count ; end if ; end loop ; return - ErrorCnt ; end if ; end function GetErrorCount ; ------------------------------------------------------------ -- These support usage of cross coverage constants -- Also support the older AddBins(GenCross(...)) methodology -- which has been replaced by AddCross ------------------------------------------------------------ procedure AddCross (CovBin : CovMatrix2Type ; Name : String := "") is ------------------------------------------------------------ begin CheckBinValLength(2, "AddCross") ; GrowBins(CovBin'length) ; for i in CovBin'range loop InsertBin( CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count, CovBin(i).AtLeast, CovBin(i).Weight, Name ) ; end loop ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross (CovBin : CovMatrix3Type ; Name : String := "") is ------------------------------------------------------------ begin CheckBinValLength(3, "AddCross") ; GrowBins(CovBin'length) ; for i in CovBin'range loop InsertBin( CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count, CovBin(i).AtLeast, CovBin(i).Weight, Name ) ; end loop ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross (CovBin : CovMatrix4Type ; Name : String := "") is ------------------------------------------------------------ begin CheckBinValLength(4, "AddCross") ; GrowBins(CovBin'length) ; for i in CovBin'range loop InsertBin( CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count, CovBin(i).AtLeast, CovBin(i).Weight, Name ) ; end loop ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross (CovBin : CovMatrix5Type ; Name : String := "") is ------------------------------------------------------------ begin CheckBinValLength(5, "AddCross") ; GrowBins(CovBin'length) ; for i in CovBin'range loop InsertBin( CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count, CovBin(i).AtLeast, CovBin(i).Weight, Name ) ; end loop ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross (CovBin : CovMatrix6Type ; Name : String := "") is ------------------------------------------------------------ begin CheckBinValLength(6, "AddCross") ; GrowBins(CovBin'length) ; for i in CovBin'range loop InsertBin( CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count, CovBin(i).AtLeast, CovBin(i).Weight, Name ) ; end loop ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross (CovBin : CovMatrix7Type ; Name : String := "") is ------------------------------------------------------------ begin CheckBinValLength(7, "AddCross") ; GrowBins(CovBin'length) ; for i in CovBin'range loop InsertBin( CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count, CovBin(i).AtLeast, CovBin(i).Weight, Name ) ; end loop ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross (CovBin : CovMatrix8Type ; Name : String := "") is ------------------------------------------------------------ begin CheckBinValLength(8, "AddCross") ; GrowBins(CovBin'length) ; for i in CovBin'range loop InsertBin( CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count, CovBin(i).AtLeast, CovBin(i).Weight, Name ) ; end loop ; end procedure AddCross ; ------------------------------------------------------------ procedure AddCross (CovBin : CovMatrix9Type ; Name : String := "") is ------------------------------------------------------------ begin CheckBinValLength(9, "AddCross") ; GrowBins(CovBin'length) ; for i in CovBin'range loop InsertBin( CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count, CovBin(i).AtLeast, CovBin(i).Weight, Name ) ; end loop ; end procedure AddCross ; -- ------------------------------------------------------------ -- ------------------------------------------------------------ -- Deprecated. Due to name changes to promote greater consistency -- Maintained for backward compatibility. -- ------------------------------------------------------------ ------------------------------------------------------------ impure function CovBinErrCnt return integer is -- Deprecated. Name changed to ErrorCount for package to package consistency ------------------------------------------------------------ begin return GetErrorCount ; end function CovBinErrCnt ; ------------------------------------------------------------ -- Deprecated. Same as RandCovBinVal impure function RandCovHole ( PercentCov : real ) return RangeArrayType is ------------------------------------------------------------ begin return RandCovBinVal(PercentCov) ; end function RandCovHole ; ------------------------------------------------------------ -- Deprecated. Same as RandCovBinVal impure function RandCovHole return RangeArrayType is ------------------------------------------------------------ begin return RandCovBinVal ; end function RandCovHole ; -- GetCovHole replaced by GetHoleBinVal ------------------------------------------------------------ -- Deprecated. Same as GetHoleBinVal impure function GetCovHole ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is ------------------------------------------------------------ begin return GetHoleBinVal(ReqHoleNum, PercentCov) ; end function GetCovHole ; ------------------------------------------------------------ -- Deprecated. Same as GetHoleBinVal impure function GetCovHole ( PercentCov : real ) return RangeArrayType is ------------------------------------------------------------ begin return GetHoleBinVal(PercentCov) ; end function GetCovHole ; ------------------------------------------------------------ -- Deprecated. Same as GetHoleBinVal impure function GetCovHole ( ReqHoleNum : integer := 1 ) return RangeArrayType is ------------------------------------------------------------ begin return GetHoleBinVal(ReqHoleNum) ; end function GetCovHole ; -- ------------------------------------------------------------ -- ------------------------------------------------------------ -- Deprecated / Subsumed by versions with PercentCov Parameter -- Maintained for backward compatibility only and -- may be removed in the future. -- ------------------------------------------------------------ ------------------------------------------------------------ -- Deprecated. Replaced by SetMessage with multi-line support procedure SetItemName (ItemNameIn : String) is ------------------------------------------------------------ begin SetMessage(ItemNameIn) ; end procedure SetItemName ; ------------------------------------------------------------ -- Deprecated. Same as GetMinCount impure function GetMinCov return integer is ------------------------------------------------------------ begin return GetMinCount ; end function GetMinCov ; ------------------------------------------------------------ -- Deprecated. Same as GetMaxCount impure function GetMaxCov return integer is ------------------------------------------------------------ begin return GetMaxCount ; end function GetMaxCov ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov impure function CountCovHoles ( AtLeast : integer ) return integer is ------------------------------------------------------------ variable HoleCount : integer := 0 ; begin CovLoop : for i in 1 to NumBins loop -- if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < minimum(AtLeast, CovBinPtr(i).AtLeast) then if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < AtLeast then HoleCount := HoleCount + 1 ; end if ; end loop CovLoop ; return HoleCount ; end function CountCovHoles ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov impure function IsCovered ( AtLeast : integer ) return boolean is ------------------------------------------------------------ begin return CountCovHoles(AtLeast) = 0 ; end function IsCovered ; ------------------------------------------------------------ impure function CalcWeight ( BinIndex : integer ; MaxAtLeast : integer ) return integer is -- pt local ------------------------------------------------------------ begin case WeightMode is when AT_LEAST => return CovBinPtr(BinIndex).AtLeast ; when WEIGHT => return CovBinPtr(BinIndex).Weight ; when REMAIN => return MaxAtLeast - CovBinPtr(BinIndex).Count ; when REMAIN_SCALED => -- Experimental may be removed return integer( Ceil( WeightScale * real(MaxAtLeast))) - CovBinPtr(BinIndex).Count ; when REMAIN_WEIGHT => -- Experimental may be removed return CovBinPtr(BinIndex).Weight * ( integer( Ceil( WeightScale * real(MaxAtLeast))) - CovBinPtr(BinIndex).Count ) ; when others => Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.CalcWeight:" & " Selected Weight Mode not supported with deprecated RandCovPoint(AtLeast), see RandCovPoint(PercentCov)", FAILURE) ; return MaxAtLeast - CovBinPtr(BinIndex).Count ; end case ; end function CalcWeight ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov -- If keep this, need to be able to scale AtLeast Value impure function GetRandIndex ( AtLeast : integer ) return integer is -- pt local ------------------------------------------------------------ variable WeightVec : integer_vector(0 to NumBins-1) ; -- Prep for change to DistInt variable MinCount, AdjAtLeast, MaxAtLeast : integer ; begin ItemCount := ItemCount + 1 ; MinCount := GetMinCov ; -- iAtLeast := integer(ceil(CovTarget * real(AtLeast)/100.0)) ; if ThresholdingEnable then AdjAtLeast := MinCount + integer(CovThreshold) + 1 ; if MinCount < AtLeast then -- Clip at AtLeast until reach AtLeast AdjAtLeast := minimum(AdjAtLeast, AtLeast) ; end if ; else if MinCount < AtLeast then AdjAtLeast := AtLeast ; -- Valid else -- Done, Enable all bins -- AdjAtLeast := integer'right ; -- Get All AdjAtLeast := GetMaxCov + 1 ; -- Get All end if ; end if; MaxAtLeast := AdjAtLeast ; CovLoop : for i in 1 to NumBins loop -- if not ThresholdingEnable then -- -- When not thresholding, consider bin Bin.AtLeast -- -- iBinAtLeast := integer(ceil(CovTarget * real(CovBinPtr(i).AtLeast)/100.0)) ; -- MaxAtLeast := maximum(AdjAtLeast, CovBinPtr(i).AtLeast) ; -- end if ; if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < MaxAtLeast then WeightVec(i-1) := CalcWeight(i, MaxAtLeast ) ; -- CovBinPtr(i).Weight ; else WeightVec(i-1) := 0 ; end if ; end loop CovLoop ; -- DistInt returns integer range 0 to Numbins-1 LastStimGenIndex := 1 + RV.DistInt( WeightVec ) ; -- return range 1 to NumBins LastIndex := LastStimGenIndex ; return LastStimGenIndex ; end function GetRandIndex ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov impure function RandCovBinVal (AtLeast : integer ) return RangeArrayType is ------------------------------------------------------------ begin return CovBinPtr( GetRandIndex(AtLeast) ).BinVal.all ; -- GetBinVal end function RandCovBinVal ; -- Maintained for backward compatibility. Repeated until aliases work for methods ------------------------------------------------------------ -- Deprecated+ New versions use PercentCov. Name change. impure function RandCovHole (AtLeast : integer ) return RangeArrayType is ------------------------------------------------------------ begin return RandCovBinVal(AtLeast) ; -- GetBinVal end function RandCovHole ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov impure function RandCovPoint (AtLeast : integer ) return integer is ------------------------------------------------------------ variable BinVal : RangeArrayType(1 to 1) ; begin BinVal := RandCovBinVal(AtLeast) ; return RV.RandInt(BinVal(1).min, BinVal(1).max) ; end function RandCovPoint ; ------------------------------------------------------------ impure function RandCovPoint (AtLeast : integer ) return integer_vector is ------------------------------------------------------------ begin return ToRandPoint(RandCovBinVal(AtLeast)) ; end function RandCovPoint ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov impure function GetHoleBinVal ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is ------------------------------------------------------------ variable HoleCount : integer := 0 ; variable buf : line ; begin CovLoop : for i in 1 to NumBins loop -- if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < minimum(AtLeast, CovBinPtr(i).AtLeast) then if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < AtLeast then HoleCount := HoleCount + 1 ; if HoleCount = ReqHoleNum then return CovBinPtr(i).BinVal.all ; end if ; end if ; end loop CovLoop ; Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.GetHoleBinVal:" & " did not find hole. HoleCount = " & integer'image(HoleCount) & "ReqHoleNum = " & integer'image(ReqHoleNum), ERROR ) ; return CovBinPtr(NumBins).BinVal.all ; end function GetHoleBinVal ; ------------------------------------------------------------ -- Deprecated+. New versions use PercentCov. Name Change. impure function GetCovHole ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is ------------------------------------------------------------ begin return GetHoleBinVal(ReqHoleNum, AtLeast) ; end function GetCovHole ; ------------------------------------------------------------ -- pt local -- Deprecated. New versions use PercentCov. procedure WriteCovHoles ( file f : text; AtLeast : integer ) is ------------------------------------------------------------ -- variable minAtLeast : integer ; variable buf : line ; begin WriteBinName(f, "WriteCovHoles: ") ; if NumBins < 1 then if WriteBinFileInit or UsingLocalFile then -- Duplicate Alert in specified file swrite(buf, "%% Alert FAILURE " & GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" & " coverage model is empty. Nothing to print.") ; writeline(f, buf) ; end if ; Alert(AlertLogIDVar, GetNamePlus(prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" & " coverage model is empty. Nothing to print.", FAILURE) ; end if ; CovLoop : for i in 1 to NumBins loop -- minAtLeast := minimum(AtLeast,CovBinPtr(i).AtLeast) ; -- if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < minAtLeast then if CovBinPtr(i).action = COV_COUNT and CovBinPtr(i).Count < AtLeast then swrite(buf, "%% Bin:") ; write(buf, CovBinPtr(i).BinVal.all) ; write(buf, " Count = " & integer'image(CovBinPtr(i).Count)) ; write(buf, " AtLeast = " & integer'image(CovBinPtr(i).AtLeast)) ; if WeightMode = WEIGHT or WeightMode = REMAIN_WEIGHT then -- Print Weight only when it is used write(buf, " Weight = " & integer'image(CovBinPtr(i).Weight)) ; end if ; writeline(f, buf) ; end if ; end loop CovLoop ; swrite(buf, "") ; writeline(f, buf) ; end procedure WriteCovHoles ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov. procedure WriteCovHoles ( AtLeast : integer ) is ------------------------------------------------------------ begin if WriteBinFileInit then -- Write to Local WriteBinFile - Deprecated, recommend use TranscriptFile instead WriteCovHoles(WriteBinFile, AtLeast) ; elsif IsTranscriptEnabled then -- Write to TranscriptFile WriteCovHoles(TranscriptFile, AtLeast) ; if IsTranscriptMirrored then -- Mirrored to OUTPUT WriteCovHoles(OUTPUT, AtLeast) ; end if ; else -- Default Write to OUTPUT WriteCovHoles(OUTPUT, AtLeast) ; end if; end procedure WriteCovHoles ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov. procedure WriteCovHoles ( LogLevel : LogType ; AtLeast : integer ) is ------------------------------------------------------------ begin if IsLogEnabled(AlertLogIDVar, LogLevel) then WriteCovHoles(AtLeast) ; end if; end procedure WriteCovHoles ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov. procedure WriteCovHoles ( FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is ------------------------------------------------------------ file CovHoleFile : text open OpenKind is FileName ; begin WriteCovHoles(CovHoleFile, AtLeast) ; end procedure WriteCovHoles ; ------------------------------------------------------------ -- Deprecated. New versions use PercentCov. procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is ------------------------------------------------------------ begin if IsLogEnabled(AlertLogIDVar, LogLevel) then WriteCovHoles(FileName, AtLeast, OpenKind) ; end if; end procedure WriteCovHoles ; ------------------------------------------------------------ -- Deprecated. Use AddCross Instead. procedure AddBins (CovBin : CovMatrix2Type ; Name : String := "") is ------------------------------------------------------------ begin AddCross(CovBin, Name) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins (CovBin : CovMatrix3Type ; Name : String := "") is ------------------------------------------------------------ begin AddCross(CovBin, Name) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins (CovBin : CovMatrix4Type ; Name : String := "") is ------------------------------------------------------------ begin AddCross(CovBin, Name) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins (CovBin : CovMatrix5Type ; Name : String := "") is ------------------------------------------------------------ begin AddCross(CovBin, Name) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins (CovBin : CovMatrix6Type ; Name : String := "") is ------------------------------------------------------------ begin AddCross(CovBin, Name) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins (CovBin : CovMatrix7Type ; Name : String := "") is ------------------------------------------------------------ begin AddCross(CovBin, Name) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins (CovBin : CovMatrix8Type ; Name : String := "") is ------------------------------------------------------------ begin AddCross(CovBin, Name) ; end procedure AddBins ; ------------------------------------------------------------ procedure AddBins (CovBin : CovMatrix9Type ; Name : String := "") is ------------------------------------------------------------ begin AddCross(CovBin, Name) ; end procedure AddBins ; end protected body CovPType ; ------------------------------------------------------------------------------------------ -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX ------------------------------------------------------------------------------------------ ------------------------------------------------------------ -- Experimental. Intended primarily for development. procedure CompareBins ( ------------------------------------------------------------ variable Bin1 : inout CovPType ; variable Bin2 : inout CovPType ; variable ErrorCount : inout integer ) is variable NumBins1, NumBins2 : integer ; variable BinInfo1, BinInfo2 : CovBinBaseType ; variable BinVal1, BinVal2 : RangeArrayType(1 to Bin1.GetBinValLength) ; variable buf : line ; variable iAlertLogID : AlertLogIDType ; begin iAlertLogID := Bin1.GetAlertLogID ; NumBins1 := Bin1.GetNumBins ; NumBins2 := Bin2.GetNumBins ; if (NumBins1 /= NumBins2) then ErrorCount := ErrorCount + 1 ; print("CoveragePkg.CompareBins: CoverageModels " & Bin1.GetCovModelName & " and " & Bin2.GetCovModelName & " have different bin lengths") ; return ; end if ; for i in 1 to NumBins1 loop BinInfo1 := Bin1.GetBinInfo(i) ; BinInfo2 := Bin2.GetBinInfo(i) ; BinVal1 := Bin1.GetBinVal(i) ; BinVal2 := Bin2.GetBinVal(i) ; if BinInfo1 /= BinInfo2 or BinVal1 /= BinVal2 then write(buf, "%% Bin:" & integer'image(i) & " miscompare." & LF) ; -- writeline(OUTPUT, buf) ; swrite(buf, "%% Bin1: ") ; write(buf, BinVal1) ; write(buf, " Action = " & integer'image(BinInfo1.action)) ; write(buf, " Count = " & integer'image(BinInfo1.count)) ; write(buf, " AtLeast = " & integer'image(BinInfo1.AtLeast)) ; write(buf, " Weight = " & integer'image(BinInfo1.Weight) & LF ) ; -- writeline(OUTPUT, buf) ; swrite(buf, "%% Bin2: ") ; write(buf, BinVal2) ; write(buf, " Action = " & integer'image(BinInfo2.action)) ; write(buf, " Count = " & integer'image(BinInfo2.count)) ; write(buf, " AtLeast = " & integer'image(BinInfo2.AtLeast)) ; write(buf, " Weight = " & integer'image(BinInfo2.Weight) & LF ) ; -- writeline(OUTPUT, buf) ; ErrorCount := ErrorCount + 1 ; writeline(buf) ; -- Alert(iAlertLogID, buf.all, ERROR) ; -- deallocate(buf) ; end if ; end loop ; end procedure CompareBins ; ------------------------------------------------------------ -- Experimental. Intended primarily for development. procedure CompareBins ( ------------------------------------------------------------ variable Bin1 : inout CovPType ; variable Bin2 : inout CovPType ) is variable ErrorCount : integer ; variable iAlertLogID : AlertLogIDType ; begin CompareBins(Bin1, Bin2, ErrorCount) ; iAlertLogID := Bin1.GetAlertLogID ; AlertIf(ErrorCount /= 0, "CoveragePkg.CompareBins: CoverageModels " & Bin1.GetCovModelName & " and " & Bin2.GetCovModelName & " are not the same.") ; end procedure CompareBins ; ------------------------------------------------------------ -- package local, Used by GenBin, IllegalBin, and IgnoreBin function MakeBin( -- Must be pure to allow initializing coverage models passed as generics. -- Impure implies the expression is not globally static. ------------------------------------------------------------ Min, Max : integer ; NumBin : integer ; AtLeast : integer ; Weight : integer ; Action : integer ) return CovBinType is variable iCovBin : CovBinType(1 to NumBin) ; variable TotalBins : integer ; -- either real or integer variable rMax, rCurMin, rNumItemsInBin, rRemainingBins : real ; -- must be real variable iCurMin, iCurMax : integer ; begin if Min > Max then -- Similar to NULL ranges. Only generate report warning. report "OSVVM.CoveragePkg.MakeBin (called by GenBin, IllegalBin, or IgnoreBin) MAX > MIN generated NULL_BIN" severity WARNING ; -- No Alerts. They make this impure. -- Alert(OSVVM_ALERTLOG_ID, "CoveragePkg.MakeBin (called by GenBin, IllegalBin, IgnoreBin): Min must be <= Max", WARNING) ; return NULL_BIN ; elsif NumBin <= 0 then -- Similar to NULL ranges. Only generate report warning. report "OSVVM.CoveragePkg.MakeBin (called by GenBin, IllegalBin, or IgnoreBin) NumBin <= 0 generated NULL_BIN" severity WARNING ; -- Alerts make this impure. -- Alert(OSVVM_ALERTLOG_ID, "CoveragePkg.MakeBin (called by GenBin, IllegalBin, IgnoreBin): NumBin must be <= 0", WARNING) ; return NULL_BIN ; elsif NumBin = 1 then iCovBin(1) := ( BinVal => (1 => (Min, Max)), Action => Action, Count => 0, Weight => Weight, AtLeast => AtLeast ) ; return iCovBin ; else -- Using type real to work around issues with integer sizing iCurMin := Min ; rCurMin := real(iCurMin) ; rMax := real(Max) ; rRemainingBins := (minimum( real(NumBin), rMax - rCurMin + 1.0 )) ; TotalBins := integer(rRemainingBins) ; for i in iCovBin'range loop rNumItemsInBin := trunc((rMax - rCurMin + 1.0) / rRemainingBins) ; -- Max - Min can be larger than integer range. iCurMax := iCurMin - integer(-rNumItemsInBin + 1.0) ; -- Keep: the "minus negative" works around a simulator bounds issue found in 2015.06 iCovBin(i) := ( BinVal => (1 => (iCurMin, iCurMax)), Action => Action, Count => 0, Weight => Weight, AtLeast => AtLeast ) ; rRemainingBins := rRemainingBins - 1.0 ; exit when rRemainingBins = 0.0 ; iCurMin := iCurMax + 1 ; rCurMin := real(iCurMin) ; end loop ; return iCovBin(1 to TotalBins) ; end if ; end function MakeBin ; ------------------------------------------------------------ -- package local, Used by GenBin, IllegalBin, and IgnoreBin function MakeBin( ------------------------------------------------------------ A : integer_vector ; AtLeast : integer ; Weight : integer ; Action : integer ) return CovBinType is alias NewA : integer_vector(1 to A'length) is A ; variable iCovBin : CovBinType(1 to A'length) ; begin if A'length <= 0 then -- Similar to NULL ranges. Only generate report warning. report "OSVVM.CoveragePkg.MakeBin (called by GenBin, IllegalBin, or IgnoreBin) integer_vector length <= 0 generated NULL_BIN" severity WARNING ; -- Alerts make this impure. -- Alert(OSVVM_ALERTLOG_ID, "CoveragePkg.MakeBin (GenBin, IllegalBin, IgnoreBin): integer_vector parameter must have values", WARNING) ; return NULL_BIN ; else for i in NewA'Range loop iCovBin(i) := ( BinVal => (i => (NewA(i), NewA(i)) ), Action => Action, Count => 0, Weight => Weight, AtLeast => AtLeast ) ; end loop ; return iCovBin ; end if ; end function MakeBin ; ------------------------------------------------------------ function GenBin( ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Min, Max : integer ; NumBin : integer ) return CovBinType is begin return MakeBin( Min => Min, Max => Max, NumBin => NumBin, AtLeast => AtLeast, Weight => Weight, Action => COV_COUNT ) ; end function GenBin ; ------------------------------------------------------------ function GenBin( AtLeast : integer ; Min, Max, NumBin : integer ) return CovBinType is ------------------------------------------------------------ begin return MakeBin( Min => Min, Max => Max, NumBin => NumBin, AtLeast => AtLeast, Weight => 1, Action => COV_COUNT ) ; end function GenBin ; ------------------------------------------------------------ function GenBin( Min, Max, NumBin : integer ) return CovBinType is ------------------------------------------------------------ begin return MakeBin( Min => Min, Max => Max, NumBin => NumBin, AtLeast => 1, Weight => 1, Action => COV_COUNT ) ; end function GenBin ; ------------------------------------------------------------ function GenBin ( Min, Max : integer) return CovBinType is ------------------------------------------------------------ begin -- create a separate CovBin for each value -- AtLeast and Weight = 1 (must use longer version to specify) return MakeBin( Min => Min, Max => Max, NumBin => Max - Min + 1, AtLeast => 1, Weight => 1, Action => COV_COUNT ) ; end function GenBin ; ------------------------------------------------------------ function GenBin ( A : integer ) return CovBinType is ------------------------------------------------------------ begin -- create a single CovBin for A. -- AtLeast and Weight = 1 (must use longer version to specify) return MakeBin( Min => A, Max => A, NumBin => 1, AtLeast => 1, Weight => 1, Action => COV_COUNT ) ; end function GenBin ; ------------------------------------------------------------ function GenBin( ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; A : integer_vector ) return CovBinType is begin return MakeBin( A => A, AtLeast => AtLeast, Weight => Weight, Action => COV_COUNT ) ; end function GenBin ; ------------------------------------------------------------ function GenBin ( AtLeast : integer ; A : integer_vector ) return CovBinType is ------------------------------------------------------------ begin return MakeBin( A => A, AtLeast => AtLeast, Weight => 1, Action => COV_COUNT ) ; end function GenBin ; ------------------------------------------------------------ function GenBin ( A : integer_vector ) return CovBinType is ------------------------------------------------------------ begin return MakeBin( A => A, AtLeast => 1, Weight => 1, Action => COV_COUNT ) ; end function GenBin ; ------------------------------------------------------------ function IllegalBin ( Min, Max, NumBin : integer ) return CovBinType is ------------------------------------------------------------ begin return MakeBin( Min => Min, Max => Max, NumBin => NumBin, AtLeast => 0, Weight => 0, Action => COV_ILLEGAL ) ; end function IllegalBin ; ------------------------------------------------------------ function IllegalBin ( Min, Max : integer ) return CovBinType is ------------------------------------------------------------ begin -- default, generate one CovBin with the entire range of values return MakeBin( Min => Min, Max => Max, NumBin => 1, AtLeast => 0, Weight => 0, Action => COV_ILLEGAL ) ; end function IllegalBin ; ------------------------------------------------------------ function IllegalBin ( A : integer ) return CovBinType is ------------------------------------------------------------ begin return MakeBin( Min => A, Max => A, NumBin => 1, AtLeast => 0, Weight => 0, Action => COV_ILLEGAL ) ; end function IllegalBin ; -- IgnoreBin should never have an AtLeast parameter ------------------------------------------------------------ function IgnoreBin (Min, Max, NumBin : integer) return CovBinType is ------------------------------------------------------------ begin return MakeBin( Min => Min, Max => Max, NumBin => NumBin, AtLeast => 0, Weight => 0, Action => COV_IGNORE ) ; end function IgnoreBin ; ------------------------------------------------------------ function IgnoreBin (Min, Max : integer) return CovBinType is ------------------------------------------------------------ begin -- default, generate one CovBin with the entire range of values return MakeBin( Min => Min, Max => Max, NumBin => 1, AtLeast => 0, Weight => 0, Action => COV_IGNORE ) ; end function IgnoreBin ; ------------------------------------------------------------ function IgnoreBin (A : integer) return CovBinType is ------------------------------------------------------------ begin return MakeBin( Min => A, Max => A, NumBin => 1, AtLeast => 0, Weight => 0, Action => COV_IGNORE ) ; end function IgnoreBin ; ------------------------------------------------------------ function GenCross( -- 2 -- Cross existing bins -- Use AddCross for adding values directly to coverage database -- Use GenCross for constants ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2 : CovBinType ) return CovMatrix2Type is constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2) ; constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ; variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ; variable CrossBins : CovBinType(BinIndex'range) ; variable Action : integer ; variable iCovMatrix : CovMatrix2Type(1 to NUM_NEW_BINS) ; begin for MatrixIndex in iCovMatrix'range loop CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2) ; Action := MergeState(CrossBins) ; iCovMatrix(MatrixIndex).action := Action ; iCovMatrix(MatrixIndex).count := 0 ; iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ; iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ; iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ; IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next end loop ; return iCovMatrix ; end function GenCross ; ------------------------------------------------------------ function GenCross(AtLeast : integer ; Bin1, Bin2 : CovBinType) return CovMatrix2Type is -- Cross existing bins -- use AddCross instead ------------------------------------------------------------ begin return GenCross(AtLeast, 0, Bin1, Bin2) ; end function GenCross ; ------------------------------------------------------------ function GenCross(Bin1, Bin2 : CovBinType) return CovMatrix2Type is -- Cross existing bins -- use AddCross instead ------------------------------------------------------------ begin return GenCross(0, 0, Bin1, Bin2) ; end function GenCross ; ------------------------------------------------------------ function GenCross( -- 3 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type is constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3) ; constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ; variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ; variable CrossBins : CovBinType(BinIndex'range) ; variable Action : integer ; variable iCovMatrix : CovMatrix3Type(1 to NUM_NEW_BINS) ; begin for MatrixIndex in iCovMatrix'range loop CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3) ; Action := MergeState(CrossBins) ; iCovMatrix(MatrixIndex).action := Action ; iCovMatrix(MatrixIndex).count := 0 ; iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ; iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ; iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ; IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next end loop ; return iCovMatrix ; end function GenCross ; ------------------------------------------------------------ function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type is ------------------------------------------------------------ begin return GenCross(AtLeast, 0, Bin1, Bin2, Bin3) ; end function GenCross ; ------------------------------------------------------------ function GenCross( Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type is ------------------------------------------------------------ begin return GenCross(0, 0, Bin1, Bin2, Bin3) ; end function GenCross ; ------------------------------------------------------------ function GenCross( -- 4 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type is constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4) ; constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ; variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ; variable CrossBins : CovBinType(BinIndex'range) ; variable Action : integer ; variable iCovMatrix : CovMatrix4Type(1 to NUM_NEW_BINS) ; begin for MatrixIndex in iCovMatrix'range loop CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4) ; Action := MergeState(CrossBins) ; iCovMatrix(MatrixIndex).action := Action ; iCovMatrix(MatrixIndex).count := 0 ; iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ; iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ; iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ; IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next end loop ; return iCovMatrix ; end function GenCross ; ------------------------------------------------------------ function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type is ------------------------------------------------------------ begin return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4) ; end function GenCross ; ------------------------------------------------------------ function GenCross( Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type is ------------------------------------------------------------ begin return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4) ; end function GenCross ; ------------------------------------------------------------ function GenCross( -- 5 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type is constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5) ; constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ; variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ; variable CrossBins : CovBinType(BinIndex'range) ; variable Action : integer ; variable iCovMatrix : CovMatrix5Type(1 to NUM_NEW_BINS) ; begin for MatrixIndex in iCovMatrix'range loop CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5) ; Action := MergeState(CrossBins) ; iCovMatrix(MatrixIndex).action := Action ; iCovMatrix(MatrixIndex).count := 0 ; iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ; iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ; iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ; IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next end loop ; return iCovMatrix ; end function GenCross ; ------------------------------------------------------------ function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type is ------------------------------------------------------------ begin return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5) ; end function GenCross ; ------------------------------------------------------------ function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type is ------------------------------------------------------------ begin return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5) ; end function GenCross ; ------------------------------------------------------------ function GenCross( -- 6 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type is constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ; constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ; variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ; variable CrossBins : CovBinType(BinIndex'range) ; variable Action : integer ; variable iCovMatrix : CovMatrix6Type(1 to NUM_NEW_BINS) ; begin for MatrixIndex in iCovMatrix'range loop CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ; Action := MergeState(CrossBins) ; iCovMatrix(MatrixIndex).action := Action ; iCovMatrix(MatrixIndex).count := 0 ; iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ; iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ; iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ; IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next end loop ; return iCovMatrix ; end function GenCross ; ------------------------------------------------------------ function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type is ------------------------------------------------------------ begin return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ; end function GenCross ; ------------------------------------------------------------ function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type is ------------------------------------------------------------ begin return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ; end function GenCross ; ------------------------------------------------------------ function GenCross( -- 7 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type is constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ; constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ; variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ; variable CrossBins : CovBinType(BinIndex'range) ; variable Action : integer ; variable iCovMatrix : CovMatrix7Type(1 to NUM_NEW_BINS) ; begin for MatrixIndex in iCovMatrix'range loop CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ; Action := MergeState(CrossBins) ; iCovMatrix(MatrixIndex).action := Action ; iCovMatrix(MatrixIndex).count := 0 ; iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ; iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ; iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ; IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next end loop ; return iCovMatrix ; end function GenCross ; ------------------------------------------------------------ function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type is ------------------------------------------------------------ begin return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ; end function GenCross ; ------------------------------------------------------------ function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type is ------------------------------------------------------------ begin return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ; end function GenCross ; ------------------------------------------------------------ function GenCross( -- 8 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type is constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ; constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ; variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ; variable CrossBins : CovBinType(BinIndex'range) ; variable Action : integer ; variable iCovMatrix : CovMatrix8Type(1 to NUM_NEW_BINS) ; begin for MatrixIndex in iCovMatrix'range loop CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ; Action := MergeState(CrossBins) ; iCovMatrix(MatrixIndex).action := Action ; iCovMatrix(MatrixIndex).count := 0 ; iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ; iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ; iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ; IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next end loop ; return iCovMatrix ; end function GenCross ; ------------------------------------------------------------ function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type is ------------------------------------------------------------ begin return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ; end function GenCross ; ------------------------------------------------------------ function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type is ------------------------------------------------------------ begin return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ; end function GenCross ; ------------------------------------------------------------ function GenCross( -- 9 ------------------------------------------------------------ AtLeast : integer ; Weight : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type is constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ; constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ; variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ; variable CrossBins : CovBinType(BinIndex'range) ; variable Action : integer ; variable iCovMatrix : CovMatrix9Type(1 to NUM_NEW_BINS) ; begin for MatrixIndex in iCovMatrix'range loop CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ; Action := MergeState(CrossBins) ; iCovMatrix(MatrixIndex).action := Action ; iCovMatrix(MatrixIndex).count := 0 ; iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ; iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ; iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ; IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next end loop ; return iCovMatrix ; end function GenCross ; ------------------------------------------------------------ function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type is ------------------------------------------------------------ begin return GenCross(AtLeast, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ; end function GenCross ; ------------------------------------------------------------ function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type is ------------------------------------------------------------ begin return GenCross(0, 0, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ; end function GenCross ; ------------------------------------------------------------ function to_integer ( B : boolean ) return integer is ------------------------------------------------------------ begin if B then return 1 ; else return 0 ; end if ; end function to_integer ; ------------------------------------------------------------ function CheckInteger_1_0 ( I : integer ) return boolean is ------------------------------------------------------------- begin case I is when 0 | 1 => return TRUE ; when others => return FALSE ; end case ; end function CheckInteger_1_0 ; ------------------------------------------------------------ function local_to_boolean ( I : integer ) return boolean is ------------------------------------------------------------ begin case I is when 1 => return TRUE ; when 0 => return FALSE ; when others => return FALSE ; end case ; end function local_to_boolean ; ------------------------------------------------------------ function to_boolean ( I : integer ) return boolean is ------------------------------------------------------------ begin if not CheckInteger_1_0(I) then report "CoveragePkg.to_boolean: invalid integer value: " & to_string(I) & " returning FALSE" severity WARNING ; end if ; return local_to_boolean(I) ; end function to_boolean ; ------------------------------------------------------------ function to_integer ( SL : std_logic ) return integer is ------------------------------------------------------------- begin case SL is when '1' | 'H' => return 1 ; when '0' | 'L' => return 0 ; when others => return -1 ; end case ; end function to_integer ; ------------------------------------------------------------ function local_to_std_logic ( I : integer ) return std_logic is ------------------------------------------------------------- begin case I is when 1 => return '1' ; when 0 => return '0' ; when others => return 'X' ; end case ; end function local_to_std_logic ; ------------------------------------------------------------ function to_std_logic ( I : integer ) return std_logic is ------------------------------------------------------------- begin if not CheckInteger_1_0(I) then report "CoveragePkg.to_std_logic: invalid integer value: " & to_string(I) & " returning X" severity WARNING ; end if ; return local_to_std_logic(I) ; end function to_std_logic ; ------------------------------------------------------------ function to_integer_vector ( BV : boolean_vector ) return integer_vector is ------------------------------------------------------------ variable result : integer_vector(BV'range) ; begin for i in BV'range loop result(i) := to_integer(BV(i)) ; end loop ; return result ; end function to_integer_vector ; ------------------------------------------------------------ function to_boolean_vector ( IV : integer_vector ) return boolean_vector is ------------------------------------------------------------ variable result : boolean_vector(IV'range) ; variable HasError : boolean := FALSE ; begin for i in IV'range loop result(i) := local_to_boolean(IV(i)) ; if not CheckInteger_1_0(IV(i)) then HasError := TRUE ; end if ; end loop ; if HasError then report "CoveragePkg.to_boolean_vector: invalid integer value" & " returning FALSE" severity WARNING ; end if ; return result ; end function to_boolean_vector ; ------------------------------------------------------------ function to_integer_vector ( SLV : std_logic_vector ) return integer_vector is ------------------------------------------------------------- variable result : integer_vector(SLV'range) ; begin for i in SLV'range loop result(i) := to_integer(SLV(i)) ; end loop ; return result ; end function to_integer_vector ; ------------------------------------------------------------ function to_std_logic_vector ( IV : integer_vector ) return std_logic_vector is ------------------------------------------------------------- variable result : std_logic_vector(IV'range) ; variable HasError : boolean := FALSE ; begin for i in IV'range loop result(i) := local_to_std_logic(IV(i)) ; if not CheckInteger_1_0(IV(i)) then HasError := TRUE ; end if ; end loop ; if HasError then report "CoveragePkg.to_std_logic_vector: invalid integer value" & " returning FALSE" severity WARNING ; end if ; return result ; end function to_std_logic_vector ; ------------------------------------------------------------ ------------------------------------------------------------ -- Deprecated: These are not part of the coverage model -- ------------------------------------------------------------ -- procedure increment( signal Count : inout integer ) is -- ------------------------------------------------------------ -- begin -- Count <= Count + 1 ; -- end procedure increment ; -- -- -- ------------------------------------------------------------ -- procedure increment( signal Count : inout integer ; enable : boolean ) is -- ------------------------------------------------------------ -- begin -- if enable then -- Count <= Count + 1 ; -- end if ; -- end procedure increment ; -- -- -- ------------------------------------------------------------ -- procedure increment( signal Count : inout integer ; enable : std_ulogic ) is -- ------------------------------------------------------------ -- begin -- if to_x01(enable) = '1' then -- Count <= Count + 1 ; -- end if ; -- end procedure increment ; end package body CoveragePkg ;

artistic-2.0

3b8ec17419a237ff15875df46d994428

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_0_0/sim/zqynq_lab_1_design_axi_gpio_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_gpio:2.0 -- IP Revision: 15 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_gpio_v2_0_15; USE axi_gpio_v2_0_15.axi_gpio; ENTITY zqynq_lab_1_design_axi_gpio_0_0 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END zqynq_lab_1_design_axi_gpio_0_0; ARCHITECTURE zqynq_lab_1_design_axi_gpio_0_0_arch OF zqynq_lab_1_design_axi_gpio_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_gpio_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_gpio IS GENERIC ( C_FAMILY : STRING; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_GPIO_WIDTH : INTEGER; C_GPIO2_WIDTH : INTEGER; C_ALL_INPUTS : INTEGER; C_ALL_INPUTS_2 : INTEGER; C_ALL_OUTPUTS : INTEGER; C_ALL_OUTPUTS_2 : INTEGER; C_INTERRUPT_PRESENT : INTEGER; C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_IS_DUAL : INTEGER; C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_gpio; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O"; BEGIN U0 : axi_gpio GENERIC MAP ( C_FAMILY => "zynq", C_S_AXI_ADDR_WIDTH => 9, C_S_AXI_DATA_WIDTH => 32, C_GPIO_WIDTH => 8, C_GPIO2_WIDTH => 32, C_ALL_INPUTS => 0, C_ALL_INPUTS_2 => 0, C_ALL_OUTPUTS => 1, C_ALL_OUTPUTS_2 => 0, C_INTERRUPT_PRESENT => 0, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 0, C_DOUT_DEFAULT_2 => X"00000000", C_TRI_DEFAULT_2 => X"FFFFFFFF" ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), gpio_io_o => gpio_io_o, gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) ); END zqynq_lab_1_design_axi_gpio_0_0_arch;

mit

66361623b8f471007d9809829ae090fa

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml403/leon3mp.vhd

----------------------------------------------------------------------------- -- LEON3 Demonstration design -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib, techmap; use grlib.amba.all; use grlib.devices.all; use grlib.stdlib.all; use techmap.gencomp.all; use techmap.allclkgen.all; library gaisler; use gaisler.memctrl.all; use gaisler.ddrpkg.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.i2c.all; use gaisler.net.all; use gaisler.jtag.all; use gaisler.spacewire.all; library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; ncpu : integer := CFG_NCPU; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW ); port ( sys_rst_in : in std_ulogic; sys_clk : in std_ulogic; -- 100 MHz main clock --pragma translate_off plb_error : out std_logic; -- ERRORn --pragma translate_on opb_error : out std_logic; -- DSU active sram_flash_addr : out std_logic_vector(20 downto 0); sram_flash_data : inout std_logic_vector(31 downto 0); sram_cen : out std_logic; sram_bw : out std_logic_vector (0 to 3); sram_flash_oe_n : out std_ulogic; sram_flash_we_n : out std_ulogic; flash_ce : out std_logic; sram_clk : out std_ulogic; sram_clk_fb : in std_ulogic; sram_adv_ld_n : out std_ulogic; --pragma translate_off iosn : out std_ulogic; --pragma translate_on ddr_clk : out std_logic; ddr_clkb : out std_logic; ddr_clk_fb : in std_logic; ddr_cke : out std_logic; ddr_csb : out std_logic; ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (3 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (3 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (12 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (31 downto 0); -- ddr data txd1 : out std_ulogic; -- UART1 tx data rxd1 : in std_ulogic; -- UART1 rx data gpio : inout std_logic_vector(13 downto 0); -- I/O port phy_gtx_clk : out std_logic; phy_mii_data : inout std_logic; -- ethernet PHY interface phy_tx_clk : in std_ulogic; phy_rx_clk : in std_ulogic; phy_rx_data : in std_logic_vector(7 downto 0); phy_dv : in std_ulogic; phy_rx_er : in std_ulogic; phy_col : in std_ulogic; phy_crs : in std_ulogic; phy_tx_data : out std_logic_vector(7 downto 0); phy_tx_en : out std_ulogic; phy_tx_er : out std_ulogic; phy_mii_clk : out std_ulogic; phy_rst_n : out std_ulogic; ps2_keyb_clk : inout std_logic; ps2_keyb_data : inout std_logic; ps2_mouse_clk : inout std_logic; ps2_mouse_data : inout std_logic; tft_lcd_clk : out std_ulogic; vid_hsync : out std_ulogic; vid_vsync : out std_ulogic; vid_r : out std_logic_vector(7 downto 3); vid_g : out std_logic_vector(7 downto 3); vid_b : out std_logic_vector(7 downto 3); usb_csn : out std_logic; iic_scl : inout std_ulogic; iic_sda : inout std_ulogic ); end; architecture rtl of leon3mp is constant blength : integer := 12; constant fifodepth : integer := 8; constant maxahbm : integer := NCPU+CFG_AHB_UART +CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE; signal vcc, gnd : std_logic_vector(4 downto 0); signal memi : memory_in_type; signal memo : memory_out_type; signal wpo : wprot_out_type; signal sdi : sdctrl_in_type; signal sdo : sdctrl_out_type; signal sdo2 : sdctrl_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal clkm, rstn, rstraw, srclkl : std_ulogic; signal clkm_90, clkm_180, clkm_270 : std_ulogic; signal cgi, cgi2 : clkgen_in_type; signal cgo, cgo2 : clkgen_out_type; signal u1i, u2i, dui : uart_in_type; signal u1o, u2o, duo : uart_out_type; signal irqi : irq_in_vector(0 to NCPU-1); signal irqo : irq_out_vector(0 to NCPU-1); signal dbgi : l3_debug_in_vector(0 to NCPU-1); signal dbgo : l3_debug_out_vector(0 to NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal ethi, ethi1, ethi2 : eth_in_type; signal etho, etho1, etho2 : eth_out_type; signal gpti : gptimer_in_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic; signal tck, tckn, tms, tdi, tdo : std_ulogic; signal ddrclk, ddrrst : std_ulogic; signal ethclk, egtx_clk_fb : std_ulogic; signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic; signal kbdi : ps2_in_type; signal kbdo : ps2_out_type; signal moui : ps2_in_type; signal mouo : ps2_out_type; signal vgao : apbvga_out_type; signal clk_sel : std_logic_vector(1 downto 0); signal clkval : std_logic_vector(1 downto 0); signal clkvga, clk1x, video_clk, dac_clk : std_ulogic; signal i2ci : i2c_in_type; signal i2co : i2c_out_type; constant BOARD_FREQ : integer := 100000; -- input frequency in KHz constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1; constant IOAEN : integer := CFG_DDRSP; signal stati : ahbstat_in_type; signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic; signal ddr_clkv : std_logic_vector(2 downto 0); signal ddr_clkbv : std_logic_vector(2 downto 0); signal ddr_ckev : std_logic_vector(1 downto 0); signal ddr_csbv : std_logic_vector(1 downto 0); signal ddr_adl : std_logic_vector (13 downto 0); attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute syn_keep of clkml : signal is true; attribute syn_preserve of clkml : signal is true; attribute syn_keep of egtx_clk : signal is true; attribute syn_preserve of egtx_clk : signal is true; attribute keep : boolean; attribute keep of lock : signal is true; attribute keep of clkml : signal is true; attribute keep of clkm : signal is true; attribute keep of egtx_clk : signal is true; signal romsn : std_ulogic; constant SPW_LOOP_BACK : integer := 0; begin usb_csn <= '1'; ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb; ssrref_pad : clkpad generic map (tech => padtech) port map (sram_clk_fb, ssrclkfb); clk_pad : clkpad generic map (tech => padtech, arch => 2) port map (sys_clk, lclk); srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sram_clk, srclkl); clkgen0 : clkgen -- system clock generator generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0) port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x); g1clk : if CFG_GRETH1G /= 0 generate clkgen1 : clkgen -- Ethernet 1G PHY clock generator generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0) port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2); cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb; egtx_clk_pad : outpad generic map (tech => padtech) port map (phy_gtx_clk, egtx_clk); clklock <= lock and cgo2.clklock; end generate; nog1clk : if CFG_GRETH1G = 0 generate clklock <= lock; end generate; resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst); rst0 : rstgen -- reset generator port map (rst, clkm, clklock, rstn, rstraw); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401, ioen => IOAEN, nahbm => maxahbm, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- l3 : if CFG_LEON3 = 1 generate cpu : for i in 0 to NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; --pragma translate_off errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error); --pragma translate_on dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); dsui.enable <= '1'; -- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); dsui.break <= gpioo.val(11); -- South Button -- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact); dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact); ndsuact <= not dsuo.active; end generate; end generate; nodsu : if CFG_DSU = 0 generate dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0: ahbuart -- Debug UART generic map (hindex => NCPU, pindex => 7, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU)); -- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd); -- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd); dui.rxd <= rxd1 when gpioo.val(13) = '1' else '1'; end generate; txd1 <= duo.txd when gpioo.val(13) = '1' else u1o.txd; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; memi.brdyn <= '1'; memi.bexcn <= '1'; ssr0 : if CFG_SSCTRL = 1 generate ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#) port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo); end generate; mctrl0 : if CFG_MCTRL_LEON2 = 1 generate mctrl0 : mctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#C00#, rammask => 16#FF0#, paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS) port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open); end generate; romsn <= not memo.romsn(0); sram_adv_ld_n_pad : outpad generic map (tech => padtech) port map (sram_adv_ld_n, gnd(0)); addr_pad : outpadv generic map (width => 21, tech => padtech) port map (sram_flash_addr, memo.address(22 downto 2)); rams_pad : outpad generic map ( tech => padtech) port map (sram_cen, memo.ramsn(0)); roms_pad : outpad generic map (tech => padtech) port map (flash_ce, romsn); oen_pad : outpad generic map (tech => padtech) port map (sram_flash_oe_n, memo.oen); --pragma translate_off iosn_pad : outpad generic map (tech => padtech) port map (iosn, memo.iosn); --pragma translate_on rwen_pad : outpadv generic map (width => 4, tech => padtech) port map (sram_bw, memo.wrn); wri_pad : outpad generic map (tech => padtech) port map (sram_flash_we_n, memo.writen); data_pads : iopadvv generic map (tech => padtech, width => 32) port map (sram_flash_data, memo.data, memo.vbdrive, memi.data); ddrsp0 : if (CFG_DDRSP /= 0) generate ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech, hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1, pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000, col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32, phyiconf => 1) port map ( rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0), ddr_clkv, ddr_clkbv, open, ddr_clk_fb, ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq); ddr_ad <= ddr_adl(12 downto 0); ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0); ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0); end generate; noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(6)); end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.extclk <= '0'; u1i.ctsn <= '0'; u1i.rxd <= rxd1 when gpioo.val(13) = '0' else '1'; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; kbd : if CFG_KBD_ENABLE /= 0 generate ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4) port map(rstn, clkm, apbi, apbo(4), moui, mouo); ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5) port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo); end generate; nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate; kbdclk_pad : iopad generic map (tech => padtech) port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i); kbdata_pad : iopad generic map (tech => padtech) port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i); mouclk_pad : iopad generic map (tech => padtech) port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i); mouata_pad : iopad generic map (tech => padtech) port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i); vga : if CFG_VGA_ENABLE /= 0 generate vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6) port map(rstn, clkm, ethclk, apbi, apbo(6), vgao); clk_sel <= "00"; end generate; svga : if CFG_SVGA_ENABLE /= 0 generate svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6, hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ), clk2 => 1000000000/CPU_FREQ, burstlen => 6) port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel); end generate; vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate clkdiv : process(clk1x, rstn) begin if rstn = '0' then clkval <= "00"; elsif rising_edge(clk1x) then clkval <= clkval + 1; end if; end process; video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm; b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga); dac_clk <= not clkvga; end generate; novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate apbo(6) <= apb_none; vgao <= vgao_none; end generate; vert_sync_pad : outpad generic map (tech => padtech) port map (vid_vsync, vgao.vsync); horiz_sync_pad : outpad generic map (tech => padtech) port map (vid_hsync, vgao.hsync); video_out_r_pad : outpadv generic map (width => 5, tech => padtech) port map (vid_r(7 downto 3), vgao.video_out_r(7 downto 3)); video_out_g_pad : outpadv generic map (width => 5, tech => padtech) port map (vid_g(7 downto 3), vgao.video_out_g(7 downto 3)); video_out_b_pad : outpadv generic map (width => 5, tech => padtech) port map (vid_b(7 downto 3), vgao.video_out_b(7 downto 3)); video_clock_pad : outpad generic map ( tech => padtech) port map (tft_lcd_clk, dac_clk); gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit grgpio0: grgpio generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 14) port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8), gpioi => gpioi, gpioo => gpioo); gpio_pads : iopadvv generic map (tech => padtech, width => 14) port map (gpio, gpioo.dout(13 downto 0), gpioo.oen(13 downto 0), gpioi.din(13 downto 0)); end generate; ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7, nftslv => CFG_AHBSTATN) port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15)); end generate; i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master i2c0 : i2cmst generic map (pindex => 12, paddr => 12, pmask => 16#FFF#, pirq => 11, filter => I2C_FILTER) port map (rstn, clkm, apbi, apbo(12), i2ci, i2co); i2c_scl_pad : iopad generic map (tech => padtech) port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl); i2c_sda_pad : iopad generic map (tech => padtech) port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda); end generate i2cm; ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE, pindex => 11, paddr => 11, pirq => 12, memtech => memtech, mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO, nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G) port map( rst => rstn, clk => clkm, ahbmi => ahbmi, ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho); emdio_pad : iopad generic map (tech => padtech) port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i); etxc_pad : clkpad generic map (tech => padtech, arch => 2) port map (phy_tx_clk, ethi.tx_clk); erxc_pad : clkpad generic map (tech => padtech, arch => 2) port map (phy_rx_clk, ethi.rx_clk); erxd_pad : inpadv generic map (tech => padtech, width => 8) port map (phy_rx_data, ethi.rxd(7 downto 0)); erxdv_pad : inpad generic map (tech => padtech) port map (phy_dv, ethi.rx_dv); erxer_pad : inpad generic map (tech => padtech) port map (phy_rx_er, ethi.rx_er); erxco_pad : inpad generic map (tech => padtech) port map (phy_col, ethi.rx_col); erxcr_pad : inpad generic map (tech => padtech) port map (phy_crs, ethi.rx_crs); etxd_pad : outpadv generic map (tech => padtech, width => 8) port map (phy_tx_data, etho.txd(7 downto 0)); etxen_pad : outpad generic map (tech => padtech) port map ( phy_tx_en, etho.tx_en); etxer_pad : outpad generic map (tech => padtech) port map (phy_tx_er, etho.tx_er); emdc_pad : outpad generic map (tech => padtech) port map (phy_mii_clk, etho.mdc); erst_pad : outpad generic map (tech => padtech) port map (phy_rst_n, rstn); ethi.gtx_clk <= egtx_clk; end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ocram : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE) port map ( rstn, clkm, ahbsi, ahbso(7)); end generate; ----------------------------------------------------------------------- --- AHB DEBUG -------------------------------------------------------- ----------------------------------------------------------------------- -- dma0 : ahbdma -- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG, -- pindex => 13, paddr => 13, dbuf => 6) -- port map (rstn, clkm, apbi, apbo(13), ahbmi, -- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG)); -- at0 : ahbtrace -- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#, -- tech => memtech, irq => 0, kbytes => 8) -- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7)); ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- -- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate -- ahbmo(i) <= ahbm_none; -- end generate; -- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate; -- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on end;

gpl-2.0

c0ebb7ff94497dc81c475da588c934bc

MarkBlanco/FPGA_Sandbox

RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/vhdl/convolve_kernel_fcud.vhd

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity convolve_kernel_fcud is generic ( ID : integer := 2; NUM_STAGE : integer := 4; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of convolve_kernel_fcud is --------------------- Component --------------------- component convolve_kernel_ap_fmul_2_max_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- convolve_kernel_ap_fmul_2_max_dsp_32_u : component convolve_kernel_ap_fmul_2_max_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;

mit

33c9d48e36a2b249f926e8a38c68a01d

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep3c25-eek/leon3mp.vhd

------------------------------------------------------------------------------ -- LEON3 Demonstration design -- Copyright (C) 2008 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.memctrl.all; use gaisler.ddrpkg.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.net.all; use gaisler.jtag.all; use gaisler.i2c.all; use gaisler.spi.all; library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; ncpu : integer := CFG_NCPU; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; freq : integer := 50000 -- frequency of main clock (used for PLLs) ); port ( resetn : in std_ulogic; clk : in std_ulogic; errorn : out std_ulogic; -- flash/ssram bus address : out std_logic_vector(25 downto 1); data : inout std_logic_vector(31 downto 0); romsn : out std_ulogic; oen : out std_logic; writen : out std_logic; rstoutn : out std_ulogic; ssram_cen : out std_logic; ssram_wen : out std_logic; ssram_bw : out std_logic_vector (0 to 3); ssram_oen : out std_ulogic; ssram_clk : out std_ulogic; ssram_adscn : out std_ulogic; -- ssram_adsp_n : out std_ulogic; -- ssram_adv_n : out std_ulogic; -- pragma translate_off iosn : out std_ulogic; -- pragma translate_on -- DDR ddr_clk : out std_logic; ddr_clkn : out std_logic; ddr_cke : out std_logic; ddr_csb : out std_logic; ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (12 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data -- debug support unit dsubren : in std_ulogic; dsuact : out std_ulogic; -- I/O port gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0); -- Connections over HSMC connector -- LCD touch panel display hc_vd : out std_logic; hc_hd : out std_logic; hc_den : out std_logic; hc_nclk : out std_logic; hc_lcd_data : out std_logic_vector(7 downto 0); hc_grest : out std_logic; hc_scen : out std_logic; hc_sda : inout std_logic; hc_adc_penirq_n : in std_logic; hc_adc_dout : in std_logic; hc_adc_busy : in std_logic; hc_adc_din : out std_logic; hc_adc_dclk : out std_logic; hc_adc_cs_n : out std_logic; -- Shared with video decoder -- Shared by video decoder and audio codec hc_i2c_sclk : out std_logic; hc_i2c_sdat : inout std_logic; -- Video decoder hc_td_d : inout std_logic_vector(7 downto 0); hc_td_hs : in std_logic; hc_td_vs : in std_logic; hc_td_27mhz : in std_logic; hc_td_reset : out std_logic; -- Audio codec hc_aud_adclrck : out std_logic; hc_aud_adcdat : in std_logic; hc_aud_daclrck : out std_logic; hc_aud_dacdat : out std_logic; hc_aud_bclk : out std_logic; hc_aud_xck : out std_logic; -- SD card hc_sd_dat : inout std_logic; hc_sd_dat3 : inout std_logic; hc_sd_cmd : inout std_logic; hc_sd_clk : inout std_logic; -- Ethernet PHY hc_tx_d : out std_logic_vector(3 downto 0); hc_rx_d : in std_logic_vector(3 downto 0); hc_tx_clk : in std_logic; hc_rx_clk : in std_logic; hc_tx_en : out std_logic; hc_rx_dv : in std_logic; hc_rx_crs : in std_logic; hc_rx_err : in std_logic; hc_rx_col : in std_logic; hc_mdio : inout std_logic; hc_mdc : out std_logic; hc_eth_reset_n : out std_logic; -- RX232 (console/debug UART) hc_uart_rxd : in std_logic; hc_uart_txd : out std_logic; -- PS/2 hc_ps2_dat : inout std_logic; hc_ps2_clk : inout std_logic; -- VGA/DAC hc_vga_data : out std_logic_vector(9 downto 0); hc_vga_clock : out std_ulogic; hc_vga_hs : out std_ulogic; hc_vga_vs : out std_ulogic; hc_vga_blank : out std_ulogic; hc_vga_sync : out std_ulogic; -- I2C EEPROM hc_id_i2cscl : out std_logic; hc_id_i2cdat : inout std_logic ); end; architecture rtl of leon3mp is component serializer generic ( length : integer := 8 -- vector length ); port ( clk : in std_ulogic; sync : in std_ulogic; ivec0 : in std_logic_vector((length-1) downto 0); ivec1 : in std_logic_vector((length-1) downto 0); ivec2 : in std_logic_vector((length-1) downto 0); ovec : out std_logic_vector((length-1) downto 0) ); end component; component altera_eek_clkgen generic ( clk0_mul : integer := 1; clk0_div : integer := 1; clk1_mul : integer := 1; clk1_div : integer := 1; clk_freq : integer := 25000); port ( inclk0 : in std_ulogic; clk0 : out std_ulogic; clk0x3 : out std_ulogic; clksel : in std_logic_vector(1 downto 0); locked : out std_ulogic); end component; constant blength : integer := 12; constant fifodepth : integer := 8; constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+ CFG_SVGA_ENABLE+CFG_GRETH; signal vcc, gnd : std_logic_vector(7 downto 0); signal memi, smemi : memory_in_type; signal memo, smemo : memory_out_type; signal wpo : wprot_out_type; signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic; signal ddr_clkv : std_logic_vector(2 downto 0); signal ddr_clkbv : std_logic_vector(2 downto 0); signal ddr_ckev : std_logic_vector(1 downto 0); signal ddr_csbv : std_logic_vector(1 downto 0); signal ddr_adl : std_logic_vector (13 downto 0); signal clklock, lock, clkml, rst, ndsuact : std_ulogic; signal tck, tckn, tms, tdi, tdo : std_ulogic; signal ddrclk, ddrrst : std_ulogic; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal clkm, rstn, rawrstn, ssram_clkl : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal u1i, dui : uart_in_type; signal u1o, duo : uart_out_type; signal irqi : irq_in_vector(0 to NCPU-1); signal irqo : irq_out_vector(0 to NCPU-1); signal dbgi : l3_debug_in_vector(0 to NCPU-1); signal dbgo : l3_debug_out_vector(0 to NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal gpti : gptimer_in_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; signal ps2i : ps2_in_type; signal ps2o : ps2_out_type; signal i2ci : i2c_in_type; signal i2co : i2c_out_type; signal spii : spi_in_type; signal spio : spi_out_type; signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0); signal spmi : spimctrl_in_type; signal spmo : spimctrl_out_type; signal ethi : eth_in_type; signal etho : eth_out_type; signal lcdo : apbvga_out_type; signal lcd_data : std_logic_vector(7 downto 0); signal lcd_den : std_ulogic; signal lcd_grest : std_ulogic; signal lcdspii : spi_in_type; signal lcdspio : spi_out_type; signal lcdslvsel : std_logic_vector(1 downto 0); signal lcdclksel : std_logic_vector(1 downto 0); signal lcdclk : std_ulogic; signal lcdclk3x : std_ulogic; signal lcdclklck : std_ulogic; signal vgao : apbvga_out_type; signal vga_data : std_logic_vector(9 downto 0); signal vgaclksel : std_logic_vector(1 downto 0); signal vgaclk : std_ulogic; signal vgaclk3x : std_ulogic; signal vgaclklck : std_ulogic; constant IOAEN : integer := 1; constant BOARD_FREQ : integer := 50000; -- input frequency in KHz constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1; signal lclk, lclkout : std_ulogic; signal dsubre : std_ulogic; attribute syn_keep : boolean; attribute syn_keep of clkm : signal is true; attribute syn_keep of clkml : signal is true; attribute syn_keep of lcdclk : signal is true; attribute syn_keep of lcdclk3x : signal is true; attribute syn_keep of vgaclk : signal is true; attribute syn_keep of vgaclk3x : signal is true; begin ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0'; clklock <= cgo.clklock and lock and lcdclklck and vgaclklck; clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk); clkgen0 : clkgen -- clock generator using toplevel generic 'freq' generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV, sdramen => 1, freq => freq) port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open, clk2x => open, sdclk => ssram_clkl, pciclk => open, cgi => cgi, cgo => cgo); ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (ssram_clk, ssram_clkl); rst0 : rstgen -- reset generator port map (resetn, clkm, clklock, rstn, rawrstn); rstoutn <= resetn; ---------------------------------------------------------------------- --- AVOID BUS CONTENTION -------------------------------------------- ---------------------------------------------------------------------- -- This design uses the ethernet PHY and we must therefore disable the -- video decoder and stay away from the touch panel. -- Video coder hc_td_reset <= '0'; -- Video Decoder Reset ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN, nahbm => maxahbm, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- l3 : if CFG_LEON3 = 1 generate cpu : for i in 0 to NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); end generate; end generate; nodsu : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0 : ahbuart -- Debug UART generic map (hindex => NCPU, pindex => 7, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU)); dsurx_pad : inpad generic map (tech => padtech) port map (hc_uart_rxd, dui.rxd); dsutx_pad : outpad generic map (tech => padtech) port map (hc_uart_txd, duo.txd); end generate; nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1, sden => 0, ram16 => 1) port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo); end generate; memi.brdyn <= '1'; memi.bexcn <= '1'; memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01"; ssr0 : if CFG_SSCTRL = 1 generate ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0, iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP, bus16 => CFG_SSCTRLP16) port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo); end generate; mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads apbo(0) <= apb_none; ahbso(0) <= ahbs_none; roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0)); end generate; mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads addr_pad : outpadv generic map (width => 25, tech => padtech) port map (address, memo.address(25 downto 1)); roms_pad : outpad generic map (tech => padtech) port map (romsn, memo.romsn(0)); oen_pad : outpad generic map (tech => padtech) port map (oen, memo.oen); wri_pad : outpad generic map (tech => padtech) port map (writen, memo.writen); -- pragma translate_off iosn_pad : outpad generic map (tech => padtech) port map (iosn, memo.iosn); -- pragma translate_on -- ssram_adv_n_pad : outpad generic map (tech => padtech) -- port map (ssram_adv_n, vcc(0)); -- ssram_adsp_n_pad : outpad generic map (tech => padtech) -- port map (ssram_adsp_n, gnd(0)); ssram_adscn_pad : outpad generic map (tech => padtech) port map (ssram_adscn, gnd(0)); ssrams_pad : outpad generic map ( tech => padtech) port map (ssram_cen, memo.ramsn(0)); ssram_oen_pad : outpad generic map (tech => padtech) port map (ssram_oen, memo.oen); ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech) port map (ssram_bw, memo.wrn); ssram_wri_pad : outpad generic map (tech => padtech) port map (ssram_wen, memo.writen); data_pad : iopadvv generic map (tech => padtech, width => 32) port map (data(31 downto 0), memo.data(31 downto 0), memo.vbdrive, memi.data(31 downto 0)); end generate; ddrsp0 : if (CFG_DDRSP /= 0) generate ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech, hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1, pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW, clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000, col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1) port map ( resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3), ddr_clkv, ddr_clkbv, open, gnd(0), ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq); ddr_ad <= ddr_adl(12 downto 0); ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0); ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0); end generate; ddrsp1 : if (CFG_DDRSP = 0) generate ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1'; end generate; spimc: if CFG_SPIMCTRL = 1 generate -- SPI Memory Controller spimctrl0 : spimctrl generic map (hindex => 4, hirq => 7, faddr => 16#b00#, fmask => 16#f00#, ioaddr => 16#002#, iomask => 16#fff#, spliten => CFG_SPLIT, oepol => 0, sdcard => CFG_SPIMCTRL_SDCARD, readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE, dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER, altscaler => CFG_SPIMCTRL_ASCALER, pwrupcnt => CFG_SPIMCTRL_PWRUPCNT) port map (rstn, clkm, ahbsi, ahbso(4), spmi, spmo); miso_pad : inpad generic map (tech => padtech) port map (hc_sd_dat, spmi.miso); mosi_pad : outpad generic map (tech => padtech) port map (hc_sd_cmd, spmo.mosi); sck_pad : outpad generic map (tech => padtech) port map (hc_sd_clk, spmo.sck); slvsel0_pad : iopad generic map (tech => padtech) port map (hc_sd_dat3, spmo.csn, spmo.cdcsnoen, spmi.cd); end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.ctsn <= '0'; u1i.extclk <= '0'; upads : if CFG_AHB_UART = 0 generate u1i.rxd <= hc_uart_rxd; hc_uart_txd <= u1o.txd; end generate; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- Timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit grgpio0: grgpio generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH) port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5), gpioi => gpioi, gpioo => gpioo); pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-3 generate gpioi.din(i) <= gpio(i); end generate; gpioi.din(3) <= hc_adc_penirq_n; gpioi.din(4) <= hc_adc_busy; end generate; ps2 : if CFG_PS2_ENABLE /= 0 generate -- PS/2 unit ps20 : apbps2 generic map(pindex => 6, paddr => 6, pirq => 6) port map(rstn, clkm, apbi, apbo(6), ps2i, ps2o); end generate; nops2 : if CFG_PS2_ENABLE = 0 generate apbo(4) <= apb_none; ps2o <= ps2o_none; end generate; ps2clk_pad : iopad generic map (tech => padtech) port map (hc_ps2_clk, ps2o.ps2_clk_o, ps2o.ps2_clk_oe, ps2i.ps2_clk_i); ps2data_pad : iopad generic map (tech => padtech) port map (hc_ps2_dat, ps2o.ps2_data_o, ps2o.ps2_data_oe, ps2i.ps2_data_i); i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master i2c0 : i2cmst generic map (pindex => 8, paddr => 8, pmask => 16#FFF#, pirq => 11, filter => I2C_FILTER) port map (rstn, clkm, apbi, apbo(8), i2ci, i2co); -- The EEK does not use a bi-directional line for the I2C clock i2ci.scl <= i2co.scloen; -- No clock stretch possible -- When SCL output enable is activated the line should go low i2c_scl_pad : outpad generic map (tech => padtech) port map (hc_id_i2cscl, i2co.scloen); i2c_sda_pad : iopad generic map (tech => padtech) port map (hc_id_i2cdat, i2co.sda, i2co.sdaoen, i2ci.sda); end generate i2cm; spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller spi1 : spictrl generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 7, fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG, slvselsz => CFG_SPICTRL_SLVS, odmode => 1, syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT) port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel); miso_pad : iopad generic map (tech => padtech) port map (hc_sd_dat, spio.miso, spio.misooen, spii.miso); mosi_pad : iopad generic map (tech => padtech) port map (hc_sd_cmd, spio.mosi, spio.mosioen, spii.mosi); sck_pad : iopad generic map (tech => padtech) port map (hc_sd_clk, spio.sck, spio.sckoen, spii.sck); slvsel_pad : outpad generic map (tech => padtech) port map (hc_sd_dat3, slvsel(0)); spii.spisel <= '1'; -- Master only end generate spic; ----------------------------------------------------------------------- -- LCD touch panel --------------------------------------------------- ----------------------------------------------------------------------- lcd: if CFG_LCD_ENABLE /= 0 generate -- LCD lcd0 : svgactrl generic map(memtech => memtech, pindex => 11, paddr => 11, hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 30120, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 4) port map(rstn, clkm, lcdclk, apbi, apbo(11), lcdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open); lcdser0: serializer generic map (length => 8) port map (lcdclk3x, lcdo.hsync, lcdo.video_out_b, lcdo.video_out_g, lcdo.video_out_r, lcd_data); lcdclksel <= "00"; lcdclkgen : altera_eek_clkgen generic map (clk0_mul => 166, clk0_div => 250, clk1_mul => 9, clk1_div => 50, clk_freq => BOARD_FREQ) port map (lclk, lcdclk, lcdclk3x, lcdclksel, lcdclklck); lcd_vert_sync_pad : outpad generic map (tech => padtech) port map (hc_vd, lcdo.vsync); lcd_horiz_sync_pad : outpad generic map (tech => padtech) port map (hc_hd, lcdo.hsync); lcd_video_out_pad : outpadv generic map (width => 8, tech => padtech) port map (hc_lcd_data, lcd_data); lcd_video_clock_pad : outpad generic map (tech => padtech) port map (hc_nclk, lcdclk3x); lcd_den <= lcdo.blank; end generate; nolcd : if CFG_LCD_ENABLE = 0 generate apbo(11) <= apb_none; lcdo <= vgao_none; lcd_den <= '0'; -- LCD RGB Data Enable lcdclk <= '0'; lcdclk3x <= '0'; lcdclklck <= '1'; end generate; lcd_den_pad : outpad generic map (tech => padtech) port map (hc_den, lcd_den); lcdsysreset: if CFG_LCD_ENABLE /= 0 or CFG_LCD3T_ENABLE /= 0 generate lcd_grest <= rstn; end generate; lcdalwaysreset: if CFG_LCD_ENABLE = 0 and CFG_LCD3T_ENABLE = 0 generate lcd_grest <= '0'; end generate lcdalwaysreset; lcd_reset_pad : outpad generic map (tech => padtech) -- LCD Global Reset, active low port map (hc_grest, lcd_grest); touch3wire: if CFG_LCD3T_ENABLE /= 0 generate -- LCD 3-wire and touch panel interface -- TODO: -- Interrupt and busy signals not connected touch3spi1 : spictrl generic map (pindex => 12, paddr => 12, pmask => 16#fff#, pirq => 12, fdepth => 2, slvselen => 1, slvselsz => 2, odmode => 0, syncram => 0, ft => 0) port map (rstn, clkm, apbi, apbo(12), lcdspii, lcdspio, lcdslvsel); adc_miso_pad : inpad generic map (tech => padtech) port map (hc_adc_dout, lcdspii.miso); adc_mosi_pad : outpad generic map (tech => padtech) port map (hc_adc_din, lcdspio.mosi); lcd_adc_dclk_pad : outpad generic map (tech => padtech) port map (hc_adc_dclk, lcdspio.sck); hcd_sda_pad : iopad generic map (tech => padtech) port map (hc_sda, lcdspio.mosi, lcdspio.mosioen, lcdspii.mosi); lcdspii.spisel <= '1'; -- Master only end generate; notouch3wire: if CFG_LCD3T_ENABLE = 0 generate lcdslvsel <= (others => '1'); apbo(12) <= apb_none; end generate; hc_adc_cs_n_pad : outpad generic map (tech => padtech) port map (hc_adc_cs_n, lcdslvsel(0)); hc_scen_pad : outpad generic map (tech => padtech) port map (hc_scen, lcdslvsel(1)); ----------------------------------------------------------------------- -- SVGA controller ---------------------------------------------------- ----------------------------------------------------------------------- svga : if CFG_SVGA_ENABLE /= 0 generate -- VGA DAC svga0 : svgactrl generic map(memtech => memtech, pindex => 13, paddr => 13, hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE, clk0 => 40000, clk1 => 25000, clk2 => 0, clk3 => 0, burstlen => 4) port map(rstn, clkm, vgaclk, apbi, apbo(13), vgao, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE), vgaclksel); svgaser0: serializer generic map (length => 8) port map (vgaclk3x, vgao.hsync, vgao.video_out_b, vgao.video_out_g, vgao.video_out_r, vga_data(9 downto 2)); vga_data(1 downto 0) <= (others => '0'); vgaclkgen : altera_eek_clkgen generic map (clk0_mul => 1, clk0_div => 2, clk1_mul => 4, clk1_div => 5, clk_freq => BOARD_FREQ) port map (lclk, vgaclk, vgaclk3x, vgaclksel, vgaclklck); vga_blank_pad : outpad generic map (tech => padtech) port map (hc_vga_blank, vgao.blank); vga_comp_sync_pad : outpad generic map (tech => padtech) port map (hc_vga_sync, vgao.comp_sync); vga_vert_sync_pad : outpad generic map (tech => padtech) port map (hc_vga_vs, vgao.vsync); vga_horiz_sync_pad : outpad generic map (tech => padtech) port map (hc_vga_hs, vgao.hsync); vga_video_out_pad : outpadv generic map (width => 10, tech => padtech) port map (hc_vga_data, vga_data); vga_video_clock_pad : outpad generic map (tech => padtech) port map (hc_vga_clock, vgaclk3x); end generate svga; nosvga : if CFG_SVGA_ENABLE = 0 generate apbo(13) <= apb_none; vgao <= vgao_none; vgaclk <= '0'; vgaclk3x <= '0'; vgaclklck <= '1'; end generate; ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- eth0 : if CFG_GRETH /= 0 generate -- Gaisler ethernet MAC e1 : grethm generic map( hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE, pindex => 10, paddr => 10, pirq => 10, memtech => memtech, mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO, nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G) port map( rst => rstn, clk => clkm, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE), apbi => apbi, apbo => apbo(10), ethi => ethi, etho => etho); emdio_pad : iopad generic map (tech => padtech) port map (hc_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i); etxc_pad : clkpad generic map (tech => padtech, arch => 2) port map (hc_tx_clk, ethi.tx_clk); erxc_pad : clkpad generic map (tech => padtech, arch => 2) port map (hc_rx_clk, ethi.rx_clk); erxd_pad : inpadv generic map (tech => padtech, width => 4) port map (hc_rx_d, ethi.rxd(3 downto 0)); erxdv_pad : inpad generic map (tech => padtech) port map (hc_rx_dv, ethi.rx_dv); erxer_pad : inpad generic map (tech => padtech) port map (hc_rx_err, ethi.rx_er); erxco_pad : inpad generic map (tech => padtech) port map (hc_rx_col, ethi.rx_col); erxcr_pad : inpad generic map (tech => padtech) port map (hc_rx_crs, ethi.rx_crs); etxd_pad : outpadv generic map (tech => padtech, width => 4) port map (hc_tx_d, etho.txd(3 downto 0)); etxen_pad : outpad generic map (tech => padtech) port map (hc_tx_en, etho.tx_en); emdc_pad : outpad generic map (tech => padtech) port map (hc_mdc, etho.mdc); erst_pad : outpad generic map (tech => padtech) port map (hc_eth_reset_n, rawrstn); end generate; ----------------------------------------------------------------------- --- AHB ROM ---------------------------------------------------------- ----------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(6)); end generate; nobpromgen : if CFG_AHBROMEN = 0 generate ahbso(6) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ahbramgen : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE) port map (rstn, clkm, ahbsi, ahbso(7)); end generate; nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_LCD_ENABLE+CFG_SVGA_ENABLE+CFG_GRETH) to NAHBMST-1 generate ahbmo(i) <= ahbm_none; end generate; -- invert signal for input via a key dsubre <= not dsubren; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 Altera Embedded Evaluation Kit Demonstration Design", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on end;

gpl-2.0

3878994eb7bf58b1b2de5fbda71e7a27

schmr/grlib

grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2sgx90-av/testbench.vhd

------------------------------------------------------------------------------ -- LEON3 Demonstration design test bench -- Copyright (C) 2004 Jiri Gaisler, Aeroflex Gaisler ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; library micron; use micron.components.all; library cypress; use cypress.components.all; use work.debug.all; use work.config.all; -- configuration entity testbench is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; ncpu : integer := CFG_NCPU; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; clkperiod : integer := 10; -- system clock period romwidth : integer := 8; -- rom data width (8/32) romdepth : integer := 21; -- rom address depth sramwidth : integer := 32; -- ram data width (8/16/32) sramdepth : integer := 20; -- ram address depth srambanks : integer := 4 -- number of ram banks ); end; architecture behav of testbench is constant promfile : string := "prom.srec"; -- rom contents constant sramfile : string := "ram.srec"; -- ram contents constant sdramfile : string := "ram.srec"; -- sdram contents signal clk : std_logic := '0'; signal clkout, pllref : std_ulogic; signal Rst : std_logic := '0'; -- Reset constant ct : integer := clkperiod/2; signal dsuen, dsutx, dsurx, dsuact : std_ulogic; signal dsurst : std_ulogic; signal test : std_ulogic; signal error : std_logic; signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); signal GND : std_ulogic := '0'; signal VCC : std_ulogic := '1'; signal NC : std_ulogic := 'Z'; signal clk2 : std_ulogic := '1'; signal debugout : std_logic_vector(31 downto 0); -- External Adress/data bus, flash+ssram signal fs_addr : std_logic_vector(24 downto 0); signal fs_data : std_logic_vector(31 downto 0); signal io_cen : std_logic; signal flash_cen : std_ulogic; signal flash_oen : std_ulogic; signal flash_wen : std_ulogic; signal ssram_cen : std_logic; signal ssram_wen : std_logic; signal ssram_bw : std_logic_vector (0 to 3); signal ssram_oen : std_ulogic; signal ssram_clk : std_ulogic; signal ssram_adscn : std_ulogic; signal ssram_adspn : std_ulogic; signal ssram_advn : std_ulogic; signal datazz : std_logic_vector(3 downto 0); signal flash_addr : std_logic_vector(romdepth downto 0); -- muxed data bus signal prd : std_logic_vector(31 downto 0); signal ssd : std_logic_vector(31 downto 0); -- ddr memory signal ddr_clk : std_logic_vector(2 downto 0); signal ddr_clkb : std_logic_vector(2 downto 0); signal ddr_cke : std_logic_vector(1 downto 0); signal ddr_csb : std_logic_vector(1 downto 0); signal ddr_odt : std_logic_vector(1 downto 0); signal ddr_web : std_ulogic; -- ddr write enable signal ddr_rasb : std_ulogic; -- ddr ras signal ddr_casb : std_ulogic; -- ddr cas signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address signal ddr_dq, ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data signal phy_gtx_clk : std_logic; signal phy_mii_data : std_logic; -- ethernet PHY interface signal phy_tx_clk : std_ulogic; signal phy_rx_clk : std_ulogic; signal phy_rx_data : std_logic_vector(7 downto 0); signal phy_dv : std_ulogic; signal phy_rx_er : std_ulogic; signal phy_col : std_ulogic; signal phy_crs : std_ulogic; signal phy_tx_data : std_logic_vector(7 downto 0); signal phy_tx_en : std_ulogic; signal phy_tx_er : std_ulogic; signal phy_mii_clk : std_ulogic; signal ft245_data : std_logic_vector (7 downto 0); signal ft245_rdn : std_logic; signal ft245_wr : std_logic; signal ft245_rxfn : std_logic; signal ft245_txen : std_logic; signal ft245_pwrenn : std_logic; signal plllock : std_ulogic; signal txd1, rxd1 : std_ulogic; --signal txd2, rxd2 : std_ulogic; constant lresp : boolean := false; signal sa : std_logic_vector(14 downto 0); signal sd : std_logic_vector(31 downto 0); component sram32 is generic ( index : integer := 0; -- Byte lane (0 - 3) abits: Positive := 10; -- Default 10 address bits (1Kx32) echk : integer := 0; -- Generate EDAC checksum tacc : integer := 10; -- access time (ns) fname : string := "ram.dat"); -- File to read from port ( a : in std_logic_vector(abits-1 downto 0); d : inout std_logic_vector(31 downto 0); lb : in std_logic; ub : in std_logic; ce : in std_logic; we : in std_ulogic; oe : in std_ulogic); end component; begin -- clock and reset -- 100 MHz clk <= not clk after 5 ns; -- ddr_clkin <= not clk after ct * 1 ns; rst <= dsurst; rxd1 <= '1'; -- ddr_dqs <= (others => 'L'); d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, ncpu, disas, dbguart, pclow ) port map ( resetn => rst, clk => clk, errorn => error, fs_addr => fs_addr, fs_data => fs_data, io_cen => io_cen, flash_cen => flash_cen, flash_oen => flash_oen, flash_wen => flash_wen, ssram_cen => ssram_cen, ssram_wen => ssram_wen, ssram_bw => ssram_bw, ssram_oen => ssram_oen, ssram_clk => ssram_clk, ssram_adscn => ssram_adscn, ssram_adspn => ssram_adspn, ssram_advn => ssram_advn, ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_cke => ddr_cke, ddr_csb => ddr_csb, ddr_odt => ddr_odt, ddr_web => ddr_web, -- ddr write enable ddr_rasb => ddr_rasb, -- ddr ras ddr_casb => ddr_casb, -- ddr cas ddr_dm => ddr_dm, -- ddr dm ddr_dqs => ddr_dqs, -- ddr dqs ddr_ad => ddr_ad, -- ddr address ddr_ba => ddr_ba, -- ddr bank address ddr_dq => ddr_dq, -- ddr data phy_gtx_clk => phy_gtx_clk, phy_mii_data => phy_mii_data, phy_tx_clk => phy_tx_clk, phy_rx_clk => phy_rx_clk, phy_rx_data => phy_rx_data, phy_dv => phy_dv, phy_rx_er => phy_rx_er, phy_col => phy_col, phy_crs => phy_crs, phy_tx_data => phy_tx_data, phy_tx_en => phy_tx_en, phy_tx_er => phy_tx_er, phy_mii_clk => phy_mii_clk, dsuact => dsuact, rxd1 => rxd1, txd1 => txd1, gpio => gpio, ft245_data => ft245_data, ft245_rdn => ft245_rdn, ft245_wr => ft245_wr, ft245_rxfn => ft245_rxfn, ft245_txen => ft245_txen, ft245_pwrenn => ft245_pwrenn ); datazz <= "HHHH"; ssram0 : cy7c1380d generic map (fname => sramfile) port map( ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => fs_data, iAddr => fs_addr(19 downto 1), iMode => gnd, inGW => vcc, inBWE => ssram_wen, inADV => ssram_advn, inADSP => ssram_adspn, inADSC => ssram_adscn, iClk => ssram_clk, inBwa => ssram_bw(3), inBwb => ssram_bw(2), inBwc => ssram_bw(1), inBwd => ssram_bw(0), inOE => ssram_oen, inCE1 => ssram_cen, iCE2 => vcc, inCE3 => gnd, iZz => gnd); -- 16 bit prom flash_addr <= '0'&fs_addr(romdepth-1 downto 0); prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile) port map (a => flash_addr(romdepth-1 downto 0), d => fs_data(31 downto 16), lb => '0', ub => '0', ce => flash_cen, we => flash_wen, oe => flash_oen); -- prd(23 downto 0) <= (others => '0'); -- data mux -- fs_data <= ssd when ssram_oen='0' and ssram_cen='0' else -- prd when flash_oen='0' and flash_cen='0' else -- (others => 'Z'); -- data <= buskeep(data), (others => 'H') after 250 ns; test0 : grtestmod port map ( rst, clk, error, fs_addr(20 downto 1), fs_data, io_cen, flash_oen, flash_wen, open); error <= 'H'; -- ERROR pull-up ddr2delay : delay_wire generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 2.5) port map(a => ddr_dq, b => ddr_dq2); --DDR2 ddr2mem0: ddr2ram generic map ( width => 64, abits => 14, babits => 2, colbits => 10, implbanks => 1, fname => sdramfile ) port map ( ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0), odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn ); -- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns; ddr_dqsn <= (others => 'U'); iuerr : process begin wait for 2500 ns; if to_x01(error) = '1' then wait on error; end if; assert (to_x01(error) = '1') report "*** IU in error mode, simulation halted ***" severity failure ; end process; sd <= buskeep(sd), (others => 'H') after 250 ns; dsucom : process procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is variable w32 : std_logic_vector(31 downto 0); variable c8 : std_logic_vector(7 downto 0); constant txp : time := 160 * 1 ns; begin dsutx <= '1'; dsurst <= '0'; wait for 500 ns; dsurst <= '1'; wait; wait for 5000 ns; txc(dsutx, 16#55#, txp); -- sync uart -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp); -- txc(dsutx, 16#c0#, txp); -- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); -- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp); txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp); txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp); txc(dsutx, 16#80#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); txc(dsutx, 16#a0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); end; begin dsucfg(dsutx, dsurx); wait; end process; end ;

gpl-2.0

eee98c5b3cc673e4274e0fb649e57cf9

mcoughli/root_of_trust

operational_os/hls/contact_discovery_axi_one_db_load/solution1/syn/vhdl/compare.vhd

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity compare is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; ap_ce : IN STD_LOGIC; db_index : IN STD_LOGIC_VECTOR (12 downto 0); contacts_index : IN STD_LOGIC_VECTOR (7 downto 0); contacts_address0 : OUT STD_LOGIC_VECTOR (12 downto 0); contacts_ce0 : OUT STD_LOGIC; contacts_q0 : IN STD_LOGIC_VECTOR (7 downto 0); contacts_address1 : OUT STD_LOGIC_VECTOR (12 downto 0); contacts_ce1 : OUT STD_LOGIC; contacts_q1 : IN STD_LOGIC_VECTOR (7 downto 0); database_address0 : OUT STD_LOGIC_VECTOR (18 downto 0); database_ce0 : OUT STD_LOGIC; database_q0 : IN STD_LOGIC_VECTOR (7 downto 0); database_address1 : OUT STD_LOGIC_VECTOR (18 downto 0); database_ce1 : OUT STD_LOGIC; database_q1 : IN STD_LOGIC_VECTOR (7 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end; architecture behav of compare is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000"; constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000"; constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000"; constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000"; constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000000000"; constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000010000000000"; constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000100000000000"; constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000001000000000000"; constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000010000000000000"; constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000100000000000000"; constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000001000000000000000"; constant ap_ST_fsm_pp0_stage16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000010000000000000000"; constant ap_ST_fsm_pp0_stage17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000100000000000000000"; constant ap_ST_fsm_pp0_stage18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000001000000000000000000"; constant ap_ST_fsm_pp0_stage19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000010000000000000000000"; constant ap_ST_fsm_pp0_stage20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000100000000000000000000"; constant ap_ST_fsm_pp0_stage21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000001000000000000000000000"; constant ap_ST_fsm_pp0_stage22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000010000000000000000000000"; constant ap_ST_fsm_pp0_stage23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000100000000000000000000000"; constant ap_ST_fsm_pp0_stage24 : STD_LOGIC_VECTOR (31 downto 0) := "00000001000000000000000000000000"; constant ap_ST_fsm_pp0_stage25 : STD_LOGIC_VECTOR (31 downto 0) := "00000010000000000000000000000000"; constant ap_ST_fsm_pp0_stage26 : STD_LOGIC_VECTOR (31 downto 0) := "00000100000000000000000000000000"; constant ap_ST_fsm_pp0_stage27 : STD_LOGIC_VECTOR (31 downto 0) := "00001000000000000000000000000000"; constant ap_ST_fsm_pp0_stage28 : STD_LOGIC_VECTOR (31 downto 0) := "00010000000000000000000000000000"; constant ap_ST_fsm_pp0_stage29 : STD_LOGIC_VECTOR (31 downto 0) := "00100000000000000000000000000000"; constant ap_ST_fsm_pp0_stage30 : STD_LOGIC_VECTOR (31 downto 0) := "01000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage31 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000"; constant ap_const_boolean_1 : BOOLEAN := true; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_boolean_0 : BOOLEAN := false; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001"; constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010"; constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011"; constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110"; constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111"; constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000"; constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001"; constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010"; constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011"; constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100"; constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101"; constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110"; constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_const_lv13_1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001"; constant ap_const_lv19_1 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000001"; constant ap_const_lv13_2 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000010"; constant ap_const_lv19_2 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000010"; constant ap_const_lv13_3 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000011"; constant ap_const_lv19_3 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000011"; constant ap_const_lv13_4 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000100"; constant ap_const_lv19_4 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000100"; constant ap_const_lv13_5 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000101"; constant ap_const_lv19_5 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000101"; constant ap_const_lv13_6 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000110"; constant ap_const_lv19_6 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000110"; constant ap_const_lv13_7 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000111"; constant ap_const_lv19_7 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000111"; constant ap_const_lv13_8 : STD_LOGIC_VECTOR (12 downto 0) := "0000000001000"; constant ap_const_lv19_8 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000001000"; constant ap_const_lv13_9 : STD_LOGIC_VECTOR (12 downto 0) := "0000000001001"; constant ap_const_lv19_9 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000001001"; constant ap_const_lv13_A : STD_LOGIC_VECTOR (12 downto 0) := "0000000001010"; constant ap_const_lv19_A : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000001010"; constant ap_const_lv13_B : STD_LOGIC_VECTOR (12 downto 0) := "0000000001011"; constant ap_const_lv19_B : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000001011"; constant ap_const_lv13_C : STD_LOGIC_VECTOR (12 downto 0) := "0000000001100"; constant ap_const_lv19_C : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000001100"; constant ap_const_lv13_D : STD_LOGIC_VECTOR (12 downto 0) := "0000000001101"; constant ap_const_lv19_D : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000001101"; constant ap_const_lv13_E : STD_LOGIC_VECTOR (12 downto 0) := "0000000001110"; constant ap_const_lv19_E : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000001110"; constant ap_const_lv13_F : STD_LOGIC_VECTOR (12 downto 0) := "0000000001111"; constant ap_const_lv19_F : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000001111"; constant ap_const_lv13_10 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010000"; constant ap_const_lv19_10 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000010000"; constant ap_const_lv13_11 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010001"; constant ap_const_lv19_11 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000010001"; constant ap_const_lv13_12 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010010"; constant ap_const_lv19_12 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000010010"; constant ap_const_lv13_13 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010011"; constant ap_const_lv19_13 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000010011"; constant ap_const_lv13_14 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010100"; constant ap_const_lv19_14 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000010100"; constant ap_const_lv13_15 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010101"; constant ap_const_lv19_15 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000010101"; constant ap_const_lv13_16 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010110"; constant ap_const_lv19_16 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000010110"; constant ap_const_lv13_17 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010111"; constant ap_const_lv19_17 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000010111"; constant ap_const_lv13_18 : STD_LOGIC_VECTOR (12 downto 0) := "0000000011000"; constant ap_const_lv19_18 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000011000"; constant ap_const_lv13_19 : STD_LOGIC_VECTOR (12 downto 0) := "0000000011001"; constant ap_const_lv19_19 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000011001"; constant ap_const_lv13_1A : STD_LOGIC_VECTOR (12 downto 0) := "0000000011010"; constant ap_const_lv19_1A : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000011010"; constant ap_const_lv13_1B : STD_LOGIC_VECTOR (12 downto 0) := "0000000011011"; constant ap_const_lv19_1B : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000011011"; constant ap_const_lv13_1C : STD_LOGIC_VECTOR (12 downto 0) := "0000000011100"; constant ap_const_lv19_1C : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000011100"; constant ap_const_lv13_1D : STD_LOGIC_VECTOR (12 downto 0) := "0000000011101"; constant ap_const_lv19_1D : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000011101"; constant ap_const_lv13_1E : STD_LOGIC_VECTOR (12 downto 0) := "0000000011110"; constant ap_const_lv19_1E : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000011110"; constant ap_const_lv13_1F : STD_LOGIC_VECTOR (12 downto 0) := "0000000011111"; constant ap_const_lv19_1F : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000011111"; constant ap_const_lv13_20 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100000"; constant ap_const_lv19_20 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000100000"; constant ap_const_lv13_21 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100001"; constant ap_const_lv19_21 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000100001"; constant ap_const_lv13_22 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100010"; constant ap_const_lv19_22 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000100010"; constant ap_const_lv13_23 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100011"; constant ap_const_lv19_23 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000100011"; constant ap_const_lv13_24 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100100"; constant ap_const_lv19_24 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000100100"; constant ap_const_lv13_25 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100101"; constant ap_const_lv19_25 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000100101"; constant ap_const_lv13_26 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100110"; constant ap_const_lv19_26 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000100110"; constant ap_const_lv13_27 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100111"; constant ap_const_lv19_27 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000100111"; constant ap_const_lv13_28 : STD_LOGIC_VECTOR (12 downto 0) := "0000000101000"; constant ap_const_lv19_28 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000101000"; constant ap_const_lv13_29 : STD_LOGIC_VECTOR (12 downto 0) := "0000000101001"; constant ap_const_lv19_29 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000101001"; constant ap_const_lv13_2A : STD_LOGIC_VECTOR (12 downto 0) := "0000000101010"; constant ap_const_lv19_2A : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000101010"; constant ap_const_lv13_2B : STD_LOGIC_VECTOR (12 downto 0) := "0000000101011"; constant ap_const_lv19_2B : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000101011"; constant ap_const_lv13_2C : STD_LOGIC_VECTOR (12 downto 0) := "0000000101100"; constant ap_const_lv19_2C : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000101100"; constant ap_const_lv13_2D : STD_LOGIC_VECTOR (12 downto 0) := "0000000101101"; constant ap_const_lv19_2D : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000101101"; constant ap_const_lv13_2E : STD_LOGIC_VECTOR (12 downto 0) := "0000000101110"; constant ap_const_lv19_2E : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000101110"; constant ap_const_lv13_2F : STD_LOGIC_VECTOR (12 downto 0) := "0000000101111"; constant ap_const_lv19_2F : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000101111"; constant ap_const_lv13_30 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110000"; constant ap_const_lv19_30 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000110000"; constant ap_const_lv13_31 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110001"; constant ap_const_lv19_31 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000110001"; constant ap_const_lv13_32 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110010"; constant ap_const_lv19_32 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000110010"; constant ap_const_lv13_33 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110011"; constant ap_const_lv19_33 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000110011"; constant ap_const_lv13_34 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110100"; constant ap_const_lv19_34 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000110100"; constant ap_const_lv13_35 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110101"; constant ap_const_lv19_35 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000110101"; constant ap_const_lv13_36 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110110"; constant ap_const_lv19_36 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000110110"; constant ap_const_lv13_37 : STD_LOGIC_VECTOR (12 downto 0) := "0000000110111"; constant ap_const_lv19_37 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000110111"; constant ap_const_lv13_38 : STD_LOGIC_VECTOR (12 downto 0) := "0000000111000"; constant ap_const_lv19_38 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000111000"; constant ap_const_lv13_39 : STD_LOGIC_VECTOR (12 downto 0) := "0000000111001"; constant ap_const_lv19_39 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000111001"; constant ap_const_lv13_3A : STD_LOGIC_VECTOR (12 downto 0) := "0000000111010"; constant ap_const_lv19_3A : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000111010"; constant ap_const_lv13_3B : STD_LOGIC_VECTOR (12 downto 0) := "0000000111011"; constant ap_const_lv19_3B : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000111011"; constant ap_const_lv13_3C : STD_LOGIC_VECTOR (12 downto 0) := "0000000111100"; constant ap_const_lv19_3C : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000111100"; constant ap_const_lv13_3D : STD_LOGIC_VECTOR (12 downto 0) := "0000000111101"; constant ap_const_lv19_3D : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000111101"; constant ap_const_lv13_3E : STD_LOGIC_VECTOR (12 downto 0) := "0000000111110"; constant ap_const_lv19_3E : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000111110"; constant ap_const_lv13_3F : STD_LOGIC_VECTOR (12 downto 0) := "0000000111111"; constant ap_const_lv19_3F : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000111111"; signal ap_CS_fsm : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_pp0_stage0 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none"; signal ap_enable_reg_pp0_iter0 : STD_LOGIC; signal ap_block_pp0_stage0_flag00000000 : BOOLEAN; signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0'; signal ap_idle_pp0 : STD_LOGIC; signal ap_CS_fsm_pp0_stage31 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage31 : signal is "none"; signal ap_block_state32_pp0_stage31_iter0 : BOOLEAN; signal ap_block_pp0_stage31_flag00011001 : BOOLEAN; signal tmp_fu_1338_p3 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_reg_2957 : STD_LOGIC_VECTOR (12 downto 0); signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN; signal ap_block_state33_pp0_stage0_iter1 : BOOLEAN; signal ap_block_pp0_stage0_flag00011001 : BOOLEAN; signal tmp_s_fu_1346_p3 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_s_reg_3023 : STD_LOGIC_VECTOR (18 downto 0); signal grp_fu_1322_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_reg_3109 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none"; signal ap_block_state2_pp0_stage1_iter0 : BOOLEAN; signal ap_block_pp0_stage1_flag00011001 : BOOLEAN; signal grp_fu_1328_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_1_reg_3114 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none"; signal ap_block_state3_pp0_stage2_iter0 : BOOLEAN; signal ap_block_pp0_stage2_flag00011001 : BOOLEAN; signal tmp4_fu_1476_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp4_reg_3159 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_4_reg_3164 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage3 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none"; signal ap_block_state4_pp0_stage3_iter0 : BOOLEAN; signal ap_block_pp0_stage3_flag00011001 : BOOLEAN; signal tmp_9_5_reg_3169 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage4 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none"; signal ap_block_state5_pp0_stage4_iter0 : BOOLEAN; signal ap_block_pp0_stage4_flag00011001 : BOOLEAN; signal tmp3_fu_1578_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp3_reg_3214 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_8_reg_3219 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage5 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none"; signal ap_block_state6_pp0_stage5_iter0 : BOOLEAN; signal ap_block_pp0_stage5_flag00011001 : BOOLEAN; signal tmp_9_9_reg_3224 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage6 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none"; signal ap_block_state7_pp0_stage6_iter0 : BOOLEAN; signal ap_block_pp0_stage6_flag00011001 : BOOLEAN; signal tmp11_fu_1673_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp11_reg_3269 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_11_reg_3274 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage7 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none"; signal ap_block_state8_pp0_stage7_iter0 : BOOLEAN; signal ap_block_pp0_stage7_flag00011001 : BOOLEAN; signal tmp_9_12_reg_3279 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage8 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none"; signal ap_block_state9_pp0_stage8_iter0 : BOOLEAN; signal ap_block_pp0_stage8_flag00011001 : BOOLEAN; signal tmp2_fu_1780_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp2_reg_3324 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_15_reg_3329 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage9 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none"; signal ap_block_state10_pp0_stage9_iter0 : BOOLEAN; signal ap_block_pp0_stage9_flag00011001 : BOOLEAN; signal tmp_9_16_reg_3334 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage10 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none"; signal ap_block_state11_pp0_stage10_iter0 : BOOLEAN; signal ap_block_pp0_stage10_flag00011001 : BOOLEAN; signal tmp19_fu_1875_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp19_reg_3379 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_19_reg_3384 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage11 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none"; signal ap_block_state12_pp0_stage11_iter0 : BOOLEAN; signal ap_block_pp0_stage11_flag00011001 : BOOLEAN; signal tmp_9_20_reg_3389 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage12 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none"; signal ap_block_state13_pp0_stage12_iter0 : BOOLEAN; signal ap_block_pp0_stage12_flag00011001 : BOOLEAN; signal tmp18_fu_1977_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp18_reg_3434 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_23_reg_3439 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage13 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none"; signal ap_block_state14_pp0_stage13_iter0 : BOOLEAN; signal ap_block_pp0_stage13_flag00011001 : BOOLEAN; signal tmp_9_24_reg_3444 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage14 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none"; signal ap_block_state15_pp0_stage14_iter0 : BOOLEAN; signal ap_block_pp0_stage14_flag00011001 : BOOLEAN; signal tmp26_fu_2072_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp26_reg_3489 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_27_reg_3494 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage15 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none"; signal ap_block_state16_pp0_stage15_iter0 : BOOLEAN; signal ap_block_pp0_stage15_flag00011001 : BOOLEAN; signal tmp_9_28_reg_3499 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage16 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage16 : signal is "none"; signal ap_block_state17_pp0_stage16_iter0 : BOOLEAN; signal ap_block_pp0_stage16_flag00011001 : BOOLEAN; signal tmp17_fu_2179_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp17_reg_3544 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_31_reg_3549 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage17 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage17 : signal is "none"; signal ap_block_state18_pp0_stage17_iter0 : BOOLEAN; signal ap_block_pp0_stage17_flag00011001 : BOOLEAN; signal tmp_9_32_reg_3554 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage18 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage18 : signal is "none"; signal ap_block_state19_pp0_stage18_iter0 : BOOLEAN; signal ap_block_pp0_stage18_flag00011001 : BOOLEAN; signal tmp35_fu_2274_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp35_reg_3599 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_35_reg_3604 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage19 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage19 : signal is "none"; signal ap_block_state20_pp0_stage19_iter0 : BOOLEAN; signal ap_block_pp0_stage19_flag00011001 : BOOLEAN; signal tmp_9_36_reg_3609 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage20 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage20 : signal is "none"; signal ap_block_state21_pp0_stage20_iter0 : BOOLEAN; signal ap_block_pp0_stage20_flag00011001 : BOOLEAN; signal tmp34_fu_2376_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp34_reg_3654 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_39_reg_3659 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage21 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage21 : signal is "none"; signal ap_block_state22_pp0_stage21_iter0 : BOOLEAN; signal ap_block_pp0_stage21_flag00011001 : BOOLEAN; signal tmp_9_40_reg_3664 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage22 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage22 : signal is "none"; signal ap_block_state23_pp0_stage22_iter0 : BOOLEAN; signal ap_block_pp0_stage22_flag00011001 : BOOLEAN; signal tmp42_fu_2471_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp42_reg_3709 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_43_reg_3714 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage23 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage23 : signal is "none"; signal ap_block_state24_pp0_stage23_iter0 : BOOLEAN; signal ap_block_pp0_stage23_flag00011001 : BOOLEAN; signal tmp_9_44_reg_3719 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage24 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage24 : signal is "none"; signal ap_block_state25_pp0_stage24_iter0 : BOOLEAN; signal ap_block_pp0_stage24_flag00011001 : BOOLEAN; signal tmp33_fu_2578_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp33_reg_3764 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_47_reg_3769 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage25 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage25 : signal is "none"; signal ap_block_state26_pp0_stage25_iter0 : BOOLEAN; signal ap_block_pp0_stage25_flag00011001 : BOOLEAN; signal tmp_9_48_reg_3774 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage26 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage26 : signal is "none"; signal ap_block_state27_pp0_stage26_iter0 : BOOLEAN; signal ap_block_pp0_stage26_flag00011001 : BOOLEAN; signal tmp50_fu_2673_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp50_reg_3819 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_51_reg_3824 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage27 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage27 : signal is "none"; signal ap_block_state28_pp0_stage27_iter0 : BOOLEAN; signal ap_block_pp0_stage27_flag00011001 : BOOLEAN; signal tmp_9_52_reg_3829 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage28 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage28 : signal is "none"; signal ap_block_state29_pp0_stage28_iter0 : BOOLEAN; signal ap_block_pp0_stage28_flag00011001 : BOOLEAN; signal tmp49_fu_2775_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp49_reg_3874 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_55_reg_3879 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage29 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage29 : signal is "none"; signal ap_block_state30_pp0_stage29_iter0 : BOOLEAN; signal ap_block_pp0_stage29_flag00011001 : BOOLEAN; signal tmp_9_56_reg_3884 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage30 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage30 : signal is "none"; signal ap_block_state31_pp0_stage30_iter0 : BOOLEAN; signal ap_block_pp0_stage30_flag00011001 : BOOLEAN; signal tmp57_fu_2870_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp57_reg_3929 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_59_reg_3934 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_9_60_reg_3939 : STD_LOGIC_VECTOR (0 downto 0); signal ap_enable_reg_pp0_iter0_reg : STD_LOGIC := '0'; signal ap_block_pp0_stage0_flag00011011 : BOOLEAN; signal ap_block_pp0_stage31_flag00011011 : BOOLEAN; signal tmp_6_fu_1354_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_fu_1359_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_1_fu_1370_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_1_fu_1381_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_2_fu_1391_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage1_flag00000000 : BOOLEAN; signal tmp_8_2_fu_1401_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_3_fu_1411_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_3_fu_1421_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_4_fu_1431_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage2_flag00000000 : BOOLEAN; signal tmp_8_4_fu_1441_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_5_fu_1451_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_5_fu_1461_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_6_fu_1487_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage3_flag00000000 : BOOLEAN; signal tmp_8_6_fu_1497_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_7_fu_1507_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_7_fu_1517_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_8_fu_1527_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage4_flag00000000 : BOOLEAN; signal tmp_8_8_fu_1537_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_9_fu_1547_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_9_fu_1557_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_s_fu_1588_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage5_flag00000000 : BOOLEAN; signal tmp_8_s_fu_1598_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_10_fu_1608_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_10_fu_1618_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_11_fu_1628_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage6_flag00000000 : BOOLEAN; signal tmp_8_11_fu_1638_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_12_fu_1648_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_12_fu_1658_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_13_fu_1684_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage7_flag00000000 : BOOLEAN; signal tmp_8_13_fu_1694_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_14_fu_1704_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_14_fu_1714_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_15_fu_1724_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage8_flag00000000 : BOOLEAN; signal tmp_8_15_fu_1734_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_16_fu_1744_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_16_fu_1754_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_17_fu_1790_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage9_flag00000000 : BOOLEAN; signal tmp_8_17_fu_1800_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_18_fu_1810_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_18_fu_1820_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_19_fu_1830_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage10_flag00000000 : BOOLEAN; signal tmp_8_19_fu_1840_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_20_fu_1850_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_20_fu_1860_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_21_fu_1886_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage11_flag00000000 : BOOLEAN; signal tmp_8_21_fu_1896_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_22_fu_1906_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_22_fu_1916_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_23_fu_1926_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage12_flag00000000 : BOOLEAN; signal tmp_8_23_fu_1936_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_24_fu_1946_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_24_fu_1956_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_25_fu_1987_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage13_flag00000000 : BOOLEAN; signal tmp_8_25_fu_1997_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_26_fu_2007_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_26_fu_2017_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_27_fu_2027_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage14_flag00000000 : BOOLEAN; signal tmp_8_27_fu_2037_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_28_fu_2047_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_28_fu_2057_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_29_fu_2083_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage15_flag00000000 : BOOLEAN; signal tmp_8_29_fu_2093_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_30_fu_2103_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_30_fu_2113_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_31_fu_2123_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage16_flag00000000 : BOOLEAN; signal tmp_8_31_fu_2133_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_32_fu_2143_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_32_fu_2153_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_33_fu_2189_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage17_flag00000000 : BOOLEAN; signal tmp_8_33_fu_2199_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_34_fu_2209_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_34_fu_2219_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_35_fu_2229_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage18_flag00000000 : BOOLEAN; signal tmp_8_35_fu_2239_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_36_fu_2249_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_36_fu_2259_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_37_fu_2285_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage19_flag00000000 : BOOLEAN; signal tmp_8_37_fu_2295_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_38_fu_2305_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_38_fu_2315_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_39_fu_2325_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage20_flag00000000 : BOOLEAN; signal tmp_8_39_fu_2335_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_40_fu_2345_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_40_fu_2355_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_41_fu_2386_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage21_flag00000000 : BOOLEAN; signal tmp_8_41_fu_2396_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_42_fu_2406_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_42_fu_2416_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_43_fu_2426_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage22_flag00000000 : BOOLEAN; signal tmp_8_43_fu_2436_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_44_fu_2446_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_44_fu_2456_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_45_fu_2482_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage23_flag00000000 : BOOLEAN; signal tmp_8_45_fu_2492_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_46_fu_2502_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_46_fu_2512_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_47_fu_2522_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage24_flag00000000 : BOOLEAN; signal tmp_8_47_fu_2532_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_48_fu_2542_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_48_fu_2552_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_49_fu_2588_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage25_flag00000000 : BOOLEAN; signal tmp_8_49_fu_2598_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_50_fu_2608_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_50_fu_2618_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_51_fu_2628_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage26_flag00000000 : BOOLEAN; signal tmp_8_51_fu_2638_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_52_fu_2648_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_52_fu_2658_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_53_fu_2684_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage27_flag00000000 : BOOLEAN; signal tmp_8_53_fu_2694_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_54_fu_2704_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_54_fu_2714_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_55_fu_2724_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage28_flag00000000 : BOOLEAN; signal tmp_8_55_fu_2734_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_56_fu_2744_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_56_fu_2754_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_57_fu_2785_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage29_flag00000000 : BOOLEAN; signal tmp_8_57_fu_2795_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_58_fu_2805_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_58_fu_2815_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_59_fu_2825_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage30_flag00000000 : BOOLEAN; signal tmp_8_59_fu_2835_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_60_fu_2845_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_60_fu_2855_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_61_fu_2881_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_pp0_stage31_flag00000000 : BOOLEAN; signal tmp_8_61_fu_2891_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_6_62_fu_2901_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_8_62_fu_2911_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_129_fu_1334_p1 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_5_s_fu_1364_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_s_fu_1375_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_1_fu_1386_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_1_fu_1396_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_2_fu_1406_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_2_fu_1416_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_3_fu_1426_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_3_fu_1436_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_4_fu_1446_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_4_fu_1456_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp6_fu_1470_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp5_fu_1466_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_5_fu_1482_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_5_fu_1492_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_6_fu_1502_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_6_fu_1512_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_7_fu_1522_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_7_fu_1532_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_8_fu_1542_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_8_fu_1552_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp9_fu_1566_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp8_fu_1562_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp7_fu_1572_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_9_fu_1583_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_9_fu_1593_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_10_fu_1603_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_10_fu_1613_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_11_fu_1623_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_11_fu_1633_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_12_fu_1643_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_12_fu_1653_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp13_fu_1667_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp12_fu_1663_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_13_fu_1679_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_13_fu_1689_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_14_fu_1699_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_14_fu_1709_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_15_fu_1719_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_15_fu_1729_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_16_fu_1739_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_16_fu_1749_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp16_fu_1763_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp15_fu_1759_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp14_fu_1769_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp10_fu_1775_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_17_fu_1785_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_17_fu_1795_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_18_fu_1805_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_18_fu_1815_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_19_fu_1825_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_19_fu_1835_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_20_fu_1845_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_20_fu_1855_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp21_fu_1869_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp20_fu_1865_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_21_fu_1881_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_21_fu_1891_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_22_fu_1901_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_22_fu_1911_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_23_fu_1921_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_23_fu_1931_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_24_fu_1941_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_24_fu_1951_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp24_fu_1965_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp23_fu_1961_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp22_fu_1971_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_25_fu_1982_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_25_fu_1992_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_26_fu_2002_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_26_fu_2012_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_27_fu_2022_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_27_fu_2032_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_28_fu_2042_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_28_fu_2052_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp28_fu_2066_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp27_fu_2062_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_29_fu_2078_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_29_fu_2088_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_30_fu_2098_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_30_fu_2108_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_31_fu_2118_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_31_fu_2128_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_32_fu_2138_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_32_fu_2148_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp31_fu_2162_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp30_fu_2158_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp29_fu_2168_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp25_fu_2174_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_33_fu_2184_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_33_fu_2194_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_34_fu_2204_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_34_fu_2214_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_35_fu_2224_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_35_fu_2234_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_36_fu_2244_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_36_fu_2254_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp37_fu_2268_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp36_fu_2264_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_37_fu_2280_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_37_fu_2290_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_38_fu_2300_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_38_fu_2310_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_39_fu_2320_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_39_fu_2330_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_40_fu_2340_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_40_fu_2350_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp40_fu_2364_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp39_fu_2360_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp38_fu_2370_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_41_fu_2381_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_41_fu_2391_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_42_fu_2401_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_42_fu_2411_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_43_fu_2421_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_43_fu_2431_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_44_fu_2441_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_44_fu_2451_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp44_fu_2465_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp43_fu_2461_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_45_fu_2477_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_45_fu_2487_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_46_fu_2497_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_46_fu_2507_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_47_fu_2517_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_47_fu_2527_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_48_fu_2537_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_48_fu_2547_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp47_fu_2561_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp46_fu_2557_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp45_fu_2567_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp41_fu_2573_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_49_fu_2583_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_49_fu_2593_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_50_fu_2603_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_50_fu_2613_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_51_fu_2623_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_51_fu_2633_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_52_fu_2643_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_52_fu_2653_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp52_fu_2667_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp51_fu_2663_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_53_fu_2679_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_53_fu_2689_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_54_fu_2699_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_54_fu_2709_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_55_fu_2719_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_55_fu_2729_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_56_fu_2739_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_56_fu_2749_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp55_fu_2763_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp54_fu_2759_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp53_fu_2769_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_57_fu_2780_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_57_fu_2790_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_58_fu_2800_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_58_fu_2810_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_59_fu_2820_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_59_fu_2830_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_60_fu_2840_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_60_fu_2850_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp59_fu_2864_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp58_fu_2860_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_5_61_fu_2876_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_61_fu_2886_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp_5_62_fu_2896_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_7_62_fu_2906_p2 : STD_LOGIC_VECTOR (18 downto 0); signal tmp62_fu_2924_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp61_fu_2920_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp60_fu_2930_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp56_fu_2936_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp48_fu_2941_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp32_fu_2946_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp1_fu_2916_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (31 downto 0); signal ap_idle_pp0_0to0 : STD_LOGIC; signal ap_reset_idle_pp0 : STD_LOGIC; signal ap_idle_pp0_1to1 : STD_LOGIC; signal ap_block_pp0_stage1_flag00011011 : BOOLEAN; signal ap_block_pp0_stage2_flag00011011 : BOOLEAN; signal ap_block_pp0_stage3_flag00011011 : BOOLEAN; signal ap_block_pp0_stage4_flag00011011 : BOOLEAN; signal ap_block_pp0_stage5_flag00011011 : BOOLEAN; signal ap_block_pp0_stage6_flag00011011 : BOOLEAN; signal ap_block_pp0_stage7_flag00011011 : BOOLEAN; signal ap_block_pp0_stage8_flag00011011 : BOOLEAN; signal ap_block_pp0_stage9_flag00011011 : BOOLEAN; signal ap_block_pp0_stage10_flag00011011 : BOOLEAN; signal ap_block_pp0_stage11_flag00011011 : BOOLEAN; signal ap_block_pp0_stage12_flag00011011 : BOOLEAN; signal ap_block_pp0_stage13_flag00011011 : BOOLEAN; signal ap_block_pp0_stage14_flag00011011 : BOOLEAN; signal ap_block_pp0_stage15_flag00011011 : BOOLEAN; signal ap_block_pp0_stage16_flag00011011 : BOOLEAN; signal ap_block_pp0_stage17_flag00011011 : BOOLEAN; signal ap_block_pp0_stage18_flag00011011 : BOOLEAN; signal ap_block_pp0_stage19_flag00011011 : BOOLEAN; signal ap_block_pp0_stage20_flag00011011 : BOOLEAN; signal ap_block_pp0_stage21_flag00011011 : BOOLEAN; signal ap_block_pp0_stage22_flag00011011 : BOOLEAN; signal ap_block_pp0_stage23_flag00011011 : BOOLEAN; signal ap_block_pp0_stage24_flag00011011 : BOOLEAN; signal ap_block_pp0_stage25_flag00011011 : BOOLEAN; signal ap_block_pp0_stage26_flag00011011 : BOOLEAN; signal ap_block_pp0_stage27_flag00011011 : BOOLEAN; signal ap_block_pp0_stage28_flag00011011 : BOOLEAN; signal ap_block_pp0_stage29_flag00011011 : BOOLEAN; signal ap_block_pp0_stage30_flag00011011 : BOOLEAN; signal ap_enable_pp0 : STD_LOGIC; begin ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_fsm_pp0_stage0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_enable_reg_pp0_iter0_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_enable_reg_pp0_iter0_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then ap_enable_reg_pp0_iter0_reg <= ap_start; end if; end if; end if; end process; ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0))) then ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; end if; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then tmp11_reg_3269 <= tmp11_fu_1673_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0))) then tmp17_reg_3544 <= tmp17_fu_2179_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then tmp18_reg_3434 <= tmp18_fu_1977_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then tmp19_reg_3379 <= tmp19_fu_1875_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then tmp26_reg_3489 <= tmp26_fu_2072_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then tmp2_reg_3324 <= tmp2_fu_1780_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0))) then tmp33_reg_3764 <= tmp33_fu_2578_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0))) then tmp34_reg_3654 <= tmp34_fu_2376_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0))) then tmp35_reg_3599 <= tmp35_fu_2274_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then tmp3_reg_3214 <= tmp3_fu_1578_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0))) then tmp42_reg_3709 <= tmp42_fu_2471_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0))) then tmp49_reg_3874 <= tmp49_fu_2775_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then tmp4_reg_3159 <= tmp4_fu_1476_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0))) then tmp50_reg_3819 <= tmp50_fu_2673_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0))) then tmp57_reg_3929 <= tmp57_fu_2870_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then tmp_9_11_reg_3274 <= grp_fu_1322_p2; tmp_9_12_reg_3279 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then tmp_9_15_reg_3329 <= grp_fu_1322_p2; tmp_9_16_reg_3334 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then tmp_9_19_reg_3384 <= grp_fu_1322_p2; tmp_9_20_reg_3389 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then tmp_9_1_reg_3114 <= grp_fu_1328_p2; tmp_9_reg_3109 <= grp_fu_1322_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then tmp_9_23_reg_3439 <= grp_fu_1322_p2; tmp_9_24_reg_3444 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then tmp_9_27_reg_3494 <= grp_fu_1322_p2; tmp_9_28_reg_3499 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0))) then tmp_9_31_reg_3549 <= grp_fu_1322_p2; tmp_9_32_reg_3554 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0))) then tmp_9_35_reg_3604 <= grp_fu_1322_p2; tmp_9_36_reg_3609 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0))) then tmp_9_39_reg_3659 <= grp_fu_1322_p2; tmp_9_40_reg_3664 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0))) then tmp_9_43_reg_3714 <= grp_fu_1322_p2; tmp_9_44_reg_3719 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0))) then tmp_9_47_reg_3769 <= grp_fu_1322_p2; tmp_9_48_reg_3774 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then tmp_9_4_reg_3164 <= grp_fu_1322_p2; tmp_9_5_reg_3169 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0))) then tmp_9_51_reg_3824 <= grp_fu_1322_p2; tmp_9_52_reg_3829 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0))) then tmp_9_55_reg_3879 <= grp_fu_1322_p2; tmp_9_56_reg_3884 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then tmp_9_59_reg_3934 <= grp_fu_1322_p2; tmp_9_60_reg_3939 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then tmp_9_8_reg_3219 <= grp_fu_1322_p2; tmp_9_9_reg_3224 <= grp_fu_1328_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then tmp_reg_2957(12 downto 6) <= tmp_fu_1338_p3(12 downto 6); tmp_s_reg_3023(18 downto 6) <= tmp_s_fu_1346_p3(18 downto 6); end if; end if; end process; tmp_reg_2957(5 downto 0) <= "000000"; tmp_s_reg_3023(5 downto 0) <= "000000"; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage31_flag00011011, ap_reset_idle_pp0, ap_idle_pp0_1to1, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage15_flag00011011, ap_block_pp0_stage16_flag00011011, ap_block_pp0_stage17_flag00011011, ap_block_pp0_stage18_flag00011011, ap_block_pp0_stage19_flag00011011, ap_block_pp0_stage20_flag00011011, ap_block_pp0_stage21_flag00011011, ap_block_pp0_stage22_flag00011011, ap_block_pp0_stage23_flag00011011, ap_block_pp0_stage24_flag00011011, ap_block_pp0_stage25_flag00011011, ap_block_pp0_stage26_flag00011011, ap_block_pp0_stage27_flag00011011, ap_block_pp0_stage28_flag00011011, ap_block_pp0_stage29_flag00011011, ap_block_pp0_stage30_flag00011011) begin case ap_CS_fsm is when ap_ST_fsm_pp0_stage0 => if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_reset_idle_pp0 = ap_const_logic_0) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_1to1))))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage1; elsif (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_pp0_stage0; end if; when ap_ST_fsm_pp0_stage1 => if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage2; else ap_NS_fsm <= ap_ST_fsm_pp0_stage1; end if; when ap_ST_fsm_pp0_stage2 => if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage3; else ap_NS_fsm <= ap_ST_fsm_pp0_stage2; end if; when ap_ST_fsm_pp0_stage3 => if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage4; else ap_NS_fsm <= ap_ST_fsm_pp0_stage3; end if; when ap_ST_fsm_pp0_stage4 => if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage5; else ap_NS_fsm <= ap_ST_fsm_pp0_stage4; end if; when ap_ST_fsm_pp0_stage5 => if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage6; else ap_NS_fsm <= ap_ST_fsm_pp0_stage5; end if; when ap_ST_fsm_pp0_stage6 => if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage7; else ap_NS_fsm <= ap_ST_fsm_pp0_stage6; end if; when ap_ST_fsm_pp0_stage7 => if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage8; else ap_NS_fsm <= ap_ST_fsm_pp0_stage7; end if; when ap_ST_fsm_pp0_stage8 => if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage9; else ap_NS_fsm <= ap_ST_fsm_pp0_stage8; end if; when ap_ST_fsm_pp0_stage9 => if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage10; else ap_NS_fsm <= ap_ST_fsm_pp0_stage9; end if; when ap_ST_fsm_pp0_stage10 => if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage11; else ap_NS_fsm <= ap_ST_fsm_pp0_stage10; end if; when ap_ST_fsm_pp0_stage11 => if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage12; else ap_NS_fsm <= ap_ST_fsm_pp0_stage11; end if; when ap_ST_fsm_pp0_stage12 => if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage13; else ap_NS_fsm <= ap_ST_fsm_pp0_stage12; end if; when ap_ST_fsm_pp0_stage13 => if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage14; else ap_NS_fsm <= ap_ST_fsm_pp0_stage13; end if; when ap_ST_fsm_pp0_stage14 => if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage15; else ap_NS_fsm <= ap_ST_fsm_pp0_stage14; end if; when ap_ST_fsm_pp0_stage15 => if ((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage16; else ap_NS_fsm <= ap_ST_fsm_pp0_stage15; end if; when ap_ST_fsm_pp0_stage16 => if ((ap_block_pp0_stage16_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage17; else ap_NS_fsm <= ap_ST_fsm_pp0_stage16; end if; when ap_ST_fsm_pp0_stage17 => if ((ap_block_pp0_stage17_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage18; else ap_NS_fsm <= ap_ST_fsm_pp0_stage17; end if; when ap_ST_fsm_pp0_stage18 => if ((ap_block_pp0_stage18_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage19; else ap_NS_fsm <= ap_ST_fsm_pp0_stage18; end if; when ap_ST_fsm_pp0_stage19 => if ((ap_block_pp0_stage19_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage20; else ap_NS_fsm <= ap_ST_fsm_pp0_stage19; end if; when ap_ST_fsm_pp0_stage20 => if ((ap_block_pp0_stage20_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage21; else ap_NS_fsm <= ap_ST_fsm_pp0_stage20; end if; when ap_ST_fsm_pp0_stage21 => if ((ap_block_pp0_stage21_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage22; else ap_NS_fsm <= ap_ST_fsm_pp0_stage21; end if; when ap_ST_fsm_pp0_stage22 => if ((ap_block_pp0_stage22_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage23; else ap_NS_fsm <= ap_ST_fsm_pp0_stage22; end if; when ap_ST_fsm_pp0_stage23 => if ((ap_block_pp0_stage23_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage24; else ap_NS_fsm <= ap_ST_fsm_pp0_stage23; end if; when ap_ST_fsm_pp0_stage24 => if ((ap_block_pp0_stage24_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage25; else ap_NS_fsm <= ap_ST_fsm_pp0_stage24; end if; when ap_ST_fsm_pp0_stage25 => if ((ap_block_pp0_stage25_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage26; else ap_NS_fsm <= ap_ST_fsm_pp0_stage25; end if; when ap_ST_fsm_pp0_stage26 => if ((ap_block_pp0_stage26_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage27; else ap_NS_fsm <= ap_ST_fsm_pp0_stage26; end if; when ap_ST_fsm_pp0_stage27 => if ((ap_block_pp0_stage27_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage28; else ap_NS_fsm <= ap_ST_fsm_pp0_stage27; end if; when ap_ST_fsm_pp0_stage28 => if ((ap_block_pp0_stage28_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage29; else ap_NS_fsm <= ap_ST_fsm_pp0_stage28; end if; when ap_ST_fsm_pp0_stage29 => if ((ap_block_pp0_stage29_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage30; else ap_NS_fsm <= ap_ST_fsm_pp0_stage29; end if; when ap_ST_fsm_pp0_stage30 => if ((ap_block_pp0_stage30_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage31; else ap_NS_fsm <= ap_ST_fsm_pp0_stage30; end if; when ap_ST_fsm_pp0_stage31 => if ((ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_pp0_stage31; end if; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end case; end process; ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0); ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(1); ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(10); ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(11); ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(12); ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(13); ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(14); ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(15); ap_CS_fsm_pp0_stage16 <= ap_CS_fsm(16); ap_CS_fsm_pp0_stage17 <= ap_CS_fsm(17); ap_CS_fsm_pp0_stage18 <= ap_CS_fsm(18); ap_CS_fsm_pp0_stage19 <= ap_CS_fsm(19); ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(2); ap_CS_fsm_pp0_stage20 <= ap_CS_fsm(20); ap_CS_fsm_pp0_stage21 <= ap_CS_fsm(21); ap_CS_fsm_pp0_stage22 <= ap_CS_fsm(22); ap_CS_fsm_pp0_stage23 <= ap_CS_fsm(23); ap_CS_fsm_pp0_stage24 <= ap_CS_fsm(24); ap_CS_fsm_pp0_stage25 <= ap_CS_fsm(25); ap_CS_fsm_pp0_stage26 <= ap_CS_fsm(26); ap_CS_fsm_pp0_stage27 <= ap_CS_fsm(27); ap_CS_fsm_pp0_stage28 <= ap_CS_fsm(28); ap_CS_fsm_pp0_stage29 <= ap_CS_fsm(29); ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(3); ap_CS_fsm_pp0_stage30 <= ap_CS_fsm(30); ap_CS_fsm_pp0_stage31 <= ap_CS_fsm(31); ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(4); ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(5); ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(6); ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(7); ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(8); ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(9); ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0) begin ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)); end process; ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0, ap_ce) begin ap_block_pp0_stage0_flag00011011 <= ((ap_ce = ap_const_logic_0) or ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))); end process; ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage10_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage11_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage11_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage12_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage13_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage14_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage15_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage15_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage15_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage16_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage16_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage16_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage16_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage17_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage17_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage18_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage18_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage19_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage19_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage1_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage20_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage20_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage20_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage20_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage21_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage21_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage22_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage22_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage23_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage23_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage24_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage24_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage25_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage25_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage26_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage26_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage27_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage27_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage28_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage28_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage29_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage29_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage2_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage30_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage30_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage31_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage31_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage3_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage4_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage5_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage6_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage7_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage8_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage8_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage9_flag00011011_assign_proc : process(ap_ce) begin ap_block_pp0_stage9_flag00011011 <= (ap_ce = ap_const_logic_0); end process; ap_block_state10_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state11_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state12_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state13_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state14_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state15_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state16_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state17_pp0_stage16_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state18_pp0_stage17_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state19_pp0_stage18_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start) begin ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start); end process; ap_block_state20_pp0_stage19_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state21_pp0_stage20_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state22_pp0_stage21_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state23_pp0_stage22_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state24_pp0_stage23_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state25_pp0_stage24_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state26_pp0_stage25_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state27_pp0_stage26_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state28_pp0_stage27_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state29_pp0_stage28_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state2_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state30_pp0_stage29_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state31_pp0_stage30_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state32_pp0_stage31_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state33_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state3_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state4_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state5_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state6_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state7_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state8_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state9_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_done_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_ce, ap_block_pp0_stage0_flag00011001) begin if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1); ap_enable_reg_pp0_iter0_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0_reg) begin if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then ap_enable_reg_pp0_iter0 <= ap_start; else ap_enable_reg_pp0_iter0 <= ap_enable_reg_pp0_iter0_reg; end if; end process; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1) begin if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then ap_idle_pp0 <= ap_const_logic_1; else ap_idle_pp0 <= ap_const_logic_0; end if; end process; ap_idle_pp0_0to0_assign_proc : process(ap_enable_reg_pp0_iter0) begin if ((ap_const_logic_0 = ap_enable_reg_pp0_iter0)) then ap_idle_pp0_0to0 <= ap_const_logic_1; else ap_idle_pp0_0to0 <= ap_const_logic_0; end if; end process; ap_idle_pp0_1to1_assign_proc : process(ap_enable_reg_pp0_iter1) begin if ((ap_const_logic_0 = ap_enable_reg_pp0_iter1)) then ap_idle_pp0_1to1 <= ap_const_logic_1; else ap_idle_pp0_1to1 <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_ce) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to0) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to0))) then ap_reset_idle_pp0 <= ap_const_logic_1; else ap_reset_idle_pp0 <= ap_const_logic_0; end if; end process; ap_return <= (tmp32_fu_2946_p2 and tmp1_fu_2916_p2); contacts_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, tmp_6_fu_1354_p1, tmp_6_2_fu_1391_p1, ap_block_pp0_stage1_flag00000000, tmp_6_4_fu_1431_p1, ap_block_pp0_stage2_flag00000000, tmp_6_6_fu_1487_p1, ap_block_pp0_stage3_flag00000000, tmp_6_8_fu_1527_p1, ap_block_pp0_stage4_flag00000000, tmp_6_s_fu_1588_p1, ap_block_pp0_stage5_flag00000000, tmp_6_11_fu_1628_p1, ap_block_pp0_stage6_flag00000000, tmp_6_13_fu_1684_p1, ap_block_pp0_stage7_flag00000000, tmp_6_15_fu_1724_p1, ap_block_pp0_stage8_flag00000000, tmp_6_17_fu_1790_p1, ap_block_pp0_stage9_flag00000000, tmp_6_19_fu_1830_p1, ap_block_pp0_stage10_flag00000000, tmp_6_21_fu_1886_p1, ap_block_pp0_stage11_flag00000000, tmp_6_23_fu_1926_p1, ap_block_pp0_stage12_flag00000000, tmp_6_25_fu_1987_p1, ap_block_pp0_stage13_flag00000000, tmp_6_27_fu_2027_p1, ap_block_pp0_stage14_flag00000000, tmp_6_29_fu_2083_p1, ap_block_pp0_stage15_flag00000000, tmp_6_31_fu_2123_p1, ap_block_pp0_stage16_flag00000000, tmp_6_33_fu_2189_p1, ap_block_pp0_stage17_flag00000000, tmp_6_35_fu_2229_p1, ap_block_pp0_stage18_flag00000000, tmp_6_37_fu_2285_p1, ap_block_pp0_stage19_flag00000000, tmp_6_39_fu_2325_p1, ap_block_pp0_stage20_flag00000000, tmp_6_41_fu_2386_p1, ap_block_pp0_stage21_flag00000000, tmp_6_43_fu_2426_p1, ap_block_pp0_stage22_flag00000000, tmp_6_45_fu_2482_p1, ap_block_pp0_stage23_flag00000000, tmp_6_47_fu_2522_p1, ap_block_pp0_stage24_flag00000000, tmp_6_49_fu_2588_p1, ap_block_pp0_stage25_flag00000000, tmp_6_51_fu_2628_p1, ap_block_pp0_stage26_flag00000000, tmp_6_53_fu_2684_p1, ap_block_pp0_stage27_flag00000000, tmp_6_55_fu_2724_p1, ap_block_pp0_stage28_flag00000000, tmp_6_57_fu_2785_p1, ap_block_pp0_stage29_flag00000000, tmp_6_59_fu_2825_p1, ap_block_pp0_stage30_flag00000000, tmp_6_61_fu_2881_p1, ap_block_pp0_stage31_flag00000000) begin if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_61_fu_2881_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_59_fu_2825_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_57_fu_2785_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_55_fu_2724_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_53_fu_2684_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_51_fu_2628_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_49_fu_2588_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_47_fu_2522_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_45_fu_2482_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_43_fu_2426_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_41_fu_2386_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_39_fu_2325_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_37_fu_2285_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_35_fu_2229_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_33_fu_2189_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_31_fu_2123_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_29_fu_2083_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_27_fu_2027_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_25_fu_1987_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_23_fu_1926_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_21_fu_1886_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_19_fu_1830_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_17_fu_1790_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_15_fu_1724_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_13_fu_1684_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_11_fu_1628_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_s_fu_1588_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_8_fu_1527_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_6_fu_1487_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_4_fu_1431_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_2_fu_1391_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then contacts_address0 <= tmp_6_fu_1354_p1(13 - 1 downto 0); else contacts_address0 <= "XXXXXXXXXXXXX"; end if; else contacts_address0 <= "XXXXXXXXXXXXX"; end if; end process; contacts_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, tmp_6_1_fu_1370_p1, ap_block_pp0_stage1_flag00000000, tmp_6_3_fu_1411_p1, ap_block_pp0_stage2_flag00000000, tmp_6_5_fu_1451_p1, ap_block_pp0_stage3_flag00000000, tmp_6_7_fu_1507_p1, ap_block_pp0_stage4_flag00000000, tmp_6_9_fu_1547_p1, ap_block_pp0_stage5_flag00000000, tmp_6_10_fu_1608_p1, ap_block_pp0_stage6_flag00000000, tmp_6_12_fu_1648_p1, ap_block_pp0_stage7_flag00000000, tmp_6_14_fu_1704_p1, ap_block_pp0_stage8_flag00000000, tmp_6_16_fu_1744_p1, ap_block_pp0_stage9_flag00000000, tmp_6_18_fu_1810_p1, ap_block_pp0_stage10_flag00000000, tmp_6_20_fu_1850_p1, ap_block_pp0_stage11_flag00000000, tmp_6_22_fu_1906_p1, ap_block_pp0_stage12_flag00000000, tmp_6_24_fu_1946_p1, ap_block_pp0_stage13_flag00000000, tmp_6_26_fu_2007_p1, ap_block_pp0_stage14_flag00000000, tmp_6_28_fu_2047_p1, ap_block_pp0_stage15_flag00000000, tmp_6_30_fu_2103_p1, ap_block_pp0_stage16_flag00000000, tmp_6_32_fu_2143_p1, ap_block_pp0_stage17_flag00000000, tmp_6_34_fu_2209_p1, ap_block_pp0_stage18_flag00000000, tmp_6_36_fu_2249_p1, ap_block_pp0_stage19_flag00000000, tmp_6_38_fu_2305_p1, ap_block_pp0_stage20_flag00000000, tmp_6_40_fu_2345_p1, ap_block_pp0_stage21_flag00000000, tmp_6_42_fu_2406_p1, ap_block_pp0_stage22_flag00000000, tmp_6_44_fu_2446_p1, ap_block_pp0_stage23_flag00000000, tmp_6_46_fu_2502_p1, ap_block_pp0_stage24_flag00000000, tmp_6_48_fu_2542_p1, ap_block_pp0_stage25_flag00000000, tmp_6_50_fu_2608_p1, ap_block_pp0_stage26_flag00000000, tmp_6_52_fu_2648_p1, ap_block_pp0_stage27_flag00000000, tmp_6_54_fu_2704_p1, ap_block_pp0_stage28_flag00000000, tmp_6_56_fu_2744_p1, ap_block_pp0_stage29_flag00000000, tmp_6_58_fu_2805_p1, ap_block_pp0_stage30_flag00000000, tmp_6_60_fu_2845_p1, ap_block_pp0_stage31_flag00000000, tmp_6_62_fu_2901_p1) begin if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_62_fu_2901_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_60_fu_2845_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_58_fu_2805_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_56_fu_2744_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_54_fu_2704_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_52_fu_2648_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_50_fu_2608_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_48_fu_2542_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_46_fu_2502_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_44_fu_2446_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_42_fu_2406_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_40_fu_2345_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_38_fu_2305_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_36_fu_2249_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_34_fu_2209_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_32_fu_2143_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_30_fu_2103_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_28_fu_2047_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_26_fu_2007_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_24_fu_1946_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_22_fu_1906_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_20_fu_1850_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_18_fu_1810_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_16_fu_1744_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_14_fu_1704_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_12_fu_1648_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_10_fu_1608_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_9_fu_1547_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_7_fu_1507_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_5_fu_1451_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_3_fu_1411_p1(13 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then contacts_address1 <= tmp_6_1_fu_1370_p1(13 - 1 downto 0); else contacts_address1 <= "XXXXXXXXXXXXX"; end if; else contacts_address1 <= "XXXXXXXXXXXXX"; end if; end process; contacts_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_ce, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)))) then contacts_ce0 <= ap_const_logic_1; else contacts_ce0 <= ap_const_logic_0; end if; end process; contacts_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_ce, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)))) then contacts_ce1 <= ap_const_logic_1; else contacts_ce1 <= ap_const_logic_0; end if; end process; database_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, tmp_8_fu_1359_p1, ap_block_pp0_stage1_flag00000000, tmp_8_2_fu_1401_p1, ap_block_pp0_stage2_flag00000000, tmp_8_4_fu_1441_p1, ap_block_pp0_stage3_flag00000000, tmp_8_6_fu_1497_p1, ap_block_pp0_stage4_flag00000000, tmp_8_8_fu_1537_p1, ap_block_pp0_stage5_flag00000000, tmp_8_s_fu_1598_p1, ap_block_pp0_stage6_flag00000000, tmp_8_11_fu_1638_p1, ap_block_pp0_stage7_flag00000000, tmp_8_13_fu_1694_p1, ap_block_pp0_stage8_flag00000000, tmp_8_15_fu_1734_p1, ap_block_pp0_stage9_flag00000000, tmp_8_17_fu_1800_p1, ap_block_pp0_stage10_flag00000000, tmp_8_19_fu_1840_p1, ap_block_pp0_stage11_flag00000000, tmp_8_21_fu_1896_p1, ap_block_pp0_stage12_flag00000000, tmp_8_23_fu_1936_p1, ap_block_pp0_stage13_flag00000000, tmp_8_25_fu_1997_p1, ap_block_pp0_stage14_flag00000000, tmp_8_27_fu_2037_p1, ap_block_pp0_stage15_flag00000000, tmp_8_29_fu_2093_p1, ap_block_pp0_stage16_flag00000000, tmp_8_31_fu_2133_p1, ap_block_pp0_stage17_flag00000000, tmp_8_33_fu_2199_p1, ap_block_pp0_stage18_flag00000000, tmp_8_35_fu_2239_p1, ap_block_pp0_stage19_flag00000000, tmp_8_37_fu_2295_p1, ap_block_pp0_stage20_flag00000000, tmp_8_39_fu_2335_p1, ap_block_pp0_stage21_flag00000000, tmp_8_41_fu_2396_p1, ap_block_pp0_stage22_flag00000000, tmp_8_43_fu_2436_p1, ap_block_pp0_stage23_flag00000000, tmp_8_45_fu_2492_p1, ap_block_pp0_stage24_flag00000000, tmp_8_47_fu_2532_p1, ap_block_pp0_stage25_flag00000000, tmp_8_49_fu_2598_p1, ap_block_pp0_stage26_flag00000000, tmp_8_51_fu_2638_p1, ap_block_pp0_stage27_flag00000000, tmp_8_53_fu_2694_p1, ap_block_pp0_stage28_flag00000000, tmp_8_55_fu_2734_p1, ap_block_pp0_stage29_flag00000000, tmp_8_57_fu_2795_p1, ap_block_pp0_stage30_flag00000000, tmp_8_59_fu_2835_p1, ap_block_pp0_stage31_flag00000000, tmp_8_61_fu_2891_p1) begin if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_61_fu_2891_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_59_fu_2835_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_57_fu_2795_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_55_fu_2734_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_53_fu_2694_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_51_fu_2638_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_49_fu_2598_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_47_fu_2532_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_45_fu_2492_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_43_fu_2436_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_41_fu_2396_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_39_fu_2335_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_37_fu_2295_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_35_fu_2239_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_33_fu_2199_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_31_fu_2133_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_29_fu_2093_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_27_fu_2037_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_25_fu_1997_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_23_fu_1936_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_21_fu_1896_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_19_fu_1840_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_17_fu_1800_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_15_fu_1734_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_13_fu_1694_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_11_fu_1638_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_s_fu_1598_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_8_fu_1537_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_6_fu_1497_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_4_fu_1441_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_2_fu_1401_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then database_address0 <= tmp_8_fu_1359_p1(19 - 1 downto 0); else database_address0 <= "XXXXXXXXXXXXXXXXXXX"; end if; else database_address0 <= "XXXXXXXXXXXXXXXXXXX"; end if; end process; database_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, tmp_8_1_fu_1381_p1, ap_block_pp0_stage1_flag00000000, tmp_8_3_fu_1421_p1, ap_block_pp0_stage2_flag00000000, tmp_8_5_fu_1461_p1, ap_block_pp0_stage3_flag00000000, tmp_8_7_fu_1517_p1, ap_block_pp0_stage4_flag00000000, tmp_8_9_fu_1557_p1, ap_block_pp0_stage5_flag00000000, tmp_8_10_fu_1618_p1, ap_block_pp0_stage6_flag00000000, tmp_8_12_fu_1658_p1, ap_block_pp0_stage7_flag00000000, tmp_8_14_fu_1714_p1, ap_block_pp0_stage8_flag00000000, tmp_8_16_fu_1754_p1, ap_block_pp0_stage9_flag00000000, tmp_8_18_fu_1820_p1, ap_block_pp0_stage10_flag00000000, tmp_8_20_fu_1860_p1, ap_block_pp0_stage11_flag00000000, tmp_8_22_fu_1916_p1, ap_block_pp0_stage12_flag00000000, tmp_8_24_fu_1956_p1, ap_block_pp0_stage13_flag00000000, tmp_8_26_fu_2017_p1, ap_block_pp0_stage14_flag00000000, tmp_8_28_fu_2057_p1, ap_block_pp0_stage15_flag00000000, tmp_8_30_fu_2113_p1, ap_block_pp0_stage16_flag00000000, tmp_8_32_fu_2153_p1, ap_block_pp0_stage17_flag00000000, tmp_8_34_fu_2219_p1, ap_block_pp0_stage18_flag00000000, tmp_8_36_fu_2259_p1, ap_block_pp0_stage19_flag00000000, tmp_8_38_fu_2315_p1, ap_block_pp0_stage20_flag00000000, tmp_8_40_fu_2355_p1, ap_block_pp0_stage21_flag00000000, tmp_8_42_fu_2416_p1, ap_block_pp0_stage22_flag00000000, tmp_8_44_fu_2456_p1, ap_block_pp0_stage23_flag00000000, tmp_8_46_fu_2512_p1, ap_block_pp0_stage24_flag00000000, tmp_8_48_fu_2552_p1, ap_block_pp0_stage25_flag00000000, tmp_8_50_fu_2618_p1, ap_block_pp0_stage26_flag00000000, tmp_8_52_fu_2658_p1, ap_block_pp0_stage27_flag00000000, tmp_8_54_fu_2714_p1, ap_block_pp0_stage28_flag00000000, tmp_8_56_fu_2754_p1, ap_block_pp0_stage29_flag00000000, tmp_8_58_fu_2815_p1, ap_block_pp0_stage30_flag00000000, tmp_8_60_fu_2855_p1, ap_block_pp0_stage31_flag00000000, tmp_8_62_fu_2911_p1) begin if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_62_fu_2911_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_60_fu_2855_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_58_fu_2815_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_56_fu_2754_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_54_fu_2714_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_52_fu_2658_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_50_fu_2618_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_48_fu_2552_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_46_fu_2512_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_44_fu_2456_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_42_fu_2416_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_40_fu_2355_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_38_fu_2315_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_36_fu_2259_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_34_fu_2219_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_32_fu_2153_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_30_fu_2113_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_28_fu_2057_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_26_fu_2017_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_24_fu_1956_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_22_fu_1916_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_20_fu_1860_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_18_fu_1820_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_16_fu_1754_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_14_fu_1714_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_12_fu_1658_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_10_fu_1618_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_9_fu_1557_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_7_fu_1517_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_5_fu_1461_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_3_fu_1421_p1(19 - 1 downto 0); elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then database_address1 <= tmp_8_1_fu_1381_p1(19 - 1 downto 0); else database_address1 <= "XXXXXXXXXXXXXXXXXXX"; end if; else database_address1 <= "XXXXXXXXXXXXXXXXXXX"; end if; end process; database_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_ce, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)))) then database_ce0 <= ap_const_logic_1; else database_ce0 <= ap_const_logic_0; end if; end process; database_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_ce, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)))) then database_ce1 <= ap_const_logic_1; else database_ce1 <= ap_const_logic_0; end if; end process; grp_fu_1322_p2 <= "1" when (contacts_q0 = database_q0) else "0"; grp_fu_1328_p2 <= "1" when (contacts_q1 = database_q1) else "0"; tmp10_fu_1775_p2 <= (tmp14_fu_1769_p2 and tmp11_reg_3269); tmp11_fu_1673_p2 <= (tmp13_fu_1667_p2 and tmp12_fu_1663_p2); tmp12_fu_1663_p2 <= (tmp_9_8_reg_3219 and tmp_9_9_reg_3224); tmp13_fu_1667_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp14_fu_1769_p2 <= (tmp16_fu_1763_p2 and tmp15_fu_1759_p2); tmp15_fu_1759_p2 <= (tmp_9_11_reg_3274 and tmp_9_12_reg_3279); tmp16_fu_1763_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp17_fu_2179_p2 <= (tmp25_fu_2174_p2 and tmp18_reg_3434); tmp18_fu_1977_p2 <= (tmp22_fu_1971_p2 and tmp19_reg_3379); tmp19_fu_1875_p2 <= (tmp21_fu_1869_p2 and tmp20_fu_1865_p2); tmp1_fu_2916_p2 <= (tmp17_reg_3544 and tmp2_reg_3324); tmp20_fu_1865_p2 <= (tmp_9_15_reg_3329 and tmp_9_16_reg_3334); tmp21_fu_1869_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp22_fu_1971_p2 <= (tmp24_fu_1965_p2 and tmp23_fu_1961_p2); tmp23_fu_1961_p2 <= (tmp_9_19_reg_3384 and tmp_9_20_reg_3389); tmp24_fu_1965_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp25_fu_2174_p2 <= (tmp29_fu_2168_p2 and tmp26_reg_3489); tmp26_fu_2072_p2 <= (tmp28_fu_2066_p2 and tmp27_fu_2062_p2); tmp27_fu_2062_p2 <= (tmp_9_23_reg_3439 and tmp_9_24_reg_3444); tmp28_fu_2066_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp29_fu_2168_p2 <= (tmp31_fu_2162_p2 and tmp30_fu_2158_p2); tmp2_fu_1780_p2 <= (tmp10_fu_1775_p2 and tmp3_reg_3214); tmp30_fu_2158_p2 <= (tmp_9_27_reg_3494 and tmp_9_28_reg_3499); tmp31_fu_2162_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp32_fu_2946_p2 <= (tmp48_fu_2941_p2 and tmp33_reg_3764); tmp33_fu_2578_p2 <= (tmp41_fu_2573_p2 and tmp34_reg_3654); tmp34_fu_2376_p2 <= (tmp38_fu_2370_p2 and tmp35_reg_3599); tmp35_fu_2274_p2 <= (tmp37_fu_2268_p2 and tmp36_fu_2264_p2); tmp36_fu_2264_p2 <= (tmp_9_31_reg_3549 and tmp_9_32_reg_3554); tmp37_fu_2268_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp38_fu_2370_p2 <= (tmp40_fu_2364_p2 and tmp39_fu_2360_p2); tmp39_fu_2360_p2 <= (tmp_9_35_reg_3604 and tmp_9_36_reg_3609); tmp3_fu_1578_p2 <= (tmp7_fu_1572_p2 and tmp4_reg_3159); tmp40_fu_2364_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp41_fu_2573_p2 <= (tmp45_fu_2567_p2 and tmp42_reg_3709); tmp42_fu_2471_p2 <= (tmp44_fu_2465_p2 and tmp43_fu_2461_p2); tmp43_fu_2461_p2 <= (tmp_9_39_reg_3659 and tmp_9_40_reg_3664); tmp44_fu_2465_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp45_fu_2567_p2 <= (tmp47_fu_2561_p2 and tmp46_fu_2557_p2); tmp46_fu_2557_p2 <= (tmp_9_43_reg_3714 and tmp_9_44_reg_3719); tmp47_fu_2561_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp48_fu_2941_p2 <= (tmp56_fu_2936_p2 and tmp49_reg_3874); tmp49_fu_2775_p2 <= (tmp53_fu_2769_p2 and tmp50_reg_3819); tmp4_fu_1476_p2 <= (tmp6_fu_1470_p2 and tmp5_fu_1466_p2); tmp50_fu_2673_p2 <= (tmp52_fu_2667_p2 and tmp51_fu_2663_p2); tmp51_fu_2663_p2 <= (tmp_9_47_reg_3769 and tmp_9_48_reg_3774); tmp52_fu_2667_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp53_fu_2769_p2 <= (tmp55_fu_2763_p2 and tmp54_fu_2759_p2); tmp54_fu_2759_p2 <= (tmp_9_51_reg_3824 and tmp_9_52_reg_3829); tmp55_fu_2763_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp56_fu_2936_p2 <= (tmp60_fu_2930_p2 and tmp57_reg_3929); tmp57_fu_2870_p2 <= (tmp59_fu_2864_p2 and tmp58_fu_2860_p2); tmp58_fu_2860_p2 <= (tmp_9_55_reg_3879 and tmp_9_56_reg_3884); tmp59_fu_2864_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp5_fu_1466_p2 <= (tmp_9_reg_3109 and tmp_9_1_reg_3114); tmp60_fu_2930_p2 <= (tmp62_fu_2924_p2 and tmp61_fu_2920_p2); tmp61_fu_2920_p2 <= (tmp_9_59_reg_3934 and tmp_9_60_reg_3939); tmp62_fu_2924_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp6_fu_1470_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp7_fu_1572_p2 <= (tmp9_fu_1566_p2 and tmp8_fu_1562_p2); tmp8_fu_1562_p2 <= (tmp_9_4_reg_3164 and tmp_9_5_reg_3169); tmp9_fu_1566_p2 <= (grp_fu_1322_p2 and grp_fu_1328_p2); tmp_129_fu_1334_p1 <= contacts_index(7 - 1 downto 0); tmp_5_10_fu_1603_p2 <= (tmp_reg_2957 or ap_const_lv13_B); tmp_5_11_fu_1623_p2 <= (tmp_reg_2957 or ap_const_lv13_C); tmp_5_12_fu_1643_p2 <= (tmp_reg_2957 or ap_const_lv13_D); tmp_5_13_fu_1679_p2 <= (tmp_reg_2957 or ap_const_lv13_E); tmp_5_14_fu_1699_p2 <= (tmp_reg_2957 or ap_const_lv13_F); tmp_5_15_fu_1719_p2 <= (tmp_reg_2957 or ap_const_lv13_10); tmp_5_16_fu_1739_p2 <= (tmp_reg_2957 or ap_const_lv13_11); tmp_5_17_fu_1785_p2 <= (tmp_reg_2957 or ap_const_lv13_12); tmp_5_18_fu_1805_p2 <= (tmp_reg_2957 or ap_const_lv13_13); tmp_5_19_fu_1825_p2 <= (tmp_reg_2957 or ap_const_lv13_14); tmp_5_1_fu_1386_p2 <= (tmp_reg_2957 or ap_const_lv13_2); tmp_5_20_fu_1845_p2 <= (tmp_reg_2957 or ap_const_lv13_15); tmp_5_21_fu_1881_p2 <= (tmp_reg_2957 or ap_const_lv13_16); tmp_5_22_fu_1901_p2 <= (tmp_reg_2957 or ap_const_lv13_17); tmp_5_23_fu_1921_p2 <= (tmp_reg_2957 or ap_const_lv13_18); tmp_5_24_fu_1941_p2 <= (tmp_reg_2957 or ap_const_lv13_19); tmp_5_25_fu_1982_p2 <= (tmp_reg_2957 or ap_const_lv13_1A); tmp_5_26_fu_2002_p2 <= (tmp_reg_2957 or ap_const_lv13_1B); tmp_5_27_fu_2022_p2 <= (tmp_reg_2957 or ap_const_lv13_1C); tmp_5_28_fu_2042_p2 <= (tmp_reg_2957 or ap_const_lv13_1D); tmp_5_29_fu_2078_p2 <= (tmp_reg_2957 or ap_const_lv13_1E); tmp_5_2_fu_1406_p2 <= (tmp_reg_2957 or ap_const_lv13_3); tmp_5_30_fu_2098_p2 <= (tmp_reg_2957 or ap_const_lv13_1F); tmp_5_31_fu_2118_p2 <= (tmp_reg_2957 or ap_const_lv13_20); tmp_5_32_fu_2138_p2 <= (tmp_reg_2957 or ap_const_lv13_21); tmp_5_33_fu_2184_p2 <= (tmp_reg_2957 or ap_const_lv13_22); tmp_5_34_fu_2204_p2 <= (tmp_reg_2957 or ap_const_lv13_23); tmp_5_35_fu_2224_p2 <= (tmp_reg_2957 or ap_const_lv13_24); tmp_5_36_fu_2244_p2 <= (tmp_reg_2957 or ap_const_lv13_25); tmp_5_37_fu_2280_p2 <= (tmp_reg_2957 or ap_const_lv13_26); tmp_5_38_fu_2300_p2 <= (tmp_reg_2957 or ap_const_lv13_27); tmp_5_39_fu_2320_p2 <= (tmp_reg_2957 or ap_const_lv13_28); tmp_5_3_fu_1426_p2 <= (tmp_reg_2957 or ap_const_lv13_4); tmp_5_40_fu_2340_p2 <= (tmp_reg_2957 or ap_const_lv13_29); tmp_5_41_fu_2381_p2 <= (tmp_reg_2957 or ap_const_lv13_2A); tmp_5_42_fu_2401_p2 <= (tmp_reg_2957 or ap_const_lv13_2B); tmp_5_43_fu_2421_p2 <= (tmp_reg_2957 or ap_const_lv13_2C); tmp_5_44_fu_2441_p2 <= (tmp_reg_2957 or ap_const_lv13_2D); tmp_5_45_fu_2477_p2 <= (tmp_reg_2957 or ap_const_lv13_2E); tmp_5_46_fu_2497_p2 <= (tmp_reg_2957 or ap_const_lv13_2F); tmp_5_47_fu_2517_p2 <= (tmp_reg_2957 or ap_const_lv13_30); tmp_5_48_fu_2537_p2 <= (tmp_reg_2957 or ap_const_lv13_31); tmp_5_49_fu_2583_p2 <= (tmp_reg_2957 or ap_const_lv13_32); tmp_5_4_fu_1446_p2 <= (tmp_reg_2957 or ap_const_lv13_5); tmp_5_50_fu_2603_p2 <= (tmp_reg_2957 or ap_const_lv13_33); tmp_5_51_fu_2623_p2 <= (tmp_reg_2957 or ap_const_lv13_34); tmp_5_52_fu_2643_p2 <= (tmp_reg_2957 or ap_const_lv13_35); tmp_5_53_fu_2679_p2 <= (tmp_reg_2957 or ap_const_lv13_36); tmp_5_54_fu_2699_p2 <= (tmp_reg_2957 or ap_const_lv13_37); tmp_5_55_fu_2719_p2 <= (tmp_reg_2957 or ap_const_lv13_38); tmp_5_56_fu_2739_p2 <= (tmp_reg_2957 or ap_const_lv13_39); tmp_5_57_fu_2780_p2 <= (tmp_reg_2957 or ap_const_lv13_3A); tmp_5_58_fu_2800_p2 <= (tmp_reg_2957 or ap_const_lv13_3B); tmp_5_59_fu_2820_p2 <= (tmp_reg_2957 or ap_const_lv13_3C); tmp_5_5_fu_1482_p2 <= (tmp_reg_2957 or ap_const_lv13_6); tmp_5_60_fu_2840_p2 <= (tmp_reg_2957 or ap_const_lv13_3D); tmp_5_61_fu_2876_p2 <= (tmp_reg_2957 or ap_const_lv13_3E); tmp_5_62_fu_2896_p2 <= (tmp_reg_2957 or ap_const_lv13_3F); tmp_5_6_fu_1502_p2 <= (tmp_reg_2957 or ap_const_lv13_7); tmp_5_7_fu_1522_p2 <= (tmp_reg_2957 or ap_const_lv13_8); tmp_5_8_fu_1542_p2 <= (tmp_reg_2957 or ap_const_lv13_9); tmp_5_9_fu_1583_p2 <= (tmp_reg_2957 or ap_const_lv13_A); tmp_5_s_fu_1364_p2 <= (tmp_fu_1338_p3 or ap_const_lv13_1); tmp_6_10_fu_1608_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_10_fu_1603_p2),64)); tmp_6_11_fu_1628_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_11_fu_1623_p2),64)); tmp_6_12_fu_1648_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_12_fu_1643_p2),64)); tmp_6_13_fu_1684_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_13_fu_1679_p2),64)); tmp_6_14_fu_1704_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_14_fu_1699_p2),64)); tmp_6_15_fu_1724_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_15_fu_1719_p2),64)); tmp_6_16_fu_1744_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_16_fu_1739_p2),64)); tmp_6_17_fu_1790_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_17_fu_1785_p2),64)); tmp_6_18_fu_1810_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_18_fu_1805_p2),64)); tmp_6_19_fu_1830_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_19_fu_1825_p2),64)); tmp_6_1_fu_1370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_s_fu_1364_p2),64)); tmp_6_20_fu_1850_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_20_fu_1845_p2),64)); tmp_6_21_fu_1886_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_21_fu_1881_p2),64)); tmp_6_22_fu_1906_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_22_fu_1901_p2),64)); tmp_6_23_fu_1926_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_23_fu_1921_p2),64)); tmp_6_24_fu_1946_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_24_fu_1941_p2),64)); tmp_6_25_fu_1987_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_25_fu_1982_p2),64)); tmp_6_26_fu_2007_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_26_fu_2002_p2),64)); tmp_6_27_fu_2027_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_27_fu_2022_p2),64)); tmp_6_28_fu_2047_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_28_fu_2042_p2),64)); tmp_6_29_fu_2083_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_29_fu_2078_p2),64)); tmp_6_2_fu_1391_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_1_fu_1386_p2),64)); tmp_6_30_fu_2103_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_30_fu_2098_p2),64)); tmp_6_31_fu_2123_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_31_fu_2118_p2),64)); tmp_6_32_fu_2143_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_32_fu_2138_p2),64)); tmp_6_33_fu_2189_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_33_fu_2184_p2),64)); tmp_6_34_fu_2209_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_34_fu_2204_p2),64)); tmp_6_35_fu_2229_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_35_fu_2224_p2),64)); tmp_6_36_fu_2249_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_36_fu_2244_p2),64)); tmp_6_37_fu_2285_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_37_fu_2280_p2),64)); tmp_6_38_fu_2305_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_38_fu_2300_p2),64)); tmp_6_39_fu_2325_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_39_fu_2320_p2),64)); tmp_6_3_fu_1411_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_2_fu_1406_p2),64)); tmp_6_40_fu_2345_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_40_fu_2340_p2),64)); tmp_6_41_fu_2386_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_41_fu_2381_p2),64)); tmp_6_42_fu_2406_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_42_fu_2401_p2),64)); tmp_6_43_fu_2426_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_43_fu_2421_p2),64)); tmp_6_44_fu_2446_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_44_fu_2441_p2),64)); tmp_6_45_fu_2482_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_45_fu_2477_p2),64)); tmp_6_46_fu_2502_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_46_fu_2497_p2),64)); tmp_6_47_fu_2522_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_47_fu_2517_p2),64)); tmp_6_48_fu_2542_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_48_fu_2537_p2),64)); tmp_6_49_fu_2588_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_49_fu_2583_p2),64)); tmp_6_4_fu_1431_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_3_fu_1426_p2),64)); tmp_6_50_fu_2608_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_50_fu_2603_p2),64)); tmp_6_51_fu_2628_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_51_fu_2623_p2),64)); tmp_6_52_fu_2648_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_52_fu_2643_p2),64)); tmp_6_53_fu_2684_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_53_fu_2679_p2),64)); tmp_6_54_fu_2704_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_54_fu_2699_p2),64)); tmp_6_55_fu_2724_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_55_fu_2719_p2),64)); tmp_6_56_fu_2744_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_56_fu_2739_p2),64)); tmp_6_57_fu_2785_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_57_fu_2780_p2),64)); tmp_6_58_fu_2805_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_58_fu_2800_p2),64)); tmp_6_59_fu_2825_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_59_fu_2820_p2),64)); tmp_6_5_fu_1451_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_4_fu_1446_p2),64)); tmp_6_60_fu_2845_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_60_fu_2840_p2),64)); tmp_6_61_fu_2881_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_61_fu_2876_p2),64)); tmp_6_62_fu_2901_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_62_fu_2896_p2),64)); tmp_6_6_fu_1487_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_5_fu_1482_p2),64)); tmp_6_7_fu_1507_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_6_fu_1502_p2),64)); tmp_6_8_fu_1527_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_7_fu_1522_p2),64)); tmp_6_9_fu_1547_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_8_fu_1542_p2),64)); tmp_6_fu_1354_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_1338_p3),64)); tmp_6_s_fu_1588_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_9_fu_1583_p2),64)); tmp_7_10_fu_1613_p2 <= (tmp_s_reg_3023 or ap_const_lv19_B); tmp_7_11_fu_1633_p2 <= (tmp_s_reg_3023 or ap_const_lv19_C); tmp_7_12_fu_1653_p2 <= (tmp_s_reg_3023 or ap_const_lv19_D); tmp_7_13_fu_1689_p2 <= (tmp_s_reg_3023 or ap_const_lv19_E); tmp_7_14_fu_1709_p2 <= (tmp_s_reg_3023 or ap_const_lv19_F); tmp_7_15_fu_1729_p2 <= (tmp_s_reg_3023 or ap_const_lv19_10); tmp_7_16_fu_1749_p2 <= (tmp_s_reg_3023 or ap_const_lv19_11); tmp_7_17_fu_1795_p2 <= (tmp_s_reg_3023 or ap_const_lv19_12); tmp_7_18_fu_1815_p2 <= (tmp_s_reg_3023 or ap_const_lv19_13); tmp_7_19_fu_1835_p2 <= (tmp_s_reg_3023 or ap_const_lv19_14); tmp_7_1_fu_1396_p2 <= (tmp_s_reg_3023 or ap_const_lv19_2); tmp_7_20_fu_1855_p2 <= (tmp_s_reg_3023 or ap_const_lv19_15); tmp_7_21_fu_1891_p2 <= (tmp_s_reg_3023 or ap_const_lv19_16); tmp_7_22_fu_1911_p2 <= (tmp_s_reg_3023 or ap_const_lv19_17); tmp_7_23_fu_1931_p2 <= (tmp_s_reg_3023 or ap_const_lv19_18); tmp_7_24_fu_1951_p2 <= (tmp_s_reg_3023 or ap_const_lv19_19); tmp_7_25_fu_1992_p2 <= (tmp_s_reg_3023 or ap_const_lv19_1A); tmp_7_26_fu_2012_p2 <= (tmp_s_reg_3023 or ap_const_lv19_1B); tmp_7_27_fu_2032_p2 <= (tmp_s_reg_3023 or ap_const_lv19_1C); tmp_7_28_fu_2052_p2 <= (tmp_s_reg_3023 or ap_const_lv19_1D); tmp_7_29_fu_2088_p2 <= (tmp_s_reg_3023 or ap_const_lv19_1E); tmp_7_2_fu_1416_p2 <= (tmp_s_reg_3023 or ap_const_lv19_3); tmp_7_30_fu_2108_p2 <= (tmp_s_reg_3023 or ap_const_lv19_1F); tmp_7_31_fu_2128_p2 <= (tmp_s_reg_3023 or ap_const_lv19_20); tmp_7_32_fu_2148_p2 <= (tmp_s_reg_3023 or ap_const_lv19_21); tmp_7_33_fu_2194_p2 <= (tmp_s_reg_3023 or ap_const_lv19_22); tmp_7_34_fu_2214_p2 <= (tmp_s_reg_3023 or ap_const_lv19_23); tmp_7_35_fu_2234_p2 <= (tmp_s_reg_3023 or ap_const_lv19_24); tmp_7_36_fu_2254_p2 <= (tmp_s_reg_3023 or ap_const_lv19_25); tmp_7_37_fu_2290_p2 <= (tmp_s_reg_3023 or ap_const_lv19_26); tmp_7_38_fu_2310_p2 <= (tmp_s_reg_3023 or ap_const_lv19_27); tmp_7_39_fu_2330_p2 <= (tmp_s_reg_3023 or ap_const_lv19_28); tmp_7_3_fu_1436_p2 <= (tmp_s_reg_3023 or ap_const_lv19_4); tmp_7_40_fu_2350_p2 <= (tmp_s_reg_3023 or ap_const_lv19_29); tmp_7_41_fu_2391_p2 <= (tmp_s_reg_3023 or ap_const_lv19_2A); tmp_7_42_fu_2411_p2 <= (tmp_s_reg_3023 or ap_const_lv19_2B); tmp_7_43_fu_2431_p2 <= (tmp_s_reg_3023 or ap_const_lv19_2C); tmp_7_44_fu_2451_p2 <= (tmp_s_reg_3023 or ap_const_lv19_2D); tmp_7_45_fu_2487_p2 <= (tmp_s_reg_3023 or ap_const_lv19_2E); tmp_7_46_fu_2507_p2 <= (tmp_s_reg_3023 or ap_const_lv19_2F); tmp_7_47_fu_2527_p2 <= (tmp_s_reg_3023 or ap_const_lv19_30); tmp_7_48_fu_2547_p2 <= (tmp_s_reg_3023 or ap_const_lv19_31); tmp_7_49_fu_2593_p2 <= (tmp_s_reg_3023 or ap_const_lv19_32); tmp_7_4_fu_1456_p2 <= (tmp_s_reg_3023 or ap_const_lv19_5); tmp_7_50_fu_2613_p2 <= (tmp_s_reg_3023 or ap_const_lv19_33); tmp_7_51_fu_2633_p2 <= (tmp_s_reg_3023 or ap_const_lv19_34); tmp_7_52_fu_2653_p2 <= (tmp_s_reg_3023 or ap_const_lv19_35); tmp_7_53_fu_2689_p2 <= (tmp_s_reg_3023 or ap_const_lv19_36); tmp_7_54_fu_2709_p2 <= (tmp_s_reg_3023 or ap_const_lv19_37); tmp_7_55_fu_2729_p2 <= (tmp_s_reg_3023 or ap_const_lv19_38); tmp_7_56_fu_2749_p2 <= (tmp_s_reg_3023 or ap_const_lv19_39); tmp_7_57_fu_2790_p2 <= (tmp_s_reg_3023 or ap_const_lv19_3A); tmp_7_58_fu_2810_p2 <= (tmp_s_reg_3023 or ap_const_lv19_3B); tmp_7_59_fu_2830_p2 <= (tmp_s_reg_3023 or ap_const_lv19_3C); tmp_7_5_fu_1492_p2 <= (tmp_s_reg_3023 or ap_const_lv19_6); tmp_7_60_fu_2850_p2 <= (tmp_s_reg_3023 or ap_const_lv19_3D); tmp_7_61_fu_2886_p2 <= (tmp_s_reg_3023 or ap_const_lv19_3E); tmp_7_62_fu_2906_p2 <= (tmp_s_reg_3023 or ap_const_lv19_3F); tmp_7_6_fu_1512_p2 <= (tmp_s_reg_3023 or ap_const_lv19_7); tmp_7_7_fu_1532_p2 <= (tmp_s_reg_3023 or ap_const_lv19_8); tmp_7_8_fu_1552_p2 <= (tmp_s_reg_3023 or ap_const_lv19_9); tmp_7_9_fu_1593_p2 <= (tmp_s_reg_3023 or ap_const_lv19_A); tmp_7_s_fu_1375_p2 <= (tmp_s_fu_1346_p3 or ap_const_lv19_1); tmp_8_10_fu_1618_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_10_fu_1613_p2),64)); tmp_8_11_fu_1638_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_11_fu_1633_p2),64)); tmp_8_12_fu_1658_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_12_fu_1653_p2),64)); tmp_8_13_fu_1694_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_13_fu_1689_p2),64)); tmp_8_14_fu_1714_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_14_fu_1709_p2),64)); tmp_8_15_fu_1734_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_15_fu_1729_p2),64)); tmp_8_16_fu_1754_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_16_fu_1749_p2),64)); tmp_8_17_fu_1800_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_17_fu_1795_p2),64)); tmp_8_18_fu_1820_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_18_fu_1815_p2),64)); tmp_8_19_fu_1840_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_19_fu_1835_p2),64)); tmp_8_1_fu_1381_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_s_fu_1375_p2),64)); tmp_8_20_fu_1860_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_20_fu_1855_p2),64)); tmp_8_21_fu_1896_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_21_fu_1891_p2),64)); tmp_8_22_fu_1916_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_22_fu_1911_p2),64)); tmp_8_23_fu_1936_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_23_fu_1931_p2),64)); tmp_8_24_fu_1956_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_24_fu_1951_p2),64)); tmp_8_25_fu_1997_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_25_fu_1992_p2),64)); tmp_8_26_fu_2017_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_26_fu_2012_p2),64)); tmp_8_27_fu_2037_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_27_fu_2032_p2),64)); tmp_8_28_fu_2057_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_28_fu_2052_p2),64)); tmp_8_29_fu_2093_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_29_fu_2088_p2),64)); tmp_8_2_fu_1401_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_1_fu_1396_p2),64)); tmp_8_30_fu_2113_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_30_fu_2108_p2),64)); tmp_8_31_fu_2133_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_31_fu_2128_p2),64)); tmp_8_32_fu_2153_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_32_fu_2148_p2),64)); tmp_8_33_fu_2199_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_33_fu_2194_p2),64)); tmp_8_34_fu_2219_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_34_fu_2214_p2),64)); tmp_8_35_fu_2239_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_35_fu_2234_p2),64)); tmp_8_36_fu_2259_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_36_fu_2254_p2),64)); tmp_8_37_fu_2295_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_37_fu_2290_p2),64)); tmp_8_38_fu_2315_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_38_fu_2310_p2),64)); tmp_8_39_fu_2335_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_39_fu_2330_p2),64)); tmp_8_3_fu_1421_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_2_fu_1416_p2),64)); tmp_8_40_fu_2355_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_40_fu_2350_p2),64)); tmp_8_41_fu_2396_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_41_fu_2391_p2),64)); tmp_8_42_fu_2416_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_42_fu_2411_p2),64)); tmp_8_43_fu_2436_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_43_fu_2431_p2),64)); tmp_8_44_fu_2456_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_44_fu_2451_p2),64)); tmp_8_45_fu_2492_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_45_fu_2487_p2),64)); tmp_8_46_fu_2512_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_46_fu_2507_p2),64)); tmp_8_47_fu_2532_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_47_fu_2527_p2),64)); tmp_8_48_fu_2552_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_48_fu_2547_p2),64)); tmp_8_49_fu_2598_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_49_fu_2593_p2),64)); tmp_8_4_fu_1441_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_3_fu_1436_p2),64)); tmp_8_50_fu_2618_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_50_fu_2613_p2),64)); tmp_8_51_fu_2638_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_51_fu_2633_p2),64)); tmp_8_52_fu_2658_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_52_fu_2653_p2),64)); tmp_8_53_fu_2694_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_53_fu_2689_p2),64)); tmp_8_54_fu_2714_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_54_fu_2709_p2),64)); tmp_8_55_fu_2734_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_55_fu_2729_p2),64)); tmp_8_56_fu_2754_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_56_fu_2749_p2),64)); tmp_8_57_fu_2795_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_57_fu_2790_p2),64)); tmp_8_58_fu_2815_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_58_fu_2810_p2),64)); tmp_8_59_fu_2835_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_59_fu_2830_p2),64)); tmp_8_5_fu_1461_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_4_fu_1456_p2),64)); tmp_8_60_fu_2855_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_60_fu_2850_p2),64)); tmp_8_61_fu_2891_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_61_fu_2886_p2),64)); tmp_8_62_fu_2911_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_62_fu_2906_p2),64)); tmp_8_6_fu_1497_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_5_fu_1492_p2),64)); tmp_8_7_fu_1517_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_6_fu_1512_p2),64)); tmp_8_8_fu_1537_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_7_fu_1532_p2),64)); tmp_8_9_fu_1557_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_8_fu_1552_p2),64)); tmp_8_fu_1359_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_fu_1346_p3),64)); tmp_8_s_fu_1598_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_9_fu_1593_p2),64)); tmp_fu_1338_p3 <= (tmp_129_fu_1334_p1 & ap_const_lv6_0); tmp_s_fu_1346_p3 <= (db_index & ap_const_lv6_0); end behav;

gpl-3.0

d7fabca6afda3cd4b721cf201445ffb9

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fft/demo_tb/tb_fft.vhd

-------------------------------------------------------------------------------- -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- Description: -- This is an example testbench for the Fast Fourier Transform IP core. -- The testbench has been generated by Vivado to accompany the IP core -- instance you have generated. -- -- This testbench is for demonstration purposes only. See note below for -- instructions on how to use it with your core. -- -- See the Fast Fourier Transform product guide for further information -- about this core. -- -------------------------------------------------------------------------------- -- Using this testbench -- -- This testbench instantiates your generated Fast Fourier Transform core -- instance named "fft". -- -- Use Vivado's Run Simulation flow to run this testbench. See the Vivado -- documentation for details. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_fft is end tb_fft; architecture tb of tb_fft is ----------------------------------------------------------------------- -- Timing constants ----------------------------------------------------------------------- constant CLOCK_PERIOD : time := 100 ns; constant T_HOLD : time := 10 ns; constant T_STROBE : time := CLOCK_PERIOD - (1 ns); ----------------------------------------------------------------------- -- DUT signals ----------------------------------------------------------------------- -- General signals signal aclk : std_logic := '0'; -- the master clock -- Config slave channel signals signal s_axis_config_tvalid : std_logic := '0'; -- payload is valid signal s_axis_config_tready : std_logic := '1'; -- slave is ready signal s_axis_config_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload -- Data slave channel signals signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid signal s_axis_data_tready : std_logic := '1'; -- slave is ready signal s_axis_data_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload signal s_axis_data_tlast : std_logic := '0'; -- indicates end of packet -- Data master channel signals signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid signal m_axis_data_tready : std_logic := '1'; -- slave is ready signal m_axis_data_tdata : std_logic_vector(63 downto 0) := (others => '0'); -- data payload signal m_axis_data_tuser : std_logic_vector(15 downto 0) := (others => '0'); -- user-defined payload signal m_axis_data_tlast : std_logic := '0'; -- indicates end of packet -- Event signals signal event_frame_started : std_logic := '0'; signal event_tlast_unexpected : std_logic := '0'; signal event_tlast_missing : std_logic := '0'; signal event_status_channel_halt : std_logic := '0'; signal event_data_in_channel_halt : std_logic := '0'; signal event_data_out_channel_halt : std_logic := '0'; ----------------------------------------------------------------------- -- Aliases for AXI channel TDATA and TUSER fields -- These are a convenience for viewing data in a simulator waveform viewer. -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command -- to prevent the simulator optimizing away these signals. ----------------------------------------------------------------------- -- Config slave channel alias signals signal s_axis_config_tdata_fwd_inv : std_logic := '0'; -- forward or inverse -- Data slave channel alias signals signal s_axis_data_tdata_re : std_logic_vector(15 downto 0) := (others => '0'); -- real data signal s_axis_data_tdata_im : std_logic_vector(15 downto 0) := (others => '0'); -- imaginary data -- Data master channel alias signals signal m_axis_data_tdata_re : std_logic_vector(28 downto 0) := (others => '0'); -- real data signal m_axis_data_tdata_im : std_logic_vector(28 downto 0) := (others => '0'); -- imaginary data signal m_axis_data_tuser_xk_index : std_logic_vector(11 downto 0) := (others => '0'); -- sample index ----------------------------------------------------------------------- -- Constants, types and functions to create input data ----------------------------------------------------------------------- constant IP_WIDTH : integer := 16; constant MAX_SAMPLES : integer := 2**12; -- maximum number of samples in a frame type T_IP_SAMPLE is record re : std_logic_vector(IP_WIDTH-1 downto 0); im : std_logic_vector(IP_WIDTH-1 downto 0); end record; type T_IP_TABLE is array (0 to MAX_SAMPLES-1) of T_IP_SAMPLE; -- Zeroed input data table, for reset and initialization constant IP_TABLE_CLEAR : T_IP_TABLE := (others => (re => (others => '0'), im => (others => '0'))); -- Function to generate input data table -- Data is a complex sinusoid exp(-jwt) with a frequency 2.6 times the frame size -- added to another with a lower magnitude and a higher frequency function create_ip_table return T_IP_TABLE is variable result : T_IP_TABLE; variable theta : real; variable theta2 : real; variable re_real : real; variable im_real : real; variable re_int : integer; variable im_int : integer; constant DATA_WIDTH : integer := 14; begin for i in 0 to MAX_SAMPLES-1 loop theta := real(i) / real(MAX_SAMPLES) * 2.6 * 2.0 * MATH_PI; re_real := cos(-theta); im_real := sin(-theta); theta2 := real(i) / real(MAX_SAMPLES) * 23.2 * 2.0 * MATH_PI; re_real := re_real + (cos(-theta2) / 4.0); im_real := im_real + (sin(-theta2) / 4.0); re_int := integer(round(re_real * real(2**(DATA_WIDTH)))); im_int := integer(round(im_real * real(2**(DATA_WIDTH)))); result(i).re := std_logic_vector(to_signed(re_int, IP_WIDTH)); result(i).im := std_logic_vector(to_signed(im_int, IP_WIDTH)); end loop; return result; end function create_ip_table; -- Call the function to create the input data constant IP_DATA : T_IP_TABLE := create_ip_table; ----------------------------------------------------------------------- -- Testbench signals ----------------------------------------------------------------------- -- Communication between processes regarding DUT configuration type T_DO_CONFIG is (NONE, IMMEDIATE, AFTER_START, DONE); shared variable do_config : T_DO_CONFIG := NONE; -- instruction for driving config slave channel type T_CFG_FWD_INV is (FWD, INV); signal cfg_fwd_inv : T_CFG_FWD_INV := FWD; -- Recording output data, for reuse as input data signal ip_frame : integer := 0; -- input / configuration frame number signal op_data : T_IP_TABLE := IP_TABLE_CLEAR; -- recorded output data signal op_frame : integer := 0; -- output frame number (incremented at end of frame output) begin ----------------------------------------------------------------------- -- Instantiate the DUT ----------------------------------------------------------------------- dut : entity work.fft port map ( aclk => aclk, s_axis_config_tvalid => s_axis_config_tvalid, s_axis_config_tready => s_axis_config_tready, s_axis_config_tdata => s_axis_config_tdata, s_axis_data_tvalid => s_axis_data_tvalid, s_axis_data_tready => s_axis_data_tready, s_axis_data_tdata => s_axis_data_tdata, s_axis_data_tlast => s_axis_data_tlast, m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tready => m_axis_data_tready, m_axis_data_tdata => m_axis_data_tdata, m_axis_data_tuser => m_axis_data_tuser, m_axis_data_tlast => m_axis_data_tlast, event_frame_started => event_frame_started, event_tlast_unexpected => event_tlast_unexpected, event_tlast_missing => event_tlast_missing, event_status_channel_halt => event_status_channel_halt, event_data_in_channel_halt => event_data_in_channel_halt, event_data_out_channel_halt => event_data_out_channel_halt ); ----------------------------------------------------------------------- -- Generate clock ----------------------------------------------------------------------- clock_gen : process begin aclk <= '0'; wait for CLOCK_PERIOD; loop aclk <= '0'; wait for CLOCK_PERIOD/2; aclk <= '1'; wait for CLOCK_PERIOD/2; end loop; end process clock_gen; ----------------------------------------------------------------------- -- Generate data slave channel inputs ----------------------------------------------------------------------- data_stimuli : process -- Variables for random number generation variable seed1, seed2 : positive; variable rand : real; -- Procedure to drive an input sample with specific data -- data is the data value to drive on the tdata signal -- last is the bit value to drive on the tlast signal -- valid_mode defines how to drive TVALID: 0 = TVALID always high, 1 = TVALID low occasionally procedure drive_sample ( data : std_logic_vector(31 downto 0); last : std_logic; valid_mode : integer := 0 ) is begin s_axis_data_tdata <= data; s_axis_data_tlast <= last; if valid_mode = 1 then uniform(seed1, seed2, rand); -- generate random number if rand < 0.25 then s_axis_data_tvalid <= '0'; uniform(seed1, seed2, rand); -- generate another random number wait for CLOCK_PERIOD * integer(round(rand * 4.0)); -- hold TVALID low for up to 4 cycles s_axis_data_tvalid <= '1'; -- now assert TVALID else s_axis_data_tvalid <= '1'; end if; else s_axis_data_tvalid <= '1'; end if; loop wait until rising_edge(aclk); exit when s_axis_data_tready = '1'; end loop; wait for T_HOLD; s_axis_data_tvalid <= '0'; end procedure drive_sample; -- Procedure to drive an input frame with a table of data -- data is the data table containing input data -- valid_mode defines how to drive TVALID: 0 = TVALID always high, 1 = TVALID low occasionally procedure drive_frame ( data : T_IP_TABLE; valid_mode : integer := 0 ) is variable samples : integer; variable index : integer; variable sample_data : std_logic_vector(31 downto 0); variable sample_last : std_logic; begin samples := data'length; index := 0; while index < data'length loop -- Look up sample data in data table, construct TDATA value sample_data(15 downto 0) := data(index).re; -- real data sample_data(31 downto 16) := data(index).im; -- imaginary data -- Construct TLAST's value index := index + 1; if index >= data'length then sample_last := '1'; else sample_last := '0'; end if; -- Drive the sample drive_sample(sample_data, sample_last, valid_mode); end loop; end procedure drive_frame; variable op_data_saved : T_IP_TABLE; -- to save a copy of recorded output data begin -- Drive inputs T_HOLD time after rising edge of clock wait until rising_edge(aclk); wait for T_HOLD; -- Drive a frame of input data ip_frame <= 1; drive_frame(IP_DATA); -- Allow the result to emerge wait until m_axis_data_tlast = '1'; wait until rising_edge(aclk); wait for T_HOLD; -- Take a copy of the result, to use later as input op_data_saved := op_data; -- Now perform an inverse transform on the result to get back to the original input -- Set up the configuration (config_stimuli process handles the config slave channel) ip_frame <= 2; cfg_fwd_inv <= INV; do_config := IMMEDIATE; while do_config /= DONE loop wait until rising_edge(aclk); end loop; wait for T_HOLD; -- Configuration is done. Set up another configuration to return to forward transforms, -- and make the configuration occur as soon as the next frame has begun ip_frame <= 3; cfg_fwd_inv <= FWD; do_config := AFTER_START; -- Now drive the input data, using the output data of the last frame drive_frame(op_data); wait until m_axis_data_tlast = '1'; wait until rising_edge(aclk); wait for T_HOLD; -- The frame is complete, and the configuration to forward transforms has already been done, -- so drive the input data, using the output data of the last frame, -- which is the same as the original input (excepting scaling and finite precision effects). -- This time, deassert the data slave channel TVALID occasionally to illustrate AXI handshaking effects: -- as the core is configured to use Non Real Time throttle scheme, it will pause when TVALID is low. drive_frame(op_data, 1); -- During the output of this frame, deassert the data master channel TREADY occasionally: -- as the core is configured to use Non Real Time throttle scheme, it will pause when TREADY is low. wait until m_axis_data_tvalid = '1'; wait until rising_edge(aclk); while m_axis_data_tlast /= '1' loop wait for T_HOLD; uniform(seed1, seed2, rand); -- generate random number if rand < 0.25 then m_axis_data_tready <= '0'; else m_axis_data_tready <= '1'; end if; wait until rising_edge(aclk); end loop; wait for T_HOLD; m_axis_data_tready <= '1'; wait for CLOCK_PERIOD; -- Now run 4 back-to-back transforms, as quickly as possible. -- First queue up 2 configurations: these will be applied successively over the next 2 transforms. -- 1st configuration ip_frame <= 4; cfg_fwd_inv <= FWD; -- forward transform do_config := IMMEDIATE; while do_config /= DONE loop wait until rising_edge(aclk); end loop; wait for T_HOLD; -- 2nd configuration: same as 1st, except: ip_frame <= 5; cfg_fwd_inv <= INV; -- inverse transform do_config := IMMEDIATE; while do_config /= DONE loop wait until rising_edge(aclk); end loop; wait for T_HOLD; -- Drive the 1st data frame drive_frame(IP_DATA); -- Request a 3rd configuration, to be sent after 2nd data frame starts ip_frame <= 6; cfg_fwd_inv <= FWD; -- forward transform do_config := AFTER_START; -- Drive the 2nd data frame drive_frame(op_data_saved); -- Request a 4th configuration, to be sent after 3rd data frame starts: same as 3rd, except: ip_frame <= 7; cfg_fwd_inv <= INV; -- inverse transform do_config := AFTER_START; -- Drive the 3rd data frame drive_frame(IP_DATA); -- Drive the 4th data frame drive_frame(op_data_saved); -- Wait until all the output data from all frames has been produced wait until op_frame = 7; wait for CLOCK_PERIOD * 10; -- End of test report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; wait; end process data_stimuli; ----------------------------------------------------------------------- -- Generate config slave channel inputs ----------------------------------------------------------------------- config_stimuli : process begin -- Drive a configuration when requested by data_stimuli process wait until rising_edge(aclk); while do_config = NONE or do_config = DONE loop wait until rising_edge(aclk); end loop; -- If the configuration is requested to occur after the next frame starts, wait for that event if do_config = AFTER_START then wait until event_frame_started = '1'; wait until rising_edge(aclk); end if; -- Drive inputs T_HOLD time after rising edge of clock wait for T_HOLD; -- Construct the config slave channel TDATA signal s_axis_config_tdata <= (others => '0'); -- clear unused bits -- Format the transform direction if cfg_fwd_inv = FWD then s_axis_config_tdata(0) <= '1'; -- forward elsif cfg_fwd_inv = INV then s_axis_config_tdata(0) <= '0'; -- inverse end if; -- Drive the transaction on the config slave channel s_axis_config_tvalid <= '1'; loop wait until rising_edge(aclk); exit when s_axis_config_tready = '1'; end loop; wait for T_HOLD; s_axis_config_tvalid <= '0'; -- Tell the data_stimuli process that the configuration has been done do_config := DONE; end process config_stimuli; ----------------------------------------------------------------------- -- Record outputs, to use later as inputs for another frame ----------------------------------------------------------------------- record_outputs : process (aclk) variable index : integer := 0; begin if rising_edge(aclk) then if m_axis_data_tvalid = '1' and m_axis_data_tready = '1' then -- Record output data such that it can be used as input data -- Output sample index is given by xk_index field of m_axis_data_tuser index := to_integer(unsigned(m_axis_data_tuser(11 downto 0))); -- Truncate output data to match input data width op_data(index).re <= m_axis_data_tdata(28 downto 13); op_data(index).im <= m_axis_data_tdata(60 downto 45); -- Track the number of output frames if m_axis_data_tlast = '1' then -- end of output frame: increment frame counter op_frame <= op_frame + 1; end if; end if; end if; end process record_outputs; ----------------------------------------------------------------------- -- Check outputs ----------------------------------------------------------------------- check_outputs : process variable check_ok : boolean := true; -- Previous values of data master channel signals variable m_data_tvalid_prev : std_logic := '0'; variable m_data_tready_prev : std_logic := '0'; variable m_data_tdata_prev : std_logic_vector(63 downto 0) := (others => '0'); variable m_data_tuser_prev : std_logic_vector(15 downto 0) := (others => '0'); begin -- Check outputs T_STROBE time after rising edge of clock wait until rising_edge(aclk); wait for T_STROBE; -- Do not check the output payload values, as this requires a numerical model -- which would make this demonstration testbench unwieldy. -- Instead, check the protocol of the data master channel: -- check that the payload is valid (not X) when TVALID is high -- and check that the payload does not change while TVALID is high until TREADY goes high if m_axis_data_tvalid = '1' then if is_x(m_axis_data_tdata) then report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error; check_ok := false; end if; if is_x(m_axis_data_tuser) then report "ERROR: m_axis_data_tuser is invalid when m_axis_data_tvalid is high" severity error; check_ok := false; end if; if m_data_tvalid_prev = '1' and m_data_tready_prev = '0' then -- payload must be the same as last cycle if m_axis_data_tdata /= m_data_tdata_prev then report "ERROR: m_axis_data_tdata changed while m_axis_data_tvalid was high and m_axis_data_tready was low" severity error; check_ok := false; end if; if m_axis_data_tuser /= m_data_tuser_prev then report "ERROR: m_axis_data_tuser changed while m_axis_data_tvalid was high and m_axis_data_tready was low" severity error; check_ok := false; end if; end if; end if; assert check_ok report "ERROR: terminating test with failures." severity failure; -- Record payload values for checking next clock cycle if check_ok then m_data_tvalid_prev := m_axis_data_tvalid; m_data_tready_prev := m_axis_data_tready; m_data_tdata_prev := m_axis_data_tdata; m_data_tuser_prev := m_axis_data_tuser; end if; end process check_outputs; ----------------------------------------------------------------------- -- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing ----------------------------------------------------------------------- -- Config slave channel alias signals s_axis_config_tdata_fwd_inv <= s_axis_config_tdata(0); -- Data slave channel alias signals s_axis_data_tdata_re <= s_axis_data_tdata(15 downto 0); s_axis_data_tdata_im <= s_axis_data_tdata(31 downto 16); -- Data master channel alias signals m_axis_data_tdata_re <= m_axis_data_tdata(28 downto 0); m_axis_data_tdata_im <= m_axis_data_tdata(60 downto 32); m_axis_data_tuser_xk_index <= m_axis_data_tuser(11 downto 0); end tb;

gpl-2.0

0c87713e49c65d48c284a806b4caca12

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/vt2m/vt2mUtils.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block hEo8ds4QehAPq5bM0bVdri0TuSE0uFiZDjrbnEDb3+C6i/+grtlk+RnwA9G+cOTDy/SBxW7jUmjl pXlbv+ZyVw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block naczDimjKLvLFYaT76c3cM3w70YV3umf3g34KG+Vb/Mr4XgmyOSSFifnpynkgJRBMJ1KoCE4qh0U rBOWObz2ghPg2o93I0wskmqQiLqLVlu08wekvzCFYfiNGp/Se3wPZhsqzW5Lv7OsPLKsqyB62HwY h+3UiEUb4VzKPiq3Kug= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 3FCYKmVkQIdlw2SYqR1WPdNAjn3fe92byO8WnkHdjaOF/F7agJuQO+9xfwT4i1QoSrQ71Lee1SeY GQnlOTHl/sbLr8e5w6XsEU71otMMI3JuVmMQNw47SK6vjHvSNBw2chnE6TVK6HQirh5kpUw5+PmH ydGcG0buvSx/VTtdHxOon2KHFDS0udH44DIaYxVu2mXAnDLCDFeqx5syiLPVtyYGuFn8iJkJ8UpJ Sm3JHm39OKPiqSYxQ66lH/qHQo5/ju3EZbEdaffsdGrwY+Nw2FCuIdkMnT6VCsZu0bptinAyVpRu K7QrBlKij7iTqXqBMFfVbczxivx7P8S0anpK1w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ycFKEEqFNMcFYF+dxpshmztuP0f1krYybiRyZaiwDKzUcQOjiwySxzqjzwp2PbOoixYhYyqm25uy ArBTeX8lOZKrbnIziP19L63z/NyX0W/hcQS2q8Qm7fx94wBplvCA99fhOMTpdk+bcEWiscRiVaUr 1JGc90MtIvDMPxYwPv0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block FIs0g2oDWMIHPFcXndVi087Rbo8xezmev1Z01bnDb9F87XrUUTZdk2nZy1Crw+wym07glGwW4oHB +pnRgSqb0Fm4j3DOxoY+UsvMnLgyCbMug3Fn5LVC7Z76ym0yT6HAVU2SBtZv5WGyb9/4IvgFVIP3 Qx8i5lyV96JqPvynhJSWAKKIXkvargDLZ3td1AU5mmwOrf8A4xNNbbLMI71BE9KZU5gmcKomoQ4u TlkTqLk61szQBCKQO6UCbRxd4QIQIBEVZzVQfwtAUVKVCjjX3AhlcN37VXh94/xgDs09jmpMy8gO Gvo1C+i9EmDNAAa6zJhSBfLma28lf92sfkfT6A== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12576) `protect data_block sYepyIXAt9IqU/mYyGNpZfqPHLkn1AdJDsXH9fnDs2PR1LbzaabPgeb4ShksrvSIDEOR0Zca3MBy sN51nsxwG/NvizPzaRVjH7vUdcsicHCSSa/eXPos6eGs3R7twkzYGECuFiqjBntjb1VnaE4QrfV3 fpGVGLuVsKtNx7Y1ry0wE4wg05sgubZQ4mnJJM1fZLtrtl57u5oAYnussXows/HcQaF8oD4gsbJe BD+Sf+2NeAGRwZ449mYcWVbvxqdMC2VSWNPRfutoLTLPi02NvrEBkD1qLZW3mWpFf14k02MqTIcS NZYy72Mt+ZRW/UBxkS5V8Eq1K3obA0ZYB5c3L47HNOte51kxpFpvW9oJEs1smM2oJtw/HPmNFVGs QGdSrPF3m6wuz1kiDzR+8cHpsz0t4ano/wcFC57M75BwoC0QiJmFzk5bpQkh9yGl2Fi8ZonWRV/r rvVhkIyEjF6INlSyQmEUdDbYtUIshCsUzIuYICv4zPxGx9TrCYlakERx6K8zBJcA6qLMp7RQ5ZVG vyK23ApT1ZIu4E3Z9o5VBY/Z+oL/XrtiwcjNmBHooVtr4dcC+8MuI172gvYJ/xAVMmQn6LXFJ6Q1 GRKreY7zvp1voQv9lTefmOrCiuW1nmjpg1mxHt6z0MK7jI6rRMAV4ihg+/k5lzje2ojSOsK2iLuJ l8zv1dKP/mqMUXDLWYRy0gIep9mVJ29LUS84V79L4i52SNZKPLaiKnIDA10Y03nTX68qQe9adB8q /eKo1IlrhM0GMMUwCoHoBv567HVFJ9VaVlpmZJlnzkwoXE85d2oFVh9uM1HINORE/rVd5D9d//jR atThblkhiBjuJ9BM9QYkoloHZLVvIQYZ0vzhQhyFPy+49jnj9smwbvxsMkXZLpagxhBKbmsyc9p3 kS9knwRSxKGwMzMi3AMPK+XEc5myjgA05FeL9LGKLRieXo/l6+hP6Qd4nVMlAKYWUZqoVXVWxjYU IiZZmbpgVU+vSNxy5rKTrGOedHO4SFzBNnM/5pG4AwhNNfOhAunGPWVRL+GvEpQow22npR8a1tW7 whyHkUaOX+3BflR/EcDKlCWIenELBRBeqkKD2Kg+qcxA+zJUTzyRE8PgSNNyA9uRpDbau3ui5Ovu 0AKIrRdbvJqRemlM9x7AuD6WI8nqdI7sWRwuLXDILfk3j0gbccnGUPp0RqEA4qMNrMsPENQldIye 5llfKXSNpL2R9/TQNw2Ikawudqg9r9h6x7/vNSvYikTvBGV4csw5vumBH50ahyJTE+QmvBzRvgyZ tytZ1kvjZupceuYoiv3gsq9MiUiUHpULs3BVKNYopdHLht2eS3qel6wgn5/Q9lrzKyjwdqQjRdA+ LNFJclrexvfbZw6aQySTX+zC59+hprrc9t2gbB7KeOYNgPH/KtxUbSvve71xyw1i1kbU7eV1uYFP VVI/sPB7RHu5aWEw4GZv5AKKJXwGSEM9KypNAeteS9JDNe9nwfDni00h0VFarivL2PycjlfiS33T pu2LoMyOXf58G08KC8uGi1upsi9FoeVSWREJ1+JBtKPizypLzNNekkXhf0hZibhGiL2t2E/xqUNH pApBtl9wyU86gZ2UBLAjE5+lR7PHhKlB7Onql/TiqOC+07MmlJwW/71eLhSyEy622Wx+070Q3h6K SZ2NeYP/QL6Lf4dNABJ+ASUWw5Ge9b00B+A0eUHkFm+JCiCTLEwq6JS8RoWugFU/mC4tl4z3hL03 NDZr0m1sTEY22aQwBzqdFAw4ov4hr69MSa3oIFTNeLwwkG6CitlcX9Pro5i5pkb9SBLtFhmZ6nrz bJfeG4mb4jZVM7WmrIa/zXQnwuYNDNiHeWUXcgvSKju100Cz02cW+hD1K2q2DQiNMa1Md2AvMQPQ L4A36ZTEsHEkSJjHJyfxg+bGCjXQGiMaL2BBBmQGSsylkP8b+EPCVkEK3IXM5NoVmWt34hPC6iS/ 6vaRcmuz94zY8aW41cysYZ4z7bPe5EX3WLLj8Q+fIGfSZi+1BF1cTHQ/mNo7sG7eK4PDPrfHof4c H6EtD3ck5By9iMCYOjTGdBqvHjNfZGWZwh8MBfkWJ+oyLjciv3a+sbferO0a0ey5JarJMoukjwQR SmljpHVnR1YkPTK87o44a9EvscnOKGAYQZe3T4zxGIDpqfJ48/+AJTCpWWSe3k0IRQK4+CaNV7CR XwxjfLZLfF1/Rh+06sBYaWT9ya7EcfLT/b7JAafklECh8kJN4XLui2SpAzRE2lCTHLfpm+/ovL7W V6IAyRjwHwwMkjPhabwKLKND0MjfKdNuAJTB+Fdg6azJYx0TyqfA9IBgEPaofeAPQnfM8YlU2HX8 OXwX5FRiDSst20pzErdgDhYZ0ZOGnzDvZ5ll6DejfmBkzcHNmbngOhEFUAl0e8x+2BF01oirZmZa 9moIFdKZnrtMddwfV9qllJprHxzxvV3BiUhWJD0N1COLjfaD6n0fGYTkJADq0IlYzHaUW7KV+3nC Ea3pQ7GNcmvqzWqUQyO/w/E9glM6ZfOuNzWWIKw9TEkILnHL03oo/I/9YzxW0jwZW78xRReX+Uwn 6ZbGFeJmozwJ0P5742x4LEk6OtEkkEZQTKZbBqx+HrtDOpsM894Qt9ksCjHwLYh9i1ElItTmsFcL XkYvU01HG8sAI2eG5KnnYYWe1ilqV93Z3v9X7ecjGgJE1N0y6kHqIgo+SRS/CkcfprJd7F18Xc/U 94Nu0fXT6LoKTRyGt8TiTXHkOoQHRydsitoiHt9189csmzU7se3PUWtIyeFE28rPRzIeCPxpEmfW A4S9bzliKouJ7SMbWDLP/9rHC1hu4QxZFHmSKX4tc0RveFxUi+U04Wt80zeBkvzBfbFCWCXeXCoN CWGVtzZ54VLA/ScIR7u2oS9iTY9XnM7BK5/JDASm0+qiznITWP24YpOMWB9lymAp8SabZEGA26+B Bj3vfIHT/10Cl9CbGZT/TGg8dxgzxSN8RdXSYEVcDPkqEauz102+9pfz2FmjtArtCgZtgy+7Wh0p 9gL1NvoxRplzJc1SgPbusiWs/1tk3vyB4Ezr2qH5ShWG1F7UIxkojk8U1Kz9mXY0SoxnbOw2mdm4 clSTH5l3AdKR+NVj/OWWkjc4uDyiVFzO198s3bYYaqA/OhDgeV/oHUDjoFByqD4Tky86B3/OaO4R 1SJfFup1uoxz1D9rQBjZ8TPG0w0kEwq9/yYLdJd3ZlclXbFJcxQjAsxCY8NSirS906lOohL2Ve2J 8rk/FDWolqcpdH2KOpFBFMPajkO1vwwikxpz1/pT42CBsPAyNEFKb+GJHfkbpAbCeHaMIYHeRxii v1msrnbf/sE8wGUtR7fchcYPGf4Wm30z5pnxwjqatYvCY0/UjCy8Ot214Bfbs7rVzLpxxpPSu66b OZAnPyBahrbh7Dq98RL2R5TDfGfueJTnBiqqLMoEJkBYtytoM4nwp07Sqv/pfVyodnWbJ9s5613g e5blW9bnM1DKMdhEIhBNtLjSpk/J22IGNDuXosObTCpnPEM+q5NQYv2hmRZ3LDm0BeGZoCxfPPVz xw6fBdFLafVtCrswestcqpDY8ogiH/Niu4MO23ML/17AL2MSCrZzNzYy+E9eFB617fExupGbVMib s5FQiKzBdawxAK0RycWRe3bZXxeSQ0QLy9iBs5lkNOGiPWLw26ket0jsGS/842b6Yw58oTao2m/+ +zXp4kOtKECQyGCtyJG6YWXn076jskwVwOLXh3HOpxzhHa2GQyNwYRA55GqJZ40XBY77V5SGmDFM Y3+xkwDZNcdnVPv8tjBtF7kwBiYNH5Xqg/REckKRao6C2urAKy2Dm2Iv61wTJ4abh9D1CVyMVJ+U XRxEcMxDtFo5zwq+3MTPvUWxJg6XM2I1ulA7DsOGttUI3IE8JbBEoEj/+go2WCNdZGGTrmTHBKum EazO9WgXAzEVm2C6+nwHwM4gl10JaHFT4KEnkvq655HonhoYZodECLTzHH2WbF3zmNw6O9H9CWQo N3Jnb7gfbWuX3QDe4N2e9vuLD5Bf4OdPNxsV5g9+/f14QPHEcgkb3pvXdfv7Fqakg4nA9lw93Pyj oeBPoTUiHV4+peJQjPirVg0rHb6nB6gdqb62oWicS9hLGXEzVJn0KDXkORS229ZqnxqoWjIOj9UY dbHHXm4wzlOdNewMHsuXCO5EM2Zch+knpjzjatQXGq1Rhkbl9ar54XdBCWQe+cxtiftyiUF6SGGc XG7RhkH+e1Zlh20lz3XSUSLP+03xhmqAN/0mors1KRAArnOOdM/Urw4nmQ5VR8KO9iqn37b8oFZR lE8pfsB/Oib4GbcNGyU49bHFH3EqM93qHWnQ5WLtIV5Na4aEZSv+ack73mdrW35e+DmPi1ygMGeq h9ix/EWz6AWlSyOe+VDlzI6DngUojSazHD/TU9RAAeFKBKYObhcKyi7PbqHs8q4xnQCQwr4aW00y LtJZC8rStKtJ/B79xDzIc72P+k6P4AzkxTekn9ajTsK+wTHfBrjz52AjEN9HqrAbFXmP6FsM+r4V 79eohs3j/KM2mMIRJIOs4025lw6gzMGuXIud+4S4NQE8RxKORW2WOnP+FUg3PojPZh7pWDQqG6g8 XWK4m3dsFKF/RQ70eGCPYx1ogvk9+JX5KXVsho3dfU7qMipER90rL2ZaB23oQhCa8cxiOrSY2bZv 7MO8P4arXOU6PU+5AhdwjAAO35JslBdgC6jko3s38ZSnKhuTiKKsLOBiaqyX/LMkx9GMNKzOLUJK ZdM+X9J9ABx29uTWIGcx95R9AFVz8uQkms1eQSO+s29/uokrMz7uzqSyn1XGaULAaj6aUOfKalMX PH/bKKEtNn+/0Gj7pi7kaTpnVVBuIr41qBx3z7cxduJOcbqlpIuPtqxT6ryfu0CU/6GBFxGiJIXJ LhuoNesNzcyiJhc52YtQnqxcAR/NghdhLMkZALe9a9k12vwCdBT2I4N4FPPlKcFDnKaBAghey5R+ E+/ZFq3ZxeS1Jueb6Ra+DtVfhz6BvxQM7fQVqlBpOEo77YNNfrW4v+h/xcZe0Fhlz48ZBjjIjmAG G5uEXxpXmqqzh9dyuG6Z2m5eDr/hVJU0LpVdFOSuatP/44C3oKNxi4JxsLtRZrzx+AQZ1B65gYZK fLzGgLKswPKiDrXwgCuEhjan+snDFuDllMNF0RHmjXUJgUUseJi4NL/YGmkYuBEmXaQjQ8Qxtt95 P2v57pCjJj+nJJjh40PwGS3b7dNcUjlCHvaT0Ls6oGUL67/hTiqOfFvHQxGyCtiA7Oy8rsfrsCcX m0z0vjkH107R+qESYrW3o8RQNy4x4943o9BvJKCht9OmSXqofWc7KiGHd9K7Rbionr7tUmvdQGbP fhVTc24A6/jWiV9+c+q+JqBAK3axxNCrnOfI3nFKQ7cak8/J143t8P5xnvIh8EqyistQw9/ESi64 ASfINHcdL//58sk5K104Tr4Sq5CLTWJjj+JtBg1ywtLDefyK7RIsSyoz2byNNxv691JdrVJV4a5I hTdEYJRGaSdepX9HBJlowEZK0Cx67icZpWT2Pmlw2+p343J5znkWumVUfHXxNFbxPA8ISoTDt5qX aD2L7j7nEJZurMZORUkWvnDbkzNC6N8YKWIsPKCMDyGjESKMFcuvNgEEir4jnPNz3nDZ06nPQ3Tb Gf9UjG/9+J5C7HKbGIrBExI4BVYkM835052wuZDcjr1JbyhxXeimpWYPaw1YsauBNMz2aSSjm1D2 70kzIn0Rbc0Tu0XdURhK5U6mTzql1WPHmzm3O5mAxUN08nHRzo5Hp5Yxxe0uvdUzga/3sdrS16Cq 3D9Zg+y9/I2uXs/Bm82Z7jxqj1nCA0lBtSaWgO9usVVgHMLPJgqrkIxX0xbbRspK4hMgv1pBYhx+ zGjSoiXdOOg2xXiqa5CwQfAIBozp0x1YYNh8GbpBg83+8CLLEuqUdezhsVA0MU8XxTf2QWDqC2MG O8yu0KTKs4oJlLTJxrK2z5FR4e3vcHUGFDrgam3ko7ESQ5KhhRMLM085HYaHtwoGINwMyNh5iVbP dgVxRJWA5VP3g4m820qwEgtNLlkC0kUkxWBBHB/gdYKz5MErWJtclnh9HgWT7UfJ/30GosmY+8JT nSwdsFdOE8IZJ+G+Rc6AsOKUT+U+JcutcETP3EC1+IHDdzOWNq+2fAf7I3MMeeH3Bd/oQT/pMrTp hziZDQjriie6DooiIHPxDdV6ESbhYAGfwBM8BXKt3Tfhfoc3gaABY7xOWBM7pgQ/iZON10WPocnT KPnDfKC4uZNr/JC8lsaP0nfsbSEjXif1gqBLtLhrMizVJs9EqTv8GruIr4BwqlFy/C8MooYkM5VU avaVzsJzbYepsCm1HDBGBw4HFMFJPrUrKX0x9A1U1VwmYzoESdjat+rlBQZ/a95Vrxg2A01FD6fb kF1miTqoVm7IaFOgk63iHkbL+MuSkEXeQ6xGUEMztLaq8HuCtSOIfcZBZJSM634D8AS+jaroe869 pfST0bJ7GMeCVAoEIg9O/2zOQjG86GBLSrVXN8Y0oqzNq7tpN289Zl8oIo66D8GRIRN9LpnHtk25 AAuumpCFhIeoSncT44kvfjgH+M9qV6ZRzBx4Fpsvm/4xRUfXxiYf+kmbtmCWO2bqyIlvQeTf/kKN flXsUiVQGsPR5gGI99hmUNfDTzpxqXw++yOjzeqNfwIp0Rua/ah3dUDjmF24dci3TXpykFSVEeBw xkxhswHJUee6qjPBYK2LQnLgAEjUPNuUAycM/TJSIHrZXV/tiN7GqfuTu14A18bVk0rL5CXNKZ06 UNjJdqYy9K+bvC2O1w5BZf5GHPNhcHv1s2oTSEsKRN6daEJjkv1STU8v4MMvbRXTHQ3+sMNgIS8z 33A4lkq3KJ7TxzJOgB3FXtcxhQK8nW0ARZ/WJsTSnWoD50JqdXmWCzCHp7v2n/crrUxZlllJaRMt lQMksGDAhL5vr0pwdwAzw4hLk7lVgBwb/28EfZmsmAWWK3zwmty5KGlTFCIzjv6q4dDnUZxIMyGy VTqjWfWywm160QOUp1j/N36ceZpVKY4rSu1vJQJ8E6aOz6NO6Yd8NdQFPSU+bSNCkaEI8lSW66D9 1DF6CnuqVy0N6z7RgknW/dn+sd4sciyIxa1cMj8xbrd7xERgDi444RIKeWNamGcPOxTcgRyVSFKV 9UOrq+3sqynaOb8BGiqvNrBMhw9eE657/TUejrfgCXGsY1GuxUQn50UDGIVIxCDZCuoyhj++A6j/ poNDIl7qonkk4OevWk8PCgpKW/M/5mzyCMn+YsrwjjuAlBOLCU8P2ROPxHAIDxiZukO4edBMFFvX jgBU9+mNCj95htWAsqFvNEaqEmrlYmPcnOHkbrkby/dPhKjQnwBGJLvDyWxrbFX8PqZhIDci8KMc Sgn0CgOSsl/l8V1a5WDtWYBdWrO9LMsctGhNAdlzdWEF8iNOLPoCVx9qLPPBRZwWcp/2sSLkw9+l 881hzAdv3pMhCWQudRNaSRKwpNc8ZI9GvWUSQ0luR9UjnL8Q8zvYd0Y2gI2pXW0YTxLjNlm8PfGC FXA3wQve2B+Ny05Lej6QysYuQY6AArlTMwy2F5Dx5i87vWOzPBoHadStrgA8L3PiPR0wFe0E3Pjk 79N9PrjfIb4ebrhY62Lc3CUmHXzUW4r1yeLU03OUfXQ/mS4ebvbvHEp1TjG7zlAQp1N/Cya+kUlm c98oL3/MkeHaDhJfOyXMMPhCzU0ugRVEh467Icfg9XCq+9FlMOUuntEORNeUUDrZw+hk7GeHm0YX 6ZNdWt+F1ly0ZKn8Mnx44imS+1K9Xqi64AKQGyetduZGErtMlrQ8rEqxgxuo0kVodlxHGfiUkPjI P0vmqgDSaVQgIJwYHtFmaK/9qQE+8OsT1pqcL0YaukXjOVRbzb0GZB9G4a6hjU8us9qPmrAVGrFg I5g1TEy/M6Zon+ZYbI9RY+t76Rms8PCzJnEnNEQ7M0rHZmsWmPWsBvFXVVf4q9b6aKJZWQJTE8I3 yUylo67zuVnQY/VBYtsFVi52X8xbcIS/J5zOEgAMYqP4H79k1UmcMv+04P7m7uUD3QREm6kcEt2q p2bF94rpW/RSWDKcDgEADHaL/V9Wb6edLJlRRuGafncP9NZNLlSqzBP/lHYpSLygvSqkszZCdhnB wK2MN6z5GrxQexI+a7JhYWxgR1EnBYSuGmBul4aikvdxzivqzVfE89pY9RSo1ZeEBpNoHs59DLAg dd1kgz/9DtA0rEFzvcqfXEOGgA9KtbFXiYMvN/vdixJVaulLEopMslNLheyl0bG93N84uWYYOcnB dptIkOhSd0o8M7pdBLEXlyGntKhykXghjIBEf24kfR0s7uGpnw3LusX4kmg6opjRRAN8vfnBJQhW 3MGkSLIgzbGO4SSo3fBRq6E4f4iRN4E9VhzbM8dHJE5HKrFC5i00c78RDANzIDWNS7wsK8Wfx4eO 8VbxFZgLviNkXpBpnv9FSDBMLN4wkOkQV3W2O5D/tVGCjGqF/+WUY71kaRu+HOTw+FxnrPirYXis DRmA3PKgfCCXA3cit/IGFVskDjFbBTe8Nwpo9qstLstHh1mKq2Y60kwCPoQoA5VpkGvrqv91t99/ yvEwBmrPz81AAVRMHILdAau06AjaGiV/l/q1XnSAYulMGAVn7/OAgntpLCBia97MmZgUtDA03S5L 8y7eMB6MAzcntgVxmPoijtlzegyKGmc3T8F3bIpMZQleeyRr/J0vHVL8dd/wm0o0obAh1UZhgjUk 3mzXcrMUNqWXgdgg1HAanF+476lnyvGX4vddPxP6QGysa/dKlQ5iktM6972pPt9m8mmroRym59G7 6MGtkujmm3fEKLpzWfme92WGzZjlxHfRXiO6lS7nE6qTouNZ+dlPVMNo8/xU86GNzaqfOnjkRqqa hR0+mR4o+U7GRfjL2JsEPZ5++2Ak85LOf9p8tZv2JYcI7ZtRRiot/9TVfDkxKleFbDCvsAWvtDIA EBn6pjq2jh+qtOxXu85rCMUzk7ohxpNoTrvpI2VgNt5Wvdwzu+wIhK3xaeV/1DUZVKHU6qYfJwDK 7cTzTfGN6UD7CQQknUfooV2oLd/hCZUyty65vXhvUX1kk6I2njZq0SI1gxF1aL7EwFvOMNS6pYlY VmDJndxd0nFszOyMXYbsNY8yxELmzBx2jGDXygK1WwTVpLuwV2llxaL9q4Tvk0TyFvLSjl6YKrGb zF6+lGl34Zak0KFYKQXnZfSfSf67BXH6bnH8IRjlu3qRVOqrSnN94eoMK0izbrSWe4PoHuoSzcx2 1KfVcFm9qtnqrAhf9ZFL32LU2D69d6+dpyNNRgJwJx8qmoiHrVkKUGfFeWIwwLxAvy7HTjE3dh/y UBk07Nz9FpxK3PlEp2AeL0KDUB2EFAfzwOsqgDRN/+YifeG/jNVCNgOhfTjHpBB1k5ml1KKFlwKf PeDLgZhZPgNFDV519ZjlmRZwuxYzUx0I8rkIyePoO1p24QXjWw5Q/EWmXPNuAHPg9mM7bPwrPt+4 1/vwkfayf/aIN9vHzKoFf1nmZ7uqYtimJ8qj218bMJZ6dRapcj6+SIgIez2/VlWhtM7LABVRHU4b N5OZ9psNMphCJ1LHgmasmJA9Z+7XJrTlKzj7bgiWeaZIDRyQLDPiCFT6dvKpJ2DAaNSJ2DSagz16 OvQzc2JgyWOeSJkuH259n1VZB1aaurShZhYkdFRX5UqAQf7rfBS+RQoQOjeF4qqkDttZ8Exxe5l8 9Np1HE2ZIke1A7VIgYvPThV99lVteEkR70YSlJQfYTwO5404ibNFLIllJWcpshd17BiHkJgcAdJT tUKtGoiuoEJfefAuSmATU7ktNtC3sOrNGr62FZJmQ6q7KuodHVlbk1PP49+1KfBjEAzSASzh9Qis 1/CxOifuKkX8vzwOTGo5/iWMTbPQD2G8LUFa1FE1Davt3143hwJIhMCWdsSzhL/R0pPDWGaowHfk lFbROwh4Lez3moI/EmkCzHwHbDMgSx6uQwTDMvHB/Gqhq6Vduf8NQeHSHIIv9J6Z+mSVKFS/9fgL JRJpuL0xprPbSGNLo70g4E4ZO8ceHyCnJk8eNY09sUgOl0NMfnZ1PCl//AfMSA8VCbnALca5GhGt +bS1Md6fx8jPFvUo65Gh7A9Q9R/5a0N/pK/ou8HPC32u/6XK9uBnPpf+FV4pfr3sZPsa89C2rrPc MGjU5ReXaNgxTkxRmnDXOTSBEO+t7X38HhsuESRSgJkHemzjBcav7RiiUnNz6VgowyWQQbnZBbnC f4zGLGvdPYrpw2X+E5gWXgQ1MohsH9uCCr5Vjgvjisa3yoWkUWeqWiwJXeb14rHYEtd5Fz/6x8TK fVhoJsJg/wGxxMwCEUk/RWQsDTYvmoQJXuKzUpG1lTJVQcIfOjnh80gauhtmFJg8av0z6laN0BJG mksVZxHcp2RERa2gsRQoj1ySuEjjaiydutA1HjFyhDpfNNUO6SekDs4vmDpL8r0swNA+b0NthVmM kfOmmNDp1n2w7no97aBtzC3jcnjdzL7LYcOHiCTN3eGZErQ5Gw98V7OsR26LBJRhgeOFTiyYv348 DlGXi8Emdw6GdZLG9GQV0Zh/qQ9hMPSCIwA0Sr5Teb27Ih1VztATLu3RKAZjvUQ+uvq+KciU2VEJ KeJYVNuUPePLCVtqXFbyANVZCnVvvvRQBHu+VQU5UbTxpiZjoHrf5A3PF9T1zysnBDVjSfYBMHAE lAPUIbjHW9ZebnbkYN0weNlCuemweskn4vOHKuIeqdv6dykcGx5qh7FuVHS2SIoW+9GYfFEuJiWD DO5XJO+ZDxx2C/5DvkA8QmlZ0qKRr/fJFQyw/+nOFRA4YxH804BsBTBz4bMUVhz5c51PTEnVg0ZO IKuMeaM/ON+MpW3k9vSWD9f7s4TJtRACDVDbZQWY9jtqODZHLzoL+lmMtYyX5UZ+hwbS22tA0Ssb WX1ypvZ7G35kI/B+KvaI9ILg3XqB2FAGKs6M6rC3vrNVTdqpkPquySa70PM/1PC1SKnSFmHkGSdY v36WHZSBt7wecfApurQm7C83VEhyb9IAb0QtuqDawOfERYQEdF9Qu0oiNT6lmQKgo3tGBCvDurVl CTXw+LfSey4pg2t0jjuzYTvYlBt2WThgGJ/KSIm2k1We3240fRNRwDvhSKF+b7TDmmvBiGswSXis JnRqllzrvMZH2ursoVHIP/3Ug8PHdvwzxOp3EgX5GT2QeGMUvPVTZg1HY2hw6Da06MPABXSdvUfO LoF0bR6FFVdOTxpAppVO4xwqGuQo0554tQhZisAi7/1Cx7XbsA+y9sEdll4N4tAJ6la/1vfQs2CX SPOra17ygCeLetl8aaMzKttAOeKOtA2xI4bt5szejuGmXtvqKrSF6IM9Vl9pNMk9CH5+PE+YC/uE yhelOzb5u6xwK4SLphZ/030wEDf3g46hJXX2dYvMf3EtNZDwN85TNxxEABCvuyArgLwRhC4ypTsZ dKyW1KZ9R+j6LZi0LODgmq3aSbc+ihCN5KighaUw70I+Nj4v1c0udSC3v5pqOf5Hy6mWfYxAsfvh wp1hTXHfSgfwnWPAePSsO0m1LNMfIX1ZXW032haUWHjyKNR9GGV+t99NbCiSiz7XHaC7BZPYLpZG yHV+rNfi2CBtrkfP9RfBlhuyFCuLMP/oExpRn/aXWtu29khbEM2ymlaTldZcwK/it0LxKswrc4dj ebXg2Ib1uNWg3Ftfgy23ZvnGywdr7pEL4nNYhZiqFoUfaM1pp82TVNtVgNbC+zRfsAZ6MOYx5aU4 QVBgiJCmYYjHfIr5LNiHc5CUsRL0nhMBsPZiD/1KV6rzaJtqzra+2/EYcDs/TD5yuyoYta+WH90G rS02eD4iZa4oTGTrB4/58BCBF2LtWwBSSnhMs38nmwdUbZ2dfWvWu712vG30QMz1v1pvXLkIfDJZ 1AWB+aWz/Nz+Im2PIwIKd3zJink0ShBsYAp/I6h21R0B37uDyNAin9Hq3souXlv9hKxkmIlVM9oE 5uEYnF4v/QpPOfFT7Ud7fk1IrSVzOniOJYC+NxvaLOMMFKB+EGucW2cJ4BOBDFp/0qqFg3/i0M/J rPynyXtg4WOKPifRfXq949Jj9LsF2bczSFG4K9a/3RFXQmtJWkNquiDHOx8J1UfD1MI3Gy4eAo3S Qj/XGeE+LwXXZzi5gemHbxSC4jw3PHOsIiswK0R+nraPh4O3iigo1J+LalY3dJXrSlpoKOJMIreq 6AML2KlmW9MzWs7NjCo2ISlPe2m1zZfDkAe+jmwLs5HHJ06j8b+aJ6UShZlW3W4I7h3xbrm29wr2 v/UBSwSmygz9pvEtf6xhkt0tj5cdonGtp1pd1/EzI2UsNSHb+tzaQWG5IRFLoy44o+HvwVVQ+0OQ AHi24i/KolcuwOhl9QvsRPShPbmSs48p15ZPTfNFfdG+kTMBnpWp7ffQ1MspklRbZHXJfZ1QHjwy rhOD3I023Mg/MAUR+WtxzzZJJnhuF/uegnnMeZZniF2EerOpy8SJ7cQ2SXpoz2aPaLbzShOTVaR1 cQapb5G8JCGcp/voQiObXhxUSZ/8Q0ier3ikbPazDuHxipKOyuu1sNBZ9nPKHkaye0WwBKRs7APs prP4RG1OrgTQRcqivxFY39Bwo5dtyrqW65pOBw0K7jHidQP2Nu7NCJhfDOM4RSl5rfM2rcQU6PFN GqM5BJhcG+iaBVEGaPOb8MqRsJ1hHts1FMiPeF0eqbb7F2QfZ4ZIbvBnuwRVwKB3p31C6J1u9jyq pJHaxUBNITy7PS4CftD2SXs12OZxybGLrcAWdmZL0usveaky59A+Sl5SAekxI9yJLXy4L4IQ8PB/ GATbkemb1ztZPdGgE9nYIfIJZB0/rYK4QYyhYPUGLTwPkzZ0qrbCN5zVR869nE5+NpIHUx5DXmyz Wq9psdTHPCDvBLyeDLx+73eE51Mbkrcei7AXm9VAjEiA+nt6wXgx1ePzZaONaONqqdr5atJAW25F b4B69wfLfs3ER0p5oMYQwfJPjGhayh87GeAolJ2ZSXrDmNjDZIy9klwFE624BxVrfgJQAQCGX8Th 7k2NpK0KB6N5a6i543dRL8VetRkhIQ2Lbh/6LX1eEg/bY8KqsFq8yBqMrkyQEIss19paD26SlP26 YeD3xoYtlcqLP3tVKykraxE/lPFXEFN6GboKdevGx7V3bwdvoJGA/+dkzPwkzunxKh0mTeEKj9gU 8A522BIq3XKCpS/RiWv3eBDa9ulTynwv3Pr00GdWOVstFUchl7IAi87voCTAptzduTM59nhHKVtH Ni1NcQU0Sj5StTzrCIMPhpU8XPK0BkHV+NKjqq3l9Mt8BDPuCcttC6Q8XBgD09mPI8cXhaXQsyLM QBQIuTzafsY7dILzeyGGC3cLEUqeIothLhll2VHw+zNa98dsZybelaoq64on3dgnvWVRioiAmzKR cAloqK+PB+7t8pnrIMQBwF1xUgdDkGcwruavhd+2CsKdUY0Y10afy7wGDbG1zLD+M+pYZR/6tc0S 3LYtCC4pl5sbcxwOKvG+7tu+nSkaFFKwKpOK7zZ0Krm1fJn96DBj+vrezcrQf8NHboB+QwnHWbsM Cevs8PQOwxWuwuLjIHHEXMa0M9x6wlDVbaskGVoJLkX0gygtjYlIRdda9GRLHLiDCyR4ijVa7/HI 6PGjbhpaexNw9fnZbfi1ylzyy8y7M9/yd9IapSCeViQbFyvJCudCEcwk1/O08aPohtW5mt43gLgc 2CBabTMEWp/gHWAFW4lJ20x0UulcPv4gQQbCkk+bO5H0UxRTHHSOXSSuYNrdfMSnRmAhZ2nqLKE4 1qEFweX2k8mvDyP43bI/NRQZZzUAotkXflUR/DwSlNFFoHvNDi7H9os7XnbfQ3QuobO49XkkNdeO bp/J1pxCwbRbPPXyUO+n5v+4dKdWUcnLpEhe8otv2OFBAM58Lu1wXtbmMip8ImqGnKxbv1N0l60c 7rKeMw5/kyB9wYaugltkJM5VJJ77w5CyZMeSdBOQfxBnyxEWCsZYY7So80PJuCTygq7NOtpDd4jl oNajaNEhgbQxawDMGy+B53T9QCO3JcJxg3lIJt7pDpMDdEfpnC9g0MoTbNUMb6TZjG7y4GQe2JzN bePiA3ZqzHzx+nZtOFb5XW2yIfgUMx33ZYB2ClA9yx/lfdP+xQGH6Ajjf776zjo+8adgC+ehcrsC ACO6VP1ZYnx0+jOP5XNCMikkTcQuSAVNs2neaRfNYSmGbgSndbgJ1QS7ff179BrL+MFUCr3VzqUt lgG+cwU0m3Rd0k+OSKCqRCnUUnDvF2j09RRGE806nFB9du0en5ZiPFrznejSmUno1N3phi2SKj0Y YFLHjGsx4p2Te59nnoYGqPRDOn6UhPeLpUeiI56HqgyTEmJQv6MUQjRUAnLsrXsqX7C0hH6yihMG 7r98QL02auvUL/xRSwJW0QSoL+94kQC5w/BGa+apWgWA2yVrE4uQ6BmL/qFPfPy+mQkxtHbNQ/rw ZPDRkd2J3XHLjJsD9/SwJWU4GwLJ/k9eZKlaeTGc+Rp8mI69M3uV9AUDsH7pH+Mf/V4JaD1j57zD FQQ3vWFJRyQV5vjwNrnZHym27AE9ZrO5SViFihpFSjavmxj7pyPCbGNu6NXCj1x1XSRPi6BWhV+5 5FHUHFX/bGSLCprjgW0QYef22mdjAg/L3eKooqV0H2UcNLsyZkTwI1Dfb7JcXa06f5+M+IeFsnNP IQm7juPWg6o89NRwZ+57Uo9ioodvujyFC+kNP04zL849mmxSVwzgItTh1Bn07Y59IZCUrQhXrbQ0 a8/Nh76OnCY674td8ztJuueLRen4xFbyN58RWnSinepOULgHt6FG1YZsgy9niFI1XOG/JkGLBJ2l n6jURrQFOWQXYQ4ko4ulECypT+TL2W2j6+YZb5V5AOiwh2eh1wf2fyWDz1RhhXEO7kUHPk/yQI1T YY7XfZ4Sq6dbFgc3A62/kIjVOu2EuFY35ghFAQYuriCym5nVaxDhSTbb9NnHRuWPzFsqe8SMdlm4 nHHHTqfd/g6fLpQqw411xIvO+41MN+9xzJLUS4FQhUUUjOMBy7i0gkcMYMBcq31kJZf+jH/M3NBf DTkNcnfxPub8JlvWSm6bJYQuaH03N3x2HvRlkWyVYY4Yl/Gf7WcV7+vXwJHSvRKIQN9Mq4iwPXBW GXkla0bg3KxA4+LE/e/xcAsRuZHRnGNedPVeKG5wop7c+ob1053nF5Mig2sHUWA/jnCWJsB6PvVC 1o3t1+TltPRI6zk1YZ6JFhEEgNO0QkbaHGboEn80danTl3yF0ejz/kBdxfbzN5vQHhOcMYviAZKm WP2+44jPRp4yCoD3TtIEJjqfTjdBp0d85mfxEVgxyPLTG3Ge3PfGPCqNg9gQEeSff7wxAt4TYSTA l7AOH1TtWX2PsvaYOuW+toUoPb6z+/Sp0vmqfaf+viR05+txz0ia8jC7bnAcH9oMMvMMiKGzu6sJ 6w9A6mvh0S4bzWqhCa5YXB24GgPXdf1sEbLu9+ji5q9AyfDY3FY1NiDnooe2jz0fiuOZ6rir6mV8 8fPVNwrvyupSZfAWE3OGzUgzEERRl3YDtImdRG+Q1o/7DSgsv6GMf7d92Nwns/i8gDblAl0CrXJ9 6Jh6nMmlb2bOYgnzvuT1JMAggbXazRLM9FTOTkLuBwhJRxf85VME+80Im41BDD+W93/85kIpel05 53GYhVL4Z08afEnaTupA7r7OTPDBAEG1ExKbZf8t5Kg4KHPwHMhhKrEZYjBey9lUD1KOKDqmaz5R 0pOrPo5Aq1taHea9EegpRY05qxZE8JkQaJpJG6TDhjkfE5KCOJ3D/kanX4chemTzssVmJ9CsV9aQ bXcL/aTVdD+NYBnLa0CsUXVhS9bkD4AwxPqqbGLYDuVP1HaxSQYluzujeN7r7UkOriQ3E0ct8JJ2 lNamGOW4Q/8WQhzz9Pce2B3A4UWEi28kYWo7SuoklxWZ8w9reQibndGZkWuSlh5bNBu0CuRbfnV7 z+B5q0SVgam0xvr8OIdP+RZw9yf9K8heNr78QUVXnKZm0SBAk9+LtFtz7l65K73cofRWLGu0HBhS lLK72HCPPiIn/OQw/OZsdNWylTtqJn7mJhfoRndh+jJNlJQBQZ+R9kKCpLs4YmlAumymqSaPC5K+ O/exFcpY+OYAy3rD2ICVSzda4DlAcknMQyPchGwJFhC/t8c81W93Vx00ofosz3ZU8N0i284UO+Xn jXFOdzbbBwxRCbfMoIRIjHJO7Ae+/qUJzpuQGvTk4LM0AY5XEb4uhE19v6gugSHiKfJ9duEIQnee amFFIfdmfcJfYqe8ylOlanafA5voV+2BuCxnO9+iSCP/dYkcnAD4BKV9833lPr2V2JQEEhVP+X0b E7tzU0WM+sEENRZp12nqAbYerQE+tb3If5KIrj3pPfxcKnFX94ZnV20NzFcLCAGxHzzPqlLvOQS1 b4sLfF66TBzqzONMNE36JH0c6ZEUC5SF0HaZBfoplxOSrJgIEm5Ly0SS5Ex9eCSS3idoBSsMgIYJ r2LkdEPrl5TV63lCuo2DOLG7+vN9d12Da/OUThtV/RdJMOdNByKRtMMmwUID2mG4BHErI4O2D8Oq l6OjQPn7i2t4t+mwIIrXSECIUn1TeIjLCedi46IZo5a4AjwV `protect end_protected

gpl-2.0

d3697f3bc00a957d86afbea35639fea8

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/xfft_v9_0/hdl/dpm_hybrid.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block K0YoK/HnGCiPh7KwW9F77PHzjFLig+WFubzflX//bISUDpowWRNhmv7R2HHuHQkCQEOkcbnrYkkj MELAYZfSPw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hQfzpgcb8za9xa62sp85jy14MJYgYOVyA5JJQYK9t1OBXmUZidB5BS6vuU/D3rpPUoKPo6UcDsYE 8fVmBZI8h4Txmrg0rkObaIQKUZ9qEgDL/6BS+PNZyEAKhB48S1/xo7M0EMoVBKXFXlIUYdVbrb1Y bF0B0feBNSRxCW7LFEg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block dlrOKrGVTq5sMike5/mV0e/KONNSJmC+a5wxfiHCYuuhWd2CfoOEu5plT6QxJA+WARje1S+3O5VF bwm0m5WT8GiwcqoBM6Ob5FVYPCJc45e9g3LmANdCszHDuORl97+gnFv1DQjf25HAatfqxEyLtkzJ Q+Gvvo27iRiDbEiNGDwtqH/4hYOinhQswWB6DY1mm4NEvmAlDkjd1ZEbGKTPW+Gtd4Yi9vWvJUmv UVlOs2V8KZi9ej3fggCGAfO8TFYRQSY4x7I1vOgMcZ4d5A1payKrTZxVtebejVCxu6rsErthHbbG YnAoJFIXf0LuRSIe+uqFwOXDYDJiItPZiMZiSw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block b89ErVy/0wJjYhymJc19eaizu9yiKH6Mb24zQC677QD4lbI0R8NWPmIbZZXGsdJ9YYkhX4rdZTZz 51B/0JZOLtFeYuwZlV8xs9nas1ybzZWaCoQdbKwlYWPSLA1dBy/LyOQq4E6CG1wW9tz//fjT9MX5 8IobUin6kWQe1/mp+U4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block AxAG3qJEeOY1dCwJttbstQbQnEbTR9vFaDx/6qX4jSZ6MqHlxC3SgXsc4c8tD4J/13YiI3Z/UpOv YIfEjbcHEZfbgYZP0WGDsx+vZjczOZpGidILa6XfUNF6gQgcYKWDKpIsAPf7pI7Mmcwi2ALGCyE6 opKUusThcfJ8ygHmyjYTtIong36lW0L7PvwYY8ZzyWRmiIdT8mH1jDG3r1qaW7ngL+CPMuGB3yJT lUIiTfAVmYoA7KS2GinpbwYsNg0JkPaXyir8ruaGsRNgvaTHcrTqBYhkQdBeuudnQdO4ToZeq8io cd3r7BdBDHVOAL3IdXZlXzIuQmFrCLJgEmjwtg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5360) `protect data_block 2rlzuo1Sb5Kh64PsSVP5vSjvnIKZbtiTQ7ZCu0SsbuS6/c8RS0+SzV15mA4++6wznY9+YyidJVXN agfeuXU9/djNow4d/wqLh99UcARifwkAmx6N0pjBfmYH67YqWrdNjJiCjHYkX0cnX9nqwDaks4Hm 6KGqpSwYvYwVaKsuoMgKZPhZABzU6tyFcUgd4P6WaWwtyxpnFUp4vlqPSdzExQRMQwbEWjBPI9z5 WqMQWYWlZKM21x84RqKHut3MXe5v8lezixKlLYK9lamvEquMqxA4dEPdAt1Q0yfxwytkFKPm1x5z 92R+hX/9/pfSTf9WMmi7mVQMi5fo1brg1s/uKSmHk4Rl0Br/x1qJvVG7ETqJbPZIvtF+hhTys0Lq CFp7J4xwOa9M1lame/PWXxlM7QX7yQDKlcBX0pWsEXXzv0BKs+Almz3/6ZjFA5s+p1OOB0AdaJpK vGi83ltjmeNs/I4UxNX714b43gOWwGVEv30a4hl2rRxh3qb0hEtKwlt5OXIKdZG8bX0iDjBkeudt ZyX0Kr/EMipzzRMFomCZ7tV7/LG8VSnCFaT+xDlXFKIlsfTyIef5gpxTXYVPsYoWrBXan2dH4d5z KwFhdbf1dqrGbuEuKuHPnRLYF6KJ8szvQ0L4IPI9qVfcs/gPXqHCiY5yCyWo1YWw4RgBuqUjMHqH 8KDBy6GoLP0HwtqjGxnx2/WdDenzl4XbtMVCsB0w6GcIkn8FP3x5PEsmpp2rJeIGyMcB4N1/JmLP XJgzJ3njS462owq6MfzDC+l//NVSrX4IKnVawHKNJUVposoX661iINLEeBWDHRUu1O51UKYo7oHL u8baajzGzgpTvmvxnNxEnU+GjhLK6ke+1tJVrzrawxl0EoMKOZShvflBPNWQhuGo80/49Z4v8EFr kNtSoUf2uanf2Gynrbi7tlcNpZgh6idOZhQALzGd3Kx9l3eutxWEIWDCnjQea8/PwOLOYW/uxLT1 gQkTYiwFs3QT3esUVhnvV+IZGF8fkTQfEwfHrx4FLXgQ5rF6FoHjln18l5dujYNFGK64jF6n/d41 2ZO4NuqaHZw957dV7lWiC9U6wg+It8eYSPvoMrJjO750tdyOTj+3OHk4bucf3aR6CRnBsYNkTNYq ZPnHc+e6rCuT/hr4htdwxmPIMCm7SpcaduN49xESNWp8soK39GzcJIVxsPQ1TV7swyYXyBYEJ/9P QQ2b749DbNL3BTllK5hM4m4GnoVWw2Y6/PsuKVNp7rgd9AeXOkpsD/94h3rJji9vVCevnDeacauj gtqLGGeFqbbOv+hYjg7KRajcp3uuyNKpBVd2wD74X5TcxOe2GY9NhtojlX5hPeSdMTe1e65iONQ3 vRPS5SRAdPMi3TvN06R3W2D3losn+JULHHQxpeyF5FpBk4QVdISJsxaRo82ZHcvBzaJuKPH3APiV dNhcGQuoCZwHFYiCUdUMMX99Tof1CKXzfKrugc0MlcyWiDM57VkMmjhmbuv1mB2PN+jwbyg3tD3v eSVTuixbI7oENv3PrcCEDVFpHtVA0pZ5ylI2PN7AYxVOZCnZt+x9PL0okR3rqvlrHAJSaW0iQ5EJ KZ1GtDavVPrIJDSIVNtGKQEmKqmndklLnlmAOMiykuY3RVHu20rIt+WDIAmXRzMi2ARK9UYREsXo tgdBiqtYYIMXM1oAx6WHymy10apBobIYvwgix8h+TcKsxtW8PGPlzLaxuC2Axv4W4yydizE6SV+e SBz0LjBLIqqBoUY2kfxBCRN+JaezFSotHT5stMZ+Sj9ztdh+ma1KI9XE15k7R4JNaaFM3q7oPweq SngMPR7/uow/Zl0xt+ZVMbngRD1E+v8yLv4rHes08kbpkgtSUQo4Bzzl3LSQi8QCkVfwfbYwHN6/ aD5aHQ8AzgFIGP5DCoJ9rNERPYuHk6/4RZdtaYPkAKBaDW1EiwFc44RbLqGG4Xa9et8ISZziPN90 ++Zjoxx19fcq7nXImx5vnJWVgVxz4fZjHPcqBDEJyamowPA5pSHLlXF9r66AgWUfVFb96pP7x+03 vY6+aJAxmBK8MnfplFJ+PjVb4kNuK2YtySykUW8M2e0dynFVNSVMwu0VH1X0oKUemGWI4Czwfbbn 8TyYFl2Oq0VNOaHSlPhvgvJVyQ4HgPx/+qfyB2DKzKr5DSosxtHmskfAGTzXm7zNeBdFsXF6egqP XJ516yLSTGjaQxWgjpc0abFRYzG8sCNaCgli9UKz2zAiziSHrrTO8MHPs/g8ue0q7lxzGZOW/9KW 5IQpXHd4K66A2CpO19PkaQSonAMo/if44Pv/9sNpMwhEUhnvH6lJQlNnPoL52c+KVn+C4iycTJpn 2DbjY2TKPtQEZtZDQ+v4dBxRbOPPs6sdT6HtErpHVSb6BUY61JV6Iy/+VEiHQOGY4CG/wqTub944 sPD2n6EkPMZWIBGvmFqXldfNDaHtJHbWc4E+cYDGSTT+xALXzUJGIgu1ZcqXlv369r0DNxY0HMcQ 7ur6sdyIM5ISPrepWqPzZAQuRZPKxiMwdE2n1HZzPo5yZuy6Nv4zZK4Gtp44GC1HgYCFxIeRyCLj K0UmnYa63KQWg+og24lAHESw11zwE3pNr1UcVVmtg489q6Tjvald/j4H1nl7l+Nz0gZWspY2/3d5 79bljC8IdYZ1Ay3WoFOdIK60DqPB5xV0Lejm00DAUFvmU6Mmb1IbgErLtvS+LYGmMLnN+h397jgx pYbYaLzmlToiN7mSBb2pkhuz2P5nrfYJZXxpyJGNvtL6ZULMGJ0GgRAdTG+435DDOVV3yNDx/RYt XgF0Ici2ru6gIhwkT5DUUsk+RiO1W4NT0DhZudXK1BNeAv9SAsdiRLO3AdiRmVT2+zefC96zGE3X OnUIDEwldvE8exncLmgnzTEbEgPi6LPWQhWjSh5CEvc/qWZ7/T2whdMhnUiDUAugBKk24mN5n0TU 4NLme0j23Nijxmuhw+WI+Ayq+7+a8qtr1C+JvE3ywPyoV8xR/uXUM6Gf5gP9bBvuojup1w61SRld ekHmXHR3l5FgYNsYwLN2v9MBFlOU/pqM7pL+mo38jRerOU/4x6x3SXci5+cn0ZMDv8OFLsoX3+kA BK0RN7TR1E8dYpP99yJdivZvyez3/0vRZtVt9l37R20vyVxr+c9MmhTv03tY9i/yza/TAGiEVjom Tw+IrocirHXy9GsBFbbv2oJCvvLZfZozeQA/VIwAVRM6C5XZqYQS/ipF+SguFMba9mDuoMjopdhh ksVjaM3ljPTi/q0FdswTXIByW3TRmjhG/6F29IjeS6cNqmrlj/LyyI7zQL0Z3ZkG9PJO2pWiW8+e a1Nh7ij4kEBfSXWlYwSSOhfTyYRDnCsi2bxCwlPYdurqeeQpDa+aEqmPK3hjHQKWD+fbBcEYTA5/ wHcYhRoNzeEa8GiIEDFIYQHVx8zW+cRI0cdrQf7AINzuOTLkwx/7F7xEFKiQQNrNPH/mk8tWfUyV MISso/IoTAi3OeO3VvSWYifulnpoYQgRZ8JAdN9knRCdwxz5bQKyLNb43+vRC2EiXJkcYpkD4VV0 WGUX+o1priqWkgywvuXbSwtmFrkBHlePD/o19HO7flhN0zrZZ6XrwrWmoYk1M2hWyb+ppsm0DkA7 wIzLyZBweXouJnLOXL4/sXrxpBGN90TPwZwQitJ4VZyxKY8iaJrNBb3K81Ygajj9xjL+uc59Wh8j caT9vHuCQf1rrExPollUkUaGCxv/lCh8Gi6grSLVrr8BnDHreUg8u/HPgbSqHMp62AsAh4Twk832 V5oLBqQO4Eeq8q8lFPd7nTLhZeCQFL1BVnDv6Shi/qzTJ+TX1NolTgOImfGxmZBAVIAmIedE47hM GxenEHkPtB1AQIjidJC+7DL+xZTMFmGcjPAdukRUMcOmCNPtMApjAVVgH9/VJ8aiawc/huYMSIkx mHK9R9ctkr+0Gw2rvfA/ioehM4hvKnf6FAJcpfDtsgE3PxB0fyqjVGGThj2S8YD+al47/ruWPBE9 w96T6VtTAl2M3Ww/Hr1cUrMDnHEWZ5JQxlye7t9aXhg8BqlEn4XLTPNMUG9K/flUaQObFv7cLKMZ icb+BSl8M3SNyYleh/SGms3vYpTCFPazr5X0nrQdkQJVnpRZxn04UkOuiq3pjMeVZvmm4U/yUBCQ hA9qm2znTxshU3woZfGQ7TJFcxB64SdqvTiW1IIyn5wBCac+ArUCwWcJLPh98WeUbZES1WdvUwc6 IjVKWF6c84YmA8IzgvDxBUL2NXp0h5PVJNxcsfEAX0Vdevwks726ujwy4+3xj8LwR1j3wC7YGQcg opcQpftBGUIWokIGuNFvpIYzLlrb7W8tZgJyuwaFz5JyaBWMHmQmoK4CKCL/kqnEdu7f6IsEE7PX NKsy9YMq7acmP4KMQtm9FS9L8d3p975QpPnyoTYmdblICSfAsT7qoyFwZSJa0ZdA+SF1zKYbzB1t O18ZCpqq0dBnsrUw5fc5EW9qnE2anCcvIAofmuQ1PtHmKRj7WS0DJ2ENGTPa1MOLj96TecwxLVoS OtR3/7mG14ypIvfj3dHsDp2lr7kOFSEzvK38r8TpA0vESohdEfv6afqj5e/1HuIy8d2p3GPfBph4 xJbafOY1uuowg7krfHHjiILU0TAFIgCgyzza17Ov0mKvln0SX2J2H2dwLhtFGlbTly9V7iuyMWyV x7IAtrj6ka/pONkMzrn3XLsvvcOBBdLzxxQmmZrkUMK8oxyrGdQzz/o2XPYHiwGXceahYOb2FpCo xn8pKbbwvikvp+DF51HS5XiNfzpX6xaeUO9s3QaBq+7tgGFH6vSO2V6hGR7BSyhT8iUwWBGeFQ+K aiNIVoam8Kh8qlZqwlQZdsecH+i9TInngguVpgBmIhpZh9fsPMW8ZtUqkJ3M1YdwAz9tCD2Y45sE m6esD+ipJL/dgTMQHySkZGmkvWjx7IpQeIjDmxF+3hOxEu9KAoWObSqlqOgOhcDg3DUJrhwVd2F2 SBzGAW9WHnAtnHWfo7DZJ2tz1rpTXQLMQmUyYbMQm8f0mnunNUrIMRvhiiqHfVtMcIbPY33+Xgh+ rEVH1IKSK1+OmPbx3giXDvXUO2xKVEjLo4Ve7DdEZD7s/dBhUb1OSamwJRWcl/z5ZEjNvDr3bEQi tH8OWyCrM9cZkosKDGAszS5fmdtBXG0tZ5KVMVhWWxajWm6VDifcgYguA17Bi4wO6lilQArU/Yt3 QD4kYC5/4IFTtXFirM0XsRwPkVRtSwgX1Cur7/tGHOOD04axrmfxLzMnqLn6eRoXyovEOxoKohhy zlsSFNSNeDwa5ID2vdfJFY1b2U5nHmJrIkotJyo3L54Q8AknSGVCO9j5cTkpdJtOMHDeeRRfemB5 OZmv/Tn4NTjkOe4gRXlf4sGFEjhqujPty6iuMFhkAFUyxicWy1jMkvFOzvptmAL+KeYrB95+RZb8 jkpN398nCoLevgkmTW/b7m/+RnbapcYjof2VeAGKo33sZrbzDAlsE5mO701s7GrOT8CjPQl+fiv8 9aKpT4pEVShWzXydeDj4D16++MIWID4kGTF28zBPXK18c9YQqXk3+Hh/uf6MWI7ibTQAr0ZxrYiR fFAZ42tv1DmsyTtRmY0jDi8EhEVvz0pspudNsi5wZxL5DhQ0afQMahbEnFBy9CE9VbKLtQPFlxUB p35SajDoHqKPs6yes7Zh6nCKx0VeTNKuC23OceIzimRKI1c3qNjQyE6m75wi/d95uprFSp+DyN8A Wvk3169jHEFjjgftmBWp1Izg4Ti7uy1/D9y0ob2R7ON9QGiD2b9weGlWvIx+sP75+lgrH2Usm3O7 M+P46LQZ+eIBhXgJZph4I9d0AWZPB6WCvCmFXHsHcyVNR8MtJvDblf8GfS0SOBUpf44yb9N521xG ofDz8s+oS8gNOusR+kxbVKiHdUtC+af6Gq8tvTFfRqYUiJSzwPJ7/HQ5W/V1NctO7A+cWozZTWdu VnxojCX8yM8kRxBckPlugNqS1c7yRcOXPVhWCqcUvMsSFuQunTKySYrBcqADSRoHCKeeC1rS70FB KtKshFl+NSamEugzNJ8Xc6lR3TUIE9xtKTbOEGtvvKaLzpOq83LhGWtcb4V8hvKFMfIyomy5bGYz rz2KjxF/3rn1tRzaAD94i1KLgZEFYlgEymD+C344MEamG61ue263j+n0BNGTU5MulNQniMAijkIM bWVBAd1Q71HOE2mjcQX1plF6Bk8nQBlJhXjKWZrT7QTjP89ilEgTLILZJtEHFNO0pU7c0YI/mDIz TDD6q+wXXz0K/jldb87+MZb/lndtgvExrttXG/NQ5BUpmPmfX1TsANEpImUgmTCUYOX5/LqI1HFm H5Zuq2VqSKdKtzQzoJAzXT/lo5wodZQvt/2LfH6vn4i1OLWcFTHoU6BsxkZrFYAHdEBysTiZQdIC izesPQQ5PKm38C6xycC9YUaRurky8kp+aOvWRcRMJzeE53y2gwhJcqcS7V9S/vjhQF2AR6WbkMIr vcPGxriX7uefSIfNpPfkiVMXdX4W1/x4q2Fg2mXuKwIm32uvgmMpvrP7vOpcP8KAvoxhy7QQTBPq qjSdmvfkJCsUhikijyP/Fnouf2tSDIY6stkmGkNyX7+QUzZFfV/xxmQRxA8cTkxEQ2kLWo/d0/c6 U23Kuw4SfwrZeI+ww87O9R39lBetP1qm/YH7bMNj+TqgVCzy+jEc2UytEiOhc0hXhYApcvP5l890 SZHCIZWfRhGbu29hH7Zuk9Kar8yAxjxj8p/SZAE5h3NwhsLnfUUOykVMaV2eypg2YeaI58rgepI2 P0K9+DdmTWSnFNnBXk1p64Kji+D1HlCnFi27EBhFySIcQmMDLHRlPd6CaC9eMh5ojru9T1td2rTY L6Dj+KSrqSAUhpZDWn6EacEljPi2+8lHPF9ObNvG+zxh+n5JwgSpTNsM4lxpq6XyxSyH4EuF6PGY bdb9tI5P63Ja8Qb2tgkm7E/kDwBT2e0qE77uUGzg9Y/nRZ7lV+ekJ5+ZK4x+mlycpmhyqyl4/E1l zFQuAP4Ttw1TbLqwKBknnkqHHejHLbrxrKVogOItnNgDPwhswsONUNO7hzzMYYXJUUynbqbNQ7N9 5ZE= `protect end_protected

gpl-2.0

3d161ccb39e967aa3a1bb2f35bd277cc

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fft/c_mux_bit_v12_0/hdl/c_mux_bit_v12_0.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block h3ETKHrWsjGzbmg6oxtLMnsg+K9TbGp0Krk5IN/TS/2TR91aTsK2/JChB9wa8eZP3QJSzF41UxHt a5JeGMIAvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block A5MxF3L77y8SaBIyqLGkTeS7GetOFp2T5HtKSKasI1NO891BBoUa74YQAHxLPoYXCiRHCOeLl82I CPufCEwkFvm0Eo4xuZHqEg2O67DflEipUlH05uNxjzz3q+N/sE9YtML3mtcDV/0W/VqbZGXLu22B 5Nv1a6D998lFw5QKGXM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Q3cfsppP5jEvD1ylOoHHJfHkwd0nPmyaDJAPg7IPVfacGSp2wcAfsMeTfofpXwd7E5FpWiRhTudn Z0aZnoHGv9kWzuUc93XQr9rIsvApcl8o9PIYaN/A8XxziuPSTnENyr8tDX0UlUCH2p/vFFbXAcMx i1ruX7xkfgsSGhBHqjV++o4cZFjECkyfOk6tBSiUX5zif5AP+IyfmV0msqP+XxULsDD72oVYIVi7 bsC2ULaRvkPPDWhUSFY5TmrcnRFZlaLZOLBvuD07XtkUvyX64lWZH0QHVh1Ot66PU9Qejlb1c71x oUHPlYzlwalqCS+mgb8WUx5RG4hXbNbJZHzllg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rWxkGub7ndtUEUp0ta3P/fKpo2q/VhbA7yeLIbfbGlcJGWp1+OSN2zfYr0mT1hU9eKToiWNwndFv 5yXBwmp+XWp1Kbt6EpNW6Nm1cp5tmm2llMpwhQ6Vg1Dsmo01JSXVMlvqnEclkVC6Bb+upuGKtFvh ObXhN+6bFwIjOBcWLZU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block bztcNs1EYgKMz4dpOC/ZcP0e2Ol44psVkkRQa+i/v0I3DrFeUQPfzECXnCYb1TPqJHfyZsZ21RA4 yxp3F1YJy/ZEiCi7G2Hq4LmU3Vi7jketdhchFbhQp0oz0loyE+2uSGcC5j/vk5qzaI3UnUDZx9aV eSA4TpsJJoC2yPFvXMkOraSFAaDLgnV4H85D2yg8lHfwxtYMzijdokSQ+uqPOYoLvxUs/6G1GtFA 3lr3C9hQczT/+XweZgCcarFAOYf6ot75iRG+aVrhjJd88OIZPbyvrnLd/Cbd2Tf0x9g4BAQeFnon C0IQ/W0uxAI+L8m/fnGiXxWm85Smo8l5IdJuog== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6752) `protect data_block /n2K3olwDR5kSgMgwpIpTp/4FNwVybwKwczCvuVSrY4VTK+HZ8muWju/cupgFYjJQgKKlsVV4kBd 7lzAXHrHdpld83BDMYgFMjw7tmdxnhRRmLNhXJp/N87Fw+TZZc/OQYDW9oAzoe+3FDSQ62321tbo Qdsj9ByO1i4bY/KmVYa5tPm/TQWDMVgshjQe2LamRMyyQba0yo8+idH8oTKRkZR65TUK7jVHYeMH 7xP+TUtcje7DuGI9jCWkwErrk4S8aw71f92zsO9wbZ7D/LIZdaQeBed6Jp/OYDOAqyIWCqrJ4YtA uBSrQowZl1AaXmqKVQGZ2ng43yiwiq90zaiir6RqN2cqSNCn9eDVesQaTNKm6LQrMad5/qHzQYi3 vbIOgnKuDVD2qbPuMFRoZCBSMiS/Ju40dvZXmw9m1pHz3CQMrGdLaBmLgX/OanMy/Qr81jTQ4Yzj ebyOrFHNKy1Uv8V4t8ioQ0oALItIaIH9URVoh4v9uFKxkappARkrkHvfpmt3srUv0yR9+4mEsC7w niiSd86hq5FpcHA5pls1XllFXwwBHP8FgciSdR2JXb42yJtDrLsAMbzkooxcovROQUpw7GAbVQRx q3lAFrQzLT7zRoCuGrmyPlSUqbLzC6pGBCSV1qFLlOaaKAoZLNC1+3L3ovmUm4Od2akOr01Tiis5 JMaQ9/gVUKuWC9MxheoZmQnVfgRbTqSofUDV0kZl8CLDDa0S/TYNF0bWlIsJvWr33CcnQ2E2UYRE zzPWMIRtSmunelBbpCWjfp7AiIANNEC810616wyEI15SwryvnjTO7PrPjcxt+HgG/iXbWPzLSNVa tBXPYe5LplMjKIzBxC1vVL0FvVNWUwiaWjLyyD25K4jQHNYhA2nkXzcfJ5eyGpfKxk7GxKfR6RFu G6txSBjz11mKgRcIHSxRR6AV+sgCB5ZS4m8bwTK8UNkrucqocj3BEG1Ry0+8OB2n5Z+IlO6AFUGN YchDglUb9nWv49DIjLKP5i5zo1fRMsKSjLAan2CxfjvA/pMqTJI+1MRPD4nOodQkiucaLtnyNEx+ 6U74RH0HePBciGTzJtxkzrNgF9vPsWjM6ZqAk15yWNyaqgZ3yj0bOdHWRRJLZtYVNs7P3BuIXMsZ 4A9wAQZn58JS/4gONVR/NK6Ukrh8cJYSsCToDSueDIMvjDFw+TxSaueKDPMrOa/8eEc/Y7iZvbBQ mZNv7/Ve1s5PGAlikUbXx/N5JD5mLJnuekZOGQ/pLaM3Ag6xKpOWpM/rMa/XNTfwfmq+gfzbLrIr ayHH3z3JQtFFBCueTxxk32Bc8Y9c0qcmMl01lFJrn6d4ICRTd46wmWum8HUBBzkVyp22jjp3y6J5 DFBBxcoAaIucIMoNE+w5Ebi8Zd99t5Ovmy+uiqbnGcfssYd2Z9lRx+IOXxOtZ/Ms/QvNz9Vo0jGL unnMJUViRqUimZIPC4gHF+Xl2oF44TrvdGQFI59eYIxQ4L4DH+6k5hjcu7UIoIA1H8z7lZaECC9a Zg+pomVRfvrMSsj+yBFppZ3N6qNWRdMLczSOwiVil67bMn/IWcWhPgkcW5hDt0aVUaJHcudb6SrC nbAlMWs4MEQMhHhcTFYrC5k/faUfY7279XV1vkFwrCzMCp5GykMoTHS3ZtrO6G0TYh3fA0lRly9y MOWZ1fqdUMt5j7f7MKBbN6hM8GZDbatZ2e3yrw1c0Gbi+2tOGMS+EC4/EEqcHPaLrxZI1diFipqB yZcIyi9Rfd8KvqQXRXyExXv9ufQu+QBqIQ+FbFEz0SYCQpcQ5EVZ5kcIzqrkaZ5vVBEzZCVLCp3U QCoMng26HHUEKZzAEAkWGVoA7SpHZylXTDs34sjRE/LOdjrv+9ndk7OFZ6gWTGH/j9ooyb3we5PU 0mK4pe9SprraLGwBLJ25x1hMRyPJ4InxhCqGhljCTYmkedo8qbkGUmM/wlGJe2ub21NVeGQrE+q+ MFvDmuBCsReYfD+A9GffLiuPT/2iyrxETPx76gDWOuWhmCr58WMSSRe6Vy7ybJ/XFeWMgG9q7Qkp PB742rVN5RjFD+96iXAj5WfAr6NHnF4gsj0KpkC97aBbwjqyhCxFO/nQwl1vAj8zWMQeC11vVZ/y Hsqas4fKlgpTbFOJJ/6LAIt20qI4cXy1EUQ7nlllnRcHO1q0csmPwlYEgvnnEXtcQfkcd1ihlGod xixdFTmMo+j6EcpnsR//hFilKNbscPk7Y5p90RvevyHOCzFWi/BLq18ByDqUhQEEaVv4D6Cd21Hi 34uHt1z4+rcvQWJUKfm/MWOGsnAgUTj+AKjMD7d1VUWxz4G7JOFsWs/1eSsepqYmqn5qbwl9zuEL fjMRiXCyZqZw8oKUu8lSiRYRp+2LCrPOChAvf91b/BHjFjJI1Q9BQfkSxL/30bkkQGIxzCmNuq4w dO4hu9+PsBq6nV7laqqoevGzYQ7NFTRjPeGpptN8IH+Kh4NYvzf47wg9ycofSi4qmdG7s2HDveMr hU2gxRTdU4xZjwA0DK3r+QzFW9PY6epXfntBt5e2ZEcZh2GCSMh6xWoGMPZU9RGh70UKcI+naDNG e2yjYHUA8JltSJYZcijxgOiaLz5dmrqgW/uwIjHtL6AgI2bUvwHKUS0YWlXbILbzovUGXCCexbR6 WFpHRJmxvsBTEJY/RjYaeIPFOk2bPwMvz5NAjxr0QV68NorxwOCJGauJpnfsQg5fTlVRiNjcDjxh lFat3BvldU3AJSIaSfBlgwdsBNiobeg7x7OGoTn8I2Jc4e7jOaivyel2Ff4BKtGwc1QD6jfhGl+u 9i87018SIx7sU4DtdIki6DBAntMLpkBuFiZzLGtoTZp9I/AeKKL64yvZBHJHYv1I9+aabLjFwp4A Uq3jTYmFn2eu77/7RdDodsDz85+/dmTpu3WmH7QRJ5WhL2Iw+Em7LVtqmeZN25atOQpwA2lJJGvo zNeOo6NL2RkUwnOiiGEXM6xZ4k0XPQ5EqPrCj9HZeNb+ifMZoRdINLTLFJtmhGzIcOFUtUJIe4dR EXsanXwPLsC8bl+XJWG/IClZaVsRxX0VJdrqzb8UJosfUbsNCiN8NA5VRvn8BJ9NiuSI/EpwdMIS nzz9aICUUJ52XSFKBQ+a6u4A20DMcd5VNzoVcdfZbcweECXf/+hEWPkPxV3KPMalITXiQbNwPFDg 4rTBG0EI+0b4Chs8+xPagFETaB+iJwMhqMXL/DCa2zB6AgW8pVkzObsFKjLbgjF39o8SQxUXMsQ2 HZfPFlX3QEGuF/9R8ja28bgh7NXZjbndIlDygw+u6bzKrjokZCFDmRqlrzKPHaUJ2JJ1AXwODgZY cd3R6Jpkif46JIgKfO9Up/zX1l34rDoonEthq8Saghq0TkgEPoZNm+OSRZjaA09P8lUU9HzMMJp0 /U0Sf5oJEbOtKQNiU6jDTzglZPO5Kc8w7sN1F2GdTawLyaEkJuFR00vuS3334mja8Y+/P3OESefe zrpevMy7VH0ZBW4hPdCulxsoFd94StTJybQhA+6SpgKdG4u3WV1XunWR4xprAsx3tAG24NILdPb8 TJqEoUSSAEF70ZBoK9vFlf2/aPeQxjjt5zKv2uz1COHTYONQpH4hSUk5XcfI9tvgDHt72lFJABj9 87lkWrweit6i0xHN3D0FP8Q1jsKkUUt+SgRDINxO8/jhe/J6CKzym/GPzZqPu+x8sGr1xacXjm+z DtSiztSiGWOlESx94CIJI/0LI9QxL+JZlbZWB/RvLnq9rqE05gAERCGQ7wh/tiDL/GhDTl/nu3RI CRSxWDcqWXzHD/J+EEhYh3gJ+mo8g1hNlTwFuPx87gbzKisTZA5jthVBwLI56YkewC1VDBohWt9W hed79b29opr1VFAKE73OibhCaPc2YKZP44JxRcKA2Rpt/viGMas37dKd6QSaOiYsYyHxQ2aMEw8F sZy01TlbhPKxTtPYVMq3ct1GfujJlLAsqIjZlkSbYbvmFCxudMKarwecaCf9sE1LnVjRmnhCw9BY Uw2axRaTVZsl33Kr0Qt8IvkIkhecYeW7pNINWRl3TrtysFMiY6P0QBZFoxcSbBHR2svhrrbZARzN k9Kv/GTul23OCcV4mUbFCUuzcIVGhXvi8CoF+PzHMzhJSsp7l8L1f7eKWsE260G3Vp8kfQrUsYW3 43gslO7iDXddFsRNKke9JxsN+k12+REJKiRBEM9PiEB+1VeOBGrM62nS9As8LkOLmkuKlB1eCs8p 1DsYHFM5YPwg2mPfVFhVp3Bo7scbj99YZICl4O/v/iT8jzAFLHLYjdj0SNqwJiivX8bOufIGunHc mRz3UVFTP7Fcy1cSxPfzJJd6R2a3Ns7eOVA9+kFgzW+RQC3O1ukz7JnAWMj/RqSK9TyAggU5uK3m d2vnuGhJGa/r+PZsq5rbQ4ZfuI3ioPN/TM/aywZJjrbIBpEWY3kyOj7eHBC/2vOVlypOJa7T1et2 gG8nmzLTZ9d9T8inAkEqZ+AQaFyS+WRTVzm82+hWGTYrPXxfQSh7gSl284mGOwBso93ON+aYDAZc siISYZWkKZbt6X+zD8vlzpxnaxZNz4f4h4IVgdYVA2ObDttBtzpXx1QuGrmVEsd5IPrbkl7IDj8m sNM5POAErfE6w9LmZetFQkAvv8kHYXW1j0GLa+cs9SzFropsKxFHsd621VlkfwWaA30iIU9n4S2X /97Qizk4mAE+Ys5crxKijbo3qgcqegx+ppBJXV6Af7uuV4GIvN3tZOswdxqiiVwslXgEFpPa8rID kpryhf0UhGUxaejAvrYFKmqSSqHZDTFp6l5GrPAYzkKpm3cvTxEz6xA3Dz/oT0kZIMh+SlFDFYVb HBcI+D4vt8hxp8lMh33DaSBBMoHcYSsOhPu9ey3cbqw2AaO5GiPWLScnUgerCIzGRIb9pkxrGFfP 8Fx2Qq9xdMLNFOdlfsl8urIAesa7g0wGAPQxIQXl6HFVaf0tgrL9808F1AncMYKzUlR0K1akziZy ZlEXEph3LZNsCBEZXFnuwCF8YxolFl6Qkb8Lv4GQIefZSOoeHMNM9+JeK4ulRQNFtfPZTeydKft8 P5M994TSrgljvcHvNmmllqdLEorJNOF+Egu4BSrUo7t/kcz+RVW2cp9U8anvss/lrHgyeI84f1W/ b6aQEnc7wthkvho8uhli9kuHQssYdhqf5aZiajXVjEa+GzXBEX5NF8QXw9uAwz/yqwerP9/RxJWY S1kMGeLX0STQB0w6BKRoYcZyAaTzspEEeYOl/D6n0noGDDlRYyTdqslsNEyFCdwdiMRpf4gKleG1 lj2UE5XherDhkoTdm9Orjkn3UzjGH4T406h7M5O1ru4n5em6vYxspykdr9pokFOuC/fYRcnyBatd a8OQFwMsnFAYHLHFbdhoeUS/lXD4fpHA8Vp37vN34SH2LzVj4yzz/1eoyCSC5pI16wpY+Cd4vO5t RafbWfKJSpuTENZFZBASB0LfGRXupCRrvOeCvBgHGsVH1mMPBQXx3kXBo0oCnMD4KIWsuvYkOkXv 3sEUBK0XzwLr6LYKKoEYl/A27YT7mlPYvYnZkQSihNEFzPxA3X9fG2Tzp3EG7G4r1IVuHLsDa6GK 883wDG4FDr8nWUWpU0Ye/4sOauRtDl+fNA26QMVilrRm58QaQMJD+5hQaJkXSKsZf0pCcmzuP2py 13O6IaKQttQ6HBtThDRfp3Q89OgyVTwlW8VfbBTOO2AGsaRL388XAlz51JfIIYGFQTldZ8CC/KA6 w+wp8bQ6Xe7AjNzaEDdtx7VwP4+FCnSfj4Apzo5V5+hsxjeJDbmYp7sEYlIUOsqPstpTFpoedzyN WlykDe4gRK0wbKYYk3OOVjZEeJL+ShN3yzNfL8T4ESF40bm3s/ElE7PDtqr6LVXrDL4V7M0i9Ett bmLAk6yDs0xtxctpthy/UZ/S2gcHJW6XpJiA+pM6GAqpV2B/JQlup0ChHsCOAF8+stClRmYc2HF1 x6InSBm6LKvQ2Nqc9SCaLuGqDADHFN8Uzs94av+tBBuVqxQyoG4sk1u5Bm0HZmi3lh4z8/GHnr0x ZmmPBvzFh44pY7FA0K4P7PIXY9tuKhGlSK6TRanTrz6r3A7mz5b+o99KKMHaCPxcIZqrVLIqim3V mUYo+CeaOygp3UxYtTJgrsXmeNtGd2oOefGd3R+ucTqF0UzunB2c3+4GO/GohMRgR91hha5X6rCm 4ssMzJLXG8NFZp4LlM3W+lqaVhOH45GuWKyBunaqet7f0RRV3lP5kP3BxblZCZ73a6pCYp1I5G3A Xr4n3fzoWObJUWVr7MdVTJFlUW974TdtIYE3nVZdu8vGnZVHGiJ/q6qWcZjYq2ZkP3pEWUMcQx9S KffTMqLvuN4z/5fImYUthqrEcTh6lGYLFsTXeZRQAF5cGv8eJZpXcw5wzjpiqYSBZacoObj8u1QF bUl5LBrJvlrjFpdnctPJkwW7azVhN7OAkR9OeWWSHmBcH0C96HxNSTprDxf3CnorEw3cvdpA5H83 xQayFcCrMW48fi+grPnUhYy88SrFMNY1czmXAvgN6Q79LgEAQ+UDyRGuHpbeyjWaOJTtaM593DKi Nip+ks31YktSQMduG4r3OyLPR0iiGlng0SklWPR6TxHEq7nZyHUKUYpscbjlHVVdJAd1Xv1pKVOS 3R4d0CODHMGQEzk0mk4sMNqGAdlhZys+NwfXsuETCjRO2nlMR7nF2XkxuAiStLz6aEPcQTGLtbmK WFIZ3IArqJWpv3jBmz4jmPKRCrDflz+FeFhpNRHF7c0aGsgeZ+baWFOV86G0KCMmKXUU/lJEQP0P mz/kNZekbwsUlX5UQCxVSJRljxfgJ5ExkLtXx8ekWXa5Rso+9O2rT6Af9Kls8bbElhQM9O793Kh0 ++ZM2RFi5IedXPT8gFMZBHLY3OCijqqDGYrtBhaRU00j+cQi2za26PFpsF/bZ8XCOnT76QarJTio WSXbgct0Frjv7zDWXkljIJNZyXMrN0Aec1u5luGWFzc3j9kG4+OGYvZGhQeV2Q0UBPZZs3o5EK+y xdhCeGmS9n0NJ9ZMQjf1QPFiReNR0XN8LQBMEiJMSEGv3XSQaE+8I3fgwfGBkWBor8qOmTzfkbqJ 9Sual9CWDo4yFsBZWVsCUvS0Rdy8v+K04Uns7R13NBkLX223hv7fl9UZ6zF8f7OZED1PplcpB4db x2C8KdnjL69d8Y8npKcjo8e/S5nJuYMDl/lZknEinQnOA9f7mroQ7ly3+iO3cWzJzS1clBMsPcKU 6BfvMyxqvkRTuQuNPXEgfuiZSPYAE2hNHPZVr3Wg47374Ahe0ttWUgnNbuUxetBMQD5MgJ4mXbwL qqFCFUhaVp5NX73BImaLgX46YLcMr8OyAxzgmeIyaM3DmE2fu3wOg4/Q2E4vzG9ndZJpFruyzEc9 NN6uVVf1RtfKrMLiSz9olRqUKav79wBa5gF6/Sh+dZI2ZKg1Mjz2VcivvufpXYnxsJFNXHg8ePv5 hHM4ejzywIKlt7A3nloNAcFwSbTQtzI0xJtNt1Kg3KvC32pz/BaTaEdiB8/GND8c+BQUudhXNEQB rUrpeuYaKNWLcQMGEBs4CcmlznK+4hBrlcs55teAPpQGTlsIAgPgNGxD0K8WVN0W8a3JrH2L+kDJ LOJ7VM9vw1b8NeIBlSWj43kk12ULezAba8s1L9vAOaYhOnn/jcKxOC3RCO/JDnwKoD7sdeeqYhj6 71pCtJQKEgYFVoy8vQ5akDj3KQdFblB3vQcE6msKu8+CE8KG9Y94nYfnrCv9kVDzubo+O84C8nAl g6N0N11n/xORqQrW08rZ/GlQ9xddYhB64/LyZ4MOtFoW6myhLQ0R9Q2cl5SIsxKk9Qlz3yRTIvCG 3fY/sgx61COImxalq0mRz9pAUJABVHG1099eVsElGQ8AXh7EcuEd3g7rqdy70D/JlmEyxze5oAMH +DznT16dxHdoXzynCj4F6KLVj8qipBD01O/tAPLeo27Bxci9IM5uSgzLqFDqGHudMcLh+Mx/ga2p EAYrhOkMW8DYtByvnRY6w+3AJoXYSJetSx1TRYQk0iUtM6dXhtSJXZ2JhsgXh00Ek0eh6sIgOClH fffub/UIrFs9rZMzFMgrSNn7qYAuR+4BoQvfwFAXChXG8BWxi0PL9Iq/DikA/mORfVq6w5yOkXQS Pa2pE2ukLL06l/OQZ0OI/F9nQJcUFOzDDfhRHlieFASPI14WYUQ6x4jqt6hEkS8aZEjIcGH/ZVht T1//KeeuKKBsYOa1pgpWxtx8ViiBDC6uboy5PaKgyuyrCeRG2hHN1zg60cchivZQ8IyqVDJazPad 891k/WJCQALUUE+yhWJzk8appdNjMAzgAa6PGz2WC354yUBLZuiYKPbt+nEZyt44SXK9e3Khy9zl 33v3JJB3l8TlbD5BTaS1PoO+kHUOStCHg7DE+M2/ffdNfm2ONuGMkM+Qe7N5cZn8jELlQpyjM2cY ljalnhj+Y7M6l3uAqySFxvVX96we8GB9pf5Jm6xcFPQY8HGSOVuKPOplBR+p3fvhIqjV49fXgoin MFg6g1EdDs79xVaJxZn8R7s6/Bq1pZozagxj2awIalXgKJwk/pHCIY20sRrJcod+/P4TKTkqMPAC +CfHNgF1RnDJJqgUxJ07y8d8qqyPEeKUq2LIyxcrIEHTCq+n1CU90EGxFtPDbca8t+hc181emurV /bJ07IFz/DcYD7lnpEBYsfZfqrNos71WVLg/cXNCv9tW3NcddsLCLNr8y32FsXvTx/WBGycYcRQO R3K9LZJFjKYw2knLXzWwkydzxWBtSI1W0VySCRxPKY4WJ9eJO3QYUzyJHx0Nt8yVg6OJVvjutsh0 ks0dFREbMXgV1nY0VxzVdoLr7U5CanrJ0aEslQLfFzkzbe9brMXSpvj++qoTRDOyACLdEllVYR4d RoauPbeq/Yc+nOtt8hHMAHV2pQHsKO9bVXQ= `protect end_protected

gpl-2.0

e57ffb1bbd343c25ecd7d66d5d1fbff3

amerryfellow/dlx

basics/iram.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use std.textio.all; use ieee.std_logic_textio.all; -- Instruction memory for DLX -- Memory filled by a process which reads from a file -- file name is "test.asm.mem" entity IRAM is generic ( RAM_DEPTH : integer := 48; I_SIZE : integer := 32 ); port ( Rst : in std_logic; Addr : in std_logic_vector(I_SIZE - 1 downto 0); Dout : out std_logic_vector(I_SIZE - 1 downto 0) ); end IRAM; architecture IRam_Bhe of IRAM is type RAMtype is array (0 to RAM_DEPTH - 1) of integer;-- std_logic_vector(I_SIZE - 1 downto 0); signal IRAM_mem : RAMtype; begin -- IRam_Bhe Dout <= conv_std_logic_vector(IRAM_mem(conv_integer(unsigned(Addr))),I_SIZE); -- purpose: This process is in charge of filling the Instruction RAM with the firmware -- type : combinational -- inputs : Rst -- outputs: IRAM_mem FILL_MEM_P: process (Rst) file mem_fp: text; variable file_line : line; variable index : integer := 0; variable tmp_data_u : std_logic_vector(I_SIZE-1 downto 0); begin -- process FILL_MEM_P if (Rst = '0') then file_open(mem_fp,"test.asm.mem",READ_MODE); while (not endfile(mem_fp)) loop readline(mem_fp,file_line); hread(file_line,tmp_data_u); IRAM_mem(index) <= conv_integer(unsigned(tmp_data_u)); index := index + 1; end loop; end if; end process FILL_MEM_P; end IRam_Bhe;

gpl-3.0

a67bb4a838f4a912269ce0fd8ddcf5cb

UVVM/UVVM_All

bitvis_vip_spec_cov/demo/basic_usage/uart_vvc_th.vhd

--================================================================================================================================ -- Copyright 2020 Bitvis -- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. -- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT. -- -- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on -- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and limitations under the License. --================================================================================================================================ -- Note : Any functionality not explicitly described in the documentation is subject to change at any time ---------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library uvvm_vvc_framework; library bitvis_vip_sbi; library bitvis_vip_uart; library bitvis_uart; -- Test harness entity entity uart_vvc_th is end entity; -- Test harness architecture architecture struct of uart_vvc_th is -- DSP interface and general control signals signal clk : std_logic := '0'; signal arst : std_logic := '0'; -- SBI VVC signals signal cs : std_logic; signal addr : unsigned(2 downto 0); signal wr : std_logic; signal rd : std_logic; signal wdata : std_logic_vector(7 downto 0); signal rdata : std_logic_vector(7 downto 0); signal ready : std_logic; -- UART VVC signals signal uart_vvc_rx : std_logic := '1'; signal uart_vvc_tx : std_logic := '1'; constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz begin ----------------------------------------------------------------------------- -- Instantiate the concurrent procedure that initializes UVVM ----------------------------------------------------------------------------- i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine; ----------------------------------------------------------------------------- -- Instantiate DUT ----------------------------------------------------------------------------- i_uart: entity bitvis_uart.uart port map ( -- DSP interface and general control signals clk => clk, arst => arst, -- CPU interface cs => cs, addr => addr, wr => wr, rd => rd, wdata => wdata, rdata => rdata, -- UART signals rx_a => uart_vvc_tx, tx => uart_vvc_rx ); ----------------------------------------------------------------------------- -- SBI VVC ----------------------------------------------------------------------------- i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc generic map( GC_ADDR_WIDTH => 3, GC_DATA_WIDTH => 8, GC_INSTANCE_IDX => 1 ) port map( clk => clk, sbi_vvc_master_if.cs => cs, sbi_vvc_master_if.rena => rd, sbi_vvc_master_if.wena => wr, sbi_vvc_master_if.addr => addr, sbi_vvc_master_if.wdata => wdata, sbi_vvc_master_if.ready => ready, sbi_vvc_master_if.rdata => rdata ); ----------------------------------------------------------------------------- -- UART VVC ----------------------------------------------------------------------------- i1_uart_vvc: entity bitvis_vip_uart.uart_vvc generic map( GC_INSTANCE_IDX => 1 ) port map( uart_vvc_rx => uart_vvc_rx, uart_vvc_tx => uart_vvc_tx ); -- Static '1' ready signal for the SBI VVC ready <= '1'; -- Toggle the reset after 5 clock periods p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD; ----------------------------------------------------------------------------- -- Clock process ----------------------------------------------------------------------------- p_clk: process begin clk <= '0', '1' after C_CLK_PERIOD / 2; wait for C_CLK_PERIOD; end process; end struct;

mit

d052dbb695ab0cee4cded615898ab172

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/multi_fft/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_pkg.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block caQ4kDNpC+yRhd9rT8TQRjEh5dHwq37lgHnP3RI5sQRwfA7zsWXwbZRhGD9ikfspHeHU7ayi3OmU WfEoUTW8pw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block VFnFlmJ3J1D3IRh9aa3aLQlPXF5So/7159XiX4axP65bRTF088ez5OE0uWO8ayvK4YW3ZqYiTOOw 6p9P2epqNjkH/N8i8ZN5SsgJ0WT/dq56xwITEDoGQp6E8y1M9iB5e3Zs60VN8QiK3xTd239Kb2Is hT+s2ECmzEqJuVm3TI8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 24B4SGNCPgvOzh0vhtLN5279M65nzAa+XDLRI8Cw2pv0wf4YoOAqzpljAP3KvdJbt7+u5dUe+Abk 0bo9eO3SfhQi0EmJmr35x3y9MUFrD6V0qKHNSlcfavPNdn59fAyIql3Drt/x+RVhVZWrvhXBdq95 /5O1Yh2EeLrqlMpZtUAX3NuKrFlVe0pq950XXav0uroscTnf4/E8Loc8mG6O1sYv3UsREH32oL5E V2Yt408Bk3rr0M8fm1mtKwXy/yHscGX0bfEtFlw2yBf/V2lqnPdBkOIdRFkZ+hc4vmgrL3zC+u3c FSfumsObF4ymosR166ClBdZcC4XDGZtq5xGaNw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Ovx259cNDtBFa/oJJBICxm0yvz+h/4r7qzgrTH4KP8268kcBQi/sVCMnbjohNqICo+/7l8gEaAFO fqml5lkEdgGR/HZ3l3n9Ome0tTbBZiNnyAZ8QsE5/wugnKRozagtWPFRBwBNPboFN5JFDfQCNnW9 DNOUg+hIXZ6UYpUjvT8= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block K/IQQ0giJwfKqgjeL4+9+HSBTNKM2ovuq6Z+1C9A+q3EeDaIdaKKu/T+ZpCeDPYUyuKubgaG1HFN MVGYVReTc8/zcsCueJF4SCCSjvLrqJpGqI+R1WxFRfqpheXCnilqSVpW+QXRhAznH/pS4qYWp6Br JkX58ivBK7d0+qWjdNaVIgFAPQwa+zBDnB1rFqFki0yW8C9cHai+7CQXpP437jSGbX4UaE7vxDc8 7LtIslDy9Xexh+dRqaSdV+vbdqT0/gzea5XE+qxW4urG1TbURNc1dsqq819daBkpNlzlbTWrQi4E NCnk/sVRC2oftsggT1HR7Wow02cXwEWoKGzwtA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12224) `protect data_block D8z/iPofreP1HyZNSgeQCyLknHrsGZVfg0k99mSqC7j4JxqgvBrRci0jpFYE5wv1oqRqAYheZuwb bOi9B12CLlfPXuU7zXt7eiEw640+56cqFI9wut9XOMs/vuwRLNJKAyEpGlaycjPhgGfBHR78sYZg smSp2EPc5PIgT5c/PLifGilSJ4g3jcsPhdgOhZWdKnz9gU75rIBuqhjwO4P9ejGriz3B2/MYRv/C 7NrCkQWG5ygzBc7ofO0MERZP2kgB+Gzkxy51M1XsXJCBdVL4afrJOGAGp2Wt2Mhvt+WbX4Z+lBsk rv3+y4MVnXPNSSBExdYQE+trALLK6zFcoF710JjD273HCo5a7hbonrOU7k9ln/LLdwAZPSsiXqGS 1kiO1yYtymKhh4uHPGsXiqVqRCCaL7lZYJW/iRZ7PJlIImJSoM0BZVVbdJwTdtIT+Xs6w5xu62Az O7+lN8VnidNspmeiMnlGJ3oJc7XT37w38L1NNrGiQ2vMGewpjBFcv59lFhbmIyWV7dNo1s70MdkX 79oaSSYpVorGvrGyMUv2F6be7Nz5QhbeIRDaO8IOTJQwbpPFjgaLChfGruFfDZSS4a5Zk6yzyDoK Hn/bbo+Tp8SkdLR0c3TKb+h2CYGQ4o561AuTDXrfwSgwvP/FEDiipGiy0ecC5ZHW7x+xyjUBUuok CXch73tQAd0djnMRVJL3q4RwSoLs84l3jexicgXtyEiGvuvjplO+tGgimUeUaC+Yp8w6QgzKspHV jHnZRNiDcmhjDRN4FKeHzTnhkiyGaAdNN0K96YT5QozsHAvhDIZuk6g0rKsm3FRDqnl8mUow36dm 4+iahHUbjwOcFVd5Ef9RuEoNth60SAT93GHpTi78T+oYZH05yTRzeYlEu3wXyrOVwhAIMyrssETK pN5JmEWTp0n9FJQja3LNBrDUn18M+Oyg6ag4R9gMFMaguxaI5ZQd0ZMQLAoXwiniEfRSOwXKQWky R8blj1WKxUSyt/H2B1NOfgUCJchv1AY/4XNF0p8yCQgD9tK4ZC4uSnKzZit5o0ykc5++NZrpptSO Ks85cLWvwmYDuf0+EaPU15NiIiRq2j0WUn2diULLk7TGklqNwYPEH1sFpm0PCIo0GovgfGil1Y0E 5KQUtABbS0ednB25ZjiYAaS8Wd1u/6ADPs2hGzT455xOUwsgAV1L6UrelERD5SEvCUNeFjvZEwbe a/5TmmJ652tRfSwPLh4r1IaDjxRoB34y7zwLq7olRHfUuhGRrCCClvb6RUPkjIgi2GhYZsxJYuIH vbhZ/8sjAR4TY+yCJcfBotsDaxANdjChO70gncuwyaSvXSN8RPmhqsJY1b7Num7LeiEXqyBlVcnI sa8w8q74h7JhCjvPUUO+pvk13Bvwhuf/RgyEIQ4PEhE81bYgaiPu9OS/bMtxeKuWNlsGGqBGI0dZ wb9lsxANHhFR/jNHC+9IiMICov4NMj2dyulDP6TXuZNp0tX4Aq+Nl+E5cBK/kL2mibu8eKKldiSg 6OuEipcAyuw6Tlnb8EEnm3hLlI+ylrZLIw0p58h48A+SNuvDzJaVYY6wtau5QFfWCEo6ZMtQVMGq /RYdzsTPmXC6bhs0ccX9vMpqyNAWsPedmcSlCMb9ceKeTT/rdNnuy9/A0p9jQqz2pwo9mPmVGmvN UY1X6psi33uMGbWplOoSdn9zGuKzAhpKySG1AhasXHajc8yGVECqVC01LG1RGw/rSuh4FZJJhnzp XraH+PJQIexvXAIUd5nLeltcou69QtAoURm4aqNA7TWXQrMzpBgBF08BmTrXS2Edf7lk4XME19hm P1gfEE4cnHNjfITE6kcoxRIhZ7FOxVsS6H5jGmG8Y/hVy152cpRHaXaU7gqjwblzmhuc7TH9AxTk CFpOkxhAoBUkIT/sw0r7XykyvXWcghyKEmEfvA2gIjdFN1+PcGy8NP/9HFyJQFpjA88/6nijAq4Y IyQGKAV5crUQBnEKik0A2Qo1GnsByDwV60jRZ3ZJle65ItRbIH00G+D3mEllKramr6Wgc/Qsqd8d AdOwQkoIzGbnwnSywgB1jKhmb2sCipIZO66dl7Vlse7qoI/DS7apAF8qr0X1zYtDSn2wP6QIwIie Fo+ogiPoenJx61SEcT3MsNNhe4bzJGrw4Q8q+Nc4v5ErKgocd+8CBm7t/aIBAmKw1AoHRa1q27vS LZYi0QMotutUhUSxPb13fxql7IcDHGYr4KYDL1/AQynx79AC2XbojwoE++1vzpAVL2Sdg1m/Urji BcldVuINTvjvTgprhRXpip3h11XwgcF4m7JORlmEE/xSYRNMIbhC6yktDScWSyfPlUYxlklUDxty pjFO/jyljDhHF7oONAVrS8kApnlSKGpdHUortm/V6o9m3oHM/+K1JvKt98nFTm8dEwxMnri2l/J7 qswVPl/GOCD0OfAOZJJ2BIfiHA0D2wdUAUmjWy1JoxPmhdqlJVHGF8dlFxaFPK6TTshpT8VauS3j GXZsHlCFmgS3uAw/czXvi7PRngtw4WVWfHaiqVt4gG2V2iyb361vHjVRbrZefeRztzBNVrb2Rxy2 gGhpuu78wMEDnTD4G98U8+wecWODpY9ELK6VBjI4nxtEOY4ntXCjoT3Zv17V3QlxmFDv42kWhgOq B4riNm12s2outsN/hlVBGE8CJLUIPWxhIQaFIHAxyrOUuIyxdtOzwF0eiBLmVaURvjKMqQLWEvZU qGnsv7KJc/4TXDdKxWXwYn4P+ROrBUh6xiN+RVbF/b4GKhYhmjsrqas0QKWFcyeijFFvHGGXBT49 Pn6/XtVQ9SHmSb1nesw92uNXKhLSTFWhilzIWbv+cbWH/VDDQkdba0tm/5Ispt+57PCuJl/agpQ+ n3bhZRAPAYqHo+SPl+EUEly9vquRR1O6EXnZYZRiFarYCoRpjktBeFZdyWweCS9T/MpV2iFMzeZb qivB+TIRWAiG9A9EmBcz9lYoFChXSiOjQAXq4OMCc3zw+sDcatAJ2dQ1XfEfWrudBSV50jwAxG7/ EVFFdNmy7b7kh+fQflIaYv1MzaZzYVEG6xmqmb/aHo/J1kjit9cOfDerr6dwk3UGTVjQWwGk608N 1vlLyI8aBEl9ySunVMiRc2UDi7avElL3fGZA+y4IETa1RZlingfAgm4aBY2URJJ3z1hNoTAX63Ms /c6HHFiPN0pHJjP3EUuIb7ezHQyIw2UpooCPeU7kyAcSHNc4Amyv5E+r9aPXc6jnqyhAvBISZqwD MXJaPPN/Gxwritz7k0WlWcwqt5MndX02ijg+Y25UX/jBpZCmr9jdRyQ9Z4+TYyuMUeq770IUnNUh Sk95zxJct9VAqROVMnr1O2LGVcEpy5e2Uibq/RtUVLPN/Bfc8Xbt9M27hd9yVyA4mZTN8iy1Y5Il rHzXXjHxQpOtAdGU8W63vMT6gXTXOVvnrtfBeRwt8m+tDwYl9co8oDU0broRtCsqPTTCwhadivbN SM78WAEWSIYiQ5zfK5Yh48i8RTyp79sdezPyz3WYQ5DgPp0tgWe56FwdsxTJK532eYDkpi7D/Tvi j506XN9N93RuLgS1yHtUlph8w9S4hgcSo/nSS0QUoQtPlFk2hsp2tkL/7Z9AlT1809hPm5jmSbNT sVfJfVzCy1q3mDEkhX3tAZPg14Q4Wv3wHtSW4PAK+LAbl/WebMO6w69iQtBPVnmp7v04QatMQXPm pW94cJr9y0jlm2XCgiyx7wPUk5kKt+deMr2CVOeCNlmbl6JX+wMU4qnV4Dz1g6prS6pX7z8olnGg 3N5tDMn1mi+Cj/2FBCfDJ3OTW4PMxsGFKRlAo87/ZoPRfcZ4LgqHLgQ9njq13nYceEEdLq2+t8sw 5JhrqbUslUlgqP4SXLjCqcHbZTAqNewwLVtcW6HBefr3PP711Rhjh4V/1uBkpsF3nprcsU1mQE5U jSD4bMDYue4UJwLSoSzR/6D5B3ONQFkpFtQyaIhvXU8riZ7x9nTTmMiVzQGyaWrbbEPQWc5r6fBs Az6zsU8WjnJvm3SesX5c0J358sAhZJHJDAbt+cw1NLHN/m/v6ZTZQ6c3wmM+uniCyI98UVQzZMWF Y0jAhodwxsRQo9heNiWYZTBGJwQN4toIiu4YcoaOoIksX9QtlEwdIQEVc+stEcgippsTJJWrjtZl DOJRFcff1SrwI9MppD6Fkrd07+1mM8A1v0NJvKenpE4frs0u9OO/C1FH50+oCdd0tXdxcpR5/YCw p7qi+lOmlXgExDlHIySYOGviPak/MvXWQz/oCTdA1JhZBZXWuhrCjQia53vv1X4vubvBHXlC3jIb 4aaexGb7KT17XeDqZy8PlCttlJlcdiitcXiSXa8PDYUljQuaPN8Jn6AId6Z/Kn+uTq85rvGdvJWC SoX18cMJSF9wO7F+FWNLM4F0FKWgNVmFPOTL6H0pKqVYOKP1i6M8Bvsb2THlgUdBjm4KGq+Q2Npd sQZGbNZrXC8b4CQcD79cnRvUWMDwJy8Acdoi2HuOQmn+Zb5yAWI+CDINMxxInSU4jcmVcwEYQNST wlLFTYLfUEV2xLkaMJ6KZhanSQZiWAEwgHfMhbqZNnXlmNvur2OpARahQzQCb+9L2i1dBsZQRIt6 3SryKAf1T/ECVu2o4JUI3DTJVYbKORrhiAUntVWXWqtEbljOJYcv6XrI+vazESESj5kCtiuZfOHl KcurU+FXGqKwW+Rn3F08FKlAOkd9TTdP6g12da8UqvGGRX+ytQfkRpA0YSNtwOA67gAzfUGiVwWb /9Hu3wo9yFlM8UGneTpdUFwFpShGl0fanaxsjAhTbF9G1N9XlkW2gWY8cYFr8nAr2YLFzYSje4yU LlYaeSqvQAqgJ2Nlq6UmeJDCQfk7DM1erUP7kGUFc93Bj2hFY9OC10RH5fug6Pd+NLwuJL6ktXqD YDxIYCCH8OCIypjHPYd8L2TXJg06acWi1TEDPHtrqYE4oPoqEbOSQmPD+RQNEr269UIIKuX5/EL5 eQtpO4ii5ucD2rdg8MhmZWZFBIVT0QFtqZgfMd1WXmxWrgT2IiwoqEnmMdvMbDB1Dbpf4r1sjcqU fCRpSeKUiuXghQWwX1g+/oz6Q/94x8ecaptMJlZDUU71WJLTAaz4z8cNpP9/yebG83WPIIu5uk4w 2vcsI+zE1JLQMISq+2aetEz7OMPnoRVpk9aoyRNi5stuJnDYzmtRqFldWpM/nmCLMndHNhChkpI4 b2EJOUJfP2rpyYhP/xETypSRA13c/6+mtmdLd3F0ARhipE+CldZ6TL9syUrxm5xYmL/YlCfHLsTi +Dhhq6gz5byXyo9mnQEJ/yIbUdSQ3dnxCgBUjOzOpieeJWoaI8V2XV9MDu09TqxMJdiI06q7v7a1 0QyVvb8xTxyB7ILOPJMB0fnOrWRzb3hJvKf/qBLcD/SLTiImtBbC748B77KKw4Sz1b0pnY2891y2 MsxJZ2ZRHbNymtt2K24aEUZpqcHBwoz0RMolMb1dKM40sn+QhJpBhEcWMkykPOpASO6GgOmMMzkC e+RXbvqFVi+0ajmwWS/Q78yJaVxvrNRASvbgolWLz6uv7uUuFAxz6Sa9Ve09tHwwmoWAn+nnDRe0 MLYcfhN6YH3Wo9v2eHNI6n1odiNqbONevXKQSiRNAdZ/4lx8sIOyL6GCrfd4CQ4qgsoclmCpMq28 u1Zo8D6gIR1GT6ZvaRdY7npSpkybOdQlQ60Ke/2YJN8kB9+SgVq8Q/wG/cd2jpF69mtq7upRMEFe raiIxcOW8HiB97sLuajNJk5QSH+HCxlitRivh4Z4tnLxzQVAjo9Rv/ZZ/MLGryzjxQg8TsqorKbx csQP9bjO+dzUkcTZPe3xHAXd239k2OrC8PF5UO5KzMCTRTss3bf/WcbV7djGOaWAA6q60Cs6oUFu nPm4AYnzEVb8EiaRJMv5fjt+fuw3NTgB6gDEmRzsw0nv76ujZcd6w3JtyOzFt9B8ep3A65Plv38U Fr+qX+3Bpobtw3Njrl0/0T0IbPRzBbEiT+gLAfNWaBjie0ulG6hKXr0/fc1CknYw8RaOc5bY99uU bJh9PUyKhmDAEY4SgNK4nb3Hhql8JSYD/54hL/+IwykB15sAubZvypxcMcJ7IjiewwcU7cQQpTmE 6GdVta5WHMKVATF5OCU2f6fyhLkqYh6INuByKwLuLTkhE5e4cbyBEMHrw7Uuw17GaeK8GJoj/P1L r9oVv+j5n2zcAxkGdApA8/m5UTFP5etlV751yaayNPQvLf0elXWhjnQi3VXJUch8/1PuVYnNkucr ifLiztNXnzfGRJXDCnQBlbuAwb+se5DVAWRekbiEztqidhW9aJUdbtvVVUQejqpuWxGL25OIQcBm asnlx7q3PsBDuiJQMdXRtlEH4GbFZNkD8NhhS/vaoPlf2xDuv8hy0s47Os6MbTjAWTXARYxdJO3y pdeYBb2N7clZPE3KlScZrZLg/BJN5MGCTdVSwozJoPBOovaQTDZGOkhgHJMFpBS398osGC53AUz1 ItAP5yMUreyJCzmGkBd0Bjc62XoMYNJbKLjL7peKKzukssfcZUAC0bDpIaVXzjD3xQ6VflyHG4Cv I9L6hN2kkjOAF9r/+aasdqXsH5KhdRMhxWDikHJLM4mqq/8GUJjOTU7e5fX6jT18rZYMi4GvH7dL m37QbNT2ESMWe5Sf2RAk2Z2wgISjv0+4HFFPidbZtmRQDPHDDNwQ4TKBJCY8IKYg1diqcMbIO2nL DXluNqZb40RTUeSmYVY2wesbm7g8eHWuXm7PvbmEHyrTk8NSA9MzIydpMFfP9C8Juxk2CbbPtUnc DtT0tZ9F3Y19CdIGpVdmQvz36r+azMQSr8u7MnLpvklJTa5PZCHjOYM9vCcu15oKxQhgdcrAzZ24 ZUi2KftHX6lysSwYDx6vRNR0X41a4z6h9mvcRbujqCMjKUBKjaReoDaN71rkPWTPwwkJ2POHLtRY E7PUwPkNW8lLjqdzRa3zr+O3wUk14M4aj8I2gRM50qZDjjiQ2m3Z/nI2063U8yFEhRCucfGpHF7R GXaX4zQU3pLhi/VkLUa5yUQ6q+eU9QU0MxNPykBA2lfMbOFQleofHjz4F4vuul5At9UVphmQXlBx 5Z3GMqDG1lMzu7yqcfd5S6P64FvFjiuM65QAVa/yVKgWIokc8sztR6odV3kyiFDH6/EKExCn9Ysp Quw+nEjhCETS5qf/A7AGMhEliOLokyJx+cnwy+KHssoeEH8cJSyPNwOmIH2FHtMb1vJD9gZ1KZri 90KwtQBfido/Fk3Vg9016gJBHvW2MP2SER0kER0zfMhwdLEiYvAL5x1mfVx3KJG4CfTfsbnmkyul 7J18IMVhfF9oUBgA1yI0sujD4vjogQyJ6JsX2Yaw6DWmnmhw20noPBIrfgrrfet6Yv15OT+554HB 51l4vNZZdwzrwF66Y/GESiOc8iQwpBbMR4Sr3eYFNG52yZiPeFn/7auBsvPfx/qN4AoLmq/JcZSB g+8JMb8O7hhgu+eS4+Wkt/r2xwXgAuSDa2f+LGe0IZr3ZOD61c1sAU+vpUnJjZP1kdapuyWKZS5e l6Za1AZNNCCsovQ1kzqpO4MUgrHDBcudxNiQFnfiYi2pXg6ClBMUj/N8PpUHMwp6oVAYesaPwPty Y8NeLNSlBeIFcAZ++kbUsQdBN4+2dWaoBRUiN2xpq8Da0iF42xCZhf4fWeTjtfntk1srPY/CDvpU mxkN1kbVVvxcboNJSImomEQhVEkQKGMCVPypVIDjQIYX6Yr2ZWcxkw6rVodk2pjNP9OOBNhGdjJW kpTZxOhtOSjsKyj3cz9u4+XEX1UXg2h7f9sKf8fO+tjQEQdv2I/c156Zd56QJcmas8tiLXEI2Vtu EMnTGIsM6ze/d0OjbtbmsHALcmtEqWGiMin+rsiSUhNhsinMEjrp2j3YtmOvW13iBGOVAIPNJUJJ 5aVy5nU08uDOzxQXJ8nkaxgYCczoCncNPv45EdRNFQly7hTchy6HpFjtorxm8YvSZ2l58L1ByCZ7 sCHfXThDtJ/dpxn+DHmPh6iuWQq9wnjylgl8QtqhfEY4fd4uC70mYtDZZWKIQgJXLT1J90SRqwkf wR8dpMr1aqWTn8gF9b/RonJyUfWGu1MmBc79GfyA17w6cHZp57xYoCi7SM4XGHtXg8rRVI9qIKzS MlVwMkHBXgM+4s4CC1hX0OL0spClaEJWjrBGq3T39wj4EbKO4BZAYTHNUGP3TffctIYawQBNajJz xnVIUYZsrK2CzNgZx/LACeaiDV7MvOBNS27u/jBKAiYQKNOVjII/l7y+T3fMnbBcaPxG231U0BRE NVOtSDmvPWuXbm3OK25zlUwFTQIlXGYUadXb7cmJpmE3LhAGGdqYzBhSxhyiZ7rUfyhKxNG+ggVQ qoQYVpgz+5uD2X4YAQW9Fx6rch8uP2oaYU8/mPGin4OY84cjOHL24DMzrao47+M6/4PY6vhsFL4H sQSvo5SsLO00IfdReog5WSbAbIdlyhGtBM3h6tVA+kcMznsR4ajwk7JFJK7KZ/pC73/R0fNcGzej icCMTb2CZ6NLQiUkFMqwtGsorgh0v6c0xEIcDru7muEMtE+CDbY4vZBP0Vhy4rSvfLx6jtP/e/fE h0R0Cz91nLkDSXV5Uh+qK9SMy7XLmm4tSKI1FDQDroJvCH3G+bFYLS5hu1yGOX1dtivtFbbfoDeK z3yvmgoGIAF41NGjkjBmjun/bW9ph83UkSdURWn5TOfsJE9BT2MgJZH7YxgcNWk90ms1aQROBkSh 00EX4+NaxeR+r7WZBS5H6x+D7F0SV5SBLpFjW4etfuCU1soTvReZEzdSZFWGamV0hqgj7PtRS1X7 Pko3Mr3TS19IFeqcHEf0pQyFBJN3VDpyX4++2gSOrFSrY+0v1y/xn0vjpXxItb2m+zxYVCmYo/tZ TywW29l8tREGHfOW7sTKbbVvToVXlqppiPhKiLv2Q9AM6hcFbTHlpeBJujOUMDpBgI0eqihXc1Z+ HhSyWukWkPVL/kDF+2/PsvAAalpLYhaRg7RALzB0sqeJWLtllDn6XMMTb6fcZ0TPWL0AbJanrNUP dVre0Bep/0p1ZcZuDAqoGA65ZiVtSHLCwjGQHHAWKxPIyCUwyZFIDNiLC3KjD/SqSp7ZnyBtiYwh Ad76kuuqCYmAnC3tuPqgErUanikY7FpsShiEa18ZV/JfXBmGBJQlrB2OTmo8xN5u9rOVKwYHfqsU /mGKqNI38w90Udq9IoOatLkT3GhbR3IaLgq6DbgJoDluNZkJQW+tiOOulTlAUlK76O6uaaWFmzQR ZqB3UTZFxPZGM57AB/DSiaHhHGy7PpDkk5TJePbWMkj78VtuVw12+fEd7OOJvunHf29N6czV48TU a40GUcnpOgJlWYW5tO8yHQN2ofXEyCRP9UvzFmn9ZrPo/xq/2gR6DFPS3Mk8GzMSGjWv7I5Grf2d Pub/YaH+mzfl0miwejGW6f5QbRanr6mzcfOuhzyMTADLtWOc8How4agUTln2Mhf8vcnLqdtE4sCp 1Y+tgQ2PvcYr4ksELS6AtniovFHnbx2mLZarWWfFm5BFgXMlM2C1LwFCqbtfk/a6aL+0+II0aK57 HBGFQ+xV84to0qWd6q4RT7hFXq+XIzoDlHjl5RGgxZ9RW7yMxZd2GQR8MkHXw79taTuCuCc4xe7Q wNwkKShmA7R28lKumlE6AVuPG4vhPLCbJhMAoL9tPgG3NtOEcLDIY5gc8jJzCcF/GlhFIeYF/U3g QVRrCtB0tNOkYxhPmbLZb7nh3MZgmQLs9jxUdvJqbuiMK8calWkUvUV107zs8RISiQ+Vv1h6DMRo 3HLhSA6/Fv828XB1BkCYYKVq40Ul85iZAUXhZ4FtZLEEVs3ABUb2dH3oscYHxDc0oSwQ+eLMT9R7 esmaXLJYMlIT+uFDk5hCK8b6FNuun1GDnyQN/Y6dtN2cmaXojhWcPnsgAc9OsW7cf/Pu738kFqG6 MWLVwH6TvuX3sYLHY1YHnzhHyx8Vo2/r5/p8ST8nEf78QkEL95Z9o/JfFTZry4zCYHuK8XLY9KxG 8Z/alm80tWXc7zJIzPpeq0J4UFSOfoqB3nWDo0aUmULlbLNUFiJeH8w+9KxVLvGhSysDYs3r38h1 dG3cawZ9t2LqgGKUcAlBOnVVlYkjbrZP6O4r2m3sz0E5gwNMEbvBGzi1iMxotBvjEZPaii1nzrum bSr8Rk/d+9WehBJVP6T+Cl7u2KJJxcV5/bTuMVNQuznRkh/XzNiVxaByZpOZgEwHFXH/oHfsbKfr hEAT1iqOvKHGMrMbKWkSn9mGUoTo3w0xRkhOEN/9NuBpSe6mInS1XuZxcfW/edmtgE/ZhL0U6r9R yH0hXRjKhBON6BDRf73Qpae6k0my+LOeemC4YGsXZ4ZKTbOSWGVg2VnvbNej7geNMP49IJ0KSI8J 3DzBVWU0pGKb1PeGYyth2tNUI3rUFi6tUeKea/C23C2qUrkPgSKeRkinklB1f9KYtSAfjaizJtTx flRsuVizndIbHisVbpyzXLFC4PLiV/1emvooiU9AZr5TofgqqhUuI+iwKi4BRi+MmnxgfHcIcnLK rYnAYszVNwQgCIdOOrHkD6NjgnOVoi9PnuCQsoLzEQ23zITGVHiJsTN7txQdbu5Rc9dAmLzzs8IT 4zaXPtN5LF86IhOiWcsCk4jhfehSv6T/ztTtuZ1+3AjCdQqJdrC3V2rGRR0wP8/c3mfuuIMjBBzB 8NsOCNFSZIqaSLw4fyujDR1KvZWwCWHbhcin43JvjRwZACGew6SS/TeOKSNKfCt17TGI+YPWIizA fqs/Yf6gRvaCGT/8A3orUKG1NS1lqGBqNHBjnYHFT4zZ5epIfufRwT+ZKTAAm0WfYEJAZESHvFUy ADAiNq/IxTs7fptMo5qfG+OC8ZZm9KaGBzU39/joa7way1QrHWOyGq6jmug4eJzjYnL3Dd0tgdEL o5JDvzL2fs7tOvdmaNVqz8SikimWZpvKU3kqODiHQRfjQHyys3jJdPlG+qAdeYS16w77Db9pLaLM peVNy8hdY1SrE6jAXnikKRCGtE4OF+jJ2QxqE0+4Goj1CfD0+Pso68OzEf6hFn+4CKynTI//GuC/ OGDX8OxqH4Nf9R9ksbeoJOOygxUH1o/LQKSsjn3wWSRcNLJ8GWkHz6SDML4hZC5eMmtAxL6jPVKb OT0DzexxFq+FMjJOl5/tkLGGQRUmzScVYysOGAo8cfRnZfybb9kWyvgXJpSbccWUnI9wKKFPFMle bYK6AfB2ICoBTYyS6NHsT0wTsNisSBRIAohY8DnCHi4cojqSuGINNSmFL4C+FbgIYgcLpgIUhhNw 8acmqINgrdxdHw0KKSJNSSQQaeTU9jY4sAg6ZoxLSN3+rgq+8hjekx9M7Q2kqDioEcpoKYS9o/4i JSjSjp8I+ICNMKI+YDW5RK4LmbjqYahhMeAggbTXfEWp0u8z8uZLZwh8dKj6+xYAp0dKEB5B1O8h 6wZKqbBxhDaESC+mm8J+DEZiHVdNynsLfOllaIbUdt5hZLykVP1ymEjfeEz5E6uLbUeFZ0ikiVtV m/Y1BF3LOsfpGdcpjxCgGc59hby/XXD5Cp22lch/7tEwbqvUU1rDxUZcY6Gj2MXYjTdeGVphp/ZX WRad0KRJVIGB4Ca3xmQWr9KlS1nxYQ/2w8ygaeNqNTB4xsmOS0OHN7IHQ4fB2ud0chsuO2Z41pqx cF7Bs599hrLeVJSbxN118Q4wzv+52dSH9ahFC5CuXsFkU617oIDB0ufgF13n4yP4ZFBQQKzxET1L EUXzgxi2MgpHW9xqrrxRSd1vHOfkpyoaUZ2tiiiyGd/nrPD/aL6UwUUu9AG1juEmUgXE1kkLd18r 4owSgqEL2uQNWaCPQ+wuvsbAemUP/k4n7PE9p51fCG9vgnGHeHVQzLlzGifsCIfxVgD7ybxy/sDi Cmm+g2p0xezzP15pOtgkDsslAiiVoD0ZPlhpeYHkHewOhrzTWocymbaEoA21Wy+S5VGVHw15kOFg efFBSgxLeakmy2MgwHz0H+v1zZZIDPh4gAfAhaD/bAfureZx7wQTpkV6la228L0E5gChZTF5C5t2 o5SmaCAwgsmJjzMuTSMUUcAwv52600wLWTVssDrfGncK1to7WddycdN3sVK+AEM/7lljDkwBAvyK CpJ4dp6rMVnV1Y1OMNtGYgj3b2FNb2smfgHg13AkyLYA5EjdRO7bII7/KPkH865z8NCNI8Th9o7u p78lo65P8oFPvdUvNnIRe7Tfu9DSL9k4po9i76EjQZX4B5+e2oa0kY6ANQdWdIrjFtdqQexzUBXh 5bs6cX+RICZJaclUsa1un0lqaMFBSMCsTyuHAOV4yumRXBV2ARtv12QA6/m5lOoknVKN5dTck84O g/ReBa7GwTSbkMrg7wctlDNtXfpjZVK8ociiVpGs5rC2nMEr+vLdzr0yZ6+IPSyTkR1a8BpKKEiX JRo1jsjpbii0uywwX5ORf2A+KKmIGJ/0s9VmINKM0k0u9o8T2J9u0B0PbTy0dOxHYTayDdkHB/+0 QIauNbSJbKA+U0P9Ohy9dYYcuoD+mM9w6kjI8670E/ZOcF4AdgZ1sTDAP3QwqkteHQypwASYS0AD JU9dwmpInuC50FXvGvna6WZQR4oVvWbd3fOHzh5ge7khB0VGfaiwXL14NEVwB51HPS66bKlR69su IDfsKA6USVYlmCwb9l3pY0Zy9idVYLv63rZbuRCjWoH+tdHlYxmodGqi5oeH1BJLWD5TAOpJnTc5 7iUNnEktZ8j4ZWE7IowxJOYRzJzBXTDmZaSE0mJT07nPhZwbfQgAQE0QQ4EjpWaQ+LYAC1RIN4ib XaQ9QcMtttYq05Y3jNRbl1d4C0jgOwGplky8siX4WIvJHhsVdHNCdWQuGcN9wKx3yJRhVG3W6Rmv AcfIf1cddN11UqwzKsGs2Hz7ti45UHhTDA741jvjdLvsotvGnlkFbnVGqZdA7NTF/W2Urs3bwc1q scpYiyHwEm1rMDxpNuu1uNzhW9HJ4c7C+0JNjujPoiPy/cwF73Q+VhmpeQR/GN62G77dpKPzQXrI dDEDHVJZ9dehHHjaHPJNr+2I3WaEaiR7iQXZUQKHiGajdxrW3++bb+ZsPS5P48agw9s4PIVgLeH6 l1hSeJRhKpR9IE7NHLfnxOH4bznDFjXNh09WPwRMqLWgNRuYKyvUKOTxm5fU+eylQDCh9jdJHP3L EOFgJNq1rmVLhoC3kXVJ/qduGDsiwlJ50ZOp7hZC8pb2Ykq1uOeM9ERvlDXurbCCBxYBlmMRsmvJ 7WzYWQvpWugeQGllh1ZUYu6bDJ3vPB9Le573z4PdYx0g4VKMoLbJsznJWdrcLAcYOzq484aTnq/x t0O/5F0ZmRlQLD2dSuv7opV4bJQ5lOUArnFNAd+T0e/PjOVczUzt2QHcJ/Xibvc4VvKl4pDUF1cm iifkSkwaXoLLJC1ZNjxASlMg7nqyAzj+Tqz8m7+zyjiF/Z6Zxlp+ZWiGP+DZjDsBtqzQujTTU9zm zCh3STXH9V6+NvVw5ZQjgfRR9Kaj42X8EzVaeqVBd5X1Gj/xg3Ttw12dVmxKi8x257cCdxnifpWM +UMiNJsZQjlhBMe17rXICVqN9yICiycGQd0cesh3abCKUACJ/tiFRVTz2X9HRMaVY7ez4aXUcj0q 52gUEohL3pzPeHlBznI6dcgCFrvEzuwvF2uhRSAV0PiSVdZAoXhrru2G4NQwU2JwC3F+W6D6OpCL v0OmyvkPaou5mV6wyxGTeVXFbB76OT/V3GgXP4AAnvoBFylLbPSlrBO9LGnPLkcpmTLyG4OGCbNp EMNA4t1FOoOMLkH3Dcu8etX+LXVipDSMhs2GnEFjtp1PgEV3MEAs1VhXniiTATMPczgqGsGgbUgE DkKSXpgoxOTmQvYgQuSusroPNPTEuVtakSUHGL5e4sjjOP3fahdD9XMEVd11b/spgnmR1L+2PMRY iaR2jIInfVMBiwUOYL1keGD61HH8ym06CZbwamIqKidIUEKz3zS9HHEBalndWy0OpVTVvM9qzXL9 S6ldeKu4mxo88fmUbAX06Zzwd+ShWM8e7Qp65KzcmMqcemgwe4gZyrtgulQK9L82jjf17Qr3O7NW jgRfAe06FCoKtkR1YVCTE+1pt0X/HVd6q941JaTpuPEG7sOg/H19tF+09tRr2EjV1r08jJXf+3iy O878uowagwlzfLtN4pcJCPnEWqDkSn9oWkCRKJx0IRtKjkk2Z4SmnsPw/+3lGebY3bpD3s+n0ms+ diHhynZEUcnTEhRRpSg1DIJl0zZtkTWTqdERfwvZyJyFeoeUYKsZUlgF3YYywCMTlehZPrzeljQ3 wPmx7rPKO78KQeozoUZW3ZX5/ZI6mPJBn0T18FaGI/3mR0ICin+iXOrbnsqigfyvdxai7AXZ7Fj6 H37ljFU/JQWOfCmG+xURRXMSE0/BEnm22zMLNHZ69xtxctE3K4/tLbP90NCrhoP2BdeAYzdqLwhE ffAUQCO+zNpNB5uvpAFSCynZZVy7Xunq0MdVJrVkyQJ66oe6ICDDL4qNGwUtbNKZwYXWU4bKyKL/ H0OoIlfsZxg9fQZfSj++Ap1hi6CLzzBZiPx0qQF/3wHuQo/gfWz8+3q6LsSzk0LkslWmt85DOWiu ZreDDZVSaNHd0VNkHn4SpCmR2atWs11Jlp6xKCxLVCAllEmOD0YnwO3tZIWTg7NRpFdhZtMeZPI2 f+BxUwMGGPXPlj+BigiOHMWpIX7iBQWyYU0bHpYNiB8lqPKBOcypaExRUzyIzebHHiBueleJauok HNCB5NcZQ1vKw7P+6MHLESLAAeSjhsvweQLsaOYzwkSWkVU6iXmrxX9JPRFNGjgFJnQifZgQc/sE JT6ZQ2Xb8cA8dM6kxxVDe37T2Nh2qqLv0aWngcxhMs05/2TdZWKfQHelIH76tWl83+oVFq4iqKl6 YTqeUTc2J4Bgk1MuSvMkd0pb0EnemMspe0cSRGPk4rkBinNRw7jmul8xh4y0QiieazoNSMAlEZMk /NDlvxO9yNFT7Qowsnos7h9FQw/GiEMIoiqQY/59pCq8a53oVoQRo5dYwjufKxNjoz8iTm6CJe9E G34nWK8AewuMdhZroADilsUREAwUeyqLvMhAUYO70ljX3vaYOcua+G+KEpOTU7c8Nxa9HT8uPuhh JS5wdwgoOkNCifo845Pxa8QL1agQ69WiZznpt9ERRWicxTk9Sh8wkqiVWx0Smk9NpVVQ4YdVZJae XbVV6qL1YDjww0nqv+yDPgQHhisssSDkz+8jgN5lAEu1Pmb//FJpOWpJuVQgL5VrO9JX4bHH1sSp QL3R7ZAEtLOe2w8s7/0SXC7Ba2ve8Ub0iWOCGqYQ4VXO6w0W3jAbIwnUksC11O25kvPVIsnruh9O wbT2Vcf9sbEm4XGH3GbIi3IGB6fT6Ka0l4poAf/41J7m1gKSaVlpeO64XOxMyoRpVKCSYNlfHaKY r4qAG7+lc9mwcNSRCu6w8CbJfj1TP40z/LV0xOi4p+mqrFelSHTcN5Fs+MYnr2Crd3UKNIAkecKj 7Gj06rjKBCrQqLKmV7YfWW/7egqtCm0OUPnG9QGXAR5DdMTl+sSfpNmEAb7oFusEhOSrQq6hVhuJ 9LvtIe37UFRk5J1bKLzSsiVF1bo9I6nylWWC0J8+2KQkwGFy9OE/mMd6kFA0H+XbOOZXjOx0VkrM eqmXgpjJQMJcSNZ8CULUcSPFV4A8RKF36HOOKDtHHE8mdkF8ufTWP0Y99fEomRtUVFYuZO//zeGW H/WgSFY6Zscn1+1/31wWShgwVacmUTD25bvN5abFnOvMUvYCnzIZW7N9+n4cR//4RfbkytxR4clj GFzdUmcDx6qF8EGguWEECI/Zo+Ln+kixJYFbY8iUdMj39fFojnBTKKGvN3kDEX54HO03NxzMgUBL lL6Xwbuxuft9Iv5CFLxtZy/ddUkIlJrNzhNVZ3+5BTMD0Ebw/vtKveeX9odFgA+7MU6iTQcZDELN XVEA4EB8dlY7BacOwMCGxX5kIzTpishx/vGZ1hdW7osJSckv7IP5YGx9LgPZmwqK+f3t28p6J6lH EdlogOjkggVRIozlfYVVfcWaHQDwuk/NIfPSxh98/jXvWeXFxl5DCi+isVr27+N3KOy9IVbcszjj Rkxy4Ie1O0YVsFmysrTwYNbK5LvUklV1K4A= `protect end_protected

gpl-2.0

d89d0ec8d3927188ffe38285004319dc

keith-epidev/VHDL-lib

top/stereo_radio/ip/dds/demo_tb/tb_dds.vhd

-------------------------------------------------------------------------------- -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- Description: -- This is an example testbench for the DDS Compiler IP core. -- The testbench has been generated by Vivado to accompany the IP core -- instance you have generated. -- -- This testbench is for demonstration purposes only. See note below for -- instructions on how to use it with your core. -- -- See the DDS Compiler product guide for further information -- about this core. -- -------------------------------------------------------------------------------- -- Using this testbench -- -- This testbench instantiates your generated DDS Compiler core -- instance named "dds". -- -- Use Vivado's Run Simulation flow to run this testbench. See the Vivado -- documentation for details. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_dds is end tb_dds; architecture tb of tb_dds is ----------------------------------------------------------------------- -- Timing constants ----------------------------------------------------------------------- constant CLOCK_PERIOD : time := 100 ns; constant T_HOLD : time := 10 ns; constant T_STROBE : time := CLOCK_PERIOD - (1 ns); ----------------------------------------------------------------------- -- DUT input signals ----------------------------------------------------------------------- -- General inputs signal aclk : std_logic := '0'; -- the master clock -- Phase slave channel signals signal s_axis_phase_tvalid : std_logic := '0'; -- payload is valid signal s_axis_phase_tdata : std_logic_vector(39 downto 0) := (others => '0'); -- data payload -- Data master channel signals signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid signal m_axis_data_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload -- Phase master channel signals signal m_axis_phase_tvalid : std_logic := '0'; -- payload is valid signal m_axis_phase_tdata : std_logic_vector(39 downto 0) := (others => '0'); -- data payload ----------------------------------------------------------------------- -- Aliases for AXI channel TDATA and TUSER fields -- These are a convenience for viewing data in a simulator waveform viewer. -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command -- to prevent the simulator optimizing away these signals. ----------------------------------------------------------------------- -- Phase slave channel alias signals signal s_axis_phase_tdata_inc : std_logic_vector(37 downto 0) := (others => '0'); -- Data master channel alias signals signal m_axis_data_tdata_cosine : std_logic_vector(15 downto 0) := (others => '0'); signal m_axis_data_tdata_sine : std_logic_vector(15 downto 0) := (others => '0'); -- Phase master channel alias signals signal m_axis_phase_tdata_phase : std_logic_vector(37 downto 0) := (others => '0'); signal end_of_simulation : boolean := false; begin ----------------------------------------------------------------------- -- Instantiate the DUT ----------------------------------------------------------------------- dut : entity work.dds port map ( aclk => aclk ,s_axis_phase_tvalid => s_axis_phase_tvalid ,s_axis_phase_tdata => s_axis_phase_tdata ,m_axis_data_tvalid => m_axis_data_tvalid ,m_axis_data_tdata => m_axis_data_tdata ,m_axis_phase_tvalid => m_axis_phase_tvalid ,m_axis_phase_tdata => m_axis_phase_tdata ); ----------------------------------------------------------------------- -- Generate clock ----------------------------------------------------------------------- clock_gen : process begin aclk <= '0'; if (end_of_simulation) then wait; else wait for CLOCK_PERIOD; loop aclk <= '0'; wait for CLOCK_PERIOD/2; aclk <= '1'; wait for CLOCK_PERIOD/2; end loop; end if; end process clock_gen; ----------------------------------------------------------------------- -- Generate inputs ----------------------------------------------------------------------- stimuli : process begin -- Drive inputs T_HOLD time after rising edge of clock wait until rising_edge(aclk); wait for T_HOLD; -- Input a constant phase increment each cycle, and run for long enough to produce 5 periods of outputs for cycle in 0 to 159 loop s_axis_phase_tvalid <= '1'; s_axis_phase_tdata <= (others => '0'); -- set unused TDATA bits to zero s_axis_phase_tdata(37 downto 0) <= "00000000000000000000000000000000000000"; -- constant phase increment wait for CLOCK_PERIOD; end loop; s_axis_phase_tvalid <= '0'; -- End of test end_of_simulation <= true; report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; wait; end process stimuli; ----------------------------------------------------------------------- -- Check outputs ----------------------------------------------------------------------- check_outputs : process variable check_ok : boolean := true; begin -- Check outputs T_STROBE time after rising edge of clock wait until rising_edge(aclk); wait for T_STROBE; -- Do not check the output payload values, as this requires the behavioral model -- which would make this demonstration testbench unwieldy. -- Instead, check the protocol of the data and phase master channels: -- check that the payload is valid (not X) when TVALID is high if m_axis_data_tvalid = '1' then if is_x(m_axis_data_tdata) then report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error; check_ok := false; end if; end if; if m_axis_phase_tvalid = '1' then if is_x(m_axis_phase_tdata) then report "ERROR: m_axis_phase_tdata is invalid when m_axis_phase_tvalid is high" severity error; check_ok := false; end if; end if; assert check_ok report "ERROR: terminating test with failures." severity failure; end process check_outputs; ----------------------------------------------------------------------- -- Assign TDATA fields to aliases, for easy simulator waveform viewing ----------------------------------------------------------------------- -- Phase slave channel alias signals s_axis_phase_tdata_inc <= s_axis_phase_tdata(37 downto 0); -- Data master channel alias signals: update these only when they are valid m_axis_data_tdata_cosine <= m_axis_data_tdata(15 downto 0) when m_axis_data_tvalid = '1'; m_axis_data_tdata_sine <= m_axis_data_tdata(31 downto 16) when m_axis_data_tvalid = '1'; -- Phase master channel alias signals: update these only when they are valid m_axis_phase_tdata_phase <= m_axis_phase_tdata(37 downto 0) when m_axis_phase_tvalid = '1'; end tb;

gpl-2.0

367607e5fe9bfe59c87928a664db9872

amerryfellow/dlx

alu/comparator/comp_test.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.constants.all; entity comp_tb is end comp_tb; architecture test of comp_tb is signal A_i:std_logic_vector(NSUMG-1 downto 0); signal B_i:std_logic_vector(NSUMG-1 downto 0); signal S_generate:std_logic_vector(NSUMG-1 downto 0):=(others=>'0'); signal overflow:std_logic:= 'Z'; signal Cin:std_logic:='1'; signal ALEB, ALB, AGB, AGEB, ANEB, AEB: std_logic; component P4ADDER generic(N:integer:=NSUMG); port ( A: in std_logic_vector(N-1 downto 0); B: in std_logic_vector(N-1 downto 0); Cin:in std_logic; S: out std_logic_vector(N-1 downto 0); Cout:out std_logic ); end component; component COMPARATOR port( SUM: in std_logic_vector(31 downto 0); Cout: in std_logic; ALEB: out std_logic; ALB: out std_logic; AGB: out std_logic; AGEB: out std_logic; ANEB: out std_logic; AEB: out std_logic ); end component; begin A_i<=x"00000030", x"00000500" after 10 ns,x"00000030" after 20 ns,x"FFFFFFFB" after 30 ns, x"0F0F0F0F" after 40 ns; B_i<=not x"00000001",not x"01010101" after 10 ns,not x"00000030" after 20 ns,not x"FFFFFFFA" after 30 ns, not x"01010101" after 40 ns; LIFE:P4ADDER port map (A_i,B_i,Cin,S_generate,overflow); TEST_COMP: COMPARATOR port map(S_generate,overflow,ALEB,ALB,AGB,AGEB,ANEB,AEB); end test;

gpl-3.0

13ba044437b66cf14d6a43b6e9360f47

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/fix_to_flt_conv/fix_to_flt_conv_exp.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VXpDA1MmGpOUxFnAibZU9WPms2lNhjbp32s5Nw+PXl5MbTEQp9AN0Eg4IIPn327Q4Tf2dxK9w/nB PAAPev773w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Ejf27HQKwS8Xaok/EigCd2uMhi9YZL0rGmEvAjATVGHbqNoWSxtbYYUEgVnlmBqUp9pZxYksMldh 4vRphm2vXgFzQtrdMqo6Eu8/zTRYGl9Ojp4r5i3vdoS33gDebIdiAhhhSWr7FEWmkznFNf6fYO2i 1493i/7AHND99khtqZU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Et73oN4cS9g8NTCGsMnglfm1UmKLE1ZhJxR0kv8IE/pd6ck41Ot7UWzo65IF/Uwe7wb/Gov1jNMX 08/zTQ4u0aknYCXcdDFDPYbOTAR5E01PpWWCnaqfihiZuhRAgBUqn/2yKMjxWt+RwS9+XPQ0zFQ4 rQBVqlIwZfNlambu7UHgwZmFs2rn+IkXSXQIXlXRKFMWycjWBzmoQkZRJRCuWx2BceaHIiGJr/qs JpxTAcQmDz83ErMAIoZOmlsC1owiPHlWIoTP/3/e7z0HQxbE/Uur71FZSe2+L2/Dlbh/qBA5pDO3 ycN7x23+zLPii0yucjPzi0mqWH9Y3KfKvzsIdw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 1+WxjnWngzLtMiGZSO+Qihiv3Wt+JNFkxpym5ndwRSq+UtcHV2TpsHhP3KHt2RM6LwAGAhCeBEYq 3W6t+SH0FVv9dn/OOVGJtQskUZLYzQRCAZbReLcSg0AfwYX020u9WDyU/bsLGq6fNZbsgjxj46b/ DRURHUmVLCWYyGb/Yjg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rv9I4ycUO75mCoK3fTnAzzFMUOEXIOFXcBp79gUZ2McQmnz8e2FzPyUKgcy7o2YAk7Xbu1ZRDf1H FsKAp5fEHzy+yNtCooxTwuYYN9TQHzCBw+LcH7lQb/wYHhH2obkCKPfbCVHhY7caMNUtR4EmQBNm aumKSjaqFRFrrWtbDL0bByHFNGM2R7c+lSmlT+lvYKvfteVCX7kh3sPGPYNdhlG3vYfk3SiGfmXP UcunORu19vm7d2Xp1HVjcdMW6uwtXEPPpIeWobg6W2OvmIGuzoP1ahCygGRk8EXdOlOpGRcau3np Swgqm4ZJiMuZ/r5qWdQYWHdfvoBPB7R7jcLzZg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12416) `protect data_block ekyEWuGG/ttiqGJ0RkgFJ1B/S2ShSpvuMsODoXXMYiqDEB9E1JqqGzlqp6E8Ad5BovO6J/SB9wdb sYCnSFJsjga2dIH77xVyEhlkiNzU99FO4HjrSXO/2JNr9KTAQWX0G8C9IC6jfTqAM+PLHGYSmseB 5FBspjCTPvRSj/i0uwQzqKZYmYUqRnrgtuhqJk7B8b5x9Xk82FvG/NRwC1eI74hWUSGE6H+bB0F6 iwa1kWgOJbB1e+N8L6frgfYOnDPhXLpWGYlVv2Jc+ZFgyYDqyhnLSvc4BcH9rcdUp5K5wVrx3Oqg yJSOO84W7SmW4vbNExruciIvMtuE6qlCYl0UsfzazG7g8q4ZmB4+oi8rQDZ0C5KrdBVYmhlF7wIS +LtBcQI3O5wmqxvbweBnKorpv2nxKhA6HOE0Mqe3FtUGdZTY7SeEprrKkWkQUWWeZJgEzK1OWukm KLefPigA7dF3lXuU+pH1kUNRrFhGnGHgl9Omzvs3gGAenX05rLWgfWC9DarzpdXkC8eW0a0VwWdu yFXiLICg7pSk5NEwHLt5CwjSgsqOLi5epYt56bOQ8hEmCb5qRD4kYwU1oe9HEkIgT1NC/axlnx2l nFPAIhE4mDlEZ1wX/SkgdS15IoCh0c4DBE2u1c2g5xrH38T953EhM4Z042WIwhBN2SEV1AeuZoEN V89EcB0mpJBngct0JJPldhqb+9gWiTYwZFDnaokU4tqUSjI7ZTsoLhAGBAUs5B19Te2rFGq6X17B ul2ui3JQIJawC5B8QLwyAg+PlFhzEvQEAxdVMNKFxIybpPOezKpoLHyA3Sc4U5XINQi9YhXXRT+0 qTpZb4faNLoUIGP7ZszKuEpTU++klwxySQfq59dL3izS1Cal79Ll2rNzRoYbki0vwvW5U6FkmiPe cbLCyUX4pTNd9qzu+CRMoKTp4h+kVoqjg/FPBpf9KaYyuwsqxvaR9JsvnkQn3cej19bilWKwd1YT /vptiJ5YzEB+4tKN3mCgz1X+S8b53JY73s3arS5uEBEKTvUWwLu3ZjgiiVdO3yf0cffGz0UI1n2a 8Rgx54vFHH3ADJv1szCKGD5oRleiIoRMdtPD0WUSshuMJJVO1/OdQFlyk/5pzBfgyhF/aa6zrsvm RnIsFjTmZYElYWc3V7LGRj4TAx/asI3zTA7tVD3hDAu6ZpWUqA+vwNrJ9UK/7FTJBpOKjDPCEM11 5UmpjcBtM5ItgzJCrOO/UIfAbBrOkGNK+UidruFdjk687I/T0c1OoKg/fvMNuoao4Kz4J4f+Bnz8 g0Y+tKhODYWfNk2gYknxGikV59FndXhD1AXB3qibm6pn35syK2Q7fttXdHZCo5l1KR77z9NnmCNn JObFtpspE3WvnxQWC4axKfKjvWZVCGzIZYNKcGv4RNzVIgWXVLTMm9X2GA2Er1QjO1jeilbM0Eiz 9c8zFEL+R39YeOM7zQHuo5jk73InkqyaOfzu20z05sgD27SjHJaTDrrO8pkzMH9VGu313TddikN/ kt8YV/1Ht7SqQlSLfkZarP/W5sYgSxj0iydQSAqsCG6S0NcH6t2dDnOarbZ+ry1LI7u+T6nxi9Up nFuutkZrFTxstz5w/+u330usGoPszaXT+M35R8toBtVgIW+qHbRI5lZoCJnc3A4KP94kGIFpRwCp eCiQFTzONAqoHvuovvupnPLRr8V8B+LZnAptYyvhzaaawuCtmjV2gVr0lNGdvJ5IHoFXx6RyubaH Ux0Fw1Sr3C+AoQqWcheYNUkWPLJLAPmaOzScaY9XFLojasxt8ZXhYRRDrwdIX9xzLvjV9HvZhwWF 0BnvA+evXF1AKYBvrhEymO0as486/lJLPfR0m+tiib9GDhtAdWHK1cjUZQE1akunpOXeRnKjuPed bOdJUJINucW2Ee02e/sgLtmr5APN/Ei7o/0hs5NmvQ0mC+MPG1YFF0jhPScr6lj15Fei2vah4zER 20xhiH1kClBRen54dlw6wDPZWfUYA8mnWQn3Hfo9tV2IZONmSwDLH20Ow/qoYU5DTvXS220Ce3xU Qwk96WHgfcQdSqKand/PTBijcqsIGxJOq11ay0fqtI8QmQ5qwIkHXKR5AMBis7GqaffOirumWcXf +Q96LChZy1EcrefUuHVNItGW2hasaPH2FDCPQuybJlc7llFu8VyqUNQEXpjBqmQKjv2TyOFGXacH VuArXcdQsaPFQ+8iZKfUUod41p+bf/xymeHdiUpV07sQpYiBowm9oWCMBmDHrjKn47BvfOmeRDJq 2LFy/F9Me5GpDLhIN57sDE94tZuXlsPm1sGcTtfc6dQy6QqpdbeN+QJAjCt+WyxkvsT6v/wA6UZi QNFpPIjOe4+fqtRtNxxTtHOnFfgKE1VlBFJOsRTQ/9LqsmlD9MMj4/h1FrinXpxLnH+xe/MFyZTL XV7PQ08dGvYSALT0n0BmG9iqkYJ6TqDFyxQ6kWLH/CDcn2+ZjCQBM2YyS0Js7pr7Pjm/0vsVKGPC 10421nb0EAHIL7we+5JE1IxUdwrHLm1fc0W14Mdl4mSnBMEenMzLYubX4/JeU6TgAK3UaIQomKfD 6uyJwtNJhCRTsVJgnd9lcDkrE3i7QnAL3NKHZgCzZijhZInVNHUwHJla0kLZ5qcSb785LuG5Mw09 CiRcRwwUYLGTsRPu/wX7p9genoApLj3Nbp2gjzAbCC/Ss03/ZYL8M4NB+1LnhC2QUWfmqIbAWHno ccuVVT5RxDiTDJGqIz9Z+wmuoa8iQfIZcRXEGQrkZ1a9uOc2m0pflvMXiwtD4UFsHklRyMd5CJtG Vmd2R/TJpIBGfv0qKXgRI+NXbCD5ZQ/OkJPtGV5xbnDryfaKM8Ijp8WPlhKI/UVHhVbv7ydZBwOA d2aGGeg21m8UzxOf5EqKIFCt2WLhRsPVWD9q68glfzXhotiTC0AN0SA/qlmiyxLDL/5cddhGWG5N eNfp6/vXQloXoqasuuyRn5OIZv0c0KgvoFjJi+SwZ8ssKIx+j7AH//3hwgXvRX+G6ZRF2T5nisKt PDQB70D7Zk7Rh045nVzofGfH24qgmwDaHQV5lETJ552p4RCgtgLPPKGr2yrcldvtc1qSJ4TPt3By S213DAr0fj6pceLnWkUswW53lIPjO/UasBXfuNcq3ppC7D/Z24QOpxRkZhI4Hjt4Mq3r0dj1ZyHJ CLnvmOEmmxa3NTocbtg9GgpC59ebq0rBtnvy9ptTeBXbNRvL4SY2YVZqlsGby8L8+gd+ngFv8Wme fzLssyIbgZxkVkYzM1LO2x6hzLG/QRCT31NBJXNrJafLvS+97VB1PehCoLLEOGPhFIxmdkDUGosL r93bc5J4AWXBLjcjZZnVSK0opx21v745+dvc+0kPuJt12Xr0HnhVUEF2bjryFa6qj0+SeKjbzqS1 Y7Mb35GMGg8/9T1EDXm2G+5qSt2Iv8vpCdMSwbG6SNy6d6VfXaQOw2fj0mHr82g/y+9XxnZqP9Op rIg6lI6xO270P1mUP+30zU+QWFWcZmNhWNh8C/URTDrkJOW1YEqsROuVNNAmVqo5D5HT5HlmaVOX ssAbOv5UtpDTjnVH2bWJlia+2srZXHw679qoVLHlc3qohjJQhX1vhcurrcak1GH9erlNhFbPmJs9 Op2qYYur+5CLIWWqfJYH9R25l65+hyuSwkwoeo1g989X0BoclADoyvmxnZvy9CvwB0Qpt18TYhzD BZSxZFYmozqq16tSoow+njR5EMO1sLZvJKNrE2d+1mkzm/8MMEVK8cGy9e1AmM+s/FkfTCZ45LyW pa87GgiTHYaL9uU8WBzzQxy64+CKEjTE6TswHAKQJxEVpcX3wSH89mYAOFwv1/hk8w/R1bOFfER7 v43xwx8ISO7I+EhwOYn/AkNs1xYh+b+mq4khQkDIEILKiV3/iabObMy2G2CnF1KvxfhA53SMwTOV ShDQuqSm3bKM6rUq6g00XHK1Rdyg4mriu56VZAFLhhkVJ6Iw4abuuOlr1bhWVW8Ol3vez0YctItb HR9nEUMFCFrqoa/nYYEhiT8HPMvkRjCUSEUW8MUF3yMnQOVPkOwLr/8iT50r5MgF2ZTsZLAALLGN CkTellOXkuheeiSb13kRQfoOGnfVx/mmGCreiceu6WkVWLSXR5FpeG3zp5APl6eR7YB+bvzZTBg8 W581QZLpoVkAD0FpYaAzOalm2khTS9K3x/4cFyeAviBO8qlut5s2JUf86l/pGhlr7QWEfubq8QC8 yBK0cYKieKBdKYAimQ8J8uS2ndQLUsrOKKzrMmDHmIdyEg61Ul0MQJpEIlEQG71VYMJGHYfD0/OM t2q9l+TxQaemCwWSptu+N+3phhfaD461TzsoUXc+SG3BKdxF7me3uHXAC2Ez505b3yf+q8K8mCYX dPfLQBrev7ArEkWe8UVQ2yVCJtwLz5LxvUZPezHljPSifs05AKRVtJLXtA4l7rsIk/e4/1kJ0bvz PTJtwmPRezIyS9kb3pJ5uM2CU9YQrtyCl1FjRDtJlB2cVaYcVrnW0HtdSaLjKLJI1G+8gW4z4MUA jMTnnu53bYsdIZNQb7n7FbZMOppOf44pN2I9YpW7wThrfoJrutgsktHyzHaiK/A/PoB0S8szYwL3 53s/l8TUHApaU7pl6BhaUh7SO6mxY0tdtiYH0sV0jpnZJ9xUV0OINkjbW7jLGWMi3+uDERbzdruu n3P//tcTnmJ65kFLPiW6FIBxAsfXevqzI4vIQHCAJt/RoXSlU+6TjHx9HnW/OL7IAnoz3Jxs+8pr FT95AfDPOSM6Od1p1MGsoQWZwdRI0Ofw2R6+U7/52fDGPCNeVXCEjEz/hnXAOkL0qQ913Dbaa4E/ ciDWmgx4OtFjGeJ+beIu1l0q28gqIKoBC0uyrv1qDK8rEg9dpDrIyhDmJNAa6/truJ69iVc/sLA2 ZyXmSdGpnf2xocHd641RDJCNPH7dn288BUxQ07T7oPQbSVuL0RZO70VrmMdMQ+ZcO+avYdct0NGG kKEHXeWvh68OfueMUAaUcwQyn76ew25xD0qpWHpB1Bn1CsLEDODs1ZR1oHN2NfsCBJP2QnXeAqHU +67JUPD2U3wCfd8UZPBy9ZPsPvLQ80Yq+lK19zzCHgQSkYY9QGjaXA4uzhPMM/m6eO0CyHFyQV21 Qzim8CrcsGVsSkkFJ/QLwrNBbcurdjjlWmvkUuaSL92Q28OfXM/iZjgv3tEyvzPEZLuBnKchZwEY FXe7tKD2rSiAP6fO9bE3mTqBZyADR7eP1wZdXgr4vWv86CI0JcPUvKcumhj5WTzR0MOnY/S9C827 yii6vJuXnduf8BMNgULYl1W1GjxxdsTezj35kVcZ3CAggC7H3nqGSIc627tSM7Sj0f+fo7dfqh6L sViZXe+YucUgKvUB4/okrQgpW8ePV/SCrjaDaVXNBrvPMgefF4pZoDY+qx6Za0fhUfxmft+XrdwJ SYZA+Gd68eVyLNd4a1vtJzT6k4b7frPtUSY7HOZtsA07J8qzZ8/CXYl2ChtLf510Hty8S9N+GeHM 0AbgRyylGa4u4aQ8Olj0tNosTVZrPGWPCRpKhxiyc4/LFe/VLu/I+4bAnXZkJdgmmR9YFjlhgdRr tc8bYrBbom93QBGbBSuejsWEdnCc+ogke/zwsAvImI8jkvyknPHDkqCSArZ4bgxK33DJQ268p25V EPyBBGjqvAF7Pqe8rotAV+tg1m3XxyTdugB/qhL4vOXwl9xfMFyHd5czwBeB1LS8DOu0WnfPAI4Z zmPiONodhgZjDq7JsUDe5aMS8AsC3DBkLA5mhtNQdionQZpxgFz2GaS4fHs1hmqwULodECX0EeJe /Iq6EDmGboUdb2YjZaz228M6pHN6AO5+zAakAw6a5JctSgRfFiA2WmuImis2lxrprrqr0s8WYeq0 fP3a1ypjzDRJmBVcCybKwPPHkm/vPQEtDgpE/02IigeuEo+3liK1WGhai4/nGLhMy3c5HfwCyOex JK0Q/wrUn21iQHs7jNBNDPMr84ZPsL57NTJoJblqjKDXwmcikeyVrMlgemXnIXZcCFrvHf2AixT/ XIx9xEKFMY+yHW2Q9lHu6lqEZxhaZOfscTNPAPk1v8MAK1GlXC4EaEgsWqz3dsQa0JcPXNa6zjyT WNnevpdbYAdO9HRsEW0mRn8mTMRsWbU0rNq3v2hMUgzkgFPWGgCuUoDxrabO0PJ3XfybOm4kZh2J szWNoGM4xmZ3JRxzYwS8+gFtnDy1Gzmfpn+C06Sy07YjKUjQCzMAf+bpoBLPzHxEj4rT95kgtGH5 MOYzYMcl9q/8vaASarI377ctm278P+l+gB3OLYz3vcVyE8v/nxOeDKSL+FYKj5igoa71Re3q8VTy YoKPuteLIx0kYK82zHMXMsrZh8508X5u4y2ESOK0L9UpYzwy9eFCE7QdHN1lYCfZeO5eGGERuMOt 9t+mj67lVmot4YoR9+dJKea05p26hOPqx7FayPMozL8h9gypvbHHJsA+Bi5FlfzNiQqcnoqNRw0+ tWFYudFg2dEYcpyM0Ced6UyRd5UmV6EMUfx9VSySKZO3n4swAFEg4IevkicR68SVprO4H8p9Ga3X KUjkvbjtPviWnIxOxy79acTdBYDvBo7754hYk0LoL6oO1wo1nH6V+d5IXX2xFFqwC0WJ5DfwOoKT zTX4RZYL6RD3p5tPBoFBWNmBXS8BQpljrRvZxhgnl8J8C+0bDLy4FeWF5Kw/pJHyHLskO4SAwc7b EMcQo99VEHkoWJ+8jd5xaDODFVoMDoVNLtxbR3RPeVXjq8N7+gpruv3FosEGLvJcZeODRibjKuMZ BsFnsA5f16gItZlI7zaRUjH69g4o+lRys59x3FIbGg4j2HdqtP9AZAo7XO2YsTpJhwM4XCZx9cwY l61i//APzcB3aCtdnzNDTDVPe/zrZRaF1cE/JMb53FtRIkCcNdkab0EVHuUJaFD0QB9VAdemzjDo SpcS5VHofcmTDIx/1tKDxO4UpW3JLQG+LkdjSAto0THXDgJjXAv8Mb86RHh83JNP0LNA9ZO9Z7iS 6iLuX1OqXDpkv6VWq01bsgscQptA61pQleKiNL3zkHKDi57H1N0zFIFuHMoI65zMA4Up8PNFFC88 qQVtZ9fc9+7fP87iEVPMIb2S6cT520cXOaqFgUuZawW+2Zp2GaQtE85/w/Xg3GnXhj4GtUtXROQD r9pKoXnSH73ZgBU+M7aETgaI8fYsHrMdWHcasqEhA542AYJfwLwiDqKpeJX/W9mTvyO029MiaJ9y 87g/RG1M2syvxVEQwK74Ke3kSGu0K7dWQJxJSxs8zMBQiFwfdYdfI26dGf3Ehlh6l8SSHhwshMhP 46wrmcrovpZ/kN0x47ol8RtfYS8QAUMiLzRiHI058ApI2J4HYVftPie3qUJXKy0uTG2sRb8c0NJJ XVLuLtK9gFDqHfIpYAaonj097gaCZne56c/m9hSXEOOkJUfztHqbDz0zMRHHNNrSFKhIPdXpsxHh SP8rErV+xFUN3hlOa4XQ0c6xYaeRQyTuR8BsEXfwDC09tkJOl8EWcjfvmZWp1h+NJFQQzIK5K+zj Q4pQMQ3MZx09mfyJxAW3vN+mnXlGS5Gq9Ln+XBTo6+b1klpOeR+sOO60ZrUEW46BCSqU3T6UxP9A Dbg58F8lj4vsNhkzAoWcdOvfUCMoyAd/fs1FUDhb0VhwvZwzhB+vdTtt9nfHTSKZk3XDuGfEexJ9 j2yI3+L17De5lp0Y85chXNtUdlwu1Yf+jVWDL9hIAvcNyWU+VLcCfAU1NySnnYbTwaE/rb1I99of IxoxNPDtovFGHX737pqoW16ZtA6U7dzsCtaLSk8TaMiCkX1nfvwvFINDvvocDyrQqBKNAydAHxuv 6ws7CekDnXjqLvyW84TBzSMaGCqn1Od3xsJZaQfPsEBo2C+tqpNPnrlpgq2tB4v4UGEjH9Y/35xE QiSoLsXsK52HuTshifzu0pwGBNGZKZwG4AHyyoTvz1cDx4QsgLZ8NbwsPdWYO030TOJRDOBLQUvA i5zgLC1AWnuv1FGL/D1dq6FIpYQRsERA5XpvwbVMwtupo7m7kbc2bmY+p5LKorEMU2+rlIW/LtM0 xi0yOB7wl6RkLcUUBGkNQ/ug0/67ALil1AVcdouJ4C0LGgcLDkvyL8p7JJ5vd9Qd/sskpsXhe7Qv WMv5a8B+jgsmvVIYaxM9gbK7olYKB/e4A5saqeIW1ZEZd8NNxs59AV/GW7GhoiM0p/DN41KlpYyj VVd0rvtlOfZ0nfhrtANNFI1USPF3SzLqHYs5KIPRRrT3pQBzh6imDFbsvDmYgJIHy0uKcuhaYvpM LDST37QI0BkpqhQqU3uU4/JQCEh9m5Rk+edVyWRJgl2TfCzPTsJgPTBw5oDEVDmKLbDTOz8gEHYL MINj1vmVL1GrvehB615GFgECId1l1PaxEYPfHoQoU4LX4J7VVMSEBL5/KStMSRea+MiUdb7XabpP NGlQ79i5+LcaThwu+ndSJSrvv4te3H4SBNlQ0RtDNpD+KRSuOnBU4m6nYsOaQYg0kqGXi4pD+4xX JEMHmw45cv0D5YdMGWzsjRmju3KtrXTeroSi7NYPOVKfzUV0dGAUYhSWmiZha5Eswyosj1S+L+WW YwJBdY71LlCVhy5MW0/zrEoTx2JiXBGzxFprNiFZR1SSGpdnXTIlQo0xWbFbZk4iWa6nQBY99MpR Z5U0yypQVAXP31w2GuZQdwbDfJWQa3YYf31FJzGn5TR95DLFYrtFUj6gqbvcrTDz2XY2heO4UPhw kCH7g0HYSvjvUfoN7ePABeS2qFfs5n5ZXHcTNo99xiCtZVbNevfNr2S6dbG5sN9uptz7PpxcFwq2 kwXgZN0BtJO5HbD5jfa77tUwuczMVDCdHePc2sVSwCEEuz/q9Yqu+HbkpAtDpKeYkw+X6/jx1KAN x35PEr5e2rrjt4J0HEpZf3Wqpqnw6w4AkTEyRh4WJgd9luHBqbWgpMYJvi8Y926Xb8/etBGntb6v tZT3Tb97fLFTUYYNtgG+OB0n4sc03Y8M765oi9bBn7YIzbsZl669dD5274jrA7z8YXXJwzkB51Qz Ygpf5fq8QAxNa4cJkXhQLuBkDHa+gmNshP8CjqZA2LLr4HULV8uWBbHbHYz9o0d5arS/MJltqz+G A0d889NKoCmkBnUmEaQzOv6G5ht7f/tHg/yf1/a01n+7eZ80n2gCrdDcepRQ8H1JS+OoC+ddDkn9 wQ8h+LZaWvMh8RdA2Wo0C6svdpM9Qzt+U/6n4naI7I7/zj8HJw80AZIsy1AYW5+w1DuIxs9RQOYx r9RLswyRAkKDh33ghwmRnIL0rvirjJ/3jPNFYgfSKzHnu/leE4cEu/UDB2mg0JuQvSyw+njL4BpM aLqEfquCE40lHPvdqH0zeNpUvsWOzRYFYogCEMoFAhvvFD4kJfwTwzpTTpcQvXQA3XWMafVtm+Z7 Ku5y33FNIXmBHts+ePeOCZRPWGQ4zVzSdDmJVr5JvbU+X9slukmq/Z3dlhE0aFR2WuXbd0hwBIvb coGG8J8S4tSTTwjoDXy6rk6VSdB4V+IIBdOG7v5i8UqMFvqS6p6VAG0yftBFU+KiQtGaZ2kx+t4A 6kefrclP4YCo+h5Jfw90f8pajbrgh/2ckL4pal1nt+g+5u20SoJgaMsMHH3i+7/0FDplwgR0N0x2 7YG/vAlExdNn9V36ppJc14sEqTlnloJVDPNJf4AbONDau+NXNv2An4mx6buq9FFtHZeF1izORDzx srYZ7SicGUDu22Mx0qoQj0VdcztYdgy9CmWuxpZz4CRYC1SURMDELBu7nOEHBZ9/G5X72rcM4Nrb 8phbs+KAZKll+BBuqwBLI2Z7inQZv0Tod7NVSwsbviAHBAB29W4AzUD4mST1/UZkaMmHlEpUAeg9 pB5AD0U5/e3Uyqy6/rliC+R/mMfVq4cIabULDvyHQaUVAVzrxzUlQmAk97zd+juvwHVWvGnsIlP2 KQPFXb29hAOJmccDV10QL3aWEaXd+rekVIpCMhgqKgrKmixaq+84Yy9GgBC3C1C9I9JAFNoeDYGl 15UPUlIgEpNe0sHJ7ec6TPX0GVMeEd/9rEMAvNJI/e2RwuuibbPBJ0yZRLGuEZ2v2C7rEbc90dml F6CW7XzPDAsQUDurxN0Z1ziXA6blqA8c4Lo7KsAn9ieKwvB9noCJswVysKdfsQRSkbTF2wOQg6oT hWMSQuIYCNwOAZy9/wIlZ2AufF1wJCgVtqkvgYa81QLrs3pu4oCEZgNWWxIHso4u4BbIzQ1xkMNx l6nDcPyYcutegg8rtSIaCC9nE1DXigSi5LPeFpH5RbQ4cbdOuBWdifT0XOU+y3yNBIMAvY/FZawV kaVeR/uDCEy6kqrF20Wtai9JxoEEAXkdVjFZbpF8fgZa4EDAnwzIy7kFnjggNpiJoCHyyEY018OX G53MTuVnw8PMOwTYY5lFDJNSp3azpzsASesZhTjSiTR/22hwASQxit22aN0qjjI4q8t6PGUbebqO oJFwKrtVe7QRFzC6VkmrI8ZE1HBKFBGjz33sF0o4DiHLvUI9Z+GbqhUShBxUM2tYmBxvguNzPq01 75xXi+KXHBhPrORVCz2qAq9aVpB/7+79xe4rGYeWEG+c59ue/YnvPPMdLT5danK3fLHfepCH8TAd XVErO3EkqrDoh/ud7IigcTjaI0gacrjvxIrN1SuTCiA6P8wJesW01UEmCpM2EkOQX4awI2j7tfcU u3lTjrMFBPBvpikurcVOYFsdK3BqVrU9Of6BAdaODWMUJSDPG235HSZCEgiN/CR7i9/X0F+OfXC7 Gc1zZIUgvg6rCX8N44MBkxrgi4x3j7IilWAQh6TLLO9pvMRfIhZuDKaDERnV+dYtKowQWK2pz4zU bTXrrL7wVJo1fU9HKihgzqqw9C9Q/vAk3oJjaJ5+o/sR2JOIeZpcZT4IZuzS9f29s7bgTP3wnQH/ UnhSM2+JkmUw5RWIu1/5E/Y2/+LgxvLPPiKI75WIMHpovXVlYRWh4rSZks5t3Ez/l+vWZ66lmTnB b+aXp4JRlGhCERvfAFKgjBmqVekVTdc6+YPi+Ky+7NTNcYQZa7zrbLcP6RNmEFeU0PxQV2uumb7J 8pTrsIEEyfQ5nSoseV1ffX7W+uIOsUxzUXVm4ZCG7/g0MQk/Rsk4VU+ARf7ZvsyoN7V9ybU4T4er 2b+oqqHQHvvlnYrIWIm/jSMAU8DiAjBfQTRt629TtWiLpOq/chG5AMYxDu+5CTA2yE8SSEztuvPP SNILmvqsM8TOzHXNmYAl00dStsQiB/l72wlKB3YnapvDDqtjIvERS9siOSNXBsmtV/MMFN/TMwzy 1ot9ksBGAqsJIKVkDLG5bR6zOOlY6hMj4ykrmUon22Lw9qimyR+gVw/+dZm7gO+LCAyr2QjrbW7J wKz/Qpq6sbN3CQBUfJeyKCc3auQaIWwSWV9dCwflaZH7KrZUjx1yC+mBqswixd+oifu6sIbVrBHq IAiCugt7ED4mI2kq41lU4cJzaVlu/VI6s3q3ERFbiQ9WqZSDdvxoY9AnvCfCA3SFMulDskhsVKxO H4f6lvPHQdFD78xKOEbu/dzubXb2XGqS9whHOeji4/QKdKyzG/2N+Yl12lyfH+zvXy1+jJqtRRnO v12FBfm1VxDBBj5A5jfcieRohm3eBdFf2GTAzQPQT3TccJ9GkRiGTVT7O7hUEyovZ0rfkVm/2u/M EX/68mXOyvi6wffoWqjEqV435FaslBG4j3uhwIjVPt0b+kw7Gz1VEOIYxTxJ699/yCUQEcO3zBvn R047yOCvRTaC/yhrPGvsbKM9TSFpxWOHFQp1dvzLoLkvhIpxpv3ldv2kxgPeW4M00PGRhxJcsg/o yeXELY73Nk5RgTyokwjkegF3brvymoL+2D1EUH/7jzgPStxAAux4W5ltAwKiKffntSxlW032QRlD LxaSbio9vcrBflGNJWAeYnVell5B0chG9jZkPL4QMFfXq/LUt7uNxQq40vjm0UkY4lj0BB/qBkYj vfrKkPUitKBgr0liVNWOJkt1DPQJJbPMt6LcaxChCIHAJejemf9jXzqaODLSU4JGQWJKUQN8Zegr 2xl1RHYSyoTSg8zem5O/56F6lJ35bdEFnRQ6GO3VJuCx3HtCm6O7z49NmS0l6R3S8i6lTjsMSNZ7 A7QgVpH8+CpEkkJ6q2fz1nQJdD5Fz83SJ3Zl5o0eHnMKeeMVleRUPmah/CKVNPrCu8euT5otocR/ Lhy2MPFHyrm3lOXVs/vL4UXZn811gGbKqZqfpLKdbCus6nae5NFWFkK/pQ+IRhC6/SPr4v0T8E5N +SA2pflJ342s+G/eYAkkJcz6T0e9OUuJMFkev3x9bmaoIb7LvEx6k9FLh88SsikVskEnFGPAwqwz qfCSiB+81ZzeFriGsJMYpLb30vq8Rn1Bg5Q0I5liVXpZIZ6FLOWZO3lMhwkesUAen7fKIyfNOYSy GEAejLicPhrtaVfj09qVjifdT4xKswpewIGKOFuZdJ4MBvdPpeOmTXgcf4gh7usGp9tfHRdxZLxF JoFbYYbDvcK0aODvb3DMznrp/8G/yKBvHhx6JDKIZUjffdgoib4Mm6R1UksWfXr8MoIVIlXk53W5 gsHUsSn77htsS2L9MIQc5Js40Ve/JQX1q0y5DXNGexNEqqY6rBO+O9g9QOqz8DO1ea4pvx8jPMRf dqFd+slr3Xrw1jm7qr8zTkpI+xfeVbdOt1kJosi08m7vNh2w/rFF8rcxpEUuTh02le+5OJ9VGBSR o+Tx99Vo2vVvMAc7nPRm0D8YuuJUcAhS5NV92f8oYV46ECfrCrkYUSZ5VL8bWEDVPFlA0lDhhLpE /LJaKhvwF7izab8uLUGTsH6Rgsn3I8wv5+sxjWVf5hLMMtGcdo14eyvUqici1VEtYMmnCRY11fpC erNHxyg2GynPdgqFKYL46ISeesV6jhi5MMwZoYOLKfcqZped/ochyfVrvZfMml6ZlhOdSSIea8Z8 ELbZWjhcfbfDmxhRXSLXppMFwAL1wyrMtOxj+ze2FFiCasC+Yk4lACsIJkgTYWZAZSPYKHrJex+/ 5XMHWjqPnanMc1Zux5n5tzecWIsyZEqr2MLZmXjooP8t0xUsQLQYVv10gbDF+gD8hQJRkAMdmccC hAMpbBZQLbu7f+ykRRgaoaOpzBrjncs8nhRq593eefy8+MmJyt25UYv24HD53foGXJnZpVZr1kWQ zSAPibQUlTP4rDY6m3g+Fl+cagB7rrW3mFsZwmthzpzEebZ8xTQR8JVxqi4DSsyuOWf3c45p8zwz yP/mgsTY9A7bHoPVwBtqv2JSStiugqiqTVMuilz7n9eXvDjjZ9FcHZVIBreGRqdTJJLxJnz7a9T4 bgsOJGr2DNnhcnatFk5TksllzsPwc4RxFrg//caVwkydUxDeaqtk2lgoLWyLXxEGJdEWgYGied47 mwUUCdS8cZ9Q2evl/XoC2KWYItP03JHKJ/eQ3jiagkHA0XguvNi34SpAx0GLZH6TW+NeOKkirTvW Z+UgO5JRbc1OdhnpLk/mKlncImQcdFoG9DfYYFoZ18NVdrt8hCdpF1irKCzAQCGFEMCEGprolgAz BmI41CVvm740qlxPnh+8yJqgP8IETwcsG+7o/N+sF56k8vyC2z/jTA+0HTpx10jlWUuivmP9Dcq0 hC6/Z/W9oZzoAcCHTyA4/YKBbYEkq80x3Ol6C9KnX6ev18MzETW56opvS5OvtwQ2yJcXxHvbAlpM DfAsnhaeCppGroFjvgBVCl2TqldfbkIC8QIM1n2m7hFxG7Hl7KZLELOe8UBoFYcsR2EP3F1A/N5G zrg+KBIKvmi6BSRGKTKYVjqymGhpKyJKtI0NfHKZ+DMc9BXbGgWGEnwggvDSzYz6JeThvdufcnG1 x4S0yU63Gbf2x/ehF5BfE+NgQIO4GSYSyO6UG2LbLr+plOFeX5PYHsEQD1I6LVhbC6Cc5XOvSA5F tsk9mLl56Tr2hHL4AKLsu9RJNxNnXPr1UO1t5+rKsVIfvNUc9GrMgFFcyMSSwUNB1qiU4GDepg3e XXHuQPsZqdoselN8ezgtAhIxiUy9Zx4RyHT6lCC1BA3hdf+iujeAiInsBAQAxljGgaiIPUrIRTJs t3iAtJl/WdfD2cIEuVTF262PjqCtrpkZlD9rKhDwbUXZ5N0sQzehRlZqmVm7sr6IrtGkHmheFJB8 rQZ0uNkZOl49EcMEwCLANZF2dFn1yihYq+QK+PG5w2acMvQjJTyZ8derPI0iurib6AXG54DxI/1C mNu0pq0fm9+nY6YebWK8Sa2BtQgxGrEL/xVVHgm/JVkXur/atI/DJRQMwb5e2rwXK9ThNJI58jhg 02ZZnsfZrW7H9brhQB7lFQQlCZyb1foA4P+cjgHSA3S/l4Crjh1vHaxzX3z9rGFFUDKYTZdhGSLT ZBX4HoJEp34dpHXlIfW7Tqd1uSxA0L1hKMwfOzcusSm7sRHESMSgmVn6G3eQko/cF+7KKLvy0NC0 4xVvFf1Hgynhsk2XPaPIgkqoxeP2an2TwAVTsg0D+g0r+IQzs6nt4qPkBQnVfWjqVf3PpiANJoms qOhvpviB3bng6n0RgT2vRVpKrnzTBcQu1Wc+kH8VBLPN2k1adDVa9YsWP+iSjY6DyTb9u0RN0SW7 clA6JTu2lkf8yqw7GfXP9X1ricAKy2fuXh7M5ibKVO1cwJRC+KraHGXMRH0ezXa7BSW8C7O6/POi iKU1DoOtVvw5TXdwV5dXxOgE2zwvl8tJlESKUnn/vQyVrijfiiC+ztRieoI5HjglIhGaKU3SzBsk lA7pe8V/FX5SsCUdaIVp0ewT9vFVB6n1uk7isbUTtbvbswspR1yVyEKNH2gPAUsRo8Y9RuGSTgsy PHCvIDVw6/5fKdaVAbzmW493MxhJknR2uz03TkfgicyX0KLvzoSP2PVn4SbFMphw0v6btRxdw+1p JLJh4KucJ1eejqCBmRaQtYPqHN0d195t/KPCvCw54jzB5jAtsDbq7q0qbEWWwXqpQTQPmS6TUsNZ S/W54mMwA3JfHkcZ/fuAMDdtzfho5CNaddCFb99wXdA9Jj+lYGJrKaB8Jet3sUHwhlAhbfyjosB7 imk7OI9RONyjWghCiAE+GOmdAl/CvyU6E/24Rc9hDhL9nPdjkgsiIaDmLegl8mCVYstqZY6P71oC YNG8n/CyqQ4MV1m0Qh9IduC+oeyWtwMN+kvcIGCqR0jD6Qkc6nLaA1i4NPp9bgtUcdbuyH010uER ryao8oU+zhcURFcxcKp9DpUBD7MexmhRubCMrNIJnA1JDvsijQwo5oU207M7Wc83eF+CDnISQO66 UhymZUwvyPN2YdT9XFJmbMRC1Un3O/puhY4/bIfEsHHY7GjpF4By9Qo/XSy7OGcMGssFWgBCHz/T 9kghxX/lfH8RGok0ezQ1gHDIkCrtfaz2Op7roQhjl7A94WwNLRef9vzOy1C4/SsXdU4dURlZ5igW 8O/qmA+JDGLRWerD/1qXwNJ0IdsUB4KQvie09o1tNzGxTA5Vq8hW+dJgQ23RkSNdCSl7Wyve8cTe Ewwsk6RRix+KyjiIXLMM0/D4EYyqP14KJ+ySDAGbDo+AjdzQohN1OJCKfm/WseBw6fuTG1BmNbmA 3WQMo6Xf6u36ibdmfsmSGcKviI5nK43001DJ//dgxtAecG+4xkRUqXV+KE4KYGi8SIc/6OK38ong qvbrj2NKAfM1pMNA/Ye35cQbB1L2udi5qagTrrrtc+dG5brwH6isU+waDA8apxxi7/B9DON/I/xS fbFiI3wNk3iOciOGDPz09jfMYK/qSqaGz0Ys4m2PVlwU0diSzJ6XlhHRrpDQHmu9wLBpJSJ4dEaU CSyJ8yrAwHVjq0nMOBRpOZFWjQyOTdGh8Hx2IiHF2987940wPCT0L2cVZvSo/y4Mrz8MtjGRL++c iFujBxuKnRbgsvtLVWWZGRZqV+MR1Yb3wDCErwfALXAd/8fbrStpknH3JzkVFlYr9Dhi3ifNhBKW vlB3D9wAHvngXjB2uK2QGLGRsaYQOmzZiPOiNXwAVyIUmF5xAF3/Lx/4RQ0otbPHfxavbZxOnbXJ co602TBL+MkbGTbNlu00BYR7mZIUJ2p7H8LIiLTUhtCn1XPdIxO9e/oFGIp44cORavnYkh+DTSIs hsaoOEJ4cXdOhIL6Z8zrFfte3T+iWEzUkKfPDUcjFjbYoCXCDntIPsfdvVBGRLprQoZeCjBHnx+p hI4lm8uvtm6AtVOv2sE8xMBzqORF85u7jJ7A/mK+bjQh4do4IfovyVPKzUZlXz4AsA+4YmjYL0cX 3hqHnufhsu2kffVc7ewzFJ1zhv0HcCZ/Q3o6UVNGDO09SmsnjSh6uJyjw8KBkIBVZS/6QeNENrF6 Bq3neO3a7xpirf9ZFF80QkT7o2wH7VBGTHLIKU2idPfqYTjxaRQcH/nHgjTQ4Vo= `protect end_protected

gpl-2.0

090c6a9632d0467787f3c5c1ebdf4ac6

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fft/c_addsub_v12_0/hdl/c_addsub_v12_0_base_legacy.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block SkeXthY44F3oxBo051+ULseaR8ZMsUOXb8fhmCDQvD33Q4qpQu0CIciw6NgDENGlGvU8Ijrxe0MP VmvbTS5iPQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mjEsfGApHwG4M86/eA3EYRe9p6tvvCoJIhlY4outTm6+hwy+o9oB/wzp8I1ZX/kl6BELJULrFX4I jUvXpxJdc6DYcDmIbifEkokIQ+UKa8XzCiksu3soubn9AZ0szDDLz1OqTiPV83aKluVjZCifSafj t48sl2S/cbCFALfMh60= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block gLihllCuk2TGWYs2NnyL1LqwNXT2Nf5plervANm9nq0KQu4ImhG4u7JDQZI94gxA9kFUODPtweUO FDwZywHJIVi5LIQhuqflffDEAlg+BJ0+cZROnY7hAkOH4U87drlRMxQlf65jW6qm5CcYgpPKcWYy TVfxVUkKP9TMcHWUODEM9udqimdoQltXA1OOjsCG+ew8Hqn0q8x5o/9/0NP02hpHZHa+7MyRMeda IPduY8uQWwvQIONKCHxUU0XS5Wd5htuv2hF9urSk0qb/myH9VS69RxryvTOp3PkK5HoMOTAwvxv2 saJaBRbFYc3WBXWrdRPMa6EypkziboEl2uQeug== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bC3La/8UkPQiaZ0wIMnc/3vBUWwRnWMmMhedqJ7tS83sCzg6YHTX4VmpkzQKu1uH+hZEoJbG+GXo l9eNndGVg6t4DveM6kfyp2DUEBRzvhNJXKJ7PbfKH6QDUTaTMLdsUCyN3wS7OBVPZJOU5T1MnsBD LVPabRl8ixk5dqmBBkI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Ii1ejnBzQWfOPrMU3lqpsalnDhzGi0l0LXIMwEl/7uVOrCxD3YuHVo3sqCtfrZkH8HmCgRZepY85 utM03P1AUq1pQgg1Efe46uw1Gq2RbJiR2vu3kmGdX7Z7tVQWEdM55JkJ5ceRR9sJQyqDEfjTDcSl 2I41lQRKMOT1C0UbdOWlHbXW+eMtTfjgzk9YpRkOTz4PqjPti0MyXmMoW23OGbFoDGXVRWLqF07j G257/QrqiZjOKXf8towDHjldoY/dC5/lZdRr1b8JJShcYVunTv+aB8wFoxiTvH34ieTTqGsN9D3G xSxf4Zj3zdnRfjKdaNnU8Hy/4TY09A+Q6U6Odg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57856) `protect data_block fNEHrxgcvSsO9WqHkpd+DkBy147acTqXtDpv2CFzNAPLGj2yGSBWt2wPeRwMu4JRVgj5G6Khfb6D Zc25ABE4F4TUvZ3B0q98PU/GFMsVy6OdzqUX8Kg8FgWDZ7Hy2G0qKc+0Fr+h2SB00D2hi7ocAIOz fAywT5+q9hI6amF896CDhaB1GSSclmWh4tJuYDC6lYWyL0Ssc1rIJZq+FpddbYBBfhpGN/HLszjs JegXBjH9XZ4nygOJuzKCpd4c2Tc/chSo6hHgenUKAPphB6OANFpsZuA2aZfGA8uiP0p201PrmrJ2 l/InIa0Ms5xt+dmeadG9pYqKC0wUyWuS1DYip5LkZbP+W98m7FDSAsZ6gLnlLtS4xciA8XB17P+P s0OmFi3iNaQg9+oPIscRq1lpfbQlQIkD//HucTspIW8qQnWPlNhFBqzu4j/kxoPG4RlEvTlKYKqf BN8etGW//HRjZIMQVfT0em/dQ+xM6JaHWy+jFIZ/Hy4Q2bAryKkJ5a3hMfe4g1sXQ5uy1Z+R70bG ij1JWK9L0Q+6bV+yrpjvGdfBi8+qzMqJx/FR1Baxrn4WKUjd3E6oyEbnjZR95hVDuoWcL0xu7VNC Li3HWJe1vb24MpWPYRKF7a+R58i0+jZvKrAY/l9INUIPQprbbXYUHWADIZYrTmw7MKRzz5CqEyri S/RQhuuRjh5tvLjJS5GAv/SSfvah3AZIQQxOMf9s1p877vsfz1DpUs9L+DC+hvwRDUn9LfkbOzCk O5U6iyjWO6sS7sPtknAUhQo4xMlvxTAE2Xf8myZ/SlPMVA2/5l6xAPI6AXkgwDUh5VNOcJgcLfZ5 Fxi6e7I2iFyPRL8QP4QWnB48tflCT+3GTWzHo1RP1g82IZWtNso7/b6rEsa7flpF/GidUYORYVq9 aqY31WqfkjoMqvdxLmv99uSKEe/Crr0p/v0Ryw058c/yaFqQHtIYDLH3z6OJO0367kAC3SwYJy2U nOmQnH8zJ4CxJRpetU4DD6ba2iehPsvhHwdTGzjjxEGtpXj0W9D6OzF1Xk+FeL6HatbqvGosDqLK FMsM0Llz5wImVGAbEY8g7U9U5bj6UYgbhba1J8bVwlhFDI56DOVtRoath/DsIAQUvtYGcqewm9Fz 5cpHzOrJJW4b2y2zHLGCNE2DTckA5AlvebPOnob3qOZ+elvuTJ0c62qk1cYNopNeTyqfNM+JhjSx dT+e5NDorFMehqK5tklYizE7QzxYtCVM0AeLSmKIO7QvzQZMdPNoG3CwmqLmyb2VYjFNh9nLLEuG BPwRedB7eL4EYtg/CCiAAmMc5QYP+jzE2AIMPjttRrueNdqgcAC2WraCKXv3of9DT5ws5QX9k0Uv /lF0mek8yixSPD/0y3nJ4joqIHd5p0PVkWO0rVErX7HRo73dKDFovozgvjQcUl0SbfDZnX/nNvjF J54WqNYF1fbU97y61R02+1JEST38A+fiNCbo/wrO6YqvfKBEPVoPUpWg6oVJ5fyXUIWZgiYWoQjl PLrsE0PlZaaBc2a2Q4q4433UyPpcDnB9m64KOR0DFSGt9xw5S1y+o0higHcJjif2dpMJ4WCNdLU4 OvwO3wDrFT6326GZvdie79GRdP7UR3jk5YlGYzfhq1/fq+RmMEmVhQyQxOHh9AyDyKSe8bAcZROY jfIQHqskJ7N5hUf0yxoscRbv79MCEJ7uqABsCLoSjncHXZ5ZgdZDZ+fUJJ1MeFw0KLVV6+n5gWiw cL0ez5+IkjIXDn92qCQ+Lto8lFPAkE6c6/y8ypaJBw40QqTvFfj3e5ss5n26oyxl1IobRCaZ6RNB K6r37I9RbElWrMVedTPBrF+QMgfNhZHxL6GwHuXH3/+sImuTxXhropauJgSdQ8zdu28VKH457Z3N CvYx1HZ3M/HHh+AON3ZSb3FJTI89P+3HOBIgcUmRYDf98TXkSot498J2SOs4s1sQOjy3M49/5n/u t79F8tRjxa8LF1mBNdYHNEyVvF5r81lLAPPEFsn0SgAgo8gMDe5ZkeGPBa5bpyjVq6QslEtmkjKW vnh1WabtxFtYUdN/0n1cMUQ3I5Ivv3oYH1H8KwBhRVgfoLHphR5dRFzM5ANiapcgG4q32Y5rIhxW fwE7xPY44oPHkvQoBIDrIg5ZF/vbLeboQv2FVd/eTcMyg6r9fHIvqxnJLAAX3LCADMuYWTqUPpUe /7vuZg+VKrHqnuCm/BA/zlZ+W/ReYgnLDpn2Fv4aebFeyRQpv10dtFywldU+iQXUCUTRRWdYaCXX aKkLol//xqlnM1J8ufGbfyrYKPpCyQ9umFR5EPYEchAvB8A6Uywo5mlbVevgh8OJvLV8yZ+tE0W5 cZBUu0TQQBvomHE19bkb3a3VIpqUuKzAtdHPiOPHfmWyCPYiSVp2s17litKghHI0kIg87qtGL3So Y14/QjSz2rnTBgmFyVfSbgPjk4Wo3DfW8iDFdtxbLitTQQMwzun2zCZtY4DKINRmLZuEdX0SiGCc x2O1XK5F4TAJWAzdFSOocjgYX1GNZy2/hW/vC48AJEssg4Jh6XDZQZAA2gs2N7LFMVDfCwmmu/cQ aYvh0PdWvs8P+JnCGSNvovOfGLll9zHeQERbCOzg6ZV3cWGn5lPTus2WAUQi7tbuEuA1NTJQR2qH 9AsLms069fjuHAzT8hgYsNCJ5XupyBE5xXihqmaU/pLgxnauupx4O962YcB7yYPUgcTUvl4WT9/I VPqk6RtYbBMYRNl9c3zpf+N7rUh7OvI6G7abNZGaKr3Lo4x9iNAmjsKD+9OWuau/1NYb9gTk9mRd dgMUqQLrdDzueukeIN+bBBEiBLFZF8CUAhmd6SUwP1uGX1Wc1JdUYGHXVa9XT+if5FOT6vjLy9mM iiUIexbr+ooJBof/arfD7smlYsadLkCfgQPPMpbfZd1sNEQMVFUMHawE6vh3A93nrly7CsZDzSyr OniXNq3DwGgfBjnIhcJy2PhHi/RVDbtNx5pbjWaPypF+s9lei1bhIv45ZUpIcseD0KG3nREjDctu ucnHp0P2rZersj+vOgsGerrTnNCJ50f4DrifYseN2KpWhIJzwkiRNzemErhyZ6KswNz3zPbw3+or Wv60VPlYGbivE86QaIItMDuOn/+JZTqaoDGDltPYi0hbEVHIrCH2QoIUMENL980bbtDHMCf6grSz 3XmIgFuS7YBIjaQBlwzELxn1Af6U0V1J1EBukcEc6qN6nXY6xNTwE/BzrG/VsxEAbEPYbbaAGIy7 xbak11s73QWL+4fBnsToe1Ao+Sa+0mA9cHfvdeDdmKKegHTJKhXoQKkfunppZ7hiqmllQgBme244 NN4r1mH1JI3GZ6Cj2KfNRmmZXDuT8nMTSbcO8tJGARR8mOZBXtNbMFkp095/e9kuEOLphBIAYqFc Lr8DAQnqSmEXx1C8GarsT4TdNC+mZskcaBGiO1nG6uVhnYoWSOIlzdRDHVMF5LJmB/mgRPviBuSF FqcH6uEuVWl1HM86mlY2n2xlwSQz6XHlhJ6UXJ0L5SLiXrj4a8UxFs7ZpwHd+rlU+i77o3Wiokt4 19NHOsWhyH7zjlC8lEXRjgTlmoCSbolpxLoVaMoggGhv8zdQCfJlg2snKHxWCk2+zQxbV9ycBhTT GC4JRdtf0iUSfI+vzvjtw47q4CYnHiPhvayurQSBZ3MTgEukdebO6PSfxgQgLILzYovpneVSXLP/ LFMO9vEImF4D0rmXYeUKsKzvPS3bnjO+tySa+Mg7xpO+jnf0J/kOHcrpjh8w2Bv6AiY3cur0U2MY HgttE2WarPQ6cueMWU253h7QPintDHV/ETzx/ZUnzdoD4oDnJM4TBzAYMjLXPspiITiQXV20ZraN GbUaKPSWPdGT5J4UxlNoASl7phs0eQUqARb2GhManSWDhcQR40awlY94gBnlZhwygK/zBWa47xwW 4GS6PcfQeE/zqs8f+5ouqgn0rjgbI7ynkMgt6ZVqttLFwT6jJjRlhctaQ9mJ5lRXaQ4ub6gqzYSh Iu5kECquR+Ia7Od5DHLhUrcT/rGy+4S3yfEzocZjVwJf/VOsnY6+Xer/aS2h3k4v1URjr8l7HeKO OmVuDJ2vyoO18E5wfMQUvJZVlFAVbC4pU7raHaDa32Q6tZwsxcjbI6io6V0zdp8lBIoAzyDTAY5K 2w7Zn4mUczw0Rv5EfXAvHW1UzL9eCEcx8GQS6Y1OpI8gA79PBAvMIb6cL2LTipkkgsg909t7ARUl cKJMCoq80udtuUGEU/F36EPbrhbvdBCSO0WluajLXsP4kAwoASxi+2EKunGSmwWNqu34EYlqI4p0 oqk4o8ntQI04Se5Q0D4pTu0GQr2lF0ubTSaF5iktCyIofS0Cehwx0pgObKZVDD6b8QnoKpm0gsI6 RVPwg3eKG0aIhJ+cvYMoWX9f62ZuHBtKAuimzKdqxMJfMln/OGl6FY44rplvFoiGGZ4pKbDx9QrB oaGl3OzwLpfVLLvuhV27Nh8oR40XH9CGF9FteM+MIqwkGwFjDOT4c4pdUo4Cipz6k8cFfs/kl9Ib e6grKb+uGLboxbtbbeG8SYoeYCaJAYzQEHcuY5J8SM7ehzWiDjK0jUQJwlbwwe4Ecyrsl9QmUxXd A4udkX2NphNc/pwNfN4K7uRb/mgsDhdxy0iG8a7sAJLYoccNNjGiEK+DZluLUlOjtpOxlG8hh6Bq 7FFuGFESQ6pAfAHHMCqfoRqMFkKC/C29MFHqZUDKsMTvZVdF1DODIkOH1UZeVzcMQvp6AOnxtdpG wbW0I44Bo7bBf8mnUb2v13hpYLn9TI4cEF1jlocWDtSprnm1scqVjvsUmi1rdQkORzRjAfJ5FtiN 804IQveE2GjLrDH08O8QvVwOR7YYv/3OYGKPP5TaalHTUtON+dJqA6ShM84cvQvAICA6QfW796zm +07IiLQF60Gvra98VeWqiTHe+la6fRzHURQqL4kj9MvLP4B4DqptzXfCDVmKcJjAHLJdsBvhRkcV OGFtCFgknC/ko17ooiQL2w492QRwXcZBeR7GO+HwI1vJXX3IrByd+PuOhPkD6af1j+L3FtIeo3PY Xb5rJioCXKHxk4/1TUFWtBPiu5VT6+WKbjk8uoaeIGrGTnWBgAmdiBdGeCz1opxvW1XTpRsQ6o6D WW7pFFFLkkfyMHd1H+9QtcZrDg8u4u5N6m9aS+1BeUCotxUoRUHgF0N7cKXUhgnWwE1mqfdAwryA UYvq59BM83asDvcSv44Plfs+pAEttW47PODRvcU1LJKm5+o99cy/HHBmKuPfP2fOBH3j5c/uvkXE Rt0Nbo4/6HsZwiMEPNnJGBHeYoaC1q0R2KzRH8+w+5wQ36MdURte+CpZ252/NmEkaK2iDBjAcFup vMzqKExzdxv9nwjr5qPbWqKJovJeQQ75FdpHHIuwKQLpmofPj0q6SjXDKqRMhkibHWW9eA1Dcki5 /KzVUidxWi+a+fiX7YZBIEZjJpVNsgklSF4NTczyUUP1Cq1kD6ZQ7oRzAxb7jYPNKegNvtlNN9Lq SpqZ2YW8T0PQMKq0MJ06YbPPd9ltKDuqqxHaHNEBROE67yyiN279hCdlacKiWa1k1gtseYrpCGHK hu5zHuuBXc/miXmMt0OpfHoEz+uJtoXZ0m9k5talTrwPbN4z2HIpOJbWv3Ujozmtz76QNcvqoRqs sUbKnFleMvZcTDiqQycabaPO73RfJRv+TeqBhtxAu7059ZIu1BWF3H01JMH5ne3mFk4lCJB3+kMM dv5buono8rgiTMzTloVltidgOOpyBVgDF6PJ+8SsyDkHncHHN2d86Wks47AMhXX4g3ikAJ979dQL 8NlKBCrWN4g+SxskzNip1C6vafQFbVtxbZCdeaazpwbsZZXHymF1Cu0lt2EMSJAV2IbaaHg7b5FM fCeBigjGejVAbzmGHMmNyhzg3ObLphP+bpDk4pEkzCp/Ql69lhbYNwCyRPw83ZRvQpYVCjpfKMP1 vTUxhP77/+aOtM9uEvO12FBD4cF1pPLV//N0vrQsKG/jUkUVROHy/3qHlXcXQvdvl965xF6mljvb 5mM9ryYpOpCHH0SDRBSlN2TYGRZSs06uunBAgG8W4ywfeNNOJZCZHVavBojk/9amnbEyJz4/GZmc TviK8CqxG54licMqUcSf2ffpI8UzRGrFMoYg9sZv//AW3U9a7wiVniQF+6i2UP4ytpgiwxy5vf6y oKEsn0HZa40OmfLfZeNZKyyhuALwiWqDrp1etHrYC3/YVGvX0xao5iYMiDJfnB1/CxgrXofvvJmk HqzC8mS8vG1b+0TdWKDpR4ChCLK1UextVR9F6Bs6NvZA7Xo4JTBmAbNHz7atufw1b0nrmTt8tPbs JpFSBpWD908svPJGIPtS7gdR89BxOY0EsMRM2yDUnbopbA1XgNQzy3JnnVALyPKYwHtzPBW2wamb ou3EjiJDumHSiLkkeVzI3/kPrrEs3mTrWGMsiYtF77Oxck7ynteiSUXAJluDyJY/+rmZERMKvYCl ZM27U2E8G1Rv3Xl/IDyNzEDObYFzKAvPhUEY5uWU1BtrlvpMyFVgxoTE0lskAcBJToJqW6kTDWN6 uPB+m8O+3mmaNIKEnOzAGppQ6fGgEGXEkdWccNspxUAdvDEBlC8dY3jtLNm7dCOQMOlESgCVih4p UCSD4NW0n1GjQzInr9La8iQecf2I+XyWnQ2lJoKnYTvI+86YYEuWuK/AuQ2anNE03fFUvULDrs0W FWgUmuRRiApDThEE74ps+VUuuGIM5x7AhTdOkTH3xEG1SOG1G0ME7ysE125GJwxRBnsI4eSv9fwd X7NTzqEWZeR/A/vsKWhD4amxLFj4iIoCUbAz2vjXQFFpwB2adjRoC0gUkz5ipiUd43B2jHU+1Y+f xtT0BXrN19uCuvj1M/kZOFoDWJtmFyxgMokY0rYCF0ml0dNos8Lu9YFiPNuDI5dy16PQrt3w8uAY UVVIERkqeur1nBCqj/Zef0bRGbR8rBbERyxCnhyOP1xe2mCC1tg+cko/5LL6YwdfTI3sctTEnVEp PlPOimYxZna85AXD4Da4Ublo+HqbHREyl1DyIbTz/bEAT6qMMly+LcCV+U8Nluc+rnjYC42bjoxg 1rwjWdpKLUb+FcUT9LqXIUyG4qID4tVx01CtSmNknJcXz9IoTunDZDhmzkAdRTRmLrdSBM3sTKhW R1XQP6YnDd5pONNXxAPkq8L2+lTd0GD6iosqMsddMBbdoidDixD+Yh6276yodu7sJDf6f7e/nvw1 6XQ/U19HYtYgTm4RD3AthkBxQ5MVHdIp18G8Lm+VKkBJjyQ02360R4QRy0KMl5day5Iu5X6Re+vW l9IE/hNbfJxnl3y2dCV9dDr9zZOdiPdHcC4Z+l7ocvNWSIjnWj7vHSw6a5l7c6TisFVC0DW7USo5 n2xLAHtE7AseuHYcVlBw1Ml7UtvwnZ2S4LH84KuIfQ5+g1Qj26vnuqwc/uTtMfg4nfCeEmDEcKCI jP5G7QeeX0BB+a+jySIDTj84O4UtH3XAtfYDeWEehtCnJGX6YR0+YMfmrx1S/t6YECnsyIZ5qz2R DbHYdR4WjamXp258tGrByaPjYAT/KS5v2NUnXd1UJysQBlb8/jTkuIgNcwNW5CYaAyOXmgVswUWs ZZdx0XukirmrSQ2iCeKjWLmgLQJxlmeJAy/3aFZMmltO2TwxPpD90GpGAag/0qAobQ8oRC+inngn eko+yt+mpQoy9yDJQiHO3KclCsZYNokk9fpu4t00+Tu56GqwDjLzpOXb+y8yQRt/X52wgYFfQsYl 6xmN+oBZ9yOkY6Ha0kg1kmheX4vV9kgQ2s/Z7m5DGcKEH1DORaKS8ExxpXewbWjstYgMNQs4fo8R 9LePcAVWy9TNAzQbjys61jwp5NvOs6i7+VxGJ7mvoUwal8Mnq2dniKwClY2SWjdQAMRtH6Vgu5oK 01UfDecVRR6kR21CbDsqD7u/e2L6T7Zkwk81hMdi7/gXjjV8GGxhfGkiC8Sko+mIEsJ8m+Y5N5b5 HlfhOR1gf2clO3l45/eR3DIs1ay4C2pVeCqbXtpi3oDapXii4vI3wYCU+FAxxUntEdnwrOEt2cfs hoWomybDQhlJ7Ihmd5PPP4kgZ0fOP1CyUjUbIzxW8ZJ1kPQMk5c/i+3DxuuO5WdvvZywe1O9x203 a23C7fzht5S+NOC6ik1HidRMm4c5BgioQCazuTwZH0rgP1SeHqT1wS6UuPdLx/LbuHtCjyu+snTD 4E3lyvDkHkdBaAvflA7ddNrF8gAsKAX+ts2+7HDKGfu/PRmq7hfdMpUlqk3z4My1HDSORZ3hpIU8 7xLvog+89HklryUgArQgCHcYk6lGiEjcE4JFYeh8fuQQaDotLN6LoLNS1z/HEBOCIim/GPcl/QCs V/52qvFgC+pOnU5OJIObpeT06IWg2hlw29qZAH54apptGCwlmKUnktJLKeepDDR+Yvop2rLZIGSh 39WNQtqEwOyO9tMcmABnVOCaApCaadKmmzaQJQ/KjdX3oJl7XMQlNP6G5d4ZgLaAs/VR7/xG2CWD aK1Dupg4H80sq+8yfriluVqLpiwLDQnKItWIOwrAtUFT/5YUwxR+EyV7BSvN0cYD71+9aLneV/WJ EvYzB0sH7AdhlYk4yiWl+mfKuFf5hgNtoA+VAVVkT/lO7xP+8GeYX9nSWWvUZq1TnWQ9Re+tpaAD 197MC1c2M0ATK39r4jt1IuSGUX7c4g8K6FpkkRTk8hpoabDPRFckIE8iw0ARzyFmc+EAM6TTTwfd bqlHbc/fquSEXNnORNdM6yeFmqIus30UzLfMnnd6oO9oGx5623HfX/A0cMCvuvjCdEQ+XBlvFIGL sefim9vM878O4eFYn+mIrP/akjdqUXRLvF/SXNOPstmpNmUnEn8EPJy90G2AKwImAud8Sgws6lJs haMlLrLPZBwAFnTN7CtJV3Z04dk+jqY3Tt58EIRdLMu3qJUi34vMVCoa5NqIwqyOQiP7RmDq16Xa NG8fm7+a3Gk8otHMtjxF5/R476hXKssKmuSdVqLK5e8cpLWqcWbDZDEWThxrsmlG4C2jBqQrtSOm 0+nidmOJQoX1O3t8rYCLtXNvsTW4HN1bCUyX6SDEJDyRqO+KnUQ4h6swEfwex702iXUTXASW6Yfi e4ngbv/fchqInYX5OUAkK3MH4uRwbiasnjsZEGwoDgsas3PSiPsbyoHHYkQR6Do7KNWR5qJWfzxn TCkvtzCy4Wcj8y8Lt+tCu8yerIoN8dhtIp7CXGmFDuP8xGzAihs6iM5WHxn5OBRuAyOrb6WBNeS6 7++DPlDz4pI433soGsZ3kxpCTrXeu5A1oexHWkEkmVSqGB3uf/Dg4yBfvuxZIJantxH6AHXOrR1H GpDL6S8vGT6d4IAT4T6gyBmOVfq0TabsqlZ+nGXSaksZjH9oDctLacpaGJzPn2Kd6Db/W3Pnq7Kc VGWM3xoIyY75NZ+gRim+282JLB2cFqYVGIoyGdv7HrewM8SZbmiYB8EsRyE2RO9IIy+1kEbxVf5d Ctf8PkiEjQ37KGQQaeaIeSsb6N2Jtw67mc0JtGLmG2taGFGuUpu/0F4OUgSQPahbibGZUTtcidoh NIZBJ6yfRfeelayBtYQee9tQrFQ1iXkrKPGa2pxZAutbRfcejRGqs3CBxQbJcK/9gqsx63GS6x5V obsVR2SOt3gqCVa2+GqYr5aaZJmkLTxWxzvy+WWoLlQmjMS2Jv0qIMpstX0Mxbu0RjYwcJNLaEuA TSHpjn/qrxHofGkADFhhM+Th1HFJ7jUVh4nqV9frnRlSh9zdj7Qr6CkJWYPCF1rsKP3OyMoGxH0V LVgYg2X17Irr9Xa2xanBCvGqfKccIH21dt973lCs7DYK1ygWOMafXK1bvwDnxD0XDtXlbjZ+bqSu QGY2DeW2QdOdrPNtAaRWdwQTXbtVPagml0GhKPbKVivp64WMDJ/7yB/z0A1pqEQsB0ubt2bZAwhT 30iASq8tQYusdELXIPIns+2jr1MnoSqJLqaTr4Bmt+5+Fb/wIUFp/CVJ2fIfWOqfMXbStdtcOdB8 E9GFZ0FAXKrQVr4AIQeHkWPRa6uG8Giii4qCC94DYCvMujqfrGiAfuXT+1OZHfcX4jMM9XYjQrQW 698hs9C7A36kGoZA2Y+FKYYu3Q/6U04LjkXvIYMicMqY+wZvnt2p3JNHb8+aYslAJadims2SEAN3 kSlTuJnU+x+qNzEEhytzt/a4ziKYDgHd1mFIjrw8/P/yyS4UGNCeRgwbsUoqsP3wkdZ5sdxdqfst zLc9LywvldJ+3zSkC9tV4GF5gBOR7CJoLoVrIg/Menl+p+clk02dshK2N9rdicfo01SvBfehST0T k3eUAyLv+o5KdJn+3DcTMoQnO2YlFegnwsCwTkxzlFDjKUbx5Vx2UXALigeNwBafU8JH7rqAGR6c 3HRCOmDP5/LRYK6B3P+w/mf3LeUF+UYszjvTW4htKZuhtshUkA4kJ28V6hbYq+x3bqP2zI5k1jFP becCEQIsif98LoLdjpXiUudBa872ErKrp8qYvb1AX7q8NLPzz61qh6OtWMp3IDwL7Z1581uPNNiF i3EJ292D8YKOEryNxIKw5Wa7RzTc89NW4KBo8KQiHN25U8Zxy1oNCHu0TOni7yuu/5gwA2Hc3WaZ DuBu92yV/yd9ny4rWKxeqbmTSseX4gud/HnrcuWA8y+2wINzpdb1bHuzlPIRkgBUYHKgfl8x7ea6 LyselDR5RmI92Z820vA0WNeZeZpH90BAF/kerLHuUFqIBhaoMnizoFP6vI/sTN4BmpDsqbG0G56C e9RcQ8ZSjRGI91UCMbrtwjUIXVAEdfyY8LjPEk5mCIP4Sa7AMcsehYzb2E34yTDm3KlazI00Ryet Q+MEN8a6juK7LctiMXaClrQEMyExTBra5dtQ2SSJnX09fgrpjQYgC6qxwqK48qoC3OQeNI0wY2PK 8XOrtGTadFdpTDPwrAdDIxNND+2Y75zNWOUC+nGQhUbuw/OSB6IVFObgy0Z2SPUPcQELiU3qF6xO ye3nQTDTFq/pJBy0iHSlaDE29MbYjytq8DzhcaYQ06IxdldEkB6LW3IB2DEhdAHpLIlPjweI1lcM kb4aU/p9xAyb3MuygCbTfUM/ykM+EiJgcOq4UIOvFrIotB7R+po0mcBCCsVclZg+UWQs0JfAWpQX tQ/Pc2tvCQCioB9PalqzFE+DE5nUee6ZbfZlceuqZ3U+wbaSV4M1l5St+zKVY8whbUW35K13h/PP 7DkBrcDbwius7CjGVZSii1yWJufZ3iqKwB3Lr4QWXYbYujm99YMHEBoyJXfh/fvd5fVtsVe5ByzI 6Y1f7qU6mQdtfRFC1g8KwlAjcAxcTvHrhKeozHRgrq/AYHZUKB0Bgn3Eo6fOESYySHYKqE0YjfjG jJ53cpMMIBi3upEJj+pn3+7GrCCS8qKHaXZPG81UqD0ESMaX1JmBy7H+Vhj/Gi1DP5OAEfLflQch EACrcg0vRKHpVfYVRdgXPETvHV3ij0pU+Z+9iRo/8vVEa1kiv+y8FRIgFh73/yWgE0jotlZBbIlj 3wVGi/VjZ9X5gsbN5anxHAtYvjXRi7HXxbCWFSQYeJ4ZA4Pywomcamv2o9S8wpT1vj5GPYy31HX1 MRPFyXmJwclVmLCC7giMUpC2DlpNfjJE9JOOyc58kIk5e3/ctkpgsYw39oblJnR0KrbbPGK0EBWd /7EgYzEPy/FqB4mMEdGvEyj0VzA9jKv0/O3T7lnV+T8lNko/N8iZMoDOOR7Yky6AZnOahDVZSUfl Gy88VjJ/osefAKhqeMR5g9TKmsJK5ESu+fOHWoisgYzf8RR7U5VKjpssekq0ccb+Yr2Fk1Px/Pbt kYC183wSjFvfQ+W9mA4Dagt3DhA6PDwYh1NHj3E1sQkxdje63TNOw/ClN144BEEFkppkoPsTVdl9 ZWtV6iNEuO8oInjdlDYhVAiw0BDUTPrG1filo4Ho8MWm+dtvDDW9a0XLy5Oovw59DkEjapfra1Ns rCfOvFAMGe+KAVKGDk8Po++6l1Wi0/YkH79x7jzuszvyNZCW9DOTNDon2ZrfawBMM78xprP3vEBV vciFBlpFyB+ZagPoZjDLJnkv1lY7KvmT5th8n5oyvb38MqZy7bHbJqUZI5ojSHWEsvovB5LLGpiF vD/nvyDsZmE6D2j1xH0mcl9b66HRPCksXs5YBRsnr1qBi7G1HL0FUxEjt3R9tmGMWhJjW+mCr4OR XT23P5GIELRjTvJ6eoDUbELcypExdoiVESHMImY/+8boClsh+MhMpRvRH3HKHq6OEbqUi6ra8xVg syGU1WoV/vapFOHZtrRUPvjVQIdZ92EJh02OnqbSanLYM4zLfdvr4Kh+3LiRwqNQkG+NxyW4ZoM7 5noLMqhQovmY4fWpPQKdWPBzPkisuDdY6ZkI0Cl5tQ235eNcDKrhn1HrE67SzH7UrPB/YElHI8Hx IzYRoYMsuXdQG/EyjGLw3buUa7KfpJSSVtvhODbt23oX4bnXspV66fWEBrYPvqmPTdJhgRyKaswT zPrcYMg9Suq6KA9Bq7BgNltSvJRXdwc9E1oFmR/QJn7BVRJC0MqrHZyUJTneYxlzYX6YWqnDpWS9 hpeOySj81XElsG7JK6P1sTouNfhXmSGL0fI+1aeKoXLUxAhaj3tfMZFLlnJsewcDF7bYPPuRDDgT 8I+HpFQOXixbTlvoBDwgTe97lbOnz78kC+KGDeffTpLwedY5tNN5vjwIbK2RtjLwB8OpmronbNPL BXc2ch7xWsDPiVOqxC2o+mNX51uXh7NIuQMNVf8qG+UtVSHfcTfjP02mLEX44ZqHls6fx5ooBIy6 mTx6iXLaKhzjn3pPWMSzbVVnoQK3latKs6LylnqZ+MKrTX6eWwOl5kLVP75ml48BRoUHC/esgAnb f6FIr1nwWeeQVr06wf7Bu16oHJkDVNps/PR8KByJX6K8GTagVhgDHC1dqkukvvsdjHklbkbI+pPG VnjkSqor+QrLG0l1yRM3ZPjAQSV2bIcuWgoAp1nhly4jHCsuxE+8agDUlfK8GirH9XJUzzdR5HqD y7/MGFTOw+7048KlEOoRXPV71nzk2TWisIGS4eO6bs5GLOFLpls6Tg3n5xgWNK82f0VuzsBvh+AD Ceyavhg8jSlRnvcgR7g+wF6gtJgkWOyKa1Zpah4HGU6a9YPb/+zEnzibvvoUwmQTFFZUQ6SiPwIz k1l/gXa3BWetb/rlTH4RI0cfJyDM8/V4eznknU1iodTqxNVdT2DlqAAORxpVHXT2miqW5HUde3Od gzUF5SjSbsFdkugHTP6y0YEmOVzpBMFumVgnm/1p2+wEENXspGSDWb/dyhKt0thoU2DxogfsymMh xzcJNo3bZjAUs0VuVSphaVq4N+Rx3K7De9yV5QZSv1CXBwhzshpMayaKgkDXLklondtaWATs1MNj PvvlWeVC7FZrtNgBOegJZbAqlHgtLvmuhp9qL+kflprjlxWgYMnxo+XOvEZjtXMmFTDVX2vQ+eqG XtvdkcDWOAgjcDAvgxpQo4ulY8cTxVMriW7yOAGsACEp9zJv07nIYQIUPeWEH0NJHjKxVM1gtf34 wZ6wlgYbwYY26c0RVpVZU0kPL4xAU9d9XIFXGGmxfl3jrcIjnETMe0WIMtb6izC/mgIqArzub3PG RAEokEqLVdE1BRUdWrHqNRJcraNIsJ6H22leQv1aGOg8V2BRyD1zUT3WAOq/kkCUtKgclrZOxRs/ qsrezePADnXrMuGjNDXWH9XmLusAqccfTfDtVXkAikfcu7QMjYI7m+1bCwU8d8UQN7zLNqfUxeyB hozQM2OxU9whGdu/6OEnoJLtc6euY/KEhcGwppAgjr+R/8J4p7rnbe6JYvxpwtTN2A5QtOdyFyJf 63/TLGpy/sX5cnhJ3kH+Hlj6PFvIle6u1fXe6wLaOdFgjP65SzZPfhkFRJXk32EWfs14KHBBD9Eb YJK6aYfmSDs7uq6Ji9BVP5ny82jSxgzTMXUo9T41zHZ82axCpNHTmXaiw9169rov0TX76/9iCntG +PTd55Fy9ZacKsXZbf1px0Cfxq+Pr8E7jC1HUTe3CeInC49Wrr/+4Pnor5UhLvW42Gp8dl2b8Se2 JG119FfUFnqd2oiWiWB4FyvwtGnxhyQsr/5nfb8Oh16lmNGpakqijBXsfGt28aRCoIbl0jI49eXj VLuJdhc44nNOyvm0jesgV/IokpFrdk6tCuYo1bOzTSfPBZjUjGEhRr0NoKJnxpyV7AykzxrpWapt jhRq+rMg0EnoCT7g6ejeoC6EfzKaG6YKVHrtt+/fF+2VoRjJxkB6yWVTSQLCSA0U1E1CsIZMzT0e bTAxacaRZ5vrVa3zAUwFakRnMgegWvF75I/sihwXgT1TSAQVtHH8lMolgxTkynRc4ixrny73ZyuD vJn/Q3+YZQcnm7cPaczaR9g0KDmsn6t205Mmk+BwYvCtoj42quk/xY36OW9tultSq4FyWYkr3URe 838V6woHbN2XmXbfXJ9nSxml6JPWikolcstUO3YpGe+bIJeJgJ5J8/LpCz58x4mwdhl2jrLRx/NE JZP7+T4RXbs/e+hV75SW8edWXRhfSR4uQyzO6ylIiKQ7DBxkzpymeguGR2KK/roGriMX7TSbrRfK rTlnFNQhOjH8G2hZJ2Hv+8tbQLAvF4i9ZKYKEyOpeWhjk3YOyXK4WkEsN3AkIGSg9CNouwMAXjkW ZhsB5+2NxId8UMROK5RP9LKLwy6iYEWL4LmsRiGGO0U45InDXCeRKd1EnH5AcTB4/SVjPD6443un xDHDdjvH+K3tcdWQK51qVsentlgTPuy82osmkr6tt7sDR7v/ffqJNb2dTY/J0acPZek1l1T4n7wb rwTPjAiV22AdibGeG+vsySLovB/ItJD0qNmLKqb8HsTi4QdbfOX0wzONcFrgU8sJvDva+3kvtUlI CGT112Duz9NGddvzO0e8cTTgd5qpKWJDhBFifFGtDDgywNN539ffztlM98bjVS4zoCaCWBS1GZ8i 2Dcqty7utR10xKk38bJPgRF6RQHcZIu5cvPsgZRAQZ0F63dyVB9xHEwrq81dfBBCJyNAMd7yc2f0 iITjboAhWYQxZB8QpdSMY07L4H+e2T+tcfFLoos6y/v1icdXhQzIC0dRUVxOBQYHf5gIWj9ntJje 9YDUi1/hg5nLaCXyMoEM+OvtgfVYBBLdhtVl+57v/c4+6993NZucmvsgi40UyZRYhDQqxL7cheJH aJPAjD0YCVq9kHulakD7PC2TVpgIthYHrFFZsfhRtfu5Sgs4hbCEEb2VhTfll0qtdA7mpjzSjOd0 cSqfDxWwT7BJql/V1qVz8tXz8T+ADNicLrW/yi2FOLHl693fQwju3fn9nWuFZtkZ1xBAOFiLqYj1 O2t/lRRfqIDnb9KgpR9YwhF9MDUrrT/rqMDlnHVxPRm3vjjN0Zi4nFJuPHWc0EDZq8xtJVVhFJeQ qU/vu4KgLsEtraRhkAZBYYjQ8jA7eh1NZsT4lOI0Fstymc+T6Sh7Ax5p93aNPa9FohhjHLo2c5DX z6YnRblPDoQC08qAg6Xoj4U+7xjv9wqnYtcdtUe9+qrtKsz+qwOPJiM7wnCZXuQjWQYtaXK7vLcd a6H3m1jUEp4/vLrVWeIu3t4clLnwZQ3ahPxEB9UM+vUzOwBG3jU+sXcNeeSWglOGm2TI//uNosSc TNPwSgiy/RBm802VLqIHM1gc9URFDGnlmzez8tuLgUjtJPD8VzEapAxP48gVGT/Py0iNbyszRsmr ZAv2MuL/wKSVIy7mcZFbKpJIUAFsAmqRNQFrsxXVaFMAjk+rdqnJE8vu2/6jkw4+s9if1bPz7Xg2 S2EXZZFkVJYOmlWp//00frCa3HU1/SezOnETTR6GiVADk1UdbaVMlrbA5FAwRXv5fGWx6eEM1AGi xTUd0xVw/No/GIWuC9ZWMCdOxz/kiKWiezwgE+s+Z7CiDxtHEtGtufwfhYtyAF1AbyTbEiPXhuwv +0CWKRo7odN8LGkb7jICxZqj3rm/TFoU3xYKiWsts90tHeoxQDg4AGs++y1iT7nCzxIIDaaKuxvf Tlbv1VxuJ8GBgzIOMi5/I3/FjqzjDV9+GALqvY8J+u5JlPp+OnGduMkzj+HEFSfwOV0LCZeBEW0S bpNdh/GDvO7femjUTR1xFTNi1xtYst+t4XYPNK4yVayAoD2M/4XdnmE68LM6pWksotGHCzaOohHE ZUafZz/x1LkSVqqX/JbDIN2oKJ/F5ELuURbTTAvGMEwrDp7XrqDmVZ43b0j6PVZDeCxtD5dKmwQL uyOXgsZbCEe9ZZVmJyeUXsRPIy066fnpnMj1kt4YNi+4JGK3QfI0zsAVS3fe54PvrbBhha8KYp3a rEInT0hmJxDtOwf26mRTvARpm69Lr++4s6VaTfhuOJghbjAEaoYM41NM+cQsbgryc9b2ch1C7GUz NSeNp5IR64uwNGE4acr8EUsAi5zs2F4MnaP/ymjekyQM8GzrgL4qiwX2x64+YQx6xAlF3IbClgBP UbY2E4Rmaq4RuTFSvTnXuW/LYWhkWCuVTHtdMjnFhYqnwxOFYrBptA3jnLrWreXP1xNpffJYQd22 mdi5o57gfNl0S3iU9BgEcaJ7S21UKI8mqy7WE3UnT2/UdBDwgw0uo4D8WupL9O8kNYXrdGeaCVju FKv5iiN1CiDKtE8EbQDfe+54Etj0KDX6BvD+2wjhlfj2Qi9JBn99CSgi2VJwKB8aEgVPpYQw0uhw bICH8fhGs9PB9LKZTojjf3n6j7YpPC+/hkBifqD7YDMRwPJsDu4IPDWbG0rflb0t64zsiX2AX2e6 eZxvTmLBXIwmd+665Mel28LXq59D76JaNb9YnNTc+ZG9+eDY4oBoCnyAhPbTVFops9WyPywTH+JO gfjGXWdDgPJLkvFaFwepU9M6OzXR5CWz5Lpi7PpPON4Krdyei4P2ftAqimnFTCglI9OZl+GGqmvu TWVClqQxlAQLamlUyGH7OjxkLd+eTgeMwI5IlfWMqB32lTW3NaTI5g11SKPTG7przq9x5HDyycA9 GTZXgJ4ZWO3W2/qzZnVijb/yPwBrHVwzm5jpyGCZWn3dbHkqDafbg2PD/EtyoMAeIphHNzvIJjcJ psj81nVhginwQtYjo86qlVBWuVm/EpNqjayFQbh8TrS0w4iyG15zagF0Swo+Q7jJ7I4UWh0jZY+o kFsKK7BHtcxq1wUNauahISHMg3hGSZv0Ymn/TAalZlIiQYeDZawpke7Fa3/CZwzl0yJwtdBvRmVc cGpeCDkvBHH7rpsUaJLELnbSoekaSlYQPIt2OmeM7xrNOvaT1FSibpAUp1t8cmcdyzjhHrSJl2mV Fs9t4Eqz0ch7lBk41xASDLDuBuBkKRO9Xq2P9CyzS33j75HVagUVQFZUWlc7q4rTuvKgk8jn2Pue qtjUuGuUYAVOCXf7e8UfvV0yE88WebDTdYUCmhOxwAH66veKwbmVlkKkO78eKrI/ObCdnXeVVC69 Y/pIr7MSP20NcHkS2XFFqNfX28bTaeJqhJ4h3TTCIshHTWRIZWo4mJtM1yx5i0b4jRZwICXJKs3y F1iNcUVtYNGWbcfPMHcZf4Ur2f95YSDT4K+I0ax+dApRxMoUuwZ6gsFgYSSGLcI/0Ae7iDkL4S/P DMk+1GUf/x0xRkDBKLBWooULy735MV35J0Xnzn/N5olvflUOiyMpRrK203Usjb1mUPtO4cjf3h9t IGl+2FC7XcpzYnHG1DbkDN0pWPp1inW9f8vSjkT/wdpjA5FNl9EN/cVOU+a+anCBfY4srfDtNDse 4ZvFt6H9aybRgCY7ZXyle6N+MqQASMJ5F+yrv4H9me2HkJmwIGbhKoNQWMaeqSCsTLvfzReBPmy6 RuxIwmneP8NtzsvJGT0aWbwQOKdVyu4ZwOVLp1Of9UEeOY2dEwZjlWnuMl2d2x+j3DNYAt/ppURs YETwE0qKn8dS764Er6rdAh0icjZlYYPwQB56oo+O6rX5brZJdgnu8+GSEA4I4x0cyiRaC2XYxUsG WbW0/pnqK/AY79IJlWEaiWNqw3mDTWM1nUF1lgldBfAjfM46DEHaQ6e59Q3cZuqYPGV3eu21s808 JjjlNmU+aIojuoymTllW51LHKx//XAoh6Zd/SAAJyRZ+qZ/+0onmNXxRo8W517EeM04cV6ArLaGK +klCWTdi3KN4prwYrSzdDGocJ+3kUW6g3oikzcIDCX/pr/Bc1AcfZfNjUC8wV4YvzdsMTbyQESPY TGVt9HUndYAKKORuc2q5I+MD1qiNqeuNJ//Bb+6OqOv/0sJhcbPYYaoyYDKlNydsRJvMCYg41Z+T CdyW8BdR47qUld63sg8+Cpc61xVbFlBGd3IUDXouWELl4hlgLOpiEYNS4QPvScVpdsKiDujhRth2 b/pETdunYnOoZlM90IdA9wxHs5uCmBHXxQygD0oo06TMcDdIohVT7T+EqD50KdnlcQBZXxMkg11p WSnhno/6pJcejpuBcLR6Xa0h4fuI/a58kRD8FgV/cKLRVvchf2owFFuOW3T4si/QwJr/lMFqizIg GJJDcAHiXhpZPSNZ6CsIm+ufTk4sw9Saw5pfJV17D5cmfo/kxmJJJwWjBDJslsjJVpHuuEeT4d3e nueSpFBqOUFqmT86NkzfkjmVtoFWM6Q377OtF/npt1bULmg/JtPYzvP11g9AVrYUr6t3Ka5nPXvV kw6ZawADqq08a2UCabxk+oUspdATED7/2hIyxVwSzyb2xvjZS4IEYMpMoSfGo9yAu7Zmho+oaqif rukVW7TNMo1tdCml8IqrgYY7c/1zQGcY3z2PGOjWTslwaS4qPbraBbQwrwR6iw2zwlpzO5zjH4wP 1cPZUFXmiItXhxDPLSFbuaFEAnuPekgSoQjthce1CuSwl9bKTXGZBFqaoAFrvg2ei0LR8J5FRvO7 iKldxasCEECDbw2S4fZ7LBL/wzGS1GL3DU5SLrYwbOz4ivIcEWY9xOj4dELSIn5Takzja20KhCOo G6aPxx4rJyk6gvsKcih2KZDTiF7wP82JF2n1/Uu30WM4bqFJxhuhlvXnqqtM2LnZfHzEP9m4Acl3 BQ6PmYkvMIdf7zxK5ekBpDadxG4SQHACpofbsvVKCo1Q7a4eYmze1X+hj2oZroTFJ2b7/zgAfpDJ tTrS6xQ48b7eJhpmdXZEjD+et8bFA0mFXwSMaKfvL+BTRkLsTLHjfy13Nx1GfE1jdcxJePjUGcwv nXtCxE49N3/aCAyK1jQXgm8kDi+Jg9CmdWcd1Vue7WDUN0ZjUT5WBvdyTQXIzq7PsqECplmOLwbB um0TRQH32ivPNYuclBQ0bS2vzbi6GlXGwr4uSNpD1wtKajOyE1qOmvadIg1EyPegNYQTTPLK9lWM F/FWIbUga+VaQgtxuunsjffFg9ngTOYnXNpKcnLMINy/peMnHcl53ApEheB14WnY9oZBaWcq3BKd k9YUGucFBABM2/8Esyz2ehd8rWIdT8DByeXaX8/MqT+f8/JBYmkdt88PYP6E6nrSuh6R0Jsm85vO VDqykX+UNd5q4KKINh/gcgJ0w+nPThVyvQB4XvgmJ40c7SWtd2cXcyzieUOAH/rTG4nRdgSdx0tE ulE9yK18StY6EJsU9krB8D3h4cPS2APG1GRbf+e4RmQd4YE4HIeOKOgbcldJ2n+D1e1Eip6/xX62 dPSuvFtWyptafpxXwZ/ZcANIGMnv/HfkMLRJ+PyvYdofOasOMHluLVPp8u5cV2PvRHF8HJPT7kHE YAegh5k7mzLzcFYhgIAtiv8eT7bk8N/Yb933KgTZ5gSLxZiNrUwBS8OU5e7WwwtpnUydeN77Fr0l teb7UkKtWg9C66OmkfJMMY7VrSDpMqoZhYQWqLkdss/1+dv6dWuxsGYFqrBmYWlmkog1pFA9BhPX j+wyEQeRIgRYEK8DwkLUgqYFLC5wq3fmgzI+pHexzEcL6qvkc7+w0KoxEEl+s/UCF5nRoBUWpnnu gxgOSSMlykOA6nSzBzkudC5Ew0GAwbv7fIft+SN/UKVd8WJ4LhMe77hj7KUV43DWuBHa0NwSuwqe XQ29zFu2fJs6Loi50n73IQA1hFlK/63/RNaTaTcGyUw6D6NcXk7bqx5DsuMIEB9EYDMO1HfpsLwh 6YOeT2V3ggx3c2e0jhDBg2tDiuLD20oUnHjcChSulREC8TrYtmevZHPRwy2/L/PPbXAQ1pH+d8Ep VjXVwH3fvehgwWFH99YgCLN9CY6r+KbrWesNoIg98nw2CRJbAQzS4sikB2TyuJccI+GpNmvrpeBf SfhftTf4x3vwCaqTA5EHFaJaj5U2nBwzqp4k7valMZdl+kVjGC/xWehP1+DUloZpdQq7SBoUD4rv +eECfGffSag3pwXpuGX7JMAYqCOis/9e4xw7+sm3PAOD7vnP/ArmoDWT2sx0L7+F2TkTaGYuQYZl YbarlaaCEO3XX/sBkDyGH9XvMFE/xEsbxpAauIqfYuJg7Pwf4snVBO8LEruXKkxZXZMVkG9S/Ol5 k8pAai5MRo2ogT3WF8HnEeyY2UToFoO0dc0iVHyzqlRyUWbs95v58Ct0AQKZBZi3EJYC/DlqkVTs igF5bS/LqDaNXC3Fo3td+JW83OonnEYCO+gxLJok8aZtkEXA8Of0/Tv9sa2eTzxAFMTwm8HLKtwS UHhe5G/Ft6oqZTSmh7lulPjXBC7qqowoeDxqPG9sJ0NGVF/rGAdlKPAuEVQG5GRml27qkw6+Y7fX y7VPOQiiFyB+QmK4I7rD0DMwS8Nsx+tD5NrhAmZW2u4rCGl22QWsD2wICbr62FNn0j4ea3fMZuJn m3HXHfOAE7TbBMTv/MMLx9KtZLl3dDqCuSeNKnMC5sVWRsGOQia5nGLCe4QvdnoFjatzLoT1vaPG khkLh7PE0C7L/NDCruCz6A44iyOSiZk9Uuo/Hkz5aF0vtFjNqRFhg39BrA5NCe/bMDoPvguaHDCR nL2WHLDT2JP/ROu6YEjv9GbkdXkYHKY2qw6klRA7ubTZGq4WJiU6nf8jvqhgKBQGPkF9cD5fVJ36 iHfj4AGrCKmpI8xwOIOQu0l6QVpfi2G/b4WsVbybvH9lpboxBeIMI1KJdre9zT6GNlEXsNuxaDIf hJ8TbQsoOnlokzbOGOi3a69sSgebcaz6Na+tHPj/bu6W/8nF4KaXn+I3wZ/ley196jUJLrX+pgxT 681HevT0kQesRaE0zgqNRG6tVn6TVCmzakSYa+DZ3NKIjaOxERzAqjY3qBHzbcjy/+hqjuHx8jIo ZkmVdkuBFZHMXwOXUu17Y56zrDcCIApcxnUuA2eOyuuMWbfdl6grsc7W4jeZTBsOx4pDNF9686V7 X6SBUGCMh+UmAdCa4xBBktnWR0ozv9lTUB1b6kxTaA/S0a8Yuy4DcFJhLRSDOWKBi9S1ZHMF8CjR WA/VUaas75B02gm9HfnKumJP2oLZ3ZOBw87U6R6A/pr3es3eiupXeHr2K20YovNaAe2WSzUrNLgc AJg0r75I8HkLDsT2q0lSi5Dr92EtOSUTYMZg857XxpEKftL/mKZd9Vke61p/wXFxvPgLJdHCfrm8 uuBN5zcLhFz+BBMiOe5AByHaQbca0BhUFwjXClokZqtSvBtmE/sQNXej4m/HVcZTRUYnAsF2x+P5 DVgE8CB8V7Y1V5qdNX/CYm7RguBc3ciEhQEZUwjQ7Tl5VEsFX92rY/c7TfKrp6Ci2NpRnn9LXe9t bvpASBQ640z7GKR+/wp/CiXgOjo9kLZ4CCGJooFBTWHSnAcZBz1Gzg5C2XaiTZlVoqB5Yv5d9BDL 2dvWbp/rM6TiL/+590F5vcpNFPf8hMaaj8V8btJR8OXHj4zeoJ1MwVlbLsA6hVNC0c78Up49eiPC k4E0ifn7MTIcFTaiuoo2kdEcm/O6+8KbrIZ+zXV0DgUQX75qQySHrRr4hfTfS2bNJRnvfJeSYUWX U+O/zylvY4eHlaTwDQGQcgbt662YkvwuI/D+usD36CBv+PO8Ov5H8awL52fMCa/p4EHKVrulakew 02PftNmjyp7DD6hkweQjc524vfYsqI2a3SLp0oMqxtL8UjdxNxdTqZyEdKp8DIGdH3GuJbmLUoB+ AxrT3cpWeEJnJ3fJvr7bOHR74PvD/ro17lfIRCOy/L2dk/jMnpWwRlRGvvhbRazyVQxx5lxNNWbM WWVSO+aWY6jJwOuZguVwx20Wwg/+WIe0jhZJBgNvqQ8f8NQNY8GoMaDD1mBu1VqBtgUTjRZFyUqO ute+O+5ipRNG2hVl8lhNicEkPz4FD0Tknof3NfWQEATl/sFKCavHJF/4BxiPPa2OowVbQCniWJBx 29mcvTWcx3c0CSeB0uCrVVzx8ef5CoU1Wor6kL3UmWfcaTxeNRFDGK9LSTuzkdozn86ciHIrF2IP womR9aYXcvx+wF/dKGVAnE/3RSDGaxSYO6IODItVOhznalKojNuTRnhxFSVRnDGFWNV8Biay27dO 5nBID3+zhb15rGVp8QXM3gtgphNLE39LjeMmcM5zwaTxEFn993ktJOQeEi8kdNSRFxQaPDr9mma4 7LR9XZmujS/RDNgW1QSgDxbgJgaDsgh9cMyibbCmDXnLYnsXGJOAFX7qi/o6VU4aR+zcjBktlFef Uz+fJT1nBs07U4IYQnfRMopSyt2UkxPYSoq2Sy3rBn2MbHpRQmtsqT1fIvzuwKZDhDe0zQHXfmZn SntoGXl2LaoWGTNfLeY/xvPyYO2qWH23S0ZX6lgnx2M6Zamhfz2agv356tgWWFKo4aHqqft56uOQ ViQfFS7CRGTcXVakFd/1no8UoDpo9234z1DAWhkn06TPEqDLWHeES/udetbLRjkBVqeWOUNeW9TC el+pUQXOO+sCPz8T1Y9WAH44+6EkCrihkWg4wUKL3H0MNp8hx+dzG8AcVwOgAWonhFZyZaG5DsQy 2mW6phhCZR6FSLALZVHfaYUf90zdpROzptcVYTKXRNcRKTGElq2f/WJEkIvglKg3IDCwKQGQ41qg zhe5RKCwP84kjsdNj5Ts0d3o7NO2ArcrWybxH/rOgKJk5yPkw7P0aoXPY0m4WmOGd3bl4dl5jvxf rbxqrqOz2fDbyJQrsUqkBH76T/kBs/OsYjkT1fbLaT+2Biiz+1CRO05rcYFVmbyWyhYtyLaDfof0 CMMkT2ik9ZnylrL8iKVHFWp49OSm2vmcmizYV+hO3hor7xp3UK4eqU1/VX/ODkeSDzLO2uW1CicI KMKOeYzYS/eKgzlhs0Nz4u/40rKSo8mwragYnsS9uiUnXhlOzEpS9isUsmMDl+wxd4FRBjC+sELn XI7eYpvayMX3RPkXTaEDGpqGnG7DxuaC5GKGnoD66kFZHSo+ud/rbv5o6yQh5o9J2Z8zuHSv7zN3 gauXcWMNz26mhhTgrCr91TQeagyPqA8EIGBuTyOAVa4fHET4YkkoJRpon1MCIEJlLPRUdbl8yyJs BZvHx9XsQUmBZ0DdER+VC6s4gbtrxzMr9AtPqCkg1zlOhdfcowGiYcaZHItcHN9j2FaIZQyPECxE ei8VnW9s14c1GD/e2kIHJGOAFwBAhvoDP5fdQzkWTce8B5g/oR4thxE7f+bFV/gwqvcBsHuzrhEQ pBwF76HQZvjLwKcQBpup+PwWTCOA2Qh8GkOCLviKXxBHjbjP11BxF+cW6lgqoOCz/CWVIlvaeCah uRUvxQFZKqQ+O8ZDsAyMjm4rYleTMNDUQVibkGT/bX4LwopY59hlvG+EMAnz1z3fQ+KLb1Mypq8S xBULgeKPWx/E2QvePh8S1pbIFA+eyfMReX7Gynnmfa4lokIvGmdiCWtiO5FWJhCOgSxU4+Xd2cJn pWrBFKV9V1PjZyEnjRSkM3OZUFFLqCLRJsG9gW0ODtPKRLOQ6SuiwpXyqUmJcDiAImr7Hf9oLMwb Y9b90+bhfSPTEiiZb7X91IbZWlIoi0SSBouSj8+EJUBPXQqWf7fOFqtwCsTT/kTee7FRccObvcQF 27jK+q/690NrSEkuVlMElLzHa5SIAc5n4IcgHEB2j/hoAuoGh5ySnx0TAQhOtyTKEUjz7YkDyS9L 2FJ9ok5pm+CFdickqogbf9zhGq1MKAp3lho33NQibI5GijRwMop4QdFdmyM72bzQkj126RkwcEsk MPMXzOVwrm799aeayBdsrX6n28ONsUu7ve5OMpNMa7Cy6G35+jHF/0gxk/O8oft0x86v6h0b6XiU Wli4bbCFkE1nqUsV1yeq5x6per//VrRHn4zRMoNe4TWTzm43eQF4Vh3fzKoyzOHiqpcdpPgcFNrh GLE/3PTRth++7PZhhEjc15JztCCoF1gZEVFdacdGafqHXq7R66dZxEdZw/NQF8l29PdjjfYxJA7L YdNcQEXihjiiZdfJe9/eCIdC3iho/kQZfu7scxX5ip3eKYt7HpOhUTnwQho4qOTQyDmNvyx6Wzc8 eMJ+0ohaD34pZITy9XQ5+UXqGX6Qe6YTGkIL9LLxAo9g7RGvXTnl43D9pxEpeLmWR2eyU9ETNdmz pEN1FHZ/SDOZB/53COTP5WPtmQxqUGmTkbG7CVu7wdTPlg3Y2mBvpToSdFz5HcxHVLQGZ+2ZzOe2 yGgJIlb0LzDoB3zVUXJ6KzW1+L9jFPxyUBrxztfH6k9j7XDBpyWfS5D1V7/ZCSiQimFL1XM1DBCW CFVvUm76m+vDNzqpX8QOcIAGrdgV10ovukgEGT1uzQe/zkqgFSzThaFUhtD2evxiVE5VhXUkaQTl pPwJcOyJ05MGiPvt69MDLk3jADndJa7UKXrjnLi04cmoN03R+1/3njAasFzbWhr0Sx0qXMe946ey 2q16qLFdSvplXXW0r74Pb0fg1RAk22W/uUc9R2HZQ6210awN/OfUVZKfJ5doZTlI26hbj4XF9oHr JPfkzzGGpyBrsXWkjr5wJEDvjSlZpbEFjjEj+GFUuNab5H5YppO/bZ4XGQn2tWrx4MlFDYc4vArt 5kEhJVMeORtacrReSRdPnX8CE477aRMYBb14DNFweErXJDwK5a75WsKepjpQwE0o/26DjZh3KoD2 +/EElE3aQJKpz2nv7Pv6uBlBHU5DFtjiMFpp8J+BJX7Dgxm/pdw5Tc/xTSwmnbEuHbnM9iwnXKAd AECeaeWf8NF0Z34SCNJEHGSM4qdP4USOukIDhaik/ROPzL/56Q64m175qzL21GLOIOKaQwlhU9ZU v/YwgC458famoWWVH+O20x2pZ1E65zdKqZVT1Qg93WDlTtqHafY+pBBMUQtxEGs064Z+Wu/GlmNC ryAp2NTH+7Rnahyzr25JJsg/U1h2nJzdwh4mxc2nlp9RyrBSjMtHWorjZm0q7eHOf9NtIR7GXdlK ImYHFrboxPv2t6O45vN0rDUeDHIcmSfIIAQqkAc0ZNFuZmLq6yDiz6RaO0Ak4q+KUqvSvdAxBLOr yQu+wZmKYgAZnLDevbaxgm8dgyxzJkmfgFCJJrlYwR7rDfZcoFHYv+7ALrRo9PPxekbeJoc5SHok SlGb9kAM4air5iBg0Fzx/CWUk/jnMeooSVdDxgv1rXWjSYB4vb2AXie38EVoZVGjU7qRPMt+jF9o eeGjAqLz1b18Swg95iP1Q3feORgd4q+Q19IRqtnBHJuOuBpdvTmleRfWX3Elor4mB6F3n3VmsMIP X6i2cGjfA4fQJrm9eI+MMjxWqrQkR1BnQongHPtQj3Rwt7wdxoeh4vMyQPqumYz0fUzJfw+VaxN9 iJKZDfqQ3XdEAV0apAZpxr9m9Yzar0TjJgQxjN3hirPxUJOd2z+Z7ENsU2kpRoB1486wC0hedN+U szhKpp20+qJUWzoH359cxfU3w9t1AMlt3I6qd4pwd/1hWkVJ0WTXiNzEZ+tEwTVSyPZAM2OpNDaV 9ltB/YPyZVG8+iIMvftcenCqe41lAL3xk4nPvTa18soE2ejSULkkX0KiRh/cYyhenz/E9rXg4ORt Oyk9oQ6fRiYCCVj/0Ml1qayBXDuvo1OhUdPn7FcyMPz220Fg03H2ZuVXb+j45ze2Wg830fYTSlFH tbFtS+CZCCdL9brTefmfyJ6JrR4BIBSPXulmntKugwRPK1l5YJd6qtWsUHscdGZFrx2ud6c6MFaT s9MP18spRuDFoe4S04AtCbXQb9KwBdfxbKXOtWbcA7+n7hi5TApshq07qrbpagDWSV5ZVbeSkBSf WuWpZrrESBvm2KnVyz1/WKLkVBTvmVcyaaRgox0wk20q/+JWxlQSNSGZSTzbSV+lMAO9ywL4S3YB fCw/1TgEC+aek3Yq6zfPoCTtodne+/rSDixT1Epuefz0Mlleu0l3dFzcskFxR5so+X8QQqLZtA7C ylKKLtdfVsSLLr0OKUrO8CgvsIydCtGkVdINS44dGaPyLalnIu2N9MCZTnmWte7QCzsF0rigtI+P OS/1aTme6kY7P7WFydTB1o8sosbVacl2ssXNVKRQk2LrDbjpaDha9NNuBHCE7MhV1kTksgu0ZokM olWrKX8LPw9zgvRAxgFBy4pg6C3mNbZA66YkvuXatrw0WmfODWULgbfo/x3QLNxB+Br550vQUgwZ S+TbUEc7k4QOHV1QpyRzaFh/Xc1tbPkDOOMccqrxTVfLABqrzDxh9yFwXSjgdOQeU5CTahzQOC4t Lv8P0m5xe+Sm5wYULm7Bpp4EE79d3DIdlbqz++3Z3pbBMuSCw07Dkc8ocZPBbhJnrwwikZ8CH/Eh 6HqKm8XBogqm0IF3ZyYR6ZXRIFD+WlwhpAYZGoxdw+ie8PVHf3P1ecCZ/KCvLbh6AYC2wDEZRAgR kyVej49pJ/vAanKqafADyuWzSy7uLobYeNIOQ/SwCG8GCw9R+5ml950Ifky2l9QeEgnjuOPfhwgE 3Jgt7hKxVCX9PBaREl+sn3dnTKW5UibJbTFUl7k+NcAtIgiUNqatc+lzDhTr7Uid7UmnxvRL9dEO 2Kd88eNThscyrSffuymJZMZsDIaPkDPOtQP7rVnBuFHHQuqxvw51udg103+e/IFdU9BoobtvxgqS HKocM/MsbRzHx8k3xguTGigM270qYsH3yhk9GpTBuYuU+KsJVhbWnfJZ1uWWUgzNxcCPtJWhV7Xq 9d26qvgmA2Hj4RjPeF+fmPAV+PPJ41wa/lan8BDPPgU5kP3VErY5wppxUfcANkvt5O0IXysCeKa8 MIt3onkStfEeXJX4jzyqdfF+xXrt4waTa/Wiyt4qXAqtxAQqXbxJH6dhDTKEQFcrgzDy4kYf+JmM cvtz7JneTk7drx0jbGB4Fy3yLC2ItY4/M1X6RCQJY58xtyHFl1VEmMUDXbrGYkxRIfFomEoTMFP0 /Wb3ADqnkI3aL6ALxDe/WGLlcA1H0VlG/0bBvxj8c8AKOTQHeOT4XCTzDBPaRCCoxmdPrBfv5cnj zs3/XTM/fE5Q2yqokXXpFRpt6lNY1EMtzv63LBkM1XOsZmMDAQlfozKEKSCEenuwWzFQd/xCQtQZ V17t+3K1I3ruh57MycZ3065qb3rukcwWR2AeHOQhsvvIZ7WL6U9Kyaw8PVySA/VWcxgfT9gQZ7Mv R7kja670oRcGEVoCI6M7HtKGX5jy9iJpwrdUxV6zIOMzxm3f2mvuaQiD/1ZmApMXNZ3MxE50rJis O7ffMIWGrjtwi/DP6Z72mAhzWhb8EHVjeyQ8Opn1AGpfcN6o9rPiYvbcEq1tZYbrIITdz6qsOB7O 1BAAB4P9z06E2VUhuI0/GV3ZiZRdxwSMfAIguk17PDU/M7K5KzmTYRQzjBzTvnyHKJ+WZvFdjt8z YzydVwtqFgx2oDmxaaPvd0Xt0frI95ODabjUIWYW31EEHevW26sAkDBpaExOCGt58U7L20EhuzLI WAMbaSrioGKgr0ne7HnLRRWyIhJy4S1vh/1ir1q6tZ6ana9W2KQCLwk+me7IA/V3h3GRYdEkVLEN wxKoKpSM+EbtexH3TBkj6WcRpwjd2BrSd5DENDBKp2iMFLX4kB/JmpeV0n7xHeU26UEYGp0e4j+e 0sDDAJ/E/DrQvAZRflWcrj/SIB6QBYrotF2XuHT0eHAqS+vtyR268QL1+jw5ocaLoojc0gVDW01h igdnw0mNkr0f4pT48bk8wr/baH1PPTq/JXD2ciXh8ipmkbmur8l+Eqha3KHZazL4sqyHiGwzWrB0 LH+fi01KqzJYVVmEuGAifmQMAfQj5GMtbYUrOa+1C30FkOAqmn17xsmMvtBOPPwL3WL+cTWJQ5LQ 94zkG5uxd3U+KUUTWV/smrCas8bGbJtNkry3GX8OyqVyOxYjORBpPfY0ug9l11taZELJzVLmRMYJ Hhb36ownCfxaZCcmWtpok95BKhXvfCTADfQI4hl9vSxH0Qba1RlB3o/5vT3s8PBiV1RxFhh9ccJr kxFwurlqblc6QKs5KsM9Cb3FdmS4yWKJXaBAblJS/q3gafxMlxljHNeQLinf+8CAEa407I0VNUgz Phhsvc6MRE+ObETK/pn06ObnjLAEQzxJugBX15pf7gwRqmeGQAyVNg2dxuE5Jin8l4EWmq/GT/pI qI7vxK/UI8JzStzGnmyiKhYuzdU+sz6F1yYG0SkiD1prTIEQ8Yhb1bZqErFlFqMxn2DqgGBZkTji i4TGGrQ4XfU8HOFedNh6dsuhPdZCWZ9+qLpD+fifqpLzejO38lGJaFp3ODmnYfjxU0rZj3eOVC7o 3QhzvzoXaa1S1DycuYJaFwzTfguAF6sEuHy+7JF+NiSG+ppfGi3wdOMM0bb+uHTbTZBfYChNX1G7 OwDvIU0JWEQGxZoQ0m7PiAiatJl5ARjPhg0H4AFmMa/Pv1Y3LL8tTba8uJdpiBwn+cGWlBcGXueM fDkqCiJT+gNQqZ3FWeWPlKhU2OHiPKAHCqr1rJx2tyWlv1rJvP8sRMWF6tz9u3EqJa0HS6fzb4qw c9qX4aSBpUj9KpkuJZuTj/RFfDr7cQmThSoSZnUEoVO3wZ8yfpgUj3pUzxYLHEnWAGgRdpqBQe8+ oJbdqoBuyuYNTIOnIEixp3xqApLdx3YpUPMjkzS6sIVXPFhBOGJbuLzcj9T8GKDE49mtPkwQZnoc V6xyhhAGoiqZB/Lucb4WPLfNe0l/kDsdUBnudMpGzeyC7GcC/SQZ0LmN5rJyOIwRSoNwZ46gx9Tw 4NPeyxaKpA17xDT8YiKMtoCDDwtkzvzVJcscc23rp3yVyBcTnT9T0ivcSagkOWoP2gQNpNqcNcix CUrBk7zHbQJd5Rv8ib+RFf1/AQ+ENSvQrRyLvcTFHtwpx3IjcuTXoHy1owMjvp6izAb2FNJfDTud 7wVEPz0csS4b3uRIDFomiGOmdRvSYci6uR+GNlZwfclh6/zRkvwrDxcC1EsAoNuvVKbG+3Vv8MWV 0q9pt53N96/yYPjmHqXfmaC8ex5XVoFUpGLllgsvUBuujzPkTYZogs64qVF6+mM4LdTZRXUXnc/Z hTX5LvF0KijYw2kiwwvj9Ngsu1Phf3WHDDDD6TvQprc2GeJAryRFTyEgPJz+fHLDYwv4r0pZjHb+ LJuUQPuoVu8jpROXnXlwAV17KY8drm8AnKMcNfiNIRZ3i1n7qF9xuVbqhOu8HPeYU3zh/QQsP/tI ZeTXBjK2yePrrF1cKBtxK2fI26t3nGanYajo7D3msfYEqxbPWXTSiN2RtpZEI+Wn7hzGCAU+4jKS mPR/DyPrGtWYmUUszYMXO6AaSFSW8EW/IB6XKA6r419EmPrFuhyZpj+8PzZFMe1OGnjsdu46aWEx 2+7DQgmID8vraa2An6++35RQlY8gq5izik741MlrnQYB21FJYrcKyNdN8CwxnzMbHuSfRvN+OPR0 rwRdB9zD79bGyzJkQsIJYDguPb2itbeuUN+AsQmI6FeoKVc9Dif5orxMZBBykEcRTC+7O/xPg2qM y0bs0kFQxnzHeU3vfVJX58Q6Gaacrkvvd6fmsHHoJWDH5xtyE0vcOemiDty8cpaGwWB1/4zjXSAC 1nzCfHVYHHGrXr2TlTF2sSVpIs716ROFmLhQwns3BPSmWpDw4ufh3Zzem46xDHVUwxhCFVP1nOG6 caAukuY2pbZWslKuiLGu1yh72nLM9wTWlUthnivfKXBgApjpsWnu5tsXZ9GUswuQxfbhXKLMYQgW 0ac2DN4d2uaOWHznW3b1wKA8M+9VEOfaVHoe+OVZU8ysmbyOa8SAdm0ouCNIJ4TPjeNlNVqZPDSo xtwZrFdX30kLYROmdCSiBNRIU94U6OGkEtq5ZggNvPYTgyiD2zONOKj57SvlyT8+iuqPHjLCgRkG RtWnPJ3COHGnKH3IzSzy45UDf9zEs1L7eMioqLMTCz+jT5rvEASrYgGIlPsKWTr13LFeDGPZPFZF +2jcZWK3QqfPJevSRpp8oEdVP8cG8so9s+KMu9uFPBXJABx1YDuTYFrllTLrQSusqiu1yFXoCJl6 DdVL6tIIzIIVoHDJhVfcNRn7JO+6hW6PPSwgdMTrkmLbi32Rv8+C+gp0bOwSwLg/R1zqInFj7vEg frvjkvCXgTgtjzX4gciV/imjf0Fd6S+zryTF6sBaPNecHhW887Ay+wpE+egSbusIXqmWQWZxJvhf EyCkBDUBBG/XztnLLFSkLpF6CCKeIt4cYUN1humovegEGDFa5E2xvj+OlXdxjVcN8PEszBzemLRM ZFSLMXOnnQ+47b3eLscpCbVuAeTM4yjzQsYNv6jnb3M+z2TQ37UiXSEtt7pq+c9wpT6r+R3IQ6Mp 1H0JsvlIIGY+gmN7ZFuoKNSxa7RMwXarpwOSm6kUmvxuPSJg09TVYk0W94XIQ69HiIkKTTnh2Oa7 SV7P3ivp+lSR0qzX0KqcPHOqeWsLwHvQHL/nfwt9Q8I21IJbTJo8HLFggTyF9BD2DujMnIp9A8Fq UmS70g2JL4wrLsCDUb3zYmv7asC5fIvvIad8v7vW4gILnhF1+DPRCFQplwPE7uC4pwfaGEFeRoqd uYcMrbEIdS5ghXRsbS4j7bmjkHVrnJFoGALTIstdy4dWpHkb4YeDa4nbSMSd3nPSaNQGKLe6lrL9 t3PDUvR7D+Vi6EBXhy4ehNbRgcFRlNGMcpyBGSwi1wJM43nWOn7LHAMn5ZzIBU+ac/VHKhKsN17t wfb3RBVRPuLfbtpDBK2oZx0l570payr1E/fqGzx8tWGev4Msb1x8dCkDS0e+Z9D+uY0NuE2nMkaO GknGQyWqzNhLj8ITVR7yqcUJIRgpr8oivMlTZV+XFNLTF4NQtKKzmzOpDj0k9T8UWZWsN1Mtt2Sr wiJ67hTNPOabF5X/nOeG/HsP0J9/UYiBDmX511WxpORRVJGsoFfo512LaNFqroECrH/zs8n9Y1GT NhuSzOgrpybh8J6fMgP4IYB7hjEDzpBlXV7aWC2sDWl3EWmuw460w6SoMcHjSUSBmUl6/Bxy8J/o GaMPq1rGsSzDWe/qxLHUpmHLD579k9ldNUNVanCeBGyuEESfrrIOXRfGAuaXxZ7Um85elVzy7yDv 3PvX84rG7BtyCT5RRAbSjmEAQ7n0Iptx77xyZ80eRA3rE0oOQ5c+g6ZKGl2+HSS1L2ImY7+jh0oB mrVHsNcmu2WpA7Yn5D8bsj1enTvDb+/V7Fjr6+KNFYF14kdhjBCv0d6a435ZNRw/UOENgaZkjSQQ MhiP9XKXax/c0Be+o+RWf38cgMbYZPUVPBsRt8O5OEEBNgqSsaOrZ8yeFCfcCt3YGaq1djrcYoFj kYI5aXOQa7lYRhUUA0zSpUEorHc0v5UZFsvtZU2WJQ2ui03yfRh37m0tJAjD3VYkhKkI4kBlCxBe YvgJnp8myspNZ6yEMplCkY9KwqwgJrYnX3tHGr2HCdZzrAWRAAgH0bRBbnEgdJAV6ihy2S6NSxLx Hrp1mrO3CncuxvPJAGR20Upkk0uSxdO0j1o0iJvi+hD1jYQXjLClaHje1rUJiA0kkiNACp1C+ktS C8sxYA/PwGOxAELlSp5oXhYq/s/rJGl0Q3O3APBXWCE8DKdOkGKdBhWvnT7gSFcmiU1kndfFtlBB eNSkIS+acyOvmalYs7I5UGetc3jS7qsyLINuztpjm6tRZT/tOveQVvvDuZ3MuHztC6fbZ86m+aZ3 jnrC9W7UI6yW7oOEkrfW1JOq8oOp14lABVInB7a1XGQWUZAcV55QLpGfx+FngMdI0Kb+8fWxter/ 1VzB5Dxn3c4kERpHeP256TnBRuONGRprX2jK6ZLRAr3VMRq27ntJLj7YocXtlA6t+UvtQd/4lyNU usJSgcLDhb2UnSu+3ACxzJn6ciSYILcTGj3eLJw4MM8O4ric4LVmegoS6yjy+4cPKI5ylpqp/s3T jaLAAVP1uxnsV491JkLY1K4NvVo0rsBnA6wInK9mQVIdOK4CleQLIHNc0Nv5KonVdXxHEAqOwXUE baT74UPrZPC0eU0Z8W+8FA5lvABuXvsgfa812N+NmxpeZJwtXpVxEU4Qe+diDkRpeoxtWPk2i3Az iAlk+95UWQulA+9E7bW1JZTqaTLZupSjbcUnShDpU4woSGv9C9+YyFGnh+h9yCrH6QXoDhA3E956 l+tbozAZXtISfNxIPWDw5fqGpVr9UFOC0dbBr0gX4rNU89o0rWAeJu8rc1Hjr2Xfy09qHTtqVauE 5NJGwla4lM++LuQ41AvFKjLmB/Dxx9wL+jEvdh1YsXspJkgRwk0pC0N43EdysgH1oA414QB0xYUd Bo6VjbSj4Vqpljrzuyyw28gpYlkY0osmR6sGr4UmCTAujXWvgkuJCgDqEls/UoUojrRSKs6OZ7z9 WToJ9lYiJQBJUf150NcFyvKMad2PVh43oL96MZcLLtak9L26PyEenCZN9qAeqXQyQbU8b15LNf8U CpGNmJGFBf6sEdfl7Ns3dTM5BdeDPKFFpK6rnfrVD8nKzS52+Dak2NshZ3DZEvNVoczXCeKhdips jBoP7zgEfmCEB7BTK18ijNSL+cW1okjYWDbAcQb3+tmyX900lzwUaV6X1Xo+SqqXtgIfWhmSDc8n t8f5IWxfiHoJIH0nXgEAXJ/Ok59sPpqrvWRLfaBOGPsipsZq4Qujdu5nD5HpIhtHxvcFA+VOC1b0 BlWVZ8cTXE22BFZ5hb6M2Tt1ruO/IiSNzK9nTWJIXOmZr6FIMyV/UQcVwSpnilwnIaQBgdduLjWs NIDrAysepht0+TDymu7SvJlaCKjRtrKIq7K8rHLFnUgzUKAzybtVGrAV7a7GBTfqZeBF3XVHX+7B owtEH6nKaocqzSfgByW8HxvBrxWfnZkcPlYA74vKrtQV2PudFw0yG32Apcv6QccaptrvhUWTI3aC dvnr8PV/8CEL5qm4065Zli486tejd1tjIPLeB9UhsrNWZYlRZrjfimVcbCa8spZZsmEQPy6U4UZr X3VinEqMhi6MIsSOYKoadOsRgu7neVTTnBY9aG3b657MGxc8chz94tJnXDZxgi54UYg3zggqmdVR 9a4ttyyTdoPeDiGEYbW9tD8LwZbeWFuau5+LKxgylaeLdY87nZPhqS5LCzmvJ7orzWQuBYv/d4LG FpHtVel8AMKHBFlxYKKtcjSTtp7QW4KgrjIok+4w17nV3nH+tGanutQBWWNM924Ui8MsIHIZZghL rbbvraj2H+OB81veTY+BD9zWcqGk4ZNYewAl+4KxetucB6JCBFxGA1Dl1MhhFuw8bBwuQMwTwmAS OhNpmBOv3HOIW/B/EIfGYpBpJ895cNBJ93IhfTm8Wp80HgjkiALbZGj35Lc94A7tWGZOQmCxo+Ud QE3mw9EnrNWFyX14jBSR/kPLpXkIXzTzCsgmA1dgrXok4N+kk6T5gi5CT23Xksqp+e89bbJGoQBE ABk3Tul8SDPGwNAqCifBXQw2L5RoLJUorzFjBPsRuLOpqIZaoTanRc36c7CqKV71WJF0juvep8GG eam/EyCv+lTo7mjp3roAa5Fiv7taGHLw+z6TPD3kYnU9pLr4QVoRHs5sF+bH8sUSuCYuvS2hL+1j xHHjFasSdRjlw4UHa9MoCV/XmwL1YsN4RL/1iH5OXfBJWEoCeNuuCEm7fMvte0Gjanawxf7gvWac pnQV+CBFt8uS5gtyO+FdIcg2dx+Nbv8MOnrtEbf5wKkEfrhNWPJzmadB/2wsakeIT0C31dXjfA4H qAWoREchu+JofaX7pLGb3RyEjJyhqV5f1MK+meMQ4c+xsCKNDhNDeeD2gR/R2MLNHyco+JrgplBp aI+T9VcEGb2iMHZB9cCXpJ0HfhG+t4z2m1459ly4sUhZkiB5XiKtSSnU3ZFGLXUE+VBVKa18kN7D m6faqTGzV2MHsjhFMfZ3qSmYiBmEcsicXEH0aTaQBBldvlIDO2fhH07eeEAydbV0XhkvQcy5gYnd 9SkQOF+Fp4UYkB22fwdqEqd7znn4FiBi4IefQP0bFnR3THxSksBr4Hni5YrxcAIN+jNXev43Q/zk hQsyjrA2wrbDy6Pa31y9ggv7F9wbJ1/cJjs7s4i2SBcP5n1+ujYrVw/9MDJLOuBDw5vQ/HB1HmpR EmeAPdBr4hkWmDpkvR3KIa0Zoj20yTeLJhn19HxhLnAlqI2Iic4/OqBsJhgfUropW6vsoumulRc0 PJ/HtbTBdjFyw7jQ7J09ucR4YF+4HaNSO6M/obCgBMhX6tRw6sVeCPTy21VcN3vTb2enu+6Sa53W wBDx70rMCYydF2xXtbPgtc8SOHG4HQpoJbCVXTw38Xxwi/ppggiEYSfge897qhKzsYxQf+mw7fIT 9lDGPbcvGmO6eqn0/dBGDx1O7QhCh8LOjCC6b9iA5j78osvAH4rvbnu23LgD+8KvJJWR4WHb9hMV NB57PcRGl34+VzEsBDD0GvYUaoaWB9m5K9kFgRHSGlLWkwIiFwf7YTKBHBg6zldBmj8cphrh5Nqb ONrbeNrGsxvtntVRpnrz1d4CEVYqNqARjOKWwRLUQkOf+4ujb5D0fDfOcTy3niRI3oa6KNfldPhS /K0QUfSi9xpKg+tnjF/wVx3O19zO67O7oG7FS8ygkNfygB9OwRygFQjYorec69VzZCQX8g2SzTfb mWmVDYoG+lK5nawVEzt++W5E21KR+b/eS0N4pABfSp5qP0VT9VgwyKZQhTwfLm/u5xYm/rMfLHwp Q+J+fkeVTX0hKDLpTMC7iXtQOXc3Wt+BrNCnN2m01T6Kx7oPgkrTO50J4DwDzL+OhOPdizoTPuaF m5R0sm1EAZ8My+KgLe6SJ+vmgshCqAYEJZVDWcXADVdJ8JGPZuVnSXxA9uYIheYSZan8ux+OTYOP mUboDWfuut2dUOFl3bnaxbFaVwc1iXkicZzm/s/H2lPsSw711aQqDyZ9bRlHdIn/5LnYEgCJvmzL +w29T9Hp/9y8MDGorliAIkxb8zv1of/uenmel8s5A7qfTjBtJ0y0lCurfQX1kYkJkFTHnudOau76 HNCEmZegTkQcoO3k9yd/5N6JIKF5DyKra3xL+sZQBLytSbXVo4sghnpLhasZ1MjIyXiKXdcBdggY 7k9Az99at/hR/fTpiuQZRiCh3YDhMIlEGinuu8t0VrIW/XXUwjUfr2k0zGUc2gL2Vb+cSf8/f/dW QNBYqRYa3TOMikqyCf6iny+VfB6b1CGaIkxF/oD0ZYRMouXCT2OkDl6j/rR9JPF0u4gj5LnbTGW1 v5sIiiYooexiijwk2HKxlXbGnPP/UeBNRDHHf6K6Hczbq4zyaqaD6y5IzVkhtQPrdXMIoKIXHhu6 7VBQGLNecDdzw2L369uZ3ZuzBok2PaqYI/NrglyfnWLnzVbewo1mq9y4cfnAlto/dArvzJgFqBqH OQn4T5AO04NDMknPQQWW1G2kBQGvg7fXSteh/ODmlytAWRhVJ0tbacsYey/fXz9c0W60gUECMd8c /UgGSJh5Jdymr/4cDTDb9TupO6EI9vnJtKG0uD22Eo7evAVv5uWEH4kxDanvHufPIx4IuuW6NiU0 RjBK2d+R7JCaSrTBocJWQPjpZawdZWC1Ctqm/s8O3NvL0Jd+FX6cOzGTVxwn9VsQM2wgX2ZKwqmX Brt97E58sfvMu44Vt5iQ+ZWw37C5C1R5Gu0DcR5Tfb4X7wguGkJaA/Lq2XxQr7xYRbN66QIbTXiN FAbt5izCJwKs4uveIf9bv0LON1oj1Dqjq1V8dBRhS7zkbuHcdRfW7OTvgnX0xNVnaQaqGxdn6Tw8 Vcvvhw8vlPME5q9i9BBsGpMqogohBkV53fEKKAm2sZvlPTPFi9haYjR52XiqsmYTF20KWcqdUahK 9POxtU1JHfdp3zfClHM+q5udlr57PkfFyGWVGlexpN00wAfeTsB96CJChvt8LKjy9oHzyRwheXPW jTzAsxlGs13h3Kaw4JDVwnY6pDJiSW/JsFaOBSMd1j5RZrHLBZEtB5O1emLWzHOQjvMNSW7bNdsP 97MBDlR8afHUb9k3BY7tKJSJr487/sEx8haWNv06Wd6/Dg+ZxTOLYTULOL2hWs2yI6furkUXSUS5 P9es0ZdNx/dnui6S5Y5lGbN14u98NG22BEVHy0QwDNleQp08SkSgfVzgFBuD82S1BLXcxuIVIzej GcbW7j4sd05vlHmSIwsXTM7N9ZJFeMHNzHMiwr1v5EFnX+0zyzsvv0lfyIvpt6PJNbsG09teVDJK AuP3CvCd38RL3IoOVcYUl7KCnt1n/6tifxfXtpWvWsaarfiFquB1m5rcylek6F5vcDqRKHE3DTT5 LKx5D9tyEyX6vLRjc78duXIRJ01vA6ldm9jK8PARkNPhFo9WhBoVis0ERGSiEJpu0ilqR4Q8Y+zo GiMG7THpP4hOci3tgKoGNpE3Lh3vkHmcsVBqsTHcmO9hpYiNKs1ch9IMgKoAbEpFS6OWh8cOoeHm /3agdqfbsWHe+VwcLXspksSrO0Cq0ijcnQySH10U2LsyR441DyewOS/syoh/3N0KkfplZ9sNSZLD rOFrqqQvYNMDR8ORuFYnRfkV0ZfLt3tRmVKPEx1EHTq1DdCJUaeH8FtIpQPvv8UG0Xbxdol3um2t 0trpuCD84qgUc6JF4BgQYLbUSzwzYofShn4xThkbKQkOh3iAEfA7FgOH4GqwZh2BPVQiGUwJn+iL ou0ld7x4iqtNgaStkKjJOs01fKattIHFI62bjrle+R69oPc3f5PoTw8ewfV4hV6JuBBouWhawMcX 3FlsNJWgRiyLl57qS2Ru9VOp647krlXZgOkQKTUMdoXK+yWIqPFcaZ7hcVJ0b+c02viPk22VFC0S ZMqTjO+9bvV23rijg6M4my9XCFPgVATntTDgIM+uKxvivcu5Kh1NZNVWuvui7VywIGmsnQKSupyW biyEGx2oBGagZEZN+lliKJRW+Yry7+4UoqGoUWdBWeN7vD/Iha2ljzQnMI4R+k3Wdu7GqQUbwmVf xbfnQhIT/SF9qXfYsbiUVxUEkSYHKXNKVeHCLUvztuL6yPCbraiJfaTYm3vDt1Pn2Bbqa3qajTi7 x9D7qrov/FXFdqJM6AmOjkJfOeXyYIZk7hR5vbSj4yLiTRk0VGtBk7BtIZE0Gx6uF97pVqPFVbwu z7W3YXDFe93RvXlpoNhqGrULTWGtMIB3GQMwfpJAnUeA9MfT6h1g9erfRt9Lr2K8bcEQfcfF6KS1 rhOT44M2mUEbEcY+0JkQhmBJKwaYfG3NxeYwpUiKvw76olyoaZcD72SxBOuoDpgQkuOPL/Iu3mHB zwfXELeOiZXYkgzea+OMgQINSgTZEV6dkmuyjZHfwYqGOs5XKwByvlL5F9hWPKLnDs9naL4aGygq gkpq2IL0hwq4QpBPrHsseDpW0eH/IHS5oPfQ5Xaz1Q+vyaUNtHLx3Lxls11kcxp0yQtxVtPK/MGS VDEabnieET9J6Ep7lNXVh4FibU4yEewWJx+rMHBN3HucIgrLAuZe+wjLa3mzKqjrpxoJrIvEXNtR KjjS+Hr3HfkzDyaK5qkCDQ5Hf1642jbgrq3cwkgHMbieD3Ablf3YHoNUg4xwA9Q8PgKr+YBNo5rs Fi+7LyVaNr9VwKeGbDfCN7AUyxV3HmJGnCj886NIaS6WmL/42Tz9elag3LopGeUaJeNWO/ACx149 Q3R9oeumwENSkLu9ZUNXho93yEG43Z6yorXK4GW0cwac1CPb97Dgpb5wJs9SkFLXqhxa/2xFdc0U LSIC3xFYdbE7djkoZFh3QQzWW9fej96JRlxTlq+DUugbYS/5MQlXO9Vz06thYBez9JeLS5g4JehN HTTVzoYtX1yj9IY14G54/luFR6TgnGccv0jqkV0L9gfPULzPAdWlpy5hLi87Zn1hiYS1xRdIRPWL g9k+Iwo7GUlRoRAs1RvR7mmZGRbfyJCjY8ZYMEwVLDj42oAw6+Dvj789cwuh5J4HvauApbpUCu2I C7sP2viSElAhFxbUJ8SJpmYCda3di/9YhPCWycVZCIhDU5u6DT8XlN9qRC1pYVsGFfdBcbRrpXFU ndDyHk7oLnnKfQ124vnvJM6wVjJbqpCTEq3ssTKugci0T0+SJOHvI1uA2qp08kCQe0DmEeeELqb3 K4vtRO2nUqsWv3aaErtYyzQnw3yO1dbPPBsbcvYDpw/KHS+b4qb7oqC7qKsh63Nc4fut60i9O3MG z3jHkHdOzVoAOBKat1qEWb00qWgG3NhpSPsTtwUCpGZJNE+cJdiVYGQRTSq2ATqhRYynH0WZkPwJ 7B/I3SJcDPEyuYxcbs+rEksfOyuuA0aBdu+Ni+66/c2vV1vyr9pv3yKJ7cqMisfi0Nuu1Fp2lQ+6 gkMP9CwZ+bzFlAjE/efRUmZ7ugb0FlpEk2UfSARvTJExSbrKJO48XRAHRQIyjD0mXhZGnj/FTUWb mgRmHXqfZmdqk6wcKSvrV1nlD4LVTzXgPRc6l5lnrFEFXXMyXisN0DiAy9SnNmL47Th37NXFJYTT OSCWsMU6Jj8S9fC+oXpv99e+ttWg1J9l3hyguHpjtTI/znNd1ubHD0j0qXHTg1TD9KqbEDrALFAK g8rpJ3efJDrvVRBM+PS2ztYgN/aLXNE7EdyCN7GfuC9TihJxTJzQc3tpl/thrgQsfyVHICW9rcq9 +Fr/6aM7TpVLXhoVZuzA5MnlbRlq543XRtRzG4vuaKP4rU+taRlx2Qfh9s/EzieGoD/Ire5iqBSh 8lPWjQe/hPWHKqD422bZNIgaKcYFzNrIGRPk809tTHDKFdUxT0cLzVu4p3DNjiH+sIGhrF1af7+6 IXEBS7Z+HWll1cXMNXWxxjHxAVZCYBJiziPQK+589YIY+v34FKewkC9q02JAhvlvSA20gGXfI2lq AU/ooFKZI9Lox9bVI9EKfmxFCywfpHbDaJ0cQaN+WxL4PVNpq3O1X2iYWeH1oPApytVtMAo8uerp EScA5x2gYjrlpzfqHvMHoqu+eF9jU45uM3qIwDX/to6YbEUV6NJ7thqwZhcJEg5DXNs5CSGYKuXb QCBYj8ZNHdkHjRHRvthK3ag6IGPnK2v+U3RPQzgy3O2shsKcpD6UxbvCK9PUeCfphaniQ4Xwlsl/ vNs+q7wB4m0T3uJmA9L9lFEeNmQ+jBnzIbYtxYejHlktgWOtpmsdTf/dOj/qwEBUiBQBRokuEE/e IZjuuOpN6uCkqv4AYvh1pi7ErkPHRmA6suk5CT5vKWbggySM90rGlRnnjzlwBm1Bmc3djBLwl2UV WKMNTYMDaxM0raSlHB5eiebfNHcxFn+qlNtxxxlA4O5NhtD060IijPGUFnZwg0396KAy55BYKRWM NWbm2YqKJSYT/lDqTUTjpbraYAXDmgrtL2zBaY6jkRZWt3E9GhToksHum6npPS1ctR+xAWdhyHC5 4h+HiYRkxl/CAa85l/ld40Va71jCGzEaDBsLYgg5rEPrED4Pitb1GmdYfHfdrh8B7TzHPQT/7jy/ IVxvrjhhgvpxtuIENrxXHoprTh63+SeIafJ2YgKSb6M82Tkgvep69NgXAH8aNFdhVsl0oDEF/wxb CbH5H+ekkLg2UW5ujD0Lhz1cEPFmXHzO80ikj+RiCcGm3dRGJAq4rbe4ir8RzkD8BI8UDqBUydlS 9hPYJzi98ljwi+MRkDmd+efu+1v+NAev/IKRxn902EF2UoVRuKYjZZ9AobFm4GR+QLpgyhA3lu3O tQSd8xTAVMDKbgzS44E04gicoLbybZI+N1ab37tFxWhSOZMRfEo6eldMwaV9ET6vSijU+fxJiktu lJ6DbYrXXuDFEUiQqUlmP3QQkMM1T0QrGCtks45biVtULJsLX1pxuekORFRBxoOR6/5i9JcSaSxd IiR7KDNgwiohnfQ+hSfQw1ILQ45Ox4e/1yhfr+txHoRM6yS25UaZGI9IOKPlDkwJPFly9QAN66og +JL76fnduaimDS+tSWAhEc+SmumQsCEgCu4jDynZFUjpquMxRfZcC/Pfg5nINuMK0yo9aITsTrpL fU6Du2dZ9lAzttT5dc9spGaW6iFeV6pZPcio3S+axthJKvSLMxDKiqwD/AKWzOwWLFwSbDc3urwN pnJWoj93W7q1Hlj0jKx1cqDhKfGYmQhoYNoXknhNEpAxK87Tt/hxnfzSQtcGU982FoIRmXzhYSVr INLUeAcKchPbeA3JQXydDYxiyTQhNAI4MndyE1Tsxu+JcFz4lxYfVYmG1wOaBsHOLZU9dayMDuT7 hl5fkDwdrTUOxjLhXwYOEXC13+ou+9jRHD9lCiSxCz9Tv89cSYBze8vf+su8UgWzLIxjWvdQlayB /sRsUgXlI+jrZ6wcJETdXwqe4AldiF33U0YAUzNiacSL2QiJq+fePkRxMY4SxEoMazMTvRYqVnol E+TJSM4lI41h39CQBbrw1GsD3bFAs++4Ka+AteVl28UBRuW2+oSPg1aqJ9GUC866IrvXBBTWmyYR Xtyhg7PgU/aDhJVRft9iXh2Tj7DlqnC7lIYxDZ6+b3iFxxDFEi9kTE6PBLwJJd4n9v2/y5XGSR58 vboptKcud2/oyxXzyoyqExu+Xbp5fb9m0pcDsF4g+MAw3MTP9RpjCew6j+0Ppi57YHt72qJZXGEA hYFBr5qZFn3g8gumOZU1o9mykOJyc5EeYKj+aA50coDR77/jpDgz/RnXQeJi+2MDKSjc43J185I6 2C0i6C/GaR1oKx+zaBAGRldOrSAP5MuXHm1xQZr93cm+LWEFQiyqJhyIpumnQtrxG5jN2Rx6e6No bVz37LRIB+FLX2uYvuugvPZPfH/W9qliP5qHL6e2yVcG0iG4p2Y4Gn2rkpTrRiKYkO4q/3/a1pmy MamSqSoB0kD2aMnMo7nEtFxMG+DIZpe+l2l922//OXhOQLsfx5/GuBLCzM9jbjBJmWDQdyZ0DWgb tGPwSKP3kW5Po9JdBSeZ3elgAam9x3ayJv12CnatFFyQ4wwHSAckLtoKAlu7LkPWUCZa9b6AKgA0 HG436O7oYUOmtTuvM2574LboennFMEiww7nD0m5en1cFYOv7pB6XN5Wo7ov+ouFU4qwEL6l2r47s nNYj38WzgIsfj9ei9m59SgX1IFoaiA9X4vvrjrtiEHqDI4Dqgzwx7jwFIFrjW6udvQyi05O8lztT a+9Mx4uiVVyyU4OSqdOzR3sdGfY/tyyJUsmKfUT90YncrjTlUk4SJ5twF+nwMjUZ/tvbqBLbqVnw UTSFWYheCTfezAn6jnVq7E2HBjqhHNFRmcc9jNucPTH8ZP44KCNigpT2QVDW6WH1hozxEPm3TtCM 1a+XFATcSJvXkQiy2QEvxEylo2fgHWxCS3NrePtOxAbtXDSbVxJqPdkmqyWyPTcEtaQoJNI/H7If LHlkscYMq09rnKF8gAFzlIS5NG8zOAsJ3a+iZBNJ+1xqFg4LSThTEBAYzMKWP8/ccyM9JWzvBvTS tNmY4v3OJAWZGjhYVu73HGImzK25uv4W6X4mZkdZYvrtwLpWuCYWJ72EOWcd/Ham1Ye3g49QaRwg EaY3p0NTqoekF2/GW3gMDEzVl85A54eDdAI+fFK4BmbW0IjCF4K55XEuoy4v4GMyORA7/fk6XCM8 YEjhhZBRvgj29+dzjY1iCWVYMTy0U0ffW4a7LXBa7KwU7pALktlOyYYld4/FJuwXsxxuXorjHrFQ SdR52izeKgZl7ZIF/kvMF7syNM81ePYhevhbpBCRDmuWUi/ytM+KGzPEWwRV3dwPCNn1UTp2spsy MCXSbyc9/PnKxcgjCptAEzmf2FK129mUhOLMVDtHRaX/4h0ksYpISK+qIte+r8ej3hphA5LGbC1V skFC5KNJRaQITUP5iE6SscAcoHZKsZwjbv1tcA8OfZwBoZgYAkFkxv29aOiI94h1MRBYgttrgurL UteS7A7URYGD7tZwxRkxvp6Pn2XleNUEbDiOOxNHnQ/RnHWf9iM2vuY7zpMbRsb57m3aq1aHQRHg 7I+U2FcXRb1rGibX0gHZf1Owk3xStLkkziHb0qP43alRqKCkoIFFy+/UlDtv+VtKm69/mhKgZ5ef z8egBH1YLBByXpfBoQr7Cb3mVhkC442lJU7TEbr2n3yTnu2fapi47+Kw4AaYMMMCAq+kjAJSeAhq qdy8Hwi/t/M2HQgSEOvGUN6UIwHMeVghr6PwJkDVA2xpi3RbXtMQczhCKLu0eIev2lpmtnxnvQJG Ofqe3seTbiS5hCMHe9gEsLpzhsKWgUNriWKtWe57OxS39OgMSavPz4FhI/rXoWp+eQsdP6+RNEt4 +jQDQvhVduf9pEC9IhDLBLsMBuoh6I8wB8da/X86wJQznVYC1vvADDuf5BZPHZOan0ofO0wIK6LR okH0K8zIWccRlgUzuGe7eDLSDFNTNjOOyaoGz1gyJ7IO/WOBMO/grtRWN0HaKNoPhge0a/FiKeTF QTQtGp73KHH0a6YusmnbnDa5lFfWCqvLedNc4SR6NNQuvVciOxZ2dTIJEIXHHyQeHVK+2ZdPaWlU TdWg6X8YhzC8P+JTl3S05D07lytZ9lQev/S+cJu1EApI2YZkWL62pK3m/9ROllCCIolD6cwI6UVn l2hPEEWck9l1NBu+uA0O3N5C5Q4MA0R+WHFY4wywXODIJx2yQkAogr+3M25Zhb4JHz0kaAU341h3 IcDW9F7gBKNxL5wKEat/p+RmdVvXkD2sV+zwhwijubrzH6JxGj9gM8mPUAs4At8ORUSLRYHxs+0c 1kNcK4eMKS5y0Vd3bqkWBpY4+ef8NfBh7bpwelSoFM9+b24n21k7+8aMLyGXBpwwlRV6rXD1RXOn WC9JTj8MNaYMNgnjNqPwb4ez97vO4xvgOU8v1FvQaUUb679+jRx6/l3hZo1elbmuB5L6cWpxJOWN ctUR7Qyoj3WA9iYOq6vUzj0NZyiFtiNE2w/W+LDrDs9BNY6WnRZ0VIjY/NjY1MAxHoY7LQF9CRtU Zx+yRFfHzXaVgLIPwBF8gzCmnndqkpgjKdj6LZnV4FTU4Q3bMTyqjnstnxPwPgcOa1QeNXGarDzA 1dllJpUAinmhF3LVB2DYylGgpkPpjDv9UNq/JdF6a/w6S8ScTutK3rN7jetFwY9BEHdrjKY+YuOW uiaW+4BkztEItiOhCIzqQuMHEQFFy3+ZoAvk+oJcdKOdyNYvghvf8KOyCYFTKwHFXmR0potfylpI UTD6qYTSA8eYZYB/Psleer9rSyvD796wyHCG/js/VSQqIIsxWGbWIRBHOLy31vzS6ufHpir2PonX t2SQ02FcNxlZwQxxCrTtEbo9r8UlN5g99YTjbQOlJ39JkwyrZjBuPF2hCtmRzEetaFlkeHYRJRrl Nh27IKae5rmdNSfxl9KPpEnXR6emJE3laolxdHUfgKfnwi5TavA8z9wF/EPegnAES7Kozdy46i8H rXIWiAWZIiVCLZDSE8JvwGn/OV0GDmq2C63CWKY3cbA6aj+hMLJrkETuO0GeTEyDXnlvHauiyn3S hY9eQtTVbJkV1RVnC4X6H9jWEPJ99w4vudGjvxDEd35NVHrBSmqIJhDaCWD0wPSB/YwuZpsegFmh vKcJqCj804NvPfaxGbq2CdzMGpNiKNgulnMAJHmV1jK2NXnC8RwsXxgxJ0kFX9g34kVWgGb3WSZ5 IIe2VDbRgOTb9w+q4V9z6uJYNVuTEsSVU4xj+eP67fOi38HMxZDWGnco69GNzaEhVsGOH/++1nP0 Aomt79bX+zrahx8HJGp2E9mEoZThYz1HZuhw9cJZYDq1yjaFxhdw7gQGj4NS3Nkqj6KgGITS9umx PJCmJyhEPWu4kjIwiuEQZpQB/wwr7Q5t+lNkY1PxcZMTzmuqN6UFhg8KEC+7vpvbytwTdmsdPZZC 82v88iEdycj+dc9nPRsSx4NNeGryYjAW5nmNLCFYQKFlr0njJOrRNRWuLdoJo9f2tLuAB2vYw1Km 1dEy1tIS0zXS3pmDarSuoGGp6h9na2LSw0Gsvkl2Z5xkFaB4doxawJFR3V/XRnNvBADNpjGf8BAp fbqRj52kBJP70I5EyAIk1F9JS+ZLLSZXKUunfG8wUPn+Oqjutnvfvzo21zHXQsN8mtrzZPnp11s3 KChrRLNN4o68Q52bTKYlkN0XJydidUl2L8tbr4Cx5BVmvnq2wfq+pOq4Q7P/2sYoe5tZ+ovFdYy7 BqFPYziUfXYtC5XNQ6G7SIgjTlbVM/x7kEmC4SwMiXBGMzwNIPcawDX4S/qzvx5D569lvRJqhX94 0XEWi7YqcPkoqm8zBKlKXEDCrE9QfAoElfXcfPLifgDE47vNVvtpaEJ3bDwCR8c8XWDANhKglp+y iVbTs/U/369/N9157tJ21GiX2+vupSocDpxl6uNALjKxgPqwOfkRHiDTtAYn+kYs9T0V4iCzWll5 CKyFv9eM3wfcMa4vpVwvftN1St4QO8/HeGwt17mCtHvMsCdMRZYAsiB0fKt9lAS3sgSr2piBvJDJ eFb8iwxI2hJO8pPiEsE9gzMBTVSw9rbHxIiD1dhGlT0y1zjJuuIdG5jZ1NjqxOckKbWNHDYGyJxK 1KLf9XlsFGdq6GKAGK0RWDv4e1UpFpP0GlBbtCqzPzMxei/gMAxxbWB0pNS0SQKUSvj1zjZ98y5N swAqeLiwUzq4J09mooZrF26jypn3WQ1mumK9PScApZJ3fRghd2u30+/tlTRh43Tj3SYZxKEtPqqw 4Z4teIMSoMLLQXP3ZxbrTVYsznoWPqcPTmYcQbkjyRBL/BUShmkutbLUCbZMaQC5yaW4fjgOM6RB Hp4EybdU4GhuBlQ50vFVqQLT8ccm90ZADlX/ZxW4VRczem5mw1PKt9v9h50JODKojiELuANaDMpa MccaEcQ25dJW+12XCS85JczICILgD5XSn2avzP1EMPh7t1vRp2rFxwGKRpwgXZ9KNus4LhhZuxHr g0g/MsyVqgO8cHZZfP4GDd0IuvMHeN/N553sxjQ30yqiIyga55lmpylXt8G9twnAvP18WDc6DGtS 7sifIydSj9WTODqF0Z/vks3kiYbqikI3pcn3g8aNrSHiwX+/1mUbxBwb0nTjWtQ2o7GIDw9v/EjG DTSkLjDGP8LZJga7QuCHZc9NzHYhtlAxcHxwux/FsTapz70Qqf1r9jTCctkpst/wiPvRcfcYuUSC OUvbxAsZjUZxn8k3lstKHGYm2YuFHhkQBznsSn+C1G6A8i9U+eaCWM92/Vq/wCh5ZsTiu54qEh1g aQgJWujq9S9j8pm8IvCzVu4tvgVXPX+6wvrCUhF7NxHgaUJaEU2wVbjwb6Aj9AQGqCaEqRvVyo8E pueCCtC8eJ5BhRQr3USAUkZE2SH2nfXsFI43QiOfMJY5OrdPvZnKbdZuXYzIjmBGFH97L5hv0xmU opdmjCFojQjTb6DJ1jN6xJ2IL/ef+12QytE51UIV8JHGiZIqKnCz4MS0/ZAH33iVMaaD38SlFlj/ h2IqjABPV18wVh9EWfXQX1X3JiybnVFm/JyDV1j/m3xyDGeWXSjHA2UgUlVjLI9sVk2WeLyrg8dh 8S/KqgtU6kf5rlC0ZhazsAlKky2aVItvqTIwDqnLlB3acFm1M/7xpxIHS9i/F9QN6tyP5DAk8V5l by2f4dPZVYOBLWxUtHrTUKWd87bzJgFyvdsarV/YVAWQ/Inkz71BOLlnx3MwuQnvi72BNi2XIL92 BLZSXfVf7Q8JoCLDJ9x2OiPN4Y2jo3mLNv6ho/RB8Vh188MIzMLH9/RtSqAkKCuWsY+blhTwVJOe RgQOwiIxR08fg2sGHGQRYH5YhKguCjYh2YQqyLykxD3UfK+eDW1O1f/5+TcBQOlIbgiqh8+iCVmM Q+QYVyzP/cPsiLbIFXhGBDOTvXx002gKVeOluUP4JLTopSoT2D30Kc2TWlqTh3vdXWohA8SOmOUG 942Rb3HJtT5O1oOmvOmdY5fqQGWUUgYv5W32Aop5QAai8OTGYyrapr0vzWoxASk0SOqnLloY7cVZ cNja8aqDWqYKFC0mDYlHHJK1ALNfkP9TKa6cOCTO8k9HBNaqfNZamWCfdNpazkiQLWvDe9GykV3S mujNMOztDjmaAxeS4FzlujhRGOCdLwqRfHnlTGOX4UR8oBQx58i3SQ6WUZfKCZEg7BdqPDQXNm9c 651GNa8RLJ0zMxYuNuu1PqpBI0iHwLjdIENADY+dG8EAfUvfG04/ek9b5kYvMSwM98cGON1q+/L4 /BEFbo5DrgZPAp1uqrKxpr50+YdDcEgebrjEzMRCat0LA3xNBaPQb0qXSwKMqgLobdGuUf0TunGB b3O0CGbHEw5bKl7EB4WEqDsKcwQJFh3/zcOHAk60bxKDjGg0yK15r9nG9bqToFMpYeNt2HvMbH49 5JiaK6t3nOLpuJNWPxX8GMgePgmRJefWp/xB+m0mcKjEgGPUPzaAqowScgDAkcv7OsWCK2jFhZX8 5rb1f7duGE5Q94G0JTpv0Lsx3yM6VBM6/AC3bB+4aanCeDcbukNp6jkQqlsotT9HdWaJDJtpnLsA RXv7I1B9VXOZkECEC+AIcfd1AbOWGMIxiyeOMZGy2mQiaem3ScIpTe/yIoTy/xfM17eJ6eR5QUzR DcHa+33ML2SmGt1O9zUsJy6kWlCST3E46b3Alpo98jdT1t8YTtWvwyti5QwW6+d5Pvyd+mw8Gndu bjVNJebF7HyL9t8KlwV/r5T+xa+WvydfvT3xZNwZgbetqvJZK2t6I2TwX+YM0AxL6Df+o+9xk+Mv 64o3pkONr5HNpAalsMV7+brqsh/Hn19TRjQu+aeiLWrPkrYjAxglJT5Sy43WJSGOwaTgeRw61xW7 0QdIe0jpcABSvlKQG+YbBHYnlwA5VEfdD93AfIP20m3qLfwpF0VKYekNqWdr87J/eU6UQgGy4N0Y /j62K3aRPt9do2ZWj8sDkJpjX5a1KeGiQ1c6ALSL2iMkyD/N4TA2D8qxgwsBIHRIsw0zP0tcfC7D MYmQkx/45+V4TWm4FbdMnUCisyLVQ1oD9z02/z/qFpwgAYYDs7z+q6cVuEdbj/b9bXN4Ir/PFCLS p2XU1c8hoRjrTFfsURxsRg8/Pjd5uTqzia8B1GSwVFk5Ki6jj7c5wDdCXQ4bOR8Zzv0bEjTufBAP Yyevu8O9s1ZT4F//cqalGugxCAa6MdGBELCs2qtLPXLE/MlB6KXKqThHJEZbujYEUBQgWeygoc55 9t1ub1nNV6L6ib2FSZn8FWVbaAdE+Gzt1CazRo+ou4CuvV5UVA3LmMslGPKpiMDCR88zz4jJSpE5 LZSuY9r8ETlWjIeimZDdar3fBh9rrCFZl9nfaEKtdmV51ij6Ei1fM/KB/RB9HKKxAlKQDYeYSyNx LtR3pkwXgcj+oRET309Eu4UyXgz3veEp4zlsZU7ikU3n9HwSprLfs0q7VJK70OhCMfHz4Xv1w5RG OnwoQlt8uyok6J2L5OJLuHBTv/fchS7/+UtKM4GBmPGRKRS3zbfRdmHLncG6zffCZOe5sSGq4UEJ BYp3Zi2CePWQCOJ35PAF9dI3xxGrE6iiGShhCYNAh6uAWhiI7DhjKd8eCYmZpmgrJ8vHpIW5RvuO 3GU+EbWH81tjRsS7qqFJdG6xGfhb7rvjfSq8/9Dg2jEnQWxxJrNH15FOjgaOQudGaaNn6mc9Gafe KKe56VRTB790lzCDGb9EuhIS18ONageWE3rCulF45sMMp7r/w++7bKlRpOKFGU/XFGGln4Y9nMZH vaGzh5Z4wk5J4TiwxF2NQ5wibKh8QyrGrIxqp6jAsaFaC7KokD0hab1dPiYlWw0zbQObAk0sBWmC sfAZkyaYCwmpxscScGBn//3PVSj9MViGVSP/zhj/swXt7yPeAuVx/RYbWJvALZfX4c/rT+Esu8jE r6/V+ruiEATOfQLCwy/K7w1bFCV5tBhe3QaDRz+fqxJpX6ObJPC8TONZcESexedvuibVo19rnsQ+ IYrZx/eB45HRuC9VOEXKDRreY0VDwgyt1MhNUFVGsc/rD+nPGK3DNy9saMosvzy9pcGKFUnYBQpL fXmZoPcn2D/gtKznJIrSllu8m2wKJZfoHKQ/Mx8UjDAb3JCpoVeYbSl4dCrzlyOxG1lQz3Z4tfT1 8RXSDTdP2FyMeCMcZEaq81YNrOMUarLe8jo6dPqN26ilSqZBJ4/j/4Rdgfaae3okOA9etiRpiopK cb9P40ZTeIiT1GWpI6j8gGfrms2u9/a5KwaWmFFkq34sEL4d5ywTsQLBiLNPwUz4xJa0aL2heRRv bpv2GeQ6MksHvgUGq7Z4C34IRgnQLyCF0nVLfun1PF/qnYCPKAGbkMkHOnZENoKZlMG86qnpCAaB bsTpx9fVvmr3A34aHHzj1I/bS6PL+5avk8omblpbd7MOZ9vtt9H+h7h1S8pnubAQkxjMUH9J4Yr7 B26ysxKYd3ZziO0Jx0HMY4wtDjqCVw4i1vNC+NeVmrvphyRFCAHAnxKGq8QrcpKMXB2aXJB0SvON BAl17P8E4ui9i/fnkfhVcwE4gleeF3OPCCirRMN/ackqmzncp1RRhxLAqyIaCK5aUliv/8IYbQ+e A/CNPNy2X2Cmy0kiFO1aq/ufl9Bx8cRnHq3mRaTxB9VyApFVKVGd93TfCdlKt252gULc+wUIqHVt nowRqjCsXGnhAQVNC4cWkcmC5on7gewgis6EEj8Ayks/JhI1+tNrpylMnZphfEjBhMOzoAVvwTuI MwXks0PG5+siEpX9Gaza62Yuq7WpSW6XUw8Hx+DDdFaOiF4PZr81ZX/FoBKH7LDWhR1s6znZmYrQ pST0SLI7A45dmX3dsK54jLrJ4rhQrfJ7v6khf+cKOZqNNOHeNAY0AhHrW+DXpd6/5Tli2iv8tLOY RBP6HkugMappGJNBjyPWTAPljOJAHXYj0dNEThXCid5Q08G1RMy3In3bPxX5s52FFJQFWTz/+r02 RiFdp6Hq7MJPqcfcIwg+TyVGOdx5q0cMEEVGsl0rLdfboIOwWCW9Tt48rvffiOGvcYuT5CFcpG89 nPCfiAbhFzJQux6G/YOaIMUYSQnZbpcqMJUsPHYKoNtagwRZ4d4W8D/Wgn8yuqDV5hR5JeLop1x8 fjoZFH81cMBopUXQPQ0w3G+fuoxR8GjFi2jqIBgU3my17cSj1anHuaMNMJJrStYXV8fYwDHBhfxo jXM/tTcWYXqKNh43Fj0JYkSQ6PWdZ7E5P/p7rQxrFstvpQazvPohBgO/MIKlm4iPvUtoFkhML7AV 11o/p4M3ZhZT3CAKcEv3xzUHk/KZQ1twlyKlbrpkbYvyJqy1H5rytkXlw5cUK0+4wkwWcepcyCT7 UlmKf2XcBAwcNHg/ADiUzIUARVic7xZ+nd9tQvQGqBpnxjUSarD1mDMsuN+r4xUjevgq0b102kqY iECvqDedkth8yoyAnA2JlWMShCzCYc1df7T1TLEBCnuFHDQBY5yKCssGnV7RuoMfO8wmOa9/s7nP L1q527mnvuCya28Ei7ofz6Pw4jA2yafl0TLDINHe0FCUFWaN4P52WkJfQqBxVC3kWw2U2JbhjX8I HvHQ1fMzQ3dVE0pV4OgD871IgFx5vMoVyNDL+FDfGMJxqABx3dHpD/2zJV5ovtwQtTAHd9Iki3bM A+UUxMwHDH2sapnNhOr3qlgmgphyvLvSZqH9+jIh/+bI1n8QbafecAWeGCxraqGA/z+uHl3dZJaU 10cEiZ+AEO8MbcEnU/+eaXGGy860BKb4sXcVTg0KM48lXnZYiIl4brvXkepj5CbLstAn9Ebh/LhQ NNWhm3BGvratG+6v1ACXoirvngcuKiiy1R7gDeWYV5pWm9oPJtyn/uuDGP1/kQx29xUe2tl/0lu8 nmro9M9bXA1KPaygjVRBW+JBjDEEVY+0Qv9GnCKpgPOpG/Pr1d2GPlaWT5cbVotN8mDMewjmVwFo PKkZX8GWnOU0k4CF39OhLcxjphObeKa35igehoxgu1ZAK/CebHExz85OtdllCbAW6zpToxOwxqtF HFt0EB5bCC9PG8um3XC7Rf82s0mEJ78AF2U50khXMd7ARTXuS+EaHOdPScEhQoLJVrMj8Bi9Ym+B wb8Vy9xd3tajFIpiI8PKjtRsbQSbHGj85kD7Gx52NM6tdWzfZ0CDl53Mba5585D6P2uTk9kDpC6H mcuOgzlqNLalWWZN7oQui3crfhPYf9091w1hA+NpNj7pJurTbGjYqZ6H4pJn7fxkzwpHFeHact1P qwXgYiKAsMojJWO622jTNjVX88FZppkUbQtTX/lbQdxcrCLRYINf/DrfRiS+CmiB69g7UAz6K+QG M/s2EKw2uVCLHI/9v+1JqCf97zHFv7pMvFf+dw1z/FkaiVDvmQvqXbabwmiwMpu8u+eYUhpSp6NP AZblq4h095iJcKFbFgUrTc8lUW9RnGtDf7F04oCTidE9cdJKNL9vqiYNtpF0V3xc/SNglDkTj4st kwJ5ZFDZTqAKLJwdIdvUkj31I6H2qIkF8I5IvscelcGivk6qYlLbT4D5TVSC5+pYCFdTdO9XPL52 48yojAKGfAP3SS5fbiqCoMLRPThKVgkpf6VaBnawNUhKhVWs4YV5rGVFs2ETafhsQ6F2TQJJgN1q 4156vXbaB8D5cwuhj1rCGvVLCtqg5y9adOd+VNEXfsX5eH5X/M8XJDkYUuBTAp9ncMI3szK5gJVF a3iw2reBkktDfx+ILlFi6G5EUZ8msm1wzYiDl5jX0FjFlHx0AME2xmVf0SI9s2aADwLPMq2X2Joo u0yy3aGChi0buFyliFkGugRnZu3rUNeo25/dECOYEJ3XaIwEj/PRAlJ3DXWofFCrPg5gYKF5dCCj 1rrvCD7v6Ai3a3bQ1n1T+pZaODc+xRtDQLdvdHMycZ47zwuHm//CRe0QBdHv82yWRA5XKbt+yIeD +dDOWdLt/Ze5n0VFbxX9FsUH1rHpviZSNCgFIZHYr0oMTaZ9Xqacd22c4AnoXq1ONjV7RLGk8ltm uPakmnr2hHI2w0jKev8xR0P/UDZAQa4Nc6W1ZFgfi7iV3ZDbBKnXtpw+guX+8RPaaduGG6jROY3O QQ0txWy0oWUFmfzAm72FlYXCkP/MDieQ7YzDctGzLkFI1vML3YgO/wbNYt2+xhCI+hKsb1KyPgXi ixEYx7uEYfUwPQpmBUFWQMDI0Ph+1F89A/HEFt9A1UqiJMAt0M9vCvGOwXMzjfNk/ouyev1G1dJu RcfR4sB7xjtrv+zbt8WRg39tIOQGDiy5eOtkADnX8koH+rw9F2IOKPnlDlqx0pyMrBNr1f/3DeFS 5RHpOTlNjExmnHILqk4XyHl76oP25pHO+7nRBjnmWTgFuL385HdRFt1u06JtwC4X5PCs2GDtjXKp Q/6UEKzZo2gyEuN8rivd6qAlF0yQmVg0wqaFY3Dprhv6V38TJZQvgdg5FBA5WKCHTxGi94CBpEOL J1f9wEHBOrNcv7lm8d8IxHpUd43RYpdWcNGVvAhDHRUl/R7NJ6Vk7M/6iYyUQ/FRAfW2hdVwFIUC A88nQ0kgrwjwE5NifZQfq9ssdlLT3Mw7KremK50yRCG5WdEVXGkvl2YeMRN6+ksu6f/3AndkiBAq j9LRiWrto7xUpEqlPvAfhswo10VgKZrpDzKi5O4CX5cqWAvdjbO+VGeYRvsnXPhrvWFPwdBRVM/0 5iHYzg/myWcdHXLjED0o0F8D1vBeODhMmX5aVgivSqbOoMjcnz9wnQWIEFwyfGVg7f9+cajmRf/g klLpaLxIGPT8OkQZLzc09S9zJYCekcoMLBOr2F48KDX23oyDY92N4oN3wKGqvtnwNoRObcmOsm1K FFwGuZAPecZuK4KWwG0UnxaSGpfF9wcQYGAb0NYZFpWVlb2Lda9Cqfl1XYoIRBL98GVmLvvktGkV AFUA0mRjiMeHORL2hUjA0OBAk+MhTerli0KxGPyFbHC6M1a3ftueuC7c37eWXowSZt+xWlJ7ey1Q CGUkHec7sGqRuIZsimv9r+E4Nb8w+FjFYjwfB1u+Ys9GFivQiXosvI1x/JdBV57iwUWuPNHxyvhA 9+QsMmxcjbQHT1hnYitfIi6yC6h4oFfH2l3HuBRy4FDqgJBtxqmugffh5QcEqcpHJxQ/xxvQRh32 Dh2WbzO3UxIgr4ETJBI90VfL7exoQVrVjDIr5rZ7krc5La7UL+DYxcE59b/bqEHkQeJ8xW/vXimc gTx7QYGgz4BKMpaW44v1cD5Z9zB61nq4hdvxIxgQv/dw9n18KWE0scZEpesbxyF/Gva3ZzMnKGx7 STP25jTs/pwzpAUqqcRIWA8zjj9tf7wFDg018nZWj33xFHN9MhkRvECcaEmE2dCdXCBxQG6rgixg W1umYsmk4c9KwlFVryJ2JMAHXq2z5dwMt/dnBrk5Q360FTUfN55SczbzcLfHLa8CWP6TRN/ri73d BcUxaKdfLwnmWTv0mphzv9LmXRlsbOPb+mFC51wLHZ+9kwg5Z13hXxdF0Cmzt88jW32uEF+uQl62 H0kI1AjtEzXKXAzZvp47pB3b/0jKSwYzayoCL+ZJg00W0pftiGjy1XdtkZaeVouGgZHXFw8g2gAR I/6jLWqUK5e3fF2YMJaMxKMnPWbeUrJYvSadNgh66zJ9v1qVbV47G6EpP7C2fvBXXmLE8WM38j3k MU+XrWCQr+vkikXXPRwDSCVmYthsAmO/Sb6uBt1mZyxgLddWc8bsZAKzNxMA5ap6viJJ8VxArgWN ad/igXd25v+i+FlXTFB1yfUIJaEA2DDV1Os+T2r+raXqpIHwAqw/gaDUTavsIWHbfH9JOAM2TFtD 07vzHhhmtqybUq6t7H7uiKuqlsUCKjALW+RKhyE5YDwoOhBgqwvtCwsLYQOMXkSqMGUqF/LiRJBF mb9xouX7W2g9z+Ez/8Mnqn8WOhgr2rtZqtwJS6KLB60q4dm+6J+tidQchj6rdsV4ehmdEN29WrXc EnH2aFl2ripsC28N8vihzmF8wOpo2i+NKy7wCEdRoErUxSSKIXI5EM8FgiQnkF4vuPGRnqbO8njw 11F5w9ZerGHM6kYGoUgNBs/qeECB9oxiI0zDCROB5bW4PWXHjOxHkFLOjKB9vtXAfa7HUNjRPYS+ WRtn1RAwYVZIbP9yDz5y09F8FyS5iCu9WcAbf4Hdws5hF19KVCfxThWWDupoaWpwyn/+0YvCDSmT sLbCRrOHfW9wldEyv7ZsWpWl1bbFd1ykCoGBgrZf5lPkePCtKZ++DaM74AO63d9a/NleEgjUriCg 7cI9szm4SRfyVmi6n/rFpuoaXmD60wfNippJ2d/sus29z3OUn4cz7yVjr8timn6h1iq3IixuveXC zCWyLcys+0EyGyDWhZCxqGqt5SUPKInvyRyJLbtFGbXXQTu1SAy0p3ALdlj0F1FXOBxjOTfsnKdU HrXDvo2maEz91AwGuNB4uaoWgRc5kCwJs0V4IESPVra7XJVl8V4tasDAJOfksGrC/rmvXvERD72j MxVvirmbEWZUeYRcYWzF2CVhFp4D4y7fdTokqERDSpDcAiXzuMlG97UMWp3lrtyG0t5QxysjbSuy 8CetR1YuCQZSNYZ80r1/A34zqbQxJtaqLmxlXZYFO+/jJy3NzlB/V+BEqm14EydHP2l18ATjupjm OA2eFdE3L+O3QUpD491GLdvy1bJWF7frk0uAHppopoZpXiSTRaCrGgRvzX8OZs5DSflDMJEeRNO3 I4oyWV9HlskCiUprknd22mvsLKmUohHGoxL0Gvop9Mjlcf77mFeX+lSj4juD7BJMWRvIVPa6rxvh WfBsE3PuhQVNePhKFkBvGFs08vOHpOWrpfbJNljHDFEIckgaCrspiVPvO9QSdIKgj808rhoL4NRi fIAgDeVlTv67SEav2DXg5gBPaWFY/hOTxAoLCC4jqPhiHJyciiMJ3XXs0PxgIsg0KpsDFGZZanVR nPz4qZf7M1kG9vNFR9R2IoiyUAIdfDMdIfRw5/dx/kY1KDzgjmhj7vHuEpVKP3wNtWpQMihDx3J3 HmxKIBE1r4zlEgi4X4gMObr+RAKCMths9VxUpxd+E3pZ54o3MgLsiPXj9ZERh+0a05NLQ7jzaP3O woCjjlciw1mjjl0SgdHki+AD5uKQEREaNWa3LSp6gD2QvuQwD5R0+uWPKIh5Legy880Z3bkDudJo OO117tSRAj/zSMimU6JV2uxxLbZ8BwI71Sw08qr5XoD3ziNN4tCziOqrAut/3YNo4nUyJjbxfq9B 4LGYV+Y8Px9ZGNlFzYVXI5RAlJAXAOTj749j3EYz0OqXRyboDER8ou7vQ9wEyciPXQiZAKby67uM Q7wsno9YZjGVQgy1Hbww+1uY8+IzGIiBiQLkFU5wfwkrQW4YoeBeP2Su72moIUTiIKywqnePX6fg YRSN5HXK+x9RB0XLyshcd0FJuXCXdBXi+pOaWwv9kWVR9NufwQSaDhEX1Kr4FSqQBY2+vbfxRB7T spEeQA9Ero1Di3YVRkBnwQ2X2L0zNPVE4kya6MjggOmzg+pYfA3RCJcS0hDnyzc0ZEJ1sQgbhOFt smbj4AIGzobRmBuedYeNx+5fANQrXCpYExkGmavq0H9s5MO/PgkpgZTtvyy3VmI0yOGRkopW0j7z f3+lKUvly7CZH/ia2qDYFEdOTMxlMJ4eCWSck8+om0rbj8OkeFBCWdyBxFxKW9RaV8l3j2X5lwrs p6cMCE8qWAoyYjqiPEDLbiAXD3Hj3Ke8pHq+rJVUa8HWd2DJHiF2AVlKxmdG2H2J5R6hLUB9CZgV IvVZV3wHcMdydaK1V4iEfivAGR0Tt8Id1EK5sfhgQyC1GAKWSSojFG9YzeYCSY5rDERdMDE3LIAt BEjeWVo/sZPKjkq4ubodLdmcpLeejkHVil5iVwksuXPS6MrmvxGOoa/P4+HMdLjsczXiMi5tm4p7 ubMN87UBYxIaTiKrx3jycJxoUC9XOjgZs2XAY/I7XoGhFZB1CbGPL5nNsQIu4Pf7AhrfRzb7zZjQ kfXMfOHtNw1p6uSyPOZzJlb1lge/jAH/2Pa2nsfDEIEGWc5aeEaQG2L2tnCBL9xqLCBqXWd/KUk9 XF1/KFTADtOP5FXbwrw4/gpRUJ8WMLd6U8nVQ4VJdOlrNBM5YZXvDHsWHv2nI5t4jZC3es17wONC N+x6YXEFM1d4U16P4U70ruFxS/Xg71KQ15EBjjCceIJPCMwFeTfNcjswTGckz5SHPN7YZ2NzNZfa RdAhyf5RrhgjY8G8KSWluR9F1viB4gELu6LFtpnBST+PQAU2wVjR39m6tyC16zWvjCgpCos3NJAZ ueYNnVhAl7yypRLyo7I9Yz3imBoEH6w/lj4luXNkulCGkd9EoUEbAQygxcloa2/SK/YEZ9mmnf5t 9WGploGJf6w88EMBH02hsvFXkb+Qh8mNgkijzbuUEX7cIzWPZB7KX9TmTpU5HehCwcOQerR6TPNF JwOoP8p1AQ6ebn0PU2KBvpXXfpf1ANdoy2lKKsH2HJlkGWsUlPMF7h6AToTS6epSyf6Dn+mAaBNG 9sgCFBo25mKyTXb39OV1xBP63IQ80YoTW5hPN4gr3ES7Bd8YwffQhAoPANHJeYIu9qXtWSEes7gZ htDdjuo0ctf+6cKfUhFYaa1utcj1wD8/Orby4vWN+PNYeF8MY3RWiMklNbBGOZqchcSu6Vy3XlWm Lds0YD3e+hO7HurRNAzg9E2TUVXOf+8aLsLhbhHAgT58IsOLOtr/CwsnKRR7qpWbamEu/3SHehwr W9D0QB0cUytqm1XdWiUGQj1PeNapmQ7q6rDOY9+/PPEgf0Jlamf1RjZJoYD3OVvS20MMZxkNHVEm cYb9/fHLM5qe8d23HfWnRoe8XC4vjxxRrT5I/kX3BpBUPqoWXKe1pRmkpFtG73vwc7+Sg6RXBuYL m+bRiR5W1O//4V+QGLPQp+BJJTMZcILVgWjHHZ8JHguLyzw2DPI43tK4xOwetBvzj6AzwOZfFws/ rSD9YHaYNWs6PclAcKYvv0GdBHGLp459kyyyDBP8fvNLbAminbcI9hURhQKMnEu8PWXN3IZFaBHt 5K2YtrttyK6DGF2BcayRFd3TKni6CM0sxzXZ3CEdg1KWGn7n4Uiq38jJLN1GwSaJ7wDaDnL/0sFw IGWIpiKz+OwYk5sauR08YSo7n+RTKFqnw0fJLk6C3PLjxr3xMP9PnTobGX/S3Q5cg0eXJjk3pbQ7 rkA3Yfb8bq5aNVZHE9sBPLGlKlCeD1QEg1mWQQmynwC3usIXnnfWceb8+kF3jV6odefMGJ6nIVf5 7gQ5/SG0zuiV9CtS5fdpiEvrzAizMzPABdtx7yIPOBCKVyeOBx+X5HUoIGyU4zU/0YCXxV4ODmGt LRAcCtJu9dbFwHW+fGG6IxT1shJbmlDK0AXUFjCyENbDGuAshJZZ1xgaPgEcI2ejWjC8MrbjXlVU 5cYspDDGzPjC3rEW1s53TGHmKSjXeE/JcHjY7TU/PqFmjBtFs/SuqOJZen2r7vp3LIHhmDQ8XxTm dU8q97bHWIbXOGvRcOSLlSoHtoTb3IRxc3M7fqDs1whbblwf3wQyDQ40vzs8FqTpDbRKC9hJYayF +7tdStuE2nZnAHlcyQjrJVPc9521aJGvIVOPrSQVVwhK4iLIaB7EhXEvcTTO1RnzO5INuys6SInP wTh+DApUtjhipatAinKjnX4PDPWjxKi7fRyK5+qn1yOZvUkhQdcAN68Ode9vaGurKoQHnGpyz2NJ RjXFcc64HMYW3+1Sa1wL05xowseRt1kXmfKRRekpkFAMj+t9OlkT0YqiYeq59t+HRMqNvXPhORCA vHM8h/iqnQZQQbkfOD6bwKYy2EiMiQHzcaoUMA7T3HkQEj3guU0BTodT2a+kkpzgYQ752GDah4Zd CHI24ndrABdy0+n7PWCZVqn1BoGTDqfw1BnK8HfQez/5xhZ1dumfaqY/CNach+cpH5zdA4GBn1oS AcdZmRQxLSWptqvUv3crKdhNPTZhrBntN4o2ICNgQqc6G3Cbu5K6QI8xl3mBt0JtiYZqcS6pY5I0 /bPgjYXQahCFr2jztzaHRQLK+K8iZrf1X+ffPmwcsIbIjP4kE1iFCzlPGOrIn8VEpoF1UgP6tgBz jkYorWwCIspX8Wlvq9oj1y6AO0a+li4lf6UOm2CCQuiX4QBbO12Vxwvlhx7hUGo5LHAYyeGmKpjU tN37TtT2A3Bn09ba8QIz5pZafXDGUMpdbtoUqVE4D+YdvLCbPcD9NzGG4m169B1zCSocgKM+hhCu mynCLGupzO7VZ5jhS5808t2G2f4MDFfiDsuiOMV3U7HZuh+pXrYR+G+zulr6a8G9YNY2Dg1+/AWV baKg/g9PIXqOYtCs5TKcTGhaeDQ+AgBSRGjUpUIHnKu0qAgNTdqCeES4ZXPuaNw69sunKr7JHKVC tnxBA2qE7opOfdEjjpz/ImbPEDv6hl56QJjBnPD+obXMRYBbpy4hmt6U5xt1EuFxbJHy1RW7L62d yKqoUL0OXU/doGa0H+fow4XQzKf1jhVqjMJJwAF+wWGw7yWdm+OCuJfasGFBPjQIxLPbVwH8JbWV 9rGOSqjUPiOhhm56pIjVhtLQhPvee1reqzWBEs4lNXZ6Pkm1x44tZHNFarKKfLaguR4zHtTNGaKr +w5OqNzqOw7GNRoyZApIxnzzdptNZZyIGPWBakNGEkK2El+1n3tcsP9oNWAVgnAgfgGqcLbadGl1 13/Pbw7/3B+/k07GYAhLQeb6J8hy9WaXWcNaX69b1TPZ156L81RJ1JFod4gr2Lvy/34ukz+iOcTn ymyEcuD6ZL4ZzIMYdvo0CY20mWffk6QlyX8cZOroAxjgdeBr5j3JFNDDg0E89Ivu98I80iRq8m0E KnY3598QwBYYG1QhR8p9pZ8qb5OZ43PFHSy2TRdjH819fWmNyVzgDfxG4wbGyDa74cJn4XGQYs5N qdkK2zXElJGm/mvaTQQ4+/bzYSAcFQDl/1aDDViFW2XG/qB6xQfnsfuQW0hvOSJYVBNhaM99wsHq a49RQiNN4Ptu21GkbkNh4Q5CO9asmWqu6bczrlXrgVDZGukVu8Esuq7nQp1CLYmruM5gCluI1pBk PksYZDlQt6UWt9N6jkH0d0eNs+OZyhA3np1bOH515hmnkKpmh0o9YSxNeWx/AXFScQTNF+3/19Pa kGWU1Pwf5uIBE4bqsuLC0Ibk5F0/QzXBNMLzlX9VK03p3qCmlMcuUPv2bUOdDc07I1I9qZ3Aq2cE iSUBaRCdq3ZLDeHSMEAG5eDieRC911C5BQhg6FvAFmeF9XoYf5jor01alfHUmlipVXgUamZBubfE G9hffULsS7DkzDGEWe01ftRGObMSyXJhBwm4rB5CtsLmyzEdObOYS6FInOiB69S1hv9VZogYuBkN 9AORqTF6X61mDlYwrGtgD/5KG82CWQAu19IJF3KJz6+5qQTpbgGfSfu5fV8N+Y49QZCCfjtMg4QG gAaEaoUCwz9IdCwQobOm9yI9AlRbGpnN4UDqNF06k31GAGd265UvGSvyR7NO+Aq2/QF4PGJg6nZh WjULxCmsHV2OyTyMPpesXxFMoIx0toX5p11teT8uh1jo9TWJt60rBjFMzPS5sy/EcdCJBFeE5nOi NZMbb5s2W5AiYwFLVUGCa1w3NohpJ85p4zy6ckeDfS+kpFPKJoGImyykjsyAuEwRyx2gzlEqbq6P 6uWxA6Pe2uoMkCP4vjdmHvR+dVXIRSl2EmNvnXp60npyW8DTsmuYszFRLaG3ltWXgkap77xzRhkx FPcGTOPT6oG6MZbN5mRbuAhjy6L0+hCWSGQCnH0/IfB8k7MktSLtHtoioXEafzq2lyrmnL+NZE4n W641vxIuqIDPH1ukrfdfovwR9Zu/UYXWx6HJiEXnMgrAvQI10lYKPFMrfUgBg3YybBXfuw6cf3mG YsqO+gzuXLE5+z5IZmw0/04q5DGuakQk2BNgyFxHF6gfoZH8wl3XkR0w87k7aUpa7HuHo6z13iAD Ftd18awtvKZ2i945Id3EL5Yz2y4jmHyvUbxShDEKqPxYAf4rPa7Nw1WuZVKxhQ5zeWbz2Ug66BGD gv5ExXZ0czQshOHxUZojTMAjzKbCjdq1Bif5JXnK/kq6mDVJyI2iGmuOCJFiB0jsPVaDZlKKRcxa VQBfDxjZljm4on8/WTRR597CH1/vCdoSI/LB0DiOClrGiH2TGyOPX+uzcJBNglj3qNX6VUhHQse8 5ltLCEyiX0VXgA5sivVd3CDSYkIEszwcRKjA1StXiKpPC/qzHbvDpvsf/L7XwUzP4bV3lm4MavYv Sr19/tbHrphC11qDXWR3qooV/yfTmWhxdAb31Zo9BsjaJ6z1ImaadFtSo1Ef5DxEYoeESHJMu8fa obMaBDyuRrHbCDyd5jDiJWAhVQeVDDsRTPTfeBpC4WdwBcV1Y+AOpm5L5A7XuDrhn104jkOpiL99 SDHF0FukkyAEE+sl7Zs8TvcfeuXqsYE3alIdd7DR8kwP1kE3tSLvADYXBt+hXQ5vu/hcDfLJP0Ft gM0bEnsYtzQNk0qcWQA68ntG6UAbuR1lHnqrbmcNOEd59PY47cvn20xsPqhiExqmxQTtSxa5XN7z LD8MTYDgvAkprPzcYA4cjFdX8qajXK29cAsh+WLdrESplxqGVv6S9pUD/kE00KQhHf7D+HdBVfdU lv0kstKWAiywiE1IH/TKjrQxyrHlaKgYI6X4LDbn+jQjO8vGO0Z6BU51YzEVCaPZ1gzK7mc15WcB 6UyGt1ZtmxxPzG7pH61LgihxCXmNhX/nstxa34Af9o68QCi4eos0WYGFbbKKPiRFnnj4/avC56R8 +H/C4I9daISJennKx7Rafl2BMZj191enLX1KXkLkpZVZKV4ceGR0hAuqPDS7MFm2U48p+hJIRq2t oqL8tUMDQp7mRZRf+jloiF7e+AQVQPjli1Taek7yXz7qp4q7l4zEV1u3se99aDEzzJR+7zPybw7m qbwL2JSPQ0/u717N4SqZq/qO3jkkVAoRTm0p5Nsae2wLKki9BhBav9oj6wJzP1WXDR7+oYDytXGD ajm1vMqztM3oL9SBz5pPN7tOWSYmmAwHI8BKnWgBYLZS2fno3DWImSGyJ+/T6d2N5UUyVIfFyj9E nWgPYrK9UjYgfYCLrqBHcMXo1p4AHLTYgkCQnRa7OLrkSbRaoirkmaWcvDVZayNSMkJkntFEpmYr FHvFnS9C0OafN4bM/KWDSCpoG9x9mzizl2CjjwzZV5qCjW9Bokt6tk/w+HNbrWLvEqG3Vm8H+CWt DQXK+bDoEpegmqubaCHjXr0xnQ9WfqubJK/yxLCQiJWT+Qs82MyCysBs1+/kMUFCpADPXKKiPbJs URlLNGddaC4jSViHvmKkN+1WUVzbg8HzV6M5aL9kG+25AKM8ZyqRVPvzRgGtQ1zHMoQMvjHH2zvu eXlqq+rHqdEET2lDYbP/fyxNU1bKoHpSd0RVEIEeAlmjnSC28Y70ftRaW18T0pgbkmS6FzadE2xy WRdCOouc7m7CmnsdFKDZ4AeztX7rPhIvJpWI0sC6fbLGzT9kmJFM+q47jKG96lv7kPvY9oQHmJO7 svMHiVd/20TpN4u2aj5GhFPVFYyulIWNTwQUkW8lO7Bi+Cx5yIVKFoHejgMOv3E7q8rEbs5lPVvR /4wY5o3e9jwY/PZLNyDziUeQY9Wutc5a7UsqdNPuYAVdrPWJ8LGH/TvqYFNU2eAWuV6a6LpJLIQg q5/C7brtXXRxYT1Oid6HPYH2wMjqRCWMuHfOROFKTIeZzANNQUB5Wt0By4yuJLfx5p88YuI20ukJ lJrsWIQOqs0ACTcwwq5sidAW67gx54bYIiESUfMPfhhazUOxv0SX1JPx46RZV7khDG4x9hkB2igC WbY3izGHTwhOsZJVY8Wr7ogu4TlLx1ba8QXltJgLEsZPD0xtgLqr8OiwpC+uUtg8NcLl5qPHvhvd xobkPMzwkKFDPLJ0A3mOVuQKIWfMDET7C/+d/ZLRBGvHFKuqTgpCZXalG2OqYi3eQCCqFYzJFkad O0VQNAb6XPaRMvVAiMyuPhONvihTmlE4wm6TzjoegWEIyaKBYETtelPIPsS7fhbl6qh74e1dzFkf tj9CXDC3fdHC0EeUgoaGYXnh1xDuukDuk7k0BGFGqIJNed6r2oHdis7+dWBfah+EZNMb4k/uMOat e9n3upKLNiA9MLXVHU3UoXlmxmKeZq4Yw8fGhkedRLL3Ee+YH96HbXrEtxhkJf5Kyy9tGaE5/rDU IJ+gMBMYDUN0BcoYXsZbpOMlhezd+2MNOct2BF/93xz695oWhcvDHRAuTitslvA68o9DvOfeHc+P Q/8jYHkEetP9i0OdQcP5F20182Pdn3Bs+2nmxlJ2Yg7wZ8rVntN1ruivCa0TRRDEKl9xnS8ipEOP gPl0tytqLByuewzmf0l1XfjVdfLqjopYhDKAIgrJoGT52Ahdoth+/CMA7PJWoWi6ve7p+k+Vo54j 8rtEplkiCAcl7MvLAKxghS6V7340tNGc1di4A9d4SA2iA74nVvsERFboO21p8OUnT8VV5Z0aph8I GBuppl5b2q2NK3Teigp65zSYjR+DFLbLVvyW/8CUr1qzY+3szav6LmmKidaLHu3ss1Xo6wF4DrBf bpoJG8PiAC2kSUkDjlVC1d1POFYSQyW+cZ0Yr0fugQKWqAdVvoBarv0Vz3Hr0MgnkF02dJxktDBk OcdvAIbhNNrX3R2E5hennONt0VoygMPfqduVpUc+bvDghMCiurxTEyBA6t84lGHNe1p9GiiZmGog cdcYieErvTRDS0rmV4hBevwCsBIY+Wzy9iQewFSf/8swPKUKGWgI7VUfD48dsdJovjhUL28poHBB WNHe3BIk13TrK8w/8f3HutUe/4tQ5WXhKUHMhbU4b2AxPmaYUn7kKVWHFTBu9VH/RQshanoWy8d0 kNiDzyOYh2OZdSYT4aZSNJnEVzlpoRqLfS+8MO27ytkRBoA6N2Jf7i6G0iPF3btnFXzgh95jmJ+Q KY5UoDd2F/f7v2OmDkTdWdmW3HU7R8dFV19Qlm7Dw7UEE5sn/L+J0ZmGP33C8ZGCtsbhe7YLvkl/ cRd23yquLeM5VrPbUe6bv1w4ZtRdLO1pxxPT7bO8c0bwXVX2+KU5VycJTqhrTIu1YNG0/VHxHYzP +pT8JAbziZFPOVthIkO5xIRWOd+OXU1+WTPB3oljz5kDCxqREzrhTzT6PgueVXSf4Lq1RItNrC9n g32NAPQx9ax24yNcm+vzI7qrCcY6Uzh9F1pa/KY0dE3dElAVix4CuK6GNN4NtiTSlu/ps7T6hRgm pkFyvkywzCnzUNNrGaXNUU2hwZkpeZZuoCtJ38CVIuF9dw3DhedHCDyxwDHLTCUFgSycl842wVhC wkeTdvEhpjvDIS/620Yh0K2GicO4CbbaXeSGrF7w5rrhhCpi+GSSRrCrdJfQeVdvMEIrYSrdiMSb Kf/POSFyX5LneJdEotty4SZf1vQqfVURkuehJ/Rkg4y1GKHp7UffKtlKghLaVh0z2y297OopQWhD sGuyz7wqi8/B5s4OfEzxWD9SR/ha+Oc3vKyy6CA0rgThq3w1Ll8/WsKU6dOlKyo+U62dbPgQpvQZ KaGxckE7ji6GCC+7nGSw5gDeN/lG86tNGMgmGfx+U28XdwRHkTW7tt6LVQHxrGYQGj08mGOye1Q5 byE7KtVt4QLmx6zN+ageIXuasmjrsDqgi9IZDx+WoTVSC7yNsgq4yVJnbZq/E/8L8j14oPdZvPZL 7MkukagBkNR1LpvUdCncfDXYl6+WFW7+YUKPsu5GRoPnbwmnNeqU34fI7wCbUXGV0Ya/LHPhhezr ocsm1hrtkz2TVh0EshHjJYZbJ8Gj6DAf/1wA1VEDwu+BYAvyv5rlN0gdkfpzDpk2/KBVONOVfIcH AP6jkfMrT8DrrBZwzZb8KslgD7p1UheiP2U20mgEEXIFUsNrA25cXGRtJJkzNopNsy9cpSonV6BE AqUAn05NPguARgzSwfOu4JErdNgUfP1wSATvO4qPpP64TqgU6Hn+JNsfX0RqQd9dkb7JS2ZxwXXJ zfKjoepBYrjy7KsCStnf7TqwEP3G2sIMd4nj/BURnqsZjCQ8jTOd2jld0sJQN7cYRbINITf1veos qUG0A/MyHl00Cfbea6uqBWC43k2pfjQYt8J6EIX++YMos5jjo5bdIS3WD8Q+ktEz+OENrWRyETzm 4Nln6NCWkAsqucOWkGlh3SriTaqutAT/+Hbw6OQBXlVz6qVBGCTF8SCY/uftMik0Tj5NaGL9uyUh vJ7cXJ/8rzdBOFC4mWJqvma5HmgUs/SVldiISnZwH8mUE+UhlhjNRHhgqJc/zruExhMNTZBbqtFu s7Oqc6pLt/DCdFoQNPcpN/uSEFKd2qwWrtBEUK95khX340U3ZkzB4cSrAvWwxtjPRqs+NUFFT2Ra +ArnF3TZ2+apJr8hSFtiiWYMDHi9HwpFACt3K/Dt+AoKayi/xQPmDniD1pTsVhwShjUpwia5sHn5 uSB8NOtpSVuykdPWi/ckgFEO3f4eR24+V1qT5UGXH0GLxzrnPpAZm8Mn1s+83kA3LHBYevaMGtTg arqORymRpc+QioQ4przZFXO+JFS7KaRdD164pNtesYUhLfrzs1/qc9fr+/cl5xBFFOcG2IGWGWL6 EkQd5Dp7w53g/3ev1OnXGVuF+AsC8vAmK9m0rgB2fDgw1cjxFGI1oszK08TCnRxKfSH+L72WIgUK s26O+HgSFmdqedJhiTOiwoYWrp0NNzp+Q26DGNjf/A2hCovIWqKBvDt2HRoziN0Jqt6xEzCfeZkQ oobaX/nYtONrqGVMrU0breSqlTrzsvC2j84Sc7ZydK+WyqZqVFBSrq8ZPsMy4dq7sNH27DtGS53u UjhdXvDQswpVPgZpqvNLjJrTNFJvKBdZtsESJ/4G+9Vp3XYtGUg8Hw76ErqS5/pnxNRNBXz+z7rU gjb8fjZEBhp+9KWlT8RKkSmOyMyytXx5Su0w3ZEDvkVynBKfHPT43J5bYj5+7pqfItjchfbIK0tY JJknbWR20sUginRzXJdCq2CkdXaJ4FaKpxp85py6h/XTUy1VguHwA+YIUIf6YLFdgUMg+U3v0ews UuL/4hlqQh1no5C2tnT7Q422w5OSyDbtFStWV+UmUes5HzlRAaKywuMV/5/6f5IjQHmMEAwTIgGj 2m5Fqy15HHvQuoybXxBtenluT7dyZYnqBt9WF9AGLHjR8vIMi+jjP0mWt75yCXPygKMzV5POG7zQ wYcHsuFb5w4UIiMSPxdetqPIhdNO1Ra/WARuVyHGKIADcGMUBWXzLo3ENdbBC9x/lygxmU3tSnma sE1bZIU4yn5CdahIm+EmP9ifGyTwmq5noOzJaw1Kt/C8T+GWZlm+Z8O8FkVaowP7P8Tt425L9V9U fw0XgdqtA7R6Ceau8qlMoF0hzYK/kSRATkyGdpcAcMUJkQipW30YKwtD5m+iw/KgyrbU2HXvBJFE pFRm9rfPwJjmOCQoahNHaFhLok2FsOMPzl4Q3pWzdsouVOn7VpkSLYa0SC5qRVxsYWt4HOzKrQB2 aarT4cER/m1R/Fm2Wk2CKRY3J+HWrytDFw+FYhMhBP7v2WfETZx2gWBYdMp77PKWxzG5z5IzMgTz j3DFQbk2oLyR+8sa7ngu7+C5hU5rW1VAdg+lnhgMG6wycQGysHCw7kQ47VrzKoTGII1GmIxUG9xM tFScG2AT+M4K8S1sGSliU1pjbUwYKAz6xwrRck6aCXWs6j4Y9xX9V+TtCx/dh1OFaCHkpRmGmyH6 zMBFyUMHuDDAJKoYbkU+R+cuJf5WfZC7TYgXQxfQ0JRfTHCAjV0vyXXVDWKrmloBLj3h1VvyO0LZ 9YmB5LNPTbmWvApSzDc8+Zr9Wyng5DH57+LK5POAccjeMLc94Y+4EN75aNp8uwO8ViJNoFFyvKPn QDKEK0J/z3D81CdDJLGXQZdywVnUSIk34AiWCrknUA7/Dz92Mh4dOu9GSszM5aCTvPqEU2kbEx9k lDvUBhBrXJbQ1SaLaaPblY2Z/8jEdrTIlqUQ/3712U83oYyxOFwTthyMTyBq4Yb0GpktGcvrYF0w FbFyB/I6Rhv+4+V33NFptxOwZ6QQCTWqxU+bnPxwlRvPcBbTzOpNdtIGKmqI8BWUcYAMz5jedqzY HySaVkb+Nw2p4Knjq1M8u9zf2grHqSCASPpjBj1Cp5RjV3q9z+Y6TF4v9KLx8Jeegxa1pSgRAZEP jFAE6VyYk0cTUKbrFaDMVRpsnWv5NNlHJQ7/YMosJDOzGsyZHLLWX8nvCRbdTgtWjdRVN+GNrDyc b1TTgbGvXpX1RigZ1VdDAk0HbzKHMp8dAfGkIOZt/I5cV0VH5F+Kqqqkox55Hz5RaBb8XKlB8pM6 QiOTJY9C0enVOCHffiiI/kaiLK0Kw7lMMK6qp7N9GZ6l0+AAPXhbGm4Xpr0MA6kFYmMh4MlNEiv5 C6UdC2Btuo4/v4Lno+euB/23SApZthLkPhNyX19pFYVarNDMA0stOKWOcXG9eOy4riJM8A6mRfEQ bK22z20T88VI916GF1iBjXKibWqzsE4DwjGxc3jSpG23qH9UmrDQdRFspQo8nJ+15b9Nys3dRedI XkJpkc96cMfVLOlzTaRnOPFjarwSUogzenwbXTcfnxTf//2zHKYQ+S/ADMfDUwME6m1b7U0aGqng SmGOxyk6AN/9T2Cgqef8aKZ+tlQugCGyHrs5rFCaAZvP85za8b+1GgOILvVGngiBXJNRirnVaMMv fEIPJ9UxEO8vrjmxa5YN6daqV2nzZZ662Q8lL5ziI9dCKRhc/n0+82ddZK/OBea0Wcc8ieZUCGON OxZYB8J7YY0gj2cCUJArqPduuFyUUtTUykJf0LjGFyNK6RTAl5X84+T5TCNWZ7MyUcJzshUbnsbq qTOO8oFeH6GnlMSuk7W5ot/jsJwSIv1gl35RecaDwnphd3klUyjygTVyRtHMJ+ZAXyzQo6C2H0d8 yXBCSLMFj2pRpMyIMQ5NN9nn2sVsGHTBgU+0EHOj50nPGT9NEA0gjhG73iBq4cPTYaHPd7gtGTW9 LZIOkWiGo72XrvLBuxKGAJAR+KKMp0FBI4wTwBG00wyaHR28CXtKHYK/TImRbhZW6xORx+/qrbkz G4PesQrqD1e39G7rByBn9R0z6TiEfhwCPhKO4cDlwGrOUwOUFntr/mSaGEhpzXqSRc0SPDCgbSKE pBff7KsLI1c0Q28mNEEj04ZZe5baSXMxwqBnC3Gl5o6PTC7M1px5kiAK8Nb7Z4yGA8Rr9LOCIlHw JDTLVtkxmJvkn/aPEmmkqJxk/ngbJfb+mGYYxP7+rurAOX+cAa6msgppu7VWHnWheAUC47rhDwRw E4xJFHuoCmSwiNOSf2rOHHlF9Jsjsy4s4nMKwuiUnXWDpNVhC1L1Lk1hluRb3S/dAXQw6VnEaDVM EdZCNmSG9ccMXJZiuiRr0RTfd28cquLBLo4vo6kUh1PlSZSu8/B08VuAyykI/9nbNCtoyrOyBdP7 hfpQy2z9KVc4eCGmkAYjMhDRa8SYAvQtkZ35aLbZjDzkjirtgrv53iJaw9/fhiFMMU9dBygWK4it JVUz3MuoY1tJZ1uKvM5d22sm7ZCQ6TpMv22W9XVNBmZS5HeU4n0RbSunetiHGYTSNUEpupR62aSj t/6nvkKGp2+wxk1Zc/ND7nRa4j2IfqwjzEGiZanBrghOdZrKgR5z8MTy5GVX/qrkU/dylfW6r3AG Q3rCnld3SephuoB/GH1o9TLgFBDGdcFOm/yXT/Rp4b8dXTN224ds9gOxixzp/Wec7mOQD0Cxycwr NGJjMOhDEeHNmD1VVOFLMNvW8pUaxSUgp45VJVLy9rAtFJxMyGUnHTGHf96elI9KtSFLPbf9i8l2 nECjreTByEL7Ewo8INls5CcSRPZvzVxd+goUiLePoid08IWyI0sMEKbqMP6EkaWNB2GeWixgU7ru vHJlHywjlh7nyOaRSztd0lcdCv/Ed989mZfmjx0pFZAlJtf2oojqHO0VaP9/AJDLsTr/QxrzaHFI DBU2ouwSGbCp9rbSIpyTOKTpGQSiZd1+c0q6HaU1WSV3ZYTo7DqRlBR1+/CYpfq0ntF06ePnPbJH aVOp32y1ZuMX+h3bkzWMlZ69DZ7TP0+tK1y9l9XB97opcA167hfQDbo0ig3jB+THV4+dY0vFc4bW bbEuXHAYQvzmM7zCofMWgnMiOmJMJI0xBrgSgqEDa/MCY05Rl0Jp7n5VF+ptBVJPMfHaUcGTqwM9 FJjrZK8ZaTw60PXBPiZMSd1SDjAg7JfxPxRXXCE0zUxdRlgip95xkFiysrjpncETRmFRMfIEhxuM DK5KFvdDWEoGKI0bG4Dh9B6BEwIWpvtrmDeEAfxziJs/HXIBDlFyZNMoaqyOBGwsjt8lz0iQ4Zdx Txp8FWIFtanb+slUq1qS1/BOwo1VFpfgcqEaoW/6FZb9/YX3LFG3HfnSetOYhIYuxqG2+t+7yE/K Z59TpcvhjKWX81WjxULyUn/0u1XcJqenyTZpOTUrc2+URerZ7S807dN+yi2fz8qFef+uIwKGh1+L QSCJc3xITu/eRsK4zD0nks7xY4Yxd+IhaLY6yHELX8iw5I0ZjiLLAphPbZnlFb5n6S4zLpXd28iB mEql4kOl/NiyIJbkoSaIdToq45CWk1R9Bbg4ifYIYM+cYuvb395SuThhMi3nLnikYM1A7n5OTdzF Sx626kaVzKtbxYZicOrpzI3AVn3TC+iEEWQwM8LTGVBJ25tfeq8oDVBjm4hvswGD7bWNPnyoWAY4 OjFIQFU3eSdFowNfkWnUhczSc3WpvA8FbwCpLmONZkhWvI+Vv9SnEAU3t4TUECIZnGwjjPhRvXfa eeAysgEqCSgLKaYq4SKEx3YCEY5DatCWxBccxbAEjpDkmU0D6b0knTJfmvb3pwM3H/k7nC5YtHKw qyCa4eAE5VAd4qgCeA+P7fpsb4/hokcfveHRX1zJ6Fucyd7kZLe+8vdmRs5FnefaR9oi9E8KV85G FX3H+m+fLSGExT9ocKup5kxYrwLwHyxKsYtdAYE5T2WSlmOg/uLY0VAUnnLy8DpMbhq3doAfRGEK HQ83igsfcftxD1gmgmYaEthuISYUdL+Qi0pvS9bgdKPeI0m+Aer+yrGxflMwxZzM9pXE2Tfo0cZP pYI6w1kJqXHkirO4qPYiUZuiJa2EOwZtC+RF5nz7cO5dG9Xeh7f73AmlNNLeZW5o7b62NAEKYhur 6AhegdBxNR1IdZ6WikTMJX9gPz7lZyRdHX5ajfY6TthLCEdJCcYALGpwwsJHBW+pPY3VI/VMl1XY OtztB01KzUJQNjEzoNVG8DLwW4Zt5sKKNF2mqfJNDgjuJWXqg5LQN8WDnr2vUVF3ix8yozxh248/ Ash7b7zNkzcZtaPZdtVEPi0ttjT6H4xhSQL1z5nxbjkgQ/pS3BfTjFMn8ufPvDFYxokPTzE8CJiC UEK0+Wuo6w+MJkRPpw2fgR2im8NBXNyq/blam6BZEJswia+froPNrWWxfAyJrPHPoq/dJeXAtF0C F2I8Whp0BKiqhanxT0z6Svba8o+DLPblcLfExi3V320OmV+LY3yV6dkusv3VrrG8aTDGlOa4HeF7 kbPyXctt6uSh+AMpKdP1ZrFalFA4qrfkNmbA5SRhEgXrXGgD5KFXJ2Wm32XMWDuQ3TzppEwgmPOH vsSC+ByWIeA2/zs/RPc2ymcZ7Ajjot6aFv8Izuwlg5vmlZiJIfL/nLTnfrz31K2+8lsJFM4qpPOS 7TUG5HTraJGOk8HxZ5E7hgx7zlgBBNGQzRhoaN1NsBdC9Jrvi+A+cU5l2oB35phXHsTetpFf7GGV CA8tVKWChu9Q8rpfZkdaVWNtcr3cG23ngXtUIHmecIWt2WSAKeGOSG9HjyBpO87bh6T8PQ2xZG4x MtEeawjtwpAcNvronYmazd7UbuJQvdTFiimSxNFQa+QdII0pABZUTQY5hXudspULFShpaKhfIPjB i5ir4uZSDl+LnI1hNy+MAsuXOlog2C7EH2u+euk3c8k/MorlDOSqZfdwwqAmzCPHS2JCOI2P2F5/ +7ShQpObn/NnTDFiYEk5pKUz4DVHanMNm0BiJMlpjCt+YJgR1qNM270AC5eZCvjNk6Jj5WaKlAsm c+yor7f9KMZDus4ihlPaDjOpQa1+sdi289HfO5/pH/Vgqly8LXTolpsT9n8al/j7Ju4wMfkKmd6h yGowwzvdTjlPokNI2569EqTml2gSux3TK/N2QP9xK068PSEHfP7yzdTn0b2sW0RnJMV0h4bcz+Cb 5NpD0Ctw3gTxvgzpbm7D+0W/zJsQZrwVKOYN9cP9bVWBY6wCtiIArsN9e0Z7jtgt/VE3WWr0trSK IKQ3zLRVvg9+48JQgJmvlzCeLe8iUMNYeSeuEI/10T24AlVZCU8H+PGUrr4V7dnBz/GP4pgruExJ 9MZJpoqdrgiJL33S5soT+T+XeYptz5A3nLbuAoEbojsZ3G5E+WNq7CDyHwPNipfnR6EWkzn8BYaM dfDPvZEeNVhJsKrZEzkch4gaVhhvw/M5BcK47df2NQ+21VGSDqghIB4ktWpesuxRb5B4tOG4pptT UoBXVT1eLGXif3Ez1RNhO6OKTzcKDGmrNzuD2XHuQysF4Nrt/n5ixGNq/a+s0um57CoWLdVjE/M+ 3CQd+/IxCpQHKS4UuO1ZpQxrTu1vXTeXOyd0EgQ4pC55FutDEtIiCUCtze2l+VcPbsQKBlNxND3p Z1Bpv8z40CXKURPAy3rCSOBqDAFH+9ibd/qlUjpImdZpH7bpBMOLzEP9OuSwxsCc9AQI9sduhUc5 r3lau0uNMDYnyWCwXp6F/oRNN3jUMDkus9Dvp/4Pza2yVsr5oGfZmXENw1BtVjBs62sU/oxVngon NR7+8L/gRI4kowsFeWfUH0+YH9WLmQOr17SsN8O+vx+4e8851B7y9aeZlsFt3gXfPoUXMVVOM3RJ jkS/aV/I12vDGkA9Lndk3pPHH68S1fi5EGmO3wk3RHgUhF+K8N+n1eME1IM1okzoVauV3hcmAG9E tDvW21UBpTywOohbUyvtsL9RNwad+D9gUPcf83MPHcyC53MoLWtuECARcUawawTgK2x1VVYeIcf8 dY/iTUlF63j8KVLhhmOPs69HCrioVmpaCoGF5eK1E3xxRJY+Inl4hXQXuiA4e/rA4bVc57ME1Mll QrrhW8p/F+TsI/+O0fMKoL/0li2SMau8WoTxIZ3URY5qpcA0McAM4xdXDoZZ/8HvqWA+CPYZlPKy ENrANpD7NO8akfxLnVBfqbB38AOFm2SE8XQtEGkGr4Fpv4J3IBg7cAPvJVVrplkMfzE4yDUDxFkz e9YrePwHGbDc9NOuTb2QwUUi6qiiE70whiO3+lvPjDa0iRQI//EKJ44BS7vNRZMjapkgdN9cp2xp pO0GxJHZe89lsj9d6YyUpaI7KkntHKJZbHhsJUcLxnnqwvu4orosQ2k0sO3S1yRU+qgai7VJzYeQ G13393F6dxATfjbHK1oDPn7JfUs7zMOgDhXJbvTQXsbiSvTsjnbSa+ksUF/NHXRYsmi1XfJwwcYD nM9H9BRcsVnsSMv1ZJ85kLNlgcuTHXas4Zsf1EtIoOCLPVnjVZNyD5z9ojAwsKIeL5uO0cbvL1TD S1lWxm5X9Hr6dbdo9fmMRr6HUS2pX6bPRcxdR5YyAYVDRyF34ZdWRSho31ClaXT9wDL2/2sA+Tfj YuB+Y2UpotR9BtlHlcX+zzl3IhqLE29qP6Qq+ZoxrkM2X0KxuXoYnX/h5RtIIndooa7hq/OXz7Ba nGlw9Su5QF0r+n/UKy499tf8oKYkFmnKmVH3CtGzLzHgPUCAy34sl8oKxtHrnP4jbrUZOTS2nirc rb3GCViphkSjpNeA48H2ZirSHRrGFmkAx7jI2rGPgiQrJw5vVSmjpTgI7ICMEaAmbUsV1dvdS0sh YYjMeDSlifkBeZtYQ5f9SLO7aAJp9IBNO6CYeR1scrgWke2h8IMLqNvyCmeiSar+QKus0Kq8SGNz +kI1PDgPi/8+y8z0cYdGg+SOghdu2kirm/Q9aV5lSy7KA239EKXZvdrHqpZxA7zyR81F2f2nMYAk 7OZwTTCQ0GE3cnt1fixCNpYhxCGoVYS75dMjWx0L0/TUzCbby0BH4V88uFzWcVERetUMSawfgnVf MjXoHCVDmJs6OfRHRkJaO4em3XBlwcNkYyyGiJopelvf36hzy6TYGVBIeoTx5Mu6sa5iUIG+Yopr dZDHjlwSGtfCwrmDYrSyaWZgrhNiwV6VeJB9tkDnL+cVGYFznq2RaWT6XZXyGKr9H5neM3LtZAXQ Van8SApKsdypa6Id55JTTvAmsKYCrciSSSLAPx+ahIsVq5ebEWXJxfFqA3RmkOUAyakRC5SYcIG2 EoKDgwzv8lkoO3OoAMdUW0gi4DUwtQ0/FVWO6prLnGU1EYQJGrxIfU5/79MR8XjIx5TQF8Z2RgQV TGj0Nv5UUgiX89ufMa7fPAmEkJgDJ0aWHeCryJNrhPS/D+aa2II1eFQzgLfFMo3QgY/3zNT4zDTr V/m94QdeLWZgYs+9EEbn9TtTKTEWwCzZ2uh9MHqvLbx8d+i5dO6QsZ85lQMcM3AUph0H6dz1zLLX ieIGxWV5VnCVdN7o5OFijkbB8W7/k3SURZZOtuf3QFlFEBaa1ECmL66dKtMbEPSMlAzMRRIoogVk sNVheDZUUKHi4jV+0SJn5Y1EkCD5I3gLvqnY3c21wwpLI05eoRBomFSeqL+aKV3i51GLjy1iuev5 9VsbEBpIPlSjglBb5gyscGpseP6QW1COArCBxjdHHOEf8x81zisKOiI8NSdy6LeYu5D1JTDdkv1S TlPXo0/egnJVH3Q26Zg16N5ax3rMs/uumcku89o5D7C08+cXrBzeOE3/+uwgmI9A2g+g5Y/W8QAt 4aBKlrdSCsOSJXuo/tZFHSJYsnz2kbzlPUI0ZjMyBtPEcoE4mnAPF/PfPEDEKue4obbcQXBqQ027 3hjFotQiIEE2UKsVhCEJkvmcMPjb2wQROaFzZQqLMff0Eo3sDPzTuV+WP7qRSc0UXJFkB8zZs2Bs EvMyGaCW6Xy+fDC1gACGWkrjR4ik7Krd5F626BqF6+OvsbTsUan6k87+bNhVhXudxPInSu3wZU86 x/e+6LJuTwMPmg+LCrHrl3Vhl4q135MIAi+Y+hlS44J17vIhyPXZv2O0CiGAxH3jotTTdxkoF+Tk og9V/CJG9sSa2EJhYasyyk/NVrGfOd/TodsfLn6U6ydjej+ThLHBwF5PhnnCX9R8A+YLOdI1Gph+ bAPMGWDDpJa0q0VyfjGfFh6+3lklyuQz1AEPopcFT5auaKPI9E0ea1gnSJBRu4VFTAowRxM1n0p+ 0oZeCBEz4Xjxz5vbptHHxVtJcajrsFDlfS3bj358uEAezzUUZkIiJYdXXIWdqORHlXZQgzyMslTO 9w5hptbOxuwOjdkItWr2Xc9y8BiMN9vohBrVMzL/8umXNOgpTuvx+pJ7qbOr+xkqaRem3pLZQ+3o cF9QhYnDhlbJ7JSbpCL9aP9dvjkbyPT13NR9QDgvb5xTf3Q+rkQ/Dg3YHASaJIZmBvYB8ZhDVbyd UvLrFazTrxKQycH6IBSxZNvXK34RCOijyCzYvyVp6nNginDYwzbA4oZD9o4y2LO99bz7euV6XkwM rRn+va+eU1JTeJSCQKBDLHG6I9skaGDqUFDNofpDjkoVCG+LbAUBNz3jS8FUoL76QBxPsWeq9Xp8 shR2trvurPo25Eg+mMri0rprxFf0RwMKGJm/XvA/AdRACx4Ga+GeJmfHu2IXnULEQj+nlpBHi+p4 5H2LNQDhJzQhKkyV5EPqAKbz0IpxmXFxHxfnizpes9qajoYsu4mIBSh3BDOpfiAYgSndLzZYyN9i OwqzC9e4FzmYed+lqVxoFKo3H8DSzlgIofqQSKDMfZyKwzK9Bwbe6SCkIZyqA+RKlG4hEK5/bBeu C61el0hSU9qROuo8eYr2oXb+k+8Yb8tVJt8fibyfoQHLm7YXRhAMJWHLfAxoXuCLGiIur3wsy22a /Fbj2dK94oS+q1Bf3t2F1OUiudtfYknj9nDGMHCynXd1++qdttBpvMXIb3zFBnQWmjitKp6KQiVP nqp2rKzdzmudC1GypNpkvJHKvVTwJpOKzB2QfUKtHG6PrLvzcHf/2wiePEHyQGmlu1GgQAZaVUwV ubHKrDqfs7P9k86I3V0xh6M8tTm+evs3nanFzssgJaN7YBK4nxefX2ltvwa1MT/5+PxuPulK4GfD TepTjwwjbAIPXhZ8OPP5V1TncZgStoIdD4chL/NyHzmDnPWwih/cV9IKG2NCqlXj4trmylkccAyi /98z2oGWsX/l/Lw+v7VVcNxco7vUP0gFm0Sfauca9tRfp71G/6ZR3cz5YUD61BrHAEYx5sCSYo0b zl84GZV5QD8YI0CopOx+taE/Y1HcUbdbkBEmrQH2qJlX6GABcWWeRKrPL9z3CIzDC5uYlGV7c59v xbSmGnYqT8/lmYjaOCHlM6AEuZdeXzu1yD+CRoGyCz9adwJPEEy1pJ7vVGE30EUch3q767nF7ITd u/Q/MYZluMTZpVW20tznfEv/5JKWP2TPTVk3Ap1NzSYxcT7wi/gSMsmSm6Bg71CDdvlizmdsBexO yXfrL82MqMmFx6n+4DjjWpxu0jvk9iX4f1FcLZYKAASDsgtruei1INmbthhe+7IQSGtKns6qWDEC 7a/g37HMyDDmaN9WqkppvrqmPurk7FjJeoUue4HLbz5J5iVM0nvLIGm17Onge0LzQ8t/2qjIc51D 9xygMbc3jnueXoOO+VXx9mrMpbUiJHpQx5YIbS6cocgc5Vjl4SSHbB6cReEHdd9tmmb2eOAcpyoc WB0jtL6uDVsUu1IoJECai1X2aGRq22awcDBHgL5LUaeG5WIt6TAPcgG4uRorVpyRBZ4A8A4PWORi 1MRty01r3ol4+SlQEvH0x8zqXtNH1y8Uz1XbAlinI0OLydvkwc/397KeCzfuiRXxEYePvR7UVAlb vWixRtohMUy62J3zKqSzl/nTPmXQFnpULjDJdOtF6j0l38RJvtXjepFYvy6uPezoqU9Ln2FvVL0i /4J1MlJpOdX9J1FtdM5cg5mxCNOoYzlapiYfut6XqJp8+35aZmbdRPWc60//ygaC4KY3hOhwR2gS s17DbFHdfoHFgI6tYrfoT3tbA7nBeFoyK/IeJB6Gl9pNUA8eZ3ioGoDTThC2DvrZkN2Ej8JcXZxS gs378Zx3+FGGECibmTmregXQvpvuEmU6y+t2yAEALc9Bqy2o9kdCuOLdRhWmWMXqFOpbmB5hU78J LQSpQirLhmbm74QgYupzbXSZCYnITnlHIpwAIxi6FjkuVjESl/ATfvdk82njAOCI37kU4eJJQ/nH fOMsVH45hi3i/LI0mFHUcyjKt6tCPE7MJVhziY2N5NIQeh8L0S6tbOuFXGtjFdFe+1bs6BNWDldX EWYlrN+rZ5dX+ccmfYTwKIQmUjyQjWor7L4vzYUXaiFO+F39I/SyASyuxEDykleAL3Zu813Z+j1E gKzjKttSozO1eZs4wZwRIota8M6QEURL4r2GW5lGP3aIYAZAe2TtxA6+vNRRQboxgS/eQwvUsbh9 zMAWet6D0YTTkNz3Fz1rcxUqB/Gj2nGAwXPQqIyLTZgiXrxFh23S3nyJkff0pP4Z5PUstLQ9T/mu MPRCfqOQXtBf4T1334nnHctay5RBqlR9Rr0iIUv6aEQH26WoegvS2mPUAaCD2koHitjZxYcCMxo3 4cfvvfu+wtXBylSVP8FZ+aSQf+8iPHFfW62BEQNGkzw1BivCL1zXLm2r8UBv2wyjsy7e78FDWM2n FNr1zUpV5t2j3qzZmBg0EA7INxQiL5QIy5z3YlE+ZMOCAVTFutX22pfQ9OGEhPdM4fr4jQKOfqrP 2roL1fAftPBZyES4iWb5ibDpeQeNT+hrnbUt9mIA/nywZDGkn7AzBqjTy1F69TOyvhif0edBzkOw 0fw7HbuPz3fe3tlCg8QG74qbx/CDMTShXJw+KMfuT/LEvvWdnricJbsKTILjgQXoGuc52sm8ZR+B Xj51K4zgsui7xTFFvz337c6F+q9IfCkqmY5w9dDK5S/Wdi7g6xKpG8MlEKvdlfqtcuk/mW4ucePz TfzuXIORsECeXu74yB/NlivoaHZwOT7Zcxc4f9SJezdD4K6WY3zBUmLzkz/5wNYN+TOkvTP98CZ2 5krQwhOQODk6ssdKCRMp9RVlQSwMyk6wkZcfoMToOWH4wR4kZXP2RDypx+L9oaoODV4JIq0zIJvE MzI3qOljDQgRtRZQkSMeJvf1NVFgN/pZ6PckMjZ0VjWjW19ySD3nOQpYXFtECzi/tzt0KKliKfqu KPSw6vetZnghhBfw6xLrICy2ermUhta9+IhqiKP2rihZbskhFVkldXx6gZ5kbhn8xne+a4D9JACA NfVsb6/iw01ykTuSaCl4zXF7HDPjKDHuQIQrx21P/uOCYriCCQQmQcda+xC1x1ONH2NlZvsjPG4y PZ5XOXdLak5LMDpV/8aMAHgn3am3Cdkio3umHsiypxQiz/tkL1a7zMgoHABvfezhgIkHJDDoiw9+ IIo0Za7qB0wCcQ3x/tnIT030Hshmxnspmk1rAbhYwz2udrMWuvQKJIRx0yYK2+dqJOArOJjlNEZh kuH59Gtsd+GYOlEGZtJ6vAcNIXJx9TGRJi/5M6ujxpYRq2DIXQYOk/XdSj5rgsKb8zVsVPUBZ5YY 7UAoT+7IcQVelJZham49c+IGWqNuV4Z59gwXHdLEMlFkmUERtWRmy8IhEnh58KBfqNqmHDF2GezY fkJZX0UpwZrqe2gXKs1QI66rBYVfzD9jUX50aqLEJXGZj0OuEU69y0FeRro3D1tEnqx97ggH8rC1 mKCond1/Oh3h4nWujEwY+49CfFCZHLUYvbWmDGWQPTp2RUiLbhM3YnVz5d+PtkNDeyesJrgIZon5 uMjOc0nWvUABcWZfGo5mNuYiUQMxZJKfSJT5DlbYvpco8KUlhsseI4BYP8eIl086DtlHe4xmwCfF tLUrLGWIZAK1A5JcS//LBEA/IQU9X1VjOENcqp2URQAs+ushWWI6cJePGvCbLiWSfgJ5ufTYIS/t p/C07w6viOtwHXS4wfkWhrhe9G9y00UKvApJf8z/rpz+IZtJZtEfDrZgH2l2nt9aq/EmEMJc626k ng== `protect end_protected

gpl-2.0

0d8c29bed14707999c19ddfaa9c3c00f

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/xfft_v9_0/hdl/so_datapath.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block WoRWT9w90GJkMAu5Koowi0SRB/yslb4fU9yuwRrUzPqAS3/r5Brk/xvMD3FfU3SbKR1iV/znDxdP SLKnkQvVeg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UVhUm2t9nTgPN2uT8u83rcZEcT0gKewQc3S2odit08Kr2/u0G1Tcl4T83L/jqrIgtT1X1M84CTZz /6R80uy89MfaACp+SV3e/Q1BJi3U/QLo2H6UHhYs/jW6a14/wbNHoOOXnyXij9ISjANyPJv41pEK a64jx+UIsNGlQjpSEVg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block b36Zt7bRNsgemrSZ/Uhb51qGOizL53jZZKY36Jxvl0AKkAtx2kAhyb4F6Asxk4e4xtyJFfrnQqJN Y2z+1eMp753aw6VIL4nEViULdSgnIvKsq++Rjw+ERxDszylrJB7CvVoud3GGPY6qTXWJLhrf1Lnq cT6ZMcKusvQaHIsV6skoQGk1T33KKb7XrKOKO8nO4iZxq2qPAX3LDGZL9Nn1A2W/XUb5N/GMcxep OjxRWmfFMKQoCbRTUqIPnDhuygcDxblw32XxQESfW5tGxiUxVybenA44qeLobTApXsWEd/fV+cw1 ncn1upsuxbr97WkhJfN+1sJ7FBCfORO8AuImLw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2pAa9UYNJ2HkwZmjk2pfJe91Dm2bBr1oFecjN8Xu+gn452ipDfINSvmFBSm+JWzgQ9c8mMNvETKB DvLhrB6ANV0MbU5WautJIlFjPWPJAQ6VOkHFi1Ng7TvXtyH/WBkMrxscwe6sINg/WUoI1BV2vYHp dYc+OBcwb557XuKA5wo= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block f2bVmbIzM+fWnCfXFXVdmE3crxoyCuAz+DaOXQPOkbG/eMaMZnbTrn/0q13CyDI1I/7+5r5MmZyp iQ14+GCClZCXlCMpPUtvKX2cJzHPWhI3FHm3SO/wFLxvoiB0O12FUtNeexpMZNcGg7mHWS1SlG6k 1jueGa5kSGWTXWktcLJxovcGHgbgFWVpLqu3F7XHmPeF8qdnkWIHyZoa0gXdpVkV3fIGf1n7kmxd 8gf94Djq+0d6AxF9ev5O3F2S/5KmTvAHadgxn0ZUY6WxjpPD+dBTZHl7o7ZPLREXDpjchPj2ADZ6 +Uf7tI78Gd6yl719w0Rt4jg9/wjSRiu9iTCCYA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52928) `protect data_block E7VAtFJ01H8gDXyaYK72eBzGnJvVaxX0xy2IgtOn7XU3bXsxqbgYoeJG/ue9iNdRjSLzbx7BFe6l I6VRNu+fJEk+IqAdb502TpWzhf6hr/p801UhYcnSEcfa8UWuqP87AE9NrUqXt+r41OF7y6yOvCsX yX88oMWfl3nL1GATtwMsYYJZ/ZNUg2bvIVlP/4J4n3UQYeaiCF+mg2tmOwp6Qh354BYu2sszkG2H JOoeR6lDyoHrqXGfoX7EwvbXwd8oeqfami9eZLS0F7fLzL1mAbIS52dTOrcR1Wuqis0FJWbE3Qxn 47Hj5Hmh2p/iltfCuCA3QK9OIBehadsRHM2N6D9lFpYcpPG/oyeAaqmCj0zSPExGXTRE0wrnJ7WO AZrosbYd2PNALGOpseQZmVDOpePuKUhtp5SFm13VlQ0K3IMIjN1R2/94xcHyimFeRFr1MJPtExu8 RbD+kxHuhnIFt7juw1hw7KqjYhbnuDQsKdLOcKGCXw77RU0VvozX3C2tSqJHbrMDQ/4dIQPqbsN9 nYqKVWWGPqJ9/dzGCFl5ZAXR9miqHcWjIpmvOEHJllRvuAgH+1F7Dhv8iu+5xcCCPGZx7tTgFZ0K IE/Zcg+v2v0Vf2B+7BA/53fOuqUd0s+yl7i62v6h2/1tPjEvWNmtyL9gAVyk9jSEHQLviW2p0EKN McwnAQay5w3OxP4sr8p7pl0muHz47mrh+X5F27z9gbfzSkm14Dc/qMc+Q36r/IdEUhfZUoWXwk2x U45dYjTnZGpgyIBcGyloI+1MCNtiFp9NKLJyKn0MJNQRYvdl+taqQjAtDVTCscQycjA+pWUShBKa n+dExsrJhR0I13RVShsFnPF5UjHXVAOqdHeLW8R5axtQzlk3KfEkf4eTuFRyy4dnnXA4fKQTQi70 EbPBG0R94vPvPMOYV/JC1toDBEOop297fAL6iKz2yop5ioIrhqLySEZQyvUqNS2qIIRJTGDclSfe zTZCd9hGEYGi/hhzCckP/MPAQvxWSvs8yFrrCP8vq4cj+c0W52+dWh+YFbjCzP+1e4KODWQ3pb8M TMHfXE68gOaLFJo3A79Oyf1cpPSWQKLMlsfch4cfdKWsxloBbnPDBSVld62XLZ4LEaTA64gCCp4E p7LQmerVHE/BtOJGKi0JkZGCFEqUNdUWlw5OF5oO8qIsK4jfSr80MPs2oe+zitx837+3HIhOhq33 NYwynpbwDOH6d+xcJFh4Co7XNSgghGajdhhyhtbjSc9B+bgIc3pF+pDVHwJFDiBoLF/hfJIOfnSG JvHi+HLgasJ0mfDXrdgLQprHs30LPSjii5WcxeS79i8HJDq8tLKiHMT/G6xfZjuIC0hA1wpderGO dUbk/jHHf0wE0FHZ3QReYolymd7MDNsIBdvJWfPLi1LKW+OUrDnclRdW/ULG7oOHzsg2A+jFZhR8 BA/kmkGsMcI0FB5wvYd1h789+/O0kz7RFtVN1ayAZKAQbQfLywfpeooUkkkI8f6bukLMhCzY2a1w bWiNiyviSALXEvUBGwFOfhl4hBV6aUKmxbqwffogByEB/uMbsfStSC3SZ5KYyrdUJ6hrhKU6F2Fg yFHM/n2ndnKJ8VGuLmdIYzMTeUAk3Z99zMr1yXMNSFfCUWRrobTrNvbB2byj5Zee8kC8XS6N5acE S1ryj73zOBwz1LUgi61fTA7uPWVo6qnDrqTPuzCEbWyPn0nqzDUztihn1blj9Li1vQL38sRWwa9u dR/aOu/btRWtCzPf0TrL2Fizs7T1EX75Z/N3SVoZIGkJXduoiiCu2DTwCmU9bwhVsvtk9pIoKloG OYehinTRSbAMsWqK/f5HkFDN7cTT9zY5nnw++fjiQmcSuZCpa+D5IhqFyEHWgPHr0eEwlXp3WcJh 3lfVWE7CzQl3P//bMgJvKlyoH0pdxemvNH4xXCXcOX+qkbHH6DhFqdJKSCPIz86xGUNg4Kn3gqcm 7R5PI5xtfylDok7ZzNNEIENTsnvgdISuV86ATiZ7z8iMk/AjONP+m5AcMmREaxf5eBtNWkibS+0L 9iW1UsXn2dqFOlN5WtQJAG7twsxWIPOhpJMFVbWkvlTKNMQOItFjO/XTs4CmA3WeI1BmH7GcglQ4 U67Tz3x7MfpCqJjxS/FJ1a6SqMa5zmYIVTv+nGWzF88D/geOyH+3NMZ8ESq94qhio+6Ds32ssYXp Q8BndWUVrHuNcQpNdtiJkjzcBhxwjIS+vWD2+KSpdVVSm7rZ8ZSmrdC0wpEe3vWJsbZ64Kdi3szR qjCJefTO5ZD/auiyOOtVfCt8yeTbXCkYxHhEmT2qpJcuSQegiBDPqQAu6+RMgg2tKp/XypReJmnq aF/lhMQqDp04hgxcG6h98BlXUOvLGpgpy4lgyLrS1Ii2wkqqv9HKGWwpMTbHL/SbEiD61MYsgL4N nU8uCdPxmDwFQD4Tx2zxqa/BPYLg5FgcWnbG96E9Zh8r/im2QSiIIrAC8h5HpSkU0oqRQo2AueEW /1CR7Fom2YPDm7TN4y3u3nONlkhqtpfVYoX7OM157endpQNolmhYMFrrW4OVJAtEcqpHK+BmQfuZ vZJYuYw5mIZXmd8t7ud9+ZTqH8Qo3UIa3sFBOGRlnvu2JsjlW+qm+2iQUySgzlC96jn43lYdqnYd 9r7IyIO4qCB75fK7UyqYWsMuEkOlrmMs/J2kwYqKFa7w74gH2MCH43J+/m2FrVqtPjypspTXu20z BfdlGXnQF8L2EsAPBANBEDyg5UmcjBCI5xctrFzArCI5ULyqtDo9zOb+mRnL8yNrx2qcG9Sq1Ql3 A2V1IPEiMmrGNZBiKhCG4YGKVGksxbjwZZW7Ba9aF7VeI3mXEX88uQ2Md5u/HhUgwH/DaKnr0K21 +oZ26PViNsKhlcfOO9m9ZkGdjpg0WfQ0QtYiQEOK4Skw1Wo3fYllKWfxeCuAVB1JiP5c1VdNugwD RIzQdj8VsD9QcRMukf7rxI7wk6JY47Lj5kZmqHwyGL/K0KzOqy5ZO8s9UjaRS7FIQtvWtG02fJ5x yQKBBsyUN3iJTsY3ocLpw53hP8sRqoozAdHVCnbfdy0ViuSoRng1X0RqkaaoO+irQ7ieZROAQSnJ YwsY5b3JsD4/RYjwyeI9UEtHOTVem5Dlbs/30uXRV1LtEdpv/EN55F6UX4Sy5AtjfVNYkLRitUwl DAvdXDaw6RCbnSdIM7xKxxKW2VQRAFPAannYmEcW38zjYoTm54HJKYilhKG1JwFaI1lmzHqMtJU+ aT4cIf7sDFeH6CEtH/tfzOtv4M4DPW7B9u9P1fs1pTBpFsFxM535mSKrDFfvVomIqGWuZ7309XLR t3gFoj//QRpxVlfr6XGXoqiJ7ZHrY9HQDvowbh432qWzlNCR/EdzMs+4vRSAJtkW2LOC+cx6TmuL sioM2wP0bb9VJQSORzMEP3dQpg53gqzU8Au6gxF9jdDH6jugZgjWibDY6R8ZoY9+6mfF3shkiLaa hrQ5JuIFpy575YQFwlGXflXaE0Tk47q0Tg7AgDnOvjbyU0I8Lo6N1MKmmliZatIn9sL5BbT699hn 7//yfxOW95kX/0siixo1bFPpOdW9TJ6bhIWPzjIffWceE6M1RIWyjHdp4qztbQFk4VjJxvk6RJBs 08GbeIvYGcwO3fNNFX9g6enKGZiFSjbgycgV+HPu7LzKkvnYfHSbtIL1vJY0LuK5YzOv7aB0tH87 H5BX83txeWICnwXPCw07hbBC+yOLKYrho4Xy/Og1vV2XxUpL+1C8bv7bI2CevqMPYlkWzoLauCHY wRjgXGeHr/zlYHHpy9s/If3g1n3a6TkXXB2Nt62lVoiPDAA3+8/HLXQ3c9Kz6/AQhQA0TzalR/j9 cTKLX5To79gVPfzzDPZNqREACVwC/2InzhtvXJWNuI9P2XoUJXiHnYAh9+JNnuNWUv8XPhbB+Jre CtJacEcdcMgmn5qJnnBk61x16USb41wPG6Y2JkO+9iAZaGG4nnbHb2SB0myYDdQM4tbcmcZlYWWA qTXZCk5IhRHUwq+jfjvlakKNVQ2HsEjuSVZcPnQjS2exLsrgF/uPPf+vLooeGxFPin1s4hGp/4gR T2+A8Xxwk36uSQiow1VwsaAeCtiCq6wA5z2Lxw8m1yT9Ev7rlA0dyzKX8BM0/jka1YvP1igrsxu0 1Jal62kiTGIeWmEwhpl8Wpc9bV9vumC3WkA6c/Dk/tcrmpUH6LIcH25nLh1b8iQYaYmUc8FDEA3o fNJV2y/ohIoVZBTwSzEvCmTZS6Ad8P3NZQugVdloNRh2c2gGEVZwp8heu/ijGZk2QVXLni8ijRwf nL+/qfjL09hM2wHY5KxlqUQNgPyyg11blfiS1Dr0g6dQeM5bJecCJh2I2bZFf5SuX7WsVFG16+UV 9SqxQEN+vmf3Ydo1LSGeODxuHbbz7ba8cu7ogY/gjwx9xP73ikP77W32H/UashHzYxXJTCxMUa3Y RNq1TdbwJxLcUVpgg80HpyOkTGo/M2ekSrzMQ2sRFBwgxteLNv2FlykCN+lYU1zn8xCyahURaoE0 +3KvQCIIpw1vYPUttQSa2sWkBzCegC8HrWU1/mu5EGOuiGqpqhjtemM/EIvRsAmSnazFEusoipAH 1w+pcSQ/msryBpJHJFv6MJShyK61d0narJp47VHJoclgcfSPSWKHdmLm+No/i144bXwd/ce7vfRC t5FP61NzAW+Oel2AEDnKfY281zrZMqL6t337PVDB6xhuuzfjs073LNVpSvKFb7tDrDrs+y3atYfv e8LAHHOGf3bXCPIZDSwvcDycMHjO2vITlCcPu7e7CCJ9uvdW6fvryLzzPhRzhiJmIFwSMAP5uF5Z 0Ymoleyt7AE3xQlEiBJJLVykJyQq7cGIqxDPlL0YA/QC5eWPPS/ikryt7VwQ6c/3MM8vgaS1r3Hl dq34ZSaIsX49ujhclfUZYEdy2yV+ZwFUo4wa/RemSiu3iEWAbCv6OSjStkfAvNpTpMXY+RHVL+ix xJHZYhu2h/4BdS4yEgNmsLk9ENFjSAaOD1yuQs115bUUIjRNYEDI5KQ79YG4E6eoUpTnV2jU3T2P shq2dGY1xeaZbev+6lf7z32Vab/BNC8bGDOCS7grDx68Z+YBEY3dTA1ZquGiw/Qvcdz2YFjIjtG9 LSbYOSVJfw6A3wc6hJ01ChUJfXkkfQoizzy8v04rzmmkadVzzrUWczq3Eoa6fTNXLHxPQ2DK/wr1 BdPRvC4SNQLZo6dhRRFxCevWNH6GSpVpmBo+rI2spXgVXvOCBJUjGk4G0pp7iMAXtolXLfElaTf4 rk2dFClQXeyOk/ImbGB/Y995t05M+EC67BuX1dqWG+CYLi2RPZDRGWphcD9WICr/eWtVVgoCG3SS +KRIygVWkB7XnokkSfzCKx+0fLuKG08sL5mKiw6ImCMhvUseYuqMn+jhSZbzk+RWWuWPXQli1vGF sObUih/4sHgHE/SpCwt8PMKiYBawBUwC6+68fR9Ud6zPZVUOYq5fdO2Jpxxj5XZ65cw+x0T1Ysfy odVJNzPqBQC//KdidSbw5FgrJF00GOGzryT0s4ePXL9UjPpQ+10LGsnwxWP0gY9wdJgkVFKX5ye8 A/GDYItJAzkGrL9HXo4zwIkvzEmbjoGt7JBd3cKPtYkfRI+9rkx8BGwcYZhnZsI2lRHnexOTA1b9 /uwpuH2CcChoSX1lHxjYF+jqc8RNvtLQr92EQEB9/v/XzDDblc/25iUVDmzG3NJDlSdqp4NT7Lwd 1WZGdskIs4IZQ1C8KHZ/KnyvN0a/q5JpWLO7OwIGK93u30F3zU/nYTZZSw0+g2AtC1gecXBU7cjC LbhykYJk+jO0tIfAV57NfRgF/E5zJcBEnBUk//rIadL3mvuuz6/h57jCXm077SKbY5WjM1RhOwiB lHI6eLyl0kX2tq4EdJ5smrM5+2Exu+s7YIMbu22yPgfK822ofNAfD1+r/Yx06lws4zO/GX939z3B jt0zBWMfPis3H7ZKjRIUzK18tQEO3EomG+WKyh12I2vlUWk3NugK6EWaKn29kiIBvJqt/BsyKM3N LCZptc3eWH051BoApcHN+nUfG8DSSc414Pzb6K43WhoPjzaSkqGsY8KX1nM9eewOIdq4MZu3ly+M keShM5BQ2qMSoSBdCwzcFaVEYsf60xxTTXdP+BrnAbZPRKirsMOltvuSKTayKB6oQMl4xDPcNTF6 o5k8vQKJDYElm4fiFnd1R626KRGVsPim8dY5vPBjl1vWp8snEe1vbzQTkTTXWiwJ3CZNoxXJ1gI+ khuhHyyqWijBBYq7aVjAP3kKtlWo9oxYynlBTEhgyKiF+e/56TALNxnM12mgu6wPYx7Z+qo+8LGb shh7gy8ffe8kgVB+hwYQ6vJNIWZJyk6bxB9hcNmxR3J8CIzmJo2yyJKH/rQ5rDNoyTpKNXmlswwB EAQxsWBoUfCIv15TqpuvObfyQMxJeYwrJ1u9DY/mPU5i1JJ4IVfoJi4ikCAtwHjpy+NBCscNxjl+ zDd2+hZMUQKnG+FYQPjmGIAelZ88Re/z3Kd14S1bEzsuNETJ7dLikLCKfbkFf8cm4ADxoDujIbRu UpLpXTa77ZdBD+JjcF8ueE9VwDUogZ5pgN2sK8wdoL5ZR9OHJP/R0/dfFMNKrwqAWfa95wvdTJwk dJxYH9MyGt80NP9CLR5NF4u6YGh2KEcZvpEhin300X0ZtSqF3fvMcXl8FatDdtoEWqd1abQchiED RvfVUb+ErM28zvoBiVSpzQhpcKwvKQAZwm33gHO9Sy0RsiGt+ecCQlKi315JBvxzk6aN1vk4d0Mw vgGdEN6rnquriZGFMWjeTs+y3bmYAFUNtStEcHoli2i8YT8+iIe9+z3+T246Gc+RjmqOJcQmCQmP 4Sma8nhtOr7YB3bIRg26VQzqk/QZTZGRNw3FtzKnT4DmXEyZ0hVG8D+siKpXFqsoVq/jhjvQIwjC rCnWUmAHPHPPFqlFVgNtdLxoSQybeGCGXhQIypbJ/bMZTph7mCCDsGY8e38xlJUq2vIN2wwzQBM4 2cg1Rq0P+lPbSdhBae0hgf6jAKCPah3/KDu1kLczLnglFMeBt+FZtUv+s75GVvvGjF6kY3KBtnmZ ZTUQ1xJCoowylpTUmRQsn2PsA8kvBwHrrCcWdpDn6rA9hrkb3jEOq9IJyoNVuXVgcVV0lIGOisZb lreZu93J3hJjtl7QC0zQIDWRpaTbCB3XHCn+0Iz4LKQKYjcrjW1N7dcc3wUQmKwQKRziyd2R0Art AszizkvQqhaytvfwyj5UyWpuwVmV4cdMqX+pkXRg+72uqM1+jmp9+0G/9qurKVV7CvuD/SfKzjnZ FBthqgZ5qN4wy6lVU7yQp/Ev5ALEWEHeNwwC4bjK08rfJsYbIFL5qaQy41BYh+M3FPBKHoqIPtid ezQQ9GcUNHu0AoLeRswyx9FCmGw79yrtHfx0m8wRBms2o/keBrAIweB6+36+MekQpfxbZP611wKW i06CVIiIxWHuRCYphaLxIRrxgTZEZCjCDmkYLsQoqe2D8shDM7rmwUWbl665eeo3ksu5+wgbJ9e9 eBXkUFUnZlmOB4R8//rYDfUh3BEXDKeEdz0AadsYFcUR0qVTEDluywnZRk/RrHEubkgPrOoaHnkQ tJQI74S4fcEsFkx9Km4mq8PkGsGHI3C6U2DPCGUM31+YJWvne75HBpqbfgyxNQZJyrpP4yJDd7hM fh6RxrmJp7RoLPmlGrbIkr/GiJt7aZEk4N97wpTtLGXexxqEPeukfnz5Wjfx+uZpnkPY6QXSZBIS XwVovolI2MzLq6Ilu5j/OoPiBDA1qi+AjV1/18YNez4J/uitl5WE/e+QRN6Gurk1e1s318h9ogwn rTdesbzhScuMDDctZm/1SGqkoRkUqJ8L+yDHDWcmz4Q62Staah/ADseMi76+wsXJm/14eXUi6ell /2gCDMHx0HG7YbNnCLrQS2rMlmYhuNkExS+J+v3qY8lJmV1G9/gPhrRR5iiCDsmEYOy1mBqoEbZH pSb/srdrCs7hjNlVn8S3nzaq+YVNNA88a2aoDDRAAQ98GXLRdxEx3zOAj9vA881FZN1bEaPspjsG IUyCjFeIqlmHSuxtZewha6VTAGYtVcTYXYOPIEDV+ZjCX2wC1pEM6IVP9jy8IhPbJFJRX+zTCC0f jrBdL3PilQ9rIgiDR8q+dcS7y8COgm5JwCA0C4VoiwKcDLFN+wpq5fwIqB7O6sN60BqO1tNOXngC ktIL5FXxah7hFPVfHnmzEK6afO67hbJJAHvVnK8i/pwqzbCD1I3PivuBvW3BXSKLzZ3I+2I1pbvA x7CDgJeZnGfraK2nB/haNfXIYguAG/A1/M4iK0CJnACLVmXpM+iM6q8DaBJ6pKVqg/kXJrRvSCKU O+47O2Se8PhZ4VsU2f7It+QA9MEXDDCjb9iBa0WSKmRCTmO8UKKEu9RpjdmZ8NiWIN9NTAi1hxtc J8gIcjGKpXD0z3Gzt3YDe3akKa0CXyj/hJt+KF2T/Xn9O3AiAOn0VbgVDW4HF61ONXsXbsX0bUqP 9GYP+Za9bSdwbUBNfoIGDV2f06FU80/vqp/wG+UzkfsFW3lDb+LATTcn9jriCroGwf82m9Qgl5n9 XV1SrEU8U9d1QVCO0/AKxQJwhRn7/0+HX4B5HmliyWlP0hjRoyuAs0KbKD6WEt6ONhee0BfmFKqI IBlyg5CzVSy8h4qOL3D/AGBMIadbvSASytobzCVnXoEvcvkeToc31h8/zvykWCYSOgdACGmeFw/V HIO/dlwbr/3hUo4qhOVnEPAZPkHjBn6pUK4Uy9/gahwhdUWpy7jP6ePjJ57E8nNsALSngbxUvfhw hKKRSSFnZQjXv8VPhrGvhGGGEdqvs6dOtRfX6Hn04FuLJqj2mQb7cnUvtPd6DdaR9QIj1eTRX2Cn P7kj8uV2uSmKbac5pG4U3jDJW3HMyBVws+eUlZ+sUw0vZ7DRdGOE4+BIKwwsY9n5Zn0A2WX0bdb4 ozRUD8y7Vx/4yzmCcMEtUc02J2yUw+CnsYffqkLunsGLaNZDr+MA1R/jPd5ghnnjeNLP51OKcme0 siTDGGMvTA8zDak71SLyXsXl9PteXXdAZ+sR0DJim2noK2uXZMf5goZrK2nZiClpQT0wYs4PfuLN iXLZGioN6GsldxOHNDJRIl8wn46YXdKgVWDuw7/mEN6q5EBjk578P9wdFx+88TY0i5FFoGW0U3y8 p5mcZu3fHpgKDeSaW3ZNEHfKndUdIyBLTYjNfIF2txlldnfUNqnLCcuDbSKekSBMl7TaP8EJAF5z UW/f1/J8WeUQyBNjqAc3hpcPULUijRRE9N/KkUQADTQo1qV8r7KkK0n9qYT+b9gi78TUsnWgfP34 0VQG0bTphWc8Aq2j5bbS34IrGXPTGECvUGRKlTQDrcYKW/yo6Tit9TmOif+5IztHBf1lCFgcuCfe k0mPSrmgUgnfsYUJ9ledyqFcbDhnE1OAy+eW20z3q1YWRRSY7TE7QAEzJ2VIqAaZKTh66rvi9KYS cMAmOTlIsyZ/vDBbJkATAxlEGLot/kWDbsbxJLIqXa+thfAhQMYGQ1VdNlf2umJfh2hV4HCKcjAe 1GvAkD/IBoAIGsEiv9KIegOqNRMdJr22RkFcZmo70atQU7GA5dK4Ke2diE8Z5yS9YIZpBUbyKExE YmNnDO0jiGTJo6HNUPsDLOPrYx6XxUvUIIXSc7FT9sWDCH6xdwQVlz+5UtYNaZbfYSAg8PBUEaag aMd4AGP5wnmI+kT79/qe9tpLXqiIcm0a+sTOfC6ofpDak6JFF2osMHpzfUAB1RyggYzZIXYDvh/N JpflhdeJxG+bz0VZLI5//2Ewc0FeT2tFrZZpJ0p2Wx96EFgOJBjrWGaCa0ZeDsX5EZzMr6fmz1ca mRmHzZv0Gc+v8odyREDbJiqdS335l6lpUTp6W01Pf9H40Ydn3Da+MxHuVyQaVLYnbZZMbrMLUHt2 kCpMAmubq2EU1N49pN5+RyCxStO4J4rk/NdGrX/9riw9fYUoNFALY6/kYZhJEZrZyGFQpA7d0k84 h7rnzgFlgC3Zu32Tcg7SkEguiVsReQjypGKHchVYS+zDLpacCaiiiHnm8KU/VQ4FIEZcYPQ+HdPd KXXvLSetwl+5RJ6ks3PioBtVZui9WHKvoKglGowsk2Lr/dQsx6qXdiwz1C+GGlTHE74dK+fkKpp7 RiO9OdABI2qyWCAHkUJVJPJbQP97bpGskTiSy+njyGNSapKp5hxGQPjPNVWZzq9Sf5dRSRchGw1Y /1dQ3k+7eWG5MVpG2WYofbgx52QMtmfP4PRJfoRxS+a50nIfuaIcIbc+34CHR18XQmqG9i2s7NPI LS6LxxUzJ+fmZ0UuGJomKYfxltv/5/ZHdH4tDXIUtI84Lxv23txduY3k1uVWjbhIc3NyVinu8BMm lEW185MJQnaPcyqN/Vk5Fuxz5rlnpalcQUpIhD/4Nwtb5MikWUlEvpMtzNe4tqk3EjGVSV6/VeFH PVQ+4gE8tFUfanBjMLnKGzqvX0ySc2fHvjB6Eyd85dJATxVi+eKE36F7+deRfPL6eU+VjAuhqvM0 hU19QRmMaCv0OPR7bRoCTQq6HaMGbxUQ0WNXyix7FHVkYYZ3n207/Ug6PTxn14pyD+d3aVxbb0T6 tEE2QKmxNxe6rRhfgAouA3qyTcXVfIPuTvfc90hhapQyjuJ+YIgdsn1bWVXc1QogqmM51j2ph4uN 5wjS8fafkBuhteAPGp8iX0kZu4aBKBA1w01lTeUYFUZR+nVQqE8+wUc8qNdnCNmZVix8a3xK/9nm m7ZuGy5FXmC8OR/73sb3QG2vn/Q6ssIMRi4WNpniq7G1CmOWWB+FDJ7zXs7DW0BWeHWBLKbqGpb9 Nnmc+JjzkAG7GGclseOPR/RtXY5r7XZ/vweUA9yHyAvaJZ2QSmqLmpIVQGNyoLEPwUYbLYL2wAXN IqOS7boqcc3tss6IKlG7RC7Nmlj4+bxsXU7V0Mt5Edz0dD6H0kKR50OekQrNWJOTm0a4MKHD/huo w2do9xLRnSMSstGR41ZN1SWQCGdIXUND4Xf0WTAYKkBSEndSJqOOrWcLH9zy8hZEQo0/kNYmHjtD ccZ5JfrlblAfLlGRnxEYOhKLxvNFtVMWQxMO2gB08NEwdWC018UkVSe/rB3huRf+/6kWbFi7BqiK LSR+FuJ1BOjwWGoO8cjd0pqI5lVgmmrfUith15aq3IGaR5xItUzEO1XCPdTtTsm/yytLXtTyZEKN BRhTK1p7tENnLQpGAa0xGgHnB2ZJhfLyCh6rxX9mGZs8cJbmZLF2xbzTu+afme8R9kShjm4Mv8h9 2g8zn0ShuzTcirXot0k4+i2q4IP/qZD5/j3QdlcwCN4sNKtP+xFeRzGD83G3rOp7R/Y2IWwuYgv9 PRIsZV4SOca1DigV/a4pMtoBolrsubIGWNlv5UU9Aes53BUhNaubfny1NyfPa0VTHiihg3AAP6Wg ZjcCte5b94/Pw/JOz9o2NXc/EAghBaJXD0ZrNZjj0htEOjzGLtsAM8EbJQPbljbPqyDF+YZBz7eM JGEHrGe9XQ2hYSI6HpHP10IG/Kf56qL6ldJ/jPIdc7JEYgspomtCxFrVH7hGN4srSs9bozyWcpTc cP0OzEmtdK265v0nWA+Vp1T4p58MfP9r2aW9NXRfW6tjr2vS/QYab/VYnjUBFgH0FoeEBsb8i5md eLxJ4Qy1kpOwCqO8Nszx03+O9J/kzXlz7xlcfzB0kzxVFEWfyaWbgrE9vUvEKO7dmF7b89vpHcz8 E182NodWlVrMw/8zm1rua5KR72zwoSZxS+bBev5q79XO+LYMpY34M1dLtC4eQGyX/IgKNq3+YPqm 7o6+LDgd+hFGeijjsXXaH3FEZwetPkfe5oIkPLlXYoJECOxn3CqSsbKoi9tTmrV4wGFdy1lYnx7V AqvqmfXRv/29ph6W9f3WSVLRYv68lNi6I0cmtuM7YGEGwGxyVE33ByLFoenu7Xp2eBA5Osg+EQ1w tGaQjbE0egd8Ls54TBpwlFz1AswyhDm4nl4gWFj2kop9JQZDabvN3/8vSfzoERiOcSOLJ2Z9ns0M agYs8qPhY480J61GWjSI0udVhtv7x2UFm9ETUSw1qI6OjZZgIkTLfa0f7TgKdNoOb9Bu6qAGqH2N PYX7J9Xf7gsLZ4Lk9/w8SWD/cc7+nw+bXcs8JMGLfeiuLHi3tbEFyIoZ5aHK+H9SY3k+ejP5Y754 J2VJLmctkclUhzFAmzh1uFYuW3dXK1DZNabHNkY0w2WuODw9LuI+3IcAO1HL1BKE4opEk1k7U2OR i45jemAM+ohE/E4q+Rr9LhRQ6WTXswEr4WM1WZzPG0yGgxnSnLSRAsqIvo0Ytz8un01moQz0DBqa +f6Rjwny9MK9cuqvFXRvXSAIqKyn8QVnMTVgYMTdG/Q7cGGU5OEEuqdv5hvBeAyzPeClpfRZmYD/ 76DLV5CjTAYvs+L/khFdbtSaYQVR7doLDQCPPnTErKHFTxckp2xcmiAFfXuK/Y8LhY0p7yieTTuI Xi10kynvgOFyV75d24z07qz2mjeVT67uZZ79BW4RmvCb6PxKtQFzrBzB8GZ4q7PjqvtZQqpO5jHK ckqFiGeZIzeZZpNUOKZz2LNHFVyeOJBx+meY2tL849+FUILwNudp6UhvS48VfNk3XIf1SG5s+05f ZCIg22YnYsL50MUGx/bf/3bgMQBOVi0oXnHaecIxXRIyv6j57q0m6gtgArYjlSUmevIQnZChETSz wWA8COUiH2V5dQGZy7ao+pIdOyFHgLFVowCRmgt+FmQR5/DTnQQQLVYoftfBT2B592gRygE18zHP 98toV9sc/nI5S6hKoSEpqJtP+viTZdhsMP8zxjgm1Ry8Xa9BuanMnlpKgWYaScGuuTw9wy1gDJOm aHz3ntrWTRTH7j17dpM4ayTxJtU44tOb12nse3vQwWigwY8dVZAffSge9oQuPK/NSK5s1GpjPcuS r59YtzsIo6WcSz3eGzh7A5ZcADzrCim5FDzIhrxRuYb6QHNrqjK4fmFq9JBWkFblNcKxrv4SdiQx kwnX0JcP66Dt+VDaGmMXanlN3stciT8pHIoEukKgCcp04kZ4WDBHUIN3eSIEN5se3YHT4gjJmzrk z+/QmXcTiiNtcXteaH9aJd/YjJUJLTb80hpFmVNJco+7gqC44wQD69lttZEZicScUT/XX0Tf+BNd nXu47hp7iEv53jQ5GOmeQZ/lzKRS6nJ3UfqfA/Zy+WHxKbwY9/IkUdL/utFedvcJ7wC6m4cOjk5g nZRhbVfdvivjgCO53muzfuUq420AYAOywhrqlwioly3hdqKid9/y3W+zCDh72NlhaGPTaeYRSAZj 9bKH357jF0hkeXXtdpvvqqguLhjKS4fsJtCfXGB9nH+d08jE0g9DAQWqJjxU2y3+zyY/LXMc+iUc zTDSgvpRAocDccfr69SegxffGdLLen0GscYGcBeQ46LrjfPBvu+TUiPitTq+Fs4pIcpKxVQQXwpl o6EX/xi4Ih8D/V1U7KnEMavC1Cwvx0CnKIvkSQ3+ruehSmM86aA9Sr7VtrXrl9dL5q2qiBCoKv1h 2IYiR9irspMQaMvAh0wpg6HTkRgWRnDhAPW3+VFg0+ydTgzqdH/2ZbH76RenPlPM9TZwuBGc7fgI 8hPTPwRvlfEVafIGo4GM4w4yMp1K/Is/9c8QEwtxQMJl7DxaDFw/9shFGznEETf/V+I/8zn752Wu rYsejQFdF8WhC8+8T6CN9CxWe46RtMUj2pb9YxopLN65bRhBXpWLmIhdyO1bJIX3W42BTt4zJnsb wyW7QqH9wkTUDJBfCbd0SmelVFke1pkjlXvRU4bubI36cqaQcg7lyJ559bMI/997XyX1kzdUmO8G 0BKFvRTPMChL+w7rdFXXxAPm/a/HYyHQt8EO23fSVSU1/QhjmehWfTPWkUs4OeaVXUezfe4H8jgx QPX3R5SgenGBoHDwXmIYwHUvVZ4kxtWKAkDN7EFxsmP+RP+6BhyQk7J1ZHGF9ScvpiGBUhUtOr3y qNOugUEPXKzJf1kiaZaT85QK70Y1XA10TuO68QYb74qvK4j4HWoHQXkAT5MaphK2MhetD04U/sQR SoscfFuxsJmdJwvzSBq8nfstxTq643iJn1PBSbIqI8un29IUSfc2SiznBNEia767BqAC30OQkCJC dreaGXeE2c7ZqsIQj8Kz//vs5tE/4E6uiRNmlQGoa4iyUOZuAS7iCyxyhElZdO/03NmZTDftT6YQ LF4mpaIWL2H4A/vXfZyGXY+trNdIKM/PBvuaSl/kYLyfRwdarJzjRWs8mn12H4ZYR9sPzzOt2+0V M5VpHNeHu8OyjSm4tjD4MklEPAFKF+QkCooeP4DUO+5wmXPzx8myHif+3TD0R4SVaTQ3p22Vgwws tC+82SnxII/FVhfnTFHxaaw8CBDESfxD2SkkP8g2dgdmiM6Vna2O4dViQf9gLZBRVyo3sOBseIoT ruMZboBju7yBX0ElTtS/bjtvEvILqbP6Xv+meCjpbTmDfthfqWiNjvpiiFXpPPCwgkNljOjQlPc8 DNYoUMIA44j3DRMUTQy9MQVEopN8qemZQg1O8ZnHsGq7IziPon47zAu1bo8ScI03eu5As6csFo7N HMK86DMT1t0UHXI78BnLAKuWuxhlA11Yq+ro9SiSRdu1V5+gckvDGpN4uUI1ft7+AefBeUZz/8AE pk1advYZAogJih0dq/qZkquz92kbE8l5SEwH+0VpEHd9dyx/0RbgsmAWQXBhMml/1CwhwSeUoPQf tFsT/N6pJxVkhz2nd1TmGqQfLRNAmrL5Y7qJIoe1ER6s0Ag9ox5+tu+UU9eCuyGFwkK0xDS4FIt+ JStl7wV7X75lwGWTzb2TtDuq/nrdd3i3zL0Ja8MyaM36L1SMcM02nbajWj2GAVkHfXHLA8ImCEqW 8VlIN/W/wSdJdSXwCJ+lR2ZEJZYL52IIDI7G3kiz/fSsyQWaHlssnyVKbJvL1Dz+iqAvzuRYqgZC kCbKI0uBkh4IFJD6n0nao6GRwRsrj7RSm4kkJSshxXDZ121qSMJXaXtzet8AtQ5txut4tQ2523bC 71BxXn3z5e7Xbo/GeNnh7AD5mg/47VV5olFHu+NKQJ3YX31zfru8lmu3jIIfuD+uyFWSlTG2bRzt lIADirR8+Qhah3vHwNAliSlnq8jV6DZAnVsBWkEsX+ZoNb4gHspkkzs+aWdre05QTdJlR/V7LBCK MSeocr14S6KIPdhaoiTpx1A4j8SScQO+ir5n/f9AMzaT7duM+AlN6x9s1ihQdfcmPqxv8Vxkyzsv QZDHPglNBdK4LerKBcEBzK4CHS8wSVgJ+0WX1zTEkGmUBUHnX5uUnWXxhsJEzwY2PXjARRlhz/9l Myga92Zus6+bmI3CAbzB1MC/6gRfWNKmTA27TSXtxe5v3dPxqoCzO7e/6+4o1XnrTJwjqkREX9Jv KjASJ6VnCQs2Bw6mIk0NgSDFvLpVWdeCLyk095XDoSudPPNKIHsOjwgcOaqAIvlzW+SChuhl+QFv L7bY7FX4HOUGL6BymZNOF3N0F/FlS15a6C6+6a2vMRWY6xHJIB0xPUahDBJPlwOeLq/TnJr/QT2h k4PuEKcakzvA4NAF/IYC8ld92vgyeF2JJMceVHfCxNG3DTUXkUmzY4Lo799geby04KSEs555iLVx HhMgVgEA/BLhlk69dDI3f4mJHNxEkpz/Gf6S4eb+8Ct5FPyUTUOHO+NnEjzJ1X/CMXG4iinKYqkK MIPnS9CN5K+dCnEy4Aj7yDEjymto6WSlbrPd1eQcdlsQjZFiafW2PByu+p32o0sn7up3ICbsqlqG M2Lb1CZOa6Dhc17s0W3IAv3iMr672RTKQVGF6FXhs4fehlNJH66Ti2l11EyP5NbWwyWqapMGXfVS H9ZDrN/FoWHAgATe5Q1nH3rzoML2Peicm4jwtBSVmfb0Z3Y0Ei1ze9NkdjGs9zWPFz4i+S+h+zEU EKfQrvI143hTfEFpv0WDUWGXz/0ST7FLjQdqoaLAMEIVBOl6O4IjaVkcGKmYJ7CD/ch5P1S8b3YX /SX/1T+apq9vmZyYvNlXC9vqt9tor55qml8A0oYvyf9adIV90361ObB8m4Jdn3DJc+VSY4E4G0Uf ah5b8sexxxRjXR3w5zmtSBOc1eORUc6+tRy8Lwt+mfrKkn0ppfiJuWalVauKIQkEnW5Ac2aRnren rbiRKbxGfSjGaK4lG1B4Gh5GkmmMyYWsfiux4btqh8Q+6+3XJMgs5/GMvc3LWHN4X+BSmBmEhnPB JBdl2lirdPLUJF3BdPOJNJhtyhAUQAvNk591l2VMD5ske2LmmOq/tj8vmHpp4YR2b3/iEDthzofT p+iI9fV/UCikWhiSA0Vlk3mBevEKaFuhI+DlVIqn6hFdC/TUjkoAkoMgnA9M5Infcvi89+B/zL3q B3f6faENnbaXDQWkWpRIItqMbM/LMeVaFdVVMUd4YdiQpli9gyDxKQG4IVJq6AWTUwShHSc8tDBp HyJmUzRur1jtiQOCxQbpSK4y4Sx5ho3XQWGpBVoS9XepaXR+9Qls9od1uDsGd180TfKmR8rAJ3Dv WAMwLkAeWc9XdiI/zAKldCv8kWztfGkhLgTCqvrgYKebLVBc251RZoQxCfgP1ifBvGhb0QT8LRIx DOpJzk3X/LCZhrTKcPBsv0RqviGV+qOiAuBo9OhuXN2MtTKQ2K5t/XiQaMx6iqMZXMJWRXsl5h+f Rv+TCfigwJKajhvxK6R0tGr24zaBrietRCa/l6Y3IBJHRYiTphQ/4Tur0xs8EXAYpq/4n+u+85P2 paNgZ5BPcDTCptKNXP17+DTrKBEmbslovSCtt0LpxiFEbqmV5bO0RcA6mUhwW3+tleWdpEpPWUzH wDM2E0RA+OzfYaSrVMwXC0MSzD/gdY+U0jc27IHcPlF6xqlhBqsNVwlDCM9cl4WCNABWJRfdSGgF mXcHFjw4lUeAERO+rIbvlJLf0/iQPjCWFk/l3y2TPMZT0hQUvP7bzxjDQtzRQxVfn9avkuGZJbhQ kyBFEjxs6i/+HzN2RvHeuQMfs/JllCuikLsJmK648PiKc1solI6+x7h+dS5H9zUsd7x3vxLYDu14 J9bXs73zKijG2/t6uSA6HpSfmBLcrhBnlNLDxKN9z42W9MNTwUiwKpBMQXZAawIRkfYNZ4fm4vB3 Th9ILl9/UGV/3ituyrK57ffxQeZZuBiP8oa3iN10eNdb1t0TZm+7BdvWu1h9UXIjs/2jHr04moKj Wff1J0StORXyALJgqEbO+L8oqdaWQZoI2ZmZE1ZrmTVFyPYG8UXj3XbIKdQROGp58NCN3galUcQ6 aiD6Nt0pSBPqlDrs0EeHDlJTc+P8Dus9sLapzgc2ap8vZ2GSYvMSxJ0oThdIEkTJEBsfz7+Z7sJG 0AyoHEVRgTgFo0os8oWu5O+NVcW775Pz3meMgiavjneng/319ZXTU5OoH/C4k4oajv5vqXz0H2LV 5MqBlNBVBe6aBEBnXBEOAgP29cdS2nScQ5pU1OWhq945+ciCDgcZF2REtVC1h9jG+7NHrwlxQVGe orRI57sZ0zFoT8FiHAHk+F4WGQqxoqgLLyn7SfpVqre5crUiHTZXa34BxGHp7AYqVH+lm6po2qnR nBDaj4dZWlkD391mAJYmK8XSuVM2Pt5Pfw0oBYvazsqim/oco7ab1uehUCCa8CkdAa7Y++uE3pcZ GkvROiUS+zOA6dw4AeHKE6aCsxRvQMPXEAfSUER6bbY7WQ1VnT4uNUcrZ6wR+4gud8/AVUX+MNl6 JBNxfTG7UMYvLfsdyBQAqQSsvF1WmPm3XUVjWC7Gp7HezyZAGzXcsL5vqdT3CJh9ehigL3Kzm00l 12t6XUocrke44UuSkx8dshSoFFqRQ/tfMVfidWSk7Bu7smZZkPQzX1T7sBbeWS3puKcnU4zqIMIA e8A/lseqlUAiIrOpzOG8666uipiVWpJkQ0pmZ94EnPIBYxwAlVgDR70gHSJu/LY2ycYHPoHFFrfC J8R5KnxSnL/S8EKh2hV1IRcMmwIcttQQ6n/J0b5mkpcAlUme+VdPc/qwqCSWT0WgDu+1r3ZRma49 2JjeC9wWIByF1FmC82GNzBm5tfNQuN/hnJiRNxfZvI1ky12cvay5p7bxsSRrFgph0KAitchyZ+Na /9I35WI1p5xk/FcTegP9xDUgHCtvZcL0ECRvLKhrmikpJQw14kJPHTqdnszHxmLKOb7ZOsT9kq7l HQG/s8PMBW5eXIrVEBgf7KyF8r6yuvWIool2Xyv515MkS7os6YPMNoz69uDkDp7zPxmNZU9qmTzt dzODoQ+Y+XNxGAZ24xUfdLGQk4md9iRje0+BYWF3UyKiyEoTpE/xUkhxad9S9egXR9cIT961U98X Z0Mi+DEJ49KOneWZIIQFcOJt7q82EYVNoAQ52MLCd0c/jvmj3es7P2dppp/pbhnHUf7Hec6Ghl+6 PePOuoDK1BLS/xwjOjWp1WIzDShgPX85paliur5yqIPkB+jSHhTUKevdD0XzKNIvEN849AWUo53N qVpuZq/i+/Fv8z5+nBC0a4Pc1LSaPSCr4Wfu6L6sB9jgeZnuOiSwMZnkQFgRrxLAxOaMdaQgdzeL cZoLXPiLFIBUkwDsD0g3N6XSIqVYshFzg7Aln95qRPYqsjlT3DZtsfafPXCk9qNhTvttXKBuWmWc oTEPv4BOzVNCGv5RVbgvsKZVVZGsWoJVXxPEag+QXit8FR5dMgEseMn7Z/qwYgC/zpAYESnu3sjw msdiGcyOmQPSc0i9IV6wwJs3RJilcvPVR/9v6HaD/jxtUCq+DdQMm9TJbgUGU7hq37cqFAlMiTZv Rl3pcP09jycEJfp8s7aem63Nr5W/C0jl/i+QwwIwEeNEMMTM5+Fsm6yxlNUwd7uKPK4uw9zU06aD 7jKpL4oRWsKYEW0P4T+iNcQec1ecUE8U9yCKKNzaOdn4TYFheTzkH4RK5VNvS8/249Uz5QzPg/w5 KRo/kJYL4UubhupIwavIN1Lm6MrZXlET2WQ0zHrczk0N2OGZCpw6l+VYSawsKgH+4OW0nwPLgIl+ 1t/x6dvK+dGlm41VNcISRoslhhAuXxAGvzFExRVYGiuCTsrksmWKBCYBISY3InUtyJAMW6+IjxJU /WTZlXe9zJpkfgCUcxqAMGsvvHwZuRwSDmjwwIRzPk5utu9EsfShMrAdOm916HTN1wFFAS4KFsf4 FHkZSCCyfUNcuwT5ujyL9aOLPEhh2zLEIC195WewBi9PrKwJazdR9HVKYJMwiB1Q/DKkjcfFMvc2 iFPfJ0HqDt3i55pHgu1Utuq2HLbuX2YBNEJ9UxlXkt2R5XN2lkQCRGxuXftrkjhrPJ8jJ/gBcD9g Aqjp+cdo0ECstuTFwZEJ+RdHEG5kn47XaLnHa1w45CLFe/4JdfAAauq7tyq6O+TG/I+MH6R5n+O5 bUDp1bSa5y5qPfVXvDOySY1gF2XyDg/vwXjWI99qe9QnSAFRY5RJAUnrt5Y144QTEuA7GJjzfhS3 MQQJ6isEVDhkw8dKDRu/zNFrD3FqNrmrG/sD3jETH8j9o19jzb2jXM/jS+mLJ4revxAmKqbI03zg CYKrRQy2ZRUEgi9ZmfqBDCvBMLVEqvNsYtnfwHUeYN2S2Lv99XV42K6wmq0hTrNbQqlbMlFeS15E rq2LY2SGWujFXVo/wnz1oGvXF08NW55e5oyS3m3EGOqZGVGQnfjabZNwH4KXQoQLn1zA3cLsUdkB +9UC7O/aBEqICJNwLfUhlRhxsNNsZ3V33uRclI3z47Tf5FAYIRYnf5ihdpAmoZGD6csa0Q8nw7jn nptWMl2vl5ihMNNE4Vxy3W0ARfDlmtz2a2Uo30AWzq0PbxBuQ5lO96g3sretfqCNJJDiSTKGy3+9 zw3Pq1h3lYBAk367zZGKKCBc11nP9dIN9g/UkkxSn3o/4QVHJsV5J5jqClABY2jOyOyVzBtHi3uY t7w+0v9MnKbdWjZqF4RpiK1A71hgQC0bD8AUh/ZBfYrtYL0QKuMU+GpBKvU3M7tE92aT14AqW5/z GEX5aFUizB7974GLvAmOPYGebfNB13UQkMJepD8XO4IxuGhA5A/pfiy5JY5gkaSFxqPwTad+dLHC PKzMkY157t5eDFWLfSg3PZr4znKkH5RnHskyOnK2m8cIE6lX8Uk8zurJqFkBlua174weRes2RBW8 LQXKbipIOdXtZPwyKebENfSpdNssiL2sMUlOvQ/LToCYCLbfw/Q7Jq1irBoqGEAvjpx0FH9sCSMR gziB+hVqcbDqezSCiVcL5Yr5Q9vDVkMMsV8YqiRBBM2vRa7BC9v84MZ8to5UvRf0SZgyAc+Hvm1k N68fCJsRvaxQiK+/X89EfuO0fRgWYdSLNFLoyX/BwOVz6dskYJIqTEOINZJlrJJ3v0yDimRN+OeT MkjOl/2wrS4G1jXlIuFjf0OGTvZDe1FYG21NO0IW4SVMjVf0p9xEXQP/ZE8KvlAJl9DQWNWvQHR0 +J5bOlZhPpeRl13ebBXbVZHCT1nlP8e9WDNPwEhgptUzTcA0x0/WeBxh+C95OurSGNg3iJe71gye SBboZ6CtthG9Ph5ASauvrZb2W3vAQF3ygaeMS4/aYoZmtVuFJ7UlUbaRwrNiMvdgTyd4B2XQUPFk oQFPDf0KzvY2SIOneXUluop6qsvyeWPP84aUX+YpcF+sStQNabW7F7lOidBZ61tp4mRMLMGDXnZx 70uAO4/szPxveeFZwOFe2PxCNB4KZLB+p6fruaTaa6LSeeLNbZFya1SUiqMedXDbjGYV74TkVSCz kTeX1ttBPA4gcMTeJvSs6i5gnfXJn3lUx5W3yaNPbeWSflhEzmH3RAN7lPIFW4XgaUYjUq2c89g1 YXf16tTTo/OevCl2oe+WMrcfJHBvuPGBeTguxFbbbYCHq2pMt48OM6G582u95yLJbhOwgAMEUVJJ LvX3RXtDuvNdDsCyxa67FWvzeU8bcY480hO1FR5mivZVNqqRvzqB+raHxmXfK+20o8SlCSFsnUh3 niCV/fCgOdb2efXqeNnTr2HkxekjN83nwZKkoC/7wOsHX/g2/bhB7W66XvPVynQOB97g2FHRNfTR ouRuQO+qEOR3yalhRs9KSrfJmon3kElUE1joh2He/5X91OysVPChDTMmXIUqjqETt4lq7WbNUusm c7SsfjuaXBNHe9cFmLj7hQia7zQ4KWhte+/gHNpjJpZo0uIQf07QSKxMxa6T/Hgqd2/zqt6xvWjh IkJM47TFwrFVwQEo0ZlXTKJQRr67lgfLQKGjVitWbIFilFEPADnxTaxxf8XXAnDeTXR1myM0t06R vrVe5lFtkBHGsArh8GR/Y1JWVJluPeJ/vJpyBLKHvjrVcm1PHOxubbSQzihTMOO6PxVYk3NZVR2Q CzXAevTCr3i7AnzZVIYoLcaQxk0YQlYLxSrA5KdfeF16dmmYryCPoJVRzIwbIq6TELZzq+JC8Cg/ QqwVFuK1zJb67PgKBuj0Ee0QDATLC+sZMvJRxYCnG7GeaQ7CzhRFtFeyuDNiQxtetSlJQ0dfXmxr cIjlcn66LeAhjncezTprrrknOz0n0Rxs7WzvbdvyUPrLc84DzZ78yAPlqwTX7hfmhrWrrtiuM/EP UdZOziDUZhhuSRxYVm2xkvAZqXZN6+AU/l0RAStMnRS4qn+sch1r8mS8FTux46SuoIomgRR0eCmd zd5A579Ebts4xiPxIi4FxJ5zELTI8oqm5xteNBkDfo/Cub+aR4lthDRSRuhh3w1JzQKSkO+LvwZd fSB8H3AM24x4BFIqKHbN9MsHGfNqt+wkG7C6jxvff6NA9R582oKjSDUR+F34ygZAwwnofETWTk79 GHKzTdxo7WK1RkLmfttD0TpjsYzvyPWSpBpzOw0rdV8NXQSz/v0NK6z6Z7Fdn9ZgN8C5lB3d3Gik 1jgWKmrTCwUG2aIDBgA/nhEZcf9J9e/8Uyga4mHAEeaDMyhF43pbSkxtXtOpXwoOWuH7vX93TSgr bFYevZ8pep9Lfn7SaBoLyD6dpLcbYLqjhvFa9pfrqy0fdePdfKmZ6WJJ7mCO9iIzXotTGeG5ePPy r1OqtTNHcpPLh7CfQXvqxLLkpsWNdE7nw8thqQPf0JLl9ufDeULe30R0cLtj9gudoIUmMjO7pnBT TDJ/qXyNdFPR1PoXB5ikX2osNjRAt6TJmRdB3fvkY8b4+FVPGOAKEV11VCR9gk7OpR/FfAFGWh0b UE5zgqW6plMdpno0DW7cmZ3A5tigiPiyZMJY4AF+KW6g5ionpIQd/+mMEydyLtqwrmyS4wZFWtG2 OHH5+oIJPvNfBvEMEWFJQrIsGrPH4Q6mRuvyPZAglgarPTwfqUAp0ZW96dc3Fb7ac91WCn0GnJIW AyRoewu/2q5mnu8esp3S+POtU/IiBZPwcwFlv+At80amQBhWEQWyRF698zCXczAlCJDvmBFHELBx fdXcEXgeIilou1gR4TGLNPCKbHWASnialDquu1RHqP62k9XjPRmbuQtoqy+pQJf8q9zdU+EAJqU/ jn2K8XwhD1Cuim3THDycEcWacGVWzeswgECWqwoeiez8R6V7n1XA8WeIqBUR6nqKpqpy4+fdRYt4 5djw83ElDr7v+Mut+6HCHV7NkhC4IYB0wUYwsr9RR/6KiGT/4MUZFW3Y74QQvO9bd4edDjVB3eeh NLLdLZm8k3FvBZPHMevTOiLRuN2BqAY/b2Xc3g2NGmP90V3YO0yHMSIf3NecBVbFB1A0VBmAV/2U nr+KpsK/ybmPGatTW7rZ4hasEYNOo3VtMN4GBFu9LW8v/seszxd4Hrask9j6LWD+v2DaFVkOqrlE 5sVT6bR516L8a85oz2Wz9NHZiC+Ud26EEh3V/+FX2+pfE0+eUW1dzr3ZOmd8dcJurA0vCwArOJwv SCm1hiYhnFu6WimFpEghYRtiPrGWEJ1eShUvlGqKEnZ+0F8hOoGDZGyfExzJVl8ymjT/yJBf7Taa GBNt6bBYiIMAeAYQncIdpBJ6Hzitg86nVkqTgq9JfaP1LxvT8uWZ6wVhzjka6Jz3IKJuX2Q4r+gF L/+/6/65AbNFTyaZF0THKO+p0chIDeLkxZTrDjbPPr3hfoWV4rXOmc15jr8snfiugqmkpHeHnOe3 Yi3z7xrYmMuD68pOeX61rG8oaarpBIIcIGwARlriGSVF91HvIw0VHhT0MyssuBfx0Hux/iX000Pc Dd2wf4dYHvie4HxP55YuRufw1b9LeWtSIUS3q/lCMFRO5Apjlyr6QIt0VBQnH+2DSQCSnAhzD/az N60PTlgioUgHXNbtnMdos3p5+mCoHgjn0ek49wbOhor9jdvGvndkexWUvVkGZAkbm/FOjvTqzbC+ zPBCofaF109NeZoZd/RWs5kH4/MMxeA31yQ8SXdD1YS3EFpOo9FJ/CiJ0/HkTj8+pFG5sMWwW2sV L9cssDXQvQrtGLExn7zjgfyi5JxUDz5XrypkE0EQ8P1Oc+71AJ4ObYUhBuqgiwJtFyALFtXHYG8S E1Et6zj+JGnwAvZjq6oa4LziLOb5Ey9SspKMR15yJ3Og0aE3pIAC+VTB01u2VgPqftU2+KiSlbtk QLOwmouusGn89UVB3wmoZ4Isj68VpQN+FP7ALMnG5lfEjlC615l/Ez8QAcFfaKlwp/kdb+S2MFcN lzuNv2nssJFTRrstk5E9k7FcT0mR4K4Y6jNgwuilpUX0RWVx1+wEP8AksauQjUe0fG/LSYvItSdu 4AE+5nxG0dSRZSjRx/akflAF/jlm9tNnRCMDck8yJYGodYNaCehBW8PM0p972w+EcdPl91M/W0yB mD74c5uzFqjZE3JZqILfYxbOIynFz/PPMNqao4ELU+NuRnTjUMGJq9F+6uPLEN7/WgSZKkau08j7 RL63qMV9cjVEN46xhLQPT6mNnBI1AXmXb40MOFjlh40pYq4nFsXePMYbf0/qA1rp9rlmt2B7LcSk M3xJ8JtFjnOBhXLsM5KkUQulPdutfTpS+lpldPXCv7qodfS+t/KJ0mv0+nweMP1DvXYIZx3Cxoa4 dgr6qXSP3F3UZAeZuNQjIrqvWOzODtXV/msnkdxn3HnZerqfx8Aa8sGITDdN8VEiOkn9n4Y+pv6i eVK3xQUonpWyzA2JSXsVMbZV/yNwA8WiyELnVHePRqtyir43UCG+maXaUFcLBGmYMqxQxeE3NCsK HcHSgylf8P5WIWqpwjQVkDtv4rKhl/IOt7Yvt0UTG6LfeodBh8QgDIGfd7y75pdW5qMJhFh6/P1A J9BRR9GklcRpaD77AHP5xNbXpCjLZawszQy+b4flPqYB1u/mVGRhIKvwZMG0rAObdrmHbCMYc3Vj Z0ggYmG7tegcIzXFUcyNTCtKTgFim73CsjJIg9+ZoueBid2s6McpproXnOk2x9Vu+C04T+1G7NqB ltwu3fKBcu/F3yglG9SK2E9wXUrRf2wBFReznstW0w5EaanGzTxZr7oIAIStO2xLNjHg1M8pYMPM voRMR+gIzyhSOSf/0Zmg4Z0+hdv9vGXgtIg23ARuVMiINkxHJ81ks2V+emugaCgOFRqrPCKI8KCp pQTYl7e889kXtTnTlH7NR6omwNs82SK6fYswhS6YlkpqhUtYpIPp0FRiIWus1D1hyWradkO0EePW 6MeegXSj/gPBCf/9lTs03Zrn63OUhNcy7lXPpnWKtPJwKiVmIsa1h44v/nLvH0b5BDYHIoiYXpaL cI4fyx413s7wR8KzqhaB3wYgD1qQSynVT1smdFvf4+ZB9laSE/Uctrs+Xc7373PWbsE6mL6xH5m0 ntrm4nw2z1YM+9lphX/f/Ff8VIuJqRN0w+BvgYPKN9J2jV7IA0ojp+xye+0IA5e9vjhTeO1SXZiG yW9BiR2UbRBycy89YnsSWD7FH/ZxULVAkzyTK1OcAp4SHcheACodhcI+lOm6z3rHHBST229/bxCy UCKuK0Vxqe9duDrhbzYH3wa7N7Dy47VcXmpVhXWk1VFWhFGsNonD8GPrny3fkua5DgQ6mQ9YRgrS Ho5s9i+FKtPcCOdVs0uh3mVZjAGtOYIExnhQwXktcOGXSnj3dsD7rxdeJJZZeRS9+Jbe5mEQixX0 dZ+Njv6x8aXJ/oQ1teJ3OMMjaktMCVHEJDQh711934iKRFLDc8bmJOQaELQLMFDkRm5Cz0g/hL/P BeW+ZF/MvGOwpSUvNID1Ty/q/6CDniMwpKC9bu94p5UnQkpDYWMLJFyRhgJE4k5eMffiumZUQvhg Vhu9+WC8Pvv+7m86F3bZPCISaQ1Svu3Q/0YDEusMZcOs6UrOn0V+tF1kaAYxW4AdABlvjmGrhwFo dFRXPOXHeZzKw5SGJtsinxGRnXunzmN/tAx1gId0Y/Vp1vPKlRW9FdGkjw+Ovj9RewBL14Ftmu0g 29OzkQ6MJDyVg4KsIdjqRzvYmhOppsG75O9odqWPsgfJu08Hf+1oPX0CI87zH2ffiVXx1Rlu43yg YCXy2kolJh2DPPRWMhTuiJH1i5f7vsASkxQt1sXS8J/vcWhe05/0l9hu0FGVPmYwEzA7LyVRJmwq KQFOshKRjXd5UhVN6mZtKO8rBbJJKcD7XgMEZ5laH5/l78puLxZC1xV8CVtDDo0Bnj3ioEcdqXU5 HW685D2d+L0XDI46O+REmniXt9mN/hazmunTgFlZB4mI+uDHHgjumfA+y9s/U4k4TEQ8QphC8WE0 yDKgrAVKeH6GqIzxWd1r1VFzsWRzZwN56lx5FagTrFnH2uwNzT+Qml8P5sTjmEvw6oFB9P4Fl0Y0 KCWVg7v88Evl1LkR2/LCM04JRK0KWwROIivaaqr9w51FMhL6bkGBPJAlNE+ijjhyA00Vi2+3hAUg 2Q1ugAqg3KLBdMQU/SfiKWpFZkh/cUg3swaH3Lq99Dtzp+hJCKyFfNTmq5tYQQb0+f/AAOSEtm3v 44lDCPAdk2UNuE8nFvzhLjJTwCkrDUjrXy+RbFrm001zIg0rTQiFG9J3T2CvALxID2rt2Lirdt2K 3oDwG23LdURTU8pGFgJEnjkd5vD7kiiGXU0wIAhP3r2avjnuBUk4KJje68B1Q+U5r8TulY9/juo4 AaijYbucwiNxTNeow60k7BqSwoB+5Jwg21s89fe2TxHIWd8UtVXrKDjwVrYWkwtM27JwGL7qXMgQ mD+Kr2hCt8dBWISwYUUHfFOIbMsTGLwliQ1nAZWZodhaXLE1Xx1X83E2TXrbo+Fc8J2jJyGVES6X Une4WtAaCJH/kIUm5BgG5KYbZtfppCW8+3PrRUDRRMGqksbKoHmnIwsm3w5Oh1Y6l3RRJxLtyS47 kX4IXPTisykj9xKGpnUYsyPwKb04LA6ScX7XworbVJuTOWuniSmd90umfpUAaH3bmxH2Vaba/y0I h+yL8MuSTnm5ad0OxVk4qVCT5o050Tlxjsc6PsokkysDSklHFDUfeOoZT2kICQnxf0w0j7J0wvkR BmhyXrVGsy5jB0HUg62akea0obDT7tVrG8Nj7cqjZH4yEHDyuYTXgzCK/51JOmjTBI2OPZi2NmAF ZfPrv1L5pl4lFZ09Hiv462ecMm3Nly2Of864arai9cROpXSkw6s4ZiUUpVaW28CXuMH65JAmDmvR rYn6jOls/SIPO7tCEOttUE9H8AMc2zVBswoHsM2vlsVM6tOFADAl3DVokBQJa61gRrcleJt63+Ql zv6soMRZNyd6LPDoGOnUHyaWuz90WdESRa5YrFbIuQIv+eQcwvYPR/jkCNmxULdblNu5RkxdRZaH 7mSw0z8Mc5+pPPtAT+WHrzc+Ob+YL1ZvrPEatkGv2gd4omSBKLrrt7UbBE5IiIkREk7GaR7Vf97x jnwguuxzZhQmncOm3KFK8iy++EpB2JklSz5z4s5IJfaH2ogq1uEGecPiL2yO9bpPcD9DtMPpHGnf 2u6QlAasmwX8VRdszTbGsxfBABTI2PDjSVp77QLKtz6S1CRbPapJhb+dn3McxJ6cFUxju7Djc2Vs TWdWYet+/MWvuhA19vdGQaG7eytryHfeq1YT5eAZSS+EeEhLu2bPh9U12V5cCGWXvsDMAYBd9AnZ o/e+O/MiV54dNJimAuUHaRWTBNQ8jG7e1nxnNFd5EFm9iPC0bZ3xT7hliVUnu6HVUxotqpBOWWKB 5C6BuHh0eCbh1JKXGDeVDH3mzN3VQgzv83CYH0WBNbr4He2xgqHTuzyME24HCnwZJrRDVicj9/Oi 1g4r65Ko2dXsVU/fu8lMFIAgScCwLm9no0tDD6xADfHJpwRvwyYWxCfWmQJ+kdDQvG4ZuORkslF5 fxUQ10yaL1S9nsJsc6NdxLi2f6gi5naPU/CHM5Y8nfpmcdwN7EA3VoNZZM883olaqGg/PQTahN1U Bc1h8GrH/fY9u9YGdWyrFRvZWPxzqzoi+NpoPlVpdJtJe58PU/P5E/si9MkBWk1xTRi35WmXxsdm U24w4p+bQEh3vJ7BLCo43sMh6Z619TNMCCDZBrwNSCkL5O/zs+e+DZ/HcdMF8wBDZmAobq4kwavs jx70NVWoRFECJ1jIOwvyG+ICMCO3xqtJ8ZoJPxEujqTHNCcU8GiHs75kJX9ljGfJqLhvByo8PpBl nkh29Hbo76s5WWibFNfswKYN5RLsdv7JCdum+u7yT1SPxxNmgRtpuwWTRWM4AUKI6Zedq0Y+g+pp 2rIyVbiqxyAbyiy7cDhU1d7saD2i5tjATiz8F5NA6u/rfbd4Rm5X+Gv7ULOQyWGY3Yc1Da3lCYM3 TG+vTdKJR68usBv2eiNnnTdTJrAOjGRl74QF2GvmWOGS1vH43KiIqx+osf9JIOyz2Lu/Sy7ruYYY r6xlT8iEHW+GA5yQrTgIGXM/C67X9KSHCkQtTvTcu0WVlmGgNvHmIzgpWI060mgqwaOcL6lpDPOO nratAZsuROwiDtuGkYwi3TxiXWRVw+clGoHCU5P/66fx+FcZW2T1w6WP5k8O2NVGamJXujLtf9Eu U9Qui+6kFcN8Jwhox7LZln81R3D85dod+ZDY8B4Q1kf1ckUb+XE3gseIO+7ZJOAe0jxuXnoQU0FZ OjHvyyBILHk9FQSRG2mhEEoEpcGCr+4ju60FDUUqMf1KMplJh6k5E8M7STQhZkyWqN70yaW9y238 Gx3Yqjatztpmla5htbudP992HgcjLLbjNyZVKf7lx6i6gIlNRtR+Bz/4odE9wOmIIMVnB9uh1nWx 8+0fMK2CavnvwOdx4gK3/4n2XnLKc4Au4ymY1aMuWB4x6Q+lciPyKddj6kbfWVb79I07pckc+qbH cE82OI0sV2CPxMIGJKkjXPWz3enPhgpXokm2Uvp7UbKFYc1a+9a0fTRXLt7I9BFbpiukncnQMP0q 762GfN5I4h/kpobDM91YxDsPBqZxLfz0dh5XxdEiE+OIZQsjg0/tQv6+GrFf/ebSFkN08YXYJF8G exxh1eUZpFoXcEAyXyVWc46igXijW1rP7ne0X0yDSZ6lrmAH+9T2CDK7p9q5j+nGFeJc4wyttpOx vIi2DGcPyJ1FL1Ufc2OfiBGJgy2+ZfN1ErqN5no6IQ97sqNHSDi75XLrxGmHcoolXHWDtu7VrLbL h/vxSw0xmXuo8IFbvpSKzDgdzzxuMVw/CGQ0Ne2ouO7j5904HcVQ4wOqle8tBXQwwyfrdPqK9oOM lp6xD4OzoXwBYjf333q0gkToFr3O3tj5eKjaJ+NptdbNW0eu2o20BIZ8jMUZaPZq7gvPYPWNvU8b N78y1qgPCulxUf8CZuPEJmUecv2/qmHqg4xJJlc0sm0p8SNy3I6kAhGx779mfWk/khflP+u0++ST xUqUE0afywa8iDPUgRfTlrNcF9TlZAVhoYcXoXuSpy06DWwU10RorX7AQiL//BH3eO9+k+8sGBhD IzTFLVXQcK6P+5o9t3jcy3mrojOavThOxwkz8PpzdVhwffdz/ejRplhYTb3SMqm5vcoquUqEVFV6 LPH0Hs3gm7TC8QiHZKRszvdrgPju94HKFTQfuoYIiIhhkehwonImRA1bYMeR+pJvESm1ulbY7Dh9 3KXWE/0G+tF8lDB32JL4YhDkWnSrk5yb61YKYHOgyYvqZQ3PqsNgJeBn1MVRGB1Q2RlRdS4uYDu7 DX8Kc9VK+YlksjOkUsGWwUW70/DpFo2mTeN2bzJAAIdg1YLT72+qPs7p8R7j+MrM2fR0j87suI46 D6UkAlDt3JEKikU6MDN3dprJNg+FUmDLCZG6Blrvk/PdW3VB/PUSu2a1etXVjuvn4AQAGt0soAbO As04kbUNUaZHEz3OjqQGP4ejNJBwLFjk1YJ8InOmTnKnEXDpvl86C4kk5i1bOtXHcshdlBcKaH7M uf7F22x3duPP43xm/i8n5MzRX4eC5A2X66KkRHS+t78JNyY47hdxAC9b9Tqp8pVv9hpL1SeUf91z ndsF6HKf5XsQWL2AYJPBIRuBWf76QCqi4/n/2RvOoB2C4sO/ZceBFSzIYqQUZs8AFfFfnVRH/lhd 7QP/y5YerdbIOBQj56aWeXyz2Owz72miIraXoptBkymxlp7OwnQpWvGvCFHG5+bOcMuWFRLFZewP lzep8lh4R9NUoqSUGHSbdqLRLSAg/tswvBqTZJUmSZ91kvAjuDZa++PVskCafIslPcLctoN+5hMh EwWSYlwCdzEpMxCKaxl6Bht8oqpASEMYogBYeFBOANOIf6zD/5wE3QERDOTyd64V66baVFnU4HAU xCw3OvvmDb016sKdcWutzVKEIocleufDUh7QP4d+XW9yTCLZNElQLr5qb5Vlq982wZtE1tF68zj/ wG/ZdxPubXHhjygerJF3zQtwRfX8lYiG1nRbtOACt1wTi0dLc1m++dupBvYZf027vcvaYmacyKIR DHi4tidMZFMynz6JAOPSf4y5UH4cCDLO3N8Uc9np9x7YfO9A4IGW6B+nE71M0QEapi0sdIUFGbQa VX59Odb9JiHp3E8l/8hqnvPha/TrzRYlqRaPzRPjJrWUXm1T+pV8fBLht6q4RHSUF3ZO+pxkOo6v vYNCf/b9kDN/qMoZzvn9jWFHov7mxJBVJ9AiEGd/ngaoeIC62xGUVY0zs6lZMCet8CeOSEWhrRzE n/KDcdCS+vQfq6/CmObWKONg0sLdLgedLrKkuQxjFiL/br21HxhL+JS/wzJzCZf+uJ3mSXIEbPFm tSD7ybls1L/6tgi1Ly0OizY1wmx1w0ctNnkPLJICc/0pbAo5eowS5BX4CVhtFGBh/OxvUmywDP/y Q9OPQSi4J6+dA2eqttSwDDXlJSpcmH8Mzv3H6In60avWYqPgsrGFGP+G+CxUEn4Izo6O60wOL17P Ax6OJXmeOWnqeKhyXHN2mKJXeAgs9BpHrqyv43tEYKCll34h6QgGAImjo1wt9YA2zgRk7nFT7QnU 876e6yZG2yp/LvtoDwLODu1IzbB7PD4hNl25JhMN5HTZ9eF3M7SDfmALha/WTzMQNOdVifVRxq7N lsfzpgL4O8/tD+nfL/XJJeG8ik1xxcCPVbzsxPJUnDwoq8zL7obB5PXrnE3+ks9hjIGRjzyKOSOb Rlq+N/o+4STN6AU2ovaW8HCvgNPOXSTMS7M5SGeNlcdAtUxf/x2mM6fDHc7qpK74ewnuObyB4Y3s MuLDe44OOUROobcFPQPB67j30SSgpk8yii1ED2N22EtEQ79CybSDSTGhHVcUDInjwu+1EZIpFhtt mWYfB50bqdVIW15ZrOrL6Inlb8bJah7DFeGVghYoCzHgx/pV4evtU6QQquU7PvkrwqhiUyCUsdSu qndPgIzCFje9zvFPZER3Itthwn2CXmR9kj68LwaJK+T2d1b58l8Ap2ONw8ag377O6nsREmccmA1p wio7ayyb7SRHIH7TR9rpPkblj/oJExaIcFSpW+RrSHkpt7tk8etLBXYnqFM47sEkQQ7/Q4NUP9Vb XShvgid63SANyq5kXWTZxKHpjKsDlkRzxcig/WHZJ1DgWpXr0fsmycTk6lc1nES3F/AFXVcyJRHJ cxeHrhdSqix6gH3PpJXYyR79125iKnr2XdM6oJECtXOMHsipqmxHMxnn0B3An57zahPdnfkc5Wng R5ZHH0mEuJA0H1PsIy4JQlTuyneyQDEV6XGhbfoVFS/XmCdykxzPz9/BQ4xJ5CvFPyDhhTdDhnTK QliuSpq60IZTcjTMd7gwQzVn09HCGOPWstwrX6WA0/sgE9RzSx/m4mzmK6p+MBwPeDeyPtF+9S6c Fna+IN7PMRNMTdV2FxtFlzr8elDUxt38gcENc9S539u2aZXK9AHpEh3sSbviNqDuG9Ci+Jic5okt mgfC2Rb0i4S9/3kKvPP08kxtKoepzYU03ZVwbdaMSAJg0Wv4fBGgn9rtAICJ7Mnq1NQn/gUGLWfj okZQ6afLmhQQNzJORiVX/lAkTfSErckitTFtDjndy1s0Q352JcbHvH8FJZaV5VpknObVWTZ0NOBY mRXUyxexEnSUkx0X1Xiog8nP1yd7t3Qfn0FnIUkprW0QW/e0R3A025gPQjYghK3pUd5ANro10KuB 6j+q2AEDiwyuO9DSASYjI9r9+gGZKodOV4KdufNqPGX17l3wABOPYT0IBrDK8sUHUjmf3Lcxrib6 z6ymrvAic9wdpdv83AyfWBtRiM20uDxAdNwpdLC6ifhvQ04BY143YxzpKmb8Yme3zfzaKHo2ZCFO 0VL8nn4L8tIPd+U8arJ7nh5BEY3BNZWW6DPH/MPFsmW7m/1J4zT/Mz+SP0tFd3S8y7V5avFaRsTX XlpPeyYS82T3+KIIml+bqI9a606WMsRl29l4xZDbmssW/c7nh8NUksyB39IjjorYInK2VRqWLsQl MVvBBL84ibRXC2oWil8QTkYyQcJhbUcE+kurJEsYQWBkRYlWWlBNLcclNet6rtTo5NGEfge4uAoO nXBNOC+1DtgrRrtR4oWNtErSc4qfYHbbCQ43mSbeGH9nfzFGOyYRD6fUPW9xz4UjblehIu+5gWrM 8P9Cy35T7jjjSUdik4WWj3GcChjqrFo2q9Rxa4kZFYxaK2MpZN1cUPB/wMk09TvU3wAzoLyScDN3 MTp461xYbJZIuVQ1XerIsIK0RCGYqdf6sfQeiUax3tHKs8CKSqOxSOuA2D+6Ze2CTzYLV6UyjEY7 /TfLn/SV+uFoRg6kEI+R4QQRDMWPgNqhUPsvOi31VYfTbhk8sDxpJX07mZNCTXGp8miaPQznxPGB qSRjgt/RhxBWBPaqbKrnnizMRGAKC4Sa7Xo8PPbFIKqXDdqWJxMf+8LS1JnH+Ur46j5CZpvGsYyf YeRyGJKzu8uBq3x9c/nM/aS/sSX03gwc9PWllmF2EkgppVwrxZv03t/ogrR04/QnTl/KeSKIEpZs KjH4qPw3cEHWJp2QT2UYPSqGOKeZBrfoYq9+aGVuatqMIdyouA7NkOU66FfPm2DwwjJF2k56fsbI nx99MG0vsXh3Kds8KtVoHEgXL4KQEi5eGPNAtbnPAoQRUpM9o0HAPUooJd42v+4D9fkqKeOX0qk4 rr7BsMhmmaso+GliGOyjNc8KsP/Tcg3CsjtGsMRVnGRgTD31MF68mBe+GgnWqpU+805U1QE8dFkz qBRoLNNKfyN+wkaDRqHIaYHzBP5pgrSo0bl5Zhm3V62oMwWf0V1UgyQupFeYpx/c9p/mU0LFMsUv wFOiuC7G2N9U2p5HTYTq7znYkNs6vEYyAt21ptknO7kCyXSt+83y4YGVih+3W9s4nzI0yLuUa3tp m6/q4GUl7GjmpdJmSifViIXAPgdwiHvyDVIzgzwEgk7Hbhct53cYdTthkkSsQPdZv7z28omnTBGT 5ypSSLHTiOM/Z79W9stcuIN3QZ4GsvvxTflqzqIxCndawwtI2EdqIwfdby4tG+Kiz+TZ7T91laos bwnRlkXKo60vV1BYka+Gc3qe8FX7FtUmL0CHwkgFvgNUOPybIiKYB1Inva0Uh/W6h5/39kKu8DTM jpwAmMyS53e0/3lJALn6P4rBbGhFQij4cr/5fy9qYTyENe2Chj2BOisDvOBfUNHJ65XotnHHbMh0 yjl85p96OywZ1JazU7Jiy18o3HI6jza2eW0U9n7rivhroapiTbROAULo2QNFAhSxx6N8l19/0KfU SAjWYJj9I1WXBFRITt5+RqxOYcK7ZkK2GKFlG/P/H6wRDqfqofadydzzpZyuulPIPWEy0Ifk2CYr Bd9EHIzDLtO+F+iptew9bTgog5bogpmScwzcBsD0klhGLCUQCjxVdgC9+cLucMTfS4BcV97PNykh e+2LSgtWe9iIoPHbc2rgsqTGNtJQeggfd1LIvjY9aYwuSsjm3OWlUnhiSMhkM11Bm01eFG3pk4cI M9a2S3yajjk/Y4/BimjGyqQWBjew+NpMHLbtJjxvV/pDPtuSPkaIcHvcoFe45mXAiOivF0xDwXwD eeka9SvcwZmFNkmgHD0CsTLB59ojiAum3RZJLEYpuT/bJtuTYTxgazu5J1oTpszR7fffLO+YKS01 InHYAv8Tx8SruycS2UGQnWAD0N1Ie2JoRMFCW6SqE4tTJ6Qye8eywFpyeOhrdtwnDyZoAo2hFP3R nc4H/sFuOZe6zYhIytej/xq5mu42IdaPrlQlFDPFsJI2NXl0eYKz5M+Gqolu2ZNfivQ156vJBpI9 kt2t6oVgamHznLqfrBy3LlAKiGtu3LPajczEkNozjdrb0PIz1CtReS520E8q58FOZLq0uINFVGC6 PDjgEIQ38cxg2DjYXQpnEQiG8B4LvPJx4Qa0WQUDUhMxAH26FHIg+5xyDZ9yI/QO8SHFSsImBExC jMZfqnC4ukI8Fb+plcW+JtfwnIFlm+Evq6aGcePR3kNfVHBQ4yFXnYUlMKjrqlcIAhYwub8S2SoZ nY2aFxh4+GPvjvqron37xrBJE9VD+qZ9XceIKljLuMSbmqaCQ7tEwo53FcxuM/y+wY0+Dd5Uh428 6oxjoQD5akeOmQ2aTK25auSpaE8NUvFMBb7M+E5SzC9AWH+HegPAi2QcfiA/VWXrpIo2uHJn5qU7 P09J7pqedF1JYEnuyKLeGL6PCnD6MKa0V4QVe9yqrCLdjKHRZsTenCvEm0+Vy8u6KMK+XVYSCi+i ltDhnebOeEAl3vLLCE7eSPgQniSjUzKv0kSKkOPokyjeyGzdCJCSLJ7vAgpENqLuqJvk+gt/8i7C +n+BG1CCPc8IouFTCI3YR9rN/JtwaTs/UgmF8VCGZ/wbws/on+JH93lJx+/qcaQgRRPR0lKtQUHN N8fQ6iaYBeFtA3Wtj9AGGJn3uYYKtKWiicFu5/rQ2UA3Ohw2hb+CiE1ZQLp//S7LVJXv4a0gsjuM wFH5kGdR2bGSqKVULa+xjUtrKDjKhTcaGo6zOke5r8aYNOrKiScbKaDmptpkOU6L8NRTsRy9aBMj OKlD/37amQjC+yNgOhjB4LG6Dp42Q9k/4+trZlFKEYY8POfN4YBYtlzftDIIQJhGwxFJS6U9UmFu nf2ZJh+QE7uYlz5fQaMM0EKK+25qNzpUG0r96n1N7hZMsWNfebWTIXK5lgRvA7qet/1hUKNW7pSj PTsjgfhNNAOgBW0MS6j4aZSvMYstNEFKP23H1RN0Vbt8p8iAVody6ZaAww/eWUWISmiADiU7M3NH jg3jeY63lOS1kCe+jnQl2yaLdgE2y6V9JiE5TvsB+CYnQtHZ0rYZABnDnle2KeIyYde9kmbvTS+q 9DyIeKKMCqEhfaioh29fm6tnM7XEDjsOPg6VfPQlir3ncrjUuaFzHyflBNhZbKfFOyS0NunuBMPU CmFLil+41oSLAByrS1Ruc3EX4y+Z8vXi+IYSZ3WWlp61+XBz2HGRRKrExhs9ocmtlC6eN0BxUrt2 UKPEfUNk41eYMAqnPzNe0cF7F+uQynHNwnmnSU4tfgOKMiykxMvW3fN/X/9fywPzS+JNDruRj8cy Fh0jMkrxDHF697CzTn1JrUvcnWaPRbOfzuLcNwEpUJ8yW3qeSGUoPPe1RkiSrYE/yuxmvvEtcg2F VhPW+RKX1+MhBZwqDZIJT4IYkPl5WkuLGYzatbn9WciWup5BmTMbJIZ+YDaymwDtnaEkQ0zPFHK3 HuDFemBOhMkztgCTVu6Iiaul/hBnB+D+oHGlOKU58LUcj03HdzEQ/tlD8cpHpc+yscIYfgbZYpUC gtQH2y84/1bM2fTzIwur5wlimZTNN64MIoo/8nglcQjC3bl7fmrEFiD1+x7MFUz3XHib4chK75zE PNDVEhF/VZkJhMcELO2EmU+Pw5cef5HowR4HoZM8wR+RvW9/Qacq4Ixc9PjIrSqQt2v9t4KyMJJ9 KCCL/9aQYeWqouLblzEY38NVrVg2I+8a8FSSFvTrvEXTpzKU+ZPN+1qjo0gOjMALtxu27MJU0ayG NbcuLXIJbWyWLVzg0trba5xcmrD5MLkKElbR+GPszR/PZYBJxMB0aO+V4loVJIMjqRtWnLq6GH7V iIJCQ5Mbm9DXsJUkxuwgDYHfHIYLmpHtG5dUe+NT7gv0pt/urWV8B/N+8EYjnGqPj+t4CPigqhEJ l+qADgrUGIj8jerWKPNwLsj7U3h1r13W/oyOYJJkxzvsA8eGVFubkMwurwf8Wi1PNoQtuL0RHNGF Jg1vmBhMlQb0nLXAqBZaFJRtEjoSmxVoUBYyDmQheKGqPRGg27aS+Qjw1I9htWuD0bh6h8PGM8rB GKB13iXVdxs1/iuNmHoHtxgJqQlMK8JQ5gEBnuU7hQ4xhQVCZYYRM/QebcSN+9tVj0PWmXE9tWts VILyKTN7HS5YYiJ9mmEXR9bwSi5pwedKaQ73B2TPTfm5xi3NwP5AgWKG6S28ZPx8RAlfupcw5J9P rW1OFVYyHHeArx2CJSBhG+vMumXH9f6YtMCsNaucAqPBs6Ah+AqEsGEhcZrU0vLAETl19hOdPjUs Wx3HqZtH9j33gpA96nXgqF3Eo2SRJ8dMptgHdbLwCBymB9wBxqjJ6109p9ip2XwjTty6nt4dKVd7 XGhCUPUGRlyu1bv2p/pGqX7IcaXMT68EdeDisfMgBHfWGTgEK0w672vVZvGfhSPDb4M59hEHL+2p JiTzVFTJ2SbQqQHO9uUx9WPpl712Hf9mVzBp5hnt0zrTowsMXeGrXf/wjNuLEr9CFv3pHCXYtjrM uF+jWtBZkfULIb2yYHPMti0HL9/PeQ2NURPwyyCHTZ9qSRGvU3RzXFQdMbFpbLNFryVcuc+LY8WP iG5AKW5ut5MT0hxvMeGmOG/QeXM4etpnNgLBhe3wxDe4tbKmYalEUhJMh6pNcbVAiGGCFJY3Xng6 wk0e2tYyuKdmehWzpsX+pF1PDEtBlnu6BfQMY4CE49VIgYjiqyH/4/nqpqrnjY4QcDhv9AcJP/z7 +3YISBUkWqVjpE9wOVJXMULuza0bpmbhKNwpJoM81LAI4dlthP/vGxtlWQmIhnht4veyi/1LMmBK IfjtTOiURhFfyE8OyDMkGTWpatoBkTbFq54ETNsUn3oWoDWGwNMakESWuHvTcJYX7Yz7vUy9yfVk D6ytti3MuNeqhnwLsMz1tuqqZpAo6v2IQCwxuwtGcEQ+cy8r2ce6axMMx7/Q0W1t6bfuizFricm6 yEfT42caamyN6bwInSt5YkDnPq1JeOtU1+YQI2GhVFyCJ3ub3VzGhpJQileRqwvthU/CE1/JEeVW 60ALII+INQXGoO2TYVpvbw38wsJILQCQB7VLadgY+W9IKyakQNXn8ot+DDLGMaAeft9hlzFJVjmZ tFI2BeJ8+UXEI6pjWb7gg5lFTBYQsU/DVBXmH3FQVAP33/VKi6JTNHzBKF2MuZVLFO6dO6TKpabT 9G2OZTHqX/5zup6vxYKSLyGO0Uvl+LTlYfl1KL7E1hxxmOzp7t7ExbSa3ksrIZAEufJOjqmhxbNc Nw5LGV+1vXxZhc6s72Bmfkpy7D8i6rJfx7xngn1suA7dEYld4J8sJ0qaMi1MsNNUVM4QjBSi8r4C Z3ZQgAdny9FHlq9H+5ABoF2fgd8sj7hJ78xrIsnCTN3pLEEwzNbRcWqBH92RTyGEFBmbs3/dg2ks 5FkBDmmDxV3npiftglj0F1Y4dbruvJtuOPCjtLzBcyWTaZA3+vVCatqllBxUBa9JBXepgOiGJPYg D3qolyoIWndQBCfTLZeMJrwT3C6WKaIMByLhYjhb97YNODpXDNUSVJ1aoXpluU0fja6Ba2CXGn4S NDyrULxH59JE5mA/aIZEkiLuhhVP0e29m4SswtR/LZwuW7WgVT6URAuiqdr3egGOXf0YxhhdLuLu 55sxM3dm69jAgw5/nPetgrmkka6Nrj/l/4MXafhjSyvHoZwHpAI1w6M05MYBHuXsAwF8FUYtuSSY RSK/hBQPayKD5az3Jk3YGbkxDGGtuHY//YDC5y8xBHtJo7skIuZ+IdT2oid6KdYmc9Es0v2BLvEO e3ibJ1ERKjFqF5oT/gX3RkblX0nC/uyaDoL+WKH5ff5YKCl8Y2BpkDyZS4poxUCi31W889hrN+c/ wkceFSHEMcdtFvtG3lRiyTj7eTsuesnScNG/qkR5mT1ulvxQCejnHk1e67KYWLZYreIpIKBq1+Gd N7mRSQh3xzQ1HOVvzpKCeNm22EwvBRJXEWS57LFHkA1S820jvyy/faEWtLz6qP2Pv2P9Le3+c+Vx 8fhtvuW7FjzkAQvIPphiESgdFyHuBDoEoWa+GGTJGWbpyWJPmqOQs9df4nJUU6xeyKC3SHX65MHF QboHat5t8xCUnQzXIpGH/6c34IhOhnZzKGz/ZsJWn9Z30LlZepb1hiCdYT4RqR+AFCD4dcSLSU8Y zJaZt8iLYm/bzS78jbOHDoIgxJ02HnYGZ9Azs92iL+0Qb5pkCkI9CIwZgsUXi9Y8t2aHtYYyzc7q IJhQwyG6mvQByn1gzyzfEZWlimSd9IHSrBHOzdhxTadL5z9QXrIMA867oaf9GsqcllA1qumg86ne iDX2JDS4orznBKaH5qD96cYnxDDr69WBADE+2A0ghTfujfgJYKpUIhOlEV22Ai1BWrguY8UptaBP 4klIcWZlucGmwcaSkHs4rnFFwhj/ADTna69fEYRHwqO+7vvX/sfS9M/M5atHNK6ciYRe863M4YWj GVatukese5sa1sRtHcTWMn0a4TCvo6M3558FZCObk2Li4erzqbvBT70KgK+ynu1N+8vMg6v7ABVJ hJUB5kf0UPSX/KgZTTz6j/P3Hx4IJA6SUEg3sng+6ZeqDJe93w2eMQ04ObLGXGmZq8xYS4+q7Vjq Y3ZBNA8G78RAYo4Mntj8MwKB+3HmVOZtH24Og1IiOIgsT8LLfftdhesGSCl0vCIqKzp/lcbFTz+H cXjlD/1HVbIWkSA0c67Hki3swy+fX62mfv+/lNB43Vg4Ul6/fvZhALaHWbO7hxxnSDs0nFAmyKwN 0o+xSQDipALRmqUdbRbr+VmyoRM6WxfPUtVYqdm3iy7LHU54snveS1QEVtkDotNDIEjWd8L9XuoM 90THc3M5/DE7NUnDV58mfSSRaq0Qse5ZSxt2GKMTb3S40RxDq8/liErwIVTpHGkEHKVx/I7kMu27 iqH8RJKNoVX3OhQjhoS2blBvVgcA1MSjmcV6JBRNGZEYEcTqmPZidX1zbfkw6M8JL2anhMZKy4M4 Lo5QXMAg1anQwIbpyfkDzujaQOhlnVnUU5FG3qxYaMELJ01MH+aQbIxrDd7K5VTxSHZgLj5kuu4Z qt2MESuGj79P5O+PlE2mjGRj2DzvDKafHc8uAxSrxf/nfRzUzTqJqD1pPEoUaKcuvojsAU6DkPD1 3vgQofP72ZehJdNX3/FbueaGXiq504VdPh+J+mTqxDql7XlZ6dSVXRL4VhesZQxG2mZM8o3WRTNQ k449Yt1nHbEBbgoEP52iEguiQ0H0arpq+7dfBahk2FDoVxhrOFJkQplQWnzn4xVXFf2F6/38KxGt HRebvDtUo5iTrlMEk+k0NgJRopcvW3H/BeY+xkRlvi6W3EPRzEdcx2j3o4V/Di4sgXUis2UiTr2a 5XVJzk9FUe3Daq2wbfOZGvW3SR9VUMlkK/y6G/ptt3gwdRMpwbQ1JFj46xw1C1F2zBEy097z3ebf brYgZ+0WKFWowzDB6DBAD3kGXBFs5tyy/PDEOzkrBq/3DnHYBktnfv3ZL13hoUJsA9mhX9qzuM46 EBWGnyH6SbdYeMnoyeNvbiXW0v2vVo7EEWJHtR2cV01c3B2JdAveCnAF1LOmWaWOAX2rv4h7PqwY AL6+yEMyvrTd+qPLIpJHoKxlPj58t5yPjT+EHnoaqfIboa557Bt+Puw416AdgHDqijUbKD1GPuQn jDuPPl4IU8q/RRt3GGN1rK6k6mgIrF4Wv9pEzA/b65gx4hWYQ9wqEu9v8S6hKLRRNuGmZJxr1/SI d6a3s7lw6tfnFCrdK36yFJ8SzkobPPmEr+fYDmqgv2KfM9p/LYNpkINeE6bAGZ1qHeJ1KIGYZz/j QdETYWCHU/ZxZ+sx7pZKBs4OO4EREAFY/oXIiGepmp2/bMv/emQ4k8tkwAyOoZwoPEB7qn7jfy/N h9PL27D7BmdIRjOu4GvhEjHkJ8DZ0DgI+usbzcruwVVzMf6xLPk3CELxUgf8FOOjZDgAjgdwwW5q ccEcl095UIL6bFAMQhRSzX6GwbEGRDwmsKUlO/toehuQM0+qUs9q5xw3i4Q2WnRBoDkJbTnuhfdC W7tj+HCU3M0G/gsCfhwsFI0lVaHr5tqK+A63ExXngXpswVKqqhD2HedQV0KVhN2nrqeAXcCTror4 DAQkU9kGMCpxaIs3308k/yqK0DgvTT70KVSGxSem5fhsL+mwugU3FPJTzNJCHc7+nr5ZgsSIvQPx PEqLT+xJD1rBC7ORCby55cgDO0E7c9lq13u+snVow5Wc8dOORt0TyAe1LH9XgN23I6cb45eU5RcH xmK/YLoLpEWoStUUfudhIovixgnn/iQ0Vu8I/2VMcleXItPkplr7mzOxhFyf5EE9Tg3LIqPffjb3 dLpW99/NikXCdhg5/70mOMOObfU9RR6EC+wmFYxGoV3sWzIcrXe/pzlGGbYuYVZNSjlTu+3mAiQP ytNAC+Fnby78G7XEPcRz1k5LC6YhTp8I6rK/cqpUWrrDG9PBlFigvf23kJReILQyVxx8/6RBgk9M Wwa2N1lTmyrsyD7MoM5ykl9zjqwKkm0gDKkG33SDopTj5QYhMi6mAg0PCJa/DG+uCT+ZNKiDbZlR Hb9v1m1wkpmhyZx0zD2ChNK64cQ7hZQX4bWJ2H8meq6TzYdKydWATYcCR46YGwiYMbfCO5NYIzlv eLVutvsrqVJafh8zK80NGyuf3mJ4zAuxEO/kll5nZGs3/u45Ilu3s9rnFsGLj/JNAC9kbWdGFq6/ P+fIYXDY0Y5jYlLPkb1JsNaiCUM5G1u1KHE34LCtdJXCNQ09UiiQKVO/Xo02BTkuTN1QN5PRCSj3 BuHkxyXfjO5A7s52WqhVPxN/IGYVgJIS//RbxSW2IifJIHDW539r7cogsFbYWAl+YToXGnXl4E+9 9BmzX4Tt7VJv+mFPootKLJ+gZhWmDgWDI/CwiKSMi9ZmrJQB2mDfggVLFj2kV1dTV54sAKYcWgX6 E0rx/X6Nyo/F2m/BkZy2quC40JYDiKK6uXJ6QF9D4AXAuylqd8ylmfD+BlH9MAWQHjul7XMLfnw0 zkiH9oFPU0QJJBs8Sskvr00crZZYxNaAVYm46XlRdFVkxwr9pnuVsdhvwazU40oIGwOmanxxAUZy 1cqraZx5pDOkm9I/rXMtLtP0ykPWylCfZBUmEq10z8jJ36DZolwkE+l7Sf1VGxi3eXEoa4/KSt2c lrxrByxIgXRYv4nnHCg3vAGgkl9zScsWCM3tUSWi8DSVTUbq2exL4roYMkL0gVrskvo6elmyCE6/ 1T62tlCp3DxzL9fbrpWf+s6KEBzn1NfuRl8mFKtvuvjECxFXuSLBB3luCJG3kcNtRB9YKvIZrzzT d/SZQDFVpofRHwJawYoNQHFYFZ/pWCtqCzqYkVDCWIlHlji7DAnYRcl0SV3FiEmdP+qN5WH/E7nF HGIVGt03xAkc7KuvYK50Y1p5qHxK9FrvswDIMp4cDseHLc1aj3dYNHpU2yH+B2xDJdl+Q/rm09La xBRTBUyNhkd+4SNYLvUJkHfRmkbtb89857SNswL8SCN3NO32AW9Db/PW1hJZzmmGKQl+SZo1rBa7 q0uAQ6j+NCO+x6uUtgrPh8+IgaIu/ze7QQdmKEVl+rI2puj5Txu6xuoqp4v2SwH8IW9sIrNf67cj 7swoh2hv1H9exWOh+u11zxHpOq+6rxAFpyOnTnFHkHPfdFrYkbZSuCKyKLBS9ENFBg7dyNE95UNf hbO7xFXALraHT3lPQVrydpAj+vGUf5OiNNYx+zKYtPYfnTVYSON3mV8bDWtXesnt89EZDSqxtYTe BSNvFLoUrdy0bJrRV3EuYnliNA6AICFkBc0i+nY53E/PiQgtOC1RK9okK/Xg8ZJaWM4P/X2Gg4HB 8X896q1MLSvcqCUBcIRjuW8gI4Bjm0F6ui19/qbkDRtnboVfa3DMXMqRTVL7eh1b3xRq6ePtOtH/ GfUVQ8OiMcv7YCMtLE21IEIUWVmf/irRUB6bdFGH/nTjiwL6vZqP8Jm3XmADIeEN9yPlpbxVr79i Nvj7E5RSzd30knrIOEYjT0BnsaetAEaLG7cnMZ6ghm8w9DM/0zKcWCzouecDggpPpdz/VjlBXU3e oLS2wtyM3OQn77ChecoSquxhTRGSTbKWuuQUzA7FBiBwbdiHv+DUwijlPWkv8j5RSgpgkYj5Qxbr VtG+j5E8VAWdIVgZzaPaf0DeTm7yFQS+/7vGLUzv4tlk6uTvjXgJaVjsk1jkVfNHCqfN9sxgweqS s32oObWH2WzpQoLBEQB3u6xhHRGWpk8H5cmKapP2UdzEGL6zBoux1DMG3ziQiszxbI5P6bwJygQe wgOnnI7T8ReYUdXg/fzzt033mE0YEn93NQj6uWgd7flvoOFwhgwPDLa4mtEz1McmzoBjLW6oei3x GxzKBewcBk/j0s7n4XK9Swzl2c9eHLwwDUWOiS9Bu4SJGjx8yBbmF8eF7mqPIrBdVYCH8DxnYsed AbK6iZ5sT3mqXpv5si8P/7cs/m1h1D9BM/AYRUNx0tV0LdUpHf1OwRHJH7acHYWQhfu25MdeKuyO kvxJaE94FoKxzrR2l2JPMpxqB+w0aNYfjk4mN1UvYKpsx0cgWc6dmsSn5itjfcR5IDCTDQU+SjUX KAvqy6Xfbr4jKTdWsLPyZU9dGj/QCaNZIZs0x9UprUNuO3icDKyIr0C/x8ZAfkg2gOSN6IztsnU3 AaI7ih8i+AQBNeSbEJFoehlBGclInaSmSuE9LcJUyczoRAXs5OM297A+mAQSqE6zY81gdJBjx5zc 7qXd9S+fyo7Wsuby8pfNS/tH9r7pSRmQoEtAH3EQ+1NOelowb89zeL3q9b56QUpp5AanxlgXouWn t/+q3fQ60OGlN9uFZxfL+JwvN1WAxbXp+eFFWuP/BQ/UQbgjihj8ufz8Hq5KuwTtS1Bxlr1nk4O8 LKJz4u2ZMTWDHUD1ldRCqsk4gGeZ0fjnDuwsaLeBk1F8pNGRercbAIEDx6NBcPZQ1fFxGIlvnafH nzEthd/m1Xe5GJ0iEyWchdDXoFsQYNCqhxaExF8CWembyWkQ6B1xHpyIQmFGZ9X0B7hmQwKcwlOl l7jweWYhGg8LlhvImqawwQFiN676+prpMMWLZ2/0EO91xVlbkoV/HzSEdDFWX7GGE8AQ0kaF6Pz0 pseiNObUvdTWlr7yN3z7pi0YCY1264lO9iyt7z2VWUakoiI19LWb9CYa0gJU5otCaEt13Y+sr5TN WHsOYzRvspnSVhgo7KYAY15cZQcTJxx7GXTNLFP57Ltm+fbhXOWQJ2RD2KykhlUELfpjbDsB+q1u dFXPXDwDy5Z0HRdLc7cWclmIizojROJQFrfSaM4u16u5xHHCGcuBnU7JHuA4neutmRb5R/e7Y+WL +o308j5hRJLXV6ZOIvJgkchgZT7PMz44sxdhtPFfpPt8u3fm10U7IZO4bYclD3O7aKdr4Df3DwUo zEinjSQHfQE6CytoB+0N3XnlLRHryDXbVXzo/pEq5+vGcUsNzhYiRtK/hHTdcNld+nqKxoIH+HEY +DpIJKq1dHsmWG7aGJbG9aFKuT5rPa/cv069ExRFGwGAcSDfEYLxvcWWsYv+lwD78JBEgYEWwyvM SzFZgNzL0rZqY29c0EmyE6PloSocLDC7pE93hZRU7e5ViQF4Ql4Ugx9UJ3IbpdoQ8h9lCJvG2wdu Xj4w3XbW4cJ1p/ywJi2B0o2a4MDf8anRV1R4t7MaBAV09CwgiF/EOofNSyh10u6XTWJaGO38+oCo 8ZLLseo+2o5EgUefI8JJCRspTDsDOq1H26sVg5s5MLHG0KmHDechrwyeENEdQzY7W9yJKQdcDJ09 LlijfQ9WYDssssZzym3V5Gsq0gaj280KRnFoDRuYWyw/bGvs2QKKnaNE9elb3lI3LakSwuXhSZvO kk+k0OL5T8feB0d+4fXgvgVJLxVnFyn6Z07TZDef/b5UXpin4fHI8ivLLT7HnKkVb+Ny6eXwlgz7 yOKgRR5gDkXlaYV4WLO5x5HHl5kaujIVW+OBikRdc5scLSbfKY+6EZaRR18N0VymL16iDMS4Ms+/ BkDoWrEcI9YSi2fPPdvk41UTnm+8aiBjPkHkMCrdxVxERqA5+T99C3g8mHcZBCOPFyZ2ueqEdYdD sf/vitN9AOifZy0/Nw3smXc6ptkMrHMCbVt3vxYWi7O2VndA9d4Ig803wmZMjcxHLQR+3W9PngYD 5mQhaLiQqA8MEMHvFsaGRjY7nZl7gMiYst2pwvJUxpEYAMYa+rBjQGfMfOAmguaARZvRQ50H5Pbo b23do9iVpJ3rj+ZF7LRAYjMWRMeMKNYCst9H6Rw3bqgtGDS5eOTDS2SWY6gac+Y7LvmyRWaWb009 i+vFFOGT6Ovx3LlMq+Jc+pPlVih7hQesMtx/Ceg+CUi7QEbMYXDMCZDZ8yLq1MVH2vIw++xjJ8uc b33ilvKP/fBIsjQewynAG5LfYOPWhDXYE0RSLsiZ+qy8MlYpH8VEwV4KaKkM4VyrPQDze6ftKkfQ fxBXb4rA3BoER1Cub17feDumUVdDOXXevYHmMUv49St7UHCCFgTINPw839EDafF2nRF4Uw0n9dM8 2IN/mVvGP7oGjjGBxRQWOvVwIdgYOmlwjjeMkpQa5RTpmCIR8SLPl0Umnk4/2O6XQdveVNmIJYKE kOiIy2ZkXom+Qk826PYM60SDWQvpEfZWu7N6atw3kXmYozRXvWvAJLv3uaUPN8AwvOnAJoRrUgQQ FV5S/PKImtXZjGWabYhfyg/5dLiMkTKTFLGW5KVl2ptzJnN/kop/pugKhjg5UkcyeOZ1goxdp8fT Q4MAb7TVP6nv7z+KtneB4uwZnIzto1GrTPbHRRrC0VkL+5rFJKvcxmgA1dTA1z5p/yLYOhHXSaiD NgJwmSPywOBL4KUz6Zv7/dkA664/HdQZV5bACZsdyu30Vo3h/sMwbFc5BFbgeZv47YDgMWl0tjZ/ zpMdGRQPXCLDTTOA00+N1G9U6l/wv1QewdfK9yvPpLb55fj9P2VopxAG9nV8g7/m7+kGatMnUTye b7S20qr1ezEjOqvtemmCkgIOOT2gswKOLQD/wK2l13qac1OASsuvOd0zfUHnBO0zc/N5yPGBxzcL t46dBpEJ7nkhwvhilKyNGx6B8LX2OSzPhDNSahQSw9uUPbDndfvnUwOXY3kfft4Q/EXODrzja2Ck QH5PWrgkKdHntTr9Bv6emQtBcC5U34KOX/3b4ssemoi1r1oG8vpAgyjin/2tJXlO/1eRlyWKiW1f ITK/36MXlI0arIyItMh/oWN4EMZv5hUz02DPLDUlg8ZSQ1WJlMj+qMyQF20EkuWRrHnGgjQOkfhf bYM36ihwLEoJd63LqRpaB4w3qrzKizf/0sFU0jvfIwJI1Vli4H5d5JOCYNmhdyhq+rd72VB0hAmZ LGsXLnRmrlIdmN65AxtE2GjL2kdPVZeKPpcKg9ARq41eDn55+I2Y0k2Xb1c3M2h7zUm+mAAxcCtq sdwfpl8YLWHgkWho9epQHljq1STVL2cev97x0mHpSn2U2uRCIBmW4tDw4GblW/w0qNFsZp2iYkKe 5VN1pcNxaVzeKCqKtoSxmCB4REDGC9CQc3XoNUFioobpFOUw026oiJo5bUqE3xGuJQUJitJ7Hmn0 8p9kun+scVnDGkWjiVMKEJ3kKh5cbAdvO6f6GhFcpblm1dYeuy4e/XStJF0u1NGQ4Q6Z2/r8brVC 10bvpwAMmaoQPFeMM5bIqzBlOAV5qpZ1Q+4ER69sZ+/t2QokeCywct6BCci0rpwHvzXKaDn9vC6P /yvKa/93QLzz7yoeoG5ZIuLr+F2n5QT2cTEx20+ziifzuKXz9sSleVE8uQgM4KdRK9rJCc1QCP00 6NIlUObk5buVg8WhqemXcVNFWUCzhW77DfIaAbwKLVukQp6GJZHEusU+/txUQ+JeeIbDj75nx9Cf LcNiP99j+Lk/TOo2cdE1Y18jhy0nGDBg+P4lTDiXg0leZKmodbFAGQrr+27KJ/b3XDQF+X+82yfR 1MPV4K90TJCcCYGRz813YurZi+qX18fVBq/fGnt1T7EuliCA2jZZIckexlCejxZmJp5z7SFysj3Z MQZohXLDrm37H5E9dJRyeUPP4gO12AREAQcR4GkqLuNxJj5yc5cm86nbLgMlB4p/B4Pall3tXuOT 3RCW8c5IVPpxZXDtKxgP23G2ENyvzxBr2YIDllceFK+7IU2TEJz5+YLCiX6bul9EEDKuso0lFNn0 A0G25LwWL+p8Q031xUV6qAQH164ySElFkzrRgFhAxMcCfbLJ2E1uDl3Kct9JNra4+ehKPo55RJtF ZJtA4eSiM8Qaw2t0P1LeFmwOtxvvCd9t4IGvERgEH49wwD3ROamdfRNKZgUqyJoIGR3ehkG2gsP3 sKmXCmQPXFdMcxILn9YHy217q6O4gEy1kC8PBfelS7nyG9NlqwBKUjO3HUxjzc1Jd218XkiO9xjg 4go9yXPPTVjo87f08E062ycmyLvjnVfnuNIcbAlLISAmDzBgOjQWqXLs3RiGcoglt+PsQGvn5NWB pt8kUzUQEI44EBwH7rPnkoeDuil1tyPCoDPasLBg+GLtTqkdLKeesaEcZietrDaJ2sCg9kiuIuLT C9MewwqEiRWXxvaQWeggNloFBo3pX0MiOZ1wafgVri1SM/0tuS9klnVzKA9RAJa8Y1K0y7ArMg+q +l4i7dIkT7F65S+LiGauxkUToIqvicLNyJHmICobCs2RBapX0BqpuMK1/YSY8kV91RrqBDsuQ2p5 PSgNCihyOn4tz22ao/99LIx9c6td/MqdGM+Pn4EOVbliNR2XSGQb2zE1Q+azsM/geKmf0MwDVKwd caPo8stBcAev5FFdDNQ+/ieUL8hFXWGy7diQ3IPEr21NVYqmNYrJNPtSGhYSFVYg8lZbBP0u8mV0 +ejvjCpgQdRagiz3YRIn5pgYHonNgBplC7PJ/7fDNTrZ0TKty2kU6HX3AHpwIG6HhQA4BdMxQ+iU 9kh3t+mpg1A2xaNv92wbU/fjJ4IMU2T8VKRHcvRHnSVLClTVQP/yPN54myakZjLkwJi+DXE/URFK qejj3Z9vRV+/DdI9myfegrjxsJCw3yDRKaX9V2zXNLeRu7ca0X6/OPo12CAgVxWZ9zbjEdKR+nST LABb0g8dPzF2DEMs8bMto/x5SA+TYSPliPMOsUX7BPthGY5OugsmcszuGPm2riD1xKPEWtFoLaZI D8EGZSZMdeUHDtIHWHkjJdrVbAVLUXQCcmrkfRpmJxaKdgwsLHDJJD9Pv8c6OSuDVN9pzFg5glLj KACCfQGlGimof7CZpT/2H5L8280V5x8WMnUYj2T0DhC3gtb8rE06Ka54HVVEagEfDfnimhNytjH+ 2BxKFCaCm6DBKeC3Tun02S3myHJpUyVZ1P+sZdmAWFk8WcWu7sP/NKJBv2ELGm2soolr6IwL8/ce loqF7FshjEodD/PUuoI3qU/8YWwQBEyDA79W/03FGh6CLnsSM4VkER9U7iXyBBxK7MNRY0wfl7Hd fj0Ss+1JCYgVsztpqO4BcYXPLBPbf9FDEsbaU+Y3q56LJSQbq6/owk6BFr1oPYwprFN8k+oava31 5nHcC80TwvKsGbzOOaMVdyytctZ0+EZe4FkqnEo6AZBe3q8j1qj+8wUZOzgZgdegKfR5grHmIs1r bO4L5CQdbbWjO3vjSHv/y0pF6lyF0GTG5J0ZWzYdDznz4EUCoMrxM/iL6cgIcXJfONRXlWv51aNU wDxrMeWMGWZgSeuheuVEzNVTqVV41d5Hfuu+46p0fuAbelZsYr6CwVNNm0De/gm9nEeVy0LCKLfU PIfQlx7KyRqlHt20UFhj5XHqKo5Um47BpaD0ZvLyDFFF4N49fLOsPiQNf+iVP2CQxDKGgABbedzK JPM64wrb9VJMbj1RZ5PaEGR00VKmr3rhUxI8B6NmXw1Pbjg97aeQ4vovtS+gHRB5UryftI1A1XcW PQboS0ZD2OzOfopirF2TwJ3srFaFIYfp4OB6J6bZe4eMPFJoc/dJoASCIMRKv0bLdF95TdjInU2Y EXpwKaiMmJ4+v93/Tberhd7W6IhPKHg6HtMXclwIEgaRn+zUy7qssGyEnKzeOjO6eGi4cC2jifL3 3j7QtV9NCnfalNfQyo1A7y49ZdfPjDKtPPmWFZsrxDu5Dnn/pNV1r0UDJO+aLMQsg+refeCiWKnx TQstjVpvLiPZQbtr7YCEMtxfJ+Jxa7AfLgikhEtgCbiSqn/fJj2f1oMdIU2/ZreU81zkikt/0xwW fjfm1Ght2nOBZRTcn+fb7fk+zaA/L89glQQ0T0p+TiV/J0R06tVHr+1RX+/9TaMpyBRJ7BExVhSQ TdkQynvcTsVpkdGAbQrkbEmlFYATSSo30E+pl01y4nKq/o+xLmwjkHj+uHEbVfDClYS8PM66mQUA rzd4kQdcmfzz/gVGWZv8aZMI9OMlgBv4sF7HNZmEogmPeBf3oqREuKFJkMOr0UXch6g4DGS2ntCp AwblLjv2f7NDWpd3DD5xDcWa7ggrENSYDjo26xiA/CB/ct/aIGvjawPRnI+ZhwhJpa0AlygWUgi9 WZI8Tizm3kmrITm8qzfk+xov3FrsOlvY2Vg1HQjarMXVD0KjoZlBkSDGYh9Kcuce5ekjRlk991Ov uMRITYt1Sv1fFuqLck9/0Za4bDuJ/3B+Qame5uK3LapTMKKtGy9nO0sZJp6+HtwD60G5EJixWWGI 0SdsYdd7IdxWf0q16sRqustTuWFXYbg5wSb5gjyNhlTxF6r7muFWq5B4Qt0mTGF2wDYZ3jIy2Z4H v5PVcJjDbJqRKVZkz1b+/GhoYdHtelouUceVaY6jli8slJoFYaBuyDXGGh2GpuRLnuRG9cPmC3NZ Z+bhLCbj6Tsi7H995gg50CSzON2BPt2glzkrJSW9RbA/1lSL3sBx3CD3PY9068eIYh1LD329UfoN ZmkmPowp3AEz3YvVMz3jLFKHG5SowaN2acvalMnGvRXz8H+tJmnHgUYDaypJQlVphOp/q0LFSK7r d+cx0SCpBwkVmQThzw9Mmj2Jl+WS+GFZPoHKOwFxXrQTUoM+NI4PAepYWPL0iaz7+OfZpOt/xxxR 70ctESTtKMJycLCP1WibYUmZYH1lZRhBiKrImmkHYolA9KcORr+Y3fua9lryFqPblTb4hetUnWj3 Ucw6UDnLIFrNKTEJg6T832N68PZK+b1IB6kjDkmsCUoJ1tXCFZ+q45b2u8kPe00MdHapWS+fLiHC vYMqJ+IkwRkZJGC3pUNAbWinR3e06CEmWOYbpEv6p5bWh8XT92FAbnRvPDwShb98pewrBhEI1O8J MCyERB1mm9q5qT5TKlnrkMsosCoo/HVPyQ7xLJlDVIHHAwaFZ/1OO7p2XPOJky3tXnpu6L9EyWv5 +Z/zwzATx+gt8zggRkIHEpgRJa+8bosGq1XX9UHkG7NU5Gs17cyzPvGcxtLuEswtQ9VXJDA9TB1e JPUAjwVEqD/4+z7kLz33FfBI23DYHjM2k9HIEn1dDpM1ar+JB/D91qwW1liUHC6zj3E3QLQ3sG/w iyoCklrjCVWCoUU8zw8dtZylJNpbDIX1fJatey3HFSbKv9XuZli9QCf7RnJgjXWHY97lV8Y+xKeJ mO/plpDGlzIWlyRienODooeOr3zw4wscKz2RnNKitZCTIpQya5KnZXPymKa4bKuaY4uE8iM23Ctz a+0VmOGlDEddHEKLa7Cxo1dnX1nAqtCuYLUBU3RX189Pc1lwM7znS4xCHf9TVDnQ9fxO9Yr6t+xg E/ao2R0WHMVYP/m+XlQ36bN+SURtDNb5/G1DHF989iPUgOvQYa8TLVTAE7wNQnsz1tShr0a/dykC ZDsb98FjJ++yxPr20dTq0pTxucPc7gxx/ytwFaoRV73/iFJZTYeHA7/y3D+x8M9ACeHfsh+P3OnF UTah4eLc7tKNGCWKZR940nKr94/5NkjdfbhB6LnlvXqiF6fS9l2GUUhQqJRMXPM3WU/0SpnOH5fS hdpkDTT5n5Y45QsLx1aNGVbDcDXMpXrbnVUTgVYwJ5qT56KXf4OfJWIiZyz0Kc0G6lU7XY1Ttxzg M+LngxuEzPWk9633R5cO//lquXYBAmTTrHWhctlX0EajS5ZOJ6zXuEBcUUoU/ujNA+lMBSMSO+z0 WmJpg8pe93kvAGR7Sh1CKrX9MpsqPWOa0gNKoDHZWJkHGs8wHW8m46S6J9hy0XNtnTRF8ZlUhfnt rSPiV7gvkw5r3FTkJKrOofkdhGaMT7RZcrCKBP4UHGShERAEG2X8JpcG4hrrVfy517Xx4BdOj8fy 1IuufJIVgp3tp1sd02YFQ5ong8vFl0GKSmAT/uC4VkUG3WVEkrW/x+QE+aglnKi7L1tM6nEcX4O1 VvZr2z3IkhylZbhkqqatJ9g9uJRJ3eYJURExHqtbeDW7Jr/Blf59jNzB4lpdD8tws3F0+OX9Cxmn MRhKwRHZZund+WYoRjgNrkiiROqJoWpqg3ua7Z3ke3b8OizvBCNYn4ACdX+5Vf/rsW2AzQClQANe H72MgtFT1f4FLzIrsCP7bln39E+Noret1P/cPUFj8YlQeyaPkVMLD6sh0fWDSRpndIUXxsGOEskk aMhg8w1NhS1O/qCzwLtEIPd0UraixD/VlWBSLvNb1Zc3e0Ucf938Ox18affmEH3z/bIjNF2copvS y0uIqqnxhkvACPMCzs3GfplTDwJEPdnJvZVMubV+QNSosvc2eWCjSlDEVk6Xx0fjNY+Q/Nk7C3H8 b1sBMQNmHh3jFAhNQ1lx716+8vhFf5+IUhukXavagKDASP9auNWaMpP+Y4qGG0tSfe/xppyKz6oG 6x8GaazN8Vt7BlE4aowwtJ+j0OrT2vr8kwvhFgRw2Gk8nkFqMV2XOk+G09OvkswRxb7NKo5+PBb5 7NBhxayvNFiGbZULl8wTwx1s3/VXloCZwpq6hAPSAsnh7djsjP8tX1wcJS1bI+pTV+PSO37V7ejV Q4LHVPxuq89UxZvxwT66Gn1A4Mxj+adRzs+ACTJELdeBPKwTc/WTwoS33Z1UK+i+6hhktTFSuGUh ZRMim7wjdf2xDPfSuZOZCcotwQyk89ngcBgyhsTfFdlgAKL1fKv28om3txi64gMXKrkPM2DRiL36 1A0TRp96CEuRuVjqEZH8vpDwtvQ6kEKTRqqfhWXqThrjNZrAdRuVhn5J7u1alKTtJ75B2n62Y/xZ a4KKFC4akB7la3otEilgrWcf3ZY5hNOPl8ginnUuhvzZgGdljN0+jRyz7rkjsfOSkUTVEs8bochn Uq4KlCFNhL9U1rdQx49NGI7VnofcDzsGDVWUti/cCxTBcT89VuBZpGIPkaP9jPaDGxX4P/tHAZu6 tyVP9lwC1Vh9IxihQ3Y2SSl19L4sWwBU0ycv8T12YA8wJXVoYNazgLX3TggKR/gSg09hJbCaL0Z4 xRciQyD6x0Nu4k49wjvXjqHR7g2zvRC2+8UaaNR51j07GtxOOlNLl8KpeAmeKerCUNMwU0u9pz9+ BTvQ3+fqAstii2ONuwtK7XkNnkqlZA3uerJXZIu/vlA9MU9hTtTzAXMmYpVv/OiYxjdGAoPTtrL+ Zaf+FtcEjhf6ZxQoFi1E0ppSEO1+ar12+JiRMko0VEJCtyNGnIlCqBDMcZiD1Fwi6xLBLmfBjEUd iojWycc2VBmyWzNYgSf37u+ENK9GuCgHpTLYcxmbd8bxF2xmLDukuMwVev24JOUsTnuLDjqdrPWy VWO2VSNW7il7DDoPuu0S/jch510bHSCiBAiDTvkXUurXv3ms1eBIWWUcsb6Px7l0lRawrp16BRJb RchOjwSH3kDkCPekJ9AkOuOMdW0Q88j6MgvWkM/5H9uoTXjj2yEV41A4aFjqMEuzdo2L7gogVp8I hhH1GHkeYoh4lnQDzvxzOXfwCNOsSAdntpqRfrqOiPgAZS8JceHwakCJmINB/VHS3Y9c5bX9R41G q6/pBubqimkEaXyCf7Vfm2VHYtSVPpFXS13jY3JeXRXsojzs5+wlFs9YCnl1GLpIw8C3jFWdvkZh W6jit36HQgnFw1WcXkSXaheV/zHPLvPodN3YzFp8pHMs9lkgR7qVrfuPJ6EdxNO0uimCJNK/JMob 12aC4JsiNOcQ3AX2rqcQWfsnm/G2gy1wPlk+qM7y7P1VXYMZoEkz+jB3XhBllavaaNe/SnSkCCr2 CvBLYh5RoGQlnFMTEJ59Ue3E3Ny4DHsLGPuQfAVs/2t2heYQzabcUkYP6qBskCzPw5VGW/oOQPej GAc9XCTt0FCGtIQKYE7tmLOaAptnoESfYSUariZe3/6rUS3S91A9ZO7xPaj0AqIbX4IvEl2rZ0B+ jaiG9Dchel9NT9K+2cU2l4n4r7uoVONE10rCL9cg69gKjDZ8wWuy4AgidYxdCdaeAaLYxEDRNuz9 9o8Okm6SH18XkiLOmrAsPKomQ7WbvjUySrnnH3pyuxPD7LL3aCMNwc32lpdQdfJx6829Q8rBA2iF 5n6pkaNWLUEn4NI9BeSJkpfNnAZ1Q3qTq/pdVIFLbfEGjPL7GrNLMIb6o9k5JtSanFkp0igHQi9H zCyREpf60q2169ANTzvivwqWOKnrC7LHaSqQPyzRpQu/yV7dmXBqmq2X4u2ZbXQXNIXR9Q6HCLGa Iy27DaeTTlQlTvceXNEbo2d/nGSMfnLEW19bEvUgSqAHnUYeRr5/IiVoAciTidDkmeQ1CEhcx23V P2awqIePDtcWNQmjTEUmkcLL+hezEp0x3DGxDEz9x476x7jZl29odNmwsw/FcFB6Nywi+ZZp5OiC 7noRNopnGkgHD83zQViAjsZDKCe4vg+93Uu9pMWFhSMFWgs2twASj3hhIcxRYhkuwcAVPi45Wgln PPpmrzxv5HOdJD801MdkQu7SjW8Fq6ipgWJBihAiResqBRKzIqGWLniHsnF9ZDFw9ysLsVeLcKjM SKxxV+69V4m9WV494khjsKWpLrWp7rlOueGSupz76fXGL/tbAq2r9i70YNhJZnyYWB1anIRGTqUc DnV5g0rqk/xgRwZPrWDNqhXu7lGo+5lGKB2a6+osV3JKqpig+BPHUkOjNnOmWJiJ8bfBoTRsipva GVt+oRbpCjJoQfUVCbbXy2s2jMJrDwVMXwNpjFJ3ukEa0kmEE0NYpPR9T6v6pQMZ4EKYVYiRA8vV +0O5Xk+3/3B7KTZX4RE9MCPdPWez28xlG/nCzuyqdA/HhXBU2MgdmgE6KeUE7/5leUZOz6t/G9+3 /G7x6m6K6MkchsEqCrDl6uhewBQV7b6s3sNzNl9x8bPVCMPlHcos6LD0hrg5p/OoZqtPRFja9MAL 1PU8eTbVQ2n3tFytd53CmY3Ff43RUWB8TOJ/3ZnSaEyl5qNRCEMUUiImQh+3ZOFraYe5DR4mHFZZ 7U1QpliTYLO0tTvr7AHNEoH3X/Jgd2b96eWC3feYkz/PVsNCF8+NX5xVxsWLUhFTW1TaqAMbWCZ7 c+yMA9asQb2GviA00opziGFgnyowqzbQtJgEAiTgWYQYwkv1p0pke8fOyZByVpIS2DxHN7Q7dPWO +0tjKA3Msm8iJmN7ddPN6cquce55dXkMN2RMPJs1iZ0pOnmx7n9uyyllE6buHD0F3fpIk+r6fb4B S7Yo932td1douxQKIChPQftqaJIpdfusS2KMwvArZF/MTGSzBQzx2dU1cocr5qYQ10jlag7g5qZe mHwL5no3UX0X7DlSwnZgYz5O0NHK1IbNGqtSpcpQnOIFawFnuPF0sxuQmQZKteULhPntKmnQT8oc 9/MdDboByHx2nngULeL6uJtry36s1cMVo/zMt3rUpC7xbBA/iTUHlQLjvw6KVkG0ZzpZtGCCZl45 lCZdjrI7gUVAsSDX8XJSxR5DnkvIZymAq5jnSg+ukdbUgHp3FJtx3voqmQkc2Q7nxU3NIV/JYHB5 591CYD1mXvEBNGi1402Y+KDizaDpZx3pN087dkFuHsjpcRDnweHracv2lNOh7d4NiRcaEp8BqzY8 eAmVht33j5PYPCeuTAhQRsRDcd7N/M5EaY9e5/E/HMxQPl/8SjAuyy5SX2BscNaXpLScet22WvT+ xlSWiVQOhfgFQEjJXgsMlb3FZcZSVBq+x+mTWCyijz6gPe9KC9vZgl4a+KOQGt/Kf4qTZddA/dL2 s/+njiPAkuVtpkI8eexEq1nrGdraEzTxpTvXZINAMSGFvB2/kKTIV0aNPkRzj0IWFJMElTbhoWhn UgjseFucCyCJBPeE2mQOykmWL0MnBYB2WWiwKLavC333dDLHhsHEi3+Q/884+RgQY+cw3nYT0OoX xO9Miz7adesFLHpEhop3nv8nr38X6wpMxlcPzUoy61sFA44Qf/M9/VNuTqA5YKeshyXQlzqNHZrV hRCij2FqEvzGkNodGsRw2zGtWwC8izP3rWjg14W5GRUsj6VTfb4vHj7TC0KxV7Z2llnCauDGYhoo zUCdACX/90vlc/bdZy2YSqPzjftrd8yiRVdU/NrDcGvnhte+fZKipPq2O0Z1Lu2iW3ZyPPucQJQF Aq71//HPHWq4TkY+6IE8B0FtzBEi2BcidRjMOEZaHMSPfXko+SE07QSCJSaqe6cNvHS4ElMU14b6 GgyUugULubdWrzjxMxEMPnJDhI3Y7I1Gp9D90Ls6FkpR6z0ZM0A4WCFvo/Vp4nMqYkJeYbQs7Wc+ N4x8YdvkSQGANA/9KWtlOyZJprbzs/fW9CE4b3yIsouQ6wg9mtacj1p4XDAX7s4wYQ5D989faU0q EMZcCs9ZGLgjXwZxIXuJ8r7N01Ie4YLHL7grWPDLxnSJR4E/mah7yk0qu/Eih8CAG4Z4nQ1NCZri kh+mYm1DtaEtjFIo2CMd6OJRn60GpXzwN8tph052K6IRisB0RHg17oDFNG6I7NteKEsXRiZXrTfF am5cBoSy/nMQ9Rf2Rx5qUNm00WvJzuPek3zZSM5/Zzna40Q6ETTXrzqHCgvD0maYjoJk1UVIlPCk kGmha6D/mL/s185QWPz9OkKJsU844M/duNzxDXFSPs6u3QOIbCtqhcK7pSrenVGo55VXtW32yO7Z g1ay/HeJNPhLjXA6LMtShRcthA4g3wrzkI4CBKXVT3HVdtpj75iHn+WS/09Do5V7SLk2dJ9k5e/+ 5JWhZCA5pqiUfXWun/cJuRcIYyPMgXm2h53qPcMMNRARV9pAjq4XNWZTaShvH9WU7IGGhpPSYYVk 7P5JBgyjmADwqi6zTE8VMw9E8WGmPwJjZ1bTlgJlwSs8uplPuuErGnj4XxdKc2ZAdJmDKTDRVBs/ ztq8DV/yZBmqe08b8x4W3leV7sktyEDCFS3o2vhMhUACc9v8ObgDiFKDly5Kt06eHD9k+sDtbhOs woF3i9t60faaPiXv4pjnBzbH2OVrQbTlAT2v+pKyIkpIczvTBa7bRlr2lqYzvi/Y3+8ETBrCNrwg yncbO+XI9x2qkjl8o9hdBbRIunF9jG63EuBkhw48Eye4exAmfKQyxZx+KoE8E6EqXuQ40UvTdSyB IwqRiDXMxwazY8ZxeEZxNixuXGJnf5cKw59aLaznmW2lIpO4Dma4mdirrA40ql9U/5T8hyVvHSFz qRcKqP1XHBM6BOBjTHNztSLluWx/cLncb9J/K58r+YYRq4Y8Ge61Mlp7RztA0bO3Dt7gUwd/ejl8 pT+HzfOoP/4R4sgpiHPLAQp66dMlzeswRCKNSmIaJ3o+1Ic/8QYIdnN6teNwtMQpC0BegJV4ErRN vtjZ0CLQDaONz7TjkJPBdbX71l0lg4tjuxwoGnMpr1/wPSBayOJ2JvqjqCEKzqPt7/xIxA8/bFVX crN64V0r7kCfEKnYRlQqgfz7ADNI0mPCePtyndqp93g4CkdhdDA1KsUqtX7Vwu61YDdaJO1j/DOU Ma3g41sys95+U/qsRTbbhc+Jn6U/KqIxYNO4CBuFCR5HjmwmxtmuLHHYh1bvpWhQBRAqHctm7WJp q17BFKam0YW0QYddZmIdr4G1/KuyQQG0fQIS9Y1JP3GsKzxhqL7Dlo4mZnC8qpFxFsY3VH8kL53Z r+u5uwCV1SRpCUojF5JD/HQg9ou+xEhy5vsUKeNzopfYFeZEsjCkr/u4/DstJD4d//ggYko6VIG9 Fwk3tbL+P1haU7Xgp8rrqwSXr/bMMHjlaS8Cit0qxbOIEM5aBkR4iN5Bs/IusdZ6fa7hx/WRwn6/ LKEcqhF3kvQqlxqTnE5NaSlrWxoKiMceMobiAi6gQAgeZgZ0MbgIwqmz3snciYensc/2r1euo3Ya 6jLE2yIirPJ0toQ96AdENigfmm7cYaz9qTK8x8vkThV65V6VyPgBXxK9XgI3psPMiqTsYH5mz7pD r0E+XYDnc6woP2SzCMRNiPNL3rX3EOSj0kCuYVfq/ztQVkgFZLl9Z7ckq8Tirn8eCh3+CIFKvTkl HOz9aknkg/a7xoMd4T1W9iTypfGF5uxgBTO38dz7IJDTsVZiDrBUDTyIPBZYXVY1AvzwGr3hX9Fm GfkgNSBoZG9dAyTKPybb+TEt//3O2sHp2KR2Ac/i2/mhkywncqLYtFcSXYJw0jOhq9zWad0QljNV jbJnxqtqKmIFsRA1YrE/dFDp/hczc2UWCvR4LxjObauvsP/Dn3CmZ6qCfSorqpfNSaGks3F5Ycs7 cchI7RNI/UkAQtHLYgD4tLAiAmalZFKf8R8ucUK1yTRswm7zp2/yyJd2WxA1iW3r/w54ww7FyNqS SNPYFtex8thT3hVys0WRX7baQ9TdkBgzoYwVenQvqPT5tTYS76s2V830fpMslPkjDcUPxeDp3BSv djDTdIoXB6lh1wMSAaRF5txvDIqD/e+JO2nJOyN5T0GGJNmAUYHW3ng4CSxJNHzQ+VNpEl/BdyOl OayYUbPb4LKTdwDO28ug31li5Gv7I2yJEhmx0S+Y0JxoAtJWpUXfIdROSiiWgLvKRmLMJF2Ryfis 89fA6zDooT4inZdZ28d6VNPVPTuhpgbxXEemhblkXvGnAXCn5mCYTDaXQ+d4coW4Q4Fw8WeEp8fy N3g4YTYy1WGN0MDBgCnRBkaKu1PRi0dS6/c62uCGz3rJLWZQnvPU0NS9cohXS2rmwMdBcZT+arzO JbBzkedhzXfG5i3ki8W/4k77BwQcEGMnm10xOdbw50MGHwy6byQBE/WjPOBeUbKUlkqqwswTXbk6 /t8drZs++rAz94O1yhkW3Macs1tNUBnFSYpIL1udu9p7rrMKJ1ZKfD1CDLsKvKoVo+kcVrXPAReP HONW1cZFAnACzsATPeofQrZY0mOoKmVpORrN1fiMtETaoT2FBg/c+jF87ujUQ66upKx2c7u7Pfqk RGzJmUzXThE507NIjcJMNQyegJBwN94LcNYujvFaWckPxurjM5U/Kd2HC3+OUIcw/PQzQg6W1zG3 msC0veYezv2hckaCUzjBu8PrpxUUR2kSz+0M105eBDP7xL8WpL3v0Avtyo8bJOnDlDIWVzxvM8Eo H/bUtgUtMPdQ3P/iftocq6RW1xhYWWFj06lViPW90LgS20RhLnTnIPM5nWjR9sBFWmzWv+EJa27t qNSCbQCjkBDd6N4L5SfduhZHU8Wed6LOsUoBL9DRRSAaNXk4UfWOCejOyKsl8lnFFneoOIdAKmM1 6sLvXb6gm+hkq1Z/a5hwwLdW9o9lKlIb1DYHHgrywpXipU7Pp8K6O00jO0AMEWnIsf054RZ2rt4w DkhvJwjBcw+0M7Q5PDpPviNEFgudBdcqiti1vey1E2S8aIXPUgn+Rh9+HpfhspphZzWJZCIJqWbH nUbCh7BULxLzzN6Eh7bZxrfbO3JB0DbLXz8RSMd2EcaavGI1RYDgRxQ0sZOHyne6X3/LBAoIOlLl UnJS1WPAtOrMPamLygE/BdTXOh15Q0jTnATDR3Hf5CmlUW80No6DPAxh+4+f2C7bD4ur7SmYVRS0 xmLPbGj4coVPr4aWD6yOTAJS+B71PCdA0OLKzz31cKktv953cNUewA3BFdqSxMMRpplyCfa+SKx2 gk60Hbou9/uZReJQ4LYvJb1/hL3IJPpPsDP/k650yJdmSEdvIUx7lDvxGYXwFQbBEVGjOhIqT/kC YtZz4jfM/x91OYntKSmp9jMqVjA18BtaGIhwWUF60qdwUPE65G44h2vqXzJcbsG44ps3FXRKn1sq MjkP1uW3qSTQb0SJr5lvv2vTEoHjmstmkh66ZaKXeiAkzfXaeO5hzXlOZ9DGatoHUab2EQyKKzZa MuLx+1WSRlP813im9HX506AMHS4O45eJJ6EEVNx0mWkP1GJdye0zR7+KvQUgJgm3z5038KP8y6hw dbJQvmGW0q1ZhbvXVyxYmQDUSnSbdFlMm0v0q50LJyiJwtuZ+MSpLgWvKLa6SQDqXBD3OWnTqv3c W16/AOBlRcK8vqYw2dk0UDRsRLCgjMhmuwJcIspFs6+Jg4OsbW7Vs7JkIRaGQ5XZHC/LNnyFcFhp Ns8m7oMzuWejBd4vl0c4xuNIUn61f4C+cEKFpPhJM7x2gFguRTsY/LCPKXr554FWT5tYT+ys0A+w lR0glKLjd+aja1l/Mxb1alsIyO7iG7T1J7nbqMxUGvr3sZ6MAWij6wioi3S1UgFnLzPECBaY2yq4 xvu4f/X7s5l8LIs+lxsGKLLqSOyJRrnhsRWHaRyZV1+bySn310M0x479NUcGNZmQRYM7VqU/wrzU dPU27kqzNDSGseny0eMsVWmJw+dgLgw0w1e3DiwlrGy+uQWQFD0S8o8vw9BPMBJKMX6R1NRkS4hf sX/4hQoE8rOC3YvyFF5YtK1ez7HQqzoaByzFLAPg0JI3KXj4JdnfnhVwSmcx7aRfaCYEygBE6qgk Qh53W7iWaauVm9w56HXZpHqoBgRFP33owd5T60lWlYoJUxO6S9fJP0oXabfh5WMJgurJIB4n4GuZ G7zmZaVYXXDGW/TLwfdTtr3cRowXkFnzsmrtrl59qgeYi1ZGQUSkbfoOo6+k48rnVijRw7IaP71L YedNhYDvXKC1u4HqttVlthULdjHlMxbW9HAp53SRNyyTMehZvWzXHp6qoLk5narZPz+aUBUzXbjS oJjyf/K4h34kUvhvzatxCz3WCdOtF8wLBn4vsfkhVRY6KsRRPT6eZ++hQ2tPVnpe07orfzteHGFV rzXp+eAogAMWnUAS2miUsyg69Z5DUlPxYItJ6QND09iNOG/rCCWwfeM5FfgUyJM2a0kDQ0ebhqJ2 BnkXD05h+vji5QojtBAxuKFtJ06v7G4AzgIcEk+DXQTJNyldmxe26SUv2KyRmnoPiHDOIzzMq9P8 AOwkfKgfu6ZLzzhexs1YJuQw9H9M6pqV0ibJgauISN0a3BCpzceqOJYlfqRisUdG/Q6gHXh1XAHH LLNRIJM84YFvPRqgRfLetAQIatPViSwJYp0oSb89BmtMpSgKYedHV8+swQ6+eVvTicOK6N3x4Qc/ NLHkTk4raNvDJ6AdbAxIHP02MYuJwl+X/0fWQJaQ425B3h0xiQ/ZYOwvXlVp4Xgoe774jfn1e5Tx 3SXYWxNBx849j0KfCui82kg3KhYbqSmV8JJsC5QlKWRxsVCeOYRA3HcHTTv4+IjvTYsO8ZL2hv54 3BNB1euL4Zn7NIJbkNp6pWi2ukJ+ESkCMDsLe/FranjtsJ3I6/+eCfavCHTjXJuGSeXgc2DD72sj 07cWXKPFYqwM1C4eagAByqdKx7udZoimKarXQqMffR6FdcNAh9oDoOLNuaojin5R7cH1n+VCSwsK GQEoSRwsRBfzvbhafqildaH5FEcDa83mCmv/P97qXh8CkjbLtUgWCk/TpgOErFjX1jwMkhXyVnLQ AQ+K/IedigJ3K4PNAREZgheYCB3HHWfHXnTaUzaQJBQ8+cpCbLX1ujWGg3JtThyP/rxsVRvSUG82 HsRrVXNuREXMQHJ9/uZ9TsGHi6N/EIS4wvMncoY0TLa8sWj9Z73STH67sMlzh4sN4P5x3kbh3y+e HXe8+Zp3+E8TfqCrLAf2u4U9dXf04pm/h/XcRoUgPmEhVe5TntdgmLwhGT3Fn4tG+/7MV3DTVZA7 u4MFO5l+uejZvLu1QZu9+g2gPlGvj/TQBBlbGb6bNyczvqZ2U628v8BrtmgPybhGz98aGsYZrRG3 pkO5k2cLdcGki+//gL5RP0bJ7c0MlPRLx8dS1P6JGKJoTqA7PFFJ8GHVlHIUFLNGD85UQj/706J0 LPUHzEPbG2ZFsXwSSLjyzk2fN1hmefIOEpB4XVRk57Ig1rUoQ6IKN4Em3FyaqUAnWeT5TBhrt22l VnxHoOZYrYfYAH8ikT0e0cjRkF8uZ/UYKvuTMCUwz7Wt/lyHrisSU4iTxvjjKzGARE2fotcIQTUX ITgsC7HctVAs7XU4MZd8klmeenpB6oz5ywHIEmFKwgFedevJL8SyEpQztYuR2GFBpXYYRgcnG98B U2iHCldlLJ578O34tUAcHXdfBPrqcOO9R/Yd+0VssIbh4A4k2vhmmis6UUWBIj6va2WJ1SudQvyg +gI+kV0jNlv4a2EaHtqptipuil7AQJQHD9cduNYQ/ABrp7AjUJ7C2JF0eIJqvw5vSx3fmnixt8l8 jVKsw13/8bl6jwkSYWEiYFP28z/XeupHFYUrxF/G9NDATCHL+vTeX766GnUGpS44jzkmL4pU8yAU ED5YQppiBUFYSdgnOqkzmpDKi1QuJXJzECDLclqJSn2Og795mFWSnfwJ22uLlnRAs7JiDrfx7ECa M/UhZE+dDfE/EuWHhopdoiCIbqF98w1+3urptTMaqJOhaujPiNdRpo40kJt8I9MwqQ505zzt2oiO wKc725aXn/lXVlKzO+5FBBwRcxK2Q4TUUAtenRC2W075dEWsaLbz3qTZCGKbOyUJHOliwhjaDlYR YFL/NK90o/5lWCNL7W8fvzyU5nXQDfx81Qex5tpE38kTFeFdcrxffeR1QZFUstSMLjQN2zsoCpuo GNUkO+9IvU6dH3/ymyA4rzoaHk1B4asjX9hs+V/Q5MVsqrJN9iyqaNPYafWOOPisdvN2P5uHdg9L 5NEK527r2wo1hcpc400oPdatFvk+SZyNJICtS7aur5YByT6L44+dDm0HBt7IkgClib1zHoqv54A3 SnVNmJSmMU16WT+5TvyAROMcVaPnQaH3pDMsfH7QzCY+Ud+PkrEQjSNp4m3dfipKzLoHtcqqVy/+ 9jcwdFQvUIOv2h1njgZi/mMnsCGeDDocDsl8BoOxz5IU5810ugwNooUkChjJyqpSvjkxzU6jhfrt B5CKgYjGSeEKxXVM5WnA5Dk4Rnx59/mxHQxlXr46UQO9Y7HQoq30xpUuNioPiUQ7oNtsaT+t6k+Y 1c+Ycns6FnHSSpmEKkrxfOTohd1/iL9OtWFT58vbfTsNHf2j14Ts7/GTXcy/hc5bdAcPnjNe2aqq 1dZUgEJl/2IyWrbHAxtHtc4TWKliY5jQqrnT4Uh2IlV7PHQ8aTNvRftHXY8/VTc4uQZP7gEcxmIV pRZXCUZjy5dp7/R2HID/pX62UwQcNKxQfs0ZDuoaxpM/ldBmlzs+i4vhwy90oe4jAuRF4ADLG+N4 DkI81RNcKQ5iPZkD081H+4sCKvgTX6RQARVeIMUyvijyyT2B16UfhHCGY2hDsstI9A7sK+a+J4Op iSu+qalTqdRTsMjLKh66Add2PES1Q1dlUfzjA//6JOnnoG8HSMg/iq34vS5rLVC4A2D/HesqHE1l Apah605vEQzzDupm042+XU7D1nQWiVeRdtAbxgveoUaBIRO7wmKGwRslDqFMPDngNd/BJObO1JyE GJgeKckqe/Y7XofEGep6eaHJLRGKcTAL9c5igQDkCDiaypCVZ2FAR4kb2vkRWJFGSyIWWpzNpvVW SxZD8rWle3fbXeZoFUeLiSxHDVPr/SgDwxtShZcL7ovh66GG6QDTajfInoqRpYXQ6BcBNJ12ZZrn ejaV8w3PRX6ng5ypDI6wy3D1jfz5z+6ErtKFgYur60dCcLYql442dHH4RnXkwB4LMwdKIwtCBKhL NuWZxrYuoY/WmJ8Pk0dCwwWWGPm7jUrbwUfd63fv0LlONCR9I/KR0txw41w+dPRcx6YYRqgHVPeU MdvbNEtPw2XZ5EFjB1K1yBuOSkSlB4vq0FTyteFUNjfhYI46D1htFStSUOTvcjUYWv88+5PjyT+e VVE9RXt+KHybAa00K7SP0yeuMglzxuVsoSjcu4PZpd++AmyMjNf7qPc2OfQ5xMMD0aYLh0rPTyUV 6VZLVv/VWQpze6Y/XRKNtQpu/Q6aCiX+Mv6Unck9ZpAhBACuQNHDhac9Ugd+aYf6hYOiPikBPVye fR4I0kjQIpCaffavBRdDvjObfeznxV21GfXwqjw2UfP3hmngRYAO5nMETvKDiP1vYcT39iraGyDg 6baMxnH+MhB19mQZcqeE2A7FAq2mEjHeaEQq7GEi2qmlWmNnYwAPOpcWHNuw0IVHOADC9LHMZtgI Gloxuy3b56jcw1tSNQuVdXYpENXcu1kPFVii9v4IDn0EAAUohHhdrQ/XWu/tHktnL+IiAlUPcqDl VyVwmSLKt7+lMtBVngecJAz7OHO29nL/dGWrszR8m9GJiXKZyG1xnPEhHw/H5AEBgpqWY20ESxoU Pux0y6GofQCUNRU70GpO/yUF18AwnovcrF/tjQbXGlDtb8y/7irNkH0L9WhX7qyvAhZUhpBsrNmd sSnIUQS2kgC3P3tG8Im1veaexOEFrAgJdjHIIW6S/qcmIFHpJ0uW4TLXb5zZccnDLsM+h5iwlPAi MrFbkelrfI6YMpJevaK2lMpvXfXdAN9JVaqRLoKMxcobc56XcvfeS1EiLLjQO6yYPrqr1WQv5xRu JMc6UORYuvMZkSL2Jk1ozHHdP6pYUpuECq+ZqJdksXZuj3Nxy8mXOoYjRmuQjPClrMNvpamm6meQ bPSehwj+j0OL9+pSDe74bQb2i6YSZ8OPBTYDsRqiQ8lhP5qUvdciCwMPjEt+ntquVTzX4XChsPgX xWWGlpUE6oLSv4GCmTo9mGlaDvseuxVqJUb/02s+gM1Jgx/47SEf8kS0Wuz2tjydpCBuWr8MAiJi Sx5+ermFhOz1LL08cJBTILx1F8fB+p2pfnQJSVrv+Cd7h2x3yXmjgjn6oGwcJ9r7QShlEDONqyHO bhPQwM2zIF+SXxokbmjL/adboTAqPY/ZCGliUkNKk/NWiFruWjt/bLnVkitn+YG3q7afFvDz8zq+ YFYsM79J3eRVkg3lS+kTOIcBC2GxyybIsUdU1TNEbimuVDkNM1f68GQYWQeE7P6ArmH23bRRVyA2 KVWiLS3BS5Wcr1Q7Gv7HWulk9iLRtw2jadapO3fZ5137ySeYbFvQ46IuEbGfi7TMOkESIGKcj2ml 0KszrIX3E5SiI2d4X/sjlUE4YjuGpVPcUjJ+lXFhh2Q3Zmm46f2a83QYYy1aGyxSXFu4DtvYfzpv R5HXIlrrxoK8y9fl621IWPAVyjW5hVKDfjH9wYfp122sV+fMhmDA1fWdk0MldiclzV83JR0vTw+Z S9g90zk6RDPsMf/NKGopdfYhhiPtqUY2eH3xguRTb6rYF52gkV15fwGjszO4OEksfI1DbxAa6jDJ 5IFouaVvl0vs/SOyJSLK4H/Uv39nxlfElmTlIqFXsxjA+lAIHphSgLe3ORRC7IpnTVucqALBAF7u lT0HGsVwL7kJkjAMRV+V41KABUpHS6N4Upw0HlsSljl5YlVXXQwjdeZsS59WT2Us2EDI8Zm9AR2/ wozFdIi1p4cH6/uoea0LRdN0ATWe36QHOneNSIozkHvNga7FTmkrNyQTK+vxB7snNJl16iPpZiq0 bqIA78CLGejjz9QVgm8m6fTjElXgrpBkSpDoApSpVeNdi70mHchmj/0YwJ7ubGRT97lf8DRsSn2q QdKsofuIrAdTySp7WF7yCH8i7mRB/EtdAH0eGaDA/txqQa+9uKlzXqiXL3s5+4+gcafiEFQMWe0X GsFpz1WlOIhcyZIchupgr3Vdc+Sr0OL+3SFGRG8ZWUkm8g/jeW3Q0JjUbyOj5nTTa5Xv/5sWAe3R TDW6w7Xk4mVzFGXPlDGg0hTYrvKIsgglLzmnud+EoF1+OiChdvKL2tyQB+KbNGYODVVWq8EtmFAr ckqZpnMv7wWB9ouBZfcneeJQ4zPxlH6dVhLHadcZxV6PNp1ryU20oRoYPD+kvj2FDhH+96dBBHga 6YGtaQUQ6Go5/Wl4OUSYCMYe9QwNm2y6CJsoL/ub23rhDAoNbxxE2JePDNjSzLxbSvgTNzgib/gV 7gg9wF+Zm3QykX9Ubibz70z4vVaiEMyAbB/QJe6yKdhHRbCs/SpjYWFm5l25kf4LYOrGhhP8T+vD 8Ji6NTosxRgraONQJBk+KPHGOtPV1Z5UtpezME0vDn6s1Ze+PMa6zzNc84RNKvdl8kUn6LMga6Ng ubV4HA/+6xzg9WxZSJ6//HKAf0Nn8EBONbAVWgN1IbAtBqBNci8/rCfAaGEUq9Zyal1MhWlLJoDH l1A5S52AOXiBgocHh4dNjt2sWbydSaTmj4DVufhWxW2NCEoC9S0GdwqxXeravzr9ZeHdh+oZ5HNR 9XnRLsSQSOIsgAQ8Zx5xXvr4ywqPEcjLKDkYvyVdM5262RIVsfL4D6D8jWz+ZjSZUXqTea9eYDvl swbdVTBlbFrJEIj31IUO2DtyZdbEmKjh0z3eNuK3vc80IGeUj17B8h/X7c52Gzt+NUseOXOtAvo1 fF5H0++srhUvgviJHSJ9jRBZjkLPJyKNjRSDhgKUXOjk9W0YDugrMu6sblKjONuxUtA2Cyel8Ag8 E1rq+gH0Ty/eJodLLe85kRbehJ0XPCUtbaUXIsjtKjQpDzvMbxckzplwVgPjbHZgx0SYYS97yvo9 1S3hSoYuDngqTUId50jwQMP3F4q30upjM0Tn4Fsz+PUE+2z0QuHRjRTSt69vX8gQPjuVvwMCu3oU Q26gKuP8sRkVG51VpaNmQhF+lKATWSti4RQmeL3pMn9niU2JGoG06KO1IC7u4XmyW9PQwjg8tja6 K/gbkYSiN3slOhTLta3esvHk+G8CV8G2w4gU4JsQ+yTH5sSuNFAkSiNB37Ip7rudTBg3AO1tho1B Y2UzDk2MetukcGxk8CEDA3sPiVzpCECACoWWlB2+KRtYyPCx9tuH+P8NQlmnYzP/w5dSujS4B/It sA7VcbLLlzNrhSPJMIMg/1xfz4neX05hDcIsckN00Am7qyVbcB5Hx+2nnAkOwda8/tBtO/oP0YQS FwfD5VNPxQIKh+jMX3msP7lqu1jokfASrxdM/AoV91gJ3u9tYzQ+X2IwCHbGQaA6DVBiOxMNNh+L 0azQlaeZ48E3CRUBeWaNjB0lXf6kdVUUfiSJlgK5GkP3078VHckAqYbJ8wOpWTnBp8gAZ2h/xnie 25id93u5XYkNui6d6FT7gB9yO2GFP6o4HduNhW1chYVOVYr1d4s/04xHElWxFZulpJeJEyNKAHPE nKAzK1dhB+Wxoj4U0bbnbBaaVhtKJ5p4ksCFhSXWerx14XxtrhxdlR4Wv8BW4pbj7x/S3aGY95f5 Ft+jMKWpks9Bw5iI/5vVS40XHOVVfikYnJLcqdxSBpH/7QoS+toOUSeakcQxPiqtkDcexU51NWxB 1L1Dv3KSoNO4tm9yrfRBfzd2Q22YDmVNSisqyzIogy0t1qeEL0fQYZ2Ksfv758Mk2mp2q6rpKafy N4dsZ3Y/0syJZRXjEd9Kl1y2CzJYlhTt1YCcHdUdz7pR0kZXtJybuFSbFfPPMVC/cxrI9tYAgz7a +5X/eCArxLcqEtIzT+/Uzz5oAICFugOK4+2G9khnwdJ0HrkPLidQ334VWHnnfifJlbDXtryI3qch XNN0W2S3+uI0d0LOByalcK/hC2v/YD3kjB6hBr+pIOoWzKzG03BXPyksbnlHZRU3fvZdXIIur92a YXCUzV0fbqbZZ0mRqLGeZMfm543LwygmddpYys/54IfxqVcg/T6Hy204jezy2huObQthnLTNGUgC 7DaQvFV555hSCS2JGjecNi/UszcKcLfCpxibrcLbH4Teu65tyKtL0xloxwc3IA+NYF4pWosJXXf0 BZyoLwR7JnFPsVvuZjnrsAvzj0Kl63i6QN/JoBilfPDGMAZIj0q97nYpPZcf98O3QbLGw2ovJQtR eheHfK930LK6ta9FHub/llUb7aBOkpvq4NkSrhC57wT/g/54FzwX/XEgJY15t7HOdWbk6Q9988pa 0/XysKHy0fuSnxxeHC7u0Q2vlILzieXFRfS9gWOy5CR99eeTXxcAZAP/IEQuoqyPBdJTNg+4kguf JCo4SrJWcPoXFOgAuiNxXGgb0lZC/V3IhdQD0MCf64JsDgBRhSS3ujIALCw5rB8d1vTmZK4DGmbS derAqgSdwvUZTyHKqC8cNRMXMn8gtbzz+dA/o2JbhxTKsqMYepaVQwET1ss2xQWLw5fstwEFc82p 4a8R5VeIiS2AoZJLPagO5jsidcrgsBVZu8HM97QpEyHrw8kiD+/bTZgoY57bcJdzf2HA+W4RYVqB ALlYtAe8ZEYU9dTuiBdaofR7Fm38L1cmKyq2suJYdF3iCpUikMb31j6Z15m/gDcehY3VLGZ0T/ic DLwyu9kWWe9xoEN0ODNM2vicezjLwmVEMPs12/Sq7ERo/j61TztO0DEfdWxUxdECoCnspFAR3Q5E i/RhLC/R3yakHtlbcKgOxyscPWCv5puSPAWkdXx9uNEDSZTKAggEvb+WKV/fWGaQrv7YbOvJeVTN pKDPYSgiisNrlLsmg6wWBWmuHqD6LXtKEmrRrT8aH0mt95Dm4mOobEt8EVHsIap1ipX7sk+FsS9V Dw/Ktcy8nIb5BNCXadyucfTcohH6kDiSraZ+SrE5gihdeViQjUnez5KKhHX66OYdCqJ34TArN/Je Pm9sL7u9uTaTtCXeWky+eAFSslMLyl3n8plfFOIMOrQKBvSBeLEE7PhjNwnL8bjjnGuRFV2OUJOH fcUzUjRAbJelP5nD0ijyO2q71piVESm5VFl04wv/jCPjyMXYJU5AgXp6qrBXze0IjBXG3kaS+OeM dpLx4KvAbBTutF+5oH3Ok+s8pNbzVK3pekFaNu+fy0K53w+2yv6axtm3DwhxDRMt2O8T7uR6YNzF j14uRh8oo0IaYKHFhA8HGxtT8rY9CGARJh6kyLAhqzz3AoYcaDrSQKE/cegbRpAJSUepohk3stYM YZ9ftQ59JBjChYYTEN6AOAJesvIGjtcZb5EdzDSi/fhNiujikl/Y7pHUfE9J6t1jRJ9G8e/ia6NQ 2C19ZmBd20eE50pziECHS9RJe9vUONP3jks4hHTFiCV5y1efA6Tcr8Y1La7qQ1M10w9TCQrN8ppl XUEtPbhywIOgUOo85R2VDwu98WMhHHoKYzanzrpF5rFortPFiRn/N+l4AmZ/dhg0RbphipnPRDyP 3GwKsAmS+a5uo90ouQiQcDc2g2SED8cu1elCzslvW8i/wOD8G1bKp01AmIQp4y+LdKBTsM6gqK79 hU8jIYkiCqFNY9FTI+35hTHKKm1KmHA0XCnkGM4i1Rn8nzrzR9jatUcFv2v8brYxC5wpNksknl1m MHTEjNRddrKJzcu2HDqrNNPvHtXd3tlZmrQnIv0oZzuyAXYjhL7kgvYv73tR+1py4zL2/OCXqlwS /U5jwe5j3WVi2p9S4p7QsAjPiJUVds/m1ctXjJ+SbBW8x6e2KBGJTUpsySh1dvm3rCEMytrqGmlW S8mSRFfwF77tQItZtOGYAunz4/HTzg9NJqWetWS7/Klo/yYM+z3H0SfXGtZH0g5b1u7qw0BcUR9I 5qRb7XoZHM5matj3mxSnuvif8N/mo5ZzX3irqpPTnk6iJSwp0hxgdhPCvWIZW2HjPnBuRcgIU8dK /WPvozxttfzk4oMfMmtVI46qsM4AA7M9vZAvvb+wcccGzdinc1Gsp3QJWbI63L/QV0BdITebxMb1 hi25wkJAaVdzTNg5tLYtluJz0BkZZvpkPihvPIyCk8sroz6c67gXQGBxuJPIV70ofMo61OyoB3Wj r4bWi7d7O47hnjMEM9xtxSmcarIhJQ1VuhRLyTbcLebj2iX7MN+Ldx0Pwl8kaPNJ5JuFD9wjNNCG YBBGWKLs+ljbK0t2YktgRczBS9K5SfR1clSE1Vup/tMOzfVTsjhfCGvFVd93LrscB5n/8uk7DKo8 EtpCfBlcKutw1/wZPlaUHGZkBLXUqTzcsB3/FikGeTzB4sA02O4M9SmO1lhcCpGRLuJ2z0oGaxQB WRK9oYqYLdrg847r3bY/YWh5J11OiGq+QSar+XudM1UJvtOn2mWCLdnlgNkxS0+dfiipxT7FIAt0 Ieq6kOescopVmRnygX5YYehR3AmSBCZprSGC/kPBJs099jwfwZ97hE4AlqRf5KlxtXO7rnQtMkun VH56cwuQjx8qN4MKkrZJw07aS43FW5racnBeWfXbh1s3TCh5OeSwm8Fznk2gSr/XmaWgdTcQRuZx YUjncSmSXc4pHR1cl647SghmVahJtP+9CIbYpF5jv155Pci4nKrypnBu97OrYHxPsfHqehrgmtpz mFcgbhdhxL81xcjXSgkp11Mc58a9bAUdht2QGiFquStc4yyZdn1Y6zZNIjXPDVJVKeeK2BNl1xzy Cf1g811qVoVx2CYXNtkh2DHPr3713/ekmLEXDOHUvsUMU5PyDLxVzFEuxGIDr/23UFmkjbAJNkXL kUMdT7utZQhspMr3UCghgijv2v0q1klanfsoiPSHSphWba1dWwF3ymtzTd5c/q8iDdWQPKeUZlH3 foI6EFTWg9mH3/cmXALf/NjMEmCx11KYRqUZQKRCZSugWhjiXK9jbAhjaWGQkgQiJA1wfkPBHTjX /54FfoFxhgqIMw9pw/EWV+co9ynAJk5H25oAT6jcAKqTxJ7Q/aadHvR5h/T+Za1iYxnDGuem6Yb7 +jjJ8NtfcbEF+HWTbTalfslMCJoE3iezn//fEOA5Catvbat5e66QNbOcP+5KinrFaa1/+RKJh1RP KUUVyR8NJIhBEFy7ZX9pQ6NIEtw+slSLjopnqit19vYhrvWIbtyL2BFDy1C1Km0NFOurEba9n1f2 7XuVdkVIHfK/sf8iDFFhEJS16kAPg/BHnKdoYdhjL246i4xkzQ72R6qMGVCTrSzM12UqXYuxEqmw k9iSfYNs2Lt3lpTbreJqZAwrzP3gQVK71ujDFu5leYiibn8KnH2uk9c2z+07tIQP1Qj0CZn5H83M TgQYQO9dKzRwKE5k4yJ9GqptqTjE288eNjztjbbN3bS89yabVlpmx4S7+KWwHsBCFp3HZAjHsSOT cuZRH/RBlgPtb3FJ/PdIHWG93InAX4RTJ0vQ8J+8S1jn7FPhRKPK7eVWN2xB4d6Hhnr9NjwW9mew 42rEBM10ZjPJZYDZs3Bbhw9GYCszG6cUbvkaX9pbWg2/UdPYEKGj7z2xmzs9fdAkLMER7Ux9rnI6 cRw70SVAlWaLaLXJCpXtxkCNZwl4pbJuDnRkpMwDbM5zMlPhOGPhrK+PwPtz73eHe3beXUDXQhO5 qnptmwZLCMmkRrSkmePA1sTyoaRNmBWYqTVzB6+kK9yAl9KXKO0b4cPszUGpW90kC2dn+nv0eiz/ AXJ1xhYzzfQCz6f7qOSjf2xZQXadSz9g4Gt80lgLLvkvy6tIynFfR70ZZbPU7SoJnkl6JBLreXa/ 1RG0RAZDK/7VU+FC2n5W9Lw4xK0EnryJb93j8Noo1X0M7i2pBtlFyA42LQtKGipMqrlwdTWCGInY 21ciYOhI70gdcIHBVS7YlrPWVWsATGTPJW91nWlRCMkXJrOSS0QEqF7rhsjZh8NiuTw75JRdvcrc 0C1rTwkkf8oHLnSQaXATeNNtytVE+1mPN4J3hXF2/wmgbR1zeEegKJIWLmSe8nbZoM3bMWs9p084 LLBC0BKeT4jjoihooAk8p+Q7TmsAL/GfyVDAza8IGBzq+bS05cfwbNbb2dmS0KhWLOBtUUAMt1Wa wKITtUrAtlAvHYypbwaiHMjPD0GjrUkWuozcH00mXtJ8R/e0BneqyVUma9OlkQe2VnP8/dXawEbZ u6P9QCTUendhcUqmItOzFHZ1Ynw9cJZ4vYs0rxU1Ybr/2JIf1gxxJt8vjw9+ntadZ/9EYtscINsH fOMJcXeDXaJXnJ6GN66/hrG0SJrKjCLjD11xXSBheJhlLwEfJBzG9k8gPPp2B6KSkhtMR0zske6N KleGGVwXYb4TafbdK6P6PfszfCcSde9z5EQQTavFwR2jiT5+RddJrjwg7JGBbXCHgDp+Yqo2Oqbk v3+P7iJyaV9RbKTHrW2yJ6hVq1D1UUdHfafc+giYkvJuysyuCR7gssNiQW6FWYWJhWCu1YNnYsi6 LhAnOTS2rw5CfQ4Is9jM1EaICUZkrBKSn1GLKre/5so= `protect end_protected

gpl-2.0

53e854c8ffde7303a6c1ba19734e3544

keith-epidev/VHDL-lib

top/lab_1/part_5/top.vhd

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 06.03.2014 15:08:57 -- Design Name: -- Module Name: top - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; use work.VHDL_lib.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity top is Port ( gclk : in STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0)); end top; architecture Behavioral of top is signal timer: std_logic_vector(13 downto 0); signal timer_c: std_logic_vector(13 downto 0); signal state: std_logic := '0'; signal clk: std_logic; signal duty: std_logic_vector(13 downto 0):=(others=>'0'); signal led_state: std_logic; component clk_base is port ( clk_100MHz : in STD_LOGIC; clk_250MHz : out STD_LOGIC; locked : out STD_LOGIC ); end component; begin leds(7 downto 1) <= (others=>led_state); fastclk: clk_base port map(gclk,clk,leds(0)); pwm1: pwm generic map(width=>14,size=>11180) port map(clk,duty,led_state); process(clk) begin if(clk'event and clk='1')then timer <= timer +1; if(timer > 11180)then if(state = '0')then duty <= duty + 1; else duty <= duty - 1; end if; timer <= (others=>'0'); timer_c <= timer_c+1; end if; if(timer_c > 11180)then timer_c <= (others=>'0'); state <= not (state); end if; end if; end process; end Behavioral;

gpl-2.0

7f090af4b21a47d54d51727f4f940fc8

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fir/fir_compiler_v7_1/hdl/transpose_decimation.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block h41zIa1oubvQSX7GMKR3gHVWSq2muia7G06PkbHRXutHecugWWiyDKE1Ut0ZHQN/bnPJs9UEuy83 +Yr68xDYaA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k8RaKiiq/FkPn78YtEx5V6yKNvZI88A30BkOqwsMNi9pxENsxXAHnJQYfEaa3QpbaoWjwodsrfy8 UA36ofihz8TbKLirLENvUtRksEcSgf5KDXn2f71KoMA68/jaXq3rAIvQrf1aUWWDl3o/JvAO0swm +EA6JZnSyrAU7/MrwW8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block L3dr1sJUQLLSk2kwg0FlP2EQ3Yi3ITcyOVpTP16TCWJsboinw0I+leKt1HEecnBF1NbmIaq+Eyt/ JiHXqiIRHXIbbTwz5591bAzeu0taAqc/hvSJH25G2WG2KbbS7klm2ImpkhOkkw+B4JNoWKpcMN1Z B5XKveanUBA2zxd/DsnX6tcj8WZa4GNs4Cal6d4e8OpsXNsrnJHm0BHCLNeMoudQCUg6LnNCCRnU TfvpUSNz9U3uq+HvrviA0v98tPXjvTpyHzldY68RntsIpZG9JCAAymnnmQxRfhdbDokO1E3Afkjl L8xRrXo9IVOa1QSuI6Q0sfOB+rYq8N+9h5hRZA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NweAXwIjygYcbD2afga5a7xq0AfM3YlzJiKsYfQOM+w7nKRrtBkz27YID0F/20eW0kHZw8OgVZWM wulKDbz6EpSU3R7umBR1Kc2nSi5ldD5cTxIokurpKVTFai2MmHov8Hgkuhq/nwvMsgiXIGHy/WWV 9z4lJvpZKwUy7b6mlxc= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block dlwcv4kbaqSpIRKsBaamZYZWr+K1oMTxXo2LTDJTxy2Te6K41nOwJDLAEnznH/AhnqOo9Nj6UUgD TwZY6MP0DUwGlM+yDY+mqgF1ZPzxqlKcE7+8gkQb2ttGdSM4JsmicjmkYx4etRnO3lMZ7UolFrSw drD8tKumGNyfHOg6jwr9/H5CMlz7RjFiAdL3eKeM3oQ+B2BIY586HtJE0Lq5NGtnRCoVDdncUiyn QdkMsH++F8PaUrio9m6DSah3Li6Y/LLWz3SC5lMXbzVjrytxfSgpqRhSkLQ6Gce5sUTHuvcn7kHR ynX11+gQavd+PGjm7YA5O1nhJ7KNk2HH0MbU+Q== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 110768) `protect data_block LYomn4AcmK7FCnFYsR0tGvxBxxGBSW7WxPSGubz9LF56MtI8ZwOILNkq+WdHqXrZW8HCkvJUB3u8 CCLUsRo3P3zEmxxl+jr70IAZCBUGIvRUo8feeIJReVP7HwpkyjVcRqPGQZmxrZqEPe9FqMy64k/C oyFWRsWcwJ1iFkfxQXsltUrekz/K7SOETEwsveipM10vByXtnVvVHdfTdoUVhysOasulakc/LYTN PW3syZVNRs3mIkeMlvabEzaQh97soH2GE2WSU5+PVMpsx/6GJnKj4yJiEhiv+MUuFkxOGu+k7dQZ 0jCki2q+twSt0Z0Bxqu1YydXkqCR3RKZFInkOFoVaZW4hI8fKQd18KeyLUcItiYXaWAtkJhpXo8I JT6/wTNGhrIptFGAGsNmP/FgpF1y+EM01tUJVyHET//Bum6bBns0Rv/2e+/QLF6JVKa+ev61DaG7 ERltUgzpZ+h9JjIDwU4E6xcmLalTO9yd+UhmNyOHXeZmuNLOQmcApjSPUCDhZDI/kIv4TKpkZGs4 a9QN+HuNnABdMt2HqI+/SnzZweO80478cn/SSMA3Fi7104tzVXG0pD1ROPnfd57cG9mYYk68DVb7 PmqNK2YLa+db1dB/FxMMkNJVLI5++4/XaPhS9bOmhp8yKE6A0v6UX9DqCbN3YupvImwAzT8Lumpu O7MehDw24zCOQIzdw8cgxiR0ssXWPBMTzY9WnpGhvEl9i88NokPwzcFq9+NBF4s7H4g6lG//lN6a z4NXhtXrq2eKd9dNxFOndpMBz0XwH4wwuqmcKsrpajuJcsfewDa84umRcLFBDHDUoIO9T3bZMU+v n/C990uRsJBmyVAywkl6uR2FdGO6z62p+fDg8P6BKPmwHZmG5VEYYJEsQK1ZK6SzPMlJOQi94G4Q SKUMbNW3UakkERghjn80euXr7MRbFmBo7tuZWsQfOQepEg6//CHAqBsX3wW9tpC79YDFlL/iGymJ GRLAyWpq75KPruBJGA0Hsk68nfNp6aphbY2x3eodOt2QHXXN9IH+/V7AgPzmMvV2kAHw2dnw3MzJ reoiXJjG3JN2vr7hdzvW6s9C/6v5RJ9b2ywJfhVBly382JWYgQ5ojxFsw4bpg9xzKIYVkbpFI371 bCx3Sw8AZXXlN+rRTj2chPv7Mi/qevj8WeaHS0Pm5YrZJbMfBzZ+W6ZH5LkHs3bD5Qg5EiI8mrmN aZxxiiRaMDsxQWJiJaU6VnWLq84+4cHR5gML0OSe/tkGELFm/jbPSy3tiTzrga73mhIfFP/fsyD3 zKfE5bnS/h3uL7LHN1KhRhkY8qb3ML5Pdi6jwSytC9KKYoEhTYcBVvLnsC7qhgSYENN3VM/kv+6G JzucxnM4wYBtOPvc8hr+5HxfZ+A4X/kaGQ55wM/9v98ckxwr2TTYSGYZS6XPi+N9RuYgz4JCQe46 txpiVPqK0lVMnqJqhIun3um76cevYIfZnbF0LS3p2rBk+Q2vI+xZd/JpETY0Vhc40H8j8+b9WpkN y1xNxVFT1/djBHle1q7EG0f8TVxaFjNh5VX7uDDQZB5Rmaby0eLqUyI8cnX3hY86CorX17nC5D7R Q2nSBtEPV+puxL83SWYrSsysf4q/p5gK2XTg89CQcQAPARP6eOsu74QIpU2qacCV2+or0H2Z5IGe YlWLQezYZB0bt/jsB6hJIYcXYKZ1kHf7x9qe3uICrjREoM4UPWiKw3cI02QBJX8VK9k2SEkSHPMF K3Zftkvb3L5hx6gJDwz9wLWtd5NGaNb22DqNdENpCCsHPgcJBvlcX2HvzYPSrL3jxK4URrm2hsmb L4p8E36yQAISYyn16385V7stGG3nqQ5vrAq0ThqayGt8offnpnyrFVxIg0QViovLev5+9m83rM51 FCeMYsesbDAAQfSdHsrkRmBGwbf0zX4YLGO+KKs1GlqPxjRM78ev4qoCklkwG3bnJDOwWgcZ9Dv6 P41yby60GM+bQjROpVRsTDYGehVzBALhSOjNHOT/WylfmieQa+k36tOeU0yviIjJ0rcpBFak7IRY XUIHoPk2G4r1X6Tx8PnTkDmTYaEMI88j3kg+1d/Pt+HEhE2o6+df+aEKU8epddG7u9lWuXhAcNJ6 SuG8xpCtOnGwtF0olQQRLPoIkKXHgjMZ8R4Ptgpe0d8h9xuxMZ1ptc2i7T1dKGVahw6JpaVaspvv AnWenVEQLLM1JgEXDkAPfEM5YrnN20IrM1Tvbzang12VQriyBzjc3HIpR1PGb0O5EyBLqbTPR9M+ WD8N8FGB1AEbTA8g5hn0WKOXtt4jRnpPMHOKf0k5XJL8uQ+4GDh/KSphR1NGl/bLTdShZ6fMhCOn SQfSHDP8oU9tJU/XyZG27vJYHikwKdVcLQxYu4ouiVTDGzwChsekYt7Svz8GytFW37+OtlnSCLM8 7KRgWTZCSlhs8YiU2thrZAKU/Uj9O2lsYHzKUn+z8kymCfpr/HMxSYUDBCbkbjmpBZwwTGyPgbnT AI3YALR8vOBz3H0YNkRSazdwtWwL0B/B5NlCekVw1wZLJShlmBW4Y7uXo7rfITa5pAdP/ftcPF/y 4Ga/P9BkEkVrMO6DemzEKZYqo1e+FXcTeRaBRXp9TcBRl1CEkrjCSHviRjXQgRIXRoqdoIXqGcW5 f9huypHhLK9GISbsWUde9gONULjh6fUqhuMcokabwCOVK0KnWXJW20L7OHbr4r6KqI8+8PvRSObI dRPVcK913/lGz/ELKA+2mJZbc76C5HxgzlZX7xjT5IA+hAtaTds1S9Hy1LKh9WOFraC8PuGTF1Nl 2puQY/kMFuhsOBZURudRysu8a5+Pq5Q2ecnUFbE4kAMBX+lZM7GRovLN96bdan8dp9UC7nD3OFoA 9V+uXg6phOuki7oRuvOdSZzAd4tMgwA6qdfoYhgCT/hF/HuYCHN/MbDpl9oPAIRO5o0+B2LUA8zS Hpka8B/ktGbUHU1z+kzXaKkyucpz9YtdaIHhNVHiHaYplsPmF+8eVuYkv/HtIuQMHEcLreR23DlY w/qQ95Em2NfiylpVcbWqB3ghNwZB2EiSFF030yfflXgQbKi3VAzgJi3eiek+E35rve1Cdp5aaC76 9TvdHEBHzl7wGdHn/zWCLt/t0GEZhvZutLX0ljqOKzGAGhFN5amO9bQwDMoXlNMqnbuxOCcf7XkZ Z2qhHc44jzHkPAAi/+zfA/Wf5T+3/mas3xJP8Yr+eD+fckKt4tzZMZv+sTtWTYLHuN5O+Sr9NWJv tyP4UEL1HP30ogzSA/a1AHgIM/EbksZ7hBMoD77gZ1rgtshAKsGa9VxC4/6i4X0dGRM/+3TfQhYJ byK4pCHRk/Dn/tRxQKIHlvs1OxAC+mgqxANA0P5fERyo8p+3vtewkR6P3efv3G978laBUrIULJu7 jdGWeNUgskVg1b4BbEp2JFxtvFsRyMr2U09qu+FqSJSbeyTg26Q3TlQGKHWdh8MYlOSH8fpSa61B tEBT7l6ti0Bbha2soO0xjphsIvoAXsNlZ7y5LLqO3tG5pKZqx+DVKXAIYi+LXWoRmZrC2KCG12Oz DqUA9Jpl/w1sPumBGBPQ/Wr3/yO845zl1s7phhbtOxKnR5+zh93Wg28dQ3LDrCjVqogAOYxRE+aD Ax/0ALSXTyS558yui0NbJTm/f9biWYsPEjH4nCPYyoFdIMhMdRXsW3CigFqE1cKPyg3u8PIIZm98 Wu7IOHl6PJp1ICDvKaD2rYdNSVubo44vNwjXWUbRkAAmL92bBSi/3ChFNiXu88uWvkJsmPgvADcc ZwEYlgY45FLGYPLld5pvzJEulapMpjoszXkvTgeCUeoKSotVWoMpZeZ7sZxaLfKfiBz1B55s02eA RZaGFlydEM9pQElhqkhJtkiubsQPTvVNJ5qrqF4attcnyWpgLvOO9X2ZQsdSPYRbIWvmXbBDaFzP wTL4zxhqUcjACwti3FQPlh0Xq0pIeasaFEkfmcqkHn2gtGDJCkaVWB/8M1PcEpyXeT9QIzNgSN3e T+l098ZQcWelkPakRYHaxcMtH5gXa95L1SLm2aQlGiKcU8ysTi4fdKLMBlAfeB4NJBSFkERxChl9 YmVT/6sMVoIAwfC0HXGhZ5nl7d++AbK20jf3kpioiu/VTf3voA6qFqL8XnaazwNvVKLJnB5ddagb vc+K3wO8h3MnmiLCdUfT/aPTEBLgRcY7xV9xn/oWKV56UtfaxnQMjoWhs681OTVLwA9buDIzkrgi ArWboBSisf7ftoX6d1NXsox9bis8NfmVNkK9BYvWbox36Ok47TyMnJaNt0nbDEujpcfWYnVV4h6O jMKGuLZJM29V9Ocyf19OVsHDFB4vIVS6oEs7J7hmYmueUonR0rgHJU4FNAl2xC0TwUgJGoYxiQJ0 7FJpI2ew/D4Vd/WmWmmCWcap4T+d4SvwMtKIX2pZRNoXIxymggHtQitDxqoObmh1YDsrczVNbmzp 7LtZGLZXGJ7Dcs8HEKPSkCMIOhKBYVlAIXtRtuhzeVpWpznYImySDXdRovyOxUd/tX0AZgVsKTKQ hcj2AiLvtdUYzpcC2hqcfCMxWdFDVhF59IoHfoIiAfgRYaeCRVRjuuv/TK0Haj7fSQIZS35JAYDe QVGiw4H6NqigjXn+mRScHYs0J3CIHkL0aWKM0CQXCi2Bj7T24vQ0zL4WkGJcuh8jmW4hsPDCxMj/ SzDRXn21qBpE5qb6IcDJx/4lQsN+dZ/8qce+ZpZw93vlIyiYHWoBYTzpVLYvkqk6w8QQC7iXdYGe YfIio4Kzgk7biGequOWsGMQggo2G+YCF4n6vzA/5oBfbqqF5iTu0zA3R4r6fwDB/r1v2cjmpoAeM Err+PFq/TtvaeRFdD+NYVZszPOiXapcYLHGgYwdXXSKlMpd+kofqmF8lAaL2yufolDAK3G0H5trH UMRz4c8aZBgE4OjjNtlPkfBPJBvo+uSHEZEXCIJaU7yIqGrzp1nwCWXWsIlGweXE/riS2gp31peB dTHFxkCYx6mfgdQ3ro22J83MepzLTI8H6PfBiA76a47Uy9l4vq5qU2LY3DGNHHDUG1UHCt69Y44o nxprTsTnM/tRBvQBWqlmENRiqajF+hiVnCveAUB10UfGDx8GqQW50K6gMu0bFZ5Sk/neTqc52nHx DsLAqboNvt49Ra7eJnCJHaY+LSRVIFTflyINTMCBq2L9p2WUAnrwL1hbq/p7YwuXlPWdSGkfCWze x6GQ/XQnaPhX8p9It0Zw34mwyW4QWImnPRxPdyqAR79bUhT58i862RuZJfx+HTiVkPdiBvmEfU8y hmiHxeM9nAL6WOTu3Tv4EFLtlW7jm9okdbY+a/TVTIPG3+CqEkKSJv2riW/b8xqW1SbND1vpN2xU EpuB+m1JjFbVKD0Jp9c8cuiJxWgGY8WD5CaloEiPZfEdToufpQH+w1jwX4fFSZHXqph971SSeZtu W5KywuHRIarOhEOzHvYu4KHbstukkh7VVcFNuKCbNU4k/XnGlz5EI5hQt+/sRNhWSZ6Czx4wQ/mx z4emoKCeHWmmMZMVo14KrC9RwqVewzUkufJRk41u6v5IYd5xB/PzFtJvJYmahmIDdZrWSFy1uuNs j82FZUkpjLZBkDKd8vdMJYPFbruXbucxCSe6iVcO2ssrjDg8JlPD48CpfkxgFxmxDU8jSbEa1JNk AYLiiKPsXf2wr6xlMUVvw5/VLbCXEFdUSpNI/PHVjO3hjGNXhrFVAho4IHbMB62nk1XCEcbjX/jb oDjBTCC2kn+l/vCA83b3C8vm73Qxijc96DiWkGgX7LiRTTegDfv+OxjMHAv6ty/IlRwbfsb+Pxts P+jJdqYMZE/wRpx0xjFC8jPPbaz9LrEQqIsP72PcZN/6BnAOvwX4zVpbGfmVUfDIS5K4K+deaYxV JfySmWzG5bLwXBldsIcudWJDAuCggKR47AcNwxVwlNxPxF0NpetPJ+i3d17sgyyLNRdLwMmbgpJP /9TboEtdHAikuiAh5SneR7Uv+COyjQs7TEcRO+5bKgY6b8RAtGpPu40nE0du6d5yiI3e4NTZY5Tv GsgzD2wvIde1I7oeq2Jk51NmWxwklt4/q0C+t7xvUDrW4Orps7eUEimH42V2QVVnBC6CpNa2TRUj bIexCRmnTnm5Fc4eOSsv4R/YrjzqjuKD/J7yW5xWL7tGzJHn9pv4DECjM0ChV6+uuHkrgGTknqRR pKtPqyNNU3Cf3wjGv6v6u56HtrIqKE53pUsGQ7LVuA6/+4G9iEhn0MxS8JVHVWY+RvS8ECuth3NF uIgm2GvUfKZrI5+UjLeqwn6S86zj9ou9HGTerSukfMJXBPUhMMcpPLbrhZ9MGc9qloZm2fk5IzQ0 hHSL1VV9BXSpgdPZpi+5azJCt9LkpO49xR/JFmzp/dQP9+6upI7hEStkgap2PcMvc1bcL/+04ULS CORXmp2FrDML3h82FXbvU7auinmrG5Q7uJvANIzNTluw9TAfedmwT4E5ZTEresGm9uRIAg7FevRB q8RQXBB6hdaqg2sC1obDTAOmbo4wQwHH3gfoE72ct0VKIxydMFmxsHy2CQf5hb349PLm+xmYyI8j 9k1aHPqURtZs/re8IMSKkCyvC4H2tEPKhkWOvkWi4MFphXxfKyG0+xZ369GTNlkJHyQiC9ZKvdZ2 QoDAm/qS1WYutOn+IA5K8pqj73+BqHNeuBV0nTZLb9+i2sNyMzJr/YfwwIfefhDYRwhbI77Qh8wP TkEDqiWuA6eioc9covG94gL37f8dKdKR6SINtaTKpm43a5vF508a6TjoLTxflXUQmEYOO3g5vO4i iv6B3nGYzq8QnBUombQYtftvzVCHFrK/c3364Fh5KF++tNBRdOjQzyXd72c7orQOQuo7bu6sRFkQ 4E/r+wwZOzy/eVd4TFq3OUUNZt9AdyubulHbFq2RredwTPZdq1WZ/3oMRb8IXmzYthMIFtXOk/1V G1K6X5o2GwGJk+q/4S+feLWAkh319+u4JIv0F2tRSAgoVH7Nr0SlmQA3kj1naah6W3HmZwJ/sEoS airoI+E7p6dZgTku43XlqXFdUs6e1Zx1odypjIqQvObJEkDOu/1Q6zgYD6t+fzoezS+B/7Z/Qryd oFm8rPF6PdGdFiijQ1w6Y8h/GUM0wlSjxU33u/lCyZF8zKLT9bVoHhOQ0ZVP1viu2hdysfLjrRO6 pMpRkggaCtzLNPsGGwEb7W6pbhE62MT1yptSIjgY/LaiV5pqdRQR4li1MQbkpBT63Ev7bKBWDN0z UQLZSPIgY/KFCjDI61dTnRexlInKgdEQaG/LiTlVSqS7g9uZd6KInf68ImvTtpxzs2IEtZ2acgAK rDbqccxcrfQ9jK2p6JzS7+OUhHSrBUJsvrpIN2hFrffp4RNxEpQX7Lucp8ZC+zExEv0AUPnu6olK UBscaPmxDP/r+QAyuJ3otH+1ZfPvvC8B8KatJcEQo+YgNky6+COX6XaE7nIufze2O8H/NZ/gvWUX owYftKOJWLREbtre+00suDbB+AoWfnOB8xPLbI/rcOdxg9zfufmtKvL1LqHnycYCBYc0MEazqvUO DDqPNlItOQ3+snV2jzRMbdHxNpsXFWE+38f//ue6TvspiqreQ75SS7jR/LTA7/eP9HsyYdjZIyJe IG1oAUdw5Cj+BEXiRBiM8GSwIgNzuimo1BvfY3Ym1/hiTjvaMaXLtDz/ajy4+QmF23jOd64bCxuJ R0bHwSK0LBeIRTgXXLbgNJs9r+WXCEMcDW4Ul6C8zvPd6uYf9f+elHC5PGAsbXrn/Z9dDqYSGLEL eAb0t7CQ2vxakZBAPlETXdN2MLbTVE/EMZeTxa3PJ19rd3xvTPSP68mQ39CrYDUp5c/Bic+uX7sm 8vENCA9IcW8Qj1Aj/vcDt+WgvyA2EiKLthPT49KX8Ana5vI9BwMEbfZVyX86qfNf7GgHFs0vgOky Cs/iSZoFmqnWmDP5GWJ8seT6Jw72kt1YVK7kUpjPkLO5nRTpdV4BbHGvy+W0OUYWnTh0mcoyaMfy mzfl3/dfWol7NmwKcetws0QYU/wmzb6l3y0K0rH6OgZcvtjWdB23Utexum+2DtQ5pfoko4AFt15b qK9mINALZunj9I8UWuwLsqBkYXSSj9hsBRNVIacvhluub0N+ih6+T3mRYpfcG1M7XBHrMF14IbEG icPWSPINzDaULDqHzV+kVMOB8n6UvuCjpJKLTdt8t0vZ0K+pq0kpDnWf2exxdCLcbhF/B+Kbqlnm 0PnCiXaO0v1ap80NQ4QKNPKaR7WmhwpyoGxTKZNUFfVjGg1g9Qoe+oclqe4kF2iRUdZ4kPuxVsvZ 5FBjiASVTDGRy5ni8f4y5izZjHLz7AOoLD0Umrhq96mUpmkxsglMxSvYj+yCyfa8XjfSewcJYP8R quE2jnyXDSp+7Eqtq/+USFIQR5KUrAGZgzV8Gb3NrnxqSHbFstLOC5+Yt/iRdkOwe4ypOgDr32vL yNQjnjQ7HqaEnz5Shg0y+T8HS1vaEOTX7XrAGQ7qG2//UJCsOVugEqwx0kj8F6HcF08KIKiTCehB 8AmBwltnrb50KXD21fe46gPChSf/QT5GP2STnyAUcciOYqiFegv6N232A6um9GhsfQx7iio3uHrv Tyo56DKO9qmlhH9hzPNc/amcY5q1UyuTufxBHz+sUMlxAVgXEu3qUfEzQAoIq6sU3VM7NB0EPZTa JsPx1H3TzZMg5AjwFZIlNx84ZEWgcCISxDB1kxLyMjNXZGNhzjZUr8eEApZGQrZJavDspP2ATPVT Om2AFFq3xJzhjNQztWWwwt8soaJ9/3Sa/LaYrkNm/f4ThY36O+hbkkYnrFe1H47WXFCdeUIUsC2u DzFxTf42Si3Ro3AskaM+9q/ON18M9h5uG88E/QgUiEeGqwI8iJKo9uE6MXSskK2I0eRZ8Vs2aCCh ituWqhiKqBL4hbaBdvPoVlGNd+s+/9nC781eBydHefkH1Vl5jbxpCPNflvpf1AboCPHd4Y6BijJ7 zNxGpFf8MOnW4cvTSLf0QrM5/6m8BtBQw5rl0zwEvo/GWBITM92/yQyfZK0qDVZ0yzBQnEA3xVkP lynh++NY4wAEQio2Gjybn8bo3mODwRxLGja2aILa5CuNF6kkN3Dnd1SJPY7W2SIw7r24sGBMvBkr zur++qu1DNnHGa8bLLP8RHA+1rym3Wxp3XMJO+0tRO8QlRr4+LewFrKEwJDGsMiU3AiRzUW2nt3E Lx5dlSvF2UbSbLRNyFj4douO87DoyCWnWIMd3mdDZe+P8cMFcoIMVC+T1y+iZ0dI1RIBjNxCBWY/ c0i8IP8X3rmLCjdRaRdWelYCXGUAmNTu/2qLubs53Sih2C0Nbgn+Si6f9FaSBNj53Usmusf7wx9t FMSbFIzoKS+A1D4DXktoqUgzSQ8I9DLfes0weNVrqRshi7kLl441wl4unVjs4t8g49jFvJIAjk42 UV2iom7OjyiUUcZsrGyGiIgTnilbP4JfaBiOYt4NWzo9OEeA+eEyqN7n26oazOYCRIoHlm07OpYz jdA9CicOWu3+m/uWGUt5pdMJptGK/85SzT8Ya2YfPejf3j+uCuE2SBlJxRCLi3/mkpOP4N7s6/17 z93EmtNNeMjjwxhhr3cdVL5G9EcbWY2PS7oh0423l5x0OT2A2IQ1tGX8ntuyAJWRui82R30vFS5L ODyn5GNnPCJT/L5HfvUDS0PSQ/g/X43UQMmMnbdOKrjgRPAfg/8vQWQDLXDEI37UefNV7bLJNRz9 2tT6Umd3qaUMzX86cPZaehyLXldb09ht9/n25nGn3H3wjEV2LMUpqElLe/s/OKeHlV8d5FbJPcaW jIdb1Di0QSXz1IFN31wFIbsT4b/7D1duOSi/bwoNs5ySfl15t39JjO4U+Ujk6s1EF8r6PoxVTXqd Ak3s7Dv6i0c/7qRCLryuwqeqOpO8Pw1R9jkjarQX0NH23i26IEB8RhwAo6cbcCGjR57k54ONcl4M DluoejGftof1cID8Qfc6v/xh0levSqZ1ieP6oK3qoCHyq+NCPAtMMfzpxmt4/bmHML9nk55LFhSM zZieKj6F4q5zFe+MzDihRO3bdcI0qMrRymVRDrZVkJSzwO8HK1WkUjRGvEuNigYG3jkv8IBaYdox dXAg7c9KN7M9p9QG37IW1WU/NAQTZ36h8W/rVQiaEyN4nTAtr/Bv41DCRmITHIhYt1dXEn5eWBb4 fMkcb5uD32T7fdXuPi+QqV5r3FB//AGGf3j6VvmvO4ICSYw54ljQmn7uSmPP505u0W7AJGr+9hnG 1YvJgvlDH4d2d8NjdNZAO4z0gmalkKsG3Y2xcFi8wGeaTiuU9cx2d9nJya3AZ77VTgiWFYDMXgB9 jKVOwlnzmq3rhVoH8OgBOaAFjjsv3pbNH7tsGYcSO4CQ6NVacmgxVG2oLUg5ZyoOAq4EuamH5s5t ZhRVADolLD6LN620urH1z/zEpRoQiQJm9/sSs+dW6RbxjqSJG19geSaYYXbvBFcCsozJ+U57Nhaz bbg38xuiJdbNnYa6FJYBezcHn6oVgvaqrrWAYBS04UJ4nQYLOPRhCvhTIRQ1x5dELzLUl1qtuQmW rMFp5bkFoIRgb/tj808T9uLBipHzuHaUOsgeKv4aNC9TwmUhMZopeCCzKvYSZeuQY5GcFIN3crGd FIy6hN1XwjcclxUcVC6T4WhKg6cmHsJSuFavURz50dZ04isEZqmAa4B8rIuxHqV5CXVYCwOhKXy8 ZkvpMjJQ30nEnrbPGokSblUQqPKSayRnTnKmLrNRK7iJNB7Y8xgyB2uNVeRyAebiTgu+VGP04Lat zj6PerUnKl5FQd6AUiwpOFwYvYPAeRIWmPYR5cKz2Mx02waCcs/JRwHXeVq0kj7e8vfIpWpYOFvC dkGzmwRU4HuKf0OZb7U/AWGIN1Acc4X/2nNXI5d9RIzKiMjusia4b10ctQqP2ieN3ex/P3e0X5Uo T3ZD/tEEEozJJGY8EHXgg3IdJWQB9mq4o0W7FtgRA3NIpp0QC42S/utJgEf3rrZCBwSp+OJILG4Z xkck4GhNsfEsEdukcpr7wfL91+WOEc+wIRFHLLU1ryBBvQ9Qq6muHPKdfqbd7ZAoxstDIg19LC1O Kp6ppC3QTVxz5xJv1HayR4rorVk7WnPZnQL0eEhKzlEQ/PX4Q+5a3qijtO3DLgn23vYI/izoVlEB C8Dpe58OuXUhG1YuQDGc2hVxRAVBI5+c5d/N3o5QqYxGT8sCGD/t7mzNFgoU0+FJjHSM+05dEaKe QSnUrWgXvZG40Ymw5xVUSQLtEy5FodbmmDkPoxmZGEsmjGcPb5GmHebdRASE77SwOFpJv6outUc8 T5IOGYVD+JgSO1OKgKDyrkC5sGvUS3635jcTyVGSQ5Y2xXSrFt9N+I2zZ5E3hhmRyLNMPKG10KO6 OaDxfacdcgKuooCr3RlSQ245IHDzELWNaWEzPc2MFQetDPWS1BQRvjTDY5plrCZ7+mnnMwX2sJNX vC2f4ZZ7shrOvwPxpK7wN5K8jqs8t6jZfzM6M4Ivkdi6seYqpSLnIT3g664YSBqaxPVZEPfDfrVW T3zsNQ8s7fNiRdhtWfRjqf4frw2f3ZuD4waYM2ZqCx7mRT00MytHpeqpx4yO6U+wGIlgwDA6fGDQ CBD9SZqUhWbYYxPLzkE78aQ1kXGmRaM3C8pj5pPKzLGpf2vGuKUmCXvkOF/XSP6Tncb7aQs1VUEb GcfTJdWu68JmoHR/n5DbjrAuml43msshf090YSo4qli0oCY4vyIxjYg69w8OGCaQP8N/kU2HOIYk CZa/WpxKnGIByOBY4yVq05iWTY9LJuy5T1eGHBpPjywr3KFYGqlkx3q5aPvH8dZq7/D0EUsx84D0 kyNypHKjdm+eeDiiABGcf4Y5s8TzAnvyMU880zh65U7jbAjlIYbDEkbV5PBpUxc89eoxoA75dRsC vrVxL1he34cupw1yJk212tyjD2lvOwL72/NtgPkffnLtyEBZyh2OWnCsZQssQso6mSwVhAZR2Vui Ozu/g7vxmIGa7kOYu0TwQSfqd3Q4EVrE7wy9+65CF73kqEx9BjJ6iYbeJKHpz2xJFiJntddq5K8b zdgHrNvAlswDGDjA8YGO7p0XgMftlf/V/iI1M5ECxYgIyVX4154YM/lNaRsywxgWL2kUJbzoJ5aq 4h6eznnvBa6HjbqeepBFDm05IF6N5oSOMNUilTYLEacmg2V2W6yCIlBmieomgtE+F+GMwdPRpCqj gQ6KTN+a9fygrRbWqyNhV+u2TIA4sIK23lyjz4SEgKvSlj5X8+IHrA4TAHxBtAdZ0NrbnrFkpnoh nVg0N0TWsVEJWQdtdO3EAw96O2GamBZIicFyeQSk6hOoO7tdzIFc+VZZqdjA/j1rk3y6hWeBLYjy lb3/jJodVhnSVSTAlh4mAYUcrRw53MVwWSpguEg/XbbzPUvi3v+WNc7tHK1XOB1qhRYiSJukCp+u FAt4+kNwBl0+asddt8UKd0jS1rhJ1aaBYTQj5b4nfi7xXISSA3D3AnrHd0/khmRgFes4GeEVqgEC OQlPF3JlETbJYVWPY1GkGGzSGiR+vyA354LyeuoAdh0LzagHbsRzZWqg6plMaDiYDkQSV60MdRB/ f9+nJjAqid8jZ3gElCfls5sne4SJsEIjJZBFWCa6Otddi+X9bOvI8+35/dXs2bEcs8ho1D9gzCae tJhSN5RZWJ34TQyYu1ZA/1+McafidctGRwu1gddZe32+4soqfv/3ZHyhF3F6k/QE++KxNhZiIRdX D/B7PGjGTobm9/WQX23Jkhm/rbCBr7IalVYOhRFLOJQR47R4YmBIvMGaM58NX58g5XGo7kUMQW05 X+MN+U4OMEsNKqBrEwQfILRUbQiioZ20XSC86UZoLyUFRX4G6p/0tgxXUi5/3ejPYj8XKRGG+NOK adlFZTD0foFQUG+hoOG9L5d2l0JnNsneIrBfOsRxt0AiBB0LYKB7KusLkDMEgCGDFu7PjxindMM/ VCs83HUcViJndQCnJs8W8Hm4CWVOBL1mJXSiqv4pbB3T5i3NxOK+Fqb8Nf7jkiQtF6BWNUppQ+I/ dPNXEO0nMVyNaqh5VDyc9GFR5c0eHo2FeJdknUDKVEHSJ+BNd6KXkrk5vu+LFNf0vP6rtBsmE4AI nCY5SEs1B3yEnNxsJ5uWfTlcUGvJzmTbZf6C9UGQCGmWuZWDyXlZH+kBN5GTgdtHSqhBemqxxeCL efahnas85A8lr4QTs6VO8lVx16scvKrRro9Lh8aqH1aNQrhcB5LcbQWhF3DKjHh//lsf5aUTNiu0 og/AjFpSqlxgSF/BOpnS0FxAq312Z0yTYcdGvMpnpsEnGyu6T98OFhmlYZmUNeifwKAne+4X5i/y LdseNrFIk2m8k5fdhCD73ncdrm8L2UnfIec/OqwMelp7sbEV4IuTArp9Z82uLeTtOUa9wmUnU0Bc Rr4xQT+B659OLeqmBwNyU/hd6J0Xx6Rsp0bOPDX52umQlxsKomcyxo9Fd+ASUfHWCgCvqjDeqwPn aiSyBoBAUpMUW6W4vs94zuMaEyd6V3csyV46dsnCfG7+pOzR4LwXPwcxFfPIMp5VEdK5Tk8/abZW stnjLK5SJ6NAHDpHep/v52pFw4QCilpvy5QQryWGPmkQoXXby96+skG4ZJQqcqXYccwN9WyHHQzd uehz8lNsJF2dFIAOeVXLZK80V+dU+RzrjQvUccfnh4NUnVOXP9QUiQg4/tMmWQriHToQPaHMfJ6Z +O32vaqTj0Ofm21ToEKCy0/oe4fgpSUEKlfXvNIqd7Ozu1xXxTIyihC64RK9EN9CONa+nHVDhEv/ jpCEqyFQPmEZzqo+tfzkZnZb+TmjJd+0v9oQFZxkx9LoylK/nZSBaa7ew9WmaupsELqcpxd+A3/N mf7QjkJ86KQr1jZprVEuCiAffYidhXPvhWsgLeGAvJW/nquRNlKwiWDi85YYM1ut+HAzrvr1FmjS Oa633zUglX84tSJhwvv7q9jbFP16xf1ohgGa+dND3hWuisM8OUc8Bp6/+sVYJA5WZ6gH/qQPjYWV IMzvVQm7aswZdu7Gv6uaRnVOq6ukIAOdv/An6yDb1z/j3v+ehEQLI3bnehAzYRqZNfYdoUef9yTn NTXXVTsdJk4h3XK1vW7kKZAaFEEeit3bi6eNANN2fefFJWahYG/JUayBPdbEK8r1OOXaHegaNp/E QtQa+QkZGHhHDbBgOG4q63g9gRgomvONV0JPybTEmscpMhuXkdNe91+4twKXESnEUhIUzzju7dSt ayFYkk41wwPnWnYPthg3CPO0irI2mxn8CIroSzT7sFacukqM/uu71clhUG0TVCNIBIsXL/dZfZ73 ADxts7BEDLmimfRi0WRSv6P3bkHhGyECrvqWVdPqCDGWOyd4M5mgX3WZTlGJoDR85QLonQmJlyEi IkhyV+pAqGfD+XI7LtqvnMyx2ZuQMiyA49QbGdWKaFE1HhpwAsv66dD0VLlDVOzQV9FolF81WHV5 wVmIGwmrxpE09Xag/VnR44gAjWj9XYohYN1FaT0GWP3kf6FKd11l083hRn/GR+mmpOGJ7rIPd46c xatAIM3b/eSV96va/If9FzJbnh9OlvAHiwsjAtuTx2TiKHNwOxNJCaYKNLknL3Qw0WN/XdqUqN2V 1r+c9oZJlHGYlKSq/1SVJu76Eg2UO5kFCFFybrNkOVuPLxKhqyZENk9h775DXEm24ZXn6CtJUsp2 brG1yX0VFZWx2oEIY4KvVJFI3HvvLct2x0EHleLdO+GKqLWAu151Pe/fyTj4ECRADG5tXlzNzUiV DWdv/KgedxJuiLnbzfQe4gSS3NRml6T8LQpSNsrF5gdZx7niN5d3XWEafUcJUu5ACL+bCYllNqd9 Ps/CVSyOMeJ32wVqtjOURjpsyvuv3PoxV06QunTZP8buw7zaTYYhEG8H+tHkj+41O8EulewaHYLB sQoxg6q/3bSbkQtuJ2GCdCi+Q49XbkLCojRy5sUdnd0aJBYs6jS2yO/kSt5w90Ne7TjhhX6pSo9m bTXvl1HfMyGH9peUyXxOYlm03XVwR5UqI+5WlOLolOAB5P4mi6j+5IG0zgGxFUg04W8UnoJNx3Uy BxY0VL+t3gZJHcAle7FKSOlm+GKZBVGMKwANlf5gJDYMqgHaliOhJAxOjVX++IEApn9OM1Q0ba8N w+rNlHK66nUjwRtCX72P66lI4atN2Jj/kSPQZvInPFYvO8k5gCGCUmH7Ys+GjvtqklSix4uJZjql xtP/C3fiMKxheVxKtUn4okpqWrNhH7o6Jbf9aVobF/pi08m+Ah3V94hwNHsSTtqxbbgIgfxE539J CRqINRyVll2drOXy5lSuHGGjArtpK/+7Xp0F+UxbCNViAbO/RISSbn+eghAg3BD5IfoYujFvTdSn y84FiE60yn61KQJOXora8TVg++km8J/EIySh+XuVn0N+UE3mw3NOpIDexCIPbaO3Pzsosa/yVnst gn8IfdjSn7WqE4drVB11YpyxOUjV341rUFEywjHJy0so5CkxVMyUyx+pkM8xrnFTXkhV2Xnu7WX6 Ad5X/8/Q97odimcPiHdIg9lZiGX+mvJBgE2DxNpNiDsURsRrs5z+VeQ/E3k8yodrT+rup28vQ3AO eHAsslslDh1qIDS7j1QD5v4WSv2rJx7OV12AWQZAVdh3Tb8awiLj30+DLPMPErNrWMcoH5DUP80y hwuV4WgW7OZjbYoyWcV1LYG7E8HO9jtFmNdgDZnMjzGtGf+X95tmKzx5ce2xLAFJ+LaTsPRH09mL fUc58jf5FhgWDdSSfp/+i/XivMTGKlNQAvo+IOgC3pd4aY57HAo37KKUzwQlERpilANIEivCuU/+ X54WtIFOVdAtv4MW35g9FIeY6MaQra3vUNSSxG63k0k0BMPyuuKkelhQF8+MTSlMjhsszP4e6+jG Uk0/cEOoBSLgJ/kiRAT0sliJaTDmAgpipsCi1vBD+9KwuB++BEfv8vl4G36OytkMFpf/oGjfCjq6 5srBbm4+5TDzsE4Iw2o2IVeKxwu+2ZJS1g/vE0EPymp3opfetRwu4GtClYU6F5bwMNiSb5dJzJ9U k+p1huIeHYbONAvq2Zb+olSeK3kIINAZJ6AkdDqBmjtTtXBPsQuRKQlh67RGNzjbkTRApT+rNIK3 sp3P4UU0bIv9t4GMLJvQH11nNz8pQwStvsokGktMpAfxUsUb7lxAfLEbNqUXdnTMOR2V6psil7j1 YtCAX1HDYFoMLncRfHDfZj3br7/LKdt/GCO6gzpmMUYSU1aV2rqQKsdn2xk6a15ZKLRF/uQZEyGP zZRuKramzRAWgeGkl114qRIHk+B0IBvvk8rUbfp94GY/ZwuyqXQ1Lwcp59wQWd9UjT08MWIa92QB M/gshGCxZsNnzTgZrwJwbDprKIlhPwS4TYdfh8N8CSmdCvwRxbtfP0bzbUg/Ms1XeXCc4iSYge2z eRImqEcKMnxsAy2EvFH8U1Bk16mOVILh2ryr0LRjVwzJRMtMDVTnVEk6XwOAxazrborkO+NtuNdd iKBMGe1U/Sb50q47lAIL/yYP9gFpmNGJ3Twmuncq1nfrHutNQb5E8ZUaXzapnyVPHWD6BqWuU8s8 nQ7nx/sS3W/hwvtS743ZELun/61kkqvPYIuvp85dIxGS2M+nGkTcE/l3mIh9VOu5Xwhw6KRZiaoa T2a2U7UeEQiQBPOF9VETD4MlOIPVAG5mN0/qDJOgQtQF8E6JAtSGVaN7hPkaIkid92hbe0TaJek9 YFwsioRFBbRtmrvw3/Wfyn1zNNzRxJkXcVE7PAYkaoqQQ5n3LKuhMNk/VMmI6cAaVNiOdgnOSQUb tfk136l3cSFbbevhrIAjNPq2ZEgCEIS3wdR1t/r7bVO+eWELowZ02ROGOhPtg7MFenXgdm1GW5d8 TV4UvJ3PJ9eZX0GhtkONSiokmMgWcrsDrfYcFvuqOImZeFRFZEFfLKS7HDJgsHxUI/FifJxs5n3k VWykHuWdosCKG4AC5MakxJOZS41bVMO+pUAejdQcWtbQj+h4XVn9Hp6puRnWGH4hfKGPsdsqLZs8 CMqlW8OYcXULST9y5mlchblOrWXZtGsV1zs2AE5YVxB9VOE8BAXZMIxF4zbTtyW+7BwbSBFy28GV 17kvBW4mTIMZz1b/EFh7peKKBi4sWwKurpoxjZ9TPnpOYjz7PFIzTydFOPgfYTI4aPO8TKxA0ryp UylF0Y85P022e2rT3AEsd73M4v7/MYhaW3lOuj6vWtA4IXmgQUIah6/r4BO7VYVXODFYk0MrdtV0 nT6Tx1jiCKHsFf4y3IFRh7N7Tr8a/CfpMP5suVSkl7hBwDOULAQbZy8+xIXMyvO2VA4sppa622gW CdjqdInV8iGNS7WtNdQoqq7WDxZCPda0HKNu7TyTEn9nR00JLiH4HutvOIl4CSA5NuiPxHF2rfxN vADl858Z6BbTNBdNrNu/z73gL8FpWwHkmXLZ58rR1Qk6M6rbD3u6h88blxZBl2AS3if4pb+CKn9C eiEZjjI0XJHxduFfxzFT6i4/pxD088vhMTRAJJ6I98l+iuC+3o2UeBVfyK6JlE2fbbkfSZd7M9lM kRO4PEWWadlVntn5Q7gfXwC+ynGMXKtUHESou9GvpI7oCJgGKeF52mcUbsD1y1t8BgucJ+x+bE+Z rMmVw2CKaCgz9FJib1t2yu7eXzPGkn1IGw0VCNrPemq33DqBO8xm2kBwZB4VzQUtU4fHTObY+XLE 7pE3494Qq7pO0R9tw07GcJ7fzmwHitummQMTcg1SHTREZOKKEIDKl8rg5MIHh9nFLjx11fkhftQD Y7iHeNHjmk5h0CpxteYOFQKIAvKvz2uMG69+B9KG7hoixJklfl8SpsaYczOLt9UfUz79aB6P1qvs R4p/PjAYwXmHDM39oNNTIb+2pbwvqpyFRK9VSI40kqfmn96aLZUnX0H1KpHz2gXRvDHmBPet+ttu FeUhfRJXg2qjTKMfIDViszXSjA7t/loUHX3jQMhb8rMcGHoPx0K2cf10tcTh/GKJGSPZ0MVKJz+p xOosgon9Tv7oA3rzUOGE1HuAZ7EaITJKNA+t88KZmO76KVJvuYNqlfW4UtZMWYklSk9s8Df+Uk3y QzOSOpcz0y0Q/X5pkE2qTvcn9DJkzRINSWNxMxK0NjpgsapxqIx+1yAbFFrsoS3j7kvOixEhRu6r gwZLP3mJUmI0t1BQDUv62zASY27xmTq3ypslUX8qVv0sPoGLhx9se82lJvFykUoWI3L6t3lK6ezq ms5XZBbhZCiCiMSqzk53JPjEpofauR8pVF1It67mjlRGQc3ZyMij2t3sINs7xaT/q+P4uZvwUCgM BUMGeSxq6dyviYUuRNQSw4cno4lMYi6JblrhPLLsgB/Msh5A0z7xmIKHhrN82ELSwX/yLQIF8DtO tc3QF0ZpObhuVEzr5cnKMV5eCrCjzxAGe1BXZLZ8bSz4pqdjJWMbVGi8jMTGmZTBCDnSIezOqyl/ jJTuigSRi3FlxT+nXciWgooPDo8/rsl1dg64STlJQbNm3hOoUGhTzaFwcJ/9ryb0Knil6gb9ghrU VUNl+SOpZrf2/aj9Z/tsRo1Jom6D7nO5CdN8Oj+G9CBtlJwse4zw9v+WRrzRkAWUoYFDI+jrynfe s0+Trm4gDV6s2BGddNMmT5FxyC0XAqmISI9PePktz97nQjCtFAVB6GpSStPTHb93MCuyVxmNoTka cCS8CM51dnAP4hbkKk1ttiMfOMmIBkLM73+Z/U256B7AtRdeePq0M9+Mwl/nQkT9zJPenb9f4CWO 4ISW0mq3yk2xI9X1TzWSkzp/qqG0locRlVMFCYF8I3yAPiLVE4Dzwkrj5DIW4REyq3XykeTrOLLo cwNWkAaV38eFaNO6LGljEs/NVeR4p8afo1b2vtX2jeWumEgBZ5mPkVkHU7eBWTz/bJuoDkrHtbTE toCoadLKoPRkiFlUx/tt9xsYtk2rbz0RDFdBoIBfsZkQv53HsIEnfYJwv8jSB9DWOPZnRg1lKpBL vrNsfYA+HcZJKgUW2gUlBjHaJFg30/yOrPGecPh6LP+N6T7PzHA7AHo9GQ6WYjwBrSPXadGTvBYK UMio2WnITzgrw6T5iwGO4W20NX9vXMUfzwx1k4h5MCg8zDKu5anpP5Q7f4jeM5fz056yKcsHBpNP DSRn+4byH6A+yW/XFSpXwG/tdbz9jHTUcmEZRE+1JySanL/XZcru1FFZEa387BcKJmtKsrNf6FVB rkeQ3A707xitYvgNODvLTinHWBSw1uAMqFS8pjOymqX50j2N/tjDe6ZHw55UVQWWFK++TESF+XBv 1aDej4ODgkJCfCWfL/5d4vSzsj8Pj4hiTrtg2/wMLF+6i7OxiHcymqASfTHEJRV/BuXzXGnqPjPX RijTbZU2jN9tWYg0awq7yQ1f3o0dr705ZjQ3YxD2wXq75d1f/bwmnJcVS0rUY15zaqS/MLstpOdS kV70yf1/SZv6GSTRyiH/skxi/Ip+0HOotHopAfUHqi+lT/PiVaCAKc2ec/HmCkN0BJhFZHujmvm6 e2kUavkTkShZfcu3tTr4HBwKPNuUFcvj6bGORi5R9EPMparWjwtFSHO/P1yN8CE5XRRVLj25sHw0 nlBJp1qePakSsgwcpNCDO+DDI3ccpLPoxtiZJPlvtAULbuQQySlSTywswqdtZqhkF0gCeZvXMigk pHb/wkxD2owZdmQqND777yCqrTfJ8dKbQniGXgCB1rZ2Ya9zrC3nX3bqo2yNcCKcvqST0sFId9vl /ZfBRaMT8FulFIr31BwvE451Hh8WdHiWHB3RY0z/xtI5bP31NRbC75PiBBmRU1hOtAAvYqBecJ7f 9p+OrVfo1ImFzXLAdDInJI3x1pIxPNvyyfmphl1GpPf4JsRDnZkA98K5cqz981dCUbQLgCwNU0Qh m2HAMNBpZ8P+i9fiEj6MGwMr6fd9lHA/SDcfzBTLZk6OTmudAIgXi1G3FAC1OkAeN19TOVc6Fl+s nafRepLrw3TR12V93SLm5Z1YygoB6exi/acOgiOhXV31uMDv4qaOk4Z/1S2FFsL62qPlpQ9/jlwb moQXvGsXMrlAP9K/rz+b6Pb9Cro2qfzvBVDbi7/H+0W+JRwPZf8xoyiFuqOzICJHiB+w1WI+wKlc l6w4D2jWYfe8OT6Xxr5WsXarQc/I6iM/eOojoNHDk1gmUBJk/TYaJHXM/g+9RHl0TY4HQbt+AQvv vLN31wav0chIOoKPFISKNGl3o0PqkbZe9qEGXkbqCpMVJ1DYJLrL+NrMlQWyILbJyLYkFNtoh5u9 GYw7kQMzWlqT3btSUbnIJ9dHrnnvoYdYD540yPA78MumwNtw5t2+9EKheZUeCZbhWFvyEuVphpXO riXSffgoKtDIqII6xIJTK+wU9BIH8dO5V0rYWpC4Fx2EE5Wwf/y5caKXv+CA3XgUEWDqlx4AIx1e Sx11Mq7Tfwq6zQuz7aUWQY9KdxVgee0vkdJhNdrYucHI5/jmkj1ueT8wsCmksNam+obCDW4HidPN zyxRvqzyisTHU5ylsfWjDQpYKOMUOuzM0BOp+7LNPghaeduC4VcJh1y3lvZEhJ4d0ZBH/3ib4iTy n2dqUPVgC0SWwYV+VhNqEDNdE0ikJSHD2n7Qxm9yAtnuK21Oo8GFE7zNEke8EJgdUJRJVj05vGlu iSVLTWm6x5rzr5Olqu/CGVOix954YtRcpVRHuoE4IZO96+Ghj8AMZqTvWwtoJAOC0/o66MCwgh4X c9n2YCpSTUiMJtJEdh2cmpT6mI/I4yh4gQOkI3exK6IyS7XKobPsWN4BoSSIsB90TH064wi6nVJ9 R8hCHjOI7GS8sFhPuWCHXnAwQ1x29J0Gtdu3QcqwGZwNCD5cb64AK6EBvXNbfU4MprFN2asPfdWK IsHyp1up/OYHop01i4jlTUyCM/1IXiaVgi60KZ4OLPz8FK8fM0mLGbr84TJpsSuiP76mRrwZw7iB MKoQNBDWaDe9JZvtKpahFhVgIW47Vb2oOM6vgXR9vP3jbBYbVy9rbzywZp6NLYXA1P5XjhLn62fS rilDKah3s23HsHVNzlpPhBOXDdZslg6m0YeDaSo3bU6KHCiBC7UXQpQwG0xfMUAoU7m+0ReJ0l7l vkXkaizx3/+Y3EmgsAes3cuT9WjDLV8dtuulhuBS2m2qX/1C4MS3NVQJVL6w/zdUryFvaRFyJhFB 9xo59LnGghfPyRUePrf0u3I/e8Zo46T1J8Zhkextk/gAHWvxZy+WA/ef0QBSVAiVTgQSX27Np+TZ wnh+dgt3dBXXBwFTkOkkWRjJn5QvfMekQWBI9dxuA0gBFNFGAwEVrxg5oInGDGh3XsKIVybFfqfW VpHgMfWJhHs5kAjTJv1rwlUxvn2N3i81+EFqpUuItryXgcGcvR5ZSGpvttX/EUsqGTbsyyLwB9VF cjKPPWaX8F+n9V3ZGQPp7dGY/KIYWpqzb4M8EOTBji0UDlTq6R78nv4jO7xfFc2tfEgzC/QGPw5W x25hxnCfeizAJY1YiKHc83TyQoab8/EpxgmvjlXrIpy9764xjO2tL1W1RnZN3tZUV0HplPOmoDPb nOKsFxYDG4z0WBkPwmvJ+xUHwEamAh3Mja8jBjaY5Qd/XMwqmQISg/ZnwRZIjmM/rFmPHEA4X3tm ytf8D3MhbDyVxlyiJUgdfxUsgTWzwoqP9+372nV+DJbvFyawq3KTOzEDbPMOUvtTLDylZKLFtVZS 2GN+c8kg0+S3lBzmkcTJyx5R64DOKMFYmOEBeunWKZEq41iAR3TMDO+0bBrhsMsKMk+TF40fv+t8 ZrXFPdGsA3ABxRddC5Kh9nUNf8XKCqyNdeLjXCiX/KJFf2q1I9zOs2hD5YTQURtui6AE14jWgeHD aGHIBm1uyjOexJsrduffObUCoyPXN23DGyR4snjqS9ZRQ7GQkWxorrrl7ja7IRjUmkEVQzuHODa4 5XaiohBTJvDczOCGknPFOJdSe/AJxrm8uv9I4HA4VI5Ou152XHB+MyKf8Fq7d2gKNXWYMKI1KG/p eNaHmdDtp9fhIqGQ1KUJvXEK45lj6BqCjiwBZYJ1EGoAKlhgqoGVuGbnYfFaP7bVOkuQrxmqOy3E piO6bbxVCGAa17slZZuVRt45v7T5MFixnRAqlCrz1Z/QYhc0kJJOLexEM/Mx5GNZ0bvLICwM35fr PJey28SJAYhCJ+CSpA8RQ3vmoUGjsR3iTNORFLGCyHN+/5suGV9mQlJccIGEIeoWMXp/bBK+BOj+ TWXPxLn4BCt+CqGOUzgUnkllhnBzZQPouKRrXOqgEElushCWl1BnRRiu/RUzt3cPnfYEBYBwjEWs SQdbs+524mX41RNm1QYMybjXMDoOZ3uG/ArFDO0ySgox3Zo3aQFhWfJkpMIq2wf5bDxtEiSidUYI grg98r+WQ3Vna7/jpyCuSCnOfaetZ1tCddlOhBVbRyNq6VMp7LvwkqeLsBzAYNTNVisrojJ+lTSA Sy1DMR5aBZY7Qz1tbFQK8sVjWHilSRd+LvY+fsN84hIJh3HdI4lobYSOoiTLzJnzxhzA1nc80iep Yob/2inomXE8uISRzeAVfG+yImFYw30zG1b4rFVVSfMcxMELSbwRkwVFbcMPbVyimjsylSm8FLiz IYBxGjR9yuPw0TVg6G4fpVb360N0bxKwEKK9W46pz+RhliSDHDVQvtY9s05D8fperHgSII0qmkG4 XZoPGHdfcdmgDo3Bc+KUMOidJ2vnHp7FYJCZjb5v77Rf1ylZuKonnMNFEUfcMDQ1cU8pw2PB0McF 88qNXMRtDBo1PiwVpvZGFaN94G5bEazC7JnXq/PmuF4dwlgSNtM1nVggUWjb1MujISYDS1abXzqD rr+VmrBv8dST3juyZY0IqJI5ndRJ7oUuUojtLFPgo858OEuKf2w02en8hd8FvCSVG5hHfzq3BNVu LRU7lOhNjc+gg2t2L0829vkwSueEqhAPAPbIsxXN/eUHRLkcWqzXP2ScTjEBjuoWWS29TDenIkK8 jsgCrBRSbQ1KuZ+fDi3cn25x9lqy3fTx+3TLQWljLJ2fXlEpd6QSEdttB0dIgQDqH6dekWuCluFk eTS/Xzd90jVxIIkTH/OH9gxXjEujaMwKqa33GwKr+mVkSnozFYzxgIYcCSFajXgA/gwF1RcoWWYA sYII6mq2YxrI0t6LNCv8dqFJICoagS0tTio2/iaJWMo0R1H6T8ANGyBrHEooXcdg3fQzlt5tcXiK 6GWSITw1ofip2xq39rdYmLNPkzXV2riG0QAStsCIs5hFo2xzG7SqwcGeqCAxTNF1PFVeX2Uz5kjw ZG7NWwMpYqqy3qoovGUh/16GKhTpFsj3l4EvzpJdetBphBQmHAgj4jpHpkKYNuP+ZsP63EdYscd2 hgCfrf0WbkhudTZ2iFC/WT+TmrY7m8hd2vbAwx1bOu70VAOk2IjtKGuXv8fyaWo492TmcDb9me1b pABbILJ5tnp5D+bsQhRfz2SSuLhaKBv/5SG+VPxvvt/XXX/OdT+hy89AMIPH8RF09KxGnvioCa63 p4ZuU1wk4BowvgBXvjteR9gKh4/tKRrIIr9ez1FMax4SplJltTe8eZy9y9jsAV+p0Ku98KkJQmk/ nDUzOdiI5tS3I81qtPL7mV8bmY/el476etMPAMA+230MDO29yxW+p4oJHwr+cy75pwI4TFWHia4Q Y3xi/gtuT6PZoCFoVLfqOn5IWFA0L4Vj19qtANg6zNqtStCnK8npWz6aBNw8BqMuZvDNUf487xBx iZ/QB0AFsW0n0DY1cT7s7LVhRdYhmpE2PF9HySRThtLPKLLaxWOZbh1JFny0lw/wWB9jSybxfcyg +bXPaSgfeQO4P1aK75BXhd7ZskJdDj0cqmHmQr+SNnwQQonZ5b1rIQ58EQZ2vTJn06iMXhZJofDE 8/Ktfw9hVABIAdOVEkk6l4RK7BadOC2tRBS1S1EiaL7YluDXSGCK7TPz2D7fiV+giVKssmrSbwHY rnU3w4s9kfd40O+hB7p9lqRHhk/hezWj4ol/IYYdmCNnnK9JCjyCiFlz97VGTW9aV3bzYnk1W7MF JXDTJ1id7GUXM3G0Iffiu+WVgouxq0aqiqNqOHlbdUOdWNfWmTuGL6t6CFON5pny9jDhHr6MbHe6 ou3FG982diCxb3GKpAepT3oloH6LjuTDr982ncpxl7XE6CFYX4w38z7ZQgBTYVYfMXjZTv3oxdpr pN4X3JCYW0dZmp32uzuQqHN6ECqgGpemSLm1M9JGVsiNBa2vgIamIDhpDHCtshCi0u2e6zW9j0eF Tt2edT3wStdw7Kmc4pIWpHvwRX8TIRr23LT67/bDt9eFCWvEoWJq/98orbXQYroDhfwuXsvmY8tP fbL3UopqKiyAuBcItmOT+yxJKiKn+Cowo47gD8njQHFdZF8tU9avM0etc7Ug2rCmJvHm0GpRdRpX szfplSuVdtVy+c0zAoMuXN6zwFfUcmDNKdJ4swNGBrUTCG2PMYy3KROUfUkZ9hwUKva5HErLUpRh cOuDrbuLUdiVzQdMVVEhgxvmZJj2PAaocmL2NAuHs9XIrwZMtCvFE/TQdJTNEEL/sE/Yti44S/ZX wcpFXaTK84gWWsPJVUy59Wgf9xxxV5Vp7a3qh7ie6PBtoBUe/QAsmzYBMWGLWsRNkEAYqMalxLej n9j/v8rrzaNNLWAzJSrOlliksXU309eyFp4D+QizWOYhz3KdawGcaKCgt+xW1ryCgIl++s46+KxW r/X29a0D7aGUyWnwbTo2HlUOVNqgfDzt9MFUWSyhxebUV4GvMezTQIOBA45Q71p+v6bGLosTeVC6 JNoGqUpVW46kNMlXPrEO/JL5bJnYOvhOdFzYsB8rGtc7fzmd/pLGxqJ0eKjqq+PzVFQPmZ74s+b4 uq1/o499DkZHj1rdyIxoD26rlE/Jj6RasHYW0MRQWFT7j3WvM4PNwSUZMtoUYzyG2jQoLyB5k+JT uAZ4NXUROqBu4KYxwUx5n2Phtz8mkhwIb2rGsAA1o3A0oykjf6d9mMWqPOzO3VvfXJGK0Atbkaq9 27MOjBHoqAYx6Aairi7DqSEcL5FZ/gX6A3urIdGYHWzPfNDHB4GI7IdAeoZcrP1JIQMAsg5s4YU7 tjKsRHfVpeSDOPPTpzNl0KBBSzLdlWChY9d5MBda1TDMynNAbW5steeBJ5nTkdNRff3Lb99JjAAc RVAWYI0HsxzTXDNbdVqxbSJvQ29aTe5Me1of2xflvwTt3lWKfvTY49kmtNzDrjwiFDny58FJNe37 F8V1QLgLenmun9t6JkCFG7Oug8QUjCG82pnk1n3Uy7cpxfBGeND2puOiyeFcxoONUGlQRodUxilZ 8gedsVo1QztuZgNwaW0UrVnCyRyGGM+kJRMjHfGueja8TG9ut4YXya4R/b9kimcPX4Kj6rSfDfqc Mwaml9rdixlaMaGPeY80Y3iVwwFjEbzTprojb52txXU3iOgD+vKAkwRGKeHee+F/L+nJsdT7mB3o zaBj9V9DuVKcgD+i3m74LQLO+mLnTLGzj18GNIlki3a8NvUbtHXqCEso8c24xDhj5F/K2k2L+KSc kQu/Dp98HhTTEgARF44n2UbSuznNTwN73FTCL/vgelGvNr1qJPRp4As1LWJc/uxPxnkZXNSajbOn 7txryVHftzLvESKRrzeGIH0Plsh1Hxq40YnDGeXQ9/mnmcGGCWR1AjhhsSD0Rx9l41zGC+GUBx8L nA9JKHN4EsaG2yElkoepTThRyJvPPzBvfROQcvZ05MUV0n/jYJO7ABOPXkwKylJhfhECRdZManZ8 /t5cm5b/5BXj0yrX9sGmoL/AignSaGEoxdnSKWuQyC6a/ga1yROy5Ipr1+GfdBNNbotI+DKBLIqC 6HN6jpwTUXL4Mdes+1nt1BGnTW0Gn881jaOzr1FlzGwyuZg0BNhSmSu/9kHaxWrhNocRi8v16dex jIuBVxKozFdQaxnLa/V3LpYjiGwxRn9QIoekwb3Ey+cumeh7LX2qGY+zC5sCVHoOAy2GJtLghbYN s3yYDTwTURv0ul4wj5L6/XMYLDwMhTLoPOR03pg/3PZ7hWrCpAL4SGUnt6x0Ii6SrIvqk7xbR+kl VoHzr+kGxMJQWPqA5hlSXEiOoyfQB64fMfbdsrQYzA3q2j/1XUsTLVc2I3CD+hmlowNmAghE0pd2 RMJEptOMbT6I+ZDHXdiuKkeMgO1Pp92S8/5kPHTgNT7X4EonZ4r4kNoqJgjiskkqcaJ23vO/tjj8 vBORCGhaGQFiJyojXZSXlazTGE2cIi/KSmJW1+bVW7d3rbIPPpNHSv2BgyiDcdAv5P5pTBkGkYvM ysNZhzUjT8kaPAFDeQ2jWmrhWW0QlGCrobqlmd/MZtilatqmPPguvBL9BuDd8yFLMYo5UbSehiOc 5ZTRj8/yw3suBL67huEbGYSFgXDR2t6KNbrV8theZUNHeSzunF3Euc8KAoVk4B3epwyVLun9ml11 IiP/YngldxmeqTzXL+qFlA/0B2s6Y4VCUrlHhimSlpCSSd3VL2Vy59OU9Rypq8Q7TQHkuY0Bvl+N 80R3pCO9pNjn4Ob42drXITFkqDumu/vBD8LqWE6VXuXF5Y/erKRYKnQfq2XY8KRZodnb7E/4slC6 6+ACOsRWF6fN5hEB3L6G3JxIaEbQgoC0NqGXq+ByVwQ1EafgSw+0rcMcVnnVLAo+QXmNNGD6UiNj /NyUkHBFwKpUqXwafZwAx6PYCt+seT8ot7MzXZvxocyCoFl75OflccpdLoVEaHxbJvy8UDZmy9HV QXyc1zOyq6dJEkpIyw78f38aF+Yp+9ya8TGkZIr4oMNB4q7RRAAfS5EgotBZNMXDOWxUK1I/nREB cjbBdUkwQNAnAa7MgJpvQNnvO8GSb41EavAcvAwW1l3ikQHC9mVlyLuAMcgNKqRfXweJr6M3p1ZD 9fWAYg1aFFmrBO0+YykQOJPlV0I/4ULTCxDwNfYd5Js8Mc1nghMfiOqSftJxqoh1cx9VdQ5UlBAP czxQVvPQQz1huO8ysbNQmj3ZnBJJRDQ000heMYfFUkB6QkgsOiUVm3FTO/4pL5ad+T63TapbPsb3 ukeZWd7rOHekagWehfoPUxcrSZeWR/0zRZC4lX9EaD3F2cNVvRxmpEiX85mmMMLf0kUGFThG31ny 2EmF3e4e8LSSK1crZmxhjhB6bwQnVROhfeq5u6FKgsSVqmIUFBCPPknyg/0/OQLVR6hHVg6oIFZE 8Nk75PuaOMRR8x5UNRAV+YX3Y8WQ5cxCshUqmsQhXKDRgSEovN6m/gePa4KBkqXcgKKhfrlKjanH JkYOflZ18Wfd41q/5HAIU75uXHqoDPpeCPuIfPYvUljASgoUG2soN2F7t0oMvfUag7d2g1GsO4qD 1UtKRfZYJvpSWSyP0Kh+5gwbDPiomWCHkfRY+r7lC7DWEtg6tvjd5tHjTuJNh1vxJgfDaRWGHDEP GT3EgXISgYRMkskGYFXi+dalckP1WAz8WoblTRPnMozTKfEvYoroJ6PT8uHodAo3mLkCANbZAqNI tANobnhbDXq10AENgM0gWfg4zJB14YdghLQdJTUBiEDda7f5kfqgddygLBeIfl1urYqklsGXqOD2 9WoiXF0xjLKtpFqb5ZuoJbD4JF9c4tlamhLzSjQRM17JYWNR42eOnUshqB/BS5T2t1qc6wZKl8oR 0IJS3VW2wBc6vh9JfctnX2UAEIiDMdLGmbsj/GADTalptuPDfOuoT3C7EKk38qWAHpdWOS61iquX CwFHzP150DU9yIXty+pq7Q2hPgLTRSYNhhn2anEdHy6yF2FOLFJcgFkcQE1uIpBW9B8OjfR8j2ql ig7CyROy26y6n8SHXoDGw/it5Kq2+IAGtLzsiAf0sMQEgzb/zofg07s1nuRk5aT6GaLiU90443up unLTc002nR7Q++HllH2TVVW2n+Lblbr5iBUoU1T9zbJbMoVFjO4ASAZPI6EXHLRkh1iMk0LJfw0S NUvtqfjTN/FO2/DmPOs8aMQocOGRKoHjWJOiL6MqlIslXWKss/V69ZOSG6mvhufR3H5BTCr0+AN5 6JLuX113aTUKSC7/6I8VuEy4hcNVBlsEJsqliurWHOX2zxvnn35pjl7WxDlkbEFFcX8hmXVBW+bH ANgjROTospBzwJSuiaaq564OmeaUY/4+vSM8hhAIwb4q2DKwiZ1S9EI463Pcoxg+ha+EiVPP/M8g 2v9l6M3CQ7NHEKAViufLTKO34UWSX7jLZr5qw3nhTF+PufMptNTiyNihX6tXZ60LeS0kDiVcDAR7 k9nKNhBKqCQwbRTQhuBd/93eWVoYo8yyRdiOz+xXW/5LjbA1qnMzrxsJU+gZcCTWjy3bRkwU+qCn iEl+Gc4BWiFCGOIEUq+kCj6v12EhcA7uApRumkw0L2c0jJ73SIJchZqKtrvFiIOrc0jpULR/M8es w4B8vDLrKXtfSIPKOF1toQ4/2xrETpAPSGtSCqgdm4rZe1PWLZTyrKBxAPXY5HXz6osxic8cNR13 bL4zp7BglAPhUl95pZl3lgxVfB9fVeXiN8l4lq4/PC7kO0g10pJmg6Y0VC8f0NH8+i9pHVnsQzyO LI5x4HwCdIj+Utg61wHDL0OO3Dv/yyM7RjWVSiHIY4B6kYQ02S8uzqelD2ozaP1Jq2kPnP4RRVrV X07K6OjddJlJOBgIkI57XkngghDc4iERptw26KhJfi431l+2tbJVPhN0i/MyebMhbV+lnvhNb9xq +LAPsYOzUp1VkY7YSlv8696Q0ycQ/nOHT9z+2vhCbLCnxEOMH8dDokmV1mx9uMe7mfzkgI8bbd5B LdvXQOkPe+OMGrH32aSioOaBN0nM255GRLMJhFAcBJxBrG8mKeh52iCzrXLnmZutNok4usDzKMsp jcW4BRbrQfGdrUMrzVGcqI78//XDHOhDQalgWelKsVw4/0b1R2wFIyOFSQVIWKQOfvC2TcelZetq kbanW+I/Q2Zdy+6A7EzZMEZumP2UzjGR4Wc3FFC2bVY2ftqEaeBbvLyZuYNCPFuKHLS+969pXv1O dJoAea50qpi8PMGNKyBww5M9SoRaxiuRCgm/1QXuvbzJOxIvOBifAoOJyRKDKI/NECuWxIn3rFWL Uks/B7BzLerIBwNWnfeGkMkzv0CiQTZ4gBiekZ8K9qLPmdoMPgWZ9Z+l9OPUN755E37UmoRym7lA kyfjZR4EJa6qwWyPkaSeXDu9Etoh/FrLuZek2/6PrzOqkR+ep7lPql4xDIT4eWYHQdPky2Ei1dz4 7amMWXaogfUdlvFeLW/r0ewdSb1cuDJ3/BEE772DPDU+aVD7ojNcp1KB6DN4bnrkxUhlA8aLfjkf U+KpTLxxjNukHib1tDEu/l2I5DwRYHLrl8MOKQF9KHPJ6sJjUJ5uQFjtkgckBC903LdvbighmaSe SqvFcuaoHsRDVTzeCh/Xx5oE7HBu76Ys8FNy/x/VsDRsF/WN9bF/MkY38RtrdtIXqO4SUUBPrvCe P+Ks6Zda73Zh2z6guGhB2qx2JWYdeow2voEtQpw4X4Gssa2DMgqN6P1LY3fIiGn2eEo8E/RSf5LE hjw2yvVkYm3dU2CJ9+dLS3d0iTjCb77E3Q8gorFqtP38HU16yzrXb3g+wNQExRZC6JUJQ/eC3hCn nV+3PEaiBSoDDlSBlVrK/LZgGJpIlA+zpA5mVoJX8vXnIHOSluG46Ayut4vSiV8Mir6R4p/cJEfw mguEiMeeuJkViHDH5P2TDhT813S1TDQb6Il5skdBmxPuA4BDFFpVIrYgjbLejqOFzg91b8MUjYC4 M8oLYLv7hxFdKB0lFDBZUHBnC+uDkXD1EoAREE0SHWj9j9Y1HivhhrWZ16HbmQ2jm38IkJiODhFy DEbfEvkrk5Js9m3zJIvhuNtYaePtu8KoeSTDZjZM7bABLYgLFZCNLKIEvZ9eHPQ6/TZ8640GozjC pynIC6Tu9R7yxn7b0XD0H+wSf1DcS/sJTK8a7iF2HnIKITnzrp2+zx5GRvFrr/nzCrrh3quLv2pT 1Rw/Ljz7TPJeEqXHfhGdI2a80pbiLZVH7K8on9nD6NdLhbYS1QE9J7kRO5vk+fH5jBGNuEQmLGKN muexJ+tfImyrvA3Fji/LB40v5bNlgYFvCAbJPHiS/e6Bdt65aEk3P00yb3o9EMr24bioERl8pr6f cbFDmaVnpsazHDtiLPcJOe1wOpQuLvMfYsJEKAZEZUjM+gTS5y/NIBdxnGjsBFr5B+VQQ5T+x3Hm iEMQ69A6q76PlwEDT8LcF0QRAi1DVMChUj+ESUVOBtpqhv85axcEMQq9uo0fy696eS2hPMToPvYu 0IJNOZ2GBO0b+OatIV/15vdUGhPbc4Z35r2saCpaJJwaMl+I4uqYFwZ0tYpLqVNfP9QUCLlBSG8D Mxbkjm2SJyUSLZZO9ExZG63msR2LEnJtepY8UHbJXXf/SwPSxiSP42qrPPx4ENozbmqzKM4tUlPv 82UiK5p5EJ5j8N2gq87tAWUmLbg7x4FO2gMXpj6PKSMI2yOjjgaGOG8WZtPW2CEg4wDRDhHTsa2w t4+fXCe6cyPXtqYbZDCk+ZgfLETrPkTwOEFylX4GI19djZt4kvXEFCRMedyYTTtKYZFBTiIVsotn UeVS54cyT3NZB2UzGx9ILoeZsOpgV4NV/IAeq6hPE00qWhmlgn9p65UEoGJgZjHalu0tAkC+3sCL Nyq+cXhmPmGTtOFYGoqj/sfjOfL1bENql90eArfDixWC9e1AKQOp6zOkJqJ5oTK6+VdQNk3LuWtc sYeN1ioH6z2SoDD4DWrwMj17yRbcW+/2eI/B+hrLob3sz3seNUVJ1anXH6O1EwZo0LfIzx5gsaMr 8a6VUuduoyMxG6NcUiUOZUa987XbEZ/lstOu0ofbiCY6fO21B6WEVXfLB34hZ0/TJbW9F9y9KAr1 RU7FzDshSoajqN2012iKjK5lWQVX1qa6qkwn9KVNl/Vni8+F2F7FkfzfuySAcGDOakmoek5TmZHn E9WX7n2yHeYq/gkLMlfxoNre8htvS0zvrDwMCtKnlKFoYti28UP6Ux9usffYB/US9PI0vljtZsRG WfzP4OcwAMERBAIgiTUB6ZKV2KLdDxLwMJjhplv6KbwleWA2iCEIEgzox1cklpP3Mk9zQ1mx5tIZ HKZMsLhoj1QpIuIdlI8Nc3V9NT05QpmHc81Ysq4XRLA98WNNAXtmdtWPSEcHjGPBGwVNvRD9QwpL cyt6s2IL8x3z356ZJMEz7lfBLm4674gG3bGv2iFD9AeTHms7frj50zuF5EfYiA3Mix4oi3poZSwt YkAPnMnS7STcupr7rXLuiYg74q06qHM8hOCjkUxlcAc8pcQs9TzCCAMH0y3yGqftvuXsF3F1OzKS 7ZPQmabs3qlWF2RmHmsYhUXFG86MMKQ4t8NStZViMct+YPswTF/D4G9EpCQUUeF6LdM2M+Zv3BbJ CixVcP2txYlvvP0KU+mdX3KNthTDw6ZsDgq6VdFoEAr7odqtLczlB+IKVsUGdByBsI4TWQDjuDv1 FV58DJrMpGmBX33vBFymnZbioWVAtFL+5zz+MJV4QhBj2LcgYAbnbGL16N+w7BtJZjGPtBdJsB/M EHYjkISb0jc3nLiJAZqVktMFsp7WLROQqLvxDWdCb3cjdHrgZe+uCI1PAX2RHFjMcgwSusBeLuX/ 58zDwJ/hU2hUbcrpx5pOD6pEry0cmlWgdmQsy0y8zf/iOTiUgO+VZDgvdzGUPFqNoK/d0R0OfH4p QZJWoJpOg31sR7dlAKGp6bMAJyNbcBaJWnfJYtvEQX/T8YlP8zjv2sJZexFvhgxeSWQUexdPFOPi Nd9AbkTHUB9kkJFfYPXom9mLr9DSzSsHrqIq9jEaR/Q3Jkjgs63x3m2coNnhmTGMD2aqlC8VZtHQ Ua23N7/Muf9owO58cLPs+zIgHTvupl29qchcJ5+zmg4IDPdD06rCURkvyjiReETAYJ8R3a6qDHuv mhkL5YmSQJrECZPKdZjc8GEftWMd7xo0dKz/xyvHcDqkzN8gjey3S93fJqsZ29JchRR2wizOzAQ7 DsjAloX/WDsa7Q3FgaiVSEDn4NJIDs73ysWzs3IkMvH0IkR9e1nHSOORc2pSrp7+D7qaTAoIq6XG h4yrs1nk+ZnmuYsfVxQmZ6iTZU6HM+L2opKjpTwE1vmZcnaN0RHheWpscWYA1TnXUMn4WJDGIRwZ AqmLLJmvrZ5DZE1NOeLLdpCas5gc4RkdNxTSL+VdbtxwVAhUdIFYcq0u8owkoOKKAaqxa2eJgLrm rPiRp+zgN04Tx+v/uQUOgRxRv1ep3TYAh0Dmcw82fLR54zeEe0eRskOKv5QqIpPerRa4/7yDXowc G5UwrNzQJPVFNmv2+JjXS1yYzuOYOyZ0p4oQW/Ua1fMANvaYzQBl7ILKyZi/VoIHMVqa3hRqmAIL nogizQmbtffjADIV1ro6h7+ONkSnOgiVrvTaLLLw73coNWAvDqHgIdrrdtinJwkD9YtCGm/B1YkE /xveLF+MERhk5a7Ehjv53VvJLkr2t4mQQUOgKDQWafF3YIvI9/OMBq5bp84ToVmdYKLJdsRMK8RG ozBhDqHfz38c98XrDUs2VHmLiMbkvjzhuOPln34VKi0AF3IAK6o4bRwCtDRT2WoGlH8c04ZXhI+w rg9amfZEIPl0hx7uLVlR3Fb/9mdU9VBVcAP1tJHWUMlojhhpve/kAl21yam/GBBgRj+QuQoGbe0u EM5q2P4yhXw67uH/mLijwV8i318PCv3s0u/hdL+1Ib+G2h1Rbc696iPu4aN5IOYZzvNUQ10X5nqF sPlq/Eh8HF7zB6N6G9omVymGnTZnXGdNKNucma3NwJgIjeQ/47TdS7OSEq20Cq54mcg8PFPc3vGD tLm4MAJHHGZqcPUJeY2qBrYJQWc7Y00hSAhAsMdesseHz3e7lWdOTiOtGeme17l4okAUKZNjtL3v KsT5oHyXByLps7xc/TQEwH2EICD48BnpG4Ro4Dio1w8N1TWW94aZFZqMmGY4zyKyYRfiNwX1awus 09mfWhBNdL9MkSYrv0PoONJQqJbNNHml6G5BJJhVwqZyiWQbJCtgGY3pNDFNLOuh47KYpXp1ssMX XO7D5KtU3w3vo1ZUCnMCwF2O4afmna9CKnXxb+RFc9QvKx4/oM8c9JhC+LgFVPJVmUx/uRpAmAjg PfWg89y5767w/m7WBWcaRBwxXqFih7CFB+qdLQP5cPDAiu3VxqMae5KfEzqSla59UJK95yI/NHNG i8KyYNDr2rOrP/rR49Ld7nWVjbRnkRztp5exXuxW/MRuTyazBZMP6qQ4sPT3OHk6U0NlaiRG/xJZ xZATsfxR7JmWzaPsSoZOWSW5eYhtD/0M5klTqbzaO6mHl+G/ZmBSzxRRuAarr1Jh/CO6CoYWB1kM B/DnCw0Np8/Hn+PNvBX7FnQoy3+wz7wyX+jAJ3BreK770d8GDZy92uKhmKNJzc5Jnl8ms+S9X+zk IE/yLFSRW3XPYvXcshJtdzcOYgR/JKSHBOfxQ4s+QZ+bpmzFcRSdVno+/uxdGqjU9WsEJicbPw70 nusU/RmldKjGlGrB7QtE2E5i34Xn97RFHNF+xHquiwdzt7i31yGZ+63tCLWdiQ/FnvDh5pFOyoS+ Y8I6gCGEk273bhJcGy/+8pybo/574EjGPKDP6/byXIdNRteepfLVrFaAC6ewM3KxbTRic85yZyTd j/0jmMsR4YgadPVSTP7shR7v5lmBb0ezECg5fcHRfbUbWo4B5P9iDMqsH+yA9KB2OZY+PY5lloCS liCVb/xBz3ChSWWWA8DZhX6j44Ix4+iQeP/jhzMmv4JP+cmsN1RTv998JNe83QPa8XBPmO0DvWQ/ pXkdtQlQIviANwJizOe6Pc37AyhWUKEr5yyaQkYS7HD+FI+1yJEW+B2WPYIQpz302FzLXoWcibnn zQTPKwMD9TDD9dUqKmBUSD0LbW3ml3t+sgOYq3KgIP5V8x/ALwykrFTjHmk3OFG+w3fl6RSp4F+i xbRymijTl0ofE8+6/vSx3WSXxHZ89Wx5jRg4uNPLGYP7Zj/Ozhr8OqhpIU37Ye6dCxW1yeo991eD VEZC9EVVvi6Yk8ace0/DIJ4a0X8xs05Mep+G7i5BAfvnNUSW3xS2f7zHlPrAcsKAT1QiJLF5nT+a R8xiXp8jlQEwldIvK04w1SVSk4vrvVyKAbv36NBWiJ6Ej0OZnlgjsig1Vjro9ThWBNFIrWZJtEgK 7agps5/rla7QGOH/a9DgEsPVW9XaiX358ztZQM1QvCaxMNc/8dbF/RSyLF0zZ0XMTjTmVnO9HMZN vA1OWM2x5fKHviQx/XV96yuTbIRnwYCwrpD28IAhNO8TJPkMJoAIOEbIeae+DQOPJNU9uJj5B2LZ XCprO6xH4psu8CJvdO6dQ+XJ7kJDXh60Fysffdly2JnxAIGh99hkqkqJRrgmL2OOXiYmvktiBnJF /OHvdUBt3chl17fePunADNukwb44Jceo+GTdwulEv5MQByFWkrBYxRum2esfkUldeNePOYiitvSF CoJU6SCtM4MqmiU1rp7hsrUZDXTICbNz7tgmLiGCQDvzcN/mpWl/GSe3x4Eaj06Atv7hMuVC+Ntt lcSjt0eFdY2zMQuAA47MIngH2HJFtM+aLcoqN4rqOxlrm/qJLryCZeVTUZI+ewx+7ecFKeQBmtJt 6yx6c3MY8yj9P8WR0vou3xrQrYkQrKI7BWdwqo8lYB6sY0PfY61nrCg+1+egmk/v7NrWaDjf/D74 DEJrhStPeBFOpKLehFR2b79pzN/yXwZqqeqbYlQkCnnXZsVUHLrEYtzg+BWN+IPXwIQeMM/Ylvk+ pNmqxTubAHVvvMgwNvWgI/8YDeacHP+LGi5UZjxdp5vGnwSDWfGAuE37T0EobFLY94Udw/ZdnS+L rBoeB+A6ulrhCY1SGcJXr6cJG1AIqm4AA8X3TMkgiuFvk3RVGTSzvf1Mgo3cBluBNiAGkA+eIIX0 CIze9o/9Yhuuty5W4ogUhQ523B6R2G0XFoQTiTI6ONHrE4I4ZHfzYamdZVF254q8l8OcQZgbwOrF WUgbcxXrf2J0rLfgET8AIWDmT2H3tswCqRHbXDzpxe0fZCAIhFW6bOjCmTwWFfO4LV08vf9akmf0 pghfuLWQFj9iHv29avCqx9udb528Wm7BYsVPUOf9Ya+gvT+fiUlzztbgas/pdpn71Glw5SEexLfS 4YkJtno6YwMDhbppN56fgJl6ohwiLPQjc7Kg8zk8MHo3K7yqKJkRLH9B9g29cxggDlkTxOgxksYl AUWX9hzfeO/zbUSwlQg1bnry1Q6hQ/OvqxXuMQYrV/+36nuPfsvD4NACkQuHvb4XfbNGt58L++VZ 8+SHm2Wb0jKanGxO7+7dCK22aa1IbnZOani4fAZtAlSwIFIEHvXTiKz1z4suGFwAPBSku8dVQQn+ tQb5b2hoAXIZ+tfhosoWX6/02LtXb42XHsI+PBvxYmwXZxS63aNbWvuDZeQYK2aXZoC394I4WrhQ sdQLN5ZK4N+v8K82QMNKuV14d7zismtKdtzNQsfXuGzRSJWHDnardAV0zH0qWGQfFKayUFpgaQPd YQhubNCqF1O+bcPcvGyziS5AsR8RGhpRKzc6fDNRkCPQ0KOPTN3SdT8s6OiQKEsWkdCi8JKpJHZL m9wqXFoeJfOx3b5lfqMLEqeK8k/dNw0JMH13I+xt9JPYaOMzQ+TB8PJY6sgIau659cQGM7xNeZkC V3eads8plMzLEjUhkCvKXRmiSyrzbHr4U0QEvJWT8WPlMLh9NCx1u+8eHzHrCO9PHUsDS+43pX90 z6Jl1VHbUqihI22gPYgLIJOKfsP2WXW0hlZWzWHvcRS52MxEh7ODB7Wqgq4j1TJFLSJuppxvrDzv tLUJnVYg7H3/RzUf1AYjea1hcjcvmlmP/8WT4coG1YhaB/HANlhb7iOsqIWKPG7sj6g1/w3Y2bif CubnpBhqmm+2Pq8ChlwYNwEtP6lxG1qdyEvUyPDszd6RqGMwP7LdbYl6+QlIKuu9m5pW2gZ44mLK 6GpprdUsxvh+ml1tjVAZGf82KwRHpLBE2eIazZspeOHbt8SlEjj5NlwCsdyGxJZ2UFvPfFkerWtz gJJy30weYiYw6QKpKA3FBt53uN/im8DgpZpczXfnMz67zHui+81fSVqsjueXlyhW/3i/yo05eqHL ZLmzoLCUjkOFeBRS+NYoNF3dPxmK80AE9N/qmQqC7jK3OQkXmNDOTFwsvtoP6Pb/n6dhLkRnZlML TSOfAREgrfpBFqmt46dy3y1MpZ+Qa/oN07qgbtCkTMyBp2RBT+o6Y+CJc/rFxOGgE/ZPuRywKj6O 1JUZNZY04gnuirRyZriLtZ7pebuTUZdAZ1CVhTsjb8MMISZn/+f8YEbk73ShKzPe7iihHe4mzhgg djQFfPxRMtnqvF5zdbVBlj55PISv7+34wRLLn+nqC3xFxWuiDyZke+pNiZK6JGCOxuv9ykEkaNKi itdDc1eIEfbjgmR5xj63nF8EAPGejSUXMlPi0j3jOUNuUDmT040bqyMq3w4IGMj0M9KN4gwLja5/ o3n4++To4iWV54fip7DKOKxR8+Ai3EIEyM0hAgb22P6iASmp8/O3FFbK9cpEKsHEE4Rfci3130ph 3lZ0rIyd5eB+8uwZHbeDg4yaEu3jabSYHASF4jNQu5l7yFX+lZX0xAWBkNI3aq/MGh/9ckTCf0pm fZ34ZL5IYZnez++BXlaH8LhKMxPXqHwIL7FH+uBw6aih9LB2NnmqCO2W/E1ToAQbv959mvw4cP4j B7Er/ZSBG0PfAPl4kmpIU9jNO6wVMOP/ZIQq3ZVW8Y+fHvU37cNaFFdRykXA8he60dNXo/CbeD55 JBANeE6SZez8VCKUmZSN2c4wlNVumkVgP2CaAqiCr4uW3zNJ5/V2sHpM2Aj/diiCN8vufT+D9MGj /UhMNZfRfEO03jtusnbb7HT425rvu6scPOlNTQH0UFohWN19ytxa2y/6w3SuAKcK/45LXOpNzTZR PAYJMy4MuP6e/wdLzC1IMucMKg2HdX7aH3NVJiKgFf4Ee+XnzAnvmS/kYMBpYjPNAwrGMY5u4Kqw B+Nf5s/4sNwxyxUDEdLN1ESBf9zbGDPQidoK+YfORgAnGhpic9b+5To6Xs7orYX/MsoM5mfyE4S3 riIJPs5fzk9VdEDNIr8DvlWWBl5m1b40va0SLXOayiqfXLWWJIGS4916fWuZngWMeK5xCWyE7kXg bCEnIRap20Mp4RyYskOVcWwDoM48pVTmCmVIVwDcOlcpJMewvH2BTaAYcjv5iwEDp3EcoXMC9Z2V 2u4huAzpRT5D9OhL9Y6iHpMahTSK4L8sA8yXuYzT7OrRq8Ikaw6eXdzv5jtUay9Kqeb7A+Tv5Zx8 eyhcfN15z+Kcc+LibQ0tasYWdKWe9PjANQ2hUpv0wHA+ZY9DWQkB6dqLFjHCHleMLnXFe10RmJ0C LGWKs8WXIYMx48kE3DCj6mKZqyiiLD1cgNsP43IJmmId1qsISYijzvrr5D28CUGk5zm9NDqe86Mg bw5OpciU7Nc3v4mwS4ipe8ZrvlYlLZBlUvWE6OB+m+YKcJBNKi2LmymhaOBcGT1+8olA3SIo2ufL JiT3C2Ls0tZPbZl1mSgBKv0Yr5f41uVI5Z0fQBt+QN5PEJFc9n+1RNUat0aC+/0ZRYEPzbiWx1kk IF726IjOd0fkeKj14anGUMQhlpBLoJVDCiC6qngYM7PSeNoZ47mkQ8tnJM/3eMG04khaxHy3ocad fwDsHOeVczl4dDJ+JJ9MWPW5QJSlxUPzbDP5GdmF1cRWDmV52YW6LeEEDCwzU41ssjxO9wrbL8nI LdvkvHiNEQAttz44LvRUo+Q5SeCdHFpyEy64HpjCojVbZPwQjIhnuzRCGIrnNmz4kYTBC6s12YWz Prd3imlva+uCilIh8EMC9r1cpb03eMfVWZuWfsM4j8r6CzFzFgkSMmTnfdQ4bTyoaDOojjqYBdJZ E1T24/FHiDamiXbeDktT+owRrIqi3Jr53X67G9DYB7l4K3xkwdbiO7DXIhoraG5BdrcgmUGU/bcp B7++5/v8FtUn9c7wGqxackpjUjNDPiR5c82oT820kCsEjg9C3kDYSaypXok4I+gKUuhFMdCMwldZ kdb2M1s67X2JeIzIHrNFpGlr/yXO+XSvsP2w1BE4tIgrE5LRp1ELrZd4S7IX2fH7nRg/rslVt4R4 iZ9XThJFjGEUMZxglvhjJbJpaj1xueVU5gzbQ488M/KmZHpOgvB1PnsSMr3s+IOK1X/alu05F3hD D8TE1AZXZ0RyzmVleRZhCKdGOW2Ky8MEAmeZc5WnviyuC1QyRjuEVl8EqVMZEQUZ8eXaKl3MReEe u/9FsYeZnkl4U6Ip2LivolnbitpDbA5oxJD6DxpqhDajpITGgVlMDQdA+pHJB2PMeii+ARjJZGVC GgHiTf3YhXjX8cM62kmtZjoYcNzIx/oXKB3/Fl5gKt1TteTnn8CsrikwGXR1MVoEsAl6c3SCGUu+ r2k1b05HcBpCku5leE1qc8HFJ1cmt7p0O3wfgREptq9MPwrOv4LSIAOjCOMDdQK+07E3uokEnSkd iJRpgY9/wde5ew1ZfgbUyb28wUcxxgBL8jUSUJISgWZ7uI4nv8GUA8qjOBQySQqJ6iG+xC62sLf5 HEvf0iQFxGjhD7q+o2dmWWCRRfMSqzrcaSy2b2lxQEN/BkO9CLAahS1s7PFifJGS5LzcTcLtSXMS sWHIY02BXrQIIgKCl1NLgiz977z6Sx1/b+USOKZ/fwZ0dIjAi1UZM8MR9WrdfoETb2uoKYQ3f1Jb ZP4KY1/5KNWh6AGejf80ZyXXK8Q1QNUsRE0PzzVvNRafXZPlfzwMwW/qKPij6yK32WiQurUoj8UE 5Cxa2aEECZVbSk43yM5SyCPRCvzkPmY37jGfjMI3ziUDMi4qTTxCEi9bouaSI3523jeQBCBFPQu3 CQaZq3dhGLqiZuuXQLbB6/e7pSDzwk+qzD8DG1ludDu5LjQX3q7Q9ibix5KgQpCrHs6Z8fM/OK8k QL36Am8w6LEdiBLPu4WNL+A6YnLVXbwfOjYtzipQSyuu0L3advVJ0+yKhpzUcX8NxLACMbeGj9h9 XnkGP0Sk7s8BL0JrhhGXXAk+8JocPWO56Fib2oFt6CWzpCIEo/V5Kvz3WfD78eTvJz1Do4T1yQhK cgnF14/3muCBP8cQT+gpRlDTx1wNqo7pj9U2G2O3X3RIA+2XaIrAoudFTufIVfDQaQLtusBcWyWH 5ssQ5S2u5nPhQfsGqd9N9k9S/xc38+YTD7Kxy52ybbije/cKv4keiN90wtgB+6tyDVFT2VfgtU6D 3Tz2krA6jPMXOBzMjozRmJj3pjqj5M0JyY+xLXAmX9xMrv8p0XafTr6JFII3/v1KTHBp96Cwisao yb8+WUi+6vHVKZU0mDdNTQqj/S0rKOS8RipCL87FlLDnJGW4WgIbEXCEV7ycmGRlEmi+AllhsqUF uKfhHKTtibabNHLrkb2O03+TdpmCi0PbUQr1rIcmnHiRlNfzvE+qjl0EeoKwwq+PTijUE+hqKKKK HsbAdXYNdjGsYZtL2kD6pMtkt9HJDueSNKyW9bNyc/kiYljfwqUiwt9svSO7h1VLmavIwj0Pgz6G 2iAi9b8QEU5d30ZLCPx28mNwwEYXZQ6vAINsLn/YaFJfR92ycn1fSlNpE1AE97P3Um1Bo80OIUKT mxAuUrVaQWUolkoOENqlCKaxE8q6V1LAPZOI4XyTWI163/i7wKHYELSpxEAOOwkJobV6OMozlrgg mUTNrtpck38YpI3RKTLXbolt+ZU/xQXRFAsIoJdBVX34GtyzsosEUItazOEfkSlwAOmy9vbTpg+S Y35VHpeL0g1tQQqlrE//WFYVUqSb6cH22TagwdRtsUz4Rx/vohNABndpfZO9yvPP00Ok1vgCJyN5 y25aLSw/ahJKYYlpftvdhaajRThlvB6EyHGPwPb6LpNc1XqEB3ZJ+eYeCROcGP64CyZFBS219TaX tHtbvjcpJwlsQGAoWGBtPY148pfiKGY2q5LeXuCN/EVMC8ObHM/fJtPTZER/5R7wyBvhkb6lp5Xo k0j+ZsVM0eeRN7tUrBK9xdOAoSrJxcDmHFZs1uYuuhs5EZmN6K11qzUc5kusEDOe2077wzBIdHou H5vJRSBGP6VRVH09BcRvchr++lOYKwjgUOieDR9GUf4tTQm7xswbNF5TvmZZP2K5lrCxAYZUZX/B xQMzyrQ8nJBj1tE7vs5H0L72OeeV1Zvptkn/nSJKaaBzeFL5sEMhActMFtZF/HuLWD3+kNPjsoXq pOpLJ+vFp+v2sqrT8nx9CV2OPm4Iktj6oTbWnq+cgR2nOs7Zz7/GOoXmdrrT6N5l2kE/Z5NhxFwB A0NY0h+/lmCDJCDe2W9yl2uNr9oVv8sZBcuRCFN4YTTmoB2j8JDDpHCN8jPemYFpisayNeEYf7SP yQBlN0lVdrqSmgnPjVouJP9HTCIsF/PXmUO0Dhgq+F2o/4iIHFEj5Wt0Pba6YYi71cMXf6nniL2U XkbJr/U5T6jMP3AH42zEqcrwEc9miegFeYPyuFMmkNBpAadqmxpRkKsEvd/SGX8GsKgMO1n6wsWH g8zS5RTWSzt6BnsLxSCnnnEPMQe0BfiG2wfKrZFCJdQce50TaZDHwhciBm/iYKv0pEACMTloQMku ZChA09tEdL1u1jlSq/2C1oLT8+s2oJSX2mThtD6al2z6243Y1X6crErJnpyV37boXcYz9TVU67AX JFbWK+48A/NlsyChtcTNSD0BXBcc0bZYzKEPp11p7d4U4ewBY4Qx2hxdDl2F96W99bdVDxSTOMJH WnfmfTOD+J5rjmVXWLUubEVrsjdh7d/DlAA70DEEGSE6hn4ghs0p3wMcZf7IQhJOUx5Uho26n1h8 TkL0lLOTIIzuZ5E3W6ee0kzjAXSUUU2kUPluX2hwRX3iuu2C+8im7PCjq5tCRZMCKRdmvN3ovhzG 2mrs+PGREZ2IiUNnCB2OjTqBaRtM+4QR+2TTABDddft0qJvsktbBNzttnToP9yd522yv0cnyhPKi KlrRjpW4i5lbmj2txZjrIU36xexoUa7XKd/XT7LiqhIAe8KlY3WDeEoCHzm41bXZDI9/RCBnoSQu CeU8Oem/5tAlSlyM2gZ4Ziz555z/d5oLRhIWTaDtTqzGFfzZXTW0d3e//9DDqjTNMgJcClk1fgDX UW1uubj1hxhPUvw4Xpa4E4KuxK1HWLbnlj3PQmdFcgJiZhO2yar1SMDCKXHDf+Rak7CHjqk5Q9mh UWfsfhvYf8zSwRXv2Zkj5hrFDaRnxUhZGeH1TAPs1u3Cckps4vmK+A6LzLVuqMXmRd3ohR6THXzc /RLmJol0fdG4lj7V7cJUtAAGVmSFWJ8IlEFjUppoDN8JxnTx++fabAb+FVwk2Sw+STaOMwyMkcsx mNXALSkeSGnvV0vPcUe2TRUu2i2bq/PmLBLaXZtIUyhIfUv0fOeK8uGEG1DomxGkORWXTjo2cdig iIIsOXPLkll3a14e/Yk55/bY8DAIe0g3+nIhBp0y1oLEr7cqBzv8EI9kA+VD45a7MGj4Ko2T/Js8 zHY74u4Y5H1FoH416QK3pfAQnLRdtuSQPe0WXdQOVw9YjH0xEjBINmZtadLMdEQv2Ub6EO/zCI0z XGKkMD36cTCyj+szTbzD4ELv1Vmg0/ADvsLLC7J4I+JekeVpEJzuwUWs25ZUNtWWfogJwuQKcPGB qNqwU2D0KNTSyhWBVVN+94skum1M8NeSDve70+oxRJVcrLGoWFgxYpvWKevVAZIn72gXhqMMEjW8 97oNc1HYn0oDq8DQUV5yK5YdYDkpu3UL5ZAz62CDvHJXglu88rJT5W+HL9jPnC+xSpnKWaF0X0oq s+/AQxBhgi2QoOQVowf6qT5wRtw8/N07xJkDJ+8c1+s4GPkk0ET1AFJQRdvvWJmT/u5JKMxj7zT2 d8PRLumeRRycYaLa+Ij+ThAvjHJO9vTXmahRS6hEZtg1VUx2p2K2dG9PgEl16k9chiyP49ijNVwA IyGiE3RkBYFFuHeQc8Y3hMtUQEzrQ8/8pQmNy9/OhO7d9270l3Z9aw0JrrmN3DE76hm6gxDFmlNY PWquIsBMJGt0BBAFP2YaQ49I181L/hmqFaWiu5GG2m9XaOel6StaJ/fTS9wDA1y2WVJIu+QDbAu6 VZS997B9tw3sOGgRFJmWhDKE6vX11rpHj3U//wA55EnwiWrMqZxgtcQ9AMBvvI00PR7+hui9DpYo DgLqTY+IeN9OetCsMgvVfdr3o7OV+YPGRzYtn/SsqxZhZo2a8cX9R8ejqtXkRb6yw4oaC0nhZjv3 XkZBUmHxiF15pRBPs23IYsq1u/OwFsRLNC2CV56D1jg9xzZkX46/TjASYD31EwSEj7wiegVIptTN E8lPX0gCEq9NCohFNFRs4DHBHrcYnEf5VkqRkl67iP2d53XMHZ95YBF8Ok5X+bkg5UvxYGyoYnM5 VhdXtiafliZhO/tTbRJlfzEn7RehgIXBmDwC5HXTW/+JIsD0xTVt3JcJOAnoLumwQGUwVcWcr8Rw pqO5H+53jDdl8sNTORmvTm6a1UvMNKDidhV6ezVv0ehvkiUrN0aVlwHyD3rUfWUGzlAKHqyEuWMI +7F5bE1WP4+z6zEaWg+os0YVoFcPGyaSuc/p42yo/pOn4Ssez8e6ANst1Knm8egCUmy0dunWtj6S 569BHSBpl9VuAIfl6PcvgwTAFxmgs9hJRmtGkv9WjwEZEYHMjzxuROI7Pr6SUKNoYkQl5qiMCh5c JHvWApUWxvdSjSfnjrti/OsNBRNTsuFY6F5cZrRFk0PvGOY91+/xqme+XQ/kKoFN9aX6rNYLiijf 0IfpkPEskFlsJ3D99S2MnvcsF4ceA6I3H+y2Pu+0eEyfTfdByMhUj13RuQFUOcv5wIp8FP2vD1yK tS2OJbS/9xafiXX9zjC2PrE4uMjS4gE/7VgEsY9ZcW0QRrPffM2AkDEihE8enopi371VT+8plcn9 7F+++IY19+s90e69nw8d3Rz2PBJ61gvQvh3YFjYVaGVoC83auSEaDNqkmx3VTOYGVZZ5/Vw+m38l ZeOb77WbHZR18SdYL/rcs70rqV8wjT/Fh9uh2A5z850r6Dl1VNTFG2ZvPJZPR4VQFRh71KAaLJ4h tdsDcN99VQAvI+EDAjPK01afkEGeuyvYjJbHF/srsxcqIlwrQOEPS2dMVaYGD/3/zI/B/41N6E8e csm+IZtZRQQTeglZAlh231fHYyJZrBzAKuMgzv5NCBRLZmZLSqW6cQQ0dUlgGPent7VPTwlyMLPR s0tu0x44qsuJbvaTAWORWPQKYnZoCpQKK1hd9cXtql1Viy6bdh0Dt4cT6vW6NcYryTWn56NEtjYT 8iqHYs8VojtBWS9Wii+TX5m/LfQvqqHCrRlDWxzkTBRWEs4BZ3iNTo4At/F6kxulzMk/YuZqattr K+RJRGfaeJQOwD3XZbjhvfqQdXS/wHXnoy92rM61xTLXLw+MOByabHaQZnmHd8N4ZSPHORnGtikJ 0V76YbHce84YDQPseoizvIMmuEU9d9eWcCqoeDZpvjfbcWY2AP7iyHs3B6vuWMcpl1hX4w7jlPvd dOxOtzqJGdg8UDIBgO2ZgR8zMR+2upyUgyvdSQ0gAJ7TYGV2TbOxIq7ycfO83A+eu5eUAcnZQNE9 kzKssfSRO//l+LPtQ0FuajJ4Npt7vgAoqR+3pLaC6ff9EmfzW7N/EqASgAV31UQ2cPXHs1XNhmU7 kLYpG1/l4fA3plGLWNMnOtAcp0+NaDThnO3LiZgEtnxtIoVLA70/BxnLKEb0MMFENJh3djKw02AB 7JEB6CaOw0y/5vI5PM7OZeSq8AyRCM8Xwr7q8Qr1n2bj8BsVwcSG1+TpgMvwwvxpPWt5Y8VkaKfq ybLqFwvlK8ub8QS/RxSva0qrFWP6ZGvjfH2VqQzjRajpWkWTK8Is4hP+NlsgemQ7tNxMifyRu/AG Yz4RzIYHA7DEF5dwgihjnRmAL7oWPhBGXP41wBT+Y01oXKkssnFoGF6j4wf+JYkTeMTyvfI4MMRN jxS4rny56i6Njbjrc/tiCgK8mCjaxCrx/wy8t/yAsXfejoHRl/B7QjUtRNKN6LMyNFuCbD5yU68t qEsxq24BWkm2v7i6Umo7jyQFVzNsHtX/+Pt1i3O9jgBpRNmkslhio8HGdS6Pp3pgDOSBzh7HWHWj QbQEfCu3rCuKK55TayVLxp7XlkZSMGzYaGo2zDBa2EQJGQz26zYoXOF9ExJ5BhuKraQoK2c2RZQy YyF6JN/PTXThY8+GHR3h0W8B5wPP3vUUzW2lSiVfkhl8VG9dQsf4Fu3GZrnOpuyS1aObxa6cWfI0 FvD2E3d4CLjU8BHMv85MAc1AHmlXmLnY0lcph3TrQIt+E6G80g+N+gJ2KNe1RCZSjG0v87nbYbcX LHg4cxOYCvAZ8M8r77rXLHNE0PfgQNlgVUxSY7ZwgH/RATH0E92t60/7qUz5q26PtB2RSlQKMFoH jH0zpzlRIW/546kbazJezKTlZSDoiJEf2leMzhSLLvjTGgc1Yq2PXRjMEexNpXvhzkRn12vrzDhy QxPtZ79/A8kEhxPLUsCGDIcUR8bqWQsGAEtVz9MsPXG9LQW/uG2ZCuP89bwTXEiylqhFB3iQKLzt dE7f362yLVXAAs+U4e2aYh0gYRlmhFj2B4TB17s1206RgJoGmzt2TMrgaX+Nzz9MTvBUmnh+6Cy6 E2mjlEvz0xPTp6hT1MUF3WvITjNtMYq6vyriYRDzj3IAANY2FEZje5RPUbmq/FERcQvhAmoIh1XU 6gasyUT8ROIS+ZvBUyY/eZVfwTT5ExRK8sUGGztT3AG2hJTWP+8bAzuXOGayzdiqpNkN/HtRC9/7 /H5tURSWInbYP4HzlFsSHI+CpnRrO0HhuXmqRU1WDMDuZsb4eAQejxlh32bN6M79td2Jbkx/ojdQ 8Y/VS3YwLwm564XDc76FLhdH1O9xhRzINVW2K9trQZCMbHmHpIgB+f/Sggxdd8hewCS3x8/Wi+FH JaYAvnZVh0Tj6Mjo8hNXEL7y4Mc3cG30uPiToyaURxa2DRrlnlil4HuTtRqumVFTjuizcgcjnKpT NkhPobXaca4MnMMZzo0Cihw/d6iyUXWbwg/DYYvJ4WSQtXTieiiaqu5hVAGgDbqiS7plqXIINW4Z hohsFVZ38DX/PtmJCatpBky0UOHRtI4KAaxmcqqbsjqmV6VwyNF8msKCftQsPzKHrdXu5zX7H5nB nCpyFl1DekJ7h7dYpOD/N+86rBtm6W3E9NXILBqyClUyzny7CMKQ9fVGDuq4XF3lXn8bg2P40zxy MWlY88/P9+xckPqxICP8cx4lMMlRPvz7HJ1qLr9yP8PLUDYS5sAZmhs/hLh0Gl2cpG0j8VVJVxVz CX3hSyBIIvJXsEsJgWYWvaNedyIPCowulKS0dcIQXorHxQYNclarOcel2G9eOiz7eFQLxIqdqFWN VIRyeSNYfk0B+9WBNJgk0+D1YDi5+9Z2YSs/minUUQRv1KpE+kPqr0TqQWHsUZhZ3+VnyGjo+H0o 7M2a6rTqJulkzuWmahNGqjZxXQqTPo1lYudr2WoDWqsOfuEMWq5a6pzoXG8JJ66cbozrLsz9sXHZ KUHReP9OikIwvtwh4ZeNR8KjrAfmU3e9g68dOmID1QNjRBbG0W85K/WOqbtUEB/8LCtoMLpForat O9ZGWW41kQ9wBawATaHJ31G7SWEwF0y1Up4W8VTb62Dh6hWpigOK1D2UahIxwk9T/+RRD+zabbag mgYcFyKjFdrpQWX5C32bxACafDAsI/d6x9gE76kl0v3O6T/cl6RRrVOspS12acq93Ia1t4S8pCTy orAvIZtF2kbvKnLFsgZP+n/hUdF5X7vDaCCewr4HfQBI9jY7r79o+ukCg3qFk6DeJSK/WuOJSkh0 aJ+Go8MMpFIlJQ1K6mJQbmZ88kkOFPxc7cELVjLCAmOBnD2xatZ4ntDIF5GBIAl2xQ3Zk6QcFLUN oVPIjnCzNciV8IwmzB1HYHhkamFumc/dl47aMg9RIydUcalnMqooO7qv1LLiT0nahlZ0j+qqD+jK Wycznph3Sg5NzoGJKFBHidg4GP3lOvCYQwvD/hx7gFhM3hBBb6slFmSAdT5Z8xAnOwwcg0MshnBn WQB8tXuWUKyUj6xGVBByKiG++Na2c1SWCMulKLXHAqu/ker+8fZzPow8HqnoVMyDr1Xg6XnjH+vO wkW9vqmL8c6mk83s/rIR09dVdFgWvHDuzbFdsPHfB5czie7Kyv4fEnPqZPnqYIIJHn8GasqGI/gl TSD9auT0NKJZ40JyZVv24O6YSDc3gwFQr+vnoHAJAPKa4FgDmu7ie3tBReJ6LRSOb2e0ha4XAq+t 7YfqtXcjTHjevEPTkSDCTmCAghy/rAi3IF7uNm4+lg8h7Xpge1nzmf4cG8OCMgZqrMMCVVau8W99 2ZRZJXbaiZ4olG0/pNsJ96/UxxNcDlDoe/b++I64L+f9mtcZVgmgwrFBAvAXMiM62OLglseNvWK5 pPT4KNUDWnAPMsCwNad4OgrSoYlgVL4LmfVkjZ4jPQSEZVe3PcJhW2zySXaJJe3aVZPEONWfeFKS kD3jvbJVp823dKDu8xSaqL6j8qPh+yFBK8kwuxqinjQPJ+6wZavTcgvS4MGm1DLhT+zVauvOLRjj rn9PkPWQi0UnnC/8p73c8aNdODykqD5hEwrrRYw7te+enHWbWRanyI8k2EIBAU1AmaneoaZba9F8 Wyk7Fb6ZUMAREJOC65ENxzgp0cuB1g5HdeXCZxjD4XPzVlj1h8DNUv37LWO3UbwtViLOFiipTg7c 99pXGoVMa3CikBuGy831iWoeCccBWF6dOaVPpJnrKU2HPPYO+AWLF9kTghWeh2BOkXomSioagrIO RLdOuDRFhpvH2n9iRWwlPi8CdPewmv4u0FLb4L8raMr1kKb6Y+qzSBuIvyu3NwZNv74e0y/amrL1 HE9I8TQ7E3EydxI5NL1SD00MrcSMFhcTanL2IAfFVb0yHS9eT0m6MJ3N6DU1vcxDTJ4r/czaPJH2 bYSSd4tPKGOHVyjIcDF8wLtTUBuXPWXWyUyXI/f2kdNRXj2TenExo+FpK1flQ5OgK9f2+VMUVkZR csP8HkT6j8IT2C6EjH4TYzgG/R6A/gIdoOY88ZDMlri1q1ssXL9WT4/V/ru5BaFCbF9/HWNa/ovt c1usNhwm8/GyM5+sYLdbbt+Sg7043k/sU0m3J5Z5sxCxz1oLeVepBgGTnVPnQqBayb2mtsvg97gI r2ElfYSZvGC/qCg6RhCBGBX5HZ92FyH7aRDblWrPzwEx8ND3Cwl9tBwJ6IpvfHDIsKxSYwwpVKDe tnrMEQlJT5qdrRAF4vVgzw56KIu4UuTVyzCbvGpZbr+LtCkFoD8ESDJfgMp/UvdlCzH2D6k/ADFr VmDiMH7KNZfz+TsOQ7N7iXtXWnBnm7WyVmJIDz6ohY7RChryVynqpzIgnyJ6A9JFMpQNEABSgUB0 QI0ro7b3o4fBjqV/fE5B3fgUFV22JBXhCgEDaDFnWw8rRwRZhSkzNM3y3LG5Wto4u5zAZe3/X3/Y 2auiBVkyNqAnMa4XfgVeHJUq6Rhqxp84SmsN8JxZdbpG3qt5EBA7BTRjlhisAPKBHJREFLnI+TOq BIXwZyTRDujgyRNIBc09QQmpVW+tawx9JyOQgvsD/S53esQrD9sVlBXovOietracfVSN02bNILRb /J7Pt9+lN6NKll46mog70XydvtMU3AIKyr80ov9ODW28u7EpmduUkeAW3r/t224mHbj35PEoRIFJ Kz4ltWlVJyET0Ip7L2d4Ar4raOvXCfD0QWlxuT07Fypades1LJXvSe7m7cRybze3z6afHol0kt98 7fVeerqF1mI7CUvQfz23SPElSQoW+IZQshYoXL+1XUVw2DKyh+BZH69eVaogx77J6LPXBEc1Dd5v 70Efc1gclKd9S16Cq5djEgKLQh9p54FgoMzIUxiW7vmAWhJiErJWy1RZCUzQVwemvqFeyZBkQ74u RMmX6yKgxpztrxs/oB4P2+MFu5WwGGX/ypXC13QrsQnKptCwZNmfhtrRdpgUDcUmuDGxUjDSdEeg jUUzgLLRsVY7uVfLZEhFFrhl7s05Q3xZnr2YuBv0mcEKdRVZ/5s2WOdirV//UbdAQxiwSTJSuw3K 0oBS0xCAeAZYduFf/Lsc5Z+RqG+nzj1ukwzhVZtUprjhsloPj0sJMt1i33l/vAMQfBmLhwGFjUCh qAAbnS+veXUiU/rbNvxOmtaKglUOeQNeiYenQ1TEOo8e4FuA9ivHDXSA3fclsNiL/15QE9Q0bQqv 81JrjutpAcmdbUoazWc1jBglKgDxJn8SLy9LXKiAN3KeCGyN5X7dSBYeXqO59CBCq92eEhrVICaY aCkLRaZr0JFlQ+rw8oeMQvFedGClV4HLXx8jY7HSEk2Iz+ZxFCJ7f0c0uPf5BP95OZpHnn4Cb94O Q0gAc837mLsmhy8fUxm0GE3bXZaJeFjLnCNbiSoP37TbgxdbBF35avhf6fFgWuaq6Bb7PdRVjWm4 Z4VQg7h0cSxrX/D8qcpGn+ACByCVWJzT+y9+q4gSy9VLDiPcb9AXCQvswypvG07uB5vkoCFjqu3g 7kjRKNKKAXD3rTvXk41ltjV5vCl0WZC1jElz8PALHDn52MuqUzN2P5ZRaQTzbhfrotdnTA/eWPQT 1WjjT7bMinC1QKOs4XQ0mlm8Kl4d1nIru/yO0X4DKbIx9+5r/oyznhj5Ey8s2lvY5+AkdEs/WKdm qNKgUnzXFNtqm4e3Alw3zikrOlWu73IxDQkxFv/yJDtwSTuTJMiElQv6apGeeF2WiE9SP57EbX+R 4vAhewJO6rIf0a4w60ttBh4sTXMA97sDLX/ymGS87R1ENtIhY33KImx4A56rQ16KM3LlLg9Hi1T+ y/GNVQzQqdEN9LJX16whoUbiQ4aBL4gPL/0HmFMi8jZR0EDkkqx6XT/vCKS8WNdXWqyBL+fN5Chq CDEmdpDCRiqWvM6d2EQFz2Ua0oPy4hcRSQ7ugS4f8apN7e0cCt4GFmngQORIdstb1fbdpIQedqok Li96VUJ208Spnswv4zmN3MjdQQTjsB6UtOvjtKGGjAbY1pWB4E/aMXxkXisp+HTy037dAlaV9MLz iPidhnOG0veJzkwOhlx6mUjUiW3vMkjM5vQjCUT3ZeDaXCnig/EjQmSLkzSv/3WAK45Pw9WiRg6d kEHUPXPxYFjl7FmF45SpuyleqZBLgXBHKCjxu2jWeOYyxrxNufSJaH57PztXXe8Q4r7Q1IajXrq+ TKSze7fAz8JOR+iyZ8Kh4jfOn//3l4syQyN8BpCsAvrMQfaSUr9/cBfynJ1XrgnXk4BhoJT3sQKn vt4plxhEhizy2cz2bvUwwzSNx4nmLQ0djLQyXfSfJrBFTTa6z8O8MeHSeZQLFm3Q1s1lEZQSMIT9 X8CKLSQc8YUF7I883AvdlIkYI59+yO5caIraSfxiccw+eM7X3CSxHf7gJPIOcmE3gh94HQT0C7ZW GJCNNU6HnNykuTEEZ77PNoBI6GeIsDjYnkeXroggpDtCF1f6/RLXiReEJpwOaf39DrJYvfEcpXL1 6TsmiG7GlmlVBPlIDaifBTPxutzyTgSDD1lVEQLfCuQNqfwpLxW0J6DlZ4D/VzOz5I/nEEfMfhWy 1XViuX/USnmqSUxUmXHaR1Qb6WoGhHWnioh5sijrzDeZ6sDcWxKvFREwQVc1wW6Swo29g9g2Tm45 8JgCN5DaE8fy6DvqSusu7CXGngP1rhYBFmHFW32VanV6F3R4u3R5Y8cocWYN1oF8UZa6zfMejzX/ aWVSTTSNMM9B+mn8l87Zm/LhMO7957fsUcpTlKX10TQyIAFYlNkGU3tq4xazM9E6k9OtL5BYim6D aOW3fm1haRd5tTsrq/e8C7VqZUUyWn/pAuk3gX7F2FClj53iL3a9dMcN8p6e8TijnlFlPkyHKmyB 2x3UqTRtv9Es2DhVuGX9oYiIxpDS2fvUEBggp0tqFTiabzcI3j8GvZ6fnrwmMX+oMXudqJiK0RmQ sniJX9xvghY/0r3JkpyuLz+0KuWnb4HCI4o16hqicTY2d5WWrq4wqyUYEn2UMbL/xk7zbseExKXo 51BBbSgqLRFhxrWVAC5PEP4floBv23X+/s1ZoGkWIv/aXpxSQfMI2TzsySFwcXjGbdODOeXy3Nc9 r+EcLuC37jiAfb8Jz2z4LwzwlbJkt8LMakhFSzNswvBRgC5/uCpb9iwzcht9/mPMEkOGPungWXB2 61TJ4bPifqD18V4nDXc68iNyFCMJYgpy2ExhNFoDpMwWoplMW6FsLxgmrdA8tQyEcRSyNat67jke ZtgSpvlq9BD6M4P98SH5QwX8xcWU7xRPxsYnlEcX3Xcq/wZincjZ6tNMMj3r5QVAeTJad61ayOEV HSzsTVEai/vzfp2HcUxU2GKtLCcFlreWgHb61zQSJDkGqZ/0LUgP4yTxVqyMv8deMQaN9kcvpEtU EUoHq6/q15jhKalaJ0BOKGCp2J4oUJE2VabqV+XGLkBSGFe5nx0VJw3jv76Ln7Hq+CMrmon0e6Gd hBU/2kDvX1dmA+gN/6ntqOELNT0cGYpAOEDh/G2lPkbjMtLxmuiJda/CYvORL/Ho68OeUuzXUw2n gUz/sihIz+2yPdTtNcoTzSpV0tqXzdGRZFKwYqVRxMzM+sIrE0QhscuaBg7DKR/WJH6MRaip/JxB 7Hhn7c2R5Nw0EDf6jtCtfkf4ev2Me41RYYKNnN33gk+iGBk4oNiz6/qTd6ssdEK0jNNaXbUIqonb P/YXnpeJDggAlF60v8LCD4iumcIDmSdaAOOmIlqm7FOstYvOwN1Hs5r+jGSkCKeVNOH9BD9piMCU c+QRFmN7CuCUkwG9hN6Zk9GysCD42YnVuSMGPoIOAQnITaWCAbQxtQBFMQ6zBgJKHi9U1qlsU8kf KpBxQ7wWBOnE8aE65NUWBir84c4+AyC+dKCOepGSzDfmkSHrSI9oZBbTbkLGtp24J9DOkVhHzvfL HYSergsuE6UPVYzj1tEXLhXUeLqoQJFqLZPflNLypxOomvCFmZkYzClm2pRhhBvpiJ4+GLDH0M+e ob6Q2qNtMJ2l9dvTcZh0DC/yP5Gw7vHYhFdOfisrDOrNy9nKHs3CAfqhZvRE65sW/qErHEdNY6gG Vh20TmBlimrKiPvCA8zsPdPaDQIE5zhx6hcMgi20o2JzFgE7yd64L+P/25bOy7UBDXSLBuS3EvZY hNU4PASFqzZOQjFHFJj/jKnxPhGxklwnWAvMQRg5cxpQeiT9EY1rFMJ6B3DnYWCtmMkUoIR+Pez2 fy0v5En3MZTLajxl7powVp15c4KZbADFQ13l4EFKikSkwtijw9XI7eJGZOmzT/jDPHdAsldB8/Gr 6RzrT9b19yj2xi8OPwuXiEHNGc/+JRRHb4QpEyvEIGVwqh0IEnD5eNLW/9q0DFeDz2lnS5OBsS/Q vVPNpWnlrZaHCU9Gw51+8/0MFkkq1hSuYW/9bJ+gQUycMy4glU00ayREXtnaMhEqxtxByTlNBhte lAplioQDfie2WcgUd/fcUH8bWRxGTpdExsLiL6hwpOquTlj2SiE78xXuWkr67icBIE7Fu+krKLnY MPgNVOvL9f8FMu2NsMK1yRvY/fqaz6GgK/CyXQk96JlBZyeXo4memzobk6IPch/Ys2/p0vJ9wi7D bwinZomCM5fG1FYwWtPAxRZhlmva5XC9mQeGQKBjwK2luZedSepdV7KxV4hDhg/aehUVCxZKjcoH 6ZXYqoidzqoEBwvalBuH3dlLJ2N9mPAPcLkn5TAqeuIDGMUoWm6i5tNkI+DjODL8cmxFTG99SnqP RIUyZHyDdoOoUkVNZYPKYiFhHJnwY6HwnryWuIYthUyeE87kGaT6qrHqx69k/IB7SJzvra1y/Cvn p0tFZKL1Kdm4Dn16X2J/muE4D3wy9p7p1ifZsC1jUd3TPWNerKD/2CMSJ/+seIl7CyokgAs8BeFJ IYHUTCTSWqwDe+XlG+mFt0KvjMAPW2k0wroJzHQk/5+A4VNBKajxRxts0PQT2ayJ2tWo+eB7TD8w u+tN6hhJr9ZFY3MboJRdoIpp3gezFd2uGBWTAwL8vCT/MQCHbBDofilflUxbPA0uyw8kZ/Wa09Nv rDypx6wem4cWoD8AOaOjijIACPK+AZBLoPgtpfl7vCav+RWKo51svEQcM26ZkQrwSome8rvLqOdv 5GmYC6b4I6mOmdV9e3fuddTE1dWEpgihiP7IcuxlLs81Dd1WA1O/w5zXkBDW8fr45PPpOE+qc6Qg hwX71hycmEU9yXINuqv2UU+7puNZ05OnTHO35l9k3KVh17MJDSdahsG3UCoPsPd3OlLiVwNwhiyr QSCNhAy6fPzMRwReP2vMrF5Z+RcAcPJVE5Wd37MB2w2bCbK9MX3GBe+SdZOgjR1DuH5c7tk2T/Tb AaXscPSI0pFXJ0777CxUyKscj77HvIL1DJj4PfRqmNMKB+TWmKEEB/I1jEPGll/5tkatmNxww15G 3zJrLrzacmRzgbzXTD40AJcHFgjQd++DVVQPJLgrfTcyrArDSJro/JdepuHs25RoOYOhD1SS5svL ujYupM9f5n4sMKEFUxrWFvcvGBvFYPoNyOOsDAYbnABtWR7BXtZBam86Mpnw3paK20Q5Letchrap BSEsGvkiUrsE9wbP5qW12UlaoAk55EqHMZobGxx8E8xbAzrXrZXiGNHtG4iczI5GQ5um55slLAc3 7lxTyUO5sBZ1HGlh4rZ4Me3TABbNvV6/IQcDFuP4EfLKDGKd9vCg4XLYQj8uIO89KP3AXWHyCtbY +89euLn9+YPBvMaqCS8nml/v5n6enEn7Fqr3HmyggwNl+H9eN4S6wQcBVfq+FIwVLUPsQGddhc+7 y5yzE9bDyVAbZgAiBf40Hlq0YIRxtglhXSS07929riCttM8yohh660iLdl4Hp6HJZG500mmHGDHi Sy2ywPmRPXESdsiflyBwPXKrHciSpNaia3eRS/FlVHPE8tTvFwX7qwJyFupw+cDUPUzl6JOx6Ow4 9Nc6ePArv0aOkiE+GIP+nF5CBpr1Tyrl0Qar9d2QGy4VqTjdpNmPbK9AAssDBIqvizHqC2aNkLBu Y9JCFcwhcOUgPUEmwfy/LY3nnGpBm4JKPZxFcG2vIZoU/4i+c6mo4qe9CtMiZ0BvE+zYSPYXdgfH OWVXJZEZ8UyglYjAqrD6pzxxi+uLJ1C80jgC3piWqFAqf9k0UnmEoM44cSeU0E5DZw/aDGA+EfoH 4Wd0aMKv8H2hCV5xF/pXZgs4uk7tAVFtnvPGYgNRSMzyXdi8Q+8PArVWzowbWdLbnPiAhLKBeTaY OYAbu/M83GCzLP2Zu6NTxOn201hnq1PzL84T/7V+xyjOKTYYJNSAk26M2hhUoK2N3G8NE2TBkNUX sI190DAkqdLiNoIKmoi0+nMQhzSuWFrRheukmEgqEUWBNxibcWxJtoSNd4Is+LA9Vj7JeHhI3Kcu GTj3skERzseoPLwWgp5E/j6rqtWvhZdV/i//KD9ae9OOeTUCPheTIMj7Oskv3xrUl6HHKsZK3LVD rF9IjgugQGDeaIRAgURF/bRfFocz5OelUpBKhss1vIzTXBW95J9NQle1HbFakZG8fFJggWcSp3vz NsQoX5x4O21S76YLT/6VD8jKrg5Z5SXcCjEweNCf60gPQa7x+egVuo0FWMaXoJi19nVg1s+ULQ+v TTNV/AuR4reAOWlLzd+ViJPbu55DsTVu2hGZ8T1j/evwVBDqQTiQ8F6l+QULGwyNkhMouT8ZNWAC bPjCOuDZWTKm3UUCfPOOZqU1+G3IdLXe4D7ZyVw8WPvBb9c6QSfvl7jIwsCu545mTaLKqXklZkgW Z3v5+NeDTYyQGTmAIB0lDLSe6uS2aFJ7ChpulgAI3z6lJqtply4ovKIM95ytwfoAN60Wvj2aGO0T 8a+XNegj1NmQuVKZ4XEemc07uW9xLhzrU6gw9BWHq7JveUyhYnIQ9LTZHhQ7es8jAig/pnBUU02j VFufWTptZKXZUhT6T7jTlbWbuXW3DZyP/OYNj0Z4y47Hg9U6GTO0tmt4f5slKjtgdo5cWTtwI2I8 wAnnD5OgSYFLNdVPJWAwPpJM2S8Obixd8ObEHfWRCIWUNwxNnTuF7smgsw8nd0B23bXsFGXssi6+ hRvmwMKkWNyTvW4wSS9/usY6Qhf4v46+3hZb+7EsW3/XNIMAU3KgzU+VHl532J5R6z8fPORi9q7l rCf+Zu66SblCe7vkTMyl5kkTYrsXnB+Gk70zds4SkjF57WZ4bhPqfCJeyq+X5rHHEHmuXa93XYRO uKKrVqWNewGYU7T21c7Pi214aA5YU41+P0lzSuCYient4qVZss4XxG2TDRjrDYBF1djKHoJ7eDhw gj9ZIRnxd0F4DD6XC6Op6aRmFjt0gLqQKnKEnz1H2EdEHSgHZvyMgflOgH5PfgsWpVSzhPt3ccm4 1vRqeeeged87DUsCJqcLsGkREaG7YFkT6rsKYyMNfcbkQSZX4VQnQ/FrPsc69nCqxzn30XFxnx50 l06G95HOHdohqCvfondZGMd9rKXDmTTNVRdZclQCVQmTFheJV7bIUpbNjLBBIkBlcOhuKgl/8ZeV /CZLI2nmF1W/HyyhyVvrX2fdsWBYfApOZA9QZhMMpxgmMI19T0BqIh+x40ZCQ9d22MrRvp77T65Z GCcUmFXE4TZf+r/8d7R8mOUptK1gjwT0Ob4Fl0avWBSZ42pLD00VDrkMh1Ucf76ETqc3ecpndTtn I1Kdrv1KdcJn14rYQL3WIOnx01sVjfdUCdehy84L7H3t9ODWVRAmv/NcAeZHzzmNj60Eg54E4VwK chSooVuAL/bMeiMb8LbWI/AIrwnDfGGkyU2Twy9850L2nZ4EyN2Hx1Cok0/aYkKUU0rurRR1hKwx 22lbk4fTs4QqFzqm50RwM1a72bn2XYeL9HFUO2bLlsvDKu4HsIM1igYlKCpSHNaCOr2mmQLdJdoj /jgmseTomSOIGufPDy9XKU3rXcPJ1G1X1ESL/F5rZgqf+NW+Zq2+8+SjjRgwwMBUZn1o5gcUzQ/b OWKbFR8BkdIPqxjCteCO7KMpneWGAFPtgsFT+Ai4Ny5+pgfcr14KwAJSzclmOPCM4LgQN3fq47Ty W6gVYNoV7VhNufm4cRw2seZK5euXjWFZ7Nd6I7nXk0KeKI5BZ8UzT+nJGK0vIFl0N2qHM9gliB4e VYHdAaNHXPF77aP9Y0j3D16CoDzg+w+pHe6jwhYy1ReBF6lyyZ+24hVszLf2/ce/xFo249w2wZwU DpRImRNKpe3RfOWlusOJpg18BIZi6woIz/5xQAHaAH+5CGcjCXLHIeH6lUjHz7KoTJcKn46cBI36 VSRynpELjJYOUaYMSOwrI9gqY2f0e50adNCLpyclNR0SMDqsda6uyWY7kVDoqsDpBNVr0pBhIeO6 t84rU4FPkWwj1QrfKHKEmwsoaOoPf/ssULpfrw5tTlPj//DEvbIn8/Nm35RER2wPFMOTlVrBoXvf tC11lDVFuRMTW7Qd81xx7q64ymvj18piIzfPer1Sx3kibBcGqveyjy/wnr4J+T7D7ZF/hapshfJi 7Ng1kOCmx8VVJKNsgJQEnq6wS/l3TuWi2Ng+QWP5wvf7pfaWqZ7AWI8SPUUmiIlv0GpTClNCR/jR ogWSuQZcMRnzw0s16S7K9g752wyUPog2WQtIR5oqADXCu89e120bpooUrnA4DEmCNWB0QrY9PDO6 UhdhoYnfI0Z+Dkwo7hCaYO0kF3+Dyg8rxr80OR3gLDg48vHyx1MjW1VCMuNyFeP5jJPJC30YsnKm j33g/yru4HTlIiZeGh5YDz7cH5Sz9cSzZ+uHdTnHGejzE2zkIoHADRbdERGY1oPBbDbUjmXRDxIQ BiSSq2ZWRJrgVzP8SQBSFGrK5E29Gy80Cf9C/7mcKb8k7UYOOalo1zWhNum+CWNaq2olu2pX6DEX IPw41GnuYIV4I0xOjkwm/OPh3F6LIslY10boFJuUm8eKB9SsmJJLXbr134jpHaGTs6bXBDcvMRf2 Gs1loccsTJM2L7MtdcrnIm7MCdaVfXVQUUVT+kTDPghE752y5EzVG1ei6oFVFRSPLnDZKks0B8Bj W6+v4wI7R528prPYi43tnFzpiFEpaxYGvs3zZg7DHBhYiTFt3nVL9wNjdWrHIoJBbjJDzsMyFxBR b1+kSQgzsTGxxo/ZvZzA9kjffjbU++pAuyYfx/PwkCqy9IcTIK+QhwA+rh4JwB5I4phTXB4JkHFy ZyMJaK6WK8FGBD8UBwvKznfzpU48v5PAy+Cby9VJWSYjSid/aVlRgfuSHXRgE1Gv2xOeZY8dx4Lk QpgcSqe1r0SzElGQrBiWtpev+jZ2NWUWRrCJ24s9mpxt15buLq2L+PEUV+GNe4lYqcJ7be7bVqM6 SwnjuAoPmxZQV7rO0uOlBwtIt7b2c/cE0oiaocVhYkO0vIdoyHgxcSjRFgiQsVrxI/wF++FTsf1R 3+WDN+hO7Ok6LsoNrXhi7xUuiWlsOLVMFSOsSGj3B0B2LuItZqNznk5gvse+RSf1epYayE+1pSg1 20e8ZmGfsL3ccsmgqfIfFgW1eUM4bFnAT+DkIO53QopQZog7sS8BUt/0Mpun710aKQarhVSFTshD F+dp6ZGUvEQ3X+hbSAhbnxCXSn5xouz2uZNHWAuVNX31FVg5mybYjVzURp7GgeDCDcOO65YwA7zm ijk8KAZUy8PlEd3JJH55ks2RdGiFGUREYglUFsnq+JynWxCjFvxbsVSrZ41XQle6ebgV/3Nrv9CR HGI4QFE7X8QiLE8LA2C/CfB069yqQHOAros/XncwIQoAK2Rl5YWR+5Uc6nIxFLgKK54PFVQ4OaUu Zrq6SBaMQaaZ5FZwujltrcwGEQpbl6grzeXWAJ+uMw9Hrb5Q0Lojnd3wMWQxZvW5Uv13lAD7xkD/ O50X8i817UaLmTihYWKs93K1dWZ53IipTzBjkoYUDjG60dvATx2PEPL2O5UVWOG6GA54QCuf4nbc HfygfL2USFWglyA2vTj3l41apfoSdwGccEi2zP147onLIqiOEpQKfAGr8+vjMPAiXXw2y8kZ9wKn YUEPxJei5B331KD1fkiDzW8TZ0RhgEdHYh/xJS9HjC/GdiSqh4Eimpxe9CVYyczNIJlHXMDruqPr 6gbb09S90SNH9SOzkuyg2Q0ZffLfYmYKUVJwCi3fdSJKg1W8H/oUQ/8QqJQt0nP2//YGReRHmP2n 4EYOt1CHAvLsvyZHswSanzmXWXe4AWYk2G9eDfB2z3/GwFZKPVevqiLodc81yAl0xZt+DuxubAzL VkhXH8s2waQ9DiWe6iIPlB5YVdoNauLsAjvdUE5Mg0yq5f0ojl2eodW/EC9S4tJKvy7crUaCp2VN 4EDZq9QJRPxxTM4TeN8ywo95qsL9LSYZpeVuv9MHeTIQAvSk1GxI2iYJQ4OBNqaMcLYt9MSnkTlk Cd14UETPL+1D7lExV/3+snJvskpZCEPOZJCVQ0AABXsTvkvn36PxHHFiijJZddS68QG1pzRMQZjS fL7E7kxHJMmGAcLoknaboD0xetVw10fV1uab9S5+K5iw4HCvbe6bLk51/paPUrUjd8LG7LmxYLQf aDsohtN4qH6cK9N/IoH//UiysFOj6dN3ehgUSPGfpEPEDCzVVWbvg9gxXb1QtI2bUiJMPyKQITl5 +wBm4u8v/feeqX3SjrH+hJ1/MXN4vX5bqqEGUYji8Oo81egJhO5cRZvS5hOiMWeYcx1g7PSQnNpL ya5JbFKc1wWJMYFa+ubqSHcv08gThJjVA3yjop0nzrGkybPlMJjS6LBqLTwwmT+E/vhLjIp/3Xmn /0KqHS/4+aig3HGKvtTLqlfkfxCcySMK3WuIDLIjNFBg8di4ehdZUOka2v3GJPk94UjdgT52vXUT D0BhvjnoZ8I1k5i3yWpkabg4wDaRJc0QbugJ0DUHdf99mTJ/vHIQtkyZ+YMiyoaLEnwgAzCaD2Q8 7pMHKyA23dFXuLdi/eq5Qun27Fx+sTXWgus+X1YAXUFYIAFmLkLl3qkm9QvHxu0tMiTd/MAW13AY 60WgrbVBsJwZQfrXnDMwg05tyJv5WUnflrEcCNQrTGbE45tr4mm/GPo0QaIFgZ41R2QjQoAhpR/d 3ebm+bnCZmMxGtOhLXDfQSXHSb1tIdxswuu/7726h5jREfPGyMAGIIrx0fLv1owQXWG57R30hNHm DUCrmwXgaZXZjQTPpPRYyaV5m2WrqkwDHxVAXhNZ6bN4sEoX9frlTgEcjlj3Rwcu/JeUChagXgsH apUTENt5dIqxUo+gPx87FcsWfHQBnp2hMt35sxItZNEMg0ka9ZxoWnA2d6XWuF14Lmlf9wJ1BXqJ 0iPVkQhlW67MQhg+3ieucxDWLO4h9dsc3jW2VouHHRYCduCAIE3PYvUIOTxnLvntb1LnJ3DofsTh Jrz/gYaMND5LT2uVSo8D/z6RTPHNx6Qm2BjZ6bU6xcfUULwnz6PBETdzRiiFnCVWJ1OK7BfgWZ+t PO8c2qEsyd83Dq15See3uhPIo3qjYbTO/Bi0cTAhgo08bpmjgfR0H8RLfklR7nuCi36eXyDMe8hf aJ3am0NAaqDxbFWGxBlD468fk1SMKgbwIXNODuGGuv4TQcwFk38fRPH0sJxQO6FvssrxetSaIwRz K6IxNWa8nGzMGz38VQn6YH6TYAUtHn+yl8jZvuRSRbVlPYGw+XsY2heuPZ1m8cd1ncNCQSutF1BC A0uWBg3Dtj0tr8o00DX3BWkY3HDBImdY6sswIqfA5WmrpvX47/LjSJZ/7/a8eG3Iqkjttu2NsKqj t5eYfTn2OOus8FFPKr9CGIT8ZfULBoNFkQ50uKkPqVOkRpDDrb5Llfby8ibqae1Dg2NPghBFanh0 Isj5Uxpg7VW9lZXf0zM6Sr+lLAH5hd2BYDUN6TqZqw+CpUL5uI1dDInhvY1ugmpppqvki1k0Ah1c vsaL8+94wU7xaZLbYvEpI7f571JiqHHgedNeXeGGWNMj/hXCZ8WDO5mD/purRtrjM8D9EdvnVoyx WmwKQyyU2FMxNNjusy04gdQ9dacdI5xSzibW2/LhwdxHT5Z8/auMrSwU4hAt0BXRg4I4N7LEHwTR dsm+lr8AGghg1dsWB7h7iYmj5HNIk9ei0LFCzjCTEAHAsT3O+QThfpI/DIc0v8DkiVnp4ckD5P0z 1UQS/PQ4S64Qh0rR8mEQ1fzTB3MNckjjGwd++khml8WIFK/XoxnqUfivnagpyil+IdS2k/mIcVMI 45I3mDTwIvbUarTLgHW8RtTico3jcvoTgbJVDb5hYFnsmwZg9BSxmc9fkcP1yyRtkLi+sV7BEEr7 cgeZSlFaoFykuX8+hspDhypV/zXoh3k6bVmVuD/pf1ErERoxTj5i2ykcvnPy+mCH1tLThz3nK/xK Zo3zsbkTqAw7yW2IfXdRttda1BshR8E1hFwM5BzmwITudAsRO5OiWuBMyPAh8y2CwVQZQdER7Mq2 7q0tIYKR0Fm/lNsrKhwpA+pxhFBoAEix/m0yXXkrifb3uqiieqmXoHzqb68U/r7hkzyMFu7uc/As 4JPuXP10Yh2ZDLrdlQjHcVqZFdMTvfNuvtErWSUMo99lY7FoubrC+D35BvSbh9SQB4wzQFwwQ94G HwpibopOYHG++TlPr7bhHY052P796l0LZK00GelWffeFqzqMj5xHozhvcBBlJnxyuJhokIabQ7ah hDXVIcvvfq1TwbFPkp5Q1YNEMqpm/gAGMS3c3dMMgJqfY+hVhppNp83E9NMm6kAgKTVqP778PAic dAapDJKD16AYqjrdVggq4VzkPYQ9w+vVsshcF+bpNidXyvoUtcBie8uknRs0QcBAJbMqIjwjqgqw 3pk24/FOmdFvqDNNkSF/H0vEpcOfVJabw0GvnfwNK45mapbA7bnr7J5uzJi0b4JDd1AXxucj5qFS tSatTu1/cMvwIf7Xz5z8DILQ9H9D/7L3xkq+8yGZkGb7qtcr1r4wE/0cHJPvnejjyoPYwReHJDYr GsuRt7etUNUD11BIipQjOE7tT2uU0yjCXztGbWcmLv//IPflKZSo7ZPc0tQMBKc+YWgMxrbguKOc pcOyqNR3D7zFZ+vwrVyxMz1TMslH0ksocjJ9Bw2iNzNlFC1IvrP3Nv/k/r271qgv2TZWKJPFiUIq R8PTxi2Sna4cL6e2b4rHSB2b0UZwl3Acfu7rpy1EpSxfxv2xx25jBwOqyW+76jjXdyuNa7AuwT8h ksuArWuTS85WgQcScYOJ/odPOF4FFmlKletoYaFX0fYXKJVD1Gv2b5KU6nTmkJUPCljtYKpZV6Sk hHWgYof4dwFMsYES4nqtda5ptjWQ3z7H1GQOzk+lzk/V/GjczxblFYy+NqNdPyZNBl7UfrLRuCVy lnSoqPT3J2N+0kFRPOEg6pDwP+7SanAPWYUUUjkgHhHBslsGp4zVOXDHJXLOpXbWIeDxmw/IDBy9 mn9bW85w7aeLvsJ+6I012IH4DczTFEQBU8JD89/QSync2yokrcmQrSoRa4kydywaQzgkjV+Bnesu hBdSo1WfSA9O99YPp8IbERbRGvq3v7pc5/9GTcivEycwbxwToxETppCS+aI+INmHwN6nTN4uncBG txo6fdz0GfTg0HltHFJMzi+jWW1FmwDw3yo/U8Nv9sbPEfHuPLRw0DXGddJP2hjb4NyLtC7pcOYp jht/iLSH6ue6EErxaHYZrDlGHUoRK2z3ny+JvjEMh4RTLkFZNkYR1pjtbReMj0h+m1NxEac8B69m 3ovug6HhhEeAjXUBY5u5XGxjx1NgUCqz5wW+2lwIupUaNochvS6mmeE7vAjwOUk+Baka9jvzmZKq RJJsQGfMoSQkkIvB0872U32kQMNiQz1a0Xe6KxVkWn+DReFlIq++w7EL6RDRn08rA2PVLB9PT1N1 y5R0jshx2P/s5zy/pchhAKCcIm6RFNnX1kYwxXKOap7QqdG+LBJXeaq6OA329tnLNsTC2Ej7T9wY ZtBnDYIHmf2oE55hAx04k0kkokpYXohs9R7LrwFZrAYjkY90tVFZfTyw4R3377+q1KyeyLT4D4Cz lgmNdx5AgUhsD1NohlYDho5vNgtoBqxEzNwc31wZu3XXDaJy4coO+nS+putZWRwtPTSsdsF0/RTt y1ipMWKR+vT3eHAFleM/I5us+abIbEdiZrONP6CUKKplCOrLAhMgf9QOD2yz6GI+1H+TIGk8oB7B /90ApVLw+UVIrOTMWvtt9e2im/K0C1wuZ8zxrZpsra6BA6mtyrPormQ8P0W9EGH3S1YF9AvAMlYL Gkc+UPKz5jFY4jFR72EUCU26Aye2WvVN0QI5hh7HLBjvZOTQlwR33p85oY9KnkDgsYxLxtrr6vOp hvY/76F6R8PSZx0bcYCVPg7K2fozsBLCmv/JBovYrDhM7xPSYL+w/vLKPi2Kb4io2kcHEmxrH9xp GIN1tvaXyU5srg4suJiDkPuoqiN4MN5A5RZM4YIAgom0MS1ZGZjlIqIXTjFNTsGZTXUbsuNFSi1i w8ShtzcSR58DnlrQ3uWvhIrM/F1JvIETL1deL5bnBpmNEEVlsNxqgHYSJYjvwRAayRwWdtS+fzHB K8BoToiPl2m/d6DRqR9umoZqGk4GV4RZxkJUgH68TeFfyGvMYijBW8sP8NeywgOnZOwdMou1tIcO LLkFsDnxtc79KiHKRZrUGhcptvhk8XXc2PAuUnYl9m0XcaxWhzPnbbhYnwQSWR0ndUtKmrCDy651 Zn7G+G5Uqmtu5sAj1HdxJ+Z2L/aYcMRgpz6D7MSS8EarlMKWYGzs8fiDmn0APbhbxhGFqxYZBaLn 6qz3g4l0jbNeHN7igY3f7NU+PUWVTIGbz6HHX/nE4yfBq1RdhosMV0n/MiEwPwVtwSXBKD8M399X fHffnspUc31YAYAarktAcsLsITV13C9GEzGJIWajVjPfOVPItsjjjaVG9yDOdCAeEqeu1o3nAAzh LUjGSK/pKEnKORlM/9MGlLOauVfl/zj1zPYzJTi+PYi23ancNJzZ+y0hUkQ9LQgvO291FVAuowKG GxFeZ6mRvbqafUmC+71iKrRRp1jq3UrtQ002mt/ppWNj4bZW6GRoUzawYw5x97OY4qbMY7YwOFrV cl/e3K4x3J9qQDwOPrqXx34VA0fAtLIyINaYtvXK4p8FqppxpkPBqkv/ysGZyo04lL7+Djw/0iOE MCz0W+ZlsMIXQHZ24XMxpxjMmBIjCkgInjDxfTf7BKjh1zwXQMkaIjnpH5MP3j6Xo9aRmy7/Yypm UVMysh99VHKMp/qYcLpefpaEiaF+sR6A6cXHOb4Xf44jD0N4gOtkJ0TawNdmKvRdcazUKjjWdfXM PbTWF3cTQfo8tdDBjhoDKE/wR390OXQiZhYbb6cGXCt2O/6/6SDC0CqZxxar7JxNQvh47L4DsQOv f09bwOh4AXKwRwVaa+HIuQaZjY2gsygtuWaTKhjzgqEVRcoe8W5sjTZw4F234EmeEirZn7X71Fx/ ioelXSvuL5Y6XbH2rT8X+Mqjgxp1oh3W+lM1yBCs2bXTcD/j9a5hxrhbVanzfJCG5LMYCd+Lfgn4 M2HbFB7een7vDHqL9WXl4VR6ldmOn/34N82HTDWPaqqDKqxAuIRcYjbX1y8DiTCIArJjxtQTJNf1 pi0w+uzTljqGx58q1UN8dEIYcdx7z94gFP9a+3+Os6c3KO9wiNMMGaCDEi0G53MX7QTKUfb5SBbq UCx9upRFaXLDvTq5au2MJMF3e7BnOM0xOEQe4oh8gG+wnHi5cP5nEobb+ZDw2Ug0T4QgZYj7/WqD eYFZpztOFqpllzzksBMWlUZNbpNzc/BHlK0RCFMhpSd61Ycso7phrjlI+OptaaGmXFNM0fQKnvoI EI5XJXyz4GMyWrjf64exPzD4pMS7VipIuV003fFk2Xw592eJLAl2v9xkud189D1tIFCBxRUcTEdg yDwU+fj6323Yo1szYpB5P31qWCPRGvDuWADlkLJvlrYGkDUJ7kpMN1VX2TYQ6A1kdWu+aqUqRuCZ oN+t/KVcK2eE0r8X+hakfLhm0lwr4lL/amQHpcrsKf9CYjjUJcemtev4lbCdCO0+Oo6wDPd/Kx6J Yj18MXiXMUBIjtorMGM7U5FWzHSGFe+6cnztBF+EcuBoB8fcqhy9jlf3aXddkXvxFr9FJtSL2A1V 6QrQIsjkar1W2LtlIuKYmomQGCfrrAmlRy3q/MKLFt5uB/gQNTkBVUCzKUXBu6iQCqNXInmhmRcM vi9fctrwzLCZeVwRlvLEdfcv7Mq8AJNJUvF6PxZDhACuIKmZBBJipk5cK5Nc0fNvVDN4N2Ym5a6J t7iCAg9A+rSLqRa7n2JLYtSWkBBp3rX75Fddbco6wu1u0S84Hth3bVXq0Uzd27Epj4hWTcFf9Ze8 A8v9lmK7KZbRirTPKlgfDz7WuZfWJXJK30wG/6SRgjY0mgf67TlUyx72d4+QP0WymPKNQafi62B7 JzFmAxfxjedufai97R/BFSPNdAtB9ULqK++f3iR6NSqGzFR8sRpw8+2/EuUVYr33lULz0GMt3otk 1lUJkmLtvpf3Ob7D+iRgJiJUVxUxaQ3lvWbDwl/ZPRyPQWtSsnmUmTcCAMPPsorTMpeum6k4nEGI ftpD2gemkx0cM7g1UTq4CFzop9jIz0TrgoeJIvzDYBULbWk3SXi4NobCTO1JAs/iB9Ndw1rhJVm4 NzBBE0b2vEUv1BcB1NQn6aLbf3T9t+iNe9Ny9eymLwlp1bIGkLhAGA2ErSoHwhy+KiG45CokfCL4 YIPdcTRXEgYCjoOwwfKp53/z+/rgdiZwkBxAMYfOu8Fi+A2Lq+Q/rg550BNL5WSROGoaISp7Y6+k zBSJgXOcD4kUZZBb6uNU2TpWIF3JWWcR6RO2QcOgqOsFJK9j4/lpmp1ydCqrU/fAtVylmTKiuRU9 OXWlktDesbisSRP1akjzudA1iRrcPhJ/lHSLcCj+TCp77wwQjGm6ko6cUkboJj4V1oBnOr+15sS0 AnC8sMxQWYxnIlie06OVPfCpI/7Ph5uE0rjci4mRQkF7TvwkzuI9MnmW6d9vWnnnsRDMWC09hRyj j6/F+MVJsJsu0gtp+cdfwYGM+0chBsPIzg6cIsZzZLkOVqEso1AuuomQl8xtScrI5whp3rEWnwLe kTkRDNtmqnrfUWVT2RhB9riyEpnJV9AG07wBZFLmbKWjw0x0Kd9589kHG4nqbcJo/HzdvQ8sMo1k r4lg6lWu13G24t3AzEdMMyXWrygWuMzUJhM/k3eqs8rxOE4RNxvo32yYLFyPNPOT//Ya7Y30BWf3 pm1uX00JCqsVrAV1IKIwtOTMVgMQcibkUQgEwD+FCg3tczm4xnGxEgKzNcd8Jr/aQfavoCzHeY1T KdIC47zc7AixwGCSpIlGgFlC1rYPyaOhEG9kXCJTdmW0P/lhFjgBVKfTomkISBihnffLHGcDd+N1 tLRV/oD3yr2/fL9IGunIOBZq0nuZzr7A1Z1M1x7FoBhZPSa/gCCkwkJRLT2PrEFSLEQeCE6fsULx pDIevn4+A/+xr0cYlmZwRyHREVc2nha0OEWKiexoFZrlmjXVBlIYLkbaJw+sTzqkaBovVX0bTwe/ KcVtgeYbyn0nb7y+edZgLhxIvlXDhAd0lKENl2PKoMTJkxKxLLWhiUq9d7cen1MjeGFKaHq3hjN5 SaDl259OhC4+nfdErddxjkCOj7cYpmfq3G9V7W3Xv8slFfxzPYMMHHIV8HjJS5zpSNvrj1wxK/xp P2HKHqLmJ3bhAunn1deS/HlRG+XAklz7mOp8boYuB4AEjgM9E323U6qjEmscSGIxi2CuCJZxy4KM mDxBg2AV8JmQ7EDR4r5W0h6qtqDBt6mDaKkyxx1O9oamYvUXcZ06fJGJ45ory5WHsyaxyWLHsFGQ 1YDETSRTzEjbFTdZwXpgxj1ve3ouwH9x7/SVTr7gnQIyW3wEokRY0fulfoBTGMOsSv+RZFCneTNW bbWzNuP6GuFm4RCpl6FqCzPWyTyN31bpH5QC1MLzRORrFgkXXvw7V2evQuzkmacZSqJ03qDQbj7y iGv9z+3fhpLtFiNtxgfwa4OnLqya+WdpqdknpP/7BR+Yo4PGWoHAAt3BVZV7ykvJPnHTKkxo0B4X M6sgoJhAK1Xtt9Wug670fOQFWQ2UWCflJRBFF4rYXhsQ7LAnxA93NZ+pgoeHUFYQj2igZYnDZznH uVLlukH9gdRRdjXjmse3zKabcSwFGOGOGntPRNe0VAK1EEM5Dr6hF5tH0OycXZuTRXAseBLAr+Au JbuJoijBCLBcoirDkZ7Wym3xe4v/y8ZlxRqEl8o7qY4omvNzqo71XqrwJiSpJSQzbqBJm5HRbytp HrW+Q13CA9nSnTkPuUvBFXvZ1pNL2q7Qenw/DeqNNqEMMUJ9bww9x+9H16shZEgJFNCTyuHoTR9H BVreDAzp+Om18xjDpLyaBl/S8IeJeLTfEs/0H+0MVMH0HrxjlWsGChxssDlbkKy243S8yxPtbTPz wqC+IFAjdYIC9+YUOUfTiDAuK8Nt0hrdX7c1Lql0ev4T9BsA4s7wa0qsKqjZQMf4US6ZPTdkH3Ww w8GIe9Igy3IrYSeQ8OjwlWTeEKvAty5fE+ISrkmGsa/JvY/bBFCULbxjlm5CWP1knAywwWR02UUy A0gJVPnwMwTYLrV0Jf0ix5fjaF8S4SCvyD7ntD9ga2Kz6rwZrwTlevzICwPzQo0fc53An1NtyW/y X6LmqcYp9fAuayt9tNd1669aIiMUZMsP1rKgp2OPZEj/JoPKdE9XjwZzUsQtduAF65SiN2VXrG2G 8aKRab9AA3P7bh6orGgZ0dlnNagqeNSFwGDx8MXuGsS6uS19p3kbKblsARa32dOo522vczDvbATt iOPaud8T4C10tCr302z0hDXt/Em3qOUhn8jbaTrImcnGZ9EOoxlr0tPlnxACUFuGuFugi+s6toQS KnxdtJ3pDXfpr0JaXohoJEGfxYRkOAV9lyz1diQChA2DFJF0RE80LQvMZVmSQdh+K9JrEVmt1HAn s4dlWI9ElmBoF6gMCYHrgnBtUG0EICt6p4GAXIN3x9nGtgHNXEFNJZAl7I7pmdGKh7pbzwXPJebs +5hZsW7eLF5bDaXUoOb815DIxjm8U1B/1qa31cmx0EtN/Bv2C7apDm0p+M/DQxP3HU3U+rii1p60 a859xJpd+ouftBD7GGPnJUYpemuBjW+X3WNqLfPhaZc4kfE1pZFG4hJArTT6MZLdPawsb7zxXw32 sCEhivuwPHCiaP7aM3tfC+tQhCf8OcvanD8h+PzVOZaZFYI062FdTfZGBdMgpHUxk61t7S2I3PRc 6AZ5gz2bZj7kFCxacOwTTyA778zDEi7Jy7fiZ4ALE2XYnqgGOSrnIVNh+0Bb4BFYifcNu8LClVmv r7AaqAijg57ar5+IjKGes2mbc6vt9TdJp1K6nXB23xXwkBlPmn+tMepiHEh2U5CfQHUxuS0uEcAI ghxiuar0Ja6A1Gqt+M3XgL8PTqglAmXa8oo9sWCzdxJSwBKzwOSXWzyt1xDe2tsxXH8MbGW5fVtb oDX59uY2FsLF+H4k1CmSNu386bTD4SrBqOMQKJhMQYrEahVYzwfpiqhvXL3KYyzlTBIewkS9+JEx ODlWpVybc8qViucX38RZyLGg5f/WO6eVUBirsN63mU+uNlI9ucKNEzlJ0o1WlaQHF3UIXQfL8TNj vO4SbnS5cx3Buh599lmzalviU6L3XgKkZuo0nlQIUJwzkFjIpS9Q8vU+CNb5XkxTxsBx9NVj7rMN Gtbsph5kFSl2C9Pb6XUWUTAKFf9u53BN0rxDzOyBXaejGshWgzW0VV1G82bJamChwwQjz7nItBZt 4k0E3GM2r/jdtoYmKXwoPcuHp+8LcOpyqs3BXRWrQ98t3aT0GgsoHYwCWZ5TApz24Aeaem0a/3HA GULTQIixgSmcVAeSF0B/0qIcOWgir5TcqrKcpe7dkGE85SsEYyRPASx3onXm+xN1y4MKC60IIj9O VJ5QDs606bXWwAB4kNyHoHOk+JqFcG2TcgtYiycsdc4il6L8B7e6iNMUOFa9k91g1oVv9WRWc/Zz I/v0tlazUHD/QckVn/1I9ypoxMpy7Vu4G+lK2/lkrTpP7FP5+ojBz+FL8mHdNgvpNOFhZsuLmvb3 Fxt+5/5kMMtH6dWVTw+crUea8+vVY+ISxIfUhVT4KuuXGck3dWCTtEwWMPDzsCQWo9h5aL73mDRi mYIdriytEcyYlhi7eFs/wUSTcw8yK1NVm11G9kHEIIw+uHQua0TKayFD6+B8ctnF+l422Nnsct/z ZrlnBJzaF8km/x6kfS4CvPBsMWOlGJ3kmjhikXO/7kGklrHo0bYVignuIJHr0UaY9d1V1y2DOTyn mxeE6P3SXdcT8CPD9ohBGNTlgEbuSiGVNsxeoRBNDKt8DbuYjDjkD2ducM9EQt5NapHLChx3bIw5 AYiw+Ncup/nDPo+/dt2xL7ZV1Hmr94HS0UsREQJuDChVx+hibYRlGOpKdUUJzW11avGrsdPTvzDr 1gTxU1D+Ax93GIhB/N6ubO347ESLLBwq/4w3L3Dcj1EMhVfxZIg3a1GCNlCgn5uIP5G/E3nBEh8V BqQ8COn19JTWdpl48VC2EuKySorDtFlK2TLBzrOyUgrSujS4/XwBGFQbQPGakTs/2BCsYoX+5PCb gr9Zbxg964NaMxTJz/R0qu+9ENYua9rbI0hH27CjnzdfhcSjorRmWyFOmCg8oSaDXQ0Uz5R7BCpO l28i7pXx3VOiIei1E1eqLucjMWR0Ng5EyV5jAvBuBiZ94WiAMwTXb89cufdj0bcWpu688U2IMn/j GklXjiOjrTh+RSliiFBwOvtP5Hqff8ma22sGRg80atnP3vUaMSeKC8HGrmFAvnHV78g7amxSDbi7 CyA+LOW3qp5Qi/qtkyi1A4z5uovzfFEJl7AgQRbe3zdpyayTXjAJSCl2rTtzJeZ2xBO5lggngMr6 yuVs2OIhQ6Nn57FavdmxURty4KSxQ7UpKtyk7TvMdfuKZH0dS8TCAjGo04mSQ0/VmbIq3cdwH+H5 8Ni2vu5ZrA+hP1pq6VgHvrmT1YOZPwGRsOyxhKjda/fotPUqE2GW+zJT6xh/vTNxBfq/GcaitH1d FMrbAo55TZyXuHzThpARx9glE9KLekkoDorMCsO5a8ksTEk8fyFKEVAQd8/qeut9/NJXjmGwZs9K d4RuWAW0+eh27jVYdATCRXx+NboYq1gRMAj/2UzGKjfHNe9nZVOWr4mi5xl/yiylTif6gcMA+t5K rYYT0UkwN3Rr7Xm9jP4eyfvq11EAPo+nwNv5W/cbmqEEEfxrb+u2Rypx0OIj2P8lhOuAJRYETwWC 6JHANrSonpeZiyG6ojCqN1RW3Z8VHgp77fox8IUbYg1Y9axsaxLKVxMkg7+dESGe35GlHQIg97B7 v3F3vHaVl/eCbBd7XRaFAP/JndWoimmsBi128z7ESd6RlSa4glB6A//gViHKJoVyEhB67MfJaxLV yekyaFbDmf8EEZOe6oms2D9Xb5aYylj4AcId8JXT7OTSrM73hlym4MxC64mmF77Fm1MyKMWR86z5 yD8uLpAOIJd7S2OF3XpIwZkoG4Wq5JIVMxJF99niRySflsih89XKZwd6/L45cmL5T1lYnUi2tCOE pcoaTJ1c89CxCkNyL8SWUtg4yM3GyK6ULzWdvC2sBCJLhPi/+b3q7SlMMVZIca8F8445CRJh1+Ei vBxYK8Z82Q5+dqix1VvMbUgfzbYQYi3VaWOe/yIuJm5uiVljyYITwejRypAHeB8ElE3GkYJL2rV/ f10g4uzIf3hdZK6wq6ZGl7nHIlj3GU87ShNmDm9C/f1DNDvmvodJhNtmoDCea20QSyx/U1EpsiXw /Bk4/ipn9bEqWSV3uQiHhxPEzZsp7V8oCvzIchSiY0YbesyAiaNyApB1N97XSLOdXVlOD+67RB6V LfFxc4dfuAiD/nm6PVJP6pv4ikaXbLDkZmI9v9CHGKHQ5wxBWFdqo3kKbljUEeEaxvpXYDnch6KH qLiAD6Q48eSYfPJSBm0x2jD/RfKMDMslZ/XH9Ef+U8wyxVJfNo7egLnKyQbTbCQF/Yg+M42qbypr FocsldpUFhG/e1pbHDKRT+pLOSWnQn1OIoShYcvguRaHuhFU0QpjdJXt19IWSO/VG5TeheBwJReX ETmqY8ukl4KFmGqsqCtSK+CZHYUmwublKOkVHD+cUqYeEWSdlGD9mvXPNF/vPgn6k6HzBaOu4Ztt hWtkCXfSvPXCBaF7PeMRkMfvesnUPwp5BncR23iKaBm2FVRpeXwQJCMWDc3oxG5A3WzX+Jzzf8pI J2sAFbJQ+dT+dDJa7DLfd9dVZLwT8lbrgu0D6OIteZb80s4ZIDewqac0We4w3L4ZdpgsMoI5kX49 pjZASu5Kh+U7QrbkrI0PZzOBGEsKs0Gl7ANaoJvA4kaCVtYM77kuURKeq/hTV3n14DSDINBADWow OYXXdWFzWuIWC4XdLN8QQkBfU6p0/z8PTUHzy7btPY8XXhGpfMItvY4Yi2QtI9tY3KAX4sq6UtbQ f0kmpYGGVyU/D1EosKyGFSMsRaOla5i6UtiX2/rPnwU4ahj/EXanqKm7xfUshqG+3xZLx6EOFkxb Kslgw+Ql6Q0SrcTukUiInVR2HLj40x9TNxYrNoT0mIoITHGo7KuG2zXZ7r6X18qioKnXO8tl7oxD vP3EaiS6pOZtEQqMsTpm22YHhsMbTHtSwmoJY9+jfPajK/niFNhdHCZdOXQg+OMp7NQeo+0YQ2ua vzFhpmILdH5DuRi3OIaEyb90e3GuCup4F+K8+tZDXti+EMHtp8BAME8AM74qEIKlWRD4+3nrNYB4 xkefgrZ0XovZjQ2ljCZiATeBWX613VGn7d0c4jOi467GjAbyCC1erbtrAjCmiNym7e8IfrMmYGZe aMNtGGoX23bFP/0zXWDY4VS9H0YhxrzIuca7hP7yAqZs65aCYyHy1mXAVbowupTzVfRfVwSYhvri 2NDxKK8RGkAC/R+j4k4iZXHN0B8mSMIvxgbhyl+90J7mM1AecAwtgjI0trJr3KKlKKWawa/mrL47 m4NmEhoYKxM7ex9mWnzlTTIRhm1l4Uie/QAMyN9KyQyF+HdpZwoJtUj7wxCkL8wx/HL8eMIEo8iX LG0vtwyJMG5wKs9lTANQ7S53FLXO5rrYgcLjNObeDAtTFvW87bT4p1sXPoW2z9JHQVIZD3aQcYjf nYC0jH6Paykey2WNXjpi9PP8yEgfPE4EoJmff5Xp4d9ywPUJnH0W3hh+xaKaXt2OyLGoz4OD1uLQ hA03Fi4E7+Djuhppq5eVWk0/hz7gVoVFMbafS35uQxuNXjaaVY5fSCeb2HXdztfzsI/84OpIhLbF GvkPWlb6zFxgoKWW5gqdVMNvaGAyy4hnSBd1zNri5zuHVhcM7t1Ii3d2ExelRj4zE9uhQaLKq87b 2oJ09qyp0Z/j0AHdU0AT+iKYlRIWm74aM6TF09T1rQXGCziVszpEKsQFqG/lt8LRIcFyej9V9cnk acp1NX7zGtIv82dNrUxqkKI5cwBTqGEHghS/zzDxz3pKurhntbpdFx0rQ3f+MTF7Weep7uw1PyZH lhdb46umtAebp6e+Y+oQ8qXIM9yQ5OkZoNCXuVHwNhP3FG86H6EfFn1xK0VaCnZhuWAtJ52CHmOz eZbAYLy5Kt4yQO8s0yJOr3ndEKN1cPJuNLjXcX8uHpTVAtSKvMxWbt/OzZbEdjfqFNItgrqultDp pX5bd6hpBDcHyoKU+ICXB/V+kf3NllzDM5x+SzHFb1qa9A5vMWznxSWZytPyohget4mcd8nihA7K wvOwc9Kj6hEWcUZFVIjoAuLxbdciUEP1uaNLHlxkX720E8h1sn0zYYeovB090FDM/qOfCV/ey4mK 5AT8Bw5NczcT8ect+AvRoKjDPxox7D755UJmQ5BbvjOuRbl81Vgwd4gaiqtSLZ3TKgv/VteVZVYL H8Tx4ilxDd5/DgESIUyUd8IWaebWmG6zrYGDW1ftlnjteLJuHk+XtDPL3wO+yQcl29/zn0zSILgv 4deo9aerHP2nPMzXlbQZW9dws6UIt1CMCZw/54jj3U8fLD4mNI0v6eRu43Nthr7fhMEj0KDQy6gW WOtUkegFGChSst/NoHIfYcRibrkG7Hd4Gwva2240M2E+hVKrJAxzSI1iRoFmeGCGjmBm0jprp/+v lPe75OwAIky6oN+8OxqiIPkR9pD2lRWhUrKfjVc1kroKtSDwxaP6wztsPSMPh14JJYH+5UXKZJ/w jPEYto5sH/fKHmMjtpZ2McU03yT5hyexioepZL9wkU9yFJMax+00N4XnF1X+6FmQL5A2lBOPkPgF WGo2k9PmJDhYtB/U95NiIdxJa7tr/JHqt7kBGQ+1/G0W1DmnXCJE8NKrxsVxjM7MR3WvPVRbanPi rCiDHLf3FPUEvqMLGBc0744WWxBUCtvuD2IHKgogx1l89AKZY/3Fc2lJKF15camNYXXeU+JPetut 5a/qx2I1LWRtfGP+DFOpOHJfVRfrBd8jZcnrgVKIgu2lk0pxWvF4phg+GtaDDUoqAXZ2X+3YTHMn sQHnZ3eI27xItY67sbgVQlRveop51m2J01+8lZHwewmqIoxTr/488Apmw1DQNryEeAAniG/7J1ym bOC2vVAcZJbJhf3R16o5uPxAbX/uTKe/wnMZCFOGXtwX/cB/EO6QNAy/XsYySdUiUdbYpIajZCQY FHmRFmo9NGtyInP1PRAyYPUQ1SB1UZFfi5GbYJO9uh2stnfTAVeNNrtqPv3j0f9eSC/WiZt5iblP uALcp/mGk47PrBr2N4CcVYVGo0AH+2KW0Kq/OXYLqi73qVCa3bYIY/sLJMD4Quk+T1XdPU37Fe26 i3GO/qQDwcHvnNJ1R1iqT1T7o9y6ZXh0+RoOl17vyLmvYlUhCvfJTJBvvdvDieo3mPUBmoYWJTLn MvLcEVayABtv/EAS2A9MK0BpYA59jvgJyj9UTYzUeh7DMVasY7qju5ynRymwGOOl9DpUSP0o0BNM 0G3n3svqx/aPuJxws5QB+WSIFpQ6JYgbZPxsyXcD7Bb7G4xaBfdUjrDlTQwXrbi1TFAY9NoWIOby wAb2Gc/nPcBP5jK+D0CE2vByyTRzkD/TTtkk33uazkTvvQaAxj00TMRvxyBEzjFfVp/povXWz/1T 8BRwdGITs4IWrI0qhxxObdaAJjEItrDv+34SakuwyOt455XWCfQAIMlP0tKuEsAeFdqZ9DsFBC1f kPHP4rMnoRrleTWuFEIyC5DgxHk7cyDm5fqTbyt8IFBgDDS77D39VLI+hIh01n1zrQJ6CdZL9tFP MQ6ZYTiDeuMZtitw5yQi216s7pzbWh6Cor/oFcvuLWV6AKVHMhU+BZENaVoKeHlYyCEi3LKGVr9H bZwn/YowLjNrImYNX2ppN+a6RPxBchaO3iXvzXOHQY0YV0K7zD+YnE/GVkioQXxYvxq0Eamo6c0K Hfonjq5EjJwx/9xR+EDSdM+HL/wpjuOjhQ2kDUjSvpi/CgmNxV9s10rn7fjG8VBdf/y0/JD5MPrv 2dieONtKhLsSuchODMEpcRtOUpIeVXByXWtDDCkc6u52349x+xT3ZhHDBtrnjoOtiErD5rZ1EE4C imAWljLsOk6gNZckdOZfh2xbXIqvDR6tUYwRSDNkXp6PGzSjcIgmQ0/hmICekZ6PmEvi32pvZKSr YKOEBtRDiA5nJBuOfoJRGJ6jdx0kUeSyN1f7L+Io+2qsHKYUlGVnErCkILjSvFrsgBWsR5/oUEIn iFzrXI4j1MzZc/rGGdwBioU0jqcMo+bsFiKSJ9NLJ2WvFG1u9Qh7N1uf1dabc7Q9TorSsXzu0ijx vWq5XUE0JnldtKsohNNrtmNPw0Dq6rcLWOAzq/w/OqTVbjWU3EZBGqFAgGwk1Q9hF2KVg78isUR1 tPlwHK0Z1wquaLmmEUZ3GL3i24y+pvuwfpA/DPG2pZZNbvQjq7BkVjEo+HCiUPPnDO+xOGm/SxjY LwUWXOxydw3y/VznCL5oTyr6D518zyQAfGH0boB+zASsI6cif1EsxM6m3AGZmV5CoBZRxRCOgN9s p2lkedN1/SVFOyjFd4CBY291nXeNlVOHvr88ZXWGPRdlOXnxoySB2rTlwqcK/WEE+mL46I0S1ubc avWmPWpOaK1fph3wk/0HyMHaocOEd/kSbf7fUCsqgiMhSsF7Xv5WQhrp+R78mi8wN4Q1jcmSnip0 SxlH2DQCuLMWLD0n8rIpqv8pcHjFM4TmpC+W7q5HVaZG1Fw7qsbVte21UROVEcp0s+6rtvXU+RuE lCIKXdVYPXfnVAjtEHRkYhhO97tnf3EtmvTlTxH4Aut2t9drKij0R465UdKPyL6K2Q1z8vQbZD/F ms8sM4UpGyFNmptHK3QwywdGRDfn+uraGL1/5XRiFgAHGnFfItBibqaRFjEAOGO4Faj2Z9V2mbmi FxNzK5S0UhX1akT6TOYcrZhrq4epHbEnZgunBbX/srHo6TyZwZIWY2MJtuS2Oo3M7qVVKTRy6sqj F8cV/3X6fLpI+AGyDi4o83ZZjgVxUsCQzBuhGqHHp0te72bPOLLyYhZ8ncY9jzzIb0/+onaS49U0 viU4sePEW61NvRMmp7WpSpeUoYi/HGUx/i/S+k8s0GNBFK4SNWSSsKGEa3YSpla3BZl+8QdFMglf rrmtDJgwNbpA+x+UMtJdCY4Yxxm4VRIwkPOrwUm5EVMsZpDpGwlqrK/d19Ya3EZydUQX0uPrpLu8 b5JqhI0FiZx0u2K8i82F7dzi+GbGiGBPLpohjgorfJFoAU/V0C4AtngBI56hJFshXNF/qOR/YMpW 24BIvJK69z3pyjga6K5w+J560FdTegxosF0VXch9+nfY5hrGTwKMysnvOY2QfBBDrUwHvZrHZPBN k+9KiLIDn88YyrGJ69WwbCXJ3QuvIe87NWCoVVP+GV/I34+IGKjlPEgDn6sK0G0+Lpvk5eufZaWn BJxCrGccMzqg8BrArGwNPhbuSAs0gYGfw1SUHUQLVQEc76DYBWABCGZ8aNnqYMY9s1VICG+6VywX EnkI972hyuEdCjj9puZx7Y2+CDcKfpI7Jc6IFddtv7dW+0bl72atTjBY5bm51lPrqSO3WQf6jqdp EJDLuV24mIWQVb5UaRyouggI1EQlZ5jRBN/Gs7EwMF6TohCdVHuk2ZjlKfgA+Na4xIVilvWQ0o4F T8B7bwIxpy2PXp1zt70iHvYSbMmBleZWGHql6t4tAtimnqDY5UxY/P8/Q26PqpAa/Wc3DAzTIX3L qpXN2Cje2oeQatorVIxLLXJHHue0aigbhZSQe4XYHoHZKx3Hxahe+8eEvyntGbOAD1XIX5xUE/Q0 0/pdbNhKcW0BPCmnwVe9KUn85bdrunxunCV2raO3WUZ49EfXyaorvZ4f9eoPNoED5qz/7Fxk8+6c BypW38brgdKP8bCZWpBI8QUTt17c3euiuRgkMkZH1xtsEisF0/qkqSO0Py3GSwCa3E1mG/DMr7mo PNv6JF7WnG98uLgiQ4l5bD7LgHXO5UM/6uQ1QaSQKIYi7I433I3toA10CN4iyFsz5JZSUifsJMM7 drxJ5dE7F7iOjYTVl2uaYYsBQbwTiRMuta4F29ecINlxJyI9i4oqSs15uNrTITJTOFjQ5UP9gpYW HFQj0/D5pD9j8hAk3EgCdYNshL1BcpFBzdadSDDte/l8QPStcKZy4Sw183YYTCXWmLYgUuhZgJRW 4NcJbjnBr8iNFhzBqh83KygNITXM/hS2c5g8JyOfmaVzisnk2pmdCUHVTf90RD2TGEV3fECAmX6h t4aSDenm8dNXd/tBsxZ2hmGfdTxwJAbR+4RbgZa/yJcaIkLrxOaCbYMRg3yjQMVMgc3Hc4T4Y3mj 7kfLOtqT7RnIa6EL+eAY61LZxvDGW8cmhBRASSSGRHSYlc/05VlwJiwEBEY8hnONmQND7i3VtQ0n 5M9/BpzRISPwj0CtIXzotg0DUhERh6JBJSLNWVZvt3cMpvQV4OgHc4u11zwkoisrMKWxTGw42wab Qbcc3ZoQtPfX0jGtLUMCjFkAxLBkxqQTZDAGI1UVOBURXOlbZbx+s5GuiGNSFGFLJcGv0O3KZ8Mq jGMo+8E3uNlYF5MDGq3f4LxeOaKCI1YwgeafbdfnwO514ka0CPWIDQD499w5h9WiQDNkRCw6FVxL Vihg/+v692ISang/plbHZOqXg+f+yak9e15VKzSchF3MA2x0RkWrEzsG42GLz3329lopqOaJCRIX 8krvTjbEFB3C1p3YnHtKQtZjpw3aAjMHbAMl14MGjSWt+Chd52r/D5Ihflux5Fkm14S+87Czl3gN DX55bF8FbdMv5N4kze9XDTfH8dn8Pwpx6JgNAbmlZacdlV9r1WS5BWVnLvN5/eOE3ZrAKDiZivBu EfA5A4LshUfw+c40sYRPkSQDfSBxl80ZYpPeDoOFWJj2tKciofj8oUHIMO3ywJ635imFxoUUmVtB XPJLV0C7F+DR75YwoYOyijeO2UVoq82X3C4SPaxZ8xdikjxUneGPtHCMC8zHas2+V9T8CCt+7qxF JSK3+9trWqoLRMIGXKhn8fQRVuLKDbWL3eniaUyH5HSwkdD2WLHWs7zXBs2eJAgdmbuBicyrvu7M WXep0VyiXJMRk5TMqzr0g8TDWimlgcjqkA4ym5GjLuf+l50MmZ2hm1uM/A39ER/ShLuZGHhqD+EH DqgnjXQH6HPM1sD8zRZAksivxcGsrsu0rGvYDtZ1KYq4aJ2vgC2P1O+9f2rNWW8ycebNoc6uPghV 4vaUvg+ir4NHdg4KzOSeM/YJjor49z/g3eQu5rjrKVV3unRj/93bHN4++JixAQT753pJXFuizwyj 7NgCNdv4EyaMiJ0AGRNZ4f+z8pEaLbzj5HoXWEbj19rsNXPcOOfXt/QvwTnjjAIUKvGvoIEacDiP X3IIOenMJcyLdNvFhC4Emqr/ghWRl2KGlGq9LU2dm0AnINnx+c5wCGmvyRjETO6Npb8bO12h9l3g 8Mmyo5sx5X/3XJtZA56+4AVsK8TS5ZARohShOrG8JqTldG8VrEpdnWdPUKySDVPtKR9qdUyv8r+y dL/qURBnaPrYT9nef8C/lzBUebBK71EddXzLhoY/o2zfbln7fPKKUsI4kKgYRCDx7g7fR+0ljTq1 YYh47zpHq70VEW0RP83Pr3WcAtMl9TsVz+AEkQ7bcQR9dMUmgYPo3MYp8dsk36geF4MRV9IWLX7M IzMzzIcoi/6wS8iPDo6Qplk8YdXUFZ75+VPrPtYKiQYhmFHlVgOOYJaxKGtex5s/0e+NC6zM0JFJ FmFkC1YpA2FbjFC3fkIqg6MnTyp85dI95KbCQPzJCXZThSug94m7dRm68miRvxj4lbTu+92fnhKu I8NAdT/5KN5i2g6gN2IMt+ivVOvb+lWczIgjYbljxtKgwhiAvl4eSHL1uNjE1eZdjsD4AJkwlmGW JBkV29jefOCsaYlkQEUyme7xon5Pnh+crtF3E8lAOWEAZ+QYu8B2gVHe0VRXJsXM44TAuKLTjbxA 6BTQ+JISOZiM5cW4EVsqvwSQXBaq+cRT92l1Cv4wULXCjH9XngZl5L1TLvd+3Sf7VEyZYbTxcSI4 hH6r+kGwbtnrKU4Qp3nWBsnKqteT5Hpa7ddUr+1obuGuZGkPGDgR0UYMz+CaCy2xYYvZ0Dd/e1sm Y08J7PLsiD/p6FqtKHIlT6ls8y6wexUnvIad49eU8dYntlxHbbZfffLaXKhUgVid+RFpdeNQhmQN NXLWGqrWSevbK9tb60cSE20vUblyDAAFoJPX3Y/wTDJBF4HzDbssxeiRdGvhNt/6b/iFaSduByWI 940zqm0AN9sOlbASHbpADg59b45ilpXp1ESn9U9y1HcSx10bFr7gpLgDXAaNdpuiWH/4h7sQSzs8 1VAM1lUS8K3HJ7hz7eIa01ka70D12wTNexJU7nmj1EWyc1lTxEDePvyeQ24tn8dyHNtuZCXgUb/V p+T6e9LlK/8VHsswkPD1KNdJLXDNnwKajhMZxKk5Hv2o5CPKoYignJ+PkMa0G+38hbErxfplEU6p rM16yxYvo2Dzd8RB6WOKqHGLz9gEkc9DfGpDKbMFeHFF/hIJZ0wL5FelRj2tzHYT71RI1NsYRcM4 4v2I9AePwuLWQnGQLCFZ04aub2cXLnGUi7vbIrc3HdPFlDNUT5KJT13KNmGXDEthrCFLcbygK8gy D6+hdUI2qFzJXm+yzSB/okWstkRkSloUWFL/1kHlE78Gc+r4xs4styK5aogBkGOUY81QW+3o8lAd I4/QsQzmsFTvZc1KCfoPJMrSMbdxova8t6SCs74hf4qRDZJptEF674nhOVmCuH4PHqCrbIAQx94K 6LBIlj5XMzZvWp9w+sORZiPj1r2Mm6Uu3ZKEWT43Y/9PuZPczLgwvxpCVpPtYCmlydB41iy5s7gD DKbdx2fde2Cx7im584J8GTj3fezPxwcJwcRdAEpmJgIgcORkdxtXPcbB6SBkSj5GLuVhrN1NvL2y NpZLuG+8jy1B9IppMo55XNageGAxHgpOnx/iwipp5yMxRw4zEKkXT/I/T33Vs2pox/9OjUaHwPJX D1lH7J06iDGdzmuK2h9cApWklrRN0bHhvin2jz3MVpJQHIc7d/nJmrfYDS0Vk1L2YuhJUyJSvUet A9VWknAoLCvH7FLZ2hYHXHSEJWsPTd+aeEMqV9EoWBD1O3KnijvUpyyvzYEIGQD2o2t5kGjqzx0H JWVphTwSdhSbmaUFzP5TQz89o9dVDqTLc91+xqwLncXZTsszdQ+Ssv7ZNj41twp8pGwVbRI39Q2+ idCv4Z0g83m87jW9uZLwZWO0a9lGTyPVVFjF41Pk/HaAN2i1Lf6QEsqMujyo9aXZXplraoQ18c14 PCYEU0lD9nXuFNZiIQRUoICMf6K8PAOAS0zW8pEG+AKNdEhrlvwzXtHjWB/tk5MKK9WU0D4hh/qO 0ff/B1+oVEJ66E3riWTRelyHwGVSk5+h/eMXSnlNweqq3xtCIv2XnPvUNwt51nu4ds98DudY6W87 lL5X+o3k+Z2tMXRz6TJi4Z6tpVDQsHk5c2OBBDCo33ZzMuQWmwQIw5pujhJpO7MtugripJsDHUZ6 WflNpA4C4Xe2kpIoSu5NIH1JjnfpY4td/yi2e8yIU1CjFhCceyi7eiRZEXO5lHRwwPxfJLuGLnho kEl/fDdu4Y88K8PUUAg9tKmHMDWOm07yopJSsKmYNKQEh/VKrxzu8BmyoUDyfEd9vz5APEnFu6ax aE0YVWQVEvHCbeezTgQVfigF5PpOPLoSSxSv1AtMOPB2Cp1UBuJENyO/xxjBE1YL88bCqSB0NwSG sYmhsNsm0/N5M08EyGlkjJ27IuvR5BsPtEFFAelR50aBBI5VHHtbND8CvBM7+8HDJXJ7aiubxCfs j8lxRW2/fjmaBxC88KL1IVknH9nIOYgJu7SqTL3md2kGn7lJgnDpEDLLtSBz59vmTYtJEM1SHxoi 7kOSTNZyTycu7lTrjwa931Fv613gcwCh6VZKjxEqrGVls7KOF3ph4+zEHffvKXhTBpxoezaa0lFy Z64jVnvxSGNHCYzKqth9PD/vaM6bO4ZQKDISNPhiUumdxHNxuC07uC5i9r9SErRZxHgMp4Cfh4gV SAXQmAaiY/pcTwPxGiX5vbjZHse6qv8x05WEx/lhqSEv7aRIwcbUzcshD6355CnSnHT1j1jeXG4l xnFwXVy3hDAIyPf7Ul8EXBzDMOclBaa1wFVOCZbT8JFPFPraQsj7iCv8h7n+Nyza2k5F3Vi7o+IK Tzw8H4SHkHnJJltCSF6d7qA+PK5JXCPVdqpn23g2ikuWAO1Poal9kXft4jr9dOkf5aQQalrRpPjx arYFX5g1l6bREiMnDY5Ls+X3BBJ4cXsF5TUf5syCSEEs2RSFsu1yJZi9vCrCc41pBU2xRIBAz0rm yt3YVBsjKx9S2d3kZIbml9Ryv+vYXkkYd08yjQ2MSg2W/tXpat6vyI76M/RL1CFImcojUM9NBSiX iBdpwNnv43dMvOEXGceTpcHLfTw03zRcJchEKiJd16p1ZNiotvjWKaCiqg41ifwTFQiLlIsr52R4 hTUTqphRg7dBLWVe9hjpb303nQXJXJDoQImlH2ZJgQMDkMI/cvzcSbGVdwQi82VAWmmdUrpWH046 IE9GOOsTnnNVd9EMl+pHtjPdQnn0sFcx899e+Kf8zPd13Hsq7Ibx31h+Qdv1hn1PY7xngtUjcb+w rWpAAgp9SRj3wCJCB7wAUYj/LKG6c5/Jro9Ral+4OIsvOapOJ7lKV5JzOQoF3PkBo5J4VRX2I3O3 RxmbthVmwV68zQMm3wPbg1jdUb0s2CtiN5rfBDCeH4ML9jYv1Bmwe/guIFJwpFrgp3kKuy7A++oz tX04JiJ5IUjHw7n9ybiPjPR3Z0RHQ0gQp3bWwES1BIzXDm5itj2+6z3Q1a0Sqa3edGKxpJYst/HO QP9c3BAk/ImpGRl/0ygz/R3yeTVpNM3kLptkFrl8+l8bLJzkuSNF8+3105+PN5bumK6nOAYZKTOz KZVu7fP8T/zCI8LzhstgFvRMYMCFz/jSWdOX0mLowMZca62T4v75OuG39WP42gBzD2KDaKyOmser ecWH/8jaVaxgaMUObc3f0/8FbSGQmsd7H0MtMR7lHCiG0MLJ8AIYtrdUF+A7KkaOZrAYQDnntmcm XR2HbuZE2xnZmzN4+uRl7TsV29u0OwQVW6NGZ2GNKaoyUmbc7Tm0SKHNptGFQRaln47cecwLv+cj Y+/cUGJ5KF/FuMgLecotzTCR4KIU3IuZBy7YowNpdzIWA+nyJpm1xGrXZnFc6nM6KGE7jlZhVzAG wI3ffmINyx4Hq4jszi4G8FKVTseURQzXW15SgfvENe5dCU8GHOBeJVZGFIdsMFfw7fs4e/wwWaSc IP4/GjRfn6oVheKgZPa2mS+rP5gXLvgS4UQjKZlh8s1rLxDPlPH9kfwXBCR80HxqsXgCIszQz46a h+kGk4vVl3/U9MmwHX8CyoZbFd7eeqBaPn2iTZUODvA/Scl6H/6gu6l88X/aLCLqUFTISHuCL3rg YY6t9jjjqgEh+BDY1mcFDu+GJweP7s53nl/8bFbTWDtT/8+Xn5QUyVKH+7GLOOFeoYGYiGWMoHwq Nyww1/Mwjly26Ipna/KEwm+2li0kKxh9H/ph+F9GfoprahOwz26HoQSvi9CycmYuDeXZZH/TGtyi vvteEBpYm0UuT7p3XLZBeAU9oL52p12/li1bxZlK+cEVkJXltqfOVP2pLWeEH/Z3kVMzw13X3Uxh mEkazb3Z5FvkwiNN+h36tHBdxTi0pXEPl4beMB0aT2cJ/KigcSnQJIL57eaRJHT44bBOjX3dyOyN dJ4V2lOGawITc/z9TY0encJYOY4ilH6/I3RgWYUuu2IC7SFlTOeCHuHMbcc4oYYCZBsAuX19AWHq rtm27uIX4ixxqIeSVPZ1gWzOokNB5JSE9o1FVpJ8u1rODLIpYTlNKvlypSfTe/W9HZzDH3mvn4uZ +wDWYd7Uh4i5W6KQacotO+TokjPYGoIVHRQMPK6VYefPNft4p9Vup0Xa7ll1GV8TJ+2VoDkJ86+h 7Uejh/hby3HT7EJXzgENASEgheUrQvClPcZtEzQrX08kaDUKiZ85Bve3V4DoyqlCTUedVYCohruT ma8jmtwLH4m/OiG8U7og+ZEQ13mkY7OoV0yR2yH+D1HZuKefgMnx71Yt5EljUOBngVnkHxsP657+ 1BA2YbpnL/e0Vvx4+cQOvFI/H73t4hZcb5T8b8lClMYBJ7GoqOiDxurr8tUWamXi+nVTagbItuNL cZRL1+qwapgxpfQkdiaO0qDOQBb6Km2+AUegFeeiz9axhrbSDMtSWVeQz72EFnl4n55NHHN3PWpf itQ4TnE4BhtODR6TAcaw0f2ffjxH2/T59BI0PsM+zTYk0GiVcj04GyikeVWbqlAzB+5GKShcsvXG EOHmGBmMbrSA/2IhavgaV6sfB7NLY8lQLbXEaQzKLjvoIo4Sum4a52f087T/UFGrdNRCVg0wSRD/ YiGjpC21hjK6fDEIlXPq7Vf4WxeX1RiC0dGOxNJK9wCVH8VV83WZ2XwgNb17gk+3G5gLvt0hlHES 6XHnF9McxNuFOhgkeY+oTPTog2PPkLjSlQ/HtOYdWtI5ajWXkFI8zZYaZQHk+t6+gBvd/6Em6sRq upWDxjcGYN3OCqPuN9swEhmZAN1mAkaV7s6tmaAwmHMuE7D483NChLP8MgVtLSlFXfdvp3VCIWWs Y1HMi1liryXzHWrkno/WKTh8fm0YwIAutjRXGZ0NDHVFW0G+o1Ms1nuwMRStqEfFbxPnk56aeInt GO9OUxAw0zCduLahOvyh37R366KdjaEqYXHstoxU/H2cNVmw02TeS3inlTuUjDb22ZK3RloCNiVq PNrt7kAQ/OvyYblrf4I6WYnco/XlkUHBlqsowNaVbXzqoHJd9EEnbtegG7Uzh2BqS3WBxFYn9CUp YHc7QhQTU8gx1xqVrYGBi0X+ypTJzSCDev2nb8PMneG5eYhWeCmsVs6kRd3lRMKQWzHVLTABm0pr h4fBop5Xehp9jfdsZm3E333j0oodPuxtGSzZeJfhssM+MfxOwX2sOQMdSutz8DGls/sSFMGdusLp CJxBcY/Y21u4sxhyM0UtBFo26P2maCZftTj237HFWFMzYssuhWxFmj1J3cypbGeQOqpdn160+fSK FsAUQc1o4mKt3g9hFV6IiVeKM4W2ywbEFZKuTzzLyJyONhYtTTKWgod921ryphW9JU4C5/uzqzhr kWEt/CfrpEljL/TC3dXJjBBEtXa1+vXwBhc10/yBErnci4Ktuvk/dSt8xxFKCCqqd6RnEwI/Wv0p Udatwg7sAYv9tqh3yCE44mKnomd6UQ/dh/4S+2oNDYKVtf9rbz4yMUnKcn8+w7qa0yQ9tVtCkNny tDXx1quoFRP7G1bsbTOcAy//xN1x+ZGWLS9SJ56ipv2+OUz7QACfVLD+p+GKfyyGWRyv20Ve6TJE rdp1Yoq0IA+Dpwscz0n/WjfLL66RRPgLbD0G2iXzh4GsgOkZCj1LKEF8XMm5myqQIneLJCypnmh/ raIxf1X750TwJTJ7vSZ8fjbdodBq46M2OV9Fw+kaQBuYyS3vJrZE8Cm0cceNEEfsjjDkOnGqgvLB u6vxtvJVN8fVpwnLzZR8HUu+bYcec0ZynG1LJDA5Y+Ou+3dbeD8Nv037xxv6ZychwnFhahbAT/gg /m2wHUhryw+pgI/56OM8iBbE4a4ppuDfAQYfgNuazADD+KZQUXXhQeoQWwqGOLfQ2fIntsz8DC9e L0FI0KF44UoKYVqmf+9GjrZ7hhAOsIhJIQohm3VbK1H5RbBk+ktQ8+kxK8mW7z+UpUYGXqCcowTn 9c6PrUsHprmSXcg7lbEtfKASy+g8YI3fymYPQseS+Dq2jVR4pmj1VMmqpiNo2ISHjrQyJ8A9qfnX iGFtZbq5dT/BmZhv50JTdYnp/Gy2+Wk1XXLb+1EDuneac53TKWYMdO9r5tyz6TkkASm3nfaWA7kl Sk+1X47W5KAvJ5WESU5ZSD042yF9Np5fVLL8z/CZ01lWq8S/RFh9TIY0oXB5hVhYIlxEPH90wIPc 5UyUi4p2OwqHZB9kBDYXf7L0Q/dcoz2nxl7PmC8IGbmC6vgJO6qsxYALBy77HdhuoCl946RpFyNq L9FAiYXOAa0qR2nAph6KlIlMsLYW7MlOmRstNESQL9SPiTqlIdrdhb3sMoglumOylViwHMWTcim7 nLvPNKUt4RkbG/Fz6S9NrX/9cF/OTk0jhBctPSRtp8IALd2kJ8CICD2n6xpuwx2XQXmABgt5L4Xm oDyF6Tlhd20ecgqUKBowUOyzRmdxu9zJvw5fSkJe1qdJ6ZWLWEoeBXI64Ao+7Cvp+M+kwT99oQCg 3sN8TMqaUx2Saj+2eovxa07kBd0YYS79D74tR5t00ENCWEM6wN9vofJqWSJLrFGSBJN9QX4o5+MM Rybfz7PovD6C2Wr6A/Qvn06I1Yr2R/uKC4B4Lyxf+z2yIbSav3iIXkIkCGbgFceImzMIyDSNyg0B ttJz5Ej/fCp/UPoGYCZomAf4lRxCaNI0z/UiKsthpQDZYhSS1xq55Ea9dSnHd9wauSf5ON/gRZ1Q e8RTm8IuoVnE+fJIVwPCdfL3ZAmBAB9olNsrNSPWFaEcC7RmGAqPzvEZTdKIpmONL70DJvzealnC +Jgl/qT17hbpKiiGargzjQR5NabLtLGy2rJpFpqA/sfJpgBjVg0hvnF+f8ZNQnFuBBEkjyakLulS n4aljB6zpf26psg/DJ+VHVDTMvB5Y8Goq1E4f7Eo4PKsAPbmjO03RhcOrgUlra2RBb2R2unA3Xwl ts4QoWg/7aTna5LhlMAntGb/mTm8iovfR6WSEviGgkX5VzCfP61I/vVTgCXZPSiBHRE9P77gGId9 Hfn/6MxbmWsNsS9ra0xB89tAAjARWSvlClFviIvI1d/VmHjhfEAdviPsTx8FUNkxI/aqFwSRekbt ie3XcQW7mRolWd7XSqifZJsOsiL5kSr66qKemSnLxoVJm89bOqhjOVfE2j5YUE5npjRYgIComOUZ IdHml9QniBIFuJbU1QxMwhW2hKwI8fRGqVulRX7+A9cPPlPwUh0D1yR6q+l5UkbYeZmoEHCjWOU/ UtLVs/fQg6koGK27hMjStqs/t3qAn6C7+PRIGG1dGRvKlYyWLwLudRC3CWLMmdfJNhkwEL6dihnJ 1PTS4+ECv9/NxpqVZYOA3+F/PPQtDD78CeN3UdaQBhRRixG5wq8U7JjCJ2+8S8Na8Bz4aZug4zXp rqKJeRaeX8vKMMcLHPXVIlIi4wu+OAJoJTevzsa9gorvbjJ+c/YvZVX3fzE3Jn8Y71AVIGN7OyR1 9GicCol8FMW1HiDOmARWNCPnJF6+L4CXVRAFJGkNx0pFQrNdUSHv6k7+qj+J4HYNygqhiWmPJj8r moCrJfMUNojDkF4eLXMEBzAx6oz0HbmyIJjZpNCf5HF03hrexliybyFX4tCcQ5vYnQDSa8vhQ2XR tXl1Qs59EQWYT8JdvuohRQztX6yzeVgDzHyboNmfvBMxqDa+4ysv9SjHiWBJXvPw+odC9EhmCtu+ 4V4tDPkpU8HoYq6Dp3Un2nE5yHaC/IrSoVDlmVxFoEGOFOx2OTz2jSvsd6jCnoRLDX3nZHjRgQ3y Y+YMxJPvAM7vXNhOwku6YDKCsELBUpiKdeCf5fm23xLPzq6+1KPp6ruyn6DLfSoikk7FIhe6mU1m SrkHTFMYBS16QLNB+RlFFB+6kPoTefYxinB3r+4l5I1zEA9Vn0BX9SbIK5/khCXoLonHj7YpGa7G nDPewN6DYf5zAraLkDgK7xq66Oig8e6HzqFdMFzTlgbqXAOL2Z+LhUw5K7rPpd091cIilLHlPRcV /4Uc2C7D2jg0hq18ua2qvvD3ZiTz7QDjXWnuwvB2qTMEbkjcBzfjPFsCkxS5Bg1BPDbw3QtV+GRi i8gs82PKFVAbgSHt79LM2s/WgkU4xaWYyOO58nNSZ2HrKF84FDMzGQNwFjwz0BuUPnW1NIAj10g6 9haYo569JqQaoT9fimgHdGkgWWYllFfUZR/3PXzgoQZzTGXwjqDgYJxn0T9RtFG0TKFyPg5Xa5cA LyKNgPKFmXvpA2D3XxOmhvrS+o4NKX7olTx+8OlUkUhEV4loK9RWCLoCqQ+U7ZPtE511xJN4U7OC 2mCAZtr5UclrFue3K14PGxyfiT5VIAlcc8zt98gm1jpIyu+wxVZwmStZ0s7XR0dph/+08b5N5y0L uPxJ3P0SgdCnPIZiH2sLTMMOTI/TpYVxOCPa97Ejc+Ds7vlGe+IGNCIklCDHSpBQPlIvLunh7FVj MvIbaw6h9Ef5DiFyto3n9vPfSAmqExD9LNZ/+FiPqaGPI9KdEEO0RPut7QuAWbBeC3M4oHhSDoxs 15pceLzz83ISeLqkLfglnVXYGm0EYlbXl1u69YE8qM6ZGjjEKhJiwMwuiZd6M9q1lG/ITyB28F/p eewmSjCGFeT60tVWAEq5dcE8chrlIro629ZtcbHB0ez0n/HqL2KTh3l0qRJxNNTAbpvLhYIOzpJM OHODa/gLdLyy3cXWrAJifZB0L5SbKvYCPdwwmDZC/j/j+EGSydny7knf9Inh/EZerlWkcXgFpeVi TZoBxAEwRTvM6EMypec/Vjb95DeGIzux3L8I+FAOoCHmc5SV0vLZ/lvmIAfJS41GTVeUhOCKdRc1 iOB9ZFC31zWBX/5CWIwYYa5VbTHogYKU3xdI+6KTpEiJc9VIjSfUY7ZpdUuxHFCVEDKqbz2Ww/KL ev691zrMDLB28DxY9EJl9oHKjVIzHUKKCcXIyoVqT7mLIrdMm6KqoSUX8ooTqC4MmSOXwl8h5ib1 F+4Loh9l1Nq5nce5IL8HuXF67i5YVzVGu3CW6ZENesy0K9PdX6vo9R+m03OvDP1IOjKtHTxK1rEF l/LzbI0IPMjoXKGAzZQwc2jIskRYwTRoTois37LDb7NHXFkWDgb0lgWPZXSK4XURAh3Zx51cWjL5 YJM3f20a5/QLpvJpFkoB+5HmTSOI/YureBR3NENITWZC+o8ODi9VStN1A5W8kjMA+8bwoH6oJlDj CXfF0tPhd2DLRcFXT4TRIjO9vX4j8nLccUYKGWCQxkaSwoOhk3kkTy80mrZ5qpOpeD5ZnbvaLAUg 8DiKekHW2XAMKIQDSoJ9w05XUA+g9Kfw2aRko3Ob3eMxJzGIwVmShi8ucLQJ3i9gwH4lixEqNDby BDzy927rkJE/N4sVWTB9Dmwd+G9ykPxl2oS8oFSKAXBxFYqGaQwD/BbvVCTYijhPDdqf6GcVmWTN uM4pHlOZrDSgWRG9V0GsCXnHsVA7R+VvyOAbX19mJzMLjqwFFO6Hr+M7YyzoaxhYfwSJJWgb+JOx r+fyyz1mw5WMvQoxOgBEUSqTFNKKq23rm8aW79Yz5yZfW5QbGjLel5MEkrv9Ro5rJLqAmIkgI+hj WBrGAPXDgGeHyOTI38olx1oq6QwYu83ldt2vGSqQf+xj7rvwO6lsrFIFY2spVEeX29R2p3Un0uFU KmKZUrsKvjVWuwRwgYq/5ekBnd7ZD6Cjur2kN0BBb/R/VzTk/ypazShWbp06HcRx46PiXfcFlQmB y3XOOUGH0YgQbKZL6WznkAaz+lozxVtYUIXVmqJKeLnHiSp6ji8Ca0gAJyjdVsltQIP5VL87p8n3 A2FCwwPWXSLM2LZErLJ4nmozZIPzj2f3l5LUBbab4t6t2yG9S/1f6ZvYTFTrZmOda0WFX2fKgsim d31mtCYeHVFITSYTZJget8HHJhGniGhC3K+eg09eoMjIXzgw1FTWxVjGx30kti9Gx5hDG6ZJSVZP 22XGWLmI+qlYXTWRz0zg+nR7CsBOOxQrwg03Uv6BM/nSkNW8O54/OVkv5DabMCSF45z2bz1st4Im VGFQjcHq+X4yvX+jKSquNyAIXrhPED2TOZA6FBWNVYoUdKwRQryUIAvkJOBdbLxePZ2hcHP678+i T1Z0Ptlh/c4Z3FXx4IYTMoO8JDr8rrpsknYsnH8bOej0uCWNtFWIRyR5HvMmRnfKxSxqcVjyjnBm /lIl7vK26zP6Oojx0wvWAiNlXTmWQCWrkAONTtcvIaa67A+0N+BYmwLh9vZuRDM7pwWqfY6KK1T7 xlLgOflYq9sIPoe7suuCzKDt1w2m4cn5YKPpJO8OVS0uxoW9RyNJj0RDwgLcWK0voAnsJTsJexWc JrrkyBf5xT+yo2skpKOm7eMic07+VDa/Kg64FfWCxyno5pPVY2UlkMcrRYBEJAW6CFq/2zu0cl6f 29IJiL7Fqzl6qDZyi81sMPanHwV4+dcnEmly/tyn+OBxGZUeKn2p1LRpG/Kv0e+WgnPkbSm9Kosa kTRJWTuGtSQ0m1WQ/RidjgdDuUmJOJhteZSW8jQ2YrJirunoT1ifOs+xpASbgPwO3Bus5qWEb3gq auQInv3nTM3+vIYgdxeZoobCNnB7Tl7BNza8k7M4Uu9jxc8uEcu9QzeHCGbvhqkJQtWNNzoKXqnF 8F/rKayKFDkXKsRj+xI+PVb/MD0ZMcRVRcgFg+wDhoHbpA9IxNwbZSqLQmMBbGFpUEghVjz7Gzza f4xFL81p4gUgdRqe6QzNd+ThfYjXh791JyVFpEIn28kUaab5LBe4v9lLja00u8vZN99I56cHNlb+ /RgP0rHCokBq60egoNFtFgzSuN0gaqDiQfb+1CU8W9N9Hgzupb2o5r+a6mRmRZsalIYUu/oUoVKX FE3DMGPl8qrBiEFCtAk+ix7OaQQPn6htS4YrfZy7oE1eLdhneRVCP4Qk9m2M/8WfM+5Q4X9kwnLa jLq5Nwxrh99BeFoRTLoW4EgWLQWR3NhNSfYe3ckbPllSs+ncnx3Oz0fs9iAB/YnvIwp8/vKH6BqG o/M7YN+gL1ZF5lXi0TqkoP5eMWuA/T2pZ+ULSpvMQp4xlOjX07DmzLxy8G6iQF4R3LvNhSgw2Y2F Z6qXIK1c1BC46UsbxfK3IuZZpBuYDRwXkeeXgdnd8/vsmUt9e/1h+zJdzi8KIkNvksLqXOEq9z4J sOAgkKz94YY+G1t0TKdSo7V4cIf4Jjmvz9Er8vLz8CcakOqLW1SvQTtZc8jdwSl/U1M3LhzyvmBj 40EUc9wImdcVSZyO8DGUtR34Kan81fdi95c90nluOEO9DcjRvSVhPxhSK5bhNRsIzBWFY5r9gHVi Gzap4laJQafgg4n/5meVUBQvfjjn/RJ5m8PiUUDCB/cI1TS74CDKCn5ujAXl0H4mOPCFteXw1QMl 3A2r2vuxeYZqwFB0W/XLX8qKNRsKI2gEhePVx4NNsNyfyyLIAPCgpNB90ZtxdN+QFVPmCDtS6duv 0vD23/54gFLAWxRm9FCWSzx4EKVinPD2tNY1MyepRSJNI2db+j/HMgdcJcaeiC6S1HgRKj0/qaWL Ix71odUYrP6FgRXitn9yzMsMxMl3rshnz9+BMqPXgW2z5Kt2kn08f3o5KfbeE+eiH/yFW7H6h+9q 5WGFTz5Bz6xFBXFGHUECY1sjLz5Ie+s6HHSJ4ruS1fwJYPQMYz1/0Ev2PVkLlYC88z4GQw/7KhF7 aND1xn4zdE+MB5KaIU+dXbOlumQhGv2wx6uVJnlFp85SeCtq6/ohSAxQHEF28dXXsp7r2oq50uRb jVYDjU22lZIFRZD/JCCEv+mjZrkU4w9hmXP+hDQjUYxBER9DbSqqxLaBKc8/oCABX/yznNRm+6bt OuAYvTYqxbs2yvNCS3k4sENKP2Bw1+npkmOPQfK2IsQxdSdvknGPDvBPLuYJbw2Fm17pmTyZn3bn vcq2LrPX9SOxTKUFqq8mLVDHVl4omQpsu1oE+1rOpcBwtU1GzI31pAUtRrBYBE7+9Tm3Z6IymCLC AUWSQe5n8uB/HQWG6WjACbMcvWzvStl41ARUuJF3JyVtH6YAbTnd5jJFKR3BvWHGEIQglX02UZNo eN4XqdtUszJFeQA9LmLl9UWb+fMOpzLS0lR62tgrh+4A1K4ygOF0TPabd4vpwYCUNsE/RZP0g4JY OHfhSQQQZre6xz7McGWGid0wjIfXaaguZIPElyUlyFiQWCyipoXeK0LHQmeB2J2ZtJI1DiN8mo9v TWVmRDXijP8zyNx2xoq3w119GOBXBSizArTLkquRjJAVONrC4xOpq/ukzno/hi8mrY+woRJ398ZT JzpUjjC6Y+yykcKFpwuHLLFhKIxBi9OgIfNVuabznknJCKnz+LdK3SqPYmd6VcMZCIpR8J0dZnJI fYGYG+k7SFFuxu9tlstpKuWKeraKLa1pgNeDRWf2baXeGzKHBxO9BlEoval26XPuwoj6EeV5VYG2 Uxz2hrqL7btr1vnH3oaIFpTobFY7dG5e8CRiN/W2ClHYXjT/SrsweZCOO/WzXTXG0s2KMHLpCeo8 GzESAQoxfwRYx6aL7tvhM4AYAvmLj/wZjgHkrKUx3HYNGNteQHtAHuotYWI3ZknWDvMXg/KJKohq +w1icCEAL6ywPdHCFD2nHse1Pf6a+ZR3fh4JpoGGxR+c9l8PaMj2oygN1HuWXoi83bfQ+JfEvqxY hOgpSACIaJmo2nGCCcSC+rrVL+s2EsBIYs0zoAOAzuq1yDPsdK3JPIhglNlp5uC7qSVJqb8P/6g0 AuVcRzpUkOz9+CdqSB8/s/qUKkYYHBBIxreSB5iuXGrob/yfWBpiZni5FHK/bdn1R6xHXLdlhUsk hKoS/r5bWVCuhC8eC4AM4KcxUaG85u//zGT3lFl3QIM+AtjMw5z0+OdpktTA8kZe9XCCcqGLNL75 cqLjZF4yb4faDvK4mxewrQnuZNKU7uqPWk1STj0fzZB7zv4d0bfuNX1l556HbhLXxCVmgG4jdlR5 arevachC0slAoJv5ZB+9ZHVTcndksSCyMVRjDmFyDHUeYNaL85mgSzPeuEjbcZ1xkpsZm2T8nZCi 9uj5z7jIYcnDKX6k2OF6brhpyH7CQttHBLllU9NSb7LnDc5wsFv9NKMCo/hB/3gyqh1N/rgXsWQM V+WbBdYwxUOmG7qeJczpWmh0Rj9XzROsZkB769AyOU511rQaW1tvnfcS7JjUEOT3i25Lhmxm19dh 8hfx+iMavV6PT/unPPQyUwGZpHu22AqNHVFj4kbib35N6ECbukdoD4vYWLFUdyhDCoOIyWI2oCet Txz1+PP5Xq16NDFTxATdELtP31tdrHLvi1y38mVgUZOJveh8w5800t1gTkbZ3/M2vQDN9R6IHAZU GlLTr56SL6MzmxQzsgtE/zUPRCQ1RTbhy9NaSmkXwdFssXR4FD1CfPJOHApwygULumJ0fvbCjLQ0 SBqrSDL/1YxJIHNco6JoRit/r4FE4sLRaWCdIJwf7P7whhiji4ULdr/sA35LnJkhRECC34eaA7im jL/zM+Rqz1kuPBJvaxgdbjfJ4o2PPu6FfM8entL5lVXhygOTBXZl9rGyT4iOVr2gchqHED1iTAC6 q6AE69GGPaxsZPVFUZYhSzJ88L2flSTN4ozrFdkfop0p/lT0Qlj/OqiulysTTW/SwHalKpjcWScV MwuZY9WizVGHkD7AQif89NfRtRRoo/C4CxVHM0ldl/lZgSOv2isqb7xUP6R/1sY4UHmZgD2kaIiM h253sGdbzxjqTUmyjSiqomjONjdYLdedjsAsRv07acxEYbYDPIE8N8QDERL61NvTfSiEeSSpEzmp 5xqpDaDyAiCX5T5h7C8A1fZvVU8pji/pZMPsxHO2fhM4pP+XTlq2HWQ3+s2RNFJum3vAn+Yjx2gr CaclXRPKT81UEUOYEG+7o57wRepVMGIr62kH+QMbVhz7jId+EzM/r7HX05y1rg3Nkti3NDCMtdmw HPkxpEjRSdzCaAMN++n6zAGJCtv2XQMSVnCDV5Ay5G4z/KiyR/PLb7ZzXht8Pg48dbU5BDtpRndb +7JPHRn+O8wQ8pW+kyaAtzpHqTvvctoqGSn2AI7QvDwYvGEveI/435M0Vxeh/wfkCop5nwPfHUJB GXeVzRAgzUM8yKw+utjWQBvuo+sW0KkyIpQQ8rDmM9rwm6wD4m1/PMlMHbrFzFZoqRC/AXNN0SEg 2Nj4PRhMiY67xFGxehlbnc06rtDa637y3+mEkt0g2fPLvOZkDiP1ayo+tHGwOC/8JTvnxOIKmH8g h85XBaRrGFMYF8ND4/28jX55GcfoGD2NLkSmbi5GjuD3uJX/JrFQrvFfEEd+yAUrK+NLhQtgyQ2B BY5hxd74URrkwskYGsu0yDfEvE1j9sfuHGBFGwJpcp0oh9hdDSLexI5BZbju9/+EUOnS6/pA5hTp RSqMH9yaeCl28BFigyju6krXRtYxbF3YJPrZTiLwhkjltH/Qla0DSY1NjYOxUIzLZ1+gOHH+aCY+ Zk4Pp/WGNLWIgUqQCF8Ojw1grhSRqaxQtKl7wX+cRp6NrTifhgjBTqRdYLFDDnjwg4CyH3rbWApy cQsEXYU5qf7tdTHaneJP/chNhA090RxMpuZMmCrS/yo25gcRsaF7XE+RvsfsQFoBQC1H2sgXeSfH 6rHBFNcIBsVpUO08oZyL7/YfWvntP5e/xAryHRJkL41oZDZcC7mBUDbjdNgXb3fsIz9rQzLgUnE8 q1FFclmRfPZRG7FgAmqsb5tSctRYzwRabbK+Mf2Pqg7cUTPfPcqOfwrqD2WIUSif5zo8bGhsTtoL nwEZ8EG9IWSIPTlq1MR2QO8Nst28g3hOYsb5yZCXFJ7xavKKRLDMFhUXtnqzJdJAu4ymmaSbO6ua ZuJrV9F5gTXe3YbU0H++zjAZUMm2vPkSQVyu2b+92Q1MmwzCaOS+USFd1j/ddqEfVDVZQrRy/U4q vNZMXcluyMLZZ/Zp3MDU7+45KkSKzm/rNTGvXabZtwxNg4r41XS/2/SRAOVBG21RRnWH7RZKuFz2 Un3A9ZgSO4luHu6sa+OEbAEbYby8MM7lI3MzNdGNdn51o5izOL+TUkJaoQImAgICznwf3rvx8WuC mD1YcCKn6POQhaRUaf92Aj2P3VHH8/vHZU50I42jOEpWWdZtU/WxHsvE7rF69YU1D4+cizrKnPNQ NQ/pWtelK3CfsO+7rcGa0o7YnnF9vC7kFYyzthtlRpQDTcZ8i5osXecALQ9/l2ZEB6IPMcI9vAen oUbbU2vCjFLaY1NYFFo20egTdueAyR2EPzEUDbttHaQH19YCIejBLLzLiFIHU90IlWfwuOxJuxjs aW0jBFSHm60h4KSHZ0eif8pi37HeJTwPNyNL1uLbdmjOHMTiJPu0ELUQfhHmS9m9h+X/c3o2kicK wFXZDzS33irNJWsAX2Hvvd4mXm9rcgn/HtnN+E6T9TtogV+FGiSStYdyCrUkAHXlUE6zYMa7pusp F6Dw/8qtK22lDEyXUTJ6ElmevlXgxuN/qlvSvmaNbX/rXlRKh88WIpPkRAjXKxU1IH82KMbAC5xx WUz+nfZqmWYHPtO0pK71FW7KTufHJBSa0ia539YNVvNNrsXeZBjW8YuMgHrUqxlhYO6kgyd0MR3k vB85iaEPziwdx0L9cHlNqLPiM9y6lSuzJY3bJCdDrOn6P1PVdOyWwAg1TM7avghjbQcep5c9KR3q ITthrFs5/pOpItuH8REVbhderxr+6J0q+ExU/sdpnm/QdBtCRoqrRPpZo52orzBh9L2ZTOPiNWvG XINuly3o/QuPEj+TzyTNYz05U85aMRIxsWlJachWLpXZS0YZgYGRLA6cH4Kc00RKrIWB97DHdP1i TcNsSJ+yd+K+GaADQrm33fBvQ2Y2mdQa0rDTtdX4haFXslCEtIvQEtx6kbhMS+4HJdLx5qnWSowb zQDRY7AFM8J5/Oy7gDCp8Er3KNEr879csWm2xo9b1aEsDkf2WS2/CCNbfu8L80i6gmZ+5sA0X9x5 UA4lMWFxV9BxLnaxxfvE2hBufmNChZrJywwOWXC9ABt52X5dJWfWUW2I03aVHhp+o+vpBpXX+sui hXBHHb5CzVKTN5QYzsH9FHbYHX3FzPgA+IWw9NKeUnTonlH5OgvovRAIvYy9nfhMM7TUcT0PKYIi zGRtkzyobZ5/wR9tkVrLHQb4DN8k1cjl3vODiF4/naP9v86TdwVb3PJYaI3Vl2cWsY2xHaoXK1G2 dCVhEYt4U6uI/pP2/UwrMZ2uB1Bg4sNgdTBP4cN7dYGgSL0HztQ3t8jc0ZX5l061RB0klMGhgbH7 7BSzU9ynUq+qSHxKg/tzMIaXiRcNScqrZ+lzrMy0z2IDsCwpkCNP5f/+rlPuFwDLKS7bmmdPeTC3 5hpCua4GaUIcsge/EBSTskMgTyRZEGtg8a8pLzIZvr4FWngnpOBf1v7pVzFWajLQiNzfnl5nJYYQ GnIVTLdk4n/yM6TlMz0SHNSyBea22bf38Jsu26HczQb9jQS/esO6RcNdwOVEhT4WtuzSLF+S96d5 CZtQ9ChXrnZbA67vLl+ClAZCH++7V4XIaGtD0mLHuknJ1F2HgJkl5huWAQF2QcHYjO6Ec3ySwiEr qlQxEn0QLEU6Sb0eyyw3AmePmI7qX9h1YGcZCEa2KA+JFv/RliZgth9zlgcRmzU/WKM2HbEbvnwT nXFgpHSyyrMq469JClzws3uiEOXtNOz0+GoudeHsGVX/9SUm95lmrqx2pe6F4s/bJnuDh9T0Bvae yFcPTjRvk+UpvmRsS/j1zytEAKEqGl/0m3ftCPB2cofX0Z5AEKbde3W04lLBM+Ei0eKUr86go1rw 6nHOQ2CZhFGZif/3/ln1scL82NS9z6PQiKAZNCjEC348hUv5U3j42nNfg7riHv4z/i/zf4zu2Vh2 zxdbBxTOi/kjphR8sJy2URm0KjIi32vPfOqRhZ5YgjjLXo6R/dtWBLUf+5ACQvLXlpWbrfyOLghx lRUIMy58lnuQ9ghB2VmpAhGecJW1QrMqwFUhsugAHT9Q0GjTOuPEVSKcgamzS73yoWNu/FN3PTar B3hjnTvnMzKrPZGsUcOzybGlxexoBbysqXj1guL0bF4RoSgVWSXQozmlLdyMx+KjoKkAVHt9/HLT bRoV61W7uv/1nvr6u3TdbaMJ8gO91NDyfiqRVHb6DSqhsPzecOpoUb+Rld4PuJdbQELxCwZQkyAH bFk+vTw3U1FtQ63JSDkNIEqWR0WqXmr0C9hovNTE56SgVHmkVe+e0dAX+PdxGEE5Jyv9beEEXgqL g1o72tl/wvtO4moS0bJttT/VJf5Lpv+s3VP+WY/mSYrAVR87nFDtLYX8sPMqKo4pseqq2mw8+ke+ vKOjwj1mJ0ic8zNwxyi6QTlxWaaqZouYGs/CYtyi3txFY5ta3WhLRee+LoAdGlyqQWiABYOZGTb5 IQ/uXUKg4z92ks4eLJW2aYF+yc6mBVkKOXXjg7XZkOflPeDkT4OR1CFcU434zdAFh78vQ0Nl7oqZ E9xJtHRq5Ff6su2iKi/5aHkRfjDY0vyOiDoy88lkxvpj65airMNj4ZGJlKf+3mwAmx0t1qYXy4Jo CBHeNC8HlvUEDv/pSK0Vb+FwF7EFCWC4/jxx3WpXIqAwMkAaSQKW+v+b7ZftppRK6JFQCPa8ZJmB jixEzGPRdUJRwdnfbNHyCLZsi9nfMjpB0thSR8E4WWA3ThQ60ImvkTA1dWdGgffwYSFyg9R9ikZ9 cwWOXiGxB8Q0/jrQLJGbpsPwAxzJryXrO04re26A6or/UbpDNSuBRQH370NQpMtR9L/yrk63AwVa 52AYg78f05/xiZapQwFhPmpCg8gsbHpF9xGt/z6+6NgHUhUQgj9mRIMXbYKpFu8hzSmh9dqwgnf8 70yvx1s2qF5U2lIzS8FMS8D5XqoOzg2HmQHAYkl12fI4nHp8DFk+a1qlK4P90SUVWu9mwpKPoCSd whMWtAPK0R06xZ9dR9DWJnaUJXKvQBgOQx83M1H/s1zQKESynGdSSBC3Kfm+YmXtV5Q7tmM5qv1R XIbm+wbFKyJzUR2qYxw8rnFni0jki628fL66Hpm42xgRlnf9B5iPeQT42NyO/w6/e1EDX7d72nq/ ilU01iDOTrKiyLqm6d5hdXIE9Z3ocwSaTqXix73TgyYSx2rugzg71DP+QGGojmMHoTaaM0lNfgJ8 A5lcVw/JHT6FiaOO/QsTOc5tT0tcS8kTCKv3N+wgOqzARCmq1bEYBMjo+YOoNiwnB1ppHqBqr72d 5nHmp+KyDbObd88bw+ErDVOR10+ADDGe/PLw2h96z7Ymhra9AdlFMjcXq+YqKH3YNOkzrzU4Z3Aj LXH/V2PI2leihvIgYnMqkb2y5Gi3zTpJ2dvFBIWVZR8mvpcoBg0NA5LfHInXvxUapwKp8ttiVsGZ tDbcA4/+JnUp+aoZd7favQIsBBTZPiTC2Sg4WHCb7m6Pr2wi3nwvCHGKqmxnPDw8tF+cGdG23SUt Te3oefFh7YZ1gz3aJpvhrdQjS40wmHAmUei/9GhIRUbOhaeetrH7LSFqKxHVSLiDfiRkzNmYKqft Ikl0HVPsV/7ouJEpdRkjE1B1vjUyN7IDwyq6fezDR+wMU3m0cQapH2AkYtobCC68ShhOCGQ4KVDq j27u/nM8NLgqWR3sjwKZLLF1kB6zyl9hlz2LUg/YcCKAmPfIXkrcy3IdGo3far2JP9no7lcjSec2 hKSuX/HHt6mhmBisuNAPvWqrbLFfHbFHYRVuFpCmtg/lgLCtL61JTsp9DFeEFAXHHagy2dR+mJZs tg7SaFxYnQuPdy5B1GU9ODcGGQi2dkN+fdTUoy0AuvbjJcDxaFQ8qT4aRKpC/fWDSmO0xp5kA8Bs St9EQrCCxSok7XgNcOw5MF5SOEFiP6Wb9XUmo16n6I8Kju3ZKUs9CF3WwLI8KUx2AoGn7ehte9Ug WPhz/jls8gBEHvtwM63Lm8wtkXHiVVKv8wXBi5S9yfhvFJrnI2YzKcZApzLXQ5IRuCAB+IqVlXC7 MmhHwhVrCFSVM+i1S+OBEGbZDrIRSIr3ft9ang4Z/izEH1CQbiIHEmOVtlP/KC9/6tuLFM+k5Hrx 3q5870HMMf/Pq+pgsQV8vCGjC0NHd1O64ttZQ+uDIcdEdiB7ccu9zJfFyQVrAQSi/JjpTMDlw51K 9CpncNPPY9HLGKNpt2OTD7yQ8/vkQ/umcUuoJeyzZkztoWUj73Dmf08mpZTOKx6mHmT5j1UFPovG oCc+VybBX9d9oBKlGQr3iptQYcYuPgW21l3YORjyeQVgU0nCbTL/Fe1lZNY/Fe9e29GE0sa0Eau7 pF0N1KDdC3V6aRU0qTbeQp9SJmHqk3jziWOstSASYDyf5RIvB6BC4IHugYjmAsXymVNRhhE+le/R cpPg7ZtMjBH4P7NCEr/3UKvHTiVFr8NZfpjBpHeH4kcW3OHPsC9KIDgQBD21x2FwEfAH4JWpSZsL Dkp4ppmgx/sGTcAo7XQkBKMJNk0UuNy+iOdkVh8UX+OsTs/pADh9Pf7Dke84dhW80JeghDubMn4z 2008p5IW2i5+HSoxrzHDyZELq+BPgbbp9QY/3qLIT1cc4tGg/pWOTM2/UKotA8xohdV3Vd3wcZyy cgEnNwse4M2aSHHHuj1ovtIIvatSNVq5Wa0B8pxLat11cJbspjFYFonAgUcGUdamiyVyUdfwP/g8 v5bRmYZQ9r1ppmtTGISHtRkbyc5n2MepcT1TIegc8d9Nw7rZC6ZUjwGzXn3uZc1dhg5L93kiaXiq w4nREif9SeX1RiuRSvs0hV9cSY+Raf/qIDwJSCcSCt9l7rQExooffqPgjJDcfOhztzJtVbD9PmuP Rl5rZ89TrED/2W5Y2dS9xnO8xwFvsFAo68jRVnGbcTKlKMaKbtuiBc0JFPlraa+nxh2jcPo5A4JQ Pla7vqVUJ3toGLLRnkx7aviR/NH+p+mSD9446R0slVHVhhbpWn09jcmvfxbwBRYOZjVUlVHxm7+K 0N2zoKJYD7mtOspP3a8qG27tGptqFIfTh9BW37Y9jsR3oKelrS772Qt6eXQH3AXKms3RLjUegqR1 G5PAXKVIgq9plZPR4P/DiiIiMBm63QQ5i9Jx3hIrcuwbL+/Awi9a+mlVmAb5fX5SXZhSiUvFI9n+ f4YYDJ7z8y6RRg1rP1PtbzPcTIu5hNBBiyGq4HYV3JVhbMKRuL6kLq91/C75KQwGAC02DYy2hmfN bN/+4OiEEquGUQk2U89xYQWX1vnRQXdBY29Gfup6sPyOQDDORPZ28591BRiL2Zif0Z+OcJ1uXtq4 +wRWwJUR+7O5SkuKVGwJko1inmZ+BENmmelF7LDaugRV37BsiZGHAw0Zhyv74jt9jN4IJcExZZ5X PClMott+dM8prdXTXDBWV9qrTVkwhVg8+DWaPAo0WkZJeUaq9pLzpa4254deuuvRuNc2fAUT68RE zU7QHbbJD2IdLxOk/m2xy9pDLXWdYZYahHLj8zbO5mKY6iK+KI4QQx8tem7QdsQg87NLBVQ3zODC hZMzBq/U3R/YPWlWf+DlsX/sSazsdSByIdbxosq9SP7qR09Tu73bchVzmHqYjL1BgautXAN6iXZP BxzyOxpHXx2aqFJdtJMUXyx9naaddRonDOE5EHOrWTnld3vDRzJ1TYkCTi7ita4i3zsLc7vQFaa0 TGYR/qHBUhbbMosQX9880ktpxvMpdHF11zUxrose9QTJ4MAdNumSfys4c+lJSA8A9otlej6A5OJK ADPxoMFGhspXJfKcVlLrEmo4ZC7DYU6xEBlH5HuB088fJ9uuBSRyg7mWsfTP8m3ZY+PtWnDol6z6 PFIvP5a5pZ0a2L23PfJqJYmkTHus1ciMsgxLeK8/NXUaA8SslDFFrOJmgSRicLm64dKKXSpr4ByT aCrqfq0Lr5nUdGppke3+RQ0QwKinG6oWo25+fBiU1EcReOdLsYQJvRwj8Ce/iLn2HXc7SyLpnLeI WnBq6zpEG+5HTIF+slo9d4HkJKO/Pdjd3bqVSFiUJ2ALSVUvMuLCxb2Yw9vJ4m5Zi+Hyy9iD5V8s 6lko7edx03496pZ6X6axdzE/H8zR4VgoGu3pvPv++/Ttu4a6QO7GSfhhdt+gN4ugWeHQiYKpDbEy KsFUshc6N9jnLuesS+cguSRKRMG7Ek/8UIUqpH7MjaQpz59fftLMB11h74xS36rpN0//oEr7gQFi 2W+RyflzTY6n9c967H5EuTLnM54GfMylaHPLLhZoJnXgq/VAtiLjR7yzdW6qrr18+HVFA3v2tKvw rAMKb/QbxlhDDzH7dnYlPk+AYFISYaT2vHiXX5eaGW+4YmEOSlCxKbRDBFJ/BpjJU0SDkHna6IF6 yFdC2tQ4SpN8mEqaiqkiigyR9svso7DMLeG8LNz5Gf1jUPYFxPSjDy8HQBTosl9ezygCOvjzqkCQ 8Aewjv8wVE/vQSCrbItx2T26KcXgNRlRuDL3kRGaPEvUQePkOoumCtG+z/a33F/LFJqxaQUVBXGZ NBrQ16TGc5pj99qE7ULWGTGci/IUuMk40LWzeJIslY9yppMwiu9BWdOCgdTTu78fxilcCmybs4sZ ewff8lN9qqOrw0oCUtKApMFLEeGbRf95HR6oeh6TuhAs7JhEjqBfS20kdi/4K/vmNip16/pRmJ1G yvpc0wX5ikICduL0hbyR5rOliTkihmhIhluRzyL9yqHvPb7bxJe/g/HOnsEN8/DK9zgCOiFQTuAn j0NBtRM4ChfyCSMc6BmxNBm098cnWdUhmqvulbseeAuZUF6YF+Z6dNGXH94fajWGHWjWvMJzR/wk GmjWBK2ztQ+Qr+DrjYDUJZcr2xK5iCgF7OyvH9dKi5XBwAbxgCIHgviyR9awQ2eyA92lxJIERJBd H31dn6hFQl1iVCrpLH+paZsQsGZczHktIB5BD+kRr8pUU2EoZXUNHc9w1SMKTW8Hn+ZZjYxD4ouh 4lvza1qusZb0wD2CdL6TSeODcDTMuZo76KkeuhnSgL+tWAQvMEbq3DcHWRCGmVBTV+6NtpwVSJ71 4zCxhva4PLHtZq08TY8C6iSk4+93B7qDNiYHa9hj0Z6EY9huInNsLh9PV9pNHeK+TGDqg02Uv0xS A7g1MBHJfa7e0n+FXcwp5XTc2lCX3/7Cu9lUeETotk5ARlMRb2j/CZBx3dBfA6MelKnINkAJKlNo X2e1gDy+w3fb790OCEo9RRHeQK0zOAlmyp4fNRZQnPFW9MkALdp6G77YjE5SoJ2ijmhleGxbIwA5 UqffqgBDJ8P1yzPllFS8o6yl+90c56e3QtwxMhB1CG4vFwAgX0/6qFcps8Bqx8tmTPF4543GfKPD mDGFcqLYkPyiffc63ffa9WptcKxMbyIMk6sUGWTwYWPuQbV6rWd3YHcefiHMlwkrz3gxht5IwG2q sUg80pIkzZ6dtYzPV0Nt7RED8A1KQXy9FFiIrT4asNweuZVVWjXiiTMaSBpTlIE8BNbApxx0pu+q ygnNm5IlOgHGuTqyTgxSzvaquxMAR0PlvTQSzQFgLIoZA62JeeSviDJcnDp/U2xKx4baHZS29ttH 1PjkuM7csJLVkt+WZVrI+QYtvdiiW/kJk9bO+qlRQoHmGV02lCa/JhKyqWiIgwyv4V/szo0t0iA9 bRZtXM+tbuURwZrzLP2V9fMLQuBwj/CS8C1baQBy+SBix+izr2CbSVp4gXviweodsjtTxvVl0ubz s8W39LPy8lQpmLo2bGlcoJnzj1AYNoHLVt4SYqQPx3W8sSwY0iA+34k6/MPa8oIpBIlZV8hUgcSa 2+2c+V6dY0qHnqtVK+Y4XUquiZ2a4BiF3aN6ImwPEzRz0IL0TjwQ0aSugfrNqgbZ0Jlho8kuGlWB 6zi1XTQmo2WahJOd1LOnkhP3wHa3oAdaoCtcKLsMudNebLqxwPQvLOSzk9jgoXXkBs5b7874VAj7 TQzLSAqBJj/iXcvMGjZOJMd1Fgmp946XkpH4Mob2TShetamLMTtjAv86sYm7FE6XgrAJ0yg+xREJ 0zWfyqHe3vpOUlxv6LEGwEIr2nVVOihezKTQASU/LYY/B5HgQvz+hmfBmqJv4tcoDZ0efif4EJVQ 1NS82XFbXHlpJDpxoRpexeSIubRShbayzaffLqx4nss0Vw/qAyfmtirsOeFTkWIO9L+ZH5OpStkl YadhZ0HdWwvFujDSbDXCtHuguIOA3zfaKNGckeO14wQesVrqFrYDW59AxkqMgaV4Y19I9t/7Sx5u LkUqvulmMhA3uNcs0jau5eLqzJHDeewxR/jcMTPwtLqHxa85uahwkOt2YiIVcJ22IVENi3ZxFBlG kSW49MHt5lafhIKzMy7ruC40BHS7GETyPoo6tRdx8X4lrpHvTu/38YrShJi5Ut0f65FFrP6/LNMY XpJvA5WfDYn3Wj6xxuzfSiG9Qeqi18fS97DJo7WEJEIw2gp9QtMiGVek42ixTAERu5mHgxaBGdCs PaHMivIK3T0J5sQVOYUmD8N8gbyZx+lXfNuegXG9Z4RorspmnI9PrJPzSwG8MxCSFxCR8B2lN4WM 75OyYZvANEcKg173NWMjXxNG9jd95fXUjG37edkPv2Ei0SVqUKYnuw50Rjp0lx5xvKyb8GKIPd7A dOaorDLNtlsvNrjkWxaxuR9WlaGJ39vnga1tAcwnl069JQSip/izPZAD5q8/u8SDJ5QZ+q+wHMdR 1D2j26BsekZio1b5s+3YNqrq38UBzYpvqpFemCg2ILCiK/WYbCOTO73f1XUDpr+ZwimjklzKECKz uzEus/I+RQ54n4ufYSxCSzi2Hqi4ejYVlHtvFjy9JzC2y/4S2OldoOiJOTSRvpEn3aJFzbI/8aXC iN1GISIu/VBIafLUZSsfEYUZGmHcD3lo0w4aDVXYG7wnM+cpkLrzkXDg0l9EeTGe9H9XqOSNT2wG zcEMUyXQHCX25ETfZa/yv4dhugzmd4B4vmUy4mwPcZywmEmG6r2Xh5IMEbPe1wkxz0JSoKTIzK91 1G88CG8kMS6n8xGpONy7SCEeHGbKP+BEzVhvgUPm/B0cP2UkdcoHtfExnmP79IMKEYTnHHPjj376 ZJje7FprMH5ohfoSFK/CBn4IruPdwSc52dL9I2M1G7sDOiqRhQjpCpTxkkCor88IB993h/JGQt18 dls6FR29q3dTVL3SA/IlKlUNtPE4ZYIpheIr0M/40487VbkPMncI4lBwdPU/Y0tgqrEQcJc+1KoU 82ByTeTTnYnClHVxOktwoUajipRexoKbN/hO4xQVInmI7kHcFO9ceyvzSs7ZIsZWeDpd/4LYRfaV 1fgeh93mSRIJRn8vIp4XAbO+XOB5O2+mYt4qoLA1Ot7aAEIC/RQL1VY921W/LEwmKUfZlAeXCoUm p5Bm5IjCaegEY1Cd81AcdW3WQB5khKzARbkHLAazLS3NcnwHlRVrkmDYqU7NbEx5zL8WCw59m4H4 0nZDeBu1nG2IBDVPScz1rW9xRTWGu7F19Sf9znvWgGD3y6cXfirLxa1wijDJ9OS8XNGGfsfvIttB bkxpP12dG1ljnCBf0NLZ1f1a+7HlpGi/VB2CYm1q/d4Kf0Mgw3vfmQR1wbnIth2j7B6kl01QClaw 8ASKrqTF51Tscd1nogEH35lVNY6RsheSttnLen3l0zlQSOVuic6yQbGu+9DiKrnVxLuVPHukzNtM LdLpiETzbgr0QzKA9BtEfZpA3wjzAWSvqjujBn3ZbWPNEipQEa9D0iFwHvNhBmMFT/FB+OyrQdn2 9DH0xABcDyS2xXjfnL1FvgTEMNTe4pJ8gq+3u+TKf2iUaT8z3jH6A+aSYNA5O81pM71j62YFDsQA HJ+qgFoQwA07sLcag6TojLSYLc79zBBP8XMdfm+jNoYRsp/9dYSHpadh/5DmXl4CLD5beWrW0eQX lU9z/tx03N1mU2TsPrSOE5cGQQv0vce8yGS2dQSpSuSh7jMqAcSiUV9xC091KTJUp/YZcDbYfwUh toG/PqJHebfO4FSMOyNn3NKQuQvi1Mc9h//oOW7R4Z+FgGtH3ogWGSbBpefOsK8X/oyQmSiJUo2B 7muhvQDoJc5j7pN3+W26XYigtmWbW2pTWPfPh4bGcwvc033hLVzHpdd5A/WfqDU228N9ws4V5uFf dSZmNpn5THNZUAVvpRDjqgvo7kL564XKQU56cgmhuSTQhCVfyR+74VlYsPCtzlbiOsYt3ivrzUNY mdM9AEQh8O5tMGEFhKSYxn7SReVtBl8dupiCj3YfDkchFDek72/q/o3D3z8BXjrTTkW5K3Q7Cueb PQjWGmu5ayRpdhoEuDxAllQVXCc8tQzGZAN92uGWxwwa4dVD72EJus3zpIJuGZvsmL1GDDaN+3cP of32mvwIZXmyWBn0Vc7iuz22wHT5dipIlrjgejezf5ZTG+S1dKwC/1cOOs54r1hryKu8B6Hi/nMi ZgV2azJ5rBRgtXPZQYrab+UCdnSfJdLGE6EL5se0u7O4Cc0y0d46PzU0OtpO6KklYgd5u/DGmTGq VggK2tpMgDpPuG2bskch6ZdwvC5KFsYSkm2eTO3xIukt7XHrMYge7gDOphuL9tVUh8cQjyxWS5Nq qol8sSJ8i6NDNJyFwVVBju4LbNHyms3i0+/XFGhhiLG0TkGjD1/E6T9NKmNFzirrwUrETlBlGjDM 1oD895KrtnWvm75wkxrVksAg/chSQ+qVM+NYaHfv4gHCfdy5lyMD6gcEqQ/YgiwCB0E1cDTL12vU I3jFQiiuAwgzOLdjabQMDy3xCGV7i01n3oacilSWe4rdqnsc4TcjtiqUaNDfnnJMq6buWacwVJ0v OzoBhlAMz4sdXZ+ebOlbb53/VCdsfM+2tyS3vxhIgqEboyW6RiKuv14z91RZAHPc9yIf3j2SHrq0 qC1oQ9Nnq+Vr/+z0KYv8GBmkTjk8Be0N61ngyfEzVCln3KorRpQOnJ++WoJfzENA/jJq7a7OmjDQ VBtPBqfIKQjy2ND6dttz0dJv7W2G8vpRxXiHsRy+0wsDO6siaqVODOEC5yfIQ2fpBpm0pkLxjz5Y q+v8ZFHBCk3oofieEOFR7+7piI9VjSWJ+Y82pOJlPSejsAS+1MbVPXJCHKR/kCA0K4KkiOjgj7B5 tmEROSBrR8yMOK0U2+ho4F7cSVgO+H4jcPAjsa0H1CuMZtTbW1BU3xKx8BrhhdrI00mOTLj7jzBZ NVSC4jbfsafmwM4A2VlEHPJhvlKJ0CPngyzGWeOefqi/Lxn3C+ZUtnIuq0beNOSDIu2bXPyOcmAl RSfiApEwo7s88iYJ8m5gIEdaVvgUcHFrebW6avFhuLRXEOzg5f57qdfdj0WZw6myq+N91onoTGyt 4FNJi10K4ifUsgdmDJxTpApbYR0i0BGdviLpBj+iZP+a+g23v1kg43Vl5FUlz9QWVEjnIAfYYfaH Z/vEX4PN+Byx3XiTQdHEwoNq6kt6eVgWdEJiIXUtqh3KJ6lV6TX6D4bqPXnq6sPlp3dBOFp71SEa 0xbEf+TCdYAbt6vz4HifuEydrnPRDAJdpJD1XKo+ijqjWfSeeAZkdP8h4WezkPSmbbVrgdQeQ/k9 raGof20rmT0HQP2l0ezKHEvU8XG90Yy2sYxTyLsWvnNH++mtmFuvvPszQQmuKnj8qFPLhFq65gHp vcpmyJFMFIBm693Xk5h94ImdVvuzixhyGMxkpg5k9lpWhzaj8WGXoEe2POPoN5s/GoV5MDORq8sR XiRilgBFIlEjjsiyJxac17ayrfeDBBO6NfqB5crRnjppIsWVdW08zRCVar8Rzkgtu3TIrpQDgz82 eV8WcY3HJIdvPD3NzIPh7tzFKmJ3T69HrUYmI1s1aUORR2/iYifoljJDTe5nymrTlWTqWzmzaWbE zqXIototNB0Ctw48sVHTj/Kt3LJQp/9SQI47mzOTkjcn3tSCLv+E0AV6mrkxWsgd3I6zCSQS8UbL z6F7jSx0UjWNJ0t9LkWxfSrUnc5+7OtfxXah65jv63KpVB6zbiMlWS20ufUlbU45DFR6SSOk42u5 eNnouDY0sZT+YckAah9ug9OWRt5c2ie4GTJzpqvYwRzEKLyfJ43KCqKGQ9QlioBluHDvUt1eoS70 /24vyZtmsfw8EVeH55kq0Hjb8Dh28Bh0KZ2SRzRbn4DYWGfLfj5k2S3OqH4hquQsUJlquDmq2dEQ Hl52J2UrfFuaiyl5nmEhtg9/68P7q2CxBgoqhz1/Bs5aeMIISzzxgKM56IXFFlbh+xSg72Wri7CF OS4fe2pfax9VJUonl3sqk8bElGs5EMIv+j7ijqFm8PvmYUc+t0cppIMjyShhBiYUrFAx/yOiCO7k Ho3mCb+SL8kEEzyVwspSYz4CufXzq1iXgapgcB4w/wULC2Px+1Xn/2GX3COTPNYcJ9h/v2AIKqu7 pTFlVNs5Jc7CjOhlhnGGqtyno6gquu6yWQ8DdLoEnijCQUclqLuh7uvZyu0eK+olp5sTIjuZKieN J7smfJOc05hrp1cUpQDpxyC5EFjLOC8J18J37rvMwnqc8ZdQDwfhl2Crvhav1a5O7G2Q3/Onbd4D 7Hnpeu7SaQKhuIi+O7EI/yuxQ76ZdHKmJk/sj+NLmNNZB/Oo3yINTM6JvsiiszVsLyGulTPi+Rw2 6652Oq03TO3GRE182n0tfx31eiaCvSzXzIlZPWlFJQkTtFMWUe+rqWd76OzqiUs4KtMt1n265DEG H29OV8b9yi3p+DCJdeSmNhEhTWEGknbe6U72NkZRlEmubL0o/2mU6FVEkkFX6CYIf2I10jB1L9h7 plwle+9gDi3QDBX1Jee41dE+HjfvYmcyb8apxnnAussIdjMdMnmP2mW7iryIhywQPYkmkHNiWw9V +xmPoO2yjAz9m4ngcrb7TGKVZZ8LToVEshDZ1UyvRjwqJIk4z+X6mjfLFnvzlGUbKWufCTMlqrgo xjsrn9upvoLCARHXoLs6RTQ41mmQV5uQ+kIZiIS0KSfaCB/OxmEDrUa4zuwGe2yoGgGDfRu9yxs9 R9MZ7YP2fVzl67rtjg6hsD8sVZTtIYSeJStLP05bIyn8Ub/5rLqUN+b150ICFY2YRQxJ/TcjFFSk g04xe3zNw5o2t6baTTgG4vBGunUcwU/xCl6J31kexGoHjMBs4CfKCRgCQ737Bm6lKx7ZCfzrIwf+ SHQHy+7YvtXqiANXKKuluT4wZ4mYNBciyiK1Jqjs9innKDi7MDPIl8ja+hneAibFftPRUMlCEZbb EUCdu2yviE7fgkvZ1BKoXrzE/gvLc9VQjum8tAdHhEs4LZ+NVdKhmQR4YXfkDfYyUoSia1NbnBw0 SwW+LodOmphX3eEDz63HT7xw/kkLs8N5/VSuJzyKZASTBmicc78QyJT3mQVYpltRqV1xLIiw7iwZ le3XThEKLF8X9KWBZfNY3y/GaBfyb6Xfd27mdr0zgo/Ate8zVYjIZKmp38mHJItypCWilB9Mty8T 6kqqlvv43BXVJ0mqtv5IamXNWX4PnPclWvZZo1mjHaUG3zH/eAm5WjntzUH6r9pBPGTjK6edJcWT flxnvhV1evyR1DXLA4Cvzr/zXzNSRx7elb+JrAHDH2VI8Lqn8w6eMfJQl1c51CsNPM2YNt7sdL2k gd+htUmmfV71X0djonwjTudHuJxVpDg6eoRtZFAAbKU5saPRhHmGNgDNOuypmT4TjCo7nuVMt1YJ kK2pt3zu7N70Yjaa74XOyrUk+fp+/EDbqqfa+ST2s3vDvzVNGdZrSh2/tb5X23C0fFGHJTmAegnK JaZ/lnwn8o8AYYkWD2DigMC9NF7jO+N0MEjIgQMvj3iHgLror5tvHqQoSPqdHbAFPOrpfH6lSnFi /VEjx5PQpbcDzbbQLU3TiRYUbuSQE0sN/jC2M2v1oDP81ACxEM08e3Bt04C396oQsF0Jz3q8DGHv 7lLBr2ue003Q4GUqiNDW5KdUBYteAv5pFZA3Lw8k9KeB66Z3Mar5ztROULsic5WeSiPv58ck8Kn/ n53aRubkOZHUx8kQDDhYyUeIKm3TcFWbK7m47nspY2hQSuN4cvyN6iyqsMINa4BBXbFKCidxnmsc Y78vgLlRUovJ4biaMJrP0V+XpAL3R634WYERK45d+ph/zkkVu0iZJXtJCCGUT0rxFwLayTaMG0Ph XjF8ZXPJ4HxV7hOaO5E1eKSzJXDQx6Z8hxn4lH/M1v6Zb7nos6MOKMb0z9hgrN8NHuPXcEIiKZ8q lu75IZAwqk74wBnwhi/uxGwMEPz6RXAfcf++J70j/3Eq0qgMcHxLFpYA8TlxqVIaXHrOroAvQehe JLlgVq3EkL0oFfdTgIi84AmdlA0513RrUQ0+hMgbfJx0iAUiKfkKperQXjPUj8U2MQvpC3GbarcU 27pRSI+AEFx3M9va+ZO3o49jyFkY5mA3HM3DdLmuYEOuD3LXJURfkPAUhikuLzR0F+2zODU3dLxz hN8o3E4rQXVwygNS5qE5flFpQxh7fJVolTybFey/HfxwcSjlqzIIeHRsmeOg4Y/sXFUEAkeVc5Jh cfLDc7dk4bLr+PxJcv4pbFNcSVlymT0MTD0zYvedTecWA7llj/mnxNcfUk3bUk1bYer0RU/ZBxC1 YImDDLMRQc9Zo4IK542Q376SBd6kbrWAuRce9XD24zWEHrWBSUkl53paRUWcmX2yNZoSFO6h4OTr KSDx9Qvp8+LYzqO/ewEfDuVHBdTnN+pPh1bius0o1E7wPmSQyyGENxmHqoIKNz/HUTV85tSCL2Ff C4noBtoCm4O5NrHjjqNL87omQKSEGfUhA/f7ZQklvVGoWSOGrATnU60CtdtoBoRmgCToi0NoG5UZ PUYlfbS+F8NyqOmmyj4/w3NwiLu5Xa1NhPnzdYlMDXeiMhehM6g7++sBROvSLQ3RtDuFxPE1OZQg 7Mn8CrK5Oq2pT7wIleBYteT7MQffqHyziNbNH5PBvJ7hKfBP+HRUnEPWhdPy8jfTB0CyK19LwyGV oii6YhpVVQH2n7QbhKUzIeFUQWdzSeRE4NJuMCipocYKwATVp58lKN01Ge53cmo1QnYDAFzBU6Hg Tks+vOJxs3p+JAv1T9JWQKnZwnaE9PR4iNnpUlgdOJXhnUO26E82RbJikdzrdkcErEuMI7tEAkHV dY6XicqulLsUbjOLFTeClJT3lDBal2EomCDNn3HpC2Em7NYk3vHHTlokmXhstDmsJ68mplCP6wew rj0spm8LqSAwE9a4c+D+1oBolnWQrfO6bDhQb50M+ES2kFTlwHpASC1Um57WrTFMv6K1viWUj0XD nvb53nz4ld0rT53zO60vEb6/U6CvYC7Ny2xgyfyPpDb5XjxI5UkKaSUtoQZ93KJ8a5s2rDSNmHdU 6UVhPc405MksdJwQKOBHW874W7ghgdR3DxVtBhPN9enkG4m4Avif9WVFq8bo9T+FPjqnJ6oQnchO JoZ4LeUoVXX8aXQ+yYtvfsfAWqcDe2P/XvgrvWy8tU1BcEzLBAVx6JcLVtQwbR9ds7iL0CfZiUih k8MPWPWlEmCwYCQLj9cL8WxHmXuf4OCZkU8+MAn1chLRCPvUtuQr/474/I6Eogk5f8GJxfvqNJ3f 6Q6VlNHKLdFkWpMxx6je95gOfsOb4z1WJruWqCGrqAx1T+AeCCBfw1pCHUL2cWK93wUWNT+P/lZQ BjSl0tFJnwb/cMgqrQSLoSotRCuKrOiSehBmipCaLQAIeR89SbL8bC4lmfWdlLfI2V2vVVnVGNig rTmmhhlQz6tUV76JTUdFb9YOPa5VWoTAmjCeILW+N1ZAJ4sPgDidTbj7NPteG93R+KZ+P5aKbBbc j5EFiy/YGCT26VZJRkRRJAOd6QCeXwlaLsmsxJ73ldxqeX/KsfYLj0xanMf6QRM3X2fPwlYrlwTZ KQ6AyLB5LohuJ55SaRrWa7Vc7QkC76I13BPwfejKCKfnf9f0Lw201A9cjcCZIMoiu8NZkYo0gQEP JuMQDXhi1wJgetd/P4uUQLG4kjN2JKsFQx5EG63yWH4BX58Xjb2VR46lu77aks/fySmp8WzqEACl QGVF5BD1Q79lM5zXfjPJU+p578RJYGPXTSVypBZt5QKccNmYTDWlWq2sCnqaEWi1+iUnMAPMDDAJ vCQRMlVKCgPMa+KQb41NhrmYjCIneQlNRPhLWnUq+n7X/HnD3nPoS0i8NG3fA4Sobfn8g1jkKTTf 5/qdAMH97nq2qx4f4X2YY5qb2WVhNCbYwUypFBPrX7m9xlbQQ+rbTXsIvYTaZW43HJkz/xrp8z7Q ZJsR2NO2wKlSto2uVkX1wRSd6KE9fzUOidvOCLDmZRxVPQd9P6dA+5PNiDyABYRvGGAQsnc/hsRI zkk+K4B0vX3k5k5TxHqer9Q11OQjZO6ZE6Gkt9e2EYzPsIGDBVKKTnTHCP0/tJuDbGkXJSqpGAvu MZPilblL4exV6zyW0KQJbjMIh1JzmvFHhgFBQMYvTsEM3J3V3xKVQyot21aOM2XtBDf05OeBA62T hoJNGC8/Fc7XdXWzKAbZltmJS/Y9sTr+nN9mtEXiYPDHq1oHgYKZJijsUvPiDpBko3NySvwY5QNI 2rqJg8Vv4Ntb5LkDZmmRXnf1+sRoQbc5tSs773/qDxKat2WtClDBw1YS1FOOsnMIEBuDmVfaVjrN tNQxIvz2N7bQZY0+WfCaTqpU9JVO9axBXo2yVBQMrH7kRP11gk6Qvak/ziZNqecnJ7jFf8yHaEXV R2UvPQuvaybFgWdp8A4Sm0DNlAGIbGA99BqkZjTodg5XC8TvZZl0LJXa2njSNh240H61Ndh1f6um fgRyvSCpLp7fv3WQcQhyMxWeU2RCZwdW6sgzlCbq3y3BhuRQU9+FZciT9xcZleECcdXg5/KR18vs 5KCP393FXxryHf+E5eZoHhWUN7vZCajoK8STdPPNESc/vtnF9irk7wDg85xgKulai6bo9ngZA/Iz L901fneErrfhIiyF+DbcCGamBDGOX1OzdUCRvpKKWI0PzM/weAV0u30F6kwvuxFunf8K8WyCX6zX fQUA9gakecM92TUznrN75FK71UExfKniVY/OhUhbxwZCzgfGZjIc2cYx4pXW71LjtO0Wpi99l2BU VUHiNEKuNyO46jR+DA1amt1Pdp58XGkjibt91RYQdOixp6HSifbf+jWFqu68x3X7M5s/nATwrWVV vGSiASzP5/n388IpHr6kQqZEnXRmwHfw3pcC/soRBOief4rZGAw/pqY20TQ5440a6BxKqRzmA54P +/beysR+eQ1MKL99rOld460lX5wzK3IQz6hMJ+L8IW5K7U941hQbq/oe9pw7bN+FjAWyVP1v0LuQ HsUBVxXz2lcMJSDbz9v+YcOCSev5Tfx9SHYSLSXua+QcPFNkqNxGTGU/LNoAB+AZ6evhQxj22qJ+ LzMIDK7gAKU3deJif5F0kHU4qJ/dM/cv6A9ccg6uRg1qwt7qMzqpgI6Olk0FFyXaCZyuEFeHMYua p+T+HX0mIaaeNphlDPT6kpaUJX1mnvGsXtrSXeUN4mm1DVtv8ZVoNZNtga2+mHMy7pL8HnX5BjD4 Wy6tc8OMp+L+fMFQB/IDgFl4mUzmoGVMcMB6xPrsLPhR0n6suSGoOIu29bKwh5BSQrnt8sZpXFVZ ssAeRj63A9gVZ/GEMWzx6nBFQdl/I69pT32p9OpGF0S//ZaMht5GM2D/8u3ldBOWrIq9CLsSJXDU MqA4bn/Uv3p9mk5GH753UA0rziZRgdxWe+OZlGBmyRK/uqQZgO2joeEz8kAdnFIQKltoSIuprfxZ pfh2H9iQJptvQhjE2o44iouaH+MkoWkJNYfspjSW2nENy9Cu/Nlk6g5gTM4ngPI/ggOAJvz/Ps9c aV89kPfcSRMTUiPveHqbZKSNa98RSBwRqnOJfuTByl5CMFaMOOUQ5WvFujXr/XLLGNh00LLR0+re K+4flTsha7DVyIiY4l41163g2N5ETeoaInk/2Eme8Y5UtXF6yMx7E5z3OvYhWu+n2KKMK0IN2Jty ZK9XxfKK+2AifiVQYy83j96ulUWErkgMU6LEYp/Bhsf/6MvsbP19FgIIxUXBsFOnohFZ7xysh2kB b2hj6QPZ2gm1s5mEzYFwMP2cYDmvZcB0NdhSw/3fcvxM8U7/tyhO4odFedH0ed7Hnrm+x/a02S/s FPSYAODf28ekR+IElBe03k6q1O8zQL49PSjhZynaZjf3qsAa8sThhh84x9R/Egu0uddqifVWuF64 uaOvS4xO44os8eZfw9DfFYIIYxzTBiiYXTpW/xPSDqvbxmrBXWZ+1hZt68cEixFkvopHBcnjkVAL N5sue48ijJ/jxTygwU4tTeI3V22IewmYC6TtaFh4RBhgc0bNytjBOo7Ic89bx+N7HGjBAPY/wbbK WHaE4wUkazg4mCNdwW6YqHE5zqoRt4n/U7Rmy53IN4I7WbLKql05gYko4Z9a81Qf2lLrZ/kir5fC SLdgwV1vRX10GlDie6X91l+PEnRgFQ2yXWX347mj9sdeOj1p/r8Yz4Q5GGrhRBRwgEzkRF+8LHSK Q51CIxxzDOtuzBY+g6kBIT871oDca5w51FdeWS6X+aRjvJEK+zKE9xsZco+Pk127nOfamM5avvQg AOXehn1o4SdZWVTY4eqGgggN7A6vxo6Jnw2Ir5RRYaoucPTcrQ2L2HsC+15j3s1Sf4obTiakeBHx L1Xo4L4fMj4dEcSm1aOc3IBj1yrmjawGceRzZho/T5m/RKlhAvyidHYWjCeW80Alj/KML+/0Vcfb dUZ67wfjCy10M7scyIKwcdcyHQ4VYr9S/z9YnLHV/I6sesDSpFxLEyjRpWO1+5rrmWI6LMoA03GW ZUJF1UmRphF749BXQN3gBx7gz08eYtk2LiY0zLJhFn0V4qG2SpgN82Gjo8XLkRa0gjYfrhUq/8Yk zO06F/E0cQZeUPB3gKh6cA9mi4gwXuuBGINT2zOHopPn+QDH0YuYPu4OPKqKuyRiBR72++wB9ZO4 E1MiVyeMRbuCbcyzbgMsa5p+pXHNEL61ND7a8C1FIb5yyroo3Awdk7AOPYcLFJ99CPklmgjkt5Hu dHHUdt5bxC5pr+O0UQuEFyt37dwu/GGuJ9+INW5hJaXOMCoTmPFlrMzxPU3sG11YJWZNmg+CwzXf kyRgC8bNBqtMz/Z8COTY9xkkXn7eiZaC0ZIlCYGeLMPtN90rEaygIUwFJUWjO0fz+QbYDNF90Q6T k7pMFtAiJ3tpSdJboUsyCN04sKSEFEjJS0wrHqwqXhKxq+brVssglIDBQHEFc+hgXO3FamYa4nff k2QdFAhml205nbgRN9BuYute2GPYaShQteOfqXg/r1ng3UElbnnonZpZtMH5/6kDQAvFlrb/bVg9 Ie8uY7blpo/SuIbiKkmu+RPjklDNFaMiwiBFfM8QnnxPCXT8wVrhNwSvlbdXQUY4a3iEabud7FiO 9FnelnNsx4HSp7GEUY18wgcecvR4GL6x4V7eChsxSnAMkC16vECfa6D0/vO+53+IR8px0Fa2GK5f HxHKGOpA09VOgOH4HP5js4lD7F6soPKZ5mUPypnc2BysA5dQLk96lCuI2tB4G2aA04ehcTA7Qi/h NiFyubszw77buhWjM7BM2V+nSbO7sdgFlEAUR9sOOVXgrg2ZaRu2CMA7qlatzJPi6VUBO7A319cB 7cLj8qdbJhPyVEDfxleLljVNh+ZigvoS5ee4DcNh4wS8U+uDSaZab+9qacx+ePLdi79YiYoBoxRf hC4teCXIhUhI0Ew4K9YhpM4UApw+eJY3Z8KAqUuj7gsEcbDhkjFNJsT41wcgj7NWhnJy/YZ2UxW4 TwnrqftjdaKgF1ITSm/QCoAKDg0KjjuRICiR4UTBb9r0oubamzM5+hKlnNpeioKjprDWmziNrDji sfso7zAJ0utmHsSmL6eyCqDtAD2gnt5LSt0UcQDoxGN4VkHhmWVdgsCVb6QzC1ew6EM1ozTnFQLi iccMtbE04xU65Pi48UU0Ran5Do//9qotl4PTHFqALl179oA2BdVhdR69HCDqczK437P14Nnzes3H vHmd6yb7Km0HNChdEzKevBLNnZewXoq+D0YJiIA8+yYCrBPWStcsAW588fPy4kjv2YH1k9gva43F X583XPydBKR0gZOQeeuFotZdYKtTMCiGiN6bCIp1/ww0GkBlGq/pmJmB59nU3VXEBdSL/FDEXXdJ WKRNJofUQcy0z6Z0ln8DQhjZwSJSOYXeFSjSxp29GvEXoHzq1GiVRDjyYROFeA4CPyjkC70/55AB SF2+K9Z2u6X5cteSG5ombXIVk3ZRrZn9/+B/IfLVSyWgETAKifPpNCKhLREejEOBuzXHp2tA8kpD MvbC0OiF0HdpxSPB0cqi8wY+9uu8jWVr258Z5/LX+8aeZV9gzpoIK4qE5CTqGqtsJOA/smdfVawi zre8fLsb3VNfghaVgP/OCVo52S6oJW73Tb0xSArdgLi65Vgqb8tTJUOhBaRWRseekgRs9srDPAuQ 7cUcoeptCEPL5p/p7tniVhgyTMzdsQz0GxTID9wTS51fmktumBKZL2Cr1zXRcAneMRzxasvQO9Y3 16OBmfNZlyWRUTw9xSeckHX4gcq/10YIl23FJiV/E9J6mejWzm2olyy7AZzHzTcdzlN5aNmsHhFy ScI8Jk2yWCdtfS/91sfc0IiPJP23S6eUE761IfMp8xlC2zRPUdq5xHugM0/3PIPH7NPQlZ5hqaHj +n6/bwDenaUqssBU6OJUGcr2R+OCnixoZwYdbTXfuXdEO5HMTv1hgS4ySlUhcJ22a9WPdQicc2Rq T+V2T+AeZkXjb6rHVYUsK9Z80pGgteofha3eDgu9U06BIef2w+cgx/TTCOel9yEMDFRPOLYICwR/ 4ChKjZP+gNQLjkuO9vwNEcLm8bx60vFa/Ufjurk4UqYQ7NwhjrAImf3jNACy2IsfRWjKFi89/EPO diuyysd0u66FLmtQjW6fwJTfyQJrXr73dqVZ/wKrgrmlNPQ4mtsmWPA19V4jXU4hnSmTZ2Rvrmaa HvMMGhBBC3Uz6eB//SYmZYbVCVfDpCD8ujiVikLLzyZDyjKPHQWeMHkkSgChVutvKAkjC4tBjjwm SmeL/7B3ZjYHz4oSy06zoEcgJkjxH97jeFjBNjGaiQoKNRnoMJEFnHAwvrCyYu9P4xS6LnIZ0N0t nb4CrK9pEAV6oYnEcMTmdXKRYfgCNAfZnQv2cc4pIphLZNh5Jhng3Ktuqbp4CB3j9HMLIezMwB9p X3LGgD26Xs7b/4UF8RmaTmpntHb8xGMvKWCBupFNYfdPD0TQaPPc1GN8N10LPmnzImPlATE776lU Y+7XFbZN14NcFO0LuypUoGEMWQHZUoNoZXIIWiIKklPS9YeesbE5OzD0gWBUqWODq1UJNFfZOdaq 4wPqIz6eJWV9jpCbIxjGfZYDI7BPwwkLD7wL4q4sRgYHxo9DFnXUOO1EDTDNG398yiaBMEdYbRS+ r+rWK40agFLB5xAjPlppBaSzSMDJXi0NlQaPy8XJfitRYkYlk7GuQZLxII3JwQFGIU6ZudwBGIjo k+633QuNb1v8FgekPfLQdz02c44sSQ54ksd01mINJmgu03a74lz2VM1e+6z5+Q4f0a3x5FDHskbs hMXcI7YIsEO8uaw44uQ41fnNy4KFSajJOzdQ+SF3c6nqF6WsMoUAgqSDLA4GkM9rXJhhKlEcrTyW VRXgHOi+hiEh1+x8jBx5x/VexfpGcvrmNVSR/OnFQNt6LAMu5a18oezjHEeaTmpLps7NdNC2NGze 2wt0J9AjgKiiNDzwJrG95PNHJXGujjySbv4BWgCJr+V/HLCZs5V4VOad+RTw3ZiINCUPEW8Qp7YY wFt0Wqlq6LC270ugzA1spj4M3kbVY3tU6VCaJB7CzENBsQxOido6RgRAXTcLt9NMOiBd/YqseM+Q BandonQZkQ4yIOen7K/w/va7SgdcTFbcruz8HIq8siNHYXkQuYbsG1wwR0QX9q/8JxZIIDbmGIDl kdn27F4HumDswVgpkbUnCoQnJZ54pl/7KXZO5ojzwJemrlS/zRMyT30yuSaJ9vpkmQGLSa6BgiQg qW54RCg5NNWmxtRfu/ZzXkgqrgz0YiyeYf+VdOT2O94726bRtApMFlH+9faOfmbYBlQlsG0Wu1y0 zz/yV6wqWv1mwA/F7Wj4tkZa38z2HYWGcmC57FGNv/VrU2KyEk1/8LYO9ubrASAO/1RJQF/qMlv8 CarFlFc5OJS6x4Bae4pQZD5nqXG39TDD0TUMmmxsbB7++QVhwooHnaYQ6x9YvogGaMs0fvS2CM+2 Cy/1gE4gJO05VbETKSv4hhKwQz+Hq3fG5QNd8N87a992tV9QQas8mGc7EU3XGxi7Npj7F2r2i4vn 2tlQ61f8ijQrq/HmVhFcL0w+tRh1xHDlqReQhSeiZWsnknLdfS1ePipZYpVM4y0w5yYoGAyyyv1x go+XDWT+5ZDK0lAEMT+G1grxee8qgb8siOnZA1GUX64Kjg3CC4eGGYP8NXaTXMRbjz25LLZ2O3dZ Y6Ir7gH7jXdrwCxpuwJuF47ae10VqtKyfA+E9XH/9CjGnRLCtbi+9Ebp+WoDUyBj7xJIrQXQ/Yko cYhkZM+2xuudggJcMEA7Yx9jYeCkOL/p8CdmusemHcNKaoMhMFK9f2MxAD4fP6eSxuHtqQNxkgQE zodGrpPsIKhCcZGhb7usa/NjtyxX6udZQBBXr2U+uvDgsNF/sMJRZM3NPLk0R3tBzT1alWUrKqBX 4aLNxiEHYbEeR1Iyk8VB60Ctma7Kb/U7GGDf6dhxTmhBHXsL8qvmk7EFzM2tDdgQIlfSh5jFKUZx o4PBByPpYmFiCVR0Eq61hFVPKW2EVy1ahuLLCmdZOsg293Ru1E9Rm6kgwiJ1r0xYIZ9fPT6bdubh 2UntFU6DP3WNGn0JzDquorWNLnHnjONkQaaoMKpEH7dvYBWXyx2+s2TE/gDtayWQZDj78hyaaP+e NZuBCPYgUWMY9qwiYiGoJwGscpuYVohT3ojKWKWv1ctEhozdAoNiE1wwvQFifwMhrwNaR8aAlLpE RtTYbgnD5WFwnHb9OLJ8kAiTRx2coK3lIpe+piYmhGT0Db9dd0reZcU7LFT9PG85NUNkoC4vWs1X KZK7fpqs2weV4IDVDtFynxU34qlqrK449C5diMzV0upgTeImn0oUnFMrGB5gcO+D86jZWusdqqIi oLQyDX5sd3vPP7brC0QWa9XJg4RPYomojGwzCnyjqGKXZrkT6klACOqdYOsOBKmzlWSzTkHorYjh Jy0f2K3H4QyS7EUBN8gN3MX6tZxn2QDNAkzCs/Xkr+ebcL9BLhYMCfscAasNQPKA3CbOEK8NyixM B7lE7gOwAXLFILk5hK4Ef5rjZ479ByizsIwNAbvmpL9c53U7/xwgd9zMtGlYYWD5C5Aws5KYfqtD bmw21O5u5xuPWrR6Os3HwlkH0iKoooUiPt87Sg3SiRhoJ0nWcjgSLteqCr+3Mb6BOeU9sbmmTM0N A+d7Cu/hJTFR+QDB6BtF+QOai7t3I/+FuDWZELY+eeDq4ZnzrfL4WAE4hvOnti2eDnYB0ybzvudg d+7r4CNhC5GJ9zXo6ygcj3havgBbYWHfSpq2KAijqnlMo+mTCV4aRwyX6v44uDRk997gdh2pCk/h clqTNxuwLkDRQqRc2+Hrhlw8LjaFKekVzrUHU4HX9cwMP10wt22YzZIcqot/LqV2dLxxwoyKCfPK vVnHvrY7KXRtaOXKhPDQSe+WVHOGUB4ha99jQPnpgo46IMEy5Wt2fFXm8fWLu5VMWdQFqi60Hebh 2uG5/m/LMT1ddUHqifHulq57DawQocNz2/8F6mKD8rHk3AHqBO4TEIiGpBYJjpmZgiFgfkmX7rjy qpDoEnDRmGv98wZTaKVel4fMwOx70jDdxIAvLjpo+TXBGzqNf1L4udraYZLaH+NH0jR/eFz1HJ9K m0LGGZ00dzGoSe5JoOsHbM8vy9Gnsp/RA+XZYhQIUb0VPIufcnjeJVaqnW31R4XTXCQ/lnYemYwR nt4TVHYZnIDIacewe8DmO/lHWJ6Z7VJS5n0DgZbYu4koVErs8dkj3P/yHWW4Sr+H5wgboK/MkFXs 8yImloUPEMfFaFkKE6KD3g+Ut0mTT/XuL2gZVG9MvF6lwvnnAe6NNSrA94Nk0XgObpo8HsaLPiBT jNCCRy0M3Jt1H1sKjTz745w++2UeY78My9vw6Dv8lhrh7utt7WaFgBZR6tpS8jMQWcfuC5lawjz9 3V8V9lkuD74KmL/v5T0zLh4LfTGFirOj0Wm2/a0ex0SnjUXJPVaRaZgjaF7RNb6UUgHhDYlqTnBR Vd3CCgNMx1xYrpjsktWndbLHbIfVDCQVZEO35BfiuptaQKln+bRjxe14M4vHXOB32yv7VibvddTO V+XaLmZ7ZcWtXNgFp1k3j3JswN7ZJOlQ/ooIrusSqtOkN8qymTjKvFcIVUPgsNoVL/0QFqz6nVgN HQ51FnUmxPryhosCi+8NtUwS9wChVQIu9PUtcJE8hf3I0KE6VjNQVUlZX2UILDtl3OwsIHkUlV1l KSpOtPdEcezCo7A9fpPwjiLpoDUUUKCXdC2IF77lasA9NmT/z2lBB91B2NrkJpPkXlFSDixM5TpK MyM+iQ7tsCFRHyMEuO+D6BCMsuYKMfHACnTfJVmALefyK6SNI8qWhR8onF1e5FeWhhBeZjBpCk/s SUs5aBDW5LVCcLNA/wOXnFGK+p7Owu5iFV0eJdW7DuVw7d7n8+93vJtX9Mt1rFiTj30zB9Yt0EVQ UKjFT9acfuIPh90fgMcvi1fSun088slza95arjPkPr1vpgNChwz5cRhxn3jBd0EGVPKDj7Pkw/cO JVN1kgmVc4JvFEP1SD+YLIjn6XjMsP8IhLrvJbbxEl8jSiQX5I9V7M8B1s10+JoFL/fPYBNtfXuW 7Ve28AoNp/pVdy6vM7OsMu8mlzC4PGGoEg6TtiylLbBcwwKkzC9x6/iS2qy7trA/1v2yQFAGJQhj 39bdc31uokTU1kaNo38YEGoFgarTLkxtFbr3+hKlC1rnz1x4imaz68yBim8Iwui7A05RT4ZEEz64 Q5FFLpTu3OGwLMj6ZwXx2LqOZN8rR7/4tS58WhMp1M1l53MT0/sv06a8XYstxccaKpSRG59Ru7Aq SUrFmV2mv4D1Y7OlCT121FlN4CDGG8mWq7y1DJXbgVT1d7Rh+PxJzqtK+Z+MUeG1NsD9Rl8/hzfv yMJEmEjiyA5LkGazR4F76zkOX8QjDf/hfHXpNHkB49nkt04ZrOJXOvLIRuO8MaKnlIu0b4M6LNuU P4uuwPDO1JP5n3gmgR3eHN9mumLzKAUQbyYyxFnLMbm0Ba+2KLhwIvXKg11dp+4hZsdslEZl1gZ/ xcOzo0/okHUF7BnoJPflQIdSVGuTZK0HFlgEBKQL0xNK51HhKR28MmzcxjQqRHH1oM1YYqg6tACe fqSqn2gvsSBpO1WNAI6s3rSJ7ACBPML0KpwnTYWGxDSzz8UCGsr+ohBML2BSxt/BCx0n1is84g/C y04NKQbgxnsPBvFVB/NuLQN53oo+OLo4xJDbUGpnMSRpNwKAZyYCXT68OsO5loN+RxctQf+fqLnF RyiLUX8c9qMT5pqS7ycmWLX7T6oXvLmbqOdSBtYIOL1wai2dlunbicuzh+4MVvgHumiF5b97i3VC zO+aKSivXCXy897pDeIJtJzm608LINNLjn7mOWgsVccF5DkpQ8+Kjkv+tbt8Lr2GljCPspdKKhjj 7IvEzDItDF4U9KTZMAKS8xxqlnGSDJuUo5XDazUtP+UghkNwNLvgYPrmVdYug/oCk6/6i+kcsxQM YL0IJKea5f3pS0sk2jj75kiNQfpWLxIz0/OIX/n9eE1FqEnX32sh28CGe+Ru1NXpedvMAGEsPhwp P/YUjANf0QSt5A2j4DUs8EeifY2zGld4WNAZyDU7vmUIKU+IrJOkbZwlQTHgJrPw6hdFiTmsc2eX jIoep24r95fVmk6rklTLClfGYaYwb4URCEj+JTrghr8U4n/4iE/WktTSV8fGpO9nz1W1ipEN+Xsd 8dPAY/qMWDJgIoI/714eDxN/QHfdnAqOnqFg/SB3+6rmctMbHcVSNmPI4hNEFhSJ50aV7Xnshou/ 3UaJxepPfHc2fAYWW/aOSVqZaty5JKDNTkGgGrb9g2UJJfRa+mz6B3VrLH3jcZTSd4FTKD6eQcgX iUohvEhYiQhh5cgzman3XnjIKJ6XCzqAnlfMkxCxpKZNuus8H83Ggk+hPNjs+79Z29ZpvvLU7a9D GQTCfmKtYoHfzwpPXN4KH/5HWxRDDZXQZUmsYOIKbyZwz+H1mM7PGAv8PxqlwD3YTKJvmcReswIf wyxULZxaV3fP/OvPbSJ7nRPKpBJRu71O8lSRreVePEgSE+1fiOIbHRMZnxLapzHeKg20x2uXg+8e 5mQPeOOcMH/hVqEWRDekfwsImqA2geJcsHwOz7u135erAHvimEfGs80U5ZokN5NzovoJ+thgTXKP s3Rebyv7Jr27oeyYlfhR8CwUlyZLP5Gc0l68Q5faZNUVINYNrreAKsudSZ91hIGia5bEp7Qtg+ug Kz82FPadgJjHguLSgKE8hOJ/MrjfAWpQHe4ke2T4Czl8jPmck1b484wVQ5TS26Nmgyu/HijFCvFC nDkFpcOzTJvtTEzRIuKwjoO6Qabn1GoK0pBwIdYumihx064S6lJFJJfIyndGLaK3a+3v3+wm62Oc XjkY7xkpS8s4uC/br4G9CYJaBrw3UR5D1mjRQbUyx8JnRviov8fqOPHyq7aaz2mgVgdc00Et4CkN s2vTxbwvA0iOJpKqTONEEer+7A6OGchwYegC7k6zmPJx2v9F7JAIwL/GzXji/Sh5bojs0QVqEbF+ UnDZ66f0j5v6f0JbLZu5YhBlaeazx9S/tP2BT6z38RrP2I05wKWo3Z93L1ArRBiGfKZd0//nHybe IjBFGSt68nw+LxJkFa4YMue2i6kFJ5A71bvKyAsD/qTuInNSYZEDLS4oOHjs2SchuiGQN9OPHCiM vxnddLYUPfuPm2/1UnO3X8mX8bx6+EAEgn3gvrU5EcKkHpRfwejgGZZGQOVxtlC56w+FKU3ItaCY 1Dv0T/JOqmXDujXOoA61ZWx4k3eKBEkTXIn6XBQIbig2FHutwx3ywe/yBQ82NH7vzBkObPR6a/V9 U43/hvC7Uvr0MZbjyMfOB2I/gu4O810mHXYV335a0C2tk9y/o094adMBUUAYi5X+a2WMsXk5aFWp yQ+FBJ5DOaCQzqU/c718nig24Z2SEZrRiurXe2nITMwsnxax1ZGuuiodWz+3cs8/SBi5HbW/ynXR IUyGMuiMoiZwfu9/KIQnX2A+0ybTuxoY9graH637qPyoUIgcvzk1Us/ycnoVH2IxPsCUjIuCnz5R X/uwk+B5rCsRxUYu683smDnalVLfJjCgq74WhQNKzghDF7keWKxVyzGEOe46pWMOVKtm1SPSXK7t vxuFplojhAAxxc977xkkttcetIoRaL1sOAYgZVwpgEz9jkcokEqtEzf2z3npylR6/9KUrd8F06OC xK9mW28tZMosCog6KLepkNCGOSeVSqOsTf5JHSWMwJ24JFxTnPBYLKmyMgwA2LmcDbnnAlrr+l76 3botiCYNhNNLM3j3Kcqt7n4MBjVZ18P5EunV8T9exSH/qYf2ptyRhBgHB+he+OCSLi7eF0rTqIi7 z7VrmutuYGXvPHLy9O3+JtkFUhyRs+a6VxyqRTSwovgWJP7tYWQvL8o/BA5WIsIiaDhLuoPZuQ5p 3tVEFdeRyDK1iy1ef3UHQbgf274NLZ1D6IDjDzOZwNIpeyroV0uiVcQMkYd+fnN0L6/OaGleGr4C 0IieUo3eQV1Dbo48QoBMdB2xodx4VWOnuAKeBokbD72bNh5Sgl8W71U/fI4aZfzepcbS+fe3B1Y0 IVy+Xt6GleCO3vB7ZH5lpAwmU6Tu8wbCoI49MIOdZ4t+H1duN0d4SmyAtAEUxW/HgOZ5QG3+IuqO 9lcDb5k99eWwL5CTDrsAJ2WREmFL43UPrlP6NcdXT1CxYksCNe3miOs9OBHKoxfYRX5e4WRQKvDJ 60OkBTC2CF452v/js93JtbAIN1bfVmt7j0ouOadLHb3nlalTGadVgk04DCAdaviGJN62dZy0XqKW dG+I9R67qAxBSqwa4IhFZq4I1nKuIkeJ/UeB21YfOeqI87BTy/a7b83YKK99OneyQyDybMcx2s20 hWXbR1JU3o3F8z7pdwcNwcOyu5ZmRFzThY2++Ul9QLvCi3PSFzCFQWDL70hJWcu1PMpkQNcLEt0p WzWLu3CcqrZaYm360inL+edYZcZMc43BY9+w3EfbxExqiFeEpyQUv4VegskLYfTdqKplkiRGnVtf 8/MdZb5Sl8uBLwbPjlhDyj5GKnmgkLgERNhaQf0dukDTWjDdgFkCMY84aWhMlLwHc82cbJSQUTNi mUScboRZuaGX55t3NQq5Mr7NzjIZthhxF18exu/qvWxmRhx7oa119LuJ6QnKC4wOEL+o22sahAdH VxHTQeSkRjEr6JxaJNwiaNachMy4eV21zvbsXRdJq17Pv9xincCt9zA4R7A5uHKrhAmah5CGTB2D nYM765B4HaYdkZ9y/M1Xk8/YU0ulPpyBoOzTi09eSy7TONDpdARCCSZP5Qn/XGCimVWDxl/L9QYz oE5/ElFSxKKgw7yMimc34by6Zg6ElxildFgtgVVk1UawoDNys2ddJn+nYl3vv1g7osQCNm7gGFQr 7a0wlRKG5dqNdNLzowpfOswYmvK6pv5XREDBcRNBQsCKlaPoA5BLV2pssZKJFkO+LthaTvKd7rsX k0riUDq9x3XLWP+7+4y6W5DzRmKjQk+oWn0/XgFv6lUeAFtG/+7v81ZeolVd9CeU5FjeVDvrkHDQ I0lULpDUMKtY1qOt98WMoJyl8aW5U+Xk1IivoaX5jomd7+GxjLOAxGaMZJuyU4CemMwoQ7enOpLi 996JJl7DP+lHgJ1PN1eVKG9KbCg8ES4tKRPmlqbr1lc7/Bkdi1ynaQ73MRbxbS/qTpS+BtzP0H0c Ss/hX99L/jUiOWbwARJzPIMe2QyfRZMr1dHxRbIlTuqa8gM3SYiJdyf0UXYTAkGBABKnY07og8qt MOROrvWw5fHVM8wvfTQ/ECRJ9U07NQTCPt2hbnkk/EqRjPnIjcilh7IVB/Zfc1oSlqTCyPoMSWEd eLdpOhwc5spiKaAIva/7uBWFgNWP5+daKE3bzzy3Om7uy/ppZ9vaVZzVcrZBnoONXPDMgy+/Q49v F9Dhms18vCPirKtHYRNcOHTIVwWQwjan1wsaI3jLt+fppuE6uApmC+fO6SSfYMzhQHN4CouaaVGO xc3Pp4JoHvf42ut8E/k/VycP0ENDEKf/n+JFRv6sUVHhLnPkVMGo+OCABH8XHT/hwAkSt5eSYAN+ 4rgNIg4OaJv0EdxzsRKaJc7+XiT1apLB/jSJRuaXEyztX6g9fhAjo+dQ+wrNCWz+mkguziFDeeV9 JN/81BaRsHjt+WXaoE+7Yz19G9fapKne+ZazgI7w5JCXe1Lnthm3szslqMJplA9Jf3waMiwAzg37 Vc39KF5W1t9Gq8BeG8Iy/X5QnZLfBmgFIGFxF+SI6no9vSDLeIBh0mfXoMtIkbh64MUz2mlKEgNg IvG5WzDpF9vmJzyPKP1hfaWfcuiRhQXvKJPiQ2vn6wQU4ESMbL9PBZiEHNAyn9esfkQINQ7AN/5X b9L2MuXTFawZ/J2Ds8JP88Et2b5IxwjrNmGBhhToj8sMTlJxby1OldaUUDp2S6NsFW1VCTo6wZCX YrZaR6gLQ2/IOGn7Qt5dTUwCpr1IJXSq0PBwaEAw7IHPTwaRurJ+1nt4n1Ern39gTFP1SSdtHyHM RCmp1npklpyTeyTl6P32txyyVUl0BGR3TzPcjfa+8EEicvsFMqqn/c6DEtTtqKe7KjDM+RAMD3l+ ZArugr8Q19sfBLwcP3/Voly4FwPXLjT7tCU/MKftI0YcURTtXVAKjpvMChI4mYieKbvuCh4JujUH QtLzxqSiR7ExyXquDk8p4ukh6+kbtNFAE9aReeeBuSowvjXeUwLPiShqVXqR0PAk+m0EJz8hSxBq mAiM/cwUEkqDy5/RgJqLIMexBkkP55FfxjwKW2+7oTGGzMfja9EAAQLpkHsRxA1VTZ589Qf7zXGP If+MhYzoQ3dXJv8WSqrUfP8QVDgRCMSLn7NvH3W+M6T+VAx32Hrhtd6LGEWzaSiUwGrgFHJAAqR8 9nyGFaF7F6FpoN8FbXeTsD2AHuEhKhYFn3hzAZsOMVpYoP7Ir3fQVQFA63PfJF44DEl+h7YxFIeO 7kqO8GfFlpKTFg4o86Fq7hZaeOfPPzDTBBpn2JIQvaYSGw5X+0Sl8vSwKDMwRdZ1JREnt+6VX7SF M+1jeE2I8G8ZZe9ZnRf8/8ndhe9kIe/QOzmDpzZboDEFffnd0UZscIw6Hl8EbytS2++qpZ/H6pkr K0Oqp7UCx0oxWHDvzK0KQjWsfxspstfoXJNwSM9rtS9pc4zSN2DFWQzIA5siKKXvMJQ0B9aPhroD 6OJ+IfWNBfxS6j6UidIb6aiJAwvlCt+SU0UNk9YT6iu5UJPYAzUhQJzrVjjhCRo+Y3en7s+lw710 ZwvX9+dgo7x2lyBjm9bQL0KsfcG3BD/Ry10JXPYfA65/nbcJjK/qpZ9wCjCTMFrACo9YJT8OQm9f Qe8rBTvLgWaHeXve/QgSfjs9+UOfZROAsQj9aUMufYT6e2jDkdUe1sOHQ5mWnX1gvVbK62FUcM5J 3Ax6UJ/UlrRBwnxFphyRQaTxIj6c6Vzzbdxk9Vo9W2R5pUKBuG1xK6gLxA3Dn2d+WYxKx6EtD9rf iTRx7tg/kQDYGjSzCaDnhZZUW3ZWY8rwye08iKrDLLz/k2+0p+rZRDXnWa7Y2e8oRbBp5ODSPwCL v+TK0oHpulPImnWsaTObdiCYYSB1KBhzBXHrNslRCQfH/6263ltsGoZGIDnYy3WKx29pzqPQOT87 8TQU2+9JbbtXtf57N9YNcqpTb3ISI9BeIa3qLCjWYvaoykw49FBvBXJiIu6znnv0f9Jd+essEiqW hEQMvQeA7GVFDJwX9kW175NIn3F00SOoA8dGKbo/DYx26ItjbRNSczH4tGovWnI/ChWoiTa+sLaG NuhPJvvSDwhDrZfEpGOW71cTaLX/W5zlWJlVo8/TcBWg9wKjLcttMDmEEgB/8p69AE0oASSwLpvn 4vhR2vodstB3xBHjBIvyVgetqjdkOwCtlhz9xWGl5EZ5M/YzrOSkSAs8Tu+y/9zK8+gCQ8IS8gBl Pouq0+KO4a7rdoB2RbwGY5SiRYbqzzy/1dwxRAFDg/sD3/+//kH5iLamD1taWmQolDshQ69Gxsqd s/uM5ZaPN/JbrlwMk/bxz/JSXQaqgtO3uq9iTuIHmtibg4ITPjjzqnpVCc0mz0ODetwNBoHoBge1 rCoyP1q71HreUnJLEFC2wf9J2Ve13IXUIwJ9l+qpbqQ1IPxwX4zXZ1HKVO9jT7fqP9FlyqmiQBmJ XfseqTFh+VtVIgSll1BsxwTcbONz2mLVkuGpukZQJCSgJmu55RArx+7SbV4gde8W7e4zI0R77b4a r2yKPO+4+PMzeZMR1i2GLE53XAezvTi9bhYUzi5Jybf0e5ytusDo1EAXBa0sVBE4houpWGSARe+e KwOGaefkW6XW+H0oLj7cQT7cpkjiQ4bCX57NmOlOxAi4B/yQGVZKV6mjYDT/gQuLnOeHYCClSzEN 4o51WxkGanH9uBugGg1k127YpGNa1P+cZkt+w/blnuFaqz4TQ4sqN83aonuj8dn2vP3zajBc7yps NdGcoKLcu4hOz9Rqw5Z31xsVrG+SJy98AubVCt/pbXj1UQMrfZ/Hh5X7OnSHnYqwyQn4cYXXBdGS ee5T4xZ7JgZN7M1925thXRl7ocreSnwhpWbyBs2fqq+8OmAhh4qImjE2KZXQ2cuQGNPX9AV7cwtW JmSb5zlCXyxu4W92VgfdoOqF7R6FXWJiRw81p3E19E4PO4izbNDFFNFPBqn6LyXE1qhy9tJRw+Sq KuVVvxDGk+fxql/IAnvvoFN+uOVUFWBGv7PPyXJs8imeWc6pse6KpKYSwoPRYB6eqJZOCXj7t7Cd SKlJDyer3YkMJP72q6/0EYwP4UVA16s2PwDyNliAT+Sw4ImGP7oDqOJL0EZJ4kzUIj5UQ3AiujR7 8BsXrEjaUuBRvqNNxWaF/taeSUsLWvGEEAj/BLmvmCHM+kZWPhvHDaUT2OPFby1NLXh8pMj9iWoK NnSyNGd75QxrXEgXtoLiDpZFpm6964EvMWPOR+HeXmGbd1RpdDV36SkmGjxPLNSYr27i0bTnFrYm Q4N3w3cHU/foysWGG51KQEAcffUuHU7kiDJqWoH4OlwGKhxGIdo3N9phBtq2MRq4RhqE2WwDQtEg cB1owIR95IR0j20uuWTTt1CKTllLkP94phen0+ji6idfbAB/h9zD6APSusniAWXPFoClNMZRoSZY kmNYueXRIkunCDLVA3d3+WG0SlYiN1iaN9WrVapkK8VvACM12RefHEStiSmBVx5DY2N7OhJFJysz FZEF4WNfvwJV9aMySHZcMWoGB5YVxQpItZuZxxt09HiP0ODP7nHmDNYubZTh/LueKNcjmQ/5H1dg kET/0rehQpMUxmccRhoyD2jr842hi9eaimHxzoeIJ/2g1yZmMrXjb40Zdfl2wSxTII4o/BL3yRnC nAOMC663XNGsL0p1EXNeYr5h7tWuYzaog/62l+jhx4ADRBfEqP9C2yKUk9+fdu21G5vVCCk3NrX5 SgKauacYr5+Lvw6TiM1a5mMGzpASk4MCWXjzgkiGyq7S4dcK/2AGCmH26gP6oPwRaWaVtOEdjYzI frr7+1N1VPf1/pcEgKx/z+pePLEv3JC6PP6vedrcF1Ge6wosm4ivJH7IulycERZbJNxlqBJM93/w M1KUNJNzQKy4zm8mclAKjVAYl+WoO6i6qKrYGXZYmW4n8Mhp4AqLH2G4j/IuTwXzMHbpsEtLuTkW xrKHyXAvBF6CYmAllWLYs9SQ/c5lY3wuG9hGsWc8bWV6KUZpJPeGGldrESkcXYC9eJ3zCkEKtivq RtVvDeFonWzGzP94Yu2BebUolycImFfh06rf+W1Kw4hIReKKEG6O5zIv3EvAV595EunLt0UsqQM5 HPAWTBIYX00qlEnaTPC9nN9ZD1NOwi4MZrXFZDf/gBlWoYckZLjf4G7gd05zI/RuTi0n9QVY7o1F ZrkI2e7mR0+1Mm6FU3MO8vMbonOdGLNTSvk+hCd2kR+it6ai4KxkYFiivK+zKgpsFY+8RPhmZVm0 qtIikBun6jUN1NLCguhFiWrMgwR+ro2YqcHRRzFO6on9mFyzxhBmIPx4sntjCqhZISBZKJxUjf+W Z0xNZRYmauUfFrcPBPaKG+xNN8OeUTUvlmRgVx58APE6ZBYUG9yCyX/tKQvlpxFdVzwzgVKc0UEa 6hwDobXzctCy3Get2+diux3p7MphCPKG4/vwna1T3JwP9mymxD3nUyGNCokMX3uEXpmdgxzVmFax gbExp2v/sJVgMJSKDOXqa9PYjmwhbgTN0JosDvMAVWeWz/yeAPIE02n3jSyRqBpgI6/lIBsWYraX fbu/ZeOEIJ+yjFjrVgowEDtRlzyvBJz2cS6fa6uExAaqcJxHrnwQSEb/vIjlJIjQpgPcEUXj16Bu QxjRuQIrbtcJ5TeeLBo4RcVFgIlCoqEoAhdaJ90/qBDk8qkcwA6fAtr0zLuKZMoPKkO/lQDLIDvi tCaB4zgSqNnaPCTHAB5+o8PXNrn24cdgBhm/PhdMf+vMYJgnf2ZF/FNn7p52Kz599wyo0HT0FQPc 0pMlh2dCkoFFCZY3yfw6dYuTqw5xWkw69nPF0ZluoWxgdKZ1cIQGH3g4Ij20f7PNxu6Auv43L9+L 87cboQOnO7bIJyb0/E1j5q38OnYkmKPdQU+4XSLDSnJl3l0jDMYTPF9aEjKSmaiFgEbKn+ib1+al dylThI2oR4EfO73wWfRY4IHTRwtJHWhQV1txiPugjmss2RluyD2A2+thGCBmI/cci3xl3eO8AUAG oVa/pT376xAvMNbb+Lvq+NKmza0KM7G1Xpno6BzoFcvI5DvJ1F0Xc09bvwCwvpc1bZQfH/oL38S0 WE0o6pQsf8JZjlNqukJmixCEiH792geUKAcbEkgFyoVQaOujjMIhWXYfqSIMRvKsAIatoQwGuouD WxUFb/GFzqqGhyCgG5xIBySCP6qOpMensOwpYrh4zn1W8dd9cRiEBFnlUeovu40W4sc60T7O3Rjf cFTFtnECN1YWeou/KbF4rPDcE1UfrIPpoTy/Hk43wAMFVf8yo7iJfYflZAAsWbjRwYAdZ0JFMLY5 naSYD2c2USf6eyATasZqVnK1QI7nCQs10LePAs2IBXT9CACt/uVrNYQBrQLmAywzagQPlbzuOjF8 kTUY8DesRBeSVF4RxtRgmhXLadLEamQtxdGCbvl/2gkxuYmvkwtCvs6zTqaYB6jrbtmv8gSDN1op 1E3gqAhU7c2q5t+0o9uyLLTePucBlFPLPJ+RgAqJloqsWQD+OEAwU3WchfaB7P5yP6Hp3OCeeOtg AoMHTNUnV/AerMO4v35lORauE7Na/O3a2tQWmsRdYvndi4+8bxioOzYsOS1k/kjARohbJCVMuG9I MeWXBof+kBrXVByyw6cqYksxEUO1h/dRmM/04owUpD6sshM8miqLKe/yhaVZ6xYI5L7k6F8e27nN rf0LmbddtLItxUrxXpEwmPSv8Th//KotQ5ZxaDkpLRZBV2413G+QPgglKGUGC/Fwk0k26Q8az2M8 9QC1Rp73Zu2dho+pfrhm2nc01g0IP4G/CIA8E6LOXeAGJJAfVB4z+vGrNPUHSMF6pWnhmgLmZUdO vTfwMg1nMBOJWZi0fKRnamXlmRrIdGs5xPlijEYf+ENSGBqX+SO00uawC+vIMdQOvKfOo2bgLZIH dqPGap/nzdi86erkouYi0+a3lPKtAHvkggaSE1JiMWdllW8w3+z7ZnVhsN4gb+h81e9rfot6uSic sqgwoCr6mryBN+DnR4+7jq4cJe1ED4a6TSbUNU5BLohaVFPF8YW9Dps2LhvRQa61ntv2EyelVytk OLcgZBrFoMm0WxsVgiDewd14y39hyeFfrkxijw/fTKneojmFpKP88xcvfsyQLCx6cTZITWgzpZBE RquK2NOCR4iZo16nYWX8NdRxoI2DlbtQ3nLEOmkORv9L66wGXXa7I1vQTo0B+6yKfgScnoL5XJWm 091AFMk89ErODFXYgmY/ErpdHnD3Lt119KlaFS/gl78PjuV2i4a1KQKORzOp+rQqTzY0CC5hBJFx lbfLVJir6ma/OBY7BErPWnIek9jCzjODw7aqIRtvQzVOjeZo+wNldxfXqlqVi+bErbTuBHQuxqmI TUBqZOUrtgP9xma5dd5NsbWawv7aO+rT5TNmaoE6123agf9whkzoTgzMcLFqqmg7yScmIaa3kS6S jZvmeryPIofZXTR5VXtJanVdo3O2RgZ+LdsubupebBD3viif9Hm0I+ID/ssf4qi76th2fgfIEs+F Y1Kersb0GCuPYFTITWujcxSgpqtWwyNJBKFku+NJHa/jYZuD+VX+SOKDaEfdkBf2rs9lk4ru9AdT EXvNXNLRvP7/C9Sx4WUhlXRZB/2sD+49OOGIO2ZkNXnbHPf/Vs2JMGKkWD8Gogya6NXWPag1LrcR hx1PIekjpnG1KVipBeDSG6uQ3oeGlwjI4/bt+mT6fye3hRR5L84FeZ9XMim4gB4z/IAKQwC4qzW7 6amI/z4cdVErE2p2CrvFFzCoYCOLKcrjZ8tDNz+72PxvtW/1tk1e17cbazDJw5vXk3iUKXuyS0qd clLFllnu0Mfn+WWi6oZiqjagAtVCVPu1R6yzQtRHetLIsNeGX1ywtv0rBvPEq9GeVRFBo/+DSwij fqAlhD5Sild6cI3NE2b7b1IoOs8109e6o2+aZjacqBnb9eZ7sLFa0sOTiK+thPKKlhNNGACe+/D2 lMsGPArNifEnJyEpxqFQ0q9antSmiL3BL146mcRra2IaByhMcbugR9tujlSFh4g7JGAr7iLvmcWJ dLAiiIU8H/UXf7NOU7j/VO+0nDzFqOIWH6/fkfW79NUeSNVZMr6SAxHAtW964L0S8b1bUB3rOY23 7M4V57HT0zr/VOTNLGacq/VHZ4k8X3NdPhFHVLZbdzL7Cvgl9WkM9uFvHUSMoH7cM5r0hOi0Cv4+ NSZmLw/Whux4W64Z2iRPFOXdKxIv1wBNLiDoaEIxl2634NWeTIe4o6+wdZ7Tbmt7LuOALP2ZBAkL a5nqy0CqpFgfqtf485BvZtTXuB7luPbXv0ugkQMCEYsL/JzIus2xJ/EMiFvuO9+nE0+SCwS/86xj g+Xok5+Sh8D2fFJIMLA4s7FpM6p8zNVigMt66zLF/wQ2p0uIkrwGp/D951SOQn+JZyCoE05O4Ctw xs96uQu6mwHMiV+VuRobSLaY6MqMLf2BqAtfBCvimhlDGZRUsypmEF+uuIN8E2DNKJkzJj/uTIF1 cLE2uHfOknav6dOAJ5QzIBTE48kpg/+FlntucqKPS5FzI7cXDVU6LQCqdOo22efrnclbChWcmkH/ HvgjAFM8O04dai5oPzcWabazlnniCcfeCkaLtUlIwIaPYPRK05l8oBnMGXwgP7es4kHbObu59FxU EKo5fZ8KxVG5zPPxsRtS+9cyZ2qeqV6JzUgpgOnljgNio9jo6yEJG9HCanWuEgdae1VfUYCkkgqa AlQLwDBbGtuuQd6L3CQARVkEacRHcrkSlG1G1UUrJ27bjRBk1cPbuGGOvZaC4kVW5vx8TXvw+eqM d6xcGfrWAdWJ4/8KVKpBAV2RNlBgXfCdGgBagn0DmFbTdCSogo9NUuD0FGQQxtXntBQib/za9Xk/ IUIey2g3N3zwj7OotNKoP6a8RCTdWZhotLBsdT/xq2V5kCZKpwhWr2evWDb5K2CQIZtRMLZfd1ZD 7dfomIMRnQ9MKgVe6USco8LGokoHomJjR7C78nsDfTu5OAS6lWFBKceSxPyUV4M70mZAaGolNFK5 +HtmwK8lGcADBi2ySYDqrU06ggFwMG6hRMMKXSiUKsivKD/kvdlzMtbleVGcr5CqBsV9HSRpoL9N QDa81KehVnpNf/9XbdneedkIOUWoGhKDPhZ4fC1aplZuadKSLx/pPiA9n9CbZHa0xDonhpEi2bpD NjEMLbZeJqjvd2+rk9w5FoY6FWC9t9ArxwdQBtSrDcQPe83UsmgTdvSx0GvD/1lcnq7UiVMfhph8 sXloUgcYVwKvMJcxO9ghgd4Cp8IaZ1uWwq6doMKq1wK0HN4i3IAyiP3KYJZ0RwSVYc+LZ045HWk7 5bhtIzc4OyzIEb94eR9nAwarC3IhhaidH6NfHrWdrkqqahdmNHoTCayr6U9PmpRTpYwFQmtbVhz+ rwMM8fdsGTUtOZg6gEqALlT0+vSdYZDs/02Yrdw7s+zKUGV4KpSR1HEP7TOWgYuqFxZlrlNEepOg bps9kgWTiFwoPBfcwSMU4OtovWHSvC3BmD0BoiNNYwy9uTCrfEdbecSQ0W9BCRPzqgd1gHjVw5vL 4i2AAiDBW2IXEvtSUufpC3n99SSByMdLaR4LKSXrUjVrHcyo4ITB3XfPONT6SIZy94Ls3jMkKR74 5HGIRw/piNNobUAsGMzMnDBcu80k6PUdP/ns0vS+/c7up7rtgZQmiYfk51B9WfUzhXwbnlcNvCWB OF9HaTRP6paV/aXWj/19aocSO0jxoC60N1Sg/qLNee2G+20CCr5tXah+nt643bAL/O2pNi6WBLuF 0Vb2eSe4NYOK082JXLgEcareMcfeJc43gIUhsjY+VF1HEel8w58op6lmxW5ViwvzdBnKpHhrmtqT 6H7Vdd89NAKxq/mppZb2tfISas4bMsc0feGO9c6B8D3vXOKq9Tt81ztOaYauYIoBsjE4cFGounpX WESIyUgQIoUX8zB544Gcvh7SzNmuQLfop4oklN/vkxlnELfP/+R+9zArO5o3CFwrPoWRz+QRqw0H OsK6xZgQErHjCR/YN0fjrYV7aaOxTRUbKMyrbN03axDUG6xxDvvEXR/m5Oz1Dk4CpPvFiw0vzko4 deCERWw1WO15tPXGwPSrJVJfMSihjqB0QEjjJzsbNCaHtBs4i/UGoFVLn3rlaAIrwLp51YiQc4Ip ds6QR6PMB3ZjwKEqx/wp5CwX9qZyPLpLjg1zUWXYoREDU3oVJj0pqBrz/i6VUJLfTWonb+Ygdgv7 yEwvWiAE4XkypGcZ6DdWvlGmAEjL1A1xiyfr+SqDv+41SSaIGdc1j85B/9BpCi0kZ2sNzuZQK8mm DM6L3zpaBe6qd3cQQI0N2y1jiUuRqAhmnxoDw6Vb3/pu5B/9URoKJz+EsBe87e+ZuDgIETPdFB2M FYVuD2JB4LX2GmRG4G5gbg7JOz68HqwrKg20OxeZV45Md0a1somieRh5eSnWEVQtBTvYX1B1DLoF OvrMVFNqBcOy4RW8egXA2y10/Q6KmrTx8UdlBvlr3GyAQeW4U5pLEOeAaMpPwTXFQeuN7RdGXloM StSaMRmqLyX3vExKRCk3VteTNSntcwaoIX6qe27n3TU2OtDmTVmmuZvF9TIb1uN754TBDUVBT2sB sOw26ZyFri6g1HMfeXUO6irm1aY4zxjENFFXZXdpFIVHbET7OIQCO20VB6Us0Ds+HOk65JYT0Ty6 9qh6OJgLMNtqT5G2qxr261uKIXHEcMBGXJm5laVGLMBvn8Q/C4cyCxsBU63Qyok3de8c3ALI+JEB z+CLu5cskBLHihFniVkP89Bkpo88rHfxhYz2VkjsjbIuaWaEh27BE6auWC3JnvE6IvwmxvZUY+0G cg/qyNx7fKNxgAw5HYYaC8P1GrT8Xv+ijSzOQIcVE9FLvjf6ZXWUbggh+1cnRjGK64m9Era8xzu7 2R7uQLef2DWGVAEd9UpZYIZOMGyy4YFfCIKleE/44o50PYBztwOmXiYeb855VahbUx/kcAc89wew bu/aoDgT2KtheCkeDfwjzP6YWDAzgk3wTgO6YNUyYWUp/9MrV3uj06c9iA7f1w3QflVdameoeK4A FOUKiLswc1POAddZuMOXptpjy/+x9NgfhAN6EoRnMPlxQDhiyWzOUuqDmBXRpwKfiVIF+2OwJyXW xA5RITynKcE0E+5g0nWNn+wlzOR40eRysKBvutc02fuskvlZSQp8hwpmpq/WRupjpt51kEArcav/ iLJ3MXlp65B02ICeGymGddAXACc22S3rguQpjOaGx2IgZUTYMdQUNqJ0y4JGieu7C7q3psgUnLb7 L3C1QHOicWVy1B5WHi2kmPmI1ZG40+D6bR2slXxIopXzIwG3jDfIwjrTrC7L4BqOtgNZUIgS0N2t 19hlpsYvB5gQcaowphAnnmsB+w7GshcnH1gLtYH6aGgdhrBDBKnYG+J36AP9FuSuI28oks0OwKVy yAihPucSAd58uFHEtU78qvpuPTQiuPYTIb6ecW8nAXIafocwotPXikjzI3tvMO6sGxwdvdSSTwua uuupye4BjFgKY602iNMZN2FReTJNM51GKL3Urt22ymNXv0Bu2MoVUGrRU8kamSxW4J0TIv0qNI6h acM63RbYOXUzAiJ4OwHQKKqyoyATFq11Ba3Y3LSRFlm8KXKd1UXIbyMglbAnXogOOfwqcLnimTm/ Y5vEkIwFdhh8GYPdp29kdKN3dmMCWUUMifDakaGiKLBM5wx7ItRXwKFlVftGHExHkZfyXkSePvDO b8agDZTzeKEogLs7WHDtAlS8YABSNP8D7XybIM6lXBpKLaZnPEGacr2NqQs5l7m8l+Fd4iCUSHcV gsqibNQoecGqw7pfOzCJGSNV8l7ly42qAabSh/A8y5ZzUP1vsgzNq5P9e8Lm64g9Xb5tFO83Q/aT aibNdZ0rGENC9heeyG3E08lxphw53I3CGMlKvUMHHFGnC44VCGKwQyWLbkF+FiueRaTm8fxl5B3f kKV/L35hEILkgHgeUlSjc0DEeUPdlXKEvbvoWhpdddWEH9E3+/54KtSNyFRDjj6S1ZSNXdVVBD2O B9XzL1bhKLQ1rzw/X5DHtq5zOl7TTIqPxYenNXlrEPHiPONCWz4bRRuS19OgkNp2YNTqGSZxrrd6 QIx9Y6orRu2tCdmywiUA5ceKo8uJHgpyi91WDnBKAONhz+WVFeAzH0XItN/U90Tq3DfSU8yrsewX 1dgkeBanuyOUIRzhiOvAt2l2dowGNb3WSAVnvGvdDdAKV5gsg4JRPMRZ66rSmDGvAOVGri1az+F0 wxnYWB58E6ef4JJotUwFDej4UK1gtX6EzeIbqHLXgMbSjWY+bNQX18ETEuwktayYPQOVyAIr+5C3 loxcdIRJFJiOPQ+269MBcfTetJ1bBkW0HxDQVbjxzJPLEkrUPH7Usah0CXcxtvpHVGvlgW2boyvU 6qBqgU363DgY0Y+2Qcl+plCa5BEICfFTRiCVMhTzksRDBcT0YFnVGb22QVkYwy8qWg+Zj/agC5WK KiIy1Km0i79S8hekxOtfswAUAO4nUBe7t90KJsuDAgZC0m8cjgSoJPb0PgjMCkUn1srW4D/TxOGG bDVCiZL1JyMFcebnsmzdBseOj46FJZ4iuRsTFhhPsEAsn3FP8p4p1ngWfudEIHKU5UHpfNKQDh0h DAzsNHNRx3xtWosz5p37VTENWGhWbH3gsZ61GfMZVzXJhICDO+TbhxQHMgGHx69w9lBCYjTrhgFt 1zcPJFSrGRLM4vhEj7Cv5LUPh5CbUunE6+NhYmM3XlpaexP6j54zVOG4Cj9vlWm19sB9WsJpIb2R zDBgXdk8hsp4D5glkSyHhS7+12l1sLTmnnC5rBzq/wjaXpdCI/L6+yIJglht7XRowu5cApRY1pf7 TnBZfW7DYzy99+U0XZsYPoLvHA86aTzXIREB3hf8g/DcPIimo90owKc6emBcmNrpTDMY7OU5jdgE +EmNP3Vt9sEMSfrVEh+zjicr8dxXO30IBrbusXKMw9ApkpEsIcNnepfELL9dtMZ2uLD3DmOGIjY3 UU48OE+dXX1BM8OcwamcrxC6Kpn5jhRXjupIkO3oet6AdB7L9stI2FfFOtfkvGFkUq4NgNuhbFMY XkDgmh8NsL1oe+Ej3+GZYA2+lQ/vDgkjoJPL9VIIRJxGSSQuvZYhyGklciozSv0zp4ZbF6Aw+cKg +p7y0tsuzDj2cN+vyDT+tX8IzRIK5cGJYNR8BIltncExUiwDRwVRBtn8oRXepo/3Ke67DbqNUSUL cg7aN+8/ZBnQtl6EFfsVA8+8Vh98JJaGF0o+KVrCAVM5Gcdz14TMqQlwoX3FBjgbYnDOKdhNclXO bbzBQgf9UrdXSpzzQQeESy114FhdmvcNI4v4YqdbZBT1t5Nb3/Q5YPgnoIIyLE6/pHoVFBsEFaeK 6ONIUy8Ln0/veu0cwdvvx+F1H67F0LsapqMt7BaNi/+QKwCDCKDSDzJQAlWnjUOADGKovfku+XqD fZzFhxalW4/x6aDcs9t6hp+HkQ7EuTVRkNujqKimF5KQlDyx7zaikUishfNNg4PIgGbT9c1c8WfT npT0EeiJ2rUQeR2QgEJIBSSWSeTAkUSmdU2vVzPKAiUfHlnhH0WYWdb3wnatg9PzblSoTrAmT5RE kiHJZOSqZOViCCKyhiUX52MKcBXtMx1jK14jjV1jA4+pvHPs62zlATId1QSUGMQO4Rh7YtuHSD8s Q4SRoyMO807Q9MEfQhPFxonLmjPM2Gmqsvzw9ORoQKdIgWrgp+cg9pSq8A7RXcuuDflGz3s3pqD1 5ZLyJGpto6AJKGpsVy+vu0ccxW/E+if+fYf2pvPZRnlmwn3VJlvYKZKJJusdPXRzxXwRo5M9xNbi aE1UYvQ0mzLO+EMkF1geQCOKCnpI0/4I+9Z7bqLXoCTv0u1C7SgwohkXQzDz0sqxa6GGi4wNAWM1 YqxqONKU2qk9yS5Rie3JGl27zhbhwAQyuRxr6MLH+Pwms1tQwfYQUIOsocxX5SE/ZkQZsJlMgbxV FvVV3DTPlOw9gd9D+KRKchafBRz+eF2l8hIPvecEvAwz/IBcU+Cm/wyEvAF3hEhM7BdEUWpbauzg IbVAU6nxG2tkLZ8amXhY8xfYsSxgD1XMS7gPrEgminkhQlKWh00N3THKXw/C1XMtAuaolYfLUyVH H/KspWHlWQvFzu70uEe4vvYFTVmsu3EhdJdbmrcmq4wPMNhsA+JR0SffAu17nHWAQrI6BJI/x/iw ptx4jWEEq9hOApWqgYawarxIl/n1hpHPghKZUVfsvnWmJWqh3K0KZ9ka6VUGsW2y1B2a8p5iTzm1 bSHU1dcPD32KdAHgrm3KGV8JQKH6EXP9b9GqturUYjmrsujn07wAbfb10X/gdP3a/MbgoOY6aBXp hpLvkv1JeYbSfWaMQhqjdo1E11sCCj16caAAcjbde5TTgOyLC7d+BlIxD0d6mVssALIF7iF3tPZm GMrabY6gA5qRgSOP+z/8K+5MnnhV+6T2uYYn2fXoVDMhe/PPT5eGHZqd7Y04hia+hOozixWnhEw0 SLx0Y1uPiDPhMKNb+VM4xMxsgB7B5gQ4f4epYdegQt3d5oB7qAHbLPjxuY0ghkLmMWHAASDntuGZ /ljK762wPvYaf1y396kHtN5P02MAO6kZRdRAh83gpKToeRmLkRb1P/ShOilquC+tsAE7ciXxipfZ cC+z4P+sxWdRyg319HO3A2pO2CDuwDWRb5+7QFGjxIsCO9H7uygKwMua3kKFfcgsDRcuzngUYAHA AiEmHQXkNhH49rHj/I7rIe7SoX3v2o1A4zBPTE1QQXDcw9zXiGH72Sscj+w9pjMqbP+W14AHnRiT 8ucyD3NcQY5lC6E5Aw4Sa3iXANeDRrqKdGLu1vJCVPCP0bPVqrYQLjuddAIouLRvqvFWu0QRhtfF EA1Uof9+CrxJ7QYSEB1d02XrD/UkV9xT1GQSWwrGh/SWzT5kgDl/EF6NxuPuGMipD5Q8+RO8HyBZ 7Po+DDUugCjZU/wCzgESSPR0Dn3cCIOHU6lm9DVAURwrl5Y3m8jb0RK7cA6Oo/6/Wt9Z0yrigQ31 8q/cNpjcsJPfJs2MSxi0xHIDS5qHtTHlQ7zfz6qGt766HntMpXheXHHrj5nzKZXN8lQqoDEkn30O q7k3zleYlxEctHi7uE2YkIRu48IvvrWAbFGYYvpx+ipgCL9mJDO40jgmGPwChKbhZhK+S8WqHp4h x+CHvAFiHS9A4ujRqMA5tVojN5RQUufcKEa5Z8s01MuqdQunR9ho+AzmHdH3GVHGwBBw+FetQ45D I4CcIvnsYznf1bw9bOJAHWYze9hUqu2ZJ2hdDd+THiz0MImJN4hySFxkXmzrm6H9t7GStttA3SGg 4L1MEX2OicOWUQn68/Ut39kpBVG+7FeZxYPKb42ZKVwXR8UU4TZfJxzJYo86nS4Efuh9UdoWKeC6 hj+YiDo1WkFgCPutSxCu8jJQn8JY5iYK63bElF7pRb2VeGPJ+0MzWHleMkx+2l0r+6L2gD+QpyeE 3ESOW/gCV3+YAiIMfLRagLA+cmnkXCitV9y9VUOVo/jvBKCwn+XvpCbMNcNa93IxeyKZU+uG20g7 Y6quVcZqtD76APu4r72fk6VvVHvim92W7fUbp3TIRo546w3/P8LPcMFWlf34PpZRb3v58YszkgpY UeLesyBFLbdsV1sn6vqslermroNiVJhsvIqHbnA8sUV98BU/A+4+kuCijKk4b1g80KnpQ/s6o1q9 ojDBewGlkkhDdvecpevlUHgBW4sCiwWDFB1NhCAmyOdHm7fP2iOBPMduCMdiHb8yvDEmKocEBJKK p+Jel3hJIxAbSsEL/c3ljv2cwWrz64Sa26bxfjxzqYN86z2zSpSde/g1qOA5OI6DJ5lIPZ1oaw8j AmWrGugddL/FPmmoFRzrdkKkVIwxlRVQPe8mhtEndsMFUMTALbRtxil0W+mDhlfGdg1eNE0on7Z1 9OlF1E6RfFpawUviOke4GK2ZAyQX29XEFewdlV6SWi/teo+YPECZhdylxXaxGWtF7Fv7IsR/tjFm wRaU08mUiZirUb9Lkuk0OoTaY6sljF1KbRzxPZMiOPJoNqQygQilli8MLx9OpeHoee/jyvPHcxEX V6EdOwl/HFMR0zUTSIMkQBLceR+SEcQT/x4HDwql7jM62w4cfhBH4HWNM18jTRclg85POcGs683u MWVsLkAGXg7o4fxkxqnnG+z0YAVZNjMmzMhRheqtsIK6HZ0NXexfkk0gC1h3Ku/tu4Tfbmp50f3S zT75PFYTWPXsIwyipzg2PRBh0GP5JbUFJu387KRSqByJOJ6PGxK7zIoVUjb3gmrhR0XcnBJjbgn8 6OxKa8cSQ4zIFczxWDoUTsnhrY0Tr42N4lUUB9KEYz6yYlkeusOBLmi9Cpy9Yf9ZKsLX7T4Kan5O zUUesd2brvuQxk8IQZwhE/fQ77Ts3fSILQvxN+JrNWkFobb6DYj6XC7Xu9xmb8hUg36jzihBCTxa cbNahf0WBeVAbrqm1WNgZIXMAFd+m37Cc7mCXA+dA+D2bcyYRWP2pjHamNTe+XhWI3Lq8uJTUlrr McqTd6vZSWbXU6sl2VpQIyMYl3iByDHs9PwzG9MRUnEwRMRgTSN85OdwqouR2IsAAcJ42+B/I20R kapb5ptLWqQ/I7PounxfUdB1nPs5q8pwIZsodEshqPPEB3zoCSqMPiUsQlopNdCMX9T2Ndt82Ii0 dEzfu3j9ejZm1NjELlZzTrLz//mZqTDzIBBCSI6D2ZbAS+EFqlnBLB3PoU/GZKeDj5wJ1Fy7OkYQ FaBIgbjHBBLd8QsgS5Z5YxbIWzcKzTFNLMkXFg1ylr9g4REXXhTvB/1rOopBkynBZ6dxZgailPrN mUS40NunDMX2+T5dQin3ApCnWet/atUkuk26pS6bEZ7liqB9WqfsWGItJ2O2AmFL0cc5f/JDWTDT IxJ/QNt3CMrSrDBbmY4amx/4WPZ2RkSKV0danv4CdMIKklIhK1qs13GOYeiTheS3K2h/FvAYKBYf achB6z1pX1H0fh5IN+WXhnjSFcW5oUTtKlon3T5kXkIXouLdHJbvtS3PwZEvHZPDzPaWrGMvFHww Y7X8yN6pbIgNzIUvQui0tPwToxG0zYk1QW+K5/yV3dw+DU8fLf8V1jFVINTmmYdrPPkvWsAJB1Dw clfWpkCxgbT0LUOOPxK4pR13SP6yeZyeRZwgujbqPbnUw9tzL3YnowHHy0kVAs5Txzfc8T/UtWKV uB1HM2/yCUejZD8FFNUYLbToHT6wa2yZEXs7P9xvkKyGRsPUjwm8V+0kzek3GqbLQpNwWiGjTMkJ 6fbRARvTDj11slUkQPauFvB++V26MX6FE1m84BhZPxQ/+bmiu3BhUUK/yBwy0aD6y/woauB2kU6Q G9JrnCYwLbF5WSyk1Qg9++Pj+jG/HMUDKHdGU0vUXHJHxv1Eg+3fkMC90qfVLKaWk9WrG4aENEbQ vdcz7xWQEluZCb+c3hjAlJwdJs5908BXAPHCS1pAU7AYj2M04CizVoB/EKe+3C2s5Jtc8AK0I8FI TSYdcFUAiwCgvr7msiMF9pMPyiRgdfysrqpTyS7Stv1vuvk+jihAM9mb37y2069MhO3Wwnc84mu4 sZwxq6L8h3XFvvy7y49jWV330vG8ut8k19UR5UHWBfdRKeiXg3EmjKxhyVAXJF+EZn4kRgrcz0nu /L9U3IYD1pHCuIWBKuOgl+G8jabV0Qqz4AHtSwV2DbDMHcHFq/krcHO1n3OWDvsccgZRC5EdlMuj 8PPJZyoSSE4kzIKg5cMKyNGwjQPkOoFhcjEwQL5WMCW+bdcDXfvloUZ7jeB1zxu17ox/C9FULOPY cOoopxhrzuUxP4tsNv/kuCcFV1ZCBic3IR0jxccDbiLpRNoxjxYk6CBcLmHIFf9Vj8D0cFjDoRc+ SDf2rXFrBErrmUQbZQcyl3Rr8vdFBYlQRx4jxZ9a01k5KAMkR55mMqG+zjKpqorILQycgGzBBR9x sQmP5BSmTJnPDSTdvsb6vyJqylDox6bjKh5fvxKFq9Ct5IIynThVxxd3CaD7qCzyotjy8SryrmSK xhkoIA4iT4HGfwk220hgJL7ywaplOnNhFDQoHJIfaeBPy/wfOsi0NjFkWxYP9T0SH7/IH4hqqlXd DfNP1STE/rYYDPG7/DTHxZy5DbNTSwTMscm/W69kl2dHRjAsiRhfMmBJ8xO6u83mgFZfhkDdyMoU ZRjrmI6x0aj21N5A7I5/V1dY+gql9NOWLN1e/Jw4IWa4ZvcezndFeHWC4o9Gaqm5FZGyvHArmvJB 8hRam11i+hRXrWt++vhaiP717tK/qydmFdXw2wHaoGXew6/86ed537iUalBVRFycIck6gi5KEqR4 DMecan09XX+XBqLeOJVBhZO56vh5lJtCrzx7j/3yz832kvZFacZDEgE1clUcbbTrSvaDaFbATRWR vLhHECjXMT8dfgkKRPPBfAWex2ksMDJ4/gGSl8KlwdYMmi++w22O7KlCc1wDCRCx5CaA9N6O6V+l 35nO19vE1RvCWzV719rYJtXwwTlueZtBfdHFFVp4WICcoiUbdK37U3QA4sQXu2qzeWcwO72tFeU3 BK6SPuzeIp89ZoykGwegW0oXJPR+EZjg+CDwJizILLzvQ1i3BA1Za9KrOP+VX3NtoFAtRwEgpMUZ JTNx/ldxU79+xDuRnp27aLj8v4et+RIRbDpEL2mv/5/K6R9Rw/DLRWvRHQZeCsL8S4RR66tYEKEr /BQLysCT/av1pMyWGi0ku12akimgVXKOb9daoDIOe3koxML5s8EzRPB6664Azo8AkAWLNw8eXwX4 CLrxv4jfh+OCxNmKJqIT14gTcH7RBDnX4S5nPrVTKva7YMKggrhpSQ/P1HlrON1qoKzLfePIf6yc juEZcBScqTahS5+b6BEDzawv4/4Yzj2DCrf+bF33Ft9v14jGapw2x8rwBX78NdeMQCI2CyZ4B/A7 y5QTeE8Uyqt652/oMgvt4VZVbu7xxbzJ+2omMZ7w+r+5u5KA2tQQbTJWZ/b3xdqs8jsQmNTDemIy hhr6uycdN8eKX12f2eKXokWyGCXI7iZZ3LErpV1QcX2OAd30xid6b9icOGgrNB0iZwrZTsIGHjHN nCU/2J5byJ12+QBm8swOPjD5xO0CGlnjFTeUpBTmm1jnHVS7raI0CVtmOih/iNedxP3RvxnrJyWf PnkK14nedbMcXx6+I5cCl7uejGnEwHkY+94vn7o6XMK1hO6V+Le+nPYU+ybLLbvQDmwsj8dV5gku 7QiSayxP8hPjDcHD8wFQezoFGJkz+JqM2BGv8WT+fQPBtPZydHJ6Pkn2jttyYzeV7xAOHtbKmiD0 611MV/gIq0GY1ChLqGWFwv9/KPazRGPAlcYtJjoHPe+vXKs26U9DOG1xsdf9eGqNZX0i1UbN0lAN X9jZxU1KJGTf2T6VRlC2uI5N2/n03wdthWlvdhgc3+RRoSFBatgTAK6UAnmo+QmYCUlDtXE2jfDc B8g9K8BFtT0AH4GHLhs5jluSo8cygHU22WWGG3gSxdE8Lx0e43P3vj8OUkDV/btfDnVy9Wvrr+dX kuy1It7hsi4G2mtwRR/5Cds+2vnPrRM/pk9K5DL/OWRbd008lTMnbc8jreOBFpftle98aRiTTV33 zIm08EIzyEE3SlO6ETs4goGDeZZ/cBrU2lscM/Y4U/ifRjmFxo/DK+cdmI1tRGhixMEngbUusXta BzGeOqDPrXNbRIZKUsOm91S0f6oRyOWyE0fr90EAhUd+tWM5BBOnlHHh+p7BpCvTv6xs21C6fwjq iagEHetD5RBt7pZ//QvJ9p9QKdYFXOlR4ZNRHHrkhO3ftLqxj9MqEMNHX26ZAjExnXt0kyFkB31Y pN2SkWZtBtkEXbTGAEIzAEQcD+zdmnxYIQmX3NnghCszg3wJg7VcuLnULp1Sk7mJr22kQhShWyoW 6UtMlRWdEIfJ4kAh3H8gqf32hbH0/vyMz+CxJDY3i48e4ZptaEQZOivEYCQ+KUN4fFIGW3SDqC72 X8KuQxEbUyPjgczV9W4JJ0Mfn4SbxF9ueTmRhNB1+Xy7sbVCn5MmE4fEH2zAZU14N3EeBVD9oExg pmA+wiJkGxWh4zooIxxJHMeqjPG+ibIiT5O6BrSSo4NV0C1QF3GrKTWFsoksCDmgJx1Y6AfiTfR1 DQah7WnasALTyRvh+nGLwzjj0YEfHxLu9fk1XvuMzuHzaEwd10t4oz2HXhWUGcQMPkHFg7eRUqDF kA4dl2Rnb/i5EiJR5GoZWtH3dzcLiYIwBf0qQIJAGWN+mt+WLNabYVT8xTQ72NMWZg95XK44Hfah qinEuLmJlHsb649KaNLGlRGMmk0B9vSqEdRulCO7Kn/8MlsC9Y3r3HU5iwMZvN2GCNtDnWxprHy8 GHAUZRuv1jAM94LhvHPOBK4mdxK6Of3b3S90Kf6Mf6h1p+NpSp9q/JKbuw/4k3MrCmByaTOLToQY whLnONpsUzCfqkoeqo+vadw84e7EyZ0UO6jP4OIa+mNohzqCmvrMUWWROLM1RiIxWbL0Z6ftBS4b qpmJBXVRGl6q+8wyj6WVz3f1rdlTIWlNKOnqeZ0EC/bvRkfGKiHj2LZ0dsdkrUHubz6orLN/oWoH Y5C+AT5HYi2Zp6srOEm+MtQiUTMHZ/5U5EWus6leulvrBVkjd1qqleNWcnIrFO9BcDTaN/kaTxaj qVrduKYwOq8ziZt0DuNqRAeZmV8wz0WqiO6Z7HanwVXdo/FaL4RMKObPPQqK2rD014eh1e7ZkE3F fdD+HHFLwi8kRPg9ZSXOHvRjXnOSyjJbiTWbrf+qKlZWkLTulZRYXjTsFTECCT7LZ0WvOeoZD/SD 2UNAWzMOmpg4Rhe9LbtObJ6f0DADXu0mOYbvMRMCQpPRPYottNTZA0uDkUAsrh9mxYuOSyi6adY6 jtJNMehQsE3dnoW+xDKsounKOvUoXTzP54WacxW92QS7DwBJ0jTcHl+YhTFXwmHyVyR3MOgfauO0 nKPKhLmQ5hbiV2mbqAxHbD6Awg2n5wGJ7q+x2a9EMDLy+wZG4V0N4L0JUw0JDPVnZCjee0P/ehRL VctUsgpOG/c00obUQErPZqtob3fG/iKYbgTw28B6Ot/dc5xw99sQjF3CyEknLrngkaQKNlOJU8al tYWUj3IEfdtlseTRYtyvsxhNHTNmFZsDkxkDDSb+NzU1fikYQp6dEwYcjfbr3DMIX/O7xhqTijli nrolHN2F0DwrTdr8NbpaNEg+msRt/DOvV9sj57LO/P9VQvZ6dJSbO2+5ADlULOMTbQyfjrLwI1EQ XZX5MRiChgojmQAdJakXDoSx/eDc3/fSBqQlmJp0KzxvCOnvsJ+9+fy7Dh2fLQS0frbRgi+vC6wE Ln3M4bjPtXPHHUAipL61V6z2aPk6oOgE8w5EUa6oqgRDi3k8ml4eOlDf8tZy57Qqdh2DKbYcV2di O4WtWPiIZRdeDp84H0SDjjQjCBeE1ntCI/D5nokpuxIBStcFuoTsM9r2b0VUBih36vdmDVJvM2L2 jKdRhIMxRp5rYBfl6U84Upu6H0liLEA9zvHFKCC7CjutuIheiHIZcMWJLALuo6ei+BuPVLFmgOGQ 96lwhwnAjpCfEDE+qgiEbWeWTfVl9e86YpYvCpPV+/bLnMavo8e7jGy8/FLrspezvVlElV7FTH7t wIp0yjzfU+26wASurPdhHRE4xjlhY+QoQzm2sTWv5iq0TWxpPm57bcCzMAXhOzLg6dhhtFAqCFJ0 nzcG3ywipm4umZ05dMdSY2thnK5MdLb28aCKRx+AqzXE9a/xUqJ7+HNQWMG2wv8TQd0EBk1ZgcVM VMQ2tr3CaPrGHTNQNg/yx53sBhXFBUyb+Sm2btuu0zFNwI93EieoKzUKT/daQOMYhmdr65Qs7oI/ lUD7OC4y6NN9/cALSIDFCICmpSIlWCBw9y9EZYZVOy+QXkHh5x8sQxHjtZWjc5SZOww4jPj9Dq5b oNniBntSdms7yuKxhB582aFJUo+zhjVUKsW6+p6gp8SQFQA/AbxUp1C+PJBpgVGmJCPX9UYR+sLM KE9ZPtqons1mUcGwQONx8UPxpWXIw1+OozBprwNj9+PA9Fwus6kWgzeHzkHl4sGeLiPKGhQwqnAX +ocvZV3O8MckRwYGnlOfCY62u1jG227Sf6YkoDGy0YqUph2JKYaiQDmWIvLBdm4NMW+iD4Rqyx/X Faia3xsdKLVAHu76G7WhefEJtO41kUJryYz4z1iaaEc0tQS2uQ6rX98o+8zUbpzpu35POs6tERsI zMrKsBYQkxBn/L1f4kMg3OR5oHbflnqZtfnGnGf7FR8IqQXybA/NzE7tVZlPJ+xVCfAhNjFE33vZ GDuV8/wOrAb9QiK7wOlSLxWqnjNdDf+prMve2TdYtnqL/V3rb9MLvp63xG+Op5dloU8ZJaYJsSrC Jh4O//79B/jgBWfLhWXhWZkbQmmJiqck/ompxsFl9Yz+Z0woBDOMAnVDIcN9hkDlaR/g+Gzv97EE UFOeiw2ALjX8eurHI4pcS+R/gkBWmX7wYAmoVsM37GlQIVQax54jj5KYG62qxmidHJUslpF3fJxc tS95qZYTwlyCyguZOUGsBSo/t+xgn6UIC4igIaNXivcbs4d9tTQgrJcP2DCnNGSUZ4VAxkfFBWKw dK0FO9gbqFgwCqx7GpqToc2hYmqwh+kJLLjMYNt57VSQBu0+uAl/eoI4oNFTMsPcULex7GpfvoEd eQDU5Zx7XdSG1R1e4tslDQZ+syEyr1MGiskdKxuPiwL6OJ0fHLeCmlt8rqQ+dhvRYB9kb/vXh7+/ rjpSH+hgzOFrrRs2NeLPhCzf82ANSl8M9KxKozhnvq/dOs7fGmYQAUKsyvo9H/97yvZK7SEo037t M10bjEXtQ61k566gid+C3hfvwjOmfxub5bxnuZiDYWU7du6DySLwSCCrEDOzhU4F58vWGQixnwL1 geg+epxDK6KabHi+YHVCq9UcnbexRpgODZmr4+mdYyeMabh5kHVX9q89jiSlKfNWhxIxWWD6b/cf GN0B/QwXv282h/GD304IXMkHdaMny7D23tvy/8KV4Xw44HPZcQVigSkdSCF/duIFKlVI59CPNRvr vtgxcEE9CPZuNlHHw5L1kLjUlsdsuGjBz1r6kVY0bUYVmnKNqUBoZOJEpr4FmSQcKt2mtAT7iBf2 XnKZwFE1r+d3JMSLKVAzj8LygxC1jPGmitTbs481c9815OTYXKEvOs5vJfrQT5CJsG1tFgIlAgBh JPCEfPB3lK7y668tg928++mHzJDCaVf//AE1GKYYaR2U04yzDBrOKvb8iod3Bcy4Bv1JQYGtITmo WPSfR0J9A1tMzR3LFHLlUxGWU2hn6fRIcE/hNNMjLQvWBl4Gs8+oxREVeou4pOuf7XQsac0oBgDe wtzWlOhCPQBd51xq6wBq5SkRCoo0AtCFG23QrMmMQ12KFrzBNosAT4I6qbRnjzTGfk3nTHb3hfji PDigOjFCytTZK1iMViPBn7vrXatMHCw/FhppNQFzyFXcmWZlS3S6La9M9+ByIT5NUtbA4TtFJrre 8ahg9teNZiZgvIIoN9Y7ZW+570u7F6EiWkBJJRMYERLXCroiiwJe+AIb2h8hd/fqdJwOC4Fgd7Rc 4jDIsUEFCDKyu5gJe2wla5YvDyF+Vb2rG+lu+EPBYI0boN3QMy4qYqz4sWIk2rTiTmSA56llSHO5 aKOuYKqCWMWqz7PeROZUpodEBvgAX3qM1enjWy2CTYr4W4NkaPTNa+WxBs72QnAtPQ4QjSH3yG+J C96+juci6nk//hiqzKSrZgS1bN0OSj7KkH41A3CET6KDM5NRiZ/bfxBBa5EovNtL8hO7stYj6cCN hl2jX0fW9fcKbssHr3MawfGzqAJNbUXwh/9qbLx7aC/j5SH6hTTih8Lpx6IYkTo1+9dXXWGRDmNH leq89gqLGZjtVNHhge05onZnji5JG3yCiY0ObmOnHmA9Us/U7wzXDEncE8ofm/KVJ2cEFdqcb9hC omf45dPXs8RS5AGkHzbQCNErCvjIrITQubGzBZjkCJp+vFheZwe6/g6xZrhsYjRXC69jhrdHdPml 103FI/lgtN6b5SrIBfePUcGkjd07ubsHKRVSNXpojkTZagz+PJZMGoyKSOsOTz81WYe8zlgf6kIF NqSecVCdtGrJItx7hDkMpXHnqq5TM6mUjeLM56drqhrRvHGF7ZKG73rxWlZGUNAR+wLvxt2MDPJ0 2ZdYcOT0b1BCAAe3ItV+P5Wrw4E4tkzdpkY3cIznxqkTDsQf/hFYE4irAFJZSEXRCw6RWdVI4IL8 fVMZUF6DFH5509VZ2lwkiwP1jrUpSBDBeGBnSgEaNEuy47vEyZuJw5FJfeWJ+pfI9Jngah3/YeFw FnjTYbHcrphA6LhW+I7mnFEMYzx/x9kXw7W3OKezrZBE3pG2EAvFxhq2rwV6QnVDgtfCkk1ebnO2 HPzEuZhPUsnIY+0jrdlaYDVZdoxmHH3oVo9cWX8kxkRch9IXWQVVLP6jCCpXnLb95+pQUh/cIcbz mRQamjMRnMxVFGRmq6Gou8OlnElspBTUxPJR8i5KNn03xr3HtL/hdX/ZHozH2pS4QPpcOUYCEArQ u0W7MLAa/BRdMqpRds6/T3+V6/Vql3tbtPDzI51Fm+KLU0vXqDPK3c93vGfjRgDexGtZ8jzs6n+h hqmhlS9yQv/jcFWTVYqI7drtR3JtmDyjn0QiAvaGlHOGeYS/+CA4wUx/yZYBZNeWiz8W+Cf44VeP XTiV/PmokZKHmcS3NJaazfITPSjPvE6atWe0a22zT6JRsEF67slceu/lmBVAzSAT2HhCwlc91W7b sPGKjYqbGIEYYdlMm3wiiLdnzIMeyLtguNu4xnHIV7gw+8DsPLz9XPRskePunTGQvJN0o6D1MGXy G9SEkS3iBf1WquTWxlBLPcoFAwG+03hMqKXI4CnMUIsDCq3s1Tu22nY6iMXVOI+Ai70rgNFl0h/y /n//tiSiz420Cx2RrjiUbwTDI7VpfTEtuzbwIWDI+i1QevGSJdtfy5PuDtzhFaZZNAflSYNE7HiX iAnCSS1smu+IVnEUFO68JP9vO1K/5b3JPe4T8A4Of1PJoWHDqfI4p/CbCL7TUlc68b1MLwkgTdtS ALpsadGXLh958tlnCA2HulSL7MvO2cviPvVu5oDxhPozHqOLSHkJuj5dAESifxYN7HXBeXvzCt/6 pztEaKQ8QooHBUZ0tiPjBCqqUlAxQr6FZvaNcE6mg+5xDg4r4uD0vcHpUWsQNmzm7LGKOSkWArhE ZYpmsSgQ07ZjoFk4zPHl5jTioWInPE752bxHFOZFxgrOdVTSsf01cHY8cAk3NpjyxpVf+ZbGOD2/ 8zuZTI/YipSFUA9UjYgFQ+sMrH7shWD8boMVXrnIa4ail5l13rm8o9HFtbYSXCBXjxGrvqnxj0Y/ +Mhx+WBF1vEk6SVYIy4tUqdFp9jZjM21cXIruabxKpSJEK00Rxq6fdmgmInP7ffsZ9H5RFfW68MN ZjULE7GNFwVaWYkB9zHCdHo229wAbi+BcC+k3BcAnCwdBv83UxjozXzyvC5p5njg+2fh+OYLTtfC PmJhfN6Ug9CHx968tdQLr8XBkpzqxbjBz8ADvXgpswADGg4EtvufyyswBeZeB6r37mS7X1UM2kJH +X6FYcfunIzpN9gdi1hyZz5eQS9zI9B9rH+q5cRzU1RrlZOvAOzUaN0s1MRaC8y/DrlsRQ8kx0Jk r9FSMPS2FB7JmTM5CDUXTyLh405lAtDVO8f61qWJxMlFNE4FKkzuGvHBRL1bswjpoo6QrauVmVS1 avvLUh2KYQOMpY/RjJ/x0P8r7koKnVjdO0C++4+M1aoQg+gXxs+v6KE4Rx5F68VanMPGorOBNoFD 1qvd+gmaWY8qwJHjmMo6fWPN4US4XwJyYFXUQhdZlwi3rd6rsaMnpFGdTUXiGWI94ukWNXeICL62 oDE0d5PXLvIdSCjeiw7Ncd2B641/oKW0ScntSxCt37JsvPPq5Xrzv6MrL5As9wozWobyq1XA4eGC JtPtJle4fE/fgd0D4XHZjv0o97IWypUP1hGCCxMwFPwEtk4rffnaA2YuNSCJ3pVmyoSIZ7ZwS9oR sCVEpow2iaxrh2t9kJn/gDjtB90/EkAmSUFxeKphlJnW5itNhrnTEZBrPpVxrahtQxYxXe3bNSI/ MTS7RD7MS7HW4O5D2kscYO++bOCtDkTFJ7cmkd4ZhUrj356ZzorDToHz/rNGUSvXVnNDk1aVPlaY jh5zOyU1nrInMB23t342W5JTnaBPCW8VHxpFkCSeU0eXJKignJIekQYEXfYvGf5IW9/AmODbhnzs YXi4NNB5etMYpDC7+nl35PQnB40EjYOJ1LcoJF8QPZW+mGxY23c4WOb+SIjlT9rwO1kCrJ1bfB6o J/wfFWe1jIMKZgNSRxaqhC21zfybt/DpRkPuDlOgXSl7DKwGFw0MfQlmYhypipp88pytvbo3eqmU fAFOH4+3VfIR7lOnAbfbaCBwXr/xeB9HB3QggPqxsyP91iLI3Wd1izAEI1aqSmPivqpJFxbZ6PT0 E+E9ZSzn7RgMpiBYraKVQUeFPgfxffOYfCcOeKJ1SK0bAilbuZbD4CD0Zq4DxARyCqF2vNr0DQT6 j//Ojdd91bs6iu03Q68QfpvpcS+bPI+KY832cS3P9AWTw8f7+P1l/j3Chp6bAZJBlvfsrQjEdazz LtVFEQl95841WXvDUcEXOvE= `protect end_protected

gpl-2.0

3b0a8fd721893b6c9f0e1fca645540aa

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_exp/flt_exp.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block XOCs8Fz01Vgkg/of+pgCwUqsid0Z/F8JB7zS1UPQnYaS/gYnW8lTyz+hBTjPiRV8NtNkAK2iaOky ERMPCWpV2A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block iAmBMroDccPSwakqyAmbtOCrUJydjgJ+PkDg/5vlahkg27vhl/dmwAmygBJryYV4mqnpbW6Xqjq4 6CflzxMRQKpee2SLAW3JoeE7gro/VjTjeQliJRCgHRAeiZsGNob8cDstXCpBo4BYCCKsEHyFgU2P KkyIYXmEliV1tItdGiE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block bjuGN2UMTSSYzG8RwvU4rbVLXdH5zH49a7kJJELyDP+S2SUDkNPZcEhD8PBeDl20Yup9y4PnkDk+ +pv+Ks8XMLJ1Z4rL9P2DLPVuG9bk2N+nX+FoNxR47zBgKb6w9hSWNNAA8fZ3skQQ4TqmYyMiLPLV YE1vj7VmylCr5vyM8jqqFBBi888XvSQn00NuohEcXBH8aLeCl8VzcNADf6CCTlW6DQGQTFN63ToM 8fAi067Nbt5uUqOltFfxHD2kyxGKNiWG9FrcENxbLeGSMnSX+XmmOUaiuAvwfg/PaRTLD/Izwhh0 n41N0fR5LGrcpPzeh0iP//j3xz52cmnJa4WXoQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fmSYm2QzeZgo+dd4HK0tNlaZQJP/1MkQExiyIJrqbzCHxgAJ1XhXNbb6xuAtH0BzwqLaqJT/4BTW OJC1Rkr/gy/HXkzHFi/sJ2wYX52lJezJRYFSAGvqW/3TKAtVdAuq52xGh0pbmVsfm3J64yZGv1ij Z4W52OAyAb1g1Oenw6g= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XpLvGoVNuJRXMoOX79VgS2Wu63MIEZC7gXgcwjnqZKSeuvqY2voDPB2/VwvNvjK1iNqjoWcelbrW 61Mm2asopjfyfOR0q5GrB+GOBtI6bDJdU4BSwFoDka55nbnuXb1qhCzAKZGq32yTb6df1yKsimvZ P84mroR1yQvkcDMu5Vk4vy2h1EPU2k3ZRv/wcxOLbMXNm3wQoZqWN3ZXpscxEtBHR7o7muNiv72n s+AR7OOiDWh9cxNm3E2thu3s3NEaP5ddRQF1NAEUNcxo2fMzhFEHCwqLmJ7qKbkCoyscqIuE/S2L zS+zbDXPK+XirTPOknbk/7D1ocr1R6SMITf6XA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41952) `protect data_block ApevLrppsXNzNMJIVoeOWZ0C4s/enUi/R4Hfbm2ynMcNZrDn+H94bjk3UG2vbXCTt7iJYPf4g+ck qOYF5AKcNgmG2eIgTA/VqgzMi/4t0AW71WpE+RdmHgIDc9QeS89x8c0CvfPyMYDvuzoL+5a6uXuZ BCxfRfd7+/to2qskizJCaolcLcd5YPJD/jqs9NanbZEPeGBWTe3a3xIJ4b3srO7Gurhlz6onfggz 8MJJksZd9q5bmbqSNu9WgQkWjPDxejC83MjyJX5lEb3dqxOCdWJlxofFSymDezjFqUguVRgfIaSm RY/cTg+3TXZKHoZg+3rY5fgF5C5Xtct2ggII1sgcsgZCo3tKAVwccHoUeUYO1xBLoxdFepG+V74K SeJ2lutnk6dH4gy5gGpNGZJi9U5WEK1Mqzdnj6oFP6zojNW0EOxpR2JwnNgz6qVEbdp4NJBtXUIa FcgQ1u1XfkI+0DBwRYALMebp/YXQ2hlep/gYNmCnclAZNGga3HpiozCZ3l6xX1tbUHFSaIVMy98z lnXvHPlizVV0P6DXc/IyZY9AfFd6cogmFHC2t8OpKeH75KSuxaOK3/d975lvS+r1YiZ/fciWWdnm 3BjXbqaxkHHjMCWfcD2l1vFnq5CLBSASQaFnZ8gnci2sxlNLsB5RJBwRYUmOSqOIRhZIL/eJs0jv NwZNE7gZBnJJTWWHa7iLSk2QMhyBX7wGOIzqcJ+SPPpmOqENP5Khip759rgVUFAN/ot6eJBMAdMZ l1SXhIJ2ahgt8hRLCh32dRlGXiFreDpLgBf++GEii4PwldJIcm4MOPAtxS72u1fcMe6NymKLNjTT 03mGnO/x1fdql766N0b1mqO2LtIyknG3nPxMWyj27y/W6xS7TDgtLAt8xVL1HUr7B3fV5ZRZqITI M9nBis5/x8WsaqQUSGtBdbbB9Pcb9kBqhNkF04YXBEH0uywltd4Q6wjrPy2Goyo+4qkkEfQXzO0/ zDiPcxhht42bmGcdxcRcJTw80Nt3LQKBbLXkobssXD9OJEK6QeEVbz5lkHD+wVOKiIrOH9IMvC7W SgKjVfVPYRWD+8sljlhgkSiNRogAtx8FOzeNkD0LToDAL2E/3awPW8LB0pewl/s2xtaBEwep06d5 KvHJDx3CRgEAtV9sYzD4kaXPvLqOkraALP03lQAgZ6Ffu25epdSq18nNIegdoAUp3y1XN9FSsM3x ywqBEUyhyNEryP3LpkH+sqqdgn8AhY55ap8uNsPo9rhj7dMHwRr7bPJptb3bwgGuZNSWJ8JvP7UQ i9L35QrF1OMZB8E2fwm0PxRyZPmPZXwUVghDYMY9uRcTcUWNrvFWB+vz5xLvpnsQJOvvWALReROs znd8n96w0i7y7Q/RSlzF0YmuX9nbnuKDmmVrOTcaGziFQhxs9fWWXVJRDuHSYvLPHMyBfvJI7q6h GObVckn/ctuJ9wTqQf8YKmW2ax8B3kcY8jrXAAOVl4urosQHhw0ZAJLAdBnz9BrRKYxG0FgN9mTh 8BBcrmVGOSyrZyyxrgDyA5YoX8GDSY+2K4Ob9/YFzLImcp+2CdMm37F7WwIdZvzg9zhw8ja2tCIg V2XWZ6XwclvKiDl6M5u1yQeD06br61NuvmcOJGTOKJHbKF059R+lggBXZrOFFfvYDKzpue9xFqeS j2aBYmzti04syeV3KlnKf07z5mZCWV856tbyBoFNPTgTHwEafUkFLpdaALNvtPI8yMSbOs2hrHtR yl638dUpQ7WDasa9dsaC7ywD+OE0sYXmnvlU3r7bMk9CguDe4vAs9JHRTEOnskW9H26mVHcfJcIR Pe9Tl+22Nu7PIrbFay7KxUdcEVGN3p/8HHSZ38/v3nh9TLakjMVh8ldad9VZ1MVORjt6J05OHFJP 0SsuC5jdOfYVOxm9dejyG64+9sZanWPwxaltKY/NWImHuxSDVdCMygw1ZJwTkYosT3N2WpXucyab pA9fyqQRrSastcTqxngsoskFvCEo23QYZNO1K6Blo+iKBBk9gbtjRLjg7J+w+BJGl+DetzM8CuTK b0aEgoXZnWOgVE111E2MHrdClHnWpAEsXQrxK28gCOeeVBiz2nn0MdA7qUpAFiUIzk/sf3xNSRVP 9JFpS/Lqe6hpuT6oQ9hlK3gC1QS8HdXW2dDggZgH2/IdXIvdpr0FiqlGP48FSVc+284lcfoIOlj5 FS/4I1FgV0Er2xHKuEnTEdCSfNF25RNsHkTaUvV+oekJQCkh58RVc6EmuI3XDa30gAidiLOGmBE4 W6wKPo5glVeOSyUOmT4BM9IT0hR5IlZ1O51z9bAJ7bZwyt6jiKUEkyRF2fn7qVJsUoYywtDY9vNz iV4r9uOUk85trxmxASGl+WOBI1zY+l8HXSPSESjxsJuQ4nvEAC9XS+5Ddrv27L0DCSPxJvY2W3pG PqcTGlkBOB1okBWrjOubtQ7o9b2vq5Td6sxq2G1zLPVBusoaQYeCm/kCMwS4XAka1n6/NrD/kViy 8IXaB6JoiZwU0WZvfw3gNblcf2K1xweoE5TIoFprFkL9OsPlWsYXwjLB+scmIdDujSs4gZrSb2Qz xGPvP32DYRdfZAnq8KwIgpWditlc/FsAPFbnhYAHWJS4aRtQJDCS1Sf6FwoNsO+rD+ZpMDhKzNNf LsLGO8Fzj52weXnedBJAFdEkH9wNJ7NfhZQ38wGjroD5IcYG9ImHTphYMQSMnFIgHVdo5EYpZzPE +q3Vdwgdox9R4oVeVyVERhKCw9NABII/rq3tZ9rybaXJDSvYVaBeYKdgv6pWps+JHoW3+xFgbcg2 5gJchAXnMPPii+WaAufB3FyMus3DsZ4hknKZrDuxkLfYhIaNGUU6VVPs0nq4IBy4yAesydeQuxB6 xGcam3r1zuRV0YW1lmFvBbuuc4fRO9dSlQzr8hjF9ZZsaFLzqJ1eOvirZwVFzCBHf1DxhUrNQhwv 1EDWUROj13X6pkccrkMyA8bQVvyEY9qdeF514ZhUCjZta0qAZTRiIvWUGQC6sLUKjUuZosgaoAQs PQAftSbsISrLOXDbFFOmWcTL/9uKgaP9NtoTNes/dwh3u33UpctV7+NIb5SoZ4Y7p2nGkl2i5iPr LckxXqqyfd/N8iY8PQhlTSITvI1k1ctm8zIEc2uu9Ku5h9vnqcznTC7WUgzDdXhn+zX9Xj7N5qEi E6TxkIs5TiXKU50IlANzW6iOu/lPfp5mo4yYA0fVbCj2+6IcohZ5J8dUpl7HfUg5IVJDrj9Omai/ BTvVHTm6xaHSkW6NI7MztnxCBkE0oKGNmoWp1z6kEcgsmR1chm1UBdCqiGoHcGLimnDowbe6sy+w 7GqhrArGDCQG5MCZsxYSnNPFC6B3WKHQP8rIKpIvl+IK67/Ex4mDZ91bp0guXZi8rIofqOvP/DEp BHphkxP5aA6zveD7ijZANXwochW4cqyT169WHWbcbrDqoTNJ1iBgPGcistjMrxAPplTpH+snnsop s6ewhfIj18Fvmt92vEfvSUrVa83+CR9kQXUQnDDQ/pZHCFO4T2g8Nc89mXhtpVgZhr0B5oFM5NiS hOZi3zDB69L2gt/4mAl+PbhvmxV7FWRiJvJ0OIZh7bUHPEHiNR35mfXMX78WZFFcqM0MsCdtxrIU AnrxMZ3wAuXSm5+NtsxQE9xPW6It/aN3oUB7qRaFGYF91cHo5K5zO6yNBvh1Sa1K8eOsKBkDM2Vf XVoUSi07KxZYpl8jDp70PTm/+lkS4T/TYdAwNq6PpVX5VhyNL8VZD8Q/oCDRp4dhHTH8Veld5tI0 9DRWshudIeVGdVIcOH4z6ecQXnvoQj1VSAC1QWQKcIFzPOmV4JcutCBNu7hT+25NN9E8MorH17qf De4IhPuR4rz2CGQNIjdCYSJ/9uYoX2gvcAzdJXXbUOSGH2/X1vJArcTnbxhjCvE8ZNpbgqIbmfuS ZhoHAqlKItzZRVHDDrcWNuC4N+NrvZhbASC1RthIPBgHNImrBwjgd3kMGfFPH9SLWYXJKRCKGNeE R2HyT2YqlDou5MFfczdAnxVEzXKPvaQ7Ihi1SxZCJgyMIJshnhYGlHLCu2HrOhJxmf4phCZSf4Ih Irojn9LtDdbN9lkXtgTGsl6RBwWindpuFEJfI1o474lKMW/r+bL/HRHYv0mr6HIDJajBMEBlc+Ul 339cFTDa+ehZI0uNZfrdj040oV78JU7RM77w11eHWkkaUvw0J3mICDyYbc6j6kqwBGE68FyCYdkT 2GUY6oOJbGQeAcWDj0aFU+L6vE1wmEduV5L6k6DPCDmDfhX6V4BENIvKIGld3m5mJz6LhwpClpLw w3mpDxqaSTcEN34EnqJBbn1laSqIikwevX+nRnXLexSRsKKHFtfY1P/qgaNMN7FyvSIAn2/E/+AT aWvy4V9riwXsYOsJMfTs9no1kCq+McRbT6H5BMh9fidt0XAQnymfA7Z+NQdIObQkrDwXWbJDGRsA 3NaWzbK7ZUNCA+5tItBZjoQivTzo58JIwaFlSf6MBWBmks2ooUhApBjR6Tsn1Bw55z/EiQyEKGvN B9jtcmPnkm0f/WM713Xglqlm6nc5xHIkOAcaHZS96/uCCmvYUqA1bh9/5bhcXnVVRLWYbfDZNKe/ CmVGMFvCPHeypwkyyikYCkfFyryXH9x8jNMV2Pxag3c/UAux4/0zggksQdTMpZV4Ao03FdoTEWvT nQl70fgObUiRR0T0d2LNk0ag1KJbQC0UT4nxboC2s0OYJW2TdHzQLkPMcQUz9GegF4o0816pljhm z4FteMQ3w3WZk08xL5ZpCfQ9bSW0RvGX+N1r95c+N4S5PyMz46JfX529Hql84Fj3ydOT6x3UkReY D9XsyNjKE1rEanFWUGBlrR7NUkJxppphzMzmxzU4xHgyIIrIYrkkiDTWJLoidJOWGSfWW7jjgkW7 MRNIl6ZvWyTUmJr5hHrCOzbBYBs4/sYYi/NS+4PIQ2t5ylHJWcD0GfER/ykcpk9ValYHzy5wESgP dacrcuCjCvIvtOhiraXBjyR2+aMYQJjASpDpg9WnQQvFup4fHjwzwZP3Umo8u3v/TO8OMajyDqYm ZRLZldxz/qum9YiwpSmmTtX7um+ECJc6/V8mXHC64xdUUMnMrGZWQkX96LGAAaKnj8EIeEqmnO3h W96JFRAC9UKj9+7x6JckC6O+QTpB8biamHT5MaK2wv06z9BxtYu9issylkLVl3O4XejTN+gGYnh/ ESzsfIZHyPPfhUgMxHfioQbkXh6qDIVIQLyJRs/QbeoKCPkzgFWeL7RyEn7fKnc0aWp4k3KXgg3t 6FHy1JICgtpsXu6EdbJKlIXX5TAR/KdDx3cxYwSFZEWB8GGcp5whTjvhA7PFS2OmDvPmupDMvWjh eYjmxsI7azKhtHKU1WGvjNXiym+kBt54s/GWQUQ/SNXCOhZL8qmOTqo+o1pHQRTbwUKtrwICdrpx XAd9Pr5VLpn1vVLo9mTqfBEsutX7dLC9cxgzfZO9mkFce+jZFF7K3fNuuzj2z2MgENFyofy3/kNd qyvsvXoxOO4S8kEpVU2jONIL3cA8EQzoTm9yEk5asatzRd29lQDdp2DKT7mOi3rDCBgJ4cvf4C2S oPegC92zIllGMAWf/jSde3Vo048tdm14ixIOwcVqVBhMRVeKXCWREVr9bziVr+8MIbMnZ4GxXK89 hy0ejG8Yai5gXWrvpBfY4Ax3bOar4nE1n0ZuKjL3fiOnktHF6IoaeN8CkzxZ9rPY24i2yZY2+05/ riv+XN/OlcXG41au3see8vCWMcKtko7ztLxxVvZw99YkWv2egatRWF+Car0eQJxWnFL5ahHUIJwd Gua8qLTnK/ovRGOwYsCpoz+5fcoQyQv9rna1n+WNmdauYLwZhRgx6t9P+dLn4uZrG0BPIJO20gEd KlOa0rNVxjN/G7LxB8tXcAY68YHNd0bBXHLvlljCAHUciaC0wTFqGJESm/tR4YYfb9NxQU5MqU61 czYny12SIQwFUcDx66f4KpxIPAKPCGpRMaR4i5M/M+5JT4fRzA6c9+rlxl/H/b78cvQanvxWQabb /ZjRvnQd2/xWxzmhfQiEVvRLvMYyZEHbJBWKYlIaorg66uAdjDTg9UgwHeKPuFv3qzUpHLNLmuok shrjKh56NtGdDfUziFRNlvAXyALZYazVUtRfCZ5T8lzO3tgwJXWxZvkMGO/SpBLCW3UxG4n6osjy LxIwNir1ZKIeRUAB7TE/8m4TS4FqJm+/clk+L5wi2E83q7QzbqHOYjRpi+zvM1Zc5cTGvRpGfpqF d00kWFOyQsK7Sn/Phhk/fNg/2wcbnvtfjS/oZLd7uy72r51ss5ISgMF4LW5470iviH7G8eKtAlvs O6CBqD8UbsORBjRHATQ8YlLIv4N1ZQAOr51uiBiU3gzHh1hw4xOFaMtjQ5qtVQavql3q5BhAAR92 Ssz7h8S4i/SFfEMPk6dPTcER1NvSWCWd71p5bQKJpIj+JWuL6vvppva+XsbSFJ+G4hqGt7aPLNmQ Kq9tV+/rjzbv/7xvrXzgPrKZ9t1V6t+eawz6xOCLz7j0WPUNRUDz4Oy6yjUqE8OG80hLPf8mfb6v pQX7kREZS9NZwGmc9htyTStBFgOg9LPyFrC/NfRa78Dtu8W46HsecyZBtcd7V/JOC7rxQ50OB3AA RJV2jcjmt0Yl8MDLZtTr8kX9t5ZW2kAH9Ob/aegG32RZ56stMl9YQPKFUasIYK13mUofEpQ00LSd Te4X5Cql9384XfFIl84z9etw0/JPsU3epGAINYijEcIklGaamZ6vK8VqN1eOypRkKvFhCbObDizG jOQ5XTJbbYHCN/EL5GYo3Pc83eGsYM92D/V1s7d7DVJMba+5200Fa4p7WSkB1YRbdT4ex4BmiCa3 Z6GkqRcLl0SsyLsnkjpAx5QIFzPnXclD3uIQqQSw0u2hX078HaAIM2W7YJdztbgqCKTMjtZy2iCO Nf9LUBHtg85Hs0gaiX8hsvJoH/lo+ERL8T1oZe0dcF6VvBpyXj8AaC121Tbs5oQmhgs7MTMyJTHG SDZjC0aGD1T+a2Axx865Mm22N6qNiBhEp6bqjipc0Eaakeu/OSJ/220t1DXj5tfk7vjevC3zEf3s yDBGjWeqrnGYPs0YL8CUSSWG1ADX4S2m/lWXUma5skxsGzS+o1JBJRhzzsfQnqq7zlPmvupIUDKj Obie14luvnal2zPJxBZxrLzRTX89sijA4ZzD7QAcQ6kS1aYLCdZ1PUI6/KQyZRjlU8gUTA4+cog1 n6e5h6KrVwOEPzxso2dBhLThQivA/mWfCLEeldV+geEHpixL9DjlM6tqy8fRH3AaVAMKNgZ7v0Wb duIMcgx20g/2CPSWpjC/lWQCRMylvg5BdQIlIHUf8IBhAV1JDEIh4SBfsVsDkmzDFy9LaQ5OSpCF 8lvSaBxaUIAynVS+oK2DiaX1+wZKAVKD0YlFzPcR+GCdTyYMvO39H5vG/c+YFJtUpyLZVELWlkD0 aI2Ov/EuSRrg5WGLQZVIFwpdDuS0iBLYzB2IPytrMvCIx8YcJZfsXaqoMK7Z+m3pVnRqc718NFj2 tmzYyzGv89iIjGK0l6I5iGxa2CsAoVySnArfANkIRJ4c6MGYQUCMh7OtbPt2ZfL8KtGJ/GW8Rj+N CqJcT1KMabeQ+FPYu10JVSgsexcCkmaW+a73AjOQv2/+ma3HSjeKR0jNiZD5xxZ8+Mq5SApOVyH0 mjR7j/+jKkIaSA0cB07pUyQmz3DkazaKZuMnTQJqqI6OX4ubNuwDr/NYFic8ZtGAXIzn+AqR9Hht pv3sjyEvEGyROUCnf+q8CIsRwMVLVYdAKc3WtSpghtYONahen2qvzzI/0cpKbvTEmVVJ3UPAJBur 73BSOMY8vHyeaPCuUogVLtZmBZkADi1JRp14DHJywOJVJoDeYLFLDPxOJXOsnMTMg5/wbSVpIWXP f8bxx+U4ymmn8C2AXctCvnVQIKqAWq7namT/kmW+Cv7Jmrky8sN0jkgBWJH32YNkw7A2wDQb+rSb hN0AnvXgwMCumutBTIreHBsWky3HMdaT9d1Pb8MihJVyU7Qj/Y2HLPCBSvXSQKGPCCme9csfvfRT aAZwUAqOrolzLReheiC9CRWWg7xMoasc4PdU613h0+7CqXeESIoVz94JuV3ucp6YCOStIL7npyBJ MLfpp7VPP1JekuF7HjV3tExCHh+fiT0XIRcdpX38gHCvPDFCxNLrBD3f6jhDiEOJwk6k7ldutmHc xZD0F9TCmOy0/VdBMuLx6OiTMAnHJNb5tU0r5xmBej5udUNSFj06OinuClyr7fRVCkgakpo5njQw kfT0Fdz/QeP2czyxCfcnIRUsfrWwxA7JFDiSBSs+H0zet1XTa8OpiwH8ntmiA5E9ZmWHP1ggOND6 UOP7aVPFmxhx8NwTHVkfpotTCis4qA3hbspda+y2ZMqVsPlbegnvKyZSXG92hK4SUF3p7m3cAokH CbvOKtQ6geHcuTEIelsMQqeJw5CxjyUPwkoELFofE8pKAbUyILl5m1Hl191mYxmcO6BIQtxML5BP +AG9+gOZyhfuIhmObf7dvowA6WTuB1aSepDjUzeQEPcIF2k3w+1ORloNqf2h+TIl5U0lkUxkHooo PyUO4/m1sT7e1+U237YJNM0nC3wxMt9lJ/5zQ1hH2Jj8j9u+ZqldpdQtIM4usdkOpwJ+2u89S/OA ROCVKwDXQ1IIDI/972IKZ1scgCuDyNET3qjIeDxu4PIpPJ4PP+IEmvfuslBH+ZnIlqXMxWBnFxvf 4o7ngdtUR8bWmxMuyY2jBMTojnE5hzKpQ1UefbvV3u/GW4EpoijHL2vdd5zoutLeYqyiax8eHEor V3v4XXApmOullogdp8GJGMmQvLQwhMi1tKtHZmqw3toelHzu+6/ymH0hkzRA9ljMwxWulImhGdJb lHpfl0aqu53T2manYEqAkZJ4SI+Np9BsZA9z30QeDpTxGklRknO9eiG3/7L+54ekFtN7tdESQluo LpLyqH/O7gBVW+uwuOsmduikdXHCFg6JwjBlFvLPC5aQ1V6wp2/4/oe+BUZddB9POK7H9WlPC1B6 1n118WuBAzcW3ycLKzWYFjpmdbMuiOg0+qD8/2oHmES6TcrHRU4WP4XH6LDv70pX7dhnd6Dr/M7v JXpzTWfe5Ah6tP43attylJStY/hjUrc3kdhfoPbixYzg+ZlsJWlSiNCB+OfUq4pBuFJom06eHSzV oxXtjLsc62slW97i3o0xZN6574c0u8PVXhV/0h41RkMKgYJgSodhjH2V4ODn+q2QBEqwIG70HWUg tsTtAio+CKj/hC1/EBz/H66u94TEGxqa00TfBNZwpHADEJXBFpcE/LUs9bMe4iK1wkb1EJu6AMbL ihP0bEIpA9P/RAhy7r6omAQIbLd00GAraTty3s0GyfBeqx+BmuBNEgcMlIM+EeFnxb9csr+CS47K 8MO+Fa7CP7fgFVk6yXmqLEyde4i5bPnPvbB3JU4WZuow8rwUeUpc3kD5Ryr0fWttk3KUldxNCMth GguXupimK7jETJv9RwjCzxKdegtTXDo0eJKBBK9J82Mr03cU8In2wfaK7/3V3rPX6gdMJeHXJXd7 XF8R6x9iVohROYTO2i5DEyaTRYI0aj4cHeeuYgYKiF28Ph6D/j5IxZ/rVowfp73gUgno4jsxhCLE yi585xvIlt/rDFIKCoCMYrNWE0IQ5NCkxdAowWdiWzGSAkvOCvhK8Q/5qLvnLAktJTHqwKfP120O ObvXWgg0NnQKcu3mKnx0AAmsSNauhq6lZRVqACxceRSI0IDg7ttxLLatgvOavdZqzqZK+9n8oKe6 rBK9/0JWS1JcIVK7cFDoROIHOe2WehO0HShg/HQyk0r7YeqKN6nvBaXDfAqssMJ34NjdZPYJbbz+ vWCa9K56w51uD/0wsS7LcEcbgg7t4VL1Mo+wnAAnJa7Fz+SYBexBPUtG1FTYgSwx5HnOIL2yNav9 9pYroF2l/sR3v6541/sKMVvo/cJZl038wbVjSvgPAm5t2tSDicXWIoMTKGLQ8kZb6xNp2eta+DXa 9FE2AlOa7bR1oRYxk1zQT+CcoHtpdME6Xi6do/2EwdtZmTKjq2CMHyImjVK83FDz7MZony/l8cbq zOk3wy8P+C1l6HVOGPLYFxlUjB+KTmDraNwHVYlDPR9iPtWcC9jtAUPleQnw+lpL0YgngElppM9H uZmwKoW8roFc3f2PmIjbJcELBxXsIrnSIhAwrCS5A5ACbUbIpLp/ssHAZY+oa20EsopXFTUqecnY 6/FIBXW9T6wisKr7dk2X7McFH23v1b9QrQ+BDXKSQovV98yEi1mNrsXAs5Z9lp9Ozds4sWQ+hQL8 OG9yVHN425Ag/sZq5AFXy6yNWLU1PvHs+uKH4FRb/ff1XCSpnBUXx/lpOSqa1rH6qkpEkPipwXgN gQRsy5SWSW20sUpf3DjP1vH/tyQC0QnfbaMeISH4b+G/wvRtE6XLH6AWwfzylIlK+lveTVlqG2uo VjR1ZmvnlSaZHmUHdPlQcWr2YosTNlibdueaQsbmi+DbvRzjiVFPStJGxaVAn9X4VP5KOe5F8xq2 hRgx/fgk3FK5DyG3WVgkaxx8Xd6gRjvtUtXP4Ra4cjqcEa7hAWBX2Uv3PlFguColySaSiuKNnvfD 4Z/3opptRzOzHM3KI8fcYz7qxYzTZqCoUYYqr5MB/75C6ilmMzoknpXGs8eTEA9CggUcnQUYZ+Uy dcynJI/GF6ZvXuyekYv11V9H8GBF6M/F41BOq/Sq0Q5DATzHOnhGXX8qvwNbiBOAf8yrk/WNW3x6 jrHZUeNGIIxcygCBFuekNldpVW7Wa8a5Xv8cIxJU+gmAcJPlD73InId3nr7eGaMRN5JzyZxrBLI6 Wf926BhEv5XOyyol8ZaVQYZi51pWa30SU04M1klchph9hhWRwAgi8tJxLSt7qZAL+EkovyBTAPQs 71pAghWNQyLmIZ04QDa08aEaRkiiyBCWrfIorWmtdsuwz2WysEP/w35rvviMkPG0FgfTtEbzlKoz 671a6mEyG/zX634CvGHDeXFlcywRte9TaCrVhRvPLwTtlVw65SiAMiM2q9GLk7Nntj5IzR5oEihc fsLjFLeECMCkYRgkyntZHNPsaTMeijeZ6PZTTMyNNyLMbsPNNMi2E7BqfmOE4L+UbTU/j1iuZF3R hfKPHU94wOJJQvoL/bU8xn2CDXSXhkAphDCCWyHQUssdwaEmuBFkS1Rqf+YyBvfTiCH1rIqA1wya Yt851sdvLPntUT0RseeX9k64M6TOMHuUhOUn7bpAp/KtX34KANk/q1P+FUWHj/CYi2MT7lMBmsDW UCyvaq0m3PKbPA0S7RDdCe8UwD35YxDxKRPC25AC+Sq8E7RVmN3ugGxWhc0SDDQghoxVQJXgOXIe 2cqLgamhnBFRZVOOhzITeQ/JVbEO3KXLASWlQ+cadTsXRsk5B7BxRwLlJfNxSqLjivP8LrQFnk1l wkVjB8skI3h+PTDcfxE3u1FOJgAM61rEWwr0oAkGQdgrqGJLPh0E+I7tA96x1gdcHB9Y30RKmXzS dTRmOmjAAS/q7zs8kvXaovu4qamyPaSZ1J0yQzvxiQTz6A0T6E+Bq1iQmNftslbOJ6xhLFC/hQHH Oe6aXjF92pkFTyM2GcdDR940HBozQnCYVdMl5zxXF5BXErkQ8hvNWWpxxkq0rCuDS57Vo+pHxzKF QkPsAraJmI+aYaQvbmUe+6xhOL5CWQpZXOMwTwLSu40GT2uyhasq+evYIdpd33plqTHmLBQxFHve nLjyFhSZk+U9sRf6nU6xTBtZBD4gplcSuDlwWP9Eg+qPzMjNHGBJgZWrJtKRTQl1om0SkBWat05b uuZ8PzV0a5jYxCzYTROG7BrrklreQ3h5UbwBFWIgBHPn+Bf5rPno6bg+IbFNJlmrBREoZCqAdPGl 3tyM0Ao6HIqoJalXPlNuAnmoQXvmDTtVQ2fk9Be/BxMYDTka118Ivo9v6KpszfuepsuWm2quv6yE 5vKg1r0zejudNi+ilKV/hl03B9DxiTPmtP4MRWvkGSSESQDdxoOzOnraXxz1/qN279i+gElFswFq cTyT7SEaMm2qDxdU2ghfDX1vDPEYKb7uCYosJ+u7DTCCVTvuHQ4Gc1DcGP9cAvIumAz/o5VOSJ0R nTVLauIHdOVFh0VamBNQd/WV7qbMi8RPY88TtDKWTsPl+sUc6pXepr1QL39m9ZqgCYxr7mtc1Fp7 S5AtF2Qo6Y+gGOvUSIptVZFtAGdWvf5dA/UYvCBMRKXAatEBZYDnbUmkqWNTpJI6WbVPUEjzmfDl gk6+ltJrrWOfPGLlJERp1nAfQL/+g5p1so//tGcCx3qXTDrRLmsgn7a0kyHRKVDCLzGqq/1xScHL LWbaRZtEtPhsvjrQq4f3euiwTP5r9i8bgwH67KLUV9qA/kw2LyTS84OEIXdeSGeR1ITFtdkRZQgo W4Sr6sCi2HTiNJCQXutecOfwhj6zXTqk2gec6saIibr8UPVSx9v4E5QlyqjtEzQROiAbKwr7RDkN 5kGu+TxSPFVi0vWvAXnQOCqhhRFfc3vHHm5dN7X+iKfhqyN62z2nhXlkJZqsxCWWwmNvspHkIXR4 /om0JNvVbWnYk7iTz93WjiJQyF8GKSniS1Vevnvtqi2m0/wWWnwZpOAdZ/Y5btp6LlaAyHFKV655 V5goAsYnU0GIr7gUtUge8u3FycpWXjxm4nXZ5DLq2OGaChhaL7aMvXJOd95TvYSJKq4uLWQr5M8N mSiL+51xnjSWO1Jpsyo10Z5rPqsthUTXd0d3tDf1U1kwhmIQWrKn++5BuhYXIjUlKIllZbUOVls7 zOT9WbgSCYYGkKmAjRStovMI322eZVkemJVeGJ4GHgSEGwLF+14XcmWXbS6cRFCEC1W0QTR3Jsh4 lCc3Ktnol8S4GYxfoppF9xlJRDBbJh+cj0nVpwtc0xQwve8KlUNNNKoNFv1TeKt7wzG33MyZ+aB1 khDnGAemdZKWdNuelYYvYj6OcxUwV0HYvavbAfhu+JXXh/ihkLFAXckFNkiAtgfpGQl1vdj4N/6o xaJdba84V4Hny3UhcZUT6DB9P84JfcqhL348aOczeYuVKdz667xx0rN1eLNhE851M8RKSpDqhn/8 keVT1eSd1pPzy0Drcesu2Io7eGZlCuT/WJcyJgEStKJ36fY87Unn117qKCkVNRX2n0mo3DUJqw23 6JmE8B/zNopBczB2dbsjougjD8TuXkCREVAjkjdlNEdZ/mxh1dha5qYdADKx5wvvhr+UQ53ZZVA1 DXjmowUhrn3CPFHcr0wXx9KzIqpvBAnZtW0C5rnPscglt99MdV50trWlvbv4jK20IrYlx3hH12WY 5cGWaMxuEtPVSXstlgJo2F55rgcFgYGgm8nToOmoLV144XbeCeiyWDj+rKPo97UlfQCrh6WCkGO3 9jtDnvta5MmaVbNygWLtE7ahKtGznuZjwe/EGCLakyh91WS5qIRtrJBog6W1R275I+W/wWdJRAp0 iMZA6nubFMKiCT+j+urqOhlPzJCfM2R7UmRtlk7wvSOUgMBzHyVRyuhtX6XStHvYnGJy+lkTnklx soKW77Oj4uGFTpsxDXaxzDgSzo9NbHTL8aopQShwrrHcM8H+avddsXLO+ksmUDt8jCUocEKSbGpT YhMBbCZMF93RWfRRt6lqx79o9OUXn009GbW6d6hhx5jvhex8Pgn9u06VkTJmHYBlo7JqNz09iVsg Du6XFVg+4+O/nizz/p3NALIFYPmFKh7q2XNlbrBNCxP3t/xxLGedTu9CjvhH3Ol6owF80DR9O1tE qVfdQFpk6eHj3KmnQ2P3bbckoVqwQGlt6fQ/4W2oYjOAW62cMV4boBKmhYWswvaEMpkFVVwAI1jN no8fdm7jqlS69zEUzTK+amOgvPWyS7jMCtVAYnytvnlw/poo+xlXJ5ZaMxUGmjY3RjDymbPqwc28 D9SdfGz4+7fW+ScA+x0hQfTh9quS+zudBABIGsWaIJnacxzzSFbprHCuCoSfpI6WhQwGQPnDnkqB WMxAjBAOW4MVDJdBIaNmT5/zYl9zvp9MlLJqZJt+EJ88H83hGwkrhHTuSYGa/39xIEMFziS4JlJe w+tvordLnSjLgCu1iRhMBkYX+GOYs9BEq+mJS4CDI6Gb6bWx78TzWfvBgRRW4mQ9DNMyzlVY5Zr3 +7galzjhEKQbCQuKunr/515R2ZqA+dFykBIviqRkc2iNpnEbA4lYlSP/hZE27DQWBvkzpkDTT39a kxyG2SRCSWgikEypBQBvNcSH8Nsai7DiEYKI7FDl17NRrLrDK97LKHU5IIYiGZmnhj57NyXdIsLX WfAO4K/bl0QpG5N07ThnB3aq/zhwoOuuNkEUvVOlNtrnrBpkv8+nT6eTObamSyF5DJURI16yrIiI 14zS2e4AAqs18JMme+20IqHlOjnrqQGU+6RBOLTkV+SWiBd95Wa1QZ4H8c5YoYa1K8X+KKYenEMW jIm/An3+gwCs1mkJd2J6j9qSODFV6a+y2rU3VJB/v6fhCn80KwXm1sO62r1WtitGaVhoDcteWlyU 07dJSgaNcsQS1DTlfqh01DTZ//Fz9fAbp2UUFRitSjexe3PS0YuFU5Jc5OH2cjnzDP4jKQpMHCyi iW/UCCgRlJefvRR7Ac3penc5vautjnLLdDopQvU3ui3A9It4mkshmHI1BuhQ5oKrWbxcFLm7eyn9 jPQiPtYS5k5uB1Jc4JwZQhGUIQiFzPF6q9O6r6+2k1d1IBfdFsWDHrqMBMzTYlin0GolFNySYigN YtmoxI8W3XCQeBfHm+UxtMkf3+76dx0u6virZZIkrB0PBCec1YZENoGypoXrctVaqWgiul3wuPnP Dh1DgVnY/va3o6JGs6MlB7UY0qMmqb5JlFNsmP5CxJFRVLjrJtt25ry+oFkGM+LNA7JdRBJFeaYV 9Rf5XeTIpgYFyuQLa8RvUu7QgM4MmuOiBa36iv13DUBLNahBJAk4kr1BGrpGOKIq6DA8gQaxBMKX snjzWaY6NuKKXNbTm1zkDko0A/ddhnFyMmnih6CoLn81jBoxhRw5OWdgtRMJZp1Qc3pGam9/0jyv oZY3/NggKd6F3nmFbdZRfSd+TUnT42na7xu4iQ4Ibdfn7b9ib70aALGEAe6mZgFn58FW/BBXWWFU PoV2et1BJoAFx/fGNKzi0L/b+yJHTgdKf7Vns1ljUNtEHBXMQp2noySQoNDJNLAF02G73H/wwuRZ 9h4sY6yF7/DYIXDVW3xt88gFYxZJCvYOZ125iMUYwyPpKhyfGfgQcFHZOR9DSYB/xtCmU3SP9oLT H2i+GBgMSEuR5O9bDw6boDRaDperTV/h4UfZCggvGHaMflEDwaSxpXqGn1TI8piQaGdN4sGKvz0c pq42OOZrO529q6HHhZuqSN5YLzxcNIPGi0MVR1RBuUu36NHIbXO89W/N1SjNpsG84zL7HKqPmFoe caLySD0JSntRdxOC8oB65cGwrLPUQsipUB6xgYqoTCMecCCg25jWDlD2CLOVpFd8jraTP2yS270J La1yA4CN5WHpaVhSp1B2bKDnsg4V74J2+Yhe83ZoQ+PF3QFaRMEiKO40AaZxVCcVLkInfVFrOeNX HcNojSFo/Ey02+JkSWpc0VM/Y43iQAQXMBuyg01uZeZZ6z/7ME6wPlkEC1A07EhoAilrip9oGY+A Q5gpU2439MRR7CN0JdEAi4SH2HhbITeVVF7/p22I9tGX74j5IzBVPz3nqcPtEm/cer8eQwzSLbZu XOhzHue7pOf4obt9cCgRTJ30+qqxTQrsQeMSnNfWJXppBfLoBJA3OQibBGSwzWJ6XWkpj6wMiKEv okEnXwXx6EZzZJH95wdqLzXdnrH0S5ABS4g16haSbABHHNFbASZX/75beZMK3tcUFrOaJTL0C8QW ADHfLfav79vrSVw5CvkPdsLrQ+gkAGoLGrQBKmDNxT2dIZfQA4yl0mCMgUKZjj0hL6XNZBEzlIz9 BPPee89jY2thO6BuEtuQVb70EqjGTC5Jo6V6N8HiqjqaomMYo6ZJMsn27ZE37BfjDFvyqYHUdK0K 7hXuxwNr2EhBZSnAJwrggBxzy2FiYtI3Dyo8vZInvX6yLW49Hb990WjS0RiyYYGkNLpkMop2lL2C g5481W/7bwE+oS9EEcHog9UQZkF8o/jItjRp+IfcMekzeuoMrTgXvN9/mUCrOZm8hMQ9w1cAf0ii vxHukNqepnyp8hKHvhNaVs+w/iCqVfcXTOMmjsIP9Vw3skqizR8WfjOKOY3tUujsVB9mqQ9dlFTG iVbK/edK+ClbfdaBGH6b/ktyUPX7+uuP6nePTXrK57nMYaJYLZFFuuoRUusQJkAs+QYN2hMBbHy1 PcSu4bfz2vFVZPgmuRIzSzjZiwugrXBXHj23lHao1O1fLWeflU86Mm6fCfW1FUdoxAHIHpQctd3H Z3HpTm92cOdIcXnn9vjeE4HLSwHiZ965JdjolzBjKdu+903OTffDda+IP0jE0YQ6ujUZHe2I0vEW 52b3GDLk8+SxvWaj5lgWNWw0TvAUXhxo8C43vNsJ3fzbdGEv3YmqdhtMhUjp62cEXqdbkJhG7C5h VkGPvv+VIia116JCoF8xZk4bbm0xTVK2eSFieClJ38q3i//q5bkhWSvkTuy1idEXlo1aNjdt6aGZ NXcdvZe6gGff6g3O4PdzweVNiLWhCM7sfv2ZSB9YdvUQtm7ymzD7PVKaX7wnKoCxOOC8eOW1KkHp 1CuddI67UP9pfH8myF9bOM7aBfhYYaQIqCPYPl9+uLVSvgrhHc9H8/ceCpIwTNqi3LG8v2r6rdNo xbRwN+4COWzN1vGJN6GXTbEfuUFAG/3UB2aX4TJc9/mJ+e3B0NybOYlsCTqOagnJIva3JeNADVUc qA1qPNU2Aw6vP2b7fYaa8PqSAk1U/GeaxC365JTXNbNS7wEIXpiP6um7oQdnnnJLt0YvzhfdflvS 7Yk2SrEzqzSm/AmkpI6W1vdzGyr5bupF3iG6SZYP2S5WFbFyUYr/seMR/YGwf3s0GZJqPkPE4kPt 9usQfRPKTz9dSxdRIx+g7jf2HcTeWswE0TepBYEUf9bNsdiO+WZHg9iY5GMALuIaNJfCbroU/57L LEPeRnbb1VuI0gAH1bK2Pm/4Oxk98e+35DYy/clMf7N4dkpuzhgGtISoGgUS/YpTJiDHdQnWCZDc mkb0h4mk11M9SqnGRtVQCkKl8dAetk7u7KjRp2hVp1AjhY/1x+YfwlXuOUlVgqGzuNPDCUc1cr1d J4KqOcOGNn+Ya9vu/1rg8sN7BLV+khrJ8vxlo+xUr8zAP2LhJ1xG3i8LyToJMzFd4rW7gNF8xUKQ V6og1PF6zvZloyOp+ChWU2JgDoY+TBA941svwnT5NOMem1JAwy7ztS5XwvJA7FPfjaMP7dmMYszW m8QvRDo8IgAnnFH9Mp+zj9y1w01EUAU9ecKU/SgJ8Alt2ilIqf/m5ixcr+adPAaqOxaJaa+kKpe0 wTGizH8r4/NoAY3UloJF5/mBiOyN5F2qIPexf76eFcOhfgRZnz+xONf7QDvOhDcGk4xUCI9DFcq7 dTHhjq1PYd9pnEnMp1wedQfdOOx7dkc7vsoMqh6g2nlpxa+LOpA3GDYHsMsk+l7tkwkJOq8kMNFr ga0ryuXH42DSH+8BDjBnCOGC62RWLn8doU8yz7sfkYaMAiCUaRl8+Xiz2I+nGbBoxMFvqBhf8/RK EawSdUl0Zye2UZBzNVvwUb4TODk8KFSxwTVCmeOUvzyAtXVy0Ulttqa6PhTAn4YF4YduI91wz4ao nmZNt2sN9ZTuBEMX48IPQs9eXs5MBmQScsf3gBSNePxXjkZslDn3imc25Lv8fmuK+lryT8YDxgAj kvmXCWdrSOrQT9myXnpCEbIbSxPUc+XLIEgFCe9VyIGO9c7g3n8Prd2KDi9lqSWgDAcycH7ckg0g le51aML9lN0u4eR4RzTpLqvSl2rANG+r/uSqLrK4HRTlOr4ijZvHXA3EIyat/PK4m5MSxm+BFWxy flY8Jxy10KCrJ8JtZ5HWyuX0LITbpsbQCozsrfnpPJjWG+XHMrtIpzOJuF2ArOWiw6UnqFEZ7zD4 bHCEaEKQcqE9bz6Dr/n5SK51lcXyHnV8NDHazZP7RHayDUX/KeKSYwHmDNcFEc70EbbIU/MlMbpy g8NeKGy3ypopkBQvj0MElPcNtMVlu78BlWfMUdqF08erzA5J+AUMlMmm4JhaZFzRnHiPKLDXzH3x xkzAXopoast1wQRwS10XE6u9uNsk77gDYOJqLS0TvLX+oAzhZzM2PJ0olAiJ1kLnkfKjtH5HGsrp lFu4Uv8WdOoy/iiiSV2cTW42UaO806du9YHyRXD7EHbHR9pKFJWo016XiMAAa8L5u0b6Q+XJ+5oI X/SOE9GHOv4Xkamh7L/KmNyNnL7L4fRGwKHj7rq55fRaXD9ff9UdzKXCFS6IRd3TikId6tqAaG+H 93KnQ/ucFr08MT3RQRJ9dQfvdG58pdUKRzNV0SCSpWwxmKaEJTYyksiS3AxtwNIzVEBUR5GwcKvC AbyFB3pLSg7jo/a6Vb6efdD3beGB7Wi7GR8zuLb7N1jd660tWFdiJyjHOMaRnjktRKgY8huTx7Ob ncEvCnUyA2r3UsNqiLPXQTXIiSItnMxO2jrL85rTOloD+/CWH7vIEr1U3szYXnAKDi9Tl6OJyo17 JBaFKTv1qCjEQ9bq+wClxt0BiOYN71v2PFyumSSpJauTtQ/zcxayUpkueua31nG0xdlSsO654+id rwNUUHsA5iPywjbVKmyHIwFdWoXBBjN5FIDYCUuCEASwhi8RL6/m+e3miNBNUn0eaZmWB7BldlNw LKhc/hbwleEP0XAUTT9oDp63+0ODklC9GHxjJos52JRo9l52pz4eijj2Mtm9OumdyJehnkhb6fDL 3iI564gj/DqIFRTizfeD0rwpnCeoCnNcHD4xHt62d6C6y7p+qbZvp6aNUejzdu2pk7z6sfXc3Ree TrZalGd/eUBuW9qkIzrDINUPlqvVslDIyeVQiRJbnDkK5Pc2H/7E4VtIoG/urG0FLe8fp0leEb4y TajgCdfYo0/j9L1179Diql0O8S3uKyNv/+cevCGvlT6F4pW7pLzR8Ul1o3BXu2bKeubqfU/T3cUH +OnvJkwVsfPae5sFLMG/EWDYJiiY8TZBvwGwkpOcKV5/XckknmuHt2miaW66IhT12HpjD0XqvZdA bg+qnU0X7qgdvobwePrMMXQpZFJZzH3oCZmSsSTppfiqccIJyvmfYLH06XDgvft4vxFIsI9CA0kv uP/Pz5oVYa2HUUNnx2wUaM6CZ+1aaEu9QLdyAkJXjQozEG/tCQ0rTMaCYaguUggtMC+bEZAE6Wu+ X8U2owYs/z8MjTnAY4JJfsYJwsvH7OHtuY9x4XTALwBtPn34OcGz9rsUDITQhlrwRNEZ0N79G31f r9qvbci5Ku+ci50DIPDfxgjeonLhZpyhmZXISTKKvqr6ATPTzUcz1sl4UDi44Emf92q2mbgLO4qV Tya2imXMFRqZncZy8NO7FSLj70gKYdpjwYAg3XfnuR8Gj8+MR/1eAMKV4phlBkwxhYAyEUW8zVd5 1d8WSwU+Qvn3hfaT2ah9jU/KoQdohp2WNeoo6ojWbzeXYZMq9jtdZ1h62shdBKAwrLvn1ycus//S 5zPpAdJn37ijyqGeL7p2zW0MsDUQmc0StI3ygyaq9VY6tG0VdxiZhZtlxtIhtaU0tSRNUHdgQmTB 90owXmREvOjpnHvjxWOfy4kB9/94dZzm7xPxsq8p4HCV8nEStkvaqfyVYIJvbJZXTH0C3aZghfO1 zym+eTMEGxtjXNIRrUhANksSCMBcvAOn4Pm09w5H/HklN7DJtMpQU2U57pZ2rPgER2fZAlmGWH9r 4L2+reW8BqqthfCJZBucRm3F3MoU5pAxsL9D+8Fjg+OoK8qimYb1Vr/KTeJFCGSFzW2OS71Mx6XS pEQseUDZyChQsFu6sznM6y2CdnwRV7dsF7oKImkb6y47/A7sZkGFP3Jcu6kR3ter5dz5qhHne83i QlcfpSXTcBOubICnSrFju32giioiXuJ8HG7uaCF06fcQ6vPZCqMzrPVHgowzZAnoa90gBAURPwrh iKg8eWTjQdKoqWrso8mIyxZyWNSZvQZxwI6lLdovkAOfGW/kUo+nvNx67yu+3dShkemAAPhmmryP iDWrVzaIy6CWauFrxCbU52/6SxIkv05/y24KEzPoeckv6G+WX/a/9zxZuQRbJWAgI4D5z0RX4kFf Tqiww+Wb9KHTBrsPwnrLur/MAOdboCnTMeRQG+S/HnK4BLyEOTmUjjxURBgKXiq9XVvDWjRWnDcB a/I2BhKYTLEwMXS0LBkocN0XD1AWJKHh4LDaJ30Eha0jtb1gIgntLowjkn6vhj/HNOtILhPAOe7Z YZZmsiN2QM+gwOL7nJUYLpAhSLhA3eumq0QzN1e4ahpWokQDOTMNoxm9GpobmNd70FL48de42TVN Y0pHkEJ8qDar1ZE6Zv90hRai28WPcGypCc7DTWLiJUD/yCkOQdRWTB4sZOX4wuCxAqPuiLdEIA6k lSS39YXI96/zKJuPvorNmrngfbI2WY4N2nY+V1yo1BC2mBgY6xSvVjppi+3UCxJiQzrdawZBM4Q4 gJpD+EDq2fa/U8yiwcEMHZ/A16b8UB7syhqZn+JMTg+LbPchh8GhHEUohgnHJcGLeRanVQNjSDtD gsBahdtff1Jr/wloLmMreYkkMdCzck2oGOD35yYqHHtO+2N6Jnk2O4MSIeC/bmyL2n2wwhFe2Dpf U2VhM0iRveY4BiJeAwopLu+Wlvm7l2nWNKjwJf/q/QHKVAbJ3WG22FzOHgVkD+nAdcHdWKogoMAu sERP2JLAYqFC3JNwxkIoC1kOLIKO/XNx8qg9uk3mI3mAQGuuYcuXog2NS6cwD7tanCkNA2N2qIvC qsKnpLEedWmTfvkMmmwOPEaiOSifWR4KdJyl5HTt8yZ4ei4T9C5pc69CgLul+72I/5l1bh0IQcn1 xYBvOIFo22B+79bALr/ARqmiVE0JLu7J8Huo0XUso9zAQqNaFdPZ7fbcomzz8gMHcmt0h+w6BvO0 c6kZoX3mB7zDAq2WUqd7+Bo0OGpUM4For/zGyGRbmARrrQomr9sOtLeMiE93/LeXJJBSCy0LD3xg q+Jpa1uhDRbF4WKFvlhwBnqbHqMZUUS3XvxvWw0ZzQIsKNH9Lk/osxjFvOkCZ6GNnNjNZoB/2Fo4 LcsomcJu7EGMyfw4ohlVz1kDRBjWHlIUf7f3ToInGuk7VSDzyRr5MYzmobOTXQ5V5h0VGMQbE/Yf SE7PP5el0pddxQpfS2V/3bYFb5Bi8pjAPpecKjxPHejPkGsXfJoyZZpQQzbopqLuwvQ0M+qUub2t +Zy0Z8xSkNgnOiz3gPSmOeboeRzJskWKIx41F5vJx5c3GqySuLNKfHX6xqM1y+ky4WkC6qXs6R3+ 74wWtVHfEqkrmoWGQoS8DeL/38son2oOkU9IIu1r1pxodLlAWH01qX1pFoB0+HAlGMqaYCzKgcOZ +z6+yXaXIgfLHdZJoQe9u2FLqZQ3arSjQQpllNTJ/xq/ClleYPBoyE72pf8wbXkskxwYvEoMFJsn GGuHvVh6axm+75CNaZFy4iXceULrzgB4Z+mz6UPS9cvlOFTv8D9fmOYFhFKdIO+87VBpyI74/HRc DSsH2QDgLWneg5kc/Ihl4UZUfoaz0TO7/LjLXstKqK5IEIdadjEHwmrAF0/mtGkkf+uJhm1X5td/ Tl7s66v+gxwa2MNjZPs8/eCdy8V6d1LxAZEG7hMRRRkQWCAhW+A9F/tjeEPOQcm164GSiz7NbadL 1eeoPEFkopcjWRjIoN0mYaRVlxjAMYU1/rigYeq8afMXYkr4zfVmEM8jVi5E2POEtcPynVYu8GTu QC1U8UdJiUiRseKXhDa3HVFezc530W08Vy7GKxi3ykrBEJ02tRazlDSinQi7OVXubm4cZ+e27M+U /XpZg9X/60eoCR2cmpuNFkqYiPwOSOlK3V+YIzPUFJ9aFjm9Vm7DxKCF4moKy8QQyFPA0T/t0oIg ikmnbiOi3iHIXhHqIUiK/oszxYIuCbHL2hpwo/DzHOrE/IxxeDjiqOU+p2prCUqSJ0OHJh/XrsDd 6cFavb5IkXjFto9oZcH7bdbP8vllrK/2FVSwJpkME2D6XjzP/nsrlvbjqHyFFizSWX4L03ruvTYG EqZinQt6lR6YisldvMvj6sJPrc8ueErgdAy4lWwB17rTditf04wHuyB8Dg4ivxNxnY+6SP6RcJHQ lTmya0CdVgMcMp/lsqSbwUKhF7CGXzByQvSoiGwFyVI+noF3Ro07g6YYf1jjYAHJjyuoxRdibfIU KI+epvr2EIsYs5cyBsY7rZ1+duSB8L4oncAfUCYDLXxwKmzpZRJCG7VFLo0/vjcfS5D9Otlnci2o i+yBdjV7QQz6+R61XB6qETl+OApMc/m01uvvGEKO5Fq4Ahy69PyP7vdjyaPv39/xOSqHuFolZCWv SmT07TXCIzgxP5+vFUm5GEigDo3pXkWMvvllm7a1Jrp14Amq1tdngqyh7qlBoENPX36Rn6R49QO9 K6rQQivl0UrkTRnHvAgnA2LhM9RdP0d1S+MGUs5UmHCuseMyDuvjFyASpVXmhzlciJY5lnlYrmPE HHifMohw/mhF6ObF4Lt8rDBslI1Y/UESzL2573oTHP6h2LubQGNhSDMxJ1hGyrbyo+sCsCLWVoAV 0A+wdspoppSTn0faDE3Ocbon1m7sOdz0c8k/bwTeWapx0ZgJeWVATj1c4YvHsRkqgdp17LerL7Xt 3Alb0jKVUkystrRmGt1AxW/ahHSMds8+tsocDN2qR2NPabhlAWWDeiclS5YQEFhlNsnarT6O+UTk BHeUuZIxH7byFASXs27Z2ygvskMmIULICQHJs0eL70NZqAwj85xmLJWDlG5KaqovEHP0dfnTgdzN VFyaj5Tsb1fBrTEqTMlzIQ5tvJFE/s4O4wy7s1Fp8ElYylc7mh6uxt9yd9flfnLe/ACgbGB9VJ6N iPSGYP9UTwgjGY/EGg4EVHSXOGt+UOaATkOoZxU5hso4GYOfpzTEB9Ey1eKEXBNw/cIW1/xxabpi TUpipOKN1+NCxA6EZqHmibjCDNnGYIMp5UJ6jrBy6KHArZMnCD9WLymDTs1kaOwhpddU3XLFC/mM FHohufIyRXe3wXa6th6U0pbTNuEl/rMytH7I7wf5nEt6GnmnOlk4WbmFNahi2l3CqexzDnQ7g1uh 3nLV/tXb3d0Ube4m1C/8WOYyhCxRHlWut8CHUy5sJHoxSrsyhc6YAEzLUTioOw2iX6PenptOdXub OTnR31h8zk15FI6K2Lx/sYoCasyPpXlwItFqjRrPDpSzsu3Xwz0I8xhIgW6DLN7NjWa+EZckB8YH WH3qju7k1X6bqShC5AorGxl5ipNGGvvK9nsvN0Af5635eqLtORpdbqWzWTHgxiFBpAeIg/9m9dW+ ovdzVZtTgdGvkHMNXNFhrj3LluGwq9E8Ky2rg4/flwGv/7y7KgpuXvuk5xOYW11m82Nflb0ld3zm GAokjhucf2ml3SEGb20ggwylGmHzBikarcLBSDDdX0oSYgvkYEdKeGyxoTYQ8U4IXXB/lkXa3nGG 9/ULaJ1+HVNPAuj176cNnOdCRuQiPhjaX0IXPPKr/X6BnNB8tRW7OhpN20KQkM2gCl6oM0r+sqj/ mqYGWbeG/T3TGa6NEMkuXYbhxoUONSezXpSQ8gaxMAsToEslvAQmQIpcsWjIABI6aacYq78X5CxM soS4QMAXfouLajWPmIugMbv0huuIamZNoFP2qvPc1qngv/M0wrMXqFzezwCFr6nxKXjtklgw7cpg 9vy9PHP+hNvWUm45OsD07vsNdjV95GOI5G5Rl7E09+VWfLFQOAblieblQyg0osYUk0kzj6cCUp8J YypWnstJl8T9abVWufqmBWw3Zam4Shf+ZIJUwl8fHUC7GohkMpKrBFECrZ1Em+D6THVw3Dy9ahaU qF4tZJJUhR3srPPRCX9nmKHQyIJX8XyQPLLzE0oJpn8hy4CNztfOvHIxYoSJ4+B0md+8a/b0jnIt e7ejTDjSzNGGKKSSby1cGqixFGDx5GfozqDxUlCc0XU663nGRPmhxU20/jikv/ApUl8V8LGdpyHS 1+nLLDhGF1BJ6KpQJ6MaxBQPmkV+bBpdnmv/oisIQL/0M86vGNtaFNhnOXofnRdvJsxWaFXZQYO+ 9IoUzHTmXoSiFUHJKryFnibvnqCJrljFQaitGVM0U935dhtAHQeOEPtmRLIL+7UmJOKSDraFG8ig 8yQIeXevFZNuQ1n/rn/Ed49n9pBBHkkiEIAcd1NqA+djY8UV5pzd0ada+nBdVSMLFS7tU8tu7BDU JOhjW+WWYfmbqywVjxKgsMX+C9A/zvJgysGn8QtDCar6baM3MYDNuGHORCL6SDZi8yC7mCKFZN1S E//tU7eDF7BTTC41D8PIdtmo+CqNThfZtHuc0l1I5wrn2jY6knZtI+XMF8bPnfuIY2jgCqYTGYcA r4We+84tkp3emnyy2GmgJGkPtUwxUKPbtB8anaR77I3rdUip6n9wovd32DhLYl3PkRq9CK4P4DDf JUqufi++9CU23HAVDLUaSrDfvQOw2eC14Z25vNShO1yMBFQVR4pJ4v9iKep/lWgKoGhnT/Dtf0mG NiEOmuV8dN3ePVQNuXsT0t2X+vfcPYD75C+XRR8mU3rhbdjbLQynbgiAWZV+qZmjqaVxIpIsUp2i U5PjGoeQpsmeHMMsdCyyCqOBIP1eGbodFEsWF5J2CBgZXFZXj3G0b1n6VNGosrBz86AKWuARHg41 iEmtLjzrKqzzs+okdNILwqlEcgIqOSg1PZ2m8YtKQkH3xYaGsHvx80RJc4V7hFTzcGj7v3NLsOJ+ mg0xm5tOSvghXWKTUH40RNiBetb8ofN4TrO5uLCVhY8XaOGWbRO/5d5X5q9crJdp9SN59v+udZwp YfGrAxUm+aJFFfJpOw0iG+MxhWhyOdqY9BNhiAtGJcVSBBirRlWOHYhu0i44xyW0waHTBHV3x6oz f6fYPqfPdikzvuV+2zMfclkC2GoJZiJGHmqlwuCYtHYxSaVVPLxP2oRI2MjKT8LybbTYHY/C5iil 8F3xLt9fiRkvxiXkUMB84+R7ntqn2IT5GeMpPEBDJrlDgj4Q/gpHwuTgq8edHWmySRCGASy+p+Ti E3wKD7mH3gnkD9/P1YjUMnATNNyIsgNJSrV7GeDa4LbwkX8KLX6rveEaki3pTCYVLKUGAIJI8oDS PkI00W24NNtLJgnB5RPjWIXDZZcZVc2S/OOICtE7x/4F8wcfZuHheSzfFluEWq0KgBJaY+iyWmSu GiXDCtAlZWyis9RDLz2LEVkLNuBEhEiKWyTLvrtOBe4971He+zANZR5f2Og7VoTXKH4H9jXfTSn7 COof4ixbUg8VKEDBjO+tFo66kt+dzde0VGY3/XIOGwa1LQzuNKfUeVO2Bwece7bubrRK12O62+v1 bdWB57CkSdvsx3rgZTgG5BHmw9vQRK9NEoA0f1f+gfQYOtapTx3SjZs5pDCgTtq1bwRF6d2jrYa2 7gW6DYZ21183Xy8hK2P9jDwDewrp7F+TNloX9z13Ls6SDiejtN/Cyr5lgaQP5J41uqd7+CFXHl5U NIVVtc1VzkD3J6qXYggfTAMJUg8y52rHF37h7lW3YADsw2vjI9RpmqkNhBJSiB3cjZqDQflTMNv1 cmGGf6ce8mwrHLPPLLD+oBK6CcKbrnIb6NO2fjbH4URyi/j5+jIr/j56vC27muQa6O2WYhOx+oiK KXPbIyu7D8yVR4t7ZqWRmC/CxuW+JpEfmdMNmB+xuSjFIU8466c8xYBdFi5+u1c4qSnWomqb0myn kiXAYgzXLy9oFGEsACOC+/ZeQ8eGfSkBPH/AU+z2+2csXwyQ82S9Cp4hK3NAGeL0sjt+FU/u9F7V KU9wx0bMUJqF2beRJIMb9U8RW3G9jMRfCXZNUlX30DdHnRYMxbbnM5cjCmsgYHtaSPLJQsO1Nnid ovWNC/NvMLILfot3w7jYFYYmNfgNPJ8TZUFQNGhK4SxIQHyfYPbpQc7Xo7of6Va2QMUldRUvdjxx tLso9EHd/Q8WuQQU2xUutSdQq0gvxMG+O9PaTufS8aNsEthT9Usvcb1GaQ3zpowneg9U1CSZ99dt QJ2J0RmwUxFTIXnyMS/5hmMjCR+DRfoE/Amyx8rVWlt6bNPcW67lVC+EqJhVEES648J0j8xJWdL2 W4FElT6n6S0MVKnvflLEmOPEGtyyP2Z0hsqfmp72YbNvHEmlp9SEaHyDMgOxjF1A/oZBL/Kvb36I Xh+ie+S1f6xRZH3ZrThsjNghjNjf3bqh7JsqSVnQQVx29kVgs+bI7f25ubGhBUSZtDm3hvI/Cwcg dAgwiUe4iI+i46obPcTHmYTXEDnSkuHE86kahWpQXwchvAV8vs74IGZNel03V4VO156STBg3oHo6 AUbrCLJM34NKi5JDmKvFLqOTXHLFCh5u6advqdE9Q2DnOYk36gddLpxOsO+1sUpwNMDZ0ocWl7xv NEM0EaZ2kL1a6TF525GQIkMKcsw4+0o07b7E1d+ZrMs11SKLnk4EPXzp3IbLCaBmw0k2bOuf4uKi m+h44oLp8oNXob5xTow0fs6nDVQgGoZb/bY7t+nGmecMdoIkoQJt2epiAqvDe8oxJKruUyuBij49 PPTgIdgjcXioVeIlkosVbP0JRRRTTOgkCzyukTFNbpZXaijnGd54dvaWdeZqxuGc366sdPf69SGW eUVyVJaGMCjdx56REoA9W/meHaIk81uDa/TiipYe//6ivsfModxe0yk1g+6BBjR5sFu5Y271WI8O +eIP/AcdQ8DoM2ndoncYlOE9eOV62T50kFGUiKql67Mx17SSsnxvC/EQwCEi0E8GDBor6tVW87te 2e+TL4A/keLoMooAyIL1x2RzsIiMNtTs4r4xhuEhxDj58LMaLxe9J+tv/A8rjNHosx7RDQZYPWZA sLANtmcxNMsx/MuOR7+hCny2JoXzFK5tTlW/HNo+gOFSJpNnH0VdSJha/dVUpeK5k6Gn9RGjfKFf c5tDkCNr2dnTMgn7jAQ4vcsoVc6zbEEylF2BWlMF4+B5F0FWeD7rcFf5iVcE1IsFAjy0pgCi+CJ4 9Ov6sIFfPXuQg/LNdqzyb4V6IgwSSVCnoupcorUfpdGkUMJvkul3zNuosQdL/zuMPRob2uN4oC1g bONADJvecTo+o1uxy1C4eZTPyl1PiVdsrRla8aXNCHmb5BGu9xcYW1qM1K7DfaTBVOBe2YxeYypy EW1jcWk9vQnYODti0EIREMwA0SNVqIOrgxdmhZRU540wmhfrpqGcX+KEZKMT0vc/Gxp+Kf67ZQWt 8wb5n9tKbel2PHpFAoa9tnu5fvrBGzVRaHWkA32c5c6ljp9j/xRP3NYrUX2f9nFeYHgnJncApdLA OR8KxSfyxhWlF+g6ox2jp2Cel9KvfOXSUyfr9DJRcUuqb4EA+4t1XZfa7TFk4Wuztc5qG/OU8ul9 3gj4O94pj1YNOT/bgoUPNC0rJFvEioSBH1GBfS9j8dB31ujkM6J0nG59x/uTyuIVKL0BEulTQciE VYpKd2BiJPmQa8YwmL8kSuTAG1rHPL3VGlgQMyoop75BXUh4AQIVQAUrhP8tK1ubL+D5UobONbVV b5S0z9LSc0vOcJ2OGrIJt7NckIUILwyFImbqr3XYnch8LCEt5R4uT1XIWdzPLhi2IDvmtBpbsPNc ySfFW4NTuZFO+1Oa3Fb30OdIkQhaCmwtgL3YwjdHdRh/BeWK6rPMFQqcl/gd9Il2QfEybay/c0x5 eYt8EVzbOGioIA8DdYxgRAGim/i8upKSuDVziaiIAZx4ZcQhmn0GLnVlIXlPln4i9IZjtNv/eld4 bPvnqprDkhT6vEmk63RFB+CIWiKgYY2cADqVFae+L1n1wD/1oZY/6NTLpK7YE6wYy6fvmLW80MNd kgfmgTXR8WpPIiarWd4+PwoCPBP7aP4ud0FVKyRYO+lP1pbAmGv0SwtSbSzqkTIovEljzl6Y1OqR 8UA2h+qivAro1cKcYyLy826dHsZPA3cSpQZeLuKr282r8gN8aKpag7cyGjtay4eBUelkFxYAExiY 906J99QjunD0uLtxw9G0sBatogLN/5mXoSyAEsqj1THDrE6MpXNDAPeS8FIW0cn/4wajRiSoHdeH PCOsq2X8O5LjZJDGZJXMBeTo/kYJeIp4Jx+eEXncEiUtHPbgfl9MWuOgNLLkKZycuTKgThjFDkaV rQHcG247N39vz3Yvf4h/Hi7T9Qtb6Cf0O5L/XJhgfOPuNRcj3WqzyVfxZX7U3Nnmnj/LwqCTM2Vj BwGVJODmLladWgeqSsi6EWXX9qaeWH5mgR/4MART8+QtD9QFI1PEhuntBHvG1pXH84UbEy7OWu48 O0AXhfOX46wb+NxE8uA0kPnyeL8h5GfPPhGyDQ2kM1gD5yCyFKsHvmPzmmvuQn7nFG6d0OXXJCwr NB/hX4ZyayiM+WvnOSqLh+IkdXR2Ve91AyVoWcSj9W1XFPfAe91FAhklxnjriTjEYDiJmMyrLsx3 riqiwRmSqWzeSFxZWU01ADXLrufltSAyl4qsOdft3wl9ey59J1kkDClVZISS9+jAuNrQaV+LCopJ jZX4vqDgAqo8ibpO23waKMi9presrjty9YmRDYd2cMusFtNqhMtIZg5kJNZ55tXF2kdxaFmfWzrv TbZ5vhmYp9r7vH4cnGUrAjZ813u4FKz5H9VjHShBcwbEEZ3w1FCxV6l3Pb3FEEGUtnefaR3M5POZ fwyH85sm7sDf3hDZU5PGssPmcwpZMLLWJOcJ0QDTvZlGHUQWYdsRijbV/G7+5O9y+a2/Ntoj0kPT 9Wk3IYq3O7C4nVkvwUUCequYA1Mkgjf7UaYjdUy1OMaQEVOjkmede1xO8omLv8qenDltcm9AGFC2 Pc02S0mO7Rrxsf5Zr24star97aNaNzcknS2adzjKeAzd+tcHIjLOzN21nu9yQVQ7fFDrIWf9cgJh xovDPWo0ehBQAQ3dGYc71PtI2oPK2vgUh4bjld8eEJRN6F2V+PSpprMZ5ZwkNWLIKt+2NxreruzY hrVR6jkR78FWE6DHzdAgOvjwoRzg+mHRJM2PzGPkZPqPCV3JoUPWdazuFr4EzpGAFb/rs8o0N3Kn b+wLi66ZSG+Z0K4Mjg6iZFuFZ23cOajSqh7kkpz2qp3sKtTnxTtJXv1eAPZWnqCW5xeiFrE7a71e JD5kfX7AGnqoAzg4n14sDs9jr6JUAu++8DXWDjMyrLzgJ925aF3Ppz1OJE0R/AWgqNlZKC8iAY0U kQhabTxJBJKCLUhxCcSvfnIHOcQEHtDXXANB+SjT3kvXWlI+eFNXEXfBXgC4oRcv1hpo8yYxD37m PRiGYm4pJM2P26Iy58bctP/amgllLmAhXOcc0bWsB0auUxTxNwtLOZqd9GVYwrakyGKL8VmgIkHk nxcQH37SoXWvBSYLqpiIRHh2c5MurB/gKXKoSqc5Z9z1xES+kKyO6WcVQg3NgJDoT6Xf4Ay6jtWa yqhxafWujPpFlEbCgBSiO7AuB+JFdY6d+Zgqnb4SFn/yChW9Ou2Y3iXTpgHQdR+3jmR68UN/O+P0 rkfK/X+mWwNbRirwENXNRCfB2ucgZfNRRpc23/IT5SNVeQ2ZUNdYIMeZyEgLktBfemozQ0Z4bvKo e3f318PX5F3rrv3G+Hn2cyHOY/6UHLDOcAwkmojzBbI1zRO7FvTumVsZIw0GoXwln0D4c+rINRFc p+pOr0mxXyNjKG89uGmBtthoQ5OMU/cmZMxx6CRn7Z+NDMG6UsiPKf4ZIWELZsBfSBJTzCCEkD4y i5c0cZiIjq15t6MwC3eiSGGVtBOYwzfrvTLlqV/bhaYtzulbtOduV6vllMdGNuEBDxkbNJvFPPZp LxaawcxVWerFdJzlohL7bxTqh0vz99UemFWHwlxwygYPd95UvHf/PYzeZz5AbjaK1dPuQLKCxY65 bJb8xaeEJC3mSAcpSZQBm3jwEa2N9QACYsVTeysQ+eA/h8+WPHJQUMxFy2VS6Xx3Bj0dXC9SUUtH lNF48srNLaEaSpn07zyHLGmXBMFFI51AJ61RcSAC91A8XdXf8gDY96ijZhXZVvU4/wjUlS0ZXqo1 8HelduMkrzIraZ5gQxO+uShz1/q0KzfcAsBUMYgoMInoRd0iXMTfd+wTBMTQTcoexqExuCABOgR8 Jxiu6+SwaO981du++QIbRPpjt9sW0Hw7WKN6PIWffibr5dBgVf38mH+XOzMTBnD72mJ9RNGL12A1 Z7GwVxZgV+/kXnTvgDf95HwImM20zETX/RhN+H4dJtQfT/hWih+XIunLYPDPhuthtAfEIW+DTcts f9v3P8k2k+bJE1SefleSPiEDf+eE/1ByxhqObyNWsbdlu8W/VRnQeRT5C48F6bd3gOR3Ei7n1E4P dE9gYAZ6EsEBmQffWmw5xGtUkkL186oWguATGte7NF3t5Od8HLWqgJmp5G5v6c5+1kaIiSMk7Rqe TAIdAZqYbwGfRHC+RKEVuXH3uSrUBLjvO+qJ8O5M9VT9Z4GkzoiRzeoHJmhSj0uaecbrxwx+iJDV DWuhtUKk7UYgLMh4U6FJNmJM1DTk0LwAFpTDdY4/ACXIIY9CeJSro/BWeJEOCUJM2pPCDMwXVDB1 WJBtMbMeEZ/cuNExkA+3m3cSZ0PZwLBAJWGbAY6MQTVbR56Vba2jJwLlCJneJygEg32+1risTUDg A54Hzi7FaFqznZIupf6x6UJVK/bcQdLoz34PEGBBnDw4p8ICQ8/fxsKsIDxG8AKP15yY6DujjKls +Em/DOs+3WCkuuVqyL2PcmWdr+KO+4aRVbH+RcUAGJXGwuq222puJRwrWxqymmlZ470/wjg0chOv bHfJ+rrR4HqFtNw49XJsNpwHl6SUF6vGcSeMe9tz1cHF9c70H/njyV55IvotldhlsiUYw6/CuYGT ql38KkYuBBKa6eEJUa7gbt6obTVNZna4IWZNAn7TDZ6j/3V1U1e1tar717OLBzlSwunuZRPujjPF 75PsmdQkQlZv9le2NRdncGZ4B2Gq77LIbW4At4PECaA0VmaxxaheO/3PkKUxMedWyyhZs2U1NA6T UM/IpTF5VPfnozz1IfVi1F0E77cItMnJW+lmJV0a2r6q7v7lgLJjHj4MxzfREAhfco7S1jJ2oEto UZkIhRLs++u2YJ43Mbvpm+tkU0egaH6VL7x5mTR8gPqcqxAuog6QkNj2a4GW19JpkKaxoCusfkvG fViph3T6A1V/lczstqblON6/K1lQbx3lxaEM6iTmUFt9PUlLud5bCSZFLqLKviO7Uiuk7cogd7SA Tmk6ahanV4jLX1uMxpOpWoa1DJLUDlDLZhM7lT5xmRbhHaI/1unWzM8fQ34sp3H6nXTne4IQ38Pu WBVM7OnvIdwHVlHo8TDBh4kfOfrevXfmTRxIUv4yrE1MjEtfsZTBGNmdAOZxFbljrr6o2S9ftTFm X7yQ4U2lA5mi98uuTUsS36BkNHe2Mu7yRZ2tVnMpK/Gyli/KiVfZD8haL6bhjPaFzqO8hQcGo04z U0stu/mZ4Thb8OWYanSGQGNcTL06En+tqUmWu3tS41IWB9IcHbXoOVDF8GE/uA3HPYfDemxVChJ7 Rtw456eeomzkD5CET5YlnYPNnQX6lglEmhQmpJsxDjdlmQrOo7mgb5XczBZgJ6X/jUakLLX0hco1 pMoSYGKAsQuhDU/y04C/Y9Tm0htF+T2t9Alzt1lkyTqNLH8tbfLdJ5yyGg6rfgXgShbKFimTx4oW pRQR13f3KgXRtLSP6r+zVIgt37cMmSh88qzVNIIlhMMWkqOkv3va5xYJDRgtnx/l6VT0NQ+Cs5u7 XxpuTBR0RrV9VkO31CUuC9yS7FpbPNy0uPw2cNTq583suei+62F7n35YgY0500x3gJx2GQX3v0XM cU5yQ+vGilpANhY4mil0RskYv+kzL0DA8bToEH+eRVVuQMPXxt9oPQrMMetc2O1JOF3+yiPIa+id dE0h4qBkOWbTF9qKbmdK8uaD626kG07jK8rJ3hvNlzlG/X64i0E+OYcQzRsNnPwBir5yDvKxibVd hWB91c4DTSjQvSb4ilOrAKJV00JK2hXOuKsmv2J/cnt0Slcf81eSCiNEbmdjxgJmoxiM3Suxz1SC s6gJOO0DkvpLP4b24ag53WKREwXMLin4CccFdz3p8gb1G9qG85h0deXIg7mRUJn6lAbbeIqqsjuj GG1/62YnkpSHfGN17eE9Bh9hWO9rc+WGkV5hOvL7cccCb3heZgnAZYK4chHIj6ZYmStGhPDC/ztH rG1MDmXFRjdR0mafsTvz5GM8M+bglMeTmirFfWx97b//Mqix0RTAiM+5q34POFQd7SNslDxvomV3 Bikzo9mceK7Z686JgEZMfplEqtPPgaeXpJ4/czGR1rnEUI0/3ldlul9uXXjYiRpsM7qWLedypfpz zp5w0uKn6TzvLp56x8XpUNraa2oFXiZf9CViTUI91PhqddHE+x2ZpRmFABwbaYcWUzeykjcj5yR1 0dDf++E+qgjeLs4sTlAMDvdJn+mkDYIPllTldBDtjvYMkedGhlraheQhkba3Ytvcipn0ZtdZa7Oz Mqpe8z/ARp8YiA92VgXNzOwHQsyi8yGgVwXTxjPmtXioHuNx3OhWWAR1NS6WmkVG+E97nFtKshY6 GrZ7wItBj+631OPVzS49sQUdj1K7p1y9aJi+L7CR4mNNAcarf4KPXCmw+cUVBZWcWiw7V1vMPog6 OfBrui7A234+XLSNr1AaOk8BpfHiS4/iL47Wv8PWEbicv31hzFvqEWRm+n4/BN0EMZGP8iZfB/c7 gZEpU4ZZzNIi9Q03GyehvT+U4vwowb5KegqrNkSqAI3M/VKaKZifrq7d53o9O1Tf3/IjfrDwKKme w97w1sBcIfC3WIc7Cs8tI6AzPvcCOXCA2sJomhG7Dti3LdFqP1tVxBWcsxavxa9i0nvVKdXyiZO/ JnB9o1cS8EWrtg21txzQRdbfD6O0vhijvTR4RLq2GnCvv16OAlIU9Paunmce//xyRFh1W1sktsGA 5LaqyoWqWFMw4vi8cFccm0gm/LJv5WlGNHugEPVqakJrOypgo3HVlPFLb64mIK8QC86Zr42A+3bX nXOhozxk0ZUWR4pQJUFT6haFecBlkCN9bKMDeAyxdlVrFvD0muJw0wp0tIGzNGd744+GcKyHeH4B ZxmqmaXz357GuPYIWM75TVreW34soKpndUoHsgT4HXej77z4TdnTAG5G4QZUp/dxx4mV5nsZK9Rc C9PXdHHWocPvo77TwBi0Y9P4cLN4GP1lcKTs1HHPyXUcTuvUtq2W0fgXbi7UDCUmXYgAxpgjo8XI a2K8SGXUR6kKKOQk1mKar6NZTTgEUjdcEl2lE+5YHalvwfJxu9SK5TL71QbMPAFLC3lqcCeCfV7K YcJMC3fu5awlEqbW1ZqDVqIuk5uUokTgPSBcNjS8LJueiJr7+iBNU+j2zdhL0CCsEajiaM8mmEBy x2K4SFA+ueaASFUpVPioF5VRSqboQTKWClbJIymNpHRtCE6NMXB0HVkYuBYVwsbnJiG1Rc2DXhFi qppup/zVQmXV5Ch7psS2h+/BUQAdJIfk0q8tpWfybh/wKxJ4xcBEJQAiyMYLg8e1ch6sKXCZnGdb jZUJOFfQI16VjKhU8fCFpr3leGdLytz5nRWMvKwTZbR8aHj/ia7X44qfGEm5H9pOL92rMJoI2YU5 EMDTYhuwHEvY6sgXgUn8A8KMztyfcP4Y3QjiSTDGtivOB0dw3weGTjiLWevzWSKsOqi2rvalyNxd jw00coBId3Cho0TfJ02sN5e+l5nhFu/NeTLNHnfuklFkNczlUhCQsim/526xn32RSBKZL9HUrhZ9 P5WpJ6P0w53hB5jR/ErKMyv+Kr3sQQbLR/JKVwITffOgW/FFX3CbiU8in1nkU0kvuUejcg+OQklM tJiQ4yVPemiVJG0B4kDBoUIQVCzBl73952FETg5rR8MxRlP5PfC9DEX8SCbjgFjFUZweH/Cr3FeB 6YhQ6yqHarQ0CHvo9PoR33fQoc6Vi0Qfx1ZjGm7LRCNDcxxRLMEzPyVxWHBO19gTH2x3ovcU6qPX o1oBQ/8/Sw1/k301mideIiLa63iZI6ndo73XVze1m2WnX447qNISBIJXOUi5cdBazSfSqIaow/KV JrTjIouxePieenQdSEmah+nHQi3orPZmrSPX0qVxMJ9w1lxxnPmh/qLkDJV0wzpEMM3lUnBCS+/2 sGUPfElxyEtv1QJclnjL8qm3RpGxhkkPKDFK0f68LqMfdL39tKkZMGrFQxDbTMg8GrHNGJCK6wRr +M/jZO85xB2xZZASwxBe4dwCGBiDAytOWSFULVa9u1n8owwzN0sHl+KnH3zuVVje+V/6cqbG9IkC I20lVT4E+VhZfQpRSqXCrcI9EssBK6ckqvd+EMpu0+aKu+J9u73KPHu/z1K7CmUtQ+BCp+9joc6w WJ53X6y9eVG7wy6G0E6HoOifXg0mplstc8IzYILKtIs6iX9R1c8GX+izkesiTDt/6h/PoA0Uvebb sqy4g6cyTBURQMG86YD2Nx5r1Njng8tXQm1Mb191IujWP1OTOMOIQzHNeS4RaOiD69GRVPS8Z4sE gXIqyXMmctozyGjRAOCXRYfHNlXyJGpDLvYPWlQiW5n8IBgYpkj+ctO4kx9gfUYRe9SH+vhnet2+ UK+C7bjE/SGo8Rznn691PtP/m8CeMpZ/CvKF3ZsXbYHLTI02HCS4fIHE/BIL69fqJkwud7Oq1TxR EbuKoNJXwO0UcqndHNPbdH3nlrnGmZ43ZUxndHRnQacSemMp2iIiyrsWnEu2fW7x5UQoND5ekFOX Aby9brcwt/tGmjqwOcr9+eeyPMlm/Ri/wIlFSYn3cDiludiBSmDBZb5xErH6nk2onqzIU+PDAMCX wVphc61Lmbu2QOmD9deUM+OSP+lu0tgNRMy3e3DqkMPo4scrJBOSod9RQrSctPX+E5zmKHpzM3nO zHCO+oOvf1qpRRWY2xxCaf/nxJM2DQSobs/ZoqHlQJMW84/2VFrGAaPrCmnBvLTATJpnu5MdbidB FEjpdeLxz44+Am28Ge+OU42j2rKOVnwIevL66SmGEApNZ7Ut+1/M0ft8hMRlzhVyh9de/+rpGpw5 t6RvuudEFdByOqCI1fYfRlO6DbB9codARTlOckGPya+U2q+KfOu+wE2lwppuWIaqW4mH6YUjgh6N dKKKTmxdgTObBPq3pLmg3D0wuFPWosMWyY5rdLNntZxq2akXxtGDze9yj4wqhGxH0U09ElxuuiI+ 9jrdBtEj04+PrifwMULzBYhlJWx6VqxSqT0BlT9dVTuho/4A4XuLgGTti1y4DPr2uIhykwWO7y9P +9EVw5ybJldJWC4h4g8t9ZIjxsqeWcluxsdD/P2aVQWxSnJC//EzzsNx0olPvmg1CmlUMyFWwici zeQlFV0BEEjcV4nz6e5a6e6H4eBbomn3RrYQZNdgv8sPYKz2+8ZbGO7r3yUNmUBxE7Varl+OVK9B jSo2Y6ja7hRHtggD51qSrGhZ3hWV+HWsU21B315pQNkWPAGFELb3GKjB5muKoyx1XjNYEE+WFiTp J3CHm8o03cdq488PXwYg/vPVCrQu4bksTZMPZk9IfW7Vi5g8u8CDAzvMf52C3uSGKzbuy2sOypwM 5LTq04UjkCSa7EZ/OI0GOZAEZkrkMzrwsKTgaOl2CTEwwvc36ustoB0mEmTFDcfMrBk7tigCF+Y3 +D0q/xn/qDCkgR/8m/oQJfWPG/1yE2qd23jp0s3pIoQybP1JXe4AoPbQMPS1SBLorkoXxHg84zuo 0VXLCJCtHbYroC1zMF8Yyhf/95W/eY8uE9urFF5L72/ioodkEhRLwrI2FXxpI5jbTexMvvbS/Obd xA0kz3TCd63wid3fX5att5pvV/DN+XZ8eiZ7EGf88lhnjqs/jFzfSLN2D8C8XJbAI5IqxkpkvEVq PxdEwJq37UKGqF1h8JWHexhnebWUvx6nnjP/ZJA1lM+G6gLJ9/4AO2ZIFLcP+Z/tM2O2p/Qx6MEN KJ8TM+z1MUiTwCzwgdNmhSLsbRbv7YVI633eRXkwKY73kUSeb8PJ1RYx0MUj26YApKLagcLpjOc8 v00g1drU2bikhDJfSrDwGl0ItfFCU/w6J1u9pac1krZOKCDk8aKI1r5DfdUeWGFO2xOBQgT9iSLJ BJiJrccfCAGz+ru4GhYHodlidR1N9x9bKBv2zrnPqyvfJKsDSQ+C3qSCBWSk2s5HpHFmNdsxkv51 qXjWmVclwhEEy9vWoMg51vxMk8EX+xULT5VsnqAk+gUrI1uPRc7zykPNqADVBfXcGCtXlhyvms6Q kqbJ6tnjyjrVkxQfTWt/WidGiYtZZjPkLDfQxDOtFeIgVQON99hWh8Dp0mBTuac+M1Ix4nqOASs9 MK8t9BfRDGGgSfoqvm9hBZrF27ZyHY+b25zPzUkm9GZ+BP69f35HLdvKj8eJBDyrPbrZE1G3NrY3 8rk+d/q/BS/VGsGSQcCz6eRYp6oD7IaNNuVem+UhCkGwR2uEvMivhe+NMLGxo0cLKVKB0eDaRpBP HRbx8bGS23OY6BbByjUFRbq5gvYhNfGHbHEcn5rmYaoxQWMjim1+cicWgy9id1jJ9cO+Fu5wqhOr yoJb8uoIPY0Cd6alJTuzisDIJGjwu9DmyFKNbb2vlaa/QCoEIbVO0sbHJglFm68GDCXEc37QvKQS ATdyCtR2MaLfQFqj6it6NQIMUbdYoNcfDz4KxmHXSzhV1xQm2dEUKCxOM6BVEJjChwz1w5FVj7nR aaszLY2Bq+TfBJKxEL/NNSH7QS08fdnv3Gxqp4iKTD37TMQl3nhs8DIRgdLTIn/P5uihm9d+9EPj 9e24182l4JZtf0/gSzhR8IRWgVkuw/6OqNN0PYTfnUSZuasUKQl9zVs3/QO4jiu0IH7PbsRsuhon fAZJG4NxJAda1XezBuV/caMzNcP7LyuQj1du7AY7UPpRso3EcGJRuRs0MMZA5O8wZu84q+YfcCPM 5Uma0geeAlfWa++Hq6gu8yMH2PFbO3pssWHnKGdt02giLSeyoIG5BbhZH09W1uWwOYtTcE13s+gM TVUJ1WYwsVxbgMN81eD2xjBh5YRSu5v5C5MBP6K8FCnVQ312ztrUijsvwc61nkDfq+TfZpnmU4re WzFQWNQFwIocrJafXlYTYGXW5oV06U+yAOMIJutZmnnsypm4okmvUwSvbeoZ49GnRDModrRP9HXE LT9ApVMxUMUbwdnXFtsZDHy5ZQuM8XSwO969jO2aBClOWZyigGD+7SUh0gXNNz4UNRafwxhYrS45 qfUwBy2IirPaHb76n66F0NdQCOyOm9ffGnI1uULgk8su3cp/ozrrkybpJba22uuyJmYDjzp5q0Gb PFGDfYL33sqFan9bjfMozBYPK8EQQpcjzHdQj9ZxLsyQDFT6wawM/hPeg9kxCSs9efNFp552hWuD I5epoX+yXUYWCaQh8FlkOzp28k3e1IKo/9aZ0ZmMaLJ0qS+OoUjN2rAaAGn2FaizNSl0dVxJJ5fp U3Z5ybakGe77F6xazrWlv31OzdCZZKv/Ayr6Bbw7OsGMNzqgweMXkjncndyf83L80g7HjLyK0Fcr 1CIRXDBufZpuOWEg7sYxEO/cLg77DS5vFSy4+6ttAFXrVIpm/aXBCfev36UgMXQF5OqLRnAP4X14 4qIwmIAXKfTucH3CeJQzdD6JiH2wOg7X0jzRsoQ9YRQg85ZK+ECtLqhHGdvkngTQqTiiMgtoLzrD nXa0DB71otKFir3A1lrOano5hOnm90aj1LO4pCBzf1eMCOtmJdRPRIei9pqdD1IvfHOy7nVbBVjf 0vn9qAWGmdWvcmEM/vxDY8pwVhM2wehRtXbZEj6fD5s76VDjXuFCRcnrb6T8EURcneikSJudOcGy MCTWf4+pD8g7WKAF/O2/0seka4mD7JGiJp7bY0ON43agRsQtRH0oinBLHOsfOIH8H7N9/57qHxx8 1PEdiWxv0TW67X7UzRpi5soQJcebUWaITjvHJOPco+nEsOs+bXUwEvmLN6EWNAEJa+eA9DV/uTjW G7r8iAgyeMx3r0R58V/1Xsm1Owd4FgcdKfClmQQ2sAd6pgkBvROpZ2Tq3EcHy8LvH/rYQIYfkhbE jtZzix+rRzmTlo1QMrYY4GuIgH7tpPBIq4vQjAm+J6DWZIpDAPxgzAmdS9yHwxLWeNM+VhkeSp9M SdDiqkdlJep1WazTXCi+0QXeU1GjlEcpMp75vaLZ8udu2bfvp4uxHUs7Nkf5V3QAJBkMyft7RkuI GzORbXqFxVQTwwb3fUSg37LXfKiX31HCqluUmimvP8vUd+67nYjlb0vgyG2eSuugBhDLD47BzWBt Z7zeUUfvZ3dewA8cBizLp2WTNsit05DvICqnaDvmKkm/ac84bbmlhMiqkfmv1v89FTpPkvXA2w6I wZQyIUFeykX3rHU2wxUlLqWBokLU4OswYOMG95LWs8KNY20jUmVJfnxF8PYJrREiRCuCwFuWXzsO us7hA+N9cv8bafxG5IvTmF83XGngiHrlwI3veTvLxm5+A+oqIyVdj/q8ASoY1TUwOCQozyfgCbpE oX+7jmsokKk1FcWkZJWkV4SdUrMoJNBD9TnlQtJ+0i71X1ZXMy39c3vxGvznPQBM9CXhI4oi/hlx c5D182RZuLzAj88e7gAGjuTMbqiVizVHYH+vkQImOcFdm98g1wUbB5e5pnd3qjI1oyV5EcgMDUCX SAUuOufNc8zUF5ZwlT9T3U4an+yZiFKZAGrQvwMpKZbnFexu8OGgQ1yQltuEuQ1XhRusUqq/PBvz roCkRmQoWAGKBybeOQczvGL5/obLnwML0sFCsgW5t7SCjh02pZZknrYdw2j0XL943TqfVlqT5Tkv Y+hxXgFB29B/OTAirqnU8j9RevZ8iZkzghZqeCmgPI1TC8LxCbSSP2Hl5k6KOw+0bSb3Mv+0QIjW LLoofccTzhurjkECxkEZCIPyWA93LIGWPkVx+hGQpzG5BKPmvL4IbDalNc2bdRfuSfAoNlVXRCk9 JrY0CeeCquoPVw98i0dm5mSSdL0ws/w4DmYtkkGbzd+2oHXFmPpggIvJ/wPSqpiwO7jQpYPUU+Kj uXYMtoQndjmCsyR8Roka/l0o6GQnMdPvBS3JaolNc/O6n0iy6JMtEcQUfYWjDC0aWZtYzgmgx4sP 7D7mfhxyWz+a6n7ro4oF805+PhCEy/8et3uwu6tSQZS3BlhJiE6t8ye3AOKvt1p8lJAHtbwBh3/x vkx0V485YJozQrLBPoO8rjaOcps3YnfFlGa/giNtdowyYZmoXcVxenW49GRThSc9u2ngsOGT6B6M vKu25r/UvOH4g4d9w69nayTd6U+13LZk+U6cj8TQxgQ04Mn0Pvp0J25v9kSGm9MfSW5RMT+7/gtl ITTOdLAqG4zJpBG5jLyTuayGQHPxJ0L/+GTRWAE+RDEKpoB/dFhSGyU/gItB40wdCmlpYSVPoLGW 2UcVG5NBo/c15jht+tAJtJBinrRS5BSHv6hAH66p/3mKN2W9KbI5e3tYj3AxKLBTHMnVf+rW+mRL hsLdJfPTGm/8HCM+MIuJg4sUvptvs3D9qPfYtgO3vPhyy4vfQ2/eBrWOfpw8gTmXRVknQ0ogNNES 6nqhGzj07+uVsl81ZFXcwpGjRhL+GEp2Oe5PJikyOLNLrmMYGEv/idKN549MW24xxjkWXk70vRYW WCiOLuH9LivEqDJywPcni6T513y9dyUJJsDhiJYmy+d+P5lq4E05NtyS7xKTNc29mm3QJ/VDQT8E RK2+FcWC9Kws8tDX1b3BPuGAYvxYxpVHRDTrzpTOAtUp6KSWNJM277/rrBtFlMzQ+LPEg+t6Yq+r 33gYjB4DSpsaVf/qoMyaBO8lXovputIrGTVj6qLIIzXW6g3Ex/LUITZwPlzuxnLuVU0cv/pSApRx MwkmANkFWQE1tbBdWFyghoUMyTU958psQbvOM/mOeRJTPfAn20Hpzh2+4Iar8KEZVYFpkvkEPk6D O6FKaD6ytdVN3yuB52+uFXrYgdeWKFiGGSxJt8adSvu2An23vD+Rp+FGntdLC1oCfPpi17+SPQvE wnwtuMLPrOH0KJjrqiKIlOYXXk5Aq+5xdy0i7DA0tXiaIISd/Utr15W5KEKOYKE20DfUc4aDN6NO /7OPuEBleVb88SZMw1XngqeO4GP5elarNNFQNl6DLxVKBCZCc3Z0qtWvrFAXduVLJeVmqTshG1Si ggk6xHTCYAf4b1oCka7HRcAtLq/ogruTlkQxRjD109hk8OJxnbSCCSTuSvy9wxJytqSdQePNsEnC N1Rw4tlD8ajZxVC/BsZASiRGbXavzWwaJ9Ta21ueSre7XpPq3A+Wu7X97J4/+lpDztRGcX9Kz4v+ 4M1pRFopcdFD+DrFzBuW8tx9ErrbqI3ASlgKKEKZp0OM52XU3lLklqazGx4D5rQ+7n48UKIfmutY 4+BTPwPelEEj3W/j+8nOlya6wSVNJ//3XxlwxB/cM9DdBb5cDYt2WDSFYUfo6P5pG5BvS3h5bbnM rjO255/rmRFQa413ZVo4SINJHrV9gjMry1fzCZ1L4ukvjsItXp2aYJzdVjhJ6XYbIRjtV1GuUXqV U0HFbnFAgoQAzUMccea8E4zuNfofF/HIB71wVU+xxhYSV8qMXmC0x6d4a1HFYu9PvrpDInzzGD2t 8NIxMgvKh/DG/1yAl8Gn/8esTQYEBr/+CXnrA5hyEfolVfkfFLKudYykkTfWO8ArZXnGJBdMtG5c VKqkxFyVrML1TDI1IdANfgyJBjoxWNVL92R2njLlIx1rc49djRwGRg1ltAQn2jWJGWzxo8frvcXs kE8B8/FHpC1epGRaex/djPckkg/mOVGpj6sjtvu+tGR/lIQwnKsZrdxrOpnjiQTbWvS6Ns5BATuA ruFxA6jw7oeKW0uWfOW9RTsGa6MgyxtCXr5Lrc0uhCiVbbLcv7aoKM2cz4QrSvzc70cL/H4dc7LI NH/jGZJwt0hMmVTiwaCuKVegT7sWulvFUsNDqAiBL9ncyGhmhcuwBcmGym5EmO1AjeZGyYhqQh91 Z4Xar7UaLdSuqyJL3148IKN6t9txkEJyfqWJS6Aao0xsuD5+gvCo8Wglw5mV9lbwOQC3DJF2lRFr OffVKeY9BcwufkSgz7uqIEdYqsSwI0DjaV+b+ihF09fKE5pY1GuaRXPxMYZyUFMLCgtHjKC46/XP KCpWOxK4a1tEx+mX2cRdrK4VerTS7HCEIgandoiAke6qofcNmFQkX/kyjN9eHdznnYYAuJAHMBku moDPdegwBducgZxv054dpd5W79JRGM1HVZLuOStoW7RsTrrCXejH40H2mD6UEZN6YLylmc0hljTj HaRRw93cJCG/EMrBaxPsuywRrjcEUKurByoMKJXp2q+VnKA7Cp8YWq4x87dsfi12K2TDLdlXVcz4 uc9iRvHRKZ3Jcb92dGy7vnNviCfUd5Lfj8KVRLLkJIXscmN+ImNQXjUwm1r/NTPQYHVQefnZf/mA Jde5WZtpWC1Fi03jYLxd8Hr/+8sqUmHeUURF4RqRJD8d6X7w1D17sulSqAN9P0FLSxHf0zsf9Krn InkkLalanRJkTzEw0hm9Eiq2RV9Wo3xZWmG2oIkP3ajEg5ZVmdsU324lzU1moVQ1zk2jZNPiGbLX FcMt9IG4OXDq94yw+dusbrXSVzkI/kytd5KiygTOPG5Fe1SM0sSEyvbtzs6f9GBGXBgeGgjmqAig cq9aFef8xxiP1Ylpzbyw3sPyKYB7dMauwO/YwtvVSgjeyXen3sdn1ezSnAFMN9Erh9U87zKYrx46 6HZrZjYwIfDHK5+aXveeFs9Xmua5uL0baqCgwa/N+qgAexfs017LGoSVTHWna4L1tZcD1oxBUWGr LMl5Gxp+Wgd5/TUCQuWfEsTLAz+KrQeH4j/OfoE9ciPabdHvzHDTRxeilG3Dxp8si5NGx18RDZov VC9EJBW1r1XbYWUAFYpB+uF5JthrSGl4u2Hdk1Cg3zH7sDIDRf511uBkpvVE7mugELtDSx9fIBND XJkoZqI7YcCIgZZKB7yoVYimsN/COxygzCHL88Cu6diVIzzbM8zePqAPiCi1NL0OfBZMXsSLr5En f8Le1E4Qls9bsifMIaNMo8B7WkFwGUF3l5VsJwDgcvroAYOVFseAU0qxOFlnFmNCdZu1XB1BWh/j FJ2NCW8gYCXxjvSn4KIyfiiAAGw27vJBoTRhAADos5GkzPwCq9a0Wj+JtO8pXNGTR9PO+39OUATb fRgAYJf5YaPOlu34I/7R2UkfxnyKY7IpT+1cVaLWNih2eqrH7rTJrACfi5h8TLnLFHINYwhd+13S 7vbii8X7k5MV72Zt5LxehwDbGfCmfEmIY6iCpkoN6iPZeRx6toW6KvdVsamaQd/Lv4HGUbaOVye0 IFjxI+T7G0ioPGFRv3+2nZ9JKdOAood+i9SPYcC2JnYYlHdUYsZ8ToTzYPAuM6r4HswDChKNs6Q+ eQrxizGtsa6ntiK/JHPdIqYxgCPS+p3yqVDI8FbfLlrCmVBtppi3cMW8XGUMOcwQnUt7mx/Asrc5 XRjHFBKSDQX3o3NL5ovtImD1x7J/ibNoC18+znb8Vx8SIn0mTZVvgJwkp1b1wTLNdScFXmRChHVF p+2XcGfMDcail3xZrSbfu7tOs+h9Aj2KS5wvxhTRqTJr0m0UIDW81vbBHBZbTuoSYDO4i0Xa3nwX ICFcw+tnjRyByvPvCSTa+gUscChMWTiH0+z2L0MO1g2MCmi8ajWH9T7erA0fQO/0oSUDckVP2DfX HVSs7eFacMKPMb7MkAC4uLtstsCTOClz5LNLKKqxSrPhE9jxLiAQ/Bp9tONQolAz1RVaEruCB8cQ jMX3bBXbbjNwZS2OTqromKk70C7hiOy2/NpFBlu7VTzzY8o4+q7jHV9FCReapHQqLSyF3FwLcXLp YOGd50DYPDsPF7ZF/uhvE8b1ZIEEIlrzFyEhsubN5TbIK1XoZhwKYK0yo7BNB+ew0j3Eo5WSfIdh chiZYp5//0VbaB+njHhxDtyiCuvhuYSOBcM660OLE1s30DrFA3GLtFMT9BIHWrzyDcWoKuOv+BzF HwHWV2+16kPg3N6fTB7RmLVxzr9bLPkRDPg9VaRK7M1Ma9bXz5WyLz1X6ZOnUBJeBvq7VEcg81R+ MM+/Q7xiOeATefugyEoH3Z6coGLNroPl7u62q6N986X0pXYwpw5kRx/fuNfn6tgF4XgeCHLJT5kR zoitxAXQ1wgUUslhLK6IgecMxZGgZ+8vERttuB6oMjjgXeoZLf5l/zZ6PnCUeAqbGM/nQcM7nbTf wY/ZXJOHKt1FHLkD+SEvdjOKMSmgXorT2e2zavv4eoqsYDROn9fxgkvhbGBW9vrKXKoqYeHHqP1L jHNYnZHUSGdPCSeQhwtE9wqJIwsv3FvQC6SIbJ+h2RVNFuqZf3E85F50bPB4J7vPzN0u0FkYk5i8 kVN0q+vQHeOh+OFyu9n9JSKUwnLoI2bFgE+CovgRK56pDR7rLSXeVtI5G/LN20HXyQE6BnR0cz1o 0StVE9164tyAt13tZ6+/SfRvCs+XIxqxiVf9mh0ZEarmCqFjm23gKyQJc+rC+99fDdVdO/P2NIYT 53krwnYJBqEItu7dcE4clqh+VGE3H0ginI3bJimrW98m//VD6KaiLAni3qPKAqTXW5+I1zZJraXA YyMmAxd3bjwkA0x8PvxLHsyPwdzeh40aTKIYLgXwEgrV80dM2ZejGPzhKNHTGipWvr2wwFFsmf7L 1iwxjkPodXc4hJ5Yd6CjqHyHH0OinnwoD/reiZCFqMy0JEgkT57kAv7Q2BEib2bjclfxlD+fNR+U ibgSnhw9RrgA2Fs1L5t9JqG1V0B8NCkAYJqUSbbSvHpaLxPb3i3Xr48lbQRwTUaYPIPV9RKfoKi7 h8Za+dsdRHRt85s9YOB1LjyQawXES0f8efJSZKesFhExwuLRXDc3NU/M5UdiohYaZcAUr6jQW6zf Nx2QdcQY6SIftSPODLhNpvSYMO6o3A9ChJXT4TlGQWNLylfMF6RH8wpe24vbK8zKakzqAnNdte16 KP8pjBzxK6rj7NxkifnRjyTlJayLeIjs94x7Ppr0TCfMltskxmxa4xOlbntxtk6w0Uq0AvlcXPPp xArKmveuPyCKhSnCQnmowepP8xjo5YOFGXRvv+Wzi+W2M2XSUXU571HOodzxaOE1e4m3lyFsFHI6 TjmuWnKxXiMcsSzeUMlXdxatbz5n9h8JL4CAnXL2j2kfdUzB6eFBiiOIYGumzt5lcVftDk4LdZs/ 5Nw+hfivg396VklhwurJE/EZtxlcPq+xqkLBCoa/zI1GmOfVIjBnsvFgc8cPl1kMnRCqvK4nrnHc O0J1EW8yvPuh2Uynk9sS3fee4JQZzySO56/Jxx7n72GYnIasuH6Obp0skKxGTEMZTV2Ia0k3OMxf y3HT2pR61qS5NESrUp536Ny3sty4JtUPRml/BgEkjfE4N5PHDV9Z2oaWRn2aoRZK6s34om7acdgh heq4mVMV9HaOvscC2YiZdVraqdVcgJOdEDa30iyt4lWcxEiRd+jnD4fYEAJO9/nVheIwT5QXX8RY xTuNQ4alQbLZ3ro8Z24AuM9vZGouz1YmXhUSqzVSPs8Ok9Ro8cNDadWshTwAy7IKa6SRT1dhsHlR vn5/Ii0YiQeNjgUbeMcz8g32YCnxDWyhEVzfxV/Wq8LmgfaEXz7uXMPfcuoEgKDSU1oAqcWJhigp YeO0KPlWOTlx+4FPFdQZ6hoU0nlpP2EZJ//GezGIk+V1DNeZWC4e1KuFRVTFz6ZJUf48cbBpNh4Y qIqw1H0P8JFnbx5OBRzKVxJz7M1QShJxhMSOjZlDbqnUa/gUe8l+LRfTyNy3RJfR60FXXY5C0YF0 iMxRiivMObKDXKbsJhORsFUexLBuD/TBFZnuNItAWd9vGwR9zpgKXdXGDexyGp8NDXOs6SrlUuPZ NBjNIszO677i/IFIgiFznsDCxRYY9CqOmBuT7K9yt1U3T8PWrLicubZ/wVDuwQBkwPFIq1EmTcKH GOKrW+8OAZptZM/FS2jPt+bDqPiVLWVoN1qIc4zC07K8Ues5pjw6tn1oY6Az67YO9hhKPyuM8A9H UUggzXnFpl6q1MzvyLoAvClKUEhaph8845DPozLLjEJnxp+3kTnRi8bXZAldXn9hjF6MIkvoixko L33ghqDVeg+01FUxC+MsALm7gjgS5F+r1ys04G2aJxstgUyS1Mt41DrnQWa4SgIvto8Ek7/w6KI4 4n+2Frl9fstN95As5NCzrS1OaYB7tkyAqSlbOzSAA3/sZWZCNE9dJ2rkJySpk3fd8Z8rM3TrDTMp nUzDivnXjgNAsiXUla+A6cRbm5G1R4idAKZo829gKBGsSLZ7KBUIAnudn3jC+a7VIV9VdVqfROrQ fjwiqsR7dEXVJUCwQr+r9UjnVvSwiPsJLA3ZLXaaWC4lQ1e8rgW8yp8lSjrvC9i6bIEX2R4/lv2U 0NIylSdEOZKbH7e8m3UJV4Lr9ta6+EeByq9hmIXWMEzBSPRLG45UcTnyVQY4waWSwyTlYLrsGgqR ovDJRe4aRP7Qd8lCG/8YEXU8CN6LZUDG1QcKvygS3HjhCDaIvpa9gw2DsK72QQyWFVMHx5Tx+e5l lWnwGybPi1tJcWm4V43VVL+AuLuEX4G9Bwj97qXVg5feWMTkMcjSj6pvJ7wqhB1Ipy83FUAHPUCZ GEXeAvwBTIHNqteStgdSIx3ZSsuiDGhBLF5EpMHA/iuCV/I0ZPhQoK1jB5/8Dn3obnXhIiMUoy4A Sn0kKcSahV9FPt56E+SF0ubHX3WLzSFXmb4VflcUloruFwVIQt6WAhYW8EMI043hpI7ADQvZQW6p LFqG0iV9DiLrsbkdkW+yAx5Y5bevOWIWm20TvOIT5yrrwFihkcV99aeOSBo2quY4bq6sROqmdVDd muYLagdpV1SbDX5aqvFAS6BkK+RTZmqmNEmw3I+CP8F3dErroX6OkkMDkgjrMPcSHvZm+vqNKRKg Qg/jBpEn2JAGKY0Ij88xvgPPxfXnWofzrCgaFBvgZFIiSe9tE6M70QRZ9YGqFe86+pCFckjTPiGz 4ivKAE5G4r3JW0taRzBfPtg4tKBvyK9GXl/m8lvxNJwGItiMQr6fAK6Cr7X3s/0Ou4y3pYj7Efjf VVZBYQWAnrkqSLrz0RO54WFyxVQCIcXu1Kx13GgLOH1vT6znyRYoBuNUtN2ybbKm7txhfu5dRNUG J66sgZgieUdwwikdWHok3KQw1/gL+/mlseFZuLmR/qN40ZVYpHITNkxVCm7T68cHoGujqF76xNn0 TwhvLO5iOuuXuFSdfzSOr7m7hOimL4PBP1kxpKMBWCAk8gLFQp1txHEa0htRrlWSSK6OEdveabTS d70wM+bJXLp32WBdox0xNNoG/tje6zS6sH3GThrGCRf9wh02oLDBwDLb7HnI2o6Eh6FZN2qwZCaR FIMYiOXWPUjsU12ow0gRtxUhbdTCy9ZHu7mVvTBze6Wd0s8p0ZkGKkKckhfFJz22CvPmlWv6QF4A nR2mTJhPfzXxTYhx9EXmfZxrOkVtzSG7kBpBwLqg97XS51W6BJ1rJDgvo4bRliirT/niAf4z/rOz fyJJgbvAT+JEycBoHX542Q6M0X8zpGQFnRszG/KPw30cgQ5twgWUiw7a5eDiVeNmQOwLfXxFiWde RJFABMu3VluOf+qXa9uwfxsWkhAqajHHjGSffhLoPO7RkGMA2qwvFUVOTKH3lFuQJy/TBPuJ4rSr OdjS3QA8fvP89Rzylpn1EhJsubPiTBTiXW0LXwaf13vHqAb71Bs4kV42M1+4+K9OibcR5enXjk0N VhEznTMbae34IHPPCK5PvVZyW24gGKz/wgE8w18xgnC5LcL9878aI1V1iIQ7/PBpCSJ7Bfm4GtNI PsqBFJAwWpRnVhDFh5X18bQ4xZA6BhG0TuIxuF8kkW0gXxX0QeXTPXoAwAFi6Hzp8Ff/ZvtcaLnG 4DFStg7iRJ3Jj9ioclZ67oNwixwrzcr17E7ds4z7LbO3+6Pho2vM5Lg4Fxlr/iuDgPj950tFI4ko iQYtt4m9ySgySgPv1+sr5bdS7/5UBPkdBVZS/fJkPsYY2TOUc1wcWTyWX2kQy6pFAyc6HlZXyO8R SRjT1oGiGwSc4wOM8gkDz64xjwIZcnkrgA9xQrUyPgQcZKYPosWJKKvxsjuqTp/Xpau87ryy6MT/ 605xrqfomSBNuqfRhedeTuw6NMM9vCsSW2Eovcuy+el1HlOawS0Lq5riQ4/loPE0esqmKLOye2+t gP3snJzbEq0YoylQc60MIq6PC/zE99LiitAbLzZspzUUnVX67bgo5uK/YVAX9s6B8DMSuP8pjhyE Ql04qtX8qIt3Dk3DeBWLd8jDkQUjaFMrsy253dK8I9I6Q8N3WEscplzF2tO5hhbrgyoGmypcDzUR on5NV/+tL8dTlBWBschdMwlHUYZpCobPeXeOfj9jBOEPaC6itLCswy90Zlg+qYBSYMry8vanwMjj vyjkv1B7rFTL0dEj7v9ryPwXjWu3oRMJQu6fpuuEGJdv0fdOTGzmR4EzeltTxvI9biAnAvqilT1p OINfaqjSW5oqcGa/pN7EGoKq0D7AV4D9w9tPJcqZGlWGHohrm4n19Wnm4FOw+zAQApjj4Oa0uD57 1w5XbYvJZOE8k136hCPeRzHmj+MhdfPZTMZ6DQNczgbxtJ7je7mRDlrOIagkR6bnneZi+Qtx4kmu huF/5Efe95zm0DOP8YupAKeFDAfyGrkLeq1kdAM71AIXS0c5Db0ioQgU6F4DC86JKpv9VYWwR6c7 DLw2fgbhcpDQz9OWIx+5kWlbMcFRht71JsYAs1pEI2g+vlcWMe6xgQcJwFib26Oc2ioivhHjXdwK 0kcW4mO2SQa5j2YN6Z2+D6BuNDwAYFX82VuQNeMIk1z5/AZSWkyIPtq+tmpSoMp4pfoa9ojxvyFd KbspAAxi3hS6X7g7HWL/SQu/KcEAOb/Hpt3o+gPGK2dikVPD/GfF2hQ2zkfWu0ym3CHqYGzdeiEA cxyaypETG+CErqzhD68LTqB5Qokk39tiHZS96oF4MFVP3r9o887Ayq1Vk9blOJhjAlEifdKpvEFv /Vkvx407iTILYd+D5RRDreRuyCN40iHYVGyCKH2tx0l/vYyoMKy9Lo4HpBzcD5oBvPdsvivGfuIl xDY5EfIjp6D4CUPECYNKFT6hLmbuDJl+8r+iuMqeyVR5V+kxQAO+Z8WczwJbZm8/aniOemxZwYwz UUENnIFR/5eqnjK2EBR9EtcoLZu3/DfXr8EOjU0lnyrqktyl2LqnrgiTQSTiMph9K59DCTxGJQmE b9Q+1uVoz1bFf85MDOy+8fXmTAMe44sXc/UJrhKiBclht1XtQCXGMl24dgXLkqVTaNtpRb1SI+Ic 0PnrfcO4dksgeP5l1aVCP+9G6ViysOTwV3RlouYamihw1/1uhvBCa4Y217rbGqE51ligj8FwBcvi YvE8+6ga3aXJLLWy0e1/9P1tlc9e5PJLI1iQS+DxO4wEIsXLeoy/dbrh/M1p2xqZKyF4ygzzMAAc U3cOYm10/ZNlkLk+DI+lpW+n+3iceqzXYNbYLGpulxNFJq/nj7HQdlXb17qvSNUptjpsCLWsEZki mKhtUYdt0HGA3NqP7gfWaJ4VlgNZTKrPH97Bmb6Ckt9hFfa66GcSH+5GdTW64Mar7S6hMDz37FWv 7Zs9bgVEotM3QTjfnu/QGY/Sd8kC3KTzSiyJmSUfihmb5Wv0ZGxfY6MO/ONIkn7UPZqF1gtCOoc7 dzQzgq33tQBhMfcvzGdEcu6NCLpPWwte9f3qTqVTYVPTccLtTodP0ePPVUVioLKqbkkr0bCU0ryX uZ91dncCrpIwV10zaFkHKy/z/KcDEVeNwnZtkBBlK5s37MJ7PMwO7s4iIGD28P0l/akNnloyA5Fm jYgphEMjkz466nyBhycxhEdlmL5YIaxxWL1O8xNgbycSNeGXPlzYCd399oeT2fxWOKIFiK/uNXM8 8auN2fGmI7US5DWKH4EvJgd0+eZ/8bCuF27Mcp0N6BkztvHkT9QNNCA6LW/8lNIQcUcD2biOYkNd jBKkGwiQaRua8RwhzStflsv58Bj86IJW+6U0NMK9elXI+ebR1iWWTfq1oWmP1xtCmBtm2z7CQPYK J5e7A46UclKgjoJ4qzkIvGTel9yViLmLoCbq0hZQHvFnCljKsmbQhsjr9l8nPQRqt3ysIIVmcafO /oqZw7bQH7t1Za7TFcJeqw15iGPcKCtFrXHiYmTHjvUUQzzPcmdkvpl/AdB1YYFFFjnzyR6eBt0N bEIe7jcZPMXwO9P10iC+HErpjNHDTMjLCjA5P5L8enesy0cKQvBM7F+Ls6/TRbpjheUxRVs5OnOa /eCJ/0Z09mhofbblQj/GySBb6ijlotUhAaxYTW1ZmkXpZCXbPzOio9XsNebj0fHi+UHBnjC3+Egm fvrsOBeP5P3Bc+LlFr657ThFLmFHfTCF9e96Lx8PUNeDHYVaLQVeptddA9fB5WxGmCZNoKhFxOu/ fxFJjb5vyX8RyE3aJJ7XvXfY6+ijk9tUFay0+ATQnZcDHAdBqRoVcaYeKQdGOIaE8K2heSkoRkTR Tzs8eEluWhgHWHR9oQaCwU3DhYTapep5kSWyNv3E6j4F3hprjgsJx1P8OYKopQJWhL+VtnzRBZ6g wrJCK5z33VypMfI/hRsMyLicljHo9RdUlLAXc3GFt87oyIW+r5TAj5RK16fy7fZqQAn8pn9bCecA 2hQNWsCHOPgtEvfYQVPDClvsvLYv+IbDopFpMDV4jqkKie2hn0gZW1J3/p7fp1UcPgx3bE2zcetG Tn6eQarWciNBcmkBrohfiHFPZUMiqUmt002+fDnM8vQeq+f5UjbxAx69NVSgmjJg70HQ5bzZbJF7 uMmJ5vBHV0MzXYxuhye2ICQlNBdh0O1ud5PEXZvGkkhkdpH+wAjtvcU9Uws0oc1vCQNid7cVh3O+ XXofmdrK0IjFE6UteVUraPkIeRlR4p5vU7hiXp7WjnzEgdm5t3l7rf4S/mIMsIBHzO5qsatmra+d UCZGEQjhtjhLthaXA7UW35+wzfrsvRrli6UxuG7UD1i0BwGSJN3FIiZq4erklBViKu8L6UFrUlvF EWLQ/KbwbP1GDce4aTUL8ZavqmhiFpINEz8u+KSIaCqF68rTbyd/bVVIir1DtB+VYWv+5ArhdYyT Alt1U0NpYq11UcfzeF3hRRRcPeZAUWoKy+SkTyL2CXW5T8i5Pp1ukvF+sZ9qKd76A9P8Lb8AjwXu YQAVS8VbVzf3OkSQ9FYf1oxAXUL40AFnSh7D4sSLDbIRmcLvlPmnr2TW7BSGokEKnFAp+L8/W10+ xbNvRnqFnGFCx9udMhz9L2vRwBvmCdPMJE1SIsfpaNs0/D5lUnN5B2+anf7SWEEo0e6mJ1b8tT3b XPWUFUsl1fV4LM4nGzrBT8r3L8PETh2uflscxAG+rqCZCXf/OLptc1nGqIwp0wmaSKp0BC0RHK9g IUXu35ObRNHS/gzUOgzYyxZlv42SLf3XJafJvmbo1CursBcSVoBWo1gRTO1SuY0O0R/9djTKYS7T +TcRAwe1cj1Azed3v7833SHE1AOJE5RwynsN7QCEVTqzQOz2+GPVciaPNymBkmZmQekTivhbsUVe t7oivWkH4yFgZzkHrJBob+RVWCLuvq2zxpZ3MjREvAky3MJsFb4u8hccI9L5DYcmnQkKWLwbZfOA 4WTpyjH9sCqo+H2Vj3WRGUIqlVPK5BiymcBk9yDfapewIl8KAeXb0L/lAz4m64Kcky1OhVAlBgSl bQRZez7f7B433dpiWNFwbl77Ogde5ss8Ae+eg5akmRs4tvwtjGhvbYx9DSgp/lwpkJp9JjOyvg93 7BKp0DBn8fHXxbwXIgyT2ToQnDAloRIjSBd9/GeC+nxfwoHWNNCRh9IBxpH8qiorp4QPc/U343BE fOf59cpz7m15KgNNUrey0WZGJAFMubhDqMbkx37AO+THHtkq+8AFHuhXD+aiR8RD4a9uQCw+G7D0 l+SjtoFocxYBgepE/5GgRJX8BxazR/oPdl991+OEbORuobz9fIz7ZjNhyVGTrGYuWI2CUcKws6Nv Q5GJ4LoIdyUEPXhgYdqC0Bm+Jzketi7Dpv8l1OGdJdBGn3uQckBNe2nAa6YU5gDaffgjKst+4wBE OB1i+1D8nw7T2XmeQIgnLfS3DPj7JMyvF8DmScCLGHkpK4yxf6eq1r12sAsq1JJm5/llg728hWLM t0LWlFujikEERwdnAh0ffTO1IQpwwEKH0KIqg44Un81AvLIsFZP4yVpUXCU5iPGOz8bDxk++SyIG c4zP+wsIjHSTZaZDEaJS1zcdleXpYbtfbaonYxjsMQwAR71hcfCuFKNsUJxuMxmMG1oP8bmGwjDq roRyZ3e9pqTC3AmsfXuMGU4fH7TF81Qaju/fEQNFcxDJnhAW84WZquL2u+rekyCClznWKVq4gFUj X+UJbQ+z8E34uLS3t7oknJkWubLRH2pNiDDXF9wIvb17UGyiEmIXz/HyOUUkX4tQmuzRQkoHf0Ei rNqdI0ZqawnVRbe9ij2vn7S3ZWKVrYP+gcKQav0FpgD7kJwaJJ44t9E3g/DG8rs6zXxRaPKZQFTr 2ZIFnDsfKFCEg8gv0Z1mYlEFU/LLZ6maHqtPhwRgD0jW/tmW9oKFb358KrT0W0cQ7OKuFXa+fQZo oFjP3OtBcrMZF5Pd+YaMYFd04jHoFO3oXIuaufHsjypAe1BAfIsau1U85G52QUzFO5aj4b86U6Pl ZXhGZxlnrYQpap5Tfr+yygl1tW+IQNLSTPoZQ2bypAnachiWyE8h7R8tIon4ehsHdWLXdUugt/QE lWpBRRW+wi/GL3skSA+xViRZf4DmDTyBJxxHzuNwpCZq5NgfS1FJmYVxu2ZDtDlG+Il4BvIaQ0mU uKeCwY5cZzdw2lq5BBojxy4gNn57xna0loK0Y1iTrKYbnqlQ9CjblJwIUmryZQB/+K1JgfnMKM4I DvhXp3BV6rhTu+uYZYAnQ6QAHEZR6sbj21Ha/yYwMXbRXGB8JwbfmHIOm2qczXCgTQpC6Guz+7EJ ZdidjVrR6K7O2q4FG+jz+joozokCnVGK8s6gmmFeXW3lHli+kUn7nRu+sXMqYv0kDnbH40aVmpHR tE5tJfHP7B6R/7As1CjF7ErvL7Oervqa+QQ5gX3OW2folo4A4YP5AzB4S90ujSz21uK3sO/ohhLe SCdQJmKhiZln+1IXPu5cRq1ye0WZcpoiTyn40Vf56hRyqa2JAvnueZTv3IELnyVFlud2v51SDCr5 n7iqQ9Bxv97I2HrmD73+Tl9BfEh5gzTQBoK5ztEQeYLew1QeeRyEkXdA5fERzVl+ghM1AoLat6oE wd3dwR4nj2Gria3dmIGhsXjPoq0N8L2KPCjYcXsuSWo6T97/6wp5buSaYmWqVLsTANuvkT1HAYuX y9A3aBxQN+69QTnJbI5VUJqyeq4RFtlZGcZX+MvKl3nXll9PRfHI6K3SD7Fa8On54s0EtxlJXOYU oDaLOVG0SW/eT2bQKwNVzccI3vsTPk0qwq2Gl1AWQYBgEQr3JlIhBpnUC6ZBVaopTVmOk7S2qw9I BbJacfyzgFwXxjHBx5nKA+aHA+k4+5l7FI0kBowaorMDq+MkHSMPJpjjNC++G/6FYzMmh4XZXx7E VlHW0PpOkRC8JMXtH0L+RwRTbcYlwby5q8EMQaAvHSZF99sarnvxjFlFO2El92EEHoKFXjdflfIO RxDYhZTR6W21/zijHdlWZ9ghoaArkPyNxu2cmy44sg8GOIEypIrGjbu8OxWiNGcFhuYU4rNG8jMi yAIOnZcLHz7YmldnyB5RavXcZMq9deHxmm5KtQDLqp+npRNyjQK1U7+ta6y9Mi8u6npirkKLlahT 9GQxAxDp0ozF6v6823gjk7036QG5alpFaupbY8EqoZEoK0ISNaiBxrwqQVxJw8/2sXAgnFf5dIS+ ecsL5iJ3nWf1B06y7yYajxCsREkpZqshdOIMYHRCotuC0WhLhcqmvO0yJFf1K0iepSsvjK6a+q0G aObY1bA6n4KbPsU01/Bd0NazT8GQZJ0s6RaqpntCz2ka5dH1kK2pAUMv77o1tEt8b0/B8xzum3FL K8HpL27h6QRmHKRzFaLU6PRl6DXvbCnFy7eOwEOpe57Ecv1iap4fDIiGu6vF1VC4zVq9+/Wueps3 tf5DeJlPST78RybDHmSJC6gMmLXlTquXuqZ6ty/0JZjOtIUydf/xRyDK4tF5ZaE2ECsE8m9wD9VE BqUL8JNEmDS39wgCSM/GXLm5qXzrSUBbQidFT6N+PtvLFRgtaouzuVjkSt1pet0eRVb5G8yZhPwf 8hma7uBJrzBnG2gGndzdsXP8HjrgfM0jXzJWoNip+I1OcLzoHmalgRiWvaV9x5Ie3P7kYoxwqAA/ t8N+YaBdlzT2r32E8LUjsAc1Pah0mwRU5ILKSuPhcFq+z6hASPjyp/mVz83Ou+O/WnO4wpzt10Nk JRFriwvfAbT/Z8iJpFSrV76PXM6k9cP5fAXGWTJaRSajiWt9mEP1orZ+8eXV6XC/7g/iWqi58UBf HbFjtWkoayub6jl7qH/QRYRYRP0POaIYdoDe9vNhnQOgpMG5IRG2Ahf0L3RcbURZNFWtp5G9yUs9 u2rL0u99tTWDIi5l9reOCZGXEnP//N8c/4FCmSH0Dusg4kC7iRTkWus1ktAD4mpYrFZNyjoh5dku rkGgWBdBNLpdDSqjuFyaCv03ZalFEcyTxVc6d/J7pzwFtEhh45na/kWiYoLSVL1PBs8UWcjjXAvu EeNNJkiCaOL4oa8S1T+j6Ri+K7Ro+hqc5o0QVHubrlnjN6gBX9sqOvA6nC40e4eDe/12CCHGJK1t HteFetJVWIks5XsfXy+4t3t3t93TfuozhDZdEh/P8+PYzWAvpG+n/GXi+HFSIIPFTvqv/8cO7Rri lvP8KOzgW2Mnm7y7pKED21oW76U1mlY2b391b+wlVuZHL/lacSmc/S/BArDG6PRK9J9Fmfi5ll6f rr+9w+IiszqStDjWPUE2IoKI+NxcAsP9iNzHI+J9W8Eop+shcCQP2a0h746Wj9LU4ELQq0pTnHEa k5VPJbBvoEgh5Z2z9B9aIyYGsJXmz/DrynyF9Wh7wBAJe0/7lIwhQitXSQwxMiqSuchWY6l1vhLF UUHgkcidZPjo+vjd4ATW/R2KLq5S3VMe88GuYrk43hZ1pGnkVvS10kGHYAywb+3CBPJygD6XioR3 PJxI/cG8n7uAFnqHO6XJzCESiLYX0ez5PSStVGabtfyR3JWlp80qn1u6O0a9MGROy1wXQxPAgSWf ixpgc3xK3d2rN34jYs+imuL+CulbUNMqcj6O/gV5pR8uLOcbE2XGe2oVaSyVMFLp6rlJtJKjhe0/ Y75Uh9gYr6MUbmBF0ZXD1ImGLFRJ9Up7AN7k+B9bzu4IkXEvmmDaiGsfB00/iBJ3U5ZZLxFHZZcx Q1sreI0BRx0nI6tLsBll4SJ2YPHSGLpLYJ4M0UFGBRjd7Zavmh+VWZ97a5MRt3PpLoXztP+4Rxsc 9iNf9pHwzPxUa8txkGSWaOmUYIBP9TXUHEAJbdgbm1rc/FlzxdwC9yBsbdaGQeKY9xLkmHtB6Y9m peTUSCJe/c768Im4ARsgmR0661yMeeSOvExYJ5Jn5dSS4DVkFJWdobmfoMP+navtsOEUh/feJObB 6K3sAPDvs0wTSIPt2lOCTtzQMz5YtlPxNr1BIXDSOtZ5BgSaXYsErWBG+VHFpYESdDn/KLHHGQ9B gyl9sVgU83BcOuBMNC/W2NDpSOR1YOkNmqBhXjPhCuHm4XfmocwNud7P2hZzBuNyoYZeiO++ykS7 jYfalAd3D0uQOqMTpHQ0fzyGFFUgubcFt+frS2zE+LTchDpvrfoShWFftoRFkA31tx+HqNuiJYBu 375N05An0sGwQOQRWFddyQyPKCg5+NCIQKa7DTUS2C2LHuGDd9PLPaVpchzQfuPbd7XUgUR7/AnU QXrcBsPPDG+qa3dl4eecdyqLHAnJ0+sgVn1iOE292XRN08DiEdBM3BFOXkqyWLMmN1gI+7GKb+X9 IVzeIzY+4kxdNGpp0DgYr/z45XC6pTgd+mg1x7GeatWMZeDymJT6m1GzxDv4K+fLRiYABKAKqxma z4//Iv9hN0YDQNBcLu93jCJMhmmTiril2NayY7gCTDjAMwe4XkfLOysmRjT479/3iLsffG7kxg0R `protect end_protected

gpl-2.0

80e5ab97f5b7cdea518e404bd6ff26e3

FlatTargetInk/UMD_RISC-16G5

ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/Instr_Mem1.vhd

-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2016 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file Instr_Mem1.vhd when simulating -- the core, Instr_Mem1. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY Instr_Mem1 IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END Instr_Mem1; ARCHITECTURE Instr_Mem1_a OF Instr_Mem1 IS -- synthesis translate_off COMPONENT wrapped_Instr_Mem1 PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_Instr_Mem1 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) GENERIC MAP ( c_addra_width => 5, c_addrb_width => 5, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_enable_32bit_address => 0, c_family => "spartan3", c_has_axi_id => 0, c_has_ena => 0, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file => "BlankString", c_init_file_name => "Instr_Mem1.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 32, c_read_depth_b => 32, c_read_width_a => 16, c_read_width_b => 16, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_bram_block => 0, c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 1, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 32, c_write_depth_b => 32, c_write_mode_a => "WRITE_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 16, c_write_width_b => 16, c_xdevicefamily => "spartan3e" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_Instr_Mem1 PORT MAP ( clka => clka, wea => wea, addra => addra, dina => dina, douta => douta ); -- synthesis translate_on END Instr_Mem1_a;

gpl-3.0

c49c5ac17b04451b6eecb3ee0269cf40

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/fp_convert_to_fp.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Bz3zlciYZblnk39EBC37my0eS8LMNmBgl1Pfnh6EnWM669zbYRDVCGV3oe7J4vs+nPq/9kgNdalA XEEX6QnTqQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block dSxSASbRd1uBiYWSiYNzteK4zAJBidNz7WylNlUeOI63yH0N3ud40n3jYapZAr0lREeysweVKMeY R0dNplcfMhz3tCqfmO/h/JwUK/L+Wrvdw3E1DhdnGydJqLfJh2huJL+VpyVqyyS5T5OBVmU/btyB w7+BnwfMmcKoR0aXRo4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block YO48NftWP1OZpCJkfk2Eo+epwSTPCbRvLbiG1ilYa/cJSLVf+KY/Si12UfMvz8HnfMrU4UsmRrAe 6i1YGh2rkEtqbTQ72ZRTYSet7cressh/Zz1AsU3xFqJpyi6/2TblhirJ5eB9az8eRYtmjKLtKGSy nixwDJtSh6jXdmq2uXzqyxo/Z1f6jyIR4yKyQiQZ9qWNBkRTJ6VyKGcZH01hbDyVq+rrVwgSzd16 mDZezK6TkAtmuHC7/h9E3CS7AMhJ/RQU21tduFOd9CY9teG7vbEGUAbUIsFESeckNjmJIWR7ROAq nIkBpeHP20AOYYVpKJgSja1kDKLNehC+xrybyA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Gcwes4EivyvDV61fVUQGZ68UqG3b9piIQ1m7KRBhHPFd7dKaPNC9EFiGBunqM0jG48/DwJYIZnaA i++riOu15BMp/djKxd4Sd+WZ+Z2jjbKQcqgy9ZQLskRCcuRv6a06GMskTJ6m9DhRu0KWPiyFcp/5 1EAHNOlrBuxx+8+KX6Y= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Jz+zH83bint92yYTU1pA0SA8FsSHHXhvH314t1buJwlcGI6QAgReAvFSseytq7E2IyOr1+oLVcum b1L9S5jdyLD9beQ2rMZzGcmco2Wgian8Uzu2A9Pek7VE12x11g7IG97jdDlrPoe77aijihv3tTPK UoL8fi1i0QtjKAWk2kTp+44eEa66WNP6bAEKi8YQe+C6KWSfX6EYLfQdVi7gPhyCeVuK/3Ul1cu3 /O6fnje0EvpCEwT8kaVx/chEsBO3SnvNtlxA4DDuEvtXaS7hczIshz2qMvavl/AF5IHDmUlhydpf O2qB2OVzVn5nyViElPXG04bXLq56gQwgLCbFcQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23408) `protect data_block tvO5u+IQoQ5sp7lvQLJu0eaSS7q+ByPD0UbDghPKdnRaCzxMaDvMCTSS/fQ8uNt2YUgI0FK7BWZJ /Vox/HjPTpLVx4s4+ER0tCPl448WMCotciYar5PkHi0VobX5iohUXr2nbZu1cgUjBh1jEMBc3YsY C7N0ZbJtaRNuP3CPT/QCNqHRyv4qsgRI3i5a+gfXVcnN4ZTjVgfE16amNDjAVXuvpLA7guCyXMAl CgMPIrRtYqenK/HObD5tu728L2M5bcqDt+JxFJXt968pn9kvbk9Fmz5p8dzYAUlL3Up+d4VR2581 x2G/kGrzNpl9g2CuNR1zDEiwItj6GtZj3V21m3WNm6LdXdn5TJ9HAp5iZ27Y2zgUEi3eyiB0XAhp l/Fzk8ko3vsnacnVWuq4gdJ8QVzxYJy1/QqcP1JeckRacmmmNrARiS8LGMJcLgdhSnbIP3cyISic 1k75vWjIyo6dvoGch1n8t6uoPDZRvPzz0eczCuM0al6ttgRLZw/8l9Rbsxy2vax8aFbkHXVWP9vW 5Ek2NARHxDGAA3jbHomo1MKNONH5FV+UQr1fkCi8TTz43IjRT0ID1DM5xQU1QPTvTqvyEOkBnjyd aXXPAxTu4HrZT++FCr2o65bpEKrCSx3Mi8/cMlir5qXNhkkK3Ut018agQ0aKPW2LrbVurdyy1Om9 H+1vDoAADgtSpvFaTwIyx4SYFpJsLnZ6B499zJsUKMb02jLeDfgP0uLgV0HvMVxorROnY3NRc2W4 0+upKhDAt0puYA+SbKIrRtymJqwBRw7tFd9Lt55N3iXjTMotHekOXba8XQFq87uDy6lQc/hhz0UO Mg5Anl0O/0pQoi9rhgbuELWrxx88S+l8SyjVzK1ko4OL+vV6issnycl01NHLobEHnMisXdtqaG3s hlkHe96u13Gss/BNE7VXcAqtR9kyW2MofWkNIci9vChLD1tWNRCEULuA4blwEraqE54a8C3XIjAE 8JT754NJXGCmHw7AAO4l+Z3AG86yGkpovyxaGAu7gy3uOThAnPO1p1CQNzIVFwYNDok6H7AyM1dr OqBJFOYMAhqGogMnLyqt4zjdpSJQDnh/Fu/3RzrYqtSt8nWqSPASdsz215tM3Tm6Ju0DXC2LlpRP OESfMP41n5YbtajQMGCH6uXZ7gjTjB7oGamm1W/B3AOS6M9Zum0nwvLeVim65Nsl39+lQG/OCuas cw0vcBBmKj6UHLQB85Xm36P+KLYltBp+vkMI5RLefz8TRjH5wj6ebw5TEWMRY5EOS7qc2i4JepUO ZvkRST9n+vrcmW4zTVJjGsACNO7CH99nJmvulL59hqkqO4jlMBx5TlXEu4QHA6jRTLd/NOh/Fg+3 i1ScRh6MUPUyo1TXEw4pP0n3YGNbFYIXrTcJTjo8UVb9izQ3pj9ycoaXDtrj4NabNRmbvpKIO2So bEVovl+/xxXKJXU3h8KvEc5TTHO2sEsm8Gvik3Nsk6LOE0+Y8iJg5OAx1uRuvv8w3IBeYyzSoBOI 8u4j5aIosxZLe8L9iYVkgQSHLiwWUzKWRCLyUBxe29v4dT4bJoonFXeerrTR8DwSJLpwuE9QHt8D i75WXW75dPwmpboW61LxQt0SDdtcWTid3zKl9i4PXUp0HaBYZ7jIJ679VJH+D4HO6TDt81JtBi1J 70ZbR/WChq3TTO2BVVr8bwH1v7m+/wcfQ7SCBVxsomRtPdiWr+6CTBhx9LS32eh3fnxThvNLmyZp 7xolrbwOU+ljEg6R9OGX6IhEwznrMAcr33wvtP2NtBvHtLkm0aNAXtoZDt+cGupL7VuB3dIaNp7x 7IHzsDq67BnIITHBtHZWIFtFRkWaydF/vF8D04mSDyVquj1HHU5OVvEdYrmt34zGqz1boDeWwI2+ T+mPlO0g2xmCJYxC7aTuJRlxirh6WTaQ17Q7MNuOEFvOg8SKvza03O9nV5alUmpatNxO+74B93ah BqTgeKJ9aTyiJTUfS/BytWfd7gCFTePUdBzNH2CjMUJVnAPRP+ZeeCO3dijoZUhLiosUoc+SuVcc ufMYDr33D0kQGLTyks9/rSNd0bCeVrvNnOSWxYio+B6apwf9S37O2CkLXxTblBTp8dz6E7NbEFwE tw09oq3FkxPY6nQLumRSKB66HhYEWHtfOpuIF+pnAqwVjYCPuewJk1r4zUxfESzAkKZ5e8bkDwmq eM44YQb53bEDroKLkmAv07U9gsPuLCbZ6wsSTm+IuennXon7UAi6gXJCiK4rim4lRG3fjRGoTY0t DL+iKNTIZ2F48JXx9XQdadZR8ecfbVKePP5t0owl0lcxNJEbqB0bRucd+SBQYOR9mZ0Oi5+SYo34 ETETGsyd4fS6hL8QO+x0js4U2+JDiv8P/9xDEpsL1s6/xsD0888O4fIxWySbudd3mvnwyS/+qj3H KYzJyTC9iHSmMQazaVx+f7NKS6gMZjCNn6oenWME2NumlgLk59NdCPQHB0qD7O3YboQlDyn/xFu1 K29uSpDpymoUZRwzvd9mHj0mkt+fhtoUWINPkjXM2I5rSWjRWiSit3bCyCf/eBd4R/LpirpmuJFw OS2jMfO3Rb7gRMTnwvJjaGPsGOXlh5UnGTDIzlG/Ila+nqIpSgaTyZa9GO2kBnymOsTWm73MphR8 P+4Wplv1kLv0IndJkkWlx/AmH10LxaI9uxbUMg+O7TyI4JvZu8TAisx8qrv5A3uCL665VcWuZfYt aydoT+dHO3ZPY3EA4VMJCOBwUXaSgoQYif1x9q+JbMoDBYcZI2fNBDpPhbV6zEzUenJ0Mvian9Ty nyJpju31c+JJR+nT1QKGldwPwjRmQWy60ckuXVKwdlsl+7ItdbjOnQiB6MlZQ84pXqo5nyfHjyQh lqkWjXAYlA0582sF1JT6y8nYVcG3fFQYKEv/zlHpt5xjzK/C2XwOurHSY2FgWJE81GhhgGDyBvZV Nc7JCsZPLcJi42Hq5DZdcjVtUcTSqFMx9GTlsqhFEv0glNJ4k2KQdHipkXV2WIcgbc/AgSwOVJ8x ZLE99Own6Xtz/iT5jEfUe0oso5T1zHZgL6ncT07uRaR2WxJ31Cr9DMPwhYzmg4JhD+JhTErT/mys +SFvkQzGBDbYqrkt/NkfGyblDrexj7e7CMSoe3QoiUEG7iofAH2BDgA3jhzDcswgUGwK5nFkCJ1w s8D/AeQKFKedWAQwDT6XAkDkxzGXOo1ecWzpLHKUh3QDYlgBR12ClYD3RzquYhEJTrCzEGSyq6b3 +KLxbmHAtNp9paxlsUIOVh2wyLNeltKnAAAna9XzlJQ7fn+Q2fcZGvi6upXa78NiuyHi8GgXcFIu YW0jpHuR/Fx/ZLmzpoc/NInufv9+uaJu5EQHFK1NWWUrJ6nRktPEysXvLXOT0rthr/TxMBT8yTGg jzKTc2MYfJRKysratffj2HEu8IzaF1BhFAMy1AjEz3BOrHbOFy6tQQYLC7JAYkfGgfndBnGbrem6 YsYHAv0vEurZW3LkIRzAz7ZLuzavtYei0gHiCGSThDIzb9lgF9aSJVSljHM/6pJb7eDVLkDfmVW0 JYhMAM/i34XlV0Pdr0Z82cH0lahsG1IbFbS+1mvslZ2IM6OyUO3LA767lvWPYkNhTjJZSLDN92r+ i/DwI6CrGQVQQHQ3AzwF5m5g5D3efu+4r+hfMZIgpweSFP1DKMsIIefx/TJx6gzymIAPeoQ7osjw BLMiGgBTRg20RiS16jM37GSR8AVNfDBKLf8tyZke3CTcS/k8usy/8qS9XTgN+M3Lt6MaD9YUEFKF IVVOMu0jkaFlg6pj/iKJsh6AP4Fl6pSM0L1W9ESsMRhkhyfs2n9UmWlEAozV6ulFQtByD9SXI6Hs L2vGKzrLro29/POUoYbW9z7izBY5gIwgxtuco7gbec9r3QIEcOWZG/3oxPYhvsLwLSySI7XIewSq P6cJjxf5GJ4XzWKtA2c7sejOMu+hMPp0/B/ecxqtcgTv64rlA2lfworBzEmVltV9pfHCYAab9FGg kIsVg7MslZfN1U2o2BThyxgvOPZOkBUdRDsyiAiSAVMcKM0WIQVbooNwA7a5wYW2WrdTFlX+DWx6 iQNFhdwKfn4JgAeIaaQ8CIuzyGDa/GsWJcPNbZKTIdibApH4emIRdU70QIyzJfveTG3xZ6kEXD4f AeLyGeBNpv5ZFWRu3ArfRFVMnJamJRLhhGiHA+9+DTcMDSyIb/pmw5XQeP/JIAbhE7bVy+tyw6ti elOUq72giqr+jcjryQMs8GJnu3Xnorf3IumoxNo3uh+mdMUpLBh78M2yfZBOekdMA7w9T5dNKgmE XOi9tbqO9nV8WQ0KxRJNO3AWMl+DSmmKXxRju3en7br5mAEZd6DcjOe3yAoODYlXaEA71R1kQHQb T6TTi8nRPfEHvKOe1QXYcF9SAJT8YHLKHhbV5jBEy7fdjnQiLsYdfMgBk3525VIaWWoyjBgeq0so 04DURZTH1cDH7CamznKvHGuMSca/54zyqXylgiwF0UNF08qcVZvvEDeZecd84CLjbIAr+CuOzTUc HT/VkSqJ8KYAlnmHdClNoyhNiyOhrXv1pvlynTeBPMTVEVQ2pqHWf4WZxyqbm/quCMRwTSk+ZSMN N7ghTkC1wB75TWcxXmJYt7mz4GmmV0jq5wTVSJoiEQT+khRKkZx5kWLYbl6SUTQkLGsJKaXjF/07 zhC9s7HkPLfZCZDV9E/opmxsOcmpQc+EJ+9vhKNMUlfjYlLDzrJCN43xO8rA1xvNaikrQqTBtQMk 83BO22J1j+D1eaDqkbSIXcMYTGQ2loaelJh4EDv4qWhsXhzbqLtpWIZoquR8E/c3lurlR2xHPM+K oMw1pe8LpZRY73ToTAqkYPlVwl9+q+gAosT2fPAoBNnc1V/WA5Yk8mxqUMbWCQPIiddmz/WhFSds LD2fMHr4ZdiiTvlX+CPiS0BZEvNDW8tlMuh4KKDwzbX5/gyyhB+rxquik2McmbCbsNV6VnxKOgkz VV48FJtAW006dIZ9R/LyC6OcBKcjs3/6I75oMEasE1Q3u4uA2dH2zvbusPAlsUiirasarBy941NE 3HAyiCSK0XjRo9GWw/3LqIZ30w3V7K131BzJDf6vOhYOPuTDrbCZfg7HNDYkMNJymYuL9pRXXf8+ cNbXU8qo7T1pacELdIp2DSJvoopQf5XXG6UXBN4PK3lWngi0BIsV2OubPn1U77N0+h/+QQ6erur7 FriKr0OVyGVaCvwcb31wKeVvJMDQuAkAYXuapLNY1cTUjMa0uVi7RgvBE385PVT3VfkXUl1P9KoD e+eqrl1fe2Z4Fzw/AwEyYGmTPQLCV3W088xwIBzHLduPZz+Bk0lBH+daziRO1Uh5kG8WFsUcOQnS GH1HWJs/N2FU8EnkGGkJck04+0okOPMMhuZQPzgL6LSGh53Lm0ncBWBLkppgL4bqLdkFi63QGVFy lO6OZeEisIBfHmUSSTWWEiUIqGrqYlnwkKqaKnLXoFJQes2SYO/zgbj78bVfoHcyVl9WWqvMre7+ 2eec9bebLHI06HBHF4f7NAYfv1oDWHtzrt9d2cKPaw46tnwTJ5XlDtM8hsuPGAIUWBiZ5JjQ6HuU ZNBpPAxsOhcv+PGGNkVOwCC+Y9I/F4Wiklnk4a+XryROViAD2AMg5mDF+C91hByNGpjDrE5P9F5O IEtnqFU6ZhP3bdb+oOvNf352yr50tahjVk+u/L3YZmcFH49OVDMTUbQ5ufKlg9cBW5jbMnssSRZq c3ss1LGEfPG3pLGY7KyFzxkYo1FUxpL7vBfr2onihOaE7oV0v0A+5SYNxto0OLqZZdTh6Y1mszuA lv0rGbah83KjFoJH2WA0dgtBmysLJ/rJnwHSk+1J4gvkHDRL7LRFlQ/r+BwK4vcbob8cs5T1MQcU AV/jTGK0PT6jojulf4CTv0vspTMsAnNvOUz54wo4R8voEXc6Vg/gmO+R1YbvLNODQOGysw9487WQ ZcsDZA/JSqh9soY+Odvj8SAt4WOQUy/c31tIkmWwFsqdBcOFDDMhK/AMyV9qx+scpXRv1tnZp6G9 MGJz6wBLJ8K6WbLf+YeDuInRus17uTCve8EPhQjO1liNIsvQoR0jzaJlGenOJPbsXmJIO+IRRker y+6ABa27SRtDpQGR3Dps36U5WKBxP7vH/Uidf96FqbsuOZO9/A0WCHOSY5mXppC8zBV9+fzckZtB hS+AuLdtnklLLUZoEkkt3iVf7zIEZizygzNCdLsJQ0Qx/RpZnHxKgdy0ivFnHhHFIpONZ/iV5Z2s kq7ReQ91KKSin95mqGxOUXOxybQUl98xOYEZb6Wl+9HtLUxvqBcXABIaRYqn01ZPFvU/hfINSOl6 2V7amlAazB3jHjJFpc1ChJ9ElD5Wzlfl9bV+xgsQ0ohzHNLxuwVnmJ5jPAf5uORd2kXeqWn2sAza jdjrRWvj9e9DPaFzmgds1FyQ9trRWF2uLe29m543qcW4oHseanuHmefHYe04xqOF19wGRZVvl9Qv ZhAlQPYes0jNF/uq+I3KC0+YEAPuE4KDsANYOfVP4zD8kjTE7PUvH9cyLiZ1yQw4pHP+z6yBKTbe A7MirrlvMCitoA+F4E/3qGggBMq6/EOPuCv8uNwU1cwXNlKNR49OxolFpKAkVII4OtEKAYCgLsL3 nIMjHWW49K0rIw2Ic/b+rg2ZhzWbkf9UwEjnai0cIxWXdD4fMGnUVyocOxD9h2Zdnj78GLSfLYOh JFHX18wDOC94/9i26TQIzEayYloh5ZKrTf0Tz7plzwz6K4nUW287qjulX9E6FgRMSy/+Gq1r5ElX weaam/7zPYQSdyg/jJF5Xwlhe38W4ay4mhIhQgyQIKOzjJjB+xJ6GLbXg0OlCZsVrx12VIKXThOw UQfIS993pEWeqBm4g9M4GuaSLTBqvY9tqLxkBmFGN891edpExSo5lrzYAJTUcCLb5Kx13hOSGk/+ WSY3oo833CfebNM9QfrLHHPZESYBbF1rQwoXWWqgEkXUPPFNX1psVZVCAoGUUNC0rWbu/7+XobV9 DXX3Cg5blrmvQ34TT/TewLInmwEhyKjBjQic0gUC3+OpDjjM5lIDcJI/13hTFCCXlLZPYlhDCZuo 6JiZG6oJUgxmUEZNs7CzXvhPDuhFSpqI6oey1Lt5W/RUi1JUGLOpUZCq72Yn17Azb2kmKko/A5lo 5mxN/c4t4PCKIHN9aqambjcyWHsOyUJE+XaH5+2HCzF0IKi9I4rKjtda67B7fdbvgLXCCYl0Wah3 8dg1Bjr88noyN0yDXApbQP7KQbKHeSAn2VAcWlZElRmeqILCIh0U+R12XZrdM69Ro0EXrMJLdXlz oFX8K7jpvMmoeOhavNARtkZcBbnbx28WEdwaNcFkl6ceMWdRBl2hjmTQAgSx4Gy/XMw62vJ70Q+6 Od9JYcvdsFaKm8odGID0CJMeByY2BwSRIYWPqRSM18ChN8eFdIcEYM1bjuxdpe61vf8DJryfyYTP Eux2XQ1UIPBEJPJ7ByWtwja5vdTumIu/OdhVHPatpljnQuSbRBfs3Dl2Dfuq7i0yhABGXtnD9tBC huhpo8apXFbBFCu83GqVhvRVMZ1/R5aDk6Jc+g61/bt5JIj9SkGWsHgWeiDu9khGQztWJ3nfbPjb p32HsPqnLVsa6nHjVvjzIpkvvZDOd0ZKgpFlSJdqDkiz5z9tpeBYtp85mpAMlV/Akn12WMA5odU3 zoG2RqZpKYc9RWXn1sVpMFAANH2JytjFPuhZUY/hxAcTQbrHwMhfzNGDxI308gGDy/sfobYYzWgv gKkQ4uVOCtlJjvdEwfc6XlaUlTPh+R4k8xmkcY5utD6vbLyqS94U9AHiYRTJ+4RSMCSV3NNSx6bB EROwAd/UR4yguv7fbTmMOoZZ8ERJCuqZvMmdgIkEAYC6WextP8gKA9ovx7/+61rLGfbTi5rL0sjK YHS38L3ccR2ZTlUtXDp2tHSebeUGhfGSSTcXMxypqoesCvJoxOxC0bSoME62Gk/cPzjwGS0QzyUZ ieK0rTcrmS8u/qAp8Nv9fiC8Jz4TQrfRf89jhkR+6iN2q+4rd6+wGsMMfKxW8gQ6ycXYeDSzPOIe RZbxwG8w8jzoR7ig4PJaRwRFC2rHH+cIMBVDTYmu+ZzGSRILPqqMhTVvrFI4zz1yBpCZx3IGCzd2 YFpZvV40DRcBVKPlfOCkOHMhBJ5ZvnXX+De62MzquVIMJwzoNZDYYE+3zev1Dlv5V3qEcC8FgkRw sA9vw1hGicZJrbb2rwVrhhuVXRr82+N+0r+PErOXSk/8TyZnUOlb2Y9bj0XaNaDAaSltnGA/Gt55 6reCt3Y3wO/g5moJ9d1EHVaCWymQrSJeNK3BnzDmH7Dm0l9WxURm8NfHkLuh/Fj8fwomoBG/Mk/F J13DMFhfoqxu4AOTyAyHoih8vlYX84GfKHizuMoFFMyJP3w++lB3bWlgLQcYVGyVuAVPSAM/qc24 rowYJUpSwkpk/1kcHv0ykhLwQeuRbBpu2F54cnkuUElw+z+R3fMTxfZwEzTgnmkdEbwvRlhdvADg /swvKGOIn6gpxFUQ5eAf2N6rxTK3p8EGQij8PK5RlR4zkrl08+r3Q0eqkUT8rdenW7QQWR3zI7/Q fwWdD3t3V/tB90xLsRS6Vlnsor4g8vbV37mFoX87QHFOwr+hOtFLJa18LJbQ2vgheOkLT4Ob9+jv 6tzw6SQ3Xki4uK+tIEYajyq9q1kjd2KsYYr4lM4GpW2IFdUtoFW0wjd7RLisV6JcInj+gSe634AB oVjkuLz4/KCdbrylQ6h5Dz5VozYfi7vAtiZHqwGZ+cB1sGXsSgk4NIhWn5mnzSdW8YOmSQ5/PaDN mx2SWLdzA1XoB+tAcpD5j9nwReAS5X5TZ0ipNNvIqr+zk7wj9axq+JkLoW9RJuZk6SNj8ylgaxqs 0ULIYAJoPQ3BiHURcZxcuph4swbhkqtbKsepwYxd/riMlmeOylOHrOQdlk5OUyq74ziQ3oy7bd3Q L5Y/XWlaW5XzicotfTXOV0S/DeJam14EabRxcZfDNdThrDmDeWzvw8F8e6nA1nOKbZxkqe9tJEIP c3QF2WR5jyzCMTgue1NAJmgkqWajI/NU4bImKlWhIWar1SAGCziRVLwCx/TP0GI+Kmyh81c+9DxH NPP09NJcktkFW3ARhUFueSSBgkNfW2xPqlUr1htag2l+li9GCEhcsTnGO7wKAjpeWWXZs89h/qmQ EsQnwbLtWYDlFByskDTgJlTfw4p8w1u56hDCezsm0VBjvT/bR5Yj44oGOkwE65sdteKcHjUeaOO6 2d4E2PlkQnisWhoBjDVTuu8JO8VMhRWUtdJ5RWhd81qJ40ZOF0HKhEQO3B1VexKv6dFUxjriTXHf o3Kr8Tq21t2MNeuNqRT2g26PtQYr/rem3KxI92K+xdIo0/0WN7y4i/BTHYmDbxZk5LKi/N+Nvqia NAs/o+Cm8sM77AGDfEJjcA5ECRYz8Gw0jUhrO6SaSB8Nu04pYvHkFkhRwMD2la2FiXxhY642yFil C+L66RrjoRpGaoOWpIdkDVKI/oI71xTLmX9tdwYTyNyzmnAXeITClj+Gr4kqZ0aEwx/QACH9kUR6 jmWGDUMFTIM162LqYExplxsTJcrjcZzyiaJQksrd/Q+mGJKDoyZhHJ9tgjk0KznYTQacr/slD905 54gWTftFQLBfCmamUkYLKYX9vMohV3u5MQv0EWS+sRFtQxVPrUZsg8jk8cfoEw5cdRoS9Pdnh3ke SHpWH0cI8m7SqE0erSYjReY3edLBFvoBNkFFH7DIWceDR4YJe9g7Eruaa+UPyUDgvQjcfuXu8PVz qPdH1vC3RN65O/zzQF33DHzOzONXRpxvzGSLHU60aiiUwilnsU0ErVV454sKUhTAzsuAhHxrr7JB j/WWYKoq3s4OBX8lY3JqQqbOWuNUxklf1kFEmP7VRcCsoA5/nwriR890S/nzdBnj5Mo6fXHoSp8n +/5zRf+HG4a3NOcqpe7/Yf5NrcmP2gov36s8psmxWFc3om8vT1lf05BUsOui4Tl+7R/V/NYBx3L7 /ploLwufmXFPMpp2du94uJdPBO14GmeTHqUYSGylplwdxOynrHjWn5RLGKiexB3y41Lk4SwrwuAw /FpZoR1Z7Fj2hA2o+huWmUdt9wVswkKE/SDZAastCE5m1hwQTb0H/m7ukZxGkuvumcpMe2LcpH5S vkAnUwlfc93eYGlC0fbOAvwJPysCjVy4FSU6QEWDEMCfNZEzldLAdDZBVDDVXLay7h3xfG2Pl/fr 3XcPVLbJTSfjPnsTzUMmjxxM49fvgPfdhCkBZWNkpOvbOxFNUVUrlY8wDmzLbPR1YL/1JYKq7kl4 0jxwvqux+YHHii4IR60KGr5NYH4SusFWHzhcEf++85xjsAcawX7/9Yn0Inb9+g6F2GBQ0EuLVYig y2fCy2EgXHIit2TS3Kd7M4vNFCjDUm8Gvm9CJBo8Iy06JFiQaELJfd8ix2vHNdXB7yxJ6ULDwsMR Dy1lg6+Qy5mu1tdQHmaCZMNvf1vECMNJZiXq3rdNJNbyHjE8ABEd6PW4KkjuKuHnmGPZuPkO4xeb NA5qlY0I4B28c7sjW/CaqJDjjjew30CXcVmM8cbLH1y9SKhWvvRcEncrUOTgJ4r3kL8ZKeEiqf85 TW4y4r67sLp1Hka8XQO6ECrlfYdDJ6cM/MjnzS4t7vrw3CFrCa90geiRh2qu06v742iAKTXnFWNL CF7zJolHffhvg1IgESp7bC5xXUwDSRzooxcqtpEfEIFEVAXtWmyUInALyLeI8SpU77Q7cTFE+Tp7 aD7u8u1mJYnvk8+jeySQf3EeXIhhJUsTjyQRX4d/JQ9fA0MLTxSXtP5GFgTwg76MUP3ikQkyBVu0 u8+BzMBHW0Ej1g+xjA8VnLFoleAiaKgJuQaoOauBzvI64FnvRAA7MElCOfXscowyAuZcZl2Q4KK7 HvHaSdb71rl8g/2sDU2ZN61QLpohhfuJj4QaDDfba53PIuOMfK6zT0LVOpmWjytJRaIXhcYYMcFX lSR4i9BlugTuvqzmTfNkyWkBQvjs9QFSjp3VWXhohU2eA5h2FXei03HLOldY5xBCJxunp6/wWl9e /jop5MrTMUSrGdMxQbKvdEEVGtBdBerdjNqBzHzNG4D0ma/oiq1t+eOqRKX5fR12u997NVGZ0Qco bmPYmWwEpcDdXpYkQ1bpj+Bkdh9Xz5l6szTwCEGMJSSrRO3ljw6TlAHIH1kG31eBppU19UKWG4Qu 1od2akTA/Jhi68SXHsVXw1cpcQHDWIO04+X/K8aIMqug6vUJlOuZnKpAr20aQjIhQJstrR54YbVP pkO6ZGiyjJ0Uf53iq62CyrwDKqlJKqos2kO9z0nPpAaQWT+PlRi96As8yXRNDzjRS1chsDQxp/AF We6+jn3bbrfZzBrAnfrqpa+2ern+hAq336n1b5GF6yjnJgoK8ZzeO45NhI/eayhOuOzCeUeM/OCR 3QAsHRxpD7olL2XPGfCj5oqXq11+GMHsjkIt2EaIWtTEOHW/z/PwD20zYwsoAa5MnPg40RmYAqMO RuQ9lxosfw9O8yRYlqI8lndmp/g8jOPDgPuqyiSKIstCX/Fdtual5ePSR0oFlQ7/1hsWB9ZbVMOv LX0qbrBtA/lSgfj/dquTOEDV0/0kM6wM0kTKbonDcVHkmuksxikqMH+ZiC9vO/bakp72rr1yQxUu dhhs6azFJ3nV5q6/2KvaRBUHvRm5EMPAFrTm/90i/pnga1ZTSttIID1oy7UdCsMK//QoMRWKzbp4 aI8nib5mG+DQCGsB5hgn3TBLlMx1fo/FnGjc8u2lr5oMVAOxveddYMSL13D+phTgYjZwiWyszfMj R5tFXYvyNKejPkrYS2g56TRNIQ0ACiFgQ9xxRkDeId/oKFOcZ6lzMCtd0u9MUpWz576uggUy76pK CJLz7qHayE5qFWULJEe/E6mdqzVjw87yU1cu6PZ+IKuV7y7miM0ewqqiJw5SOD2NQCZpR12lAbkU MuDvRJOJEXX9t5TKX5WfcN9IMpXgKx/5tDwcptktDvGqsvSiZXxfNUwZqovi4jB6c1MWxtF+1VyJ EsgIQkbfBGaYtIpUclm1BjkzdOnhvyMNHH97KDdh5EI8Hc5EGz2f9mEaH0rRyHmKeRBEgia5soG+ AH5217Vy9fI7oljuoiMmnACa3zru88tFRu/rDRqAQpkQP3DAP9wy5tmyM5njClcqynLRXfkTOVa+ 19bsaeB4nZd4hx+9gx4qDzhGWNG4PxFudib07tVVT8AYj94aJzlHmVbMmoikOLRqu6un2orgiJaF ewvnqZY4FhanjJw2ZnZWRskQHK7zvgwwRQDFDScTbPSkHKfwh0V4CEiE1cDyUByVnxN1rTc4N3Qu YPm+i8rpZ2oUGWjZFjFMJdZ+xvspwhBd2n3ZRKtXbZE6s6imk48x2Z8wTDK3WQmIZ1lCj3mfPPXD jid8XP8XW+guj5u3RlK2ovbUx6j//q+dlPBWF4atCTj/54jyYXW/Dpa9IsRmcXrxw9d3+l7tiJg1 +ZD1YyeoUh0bcTHBJtXfqYMxiQQ8+zgG0PKsD3nbgULRl3gE9w8eqN+hUuEVQhdjjmCKTaQRE7aa NLBG9QS5/hsB/cvPCyiQMizf8YPQcLtSlh6e6B+B1OOIAjWBBiFuEZrRo3GIj0pDNeYrhhlmlTSd +4q4DYJLF4GuAkLqveyVvRMbcKUFd5L02DaXPS6/SmgPF/WAwWdLdfidQcIvvqr8AS6TkVT6kJ9d v9snWSwTLsGObVwV2BjO9TgnVIaGwqacfGynAAIckgUacEEWTAg/6CTCpBIskPy9Rq54x3/F1ePL lseUS9v4eWxc/3DM8RclYl4VX8D1GO2TnrTsERtJfrUNCcPHf1lCdzw+nFUAs8MFgMyKkoPL77e+ twsb4tVdKSJMFzXaPvpGAwQE/l5QEEKttxXWKui3r27mDFmBJBCc8KzGzJ/OZy894UHPCFS7Stlg B+Jvi6R0ZUJfHI0d2PGd6/jcZIpbAu7lqgCsz5hFfZNhGypfH2uefnT2gU6vBpCiuHgCeYEDM23S Vhcdr5zNu+BmG0QdYmZHSdYTdntQJFHj4qLEVH8f5Q0C/OVpbB4dE2vDV8U3GoeG8yA0uGKdBWyH Tg/l1ULi3XztHu4ydj/pLbAinXfqvTSRFaiSPqej3hCWXjA8/hWWsCKvrK1Yq5abiZFS3wOYT1QQ VZTwluGOOLU6oQRdmeew9KuZEg/xeHE6GZ9EKqj0IhBQCvnxIu/UGASRdwI8Ctb/ozYHl4N6PdhB aBm61TcVICMoYcJW3ojrfMEQz36s8ITCIe5BbqRuBxuQNRZ27VFWmRDisWh0G0URkTMox16D5jg4 F/MgovX1HO0kjyOAHWhfsiYbMTQyvFvoUNPB4jfavfg8YSasX+gNFphKRUSgR5W65UL3QHjJIkkY Y7f+ccyvjugwcZGjPQOoKPBu0O2KCkZKN11Hio2PgSOgxG+EWpjDGFadMgcBPAqZfJhchm8hfdFT VbMaS80A9Zbw9o7e/1j6QY+FTRVr9L7R0ETCFVHAxrBzcY2Gb5BShMyOeabjK7BbUGh6hZ+WnPpW aOux1omrh2W3Cb1Igszbrsuuj4eWZkONIVHfIX3hgiMbwypwaMs46SHuoueDRWoCMJJzZT35mzQ1 +tSPKkq8A+0duAqZR68Um6CKi5ZavhlzVzB9LmVnMiO0z3/Wy2m68CY1kHtF9oABg4NeWAdQiKeM UJVvVfHYZvxD75B7+ABuXom15jfkgbWgq/CJoEpzPc4EeY5sKKhn6Vxd6HYPQt7XhpSbDOqG7/NF VCREPOfwJgJ+tcRK4VNuXwsbQa5GrItJj3DMXYXhymuCoffMuxbyVUgfH3ruo3IPO1XQK173cpoP f6Wlb9Lz38hmaE7P+vJ6LoUe+ouEdIjIfdU4AC1yKxYvT+fvemw16nL2m2TAmTRV3ai3Jyfk1oO4 VRIN9Oq0BLx0/thMnK0q/OsDoZ0Pu9plV9nLhmmkZdll6Cod4wqUFVf8I7E3MaAuSG73G+23uAh9 kNWaFo2D8zjtOLWs+I+QokBua+qfQxGkhQAJSG/w5UBWs8f10ednkWfIOT/asrz+JF0y2rVeHLtU cJYhPbWKPLMBy6gK3DgG8lTG85L9auuD9RqfLt5QNKjB4jgntZFnlS+XMuBbW9yfVrklHT6ARmQx Zofnvx3cGRD8Kat5+dpf91Cuo3Je6UsyhitjpnCQTl4YN7nON20BKcov7vo5Urfb2m+wEbX0UGgb DXsld6HKQryuBBbjvGSdHtZMOl3hlL6i7apQ3I2W/T2OcU5n7hal6mI7IGmq1WHN5YTDRqr8tFxD wotnrnwQfLo7ZM5N8K1Jssh9TkJT/lJnTJh09Wcneg0lAGGJy/0GF1xt5tFB3FxooW5lln7P4EpT 4pXkHQuM10PYjk5yygM4gbaMC5iNXPUxDxdluUOYOsgcp6mkr6gkeOQ/qVGx36wsoTB7WSeWOLaw bmWbWeqpNBoX2+ZDxHJ1DNglmTBs2g+eTOSAzuXYetaZkmreEVtc91nP85JnIylYl2/yAZdWLjhW u78MhiGDiE77CBG4f5yA3gLc1S0I0+b3Fqr5oqc02kguVuMBzGZoWWkwXAQKeM1gdVh2pnIxztMe xPlyVuTLIr9dO16+bj4FpYRFgD1+P2X/iON78geChjcB2AHDbwDaI2WA0L0LCRkH+Bv2hENPrQD4 VT61Swjc1fa8TihPOxWC/oYbcOavFLPXRJx7lodhhwHARx6FMNzqRDKuAuzxH+pdcLiRAyetWYq2 dktEFUx16TDJYalibYfGjD04mp4ucVX8cfZfgK+QqBLZAsmdqFR2/voLaeXAgWc0XQ5kcyvRhE9O EBp601THQopYHzVGGgRmBrJnclpOAMLcACTclkJHTqkVrPGdfr3cmkyLYZacIUGOqN6Mo9yHQ04v IFdAvszdH3jipHxfZ2S+h4EYBgKpxT82LO1UXmJxBdRPhTMWeR0HRpafssBHA/lX/H/8Y1NffaqB HbhdeOdfx/4mg8W3AL5sxp53gIPy1fAgA8D30RWhw/eIFfXWsC1QpMZpDsoOsg8om0LojIzXvSot hFnTbld4bbja30nfiEYuTiLWIc/V8yrGSFm15e4me7TGT1i2Fd5xfVe7NIYWqmwMETQ2gzyGj4AZ b/sQIJTmjGKMzwkOljkUPjqFqH4ndk2erkQiIby1KqPPSmZE/qTKyHYJ6sFc72l0Aa6t9ztVqt9C BmLdXraxCuvgZ4EkqiwTNHT7VUroBEDtvi10zR52EYmokwZpGn80aiiYEXBVFc4BzQFD92KfWJAx 5hy9NmA0Gl9qbDDWEB/snQ4YaRv8Z8cov/cDpyfAUdIhRpVnY9taXIxS5hfgjxoFglrjkb/bUfjK 6rYYtvb9daFQPj0o7MLN/aXMDNZPaAcO6hjntCLwM0vtWH0XZsUh60T3NT6j6V8J/2ril+wTfgsi FQBIXFyu7ZuCNYdKJo1U9JXUcFNn0t8tMbaQ+v0CXTumP878rc6vPq2Lgho/idQ0YGQ2RtS6AL5M nljcdh/YHpgSvDW4E8dV2rnykEM2ed0oktq5B5yKHRFgupKNubpTpvvejojZoyqU7bat4ZgiaGgB mngUOPdhcjxTZ6YNQSgEkrotVNuQ80oZGiy3XdgmvAuZmuFvbkUH0m+wmvodThMqvZ9etrXHY8R1 x8KhHXaj3ywbF4CnsWZFmThIhZQGkHzJZLwO0VSEHlkRLr66kbmf4Z93AILGBbX7CEAf12I11Zpu 1Jum6QtxI7hCfYfn+9XO5Xvgr22iywXVSbZAdmcyr7DzrDJ8aw3ukW1k6ysHIu2O7HlchIAqVKYf X+BN9n28ezNl6sWuTF5Cy5MS4ojLxp6+NBUAAnp5ITxP7ewHC4m53a7DYucT19gmPOtFxClx1GbG hJj+Ac2tgPP9coKeOF/rr0tqccbM8QW9SAzCXKl6D+vcB9IOe9AfJyDgDn+D7mtbh8/1Dtw4KdhF jRc0R7D5ry5G/XR7kv9mDUgF6BR4eTHyv0A7YAmArAtdKmLmFYIzWCws6pWcrv8miT98bTMBDjtJ in1NA77I6rMppN1EH9pJ4ktVrLgVQWt9G37LfZmvmTOASELzN/D5QG4k01tZ/e8w24gaLxr7YlGs f3iWoSzbUzpiKeMyAwm49el2cSTmzKoTpU/AWOAqVKLf+LNraDb59s08Lzd+RL2dw9H7lhWJOlhY jUQiOApr1d1iYYqACPajk2WQ0wNQbvNWmmIvLTmL6PAYkwsn1I68+mBp5k/k+fF8hYibpbj8dFro DTjrhdFkoQS9MIGCmzRN5Tys7ZDoiWa/0XICEJx2zCr8n8zsEib/qrx3ls65oJNww8ShzAafjwco O1i1UP17zUhIL4yc8XlkXxFcFpY1zdud9aNeIVXakZwg6H2HK0F74+QJpMoR43txcIgqkuwoQnSg 9a5wzvqfV1DfJsaHaQ7Iwh9nXcuAmwN67IYsCs2/qRX3X8iVrmfr3nN/VPKyuJFWcuI7vZiClt+V wpsowElxxCi1bU8x8tpNJoa0l29ubbsaYSfx4rqVnjFH0i3VWEOmqhTUS5InQeeRtYeiZcftWn88 0n0cxIHU5KeG/Baomo825cPuBChctdIAez291SIdIpCc9hOX3LvWCWSE9LnlZ6EX+As48lXAKU9I h3fskQccVbjQ/aCrfTb75+14lBVmgssNyynkYQg02dWhjwv4xptUG1J8DyM6CamCPkPcD/Kyhq2A 99UcJHKlBl3NfcOTHCFn/TrI3hmdoibE3EODswZSeeKxVelNbLViKyZT2nwk9WlkCIkkaBUlH3xJ NeVm0UVSSAHpa7paKMb/Axzu8UjE2Mo4Mw8JkcuswugCLegB1nWaV2HNgUZmFrhCrR/qBurkCYVH KjOMiOrVWn4eiFomAbGj8xUup7KzK2VfNOF9VOH23Vt3DghCH6ECoNyo4egGXISLdtixOwgJo+Cy ThFrQFsmhVsDzKl6b4uWI2+zt7QK+3Ih1SouoBBVpXHAhGvuq869YZ9sZWAAb/6F8qQhn6qpaPc+ Hx+UGyZ7/qKe2BTUsScHb+PQPO1KpVzxR0lpJ0g6m15Rm2RC1cCEmUh//0H9PMFUalvzcjNwHr19 ckX4+Z6A9J1hey91jBLX6NPDC0HR+ZxfHaWjmphnb3LOfIPHjyqj5s9m14plQkOkVfHOJrXcKd0J R7Wy6u5CunGke7A6MsdLlxQ/wyfQICB4cmfdxGcYTtXSSBCGF4fpWipzmh0O88BJYCXyXJ+PHA3I m1pkjLUe0lNHm19PxnAWVzXV13Eo4TI5Jzj3Erqwx8SIlPrOquG8/g0W6gRGFq1gCvoC8vzXbex0 YRHywstltVyIsV2G3TAwmnxC2PycCJNlfzY5hDV1l4Fl7NgU+XXzx72F71X11Q/YMTuVoLaqO/mn M2cnfX8z7wIOY8ln/dKT5PtsklqvBNvit279SoHk0Gd0kKC5jMCXAthuMEUugcn+wTXvEHcvLy+h kfldtd3e3xAdJ2YQMtJyJO1Orh7/3XnR4h4o6k8I5edkNEWxEGfs99ZOjuBo3S6qYbbq8Swpgp4D NyylFnRTWfas/KqX3hyelvTSCP8QGePfCEzrAwIjg/L2wvD+Xkq3lJaws5tNOqNIqKESkVj6+F7W v09ZzrwcCuTLidZuKrwlFirewuTU7daLC6qVfdfXnhps0Hkt4eKf/GR6hCoG3vFHcKL7dRKTNppI fAE9LACpuPyIl8VvYGXPHLulMHrS1LzFd8G4ISdb4QYo3BCouGB3IciEuRxh3OwGK6lgTgLVknEv n3abTqK+CPnxqae9iNEnyUfdLwr0YeuChcbI3uC1LfVN4RB1iRkr/GPComKm0icDZIte+8e3hdOt Dt5E/uQJt1HNzhRB0CiWPomMrHtTa//2kmN38QMmpY3J2ceq2BAM2lw348WxhRsqpxIz9liqhS3Q eCwXWYa4BPNxjLKYTYk7tSwla6kFVNhfwnWjiTXhtrgB3h2cGkfCm2Gji4pQ18vGwOwy5yGAWVYK z5P4ZUEYPMiB2CvMb/LM117u3z4umsRIeiUjcFXeLwEnDTiKi7a+eVBbFNw4auibJh1/MSKPWb81 pdAXTq9yvOVfZJPCAmZ4W9PxnOh3/UmlLyzA0RGJWrxwKQFtZV8oMYpHkxOwKUneudkB0wHuIWGI Bf/RVHn1e1iweVQNkHvMitdeGQNrxHEPCD7IBNNo9uDY1mxCvAq5nyqw6Wn5L/A9vT86R2Aq4QCJ cARUJJp19OsjTIpgD4DTLELv/x3HEonA/bb5uStiPZl1VNl+sY1mZRrxxNgUapaD6bzFY2sFiu+m sJMm5cSQpo4FlAjFcxx/Ez0+W9vH0zb8GcXTuTGg4KqTDvKGAPqrBTuehUSxvaOO39Ji6usvO8BW p1aHBsIPepEz8bC93vWPwSt6QPRxaNuCLbjzWyMpI1GoTVNFyK8R+6qsq0Nwal/usAHDN8zE0o8m uBY284Olp5AcGvlc7N0Mzc5ngdh5eDtoO8rA5Y0fUqi30kMaBjEhFwkXKC9SXyCsYuPOh3/C2q46 uQSB5JiXyBUkwZL+x44JHzT/uQVIYgN1vrg4dNfvUA7/MEvU/syj0hoEfCmxvM/4y7hNxbfpRkeI pH99FgU1jF6Ur2Pi13bu0K059cCCf/DLecmV/SDUTr86AIQAfCIxD4jJfiSpJPandKigm8NJxgc9 9XOYxLXnwJyqaurFMiMjuqEJKmwhHGA7UajyCbMsuomwIJ3y9cCXXtJet8N7kGtf89zlsLwLRqDu oTFOKu3Tg/7pYY5cpr2/GST9J4jkMITqkksXlglBf5OYYJvNs0LbpJLJRXIPbOMhxE4U/aKG5NIt 2UmzP6HJDYdvsCOoZwCLPAUyfu+XxJNKbSQRDX+hRn6eRDY6iG9bofwS8AVcYs9jyB9LIpRvsjCb lno4mf7sH+FpF4QSYRuaYLZ3JqDGQMh8x/o9p4sw/idL0OXFVRkkhDYyTzeparjoCqSNx+wxTscA ygX0hZ578h5C6bJf941i9D0PXxTJd2kFtEqHamtNgqCZQpsL8s6gYVgS5ASS00eE/twHKFZl3pY8 YNTVnRHJmtcd/39zMO6Af+DFWWonWRSQEUoP4oOLsHlXnEv4aGLtyqEQcmCbCKzB7/Eg6NsF61qQ nt+wKoS8DpaFw+jLFwDtgCFEnW2J3piQGgWd/JI8f8CzORJi39PAg2M968Atuv6g9LiT8KRu6X5K 5u9pul9ZeVCcA7nsyJjBOD/R1Z6o9/mHzZWV3OavA0yyjS50y5u5OEYp+wY7QtdYIADL58cjHNbV qrE30MZkaNvgCwLuQkb3OVm2LeotENqX+xTAl8iO8+nco9AUfOMK1KIOJNzwDhdW8OgVUeUA9Zf/ KeZulUXw7OAcrvUEH70g1l9Mp08fC6IW7b5Qt9RQNWZpDRU0fbwNhPvKvaLqJETG4TfLlzVBU3ib 0DIdKzPQdP7FvtoWQw2PY0gUL5n1MdhfdL8bBuOm+2lvBB7E2LMgscdAisPaFYpNY5miD6/Em/8G Tq1OqfyYrVv55d9O3QuQhrxNaTnBz8gzjQLyqjrjxddRMXYAzrK86+hm2KKEmrQZ7Q9NFs/udkmv poRgSG63OIhBQ4orfaZ7laK1iJSJ/3lkGMsa8C49OI5ZWDcchT8RW9pBazgwOErVFbOTOwtgDcaB nHk/1LCsJr/o7I3Vx384eVfdzp/vPI1rsx0naL7RRiiqa4+bR+4B2XF0RTerE76fk9AZ64ubz4sz gDYrf0WhLl9GhQoYbJD4Fe1fRyZsSgrL+5OfpAJJR43xxeq9fRCHdLmswr6HjkfVA2h/5aMnd5gZ namd1h/e1BwL99jzuInV0YjsgwO5SKsU0Zy5bSvBOcusEj4TImtAtwNz0XVB/6A6Ash+s6zVkSc0 SC41GbWu8y0A5bXpYZitw19GTToElI7MWcyTboPVG2G+CXWNBjyn0y+WtxWlsi1oC5mcmhS9x7QR gXSsFMh8M7SevyRYejSz/rb2ytPWrI/+GxyZPkrCEdYbwd9LQf47UVVKMfO25lRMlnwnzFddsB7c meKcn4ygm/wtPczjin1S5cHujrhJQPjM+Y1/lgNMh4rwoufjTt+Wp0uNB+ulzJ5T7BkLPwGHTJAf egkRPh9QJLS+jGBi3hcH4LKB+mTRYD+TU9v8FBTkvKuyvLjWIG3lhlwBCa/Fg0lyC5i9zRA7tBOd Y1EFhpfCbu83gEDJYp6DxEWwAXfAQxtin2+D2YFV/YCPL/gLumz9HUEvjrEYk1hp3q6QCyRZmpcl bAXmn5S00sj0LbreoBEGDqwcl4knry8j+tWmD7o1baWT2gI06aqhMmJhoTO6pacjMJDufde1tirM 1/4iM45hflkpNPOMTDWGFXgCnfkcjUuYog3cq7MMw4+dqh6/kJrcyzaLREMHKSCvmvNpqOSPWDmr R3MFHUCXweDbB6jtOBb7K1HwNS+JxuA7HVDIfzTBfLpQDmuSQwy6J5e9/t/iQ4fG6PxsH9Oklf3c WDi/klWwXOTVHJyUpApjN/iAH7ro3eInsPX12JPoMKUKEUqQcvwO686Bnjsv1Aaqqm66RugV05qv l0YlU0Gahp81Y6n5v7MJpqy11sZAWlFRxxUXAZNibl965FbqLp9krH1F8G4EapiS17uuKlO4Ero3 CUSOmiYStkaFOYwrnrnkwb3vxEkZppBpqDUBqdNFX9/SiXd8XqnavCurmL4/6ad4siI/Xhu4VN/p IChtzPD/0YH405nbkKlQSHSW5vIdhCQELqLBRrtAW4Gn0wn7vL0YEG8/kSLcDL/jmp0QWMpiPHcw C7T8Y987HjE/WADUCei+GoMhLL0J/DqciTuFcosOiMHk6xrsIAsmnFKyzgHbW0IXJNAgAaCKqRU/ sL7xObfw50jLhzDxUBKJ6o3YS1QnQeMZ2douz02qtUHxx3lcgN1DpLHRIEfaVoaE6Hot7oKblLUy 4IU1jy5VGazZ9hMF6c7Zh+alcOrVO6aDzxzZ3OapasKI7qooOxGDGMFo15UW5XbzJxTLpr/3CJnm M/S6pjhLIdnG1eJ+5GSGWrmVnt4Yn7yyESb46IZxI8AkOMQb+CAGkgcMSqje9wyqUuHSycTzce8p +bMM/lxBaNyE7bhBK08P7PuMw14txaej8zYBw84xyswxv0keX3lpqqtqAjP+IgowiNGVBKWykyRk qsxTEj9XbBDLaFGXPJk+3W8DHLhCKQz1/ujMXP4RMwhMRUsUrBgxuQjyPxfjyW6fy+jRAiXCYhlt 4YYhvQeWnXn6Ckek7GW++qsvlr07x17h4+RKOo8NapSYhqGwAM6EE5dfu6zqTMzRhXOdUlIspsyA TzxhLT+PedFad6cpc/SVbsIajPDne/5QxTmhc0S/YX6t29x50hssNvrmZDlZZiRT4Bmu5UJaeiZX rVMeRmDa38Q4W8JQI86uOdar8eUq4wqEaBGgbou0fXEiMZ/b3vlegY0boTw7SnHGxLAiaJxRXP08 uV3NN+fUwL0dLY0G56nk0hzCuV8vH8TsEPg8U/8s2s014y3WZsy4vEgq2zoGCF7AeKcs7bh/Cocs HfenB34nZOb+Q7XAHFErda9Onc4Ig/u3VgglpGRuYmszHKiecGmgpDGZgfrCGVZuy4esCjz2Qi4h JoUyCyBSoZx9wolZbx+DTrJxKbmjNQ3Tz9M27/mpjTkY5eKNVRpeYRZsW6KMID0N14t+PJr8T6V+ rGzOSaMAuKrFXAYrP51qWRQHj/4ZmSsqnZFgbtu7Y2Jir7vFTqyA983UIZJTof152p2gCGWWN2ld PJzoCAEwUwyTrRJ0G40BKKcBvkih0rEXV+tnAtWbS7q2dXz7TSVnWeKa34wUFgCdFxjyKfMhdAAi cmJgP5a9Vul0gGG40vOR1Axrv8C4zvGw8mfJ4fDaxUN7bK4m3D+O8MGexcALkA38LImwuwMEoPzC /MT6RnoXbrFHrcwRuMNqcewL6Y+1DiGrVJTgwxoqWYF0IKtenIkHPnv6qhjagsiKrPbuij7hDWll MyWJCxpjaDY0+Nuhfem+R2TbxD0jtQ33oO7/97feulI7bzo4DRfLlumz4zKLbFUk3nKbIcF82Eem zPiRrdWirJMQNdslUgdyOp1IC9U9E0wHc4E+twR8D5d0ralHj+vUn7N+r7CMWI5Q7sqeys72nZN9 mF6N6BVuTIX0pTC4H++kgoiDP317boPdC2aPfiTbLx+O8o+Zol1wbwNchjX+YGVd5DE00nJ1bxQV Dz0wRKrDLj8tsdBh/3ckeNUF7PauZs2QCTvjgNbETHBAIk1aAB8wnevdDcgcGVl0isfwXFZFxWTY ThlYBqr86OVtd+Nl0/7frqOcGuVur6XWSukAZQS0OaCtgGV0/Um6Yi/i90sTKF6NhNfS0cTr808t MTI5zaCvqISij8rXnkwHxGJIjybjp4Gzog7vccJVZEDrYcwjthbes0OTYb9AX2z6ZJn5Pc//vIng GA8zt2lQe+9ZaH7MzUEXJaPxgg3YH6bKG5uL7FZWuDFhZlsuMfeTnsFhbFLQuZINEYndYcb6mW7t 2c5vtEIfj86nWNsdEv2SZc1JDeoDKFaqvKsS2bC7A0QsNgkmNdr6d58WrAauxr87RlN0oSk5G4xv 0vrIirEyVLPAgNm2Zfh2vlCrEtn23tkfXTA4rEOhUeUBjudZC78f5F/rKKmMAB0PMG2d7lCuDSBb 2CeaxtsaUzDBdHzXyIUE+PXY92H4DLkaYMFj92/S+PuTeLEo5N9KLAvMPJJEh483T4iBh76qvu3k 7QnmLifjH/4PPtqtUQIn5HBiDDcO+Fl8m2qRNXAv+i/vng5eieOXBxx363DT3H9H6CggZk99oaQ5 YisDQWtdtZAkN05Aq0Amkp0aNTx/13114eLtwQ/vGnCXLZH1adFBxVC/qNJkTeuRTyTr5qO+ok5g kxku6r+VLEFbKDT76q8nq0qhy2CWY3Ib7Rlcw+jqn6lfUKNu+BCh8UJaO3XxxbApoPyt1c/JskUr 4cqHPeXRAIibPPcPCOag/rhFh4A3AYQ1stQMv8UbmVVzPwGyZq+7QsAvjaat1GXZd/6RXKdpy9xt QDBtu1UN/WIBA2BgJKhUveYoZO/y4JKfBw3189zN+ro7Lu5K20FMTmYcSEey/n4bJKmMkGYCGKVb pIh4a6J1QaJaAGsa5ogIUfjzl3gMCFzpFNVV/SJuEqAPuBBaSrq5iU3QeiaXBfl/gMDi6sEyyOfj jDDLlKncwHu8ox4d1mr12KZJsb6EipNMRTtkp6vaPOxqPe9VZ7G2cQ9oU2zRDpXbTxSwh0LZuGzI ja5p1ts1f/mTa0ssrbEmubjuigibigoAtmfvNXBGDieLuRYepFzkej1OGl+Y0u3GGp5i1tI3nR8R yFD+YvOQP8ZgLzmQNC9efsQRTvudBK1+O3tBatej0rRQg5jB4xhinGZNllz77cDl0nEkQla3r/Ci 42spJdOBREZR/cvJmaAS3C6QhoOFXVYGp/DUTIDxz1SHZBE8f2w47N5rGtVN+f/PNs7e7UvN62h9 CI+9HvqtLOgxm3OwJPRDPYnx5mio82MHgsm+F4xKwVYjRAzRyBkeIBVNip9RWFT5ISnT2E5eRrk8 PoDzDIhxfYtNFyJXW8aAC7GM0tdSsRL6YmdzelyHwVbYXZQsb2YqjtEWjPkMCnlFEoAjgztKFUsA ELSeV+fivKGjRGpT9ms8TJB6EPhcK2SsLIVpWw6iGvj+ZpWoohW+//b7WK7NC/eG9akhl2UCulHC EyTwUvW00tV2hMqOFHZpxP6oz727EOGKT7fr/cg+Aiz979Gp0313sDcC7PcdsFS2X7wHzk7mS+N2 kStoi469ljD5DWjkF6vtVjszugmN03sA/kdo9gBut3U1KeSMMYwe1MvoxUNNiP1l1S8puqyVYIpr vT6OF3u+CjGgDjUqL+65nlfz4RAwIMgLUB+XrjNrS/XDyDmwT+TKzvqfV/4iIV2HISkDTIZmOECX 3BcoatRaMwQKRawNctOs7EHyj0ZMlMgl/vK3azlXxuKQNeUtdOdY72mYISmFNzojHRmw7nI7jAjG uobRM52mjZYBtIRJIUYVt5muZajzuOmsSXZKKN60zHqSVYWjiHa2VxE4CvEA2H+xORcP1TmzAo4W v8rqD3YlX4F4XyB75A/Rhm3eOMLsEuvHEznitaaOliTwGEC1E84xvU0kGEiroEPZrdKbTbZnOpOu kQ6A7XP9u0W5L3bXMAaJ8cFX0Qi3lcoDMuDH9Dm3UotSqnWd/3YcWawsiUulsuAeELPi+irJOwde D1zz2X6gtYSZmNOaWSAyYmOVT/daAdbaUMN26ZLwRVWOMm0altsKIrimSBKDIww66DLR/pbBi8Zk PAi9Q2hrcoRNdqe1ccHybbQGGo3vVt7xAHxP1IquG8js0VCOt0bYxQrN778FjT3h2HtA4bj4VXOf oVPIwg947x2uQsTvtuBV/HXdXpP/p5C5Fx0wsAsq5XoO4eKbzJxRaIBsVgN+2mbEuQ5LPtzPeAry TtNTBE818USuoT5sseqK5jRMbkwQ6pcX3mXBnrzYaimE/SiPsaIBsAjyW81R+lBnJXio2Lm3vUVV BEAX19wDrI3BoVtPZk3DQBYrNcTu7mms2Fq7UhKzxmYxAPdW9u2tjR1Ypb16r+rtUxElo37ixTV3 7QZqRsl6ghwAtdy9oTO3YqHCgY2DA1zxHhSXpXVw5gXU4Y78xAMXnkz/XxFbAxvDMdDuRbEZpHQP z6r7oHKxI1K3hITXV7eOK/bqkA3Mk/sJMLD15p74isvIBcko85xNniu8Pc2BI3bcNACZoZX/hqua yM5h46V7WTNIzbx2q2CPE38+Wx5YV94c7rs5iuQ6s63xGYFgvYBT0QEmFw7sMhKDPYbDzloI5q6w EIC8m0i7vUs+sKu3cmh1RPNJ4Vu/9H78KIPqOxLDMLlc5c96lsh44RMSWyTZY7Dmv9Jd808vFNkh v4YQ00BOx7FCsZ2z6sbP8S39/zD3BNN0E0aGCE+b/VRrO1uMC4MGJb3iIQxv2IFaSwZBn6tITf6D R0ldMGI95aloolTOEvmIhkri5ljiSTGTH1SCLl3sA/4Qnp1BSgjjFlqEAzHrNMX65YCnVbmcLaWO DjynnPs2VpNUniQT00OQE9bLPgPTay9b/34CHdZF9lr5h4w1gFjdAXsuuhtlPnumVKTiPs9GBRyg Kv0CI2DDSfapXc+rFJMyiBpfLpUTJjlcoPXIXCvuA9zgx1XxBIujVx4sgxNZiHAmHsc9DJKj84Ks JP5ITPWrF2FTijUeLmo9miRedLH+awLTDfSi01LDdHu/JNPBu2fAbHGAJbQ6rI96WpuAvEK4yLyg 3hMqNQ/MTDw32pHX2PqTzyJsjntY8SOcHyJDy32H4Sadw4XbFDI0uhLxd6fYJQMgRozpSPyuJIGi Kvzooe0PopeZitF5J1gUOg6USCBiU0HxdsBDLBZkIRCsNLXrQd9Alb8eK+1UX6/7hFQQt1GD6E6E L1FGbKrqDxsVbtIEXASfxSLZh0WKzxG6QL9gJi08potaLx5QCXkMtoMd28TcLcf50DMiZ4kJH5TB 4sHgxvU0uQuAxkSAiww5osItgCg13kKWDcdoqaifNJ3juxfZdPH7AOYc/wypCyib89j+g15af25h xAUOQ5xo49rPUuCHNluN9JabCUkTo30SdJh8ZWzVOnJyN+zKcdPVq8jbaknifMbF+q0fcu+3Ni1a hTJ5RYQYbGHqiNyk4twbHh1pmb9naiUzeKr9w4hXOTfUvjD8nL9kDYZ5SC9M8mif6jNh5t/QcGkR mpKSt5SqBKDUZyNARS8iNKADZrPKayHhq8Rt8o/ZEOESo2ZDVAMhapIEa4RHraeS5ACT8p8bqSFz 66OksKD+D2S5o+dSz43aWtIwnzr7r+rPuE3SXQyTkU+cOGhLRhjRx9/Ll/UwFaLjRcgDddCS2Brr s3PMncX2nU+/kZKpCtY/PnBehshKTZ1W+3SGJ94I6h187AGe5ldagC0ka9RIeVCK1M/KO6ntSP+v aWhK0JfRUM7tspUSqSUdWdA7k273ei/eff945zBhievBXb0oBDrgErlzom3/eyEkx/BognDdf15D uGp8TpD4USqAAhuI9SxUgfFGzJ6oqEt1MZqd6fkAVHyJzETYsfmb71IB3mAQtLekYxXG8wZleAG8 lbPePdle4G/vDt84hd//KgOIZvxxD16wR5ky9/h3EPtT3ZMhQ4gmiGqb4oD6a0MWcnCwRKf/qHXU AP0bWh7DyJ00nIFdK2y6JRQ+Grz2Hr4qpQR5ZM2f0ZQYZql8FJ4/hBinMzd6Jz7A99vFaze0VDgP 90o/G+i72oOlOr1iEmtSr2rQPfMs36HDSbYjnsBfrou0fPDxDTLToc6rLzC36UFVFeOpWzrjJbmT JNFh37Ywgla+riB0p+Re1XCtoUXoSCvN6arCPzvqPQt7q0UmYZQY7RJQlBvXd3/154WWXRWEN+XY iRLa4nygxEiHJrE98of/CC5KZX9a957TTENczP9QEDHI/P33vM14ROwpDpfTxb2xfPnTIyczhkqM TcAZXUZNYQzZ1kMWXB/BNuT6ChiUE/CdJAAMEOXM+CGMiKoMPh5A8LSaa4gaAVbSrE8sJEfJvSO4 wmZvCeZZJxVCaUUvs8LXa/NEPlEGYxxW/55a4Lvi8ajSYk6JUye+Wy7/IVcDsqe7R2QNDv3boqaM OJg0CeOjNgYGlVhTxS9sZETRcmllCUwvyTP9Md8PBbpNjiqKoFosYurDEgS36qs9RtCXAXVg6oCv LChlfyaKs0fxpnOn0SxH7UICtx+8bz98pTR7OPQhF3bHwEgcUmpqmsD/nsxBan7GUOAn0nf4iAUb dj6SVGUYh2RL7NJKevy0LaAvKbl1xjbmeybzmJlGUYL0T6S7YEJ6kb7SzVE9glO/bfztDYDtt8YL wUkBlaBT7DoAh1ksB4IecfPJM5kIAHCH42zPTZ4DLD4f73aOpwgyg4g9WUw72Os/lS+L6AWRXLDz +K4fHfGHsm91GY7OM16B3lVt4tS/MlmQd6R8CKJ9ptCAIvs/WHdMoPE4w8AqNfvBqzPkWOW43z9f 6kbRE8CwhEzIMslb0Cd8qQrcJUS9OI0v0xMHsq7gGc9k2is9jwMZMN0ON9i0xG3xjoFcrqEM2kIE 8Gtd3w7jO6eRdn1iLF53yXHVLWi9Oqj/XkWVukqOOx7J0STv8BVmGYIF7aoBr7eccnYZjlkXNgXy XHgOijp9+qziTCSKWc29vOibJBRKgyUPQXD6Stsp9JfZEe6FHzTaZmdg0/mqvCSbTUit27spywjy nubMs+Hqk7APZoGK2qqpEB/t21z79q+93/cqmgZU0o0CTpC4LrXmJQxRw9vrW3ZuhkfZ3LvhuepV s4QiwDVnQ4/R6HVUabUY7NS5jqXJhLO95wMQZrbR/MHaSFW+X0qDg0F3yzfDlGu2kHHVLBubuO14 XoXhsWCof4M6WrfPhqp4v+R9EZHMx7AIromC7DiZb1d5H50N78KholhTBINV4gvHQvwYXCjsGskb ePppkrJeOITA7vFdHyD0DcHm+Xwz6VpIi91ZewRmZUTFv7R3wDOguVuSYUsN9icz7LcFdbUNbSXP +xGLSDBr+tV0uwDTPO6SuJ0L1S9sN6MoI9p9DIharqcMCI2z9K/EWoZUKkqpj1XXHQrnmm8qqOhO t5ddTrD+nxZRB85AOFjn5DAIHEpgbXSEEyD7gSio1iTG0w26XF5R+0eRj2YJAEyEEIhYcDKgGhyF koh/I1qWoBLQyzT5g/8Rf3B4Zxtu/zIIIp9ocYcvVsW4TJjrj9OJpq4U/8axB+LEU2TdZuvjNXda 0CL+iY2BHd8auQJ9WH1me+M65Opc7oOkiYrFWoS9JFMqjqRomOwl9xq6WAln2HvZAKDYAWV/5Usy R/5hhVbdlw0uSqyZO+wVVsAnFo4tVvEgqVeCvsusfUUILWhUZth3vz9uEtZNE/c4fobfMf7qZxxI twM2TBf5H2iaDKNDNX+nqqRRJ34PbVkaPCTakucqgIzhmFFIyJKw1TNKfb3IAahhc3LiLc3ha42a fcPDPNiVxOh/Yv5i6BPbdow96ixMwuWm4MtjUarE5gF+OcKYybcdjPPdZu0UhE8783bnaOkNxO8M dAazpyOIUViM6Du/Yb2AuGSKyjg8NO4gkPlCM/gIllX9/SJ2OTkuKiobomRcFQrnQw5q0Bs+nQ8I e1el3yxrQeW3pbEF16XecLjQm3B0/MBkOGWA858X6aUnLfEFeKUuIVH7Zry1hsRrspZpgMQk0NCN HfO3YJ6Ln0wQ8XXRwMpL0R+QzWVMvmxLyeBoECrKIhnPwZL+kggvmZI/A+uWVVc4FTBNVydcYANI CJVPGco8gAfhI2fRA+7hMVjSQFf5EwNeJq1h0GdhDs3EkTM2HzE0xvqr0o9wK5R2GGEb8ojJ2nOK PTzQpu06kB9VwzX6ECdrFU14NqcjR4eT7iCN/GUZtiN9C80diyVpJG1wkY9GxHzhLgUiP7nTwBh5 s0szhsmfceee5Z5vNWKkx+UsWs7HoK874zP8b3PhOPifHlsncDfl7/jpVpF6DD0J+/m/0DNjNnPT VNyjA6uEexCTTJYjIxdGzz4FBj7Try9FWn4zoLSMgM+i46V7nB183anf6m/+e2h34gKuB8A03+Qb 4SH18NPmOj3RbV0L5Pec+LoF/shT54ZDOUK/rfNu/hRsRGA2hGMRRHXvq9Z15WwKPJ8szV4VQmku gmd5H5+VPYppfNIqOtNvmLr+QTzX7QfJPPaVrPePaTSeCNuT79HbXugfLHCYFob6+JNYKGmWyFq7 P1hlow/YNFfM0HuFVFHjMlz+1VNIiq9vTYrZNQKQu7Mn7v84a8Gv6JUIcZlcEOwukNcqKyQubr8x pg5sWoxpO0/01zVRS63vvm6rjsL8GbBu66klgVh+/6rmKnvNyiXoyl108HIaynS9cAfzjS4iIp3H xRcZ41ChTz4bNb5YZvZvYLANCE2AcjKRRo4ClleMrmCc/+ydwTnvA8hXGDD5w7xxYFNkIQKr85si fJ36iV7SRkiTrIESLA3WW4UhMvFTdsExGB3YdiOtBJTVPA77vy/Li1+X2qihYv2dwnlDtsJASuOS wiEs4THB54bBnHCg6uxi2dXi9b2atiSjLhnCtiCKKpWvMfFqm0PcxnBQulzFi3Dda1maEVjunVQJ Mk8yn8KG7C7sBpFLyW3qSAgybXVulSmOe4vPJS20n7oq1C5KzKrnYuACjA+Lk383SILnMJ/0q1Tv R2prIGBlbzpbL/9A2gjrl87Kdz0SCyZxZRBScAnGWlBHWWYHR2aJ5Ti4DYRyf3XHq2SAsQHVEeKn P3vhOj36L1OQI9+mDD1F23mlcMZKXAHRxT7NhczMssCthcQSrsusQB0pDyHiYG4ibfe/ZQbYyBNC M4SdVPOSv0I+fz4dAXQJa10/nu3/4j7JhZdMWc28q72RY35yXiASTDnqPEOis4eahMghOwVhPXZw rzsteomMcWDdEvAuKDMH3/hmu3CwDQRkGYDd8RuzRPaFCN1WHgpljp7stXGAKUEK1JwDM6+v3nnd 60aXMUxqQBaEebs72X2OwfxDOEwIPv8FrF98XFp2UvmbHucT9CkN4LIHooyoLwpvN5YF0PsZYFTs S/DQtugJrA3gUH0atlHt01Q8pH0oSBz5HDxs1zuAAFO5i7bpU3qNwbaxQ/gv7EOp0uFFtJ1iKX9Y g3Zxsu4sBgs4Fk++s1AklbSaXf+reNZPrv8JMjUU8Gasotviza3DCJZW5AVzHwlSwIuighux9BIn vFkfD31NFfjre/3/h5gxeonX2pDexaje7l88l6iAw9WAsDl3weK/vpI5VtZ18PaOV8btfnJTxoOh sbKQqDDoNSREVkN2avc7/ZL+fdS56LZSrOrwLm+SWab11Qk8YV4Y8fTuMHdLEEFKPb1CbDeDkG0/ IkpjJ0JmWt3s3IHNAYzjBN7dcuKXQxZvpqSbLEGL2egyMwRuZRmj8ylP3I6zj4CSE0nhwC0qq8N2 YeZDCuHtr4nYDg5VvTBiK7UOMO/oWxjBy3ghN/3CCAlTno2jLinlUatt0akvmWWn2qsT+FgdbOGK qHuj3v8PeD4nVlByFFXW3iIR/1kBi4ocPWjn4PsvmP24jCCYihFJw7+XqAoAlZC/RrvrpUKNnGzI 5EOInRwwoMiQhBqh2ZZbdmOmm6rWge60hP38DEam70uZMLYI667ZdXL13X7Kv9wr2xhL9GQZmlqt Jo4Az2gg+YiglXBeGVtbfI9DeY1/4nbDhzY2ZQadldlxuzFln3D+Uf+Dprfzo0zZVc6rpEw7O3xT q5IR4vGDkIqkUM6lnjL5N1SRPQIKIhnPZNIL76jRwOeRvANvRjD4JsOtva5C/YkphVIOR3B76dA9 XqNCJaJDcle8Wt9JW0sl/5/P3iFxcUZ8kraj7IB+D3ZnEe2/KIeRnHqlY6DeUWwicZA2pDpKeZyp dwpLWJczmWlHJBKAufW5j9SUWYvWlmhxNaNbLWVWkyqjqvzpnDMgHGtJR2gBdTZbdIitMAHsz8w2 OKUCaeN/p6pMNvRqwNxbs9ilzZZ/w/dcU9Vbxt9ZgUIp9GvMMKdiGCC8mCBUhtOrrn1aPqO0h3zK AqFVdsP7kzo0RASN5MH3cSTHeanFbfeOIpx2KT2Cfe/ZRgzyRyydf2w2ifAvUIFy9eTkH1GIkaU9 8/zrA7Z2oSqDKT6v2WkaWmMxYIjLEQwAPBf7oM7QDlVZqhjBLvf0i+h0FO7M+2egs4rJCfxsi8EJ 0aXM1BeumCeTF2JaAxaKhWj7+UGnk7F2mib7bNoc/j54f6tGomON3PnV8Kh1oVV1Ahw4RU5+q2aL GaO8wh1XbI9M75z2mzeMCEI8fc1CaV7JApobFG9JzzifVXFl6Xxss7ptEZ1uAu2SYAyvO/9eRs96 7Mvb53YbDK/H7xj87zq2IrJsEjFA6OEHHC2MMDnKR+yexiDH78M= `protect end_protected

gpl-2.0

7221564564418bbff97734d07fd84cf8

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/xfft_v9_0/hdl/equ_rtl.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block HN5uF/iyN8CjX7wyAoLSx6KMAXPVHpjEg0qN2yVYw6s3q1K9ZpEHPIjyNkuZ9j91Hb1viiaQQgkb MmHBunDIYg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XxC9XYz3JpDgXH/N5OY5eLn01tGx60tnuFnz0TKf+F1dcLS6ZYtyhtMc2LCDWAeMYouxgyKcXFRf svgSSd9QXehKBk6JpMYdrZ3DA2npX3TWfqaTq8seNXO+KAU5cTJgfcMJWR+y+i1iw//l6o8U0MMQ mw2S2yi2PW+l1p7dK50= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block BQgX4KxawYd1oMkod3CFP85bfi8vSUlEfOGbBMSEuByfx86N84Nvis8+4Uv+6L4fEhUIoR+s0eUW imPkZoZRigY+ldlghlCN2dPvKwvIdLjEK0PxiSp0CYfR49KFm4gTb3mtQCKnJ4L6Q66XQW0hDfSB M8Lf2wk+D3hO6CXasyZobf1bNqCEbE1ktwPuvxJAmUgy+hcxleODrjgGldBlT30xMRK8qPHfKwwx 3OA8YDU9+miXDwHmcRgClfgz1/U5LkEMpF4RSp0xUKNkaDkb5+NCVsLtYgLX/3JJQQCo82eJ+70X ETOg7fICNeJPUsHYPnpoekpPq1WeQp7geHbwLw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hUo8wGF1EaKmDHEucjW1MNcnESsmLqHveiammZ9quKNu5tDjZtVt2SYgdFNmkyat5zz6lQqcJgFK 5Hpt98NzLdo8rRxL0Y+jXWeF9uqX3tnLWPRIq0T/tb9bcLccu3CJbNKvrGyktNF4onB8cS56oSIn DPN20AeBEpbJgOY8hm0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block pUjVQSDhze322EXkHoD/Lsea2gz3Io0eoSjVqLZT/Ly1+IADS9mNz6ekyMXHEWWqkc8stwEDhPaY qXCBLPv8BTaKoXAlXs3j/QwC+4ZvEslTks15Ur77ZHNP6KSnGPZj8CKxSjUawvq/jSOLU9yrF++P lNHzJPzjh3Jqbw9FCkYN1rQfVPC9dJIbAnLPDNCxy/4R1HWkvWrl9s2TlbHUcPixeaDR0zEoJAQh BIpdMN8o5vz95UBGcxwP9OUcP99zC1Xuk2wqH3hwGY9CvOWomHJHZjqlMBpRxakdUlLxib533NfT D5qZHHRVutqRAD75HQRoMKl/+5U7dTK6MV8taA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9120) `protect data_block XY/k3vgyKrwS3l+5zHr8vC7O6CDKctnes86cua2eFNCK3boUThKUvIeeD7sb+96cJ3SdCbgw+L0z 2GpWR9tIulfdg3E64N17CkwXGUP74otQhKBn7fJcNSF1DUYZn1eC9MNyCK3emyP6eZTKKFGzqxO/ uHE2ZHIBPeXCeGapaKe0R7KKOJeZMOoFNwwA1w960pT5quTZAe9btO3fiksn70MXPoBxWEXAPoLy 9AfFh0AGOVfx1UZHjM3tkfzOk9H84vY33DOwk2ZVYiZqbJVUTqXuxpsQRNJ2appdsIugP6Q25qWG 3vai10zuXWkij+wXOKNN32tQgKY19svKGZ2kFuEJ7GOpgMi30Advv21ZVOFuChUdmtX4Ljvp83YS 5cHF3vLTM/OgIMk0D10LeqgVYaw2X98Z82mKaKeHvOCuVOJS8D+8eNqxhsVBIQFEOq64nQaAdra2 2eXq4IW4kp1yW1PbatWrfweyg5TSk3KVJPILP83PCwqY3gSkv5Cd5IhQRJss/tMLmK2E7dCes1cO dk1JcP2s6oKeokYrgGxGqwP8SHjb7/ObnVJMtrg+XYykafk3p3UC1dhptkLKSwVErmxx2mu5VJ31 WkqMaa3mrH3loLSO7lIvTy3w9ucA1WmMW/LxtcgJdMsDvheRGufglR0tHLDxbyMPK8rOHo3YgFB7 XtGDZ6UTSFnsFY4NaVu9uUg1LSg6RGJ3vKn2Rw0VqUu+08RmoC9FhnQ3ryhwYIa6QuEQWe3zljCL zafGLswkAaAa7rR1m4avqKnCUP1NvlDAkeuSNptPIDL4Wh5y9YfeKdOOOQYp0fpH9k9KkqDrSIuL iME0+KiCT2HQfhzUFUSTX89gVVXtU58/nJHrVa4EMGwJPooBDkgb9HJ2IWT5Mb2Uv/YFdApyonz7 Cf7qRSe6n26gvgarzJyn0njNwCbfY3EbWa83+Dz4MCRxDSGdayf9TxKly8jd8JGTrQ1Ub9ZO2VTR zml0IdhePSFqdIriwH396TZHIAJqTS3M5Mlc2g8ExYSF3Zkd6o32INt0Efuys2+AvHBUIav3DM8z NADn/dDiHxipuCjbVQsSyD/FO6dxgPUDQ12YKbu75iFu0phxUsvqveWxoGaiGqQHNbdchfd74NmR YJYjqOtt+TUeihfIhwu4IvWBkvIp/HB3bnax4IB9S09A5TN1anhwNY74s2xfqlGJctj1h3R75PBG nWmBoJfliSnbONq0akZlYH06AY8WFxuyjMqDUGCKdpCwk3nnHiIQgEMe9nhfW4Wth3Bjvmo1MyQz lkddx4Br+TbBLWyYbu3hFy+vhW9/pDNuiXwaIdLBvmB6vgS67+oujnb9vv7YAeYzREPEN5paygO6 qeDieLHM6BplIr/dMKekQ4fQMRMuaNbX7NZKskhbeiOac8jFKqQTmhOv3YOIfEz1z/Op1DvdxPj4 mPSM22j4tT02gRaQXt4AYhGeTv7SKCudv3hYuc4EvISFxFnBWu3YdwxEpVLO2kiiEhNZ2ntoOmvP chj4LBaAc/Hayn+eZPaFQKWxlRFmamKFFCGFEkVN2ckILWuQimbkvae8FwlCxQID397O6Ons6Dwb 7mHqGlqhmKVQWe0SZqQFPQ861NirNfZ3u7giVSrd6WMrxqo6Bvk1koeGl1z9hQ2Koe3eltZuSbet TMQ/YG0PfFmbKT87PtkyQMctrwe7l/wDoTWVSoYcwh5HxE2yBbnV78F7ztaU40Ft90uYIiRcYUSf Dr4SzeC968o2JpBTSjPznouUQckTzj+/ifGXIOZZdgbglvsVRQard1EmxDn+u6K0MEYB7jEMVnmM oTeb2GJvNvJ+jiPQEn1FSCWwV7+kpIJs4mDLpCCcCxrqKRToAtUsfviH2z5SwbQsP9ZZJxyQY8na vFgnjliSckzuxk8Y/HQ4wrtCH2XnyImBRtvHKpa1fOYHx6vxaBCRtipT8UmtR6U4O4+7l+D3PjB9 T5AqwaOIMMPc5G++3um+V6mnwS9WyyewAdQszZxmTO48Ajph5JZW5c4rMeSBhMRUsMi4TZMfGmnN F9JSfPkqvtpyVcOmZNnFgSqBXYt/htRS43iEESe/yPiwnDXXfTAS24n6H+EUqy/y+EC0K+0Zaynm jqgAxEwFAMGRn065ILWPUXMIaC5RgFlPWL/EXb2krz40ZGqBaGWIDx2M/vyk2Y8IWf/PooNOgeSv tkoY4DoosO4WzAIN6rLIeWOg3jW2Q7688hTqavSQt+G63UmoWCgXdkgLyJXeYmfjlU+BZSaBAHsR 2pJtYtgdRvn20kWcp8005DAHHmsEzZtYJLZu89KhTUv/Fw3rpTYdmPU32U5Ybfl+aQhSEQfPfbOA XKq8RmKDk9Sf7pMZaTZuuEPuRgJsLBc97pfOeQGo+2o2PTji33PhtXv1ZlQ/i1AaIrnagM6szhsp RTWhOSrzpHxwmUMrgoQ97WpybaLPFAF2LM3PuediCpTOCyuTr+NEpb+Sll2B6ZXQ9ftRFGZ1PiNH cmOZmuDLVkAeErBtwNaMXX6cXtkmBQNYeJciMFqCfIg+/gFXVjCqjqLLndKIhCRehgkyXqjHuGGd UGJ0zfQjYykmB+yq5P9GOdvCGOwtapY0wjqSh5mFYcyTpk6bp+LEXQXWeQIQmS0YCRFYG+35Stqw djPfelU6m+zd577s5Hnzni2Yp2t84IUnASz4+USKoUHkhdqb+/3PRddOlvhaegAILqvRhtReV+Yp 8WPToHM1xxI+4lwhdJwXwAebJi7OjCabZ0Lzi1c3mD0h37asvtMY+ggX4heviiU7yIHjIW0LxTUZ VqrrK0vP2b8cvtM7TMsK9lPvOx7lCRi/R/nKDJIeOzFthWG+yADEPHNpcSexGPySxFwUjLq7R+Xv SeS0xH38dqhrRDqxCUuYfKyE6YxSqZQS+SI1kxSYbRrVfsGgDrv1GOOLRBeCZsZoYVJob/J3uyBH kQKf0eFW8paAfaaVLtXPcxRxhLopOVluMPPvKrZngphdtJED9IzvBj+9yB/nHsiNHx8QuhfP7860 2TeMJfGIsenwx2j+YpO2DOBkIQDmi6kkpIcS8OPHdQn+FDvhWq8/TIK1N/vV8LCmuyK8Gv3M7UPF sMIZqa5OmmJQ94WZoiWZyXaNY867iQdfBeqh4U45V/wTXtgqkajP+f5UIRiDg05dLRCh3T/NHy5P ZXIh5B1abwAAMV2+jm/AcQ6ricSdqtMFPOLdQk1TCslle1ZgkwFYru4TN7ANiQNgs0SEfa4zCREL QrLi3tRDWmcVNPlKnErHtd/5O6Id73zMZWKnf6tQhzX3PLtDG0AtoqjPKJL2pLYmJj55V87O6H/3 ym3g/ORpx/RDU5EeOqaJ9ELR7r9ayNn8Q94ap9QaFJfC0UKGZzO4EDCn529/1Icocs6Pq0yrUzbL GlcOmKHvnCUy748vDWrSR/kawuqfS6TLEWJHgxLbhHiaq4nh0OOxrb72YS7o0ioTKriKdQC9a4IF L5sOItmyl5288PuhdjVTVSCqZSCjKtNzH40JJJBUTyWysrkwXoSFMwmqp+GCXfrVt+1bsE0mk+dt 40eY5sm9+Xix0WnLm4lhoytrKzL8gwSulDi4V8dgqwGSle/+xn/0Kjt8qdTmuQt1pCjiGf+0c34B 52k1MKeiERrJ3pbt1uw1I9ysJu3jSN32F/s09zUv/sTu81eLOh8Q3BJ1mLiO8XLXs+2JKKQTmuZb L8g9FjG3HCRiSeqSBkfP4WuYYrjnY1iEBaZRN+BJDFzEuVaNZVFjgqYenfAeMIQsilKvwl1cPISQ HO3FsMMzRQ88OugRBx4P9s/uZzytl8+kxBOGh0MyF5v8zFxU5qCtUDgXJV7dZO4CbeKWZg8/oGpM 4Iscj7Q74OTp1WBvruoNOzopLZ7vYpZg3wpN0vH3RKcpqzFPz3UQhXlPqHtqe6Mz0m5nakWD7Iq6 kQHm+vC0J+vNdnI8VBGMgit184/JJm1OQNjAAj5Vi2IknHrhyZgY8G9cWF1xLU0dSshg5JWJkMPp 0NF3RtgVp/0uW7deniUAppn7Ff+hfyyDw8r7H9cnfvlrlE8I6XvjUfzcLpjt0ijqslCYH1DVpNNi rCp2pH1KJQrETVyh5KxLbzTTVMxTBXk33cgM8JtmeyfBQsWtvh0eDarY3XI7+sURakP90aOsPnmt vwCv91PEthHEhb57R1eQLazH8GOZwGA54XOYcNX7T5P/7JDjj2AIH08vaWfbdfko0w41KL/usRQF wnIxxSBuSzVq9teHpMns+pJrFRFz/zYmBac1t5QNjBcHEOxxeyJB59SQTU+eyBGoTgjibggmloPA +dJ/iSPUlugcdsrqoxzAuG8x7IGEVWZxOIStqQVyXOlIm62nvLRnJAEiTe1BUGDf8F5CWHMGU+0Q 5HbJaH/VM5hWLYpRue/VVxL/UgnJEqRJL6Ga/pb09WGSE0B9cVg+F1LnCmrzWE+iTQCpxKQxXp5r R+Rp/LqtYp675mPT9cL/DPglG6QmgD2kSPTXR7V2bu7Vap2rA0xnD/XbjaIgCwndp73PdeJ5PAws H4RYo9w5qowUN9Ana51UA+Y09TaEYzArR53q6ZJ4ORLLFSrk9tOk7kNjFjN3r2VmkCjgZdw3Cm0M JtenEpMxt4mtIPFXtyrHVs+nSy+HMTHqAgEous/pLJ813gtoxPXcTWAA2jnpqcaozwlxTpSH12P9 eU43dhg+Yd/m8iIH61Upjv3K+Kj22Nt5IWByVj67jbPqkpMCeIS9tei0BVS8cZ/zPxuMCEqdO6hc cr4X259+so/tfiUj6gFOtL7/R74VqjGva0SCccxGtnwZlVsrpwvMZHqZuHxCNPasfZteMmbDvCuJ Ii9SUUAz1g93EgUhDrhGfz+VnuQBqBFE7+HEM04FLkvPQbG+oihOJEXK8riOhQgQZmmKQUqDodDF Hn3pRoMeupC1NZKS21B+5dT3zwMcdZtI7KP630DbSy3qzr67bG6oKc8m6Ctr2W+w7eHcSMnlJ95Y 5ux2twS+vsh+jnn67rM79Ej/LM+1R07H9j7B/XUPn+yvC0zZPGVTposzDxAvTOwhT/+HiylaqQJk g2nE3zvsbc8v1e/U6PnvSCtUjh2/5giAoKrmpKYQK0HuNhA9qge7HyvSxewwVNvNg1+GnGJr9g1S KZma9vnJvfbNutirh70VfBT7VRswQkPa0NhWbAxUQmUQs2XjaH4JPC92Tjrx6thJvHIfdw1xkW8r 1U7FCLwdGKNeRQ5oS3EI8lA1SX2FjO1itzGuzSDk+i9O0n8T20EIsxCM0v/tnjt+Um7QsJVwBuaC GzKh4IKL0TtEGqdxX7fw0a/zzE3abDJxp/m2tpBlBewg4YEcE+8s2KKe/V7gy5jsBAshrOKA+neo gc7aPoDpTTBs9gonrOM/gt5jB6Au26Il2UTwHX/xtgmIaPbXDcKJFAFY3mTfCsSpQ58O5bI7Og8z tT9IQDyK9kshpigoEFdsXG80sIxvYQPC6rk9Sofs8A+lYgI8wT4y3gEHbA2AYDcaTYUKGI2vKjMi NXSPNh9Ck4TTxxjbru4M9+GJnQkHGifmYwhM2CFar/e0YoMdIys5dc5BuRrAKhZQbbNCSFH3aNSw kROmbsjIJyAmgKgy04kk0pLrjPf37IzHPJaexQHp1+ZRFWFTvc9PJ33dwYG3fOpp6ySjp43rrQLz O92m4GIsYAz8GYJHDPWZN2pwv0iMtXge3v1/bru5Gsfn0zSSoNJ7jR0dpD0ajbdLZK4X30+W3B7d Sd8svmIF2Egjk/CeHaB8AcrBKvrGsumBDqKKgTypGq/MazmlufqL9c6raYYw+W73fB0K2pD5OTin VPOO7O6fr4JAbPmaTNvpKz6aUy41T9yYWXU8H2YFFVj2QrOrVCfsKvAldt1pVaGLl78t/T+aIUk+ 7kqCv2yAh7r5pN3C8ORYy0tKY6AM+TUlzgNeUqhsm0BUfkZ7EWDQuShIjAgmIuIECe7bq66ueAr6 JfYltxeBA6PR9n2vNQa1wtvyxh6N/fyAsU2fpifKEleZhNP/MzN+pCjyQzhw5itjJWlf0nZvvwDx zwcq0yTKzKpmCAqPorIpDx8XMyqRJGDagM4eU1aQjhFwGWHxjJh+22RfbIfS82HdaRvkMWJJipRH 3sslqwFYyaJFdSeqPOE4VmzxeXV4aTyTtyeZY1vP/pM8k2nXBxd186qx4N96WyE1YIgUJdQ611Tg dx7MdMDsY1Wh9Krh/3a/tkqcDKUkzRKDSpeRSGU+Lyavkx1t+Q9A4ah5dTnj4sYB2UY2nbJkjRp5 MBmGDD9MRf5aML/3d5oeKACrP5MhhfJeDyo2WZ2q/hiBuRC0zikPaRO0qWNXnqxFbBSWBTLIRyZ+ e9LAy1nMKwbSprR8d/GsoiPvBpY7/w4eCe9UWvzClrr46g/zRPk5Km69p04megtm8e7FSPG+NYob ME7w1QLNplbLdCNJFNKMXb2H1ry0CSxUNIgNeRfKQcifHE4EYhvFMktAJCFR7IEecuA4eMkycgR9 kKgwgFI3mFYO9MPmM0EUYd2S7YIRUFzlVrMQzVFHLx1gUDKmHwyhNFWPBGU9f3a44gGb5NyJCbSh MquRxYIPp8OukgRA6SRAylZyBhlL7muvHf5V5GfiP27g8GAotd7++oBS2yWGvLpPv36Fzt4nf/qH O8dCkjgeSK7Q5sPY2Nupqo1NnQQZspumDTurWP4VSBFTUgWR7qhoqNjHNnT2HjOHLZ6nmDiK+cXy JF7OHhTLzOxaZjTg77CmFMVMFGOr4gXJJtU81tMtaNn8WZUMTjpAs9kT1bPN6isf3YfigM601KhW CB+Q9JCUKMUlEL5/73h95oWy9zjBdmhFG5BOwu4lQ92FOkG+36xFad0LyRy6TbD5oiiWTfwKhFlR wAYfgHryaSd/IJRNsH5B43BIT+w/K0JOqrKVwmSuLofDsuRNws2ziHG5mLLS+SpE1IldZEmhGcwy 22XUJtPufu96efLGojQJNKqoBFHeJF2MGmC0GC4Cy6QG8gZLPxhEkd8MbG2H8neS6X+2jiQt8kCQ EHu7Xfp7id3fgB52aOkPGsSPQPO2euj4WFuRhBCXE7CcHEob4WI7Wv3YgQybv8Hj8P//vidHPWPT KC+H1IeUwWk4sZNMuiSxoZz4eDzG7fmy7D7jN2Xa5uTj6R81IxHZfN4pp2Jk0HHUUA4xzXuJBzGQ TmruPxoEG9GQ8IY2M6MQ53FUnMhPvzdQAVjNHMmlAP2yAeWJ4uUQxUU6kV4fMd9U4TitaNwSI0SJ nuR7jZGLDvyP9FVdmlhAKb+Ni18rJ98D3+UK42jgAXsRejPmQ281dP2/hmen8Q5it1kl/xfZ567W nJ7ShyoLdG2jFpDG1c0QubFn60ZQ0uzzIg1/X0OFnGNuUDLFi78b4sruRxqQ2BsBs9yllJJFaDgB fvAQOPc5VCaKq/saolFSV/NlylZXlo5id0ncvwvljCs0D7V8qX+vVJWpF5d2QSdZUfigPubOvL7a Ij4htBVHbg1NI+2EDty3PElr2lg24h4gmlTcNyFp6TvBr64DA5+K9mbYU9M21lAOkkr8ovV9xM+2 nEZgij/jS+z4JfG1pzBaDB2tfPk5SGA2AHvSyoBaBIuSM7UfljohT/IFdc0uFMaT7elpDysXUkMf fhp4P/9WL6SWS/UVAw4eQIN3/lB105fRhI09UuXyxiQUakvYD1poUNednOQTD4IV8iTQT44BQJZh tSSTnEvddsYYA1p4Z6beG5K5DGAn8AmHxUO0VWpLTvXlYnlrQS7RzfAonIU7XAyow/eSmRsFdBvm 45+NNmCR2akL3ibE4SQkfhL4ZX9wLk0YtzlV1gEDtnaKWOQY6uc1BbgicylzIiVjVoL8thDd+x13 mWtqlnkZ53iG0xG+VjFX1xX70CZai+6HFgZ42LVexJ5LZXZZl7eBVMvywthCDXXvScQCirrIRqMv 9+hPS2AMdHXQfZfE5PrS2uHgRAZXCfX3rAa8sH3Zihio5HxeolA4z4IVJ9pDrikNIKwshy3yXeVV Mqz8jLUteqOwV88K0npXj3Ath+8eqzO8BWqtTILfyjDmSHlSDinijXj3JHekqBofudcFhC0TTHCu ghEhSfmKZepnkXETXZz6Kmy2FinGF09FltFZoPsiqGAR9MZzvtW/U2m2s1fJ1qqcgdrfz2b9qSeP S35yGz9Kze5/lKWlX26p3QIQKTThaL9evXLsHvON5v4aclXZCKRuhn5hxCHRVJRtfUxop72YWCUj oN+r6uh7z+kS+/Y8iFLfnhckUbHxARBNs5PA4OER0T4Mklt0zJDHJ6nE+qSrpXQ+o/mVQE+4/OeI Un+HyGtL6q+EPRM2wn+MI09FXLjpi0QobDmmME2W7I+wZrVVy06gxBbxBdpvakJ/DPJy5hYnjwkk hDdZo3MfJ29pjoQFGjtVY20lU/leqpIs/e5vCNAsIhJSNiOt0BWz8sk3T15T3p9WkWVP4G1DJxO2 EL/l1H+LTp47Yx9sElGMQtq9xTyKCM63AjzY0+k+nsvyG+XKqyKZnU4N+9mmouwkB/tUf+Co4fx7 vnqRNQvcbDkTpOnQa3A3f6b71A4m8Hw6TRzlaSYsY2Xa6k2I1w587Var2jit8GNFAsl83evJyrd7 zSaGXc/alezWCwKCt4XZGpdKNTOmnUHnrKp9s0WlIj2UCb+zgMMFKtb5flZQ/jKAuFZzPhSB/m2p XDPyb/89LR4ayfklx/xVZNuX9zlVR6VrKMBAk+hHF+1g/Xllvi8IfSEPUHTNBHDo7kzy/+ggGlhC VzPIxdQ0+f5fNWNHXb0R1XHPzlBv/cKBR9qnH913IrXlt2PYHdapwSwyTadESqkG0DQTkH4b2OGA w9SfMgXRY5UgerEI67wbJkf5DM3/mmsuJRvMfcFxaJR29ahKZ9/c9VZw6JC7C4FQxEO+YABAO2nJ eDU9WAEBCOY8F2hx0eBVFf/Fl2ELZ0XfpdVEhWwsZCs7qWTtLUyq3C4VrigVux1gQ1PICcuGGcSh 5+l5FL7bXijz/dDXZ/PRUklWEUPZz1dLfiHJuAuf+blYunuXdxzh++VSQwzx/jl3vWzeqnkN/0Su fgzORfA2VftFt0m1JsCFjU4ltxYNCdY1mCehArXA3h2z13RtrKT0ohvf3Olv+jeTkbB059UU3D6J AL5o0cNB80PYwKy0KwNhEIz4VK7UOqOcEQZy7s8l7E6EbuIulslTbNeKG11dP31ytbYSYl1aADYi mDhkRh37RKN2Xv2n6QtQ4tU6k8GN1bmyY1mnv+pggSJyYUqCrHe6SOeAIkbChBBbFKXVavmkJSNt KirO7BvEPPu3UZ8l+1utK3uAstuRUBDGyxRggjslBZjyTFozNdp1Pjg/XaHxk6vfwQmGQIogvW/I yCp0PYHvwC+wFGEdXtZR9rP6m3ifE/kGHUNy9WWx6x35HS0Ryt/mzrqM50vdE6v76k3wBCCxWteK wqGJBOQkYYacOEV2X/XyWKjzeaiSeSN4YR/+jIdeV6R/mL9BIHgknWpWne4hlYZCSIV924BfSu3U ME1zP0dseL2+xgLHQtRLnJXIuqRXzrbeXDEHpGyk1FzvuFCUTpovjSyk9T03I5HT4jtnZ4yKtaHa /PAYKvqhnlNfnZYyEIqQio4HnKZFYS/rmgWb+sOro7sIo6DpxqIn9edGrIe2zfiIDtmjqThEt4bd MZhcEXghj0F/GHDFGhuZYaTl8eqhx8UrRmsO6fAvkJXoLxTM6JZ6n3fXzxYriMyuHwezY9bOXfY5 u/WvPt8BW68WpQlCPbERkQE8dRYNmOuBOTMky8H6htTHXLc6AYcj8xQv6FAH29fLEx0h/ZEcmwT+ mMOE7qCbXCJu0Df04B1lSmYhacnPjf1RcPYUlyK+22xikCil7r1vTeVLnHdy9e3k0aTPgQdE57Fb GJ9MXz2un0NfExjccXyOauqVUIX193pdKiBNZ6t3sU34JqXxiY3CLkyIyGmf1UJ38X6B+Q2lWLKp OHf620CTcm7rt6EsUCHstj+itSsFjal1L+/1f8YMRxbpha5TyOg+g5nvSyKtIrzudmmE/Yy73FiQ gytJByWbuwSukVk/z8bTwmEahds77wgZqz1mTqdBtjaOP78Xt2wFI10d6Dljw50dIrOhi4NSiqC/ DgxUJqu4dQb/cas7hjgFeGl2sfEVb9OSDOhOE2vwMm8vB63VxKxkfnS7GwvECyG21chxB09vCAxt cJXYBN1yzQvuxrsa4a9rcS6kTxiFwqePpWtY9+5bKFWzOVBdHJ93OlFhs6zSSy2rOfpN0UAEBGAG NpQaMbmAp3GRfsGt5vbi98CM+T5FYUhI04pQYAmeLxBEI8ZPOOzrqnKiSyc05LtQeHY3X09d1+KT l7CU9h93izFHV6aKN721yNFQWecBQJ05tb2jVwe458jEYKIKk5vWQVvai0h52JF2Xj1LWSv+kRgD SSZQe8zkk4vBedk0iAZOupvu/PoBjFuzJOX2GlacuQOgIoRqPc4j4T76Y/916VOhJwarXAPRLi1Y k7viFqMuxwdKcNYolMb5goAoZ8gkNyIvxeF1umRw8uopWgMCjB5Sn1/XPkcfR0n2wOtiX1gXqdAS F2UQDkuB7Tcp/oXRb+4duDepS/wJf51Bos2HWOqR1ux5mIbQpgkfTkyVh6vEOw4mnzFWd8y17cJh bJslePJY8T4xIg+6rtme+h/VPDXeMt5El9PCDw7Pu1/uV6tsqyY18CSusARbMGFo1Is86sT1XhM/ sMv9eR25d3tNTW5Zb39dZ1fhbwppB+r21Yy37IT9uFFnwFTRn5b0Ac+ur5NDuJ+q1gkv0v1n5w5u jT/0rkZKKkUpHOGSwZXue1O3Ze7Y6NrxIsX2TliDmRgUdtad4egH1sIDpNti58mcaOdO0uU3vSij lhmoeGXymVcHfyq25FcBlD8gyjsJFawZEqp5zK1UO3Fai2l9F7rVVH6F43PIVsV9G8Svivn8cwGl RhsHX6NCvhWEM15axpPiUBbRN17sNj8jjSg+kuTp0hXGnfIJ3Iwpd14qjxjab/Dhf+if8Ax92IIr GnY3JjItpc+Z1Dl6CSIQs3BXmJSUqivxVGqHS2bAO6uNasaxuI/0IOV1+Br9DmY21XR+TB0/3/gM y+Osy2U+S7T22y4092UEn1Knu4dIPZ/DiZx8DNRoTeIFYkB2QDVltxWJWr+5c4po32BEVl8jZLK/ 33wGqjoSvDGvI9+e5hqISwYZtc12AOZC9y98qhCBVrMF8b46X76SYVQkqqMTds1Esyoq+dcn9WnC YokYXxfIAdGhW46qR9GisxlYy33lOgFlpQV36dAF47xLuuPH6b08/Wf4/sOcfUykov8PJdBKoWSZ Rx5MnhpO1fXsXh4xXJLFwZ0T4Vy8OGkPqF/2Y4xK2qm7Wc4fa3N6FSL4XmQQC81llR8B0nMlGgyO yCpVvhzSLGlKePndnZKyXjATJrxf6cbHDaoNqLR6q7AV7dq0T1uh/85mODkP06dxaSQdmVttWR0p /GbdGGXdLPIyUE3t3EiEjkcpFjribc052KLIg+8kybylRSYVaC4LBOpAmin+lnUBcZ4bAkMbufwH 81CeyRCeZnnW78weDdKoCHuopIH0pqyd+wl30N2W0gzrv/absrIXnq2oT6MeLpcfoSzX/MFBlRyq 2hsJSYqxP8T3QNYAk2IOTPvP4Z7ml/lBz2umlSaSf6Mux64wCXYrcanfnitnaJtbNfPzXGGgkY/3 T6+169P3rqjR25sirga7nBzkJ6g52E4WLTUEbNZBA0Mk365xNBVj/sARuhMykRczeJoqj4qp2fsf bahAEtYtsOw29KQN2tBCJG1cFMlZZwsGt/1MqjsKZz1Y3Xxr729izPlcWVYK1bav7JRS90zdFw+k NyfL/gk3cXaS6o1/PAiqJ/l8UfUcIIDv9votIO54aWV4oHA79wu5jvRWUEQeio8NhZDZpUR2HxFx Nh9jPkvo50EV0uP13nmE59g8zTKV36mBGmaJIaHFA0y6k7fGAUZ/ZowyS77o78WbP67BIpUxLayy CN5mH9L3sV9NioSYC0sAVZwYimb7CPdNH4rREwKSpWlnBJ2xKsz8isYuRri/1XdePmgEWsFZYLet `protect end_protected

gpl-2.0

ca0b842fd24db088b131a4c8e1794920

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/xfft_v9_0/hdl/logic_gate.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block kVWbJhFaU2/suMFsn2tNEykxqc+UIp2lPRDfbFZfaUFt0l8Wkxj/xUQXoF0tqFBGmuBlVMYJzWVV VF8/DpMyGQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block oL1hXiSqaATkvKNtDAdk3rpBmjKzUTp4/Hc01LmNpNF4MujkTi24mefvgMUvvSZ15EnuJkZDMVgZ ctw6wtcaZshOJY+RqODqgMVWQScuSUECj2Udh/+3YZsA1GwFDRgcgi1aWUd5yYb7H5qt9eK+1LLp tpsLed/8vX6d5COORVA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HFlEKSlOXd0Vbw/hoWdUjmFvczI17ddcf5ml1FQyFVdlmVcE7lJ9F8fWYln13Y4P9sA1Cc0yie3R 8ELq5J70siJsfrGjR2sJsk1GIwX/KqvgOkHCfXVU4uvWz3/hZq2xH2Oi2EzMER4k3gf+ma5pISxW qQw+kHZWZNgMHs80kgplhs9n4+1pYdFHR9PwsyhTyjJLRJWS0vW14cVtyd/Etos8MhmQ2PDl+3Yd 7Kjem+8Cz6Nc7sJOhZz3tcNjXyudqF0HtfuP+1C41yT0rrSQrVWrVXt6L0O1y5JhdAhXi26X5nTZ mvq3JDXdjTWm+wCARaoBGtYXtJuEivZtjeWXIQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Xtw+vVkYp25FuoiE2ouYuoy/T0R1gFJURdK5jZUZLx+y1EiPbSyS3BY03DeA0EC8PqJnHxiYKhgq so8r79rP01w+oG0iy58AlQ/EkOiSblGQoDMOmudUbISCDlYxekphJ9JUOPdp83YucpQvkVetJtL9 JfTrRVYcy09nWUsPbBs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block YbraWghrtXBNPvlgpavWboF9dU418z4v8p5cHNWxstLCMLKUqrbHOwXmIf/W9s6MCslXSVhpbeCC +5Hourj5QIk2O8K7mjVM5Jj9/bmMz6XMnk5+a/ThRJfJ57Mgv1+QexUgHqY78zIrrdA9hgHLFWao lOqnZscM7IXYRexe6Q3xt1qjfrgtR4ek1hkOoIG4/23wGT1S1QnWtMF1B6pSMW4YLscKNFwFT++q hlUEUOqIDQrTU5X59VaXnCWLzcQ9FYvfvMuWpg9icMlMUI5fjK2odRRXkrF2OOrOgFokILq2b32Z vrvs2jqeytcFVB4jNtzPnV9UU/L5mnyGOR2tcQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12128) `protect data_block T2MDVMdAfdkQFa/B5N2C2UmGwZMXNRHHVdieWFxDniDPM/m4MsLIY3pxPIzVhGqFmc/h2PBLqCPl +W/ANPc7OYVkitFrJuZQIiSuF98DyP15jfxSvondsyySF/HEC/gNXIfSWMbcpQfCQn83SlAxWxeI etEQqLk39qrmeRSm5kefpBAJvnyZx9sYhPzWR353QvJ5YaPjIxZA2wvXQEgbjv0stBbFnLuGM5wq GAcDsJoOcHDEbABsTLnym+C2kg9HmmV+KZE0Ox8Ji6y7sHUbmtWx0a7A7s8XET52sVeNKcDzA7xU ocp9+uR+OJYf+24hmhf705J9SPK2P84/eqzg+IEZi10gu4l7Qk408Yi9GQmVoMszUmvyrHDwhAGh IbNydRDQv9O58ke2eDIG1fRS8Pvgu+qepvHSeVQLUDBR3lBcOIQqgH+AWRaYLg4jBBdN+jEzVx7+ 3fX9sfDKNw44L3hSXIaOKHX+MZRfSrsStVhXdOtBVuTXuj5amOlbl+/YkVTvKTMIj3+kFGCJmI8Z XAHhxsiJK982YIvmPayLVOhdqMQ79EOUAAkUh/L0NQgbJ8FkO9A0UuCFw9BPrM1lFYNf1mQVpazt vrcCgvQaVfU86G8ktlr92uPlTsNug+SG/jt8Q57k5PtSQzco35rprveDbfD9iT1ZbaaMltD8Xtlm xv16SKYhCS2dk+ItnDCwlpZi+9KYnRs1DkQwyCO8Y+jWeShHi+SQR0NMlZ8EuSsPv4ZzoJKVci4J +CSaX7i6c1eNJL1wWjwlWg8T+o5iKGlCkRsmYnJ4mkkLKf2Z8gB+z4I6gi4hYVZk/pVcSWoZgbgQ 5GvQiegAjlkQO1cspU7sxgkbduWr1+Ya1UwfR5JRTYaCkk6iSzKDlsgUklzI4Dfh83lbXJHpiuab fcPh//ZjI3Hx7i8VUHMRlz1seNQeS8XC2tZ/VzdtAPfK8KZ6E9chqEXMJ+CsC36ja80ZV8RXcKZ8 mxFeE1T+agS8TUBF8fYL3c9q0h/02Sz1/usSDzlvOk551/eGtlXlvzDWgxPByN8JMKCK1fkuH9TO LVcJ8UTkV7OFeQiXLo4hA+qDh9g/rZxUmUMA9IyK1Yb3PVE3Wc0pE+qcmhPwWuZctJkG4TMj9sC4 7PhrFg+SB55/8cIegrpM8G6zNgRwe045Wu6++sZB69snF3T/pI9RnBnrC7KuQ5mlLHS0iTeHgthN zytptA3uxFHNtJVJhtruTgcep8ypy1wSsLXYAchmssDoEgO59WDE0z8jq8nBeNSpUBdPlRiil4w0 43ECWpBbTFGAjM2/5LHMh3N4qhSdbOImYA3b3sKRzNCWwoxbXGyPiQd8/+IWM3xlvbbutZh2TQUw WLlOn8NHjfx5IHAazYLFFulOnyPti8GR48wExxSNNEn5XQ3zvYshB+ZNpwA42RTNBm7g1FOlV4X8 cZSG9kTEBDwrUTHwTXZGI4TtZ7fxnPfyskEKm8HD9gAdvi/3lu4guhcD/TwqTw/LNROUq8BZR4FS QOpTz3LE5sC4ockrL7rYTf8m4Fs+FuBptF7uz0/c+9wIs0kqQN2pzxBngfUg1M+SV+ILhZzrScZI GTzabR3C7tWDkSioQQ/xNH2c4n+1X+Z6ECdL0rqeFl4NMjyWqxxFWLvzLWahFRgWjYAqdd9Up60B /EPRhmta1GPrhwN0tkqhgtJhrRX3EOVdBLPJtOz3fqloLQuFGRhscsoUxmH91UUFW52S/mVTQSKj C1xuLWgtnM9Lm/hrzkdgud1Jiz+5FJoUpHqch+oWyiryZOaShDsj0oOMu86CktXXAKQFVVnWC2yP rTUJ1tfVciSur33gJ8vBd7mhbBRlhJBmLOItWR1aaH7HnPwTJOUMSM84AXu9fs6/Ide33vs0FV9A MCPubiL2kyRdRiBmDaYL/K/igfa9fJptbKT+0kIp2lR9sYgXTNNV4c6k/Qu2srwZK38pF9NaBQn8 QXZi9nBjEdTV5s3Mv93X6WHSw+Dfs13zQqt0ScErSWDsVwn9RBWGpveJYxNhJqR3v7uAn9tbAF+o JGCIA/pockAbCw7MqcJbF3tJtqib8kZeFwBJEZHOaxgjJ1PihQw2edeVngjmXOOJvNu0pscbRgOd Fs22uu8Lm4zq++5fr1H4TtW77C0+U8jN+w7gSWrbWT30sHEz642njMwrRSSA8veq4Ga+P8V3NYhF v49TBmvmRVoUDYUgd9c/hkSWbspU4l4gdw7b705aZyGy9ASeCHv6K9UUCYqu4aJPXQPMuHBMaJ2N zQXn7k65NBwGntnXVNdgzimWfntbGguJ3cMhZ5D8puEGMSszl5I47UcKnO6klVR//hhdvx1rJh4A 0IVgNnkDYl33bmxNcrtRmh2uq7Y8IQGOrVb+ZzBmjJH5jeJUmJGkeNCFXR+lOBPtkQPkoXu8Qh2/ 7auMlAjwHg1TEGyKLG6DrW9UqiA2u3OijtUkjVGjGwzS1fkWHzhxYa1+4AXl/tp8K7RnCEEgASsK 8iw6UjKpqkwb/qOTBrKnQNKriZnkE5ifuR2/5EmM8YYXZOiaXMkRkCV0ztYIlY5wTxVAek2N0s6+ EJoRQY3n4wxZ8Z3vv/NqxlYazhPD377ye/zJJCM1uLUlfVlPp2jKkBbaFron+Ff7rRi5k5q6rLZR XTCXVZD8mZssNPL75XXYKIkKZKezVHjCszCveewoIwG+RSlrk5YG0P3/CKu6tx4SmYeEXI3VL98r Bn3hIDJr4JHhPEmozVzx554cMyUlUciaMUorNfZtCaMkQnC8P8+lfuYP5BBgB2SlNP6C3mwAfIow 9FnamQvBrgJbliwjnE2BJ6aPVvASH8GhaITlm6ian4ZmT1Cc37W2ynCR0JQyfzVnrsksL0A+bUMe beu2zrx4wtgWkejugXsImjwB7Ara/p3HFoEX+yxoL3yP/2EYr3GClTqQisTkz/2rlUmxhZY25/0p QuIAOsadZ7MJ/txNVMIEgj0d3ltriYzrtHPGGFfPx9eOlOzGNCL1YbnoE76fTzZfTfpYNX6CoWZu KXXPxL7cDY/XRM/6K5orKvNAe/3M3TTEuKY8rYfIrSoUWc+7mZgUZJvcvBASEAl9zVasoGHxzWm+ /JrVIM05iJ5z6KPJ7Df/JgwkLhj6EJjgYVvM7klcyKyPmwanvgx+kCtMsHlfHBUWheQNZorLEx7B IexEqU5DiulSp2Gzxd5OHYi0PWjCBpjIDDEp2AK3OJl5GMX9lZp0SzE+qxHBTzJjqfP19wHeJ3Zh 2nZq1WKyQgDe+OsbuDZ1ttRO8d0hH+dma+pDfaJoVrwToyYioLRr1My8JB25/2g5ryo5XQKTHNrz GKTQl4+QGINLp0Lo9ly8wd7sf5pBWxOx5foFbOl8OzeBRylPKmgWwIDmzmR7Rvne1h3BC5pQwuV2 83t477b+WsVqr6kSnTRS6ZbsrU4niU/QD5aP3ERuaK4VwbJrw1HllbTZDcu5i8goC4EJ82hWFi6e 3f/RBe3iTjeRokvjn+VKsnjY5LzNdHS2gy6TwaKDa7OAlRh88Div7fqt+lvNYZDDhPcO6uEQgaSN Guw79kVwJK5/rsokuQWmh4RmTkhEPr0VUSBNhW+VNDc+0iV6Vsmaj/hKkIRXqn9OKDoEEukKRcmZ M3fqPbGRaUWS7n1DuKYFOMbt9/WfiIMdTCaXPmZycQ2ag3cDoOsa++hFklRfGlh1OniOk4l+7HC2 51ZuaLbjQfdwrLEpKwaAVQ3aRn1ta5UFULYTiUgMNvORbb4vgKsrlyombcQARnNN9s5KbosCf9GX 1DX4aasqAX38LhcUvRacmI11PADm1OpjXHy8g7ejbok7NKKMPZqwcjquZqxvZJJ/36fbcWN6bcBm cz5/fBnc8xOw2GOIG1PIyh0TfUkXw00pVso1TL58xuO7Fbz+K5vbRIo9521l90C30wGRa3R4Me0D z0fXZkGVW1vAPH0UlHmAXtwPLRLm7LMMbMhHTR3NNcZxaBDeYjklir/LnQ5DaJyd86qKXOlxGIk7 wsS9SeGe996O1ZIOMS7kaK68GQEVsG08yQ/8ATppnL4TMxzUyX9gh/xEVqLfYAbzGaUPlcI05Q1L RJUEpZBKnyRvzsGORkguCOhPJgbVQnEbX/9H1KIqO73/rrJtPrMU7WyGZZTC5bjmBhqDB5DnGvPN tDmbqDGXSjzE3Q7zCLihw4k7yCLIe937qPbfSxA7rijS0mho3JBNJo3+Mk+pU9DE7YSWYU+SxsPH hFblaSK/2aam8xE+6m1vAnfVMW/BL0LKJ2rtRZ5cAFZs3FKGed1AtYYLy1+Ulmwq2m7nwCdo83dh 5EerIJNo+Ph5YC3sGY+TtzZlU1cyZgpMayBmpbjxCIYTfCURTtte2gJ/06lk2Xc/SrAe9kM+FyPJ pgyxREmwmlVvxrIOIbKv2K/W9vYer1V129UqtGhOAbpNmM2zyPZEKfWM2qUnkXBlaRTkfYzaTN6G pKvhGEjVKO3wLv+dZYAleNCKtgctVJ/1JPZ6IoROEdGbNkUxc6I2M4sbktExuEtmvw5HC5K5gluw XeoFSbXldcpAkZRkBgmT0MunZoPE3T0eaqN/d0Llh8OcJr/i+MCBhswjrhYyCi08qn/owzFyDpDp UXJLhxLig2mHZE38547njvBpZO0OidvSY5Ouuwurys8k2YD9+qUo0ALxN1XTZHxuEruEVt5INqrT pas3CBMQbWNguQyU2POMq8LwF0f7J1VPDZ4AlMGmRmr8EAhP13WH8kcRzrrD3danNiCXwuZRrpdF RCdCaJLrNrsrpe8P/NPgSj+likU7d0PtSBzU4tgPl0906lS7hs8RR2KpSdLocJcjJ46Ow3efzrt+ zVH3gFd7n+lCoWZ5ASkKlJ/UAP7erqHiWmHj1gHoJt5zrGnROxOfRilTGkCVgvG/OXqRGuFoP7rY tys3PEhC9DvcOeI6gcrGNWWMq3rE9ox9Avc1srujqo0cc5SKXcSJOdeKOzUKW6FNeXS/2AROnqKC b4pEnOOnr+yOYxV1hE2nIOfD2o11kZ8kcb5dUvYPWDWM70zclT/c50Iq2ni4VMsSSwgQGsk+iwUM P1bIKfAfkRBVf55nJLzYJEqNqVPeuE/c4l+SxvDonQlU7aCBDOsAaSgqqW/sXKGbfLrD8tVePKZA 3kFMFsP8dxf3DJLKLDwnsHlKJZ06gviZyvnvcu5kP9DG+aMrlsAnGTRwSLzBBz/zRkrCkB0JEmd6 qVxz4N5v83/FSqXowrSscEI2oAyjQbnqzvZ4hjpSaE+2p0w0bW3mmbdC3jnLy7D1ijmUgfoGthVb +g67jFAxIEYDltbQsIfq6XApZLEcwOa6lTO/8VBgLV1DjSVv0XPVDp7HNxPNMK0z8RMEXuf70+H7 l1X+EkJcM+rF0v8taBhFsC38u9Vo1NLVJIU2WaANQPQdqVp7PFjwvThbcZHik/5QZL4lhIC819ff HSfmUz25FpFP0NCDrrVos1GcXsBOzi+yaivHLbIdeN0N0P0/GVM1x7ZDZpwZOnCorA0VQRj0ezbz meqXL4CPArcvQG6tTXK/oPkP+bR9nyPw+Dkt2dGJYcHU5j0ESy17uKyRoLTsOwq6Sj+7MNUrbZsB 2acmWpa9WLHe3tG3d2LcAnQ9c0JFO4GejgOdHvAYbjLviMxUdw5rt2uwSjPZCyiuW2j3GrnSG0vn wnNYfwP27gWSg2KjkxZ/DI/27c383FmXqdWUuf+/2lwUdfA2BXUoz0YhfxNKhgqQjKoYE4wylanb fxLJLIsqsOm6HNsptm9C/zjt8DJqAwZ1+MqkfJyH5/SFdEGygT+vqtS4udU6ZsUBE6rAOXy4G0Rx 9RMwwsTXFIk7XnJwb+C0i0qb6V1PlCexKDFUChaN8TGoTAkXBPDOW4mmtrdbjBvAMchFky7uIVz1 IRpatwOZpIYPwTP787thz7meRf5tyHQ18w/szY6VQU2RoJzWCGlY99SyRhM2bDD7XmM8qeG+npAx 6i5+D62SHd/YLZ3VP5vC0Lq5BEu2f8BFayv59oBelamWi1C/lGauHRDyAO5O6ACNvTBmFXLC0VX6 DJat1FxEpow0DkMV9nZYAV1At9vCKhlnmMSl1p7VJUaLNNsvwmu+azEdD9l8J4EE9zmLbDTpvO/G wS2RyxABq1M4MMENdRksbHiP+w2wl5qbNtytKDTM/gF49BIADQy0FvZd/95uVHesxFj+ye8nHCr1 mDTPv9Xi+ZUisnvr/euHA1uG6VJshol8RSa9YI1qhCgcs9AzKO97zzhm2HMFrVtAaCz1CGV57F0G cZ6FGaUfJSRJ8vDMRtAdCQrOPjb92aNMM6IbO2dGgJukts5OpkzlleF/kMf0egCX1eC589Yp5Qty Mz9xUYgNW/fGyMLdAJseNbEfOHLPs1NUEHEVGUc1JwfIaUMWtP1AjDV8PjF2gAxSq/jAgr6dEHEH tdhlBrYpntZd34Eo+Gd5+UnmAi9s8tmyJ9oYQNVDcw9J1AvUGGYBrpoG+4FN5xErrs+AYTftqbQq /pGWS9sjn//g2SA+KyGfHU6ZrHqQ1NRZPa6Qo8qkodGDwSuCjtlK6zFqPe4ARv9IkXxN8NaYuqjL B/DQ3pNpBqk0LRWMg1/Nnb2pCJ9By4FSjoDnXJw2TzQlKWXe7NVXUBeYVDbaAtV+bfRgR92MBbZ8 zfm8gyMccrvzDQ/H5nmiW1/srE4bAEB+ZiytWcNoK+wwm8/oZkc8AOpmXk5lDRVCZIT5TEB7fWJ+ h4aCK6kJa0ACayy+gfEt+yC6vXo/BbV4Rx7Ezggc1F974v2tZKb1n9K0uMRV/8USo1iPyVXX2mSu iej03Zcr2m2PsMyyQ4U0nits/zdC8U6a1ScRacHmQeW+838v/qG52EC7NJif8kwdz79SiXJkPXEr MQAQmhGR3CkwVtWU/NFy4XXoop4+NsnmXbOL5URVO95SlX9mhx9J1K1X0l25tJD530g7Ujl2+vi2 lrJ4/doLStGskMe3qzFfOVgVomhz4VByyLXm4OAYZB8YjUpaGHtA7kvgSfxutXd8MfN8AFgc1r2d J5GXcGK2EUQviVaZPX/NqZ52YtLGiEd2AlXNq6ebILLUg6psyYd+eyWyqpUaxQ70P6HFeARWBF5a qHRF0oct+C9tLQv55wJhpgNyPYmHtCsYX7UAc9v1LLpx7jZsEGutNGXzSkAbvZipYhmnPInWZUYP 5LrIpfJrwMwPdgjE5Hux2uTvmhAxe+TdaVkBrc9gAVYtiMjJLIB0yW/5re6wXwqj4T0oGsle/LQV LhMJiV7wI8AZycvrOOZC25p3OEqj64WvBLzJFgAcg40lb/B7uar2wtuPJFLEczd67lySrv71zY75 uFpiHDqpZ2fHcCr5zpKyuKR4mq128soAQ+59untEjOP1VFiJtqxhYYymBq6dTOHPH/THrCHuvwFN N4p1TIKPW0VW/8BXwKbectNgi7uldx3jI//LLoHQdtHjjZjC2Uw1WblCSr/6bbQZo1lDilbF0XKD 0rYqOZ+053PrbSzI/gYodRP7O/vVE3MB2CM9kgQn5CDPAWnu8z4AEV+3RLaAdQCRLhqVuwIBsdfE tQATSn4TdlpdajmP6T3BFqL2yobp+qdN73rrEf4js46K1cJDGA9UQFhyp87x0ycjIrS9zuJdLTHQ MTZFD+oSXV2emaFAn5Aw6vKjK3WkU5pDvVP8FmMbU53lSFX6ELzNdu3DMhbmFA0/7UGgILuz+F/P OwhrSR0ghoSJrPFLSNkgBzkWLKzLGb2YlNo5VLLFWW2DNIvRS22ECuNAnI2hODHa+4Sc8qUM/Crx q4uLIZCroV3nellJn4+Zpb+gwOFAmii67Bpoy3MnmKlVEnGGFGA/dS+/Z86gyf+Zj9PAhIG9ITGX RplZ2o1wKOt48l6vcU3LpJUxzNfj4UED0LJFVnTZuwBI97wPfK7msHwpeRFNo6LI/3E79dC/3D20 w1wqFRvAlnBBiUmP4Dl3+z48aMlcD3e2tRGs5rvvGK6M1ME7osQepRk84lGU0627DuDTqbKCFlGm ETNIZr3c2Pe81MyXg7dzQZmO/IafSLdkFjxU+XS9xBynxRk9ZAouBDMQwcgbDhvmdmGwzA9CLksD hXKo+0QKydhTVPrk2owRtmsTMDo2qX5EPTi5GPENU4nck/bAZelMMsJKTEyvzU5qJ4vBzPyI/+K9 bL7tnXZbm8BYoNtH2ZpbzWgTiGeQBoItzo73bX+HWLwx9aLXvNkXzS8yeq0/MbSNPjK+yyre9CP8 qxpOdKKkQNaflLGN9ZSxyGdnLux4na1ycq9YxDL4GZEP3u7hSRZSug5Q0Me46GEmklBdmV1Md33L cirM8NCnpYbpXLXF6Ws+BfFHn21ILO0Jk6rsuncGgsdeAJ4+jpmy7rTBGIinoSGoaTnN2iDsoaRD gwYptHh/788u+GDhCC3ktKOzT5NuSMRLAQMgnWN5Q1wZHGVKG6KntxcPxMhhlJxsZtnE0Ld1majj MTSITfJFXbYqUesn85uqjdHp8rarSeUeMUreEpKQ8EQT7f8CiegRWFvl8gMb+x5uMeprf6KN13Gh giBM+fEPi9F/gGiZe0a3uLV2cC5W6NKE1F+owHPluR7zFjFxheWT8MZbfOy7FwYnLvxS3L6o7so8 r/4j78HosTR1sWE/T89YSKYDDuN805cAb9o3IX2IulrVmZlGqOdIOP6EwCkBfq0w8fP0UK3Igycg 9sh4EFupOSWsvEdbU4UKG4ZH5sESVx2gaRKvktnrinR4cR6Ynhyaio/lS1zm7IXoRWhlVh1CgGhE aHts/9xlGFMcCQkLLMskIHybyJ6M2lsnmjm5mWNvM7BOZGyRCFVmhIDl+LMFb91r/zNuunasKdY8 cSbMPop6iq/DtnZKQWgyvwS4Zd5zKjnTxd+Bn39fmA9ILZNdx+VBTCV6J4MvDCwlq4U4IWIYhGKI v1h5UrZikRDUy7s278Kxuqvv8Zyz40cjcINrWliwYncw+sT9DDiGi+un2XAWMMo14Z1OR7xOz2zs a+xtukSntrmcGho9RFyMrrHQAaKqQzDM6icvU1hWFu/F+5O8oRu2WYVLpmEwoB2KQSVHdix5ATiF vi6JW/y2RFHaE2H6xMAarJ2+BOXY1wiOGvi1SFJns5RQ6bxdjgOSs3KpD8B7HsMrCEy8limnMmLf ybLpclj1qOmhA1FFbCRJ8AR3fI7Nc9ba6xfXXowCk5qmU6wz3mc2hRkusM5KpdYQdQ/N8QJ4xrTv axqCpMYKyhznCFgh+boIvq9AYvKQHecysJsbQQAe788IPBZSPTPU0avOc4shz9i14LRFpHrFedhd vq/g1lYt+IRBSptSP4pxDIkI8d++bXPoi7YwSq0XktJIlWaLQTSROfuxKTQBtTkWMXKWSfUTECFh ZfUyqKs9peBdflj9EP9EvvlNwaHd5/RIT41kdLoLdFjdE7kJ2n9MVJuhww3QLU76a4HUEe/b8YXu yMTb+2EiQbXUpy9fqzVBR5zkP+8YKttJ9OZhgKhn7GUQrpVl2HZb7xsQ3vV8h9yRBi6MUVIND8PV abdtB6LPVFxsTE6cv7ueC5NxwGLvGqDyEBXMAa5LLzqjjaJx+dXisWGGs7VeG2kovZbjqyYQUGvN PlCHdWwJzD8CZML5Qyv0hJ6VQw4+miRLqsh/s2NJBdrsIbZaHKTPjb7fGRbtCurZ4fWH+8GpxQm6 3PPxxLJ5NO9deNBrLJz/VCCjAtIOuxeGp5tac4DC7myC+m0vmM6v7vn8glmNWuX3IVh5qYs14hJv 1+C4xNwfrym334/kSbUMa9xvPAABXjXklxqMYgQNqx2KbcCg92cxzeBkjf1UXGFhK8o4ia4seP53 k+mI1at2wx/wImE1qdNt8iB2j7UT/7r2OmkGsBSq//snC/2lUhQ1OPQDkvGJIjNeDaHlFaCWD9oR Yq17Ql1oTCGSvM4D6xooLmUCs8pixyHI5Ni1KplTedBRuj6TCNvOGkh0CSwYJK/fhgWr7IhXnUaU kjP7QJsUJhRUV+2/P2FQKJxrosg/KXI+Hso8kOx069qSKHxwWDRSkTg2tO5beJXIISYemZcUiaZY 5ik7brhkNXf3UHCzC2uIztw5cdeEuQwseEFtMz59r3gm/bmAaO0K0b9zAwxRSNh7xVqsRp0b3w/3 cpdD+r0Cu1lFDMZLqF1HStNL4ddR+wFHBZ9h1XDWTJr23yPMHQnqH11w0dUogBHFuxTsNW8cgV3J 0pKuZAHQn4LPz7OCZ/2bRktuunskd6EdRJ1v5rLacATtpgGAjmqEuVu8qlisJcy1SbaTVeSXI4FD 7Od0H2+c4IofOan57YM2B9TdB/R3hq38RO57kTK+UCOwKzxQzSbTAzJ/a6sNasclkJ2sUk5GnjgC eyiW4rnRILauxZpTG8r2v89xtlFWCfybUgoYSLbJCI9QVjjMfoK07DAQPogMumPWa+tV1V8q1UxX laEfuU63CcNVKnsZH6lkvFGtqCMWw595fODkoz1z2IHTQ1aitIU46bZMFdKkMg6aJYYBGVA/8bG4 0lbFg3l5TRoSjPM+BVHxgvWIhBtpgnhIofP2JIG6AOHJv8j1QRQTNVlKIIrMdQB7N9Vcyj/b+KVj J2pzzBLSQhAkrGRLtRhe7gmlgWsOoTecKzcfOILrf3pSVI9qFvIl83ESldwiNbaZoBs3d+i7BiG6 uA5U6hY0yq4efC0mj8yqmIdTDLGQtw2qiSxTOqc1H+r7l/VyBWonFwYkd1Tf+4MZ4JQJaGoK5qPX uedonUEyEXZ55cn+4UPt5BeAOSWCcpIrwZ7SQvM8EKclvdSYve7sjJAmC17av/iD/CmelVB3Ezzy hddYrPl+7QJkHUNzvt54MGvvbwGrNTcKeBivX3HXAo91CAn3wn4LktLHqEOaekYW2F7xc3AWMFk8 HHwVJuQbci7R+Pdapg+YkmN+oFkb8JQa6eUFhYlULWQbEEESKb21+i5Y3K9hEYEDiiw0l55gWyfd CySCgZg0kiw6W25BoHOGhKkA2tDUJxYf2JyuVKctDcaFmOdr9cMjNhQ0z+vxN1whOIXecLTp/Zkh PeAqz9SzmXP1qGhxpiJKjmQiE9tyqtOLe6iaRzfWD7wBwAJOr2yR/EVJD1bLD29G59I9N77+9GmQ pln0Wl0M8/hOP6SvXtbIM+bsJLjip+tTQtxGVSNWmW8a9VL/uBgkLfsI82mFFvv4Eu6gulkUnHgR JJMWTRaxkcRWSqH8piYMkBhwREfhS1kkvplD8KBnVKCN/v3VMoOTgJK8j3/o7CmtzrRYgu3JzXTz r5pjh9LeXhIUr6osU26WqMwLCrD8LfB5Hkf30XIkxxGIhOLDKN1IA2a3DnzO07qi6qXf1jJrRsxD ijW6FenCb2b1WL/wdsZRk3R3+gqg8PWklyzAwS4yzv6lq8aH13yJUmQ9cytB769TvdqgPZCu0LGj GViHBgYq4F+UjAVgX5tyA0JzOfJgF70QxjGOiQ5LPaRKpEFkPk09JONkSBJtBKX6NUDYjjPmABRU iy72cciGLD0sC4ceDy9kiXEP366X1lIO77PnuCJk929YuxwyqSzsC+m2zo9dDzkxcCmpnRiDeLiA 5xowGxpBIAijtSzhy6vDcuURlBKBaurEsgY3SMiPTo4ePaX/bMUKhdA0g+Mvmj92S9IK2PlzrQ8g pP0wzubvcdW4zS5Ice6whT/48FVE1qTBxj+3ExruUttToIUT/iKo2oPu51d70T1IdXySxzw5qFB4 iiJNzSEIIQRDDORnIIEDJS9l0/nO/FN4i7R8nHDKYQ/IzEZnwDGf38a4egNpnKAku/XxIV7A9Bbr 0fqEEJWhFDpuFBDeEquywEnwhoP6TgT998Jmn6n6YTJOqY1vs2piQlX1hxWwy12+ReRubOpDTyPg GlKhGZeEFqxoZsjrKkN0BZD9KFkkX8eXCozzjtEcri/qewc0eHNe3gsJlJfdytUfIfTFNaQg2SN2 RqdJJxMW3LrmlADktcU6mniVXddWfYP+qoDqrUv5MyaLKDnuSUTtY1/DQ0QrffSX/yB/Q4kIfBAN 6a49e3Gt4n9VyDM24GF85s4yW/JGN+BqBSN1kL6hhXIoHK8aoDiPct53LC36y0rFPp4NI4JR/SA/ XdEgeqCV9WzxT+8yfhMOycBuxwByKLwd6cxlqngFEnKblrJlvuFUsRbbDHdVBUfyKVTBZgHhgs2j JZ5yFXoBZ2HIp/vd3V5NRxCSxpE/ErAbigzj9F8bXRl/M7CuWrGVV6lUfKWbFSIFDyTMV7ikrmu8 WAIwnGqDhkybA7QfPjWnlyWYBs2hnamGSld/Kge8yWb4CMemw0U4P8goBKJVKil9AjJop/OXxw6t mmUs0qkmA3VObvOQOs4xCfTCktEF2BDRNDgMYtaR+tJZaqaGBi4yfEZ7UxrjptkpzOwrW7ulBrmN UxTNf80bc/FlC5yyhCxjJu4X9L7X9h863KPy35hxBvroAf3hWYdvQkvq5cmhoju4x9flXs0FB5VH YhzBAWstlWUZu+xzvXgsN7U0UIt025AlZLIMP0XFGFiWPv6MaFouxW+iGavGZV999t+tX8FNnOxu CTqnekr7rJuSDpH+Yw+NmX+ERk4HfelkaJqpLn3IT2cI66Dx2gJO4rPGENaX2+Xj1UYJuudHDhK0 eZhrbAmxiBp4QWpXn+xQWIcuRgInuNlta55qJ++/TKB5EI2gLJnA4uM586Ucxo4tvBtSH5NSliP2 lUAG57GI5tnoaE4pzfB5QHg7Tp3OwM14IsYHkdSFPkouT73IBzEM7O+AkaPP17RUQJ0umPN28d5H e4VuAtAJqHnTcVyMrem4Z3ofucIK6irD9k1hX3aDu362NFSoquhbQ9YLlMFfmyQHTDSiLSB86C7C BfQxsYF8HJvDeUV1JBqbmiVDaxAPzG9rB5bPg1nS2I975lG36FMUIiJWQqZJuMfc3hFB2cHLDiu8 mjEgPmNjDXmE0fEYj+57NXUugSMhQ7r+bIGix+TEzduQMKEjnsUE5agwRrML0OM0FuHCYc0q52IM 1UX4wQMjgl0axZai0L2Iv9WolzUMLyFxiNGr3O7OAF1qFAWZQVMOLOOpEhqMOXIxGAkI86kNwbtA OrKox21SicQ0/g0AgRJkN5VCbo3vqg2lnZvaHRoPR1U0jCFQArx9pMmv22mj/CG04T0BbWd4IkLD F07e0k4gYAV5uO/erS48GIwwsA1HItFb490y+oPZXTI+iNPmWlAEtDhTR5RwmqT1g6UQI1wcXkt8 NwJSChgZDgICPzhk0iCKLazUImrj57xwRXTn0Q8I0CjpHkzQLulRmgvW193obIJ5dClUIeCUWpMl s7lRsREtPB3xS3Oat0U4kpJ2JrqlTq7GnEAvTOmL4ad5SKWfplKjNrQvPcF70HmWyOts38kiyU1e ejHQmGde/8z9ce53oO5X+GHfc4QQQuLN1DGuyKArZniTcbcfBKHOaAkNa2pRhbtS0GmNb4C10rKv bdl1aO5XfcmIGOEwcMgLVlAyNWcBVuYBASeBRC0rXTJODQ0erCxz6daVuk01yNjN3F/0y+hUu0Qy sE30G/JsF2yLtteWHdPKouYeZ+3BH0a29zh0d2V529UgitAgKo6cBUXOvHiQUSDji9eE2uV2Ae94 6ANiG8ssJxs/4BhzWaCxJ3s2APhlCrFUcasKw3f9FE02Yc3DH5YgkWIongweq3DrotJ4Bk3SFQx+ IUXILe4yNS4lCRGLJ7J/25jTJAOvLfn3aojMLXl9Yzz4HziAkwahZ6jO+X5RW4AhxbxdFtGZYY5r ZaysX6c16NkOTDHHbKKhNNXGDj81P9yYPqTon8JN5L4jZdiigntGJtBPHH9TvCS2HPnnEHVJkQq1 YUbIaYEhBiqoXVhAIPVeNUVg0phRK6nQ6C3gOtpS3g7YJpkx5QRFKnf2N0LWQ3XfAlg6gL2jL84/ V9up7w6PHsqXWYSCEgtB8DBcEJenJI4W+Z2QetQtZbPK180KrwNZLLPUk4lMN1sV7wMBBQazwNYL agl2vZk3xE6E1YHnTF7zXd+Z5cAsUNkS6yMXJGhWnfSIg7PNaKVHyqKYnpQbXzLrnO/p+Y5TH5wH n5E/M8x18UswUUoxeRkkj9kqT64u1amEeQYUw1qjPqlHNTKpzoL8Jzn0zvhPpgzl/hrNNupr+jgq UHe4Os+jez/c/pEDV1LNsNcZah4SUgaDjJaf429lECXhKQlUhp/B9k/0QhbKmc6uTSIy/HjlxzvQ OWiI8oQksyzBIBizCDTGQjsisgSDuAo+aaCYOU9HgpcN+W8P88yyf883AimoKS5zWuyIFMtIuPMI xY0BxbIrYx0t0ONm9jvAaXPY9RYPEks+brVKr/MRAjiE4bK9Rr9q4btjML/IGQ80nYvPnLsxlaQ7 2EKzNPwL4WX99AGUcgXKozHwCU/5AYjBQbZ5j28iTdMmGKbtfWRSmfiFWCk4XCmzK2lLL6ZveXMH s9bILH6UtUM6Ih9sV2y8AXaont+WhXqk/xCB6rseBGgVSZdmE74G9D8MFnd36OlY7VeOuyqMIfre H8m9S/SH0CNKlkhkUgZ79eyKmYBEHVHzk0/dxVAFxn9xUX5c7u+Z50kOJ9yXlkLjSfr+GYrsxyAj bkdmqTKrBpYcMQYh36QbGGwSF7dl761uSEPlJS2mPPP4NAilaRUW+8HCrU7AV9LPT3kx6HhX2GV7 ND054SIqN5vWDAaKAiUYRMu0f2lL7MI4kykqI30s/NS9xWMlkidrZ1JZJZuboQ1kFZvIdLLK2I9U 7CUQueVCjiG0B30MopeuBde+B8x2AbUIXZaOsgwy7S4JeYA11JUDmuyfT7K0yKIlJf3MOpjokD5z MEBkeL+f6JDU+DNrunz9Sbqe1Tk5LP/JiBPF276AciYRacFDuryciq8jb0xBfTKPUbr8A7ygIAWP fohzNURHV1ohs5TQwTrcXHW4w5Cje5+a1/0ssPtZ00EHCnd7KtlY9GUJJcpnNoUfw26CpchQeaAn tGzUX5ke2FfGP7vBzJl159OlWd8fwt/8svrxbRSluvPNH98DEL2SpxJvwed/pgo3MWPTR/JayqiM 6m+MARLqan9wq1F5fZhG2udg7j3aaJ8CGAYGNh9eAGtMlLorywNP2NAcew61fqjc55Vs84Mvc4Ve v1lakhGVjYWNJ968nOBXRhZRuc9mUd59KykYf/A7GFoyzx/ID7f0D16uAZjapIwgWWkjcxveYpnB 2c1pk1ak46Uv9eUoK5yrd7BAxNfB8Ah0/aile0XWqX6pMPdIuxzbGleamV/XtoTuxQ5sfaoil9Pd Al6+g490lCMuGe5IFPr3ErFCI+ehGgwQ29fwsrTmbOt8hJAh1RlE8YFQYJvVjIrry3mQ9zQl7kob mWR6DimO9Unp6PfcuaUviCcxrctzbvUYBt7w0tGKACf4DryJX44Pp9Sj9525EMz0b5fe0nyyjPzK krjz3T1rOxraPjtL7Sp2PaCfyKCDCOmS5OeIa0iyJ/JA4lb14Z86WbOINlVTiSmLiF+71afg4mYJ 70Z8KU9syBPE4TsRc3TxyyWDExKB8Booyw4Ru3QfyhzuOEQr9IGFUFnui/bOCbIbPLrB7slDAgBB SdWR2VcGlGFnose8wP0Lb+DuGSXYkzeASi/nWqBBiYTw+bsNtNmO7cyDTYsz7RSGJbn1QRPQ9SX/ qtp6XxOjQWj0zRrjEtduGz7mMXreEfZLRxTsG3Acl7j0StqMTKBcJQZiBPkuSmY5fs8lphsFdNyd NKo6dMckrKp36AFgZwQwFpHx7+9689DhNcRnqxkIBa5ZKaxdtqeoGNbBE0UEH2Mv9kJp7g1GQe+T o3VM3nGzsu8h0wzCXt+N0O0IZ+0j+gE/+kaU7LYE3Uj3C0nSekYp4KaWNHp7+K7+ZVfKZdqHV0hQ HyTOwrhlxRwQYKEp/jMtF8+82zKfSbtPr1kmZmgcdr/rWLSKzq+9hxiEjlp4Dtm8/VAjSxTI0THj KWIv+ZJQI9xXn+kXGQUkWgQNQ+EO7wvh3fK7xGv8k4whFFaJWkeZsxI3xETiTb5iZDb2bgv8r8i2 2ku36162aIdSHZAnH9Q/oYLN7qAS79KI/OPmZltOb8+zs/XrxS7y9zChjDk= `protect end_protected

gpl-2.0

5aa7e346d06f018aa086e3349c58db1b

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/c_shift_ram_v12_0/hdl/c_shift_ram_speedmux.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block qnWSEy+Tfa4g3I1AGf+1G16HfHoMRUTbt/nBs5Ps5q1vrQ2GMk8vrwLhoDLv3qTSjLVzZTeZFnT0 tcBopceYZg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bKqMuqbhTPu5LzXVf8VKSEHAv9TxI6LxTHTlxGAq9U7KBAsUXPYzQgVtFK3fh5Tmgp7m+ztqO8jd 84A5hseDVNAR8xI0UJttZij1LCNOlrq+W9JUn1Axg7HtEnUS1uqc1XApEaFx42kExSQhCqdgBRmc M6aJGK76siJAtknbuG0= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block RvPOjoHS9A/gRj14yo7Xxvwv77pUd6Z1Yv1+4SRHfVbLp0UWo3sPkEYPjSuqww8zu4QZjuEBdaRo z2aH4vsnCDpyKXEcjp5ycCkFPWWnCn3ADlFH2a5x1N++EvVg64mebxF5oVD7C/CBU693FaWp9S/m kZf0Ppx69cNiisTM5Xhl5QEpKMa7e5yh2uyNu/9KgHOlDPnGTIQn09tREbEUdTbGy47WXv7nbmZT GDfe3HhYxsOGSP3GRM6HWM9gPj+Q980zaLA8Llghc4cwk4McaOWtYYHBG1B+bJerf1iLdJejvN6k RMLSekVz3jwqB6DqSfYeTKwSW8fl4uskC8XiBA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KaCegTGHSUF25vioJj9OG8bn65TUzXIOfXSIuhAhieCBNPUoSBGXJd7iudvy+jhD5KS/N3tztWGl e00Ks7YaFHOMfMeUecA8bAj29+xGzaw+RszE+Z3z8ap/TFlTK3zP95M+g3r5Tp4qXNtfIYD+IYy9 +bDZWWip5QqljYuMEAU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block WRA3kXjkQbYPaa001x/1ewImZjKUuOPNOxhEM0+HaF/rhdxNffPCvDYJkH+w2H/fU8GelpL1JtFF LNJ5BaL9nzLybqN00HkEM1ZehphCQh3ZfKXAyAZ4z17yljqjGR9VF5iDHK4E+G7bVkL36u9POKiP mS7ojfYkDlhh/luQC/bojSKQYub4X9dibjxtc120R+OdW+92jxznGvArjBa/wQCeqWXO6BLh0r5l iH32Rw7MJV/I6+oVdkf67qlBvKttmVvX+Izx1ENS/dw4Cb3CbEIJFGbo01ulU397IvUerEGaJH7+ PcyfMPx5OdBucl1RJJAZn6OAqcID+T0o6Vmo7g== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11168) `protect data_block gDDQ8PD6V+LreHVHoLVTrdMvdIcJNXnpsoQuiApLQen5ILMHCLzxy+OKHkglZowvFeJp8M1Jhtx1 1zdwI4fenft2QKxnPMypP4CDq6vy/7aWBVCI/MoyHm24OeIZj4VIyvYcv9rvs91pZ11SZYnf1HB/ C2W0ce441VlAgnVsWNHQ+IGHwj9zGs3Sn9sJoGzZp4zp/Ey0LWU9PsFGdfqcQOX3/+bOfSJK+jZI 5bEfABM3hJoB0xs5/ZGBzEB8RBXDNxiMPJ8lbNAR8RUPmfSrv8hi9TEjWxoICTcAV10G4pwJEDAs 9w3NKYgF7SsMouiy9StoOaoef4oydlXEhQ4mJFq8eJIAnu+JkVPwkTi9aSlB1zUOdcjfnaBty9yS S5PplZMYu4jLUDYzJqPPUG3iXH//IaqgKVnpryINqfvMB/SlQy6wBXEMarGZjqF0Yv7MePEmMDP5 eyqG+DCwYsAdXd0HQhe9vvCL9G/C+2+6sx6T2WXdt4R9CUdyTYbP4PZg49arrxhiI/4X/U1hpbQ7 JPhqotqzO8SmuwhfXL3j7iTOuvjN8tCx0SlOS+77ogX3vc79/w1OKLw7befYUQZtxifBNmLQ6cRX Yvg/6gFhcQ2wIahMFaLGELyebn3d4KDgd/rguuF9HrLMTVxmph1kLGrStd+2976yyrhKtTC5zaIr 4LUziL0rZpuxuJOsxI7ly9Qq2Ng0QvR+j8lOZqgfWpSHoeZaIXMECNAShimRrPpfFkPEqFnmBg/z /bGrHOCj335AVX3E6iELKX/BAGuckGtWrbAb/QOuFNcNzUwussLQtATlaWXTmaSr+cA74xI8cO5r Mv3SRa0JUV3SLfbr0FPFe8IPIlpTqmkLUb+2yaQUcoSoD6uBj4D3CcrgUeiWspaWCI0UL1FhNnI7 c4Tax87uyeiZAetGvGnmdQYauOtd5sb1k9b0GusYk7r1mwdR8FzA47jxiGDbtelLhCfi9p34gZ7v xBTQ8Dcc/p8UdjvWTJRHObtKPdtdgJm/qWSjzti8uC+YBb/1jm6IzwcjqSOmI8r3GwNgOFJJ/S8G XkeIgh6xOpi7bsB0+cChGGLBv79sFcrQTlSC4h8E5N7aP6gsnohAgv7n1acnR5efOClwdCH5Rh6r +Jk+MtI3P+3OQaxSRDv6roefW468Gd1BirErR+/vdzedB4ShWr8B05MUriKc7+r0+lcZ+EzAi/Ms Jw5jaMAR16Y+Nd5iJb9kRbs1n4JiZo+y1iGL0F44yUAdCoCKrP3AURc2pbZpp9py5GPX+onku1Pm StJycXJwBDEubwy2CJv6iUlLcu0QWYcxp928x5TTmGNfQm9JP1hsArJL2RXWuIHRsD9h5iBkZyxX hX5CuTYeSIXX8xVQzG8C9Kzy1N4iOWZOFe0oYt+0bW+BI6oe1KOG+BWnIyoCi4+C0SzKKSDOdUW+ mW05mYMhNoRKY1zWiN8GVCNbVOBQJBx+omNp7hZiY8d7XKcNEJaGrpSZXqYFeQ1gEhBGqi7oqYdv eEx9VmqpwSdAb4teiseJD1Kh4er7GhHOSveRITDsMAaDrRG5GBuDDBMqvjFr7+AKgahZH0lyHrM7 Hm0UEYP3+wkFonJHTRMtFhHgbr9VZTa5JzT66+jTm+LcyeLkLw8C7nXQxsnjbmkGD3zXoso801dv tBtrizZxTI8NSpA50rejtsp8JSvE5G2fiVm1ftdBrW3VgNGgRq0aYObQU1ujVE2SIiiji9j/NMJj eWZHKm77hLl+x374384MrlN/k6V4aXHGIAeO2JvcQV+YEyVvvyPCqANtXwa57G+xGxd7mH1UBEyN HqK+Ot7bDMAohaDLzqx26Z/CytC7j7csTmWHP+Zj4YCBS8XWgitPHNhIWlywsTWbJV6POOy/lVmG nsO9I32bd+d6gPn6u8528R5x0WVxBizdix1UF+qvYyjLnFkrrk28lEQHz0t3gb56i/11z/JJA55w I6PsfEUaGyNRdsgNqEq3tioUxYLu+J+G6Uy1truyUVaId2wjBdki2mYqylAC4hEBcEAr7sXXniFO ZCkBUvNlfW3hkLx7nodSZg5/WZMUA8PXg+Wra5nn2ys/n/pBTylMiJvLDe58/LAdHhdAvwM4077E onrzky0Hj1kn5f3q/o2RmpcG8HX3lGL+Uct54w3ecvY6vaqOq0mhSq39RrqnLjw8Np1J1H/ziB4K 8wRPrp7RWC72qXW2Q1Mz2xKBKwknXPZFMtl3G5w906vSYaNACBHMhEmvey00CsXunIH/0Zcl0+bA RR23d26WuCiWjA0PjSsL6/XHVv36ucSGMczhdk1BJ89A1wOsZhrv65cYx1VSLetvOzdjY7eVRmTB pX6DjS3SWgmHK8NX4unAc9dTR7ybevTK15PuBI9b++/fzcgTMzRtotFUzCXwXGwZouesfr+BuX6R T+QoZJChiKwTmi/kehW3B2ZqIymBr3PCzn6mKmG9YaoE7nM/8ER9GIoZDR/bAPPfsuH1yk438dic zgpu9fyg9CEgRLbeHf5WO6c/35HL8NgjGvTO6IqtA9Q2Dvru3S0pTVkgY2JqVVwsLyuEHdSkdJjA i62Y8i66OAM5mC6LWj+n99fqVoMFRqG+XlcC22SdmrZUu4Lq4mbiUHXr1ZwWPHUvpHAB3M7wkQST WW3oTnKFQCHWarinXE+sSMHO9CpySHOvxUpN1qulwVhJgGd+tYDYDijtvu7Hs6/lmixNSPR9C2o9 H6xprmIeRc9VInaCxz5c7p7pl8YrSIveu1DP1NDo8uRoqoBz9r5VocAOXlRxgBzLSC6J/4Ub8eDX RLZlYSL0VUse32bkRRexISkwHCBrtU7IEoueFVnEYksReWHkE8VodGDbut2PqIKQMX1s9vq++zBE lHjgwmOvLCDoLQGqgyUgafBoj9PHr4Dp/nZ7MgQ865XizEeHCHfbUnwLnxVjQp83U/bnvMeUKFrd xLvk1gDymx/6BGaNWVl4QCTJ9Mw3bcZWPloRS2NppaYJVYZ13ffR9xF6M99QgatjHXDVXGa8Mc4M Gw0JsArFy+xmtiYwBES7eUYnwYkZ2P0zz5aHJnjZxPblmzWWW2bsn8BK6zwgyxebnzT+AaIDJNei q/SC3GsX+7ZRhr7kFSUGBG/jNfeUXtG7tPvA9AlMoo9s12ZK6GxSL2B2fa4OzMjCCRu8MUdgk+Ud 20vxOGjWsRFIz9tMF0eCJ+wPIuXska0ct+SeiOx2m/pvc954vPO54mwJdMZYLtOGnzDI2pVHt/+K qMfU8pv9qaxxMZ65fNwtQfSumafNAlzvmcNLMWFPIaMD9GQEsGm/Bl5pWVZzs0Iqwu0IiAdoCmZF YuYzlfu08ryeruLrKSbHYlG1tpOqOrK8dN3YHx+a973c1c63opmdSU2xPPeoJYOoq98UxkeqWxuQ 9HC+X9VqOXKV+hncbzl0CdXQItQAJbO1vRyWJtutw5N/Q7pwUQ9FnzifownMKVNBTrKACNhMXrLA +zKDt5/RBAxNQ1YpSjMmsSE2dSnvKKX9uJHarP+FZCAGQgfzkbLANerjhGKFilDtB7xNadh1TG5a uNWw3DpzPan7DtzpBh+YtJZQcSn/sVvYhPWkGgUztQFGfQqP8zeY5UYTYDFlzfjwwNKI/n3rxjrp mqHErugEA3NA/mAJzzW20dmWyabEUAImKaiDSXzhprKwDmW/trq4abthLyQmBqCMkph/zxQZzdBx kCepMVcQWYZls/Ua1IKqUh153ikJuloLT+hax/ZB2bXSmfyZ3QBuc+Koe5z6Oc81FEU3KJHt5U9W jqSQfTVH/QmeyaWaAhLs+P+7UGoQteWnBkyqJp6aMNo0cWH08MI+qj4sUNKAYP/ZRap+e7KYvj8z Xk2aqwDJUGZr4yZC15FGYRBafEIxdAbRlQS09a/rqHuqRfTmsyx5/Sw4n2JwINSryU3YyJy4tVYR Gj7d6nh7li+e5dcOf8mLucXz8mdARUBfEvATteoIF/7UH8vVdctUTtOcYJCPjsZS5tV6/Z97D05B HDwGMB2XQmYooIDsyp7dQfGWSshxF0gpnKneh1k3witXSMX7XTuHYnSaA1MJGCnpWwL/SO3EtlVy 1CsKVzDv377fgxW843T4fXjegnJZNQYzNEwJ/zXEae3xrs7E8KeNh3Ofz8nWKP5gMvAtRNhqiAbr LfrfeszdouPUaLzJFYxCyLWjbjRyhLUntJUmue0CLLGFHJk8r1MjRBqlUFEi7y96mifiVO2Dz5TN QD42XGm5BDwelthEtvDUlufDE0mSBW6oNP9Sl1BEQWSeQnDzL0vhl4890xPLeIBzSSxnHMBzXAqj 6ILOW3RjzQB6Ee4yYOG0gAupAtlFR+Cf1SutmKb+ATWJLj1EsP7C/hmWDGbBCIsboAHv92Wa6bry 49zu+DhCB68ToPOcKVqEa8lh4HQvn2/EAzRoBJl7wWbgypbexFyE+JqSCOPXA9VeelfWM8SHhJ+B iHob/9O6a4xcMSG83GzA02/Gb6IFSPWvG8YOln3T1Y5Vfc7K+BD9FWKPbcILLJhU6NCVnxHa4GiK h7YFIeOmAubjHleZU9BvVfC5k3ERzZh9U8Mxom+7Hr40DLNPaORp5T4NM0XIAF64NUize+QTJjw6 GUbWAgejXOQ1WrgN5yuukxYjQMlk5ozm8tl08uo6VsLTSIV1zONH9I+XCS5uPEiZbPxMMrg/I47r VQlp4TnQxV6uAM/03ioLwmEeM2vxTQQnNX1YFExKnVdZ9H7uPQmMFSwdiyX/ukcMgG+HWm5e04Hr 6EMrPeJRoCIInq66wwwH/vWAmg0LLKA2YPgw60Vymtyuv/+1VSO8pMTwzshnOu3NrGavj3qjN73O 5i4C/0FS7NZxhHf/bm9YsOnr+nUW1+s8KP3ZlqVat5J+Uo3/s6V4inrLA6XHjhwZh7cip5my5Pnk jXnsKHuTUxJ8mqmh5F8cv4MLv8EoAXTDqPlBL4e/bHojP1+G6xNJYHYy/JYmIlCt+YBjyUhU5hmB Wx1xQBT8X12nRAm8YtmL+SC+5Yl+rlJWx8pribbxDxtWvbJAwicECTN1ZFPmOsODp9K9fdhD59p0 cROXGLZakoT8M8Xuhk79aurITXWHaJUeHpu1ZbuuTVYz3Rd/BwHjXIhoUQ8cj6W1oweoGbzrVPIq TiVgHzIwWt0WrPxJkRNxSwzqI6T0Uxr1BolOmGacp4gmUvKEFhFhiS5jeMHDcG5pNo/5IgHlEYdd Hrw6Ep10hUVSnw+MY7ClNv3fuTPDzkPw9FoaoCCNUR3ygF/JfpLGxj8awqnsgQBMWwjU/shzH6vu YZ0Tm1zyDXdKIjyeFyALZ14kKsLUZqB7ypJJMqt4M8GWK5TN4FqwNCRb/RoppLkXnceJ7OKLOFck 0NgLJXCxT4Tu+kwLi+UCj0AaXzkHsXpDtKzYx31jnztaL1PWKVP5FK40ZPPTDfWVGQYsHoiEqGWV NFiwIHePZkPLrSgGGuXMLRiRhqd45BkmpYrVY6lrWyQxgR3HkTBY6CiZl1Ui3AuQ4kmSMpMdWoaj LEpxpO67wt69Zgl4qH+fiZOU3XyBa2p3uPiE8UHdswAsLG6LqNTwFNg/3JVLaQ8CVEsYoNFe/6tH 6VYZUCXHxvqPGeOasckU4DklnKtyEN9rRfqy13caD52FvjF3yrtoPqPDf0gOiwCsAfhpcVs7so6u w+4n8t85H4lax/5HiyL6+DUcqqLsCDlQ4BjAkANtJ6qlKUaiLxQP4dL/qlYE4TA5fTDSBSZzVu09 ilxDFwFNVX98yTgaqseYpbJiV1CKoqanVRhg5X9zAMEJwgfJ1jGZbn0a/oFaGQPp7eGAr3rqkPtR 3IuJIycSAw0piTqCG3RkcKk1sO5Iwfkhy+XVd1dsI8KegrRivpN/hrF18SvTgb/efs4uYUuKYexf O7Ode/M7o/JFN5P8BP1CsYkAtqA72gq2x2eXYV2erX4eNVMgypqU0JcdQjm6zUF/fMVnfKWM0STT JaJpvPqg/ap6rDung6Q60ZcFS6gzY5gGsHz3h4LbUnIypRboU/9p1TfC/mfvw/7xK+F4ssa4sgwI PLfUljD3vfXmQ3QfaSNt8FRCo3iT0x1rq7RpZdt6s8+2YY8AonE2Pn4TP9KbQEcUowkq1PDDCo0p pXYGNkzO4RgWbJ6C+U0OT700GXAokaTLVMtIjS2+c5vmA2qs3Ii8rjqQelzxpime0S8SanDS5p61 d3JCHk3BXrYMYQSBVP/gGx6O9ndebDxlaxezC32X4C0BVMkS2g2474PI7hFTWUYkFMmY183i4ci0 hiTOtAqrcUjKFHU75UnMPhLWCMMoaZlbGehy8kObBAhoMSQrER3C2PR3S5mjlndpnEzV35eKq846 AectlgbjcsEGibuIwbafjqycmuW85bsh4dj4kfn2u8hzJzH9V7hQz2wwD3E3i9TysphSMyQl+i5M QpK/da2LicGKRQEBD1Qy34TzpKwH0JY8HV7jelsLbjxW1ofkFcH1G10Be9F9IuX0R7MTseG8VfGV Ca/YJAyfgyQngGQGd1yn0S1W3eob6oR0mGWWrrKGDhRctP5oxMhTq9b2PZo6ZsLmDs6lwguagG5r G3EiN/12YZFSU/n1gpMFyJw0nDNWqkS17EpJlyteWK97jYVdSk9+aQ1nNihqxrjT/x3Baxp76ROs dbUunB+o4bKrBAWWdf9OZA6pHyIe3gLSTfLiNByqax9O1gYmPhgu6ws6AZPXo8MevUlAdPlzbwAY UeB3HITFlMTYnjEeXUkS30akyT3U6loHwQanbQbH6mS1oYyxA8NKPTBtQEtm66K0lPIPUjtihL+Y Rl4336RcvnsQ/JKHQsncYIorHGFTlvsqemngtFweWnmDhGUJr3F4Wkmu1Yo/I5Xw554oNBqu1BJK wcq1UaTA5clXXXgoAVyd0H4QVw39e42pH7N7qEiiAI8b4JeY82lHVo5F7eTjHKZQRsYjm3GWjylM UO0pPwFBZNitb+MAOdEuChfBLcPHksxZ5BA6ZE2lqFYKQK375KZ0GYnl/jLP8Ny/wvBHOi6RcO2J 0YT7TkdTa7PBCmIzd9iiuIVlSN1yv3+DVquNThmEFE9/4gGQ9iG4XKEEBtYjwQ5M25xb2TqUwgw0 arK+4NjHMNpoi2pgJv9ns97qLDxxBp1olJFB0b7yjv29Zm5TwIYqQJvucGHccaLJkdPmM7kBL4wL VS32RTo2Dmj8lD+KMTZZCk/2bxbvLurbP3ixmKUE2S4wEN6rW5qNqHBwJPVH1UB/ktqaAx0+IJOm EHD+Ov//eS8C0MUB2XiMemlysPm2f8gJZThDK4M/bY4Y50Fk1EtILX430AW+RsXOK9/FzmQ0p8tT QXcY292Op3C2XqXs/M7cXYdcZw84DfV8wXqauX1BIhqL0U5Qf5jsxBcW1QmIA6W+Bd6yz5t6yRMs pYNoa2SNIo7EgllWNBL+y/6NanJBB+Y2u00dcj5wrVfoFKoHftefOqGJSeUhzi00nbj2oRo1kzmr Tl+OGq6wgsp2UWPjs/qhqpUbtor/OASV1zm9Aa5a7PW2ZhNhRB8zOnPM/ONze3q8eIBhr634sU8Y oYsncqrKuRSYVkPUUtdyYFnLNY2jaLkrxnL/nDbPEXKWXXyBcEu09al/UY7xI4CX4exxZuXS06U2 YS9j+i+yHzSjc0ZcsT0NMu3HZY0bnvQMwkOMVzwlbnlkaWPThtfSDgHatTgri5U9MMVhpa1fgxHd 1tkecR51BbfrZvf6ZP3iiV/gXk9yIAbjTI4+heufyoq+dEr0Gls1vD6TV+x5zMd6zTGTGb2bxiEn Sn4WCas2UIgcVbEx2e/3AGwLw1fbpMGBi8UoXl7+torGVT6aRdj3u98/CgFpR01TrxoqC6PtWibH EBFPvojFyAgRYPEs/plP2TR7Z9gI5vphRSpmZeOJKALbGD7bciAk/ocmr5sPnUNTGxqJuyaJC6w3 B7ZYR/NMm/66Y8a7/tH7xJnz4wf4nyyMCltutQb8h9Xp7URS1xMarpakZ5Nl1R6/iebJQdyf8hLo sBb7geEV5yPN57atcDZreJ2gYJTtQJfG90mFo+UVIbkCrQAvibcPXPouZ7ghOFwO7L8W2ciGTnam 7MHiwGNjjyw0QCGnDuWTRHMq2E8ZSwpLdi/RDMMHu7nuhBs43/D3zwcid1+6lqiBHV8EuomDYU19 rTMex3WDWlSxLIIGRfIn9Gux14SHPObD7Trh6CYX/eruODOcrayX1wt14i/7BFhIyBqi5RNLZYKq TiARIzU59sVf9wUS4KcrSkLnLhA8Y+TjU/ZHlP1LrsaL0uM3w/siSCnV38sq7ixd2hF72ASoee/J Wt+PiZdqyx0GSG2B+gwLDlD3DmM55AMWSYzlHfgeZqGRDiqc+Mpn2e3ilNHMiSo3NQPThTCvtaty wsfYP46/t3HKuGYcGOBkr9xePJ7ohQ6IvPQoFDvPk+YaUgOMCDfmhauag9+TfQ2INdhuj68vCM9W rfGKTXjy8mHTJA76XMe33ihERPDM7SXVPQFKOZ4FMFlSBPi4CV54rNCveOXwD3mhPI6ijMd+SQj5 tkr8bttoEVt+IzSMGFAWZXBwETH2xLx20W5VKzBUjT9LFJYLg+W2IGHtNPItqWqZJIT5Qm7ZIxoo MKF7Q5dYiEHqcYl8VnqP9NpYqA4fiilZJE7C3imIJXXusgOdrsRj92aaJ173VupBAakodjj2jrR2 0ZuJ5Tc3wlifPHO7lfcz6TN3SILly9YZkBm7LrJf3OAVJUKY25zylEXnAsaTxBg/UrFcS+N32f2C uaZCguZV0wUokERW37BHuY31fguqsjRGviQFwSiYJN2xAATeZnX8HSfl9GaO1jQfTzJHK4NBQYtA DwYd2y/ijcX4mXp6ZG2gUpIjW8/4pgAvNdO/8wmUgcNWtvTPODpT2udO/RAdKhuZO8zIkLa8DpU/ BAK8kLapYAsjliE4PC2ozTIxaNh8r465vCjESAPKkfkV8o+GUIGphy81VnVZNOBYubYc3b66lW42 BPz11c4M6EYX/+9UhEKukyk2BcyG8vLNUAgpb2DR5OghZdaBg/caKvmgVQtRjT1GHwIiBKm47WQi owo15evF5bDrOk91za43a+mwrSb/3YD62xL2UWypmmuhUST/rRIg5905E5eEOnlpXGqItn5XIix7 AMAhSzq4JaXyGK2SzWsX34GHM7V+gUv3C4JPAkZCyR8hokwViEBM/AYCOcfGfACL3bpeZsLYyml8 o5whHT94RQgTvJNbNaVulQAYcjBNRoguqtAVqIxzZ0OxDQXorAXScadTCsr/NgCr/Xhs2wzD5FXw 5iYcD6Z88F9OohyIMLElzdEdKLJPtftoVL1J1dS+hXYKxA4X/F75uLTQAjP4Xj2Pcw5eGOw9oXx+ C09HU6Vdpt8PmeduQMIrdybCuurYeOyj1S9s20LwMh+Tacg9/8wLMWUydLQMOVBe3FnBU7+nwgwu /mtQFKlR5JVLFoEUdVJY4SpyOUgdrHcfITriTiB5CQ+b+cfvnNbCH7IbjrS8FKot3Tf7+vA3nV53 cy2NWhzJL/YKr36rLwsaRfNpFZLVwWRSG5Sdi7XL6A08S4MC7aJ1br/PfC5S0K7R+7/f4RJO7Luq QxDZBQbztkuiC0RkcaAwzABT8kiZ++5BfINppOrGvCR69C23EjIIZc+8P8UNjgZAmDUxbEqCUOpH CjAhfSJJEd7Zh5DXOR0Iiy97fBwvyxauYYtrhqL6hGbJ3JFvy4JkqrrRIMnOc9GGKV4csUmdrKSS YGslqgydmklFdGpTmtOffT8U8g7nWpuuWcTxtIVC4psgs+nNfWzPp+8a8P11RU6vj8ymtsP0jNUG wJJqXjQPX/Vx8aHARwpi/b/1z+11Xlfg3mv2RCjmmsa+t0880wCD3zn3YIQbgZ/wNkhYuT156Y6b HeHNX7fSyMVKmkMQE8z6rlnsWlrPIrmqTWcHj2fmVKpiAoWLwH90c2/qgsB2gvn0VkutCqj/UuQt 2zqAtblsdhR19BPaQlOhA9Ey4+vRTuJEurHVhLSVCcIekke7+O3oJggVR33VGz9RXXQkKWCFjiRS xo0SJB6cuYmzt6AID3+NKbTzjS8SEdquZwq0XdHDdu1kSjgxvbMeOxeF8t6HcX/UjLRK9qjTDpnX h5wGNjRkz4uWUdBm3WUbYsk5Gp6N4yBI2hyu9K/I48ute8x55jnvFBCNMhHqbKmfIg9U6UwMhSeY x02JEc4VA0KOoBIL3ymiv0y2GNTf0Bouv+bLmRRhK6dWBZdi+dULq9BS6nm/2jW6aS/H6LzS2CzW tNuDLVozaZB9InPRVOJv6W0QZosXGUEgNXqpXYILwyHpyPyxewV1nwHT8ABxshph0LQJEGE8TpPz IwW08tPwnbCiuDn6nfcmX27T+0catIxNSdO6cnuIVZ/DXlGp4Cma6/O5rmVtDNcRws6okYQpGhpi 4dSe7zPvDs3zXNOqcsCaKCnqcQ8xAznvQeDb+ZK/ZejAdpaTd3FkAw9CepZrDA/uQmDjunJcRhO5 hEWXyImakVbzxWIEK/P4XCHsvOUYUWkoP7jWZY/koo5Zm/PaO4beBlRoMkhhDUAZvlEGRxiXgqQC ZXlTXn6PgeB8X6+MVogMI6Xk++sNZl+MFmiWLeTabTvM9DY7jzY7Ykiqt3uG1doS3uvl/soLlvx8 u1XZ6lsuR1tGcaBSbnsNoWSnKY2DwRgZSkMystgRX07qPaTawnPRWnq9bcSAnkRqmsvaRDvuKDKa USje+gxM6Zy0FmanQVaAD+Fq0JekfQYW6IxgDHdADKHmt8n7Vmdzdl1dN0GcnsVvkJLjBXCImy5T bDuihi4xy/iJzmP106oetC/x32oDHYrBOfx6Ds6lZtkWe+iDGWVYd28M3Ar0XsuEnd7EsFufwid0 A6MNyMvlO6couLJmn1WuJ2tvSe82YWx3LZEW8O0RXGq/yye8rSFQNN02/jHDfCGG0k+U4uPIiWXj G/MNP1vfgH5GxCDeAXipk7ABt2WENx/9SS4R3ipmzrN0wv8i49l3UH+gVEH0IXzBeMxubX6Z74P8 g/Leu3yPtKmagHdyeDiscm0XPUeTjzeTXW1ndYcdoZdfbvDrGq4aDikIu/eb5incBzGSx5Vp0S0t 6nNSDtMMTo6tHsf7532tQag8dGZXdoppSTgfTTymnBabsGJPrdp1LZNX48p5wCeyNLv0BOy8v+5b oml9nCo7CPyBgnsDG09Zp5DOz6fWyKGxXNxqjizWHG9WCIPvAza4ZeCuGu4YCgQEyVPgbQ+g5UTP SepbOaw2mPL3gzqoW/3FiX62BmZNpL6e8ikIj/i7QzWWT1/VEqA6IhhYTnv1L8yBozrKyLv/xGF9 wd8lyjdIwY/tRil2DUO0RKXfnI1ZPftdFSTKhUxuGsv/bHQ2aqXxE/w+kSGC6z0SCBvSrtt06VI5 nY1GuYO9ezxfsCiCTle+Ft1YaJB2wGxSJPAC/WQ+63HdS+mR0VwEEf+N3bamgogKV8KfNlDPqqO+ CQmv6s1qScGlhO5L+APGwUejgjve+uleH94kUETrl3z7NWKCnra9fJb4ue/jkBrWYvuLLV41XXST 05ARFLtFtzIy93oKdagcaIIm7ZFwFrvRCxdbYcYOq7M5s7YVV8Nqxy8yyRV9ZzlQ8+HsIgQpu1tU XupCZ65W/NSzav1j6IiUftBwJff6J/lfs1NsBmzReyMV9C9CFyxzsVVwUZNKrGL8CpujZ34mkxFp LVMaeZh8nTJhvFoB1jQ6waBZHL4i378iGggRqnYF0Bh/3f1w+BnSC8bd84qMgD+ZdSUhgZKt08eK EJXyPRmqia+KMDw2s7Ek9ncACc5QFfxNhFeR8oVT1tXTVTyrJHozl2WBGmDTF+w3QCzbLbl7rnVI Oy+TUg1uA1ar9xW4fbz4lX9yT4bt9v/fsq0Lwoyr4qv8APXe6hYUOw+GMTa00JvuNJ22T51OLTj/ QSs/V5B5/DM1hCCA5H/aN1V4scveZqVa/NDAUuXCEeP9vXKs6A2ICNA/D/zynBf74eVMUZPP46BO PTO2v++HHMrG2aJPodozZvV2FdFcEd0t6xokdJuI9kehwwcMQ0cGy+hXQD4lZ67T3C8Uw+A4pEF3 uXt84u/Lc2ZoNXfBRhIirmigy6JRbM5kl6xcg0C8IHfE7/eiYUoaWv2bFBNySffvBfiWB3AMX5Jz wsZ82hhDl/3D0NQSgvpg0x5h9Irm/avJscJXPnV9+4R+X8cT4oYu89G6wAgyWulCdT3M68NoqFh9 ZODnHST+6qwv8zukQK+1LsUoj70VS6RvONDuiRWpBmwEEIp9doG31lU8aY2jrkOY+DmQOWR0NPTo HvBo5T227iVvzDoMqLVIj4zvGq/vHAY54drXjnvSO1CjEnBr963AZvNHDioEEnpHQ+94JtOTEBva prkQDbdk1c0YMSyrmOj6FTHyDQou/KieLdpp7MetdnEDWE4D7tDRfiya/r8NrCIEdUGUAmhFFPwb JNB9Xo3WifbS5kPdjD80hj+3R91KSRhIO65A7PLevjfJxahREQyG6zSHOs50NGosQdbDRV/jfpZf hI4onDK4EEmdOSuIK+o2Ocdvkb+6dE7e88ZcIGwuiTXaeiE2Om0B3IXsi5u0vh6RlFDsCp1ZdWOK Dvq7K57KP7NIf4S0s3AqmM97r4lNPZxp49xeo/38N4NejkBGO8FUUyeGtFwUUkbDapk5dx2/rS/e gYcsVZsktcG0u4osSEf74Rjr3EG4FFssMDS700X55evuleaX2FEXvEIM4mN225cZGuaPGkMWlA32 J5P7S6Q+F04ClPc1IjiUAZ8kD9hROT1Y8ItFTt4ekxW9rt3pWwBrhuxgOszrgdoUZYU72P5OrvOs J/32GzwUzkgZXKvdkPbvP67NrmPXq8yOixlFDrvZDlK+cFyTPqIlBuG3Io38QAjmrhNOdCI+T0HA en3GmAs6rI/wYiGQcqvh7pN39LcFdru0VGx5O4B/LaNl4IOi09qteBB/e8bZX+sqLv3eJ++sJ2R4 EzNXbt4RaQQ8tHcA5l7ff5J7r9/V0sRqn55lhIPwu2AAiq/W5Of2V3XbikBky/CDIYdzdUPr1jOP QRm0rhZWegJyRxE22Gi6yB17noqUCI4eM39XwUZoYvxxnSCN5S4ZeHw5GKnVdXKj3Ia84i9ocpOG ENKcTV31x0gkZ7eHo7b96ShhL3W8dcLEjNV6kqUvctpcBrx+bGvPbBfd6ezFLTmfS4+Lxnknzs1I IzjOoMGKlLCuUa+D0SLCZwQBZDM6e5aweyO0rlORQtOe6zK05nx2dHjrC849R/AVryHnQFjD0NWB r/D9FQkbx+ILpuJBAit4/g+kiFFLu1ZFYclm3YXveVI2do0vlO9rysxmwwGhUA5uavHBmfaELB2u zNUi6Y5lrohYFIfiW/kehs9nFTnJz/2Ie7MaPuQkjyB0yhCdSva/4a0qP78yWhlmn4Dy0wD7b93p z3AMxdk+Pi8l8ituwcMTl3yzTWS+EMy1R9VOIEB+1sk8C6x+3pIi+xYVCRNrWYVLrXjczLmy+qdW MwjpJSQ1uDTny8FV5Jo2rxuZvY2cOWfDSLiGb7RYnxK38yiLYQeo7hpqPEHKTR4hH1uuRR/ZRidm aJGbyqoYeB7Za/kedng2qP0N69GmNUYwEuLFPUQACdHwaSI1RJhE2kadAhssR/V+vwCJy0Q0BYF1 dTAddXPbdM4OFqXsEQUmIXFdPju42lWrBUj4WZ3YpQAcv6o0tqUmIh7xID2HG6tYXXW3TwyZDZgX t2BxDZFmz4Ic0fu+6RWD5Kw93B86f9TiLcbcU6qnuHoMuIl+eGg1iv0ZVYjIOBM69hrpg4xBgzsQ QYAVNAExtp2B+B5ubZcZ2Z7ct4+IzcKnmWWgM/70i7/AvJ3qTK1cDQ/DTQZ8Zwwl7iOL2F77Mp6d wFYVzg5SM9CZCOJ8vDCCe4vAy5lrlduyTaN6vYE12rUJxr22iXifv/avQjgNxkVUewBJ6uujgLv5 Ml+oi1Nrsw+dGABEKI4AFBTviVpDjoAik1L+nrmRPnL76nU9su/tVr4NJAw3RwjAVbr+zw4Y3iWX hQ8FRfJ8B1B0tJUdh3yIx/2YcCV3QGI5xxuxOlt/lYdDM240Uu6hzKecsqgdwQJCb2tZS1NrgFmD to9DhsuSpwxWiaivrBuTKF8vYQ2/X6U8M61IbNqv9JrXX8t4qw1u49jWAJGsDGH850fpLrNyS3fe M7kPXQJcICCeMYKzyQXCVeO6QoUHMQP5btFQ7ayhtLuixNthOHP5eKxTaFis32DCCXkO/CDhWSn0 LCMpsd4vQcIEZ4lyzp3VKfgi5QyUGL0ZBbk8yCPRU6Ln50j1uwnpQFMXVBGcHzCsDceTBG+5d/ml DR9jO0VuiYtvNSF2KI00MmVtN/w8SmLprMSR6uCK6zoc/2cF61le9KFAFZPryPaYbghzME+k0Z06 XOiNAQuxulnP3fUP1bL6Y2OVZiZmxxidKTlqx0iUlVbr+gHuxtyLppjBgQzC2AaBWTH7p5l6KKib wfvPqmkiio/1u8K7jUDAmmCqUnKCuWSMbTaOrwxpMYezD0IcoUjdNhs6bKx4w+Ac0kRd7mHpshh/ /qoT5NAWMygu56MqCY0XYzA3SBA/jdUzXONO+jy4Zmm1CUryzzl9gaX959u6hGNlw/TAiiTDrjz6 J7uDGes4aHab4zsvu/QIopnqTPA3yjnQOGf1HHyv32kGnIVNF7Xh0tZnWb9o0KAYSuUvoZKwzfau 9rhzQXGCNtRY0P+LKLH3E7m8EibIr3jrbWjUQGlUHyYy+DIXYczdkSRzMbMpGZiNxjdELRw= `protect end_protected

gpl-2.0

867fa5d8c581ee99a8281cf37fca8795

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/xfft_v9_0/hdl/twos_comp.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Uq1Bg33qZa2pXc7Mdc7Fosl8MgjMdmwVBFXrvxnQb9XnWPdP7Ls67dPiQR2Ht7jDFl1KCYajYPA9 yZlPlTZ1ug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QpII4XczNotEI9QcV6FyK0xMaL4cD1CkFRExUvEW6EMNMOlxApbMunLfbh3+nWEe6lSJnAsLdwLe P9oicl4PVNXLgw9O19hRlry02xgXFEJ7BwMw365C3QX+ad0bhmW+EorLNYaH3kt1KJhHNb0scDGv DtyLca9yQc4ifZEMZCw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GdiwjjjM+nhyUhOyry1jT9ufQYrmPPiO42QaP9amACA4LLEvMh1iSGw5FZk7YbNd5Uz9uzYST/fZ ktFytX32kOq4sw8N1C6ayNDhtjNk1JlOAR567b1IF5VXmOCZCO7DDN5d87oHaVkN51RANXAFav8C XDoA88JJzy1U7PbNAGCi6fIEsluiV13K7REMvZgiIYNzomMdcmapSNc4nxnzsU8sg+KUCOq4hNVp OMQv05oXhMwVS+zSZ95ZWfbAtHCzHS4uEhhlTusuWiR7FY8g3rYYit+FdSaMpRg/HWhVY6x/gnks RaLrJz+d6x4z4tuaq2HKNFxSI2esIW3qgQCP7w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WJkzYT92F7JgSLMfs46NEL84E5UFFeNdH1dDFDpJvIA5N5hBbXjEiBR5C6QTVDhEEiVaRU0PuPfn JpzP45ZZYrADvNwluQQvIek8uNfaqqgB8CX0HRsPQyxBbFt6nR4PWaubAioZXiywFoAdEBIrbFZ7 E6EZW4RIG94scrUw5bU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IZPahl5nrhXLG5zW4y0oab+rafgzIMbfqe4s7LaWecFT90keMI2uNaljZtRDktgUMdXNBfKimkli meHhJ2UPvdkhzJQYPmMI8ZMEZwN0DSfX97aMOuGO1gaBHe2Gt1bzIROdz6l7WCHaVUrFCeC8+TXD 5Gs8HxtirLPyZGYH3LWMwh8/P6+k1zkgwD1TQEy3OXooyzBIdkbP5yBGw5Gh56hGrd7T9LoCSE5g atQ2JdUzqJWKh+B/RcFvnOTewY+q0BtsHppd0cFr6fHr8Stu/Nchna6FpKEKdTu7D1Cu/moaVV3h baCqRBLHcYLtnxhCG8u6yQ6X/yGJYi5v+QQ0Hw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5680) `protect data_block fdpqCfYhJDfD19x27e1QrVKXMyA+54cOTQYMl3DWmmQ5T2LruVlfO00Gv7IlNSGF0j0yjORfZo5X kVJ4QnPa4Nf9jZWja22xuUNuMCH5B3vqaCnAG4zBha2ad/76aNl5dwkwuLiNMMx0VaaK3cs4oL5X XgLNlz2y3+dgk8bo97aJ3RnX+xyoDzlcbdWlGtOVtioobz6W2GrkiLzYcw97N9yVKj7udbl33d7d sDZcjfwybV24cZg0zVhXvKYB3PYkJ1Oqx78bMa9SiRitHxB6X7ICZgU6bU3FpaSjI4b9UR61dEVn 4N4Nv8Udcn3YpO42ZGQkV3ZVt9hqfpLWWQFNB+3GMfIHyTW9GmXlYLprP8436Q3j3brzO7Wc71eD ImadJTmY/bjsAPosP55qYv/g3Wpexm9GDBnD3OjyO8o9PCsC2k8YlzmDb71WqRhcT2gyVuC0knm3 YfyDx8IS33+EBqObYjIhRpbhRGBGHKXYE/lESkOUFAmhSyUxhDBHFrsouhyoFP43TTg4P2r+sKNd TRMcCiMggM8mCv5EoXU2r3tWhdNqaRWRytGEzwDvOOgsH+gbIxbDTvFoFiQJzieDlpFcGqKUtc3k W3NURuGRT/uBhAEgHg0Clbjp49GKsyVAjkxAD10B39Ygg+52mFSCgxnx1b6EwEE8hmMcN9kw3pdl mUovtfbO4ihmTZqwn+wX2eM76rDiahFwA6RCs/5OFvhNgmThufuEIgmb2FZTpnVHtCiuIhFPw82V zgcZ1CBR+ueV+9zK7WFGbT4VxSLqlfoCq3+vo6Js3z65yu/9jAtINOZxC7jLHJactBnQU6fnO0ol ks5OQlH7roFNhxVbLoy1liGW2bt93wV29sIVmFmq9COru0LVOrlgswXRYxgw6GSHoBovNHOOVE7e 772u0KItGx9vnjkZlZq99iBj1x2hmHMSh5ZGd8hbaD3aKIvMewgf8gggbIRhweOZoLiCNuzAlsy5 NvxINQG0IU4rJnqCMXTYVff6eg5nBdCp2HQQPz5YxOoBBA1bWLgkD3h66kKTZEoETC322U+3hot2 qss3s4BrutlsIhCb5LwUT6oMN3071P43hhKwVXltYzPnXHCOjLxFVq4vQ8K7uEDfJF2GKc15Hbol 4KekLkBtllskNd/7SWOQ1ZoSAzXCu9UmsBt7tjskA7r9PfvOahYZF68bUGo18EyK0wqKU5NjZcKz aBwNi5Yb2eP2KsETzg4V5y4ou+ZUWIi9aymJw4Axygf1kxsnU/c+0df7I07AXi2B7f/An54QsKmV jVDvj5+v9fR6JTKA28qiCFwG09yi0lWOx2VYGKk8YvyqHp7koPk3LgRR/VfDJ6IXQUvANiCAN7vS twyEY/JC2uOytddfvXOafZfdTVkE+uxO2kwHSPUIVxsbw1MrlwAjZPBZWZqs3L0vWQE0uZ/9G/yJ txQ1mhI0gqCnZJZKM/ajkonTYtpZ/NTUwnBRZ3dOZoqs0EksjF8EIovHylgeukGEhQwBJXdRyMEz DbVfw5gbzmQQAwG3ZWpnkuPr5rmAh743NEZxNcsbq4nhZiZ4gtmQxgYEbHtDUWavOcxNjdcpUX5T nU1bBBVt12rp0fu4Jciflh6icm5AUZaGkIeuZGlcjyRH27ruitGg9rrP3N/78ynGdUUnlcxVl8xT zT7rKfnWQz4jhVGMonOOZ/aPROonEN9F48lVLkx1+4eQNn86FaLJfrnTZTDrKA2eA747m1YLz8qr J13/onKQUW108cflMvT9+vS6+WcLyZkS/FsMT/5jaXvhKdrwsX7NLnZU2G0EipPmWwWuF7XWLsme Z4ZwPnBZR51w2gOi7WPPQNCe2GvqIA3xasNVMDdq68My1Y9n/lkApNdGCTObhGKxQU5Re9Urmx72 xulA/DFEkw7cceFIEyGI1A4+PgC0P9hgXYllaxb+SevbvKZNaVEcSDoIPDCholQqNatmcTRYic5o shw/sPNcqZR/rPT5mkpuf9uaqfU40Fu/OfQ5zvpbDQYaEMTr/bjf1/4pnF9KnHF8ehmK7fgR82sK OwAtalT0R5fddZw9fcftB6glZTcoGo0WSB+V+rrhdPeOwk2eEq3riR8IXpIGaqHhcpTgP+tsTCPn qVewRJvrmBr7U9pQm3izyQm1uII1ViDmbKf8PcIH+VIcTvrYGVNC2dloMGdWXWlNEwBLvNrN4dtt 3hD2UzlE1IOQtWv9WjDePhKGRDP80e75RwXvrz5E1Vi0OEODk75YmBDylDi7tyY7+CvvgFpnuRAk frb8bMWoMjcG18xFYnQpvXUW10e8DrKMvFhlbjb7IhYZqZZ1SqTSai+4wUK3ZqK/Rr90wB+zuArP 64HneUjs5a3g+G04Aj6v1s2cMyI5zHk07jXg2S/gxMRHx6qV4bcMWocaJH6rPtSlRoQ8Kt3+AYJV oFDdnIDKG+LQnBuAXcNBTo5dCRVKWsNkJcr4Kwi4ecJLjAptvYHWLWsCKGvRy/5GBvsQp/d/8Kqu F6k+xh8v7rZpHqAtHEJCNV0tbcWHoelFz2EyQ4g0lHUVf/3ExtLGpQKvPuFHVJieuOpLS+O1IEq9 oXrk7R7HdzYMaO9sE9v0q8A6vUT1L5SX95SXT3+D8PKpaSFXa8ZPT9jhYNn0236GF6PVDSp78TfO uMt1zOYXhhoXfjVO9d+OLKn9qQwEZMdAAGwqZc/8u3d/NUZ/vlxHREgAXfoeIOjE4Plqv8I3xoUk WiiZO7KlX4Wai3blXQuNGguxeq4SIqCEH5bC+jVlHXEdq/SVkb0b7w22jaTXn9IA8VPx8N7f5TBf lvV+EW0FXSaBsbpjWnxkk/0+zvDHEQRngtSFueMrpGnpZkMF5IOnIHcUswn0wDyzIAApLlQ39cgm wU2oBdpWmHiLWZ7V1K9Sv830g1iKllCkMWSAbPKLWHhSwr7vOXRns0kBobqvbxoUBH970NlZp10r G6ThZc6pSAknSBkNvcFpftNvszCGqltURk1H/hSHr/P67c08KmTK1KZMUoAUdKD+YcId0OfF+Ddl eiGmLRg2/z6TSfCdpmDks91Vtdwpb2xdDD4XO6A9yCpUDirUwNBV4RTKNRztd0M1SBnXRfxxhiwM wJyiEfMbpSdFqPDyKvyWt16E6midcNUBDPzZZ/uY9KL4Y2FS6jWssJ3E/Y2GiQtP/+8GyskjmCBY yMiue/IgaDmYcv6P7Zr3YOrs8o/1K5tcxoMWEDOIMH6QrW5m227/dmEFrsplI+ikKcklnC+D3hlU uUfK3AaUZKu6x4Ssj4wfjiU6E9cNniIdiBcCt8VQFKw0xR511HXOuHPZMdAkMgGdowqxMGkA9vtA 3kYL93WCEd18XoDVMCcldx3EESxLsz+egGlVDbfxIYQodG7mu2DViUvyamlF+3r/EGaSaEQNjI+U FwAlIJSOww6qck6boNLJ2fwFA+vOOEhw1I9Wt5kZlXoQ2ZCZpBkwDuO8peLSI9HJrf6b1RlY1n8W mIIm4h+ZKxwbJXef7aDrr3szkLu7xEbem/TEnzdkiERcfHBjgv5i35CTFF6jC8CCVMMqyZVHntKL PVRw1mZEt/i+Esdy2BH9zyjFcCP3qt/G94gfhHQbBWSja0chS8hrIDflepf1wY7hI5pZKZqcY4Rb GAat+tVDyPHriJ0YwHGE3K87wtp+uGAr6GGtzzOBF7j+sSCiCnta92DKYoWaDdnQnWxPcFxjEvc5 Lf9jqNEjvU5//l9Bw052u/4os2AX8Dgd/h6URwAzUnqs2FIgA/yts+KmkLx7ps3fAPKLKIQ/lwlI bfKjol4ppSZeOHGBpoGHBTHCpmwgw8AW3L5Pq7yBN+Za8xS57dATQ/6BD7XfIFQnRMkxHNKtU+3M m9M+71JqTzb/RF/vDp7wtERLxlIf26+bc6dxqWQZvs1aoKH3Y09sJu8VcCTqygxJo+BnokqszRvZ 0j8VUIXbrAumcqXKt7xl+pVrBBnxr2IQX6H4bw/LvsxMaDGoddarLg97fBoKIjD03M6e+LfvcMUH FiminUNoRJWTKZhR62nVm3h/Nxe3TbjGcuspsKr0YmE2zAUx8cBKsCgX43wWm2lqqKPM9ZoJXBLb ttEFIUjo7ddkdW2j8v2bYS6U8Eh7TT6ck9jeKQDeXPnFyrTtRrXnGJtGehbZ7nWRm68tybk1sNpx zvGwawVmaOOVitu9vDb8lbIhCBZWlMF/dQhXskhOB3EOI1uMBf2MZN/izM0lnRCECb9aJ/wh3CMl 9GgKvrmI5kUMqPm4gGw3NwxO6PEPHzi8PLkXhs5XWH5uznJkSoWxvGpOKVdHd+vaQfH9GiguCLPD 2eoS/GyMXAtWtcfAnSbWei1ALV94G4JluPBYLcXbFUiidXR1G7LkhuY7vhB5XQomG62hElXMrkFr NXk3EFR3LGpcUXRZlJU9kI/qOYeDC2ATN3VaQM0t4VkQ2tUHxQ8s+FS0T+Y0SjR0S+Zfue9Piqkc lbmjG/0CqF4Vm0J+SilsB47UJWFDpCn+N6qFiMqma29kcGFwA7GYIANWc8AzD6gishwpvC+JjIUp nBbs1MxtiX5hR4HX1dtrp6keR1HJneON8lPsjqelNVZscmPaCFS0F1wewScSCCwX1jTnE2KMBXqj yOHwkbk5HR2vQpnkOIwy+QcIk7QNoTAjIzdaDqXyejU923nHZI5j/rpwi8qz9US9tuwP7MTDtv8E NLO8G8ANT8Dy3xqN2p1yTzcRKeM8Z8RPn54CRj1P7/ZLC33fEYuZd+8jNUHFTsc4gJsPE3ZPhwiN tjAgXJefkAzostHpHhAGzYEezVHLd2o5LaOzGLMFwCasfi2VYQIKnQpeZEx9DyltKSg+t5sXlKyq OnTuBqzt40kJY6/YbGPPX6InB8TYvR5XZi2LN64TQrN/2OMQYAOwlI2Zs5GDXRaolaEaAlWwhRQI XFRUkYOqn4blQKei7RSp4bVoalD2zKtV7zaxEAcXXAzBvaUWpUmkaS+8q93Ga1ou6M+r30nnAk8p QSukLJOj9KY0BxjZhIAXl8WTdrEbKp9BsGPETL6vnBeP/cV6Mm7lbMCTLbJ//ww/9zYyLE1dFhkJ ioM/KT793f1Zp4aq1uetLYIVOW+wqTds4GoCdvf7aU75PQyiFYhmpHPC00D5aUyXJzeH1ekZmASo Er4Nd39Ipc5ZrWdQiU+ypjaYX+h5Ftab4hbWAgDkIWFA11mN6G6Fz94KVko+F3uZn73iMezQ/3Yx xrFQir5q42Nsotu2FdFDylmZBudHaXGq4USxxMyP3bfIcLTufO1P1KN5TN0MabVkw+Rzbwpc1gC9 Y52WXCCs2zDYKVKto7ptxS6H7cDdnrDt3g7aRTosRRDXfuTKjBq4kgL161HbRB+EvuMDLALHOS9U KvQl0eaIdI6fabZtR6BTTifR1RiLQbOVvwVKNc7ioF7gCgGUrm0X69fzPJmW4yYrTQidqmSSyoxo NHF7HZf0bsmWsCfoUQx4OefBWAvRNcSvrNAucFRL2l00BkRRST1SfArOpwiGquVRcRnAYATONws4 DFyC8JbLeS+H09qXvPtv/QPEDpvm+YqPHwoJbBN2RinCIvqJBJA4fktkMAlvqX9MaqCNVBjQnZv4 e+uZAcOjA9NIzAw/ksAPLdZT5MPfIP/HSTZoR94L5tRPNOx9VpdsKlkHAVEv60bxde6WJjg7PYj4 acz7QbyjW5/pKMTQu+NqLYjte57wdoQdmLfnVCP1OKjBLyNJdrEgNWpt3K5ueMo00ZpQ4KpH9mBc 9aRZpe3SFYuNYe1iqTdWCPl3/Tb6USXfyrt93+gqbA+t39ivBcL0NUPTUhdpZWEzJKe9IojKoM+/ x4JrYfa4Q+SclRYxFkXab30Sh9bbaJn5EqI49qs3IBhMLtwT54rN3jcl1oec+7gMqYfidTGpRb1p obeUKHnQIX9IB6pzNsCH4bxHapHiV4Q0HskQi0NdD48rPCbBTpp7lFoxwDF44UZarOxqWSbjst3S XbITOICQUZB18tIdfZ+1UoRIe73Gw7EZ5yBUpAH0yjH1xOAN333WjFvEirWnc8HzMH2s8pDSvNoD r/2/XVmzgBWqNrgubSeD0IpLcDneTOcgr1ZrfRqoqFzmWtbKYUAK7MFnZ5XV5zXBnW1TuXrujzdH c1NssyU8o4KLzPMZFzLYfRiZUQBJ1w9gRpsUl0ZamU9u/lCF/9LZynpWqgPs+c4iXqa2PYZDdQo/ sBH3JGnSs/+thnDrGLsgldknYqaaXHfKN05p2K1/YnB0d9BhgE7ygBLwm65hBslQWcSb0ssseNKj OMiwHb1UaUOr9R6z8Ria6V0iayJVdfYirwENzcZxMK9Bhw5PNvyOPTNEOlfSlwErAxColmxj1Cgh /hAgWC5yQyJtY6gReVyD9clTB77dlayMGotclPaFLsGpwiCwIKCsqeS+/Zy9tXgPno2tNQA64pYo iH+nXAZA/FHZd/jE/m6cg5mm70eqoOjS4z89mU1MtKa/NTkT2EYdE7z7SHJrxCVy5n5fk+TxO3xT vce3rOIbgc4r/GQ8hRqC+RcZJCRaNZZgbh50T09j4XkzPgKpiHfRXhuWya1V4q0/ITfg/A2oTJs1 iKl3vXIp+LXoxDAEb/gCq8adJVZcmH+ZDGKT4jC5XAKdlYdCXa0KEogV9hB2PhWy8PIFD6Q+8Pxg yKXjLPCt3sReQRDQsjgugMip0d04wdbKyQITAEOocTus2Gmve7uWvUY4Oaf2+7UngHGWAinS9JSj YEZHJi98AxO9UiDAm7ZzNnN+nvmlaFDCM9ZoUYgurJRXcORO8S6tEGrk3+cC4Lzdcrnl7zC+ISke 4OEKgSDNvj0LVllPy8FvytT1fjc5d6q7wI/hlYfPtIqy+oioYayIHB1pvZCgQZt6Ui5Y2jvlh6kl /OrwLPyQCn0TbZ24esW0WU/vb3jgnB2ggITLJaQE+H3aQSGBclGMczq9p9WNT5++W0DMx7xakvhT k33SkYsLBHVZ8xfHcxlDW9GKFHU6xvwQ8acfGJYRvqtHabBcwQRRBtk2hx6O6BHVXsVEUPigKcLk bcD47mV0/tbvFKHnqopnoXCtI0CLZLLAwQK0bqm269NWHqkfZDzTrDu0uP3180HqeSYq0vXAY1vX cPTLNmcVZhQZxqlouj4vg/lbamYYTQKnKWU99BhcOLL7567qLPqweuM7GzrGI7L+BjkwIufJcTnR ueWUML8CzdOW3ZX32LsCvK2kfXKhi1jPmUk72SqiVl0DW9ZU1HQqKdPM38C/qW5zWcwP9d0YRfDz KQTBXlqk/vAzgQS8/56MCFyJkNQYqDJ9UwmyxWp9wJPK/SXxTiDvUFlm9rENvGMZsS9n7kd+CBbH cQOvct6puWQnlaLpBTThSjJUkiv45XWOLGhV3JasnVVMKfsoEcceugr5J69/FYv9NWdcVDcl4Iz5 0GuQAt/VdcEIykl1e2i6HDxSMFvLWQ1YMWAZOgBRenFpBYhF89Mt1KW3NhxKnnuTiJGLFHe2jS1R ZMWwC8jNFbl1ii69FE5swuFU/cPHF6lyTO2SsIIyJpAhfZDI5A== `protect end_protected

gpl-2.0

f482de8bb9212183f182271f7d110a43

UVVM/uvvm_vvc_framework

xConstrRandFuncCov/src/TextUtilPkg.vhd

-- -- File Name: TextUtilPkg.vhd -- Design Unit Name: TextUtilPkg -- Revision: STANDARD VERSION -- -- Maintainer: Jim Lewis email: [email protected] -- Contributor(s): -- Jim Lewis [email protected] -- -- -- Description: -- Shared Utilities for handling text files -- -- -- Developed for: -- SynthWorks Design Inc. -- VHDL Training Classes -- 11898 SW 128th Ave. Tigard, Or 97223 -- http://www.SynthWorks.com -- -- Revision History: -- Date Version Description -- 01/2015: 2015.05 Initial revision -- 01/2016: 2016.01 Update for L.all(L'left) -- 11/2016: 2016.11 Added IsUpper, IsLower, to_upper, to_lower -- -- -- Copyright (c) 2015-2016 by SynthWorks Design Inc. All rights reserved. -- -- Verbatim copies of this source file may be used and -- distributed without restriction. -- -- This source file is free software; you can redistribute it -- and/or modify it under the terms of the ARTISTIC License -- as published by The Perl Foundation; either version 2.0 of -- the License, or (at your option) any later version. -- -- This source is distributed in the hope that it will be -- useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- PURPOSE. See the Artistic License for details. -- -- You should have received a copy of the license with this source. -- If not download it from, -- http://www.perlfoundation.org/artistic_license_2_0 -- use std.textio.all ; library ieee ; use ieee.std_logic_1164.all ; package TextUtilPkg is ------------------------------------------------------------ function IsUpper (constant Char : character ) return boolean ; function IsLower (constant Char : character ) return boolean ; function to_lower (constant Char : character ) return character ; function to_lower (constant Str : string ) return string ; function to_upper (constant Char : character ) return character ; function to_upper (constant Str : string ) return string ; function ishex (constant Char : character ) return boolean ; function isstd_logic (constant Char : character ) return boolean ; ------------------------------------------------------------ procedure SkipWhiteSpace ( ------------------------------------------------------------ variable L : InOut line ; variable Empty : out boolean ) ; procedure SkipWhiteSpace (variable L : InOut line) ; ------------------------------------------------------------ procedure EmptyOrCommentLine ( ------------------------------------------------------------ variable L : InOut line ; variable Empty : InOut boolean ; variable MultiLineComment : inout boolean ) ; ------------------------------------------------------------ procedure ReadHexToken ( -- Reads Upto Result'length values, less is ok. -- Does not skip white space ------------------------------------------------------------ variable L : InOut line ; variable Result : Out std_logic_vector ; variable StrLen : Out integer ) ; ------------------------------------------------------------ procedure ReadBinaryToken ( -- Reads Upto Result'length values, less is ok. -- Does not skip white space ------------------------------------------------------------ variable L : InOut line ; variable Result : Out std_logic_vector ; variable StrLen : Out integer ) ; end TextUtilPkg ; --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// --- /////////////////////////////////////////////////////////////////////////// package body TextUtilPkg is constant LOWER_TO_UPPER_OFFSET : integer := character'POS('a') - character'POS('A') ; ------------------------------------------------------------ function "-" (R : character ; L : integer ) return character is ------------------------------------------------------------ begin return character'VAL(character'pos(R) - L) ; end function "-" ; ------------------------------------------------------------ function "+" (R : character ; L : integer ) return character is ------------------------------------------------------------ begin return character'VAL(character'pos(R) + L) ; end function "+" ; ------------------------------------------------------------ function IsUpper (constant Char : character ) return boolean is ------------------------------------------------------------ begin if Char >= 'A' and Char <= 'Z' then return TRUE ; else return FALSE ; end if ; end function IsUpper ; ------------------------------------------------------------ function IsLower (constant Char : character ) return boolean is ------------------------------------------------------------ begin if Char >= 'a' and Char <= 'z' then return TRUE ; else return FALSE ; end if ; end function IsLower ; ------------------------------------------------------------ function to_lower (constant Char : character ) return character is ------------------------------------------------------------ begin if IsUpper(Char) then return Char + LOWER_TO_UPPER_OFFSET ; else return Char ; end if ; end function to_lower ; ------------------------------------------------------------ function to_lower (constant Str : string ) return string is ------------------------------------------------------------ variable result : string(Str'range) ; begin for i in Str'range loop result(i) := to_lower(Str(i)) ; end loop ; return result ; end function to_lower ; ------------------------------------------------------------ function to_upper (constant Char : character ) return character is ------------------------------------------------------------ begin if IsLower(Char) then return Char - LOWER_TO_UPPER_OFFSET ; else return Char ; end if ; end function to_upper ; ------------------------------------------------------------ function to_upper (constant Str : string ) return string is ------------------------------------------------------------ variable result : string(Str'range) ; begin for i in Str'range loop result(i) := to_upper(Str(i)) ; end loop ; return result ; end function to_upper ; ------------------------------------------------------------ function ishex (constant Char : character ) return boolean is ------------------------------------------------------------ begin if Char >= '0' and Char <= '9' then return TRUE ; elsif Char >= 'a' and Char <= 'f' then return TRUE ; elsif Char >= 'A' and Char <= 'F' then return TRUE ; else return FALSE ; end if ; end function ishex ; ------------------------------------------------------------ function isstd_logic (constant Char : character ) return boolean is ------------------------------------------------------------ begin case Char is when 'U' | 'X' | '0' | '1' | 'Z' | 'W' | 'L' | 'H' | '-' => return TRUE ; when others => return FALSE ; end case ; end function isstd_logic ; -- ------------------------------------------------------------ -- function iscomment (constant Char : character ) return boolean is -- ------------------------------------------------------------ -- begin -- case Char is -- when '#' | '/' | '-' => -- return TRUE ; -- when others => -- return FALSE ; -- end case ; -- end function iscomment ; ------------------------------------------------------------ procedure SkipWhiteSpace ( ------------------------------------------------------------ variable L : InOut line ; variable Empty : out boolean ) is variable Valid : boolean ; variable Char : character ; constant NBSP : CHARACTER := CHARACTER'val(160); -- space character begin Empty := TRUE ; WhiteSpLoop : while L /= null and L.all'length > 0 loop if (L.all(L'left) = ' ' or L.all(L'left) = NBSP or L.all(L'left) = HT) then read (L, Char, Valid) ; exit when not Valid ; else Empty := FALSE ; return ; end if ; end loop WhiteSpLoop ; end procedure SkipWhiteSpace ; ------------------------------------------------------------ procedure SkipWhiteSpace ( ------------------------------------------------------------ variable L : InOut line ) is variable Empty : boolean ; begin SkipWhiteSpace(L, Empty) ; end procedure SkipWhiteSpace ; ------------------------------------------------------------ -- Package Local procedure FindCommentEnd ( ------------------------------------------------------------ variable L : InOut line ; variable Empty : out boolean ; variable MultiLineComment : inout boolean ) is variable Valid : boolean ; variable Char : character ; begin MultiLineComment := TRUE ; Empty := TRUE ; FindEndOfCommentLoop : while L /= null and L.all'length > 1 loop read(L, Char, Valid) ; if Char = '*' and L.all(L'left) = '/' then read(L, Char, Valid) ; Empty := FALSE ; MultiLineComment := FALSE ; exit FindEndOfCommentLoop ; end if ; end loop ; end procedure FindCommentEnd ; ------------------------------------------------------------ procedure EmptyOrCommentLine ( ------------------------------------------------------------ variable L : InOut line ; variable Empty : InOut boolean ; variable MultiLineComment : inout boolean ) is variable Valid : boolean ; variable Next2Char : string(1 to 2) ; constant NBSP : CHARACTER := CHARACTER'val(160); -- space character begin if MultiLineComment then FindCommentEnd(L, Empty, MultiLineComment) ; end if ; EmptyCheckLoop : while not MultiLineComment loop SkipWhiteSpace(L, Empty) ; exit when Empty ; -- line null or 0 in length detected by SkipWhite Empty := TRUE ; exit when L.all(L'left) = '#' ; -- shell style comment if L.all'length >= 2 then if L'ascending then Next2Char := L.all(L'left to L'left+1) ; else Next2Char := L.all(L'left to L'left-1) ; end if; exit when Next2Char = "//" ; -- C style comment exit when Next2Char = "--" ; -- VHDL style comment if Next2Char = "/*" then -- C style multi line comment FindCommentEnd(L, Empty, MultiLineComment) ; exit when Empty ; next EmptyCheckLoop ; -- Found end of comment, restart processing line end if ; end if ; Empty := FALSE ; exit ; end loop EmptyCheckLoop ; end procedure EmptyOrCommentLine ; ------------------------------------------------------------ procedure ReadHexToken ( -- Reads Upto Result'length values, less is ok. -- Does not skip white space ------------------------------------------------------------ variable L : InOut line ; variable Result : Out std_logic_vector ; variable StrLen : Out integer ) is constant NumHexChars : integer := (Result'length+3)/4 ; constant ResultNormLen : integer := NumHexChars * 4 ; variable NextChar : character ; variable CharCount : integer ; variable ReturnVal : std_logic_vector(ResultNormLen-1 downto 0) ; variable ReadVal : std_logic_vector(3 downto 0) ; variable ReadValid : boolean ; begin ReturnVal := (others => '0') ; CharCount := 0 ; ReadLoop : while L /= null and L.all'length > 0 loop NextChar := L.all(L'left) ; if ishex(NextChar) or NextChar = 'X' or NextChar = 'Z' then hread(L, ReadVal, ReadValid) ; ReturnVal := ReturnVal(ResultNormLen-5 downto 0) & ReadVal ; CharCount := CharCount + 1 ; exit ReadLoop when CharCount >= NumHexChars ; elsif NextChar = '_' then read(L, NextChar, ReadValid) ; else exit ; end if ; end loop ReadLoop ; if CharCount >= NumHexChars then StrLen := Result'length ; else StrLen := CharCount * 4 ; end if ; Result := ReturnVal(Result'length-1 downto 0) ; end procedure ReadHexToken ; ------------------------------------------------------------ procedure ReadBinaryToken ( -- Reads Upto Result'length values, less is ok. -- Does not skip white space ------------------------------------------------------------ variable L : InOut line ; variable Result : Out std_logic_vector ; variable StrLen : Out integer ) is variable NextChar : character ; variable CharCount : integer ; variable ReadVal : std_logic ; variable ReturnVal : std_logic_vector(Result'length-1 downto 0) ; variable ReadValid : boolean ; begin ReturnVal := (others => '0') ; CharCount := 0 ; ReadLoop : while L /= null and L.all'length > 0 loop NextChar := L.all(L'left) ; if isstd_logic(NextChar) then read(L, ReadVal, ReadValid) ; ReturnVal := ReturnVal(Result'length-2 downto 0) & ReadVal ; CharCount := CharCount + 1 ; exit ReadLoop when CharCount >= Result'length ; elsif NextChar = '_' then read(L, NextChar, ReadValid) ; else exit ; end if ; end loop ReadLoop ; StrLen := CharCount ; Result := ReturnVal ; end procedure ReadBinaryToken ; end package body TextUtilPkg ;

mit

befb1693c5607202e280217f9ea0e753

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/axi_utils_v2_0/hdl/glb_ifx_master.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block J2ZnuUy2qtUDmvL9lwHkNuhPvdMiRw1GcQ+q+XTT6Bl9qOR+wQn32bntBW+qJ9qdg1ChMWbh2uN9 yYsU13eSow== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block dokjGPbFX+SEENR2liFVeji8bFZk5aShs9n3dSHnD6UMWvkhiEMA6sK8PhWWmoER75vPPte7A0cS bDJ1Yczg2FL9+BnOJUXGrWtbLb6hh97CcHWR+nEKYcA32AI2B6Q2oy1dHwwcI5viwFo5NTQzzAo6 hcrwkzgnovbJsb+EIZA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MarfcO8bHlPnIq5Xh4R/dXdOIitG76+bzsAKS3wDwnOFiXEuMFz7e4gVMa4ReQM12EnvajBLkQcW BrN+yjv6/i2OHOAhuRnS5eRwWGDrnUPrelNnzoGGtxrVHOSqBYAx6C/4oJKGb6oPskjl/GlwugYD BUK/kmeu6iNMXfZU3Z32F8iZ74rw39xOsU3PNyyGnLG5yNwgU3JwLSPw0ygmgTFEEqjG7k+22pB0 26ZwxaOsAd117rTjGEuAWK1mvwFTc2i8gbFU/A62YlR5Et6JirkmED4r4fRZVg+LoVxuwK7SDHOC Q0UNHHy9krbNdHi0A/bUEbNp5L3m1Heaaj1q5Q== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Qk1zo4VzKlasgJhvj+UnX6MQuzQzG154L1WOEJ2Md0aWs3IqiPXGs2Lrt9XG7h/YB7ODPRPJe7RD QFbNj+pDwkzmDg5snUVGzqOThptKMKXuupSoweLEIADu+A/yqaPHPiUXAfbcPvi4REk6/bKptILE hwk7vuFK4XEmD7beq2Q= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block WKdYpHv5IZvRv+FVGs0lPNikyUt2h6lNujNWp9sEfTXjQ6OvBmf5DK0A3aAuOdlLTpeQooxlG0t6 Y7FlVMTaIFs28zGa0CHk3T8PgRn7rYkerxFhY/C9BW3QQLyIhO7YA3c2llQPUzEqcJH4EsvkSVZh As3iGOp0tDauglmNcV58JiwhLIOo588iIGJhdZIerWLEKDP3q6fZxlzopjITgWSdWWPEwOD5Nqsw sLOlYv9cyo8QypW/1eDqWFrpfk/HKWGeI8A8PBv1wnYkZPWQsNVY5i9xLYcZQzlJFjzR0Wbv8Rod k4Wj/9OaagFh7QDl2AkkDmaxs8+EfhKmWT29Hw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7200) `protect data_block IPOhIRx7pHuZHsG9QhHmKZkPZRSZaXlsjW3i/Sorb+dAcZ1FVZa+5IswmzT2WyubQ318a+KCgPSO 7xkeuKVvmUMx2cx3pCJfHppSIw5UYPXMh/osve0JtykkJkxS0PyAHzFH54VkomJGfMPBRVTBH9xp gjW1srIhcZQthTyjDA6y4Lor9rYLvhmCvE5ANjWNzssbf3Ia6OPrfmgp72xgejQVRTUtWpmI7AzR Xnw59NXUTQuVr+309gGb+qv3KMGHl1tdSK46GL+/43BUA7nWNRK0qfeEiJwQyDIoDAx4fyRUOZHM OgqstcOXtyKskJrxcZUgqv8cMZZhW1l/zFkBZ+xG1l1X+tbu5XrnV0tkQsbAzclMblGS1K28hQnH kDgCV4dQ6BEnfv3P5WBlrRc77kJxsFFMZCvqvHkxWUeD4oXlDKSIBTIanITJ+4aM8iCINNnRLPSS c1mbCk8K5NLKIxd1Dy3OhnjduJMR9KJ82UjZ2IsjbzFRx4NK74CaoZq0l8HyQKWTvDDIvth+QAWL QWztUBF/Ik+hkhXPbssVvLYh9LTto4WMCpzA0MLOX5o7xpNLmIaQg7i0uL7zVF+EWNVmFk0FheGm LJCkK7lq5Kg8Uhp1/ARNLM7IWZHYCqARVRbBrqLlqMErDAf4QlH8wEPR/jEFNBhknUw+weDO4hmL t0uIiJvn0NqG58YxU0s3WxcEtDUoDfkWvVbBqbVbcmmEBTmYf2DwVBbxd4vthFLZV1Z9IUowbsFV 2t1l/mYP/mPnCX/QtG8Lqget84w/HwgCUyvs6spFFgSqFENxKc0l15GTQu71uGAaz3wf91WQ5tNK rKxdIIdM+d7ZY1MlBOUQFPEcbPj/cCL1N012ebBL1uL1cMSw3wb2+tVhjlxDHvPtAA8iLNqYUrjH lzxZ2zIuRi8FqNjJFKH5eqaRCYJmbo1miz/ngP2Au4OiOmCKW5pW1C4RAWr3/73duJ2YeoNqFSeU wmvWQq4sw4pV2OW2/PLTDLBChEC0kU4/3AMWbFITjWrO4kOG0OUqLUspIBALwwKpru8rYZX/pclA erDcwc+/GKkINs761ft5lU6ydd14gyeElfZ6NT1IIvcU1tnL6I0vcJjeGuJryBPpQOG3FWh9SGGg sjwiXHXFYhXrFqHffOUtKvBarCHv9S+EFYU8a/gR/fPcdPPLaZ3DoZY8BbfimS9jdU6cjb9es2hG uuNOmyNTFSGrJRZVKYUsZ+dSgFXCAg8BbKgU/WpantFOMiiE0eCLzoW075c45D7bLmZhdUfoQF+R OX5R+8BAMp+bvneEz/Lmo7L8V/uYop1/4JiGt2iG75s2dOKV737JKcId5xCwJHtmLHrVlzNRNYGz sYYRATee9pHBSomf4DhPG3QzrpPF6qpKWLUk32cajNxHla6DMG8jWJjG5FfeJJWVWLV1nHrvjrAM Yv7bYH4BbqCuU+XjTpm9TLg5j4Ic+GJeuPNwzyuJv+KQZLFPciFVQWgoQttMxks1cnsTNWRCfRPk Vqdv/KijuUnlaB7P3Bx5EWY+ZR02zLSAFMovwo1m411KqcrNB18P6yRKtsGYd9HwIrClfqHe6D66 nXDqSsuWthn9ibIoguwJJLD+/UHZQLs0wpTUEPSa/z7uDee8TiDGEfCrXtD6g3x5gI+z0AbP2wqv /C/q8RVO+8jg6b1DzfXteCJN72o/+1GiZXNh0E95VEgjpCYQM6HmAqDAFsgNwnSUogd2YsKP3APe mJoXDWaetyDIew37AZldwzdEbB0WFpUyAo/6v/2UxgotY8WlrBFWITQl+4tDB4tMxwBPUUyGfrK7 LefUW7vWgHWIQC+zn+VeBIlZfcKToq2AOM+7c8mytKUQu2CqIIYUUBWgf4FpDe6LFaQLeYZwdwt+ +QXnP2WEctvPwfwbfnfUW90W39mO7Qx6SwHKOWgFt92bEfNXCxaA/6I1JFSMyjTvT+BH8XagBBUj gEoxJQEnUOkEMDQrXn0224I3T5IJYj0e1VPlC4mUzjhxFAitKid6lVJqhdTKdoXhei3mZxz4qtPd ixBH9Yy4B04oj4RH5m8XqSxOXkQtU8qm20halqEl6PEe1H+YbqyWRSzbw1wThkkf7qiu7cH8VNhW A5TspWB4c9K/PUCUPrwspZmYUTE3VnhcOYRuRT/Z0PCL0gRcEdGvpMR5LTUe44dSEUhwtgCUxx5N kSBfWCHxI6jz7j5jVjhGm3QSZ0896OWfM60ri/Nyn8Knbgt83twgwUESCaPm5rXRwPnL1R3nZYBl 2otItOET0c3A2ekBP0JPly3n6c05W36GGQPu7vVmaa42XlC8kyvGJkIQubPTJ6YbWrbDkP1GPi0s hfk+hwDun7+Tl2tco0mz26y3iMydKpglmYrNDjHGa5wZV9nMIClblSK5CmsRk+CUWGP5sy0MFAHh 0+bFXg/+TO9hEiHoQ/uy5fd0dGA+ZSbizAo/8cZJ/Olg/grYe1l3T0NC/z+CzrnC+LMKcqCZMg2q /Jn3E/3hBDssHZFXVb+vcEX+Wa/Z/qxxj0HgJfJ4vrMbQSyZjlt6Z5DjMye3cclON8E1UOR75ZYH 8lXEEIB3PPgJo409iGg4tWrOvEGELW6cLxxR6xuQaaE45v5ad8hnZczq7DuG0Q+NWb9ct1U1QGGt Lt04nI7HtvjwMPMr4gNr18RAlwHqBtlVA8yuBTq7Xb+lxI3lGvO/T5WDvVRhrsSXDBEiON722WTT 7BLpm6P2/LU80M7Vz9ps32y4V0Dk8cxXwXw67066SmuZvH7cZQ11tlRZdGS6nFcfcBJubSsnlBJP hprCge8ocgB6a1EBZOuWb/YGUgWj/1QulKa/exxTfqanjjP6HzMCDhMWBGtrB26XRqR8stTQQ2Qx JiyE8y+nLB31YHkyBSmEIexu/N7tPGNIo2SFEl/VDTpBFv0k7yYE92lKkqQvlJcuteN1hssr3E0W bqz1odLYuXMp7x0M0JSyWDoL37vq0DiiTjW825IWm4J2vBMg2RUgKTsY/lY/GUfr3iZS9SBXR5a9 LN35nRf+OjT6/HhBe+CQ9yg+7DBitGfKhTNcs305iCFxuIOuBttquu3vygtPd5effORKLUurF2AL 1FX8y6QQCjVOkk9dcL44U2i6x/anhCGUkkFcdNZMfhIGDW3zKUKONPwia6RcjGKCwWVTpJlH3Pma upe1L0rRLPtDAnZUfi05EM0eIXXWyvGmRCK1S+wPR8fD4qoTvZxpMIcykWqTS3Qk0f9VrrzCDO36 0M1XDynkXb/cqMuKbZJh+5KYqC12dhb4JjKnOGwE0uw6uzneFVgKsGgKlC8J2f99w2DBldWh5UQ/ 6l6IfzMPi/aJyPkSlthEEw4msIjJcFRy+9qWg6WxllwiYOhLpo9eD5HwCrFCrWETHGPsyRcmLcRX PT7qY3WpTAcU9GaFGo8utLl7kR5E8Lgxx386yH6DoFIc196I7ha/zPAo9spVx12Ba1OCSW5a9dF1 iKcnIsKLyG/X6boG2cuvf+nq3wVV7GhfbsHMXrGcFKQPuU5NEl7Nr+ds5ZlRVeZq/kIzZDlURQNn Xo5SSRSAXcreIEFvXh1DU+2nUL8u+FJ/6W3OLH+IKn2P8n+JIpJVQcxnttMEdoJtgJfF9vAZZYsL N4FCvW6nVErST9seirfujwCksc77bp+SSBBDX2xZKIGaREf7y72wUcOd+B1Cy8+SnKo370RoWdM2 ugrIqH7ovt5fAL+xtWNt70Jt4pI2R3O5EbXlegS8tbxTxC6A6ety0EypqW1q5ebCoKsoUrRdbAts H2BeJhDoyUyZ29NAd+xYv47EkGMySlBu7BIZcXAigOdoavUz4Ym3/Y/ROsW65IffblDn5CzifyXS a+zprVYwYbnmbOvoAlm4sibVuo4Q8g2iNrKA5kEpfOckfE8NAFOiDZTeNSDTQwM1ArR7wCRSaOns DlM7Xyq9z3D5+g9mNWo+R0NeEM0VoIB/yevBfZJiHMmhhFWqgGfjUTKhuipHcFImCfpzItT8dqno fFAbNT6YDRrJ6ge4ckLseqiLOvrqJS6mw7ChTJfMOo2Kw9V7XJxZa+fEe3gR7IFL7cIbwtdYOTlP hnQUNDL841vmGvB5MQWwWGXq1PrXicEfnRoq6QFshfAUlGrN37ZOTU9Xwh4eJpFNJJtUBgbgL0po Pwj+KK7+ZBj5zfy39lnqJrkhQYd1V+pM6KdPYFbsmIPJ0YMWoULISXcOMMO6xyXK5IbHJGKA1Hf9 dFA+/R07l8aswxOYaM49SLx7oI+nLGhUdj3aLNrgmjcFoKFITTOn8Z201FGRtyZEZIhGojSca/B0 KI5JlyKLzNDzw36DIgOe7JvvbPen7TP4UQZJdHXRk/ior0qjEK/aKdiZLMEh2s3y1XiGyUUKd0HO luZkrvhPqreNSYM4eLpoBpw+B/F2maxWbf2nOsUZgJHdJ6NHVTiKaPqiw12hxGdoqEBgIh+OS/pF +VS46aI9eis6Ti282zJpKltklLSZzE5NWHXtZQMsHyVB0CbhnhhDdnpZCB3ha4cuugWVJ4geD9El O/TSuPMvVLtEuJ9p2wxbjGf75NNHzV8K7JqC4eHubGthlC1o399oOU7Yf6NhmGcvvIlgdGI5i4XC aBBI7J8ZxhmaqnMvi+8qSv4vF/4pw0mL6Z/cBG1Gz7n5sRdOLdYqwCwdd1TcrlBQxQ3DpCucXcsq 7PL47y0M6Emrzw3NJwJiVjWpILy9l8jftXiAfEMGKKLbWeqkJaj0LPIzympuX3MJRBPoiv35s8ut ulKKFjD4Y6S8FfeaMKSmtr07fnKi1y9YVh+2c0aq/7fOS7KblGt2pYi8IDiOK9I/D6ZW6dcQ6xwg TDHphQzPCjBidgHXBe0liC2SqhLa/Rj0WZWQqCqyyQyJiMQXNbQ3RU4yU4QNPLWo8r6zIsY8UQPL lsOoTBfBzutHUTHiaC78bPZepSRIn4aYsLZJPjiI6J1tUh/mAFED26siUqPSCyKuqXf1MXidlwWP bE8lHX0Y82cqYET8d99Y0jfC82Sqvdh+1/wIuHQrl0MzXuI0RTLYCpXufy8obKApYOru6C7kdxAt wMcx6u6s3ajHrb9uwLpX6sEPzXHuGf5H7Pb8na99iBW30RyeZn5vhwu6yCF9IZjuRGvo58/cq+kz Qa4PxQ2xBhuNzDN4JcddcS5Z3J7jZRo9MHLNHETrqi4ID19huDKbF4epCa/OCpMuiQfwlHRLLeMI ClikDdicamu553w1aryoTdrpp45g5Egyk/CCVzvOvS3ZWYIHqFFccqWwg3DMNZRJolw1HaXogPNl nPOLNs4dWL/5z6EKdVQxZFStYoGvbFPxkKHyMWqrbGVgO24l4gmNE81ove7FCVg3SwEng/89R/ld c14PTxd3zznzbHIPQJIXwUYniyrw8/f6Bw8EPxwB2jmTIWpVP3tEL/E33128HdlY4uaKHUtidB8i WxzVJL5EP9Tia/Ip2uqGTfQdL7KI3JnwEUmevyrxnJv9kOa3iwNcFh6aQmZnp6rocqnqJNPwjD7B KDpZUHgG4pPNsLmgqHqdohp+yaw5y/mHYfS+9CTLstUGknMthRSf1iI7MQn2rMFIzRBwT2Gv+KWg Vekm60G920oMx8cNIY3mmh0ByooONEgjBf8daR8U0AVPRFu5OhHCiKx+ruqOSHxlT1gegCOTb4l+ rnDxZzUEkEy3Ge7QMBKqnaI2RtkYVs4RcqzDRip5Mqnwk+amalmrbgybu0NJaA2hM2XgP8ClX/fB blIzFyEixPdEZYgaMEuFhljR8l2xsW5yuXnkjAIab6h6H/1WmqFK15SGjtvj9ybRX9FztZFuXY9R xvkDfwFQcC3ljkLw7twCApAMyTjtefsbKF/aTTO9716AubA45tZPcmtwTXTsggmGfzD9U/a83ZDY vYF7eZSD5PapgQf6EKX6rTGptB2+nUHqeVuHark6rOZmgWMqPZrHpcHhyZjg5eIES6HAan06bnXB 8G7ZraFI+EpyWOwBnruPJEjMB7lsTGL40MDmUl+DwJ/xWdjdvmqhwhj2j5xX1q5kN53pZ8zjrOfz TbyV/XpKdwVGbCsW0u4+J0K4G/u07T/XTnkwUHNpDbRQhhn/5FdqdJ61K1hpIwbMlzwAnR3HWiYA H/Xaqnm/auGm5rO4p13+wu2/WRDwbGsQgKYFoUg/Xuad4wu4tnfczivNRpEE8sjVMFyO314M0Rbx xULXT2rUfCEvnyCAxzNsceHsm0r01XOtturIIezrk8LW5UMV5VIlhnpsQA49WRTUnGbwa8ystKpu JZbmQsP2GHieQ+NgJJc4KCTKiBdyvKWl7yJ1vCv1bIvgz2T60g6yICT41XeQLfXOt4WaWC+bhKFC mzUoaMaD9CyGo+X3PhT7e0Odbf8UUH5U9cUDFgVZMAlaZfLFSXPb6nlvKc+kGnhAesQWyEJZCXiu vMzZeYfjY8Tp16vaXzEBgEq3pF+Dh/Lnil/qyp0eX1DAAM4yvhqB6G5e+/Zp8xBLpwFCZi730CJY v+KYPb3V3hYU8pPMgKijlcdMh0Y2SWygNJhdT7jursbg45C7t9fJr0K1mNzUJDz0/i8DuLKudTIE Ncf4WQ2lcI85Bvk73cYvsCqTRZV7P+WYeHhtaWEoaO5UZJPH0bzoQS4jyijsFl/liVLqSDgrZHoK c4QQW2ZgGeZbKMozQM+vHkNl6bQbhfQQpKw6WUjRfcziIEXVDbTBD/D0or2oLtzIbNeCrit01XnX lIXw8M27furr8R4aqkCFvsEB4LZLYiijH60RmIB8Pbh4MEjTUFa6CHA/QQX+Shnodl3VHNXsKhhF I0XJzMGTecWJ27BP0w4M1Nj+GYjDvnPewRPZtCcgmaQwfJcgpEDhfOSki0/C2dF7yv+n7lu7Pm2F 2LeNESBsblGOcRsGC+AB0tbYWMwmjIBuLNUDdwN3vDSIxAzMug0gyo8BTJ2Ti4WwGAwEocYP3MWj hTM9xVwdJBmFb52l6TN9HHQXE0dyXZpupO22GXX33lsI4ejztqBegZnbtYSnMFOd1+BMq/E7Ql9w mzgaJelgpyDkZFJBmA0g6cq7RPmVn5uYIQ4g2YomB6DAjMKmhpjhxYpBMVbb9YT1IIqXkwfn4eh1 XUW7arhFZ7TNCXT21uX9TIZ2w+TbndN99iQSASz5gXdfGSGT/FaBZyRktNjK9YLaqm2CMBGE06Rq dgYkyLE/EMiwxdfMhXCRW6nqpKA1cQMAjGY9tPG8+GaPhyGR3G8rRDxzK08tOyhxZTOq7DCM54qU dsJ/VQPM5ZIhL/96p5Iyj9zDsCTTfHrTL++AvfMeVwb3finXxtnbPbxj8jonIIfzywyyAMEBl7zd fMx1/2O0RB3ZkdALIh+997dmfRI6z2efVqSdF0PlKLCJdVo5ftuC1M1iWPeHtgyTIUSP1j8P39IX 8+al5o43kRiRWDY5Tt7Ou5umR/R2oF8k3jxi3HBr7t5BAFvOupRtc01fE+RtI2WjtOAhxSJn0X8U 4NH8W0oFEbeFECCzhdVRK/m9two6vm3FZpQGFu2+fIsSgYKFbGlM/0WfQ1VwGh26pu88nfG11Nnj 96lcsu559WnsK3SHVHg1y/qDSkLuUIWLOrQchSjsSBXgjbJvr3mIZXzjFRyxzPFpFakFkRNYyuCd IHJR4vxjBvpyGgGHMW7lluNemmLQDYVgU50AqMcZ+rYakim0yrp+f6S8YbQP8mWZsv8u+/bG2ZVu cQG2zD140zWDPEAWcG396chzGfALtDKon9KT+KizI6+UtqiC2hPhrCAcqDBOJ30pYCz+jaI2lYeL U4DPxLE2zr61vzzVZBk8R6G7n8NYgnQ/4wOCY7gP3GV1neq3bVOUCK1vcxn9w+37lELR2iMy+E+t 1A7MUIaxidEZ8l5R3UMfr6fMRL9aiEepLA/Xs1MoDIoZeNuOUl1dlm/gBZxq3YhaeHnWrPLetO/h A76O5bxB4QU7Wgm9DmMi93NvuJubFJwfvP7VV3IlvE7xeOMBlnEA+s6FR2ikvjPlYDawWtOayON0 G11NvaVBp/C2U/oxyFhQGZXC/CqbCFt8naDjRwle42XWeTHT2tMFTuHfoIP6iIyreuAiuVb9B5hr Hs67K4bUGbCtiG/5AxanHk3Vkz3WVYSbJxBWzwAPQt6f0ieamOmLSvVInXao9TQxUNJrXVF4oaBw sZYM60e7sDr07Ep2ecX5dLTLp2oRqPk+Gbglr1iHlHQjsX8HLWJ0EaVgOmwsOOIg90DGjyN+cSpB sgtkMEVfO3JJp3W4JgJo9IV9fsvFFl4CklZ2uaHyB7Fs/nMkRLmN5O9UmrINVTL1EkbEpT0hFGWK yt9rkf+q4tEI71cUMYMhzrzt+QzfjTe2rY6/92Uc5cUFu/LteG69HAVp7Tr7cYAF6ZVOgG2/4XmF A/8pzbuRytTtvgw0+jH03owoWOasuYb8pgedER5Dx0DCO2IBAzJY5ceHOGW7rFTy+OEik7jVEBxd M1vRTFnjd8Y34s58gv6VKE4bG/34mwlpn5i14JKJuyCFDXt81gguvlplBIsVYAcfO4MPLeo6/lfr QBJh/M2Y9fF9GpLz0hPpVQz430B8YoMQwCqbAMvpV0/y7CiC/4WhcFhGu7X+fuDyGSoAf95Bdibe u+ZPwaJgMmpnd6igVxtTCqV5Ha298dtatw/WRpc3qOpU4Vkz/O21CfMMfmdiw8/0R5khZZNPsM7M 45j/ju5vEnJV5tx+zBHdw6xcLwkxyyTOxgZhibqIdZPe9RDTbYIjz3fSFBlvzRSVlHa6n8Fvchv6 pBqt9EZoDAwMCVKREQIDgTtxmIjZaYURrlRqRcc6V/1tG3aXfKCYRhWWJGSBiIAFszXe9LhBAfao uTAvkteL9G5J8ogc8WIxZc8hEu5Zh5BugcZusuKcFabr3SXh7pr6DHFSV3xfC/J1AFbzca4Z5YLD Bp5mnxFGCTNK0Cjx0blcSSpWozfYvAqzSpzYIpbEKPHIlYbxncO00CFrWPiKIaDvh81Hhotbj+r0 6/5Rmmj2qbeCZHTv6ezSMwD8B7Ztd/LY0ItzkYCVEt8lsunZ3wCGyIm451EbJvQg/iyhb6diVbgx D1eHsMi26s7YWVhHQJzBh6Jy8YPRslwhz9x7W5Pn4TWv4fVBZRXJnZwttcemri7OX9ONepDUxsTR 5RkbKV4Kx6XoFrmZwggYmraHveWp8qal/0fb6uqj6RL4vRHWp8JuJeyj8Yyu0U2EdHBNsOvlM/9w JZ/kWhIezK88hMSjeP1ReS547Ot70Qy8nJI69RN+yzV8Z4L+KCLNcIkI6QxcbyYjEK3w1wGTDLqy IRLESj/RrMsgjcl9wkcpHYc2+b2DtzzentmoMNb18X1uu5d9EZiu3qHmA2QdDvGGQrwDMfXNIv5K xnrWCGdi1UsqOvtWUNN4ScOdflTd5jpaHvvgyjDKlwoCJ1dDOgJomYL2d2Ni0nEb4fV0Zr3jC0sq Ucws1cQQr4h9gK/AxcSfC5HZNkaL4qNKGSnVKcJIOEA8KuIHRmc+8GIkXIPsTjAH53SaBHD9T0mg GTAxUX6PR7aepirXogpAjaVo `protect end_protected

gpl-2.0

f3c8497a43e38963bfd20acabdc2bccb

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/xfft_v9_0/hdl/twgen_quarter_sin.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block g8/8e7iWmwWVIhdWKn9UA3Oi+EV2zr6WM7ed+L4FEp3r5GMOI3U3su42Dr7oCAffBFexVVTl3RqD X2zR3G56fQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block h9qO4Q9rOYob/UPRzM9rYG1nW0zYgYuu8wkxSxCJaE2yWGl/DPjOCo0L2+ow0qa7l/NsOXigG+kl HUMzDqlNT9iYQxjqk1iYSIwnHTOsWMjaDarSNidXxNezKCJNt8/SVCjilz6roldZ1kW/Fff3kmT7 YVTvszSkLPgbT9vFViY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block p9tajOxAo7TxWTy3+CwcgR95/NITNrDy1XQrA0nCYyHg2kLB5xlIIlNRU5RbUw2V5sKeD8hu6cpB kKqSOic1oGn9mOlxZfCWCWocUep8w9TTM4alS6Pl7Z2jPCye3ms/TnaBh2jF56ZZzQ4IaQy8AzSJ zMM3r4WrRmcJxRkiw1tr6yTuXMbhD70ly+iVxiWJhzgkFp1PG3oJ5EHpRqNfSzIbsV7b4tU4xC32 sAwSB5OYCVtl7vZ1uiXS2R9i6Ufatst/J3SzaOBmfYSrM8PupqTnSYG9EP5V7EmRZY8x1ZOw9N/I TosuIcS9T4Nmcn143dFZqrBPLfy/+YF3vRErMg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XcjppJKjZueCXbveEam1kpKuvzaShxMPTKd3GQ5Sn6KeExgSqO4HDaufcsKgT4Ry07wenmZa7wWt ccDZE+Via2U4aU2JIzy0kYffeTGpo6NQ5T625KFgTgijat/V431eFmCtw9rP0DX9QMqKxuTdWQLl 4POdSBsVAj4LWB2L3RU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KkW5HDayltxMCDSbS1VxpD7XjdDn64r1ntHdZssM732UcZ3VTmfGNPYHKrm/fHBVStciml6ZocEV ZAzsdrrXI9TwuKACwUu5RO/6eX+0rFRdX6AWTUKLMiOqKekjbxmKtrHy1cQwqxow+l8D26PVOEvP w8jjVWonni5eWWL0z9x68QzPHyKO0/qcL4my8ZeBjW+h2RsNMb4FEFIriD9dqGADVd+ZATtwRzhw HKoXaPu5pgUvA/pKH8bwFRNfzLSVJoJDde1OZZgow4gyF41fW2jLgQUP+QWOkDqnIxNeuTOf/kNc lB8WIw5vazSK9I8EO4UXQWw6LpH6vsLNR1XQFQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15520) `protect data_block 4ASCP5LbPr69ZGZ6J8Lo3F2Rf4CSL+UzuUkl3YLEdg7wVVeJ7S2tMpUrPrDstg+XzGpyLMN8EWTh XogyAMYSuo431n5ZADwEgUg498ISWs+q3PvnFFYIx9HBejvlyF5F29tz4DFqXkgICQ5eshNp3N5c uck2qGyZdG7zT7OX98ZfExJncoag2GLppTkF92roMhHCT5tIKb7WZuDSL4xqRAXXM/sTiDBuO2MD piLFrhqjfZ/UMIJusRljo4kxH89NnW38MX8dRqJcA8FOozmW2tFggvqr9C8OazHGYincgzhFokzh gmY3oF7ywBvbPh26b8uxXEIU9AeC3yr66a49YWCaZoHWnnNUv+iWWUNx+mdvnp4hpTDgX3L+XPHW mfVRSjz+GnHt8/dD7g7IBCMFLkGXwjydcaxmt4lnxqoUpK/MRA8mY7oL/ZzKdS5PvqjQKnQ/YKJf JDwcPsgWmigPXOOdfFTgf8NDXDtoBtrccOmN8XAnIcmxrYF/C0qNGN/dyuxlIVqHd6IVVB9tbmZ3 3ptR1W+qFP2njW6Gvd0MOgQOCtXaKObMaBVGU0D7GW2IRfTQ9dg2uobWKBwrRYN5BHs/h5Ic/Id1 6W0J9MSD+E+02dhFaufSBBvXKDsUFdavcuAjniMcQHMHq+VWUx6QEckIl6MXd/LbaHYnMZdzX6tw ir0cLraRdNLj8YIo4EnLxhi//QyONL6WgW7aAwXZ3ZqTZQPV4x/7azKgwwAwoPlK8Abs7gFdmhTd /6qaX8rM7NMtr+TvUiA3NSxiKlehjmzu0rRFQ/eP3Gt5Z9CKzfGY7kthi9UIWLBtsrbPzeyHNulO 6eJrrYxnrlmo9iF4U2Cl4p/VoGTmLExwcRYn/H0kJ6lorP9i0iVv72d0c9EtQjRXuiFT1n9C/s/H ucjyN3E9x7SIexDpKaIP04ru4dH/Py8oDHFUzWIrtYa7y26oMlPqKLUPdabJlbJc3M2ZkFNjrVzp 5uGfZfNtWDlKu/JHqo+1xltfLqfcHd+f/oN/UmLxlGHpUfwlJlh2VZLzBLPh9Wq7y6DtOEPcP4Fg VUG0CSIoNCoiZAKYG68JpMN21A9tAWaL4ZWGauG4aB4xIZrfC+PNRVQsRTPAWOGyf+WeUXMSN5Xk pMF66826P/Ew0TyVLB+C4z3DiQ27qhSRvjmDDsBpO7a7AXkD8uoihVGjCvppZhRJUFtsD4IRYNBw ZKhxA4898o1f1h/ZlWXsEW3TREGS4GLS8jZAbmV24TPjIwOgpGB4YToo8i2+WyJHmEgxClEA2tLI Rmi2DWXcCgIfCoLhkL4WvptPTcN8gCo61becFspRDmKeorOX987gm/5Nm+1lx+LzpsIAhVQ7xLDj OE/dj+Hpu7uVAPepT3S5zgvvQgW5ISp3GAjX7nMlMz8KC7Bw2jSgC6aSfeoa0Azf2IFjeAxwID6e hfnMfmcqbZ0Ous0mjHb8eADi5qhOR0EijosQRfLP3QoWWDtZir8XlsnRz4Sf1dY5Rf8tykL2QX8v MEEH/G8IgORS6TRIwNEEWROyM2FjxMJLVX15xMTWDc+/SJ+UQ6GMlPcd99XXZKP4mi88eZVnH0UA wDonTx9pfm7yaS9RqD0x706UKYGmXbwyzT2N4hs5qVHs1uePNWjxPRONlhAFfshNyDQxjKY453hA BYVJWikJEhPW1YoD1V6a4712hnI8wyBTUpsL7X0lZmp9q5S4ymq/ghOwQUUVDe3ELjKD9eWYrDQU h66gVQCGn5o80VP/w90Oa8zLrlgaOGlGthJ2D4ZYbqKNxgokJrbORbwsddKbYBxMJw9Bhkk/tPtv HI/qRQDLARYPSTaxXMu7+nBa0e83KmQJXIugDEl1vc+31rBwe7EZmoYUeU5mV6YcFcWdcDfsW8K5 jyGL8L/Le7ZCjfr3mWk1tJtoRaMc2bv8j0HwmlScrkd0YuoFI9CQySaN/gMAycRCt9Mv1NmXyuWm AvshBUCGoWlJhUTw4XPetCwS44qy0hsf58g3ke8oSqORSNoPMKD6OvDKRXJb3QPMyTmVZ2zU7U95 fjer6uWWChEJpc/Z05dmRtMed7a8Zqf3iic5OKk6CLh30OXTwbkcs4olGW0c/HxT7xN0rAai9X9o c8AKvxuIEWh3yQbiwojdzHznJ3U3cbAVzzbOYah/fQdcHcePrwZ99UaGnoZddtIfotedYj0IJQ3e soY5GK33mDyWxZ3UpwPViy1zf1y5hzk98Ku1YsG5Ve7i+VaLh6CgoKQFKBIAbJnlUCjRz2lNBTpv H6CFODvO5HRKmRp0hec51Q8cZbMNucENg9t7bj5n0CzfgUTYSwhE/PvCn2powB1mBORhqvdgXApc tX0nBh0/b8euoNWdFHfep/kB6Zkv/fOawt+TEbR91JT7161fVMYxRzSZuBa4/SOykmLVLBEd+DXF 3WOLHsHwjsCu7hlRnGwuS8nJNC2NXunrbebUN28yf07AnbxsHpfk/s3rLC7zgCy/U3zJfAXkuZKB pebAhdH+HH4hRsbuINDQw5xb4kC/i0ljxW4s9DT3/MX0nCVOH1Rc2IBMBriLLnxwJkQ0UBnDLy7N THc5/LUhtNLSPlSvgXJsu2jACx8cEpYkcWJmqdw8RKBGTXgQmlnnLkH9GQ/XZFjMFWJA8YCP+rs+ knxX28L2rSwKwdteT1+DjHpiDB+aBb6ROaAfkGq9pAPJFSMkYZP2eY+jWtdQN+YuaNDlVGgO9Dsb 4kDV4GwqVauoPsC8Qk39uarlq2txkAP076xt8eD4Cw3HCVEOz9JCCJLCooW9hrmu/03rq20W90Bj leTP1HFGz71P0F83SCF3sccVavXZdBIypSIQCuesRwGqJqgMPc1boCoTfwmofsJSJF8tY43C8ctY ah3DZ2+CI4zwygvEKk/me3rN6apIYHpp0mBMKGHrvKKfq9XTmJ7X+yTFU0s47lU6AJj3gFcEPGjU Us38w21a2HAX7qR9knD3Rue9tLhbUtKkR9qfI481ABJjDQXtAZWCBrGO1uyFqlMOeNT+X2PjNAXx U4WvYEkJRuLO6SC9axiafGbW/M/rORdrHNEuamdJljRdSLlgxzKD85bYLvP+jyEmwMZ1TI/7gsqm BzRDnTqj2EEAoPhO740rN1NBd3sxPBQ7uBChk3fW1DBdDlyWZXtJvet6qfV69yg6kiSy0aii3x74 2PKKCcql34ZdSYWFh/RFIUTF5LrowmlbHQb0Fhxf8aR1z0sIBjQq6jQk6MLhgD0eXs1ViJsJ1I+o zOEfkLUydQBAK2mBfVSfuh67DQCgLf2T3sSiicLvlFD4daWyj7taPFMLmakr7blLGgvD1EZnogGs DZoTToyxLgrAGBcf5vRTak1X5Xy2BdXM5g2mQS0o9D4LQ5DaPP+EdU0Obq48jZGG+SdoUjpyEWL3 PVcx6v1IIOUCThHeiN0rwsGmR+oQ6hX9oDcpC4mDXCuX0LXxxgx5MGR0s1sCt9OeG78H5TgUBDTD Ptw74GOM95D1PsXbz3rhE/n0Vmb8CePEx/r3GuYOX3+jI7P21f8PbRAfRX7qrvQo1hinERlohnvr jfXrDOdLTJRhfcpHhnjiYNQZcK7C68acLDtFTxh7JWBO9fODcYxpSFmBuEgTVGJfJyvQWQUjmuR7 tifcXrTJwDVRYTZ07QVpR+aWDRAWYVtunj3OavrnfAfe5eAIlMeCcwnWfY5htuMP4YfeEi9HdlhW gBWZaACeUwlbm23J4bGd+8HUY51zGAoQcR3klnmEthn2QXNSuLTpjezqecqCBuvz+vxaSnLpnQVP D9oFmY26HJAWQl09PO8ghfctCgbQIjaFJDderGfQShoV+Uqhj5h2eTwG2SSV/dUWyNXth3ZenMdI uXL4W5Xc4ZtUP1U+brw84nW07kr6Uw6BJlf25Bp20ARZAVPAx01fyL8+H0xQP4PzspI6JJGEbKvz /8MDp0SYmRVfohA0KR34/n1TMfhjjmbkRHN4UxQ5qCSjRjTm5l2K8dGZXOUMSEcl7qpU8icLAQAS zef8wl5V/w91ON0aMZC8wUgYFC6u/JE1ulCAlcxOH4NeGrNWGd5PJj8pkfsekp2j8+rvf6LqXZDH eYQGGR5OitkExnm6kPTIwOwgKSv5to3AKtMIqJ9cCTlJFt3VHJcp/HXO02IjUcyD7lBzmaP5eGCp 6OLfU2lN4B9KKxRtLDM22f0/s9ZSfiXMp1rigsrrQjIwDBscA+mXjEDOkyT2pTDDGMJkUlWvVJDq A/XlMavdygcm9KlHPwWW/KZDqUy5E6jpGn69tkGUo3J/9v5FX+wxwcBxPH7QFpvBRlsZUDDHBkNs R/cDvaPkA30Wrx8PvHCxcWWD5Yypy3fRi8mmb8Nx0POccHavGQwoqe7x8C16xrTLcnJn8jL5mux3 GJBjBj+lJ1KZBBzwp13DxcYpPG1SQbpf7LATbSVxwEX/8MiQpghoC58AI5PPwVz1pnN4HOJfFLci xJ+SciJU4Da3PlCumGTpsjI/Q9idKivl7akloIkuzC762hgtpQ1xbNUa1ULPsJSyu0H06IHXspN4 ovI0yE/u+/tEUtPRMmeZAlSlbudlX25bh217bVyUCpYAi+d+5KdyirCgQgmtYI7a/jNXryTprUNJ 73HtKjnLxXFUEZUYIKUMygTzhlOUD1h4X6wt25Iu0JPuevQCWhd/NnUmMxtZ52NX38iS/Cj/VoW3 I/9IDiqLaxKSUPSZRoGUT1N8+P+30VVzYS22ouAbCO1cDbmEQG795GSNihtgIoUBk5k42g2BWUxy f9Dy7lkOSXiAzMqT0xc1pmBjZ/Dc6IsBVJwCXvI/Lsoz1VyV6ni35btck7haJDqqQh/70sLrwq1R 7bTssUdjF+vAeZkQ4Me2PBj5bomGHnENclIsAh0Lf5DKIkZMsZq+O387DbPPakz3jeMs7I06zNQv cy1oDa/onHi2WrjehfnqT5O1/aK7r5WKX9YyaEL5uArocyI8kerRipDEI/ji2QYf4KteOp0fpV6G 327gxwEzeEtK3a12c0wsCQdG6h/EY0oaZHVw9spFPjg8ADyc9VoYCgbByiuvLMJjK9pLuL+B3SG+ FQ7ghmnEKcaJj6YzePtCtCIw1GTdo+O7gtrOzqBbtExZ8XIRFFexeAXvlq9Ig5D1G3q1kWauXezH 9p0A73jAyzVAzjzchNWbJUh3OIsXzFOqisYsdVtXX6+RiWGXN7uZsJtEWqkxQwLyZ4/BMZbMRJTj +aJRR7u/jrbM/UCIYLFCtNTF8fSgynUtCklzywfGq4InnESqviDa7za5KYxRRI6Sw8eL6xTU6q6+ SHoU/MLkVyNE4rVqml3V0p5xuCjqYndEZK7OtPf4pmLhljnBq9x+wwJ2tMs8xvISGd8zqmF8u6xy Vgc1wel7LwHG7JMExyZ+5KBw91GY6jxOAe+HMTP9T1i6HuUwYpi43RE6gtn8dx734Z8HNQ5UvvPD 21+V9XKYNBwftkna+9WAUTaqbxBp9F4TmJNWQF2MvYxKem00xWK9j5oEtuo66z/rC++/+n+GrKyb Ff0T5/vRwoyajF+Ky47jgtW/0DpoxmU3sD2cKBSCtjcqFqZOyanR4Rs4V635yIZn30TrkN6QOHDU AE1qk+x1zig/KbqpUG18dJI2DKAjUssdqI0UrbWEyiDL1ujbNnbp9OkeX7vLdIfUMwX4OoJY2fEJ tEGfBPwLvLIG3yc6zRR0vM3wDaZsdEDMhUkofQ7J181uhQZjSRLkwrXP88MuJWZwAtAn11oKv9AW cFoN7NLzQmlLJx6N8F8EgGb+c66AlCVIjPHU6WYrUcPBw1JYrgFbuBWSEH1lhItwYROc1ZOttY/J Tnyt+PVWM3LTn2K95phDPH1xZQozLDVQLybAIScW0nnNYDyyuvOOmOTVCrKq280ccrhiRliH66OM LCfdr5ZhYdg34CxWNACDHT/qlZDoMCYRJV0+0I1WUPN8jcNp24uhODL06kVj+808jiStyECSMd22 a6CyqyPYgqRsVF0vTutm7e/DHdXAA6SBgryO5z8EI39F1UI3/8zuCTJSdKd741I4qBOzEmkSahqD FUkweSOTp8M7AAUeOkDatl6peOMI8oei4GAgNP59a2uI5yY9q07Iwtxg8R/uRfVrBzsu9E0yAZAf nKkffTT+GS8gIGeGaCDBoFvSCpYzsbMjrdwUqmPbV+/ggagvH/9waxQpBpNjwzLOKFRrPni2jAqR hU9L8C6xpvRKF7JbhZ4Q/n6Ntfct31IdW8fcoGKMFI/e/uLKuRHAGclUWGsqJv44xXBCwIJz1fBO i9sxSyGMLTjzZCXVL1YRYML3emzdxgyDXcJBfgskjjLzgK9dlQTEt17ef9e0Yw9f1oK2QUC9cQUJ T3zrP1RXu9725hdb91OajF+Mj+9kIq57zSAyV7uLWhGiqcWWsPhFeE+0SzkoRplreiKWi7Eb/D4T xuLHIf2mqySrQG+rM8ZtKEkJEAFPhrE155YRjR/Ph7p2WWDsaDfD90341KX+uZJm0t8rzC0KTtHw LFRoHaksxkNOQDxZpFGyNbUhVP5lqXpOS/tpw33cWWfcIkoLyFuZ2Dj+K6t1mMXrQqtqBlBKP8/Z pXfihvtuzFl0bi6a+zVqommLA2MjrDw+5M9zoczdDuI8PraflkJ29yKbIA1Ws1ltr9d9lbF9qW5w mQR6m6aW3g8i3t+AJ96Z1X45cMkdcHolv5dSrtgrSxxABUzwao7Rv5+iRw2CFIZp46Ge13Jibk7B 8kUAlFhfIaEZloGR0/ifd9SB/8LOnNYS1QgwPChRXe4gahAWl29MGPaL/BCpYg/WVU788zqZRV/F PoplI5DOufShFs8uxNxkvEkH+5gH7yKdbFeKLZz9pqaEGsCsVR7c/dTwGkpNJhnnLR6ztTprJ6IQ uclLW9UIWpnQv/HTE/WZN+xIjwWIUcvF9alRsIdtTiKRsw4e9fI3Fw6+mQ92V1EmZCqC1w+nA8QC uGN9BmxsHGDlQKGe42IGZk2jbp+XQpr5jTQbltPJAE8SSA4c3fsFqXA01JyABdlk2W8nMPSARae7 ERMlIWFnb6BPdz0x9nkUehQhmduqzxUzrUu7kixzRRe3eAWP9dX7NCy4Ri/aV4Im2Aagdu/LqX0g bzuZ89MtDEPyWwELZtm6PFQtYR2AhhzhAYOjty/QD9hxyBU2LWHzTaxw6QQyzyXeDQINqTfGS722 yWJ1vX6fry0QL9evejfBUoS4U/Ghp/2HlH7RrAVUgx62wZiQmYDRLtrcRa1v9rATO4UxrthmFBbp DpMrPhDCSZNU2z0bmkQTwkbIe1JmLuzCSdHwQWWaiZ3/o21gVuS8eJkA63lQ2NZ+rRXB/E3NbCDn 7GJvHoDOsMd8hbfyCJTsUNkbk6DCLu6LHBZfAZntatlLrTf3aXMvPOvLyqMqlQGFaxQWYcaIrtVN tOOZJzwfedlCNxjjGOOAGQ2wniTacB96c29vYQoZcA9Q9dG6VNHVqikDNApMQvxmxd7OQpYS/MaC mN9mfUY7NoEqP6E5WdH9Q/JGCimFC/HvQQT37GjVriF46+/RAsYxpdGjC7SHX3Ra+Atl7XsqY2Sq gzrvNy47CZP5DSwl7TNBVRlRi/yguHlsUTrn7zMPTRVQZqUxdhzQMbQm4GD3tbwje9Ev8TYeb8oz hoCzm/zus/PJh8VIB6TtD9q6rvj9Wb24OLI9Dlgb6zQCbSbO/ekafrr/NsAV0CXvv00xisL7BK11 UQR6/py3dnqRE4mKNaeM1ZqkRqP+e5V17ZkBdDjva4xcRp1S2zQNglwyqJru2Ad4vGYpk1J6Yufw kOokc2df9DcUuFNd3Xav2F+ceLb3AVh7tAOug4KD9+X0a+BEDZ8X4txoXqVeKaM9rsAWRmM/SQ2V 5WL2EZLkCGcNX55kb9iSviGniZqRVYHg6v6UJTOofuI+4AIqx4FbOPThmgEnUPiH59tNfo0WelWK y6ZUr2/lTKB26qI84jGm5rJ+6Flr7T1QvucyCPWMP9MwFMe6KXGSsall0fc5yo6LVx7Ussyd7U51 aawdXZjB7jCAi0m2QQnOWMUySv1XcvP4MEafK3Odti0bm5cCzalSCYGC3NxXAF8z2RjepNZz5WYk Y3+YLa2EU4Co9FGtjBCakPgYBlpplaZLKO1UA+ArJlUNmouyXLco5U7SBakTfgBFy+7yOSwzFrzt ppa+PizfnRx8Vf+KLGUoYVvx7EDPVpm54OTCKTen6WYohlfuQ/3h8GN9P+2CKxsRpP35N0VaPQW/ QQ1ACl9wNaWu6Kq/A+0gdU3EQh4r4YDAfPHq5XwNyqovk5s+lYVh5XOGbiCA0dgp4h2FtGFcc6xQ 8uIHxPs7zg7MCS1Ku7AiSnrX9neqgZMJ8OlGri2JWAu+C3MgaLSu2X+2lbErTngB9BQ/+eO3HwU5 2ix06M5YM19OuPNf6OT3xhom+a18AAEtgIBufuOirhvzsfluW+Gh4I6YJUnqWyi3urK+iTtW0y5t FCW3UPTBVSy5vCUEGOlqNTTQrdfyEOX60/4hCDwnoX+djSDNFkZvGlHhDDUYJFALxnl1GXXRY5u5 mFlu6K5oqucPAyyryA6qTSqlN/sf8GSH2zLVgGvuODrPNuSmJOOUJ3CRcMMlOlswjoEY+P9jL8Q/ yL+RLCq7kINh3xF2/6J6cuETqxbf3XbmE7Bk1kppc94C3dv/LbLWSlRAdkXj9nblOTwtZJiA4R+m BOFnaims3n7vS/yalo4jGQFhbSFn5WHbtSeUsOS1ZTxOuYZQCA+BDbidim+P6F9Hnfhfq06FbJZ/ ECN4NCxpkz09WlRy8A5hb+El9YUT2i6uajcg5tlMZAzaLm5gyUYykO8cFFnpoz38+MDBrEVVLwas 3AV7ypfY86FzVMYGHQ9l92pnns6hTy6JHMHe5mHFbYdnvxwA1D1K3zC26+uC16VRqUbgAxiqkkQb oRHFG4XxbDt9Ekc4CgcHt3QTpt+Z/HEsj/I2KRtfHerkjQJzSWyW53S5JSLJxCSLGfrdttuNwJq9 8vUXhMOchDrz5Lgcmz8upJiskogo/RD3GTwE2O2T5Ac7vyGvPCocWkzMtvoV3fLYXF2LRaA5jP4P KJ5vsNtX4WPI3y6LLctMpR4bLI24AwBojykshsH85ethiGi+4gNgO90X7c6dFbVOfqEnQe1/1QLI F7Epj9jDLN6uEI69hGe53rB9azLtlqOmOSXMJvxCN8/WbIgG6UuDM77MGcCuzBD6JGMeZ5kWiXKi /MXbriC3mMY07wPTucHlQp0oBV/fZUWjVRFETZQdGIr19u8jzv2fKayM0GdPcHLMIfWnAPQqE/To qeHLH7TIFn9iXxMCtGDS9UQDd9hih9EkmLZBfJ4+uRx8+2/fP8w3dQqAV7AX0dum7gc2H+2/E6I/ DUl9rkUj6EW1t33PB+Sm4BY2Df8f4ZJNGB4VJdKYPikvtQ+JluBtfHf83kIigtTpwBEFq8t+/tPi ISO174ilmcpPqSklMNkRdCmQyuDEElFJtSGewf+i/mQYknAmDr/Iwy87mXKCDFlukY8EMHHu5uVp E24qWu0qwhyirPozLkbq1s88UdrOHJqs3Q1AYd7GLtgZZVLVS/vJVkn6NJHdwM8ywqObb5OQ9rmG ogArOIphgPyGQpkrivJWm15l5Bp3n1nZzaOVAdG30J5KSdm0EOKbuQQOjtbwesfRGhcEva0Glmcg ZpgMu/QXZQSKuT+9fwyLlQe8Sktwh+bA5EzenH4SDfqTEyqxHypGXWCyZZMv7t8ZIIaU7yCQZRHp K2qZJWP5blfph6g7Ac5WjruKODkzZOyBVGaVIgLB7ibmhIeK/RQOMUhMF2/WMzV8vzQsDHSV9txJ gwqinDBMaSqZZmwqSjgt9MNaWvOFQqIufd2uHtqcha1VOk7C0Sy2raGj05KYBxsps9PGhZesKNEe jPx3dVG3UetVvHVv7+mBgKcrX9dTKzVYBqRu+gUHo2O1WjpRaK3JsbuU443vJcBW+3BJIspC4WN9 GzjjzrlIxMML75wl0VTBgT0wlmnGI/RHRD8Bru8dhTjiNIG6LY9XLekA/6VWOme1lfd40jpiKa8l UgolRrMGBXYl2E8QWq8F5OZkwLKPSSfo4rWlwX80etkwOISvtLLJ5j/TNXvlkVNBfdVLoWdGsM8J KLDYlYSZHMxapFU5cpflZ7cU+Pr3ru++ExGhpSQQTPICVIrBwSHBG+Pm97rB+lfBbCDrzFmPAvbd 9bXKHgGzpSYN3na+ATEi4i8mq5Qcsb4PY1Lg3+upf6qhkKIxHYflCR9xGquOlYZI2gal41qZHQt6 QhUXzt0L7t5qIwdtK1P1atyTtO1pVaSwg6kYx0hH0PK+W3bbANGV1tZUtJ0jqEKpEHY9g0up7oAt +Q1A0R+LOslXnJMOnGD7KYZcoo2u0yaJ+9hRFNDR4pwL5AymE3LMFTnai5KP+Bl4HAYRnG9bFYRX IpkcjWZ/bIijk4ZyTeAlQHQM4Tuxxjv0FThY/PlMHWd5zxWy8cdAwUCw8AhFrASRcDqHcabScBM/ cA4mb4nZW6y5zEFcuI9FeKdDOFN5Xe9ElrTaz9/UKCGnMI3LCqck8rvhF2e/zxR9XwvPaOEiHoqA FC1gALp3NrioxBOrSmfWJgB0Pe67U+CYMLwDq1ksRyJE5iczBxJe1/tlhqqnj2Jxn0DYQ3vpu4ur ypSK1A6C1feo6uft/99Vvbv1ByvD7h8G+FnHgJVy/Nc2zcd7GtesLJlnFQYfqUu89NdC2njYTI7T WlEwphI/6IS0r2wMZyGuOgmG270ePa4/Tb3o+9PAjyOmIBA6O+bTSSIvVsP271zwrWOT4l4J3KcQ lGGLTrXjNmZCq0cO4kFa0fq8JyB/3Xd2WhEMdFx2bZY63QGZ7ysqXxpduU1DnBqIJeGJcPZmcvqq FMO4nunHo+SsiFwhs0bKnHtb5LFT07eaXjtpMHTrrG9G0FO2IS3EI/ZsjhcxW5+yQ80uZWv6p05G vWj8a7vGVTgeNEUXflX6urrTzYAqrzUOlTZofqITNhLZSn5w5bj1jYSHpSXSvlY2rdfJpvWtd9Jw 3ueVVCkLumHf3m1EALkh4muIco6aIGKD7EOq9BZ+AdBMfouzDXcoaGtnV5rW9kueEpi+qm+i++Z2 1P2AGF9gdz5oi70Yd5b7SmGGnhqFe2Qsp3wWiI+X+H690BFLoRUb+npj77IjSd06s/0q0gux060m DFdpY1xEGT79Z3yERp80QC2mLH/U5RZHDj3rEIzfAqL6x1gn6m+OGyba7/xVIfZP9wxYsw78unHP cVGsmZmhbuc16KYYRXE9ySRVH8oQ5D1nZc06lrqd1Mx8cQ1nPHazP0Dgon1PSdpTY0bfqy/9zdF9 bWKHpQOnqYpJSXamGDouOBE0p36PO5zSN5/rXqsb4t0cuC9c/dJtDPBcls2BWzkKtbj9HCRo65mX 1SriZ/tVyAW7EKka6NtBlYN7C0xSjR9/c+yvCGs3x2/R9tTY6FS+D7Airz6zTRij0/p9yCHPm0yW naxFWHWmr4rBd4mxRtNX2I7xhtP86oIybb5knys3z4N9IYGDcT5SOw3rcymKFKRwrAiY6W0nEXL+ otUOXPMXNrPPlJdz5GsqYtpf2BiWrpfE+yWlZ7fSpZifA1YLz7THPT2mqvbOdw6JzGOLCnlM0Oeh 3wol/e+TIJEZ4WYYHx+m/YI+TW0h2r2eUQ0i/5XE9RD0EbEaAI9x9/WQJX9V8UXubZ895ViQSO6Z iO4yaiNsdXINQ5jrMQPrj98VT5UJOPI1BUOXTV1ZTRIRXrnbQJduD0cRgOjGjQc1Q6J9c/WE+Qwt lhk+Vd7C6YU55Bigt0d0kFaYhJoFo4jfcGpixEgzOrXBek6CoItptED1upcrcOz0Jk53u2PB1XAg fhUfQFGRsmLLdX5qRTj/FHmP21yJBVpF98ai7FDX/2lolwZfdlwQ6AWyYSzSsdbnWu41jjhbYmyB j5se47cSg+r2OFS3k605g+0MtHSqOP9NejtDtJlk0NUiwhj/ddqiFjAtfq0dQN7+SBWR4XUnvY18 81fbdaiovVtV6QI8/bG8aXjcHbO0WtdjZmae7Rw90AM0FZT5yiAgPqtlFGqaGMzuZByRgJQ3XUcm 9zSyUR8tQPJBn3iDrUDdN/JiRxsYChwXy93w1Kfqf/tb26nlItZCZAfj99YaTYmoxBYVvXop2G2L Prv5ZaeSwAe/zVGfpJUH3pqghHGCm7P15ilzX7/+H58KARcs2x4b0WN9EyGp9TryGExfyVosx9yw pG0xFpLOC9DR++HsMeys0CAgevKpVsXmm8qJmTSyUT7vsJLPF9iPhuv2hmH0BFTLZNx4pAXfdudB WpblvitFzmP3VWU5FY+4tfLeYcVvxS3E3JYPdUjZxqDaOcvE/Bzu6BFFTZd59TT9Cek4gNn1uRRb iEmo1lr+u+7Ro6PqGmgkcPEKBXj4cQsJ9Yi2KYnmYbqhXz3qMSDjlmmfCcbvTYZDUEd/KdcF5z6f zPCuIUxNuglWn+eZNxUS9vLwTcsRIAepCFH/+AMccRySz2mKshNPadcE9kMzHSyoKqMpX1QwXTmL txYdimjb0tU8VwUBL+7toyUb9KizBzQRdPoLQJ4uUaM9/4gWYvhAKswlBDJK2/hnM1maWF96nmhK HNZvfK2jHSJpWNjX8DOQrhgxyRSiYq+Ykjw7glOIXZoL9JUDLDLaUfriFvzpHOeeynkaHETfiS/2 emjcTIlIsDV2QClyxhwvd6tvQs4q5ZNAQiCv0BDkq6lm3i0bbkZ8hZyyCfXtO1nvCC8NcZNQHaue v/arNY8ahJ1O60Y/KflPe/VP/6mi0OOGwZQ3ziEF4Luh+m2EpNefI/hrTXE6uYaP5SP70t1EDFe/ KrGmUJNvaTOkGobCGs000n89Od57jLZ3hb38SUVpT0AQbgJ8q5NyOVzLr2VILv9k6niHUwAwJsjE hXJlwJUrrWr2/sQrt1mLJksXsfsOYjLSw/U0W24vwycXFT6texqHJSCE7cTKQ96Cc60KO+zCJFJi RuRZup55Mn5NmsHWchoWd/7iRLo5NIvHa0adjsKxA3C4nFCruunk7Sc1MaqDiBZxciJFibGJfDIq OheqY/p+DfBOSoXfs9PyOX4XdIA4CWeFlkEJxCgaTXadB34q31VIzN9EfNRvyzvR61oIrk2pUeC1 fqrnOpamu4+QPiqkuMMM8V1+qxgNLaAuni3pp4rSqcLJ+X1vCNsKWSaz5ZR71ruqI6JqwgUPwMga Hz5+vAXMWYzKH2L8qCT5EiymQcK4BhIFH5WjZKqsjcOG/cF+FrzaEr4mCMI3z5uzHRBLvgCoDJam e9ATWjHA3Sda6Tgzy8K+GWr8wjxfW12EZOJhiczj9K4d0++fEYIF6zAg8bGVIpZzZ7CYQ663Fe8J fQJ/zG38xejOwU75T8/VGYife87kX82Brxu6KckrCSfOXCwfGaeuY50h2h5eBAELJZEfPwzFq1a+ 1fv4ekk2IXArlPnbeTfVO6Z1F1eBP6Swoe3kExwiABcV8l658P+euUZgghSD2ZZkHU/4v0wBUgBs nVeTwDYK+nKb3Ux3ZBzWVyXlvHR3HGCrxPdNNG858NYfVWnufukkCWWZ5xjx+dE8/kNIGUYhXgS7 1w10SYF4tdy6sq5IO8RjLTMdJEVy4mTkCDKd2aznOSnbh9P6jo7s2FCc1OUFMdXUhmBSzKcHfvtz fzZam6CXzF0jKQ6AvGdpjZ6VSkw6WB7NE142b0iSLAiC0kA4l75I3ywc7kHLss0XqLFLagNy229x jtjLk1QVEy4vykNTyqiV98EnbN4VXS8rrxisz4XuYs1HRWFpiXPSw3loGEnavzOqbVgxqswbUnnZ htYzmM8MQbiI2whCANnDGFzq14Hmxobtnag0Oe8so4sPHMsJbx8Hg3CjpTk/8Oev7S/QKuZOfLhd C4/UBHuw7EiQDUZp4A8Qnc9tCGfqXm71FDoQ4mnL+zSGgKjUCzzUcHkHQ/WQw0heSLplri7DdhZJ ppmYB7bYlrNzlPEHTm0UkqTft59BCewqd9eaiFusbfsaLlVSp1FivEKIh/nB4tZm3z6sR/oqoVtb vd1snopVgwxfc3NPM1FMisXK77LdgbFh98RjpkF3Jock1of93xFMaLYhFvxSxTAwzVu9PNHSrWY6 8MYIoRh8uRaYvRJkfRXk1ClhGs31DW/Y5gLqOTFoIgiNoHHS56seunrg3IWDFA+h/Uo7vlADJo8c dEuAMAjFOrZpnRf26x48emcI070oMX1gFxue1agJUsntls+0PxViksg+tBROgU+IhzwIOKT0e8nz bRuHbeiEBAYRP+y7w6tVoH1U9HmAbOyqYWZEs2F+m948+tty9CZ5jIr7Ytx7kG7ERZyOaigoPPsE U7Baxng5fbU4DLmu47htoBPl7ulSZ8ox05lY9vPDrkrX6hYYZ7iZzzW1lYx0pPAZHUAX/TBNRnXr vm1qx2sAUMR5g8kF06C9M7FeTkI9BhHt8AZ9T0lhb668lxoiU754lTAwTmOfdfQx2mdOpA0Hetrz DICni1pBvEs5M4TJK0u6sPRWS8wH8tuWfW3TLaPuqLPTnzRpA45LIyRzysMNOqVh0mvaenKcyJXz 0FpB05MtB5FQa42Bc9uGJkl2G+qvjgyvqf7eCHHMqEw2lwTYR1r0ZTt2kkWp1l+RBCdCfsupTD+L sNDx8bgx46SV9LWamjQzrx1lIDpc8PRD2SOHRm57xeF3UD8gde2lAHc90OecDQ15zuMLKTbkc8EF OBjF9hIfSQMHKFJjTjKSh7p+gvI1vnpaVH5KwhU4V8XeshPlcXy814+lNpoR+CQ+mKa/qQ09sljL s/MTbxX72DHNUZBGMqSjhn9L+xVxWcoIGXGalpQvxTP58rkJGzuVv0nsb+MtA9bpaaW3GewWnVXq u5lF/AZme5sKWgbw9T7nUcu+AsAV4WsjzueNPoUHhPBgEsU94Gmg6lY0m3x3kpBqNeWYSOmEMHCj y5fwpmxi2DtMNV7DZn1sIsYftYIFi5yBCHd0FDxyFF7BlHw9XIGQ7f6evYUnei8PA+Je3bfYSHKO l/mLssfH/yA3EvV6OcC9doK1TOGzkJFH7ot8uIBt6JSrC2jvc8+vMRlbctU7W7N+62P3l+xS1YjE Cpx0P1x+/KDu1zgrQvzAGEpqjXFue1ogOY6td0Mdhv8LtzeRmhWV/c17W+vHevRFfWjsUL47kIGb SP/jBz0hloI9NMByXvJAocqFIJGAJmNP+RI1sk2lPsn53XClOml6eon9F85yEqH/bg29IHfY/Aa3 ltxAp7ldvFkluTG/g4axq1JlE+/nD9nNeoZzE5ll7Yyk/ZS+TuqBln7kBT5iS3SkoSoZbWggiM+9 HDBePp2jJ8Le9Gh1dpJG3M+NQkZHuuiPNCirC2hKB5i8lhrGzbpOTXCSXBAyic59aXhzhWZZqkKJ /iQDnP5ta1rtWGD6CIWEA2ROh+uWep0Je7oSK1Qkpajc+jVW6nAyyTluCvIoPbIxVNy2Lhl9P6Ua xjkkDnqdDfgusr4JNATx3KrqgExQUsWsvCqxZXKdxaj+ILpitWdPSKnFZzRZNclkqUeUxJAet3iq zgM336C1Yo7/bUIx+Jtb7JGly4HIHRxGRJvO97IYSWU2Q04jbNJ6MupS8iG8I3H4ZCWFd4LWKeiH dzx52YBYsyMxRPmisuCMa+mu/B59E++KOjmrPvZTottiTkYQ3QPaP4OkjDyueYoncUK1WNrLfepj kuPggd9m4LvEuQu8SdNv34xiYAZYnXRd37Y5EuhjAA08TfnQBod+eg57BhmfOlsH/V789hIhppwb 3GYas95iSFC4HILlSeqUZED1KNRgBhmBN24f14HR8xrxJHWZBSxv61SV0vK498HDvt0RW6Z5XZL3 XPv6tgY7UEeQOfwtZet9SU+1C0wVVsde4iyzXVEluw+a1h5M2G2gz5N6F3EfLzYtgd41j05BvkI/ tckzP9dnycFcgDicKPPaEnzQx6fGA7T7m/hkVqfUpHkdRvumO4+ndmmGIDX9LFn6fxSPgt4aZmHN KHWPIXKhU8Mt/fQExmiCvEt9tEeuPkCo3OxTXQMQjNnFZcpXp0aiNkk3CIN9NdgifI6TZmTltn5g rzI/xPbj0e7QuUurI+CDR+WMJa+tQezAEbj6Birkb1U0TmXdlyaUYavfpOZptI3hO8KmNMH8PgPp JgmgquIcOEecHh5Ij3BqYBEZ7nwjx9BXGDxgzZYenRivgzFU3m3wNUC+7xhpg7Ast54weJktjwlI Ec2E7sihAg/lpAf1fqQWMr2JJWKhzbX8cUGklHlm2qSS19eCsQSl0VTLTAf6Jitls+GiHqTpO7ev oZ7Im+CqRrwH0GmFstNb0wsYLYBAQF/H1e1z9VfnZf5FqTIY4tc5qZIRI4FPFunahgUrAty0dZ+2 H9Pw8gJOt9qJv7cSzP2ZGl2hHgOpBfnn7V8xyVUUIzER99CF0Bgs13uALhZ2CvS+NDhBy9MA/Djd MjGPMYKC+Woi5Vot8IpClOR9GcPAac4TXR0oGP+PDjWGRHQQdt94EdpFKYOHM1gI6LsJf5xbXBN4 /0OOAPzibY8THBLZnbQAabROp82vDbU3O5SxQygfrUz2PKbztFXWdCjXsK2hUL+C7a4RTqE+QRbo a0KJMBQehMwR1iSz0XRlqinTVNWGd3qoUS1ygF1bM3rPx2qjU+56NecEsgsWrmuwKrhY5ubpgTSM BKpschlLgsrZ63281+5jqrrAvUd8XknJsSAVABwth7FewVD1eV7fDJmk3Rkdr3Pm36fMlVXP6+Hq G4bBC7KwBDeErE5yL71ukeuizlaTlKYa4m1veRoRnKKmxCvaKlpVlPmtztteZkeLhoWGa92fi8r5 AThJHJvInmj8yZm4vIxEat5eevPrTOPpn3zCh+w4HJnlAiTytovl6UXshn6MAqBc82QEvNXVXG/X wgreSlp6YfKUKztApgol37Mw1K8pyHqzHKboKFVN1746D7XtV6n5n1F8c6dTRo3m4sVnjTMOq+EG jxekoXiCFKcr3AK5Rq5TOFwqllfxx0fO3MdRSmgtICZExyTqarWrbWFYmoem4b8OCLivyCemnLhs HQMCDr7oQYJDc1oxFrLLnUo+961/hNgGEzGDDqmIgCgSm7fuQijFz4Ao8J9cIpGTUwxiGqdrAIC1 dpmncCPrLWK6APPYQNh774k4SxsW31eO3psNI5whB3GuZ3G2zUJJKeWvtFcf8Im9xCwOoagpcfUQ enxRq+5CbnDfPgohJEM98RDa1av2AtuyN/lzTXx9hUyTqqE3N4zodasi5vUoKC7fnW6Spv4qGZwU yY9imCRnjHCrrUuku50aNKyKY0ZgIRvW1hazjrsSwglele/r66ZI4JNPUYSOusEhByxZwQoe/ack dMcHYtdMB+f/ju0XiUUDVQxLX5ZaBaJk9V4YG90YEiuGYgC9DBr4tWR0VdFfdzqaDRVpcy5SKvzx 06yFDe8+x//gGELaSZFnLBsliPWhUj88ZVjoUrZoaLO6judmklv75Vg/9rCrf53IR6/936cC8z9b TyG/kjZpAE9EFF2w30PR9qLveZfwlMVZd+Axt6oTYB3YXQzkgahk7JtH0FDYOvT9gXJC+ILJIfzF zyzDpCmoaIwcMVRQF86GmVW0RTpYKzOJqdhAfcqVdW73QrmU4ZzO7sxWYOe5YrIzxRviOMPP9/Hg YpPvDGLxylIjE2AMWC4bI1Gt+S453Hx5oFCNoJETG+epF142TBeI79N6Von14FQQC7Yf4PqphZhE dFeqPAg8Osw1mPc5+PUb7b1ye/gSMPh3EWGSbd1Xx/0Ra/wwBJCmioca2rvtLUBR8TFBzAu3Td1X fPTyIPZ4liKsZiCnAe/uhgtqKXdS9hlPD3lY41UNxgWXK3DK+daK+Rx3AobldEb3WJ5bZKB75CAv U4kwiLKKF4gO4g9f/5M4VgPmYIXFk5OhejHzUZLUmdz/HOA/JoVElRzyRMqfjCstNgxRrX6uHNv0 0cHsfSEbH0UPoXdu3z0dwBnDnV8Ki4zs5/kr3edkQkUIJ4x0K4SA12uWx9wOgfahaiKN+SPxvHKu 84sizWwU8ndBJ6g+0ZkywmtTERRic326xECyxHVx9lf0WdjadYRI/f4AqA2yigQtRfAsRvm0Mjv9 wwL3WJH+76JcIJEzuH76l7skP1ynPkbxascnBFl2dIxdmpSvXNdhS7iP8PdBWz1pC+e6n8llbB4R XpWpKvH75nITzfhpg8qqQ4Q+E0cakKZ01S1rpgOJRESDf4SL5c07Gjb904QREFs1yWwWL5Uj1AEU ezTJM4gO14//SwYBZiLdt05e5XHojxFcmCEWBuXMo9uTBhlq8tAOyEV5HpKILl5mCZGiKCUiM+GU HjmXfe5MN2NnnGLkBr17z9GkfoSUg2iiKltR9M3uLZ3C0IKbcisnW9ufNG1DJ481sevBR6dQyG3A 8fZETe3gQoITHZSnvUdE7Jqgqclw8sM2cZ52d69vBDMJTrL6vRIgXPrlIOoG+VrmFeO0ssSelyfY gVqcrUUKTrFucf9lqKIB7wTMYx3fHBcgIUKfGLYm6MMR37AdL46zX0oiHimLvau7i+aifeLOGiZM R4qgGWzvbfIv3N+0UXSEQqpYWf82aBI2BleXk+a2tbTJzifTm0mrqesMu+ETzGrf2gsKUIkhNfv8 jtCP15HNUkHcdml3TFqGaJRdofiESNecp/kV68nur22up34QCSZtNYTOGlbyHdsO6Xd17voWwK39 VroXhrlVrhAiPJ86tluEAFA8t/X+NelPZFYLswtCNH21pKpFxG4EZomYWty7y9yDAidRPQIFG5Xd NXoj1PzLch1/ei9n3IxXNbEfbF+4GTX25drexSlB9H34J4kaCr+/Dii5jDYpkVc4g/hS34l0vrwp DhAgG++sPJbVFvXK+o29CAIfzBF0V7FNH+5x4Hl/724qnKCfVZwPGGFf0y7ZGX1q7Ekn3osg2DKG R16ZOKFP/iesxibO9u+w8PUbeTiPCIWLuTYFrZ6VcKux9JLpYiUOj+tG2+mKI5doLQ06zcO3TfP3 aAi+6LwtaLErtuyubAbJrNK9dXaPfnh+t4tw4J9k0a0lHxHLI8kusuwHt1T7d+Du0MpIz8HDemif NMUsxIXuhp4JQuuFoPVknCDSdKxJF76rbOKBrXXKv7JeVTGf9bI7XD41BPdJjhayiIAb14JAoOpO h8+bscaZnJAPTa2homZfxx50pJd8jJfVR99CAp3Bp0Efqb5Qs9/boa12HSmnmAcE31MctOEF5+oM 2sPMt3KwNCFv0+bPfLSshGHUe1FzqSk2dsdyG3C0anrzV4KqFml9lY9sXKmhDaTAH6tQJeOcUqzf jeCmTnt2LJr6exRjINhVg0XJl2ljVmYsvcKBavVKsQb59lr4qkjAQoaolP8NAXwr5XywYoYuEDSK JxCLWotcdYVnEWNpijkbw0PyVRRqf5rHWD1RMN01ci38Pu5EMo5TY6oPp9hrMq2kVFsv+NaeZZfa 0i9bg54MNnS4U4nZtY71LSAUL5tCUjsFKjwWV4+hp40+3qyg+C+FzdF6wfbUhov4ELh7CPsT5kB0 9C/CnOVPdJDxLkTwfZMtxoCnXRmHbkbMMKrXfATyNU5zqPgLc7jb4+J/ExUcDNmJFA80GIfSNkMP DL61o5jav1nBcGqWCz3Kj08/4E1vXQLP9crM3joF8KbN3Z5HPPFQJzHk3+b3bHO1xNMI3JdllSz4 DN6kWWfOxozoF7rvffL9079N4HH2AHT9aNxbgO+FgE3MQ5BWlSksLmFx6LZLw461toVnN7iWCwOk o4cFWVRf3P9/G6UShpoufGnaBIfWyUUGAGZV29BExGMiXR4A8DIWVth0nKTEL0YXNYLpVbFdSu8Q V+j0Z+qy0FW1g8f/zMvQ3RqqRGy69Lh0hbBURuK7L4weUhJK1iMV7ehP6FWfnlKXB8JHHkJ+DDMt k9FqBxagpuDu7KPyPxnYG+At6LVFQwf0QTtaBlWicLYcMQZFfY/JcrWy8R4ICLau1rMNYQrI1sOO FhnxdW6r/Ck5CHehELkYNiNxAZyrBUlpUS5XYH6vVk0b4khUmq+b2FiAXRmVDsgj7c5SPECpQSMc vlHJqGLxNLr9eoLbK5ScDNPMxLruyZLZkXCcRHlrA8oIj4o1TSeRBwIVKK+EUHyZI7YFbfHrmLBO cMsLIwg9YsZXdqzJW5Yi2jsIf8PJtLU55GmbRoP5rZ5EP74pgd6BLiEY2hguLkF04Gbs/hY1XLqA v+tmbfMW/mdHsSjfhnKtoCTteOHKPQ7bbkqbsinqPGK8EMq3Rj8VFr8dvNyu9VufrUzuLoFav+sg zv6oXZUU5lJAiRnwpSUnx8WdRysJBhrfiVBU9Apu3h9MKB9DmOheRaIi9uf2vUPbQ/eqSWOaiCbg jBkSznjnv5RY/l8CJoNCNfD406s9fDw5SDSTgW1NztliqkOKFq5QTGTaRY2JmZI66BupBJm4ofXS xWUZu08VnTzxQKV8KMGrf0GCQvwoU/w9lC0p28vG8pZouwqGxyCMO3NoKGcBI+tRJI0B4RGar1GO 9j9d6nxGx36gafs87IN3TQ== `protect end_protected

gpl-2.0

37856080814703c01eb59f6a00bf8516

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/shared/align_add_dsp48e1_sgl.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RvXkQ8Q1bO4jVN0SJg72mk2bp/a8kb9Jd6RB/Bg5aFfz1cy7fMpNc1/hUuCuKHiERslX3w85Fk3S 9tdzdCAdSA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cvvZvv9BU+18f+ciySQzy5kJeJDMXv0JRzPA3pyidP1xwyLBrV7RfTEfV7eQb3xCSjYsGZvBMqy4 46JeNGQbYeOZwiMeuDCHpZD47E7gBxXkjYojNZFRDbAYM/J9JJa9svngcxky29esAqCmKJG43s0B nMU98UUdy7WrdECtE0c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block m5J3MwD5e1rtt4DSCIxcD2UATTXmwe3JH21qqkEG323DHUUUtme1RO3OrzY8icl09cdfIWqJY5AE umildv2qf0SHqSwZtT1ZAO1132fimXauL3IItgsvOuZ6IgyyyRAoDa4PBdccAC8rCfQaMh/UqjRC 4VWw8TpH8rcZURcL8ZYitlGAqJQGdcY8R8HTRxoBwdpf0eCe5fvl4x5xSj/UZ9ZIisiB41ah0pj3 UjdnoEhsOX7zLOZKQ291+gq5r6G37LY6y5IXzvzvoi+eLT1o5tEfGVemkqGCGfauTwSUZXnjTerG jIy/lg2JxJYNfpzBxs1R8f1temuouzTwVeeT+w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block tryOv/dE3EFUwO3dbmutrAmlOHeZ9lNAQOMnA4uZk/+1TOtTXhIPNWcymLs1YIGXaN5wp68xVOmY i1C4k4Ovhmpm6t+XNjSXsgBoMRKVXF/YSbkitKz67qVEyb/9VLtjMP8miw2RxUETebnqgiXmUndb v5PXKgMot4XQukIUYHM= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Pm1hHcjXpv0yceWkFm6aKnOrab6IQ9IS8+EUXbCi8QrfslX4DeG5cGyHj0PMadXo3ZK8+1pd9sbE siLiXsqFvPt7ggdw2b4TTxDu/unusBKAtzJO8bhFB5Mn+OoGdgpJE08qu1rWNzQ7IoVYSwZA8y/r apXxbyDPrO6fD5l1YWQxGpRNL//llOEElPOkoPFMIYqcZgih5Ywu7CvqgcexZRZW7ImIAz0dIsRd p7lU37cjB96tsiLtYlwPap4pku4hltZ+UmKTjH6suRqJz7VwAck/l8Vm5WltqDqgepTecWOpW4ca Dj9VKrxXDf1rSJhRANOAlHsrOcU1YQIsQntRKg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20944) `protect data_block zy42eyjxZOjtQynRU7OGb47xLzD14rSFyFssqQd750fK5WEC1ECaVhllxE8oGDzK9WkJ5Hm8XMGT 6akFDUREf8SZMS+J98W8A7DmcsZ47J3jcghoiQnrMKEJEpQ5nJq5J9Hb8uBipFJYMbvkidhynQOD Fht/QzOtmuY5I7IjEl8x2qpU1w6OZccvkp8k+Q5n+8WWeCfd9wGHDy6rW+heoHYAsMkaDyn7oC7b OLUbuBdpavwyvpyxjRezjiHqplTzfJ6yyxjNIH7gqKwx20wW/6UZy2DA8STLyAQSxPBRxyDc8BNq wkhpP45C/pKAX/j6UHu7B5dJBcHWyvLFx8ZjbUFJvvmWVbZy+54YAvfWVY4f+jwSzyuSpFM6ua0l EIUtRKz8Ch1IKXOJiAmKeGn7GHClr7vPJVkkdQSyqnpKxSA7spCSWq1oyi337j3gyyhvHpD2NNsX k4MZlJRmZExuUTqpQapo4OAEa1mCPtQxo/j7b8ufLYXhEO74KYguIuh8bzdaGJfyZoD1NDxb0l2y 4NbR2Qt/qSTVZpAkgBMc7QvtiStEhWp4OZG7gEF62lWG+sTH8QH/nOwyfoYR1FDpONOB3zlyrKMV vcjEtPpPq5JlTg/2fvpKaYxB3J61pPwOclN2M5MGtekQnZQutysrlM3112zfbODAxLwKOBuCSNkS eUPe4qOEPEQh8qD96se43FldvKNo2hT3vl66gCiir0eD5sFS2HsF3OP5wFShWGG1jjjm5qP6lCA0 mEKP9bytiabsJhAAiX9qCnyUGY3pX8n2b7Msu7fW/KzSu1DPOKFxnHnbK/CHYImrmf01TdOBTzvM jT0MDvuossWLhEkXK5DEMbohoctXouJKR5PERPJKCXsDRQnA601BGIvf3pMySi7ub/wxMzB22AGF w5oLTLmRki/rqv7SWd6Iu5ST2TxFOT3V0xea0/bU0BTCrDCNPcSC+8XAvjc/4yGmPoLPC/yrEuyF 8vjzqprouPPZpP80xSpRy4RhADUT/BqVgFCCezGCxDvIZIHqoZWgg4Iz6wEz4zV27ER/GOiYc05r B7kwXpvKRnI57mJ6sUNnSkssSHMOyvqgWBjKWWTMQ6qJqzZoG2yQXFFxzMNZeZhiEaXK6MGIWA6g GTqGkpE2p4Mi4AX2O3UFx9mmiifZsIywjr8RD0Mo4kCuwkcZvCuugE+NMJw3rIaBuS1urClGWjDg 2nLg/+RPli6wtY5dkReL3yMvq7ucLykdyRXWSC7xRxZqwPOvelTe78Ed/ZzHIEp0ISKh2XcPy07a 4MDUVG+0DQJ155lqWDm7MJFCF6S4QBT8ttS2YFFcb1IS1B/1ZMMKTY7QoEMp74pZiT2/YbEiidzg untF8gQS/Z+h4l+pEMZbSB8aBozGGHIWLWkIWRW3GJChPYsm+YirVtk7zgnRcBR420udFNKhjjwN ZJyNhZIzvrc8h8h49ddG7YZrrHvdyjyjctZtA7pO5Nf8pKVFphpxlShxvHnVMFRuCkjBJDLDwxMw l9kJianiq2QncuAQgMBDLo5lEHVs5F+ErD4DZmuaw6HwnYiSACJT/e/IVDW8jh/HOMxG5polJZWA 9cAsUUZN9RtJYoQSVyUUdZwUT8CciLvRch9TyqzXoAheWMeDzWNocqm2Hgp1fyDU0WVmJqAVzaFK 1YghfiTRdyzctvCGTj4mm01camHpXeWAQV4Jdx/OrKEm0giJrtcAI0Y8DlzsCufsv/ybEWezqSlh +Ah01QpBfdg6NfCdoBZE6pJ0DuKSqvI7uPkK0xSlH1WRbAHfmeA/dZvJ2a/9fPooPm0CjfM44g7Y eOsdKx3ILEG0K8qPdT7FN4goGsN0R7DOGZ7WaTAQhyANA7Fo8CeYohpcSu1AJy8cpsaO/nTymvQ7 apeEjMvEt8BNx8O+y2kYLWV6AYy/KV0WdfsdZDmdT7bWjEJzuY4oZCK7KkKgmWwT2hSTehKa072p l4qmuX0+VGKF4B23gJlkWttaudaXYJl+i14W1dx50SpjzLyQj8oCYgWFRWBcMQQQNNUEkrK00sGV RFnQmdwGXpWA6qDYS5OPOuaJng6CaCL5AgHxqfOiod1AR5Mu/TIG09SYavKgSfcgc1xMSFIM7Eyn qZs8kjWi+P3osasz3BIJxfCZpYYNJ9zxQpl8yrGJ1U7CBOJ8TEkl72IaXTRf+VoKfAj1TWYKCz0G 0hcAc0P+ncbnKemEMU6sb93DwC8X6+vheweFlvE/hXctkyByEwKtUWE6hOOdKRDG+DB8Ce5+zfPG zZ6t0gydOKH3EqsLYXpGyMyxbvas1RGNQghDaluNEL5gPct/wwxjIsk90UP+VTG1hOCNxvOL/Pko KZOu30HfEwg3vvFRUDuDYvkg30zKk35qD2Tiz0RBEgHdt1d9iagFQHIjphCarv5n+NX9qzzdBs0U dR58n+Aa2wmwHHqrmGjpQ1KgPyTPyFp6oyQ1HlptGzTlUgS83xhAswjc0/F6r/qUTUyz4B+TQVvE 5aKjUuJ0RpH5HXZ9CFEuhc8VwzbybVgmeYwJNcQ5oZv2F/10sj6Pzv0LiXcjfo+ookgkaFlEctb+ Lc0y0dqqefqGhrEXoeYyAdw8K1pZPMGNPRuZkuPD8WDAJKIJH58QFzyLuxKwja1eBT4sAaGOwPL/ NWj3H/j/4uVS1lWGxjD3xkYdeQejj9fE9uhUm3AKnqhpwjk1kISIXLleVRoteFRgU4XoCy0as2bq RfC4ZUobO8WWydo55/6TBqEyIgQAFW/wLFfY7UWmYmIDPO6GyR8nA9JOCbINb+trWendA6QuHrvs cfJcAqlMaNsv2pTzX3siVGGu0ltMGp5IElFgMI0pWS3fK5BwCnFF8LM1DK4KEaqI0wNgI4+v55sJ FGytEAvMVojywFUeXuGKJuU8S2vcsdm6KWbFG6oEYRczBFQMRj5bu3lUpidCT0X8YPoApHmxjdhw rVOqDAvJTafLICegnj43vXJxelm0XgvWlzddLh0qiYMu1JPw9MyLjatTOJlYgzPgjA+HbwGY7gW/ tH6NCVyrIPRb7dXFMoALJJBQrjHapAghFrKLrUwmHkzrTH8zF5LfLIyVK91uHeewxUuugP4xuD3B Kte/8wxF6NMRDTSG5RkOovPGuSUHf7OU+AinSpoyz/O0lcv0PKH7bRLNCd55+cZa90sS6k5PimxW OjoUNUDSY0N6Hvb7HoTtqWo2zwDq+SOIxUkNqNgAg1LBxVI8FUYlnpPHc95uZlpWV35Y2bpNnODu ykHVfeC/gPbOPbnVTsr6CLnJ6oBF5Nmn/5rtOW3jblXFMoN6F30RdPRiBPLi1VUNbpsB98TVB9uh LWZ4xhzA+HPbu0JY+tFQ7R70cdcw9qCiKBqDNVZd1QPvl741iV15NnK3qUp6P8nkqam6ZTftqfDp N44ljD1Z2qBdU/t0+wBiZvACMKk+/8pvlAd6OfFLHJX/fQem4r/ljzZHAVF+HYBhOg/zZ1PSMyzm Ec5p7NSmdd9TW/27sZcM4PYAYnXedlQ0hmrhWxkMXhlIYmFOtqyIfN+PGVO0DoJouA96ogKzTdA6 vtVyGcCLON+oWXuawK2/5g7XvcZjesNHs2KhxARIu41+uojOs6ylOnGyBR0YGx37nNQmGb/su+/G 97RYbOc88fkSPI3OB/51pu3wyTNZoa5xkJALlbVjtJ7ZyMOdui8qn0BWF38iFgwHoTyYa9/eKY2a q6Ut5dZzqIT9ud66GcKOaqWdhKKgAz/nqhF6X+Jv9vAML+0Rd8EqyGqMBIb8RMuBudViIA7riCcX ZbSSx39vfTpuNVNp92wPGwA9nXXqiWuYtKSFl0ujq6mWco6DseHcL02XhvqI5Wt0JfhUITgR/ODG TWJdqZqwvSTuh9PZzuSmyGa67yJmbCfKCCGT9Qi0zMkS999AFw6fnht2sf5N5bVLcYrb47dKofjb AR3wY7lSQSQEyw2a9MYJbu6NCBGMcNQ5cy0E4YmcPsMIpiQMXkjmhzN60NK3it6sMkaTApqaHNPP PIWcSCwj7fljrXan3fmavDbdAqTRamaTtegr1sYpawhzbTBM2JJa0SaAFwdzh2Q1kDVdYSZSlxc6 fHicZJOV7dd6gZ56xH6qd5brt5Ijvvg3VgtWL0uXhlStNQvZC1KsAAQd6a7fYoV5iQK43gLfDzRk ASmSJwdo11VfWCo7qhmS2T9SsVWNBVOlvERMqJY6QkSFAgDyvjYAmhePii9UkdDrEIOd3Kg2GyAV H28fE36hwklE73lxm2jdh7aggRyVTmYuBSne64BG73wsybJO1I8d65V96dKKj6UxymLliQIts4Ph IshOOKbe7YF0wCjI/vYgtS8RmaqSP5kynYkDWoKMC7r14mOXq5ZCH4ln51Y1LXnFO3Tq1fucRzgZ RxGrbzbwGPhFEJioCS/1h4yLLI0attU63PVMotnk+dCCE7JxLkr+kMssYgMJpNs7RnzFwj1VCUFN 5PDTjK08X6f2hh5+lvEbUwfWGXkHmxeCNrd6yMHXdi5SrWJuWxbRxz50VRn1TS0b4iO0Gx4Jkafl TPWdxpTtQezBtGd0zDUnDpBl/rc1YzM7GXaFatnWlEKtGXxRRjYUUgOy7PYRgkbKNxstky1447zm J5I4DkpOsf4liOZ7d8c3A7vcT7P4IChHfGIH/HRx3L5vEsYEWXHmSn5JpDslkkJLFnVvae8Y6Fp+ E0YlF1bRqpUnIaJEo2TvCxRUsggxak0CEC0KDNGP59SEqTP76m85KJjMLju+od08m+czRz/h0rPb Ad2WgbXGjmVZhYP7P9LdfxUM/b7vkfGPj5r1uaVBJH8+qNQ77V7J/Zh+GC6y+iSD5TjpaAiPbTk/ pyVBfjx4e51kCN20iLGgftUOWs7NZQqOVNifadt4qiH7PXaN1BKZj2FBhKxnBdUGuqs6tfKlzwLw a15OPXqA4OamU1jR0zCIcSCABZbnNCI73Kv+ZnvQouSQPGzMeAcyV8Dh22NCA9FaNjxXE86QgDMu ISstCiwwYez71gRMImi2mEUuUOiz1FyxLtCOQvh9GhHa4/HcYiZ4Ft7rl8k8jksRWQEzSyCmj2W9 9OWD2DzoXE9ojSijSRE/V9Ssxqv/cHWxEWqxzx+V9O1xxHCXfm2H+LMkmPgVKRdzyhdeA1H4pz+0 RHcu1iwHJhe/6KB/yYEB113nH0FPX+fKTG6yIyiZmkdbrS5kjZ89OBHcIuYf2SzF0Y12FpqgFwL8 Mn3lgMK2gtrYxXiX7dcgrTvhFxDyQNzLk8dh6pepwlpmwJjbFokbS06St3QOtXxF/pWjWAVyKMx5 FgBNgqVDk27MOZv4jOwTtSuz1zoJqxx6Bd9kDa0jMOk06jCHznitfR9KN54mXjJ6al3IO/63EED3 7Xixu/35Au4OOTbxihdxdvUY0dp8pA42c2cSO6DDRnXbffMukSRle+S419YHCJzxh3dcbg6KZa15 7W0p70xH4oasvlFQhenfURAnfi4F9Wg0LhyGO7zdf87ZshBXvuC4MR1qQkNLxIw+8HAp3y3ahf9q uNVRLj3vxtx4dj4C7llbnADM7WA4j1xGrpsf3/bvqrOymvKDaw7/5P712PgdOoGvFdWiRx5SGhAc cojLKfAMvQpHnKB1ViO14kBWnScp+3cnpqTqpJ5FFWOjllFd8b6TZbxvyJvsaweZfoPHwO9r63TB f1Fu4Ws5uIGd0M2fcf+XGM9zy4Z/BEXVE07vVkw6YwbufHhF12B/78kJKyrzI169q6ChLbVjhcgq 942KN5pGm8mqrnUmqoaJu4AmWUODUvtRcYrJ1mrVgZJ+lz1BUlnBKXGHTDz3p6uxno/SIreKHS6T kIimI5BxmQeqBwvp3vlu4EFWf+rQYhNGkDpn/VYJ1CenJogr//Kyx6yfnyruqB5vWs5FJ390uWuE x5f5LZwjRnhXikrEk2DVzWU5sde3qy5wE46wdgt8VcIGgaqDGCHg9bWaWA99kRmbJJP4INHZeTNZ WplEQYvmZqkem49vL5gqTw6W+WajnS5vGiJayU3fIYUkNyqjmGC4rkViJ7ZRkSDBjoBUCpC42Wtj hX70sZuY4sDisdB+URtczFuvV2JfWYNQyuyIrjrpOPouDb+ba2o2S9mPrB4zid6zd37ak68mbiFX Gny8/mR61tMlB/dfinb02pZSEzQSu+boHnfcYE477XmT4hsuecFLtI8K8QNDvi7xjUAX0yy8FtKB nWKEXXpeOtrzdVKD4MYUNWKKKbPLSwb69mnn9GiFC7y0F1dh7+hfnsI1v90OMNACFSf/icE0iD89 Lgd/K401xQHSxUxVQ+wMBDm52NG7EfVy+RY4t8TtCgCJmyXrEY1ICxpR2FLDnJ+05QrPVEGAh9GD ebr7zeMelfFS9mMqHoUSQTuGLCT/jehy/lNrH/lhwl/VB6CGn7EZvYHmMwbHuvTCeuRJ0BIxdfc4 Avb1lqcCLJ3YgrfeiamKuBKRjh0gTyXpSU5Lm7fw+VdslrZ/xAvH1h9GNiEw1Jb1tCfk0nsx3xRu WZU+TDmfileaS+XtQl6rb1ORyf/Jbc2Wv8sSffjljhEuBmRw+8pnfwWT0DZGjyeKXDgzHSwHIOCE GykPzkU5S2a2jf2ykflHJftKqRdXT8lxmXrg1metiL8ciPV5klvMvte03YUeQq29WDYGlUQHYBh0 YqxNQYFdoUE/YLUeMX/QAX+UTCyyo1VqrzNpu5ZDv+c3B6y7YDnUY0SE1Qy9VfCrTW6jZ0qPEDYh jH5EaJDxOyRvGIV8UGWpmsXJYRfYFWbp/y/gOTCfOet5lH5o6e8kkzLyosyqsuxWhotNfbvFP14C akRokTaYt32XDAP8bd5reXZltdI7f6pmlQWNivd4EaHcOkSnVYISS0K6Vdk0rU+WhVkoKTsEbu4t kVGKybx4h8LMSP+RUcvZWf6oL6ZyEC0TuxPKqw749wMExMGeIW3ZpdfoGHq+2H+cLIzkMvwblr8q x/cd5pgEvLrn5AmBNIyrrJKkB4m/vXX+OTjScGye49QtJ8a8J9aaSJPBgVXQFItD8/BIsmtAZGBD hkNTPMpfvQh92BSCc+Lev6E+6OBrF7K9mRXkCgurOJhrMZCX9yI/6o+nZwnfD+bsVp6x1YIXQPBg r6WFuGHZ9i+fqu5LjxdGPua00s0j7xAyds+sX/YDcYkbY6OW/GU3hEzvflZWPNSZ8gcTR+LiNlR/ qn9o/PvcSgTs63JvLBOQJFz/GZ4cDRi748SwFch4H+xFrJdI1biiVspUGVEFS2sisAEXcbSByZxv pj3m88TgfAlLrCiFIKzWb1IOOmOIxH+GjzLnQ+zONUSCLYcqGlvB47FQpS0O2srLrWzVJ3I19L1W lOZKd12ik655QjfDcFkFWwe6MtJ6eUBeA/MdpOYLD+EsmXTxsXs9/6SMOh+ImBXReSYB5CmEfwJU Gzv8piDRJH8/wAP1kmNJChI5/kDjQvBTg+ISHfSWc5gdpKMRueUk9E+W+Mg9P9qT/pz0eRAJE4ao 1N4k5UcGZsfKiT+2KA7yzT4upsVbkotS37I0RoJXB9LSli10bACXE3xtUsuXMiao3NBuBauZ5V6k 2RQU19qF94ErpNrHj9VuZoHqaI81/M94zRxwbiYYg37TNJqfZpwvhbdAQxiEFsvZZCDMZPMRq49Q bUVfR8rWVbPPzHpUjKqQB+M7bOtIWn7d3zsoJtea1644d5ofRLBIvrKNdOLLLjekurCaUMV+/yQQ 6S3gR9eMe+aCAKNh+yyf7B+z4vSZ0b4PST/lOV3eTzrwngkYP6N+4n5RHH/aMV+6O+yvUX6/tBOm kCsXg4D5sVZf5kfMuDpW3PKj6LiigFrxws+WTpKN6F+Aq+RI4Xxj5jRmsqhQeEHm4sq9OI+ZFvTh GiB00NlYIRKpAnPketnytNb3yjfUU4KOG5nQBD08vK/6TakKmmkTwFmtSMsjCwDoeUf/20GByctX pQcDawt+wyAvO2Sn96MgG2YdS1X5xf9AuoSgVcyf/hXENPhlJVDLnAPxPDkHw77TipN9qfd14x+v gakeU72Y5L8K66xOG4IbflzcfqNEnHUNOTBhIKtoxbXlpOc7KMkAF6G59n6e0CTwB1gsJRTCvcQf e9xOdIYVbCd7CU3e2stAqkxOVZg8o75vGZeOLZGqvZGHrRs4AbW6ijakJrq6nbXq/zeaOHZz2u70 d8jYg/letbQYFbdvCCMxaa/Rv4Y57GHxbfenIEhVzLtN99+lCYoSD2bngKvPM0bay5WkFAPSm1AV JR3bSyKSpl4/jdUO86w5IVr5ad53Uq7S9r52walzNYgJAP+XN3VvcdIfcxayfcDsaFuonMFic4Kc bp8S1L2Ew1u4n5iZuL4cUtme4M7bU3AmMmsk5aU365vYVPlmNJ+N7AhKwzN6v++C2dWlyJ0yjZ/8 04gsTOHzM5CsbBoHl/d15NTvwQ+XL9MMVwpsQ1mbGejbwxyUbYMSn0s/hgT1TfHBRV7UszFdnTAb WocyMNmi6um1fkdoF7wzacsN9QO75uU/3ZLl2wsoBldBnxLx6IctQeDOl+a/rDpwHp7JTKTSoeGe ALt5x28MD/niI5KpoXhE4jqNJjEh3ML+CTO02B1y4rHJW9rz5q2wiUKs/2qeiD9DZMgrTYw9D3Sp 7U82VsaNopGIPcmHLQGA3lb/PXzhBXx3OMoUcl9Zz0u0N/5chc3XqYB5ZssSPA4myyDUC45Rljq+ t5qdWmg16hAnQ6kjuVIk6mRLzZQ/eFTiVQ1niN/bAzcfC4vXKTwMuqHGks7gGVAw+ZWSab+roLtq UU74o33pkRTZu6zMgcGhyNUcycVmVHaI8hXtaD6/mGOjIix0P/ETwTyMhibvmDd6BGZiNDoCOVoq crurssAQHg3w6SE0bwSP9567LsyStBQomNuq1esO7JDyHJa0VFhWUQ/G17lD4rHmxxKEiLL3N0Yg Y+ENU+iy3pZNXSb7qbWEQhUvAE4HQ6Y5qdxdKLbs8XrRHTTFu6CKaoMm4LQK1PHC4Fsp40RNv+B0 X8TyJu8if+xNhCuMSl1TsCkv66KPg2GnKKJA3mokT7aa/YxTfmSQh7uyLnJlvxjJOEows7M1rliX EK1xjKFs5S6V19IKwEZFNXNBdvQp1mbX8y/iSg3mF5bvcKoUSE15sh+2dkS9oxUfASlJJrmBtrtm fj1zfaflMH236Soa6WLzsaxakkj4ZjAEOiJG8Nub63GkwnvCIAzWy3GSqADmozSGeGFQN0CYFHPc z0KFqQ1oikgVd6pc48FwxhwN8G5ekF15u8nFkxUJf88OdaCd2sVjX5IDEQ1tP5jUwEs6nWpPPsCo 09Ykn1sCBqZ2kzOZ6v7RruQQkLxwS0hkMDAYXpa5/4HGfyc5SQ3UsfOnm1+nPt8nERyL1L9Ej2JY D5gLeZ1Kram/cPZW992SiZ3UuYwSP74GTumWJl7SaXG5eNKFcBhF9IbCO8VIzH9LNJmUuIK2oqFX KPfTBhpgVKogGI0sb0kHh+tArd//jnxhy7+6iWv9mjj+SCjJFaltM4CUo4jrvGCUmODNvF5rmrLR icY+8M+dfYGWjz2yFkSqTNSs/RAwzs94+6NvXhVWkpwOjPQAPPhqxCBwqZmtTuGq/VNBxNetgRhL gJ70F+4GYxowGNC8oQsuRLK9EfNgDVNPYbVijZZkjcuA7x5vw08agtf3K75F0jK+PyWtP4VDB8wl YIMByJLEHlD74PlwzAe2TfJUHqRDPHnvmUq4yUM3scZY4aekCCv45kk3vW+dBtEHnUKzuwygYV1t WR5fvAfi2/tUG7zxALYdr0c5TqXgU7Ek5i9uX+AschQElq02Yaqa0XGmhhiBqcMt2ILW6/2W/i7I G2U4Hjf+zPOG8DwTyUfKOYZIssPpifaiYVFuIHnuGE8KksdqYipwOynqssmsklOi23J8YXecHVZO CHIjY3ti68Hd/KPAqQKxXdlZhsE6rzaK236Z6uNaZ3fgbC93f6TVKp0ZVsAr6AA8ZZH9gxkWpSAU NBIPUotQ/rwE4Wa3hcN/aI8GngyJH2VJTT5Zec2fjXyRXWzpdOYD0LbU1xG4q5qOfMsQFaBAr7jX sZQDpa17aUrADcCFHscAwCp/uZaylxuM9hsF5F7/4J3cR4i1RAT7Btr6xSbvg0EDiQerw/HEFmT9 pCb66up1xSzzq8cMW8fnhY4GevtSR5QM0l+n1FoqzlIBIvqWWHqVmWIjxjcDR28GigTDGqXezKdP 9wKSNO7zAIAM1yP5Kxk8/eZIcorLGc43vGFxzCtoD9NiWZw6gM4z9i9igRXWdceicY4lM6G58Y+i cr6/8JaWrLnO0oFtPJQEsOLeCaMBcNOmA6xrLnhQLAplKn8zPnmbll0dJ5Q/gZRdu+CZaZhiiWRQ 8I0O8T4wM9O8XNf1jyuUNjbAVHslyVKAZVmC/bMQ4RM/7W7XTerLO9ZaU/sgsyuoqPTSczbgT1Wc UgyTcfEfVfIPdCTlTVLLTob8tGowNtp5odvT3LgqxbpSNLOOKuM9OpCzFZ6QbZQ0fG1xiK3o8QIl ewubEM2T1LiFgjr3iXGPhzXiGp+9OpiXe8H4NZVje8zCRRbJbegOzvGzEubYRHrzscFJPVrXrkpQ TAc4pp9GgBdVfrZV9CAkMzvHW/JMAOTxgY+USkn5tm2smSuknqZ6M5tZlnimrZa68NLsC+UoCmGm DPMI/aKooZhKRx1GZN+bIh6PN2/R1eyiv0KOuN0vv12B0xCXutkcrxOUQCas5m4YBXJX60szQxzI pyZ5Z/2d1aOISmbv+DHviZr+JTqFE3eiTNEGmDdDbNNIiizVYzFsYERJHnyWmLj4leMClUwEkUWK YZW0QiUHYyiP/OtA6oPg6K8gll5e9W73naMTDM2h6QU6teFQTd+JBhSgrKIiIYBq2G+bJ00KD/PL 77KPDD3rnIT1m0bVKhPUMYl3VphXgMd4Kz7aeK4PGRyMKx0gAWxPFE/TgjFanosjGhp2gewLE/8N y/R+QUMq8hHsws0ILSOGTSY5m9xfBIaXhXK/yKOjIYRZL3RhUH9gPyEAjXCa+dHi8pcgXyi/Mrp/ VO2n82NYhsV0L/M/z6Wq1rRKe1xb9iFVvKPo0X0GX3KcPIac7YKeSdV9Anr1btN7SvCfAVvmygBh 3ARuwswXSVj8SsbFsxaNWbT/oGc0tiB1coJXi+G6V2/+olWv0LjsAqcMW4HM/HPvX8tf7Fi/HJMy bqRxA0+nSCO9jc/6MhA6Mm8epi5ZHwSfGJbncwHrNjdJzV4zSWYgvpaRMtbxz/2BKcFPsLuxsprz 8Y3dTYfw+xg9gte1QIrfv9XJjbQlJ9J9AJYaZjGMQK22+s6aTZqoN2o2/loL4NMbsdVHXT3DrYE5 tlPP8VrW1hr+0ZDlxaeVIySKA7n8GjNODO7Pap62QhToHPwB9sOi7KmHebxoNn6FUPQbyMNQGCJI auKD96N9wteON7OCA6OrISc6ZADliwSsP8KJ44AsjwEvlE2W4ulKwHBrxnTsUnDfrO3Cb3O52E+r vRkxmRyGWsWzmTsaPvB67zhKCY8/xkzHYhFQsPH9pI1wmd5ijJiRfOJ7JyjkiIi65/hwbk0ZhGI9 YakMbH6e8xs7SV0TfA4/A6VC3ezOkZR5dSOmM5vFDH0LIy514wR6JF4T5PqKdtV+Dw7uarNj441x OGlWeRlcxywzWLEpQl3Z9hwFSitMoWUzcrNdUcMDlg91b6jBeR0M8qcki2PjzZkNuoLqBXR7ZTtM mASej37RWkxcRvMB3mWLLo1u5BVF02j5R/P5xpr41xza+Jl9IW6G+jNTPvefMYbdPGEO+Pm0BppM knU+JiYahBhPPL5fvx3ijy3APU3ON1v0o9WMtDl1AGBzcGRukJpTH3eroG63ly8LLJb57aAHeeOg ixjve6y62BMDNuQ6wUxeKq5EevLfkPZiRSfj3mZ94sVbc0mDpQM+XwsIx/JAEWWQIqRjTYgMM1+0 Pj0PhFM9E9Sm/xVK1NfQDlEXJDLRjgWYjb8+eKGsT7fwnNwWda7A92hV5krhkizbeuvnquboC38/ Dfm+YZOx2etZf0I5X3kzPcWd5YjihrUEOmfqapjOo62mLOPA5AEv6YIswKULi4e742FPMNpXd5yT dN8SVNNyI0gAMsO3/lc7xROEYRaqZa+dnzijf3LFkhacK93sVt4uRl5C2H/K32/jSMkdNSQHvdHZ h853CGJ81IajiXDsdhVrOsOj1WFg9Wzz8gTRJdSy70nty8cAv1ehFFimlHAjDeZdCKmxWNsGzGe5 MeRhqCffOWGqHLrw5hajrrCItBwYbeNh/9tRIjsCtSCWYDNHJtKLydjPFHgYlYr/gIFkcQY+2wfk 5KTx/eBzzbaMVVDRJlH+BRGRQfVuEeePw9qJ3Vt3tx1stNmGFFYY95q+N/swyBzYbGymp/cbhVvq 6rQw3SCr3JW3ONNSCxYF2zfnKGG8nKS4xeru+azymACRpBQv6vpzgrgrUG8/4U6LcxAr1FCpZhVP zmJ4Gm89klFtq7GOjJHzGAL6HJ2BwLyX9V99EKcP+86CxKukAUQDVC4XFNhOHPlmXJmgGjn8vYAi 4GbLuAYyPl455FE2MYLiKv3F/rwaQ5rk+zZGCRkgKjhEJqXcSEyUS5ojJnj+1NYju8MvRInFgY6T ZObizs+EqVIiyzQ2QXNzuHs9fvlnaaaaWebdf9+D9pCArpQkilrc/U1nzYJOcNJwZLJ5pIJ1AbP7 X7NYfQBlkPHrpW5ZXZ3+R/kdn4xi4enMk82NdpwHCMO2SIAqQzBS3BYiBbG9A4fOGfFIlPQdH6nO OeESwRvtiN7kvL/MI5uN6DHuZZ8kiqE8Th9LYWjfSAT4dv20AZWj/7etC55QDspGXAxBjVjn+UU0 yHretLLZOnUUF8NG1BKDgDV73MZLlxl8Y7uk6zzvNR9RurBsUQ+di5QY6b8MoJKumzBQYtqauEM+ LvUREFgRGlHonUw/bm4x77V1uZQ76J0894THl411cRweE/4wfgoIsEqJGF/6yQgD0uZDvXyUdJ6h wp07EPN9vOwKJk3UkhWu/2qeZ8BUsWjG1X3gA/gwDRx3OD8+A+ulMN8N51fGpJyVNurYYiJL4izT BdAHDsqX30qKA2x8tH6koZTAXY+7HCLrAHz1Kbh1Uvk6bgv3oBiCb2W9DEqm1nQ+wU3CR5BjBhPg Xkk5zj6CWgmhcpACwuM8hS8mmTcZyDyGTnDyrN4nf0iFkowyF1oFr7Xwg5vi3aAvPTcSEd/X5FO5 4x/Jh6doMLDs15p/GVGnA38Sm7VN9nQB4zVEbrSJaMsJ1rKzZUKGYhYKyGOETBQvBBbCmxofsN1B YNZGYCAcUioKilzIGfiYleVe6SoDLV2khKCt7sM6cxe059cHihouTrk2o0fstrVlnLFvr5FpcPcC NM7dtzg0LFZ639hIAF2M1Q56WCkJ7rrYVd4KCfg9fEqwWb6ERluvRifJX3kL7mMcwZLeGeiaZbKn vl/5vE2c/xScLFhxSkHO7bDQgDYokqyvPabPNYJnNOA2u2v+W7R8hI3gBEgm0fcfIw0f0KJLV4ku 7+fjx7euKARVxRb0lYwEOMJH+MkFPBdD0p77aopjA/bDqfOXEOiba2MTy/rrXO4cCD0rvgSX6gRj zXzNgukAqgnL+WncWCjLm+5c2aSriUHjoF0xuE6EfD6XR7aY6L36n7Hs+4Ml3VbQhQH7GRNnMAei OinT+xO1rjc1D6ZgImk4fPFRkxfG/xcsdbIPeAvk6/q+bwzUM84tohy+NpasG50kI+MBjdA2xadS ShOaOWL4lFVgX0k5bZQgFVCdtnmqDRzgASp+8yKXQV28Nj+VvUaNW6WPI3klAOnON6dEEUUMiRCW pR0R7WCKYmkXlI/sDxL2z6Jrls7fRTN1XigqTshDdCvK4mk6cPZbPBvt/kAB8qYgehyqu7P9VNxT kmCh3QDk74yr7oLgBCZqz8oiT5zpNenr/2SBtdjlXK7PJ8RlOVcHl0WLqBYxRrdBstGxAe+27ri4 4jLjEctZnV4zDUYhZ0o5nlBnRkiX+WSKRM++NYvZuEMqoWfFt8FQaQNeBdyjLrgWA4T7KYZoPk6u jYrmWY948wm6GELNzyJbvITXn+PfjyFGV84nTaLDAzSgukdxFo3XlT+QsCfTs3PwVHJnWXR+rHSv Cl0Ga3yhIREvixcB+FDhINVBPVzaiYORCHpl7zBRvL9g2Pr+g/0Z3laJ75g68OhIBNroTy+Cl2Ca PtNl3aeKewfN1rMJmY9NUu29SdRGBWHvT2tcVUsM9DAff2GKj/hpdlm9Hchhyuy1QCRyKbtiJmkb kcwSdmXzZbYh821RvE8J0ir/Y0lNTlrwuatbplFQ+GrjUe6qWN5O3xZhgETmYFwaPpabjedA3UQS ZuYU+pD9Vx/YQ8GSxcZyGm4qHmg74KtEsRJFO2pLgwSAX3KWsPQkVyUMGt1iVadt8y5uXDcpWW8T NjFWV7LN41selHro1Yk6xz94Ha3k50XCvswGJD4i/um6S67voI2FViIGkzzIYQ3Tuvy6j7t13QpN WoLEZxJrxAKTuVKPtk5ymQ5Yvd3OtRG1Zl/6lNNMGrzRrKe+1n0hZDAejp4rKf1Y1NksI3/JiNKU iV0lcl8VX/ZlfWL5s7+rDA73k9UJTvC/b8kKhlZ60acoo4w+t1JjQpegdbs/LuCio3Calr+oOoRN B3hE0k+i6VUgdzJEPjZxqQeCWdvWDzO8Yumc1NRF6tW6dA7Fz1txq696ZeUQqWe53uFNTeShNOJe ygpw/kXLxGqKWWXzLXn9o45LA+Foz3DTpcDllI6B/w0en7wA65YG/zChKuVQgAtTNbKO/kQquc5r jxjnj2uMTWdXoj0qmSx2rZFt6cc+rYmorbwWBEV6ks2xXOdQ9ZSn4g9bgLLQC4RjHnUDnxzfPeqc vqQo8ZgSQTnLKFiW69UGF8PSS9iaojgTLqEmDuFkqvBdXwhDAYgxcLwQRpt6oArE0VTsZo+L6JVf SWWCvcBuYVjcKj15t8jwRFbfPnsoCJWPRb2tKH+iyyd0NkLaHykIfLIqhrAstgqudUWzMZj+B6XY +Kr8SbVawR3GA+hdrEIzKFhhFComb3oHkDPdOHBSA+xXdSPZfw3NV6UiSveln6+jzT812//DDTJf ggFDiCvwFrK59Dgi1TAHrkETMQusnFdrNsP6lMwYxIH1trQeymy1gSiPsPotLTlOnbr3TUfqBZvH VnuYlWuUBZbStMMnHN+ex1lWcstAUlxLQbp1kDYzLetcpcmBhH7yNPMuuFiQTtVF0tQMPOK1AEq3 QJSFPhBndft6uwQxEYBq/w5Af5Pi9BIcIvdHAZC37cd87SXKKwLUCoc/gy8EQwztJFGK4uHtvzSg EyoU0nqKLCJGcaORitA0qpMg3mgtvbdgEoC+JVU4UI7cRBfZ6p5LddcCLVGhn6zIY7uPpPAYGBqW 1QR4GfEdG3q4zrXNEAMvoEZ7/P5BCqNpJYmt3klmkyKtyhrEWHtBCnp4kze3aVAWgaiIj1VOSdGU ttamSyjAlHUTALbJSO3hWX57OusMYIgIni1ctbJNWS5+h+rF2uEwn8/RSMoqT5aTTkUmdzwgQzyY jd1n6dNNLtrBS0HLWSeCp2ibiX4ZX3itAyuqGlWfKMj54y96Iu1rYWg9eQRfyVD+7egXU2ulN+Gy Dxc3OWwrEX7dm5cIIfDhP4+oNcVtN/GIOcJxtjdqcJiVZg/hkd9pZxGPPZY+/WGCd+dc6FsBM+Z6 +WHk7Hw2vmXBxh1ROoqbQjll/MAPeU+KaI6KqNf14vUMdvEyX9S1c3wLsPB3w1DZtJEn660ta0vV 0qYSxFXjs2idMnFZpce+i+coctx8yg9kKLqyvPiBbIAw2ZTdw68Bqfhm+4+1FncNGEfFnXZN01Sn Tl5TT0ER7PzWUDl7p/1hjoMqXlAexFtv7fc0iR2O8eXqImfZs8wORk40oWs5jnwmRfMvSzOlG8WL nC9CYe3nSjC4YkmJJUOMveZv2VNCidGdy3rxqpnee82JN5o7IbwoTwoTa55Ml9XO8xqNA2XA2Ohu vQ2/XYyBs0qg7g8GLMWN179I0eEmk/0LV83r0oiG1TzhN2V8+42synYCg0IBRgG5LAm7a6qPFoiR M9UB/Sv3US97NAPT/5l4hYPZJOBKjImQrSeeJ7TYwplHCoiyPulu6xn/yCpYLpoM52Zmcl8ADOQ4 NRZzOxPDKyGDvw2yyLrygX21E9ihtGsOUZFY4+na4orqFz1dArpzi4LtrfYE3otdk2A68CJy5MvX kgSuYEHwy09eme4IMlpOC/swuVbNRUzX/wTsurz/xW1n50DMTrd/kxg7lw7oJeDyQ1iHTz+m10Yl rsfB0p9LscKc5n0xBfH0KbEK0rz8ozcoaUJc0aJTdxknmfDekKIxp9JEWoKFY3mxBfIGi/FNR11Z dyJY6xQsfytkWkd0ZxBR6zL5mto3qhLorA/ylku5qJSDXXh0hJSBY1UMQsYrHuliGoR8zDgh5qQr C12JCXT2oBWptRo03qVOXF9z6IWO8LWNXMiy2ZWY4R42UlVZHZjCx6Xz8z+fnnxuiVRYXTiNelZ3 CoFXXdnO/H9H9GBY8/WWN0stLsbNjvpfRvHxFn66OYMONdE13n6XfpwnAce8TQSW4ShzhGCcVs+p sn+Er7M2l+HhJu94MHUBIcdcfQUt5rTnAuK9D0LZt6wqbsZlKrmnbZp40xA4c7LJW29uGM/TTygY +Ye8PrYJ2B+AQWgswBWFcBZLr+Z7QTcg3zYWCkjQZnTmO0nsma1AuxDY4wNdELaVTpOAHl7PkE8D Y7b3P8bE8rNJR281KgyXGdGchLNpWH/5yHnLPBJ4KX68Oyy4QSAtHgs63MUPCVqV6GPTmY06kz0h qfVL0PIfHtgiuFxKT5Zv+n1xw4+/lR4zWdgbxgQKvbP9C+mfNhPadWUL+V+2YogU2UKZ1iJHXvk0 HyZQS9F3X36V785Z5GVJfZnA7epqpCvWZEn69kQDzZa0jmGvDeiU8nAfGShT8nHchn65EtGARq8e LYFSQIoWPmQg9HDwEq7HV6d5NJUAMG7n+tBPd7+Vw8smLVZIfSKfu8XtKfjHiPIr9HwbfqOY/mCx brbzQCDadnwkS6AAkKj2/PnHCkurNust7ozKjfmQAdMKse+a+cmCvL3KzGexdfVhomK2fRMh08+D SW0FCOx13HTm7u6msAdANOLuVipdXu083MvbALQshIx+6dZhaSBc0bjaeJ32abuOnsXPuFSQlCBM J1sFAkOXrCdQVRCecnP+BcbJxi20d0pmvIG7i6RANDYMChjZd0Lq849k4DeiZ9fGDXyQDHL4rpzJ kVEX4Sm6VFvmGjstG4t1e9XnJYgEYpjyEuPhlFFCmrqQprqqz0dJb2JsZxFs2hEvtU6s1fN/n2+h WjYsKleCVxvLFc//fyDtLAVZ1xbVjFotl98ug1NWqu8FnEIRt9TSEmL9ts9ePcM85i5DLw7IVd8h teuLzmsONjG4n893YqbG5JH0GQBVqmD7f+XAceeHSpK0Ap+mPnqHruHw4LRs1bawXpS3ce7mkez7 AaZ3KZa6tESNLnW98WpWXylxUrUiR6Qrr/lUOCnwOS8c3PDERTg3gI3jUqYBOW1ffdlVMbawrCgJ V+78xNII0/OaJ75X2qbk3alHLab3fx8NZZLn8S/FzdfaLDn0BlPEw1zOlwP1JF2yY0Y+Hqh0HBMd Crw9TbcqoSc0hoqv02j3OxDONue4vXUVstdGgPUij6eXBD7yifLi2JwgNzfEr5FYXKchf/8QHF8x jvkufBQLWMYC4K2NVRliTXZtuy312xO/Z4VgtWXe4ogcHCodUHhf9uZXm6OB+ctlOuzIclwTsg3g buhRTcUDFlBr4IFP0HqBV9MHgI/1vFnY5uAATPcvy1cYpGL4eJKGwpNX6t888/LdZcdXML8S7Gfi P5w97NgjYeojksDsR3Egce+pjx3umv7XyY/FzMU9PUfwDinYT8Z9CVEPvfZ1TvyO3I9li0FjCrJL W9JnPGUPpkx8sFrd74uRKLzm6wAtc3bW4sIbvFdADUT5BGJGbB7FwYmYVwDRQEw5fsdF8YUo55Tm stMpBGEjDvXYci3bS+zLIg7irgCMj4GtLEf8H9BYxNIztYaiESEMIMseXXA59S5S/z8sSvpqEKut /hp1YDNDbIF8UykKTXZAtAC8Qwv2xpTSu4LUuShbM9Uw+/TP1Z/DnFzjmpHPvIyV/Dzi9AoWXYBT Wx66tGIBH3yWYB0a/PJPjRvN3Hpx4E4L5ZiBxeTCwuYgNbVOlhwDNbQji8kPvENo3D3X7ICVg1NU +Isgr358Kz5hl6RvMtnKyqtuq2oQyDItESQuEY21vQbqMq66NkasgssowaNGseWqx25Gv2dmYkxk z7x0oCl2F9ehATJYGr2lpGE68e1pIthDSCm+0mHUOHtJzgK6TVvHQmyM33zHpE8aj7lVijOb10eW vsar+sYcf9XGtrQmZv56oxJKAieRksMFQCkie3/TYts3yMpw4sTWRqOOJSMdSF4FqdCFXLwuMifW 6GuCCmHSRxg2Rb0IFL0HcBP5yTdBnhVIeUk02JANWiNKdsMNVxz63xQKf6RtTWOVnUi+mvkbLNk5 PpdL1MXJ+dLdzf149EYhu7xHeVFARTht0dx+yltmfxPZgnpCqdGFM4HK40jToVcgC8arIOr09/uM 3lmpeZ/Co7j14B7wxJpOraPH+Q1ENBaVj12xiT8z8nqcaj6b8RoHN+OvPQBJRL6db/LaB0mKteEd SFED0yuOGpFrBKRIhn1/oFWEBx8q4Ne0xTZye0yR2N+x8/yId6kE8oKIKNF0uTVc99B0ufLe0pO9 bQB2QQsUk30ithkZ5RrggTof9c1MizwGI4XcyUzuMInmN1z+KzmY64CdFB4LHsuFzKAlGX0BoBOs /1GJlIjMN90nhmcFvZAkoYQFpMGbekQEjrb+7J0pfuAbMQKTPnXqvBZIiKh7q2i2E5Bfb/bawY9s sf7CxADfo1bWvVb5u8FnK5X8LE/j5GtHWDS585zhJzc9HByVrfiaHJ+dUijKNEhhxr0bxhBGXY6G TVSVU39kcaVAC8lyAsNfodBEaEoeIjF9gI5F5PLDsE1aqLtGK5Sf7Pq7V6cCVtvtq2EZeuzfrqrQ qXG6f+Lzx+P/O3tlOdoMG6H6fb4/rLldQ+2veY/JXdDnnOjl0FRj6cyHcmxG1LIybfjTmqQKteHj qlybLg56Qo606o424pqLkP1O4w7sqNW5qkZQwvHGtVNfy7TZ6WWE2bVLlXurzLeZ0Kso83WRDg5L NiMNgdcAZQ2+Our8zlBP2TzSr6TFlT2GqK+VOL4873dN3bEPkPxW8/jz21WkTAbdgu0EB9F2UKH6 ho2Ok4g82KGzzzWjwVtzHRiLQzSnnuFTzwJKZuqCtORboL1Q0Ge09M8BLz0lhHnCre+MTtBnW+PN qao5aA7OmACCKC6kK8yUQyEE5n4bus2tG+oStfzoHD38QrUovjYeulZ20dcpYERGf06vFEpL0UIi Gc+mUMvKRxnv3iw5GG0HYXfL0F3UwB7+/RV4QxHIrpYvzNU5+bF25lt/2jSUQray8ULcBgEjtbpB leP+ojiiGBae0hqBnuGKjxyyQ+mVnJrmgX1KOhTR+GgIqpkBqWL6OBm6dcU+UeN6pnns8WFiFVCW d/YXRRk/Gl22nk1BzU7DoukfNHwlsgQ1WsrqjC/D0IEHcTj8ECF4b3TRHQ6jHPaQQVwKayqGbmus qpe2MgIHsWh3Xws1YxYu8t0rxxjF68OJK9j4C7Gc0HJnNttj7BcpreX0rJ6+dlQRQu0OY38NHQct fS3JOVXP0w988s7219kJRT3kuFr4E6InBqqecJIFv+4Q0oRRWv2+Ab2S7xYET3Aht8kp+VCvytAh FEkxvz/WmRasEJjlygN0oFuHgGKyUJSaPm11dWXrt0TFetFlAfqfZklw4DQGz7cEi3vpyd9ISInz qODK5ijdfMPC2f9kSBuqDx8Rb9Y79OA4eO3Il5pWjZr7yD2JXyfP21V6Yv3qwkTee9BQLH4Q8CQF Lnj/T/KTD9eqpzY1lVOTaatTAIOOnipyR78Q+G9ZL5/8lSqb7OTZZTUvpL9LIh2MqotFPiTvKMZ2 cjurfchA8KWe39FYGWCx4CuI79B0eoAWMOEJ2dtvq3OQgsn29s622MwLqjBxLmH6KZsxeHG1pSq9 4iUpdJthpNyZVjfVnahY2EmeU+Fx5U6WZ0K0gsoa6EWFCb2UmypzIOMzqQmLRb4LIRcJBMWKsT11 IyGJDcdrEqOrQPE+YZs5T/8qXAfl1He9PkzRv7mN5TmlUk1GVYYS9pIhtDzCgxHGW+Wh+2tz++wT ujGOAEvqaSjhoUMJWVHr0nC2qszH2ofqt4fKEjvrQgQq3cjFyKRpPH2JKxIDxg6BxF3u4Y2n+U73 8M5pHw8eWvwNR0YQl/4FNAzL/wuyf8tewe+mJjteWsGWBHIMRDYgHTSQ4SPB8wU50msPmKPn7vdd 05Fs8ewcWkQyeEWJHwdtn3hCrxx6+7r1KiFy7fcfGS+qu5933KRvINcN0rxGuAiT8zHB2njW3Nzl Z1kpXGdlwcuZMr2XLYmKuxBGVDy0vuXVIlAbCOigBwKyYMUXuWk7nttNrf7n+bpPVl5D1vGk8aeW 1sr/EYAwGOTzanlQ2cIqJHDCR7ojkvytUnhkhfl4crIXsMCt29Uk6WfoPf6hnNzQVIBfPoBXX1EW D4s90htLJOaG5PaB4eX6kYS3Gw1rgeQl1fg8qyQCDpl3aKuW3xsSXoH5xhG7p8BJ74t7QrRgcfc5 bLtKQSvOJ21uDUg80Lsu9GS7filZSrdYgER5/9/rQy1LmvyeNJtCRi0xW0DF21vkCW1HYin6QMbL 3tadgM3icSnbVAkOKqy2gJmS3SGEtogQHUqnKpfipO5FhgB9QYWNGzjVw5tswOarP9gta9P9X1Yz jagAo5MPFjqvzsOse2wrGhYUuzkN7PTXXFytBHLEtWoQ0AEmSEIQmo15xavJlZ/mbbWS3Y3ewCMh p+Y6pflBRM4VIwI2rhhqJZsnvBTO25PBzQHHpgDYlTi/OLVoerdxR8lDFjtYZAHZsxCMc0mksbIQ 9lLJqgMjnA2NeAQqw8uH5oZc0GCXqVPv/ywpeYGDaiNw6+u6sh1A/cOpuNFS1ZNH/SiFkRD7BmZ1 14CZV5FmqDgWn5GWibTecqhtDpAegboO2gLXu49OPw5MjHX4qsHIe0/wqz0J9m9KZmxiDaT0B/Mi b6C2hk1X4jVuOoTSsVSJRDjSu+fqOm33VRKXPsjK4S0RC+C+mGjnBlJKU7RvNeeo7eNPurG1rSwQ 9fBnGkhxGpMdQbNKENfci+Tsj5yuFT7rhzCYVoRVDcSaY7GSCs+U0akVk4CckpLrZKjqFQ6y1YSk kuuF0uBzoCn4CGI+DPcbLA2TgcA44GZ6HdCsYGSSn67uE9jUAtqi+l8ofQZl0TH72IeoXIaEsRBl 7Lg0x4Ljco8E1mrSZAvRNYGld5im383IAErr9nxu7/z0nw71yliyxnWGe5J2k2pFUCuQIkuvykCP EGzwpzUtm68gIXeQr0ZbjnYSxwzhy3ajdpylJRLx1dBRqwqSBJjZzhNUhoYem1nCRadDUuD02WbE 2BP07t1SX5/Pi/ymXvAt4nc9nc1fXhKzEZP0z3EExJ45KWD5aF5nNtWJQwAb/HvBO15l8bcX7ZTq hm85OQrghaDOMG7NoN4WZItK8vEwXHticOXW+Cjb1KB+946pnArzh5VXTlQdIVBCjUYIH63D5f9A QU2RK0Pfm895tE1HDf4sDIRR1KlPnaCvucZSyXi8/5uWY5/NLM0sYWNuJZzo5GDAwZxYmXSnFIcG xksI4j8DDQEHKPBUBCKZZG2DGlBW3/AMjQuNTB2UKKJluxYR7POKCs7UoRBUEHTqYNwp6lIpZxZh rVEAAc11BktzVmSPhgkG+8vpeklhXtNboX32S26T9XvT59Ur0ROQeOKKE4JFLelv+VDISKrYZ9wY 0Yw97m5/LFJ83vxjTHSLQhV8i/Ohfbs2NHX7ju6dIO+d2O970Le0oukvsFbJ+i8xdNPWqrFw8rvH XHGrdFRGj0PdvQHED1RWYqCqz5nLADLV84zmG/TG0vkxw4/XfEln7MYqtO5Rv3i5hsEn6oMrDcuG HqkzZi9LyWH4ZL7ZcAAq/RGDieR671U019Y9LAlDYqm5EYPpBGgB0XVjSk7He3zg2opgvlzevK8s DVz52Qd6Hm4Ja6scKTAHCLT4odZuR6Bq18cM3NI2TbY7BIyLouEmhyTodqoXjL9ZPUSlSx5+fLF8 rR1tVwZxctFlHpyCPRUejlh48f1kECQqwdKUfZSFCJmA1Pb4QgvJoGoRVgJMI7LXqMIY/UBgn4iW U0xY8tR530WUPmeAe3kCn1hF39c5mEJn3a/zp8vOzDjLpd7Z7AcA1fKd9HyZfFQifBg+b70VRsIL EN3oeQpK2ptAa/XjtRFk4cjyjx3eROm86hOacOhKlxRB3zmuVBeUKM8oIY72rYuX4uXv0rm+4ImL M/Lj7WG8bN6eC6yLBZ+wwx+fyUPnnZrkCWzBBuyAyrh4f11+Gx0GlIhGSmZgtRrT0puw3LQTG020 gsyAZG/nuckkHMU3F5e27d5CY3Bn+O8g+JBDRM26h7d/ieK3DNqWhAWfUJBuKpVx0FWWPj9iiJoH 7vQRKw0hRKkcBFhLM4+2P57cLY0uKBKrknPAn91uCkyt9mOhTYEgKtaXCnQBIOLeSQU4vrFBt/66 vz0ptz2uzkDt61kdJ908I/zquEEUd3FqmazkI000RxR/0dhNV0hn866FoAkupFfRpbf1C4u9yNN8 mwdRLzQrAeN2E/CITSSUS5nnqzSvds4QpWaELkK60GAw6ro4+27494KZMgeyvh5k+ncWORHyxuO4 2pyK53uVVryajnswBiyM1gvCMWAxBHS1REb1b2tWVJ1HvoH4Ebm95BxTDu/4iNfAaRgVdRy4BHrm Vs4PWxOBYk4GEXAWBcytn8xpFLhNzZROYGX/Oix66p1WrsTAArsMkM1XhNgtdfOsRsENYvE7wJJj gDt85QF6vNNSo+7tSeX4Q4GWoQseUVhqslWwPTI6VyMyo/95WNILLlAHh28S1hfb+BPpE7fNZEB9 ET+wxs4Bhmwxn+t0prgTXLYeArsv/B/rR7Fk/aQYIO1DYdXKasTPl2p9q8/boTPl1XInX5zO+Kut haqGPGORsUePxrL/8RNvvzLLEjRfy80P0CcQXC0c4JpCMVekHPoJmlelNFg64l/qgz/sKqG6ZX9V FW9ohTCmInC6ajedK38RPpE6rBWvOXfknwiv3wkKnRd911y7jbG/wD/Sf/29grp51a9s0q6sWIAK bP5DJYn+Y4paQ2Fv5ND3y4GWoITJhlA9QHHUg6cV+Ox9+uPtuoKgmp4tOmYvFgbPk0fUSrYr6xjr Sy3ahRYI9HZxWarDRgGVP6KQN4/0NjKVAs5XPsA6ukx1LjuukFxCT0zboatK2olo9m2tJKe4WYvA KYhhNQmbg+qP5GLqgf2EWjqDgzIdBZcsIkW52xcFqsn+9TeLLykI8xtwdYNvU+zbqeE9BZimfiH5 I4R8dLFuOyzjofih6LGkHYBsWYmGZxvUBAf/R5LBuW3RGF+uFbtVxcLdDsi4M2iSDLxJtZyZcb5k aN8hSmrKf5kIcxvdqbjvkXYIY6t0K1XN256aaxL+cYOJyAYV6xchjukzAAxsP9A6CjwMgajdZjjn ozuAfXgx88vVLWbz+JwXdMjMe/xrMTldhD2X2jmorhbuGRhqUqIxmo0Gc83QNu1KlEjjhPauEyjb L/kpT+kHOk6jeJdYlzvfYiv3HsMBrdTzc30n9Opl1Xy9VQ/BRCwQYV01aKpfIN1eWVH2xMyXs1Ak +cWKObRSgu/4bUQFhOBDklYTmaJ3EAGe3s3J5uBAoDdIalQ9knomzGCx5rXQHDhaj7od3bt0NVxr 3UoahaxFAl6rXh86pEpjb8j5gCpZh9cUgFsw6/ebGAbXXLtNlpNTw5RNTbQC2V4wHdGqgBFDccbE 6KADFSA+lo++NThaDm35kE2RpHMocLfyFavVIDGr3tSgrNmXBMrLNo6FIzRUEPZqoOMGMFA7bslF xF2CseW4c4UKc4LBMXmPX52oSKyDzhAa2LPDqyiSGamKDMjqdhrN2nPARfZMW54WDDvLqLMfDZMT jSQgfoY84c6gqDyOqkBpj4Hg0ugKddu/EWVG7qbPe/JiVZrbWizsn6aQV7QLtnLgd6IWHntwSmYg +o1NQM+2xgStTKfwf7oG1vslB+5yUbyIyr+poRBl89qt0UGD/fNJ4ogBpy+tfFExu+DWNkuTLeXh do0XZT/4DHecQVELAxoIlfyxSM/U6ednAxZLIodrqPtfkE0nARL3YG/DeHQWgfMCdx4c7a4Ro7IP OS6zxgHXUw1ikxkWFxTQADmGJlfeL6c1KwHxIsBELpquB+gbOd2LkG8rNMLWwp/ud+mERr/q3u1p ZlFXw8Av5/RTCA4PO+pPgRSB+HWaKjrpRAMelF/jJaoDK9vaNGHLS+lpSylF77m2zdn774WhbtMI d2UIMftQA4SjZqy3o0ZsLn/M7oulWV2jIWi9Hf1UO3rCW6zUrRqKZ78XTxqc4U/M6/T8RTKA0sNn QRN5//SOmSK8JaQoUcco8qEgSjtc1f9kXaY8pB25ruvCMkclS4riNzhmV4kxBFxfWOOiceCbDD9R uVLW7A+ctXsye2sTo/vbnFt8a75Mi+jABZ+tKSfUIXYOqgl94kG8LELfc0/33s3IAGC+WDEOTZEu BY8ES/uMw2xfPzuUgZZm8lTmeKG2vLjYFS4TH1PZrhXCVtPkaqtP09AXEygL/1Z2IoMqtyhYEz49 nMJR32LLVO0kDY+DpBcIij6eu1lXXHiLbJziRR/P1GtXlWLOngXNyf42puvsHUtixHUYnomC6cZY geHp1p5GtIH03eJ2V1i+2TdEMS7DZbqBgyTKLivZR6YzKw1D9tSaPGfD1p9ZHlTWVfKfGhtdhOIs oT7aSwb+X/JiPSLd5WfyBZtl0wwPosLHXKM4ZEbH14DZiEkyQFCi4xPtXJGP3Dl8YSyLPP5OTUvS VfJDjJ1HsSBu2zSAEJ/BvIXkQyTAVe3EexZK0c0Cpafdm8wscGfYSInYtLG2G9qxGkYE1q+UtDMW FGX88NCQmpDL6Zo9gEcDRxs8S8iH5DNRIaUyYtSaJBSH39iTg9sgTJk8+tw671KpQMvVoSEomXpq Fous4j2mXUqbCdVUJ9rgCcbuWEDiEUn7h9wx6twk1mGBGACDzzcu4+iElVu1RIM+iYF8Pivmrpa+ TtWZfUmkxdO+RBGtp+GuCw/mAgldF1H+S5oy1yL6UPKU5GVJ1SCRTA2K8xDdEmuNUuBe4pjQFoeL n/8ijWM5cbVDi14Y3IvjlbdvHDvankqmQueZFAj+ReY4Ah2I4B8IhJKug3v2FL5uopj3bqiixIVU zNVQvgdhoPtlRHV9Ra0R9M9fEYkcaURz6gob05Rr4U0Zg+TuAMkIfuWZrWkuUzGHrlelQur4S7ip DOg7nuX3siJISnSGFpeZiM/Akg9PORsdJRRxy1DXKjJmJZSYHjNF2T2N137IOZXANop2MsFNjd9D dUWHsNEeHzy26PpPhATroWOM+lbCBgfwW5gecuA2CreYKbvDcRgnHIrqWotLVG7aM9ijer8jcCmR PMCTZgiYMY9SNOlxGwMn3gZLP6i6zrUR64pyHpXVd48Ue2VkOSIOwfwlee0OcoSG40oJTckghfnS wzTw2gAF5asCslB89ThYjaXu1iRhsC5TOPiShj8mufOfVGoaqUGMbZfypIcJZnax9b9RIv+ah7En crA8S1WF7ghSOdD9bu0zj/2lFLgjAxuy6PNnXpOKtnJp71xvctOJ616BithmLSwfhlObXEmhIZEW RvNh8LTWbTS2RMq/baIHsN/KYDofBQME08whERV5eYblsFTh9dVEamgGeq4I9hbE6Vr82lZsyBRZ e65GZHd7tqbiDmVWQSH11OPSZCy0ZfspbpoWmeZOBYyhdUS1a6zVKJ5XYWzYuyXs2rYY5etWdl82 WvDePCPGT/duwVkadI9gLNSEB/za6lkosdnRmEWlE07e3frUtjlgbvDSGSzc0YUENUX8X79igahG hM6qNU+qCcPBCL0kuIGdLNcNz/MGDHm19DN14w0PeDQGAd1CwWzRGy+Kkjjdcvc9FidcNN1ixSk5 dk0aWt2m0nSqLRF4lf0O06lOEXeOTK8VtgZZhpy17/PYRwKWON/1jJ+Ij/zNSM+SrWl5KCOe8cYy tPY/LW1QN4S5KlUwkvIAs++zDnFv3kV1dxAj4WQtXM8dOBNMqbl6EgLXLbC02DgtnfLEM/88iZGy gSzgBQAq52KQp0TlSygnUZoa3fji+Wkyp8rThLQDi2aWUnNhfgVS/KyAwMsuqUZPeuKOoPB0xB+u +tvSNXllxXXaKYeljEgYRSFYTfPE07VMBey/sIquaXiC4zOF5Vtq86u7b6jClq57pK3pu7PfFKhO rRO1/+eXTWb8ESja5rd7KTIbKSsxkdYobtUJ6Yz8AGoAR2UfVDKEn/9/8msUMiJlq+YW0WvwRoEL 2Z+q9CZyNNCthkws6nQcf5+h+5V+sBeANFokOSceIfFkKu7a6w3uWpJ7xeRlGpsURuujx58u+Qyh DwBmV6dlfFg787Ox2uzQcGD9g3uheHyKLKs93DyAVuNgu0pE28USgzM9vFtv1ZNDq8Sy1VutaEr7 1sfvsb/Ib5foDpTzl42eVy/dgI51mDTxQ4xSNWWs21RBLqtJJj8XaGAVs8c5oDMiJ5vQ0fsYL2AU L4BLqnBZkMmCp0PKzNEk76z8SKm47vedIy6gQuwiKzzyAwYCfXw7nK6dhwprdqeF76k95oYQYpvF zsOizBF2K39bqODwIkBpeh18JHE3gjo1h2NPY29K4VZ0fXZAylFUbc8zd5jRtycvACkESYEQs9xT nzzrxLjsMTCur4B6STkjJxP3hFpG/2BtoPVicM2re44QiMbCPHGQS4idu8Ml/5fcWBHxkOrkG4L9 PadHTCxVaEa4X+qhz6yW5On5BmnYA6UsC4OgZjrr+Mg06hev14i25vbVBUB6ZDfNppf2SwijLy8/ TxHe7BgR6nYFN53qPeOWOiYh10khXYKncGt7vtAN+nCSQSoaB/raYdpN7LyIgQINsBteRKm6A40w DGZXH9QcCq2Gu5ulMFUnnQhDGkr+eW5dHk0khQ3AYFKSlsRMoeiD+26N0o7OqSVPmCZ8+zf6lkOS PQYV7pCNFz7hT8e9qIxtdaCJ+KO8RvikRHBaxtltKW7gnPPr2cZhlxC/7S4CLDywTl8uiaoNbutR kDfwC3uPnxohuTU/NnfLXh0Gjnx3eVf3Zbn7vy8hkCAXjC/YWJGDD0p9Ed6I8fwgH9mORdkruA2r 39BH6A5SVZ0nE+OQUsN3vK65dZ+B9rPipjHynS/V3pvsKeUp7JUwB0SHMQzK3YSu8+8YbfCvPfGC PV9i6u2cej2iT+IRZd+4tuJlAvK84tyKs7C7XwQCYGv8+XrZTkx62+zacpImzVIn89seYS41YjQv u8ZP6afy1wM7LAkrziperiv0nnSnqoEhYts2dvAlx0/b4UrzOGQeYKGHInxacCnbPBzQGVQ7YE68 pl85kEyYG5J3EzTOxVqzpmZyszzVgJQFQ/H0e8fn2KPfBlfuVA1TX6xh6sBmzm2zig2thsaUj95X SPgSon5D+PmRTjME5Yqhf/lwc+kzxTchMA== `protect end_protected

gpl-2.0

b2794c33b602875b9d0be26ebc3defe3

amerryfellow/dlx

basics/inc.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity INCREMENTER is generic ( N : integer ); port ( A: in std_logic_vector (N-1 downto 0); Y: out std_logic_vector(N-1 downto 0) ); end INCREMENTER; architecture structural of INCREMENTER is component halfadder -- is an half adder. port ( A: in std_logic; B: in std_logic; S: out std_logic; C: out std_logic ); end component; signal cout,sum: std_logic_vector(N-1 downto 0); begin sum(0) <= not A(0); -- S = A(0) xor 1 = !A(0) cout(0) <= A(0); -- cout = A(0) and 1= A(0) PROPAGATION: for X in 1 to N-1 generate INIT_HA: halfadder port map (A(X),cout(X - 1),sum(X),cout(X)); end generate; Y <= sum; end structural;

gpl-3.0

5feb30548a4d5c86f29c8c8942e8f806

YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA

System Design Source FIle/ipshared/xilinx.com/HLS_accel_v1_0/dbdcd11c/hdl/ip/HLS_accel_ap_fpext_0_no_dsp_32.vhd

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.0 -- IP Revision: 7 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_0; USE floating_point_v7_0.floating_point_v7_0; ENTITY HLS_accel_ap_fpext_0_no_dsp_32 IS PORT ( s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ); END HLS_accel_ap_fpext_0_no_dsp_32; ARCHITECTURE HLS_accel_ap_fpext_0_no_dsp_32_arch OF HLS_accel_ap_fpext_0_no_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_fpext_0_no_dsp_32_arch : ARCHITECTURE IS "HLS_accel_ap_fpext_0_no_dsp_32,floating_point_v7_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "HLS_accel_ap_fpext_0_no_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_0 GENERIC MAP ( C_XDEVICEFAMILY => "virtex7", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 1, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 64, C_RESULT_FRACTION_WIDTH => 53, C_COMPARE_OPERATION => 8, C_LATENCY => 0, C_OPTIMIZATION => 1, C_MULT_USAGE => 0, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 0, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 64, C_RESULT_TUSER_WIDTH => 1 ) PORT MAP ( aclk => '0', aclken => '1', aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => '0', s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END HLS_accel_ap_fpext_0_no_dsp_32_arch;

mit

6810724035b500fdbc07b7394eadd5d6

skordal/potato

src/pp_utilities.vhd

-- The Potato Processor - A simple processor for FPGAs -- (c) Kristian Klomsten Skordal 2014 <[email protected]> -- Report bugs and issues on <https://github.com/skordal/potato/issues> library ieee; use ieee.std_logic_1164.all; use work.pp_types.all; use work.pp_constants.all; package pp_utilities is --! Converts a boolean to an std_logic. function to_std_logic(input : in boolean) return std_logic; -- Checks if a number is 2^n: function is_pow2(input : in natural) return boolean; --! Calculates log2 with integers. function log2(input : in natural) return natural; -- Gets the value of the sel signals to the wishbone interconnect for the specified -- operand size and address. function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector) return std_logic_vector; end package pp_utilities; package body pp_utilities is function to_std_logic(input : in boolean) return std_logic is begin if input then return '1'; else return '0'; end if; end function to_std_logic; function is_pow2(input : in natural) return boolean is variable c : natural := 1; begin for i in 0 to 31 loop if input = c then return true; end if; c := c * 2; end loop; return false; end function is_pow2; function log2(input : in natural) return natural is variable retval : natural := 0; variable temp : natural := input; begin while temp > 1 loop retval := retval + 1; temp := temp / 2; end loop; return retval; end function log2; function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector) return std_logic_vector is begin case size is when b"01" => case address(1 downto 0) is when b"00" => return b"0001"; when b"01" => return b"0010"; when b"10" => return b"0100"; when b"11" => return b"1000"; when others => return b"0001"; end case; when b"10" => if address(1) = '0' then return b"0011"; else return b"1100"; end if; when others => return b"1111"; end case; end function wb_get_data_sel; end package body pp_utilities;

bsd-3-clause

1910d41c8ea8a96dcdb27145c41dafc0

FlatTargetInk/UMD_RISC-16G5

ProjectLab2/ProgramCounter/ProgramCounter/ipcore_dir/Instr_Mem/simulation/Instr_Mem_synth.vhd

-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: Instr_Mem_synth.vhd -- -- Description: -- Synthesizable Testbench -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; --LIBRARY unisim; --USE unisim.vcomponents.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY Instr_Mem_synth IS PORT( CLK_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE Instr_Mem_synth_ARCH OF Instr_Mem_synth IS COMPONENT Instr_Mem_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN -- clk_buf: bufg -- PORT map( -- i => CLK_IN, -- o => clk_in_i -- ); clk_in_i <= CLK_IN; CLKA <= clk_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 16, READ_WIDTH => 16 ) PORT MAP ( CLK => CLKA, RST => RSTA, EN => CHECKER_EN_R, DATA_IN => DOUTA, STATUS => ISSUE_FLAG(0) ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RSTA='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLK => clk_in_i, RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: Instr_Mem_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, DOUTA => DOUTA, CLKA => CLKA ); END ARCHITECTURE;

gpl-3.0

694a9c7d20f35d80bf5db4b8df860872

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/quarter_sin_tw_table.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block m3yoXg69oEKAI0iRZ8oeGEK9l1g5vj1DwNLzZzbUGdsMRe3MWag5v/leu1FwYdY/Oh8bFpiDMloJ csIBVwuNdg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block DhnFsRZMfFnQHH3SAhfeZ7IURTiRAut6sZT/tIaWKrAuyPDeeEqoZB8BCc6IzFJ9f+MkSsloH7vu d5oHBaQ/TSNNkrT7F6d8zPoBSRuOTuQckL6j/saWfKNkRkfACOhmJFF4ZrvCLJSr2lTwD3SmtMqW VE4iBl4BAE/0dypZ4FA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 1wMEtZh+IAZYjg0r/5AhcCJJm98KwqUtLX2ilLpQ8TQ8HlPC6VbWfD44Zli41PoU4HkRFz9VHO01 phFwwwNyy4rmT+Gv20sDmJU7JJqYJQR9fvyWsxD7i4BBQrGwvnMOK5l+aJ9jQ7vta3YOOa8wfBjq aiJ902b3GV1L6B9JITFFHmEnf0ELF2jrJaZbDi/1RbW3jHQQzKS/gSVNrIWQWTWjCWaGR+Azibqh m7jg4QtY5XGieqKxBRdXPaRANkkeqNZcvn3Eq98EiQbeIQlvJFOFT5OA+zKjfB4a4Gn1F05qhnol WCtklh7m9nFXj+J8+jjBErmD3/FL7ASHRDnfFg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block qzhU5Qu58P7bgX4p4mjygU9RGwR5PlyBcxPlHZpQxsn/HnJULhfvMGSLb6fMwgcwFf2jvUJFcsrp v3FDspDYkeBZKBJmYxGxdBJyQPuBnKZiBPn/aK2R+Zj11X6XoPrfpzBoaSoox3jA0lBEfGPDz/MA ggEghDMBUn9NLAUuL80= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block RiDgRzyP5zz7TXnkugBc7q7A/lvDSPSW4rhm7DvPFSXzKwHoJDv/tj61jhvZmdKoExjQlruwygJT VAag70vymXbl2BmO2FUjQlJvnusCv04pnYeo5EuYA5BwTQgcoiKFk2VyBTIO9wzTGQ2RUH/BGGay Dx6t8Exj4RsJT5YpHyx1xCA6MS2knvPUK2PbWsJJbbKE3lRvm8iFu5wPePGoiOr8VlCeDMrDNruS 2GaqqTLvnLoaUZ5jFdnBDrczWN2Z5bZW9vKQ5GsMv+sOYB4i+9Cp8/8sVtXzil+DRW+Ycg5W6s1m xjhAhkheH56mtk6gcPObFOouax/dJref7I+f4w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 297568) `protect data_block eQZSyKXStIkUkFpxUX8HU7yX33IvShulV7D9HlNqgHOXf3TwUcXW1tZs5vkVRb8ppZqvyM5fZdFB WEvhl5BC0Wp+sVofafI8HfqIXsFexxChuKJoXSoM52sxWdAtTi8R/IFqmSCgl6NN7UBBbgAsyDgz SbUCdNozlmYqeGTU5U678Po1xUuyA8GSFew2QdkNqKnj3wE2BFT2dY4op0MJRii7OQrcVDfhBsXI ZE1rv1IyIdXinKGRwJp8dX3fUx3tTswEfTsmbGumxpp9ItVAOn4+fwPnWyZIu2/pTSqJ5vD5kkXu pY+2uEstDE4yV8I9w86KPwnqnLKcdPDk8oEiShY0cwoa3+LzNqkEtzgQ+PkkcCTVeamKn0VDfd0J m+y1KfyjzYcMhc0DMocJYcOrD3A69WyIWFvceuD+ORiCQdNLwdBgzQ0v4iK+7UusrY/q6YuupBZF Fwx4YPxyHesJJdwLWGOZNe14LnwP5egs3Tl9x035CRGQUy2Wq4jwVn9awIcZeKmaRNlnmU1or49O A9tPs/Rs7+uR6zpkkjc48+aPOU/qlVXL/FE+bF7aKdwjT0z0/sLrKq1u4mUqni0aiqXRDlwK1c1i 0vn8bedKDY5ZOrx5znYfa6e4kV4NwOhFqJ9NnQOjf9TryJyOV71PMwYA7eAxHgwDqbWb0ZXvCQPD MYN7KmBOygMxnVAUcq6+QfW8xxKrDRgi9ckGKvuoC6wfFuey6spYXAqYRQkq03tloEH+uCUaxgLe xsJMkwVHmttqnskYOEgWKiGa3JCEa2cEu2pd/hwmEgGfk71qYAXm1qqnnJOos1SWh3EhmMgFD5uI LDn+jHXDsJFFYeDr8mDt+44Rc9Pkt0anG4uTiCSGKpB4k3R4Ecbl2lAPKVRxHGezZReryrCD5Y1N i0DIr6QTKM4m2Y1qpIwrW5YmF9L+xaGMVVcDJePiqx7xAdFJAjn0xgnAwgynNn1gOYmOY3uIvHzz Zurw5T4yWzBGxEpSBFNA4uyMv3U7U8mIrYAJH8RCV4MBrYRBrJmtd8ThNywGtrpRa5E2OQ2Ry+BI 5jIew5T52k3IOnhUsgPiTFSCa2qayvH8sQbtu3bxiYbgQLqubOe8HH80WufxHul/rO4eLye7JAaz TUZpEcg2Bz4qTOmxOSGH4vBqKqDZuXY7nz1ib0zEWAKylCyCmAtE/jNWZO0a5jCvSIm+7+2NKusx oTjHcP69w4ZRWtWITCPEWGPgzPPhcFNkW09VuyLnxAqVoBNBlKXYE6jKXyX59xcyiY7xC7sC6eN1 jnEcy0gxcxYajs3J/hPNf/tflnbWH6GMQ3Z0OjI/0KZvEeDvJDfggMolabDIzOkLw3GZPE/PgjvP g7F8iTmkHkdcUj6O+nSWE5p7W8Xb0v3cLid7ovoXWuoGu59GSyiTIXpcOTHOTpu/c88uHDQ5Lv0O yE22d3o32JtP0zdt85td3YFqme95VOg1psAhK8cj8RxVp0LBjobI+Y0/jEm1MtIY7pMWYbqo/XR4 DEpzDwpGME+3DHpIl+SWy4xxWyX1V2keqGA/gMNHbR7sA8uMyLAp3Z6KSecsfZI22qUSn88STVjh W7X7o22JZu+AhWjv8HG6uYrsNWCa//1HQq1uBziNNPnej0QPcgirVrQD6Z07FUnHjMs7DgEmInvl bW1Cvi37mujpbgyfL+t+h/YuB2+U9yl+9/ipMl3O4620J5dYqYTy6JTAdef347V6Ku2LGDl40cov SR+wZ9GrDy2KAR3ySbjrI+4JHu9fhoxBxWqgpa7jIbZ0wghisnk0fMOm+i+b/4qCUsLk9T0GDHRB NH+CJ6K4xmGXZGUkdC4nsiibpo43bv15eanTH73GNycXRtMdv2kI/2xCSs1di7RNvbeqzQEfAn6s mELfAgouqmWid/p4XJcMFYJpXfqC5iRoqElFRmZP4u4hE3DOP7r4LcKuMYfZL3F5uwGK4jXOHDJc 1BIXAmQhHBJ/hWcVLxOpel70TbaO/ykKw6bW+RII7VsYGJy+wfLDNpJY0aSYwllzSjhSF7m8od4B ZC2kflI+eHGo+55Xw9y1xv9HSvqHIMTkFneVboq2k8bkd10KXe25z2mxSy3X9WB9U1yfSYTuq+Dp 5MAIRIkLZo4KvRluotGd4YJZdPjgsJtBDfxGUg//oU4KXWIuTJu/fe6lIyzizYwDRl5wfI6cC93w VUAHoCSYqfkoRBl0iPchenXkTLDvWdgri6Hl6z7DpE0EJwoXU/HsjABBEelBI/h+O5/iIjpcrvme P4MyGctYUMkCD6Lz1GH9edggd2RX2Its93Eadp3sEC2iIYQOHI/d4FZf8bnrV2zEQYrgXphnfkFG qd7EKO7+bsM2GlrhWfZrH6RGTG5OV8HylZDrxT4yQ6HTnhiQvSuDaCWZq8Euz3kOoF4QH1qPG+Q3 UAW5fRe9Z3t4acSlJAAdlhRbmfYRNdxmxQ1xt0RjN61KvA+uCjcaCpVNL1dZ7foyvkR7CLTQFhl/ 0rqT/ERNwOwBSIPwVbDQs+QC1rqNOpTf0jW9u0QRSk7vnCy9Io5JYFrc4sH2YgABmq0ikNWiC7Yy Qj5RD8EpR2VQMtah3JCZZ2ZO0Ceijrqui6sWf4o6Rgb2g3bpHHYNHoXyOV9mw3NkiVXgbY+v5CDO k2dCB7OF6XVEA5nSS9Cp4Lc/NsLPN9oyBT1+IUrC/z5/gMmZWbY6L06elGi4YfwR1gU0iDu2xrEM QM+uQGGjAXjrmaB+8jgw/Xkk8HUgKIQZbiV0b8ZfJfvzXmXFVw3jCe+RF309hmc/jZH+hgZv3fWO ieDIKMKgMw0F0wdKbuYixXgDm1iZ00dryY1wnSstKnbQFD6fKO60AdDJv0pUU+MwKOeTREvFwsDR PbW0GLXoOGfDetWi6FZLjIgR+od0t+/bSmhfLxvSTeR6X8q3QJJHyW2B4jhPSkKUTy/bcwofSkIL RIjksdmjAUEHNXDyrR92v9kHPXt7uOI7me8OE31au6N7wnbKedtI3qpWTRnKXg6uumFOEs2cochD tF4TxRPMzaplvDEWO3QqmvbxUC7Ee7uOLIX3NC81BUJJAx+E168co7PnCJrcqW5vJazsSOOcCxe5 9MPiNAB7x/x9swKsIvDGQvwJp7c87uVDj6ltEmRy6do3/MEKcju9t/kra6MEqy4Owd1+xNFeYiBi cRV1fHrYgbBkPKqHV8PQuMV7ogjO7p/xfxQQcslqsEKQnF4jEHH/fdtlmq4gKycB4QCTpv/HiFHW Cdk19Sw1HBA1xBOM4fGHGkbVI4HHMW7Ytzxyj4SCAQQT01zO9Y3WW6bv+tDVj9KoSH2rTuFVeP0D fANVIkV2rX0PiqcoSdBMx58gVg86Ok8taqzUbkz/4stYbO6oBpBnq6LjDUl5hrneeVX95xNCZm8T dUYMDIDzrKkEG9cdXDNuRlcBuZXNZ8gd4kIZidyCYMXcacHS12l/2ZiCCNAtA8ABY3ahU87H14qJ +XxWXbHJk0z6Grn6m3oOwXrEQLNm4PY285ePT8pmT8pD3pAK0SSBhRYZuEPtjQWxGz+M4507I+iP a9Frj7qQ6LBubOZD4rBcZi5WmSiou38N5W6gUHVg9ChTieNo9zXPm1mYrTmFeVn8R9y+px9SM3ZA CCAwoyst5W0f3ii599FizC/JB/WzlZLqqcx5UUz+TDeCFFtWt0g3CUhZeT4k2WKmolPNCQXgEux9 FNKoSfS+svjnGXud+I4JLY9hz6aWKysZ1y4IN+cGf0T5VcpRA7XylVwtGkeK2LUSy28VoHyD71dP L30QH8l5D1zQsq83Gh5NrVeL8r3GO9jUnC6zFPKXjZsJxDswLBjtvjPAsDnwo/dy956abj0MAFFB M3XMuImIfZygFcrFeSB/FS9zcIL2MgJMAcEg373FpI+chNI/GTOdt4ccQmLw7fSkTG5jwGmiIz2z F14lIIzxHTVXhtCWW4OmjVeyuaoA68GDItjQt9WbVep5Yp9RS4ygJdKcjRI2ow1qh5mRR08rRkGX O+gFL3x0mw8niEIJUiQzb23IEj+bGmbOzR9vShts40PmBf2gkWMY0r3iCuZ6+sJf/4dPyb9gIQbz 9IS9BGrXYj6Tvkh6JZR79vJ65NNiM77ipGSbdx9ptnUxe+PrujrcKWryCcUdjw6W5cq5vJmWOSYL tdErPKb0FsfQSA3JBkldKdHnHk3mdQ2s/VDiiAFm1V6O3HHEmwW/VTYHkS/UwxQ05ZhhAHZ+8hy0 q1h8+f1Uzde+xPYwruqmXp1kKr6JIuy0BnuikHdamvbxDkfJxR7LwLFf7cURi+QaI5XWfGUzm9hW VNEB69Ey27LZIwaict+wc9VIYE6mLShG+SzFRblfXlJi1r3sX4d5dMbjWV3odA0q0X07Z6acKIrE r/46/+gTvCF7PmeWQvgGER8XYgO1jEUEn3BoKwE5gKfrnfZ9pAUyCfewDFiZPtl/4ahmIuBbHMxp cpUa28pDF209h50h9IM9F+BLBKcZjB7coqPxSWiQ5sItECAm1dndRPeQzh+0eZsEAqNyHcCQLKn5 novVHWFVu1KZLVXwtvVGd8K7AiXwMiCBwp3XNyBVVzsObQhgs4J6aZz6JOZ3iDTFPdbbjSUC5J2c sqC2tUnHfHrquPupu/q1U4NwKtH8dOZ9m8bEHDfQIDaShbLivOKLH22ToMkEOYRbHLSgz9Czc9y/ /Wom5kr85Q9TDV0AUxu01EkhODoGUMC6e6c3yBKLybgHUmZJaEjyb0x+INBzDHdF/nlfH9je1Jod ekmkODdIQiHdKUCofi7xZ2qDl/fRZReM15BnS4nxxGqlN9vGOjUnLSVtPoQPnwqQufnShids+8m6 +NOXJ/Jmi1to1rJyGp/SyZVi5Xp3qROhdTxSRZkNdtD57eKsxS5vOFUNQFmHU0F+/5UX/txtucrk 317SiV0f9+MisivZXMZAkbiLHo8jhk5Da1I0TCD5pn2ktLIYPlrvdmgCyW1SM77DMVhKy1sIw0s4 WeQBUjzuLWTzA3N7ZMeS5GJTG32XTKrMCEYM5hwbXJH+6hM+7KTvrSuvhIQCqDRwmqMHvFcYarum 7sk7R4I9cN2ALfulWpgzNOR++iCPB7oqnE0jNv9T82wMEG7WxI0Hs6HiRKJmUj2K+WD3nkXjkItq oRpweuO76Kv8lp5/GXe2dswlDnL1i4vsOx1vjPYsuE/ywe06ncLpas2XwdMXq5WNoRZ48qKGZ2oh dIQ7vdrHGL6m/DWRcaguGXE2Ruov2VZLa3HMcMUyTJEvLag2jdISgGpQ3UQBGNeFmCytSM/YWqRN yXk9dqVkhuSQc9x0CImn9VDxh6WJnFHKu5RJGAHIrxNAOktWxTS1faROwg/ZlJX0+Wcz8+ZA1GDc JTded2fiSPgpfghXoblcjbvi48zEzEU9JgqGeFL9VDXC99UPdo1h6mg8zHS2fwjT7FHXtIeHUi4d VxvXCOibUUKM/M/0Q+BVyM/NzltDbW0+hyiahIf9Wg0qAaS7qJ1z6IORr/QF94SOBMOryNSIpCBR uzVvE8zJRB5z5GXKfm5UBiV/QO4fqQPDjFQUrp9LjLOCdksoAdjc/drEf5sfMQPjBfTWwg4jxk88 ZZXa3GE995OJ8MnuK/vxmOL+j+v5lsj4yVNcAtuEyid9pUNQJeQPe43DOw5t0GEfTaRmAXvy+X8w csX3rwPqC+Z3tE0yPksfW5Yzssap2AJ4SjDhmcoefn/bdd8SCyMxTb0GxN6Ioq77ggEfvdMUe+WV EvK2Py4utVDWWuCMrTcK/0ToxFw4gdNnHpF1EXiAHQxDT56a9cGHSJ20/4rN6EQ6CkGh/ETaDERg ATMm8FxYHwM/AiLrknXzcAyDDLsJkrnnMxXPQOQqrKJHFaOaDt1pw6tazLd6yB4smQQuR9qM7UmT QwA2CbbfFIG8Jp6/JZoecSiV0KMItSOrTyI6oPORGEuj3MfPx9wqZsM3X6KxDyjcbLh70A6mRxC7 bKGprlpmG1HjXMnwGy6KGjpaEOxcqkMaz2j5vrdOQm6Kp07HP8llCMdTk5kncvbONNVptSqtPyOi KrINt7kmtx2nis+XCNAeYTjP0lOiKPGbqcaZdt9+JjZXaHDqiXIsIQYPV2x4ZeQ30L83myWNXi8J I2fZNHxf798nlKiONGRVkTEmKnZ1Zlvw/ZDi8sd6YsqNNd2Z/DR+4zO3+s4eEyvM6Ul8Kh5yEHJb bad7duarkxElLZSYuyqtwqmGvW1UlG95IJTEo+ApsjFdrL3nkpBGtFtGdIInGa7nUhwwe74GTtWi JsIXhiHXGJWsYujnJtVPOw1iTLO6VlA9RUw1lVGX0ZnaKI61au7Fx24IxDEKahoaTF/etbNzD9VB vfDZkIfqcL1Con0tDafC6pfHBokFHTOTx1KjK9XP3UpT6U672Ppa0lquXatGbjadvZuwt7Qml34r b3690tA4twKS0G+S7k+PfCiDp5TT+z4Cv5eYC7ZUNoazlavFrqmZBnvxcoTxgKXtCumDmqzo2O/Y QB8uwvMkqu2zmISZ0kA/0D8GZBCsczfzrYMBdgoI1Og0U4IGh0qWGujz+ITfW/9FTuQ4TKT5pt6k uLdp+27mhAtGgTWn51jooMxSSFeh8G2N2fJvjalBYFkBy/5b5NCIvRlOXhvZKvD11XYnZO3N4dh+ RGAJ58riKb6Fo0rJDd7JFAf/eShqnrbiBg/ad52luSRpimVAk+FPuTa4FFkAI78As5S8K/o7BFwx KjT4dJJ+bMmivWSeNbv2wnp53teP+rUuInIa7ZPa5EQjxbMQNB+ANxKDQTzG86YcRK8D0JiYxnPG jv4mpQJuUp5oTkE/ytUcVP1rT4ZRqZf+Z/5PFm012r0Uew8ECwjpZ1Ssa1lfqhlBT8EXbcKr4atx ElBjKVSCnTKLfRRC3tOY7K3l4mcxT4/fM7pRoE5kPke8w4qS2mN8uY4RTFaE6Z5jvOr007GgNkHh N+EJWTBOZWXtWe+axy5bJeZpiQqXrZ+GhjXjMksJ+pdLte6Y7doB2LrWvvmVXt9F9i3SDTWrUz5w MYIgW23KdhVRgSIY0bQ/bFCQk/Fzutn6KCE6awntGA+h8JJmZWiVYg2zUuumMQexkM4Dq8uTY1DQ u9vdM0lGcrlHnSIveylcBZLX38xgwAod88+bcT0bS/wJ8OBzioIsMUhk2idPoKTa5Gufr32pl2T/ PRMDXXb1cyB7s2PO00SKG2Q1qpEuAM73bTP2lsWtm0kangdL8ux4ISRKBaX8mGUH1WGrRCQJhsKN nydawcFotLfjLqG0LSYTg9v/fv2wk/dFCZY6IqskQ1i1HIs+CkgB7P7iS5L1cqefARVQRSukESJl Rv0UrhxaPbZyYpcCzkS/353LZJenJ0PZv3HKXnwlp4wfhUTPNFOA26Pg2D34d++wBK5FjtHBrcKp u9pUVJT51M+AaCJsTX5pfu0WlUNWgfIjSjq41JOf5fI2vL/Oe/mMXx7iJz0hLai3sjUrFad0CDGM 3TL4tPX2K+b7OI97qezVo20j/G/6qpbBKfKI3YyHktzvpV53vbgI2R0SiNUbNSWBh3OctqA5CQoE r68OR8KJFqAg3AjaWsz7sWYRnVOYc6qz1eKH7+EdpGV80EYAc+phlYb/xsDhcuSJKAfU8OlC9vnE rQ5wvtkuQij+Vt1w+o3RcMalQyVwGXznAC8I3zLaPQOV3gvpuA5lPTcPLZU6mb53CH/rJm+u2FcQ D2DmlJb1lJvh5L/5Yg343QiyqTZNMO7076KlQyBR74XpzUoApqZBGdtOvLvKeoV6exK3L6QFst+/ hSQTtkJAHF4qNcIhKno/B9XsUM9v3GLWE7HM5/20jfJ9BuxMhNf2pSisLsSNGaRQLV5Gi5JwpOR3 D1VOF5aw1oSPHFw44ZdXjIS1hX4qEV+CQYjg5aVnH4nb+ZlFo43Ha+P5tyeZwzai15q0/61Oa7G5 sSHYwLV3UuaAMo/BG3p9YEhxyRq7Pe/s/41Y2SvCcEiwA04ViJuPaxPuF/WwNVgM0j4jt0ZBofZM JFcJNgo8e0HnEXCp+/fayfX/psXWqiJM6gnkqwPWJyPCUCBjWCHFfVMP2oh/hFKs6GmDVBJrfkct 5GS/7S7ueQ+xstN+vBI8gdV0Au0lwXSFlv2ZvJX4ekEFCCUY1unbwjd1uAQn9zVEbZEUkkVMg69D b95nkYzaLFho9Scw7N9pA91THAuA+4YHW9caCmOI2qFWebLE7gVj930ocC3hDnD8nkLsPK/P+dFL Yik+E8mMV30CdlKTByPxDlYKbwp9NOYw1zZvmb6WWt5UGVol4U6rPV1K1/CJZbq++joDiJsaQQHw 5kts1YOUGiznGScrXgl+OE5t6vYtP3GGFAQH5kSbzxSBFhK7qmsspfZ1H1XOwpWBegRU/tSVTZe1 ThKljzxsJbGtrOl+QwbPfSWcpC/VDFOpAF6LPxKRoUrR8Csl/gQhmU/UsIs0YWa1BeLGjp81zh+n GZ9aVDjkR7jEyi2DcC5Xwd9fUmmPna9UaW/EDBW2z7X1u85R+w+kXkOSEuSPOJhJIlwwKRIHA6BY ZwtC07sBzJh3SCvNMTeyPEDWvk13yCjRE5lquqjNG9xwSxy+YY2+5V7/Gte4vLvdCkohlckv0ZCX EIbSH9DzpPsEMfenw3QRbNLxD2YhKN9/henssNh8oE+QXrQfoqBB98e3scc92GZ58IIm2u1lyVK3 m9op+VQP4E/EKtZMHu4oUjh9Qs4k/yHFIQ3ZNutdTxspdMOR5HXK/g+1csoRjtYTm8dbdCcOdDua vdp2V4o3ZYJvmV+TdLi9W9AzcSLzA/JBzpyqF5nAaa4UGzp61F+4vPV5E6oz68nZDONDfI/pESky AuAeBd+bgdDPvzMWrNA1UnhnaV5Z9ajyk68Kcu4OHVpPCVYGwIbmaV4ClxN/JmvemMlX/iPYZHki OziGHuKW8RlzR70XlvRP6tasIN/NjUicyXB23FcRYA+nISCMjBfEIo2cSAuJoE6/2SD2WYaZZ1hR p1gv+BL2Ubhwv58jwQ8LrYfiHQgI4aJe87fu9hVHq8T6LxkRMlf92DdlahiT7+p/Qyfs+GxSk6bF Gbs1FZ5IRobzuWOqxwWhmmF1mAwAf3Nrr3agCUgoSU9VfCVD86gh0LnQMl56XxnXOPOs6Y2d9JmG EKym2A1opi82N6YHfdl+1TpjtQpVk9r/G8u7djiiGmF1z/6nk507EqgO5cS84yZcbQBdbaNyVzN0 CCdDBI0/KAr9juvUm/3C0kg6ycRUpT9g0KSN31pSmWYPtHW8QqdQMnQ4YvVB7ao8QVUbXyIXriYR TLwsp6A/EQKxMiFgzb/6wuxpCb2YEkQhHGXJwBNS156bWzA0iYYwWN2dHtXmHrR9vNBYddtBD/tx YuFmogF0ud+nJibUaOL7c0JqpR3UOC+6Ijl1QAmbH6moz8lWXc9mht6dtUW0mjv9eoNYXO0wo/bi OMC8B+Ql8jolsE5Lpec3zG0BIBcbHsbQrntu4s8DsW6i8IzxjQX58uZ0V17Y0N1B4dnBdxCpIZHj jZ1QmemctY+EJ4XosGBhQo3Ec5BF0WQTtzr2bcuQVWyTjbKgF/ImS6R6TW8J9wo/YwasqiLrRM5W ykZWSDd5K7HP67BQfiSlaZ0FyLe6eUvk7EpSRZDTf/F+v59lGykDbJajxeVZSp99u4hz3apwTd6O SUB4Gt6/2mV9QqkJFdpt6IaITspXe/0x8iOUxby2vCj+MZ1fWQOh8XmkDVOPuECVGmPskJ3Yo3Kr KEITk6xd5o40sOf8zaGBeYEOJjjnCfQymK1HEw1gclIooDV9ML8LazHpFM/riJHMhhJMqXcXSG2i cf+u9rvuRoJwdCd6X0DXq3QpkW0sYBYTiRPbQwbM1RBko79KNx3feT7XMhIdgw2rhhy/JwHReZgx xWeGSOjgpd7S95yrL5xJy9FYc7y6HbknYt5ow5RqeuLZPaoVX7UCRREPSChX0QkCZGxxnqVqnkAn GS2O40k5J/6uQ7tzytEETFuoMFdNbVx5ODoTSBYwwm5WFWxx3+2gnWrtmHFgjYiarIjZ8JW04D9z R5xGR+EhMQle0VqtgKpKdwV7/DxjB9JzMVVRBPcI6XjEzj1C0PJdij9m43RTbaUKleqEeHltN/70 WL1Bk2wg2JCs72VY9ipfZadjwk/ThmuiveJ7r3x4VQCJ9lydoUMWdxI6D0azCf7ScThd/Dr3pm8v VtWEpEssjCLiQPNmEkJEdcXRJ27dR55SFUZwG9tKPDIaklw968Qw5fa8KgDLTRSfMMT/RslYfs4W uD+6lXNGXDmET5op8jaoXy2RBMVpgGRLvwV31YyZP8HjcuxnGItv1Zq2M7NHtuOFJ/H0bYxYBcRY OEqtoL48K6kR5W7nUkowjAZwO4/tisMUHBiJhMSrbCq6Qg8WTGUT5gvNoCAbrHNtP/iS98BO+JDn QCFypnn8dUxgk9ETAZ3S+U3KXpi9x0O3TXmwrGd79zLYa0fazpcRkYzRY6q/cxpLxgYdP3DrK2uy sG+cfAKJlltPQtuAEhEb2PWm7dkgrpFPYVsv48hr3Hlmxn8gvOuDxHyt+0s70V0a/1hdDunEhC95 tx3lcbBSwwYaerZk45Nrr1CdxFdFHxEsOGhwGKPJ8zTmOBPa9c1PPKBZduPkJ3eA42am/hbuA80i Amaxk/Yr1ILt4r+HRWBG03VvSMcHP4gn5ALh0OeZMzvrfKuHhdYiEyJItedQAAyM0YFqrbWAAnWO GtSLIKmroGyWM21X9gcq1XYDrw+2qCOSC/HavmBoQ/AbJ6ZSwj5uUFRyEO1MHDfEORl6BpNGcfho 9nHtjv/Mj80YzYxa924FLsTNVjTu/wxABVoHFgm0Bu0QLY3gXeUFnNEnLfE5ogtxR1t0RINbkyv/ AzYK7Sg2heBrDYbu716HFaGTrioI4NmyTDh4q4SBBrIo6t1wJskcwQR9VgEp6GUoOAY5vdm/QiMb jOucSbj7Fb2gTEtwZHspI3iBuYwGwu69AXgrAgRkT0JaJpDFTbqE/L0CXFsa9NCW3hzfLg3qmBc/ k1jrXnjRcsV690qyKYIgu2KsEkfWe8ChvqZ7w7ZDXrrvdOgdOTzA2xfOTm8xn7H22gYbmvAuR159 cO+SIDn+fuwGtXqn8O4cxwIog9AkqpyK2ApgfYVy2kOPzDgjNxOn0sVphTwiR9vPeGMHvFDvJUAh r0wk/6fPdwymm8NvY+hHrZ6X1w9Tg0HiHUauznPK+vpqpbh5M25oHFe4nzp0ObRBMXh6r0UUew89 kMZoVUGYDqAMW8/42tQ1IkKdaxuSfaQuqQAE6vnbliZLo3etEU5xgn/mQGLnfY7IVafzVTxsswHo UWUXF+8JaTh+DtYmH0K0bSb3PREz/e7YscI0yK6aj/yHRb590KKr5epLZiMorXP1R86BqwrOOdi0 AwaNecRF9iu57ijgnW1AibZ8HCHvkNuq4eZZiBaAio6gNLm6kzuBo1lRSm0SejF5Viw2oI9dUmIm TPsp44Zc5xeQLZooia9J79YHiLLEJsTJyrqwmWuEmVwl5eNFNtLQHICCZrzyfR4FUOltD7oZk4ZZ J0PRoWxAUziAazdZESbvJfrzF4AtXlnVwmSLvsce0V7vrxbl/mPBIjOIA3edGZL0H9B5tk6mR4GI nJKfqHyjp8lKYJLkTAzIH3u7tnJJoRHtmZStyzqIsHILxg77ktzknT1MjKnp+tX4yLYMHbtBRL6+ 8jAm86l7DSaO6PyM6ZXggYufL7/h2P0SgKJJ/YLAK3z1aY9/EsuXqU4rx7XqgUN8jPE1NFWashsL yeer+AD9EUodasUGI+tKBc6c/siHUd0g9tpx9G6PL0zayCJAexGQsDc67drDUjtKyic3WKUOv71o OznRHwlLaCsSJL7/or9wsSImA0wy0LkW5gUU/5V34hg/xb9YH8o6C4gBjqkKelr4/4DK76QjHUwN bFNBjurI/fa7teduJci6IWS/NIGBfEX+iJhNcude1gP1O11SiZTLsoG1W17dwjNiYoQTJOuIsM4/ MBSX4cu9T5H0bC3ahOW4zWOyv1oiCcBW1w+hJJGDcn8Snew5VxJnk5pqLPpaPN5iFPPhaXY7ZSNK kWezxZVK/krYKe43jP842YGv4CP4xR2rfc1mkzsjOh6JHI5oRwD+PzReRB+VQIotQ2zGmDZ8yP0m CfPvtC+DmuBWh/I2d6gZIcen4A54T4LYPawR6rQyn8cvU7MswwwwLVWkq8rd98gdEa28esCOMAI2 KYF5oUy5l3iavCwFVt7CV524ZBv5xknHmV+W9tKne5jj3NoD78/LNQu4ZE1/UqjuTMnyRAl/TGf2 Nv1cVMZnQdewqce2/wdRKCMEskfgxgEElBpBynK5bZbusLItaf54lMYd7TsMNOO1WvuAzLPV5pP9 fkxgk9lFSbLpKGdhf3dPQ/uH7jAF32VD5bNDOFlcxjdG8CRzu+TpbdpMKg5P0rgKwysLPZgtTn6t y/cpawjiKrLDPiCZK5veSSpABESukEwfXfRHwpJ9XbwgstsZyCmix/5hmYw4E/hzNaw7+BU7JBc/ xTr+O7hDQm2zyCUCIRzkEZfpUEuA+QeY9sN9nDvioMN1Vwx6qN87ahSU8NV64R/UEPUHjxZHG93Q 8Jm1++YnLpSg3aJzYxT88H2adSokNS9GAdEMLHpF6s7l+zM9e48v0GwE+8N/2B17DgJkWqsdWz4D GqACHr4okoOpe8HN1NWg4UsBN8sMP3PV1qb+RBawDTXs1frlV3kpytFlL7zOc/0dXQ927JNAJmDv kh4FmUPKx0KtEAyQd75KxUjtUkgwNnRsK8EYDXFKmQfSNADeFdf9Bq1MixusEeVU6hbTQUYd+DUB pATf7cwR8zcmozEOB88HrhbFC9BPzcu26Us+ieO5xbQvLB5+NZR9PuByN/Hczjio1iLP80hXgbeN 3iYvuUyvhVdVMZzmEsLXrbwJxorxpvF//lad7EjzcR0QNWDrMtzUnxl50TYGNxf+EwupNi8fPARZ Y1dKj07OwFlJv3IhbuOvlInGM13QjJGjGad4S6Ey9jeUoPu3F+ZC69dYG94np1qVzYxoC+OyIVRV 33G5xEd5+8NW3iWHLHzAPy5PCwIePmCYjJGCfG/JGMjc9Iezgu/WKbDqX9FB9qibYOHnVU3DJPln LLa0h9ndjNVpODko4GMc3YhSPigtjud2CggMjKuSVAN1dr3QhEZIMRnq9J+XAjTAX5J/P9KNPjSf /+qy6WWI5S7a3oniuHjm+P81VUpVv4LV6zGxuMtltE1flAxS9NrJ8yFtgs6aVDkdH3vnZa1PTv90 HD26sWDzKFMpe0xKwlnO11Qjp6l0Nf+yNASvF2M2WXBH5yYOmprT7DfGhByokEy2vLXftuzoTq6x /dmV9E8RY7bUpR1CVkA2Rc8n9je9aCqW4whq+FBSFjX3gnHDpI8tNN2lrEzJxkteTXkhnIuaUuag pnXL7QRlPCHleoOiGS+RSe1iit+ezZr40mghfAMReeQaIFYQ0/YNFj573zg46Xpy3ygFv/+30u7K 0Q/xX5sb0bx249LxtGaCGfUYdeH3VQyErouesIoLTj4ymECFTa5vnPimeRGH/I0brLrPxpB5vOAL AaZycDwqVhjDHobgGM22vcGaCBKwESUeRGY4IYNTRc2sJczyFWA8hhS1B2VkD1qM0sEe8BpGz3He 8xcePwHz4RAGgJeO/HX3H5UTytyBwaB6l9GYsWZNO9mdkn1ZOAQ5uzcqLDXNlbjpzsocT8S68Aqf Y1+qmnoJOXfnXi5vmhudIN8LIbZPu/gCLCMh9PithI55PKtdBYvKaiZDIKfGR7FQCwBW7bjUFOcq 8z33Q0MEJCzm9+shGcGrDH03bvGvca+Yl7vfNCAzVowv9uVRwXdrKe3Hw9ymQSnm46mo2JS+Y7dK gKq632O1jYz0RwrCcEa8EIL0EYPvF/rhQIhqRdDwP4Zm4h/tnVR2niVHYp8PdhvrRJgfoJtZTdpY MYmQqu+vbMl9OSecHTgcVpLwPueaI4lVVqnhHA2gbXZTXp9f3nAhfAfAPMcvU36Lm4jewfiO/0Oa wYWlWJMa9hYdsTM5NwfoV+F5DQkUwx9sl+CLW5XddBpvMqu/Hwes/Q5DXaKqdoefvEqYPsxtvgGT JTrSDCtjE+FrjuG/5qX+ZZgRDhbMwgYguaZI/geRVKOwI/7q5cKg70APkP7LJpv4EMhXSsjtXxKo Qb0li9nwT1oIdftXZTyEjn5OxQUgDu7FiwKNun1koPqWDiLiSQE+qPMcOWojYuEa5JQTTduiteR+ OxJvYc0Vo9sv8vdEhWnB6ea0TXlu4S7IoMnmR9xGPzYFToJNDfTVy3ufLMsNCW14D/BuhCMzAGN7 z/htQzqwsYM601+jDf3Jlpuejas9xUyucCUgBlsnNIvFF77yomBgg9V46xuqnIuevSi2Aas3PNZb 8NANXOnQZ4ltAUlEW1kNtXvLCmnO5uiLjruj1ujjeoyqAAKaFuNWBIxVe8ktnwgdLCtnOGk5K/gr OMVAln4GdQmroGq9YaXMnVAlX60luzTBTTJHHbVUNPjL575ZhWPdw4GpCvt2EJrPasl2WySalFB6 bxgF9PZjsxTTy5905AEXKf0c32OGoa3Ftq7G5xpePnBeDJeUFDITJ6iy6IsWCNONiTm7J8xYlQBP iiIyFSKFnP7OSm76nDC876sBrMwndXGio79WHKXlGzOtZLVvTpfMtDLevRns34NkIJ7xxeuc2Rzm I8QmmBOubCc47ZNwRfpbU2xGFgwGvyYH8OUun3XfjSXHQ+qVTOnBjgNaYSMngj2Olxb9PMDxAfef AJZWk4mWZ+qsEl1862qASVS/pfyQmBOxnHxrfeo8oYsPT0OxZgubpDj3+HISRHI+m7Z8rgbDy5ep AxNgGfrThZSrDS3jrQye93Dj2cKW7q6duFzsVq+9FYQeYB4/cAe01fE/4Qd1N7UqtFHtUheNPxry IH52KnJONaTiza6Q3tX8ImC26o+/mfmvj4jIo8HSkCkLDqCD9z5dzUvuL3vTHIhNx2Gj4VMzFlda 4IBLUKXR6veQ4hn1MM9l2zgZTqC55C7n+hbBe7D++z98PYQurM6qZeKmg13doprIJmQqWsVdUmxk j4FQMUw9Sx0uSmcJu8DeUZXSae2a9kycmlqvyAE4PiwipQd9EdDW8lwGthJJSW7C9Ev7zKhETEZd NDrzC9asd9gxfJw0WoLda2GugYAQ/Fe9L/R1+8dbXSe36JuS6Ox9NTUUt0yOTOZ7CkSec+hndjQh LBo1ZYQjuaMa185mpQFXL/FheRtBPAUciF7yWGbrgKMOzLgnFcSYGQNB52zmIh6m7IdSyy6fv7k+ lIoPQ+de1MAx/QFTEIQBeWwLYUg9CUvPhEWCcy7vW14NXFMMgGYatpII/E5EV4Bqd4wapDgduuSs S1c1qctfvmoC5s2gZa4oTR6Xom5w8Ob5jXl6WpxmDSME3X7UIcOX0gjzMS+0nxlV2Bnw+TozYtrj 7r59f4WWSIZGZqDRh8/SW1e16jnW5jZta6g4SG3lSgJfeco/S2JYakmP0rdSbAfLtDTvTobSIrKh mumETCkuyNwcGYGjapAnfDVTwzUmI4JxKXbfxh/EujWmHztxLQi+TUyj8ttG+18p16RGFvKfIFqG VHq3o9yfZxKIaJ0JCVzI3QzYSzbiIVNrD5QUrCkWCEb6vrH4auGKXl5GpD2O+yPYkjk4WU3IfkbV CE7y7lVJ0LLd1P1m6b8/idU5drv3oNIBJotZ+Xdpk5SSp/6EIbFiMiQuFTyFzwzgz5XYMJ1ZcYPD 2AOYgosOMD5de+fsMX9/V05ycBvBwdhpE4t598iLVzy6MozvRhwRqsi1AuEEId4K6fPP//1dx0Pq wlHi5pC8fVc7sV2bNUz5Q1txRg8TRvUlulsKibHYJloFFuZV4EP1ZD5LjOKRkAwI2laTqbrQNLLQ w4nrsVnp0+zR5ncINkDvtuOswqxrfcbPIQvb39UrOyqDCwakdR/HmOoo1HR8lBerI5YCZi5FZkgD LiDxbpffa+83VHMxAM5i3QpIetTRt+zJhxpF6+1WQOOM9wQ3+pGPcGmaR6LT1B7A9Y5DBxTGGbjm fzRkbu1+Ta+7kjzfhZVhP4MiYlK8e6fJYbcerw5ylsf1eqo07Li9yTCVstZ3mi3ebFKXdne0Maim bXh7M2fPsGrim6YBfULnTlnhDkbIoP8qPiVqnTFGO17rn053Bf4NAC1sKlPqhRge9kXA2EwKn3sM 38e75nd+F8WpjYCK0NiIchzLmh+SHkmdfurYg6macRFIjM8pnxx6ELWcVN7AUXgDu3YIcjXCVOWr f/QH2PxZUaq6Yo20MU2LeU6tzuXjYT77JR7Rx5/uJtuFVqDRnL5Rpt3e6h0lRt6lVVrL3IvbYHxX DNio3SDczgo5AP1EvN+/H+PpDVH02vnbub50+wk0KfMbJ/yMxj6Hsfvt4w/+IlSBhR7v1V4uimuy 1z+DdelJpvjRhCq1UUk7ra0gOWhafcto8V8E+ozhAyik8shqEcRA3Wdwdj1aNtdJERffK8/eHBBo VTLWJkTIAQE2zVHCOBOGj1s0ZjSW1kgwDV2+1KyHUmwX92Vot4EYjMboRn1essTs/bneEyoSi8ks +2GqVwIoUJSVKiB3rpe3aBFcrXCxVk337g2R+SjnkO5/LccDwDQOqGR6UnuLCL/Nn/lTjauTZdhw dpPYo1PKqFUsWYFaKDD5YJvIwH9I9pQWoimTEXhOP+30SKOhcOSeac+IOU50pjg8D77x/ApA1Sh5 nP/9CF3ZakCQRcY3DY4ze6p2nk1z3vOjoFb3kLaInVwUmCsBqCNlK/JR8FdqVc+wEk1BdA9qA2kn Bt/b7SRUHzsetMTpcBo8E5xLKHUjxwp+Uylnwuz5iOqGVprweAyVYZN+uzCiD9AwbzNCjrlFGDZQ RdOPljsv6v2i/PoB9y8+XvdIiftDHf1OUtfV+68F1qAe3vRkF8Jbzo6TEbss4TsXFMjlyw8tk66c 0qrSPj3f6ypf3O5NGDfd8pnbIZu0lHwfNaq0XnLO2SVFB9QMAy+TTGxoJB+6qUBEMOa1pdi7edPZ vCU6MQfN/Rt0rtg8UF9QRFCJ+lonQht2NOUZ1UYPnv3MpGdmNlfj6nG7ptgCVKksrQtj9QOIPAEr jQrpXxvxqlOp9youDY3fRoYIT/Nw2xTsq81qpExSeD2+Je5Os9Zui1X8sRdBUK1JTKL4f/n+l3FF 8ze2W7GpWI/t1mSUltB0IubO5NeJP++TBPfxWnFSA7J0dxbECeH9FEHLgYpFrPtJABONkOrmW/JQ WGulYYQW11qYkXJ0gi8r8S93t8c5Ugv2p518a4IKVE0P92zIaEVEOQ9JlGRyMcWemjhNRo7XFs7M iUO9eVX5snVS8nJcqkh/qL7TTCP/sKVRaGueD/FrjfwB2BqlV1LFgviYM1lgENSd1pOuYQ/RmXR/ JcOByEzWTkzZ0H4tomSrMz6bwT4AJhT1sM8abWoPLRKTL6UyAvwXBOZzOFTdnxWpRbvk8dwUc+jc mqSEqmda8ix7PUwRc5+SMnn3crjHTAlEsxIJb3fuPsG+a26P63CxznxgmnP8klebrYW7XxKjrHXJ 0oUwptJdZ09D/n1M8RjuZKKV+amnCA6XWtcvGiniZ3JKSqEhQ7yyYsr1Aqh4VJDfzTZQhbZn0y9M FY8zP3OMNoa4Nkpt7sutvka7OhNtA0Y5tEC+63oMd//e1QjWpPxlNaI7zPuoeJtCytVVtpeeNeoS Dwfl0em9Cu3e3MviQeCGsgUtkgNibABrOcjLWu+ZKLAwWU52jhTJTrjM6vjMELulpyd7HoN4TYHn NCx+un9AwqMdmi9a50Naq6rsiqJQSLO7raHENCmby4AnaN4D7/AkBY/1m2j6fnuoNsM6DKrasT2I 9FOa66nGrMN7ajRbnf2fbpRpamR9PynI9jHoc0fVDaYQxih9op3bMhshKlGFIMndXv+UXsWFhUsh yiEs0jVguWc/meE6G/tnFuqr9x/geNkYCNoVha4xs3KfC2rWZDgo1I8BIWtRM8A7TxETf5DYX/Z9 hnOcjsdiXVEy3KINVs1rXCigtUMbiD+HCj5tgw28RnYwwbRlQdE1ETPcXqXeWsY4LBr+IGBnVTsL AQLBwl5mo5bjfzT6LVTQHgR4nS6C+H5v75HRN8Q7g8wFLKtv5ScLxgTRRwrIL/vRpL9pjDEl3pRt DqggYGFcGK6vCSePmqbDAXq9JBI2mtgFq8qP7e+4l21AcsPn7i9CpATrd1v8vsCFJkSnnykcZfKd 6BEp3p5kbb6e+5JZDSgPeIF8e79o/ZqnQFfE+FzBGfqGVBI5Le+hRZAKge47WWOLFefKDZZ7eEBd b25v8pjJLxiQlNYNWpun2puQj7aQ0phQnGVl6eRIvr32pIS4rPeKyvnX+3SreGQeHknvghYKZ/D3 564wYYhMmj2rQUtIvTNrsK0w4fWyMofgsoZlDcqi4tGqc/ruc2WHTJ91I1T1y4DN5MO41J8F8RHo bRAumjfGKrTLIs1RF7uib5u5lPdhTTjW1PVldKF+KsiO+lEIq8gTrb9uKSkv0nzmpHVckVml+ux+ RToEd68x2CHonlFkRNiH8OAwIdOfdP7s5OMzYc3Xm1+qXg69dXS7LrFIkxqqTuSfOFg0FGtTXXAZ lwe0euE2cdM5m2mqNfWMlrl1gJqq4lCBnccgWTdGHwmvq7xKIGRFfuHP/OHFu9OZP/ruM+cB9Xc7 m7ppgCR45tjxzaAyqY89N7BASOVB1dtw18b4OWzoliut904OjNhC6wHqVzfBEzEzXCpfbL/TTXAJ U0atzVEFM7c9EJTXcc45I+xb0g+T6LjdKsRHeQKc4onTfOEIg3Hoi9ZNH3Le3Tw2dqNcsavLN5gV mvh2bLBvXfn/nwoYaFrqtAOsinVjsR+CtRJCkS+I+RJzlhTYWFM3hRMfgZqrTVDbxqcmuPT6D7aG V1PZ0JlnXvxcnDHXbQ5spDvVCpT9i+dVaFWqgTZNAIgsl/k/+6JYX5Dzt8iD3sMHAxyFMZdY6Uqi uUVafgQSYgJ+HfV5257YRRjTTG7qd+bh9T0VnTlSz+tgXJersuSZhACV1OztvCqibe9h9qwX2TGp zlz4Jou2hQmM+zktnZ+Wp+uSF93021TyJp3qS6rd8gMRSPNoSM/bst8i2qPvPIR0vPQr1TdON0dg VLTE+rN5FPuwzbawTyxFYLRGH+6UZWfirwYcCP74HzFDjJxUU+/Ltzg4tthw2r0TVYOOY5xne6Xd P12/kLZX168WSYLWmRnzYK45/OKSCSEtC6sGB3pcgB4CkpbNMhH6qKa7fHV7v0RIjoV6X2u+rzN+ /pKE6pWaGQURutg1NIeDu96GL/ImQwvZQXTsRumC9fuLyhpoH5Td1vzZ+sMDSd2JftlhfZ6TYGZ4 8CALONxB1cEQHvHMtsuo4srcTjA6gYXKuZFU4I2snwDYJYKr4ynuYjzTvNBytiN2R2hG/aJS64W/ XJbPWGjqn5ItrWj3ZO7wxuRTs6TSIL40VDVFDsbefz5Peo28W/+68pCpcL3d0QZvVBvEf8E+EthY hhcXuNFnp/EQ84vCuf4/CBclJv/qxm8IhUxjDJm2DNOKAl4bwJB/wAl9f09XLs9Zx7WinxR1JYTt o9ZBFuKg5k6YpqEFeNMWBjbaol7+SEeCOCVJa7L5MK2O1M7aUisqjNU2G/blbpGT7GzzGJTv8/1N MIIGZWl9491JtQNZ8o/RkJq9DRCpcunD8lqFMOyRQ+IbIp4/+8incnr0QWf1LPgF5ciFyGA1xtgi lITZmRXo6d/bauKyzkNX6XwRyCp7ak52SOvDQAjsqxaE5W9mPFLfs/irEm9hDY6h40j7PpYvKpwa SeXKC4aGcuurbkeMALOxAa678R0nxHme5fBHSXK8PzNGzsXGihmFBorZvkUf0phGW0wnNNQXCCNO +0j9SRvJzY65kP63VqIEvrc42wkS+vPQtsEups/DL8Rgh8WUeVECm82T5Ia5V0IxNZYWYQbdsp9W XP5wP49e88aIiCJuj+cDMWE3OefoyffXlRxLmL2NGoesCAcTgAZ6DHcn6fHi0adOgtPwdJM5jLjX mEtteHDwL30frSESMnR7A8Di63vm/R0iZCZZrA2r4tOOrWDK7Wfz4xdU4vSLbHEOXykCLrlgqp7r HqPaMVwdiZHQYlQL1YIl1zZlG6ARC9TdcCb6jZtzTUyXcH2ScDuvnkOW0DejyPLSjrvcq8t9rpEb ZGWzqZMM0qnJlfe+5NIExEXwPDingJCrGuVu2astICnHqeG0gdfwBKwIFZ0vqaZsrw7zWhuZGzcr N1FFtFs9WGLOhU0TI0e5oP3aR5JD5IsmrkYmwBd/GeK8Omq3LF3G5zTk5yKSBDsiAxRyceAbVE2Y KaCyCxk9+Jlxu9F3DSYRXaXrDi5lnNHMZ1CVj4MKgFuUM7CMEMCTr++axW5C2QWtjfT3CPjUYSzX nISnxtSQOYfZqlYJQnCpam7MtTV1Jr7X0emBiKc8EV1FVcLfNjm4TCGVq7oDV9Cu9tJpUMBgsY0c DfcQmFATFzwJYmbcI1XDZQeLpCdIO1op2p0BNBKB0K1Dq3tHCJelM2gk0EKmGKF1fC5sldEKUpJi 6WxkOOVTCxTuAMi7NsBbGGwDtX7IkpdxJVRkKtbVG1vgwZub+cxHrXX5qyb9e/HmkJ/3miQhPZRO IZAR3YAz5Z9lH2/Ufqj5qwcdj2mJ1+ImEmXIZyNTMMMlNu0Dh8VYgYTIvYDjwyaEjsOoBs/agAOp ammxY4KYdwCG2K/sVuSLEUEbX1AXklZ93Wme33fDLkFq5/hADorXm2f8KJTjIt8tlm+kwb1giGpA Juy/2Elv/Z7lRG50mPS0kjEhnFBL8PfM47RQ9Efqp96R/v5vRjovxYNWN3s5hGQZUxeKsl3z/fZg VCZ2KZ2kAXlzoYHmqZ7CDPP672oFuMXNGmJNiSHuaHLUcpzPio1rFIw42XA/70r+NAOQl5TpK3km wNtnVw9PMPMNQxk0t309iRSkzH8xTxN7zYtEWAUinUSxnWrahVdvj3EtGOPN7p27xJNUD0uMD48D ixnvJwst8OiEpxvNJuThCa4m6M18l0gQzAGC7yoMisC/BHARRAk7fK1VAgffeLJQAr3W8kA2Qzcy q4a83muID04lFUAIil1DNh0xAf9nt9+gYsl80s5+vjMpvUnyajnyfzvZ77aw82I/IVo9njw/RyMX 5Dp3P2kq1I4LdWbbRQlYoRhIWjlyvyoorBhIK03aVqql/v4V5Pddrcif1nt64M2jpIDTLzU7jCUI dTiVXp/zZ9wpRjbP/rP4MBDAHpNz7F3CasekMppFvymzUkoHAH97YYKPBP3CcQ45GgedysGpzQQx 78Nw3+gvcZJLiO7f9IdmYaPWXUvcbPzqBLGy4o1Rr8HrErPt/+RUdBPju2uzS7+td/vMWCaJ4EGq AiU/uGiFZK8Wha9iLB3aUqE2jWUVgdsWnNZ0WHbTxeCq1F7wNgSAailXPNJpykafaYG/G0YwHIbZ UM8ERaMjwnekXXp2fP9s70pEOKL5CgX7nR02zUb32/uQbATurHdPbH2RHjm4Zs96dAdGZJZrm0UH Q5hq34V9b7tA4LV2r727YGi66chYLji2YvgCpMH2jU1vfx+McMghO5ALhwFzKI2mnJCpCJpzz7He zd4J9mwEXWIgzgif5grgEcpjHUXfb9CTLnWTn6d2G0cgQhYHXhTd8Ia2luI5M/L6JsR021YdooNL wYlvO7Dku1MKSoH8eoMCB9gebkvN5IT3JeLz7rA6RzOxPqenNwZuVdjZ5ikNtTYUi3HypAOJYZ5Z Aq6e4b/QO/wOtGxUXbu8A+aBJieWwtNRoO8XilxYPocea09oJ4vRC73bKHx4v/cCFxyjcr9y77U2 T3l7RlM/RHpgNqUkOYopZaznZs5SCFrDjTgQxQl+WxRn7DON+7gvgd5G27eHTIOxQaROqkhV/LNP +uwFwWzu84NSc8gFvunmkW62Ls4xsGu8y6wyXoAp+i2j5J1LdmqHHpXjabYV8z1Wx9XQOa9NKU1k y4j7o7y5McXK8CDKRw3+7mtNjLwJ5uh4M0+33FLME8AzceDBimzt616sF6ATnFn6hozCZ3m+Zc3Z qBXyI80kgYS+BbOytEeiyKkFtRsn/sSGsJ10FQjqh+EvpUfbyruxf9PWwgxFo/z8cF77L8e+MprH e+nc4/QQaip3WNWftxXIqagSIvfbXCQ+uqaGLedClmFtVP8FubDap5yJv9HcF9O76yH+7IomCpbr ZX/Vxsc/rrJSkHdu130cXEwLxbBXVC16uJBTAkXa13q5eTgAJn1tJDVMXdGR3yzYB6ZL0AVGS9NG XWbGNfU66bk6X1PJzYcBdlWhKXlnRbO7CHSMXsrjIyxuZ1/pjpHGHCAhZ6mVXxvpO9j3fiwugPDL prA2jmOYRh1jgRrj6McPCPvyVpfGDgKVk/ZM4DwUjIfnMDLpYbSuQI+HTkimIZHApq1/0J0GTo6n fk7hPRSiSkGEUmKjVRUdOuDCac6dDYBWJqks5zmdH4YVfbhXSG6PyYuzG9MRTTCw/sjHKWKxOD+e tY3qQa1lkrD8PzAHuf1sUaWUNYj9JGx21UlvH7WEqySCsuuUhS9vhRnB1MrGO2x0hDfu+Os2QKBj wp7p+IiXniGC9n6to4Uefy5hi1kxIosiCL4wlkWKL7GkmxkYvYiu6aX10qdJtdPExPFLm+tesH/i nbyXpKyJk2qZFProXN/d979eWgral0ENUvzhCRpo2c6lS71eehA3LJKiA6+7Ay8popk3fqo2avpB bSWdknYBKjhPd3RGeLS7+BECSgt6/calOnfMSI34qI63B39KKnBwe3sMKZikNsDj0PTTLeqYcczx KpfTW2bzcaYJjMJmyXsJvYu2DEeogzGcprjaXY3BkVO//bR+kI2nUAg0/5dZf1hsTPDO5/bDg8sB l9ayDRJdXVgvSOu1UnSsmUajtQvnhmZrx4+qfy4HnExLkU5UmTY/bhYmCULLxXNa4suD5FSM7AdV WtnUi+Lbaz+t14k9S8WuHKIY5CAHAjrnMAEP4NxYgHs8IHoOi9XlDGyZwiL1MxVqGOR2paiyNXDZ S3ycx50k8Xyq9iPh1kO6uXF0bCewrQxvzjTBkuD2+KaEYNxLeajTDmhtyPSYhe4iisYvKbAofkAE daJMRo15poBXawj4UPuIoWLa2D1oTuXIiMXIkj0xb9WDq+uNJ4imz3/ubFRuzAd1oyEDvp4UFWir Q4OHkn9RfewpTizpLBNcMKaVaxtClVr3C3rnris1IpLImY2vlSgKmV9vodhxYCd446oNnKnBoia8 EjGvMkTR9/b5wNH8D2XCMzGqhVuH6xqzyxnHUVvBgoCd3zGK9TnZJcTtiwitwu3esgUjsRfaZKhf hOWTWFNt9DYzp52/LcMliTq5lMBsEQeFWAhgl+sN8EQ495xFMLmGgbSRd3elKXJNup0zn6lvmyTi 96imZjzkyliuy8QH+uBLVyWQ8pOqC7XIj09nKg26LWyqkChYHIF59NtSZChFSRAnnCMcv7S3sDIC z+LAX3C0S3ERm5HD2OBi9bWBUPKGamwQ3Lh3WrrFPAeiNUfp1vrOIGzljFyI91JaMth/4MyM3aAG QQrzwhthCCAw6D+YL13EMtiWRbm03Io5BNipN1wc980Z9573T8DAmwNj8SF3meitCWeVXqsaJL0Q IC15DAVP7wnIWZM24lzke+mOqpha0KFotLu9QZxlQD+DFc3RFLV8JZJopOjEhmyOlWEK3YU07tOW AdBpFjcTkKQIArvC3g666BpCYeYzYVmTd27i9WfipDUv+jeeFGX8kNxrPT53pCEG3AUrGNTb8HLO aS0DALKx5n0cTr1bDLQhNd7JSMPo4FjZY3wwpbfozNRtTfKvVQtcSXHdsDtvZfcpLkmqBpgyW0md 7k8qJ0t84DaK5uq/eY0D0LLeC/eP96hibnurunbifCNEr7IKNzC5posW2HZ87l5HugiahZN9t7oN w/a4tcwPowv7ZPMPNObfqJ01kUJFlpI/eOMuDykEzReTffEJmHZfQUqb0OMYTCfTpBwEnBwK9UJI VuUm5ayjCaiv9LRbxQUBOlI84CtNnFAOcs309zN4ZxguHHSAWcWKVui1pJunGHIxo9Mk2PU3zPjJ AjCy2xu6KCn3FKPEpR+GkIQNd7ivz7U3U8Ji5dV1jiVH1qOFWOzmkZOGn+N8puIIud5wxrmjytpF zu4qI8AxCmqzEfZILDoA4CQoW8/c1doybo4QC1ZeAX3M+1BTuMf70lRylmbFyGNQyUITxHaWJDRv Ot7+E8vOLJNeIxlzRBQd2g6WFz3p6mEbc7/Cgrhf+VXWSxV/Blp0fE1XeFdeAJaJKhd/S9GGip+z urW6egGaGFm476rFwDA5dvNTchp6S391a2UI/MIezSd+tcvwzBkptPpK+Do22KrUXp3/+0TkVGrH RTMeWLAlIci5o23+3EInh7a91YuA0bSsTCEwZDZ0VhXs7Hm3dWeuWmAUJONYWWciGL6Ns6UFVAEb EkpK8qKhaoaUVLE2XNwI8MuqKdN411Pi4M850wU3M9/Zlfb+gblCGiZ2BJRx6orrBSYYQdG/x/EZ Jah5GUJM/ZkEBuTZAV5IEN0YAuKx1Mb56jUT7iHxeCoo8Wd+pISfptOO++UPKA0p/8c3enbUa5bU Gve+su6yX9kAGR1ZbyK+mZ+0a9CVXF2UcTsILk0aygTqznfwNVy/PfVnusu53bQrGtQExushXEFO 4Nr+PgfeUpt6QFS4iAO6JAmv47E/rl09Jvs/dVMtWAm3Kuqz+Yzu0VZpHJKCEI0h2J+Zk1vrf/IA NthNj75A2WhRZ4TruRVw1plf8fhfgkExNoHUnXWLACn+Ty5FsHE+jtyFaQQMuClRUiELoha7+Tv5 +a9rjYRtcuxJajCDGMOzhx9qe+Nn3+fg/iZhd5Xe6CATVtQXArix7nP99Zp0yyAB0rabcMVcMfnl 5b5zdnp73FqOqzS6AU6UGtyOmhxX0nqczec6kxmP1VvFZpzM3I/QXzxiLuHMhW89JDqYaHdopBzw VgyfkzXpNoENQjp7dyyshvcucqL+ATpv0AB/LMQXXqJZl5oTde5RRkHFSCO92teUqx5s22TpQx6m l02mDs9o5IBj4mB8USMbvTFqaTOVTbWINKgFch9VEinkTJlUrrTLihRea0Yz1geEoG1PVmREpyi/ aTdPlNbcrI8xQQoZnqiQrV6N6mwvs4rkXHg9LimpGnD2hteeKNYFz4Q0Wj0T3TYXdQwQh+t0FlNE FgbGWFPe//b7xhfFb4mX+kGK+0X7luwhrx2moA/HBtdOJMVEl3XeCw9tnLf5HNESJrt5jk+KvC3l AS1DimK/tT6luwP/nZIhKvecpzae6qT6QiMv3xjX26xQeEbp5xwqFRck6Xj+FCQE00ZE5DL5OT+A a7Ud0LBjlmJoVfYT3IHD17kpthM5MvURkMG778mF4uY5jxflUUOyK29Dtnz+We9I3ZS16dY3AuvX 8FkpPO0+yRKC7x63TYWp2v5zukph51fACGv8nBeT0Zdnd86+oQegz2xBB06wG4ar1cgoET8lS9yG zAtjDsnoYZMbwm7x5OoJAgtxvF9u22gttuf1KwD+/+5xtk2yv8oth82r28sDdaOCDlo3LZ6Z5LCv QVGjTykY7ULMSLOSI/RwdrJ6Uz3+cgDFIq4EUF9ljR3cms1wk88Gp8VrmzssaIMbF6n+PBFFYSH3 H0EyMAaRPXZPGz9F05PtirE6GTAlhFBYS3T/vlZ9rts6nSS2g2ci2lacDDc0x6oJpQxos1AHmZRx yvpYGz95oHTTEuARhh1qRbT3GA9LFuv6mo9kbTSDzsVmYBMGbp8eBSE/4geBLjH1Pvcw4Dzz16uE oqNtazNRO5aqrmrUr1kE411enQKAlUycz0Dhlmn7mLjvGdCpM9LotCKJHxKmUIgu+LJKdzTmIHAg ogjSDoLd13tZ7IE3WXLafIOmntyBEEKAM8pjE4C/IqUIXOXLVW+N2rV3y9AytFYdNNReLL/G0Gho 2Zy/WsambBsqRCKYT7dId5xh+xuJWGWt6pI6rw2TSfb8fgWLe5BOpoQdTWHY+MDPNmEkjZxBFLnN LgMpp5226JW3ZNj0gYwyO5v5VU/PQXzwignEB7s/qMm6U+lPczsqFUo3dmJqUR9AGwP+RCkfSmUP aDAIYvuMMk9diK2UHMdE3nEC7MFSJ35bNk4PN+DBNQteqkd1aZD1DKpgVm59/Xov/iffaAP/vQrn tCxQ+XkyVSBgZTgEO8/q+KS+fDK6AK8EHtntjhDTjnl18uuTmpqS1ROM9cGMghFQY4IrpEGC3ulA cR0vOp4+MABIlf1awzzMfDDZqejkr8DR5GDayhAwybckXYmjg+93Ao9amv8DKDt9hxkrEmE1ZG+H y0QIo6YqCu42XtDgj0eFqkgrNH3/mt+mA6NK5xqXVgOAZw9HM5Gm6xGNjNvHqdUjfljUZUcj3iAh Apr1AfOwyEPIA+4iwCkKlYCKhxLHd9B87yHP2vbQznOaAqzYQoCYT09OSVJ0AMWL5sIP5t5Rm22c EW9hsbIpyynZiwRnoP9UlEbDanglTS+5Jijnv/XUo3/1/7Qhhd57fUbAI/mb6eBBfngio2zMUlPz X/vAnWWecVtUT/f2WnRx1u6yBSTms+XoadvPdMBkJDxsNu9w011pNpqJ5u+NhJAS1MRy0YYKHyYo orMFJGpERWBHW2AmrpVe82OyFXl6UjqnwSxzv4GGHkIacqfbcZFUByzCKPo5sr3EhlPGYHBcQojn A/75Qv7Gqps958X7VdsC3lwLJa4EZLKSVcYcMIalVpTXy1DJqdHBJ1TPcVJBAtwgnpzy1Rt6mc+I tvZF6a5p++oj6LunJSv4MBo6bJdMHhk/hqZu81rPxlx3R5QmYveq3lRjyuiNl391usgpi5Aoi/Aa iOHpIekm9oNZ8JmxvlovOk3kjns5d7jjUiSdn/J7jyilXC13fWmczpOw0sQUhO/WBd+Q5XDvZ4dS fV8vz6v2iuuDPv/+FVS8a1HskEOgJcBqWde3H1a4uKWSZUzFmwTNrN8fTCjIXdsBftvE+cgXcKsf Uf/izgJHMzD+PPnwTTKTeyMWRPzXyD12bpxa8Sx85y5LoajJO8ehG/lK50fIzdk0yM9DvJAFS1Rt WiLdUfi2Ig9l9K5xYBdI1e/TMXZt9d060UP/dJktQsj4DAVz561jcTk8tLY1riXd5BeJjJ7eh5Ca UxR/XsrYXTkbaXg827devvp/9SxryFFMVvkghmtYYGpl6FxdoVyzHY6dj7rKqMTYrPyIv7O0ATBW Y0t8l202+M83IluNa4gnbLCdYD6ZPnGHAyzE2+h0qGLiC+tfM3G4XMbbmwPKrhRpjehbzhueNzz8 GDWD0zDM/bmqtNMtUNMc33ZdKT5hHHvU/kcm308fMmGCtzGB//c7Q4LePBshyfhSdXlGole/N20n il5C/6I7DKOevHu0e4GcxpHV8PtM+zJAihZkLD+4X4kLWtqPZ3faTcB8AgzDqn46LJVM7dDiq7E0 DqjNUHxlxoOCfZqV94isydB0xg3CxUhwNzMGGj2Pwy6+TKTrgGWUw97jm2E4PTvDR7gzNuoyg7VA ECL0beT7LbjTHX/Lw1RS9iEv0yXdcq3qyag3qf7pN2qYkmMu09WIw/UNjSsx36JpSMlEygchy4Zp 0n1tggkHEUCZmQYAS7GMNzPhnWlBODzPm71mtH0GO+MY6ne15K3YSKURwwk36ZZ6tdHAdPO6cdMA D4QayBu955ktLC6v6MMWGcCxlUehRUMpSlOl3DRNHxp7Wy8rAgo34/YRfUcwEl6vu3AydmWUC3oT 3YiGnwoeb6nE5KYOy7u+WPmzmAMyJZh5HIt+ktpIIs/BXnkgPWwH3fY0Inz/7Ij09WYwnG3kb/gf h3MiR6Sf6cHKdDaO2Y3cOUyj7VW3lhi9Dh6ftmP5fOsDCcZHCuRWzymf2DenmR1JmQWlf79MxZkC zfmutePYzprb09uZOdwhqgrJTHJBwdXYy3MzGq/AgfajAfWjdso4pMgr+ffiSEDlgM92Rx2aEDxJ +unPxp67nrLfx8sS63jE2oIcF0YADJ5sGz0FC3GNLyzyN0KlEebEADDPdXokVNvWxNYydGxppJuE sTiFIUOBF97mVObhsS7YPz/IXLJ9G3PhOAVvkGw7YJq12/1kcbny2kuPa4wNa8ruGu5bGm0yHyo1 lyk2+1Dla8df90CPZxr6n3kvNHUDLbJ5qAdkdOIahb1r0pD6fIhZB8juMKk2uUhQogydDQKb7uUI uk5KV/rK4olQAtQhBOfAW0OVFeQxqcpR4XHSMEe60PkO0o18OAqhnPL+8aM5imSSsrXIh+dWv9Y8 TV779wyrZtZ0XdZxUU3Ms2+sBTtkPugzecZERisQ9hAsDsDQVyeLaSBLjEDIBTpiDD5ItE7oQbn3 7XcCBkRckAy5B+dtvZpANNUsBgfLZiEESONpnKnq99q34KRLNsFLppfYEkR2EZdO+s4qbd4zdRBp +zIZ69dUqmchkxiVyBhXGhi9Zxyk/rPcjAuOXLufVI3nC+p11VHa+ranoFyjswj3f+05WoS7+p+N B2hRky+RP+n8p+fvDOqveOtzqg0tAHdEnGp7KRNmNcYVt9lr9P7xeOdN2+h/PRPpjvc8Y5LEOZwY zJvTALCVa6rNgDmLec0OggQSydB8irOBQdidy3L5GjQTMpDPIIzfQnEcHzVtqLvy/OecrjGmLrQ3 2T5foP1SYRdryvhOySDuZjuzWmrxVBXDaat1XjXD6iFPfUIbcocy62M3A1nBwHNP0oGnsVV1NTun TVdWF9trG70J/m3L4DszH6vG7g5jffbNC03wHL9lYfrsQzAC8bKzeVdJkDZtSa1ONZdPTChDqN5H G0w47ymDsMCKDHi9zAeeYpp0U6KdNzwzXigTT7rTsY1MfH/ZapTWrmTpQriJbMkaDr62rnsjzjK6 AjKhfDEVyR9pV6NKzYTAlAZ0IE1/r/7EkdFotg0MqeRd+bAEpm8iRK5f/ObRKjHtFiXUgUkE2L5X 6VPBXXA/8+5NEcwbXHhGBfnBrcMVjCfrwmnnsYVuPZxkhNQRclRiIsccFHGhHd9uNH+G1ZB7S80z pWedZjpDdevOzY/KHHiaB7Dzsg96aHNfYEoIUHVmM+fNg+JKZ1XnrlcZJ9A0kG3xHL6DqAeTpoWx wVWGReCo3e7wdFL8lZffAmCImPHzeRLi/RCqJKF3JLvZvTd+JHcMc2fl4+bvSpdb/6fkLT+mar/p 0q+kyevMsz4YED3ce5+1/0DhXekEyO/QazydeNR+TKtDckHlTP8tkIkzONuU4NF4+Tisf+oA2Pfq bLM7vKwrunJU3gPgrlQfUXfkQE52bkVUtBACKZf4XKx1YgqzGf3DzWIPV6VFX7DDSmDbGRKAp7of jXBSmvOVaLjYxsxJoWThQGdpsbkpA3DQw510q6RbVfEE+IF/OVnjdR7HC8WSPPTVkr6suRyh6j1T ukSS/xnu58p/tCdkqowXPg3nCyM2hVKI+zIYvHav7rhPJ1Ebfts7JM1mJ7BoKNQzTkHf39ulM8Zf JgyQrrEf0U56GKVazlMn/GGG6BtLg3Y0VCwjM6M7Y3utj4KPiKrNnaAwiH8NCZYAA9R7a5QZ273h LhtMKzn1VIgZ88agFrGByQSZVNJFLzlRSXqb9leEkI0/3Pi2jlMKe/6AWCzy0GbDOAHFAYX+t8CG 8qpvzN9c26bZKsnEh+EG4yUkAKd81rEnc2mbX5p40jwX150UscfuIEkldw2B8f4n6KBYQL5Fcau2 62fKvbDi0AOXlqBP92qMrLAyuwp/ZufkEqKLHKjJFsUbWP2/SXvDfA7Zrcfvvf2tPZ4jHiI9Cd1h 5rLB13BKnMSiwm/X3d6sxF9FtRoRwFlB7N3ll3xs37Ts9uchIVT/o5bqj1m+wH9eExj0h427z9As n2n8RRgoFStdX9KJnjM2nkP1byMYMgQh3EWgsMdjsM925I45cnpyvAHGU42fcM5Jk1WdpLH9hMjv 9P7PzwR+SVq3W2orE8yL2/fmjz7Wpp3YWnQSU6AhS1IayTefaJWTIFaV2fuHCdduobczKC71+Fkg El9AeJzvV5+a+xYmZzmN2SsD8QteiReKUALl8IaleHBexoVmUakOjmWSHQsPWbWZtYh1aVYS5zDx iBk4KkOd/k9K2Taly5Y90KmaxihYh0Mxq8tCMaYPZdZ9rtu82xsUBUMU05XG3MaD+SIhPVIL46// e7TnqzCKHDhZTUKiWYJgc+S3QxTpQBSsjDppeHVFH4xQ9oNOlFGCQmxiKPsQgpEAxl6B9tCImfGs WwQxR26EfV7UDibKL2QowlhR8wI4XAxIgFqnRWwgB81ts877ZU1Jj2paQoJmVjnAWAUIqZvmDUfJ qtkSZTCYRDnHSftqlvJvgk0jNLETpPJhgtEjM7v5h3t7X4jdloRCZcGfL/z2Bec8SZ5R8ANd+hIo ZJtBnZtv6Ho4eWUB3fK3FfD+o1WgUAYJDZj9gfJ707TUsPExBgmXPHYUuAR0iiVlEmgRpkA9caap OfNuSKsineEaBdxuyY2hYPaK/Om/XjRPMQbnPBdwKyynZZaQdD3TJymfvmScsFheJOzYaaQ0iDXr rz6N4c5RQm/WyJQUqW8Q/gHbcRFlpvLOWrqXvsE02KZfyPEYPwtfsYx4UiO3LwaO8de+Ff/d3LHz kK0VoDuHVIrXf30WKhJXd4n6AxtkvwudRLRi2twaC3znsz8EQWmPN/pacv7wKxxY3AtHzUHTLiE1 HOn1nxqOIMKyEqcZLCnJw+KT4EjiqHYZdfO6CjFle1Cwr8O2Lta/WdSjE40B0A6sdQklEcVzMGId txTZbkrj++20ldiHRkibmgL6EpFpaCnRz8G17Ej9VmvTUj7jw4uFHIVkgyddFAF+tvf4ZnmD/Nv7 dJFu1qmQNRdv2HCpoQ7IjwUJMby91XREPzRvgCrcd9/w53HDCx2liphKwupgMyhibo65mH9enaln nK3+cMwZH1HJ0v85gx9JLba+hylXAyejPKQrVi9gIyRKO9H4v20W36LEvuXLi8cl1RfMp3ABxTlL yNYyOzhrSsib0MsubWv680L5VDWgdEfxyCq1oGBBcIuL+w0kqNU+tKp2XrT7RD8l6t1sqlh3bvNL dXSBwvz9eAGa/svtZ3ghzBZeg0ih1xiXMZO3SofEaigJiMlaTnRd1UWh5TgH8vjzidtg1xOKMdkj 43JfH15jFFAvKu8LYyil+miD/CXe59oCAQgYGyAuB4vuvS+nL+R4FaJ2xSsyod/lP9OFSFbTGA3C raH7IQ0TgzPVkW9HrRMZREh+sRLeeBzpmLHSBr0HslfkXYnbMC4QmxWw7u+SgHLSUluPx9hnUVaw r1umR/UOZf88G74oSNXqZtU9iLznSHALDLSx8i7k0JngsMP2adFAGylhus8b+qwGfJZpv2/tDUBW 1vEuHXphtt6WFVR5KOY8R7tpQsbrwnBqq7bNH90tF2XKlX1dulO9HVYF7X1oYYcPpwNnY6CeK6H/ NnFMyCyq4LcmcXskM9+obksEyJ+Pkzw+OQf4UWPlcBmdnZzrj9o/woYPACViIMp+GWWTH1c5cZUL 56opOGBm+WA+2StD0DIeACitkOZrnfEeRn1U/+myG2W09KfF34Hbvs/U/JOxesy+WDZRUQ+QdjII 5IKIV2bXyRlaPb44ZOL54wrksGetHtZtI+Ccdjk05wyNiMWLx4sOJzTfo7SeaggpbVZpiQ6YDxpq CsLa8THeW/eOHSLD+4iKBQVlFcfH726W4ULT4hwKcnd/h/5uueJzoUOIQTQtrolgtvMaF7S6Gkna Y4Ke3WfTY34f/Dg7AFK4rurl6L9eZfKfPUdKSQsNPJ1WNrkM7vCJhcewNDvWiqDaF6ptrYTBASI5 MNb3kHwCxEMmjdzznIWy0b2y+1V518ftsil2Ki14wzUeNEo98NO+wm0QBtAh03V4Wqz/kE2EHNlL Rl0/5Z+FKZwaPidTsCO6yUQmJrpPoWdiemuKFDL3XGttm48Pv8jIgiOfwkL30ntC7O2PZBubdcsm 9F246lfr7z8BhifCbCETi4jEIhB4uQS9C7d9nQZueaEM8GICxo0Zo2NVUTVChHe62JoAsCmxlbJa wZQIG18iQGzK0yQHym9sX1BA1GQL/81NFgBJaM8G2pvEPLoa5NCY0SR9fyrXRveW2LnKtpSGUirs D1H8mW4JRDVyHextL81Y5WyKn0Epmm+9R/B5XeND4w4Yc4EcQAd7yDWuTgmB3OHHl8F+qUSEiyWy HsXqiA9b7WJfYyjoxJvWLTTXJkmadcPiMn1AioradKS4wEqopRpLHpgL63FiJM5AukOoNjjXJpW4 qMC24SiAhzPvovMQkA4gHfK3o55ZGoSKdlWjrVR1u2jQEUCJ44HuSNYJrcsS0iuixkSskF8C/BS1 TiP2uLjzEDCilLr6//gGYSFpYFIxdYsYfSG3JMbYeMESyWqx0YK3hIJH7ZQVw4mBDSJZu8p+0dX2 1zxfYdvgRzoxhDmuX/yFIUI2s5mIatjWR3q8i3j0248/28Ntreleu63XXl+TKjtAOLglWDJ2bvfm rz0oL5vNZ+Hu5x69GdVmWnbqt+29+qaF0LRq0ZvCZSEgji+C5ejc+zzPksnecAtKDJEdMBGL18Fa I/RHsUClpjv94Henfup3UiA/VuQ2+5yHSwSvAHvsamxlQU8sbzorvfhrzmRQo2khYzKCBk1Ikfgv qkIcm/wnVY+nHhpk2N/ZKtDk+0JPyXfpcXVaD1ChPDfv8pIpxIpznkrutfPNG/pOtNrpc9LS7Z95 ZBZ1ToWR8LXgS2nT0dVhybqdRrXyckUHbeqog7hWCGLTrG0Oxp3lDy/Al2cUtTu8wJv0nwvMWyK9 ukmhcMO9Xi4w289Ypc6c+/ES0UqVYGcyGQ1qgnJw2CwsrHAoIE5Yis3QD02+1UlJASIpHIH8oh34 ifEac1+05Vf0DNFH4ayPYqbhXefsd8vFigXVl4yRMoJBi7pTQfHGRscvwStkrYDtZPbQ4hPYiirY KdnRxfkYcDnyCmp++9lmMcEzfszwzj1FtMsJmpbCksBex3F51cd+2yTgxo4vSl11fwrPzpn5/BTc HaGqj+z1VBiBLDfzJ6jTuck42Gy0Wfl8mgjavhBqda0g+jamgq/E2HBdQBWQcYTaqhnooQNfGSqs TQZEpQgelCxBwnPcnKgw8LGqTvEXRVvDfigzdp0eERJRSI42J9gX7zcELlJ8WvyMEGyoEiau4qsF OecXBN932unSmuKJN1b05kJgwZVoAHQ8G47OaLGvj+HiAEwnFlG3cQKSef96almAfm0icIEkA6IR 5JONmisa45T+Rv9VmicmEQoH8jFU7+25n/I+0V1Qy8ok8IT1BavLDfe1qM9eJ5i+SEmeczuSdyxg 62yLY5xFO+c5XuDWW2dHmoSsJ2IHI/9LJnn9dwq1YRmm2KYug8iBstRJUR8dZXkZ8HzxVtpUQKwX ve64mFtCFG5wRAQ7IjVEZMECsjp0lVCQInm/V8O1pd0vebMo4Y9A7XMrOFPtKkyJ3Fpfs6RFCACU TXHGo9IARDpMHgeAU/167pPDpbYZ+3HLmueCniFJZFGK7Rz73Kp5fMKvWNqtdQjH9iGOFjC+A21R Aufkh04WqHaBsaxNdDDycbFkN3ZsK6sibo1hGaqlIZL57oH0CS1h1DkRyuh92XcExHbjPQwtgUzf rZg5E/MVeCEDfOIwN140VJZynw0JG1ndfAGFdLGxhVEetMv11yvNTf24k3rchSe1KH+Bc8fj9vJ9 Ktq5jw08cJk3nG8HeBWRCUXOWY8b5V05f6qWcB6NNVfVHXmvRE8ay6gdvvL/JldShB+OBFbujwpW ScfHez3rP5XF3NaZozdWze3emt3QHaqShTbuy4HWdxffs5ndXBvnLpaI/3qkSIyB7LOxGldFYz+c awEmaV9Kfv7PABrNl3TvGdGt8C7C6Q7X286Y8hp2gsBjLoKf7hy3VWOCv27BsdX4uk729ZwJFkzY ICL+V3bYRvwn/FObMmO5B/vIS2Hank7vDyonMOoUkyX3UjyESlCF+y9cPWkYht940U8E0i5221ry d+xk/BjDDR0dMtGkXiT8ewz3L2cd543cr5kYVEcc523F6HvDJ5MvbwIPNWrEu9WtlhWSOzKRJy1F AEgv8C8P+H+HL43YMXuN0F7GkSCx74UL2N61jTg2/XRVI7dSzBA81d0i3SHlGQ7xfuXcNtebsfU2 2mRWt/UVqFXGvhVL3vGvwVxpVN9WE9xmHVpylcsCVL0NwHp5E8Z9pkUdBVf7BSjG+7KCyNaEGRkx Yt1lx6WlO3BEE3a8BdCxL+nuMXDKjI2xentsWkNQSI0z7JpDlQEuKX+g41puPoAlRjAbWN0y7xXB G0s51JjkKVNTaGXdUhUMu+Tq3VBGsxM3zMPRcoWFeV86I6Qr1gA8ufJqOaN9h5BerhmYGcKG6Vem dYoycM49G/50Hq774p3CDEtBYe2K3CbP5MHw4IsO82VKOZpYcYGDQu8Cxciv83hSvK/vtK7VcI7D Pql6X/B18ytutX34O64/+yEneIJ7vcit/MJSE5cP4QwqwOL2WaRkWPUDJA5afKwyQdEq9vSWhfDW UkUEZzz9+vD7wBd+75wP+Jtu79MqyevuwIm8YpHy/af6qfBbcUZT7zzmJXIsvJ3az5cBkE6x5UyX 2tjiIj9/3ECfaDBXbBc5NUxRZc8nfYHmp4frQALaaMCEilo3Wi7AdZzB6aPRCUc1Cvgtj3gPJU30 OfEsfXaeXonVwxve91rdF/EHNRa576HPJmXps9FgnUBDfUKF5beFtUDrmchnUrwYbw2jW3wyjb9m 1TQDooIMqSwK8Ab1rFDAFzdVf2E2MAgPW7pcT5SWn4nDWQxg79VMtPKz849M3RszoufY9TIzTRcb acpM2Gu7Mh/8YuujJY88M4RVrdNstF9xlw4rvAPJTqy4mcHp+1JqYXPkJYjf4dYlcU0/4J8UvwVB L1ozlYKn1CAibr4vmyKBDdURZRlbgn1gs1SVsQl44HrBnu+mm3Ewsy431Z6iQWYHbzFh/SU0k5Wz hVbT3AA/XeREvjvF+dpi41AfXrvm8L8bZNhHO01OaI8zh3DxE/IC/avSCLi23PEMIXSBlNRLSM2v 1RwAUfkytpjp/926kJedrkbTnKKyuzIvsqh/XXwYd2dw07yxGcnYbS2YXsVwqRzYj+TTlyROVjqY uGusSiXS8wd6QPgS5ji5NSwXjZ3Hf4QAZUc6Sj9un4+Zk+5JciatTNXYYbI68D6zGKFlSPIjthe3 XzyuY5XInZCeEMx7MFWvBWVB61E43dIKxF4t77MqluK1sQiezYzmrQkaL43qSlkMi1TvspzyDMca jH0X28pVFR3Ue3IogR0CTyOV86kokeI+bP86mGOMQX2t+HmPBH0Q+CwPho12XFkmMM4J0q8ohJUx DaJJZuTZxRFkPsRaj0L5eL7wctEODmNzLuYwHhd/Mg+vXh8kvXmJKdDoXwhl8NJvsZF6plTHzhjp NJjlbOe804OYeaomUZBtTlgYjVqqNZv2vu2QW3d11HnrUgYXBibZ0xyHAzb1eg7+Vw58dNYTwfpO KJJufJaA0lc9sOxvJjXfWXOJWG/KVdxdQBGnZylYpD2335wzNDFqKWveslIs+JC22BeS34E18squ 540iTAe5+xW9RwT0IHHLB1m4pCXp0jZ+bLhrYU34LVQqrlCTj4nEgxvZHY7zdAZozo/fgCgdXwyD Ciu0KEL2zvZ/JxRLDFuLQ5Hkia9b6MVvLs821DElJDLPiCVWvkNpbQujmSFT71x88G0q/Z315JL1 dBtsa5W4t1SotR/7259WK5PpaGrpOVLb1cnJ7A8KfWdJR5lZzc2Dd3nqKpsCV6EsIgYqWcvjNa++ dM13Q7KXTiROc4nanlc4M12/mSrcTaRmoRNVGT1lBPpdo7Qy38EGl2YvMLsoPFYpiJ3V+eT0giaF 5t7Sff9RUdVbXgNeF0e5n7gFMOzCQ7IqSmGkn2KWNqtT6gbzw0tvi1m8sisN4Q3PEoL9NTf/pbrh APRnXncdafR0MNPY8IUuF9+4b0CHUN5KhMsXy3PYJ+ZRrb4+Oro53YWr+OBA13hA5DWyHiZLS/gJ sDzBgIvrnEaEJY0JE5dp2VrOZum9LvKJHDn476VCshQ+DbiJdOlA3rutFDq6sMrIm1Q50NwFnPen mEpPXeEDP3FhMCFeiGcxIGqAi0WTUq4IuSwlAGRwfni+QaTTJFmPMNmr60PUixNgNwTSpROwa1gJ Qkiwr8f7IHkPWv5veqxl6gmuduNIElDvz4Tr5Z+cABaXGVtvr0VruYobwYwrwWq6Ye2OBkKPQxW3 /hdP1HQg641rph1DyDgW1WKCFDfE90W7aMsInLYYmroFoWlCxdk7tWRvfVNwfXy5EYSaePpdO7PN hFNajaUOTfF47ST3nUmzVvVua+PLQf8s7mIM2oa6jbcz6fcy74bc1chYtEsUHAVczIZisB1bmerA nvM6q2suAVTS35k2T3Tu2J0F7XrVwyA7dCGnLM/nWCvHL/xXhgzu7CyoGgVfl2Pt6DCYqx2j7qB2 b6ZkUeTRYNm7IJ8/0yPopj4IV3mP1Ik3GhyTptteUD1p0N4P0pou1NKt86KAX3uhke1j5+n4gI+I 3NgfDb0yJ98VEQNGdkf1FScqCab0IlrXMG+QNjriBTAqNv8y5HbLrw8Qp3Wa9tNLc0cW9NWg6Nxl 7PdNoTbZUagWDNCkJ3aeVNwIw3HIaYbCfK7sy9RkPQN5t/ZXBvUkShnK5KNUgZLpdl+AlgNLUqSx 4qkR/k0d/xPMbPXwP9ary95cDiejmaLxrNuofbBwJieLzVALg/QLoH4NYO95z9vdqI6+gn95kg+C /qG0PzrK2qwKorVTA42uNNMuRAa9F/eJlJ7i8CU9DK8aUD3n5HEFFTeqkCytqbkcPhO/1FL3FAwg wWXeJOuZPqnaxIXwUrxmV362LbrkCq2jVAzMV6zJ427lxdrg/pFg/oub9EJMXsXGEcdJ6jakwz01 PVP0FPKdgT9Qv7UFG3berkGM8LyXhnLeNUz6q29nvp2y/YmFEbcBARl7DKbiOQzgzOlJRo74u26q 4iLbI89GPA1N/DrkBmoyu9q5ZhghODy2g6P4U95nReWwKH3qb/aSIqFtZSiMfvqfGT8hDvN9B/df AtM7QHiBZnmvpdB/CIfMFN6j5yI1m/umVTapO+H9ZlGoCqh4OPJIaHPqXQF7NyOvXQLNngbNjPYb khUcxRu5QG+3rBKWySvfrnzuw+6YLPn5tZ6VjA5FIQS/dkcQYCXvzDIHrCv+MtYGAiR/GEannLG8 bpCcGy3JZxxGFbYMfZphz/ihX12SiXYtd9JZ2BgL7XRD5TP4srw6+zhFb/RGIHmVsR2JsNDBnkHh yUZATd+twOwKXQllW18210i4xTfVX0caZn62YsdKBKscfwUFufb7qZ/MKOETgJGjoP+c5QmqQabH nPdfR/WK3YStlXNio911i/ZANPjXQt8PQuOr+NkKlTUJxm/bNBlwtKuoFzMp5KtIfM+EDln3+SdE FT7vyK0QUGrOINlRYT+fhEgbYywHjYu50dAyZbZIJlWDtdDENRden09u2ll5pZaMqUI70KNasTqU aXhkqX4SRMaiqtwPHoqPycLRW9boT8UIWdzcFr+BpTdJLIBRIPBAlqe57rDvkE3zlUTH4mTRrBOr c7b/FcwsCuf6rluh97n3HZG/q93FDaCqa0OqFQDNgkAhn7OwifpEOdk8n501b1UVE1yplvJnf9BC iTqIcxLOpWBG5vz0TMa5ZJM8/f4g2MhRD9xgbRT0sD8XSH8xMfiMWEhcJoydjha+0RjV/v2AxLXW fgbV2oSb0ktiV7IygrF1El9nfCN+dHaH2i/Gs2GQWsdfB/KrQriRZfpoQXzcLeGc1KfEPdLBRfjl GviVMBtBH6sgs3ZgbM/faWLSeh527kA5MJmBtr95k3TVeECx7Djo8LNOKlOCUmPrM9HNkyGtMYHR EP7AuA26x7xMrFnQIw7DjOp2Ujx4OQW4useD4bh5PzCapHz6Wi8Gx2WHyKii80mxpBb4za8/Jcjg OA0Gikvt1n8prKN8WFLn5OhOhIBw4uyEVlOiJG8i99DeKdktAL/WVOlFmbIk4xvV47+oUKf8jsxK kjv1E5FEUJ818eYeWy6GbtMaqlXrEqQOmOG+4EGKybTKkSVOthyBZ4IFgHIwXnqxhpRiStuzPk9f JjpiGLKmzyDZFRnF/RdqCVpZidIblDYFZ6XCgylj/x0Utov71eH8xweLZRJBwgRQHJTiDQc63vTJ rrPvpZuyizmJL1xe8Wjp6V9/FV8Verulazb4ds4+DWvHOx3Z2OUSeZd6Xlma8E6Z4NuJ3uPe1wSy gmq3BVs16LmAZP+Sl46jwIHvg9AGhhuQn8yPBisoCSX5MpH71xgG2BiRUUxPmbB+Niw/VekVup0f YFhF+X20EDrDMvFDjTsXjhZLQ51ivYshaG5AHCu6dbW84ttAEN5tx/lvqISs0VSqjGhoWOxUl5gG OEbSqkXc1I6XXHpLZmra1/WuxdoZcEhpnVUnMFmG3Z3pD+d5aIlNB9hMHlpFt9cQdBCkOrHH/EzH 4+PfqtdYW52Hf6BC/UPvp2hgYCoBBBF82V7Oxt3C69ZCFAQvv0D2mHoi9nGe1qQ15OHJUaQyzNGI 2q3191PWl8ti5GAgL1lyFj5TO+3BtpSB0f90kkryWoMBTg3DIh/YZmXppSOlkRqA+S5TKOHISGoS lVd9jOKgg7j0LWr1tnDJXT4BH3McUvyjzn8YnI8o6U/G2GqCOi2K93qkAn0T260bNkpAkhCh9j+O z00CvYF3jAEVfT9ng3SyiQSMEOEiuXbxUXa7GKu9GE+FJ8kBVItlc1RGXdf6AITwtMT1s7bCfjss iMt7qfFE7DuRdgkkgyfxzMT+4HQba1krwiYF1U39hSqcExRET24m4SA+ikYt6z+mbtquPCl1+h1U N/GBL/l4yXHCKCPcy/HJZcwPfklNJv76J1ZG3mHeB4ycP+7tBEnpTkPGteOoRMt5+K63m5L52BCo 8OBU3O2mD1W8bmCL9JM0kPO8uFmEjJ2fZKUEfliNOWjbYBZQY8hwal/AKNdJ52fATayZFHcABlHT /EcC8IiXSqlMYkb6X/ffaMhlwK8vX3HEfDb1n8pgPenKFcNQvG+MfYlIYtBrpAYCeCqvNp7Q+1mn xR2qLEFdFWrH1LtauEaiy8EoZgmTwDFL9qY+KjgjY4LTrG7SnBbWwQHMIvHPDrOiowBTTFjzS/gH oWaeU43Lq/URsosyUsu0u+isGOIMz3/myr0gLX1jtEnDeKBh8+7kn4f2edsJ6JRxTk5bEpbz+GFq sknI1opMsEm3HSJ3T9BgMkMSjhcv8AU6XF32phhAN7i3F4jXmOiwr1ZckUOs/xh72ErML+cVu39L sjzjAF4MEYWl1OCzcqSKPax6ff+PcJ9rTiFgeHU3CvgCUp/dS3zHvpOzYF8H5wU+dR1BpCXjhnrt PpCXeWE3xswEbx5KfxbftQpyC421gPsuwnnUP2dUUnd4bhPCpFPzqNFutb7JPoLMMpv6ahU9gyci POo9bpjbXZSpM9rVzxX01ygcD3gWSzQx8uoOQrqUaUc61NBvmECuu2+3oQITliT7no4gf/lCnj+u B3VBoe2gWCGBxJtFlthP5kmnD+UycOZ2BAvY7pCvMIJD94wMCryhn0N67I6uCvSme0yOWpv83vDO C8TXnQ3Suk2QRf3VnOSMb3y+RWXv+QPJhQlMgNTZ52vN74F7IlCzcK07it7R/KnHRpdnPNUFdFX7 MP7egJzJ3arVC4UZkL2VFjQ0rDjNaibUpc8yN4eR5/oQJugvctLngy8N5WDxjdxd6gYs1EAGCvzp uRQwqpcJKXiOc1ZUS9Fcb38K0/vgezCAQxGTBg9KuFGjQoDLD7Dcgi3iay7YMy3vnGLMRebAADtE i1s4I58hzyjvSXEkORB1vQnXcZ3RLH4WMh4K4OJ5UG7cHV1tnn16Qp+YhM6DXG9dx9lfO8fDze7p Npvc3kD92KUNQ34c28VjZZ3kLN+dgV1UlWDInEkANOkuEvKHAoR/QbAhqxyNWmY5Yvo7pjNHPz3i V288P98mMmoIkvPGfzKY3yNTDEqg31vLCCg/TjiR8ncHmZvK2lAotKRc9MzXeH0RF5o71s6iiNYE 6QfFUz1tyR5gDc0OkLgc5TCyPACcZarKmDzccfPibZijae68RNcoPiypo96OX72jImyJBQYqokRx TfkJBsGfA7uSxeHGSJp5qx2h0TK+ASMwKZf9geMX3wWTEamCSntm7Oc+xSgU0dBuIrdpYIpuU6ci RftAfLOHsGumgJPq3qiBCAIzw0J0v+5+ApyC8aI6KJ/hRGr1+Fqn7TVvum+YrP3WUU5c4nP5mUfT hOlQ9eu/WgXiePku3IvSbidZ6OGtVzGUQz0a54xIzx+JIJgiI+/McgH3TQ0afLjee/IYX7E1kxnu b6eZw1tRLAQVmRuK0MJhYE/Bx/kgJ5uaXmf3gyMeog41FcwjP6K7LrrikBSrbexJeLT7S/JhH+Nt WCilEiH95ItDp4B+1JO4mIOWqFzqaaav3K++4RD/YidaBrlHUC9Ossrm2siwW3Hy7MZ2ZdwzAtXQ 3NT5M5XhlEiqvXoZwaEOFrYMq0NOTuB8xAd6nzHHnxRBD9p0OCs/NVVCBztH7SY8hYDLZgyuGdk/ HnYNneENKYVM88vEE66Ygxinb4Lr4iKmiikUZsf/lLa2q1bjWeYWDsnv+Uhhj1vfKTGZkcY4PuQz jfDPGl+GYfEk1019ceeXXvGD8PorVixPaQeqtlqIMJ+6OV6kieyidaxB2kDrBJaa/RpTdZIh6Zdf mMe46+3IcDQAsGKlyaJ17QhKF2ccG9tBjFJ2nfVnGhTidOCm2NCeUPxdlTccof5xXD++lXbCl9fi fIsp5Qahpbs1adtBV0X03zqcPUWJ+9fwM8S6O6Xah74cuizCrnrnN97T2eCkJuoYI12zQXaXo+18 YKU6NIMP2Das0FyevFIuk+/X6oMWP+cQrk/CG7AnmixZI8R4VSMsk49PQqouXW2dp04WTVUg5qWk cI/sO7I4dP6PHHXT6lWQzYUoFp9KHRNABByWzd7vLDcH+YorqdYi5GRVm/HRyDzm6u+vo0jfY4at g5jV+yIG/d1S3dy9K1vxngb//skg64RR/X3XOAV6J3SFzsGLcJbDrPqBS/geIlLD2fkiDZlmXreD auk2OLHGY4xGQLMw8KATCwpejMJE+udXJEAJVjPlJRpu/F34D39e94ixwWJP+kiKoKLs8ptxKu+h kfvbZ0ehPmCBYp+lOsEPSICGH3UNw/jJZ9vtJqZebN8m0KAm6QenZW/f4JW2Vh0E72NJte+XfFnM NGT7TGLqr+y0CahLRckJQJd0FQMLQJJjAn+ODJsFCPRB/ax+3y0eRVyHHd77cjbtRYlqbb8C55MN kABBqB3SGYedvzqmEikcAtM+BzpFn6VLLoqlkC3RUmY8cbA0Ej1lZ4O5pRsDeLcRuRyIulfODpKJ TLZdsSrRhEPUormOHwnEilz0iVYD+BHNEfFLgKzazeY78ryBA96lRaWoo0ETqivpYGBdK65AM4qx fhg3zVokQkWNuk188cnLL2TDu+rYqhzPXURaNTV+F+WYe7r3T37OOM0KV3BNfpF/5nofIgTytmU3 Gsj04VxmDKe3FyC8J21C3SSgXN1IUxQWe8QjLLZV7WDo5idCSA10DV9lXXWRZnytwJzuK4MHxwdD iBWdzkfZGOVQ0DI+btz92Rz9ytVd3zjHrGU1X48/FSxr5bfk76dJ7F/qAFfwcCaoNQYiriPG1kP3 PZc4dDKNH+6LqcljO7OuDbR83I0ohMcDrOI5+noIgG3EXf8IePzjK2niepQnhQgCwIjNOICtuXlf YANw72zb9Mcqi4cs6TdAMj7xENaGfR/B54p14lnmkC4NbAH880Qm1LSVGR9gTxaVPEXiEMJJ+oph TUQdfL9LNMsA5r16GSMNVTGJtOlwNUkQH4iadzF60BmnR8Q2Znr2SD1/tH7aRtvi4P/AGKd44RzC ejlL73oKRAXXBM/aOAdf7d7Jbcvs6X8CZ4JunUYXHxTAPS9tJrvrRjY7UGNDbjx7YqquEYrjkLC5 IKrInyEtNCcgA7kJFcMq1euJgdYu74ZxJBnOgWRtSSX8zHu2lu8QGmb/rfAYxnzIaTP0WZGdcjLp hn7nG5Zo0WGNmvbE3z3DacDf6T0OQIfUaVGOnOJjb2a12TnbGrHCDmV3OCVgB9VEEom3MnNGNwwu MxJhHXV4kJiMJvHHZ92fOXlaQ3FSdG5G2mUUOnnt/0vqCx8cLsIOCwch0vLddaMeGelUCUduhQAO 9iDKMCjbljyYKOxTQ3kJd7/D6E4clKaBMLxrpl65FIzPUoE5v66zy1G4E1hGSdDDLy3XKkYo05uR vgYQRkIr2GVnn6+txmLwO6jCSk+cUIE7f5o0vXvCjnkyIQY6Y9l2qSVNJx1mKaKhSX0YBdIrd5BJ elAGxesoRTK/jr5J2Orab6J7JzzDI9iRiynIyU+5GD7aNJdHwTBER+XDjakKsItyDuNQkKlCYVRA PpGPg08Zp7+xEyq/K52VNqRRp0GZDgZa+16D0Rfn+/t5PrEzGs+Tfa+v1i2jFvOssPbcazpcjh6I D77Ab0Xr+JASR3ZExL6YqoFAQQL1TbcQlKUNYpRfPWVRg1O1zDJ3DAHBkIcKHd1iSjqZadLuiBs2 D5pffiX8SvXCCmOTAmKGxuJlftZwo8BifHq11B5jswBHi/iwmPEQisAkXXgHuIgHNsLknttpJOHL Rs9A8vkwvalvjm7ZsNlUhsbytWfo2RQoLZXKKlgkPWQpZu6ghxIBSjDV8hrBvmqxB1vhP49k2HXY fruC/DH44pZoNP5OCI5a5qb+yi8rESj3nMZmAAx3zNn+ScKeIz1ZyfVlGNuz3zE64j6b8MDfiAja Dcs5ef+2pXYwwjzdyhogDIfl+BVC+DpoBDD0fPzhvseL7mTg+ibh3RytYnP/MqsIW56Xw9euy1/5 AQCt+xkvN3p1lTODa02yPsQa4oYTVzWpESyL1zWmsbXDHUWzFxqmO65a8hlNcusm1tiBmuspmASM +Dfd6XzcH15iDAuLvzsXhN/r6f4U6FtcZnoenzZImMVjK7QKdFK8kyEgS33rvYqm98JUd21gNyzA JPCFyzd1oygD3xjd/wahu0KFYmbY6Opnsi8TEWM2Yh/l2F33mCNv9bTQwIGnnjgeBRQD83nn4zp9 oV7MHh2hrq4uLOUBO9vBM2EbULYbAE5I+778Lk2ho07qdXID048hj0O/r/odqVKhx5d0+jXK4Jen fvO6Pcx+O7PYAQJZSSOLN96bLY2DGWWh8kETBydlugHZm+cWAwZ7iVjeo5RRmvn4LzgWD1DrkBjg br7RqKRxtjs9KvGvUa5TF6XueJB/o/MZjhlEDsn+1x+AycldouxomuP+tQEBp2M3s1GXgY8C3Lk6 p3k727We9eOdh4MOQ7zC/l2qy3SABaaWiiEk8WQtZLwU6K4vbmZETZqZ5BaZ/pbTSQX6UxwtZXOM TxYD5EoZvYgARJzjZPFZg/fADFdVKuCedlRkRWNnrQ6zFiPtvUNJ+Oa/5hXWJ8+oNl2yXnTjlA14 cFzbhjyYDuZUUl9v1nk65vktn5rJro6dci1RBb6c7Mu42DkmS+4kcvfEgsFi103ImGz9/e0OhWDx 6UZmvOgrs4obcyRS3Hdgy7GifqAwTNNudxbi3ieEsNleInlBOkGnPnHzXd4+9FtkY9ULedzr3ijc 9/URz3QbAHJFRm7Wv3EXWcqMArxceXErTnHnEElAKtfiuZRVQCDCctO/9eDAz+/19PzuJwf3JOyg ZTGVdfetF/+dz2js5X615B87+PMB9WXHhW4WexJZrNkRkYQRgh/x9UIAzGhSDkCBIUDGT6RTxu64 MQrkGic1rGncHVn2vyACXVpKFDfeKR1sUGRv7Jt/KbElF1B/PxcZgQcbuve4n7fKXtrcpb4A8e8e qo1QmWmI+t3yHb8iRk7oNpgHo3V61yXDUh9bpvJapMuoWyrXj1mXbjfWM7JM6zoWnJuePhzm4oTD kp57mH1karc/d/mINZ+aT50NdfvJF1ikXFMojGIovQTtp2ucZuh1RyE0lOryx8nRPOcyXW1rI40N EdjCkm7OUcUvqNwhHq3wcbBjDDQnLfRxRLYh40bo9hRqodrR9XN6678039erG9/SxkhKcsL42roO obR2tAfejy2E+J+Lxr1SXJJzzYEI4GLP2FFWbw2+S1Ndd5vjjO3oBwqCjtGysScdjMNF4Rw35iLL L5BA005+08B8R1iBSnmvBT/oO2LyuZXhs3eAsuzWL+y1TczOdIzUr2z/Dss653f/WSj0HEfutt7o kK1ybjgxPoGh//3K5Lz2HEPhb8BPqtCfCrQe5WaMjKTJ+mqiQMrOspQQV2UBpMLoMaGEKRaeLYoF aLGtN9LDCHoxCflRfIjBYh1sih6qe0GJJ/VVze676zF6OKJo5Cq8AdSMMpLmUmIMSHh+QLtDA4E/ 62nEsAjMs9dRFeXnQlqP1mzfhACKniMFy4+2j59XCYwTAYDfdntMtYoEdeVOrEWcm5DxCIBwOHFg ySyq9/9u+lRRKh/tzViht2TJff36RkG5//xNifWjNBfQUhaT0oGqYjDLNU8NjgTkpYG2/FpLPkuJ 54xRtdQFeQEuKfvVP+NKgXPPEXTRyc3LybIT+sEjuUIgjCks4cKFt4VNoGMS1gNT4Kcwxx+qSTj/ h/QRBRzdtkO4mJDFztEWpWiC4FDcgJAZgm9t01qTnpSPityTB7b8Nnn6trOqPqj940WHQyWuiTyD UCBdYW6eibNf2uQK6SjQSWB3tbXvEMnMWi+sTvgByVTNZkVzy8uJETw4YmRkaOzHBayfdpXbkTWU LlUl72MzW2bG1W9S+9ec724E5DeNX/GMcv4dgqgLXur0EPzUv8x6ecEpDNRyu/LolECyxCPjQq23 Oz79nqaLOkdP6zK6rDbQvCXOfbZDnJpYk72ob7fIyi/isbAppPpWBP4uWhHmNR07qX6xr2QAcx/k T47xBBgdce2xPDrv1xd5J4ZbKEY5rZo5ELR1uwtUo37oq4LXyUR/Fxe4ubQUgCGdJCnLGK18CtqQ C5dNO+3LTIfaE3C1VRQgQF9aqYFLplZpipuFo0XXvp1e5QpVKIRvna+ltJIPyJBBcGOPVPq2XZZ6 tdNPUpQbkx9RIslSiuxl9yjKdyuAC0lhwuJgyDEZOX9YxqV1/wTFYrUkQqsKNm7+KPdxLfL5fCVH yY+9qO/tHhPcWOqW39K09mHnGJrIcIYH33HQxKAO3PSqrcSIxMr/6paq/hsio+a5gIQ3bD7vx4Xw 6d3gMQWRzgDVjInAtMLSanMa25ERbIg11BAD8/Hxct5JOkIxtq++FWSiyWnHuFmTjzlagns/UH8x +cGMSrV3zK5QkpAFumzy69KR9pBcc6HQ41ANx6+zc+eowGTMd0G+XNNsc30Fz5TMxuWBUJlO8g74 Bu2ih1qWO1ausQnD/N5Ea0vvJTlfJfjeqwr5QzaSow629Y4/2bwUrC/E1ZnL7SkMLcfgzaBIO/DH eP6j+HO74uEuJ442iEGFjOwneFESswnppSO2gudWI4/1Kh9iJOtSKCfPJRwMUl3oLkxzJHkX1NH3 6cXdTlUPHq8W8qb4g9g/nFL0HSZLNMh3Munuv/Qm/pmIZEe6voqtR3MBAxSBr5qi82S5LRma8bUt 5O5OOHwfCVgahlUdBDycASG19AzqfMLC3GF8huO3Y556UHf7zLrQtPIX29c2FV+B+sNGkBZTe4Mb ZFeoPf/ZSBaO1PYMgftK02XFfs1RX7rhMTiWUD7/mz3MM+vm5n8QHAGgM5C2kV719Xakdx5w1dxr FzscFddWHi/A+jd+/wRa3CDxDQ5IKGv5HD4v+wCcaDR75w1qMfDMBBoGMnwmLPAVVRnnB2u9xUcg J7UKz2LH8zHgnrxQR6c/xjZP0ZUiJ6DlTw5qCUL0RFsdDWr8FLPi2BLIF6VuA7MNO6TUH12A+4NX SRlbEz81YdlZjk5k4bQpvTVg0ZOb+z6YFRlnCI9DD+t6XKvtn7OTsukm+I9NoF4mNkVy8hpPig0f KzWbHIlm6PtCG87QzS9rWLvjJP8F8VsQdzPB7lAA3hUAj2S/eMn5rUcxZDYEINKualtpjbDuUaCy ps3rIJZ2RkyDYBexPdmyOJMvSF2xLi/OT09QPTezpb2sdCB4vR2blQzvN71TPRWEsRDyGQgd2Bzx xSYL3XS6/2pmqmLbPYazzIHl2eKyLyAHecRI5xya/l2cig8oswGdn5xl9PZyr1yUsoZx8c3cCZQ1 rHnYOp919t6R+BEerjbY05KhTiF9DtPCHEw0c/ZaSmWu7aeHbRt3tzHIqPsEDQoeoLtVtjTavFvI eWmYRlBU8P6QufAN9JSlwETQabDLonhRYTu3Bcn+T7Y3rEDLHTZPLN6lcDA97Igbvk9P6gwM8fU1 E4u5culg8tZHy1w+Jlb3krOFQLGC43D+dmw63qFAs2lF292sEXIw0QHd8O6CML/85M1e3LTmqYSN 01cugipVj8lgKFwJU+Iw49ooqMijxQiMtGKh/xnJ/+IqNutT+lpB1x+ywRRwrZ1dRCIFQdryKvlz JGrhY+MC6dfSzcqv47WkZdZcg6lTB+czbjw/wVxCsWuv1/eWdUAtRsKm4ZCIrElnuP6x7LXSVWXn oC7FkgBx6XG8F30iWFw7GTzmol27MtMlj16lH1tqhD++ps297ZZWye3ynrWQNbEctrkbvRrIuMZn 5aPgVzXKqcMByxGvZ0uXJ9IBtArI5AeYLfyJjAIkYhqU/eBDY0Xqe5Z7FNowfaDVHxFVqiujgZdl ZtuGkK5BgK52S8XX9dnCUxEGqnlGlxN0hgqp2cvEMIKQgh4Hw3fGM9BLXbjAQyQax8M8//KjFZa8 rcu1XNAj4OdXNAbWjBnG2fqAuRNDfGZZUT9u+ftN7WzKELUozpCYgxsyKGLaKlFpdq2yxxrIH0aF JzwcJYKrbzY6s+quVRO9iJUCwiXyH4C+KrZz+gK47OJRrxGjis2SWe/2lA5DJOEKtED+tiXteW0z 80Gm+/P8dzwFghjLCsufejuZpWksh5+ZNBJAcOrvnx2NMakHbTcICWMexfd/t1bNg189pGjFOemI GmOu276xUAK4g5Zx82IVNXGcQlNoTYk3ol/iRBIpzfPeyFGeF3BgR8WMJov9fvU3pFD5AT+2LqJW wpATCN0kkKikjkpnCOb4GP+8VkSjQ+i6UKmL0lBsUELLZE1g8eCc9leIqnlhZZ2hfx10upsx47ZX xQJH2rlBk/vtqAG5f9PFi7xPY07E4P2SCLtI1Ry9o6y5CXnfDem/oJ1WeOBoaDWgZ8YQKdGve20g sw7t3Y2767xi41qmacgINcBWxZkdwXYfEq1hNwAAtM+3n2kiCMb/JeEoJEXghqgIKyHWf6LxEDSx /wshGUmdRLXLU2t8zG2iAy5+U1dVHo+1d17mm+lFWlUJz1KFgKNmVOQ4lrF2y2cXOmMbIryB6qfC J6cI77q5ZHA/nQS+B/9bj2jJywGc/FO8oSWjAspuZruDIEYuxqngY0DqhJhsiQGjvB0mm5St9Nzf TIC/T/Rw9EfT9uRRFAj9uUN7u56O3xVCJM3R6p+8Jj3g0+z/ZvKGcPvbdMmGCNNImJQLGWQXPkmC oz16dv2jFXxNlipaccerSVJShPlX+Hug6L11aLZyXHyzbnCW/jpnGR2x0RQsKqixwSfJcdlV6oAN H0P5icSjSjj/ZfHypmvAN0YIPJc/rU6qbCqJQjtZaQsQiQdjRhoV88W/Ia9C8LIQcyNMW71Xu+F2 ZmK1mfjZtyRt8HMLVOz17yAV0GptSXbPuRk6HBZN8YZVzSR7Ym882SmrYBwASHU/sQpyIFLVAMOC LuDCCBRojvzCtFn4rmNmWayqRd1A5sxd17ayCTUEoHPJKsnqsysfvMebmRW2iBDL9YpARY08uBHo Em38n5lqt2CTNGA5t8wRZ4tBQz0umbel8KGugNcHaSLBtOGLKht2xcNQu9uic30FLpY6N/byQim3 23Lqvbn7gOx/6JcVh+9e+1sscAPZs0VjMZ/JQW0PcOsJTJL5T8fL8g+qDYgAJuB5bUFWTEdb+D7E t9/dJWdOlZc/cPca/oVaU7hFuS939l0bIHoIN+KbRwS/kYseVUAGrrgEiNQo+GQq13RCeQh6ZQT9 weWS5AgpjufTwD8E9VCVKJyZfgcbevuJs9tGzw1xvWmY8wLn+BhyPRoDPT0x6kDTMPnLvSPTXxsf tLtukmzprKcvidZyHXHzMeRW89jDnUKxdTNn1cxvqCJVZ/4zZU7o0IY0ZeejPI2v1bWzn9eWdPMk eLHnsEjs99VXAIvjOWFLShZTG1gPc5WsRRa6JxaS2dJslfwvbIjcVjF0ll/1JdN7mGBj5s3Ma9Gd T0GlqJQ0x9/AUnNqSZdcXHmqqLI6Az5907X/ory0tr7as5OqR3jOO9zZdk5T1BrHkNq1QlHFddpX 6ld36zhtAJ3P/igTWyyw+GTgal5JmJ7pw7Wd8OJVHwc9pCzeKOGS/OWjAt8Pha98/ZCScaLF6jIt uGL4nTsryzHIiYjTkJo7RHcJZBXYRvCAi6djRADx+37HwCgRof4IpWZTRDMkyn1pjGg5hkougCLa X6kugZlkYAdy1ZtQ+3DvAjm9ktJW6rPObjRzogzabauqcpF2eLqY3urEIeMHdLiW+69Yh40Kj0D5 CFXrQDQoteleXSHh3mq3DNke+mCIHKz9JmUelUmQD4v1shqpyqjGxsEpd/Bju8JXWYcSMa04vsbt 088f/e7uK1omIuSn9U/XEslveHz5yIYpN+aT182tr7s67ucxSCJ7g9DLYH/2ZkKJfAw/3bhdBWEh UvVMCy5ik4/cOSf7Re0axHHJNH/cpxSKqftj6py77xNUuYLvPcJS+bbYEpEa/NBksWpE3y/EwGwh 9g8FfHhYitmoPha0ahaK7hSn1UZcAofJj/0h5rJwS6t8TEKluCzy6XprJ2te2y8Cd2SAsRCD8iXA AoTO4/nH4cebvHGB0kGHdOgk1giq65bXElvl3xMoNyW6OoUViDZ7xWMAZbMO+9wFq08KnXKMdKTQ o7Li5+4T4mEg1m3qUaWQxmgeFg0IXa1HJZgFRadQSpWwT9Sr75UxJLIvmpTipZ5WJIByb7I43aVr jAcOYJgB5+AJIoaLKpVve+4cVBvMEk1CVDz92Hh3X1s3RAXLAONNz4o3FwnpannyCEGErxkDOvXN bpUtoyXVBsLHHzLq0kZ7/yreWkmkXJUPQ4YkQ7CWanvmY4OaODPyyjzaY5CMB5liu2YP5zZS2/E4 OYig4tDyg+FektOVGTM8spSOL+euFQ/anLjdvv53wJkfZcMuk9Ei7wbJ6vDUHA6XP3bzTuR8bcK5 kfZzELrmYGKEiRrGR+pl3RpFA0lEIi2zCwvrPEuaXphLlCirxNn2YUPvCAdJx4AXe3FuggxfVrKa ecQJTz1jN5E0z/ZdY2hLciM9XxwbJ2zlqfo3OoXbby2k7ZSAxeN6QzLYFpVJi+bPp2N6ZMPTvefM DAso8UUd4bo7ldVvD/0D1Ok43vZfyHhT3q8Ss0Ch+DvHipKCyYDnAqoaIVnkb7aQERiicg5eHoaq eyOa8rb5e8vYPK1pTME+G2qERe0CPP8nt4WwtbhZcGYkdWW0OqZYKmIOOhgdL44olOMNfrlTieTY VbnqeOld+WKgzv2CMBPMGfBpI0XnV3O3wqy9bOi9DOwd1gpH0/NymXO2W6BMW0o8wBl1SqzIVhIJ owvX/7VY9c4yC1q6JiHkbFnNi4X8y5ZlyXJHJt5j5shw/HtFImBNGgxDitG20i7+Fj96qtMmnfLR rtTFUSGGoruoMcolObsHaQF2WgkFVQo7CEqoOwHb9iDNVX3Ry9LItMZ/D6slZrq4GcZ4EwnHW6+P LL0I3ELXQ/4dn0oKF/JxaWQq0/HKE6MlDYcoeLq9hkMxZJtT5U0v2844bj6X2r0ncTYUDvnvkheL r8dBcfOujUKEJXttJrEVafGsY1KySOfH8rDEDAlDdHaXorI1b9abeKSdnDCPktI+3jfNZL+hVE+r 0G75PvhzY4S5Wz8NMPvkntmrvyh0KH+ZFSORDBFcUEVtvuUIYpBrbAnpp9DEeFjKxHRqIfcbgxVj YsVEyN/IV2Hzv9XHQt1ueeDlNa8nCJdd/uTWYphBqt9ODYFOcDvRKQQ+y+ffDMPbYQvSPd2ZugWH U9fQggdvQtI4dpKkqvPmIMxD2KLTeCWYcLdcSbTebk4eWmh1/1fMr38pdn3AETmK+tgef6BS2zdc Fi1mwHPpoc/ag2hFlOvQd1mWrwr4Q3+FeRswkaKeRxTRYbt6/VsVtKLA+wcGCiXYiR0lnjs+4djS enj5hbu0OHZtbq7k3w7ix9YEC+iGwcKy5sLqP7wEUxyqiKGIkfYhZrrxJheIoGNoPSfva1gHSyJt 4VeN1BO9BRgs+FG6CwPM3YYFMPwcsnjGuI1LPnuS49ST9PAGaDPQAoRlFCHXRm1MPfaDlkKpsUbp xVlCe1qAB3YobzZ81DBCBYtE79d3MxyjO4PeRv6cbR1kN1urqp2Xh06LrWsyDOZq8UlEl9x7fDTp 16Oo1Q3mARgmmv4RPM3rJ2NbL9I62l2Is4pY+J2WYLNfzulI/4vKxn1k2F2ZimWhtkR2o9I4OodQ F1O3Ybx3m1SEssccFXIb0qaKi6H1kE0pMmCwhjnHOm+RlxpJfFGHmxbF0syRzaYezMDBaM8ieyaQ 5NsJs3WTSq9LBYX6RtfuLQi1QxtzF1hhCROi/Xny0xQ58wzT+2z1Q+3n99AqPo74R2fUfQc4dNpv G/la2j45V3PWQN0oa195jg2hlExnlZ62/UQ9A0w1ilwONs4MXczd5E5cZ6XM12ECPgBnzxWkiXhw wAmPdC9fer9WsYNG5RQh30YcfMCTvzxQ+kcqw8HASdA+MutZLXCc65h0Lgw7r6jOqCxj67UPArmZ 2yp2lcyoOvlvkOxYmXe8VkHl2RuMLJ24jD+K5MUVt1tmiuw02xmh49BiPXfCtM3aHfr/EIydRLzF lizMX9x/8nRV3Y3FoOFog4siGnYiISEFoTg1ZthDCvnVIYrGYJlIaPGfXOyflG4dgBjj6qhe1cUq mC0JphKnfC5oxoc9w7a0kl1B4MqFEqshbWTSc+GMQfBxjtdHxeavADjHvIM3wLIGOeQHdoV1iFf7 RNx6La8vul6YUb3kcAQ48FkwKRlaFoVVeV59K7VqhKURx9xay176bXHNwJSM5GmkDAtajDeJOXzy H0nF8sKRDj0XMafiGVkPOkx6P7rDv9dNT+kP9HqJXnaRAIudIxczR9hootHITGA/FXdJvCsuUggV bCDj4jwgxytKMY7oE7JveRwtlPICXwjyIUYhOtORd5a4UncvFed16Na5wDUHWgrVwUmgvJ5otb4C MTL7bkktMM/N7ttQJaVRuw/GEuXP2Fr2GLEzz8KVctM5WtZXRy51lgeJBJTgbEyVDmBl97KCUD2f bmlZBli/sBHTNnlwDkigkhlPteih0MvvfNPEXKgaWA1qcHB4zN0N2oGewdF19vhjrnYESL9E6M/9 qzRLn5FUiRyqiH/SD1jRYoFBKWv2ztvg/3x9YGHM+cp+SiHYtyjOVnuc1t7xcs30qGqxTvA8zNZt cF+XeUAWKOhQTUAyG/yos4LOa2/EzqVS1hyr1mrSBPh29tlXeigUHGQgg6ghNHhbwgrOl1jPy8a3 EzYt57f8JVTMN7wTQNTyiwlCUHh89XAbtrXioDfFuvUn9cufk4McAAWVuZqSbQE1vKXStcQjB/CD R5RvhJTo0+gpOXWtRfFVD55CYfaO5EB0dRsw45HApnXZAaIxUhrby9yKoiEnHIDAOwyHQi7hGvQ8 LI2BOCdk8GO2n/Lp6a4k5B7FzhsMeynhV8EVpQYRSXKTsmwpGzvzaLK1gL/3+Kny/oKmWnsTZIpF zUBWRMWlVLu1hCmAJE3gBAzrewce3Nt0JqJOqkJAsXYrs9KTL0KJLAup+R4QSuxrg8A2P4ntEcOj MsvTiboCu3X+1jqbdMrRdzMj0w9IIJB4yoR53njV+lU/TbbZZk5sINeRSePjiWI8hleOMeIyWpPN hZmvP6TcVb9QshYbW42d25ASHp+vxvo81bsoQPrm0FYpUPy9VP77nqHMnS55K5yEyQOuPy70Nlqw 5WMh0YcFaIpg1xi6fMNc6rwjkikvCfB7lPYUXqfBTWljLCQ83wZ27jgHcRMwE7iUVXsMX137ZECl R19U5Y9kcJR1i2AugjMfoJJvmZxIwlunkW4z0N8Gt5iZSRD//uCiXYp8Ze4citfrXdSzkEQ/v6MW 98f4LGnsS/wKrdwI8ipm/ScpOaBAWlc1Awvhx8zQ88B8JOq6oHr52caw2mP+5IfVrW4b64fu3QKd 3hON9ipdf8Tk3tcVsW0woAgedDFTTTvDcIcA/sBbE1Ng+Sjyw2XKs7W1VdrU10Uli603EOBU2lU2 yPi/9pTpFS4k44oLY5ZBhkCAUNVIN3bbM5bhZc0i4djbmiETBupRIpElZlfuKeYSkpaoALMMtq9C hbKkDcc5oWUornZ0VlZBl1sxjpq6BGN1irk+4ClsEwWLhd8e2db7/ruc/YhLC760mLjn/wsassFZ O+Z1JvAqcd0mFqdLM2tcrsGDs5wOvk28psxw9PLDNohI0biCjsToLGcktsPW4qC2QOzLMu37KWPX TbzzFpfrzKAszuYj2Sfjoyy8tLFizLXMqW/wE1qJKgiJZfGPlw43N1VKak1JiZVLwfoqnoTwEzPy Ggdnxa+5s8o0YlJNd0Go3BkKZMwW+awJdU2/rHJycHMknRcdB+9LTpkebxd5Nezt+RiUyKOGE98z ekWmPkR2eOOE1igitag5hsJKOMq9w/UK/emyV9Leb8HDztp2SFBJHT57a9cyk+/kr5KoWUGHwaJs yZWZkH3ZTqeZKbc8MZ9N2Mhc5z72c8UWHKert/E4CkrAPbYZhe6SqkmcYb+ncdNgW+Zf+dzxHQ00 4sN9BdEyFlsWUDHus+660svLnzAhZ3DaPFH75nJ1h+1C8KrQKvbJF9l/saxy1lh8Jd7dMEMXB+vi n1ZSZDZiqRCENbCqhf9WagoPv4JBpYGUAymP3P/IaqmGMKHVmhc+Qe/gHC677fR1Dne2CNJfBIKy YJMfmV6VLSayHHY8I6IJy+MkSlQItxD2I5BMIpYep4Ed7irV+KxRSgL7nCiv4TAHpn2lHImttMN3 GKSdhMbAwdJikEl2Apd8t9SV+ka9YwdqmNmysxiGkc6NuefbWjbZkgT/sIA58FMOftGLtGGjlaJI 3Rz2IiEWG0V7x6JzG1D2W61hQfYGAP82pQFjtLosF2NnLFgIBg8YiZyLPj6H/DAglgHWbBOUu5+T OdAFNfVHkOQVN9vst1VmkT9nMwCFNZNyS5MJNO8cFF6Ft87xauLtw0RqhT4vEpjLJFQVri138jNc A47QVYfhR9fP6Ccuc+JvVo4Hzf6yvvXysI3B9zuJY98rvoepkdRUe/NTwkAGRwAtrNLcGxBPiigD SoOquBlIJ6mwOL+Zdon7GYxRsZU0pWwcCJthPNdLMXHzYVDtJWryhVfaINvdPN9dYhRGvl+CLTGV k68FrHfQMywEKPd64qn/m3HUMxPEqD2ElGhkskseGaGrH9gacf9fvEMxRDjMXnLv/lrTNEJy9nsb ku851lmoCgyD5E6IgVv6HiJPio+dympKGpfmR247pEE6zt6JrlWDLZxWWIylybq7jAsmqngGPR+Q hyQTaQN+wxeEE9metyegHDzZH/dpb1frs52NWO+fRGEzFTZZHfNKumSR3SHZTEC/KrwxcfsbVQ7d EUL/C1zpl3mxkhGh7JqeFN8YUPJU2B35ESGuyrbToQGI9ydCzlrVxlfHORisqhcgya2zZMaPftvV j7b6H7loUTnNzayCfq2gxC0Z4ZQBgzZrM9m2qKcioHoA+mR+U8LQ1+1Nv+x2Rk4jKTKOFIqjniiI pcO3qQ2cRnJ+ycucLP8tbp33xSaVWr1LBq94XD0IUnMSZtcawwRxULCqm53yUoBZxUIFCogZf4jT tsY5zqgCWHdm86nJCiotesX0Itezf9JjKAKW2sN3QzL4VHw8ZaXzzt66Id9KMd6D24a7X3kYcMDC CsNTEaWL/AeBZVDqJqfBCF2rLTyxovQa00mqn3XbUuWX1ybYKAuMpnjAxpifjRq7ZPeE7zSnHOZt 3teRzrNHy5LgEtjbBWWkShhHUNbcIt5eqY9QYfRenTJpJLR5J07FBqGo2QvoohhzSxB+zSU+eaGK XfScaFHk50r6ilApEOeM67eOwoMTiEjlprSKv7JZcLqlagrBGQgpwaRK2dbVmRBFQ450je2VDKyj /XoNt6c1d5hEydSqL++8uQ9hmtC60UyYfrSibh0G4OibyP+6ZvhmpEpirM5CCymtt1vRoIDlDUwr E6jkY+jGM4mqVLgVY64nXo7Plo0EeWCF7ZXz9O1Wi6reB/PaBo/Psom9RzRLTaKZN57l+nTFFpJ9 ArScdfjYzDY4fUXje9cAKF0cfjKLMR1dZC4M4jof/HkUr6teAin2j7qh4qFtHccQDsMRhJcEvvCD Us8x1bA2kMOniPifVOEq4kEZeYvcii8w4IW3JEavYD1pOG9gP8yPyuyDNbeWebaQBTO+sAuI8toD lnSzTi9GTQMOLEeluv+TA+uXFaecQ+rsRgHXhs81ayd5YXRqkOL+IM8klsu6nDGB7ytSBZDfnv/w ZCYZQBYp6OiFybAdrdBlhs8MHH51jvp54o3OdX6j7uaLnhWO8ql0rJ3g7H6cYme5n3s58r71e9we 2L6/gRnBMSliXD0KGdtETHc28lrs6Yo85Yh4tVjiD9vwxpsvnO0H7ACMkBlorFRKzPPoEg4KEz53 1y2HVBZQpdd+DFiajlcpFUni6gmW/87+6Rj5v43lxoQ9aezyYoP06gB4qNDXu+FeO1sfGioJmbI/ wtVvxeFCpuO66bTUvVzJ0mIxLSpeG8DKTSOryiqG6JtsNhdxdgKX2ozy/GYzhqlMftgcV1GT0Y3P Lo14NMG4H5MUI7U/lI3nbzl/a3FSdwjroSSd3UajJAu3q8pNVOViLgSVKDbC5xPyEweUpZsV1xMZ SZyUdsKdTquVvIjkVsuKoLThOgAQSbGZGx9t2fxKjhnfgoFJTwUy/E00d8Wf1cikfxa12jYGvRUN sU/wqACsoZq80HnarXDzrNL7F5YxDl1iEZC5suEflS7A4eJDwzUCQpCbKmDkk0jPcDzCguNb2akN WGUIt8sdAWnnoT2+p/ZVLMnFzqgbcwJAjdHjhUsApmpykGrsTRzV7LbGAJZrBaS9I/aQXh7OXAHI RQWC8gSQR7Wg43uIJb/bornhuK6om1GuedNiHMUI8NIXPfe7bnCbElsQNX9HYbAsj7atpE/70Wnl SQksk/S+cCq2ga/Ih0q+QKWFf+A7j+FPLkCemk234H4TN1iQsp/WFIJ12Qdaqvyd+qAxX9ylxBty c9eYGA2DkPuQ+29yp1zkdWC1wDxVah7YxAy3+rmPNfrr2q2VqmrBUgAIFp8qcLr6BscKQDSabvf7 HwLbapiPbZn1cOd02ZlsH7zJHf+4hGuTH0Zy6vy/4u3VxTNWSrEBHWpd8XpP7ZMfg9C0myCfje5H cFg9WqjYvuWZqazdH9TXQTLlK9VctxrUc4Vw0jc425D3d1fCATPvqf5BA+uBOhpzZd4kCDZVOR5G iQxaYJFxOWkL50m9HUXuID2GRXZPejwMNm5g/QTSUcM5CdDWVNMNJD8svuZlxUHhYVEQ5SLAyFfp 3jmeGpRZ6JMRiGhWFdDiY57yjAd0WEVFXV6gzqNDNUEwsxTsxocTjQ5LM/MN2ohvzM4/65JRiu8K 5RulqVd7rOAhJ7M1ZfcmUYX/8MdgKL+MCkQMXWD+erVMy8oP/ohoNssqW0ZRNVY0gW5hlFwWlUS1 DDY0E9DfUfGHlZSy04S34ZO24MTqiFTNS4GmXk5ub3K9qYchxDIBW1lPcMq2Mm+jBin/czwIaUhA hzeYiUMkNQdtYK16vQf2pIoBrcfaFMuAGaPMcRmM3/sz1eYieOKxrVpz7EIOPDJX/aMaclPP9v4k 771uzGG7HyD/I3dHrYFo/X+lX8q6cGiOy6LrfXxZ1CU/fnE0t0LSev73k1Quid8NdEVKjtSRJ7Fj MmSecHgtnua6pnYjZYNwXqdPz7jy3kClpwkyfbM/cppe6T/6Wgok4cWn4CA89Ny3dNCHLXz8gheJ ZV9h5wu8b4SuUWprVzcfubu960BuDVDb/r6nOgHtLj/q3zfw8zx3h+gQbLPhIGHUF0j5QipabEog XZwP+xVUGbru7ThWMGakTIJF79d9smlswM90XC5bsox3IPFhjMKkR7vF6yInZoz4kMQJjUUHQj4Z e0QjqNI2D/4rGE05pyqeq0LuVzWJRyoQ81fgk07aeyUvMgRHozNTogOQQXIjU3saAkRWrLRZq4U+ q8yGnViepAkUwj6wCpAufXvUj3gk94yT7W27bBerF4hcJ5LwxMxBzNKyZrRPJXFkzIbU3+fk7YkQ 5i2muDoCoWnd9Xxe7Qy66zqqvavxC+iLj4s5L0e2/bc1HELj1WPgidKHB0AyzArPHgZMoUTOz1Wh 09EsLaNJjr82lKknoNbwgmVFmTnaKVbYsw+ICsUWUMyupBksdKhJMQA2htwFHX2AU88HTTzsX9x9 FSawNpbUJOPmPuTQ3QAGsduhFd+jSoVr4rvv4R7H4d58pux3KMLkY5+MJ9xpyF85SDAtDYZx4Jh7 KrW17dq586OrGFPfnO1EzgqdQnGd3MujO4XEhiEtefiZZnQfroDTtHsGcDY/lfKu2sLk+FYxWIRo xTLgI51afQR4nsH62gsDB7sFSudLZ4LD5HGAQqZXS8cOTocR86RZKG2qecvH1p14zEEi7Kfl+ldC 0A6vYyOpNGo2+F+MfU3NONoXe6oz6O/6k3ml+dUeGdtqHUDfanKeQf8GCofk4wzNx/3Ka+ADIktQ IAsOt1MedVv6a7VbghCqSTY92pNWz5EXK+U2VF/MbLlN4cc2nCoTmnDEiY8KurVbvU99ohyaLPd1 Fn/kQlhlne/QqJF60dpkUUBX/6HLnysatKFFolKAwCjFUg3uZ1AAEpAjf+VZUt2+loyqnaXxbTs/ SfADSRRVuWFSc5+aIpHKPTYViIp3fq4YG9Yhb2+EPDLoTN49eF5W8Y+9aYwAsE1Y/MuTeSWShjoa 785WQu03ywPT5fsGhD2NW5PYFMwE1ZfNhSl+ut+Fh8P7KLhKODj6ph/BoYQxROYpJUN6T3HjR7+m 9BcIYGiS5ejup+1a/wP0uc2AS3Pf8CmXpaZm2MwF7we5a7E6Mbm/uWCPh/4ceoQ9mLe9W34lq1Zo XMe4h5dt+MyRzOBHwCSCfoP+lpzVhHPDEdOTJBDqd6qmkNt8cbWdq7qnFX+v1yQJ46UrM8qLyYB7 Vb9D2jVEKx1soT9e43RMqQEIcaTFciWtYY1hm/U+buWc0L2eOKEIr0S95TP7yuJPjyKA1sF7Z0l7 kbyq8YlE//bs4lA7kE4yeM5yKY3bqR6EY7wOn1TFORcS/1ohy1t3AofEbIxr/iBM+cc4dXLd0fnn cEg9j0K5vIxQXkdqZjAYC0Datu2clbVH1fjBls7+owZIwt3p6uAc1+hGkYl1+o6MZMKoEJtjoN6I dEC5burX27uHf2sBwJ59ZwQ6AtXUL65H5bxdNFhGJ+VxB6Sdgzo8zVCSGH96adv8/c2bAG8YjpGI 2o9lJ0oZZAMbMqOsx6hn7t5zuT/RBq6lTmpRriJc+wUWfmdSOjOCWAoE/uirZQYQyZfcTKI2wuwP WJ3c625bvYv10mz1vHaJLOqF+NJit1d6amhAH+5z49C7NniDB3vWVn083neZ2eWWeLU2cMiCwvWC ccxyv6iVpFQ/d964VyrQZbFvRDGBrOI0RneViAwx5ae/xMXTmp5RZ5DBtLJfaVuwjevh/3C1u1Kj GB6V55xlUlclsjKLZAtY7nuUAS+TpCQDSTVBgQ9pDOPNa3ydDOVp4xXAWOQkRdPUQ3l2NK4UQJFs 5xkX7e0D3t/qFmIqKP0zqeGBASmjLnGmDNBYWuPVtT8o4TzsvRkaXm5QooKnoNRJ4HY5hsEVH7cy QFtt6q2m0kSdleF2/rGCsNdOWolWojXGWfapeN2OoV/3Xvr6+VTpmxry0PSV5EmcyMzPe/PcohMK 0V94N2tRd0Yf22y1sM7OEIUjpZBxwfOvTsUFxUjL8/ibfE38gTDvknQzWfOTSwhTXK5+APW+hVkr qEt0oUrFq7xGO8xwQVUo8ti+W0HD38UGa6i5s/EkemtpuNYV7ne+U+QgGhLDYhlCxaExUl5p1F7+ JrjLP4zzv3yzU79R4mbiEHmUN6v0OT7eCCJkSTMYhRf6QczSozuobcE+a8uUWuN8BMdVWO4RpTkf L0NTZn2rdIauR7UO2wUaAjzYBH0iC7tQtopkcHmWBkfaqYMOjRZIlHxd21pIuenciF6u09VgSJ3X n74NcW3rIMNGJPhmzKXeXkdnXuclM3BD7VGvPLPyK7ADZNhKLcZ1/z1+I8o2PN1xRrP9C5+OXYQ8 1KUjltmmVAx1LCoH9xWYk3Z0EpxnzJZId86QecmTOqQ1DxOb5RHXCEAvfETX2WruRSb8K4d+QHSY mDxBljiG5wpkGwl9yDgquFVENDZDslYOIqLN4Z7nopvxACcegbmjewPUgsHawNY/FtSJAYW4JtvT En1ISiL5TXFK0KWrNx4q9ZRfmiKMVc3aeJJVBOWqLSWGs+f6aHEnB9s7IEE4r8MqVYZIkwgJD3HU hjSgNjW9R15oTBeg5a77d0TXhuCP96PMjCVjhYEidlniLdwa5gfWHESuO3qkl5C4lM2toHAYS7hG yKg7jm9gDQ2Y1piTPW5ulmb5w6AHqatRS9bdXyb3stRQ1f84EfGcYQ1vcVQYdwo0R2fhPrJTDZAu iGVYztTfDbkTexmS/P9jD7a3yRR62orCzHmmwGjDuMObdPtHpZlkrWGFz3jQLxg04dfOgk9eEfPC 5LG1I3a5yqupQtii1Onau/rWwl1VzcIVUfvzjjOhiekAOH2UlD3WPdnvlmRFGWhoGyOtUQETPPLm SCRwdrstEJdjFbK4CzakpvtJIcAF0Cp3o1GKMPG7paKFYRSz+6O7dV1D2zTPZMxQde6OPBVLlxoc n1wzViUmlyPh2tBDOQY/Oe4NQZPIF/Thu6OvLvc4RfBPzTGdjMXau75m1FJ9J2DUO+MWwmPEXryl KGussUnyo3MOH9+L0PdxjDYdK+Je/SRyEtmtA2x75tnmLvP/3cnwzWwV0BhJqO+hsdbB6BJYNzpp vWrzVf16a/brDFHq5S5rX804Mx9NltjY7GIySgrwEnf/3O4NlBPM7GSRShmI3kcaiW3/ZUezGuWw BhV9xvmbWs1BEihTKPioGCm1b1IsnsEsxX+8DQ54qn6T34lUyxuOsHE2kknxKJf1h5cQAYQHBG0/ NzWVX9uH6vKZU7f9TNpiDW0ctvL3KbZ5NXSfHKtnaob0vCWGq6RlZex1uczfPbRf90aBjH+RQYZ3 uq93Dk9StQ+j1fVTeBxS/HZ9iCeEHR1bVV5lW16bC15X015CobzqFGVOnAzn7gV40s1mWqWEVmSc mZZVV8iYS3oZC0dB/KDgToRhpm0YvBW7x9rynoIHjEa3uHZj803dKO+OdWtu68ehOLCr1n7Vs4vv sFSBPiJZzf7XdERUunvnQ/ouirG8yukm7qxIbPL3PvyLcpAPK1+63dMTPCfpnhhaww3UqHP87jOI QSgy6AoThRzdEQOTgSym46JbETZ+oCnC1Ea3k5NK9c1rrJZ6vx6uZO/I8JtcnY4ukTd2b5yOEk21 ho24Pmupd91G6n57CV40ctjNO/JxLYzn/fZ20UZNaJ5MKQ55cenI0wcwSlDyMCOoh9qZL9YEQwUk y+dgT806gTj6zEEXn3LxqTGYSG8fnDqUHVP+RYh1ty1klqiDFIDgAjr/FViSXyKmxdr9Hn7Xwr5s J/CEJEHM06YwrR+CbJeJs1JOoWQ2ZdEZquVx2uKj7bXQCJIGGwkkaudHE5W79w2FwBILrWUn5Y2M DN/QV8ITQjkfVzYhU2WQAwXy8yned2HB409L+6Ew21SlnyZb+F1QBJXP8+3RHg7uZSMa9rAsTLWy cjb/h48k37vqNsP5JuWtxclHwh0H8bkjr0llVG8Mq3pE6IMhpiSi92TxQec3aGv/xoRdGAPGo7pY qoCdpSiDweoBRcLZZNE+XTbaPyc0kXy6BdLefawq+kZ4AMUFv0YbBRQU/bzaVknrYDF+TMrriLaE h8IwDGHmyQNIe/L5Hb/BJKME+XA8Ye8M6F6QpGOUKpozczHxizpZ0PbPk+MQvdUEYH73Uu9PXz3t OgBJti5HdZ+OUTJQ21rx95IWop/aEQPQJmmU2X5chWkbuOVt5eCWI/Tj0HC6CK5RnIbFP93OB6uH N5vBRuDIXzihlDfKNN0I1AZHNf9I98k5PZ31lg6qd/i7CfBJ8Iqbeg27cSBOzZ4+FH+MvW9XP09p /FonErU0GT/kW4bsoYTQjCc7bMgGVPbr7P4CWY9Fbu41UEC8TDDA0GQ3N9Mbj/EA+H6yPw0qtgUQ tYDaKASjO1wN5Ev3zLTqyQX33bmcu/HxAOCekAdqhAkqW4qFnjEKvsKiohPxdwDOyEaQeeQloxSV 7HcT94K6j9iIsURbG4KtMLaYemT7hgCKru081TkRKpIZusC+sV1KX8DVR542E8sapHyq/ipTcTJ+ 9nSZdVsnI+N+LYl/nliCQJG+qncb+3Qo8X75oVC3Bm7BGjJLl3E2SeyA7oYl7C8buDzmVU890Cf/ GK87trpGNGAljwUa7gNwIqUimWadrzxJTJdBUxVuNoY9mQMmyPmAma9jhUP8JZCGAsU+AW7tByb1 bMf8nnYn5Rr/Kauo5cst9+1awWoV9clKHE77TugV1SyZbyHYN38tagZqXcMqMLIhiN5Km9myifM0 rkrQre+kwo2TIt3GVIoPO20c3ZJ0smmYgH+wZc4rE4yF1XFNR6Oy74ul1TfIVDUOS3BDm7zGYJao lKVLRV98oOr21Lf7Pvp+BNo7xGzefemTivSoeNL6CJFf1Zg3PiMDTTj3JcLyreJnIGC/1KR/4k06 C2KsyXr/hXladdnE+0EA68XdNyKNhtn9n7128/fskFMLwlASq1tI7Fvv7kc/rRmyw1vvP6Y7j9x1 5WBKOcqrcj9f2ErPBJ5Xe2hRrHgoYihjWsyNYjKQcOOVhrfjazmSPt28jrtUu2fWZX4wSXZRkyVT 8Y/uww6SfzB8Vr0hrGk+8HaLGyzMgudZTGDb03tho2+6dxv9vHCJ7v332VXeQhdet9Tnyaka5Fua 1PIMYdm4RS9l7Yrhu9Yik6Hv23oTTrcNjjtxMRz6umSS9Ppndb1bm15mKVGi21LvXXchprlGgNMu t+pa7BtwCxYziIxWkbUcwb8g86QY1HgNScVaNs8EOmJQTmYAvB1RSBhsvmjjfdTGKhTQPT1e9OTQ QApQLaUBIah3aLPggYoExWSK6bx4wLkcbMxNzGKp10hcjStpvRftgfv+XVxhr4CpibTH/HlwT2aD Yv9rEdczmv/nv9I+uBqQwP8BIOcKi5xiePw6fOPf9RhI/y5+KUZmtITQS0hJUVeoTJK2JsUvV9Rg CjyfeZrtZlctzXlwLJ3mQSIERL5EO/vOMEwyiu5mnlaJfyL0VIlLL2zj8YXsyOn/XwkT1hL+SLiM 41jbYtTwOHuPEeXErMUW8hMA5yKQDCypLOl+ZF3oSN1qnCJDc0W8TY0ETW7s2LwN+1e19hT7JFYj 8+cRIWV06wgIm1sybO5jrKJBMRN2nBHWxWPTY6gUyj+ewMXB9tdzS+E4RmiRxH5G97xm4foVqT0m vEsoXXdt8DqBiiEr+46K/35ogWkZoub+iJmsn/uwhpL+yPouafRHRcfV6Ht+YWoWBucci0VL97LY I9j6ItQvSj1OmdF3yseEgKQWFVw3NVYll/9iu6u78u3LiilJos9IvvYIveFAr9oWuQsv/mrn+HtX Mogx8HVzB3j3JDKLE3mj8L4geXoAYP6EiFKb9hmsJZMDqhLgQLBoWCFKjAvemL5spZ0XvWyyrdiA A3PQs1xTr5FoDbPLgaBELmxBA61G/vZgiZnBBaN3vX7JAJxNwOJCnDxmiGdACzSR74gL3mVFBJBs U455IiuuwCJwVMbC8rqk8SzLYCEdqSw0h0LuZhMaeQvwv5OV5qrEWP7UbZvNHrHSqWebCz8eBjrT 5KPiW8XocEIAum2x+flxv2Ckd9vCKjGiWUoN2nScXHDXsX2zcvLJn9XvAgdnCXpvLRkt4Mmf5ojZ EIeZh8/wZlBxtR2jDWD6uoG+1HBRKsMw2opnnsnqsHFzG14Hy/9IKDTZLnIO9w1nixlxRlwAwjAH 05548M0de953i4+0Cp7xQuJ7QJ2c0+CQ6J36MfgLerj4SMHtSo4o+0zIHaheCypN7iZZhspHEOK7 YBXfXegj68QPsv0QO53pfbErPkF0MNZeUkjAtBfFP420ZifhqfAyd+IVGDUQ6qycJ/LGMnX0w+J8 rTTKBPmztlkZRpT+9FgWJcU+f/Y2SY4njmvzv2CvtnpNRHym86DsPdktD8LMFHYusZ0EbCh0OHbO eZuPkp42uGcof8CxpMHH/99YyYc7bnqHrP9+sFQXG43bE1fK35/YgZFDMwX2O+3WFP8Id0IPFoQV bnfY94WIZ6cRSEhJjZ8vWWsr50ym/QYTLOCSzI8cxnSB9JVAR3do4aZ2a+dtrjCOuZWh7rIYp4jb FP7mDL+ShrH6giago8DASWFMZlvQpDEM+1H/HAeGjL8N9OdyxYcp8LPPd+jYrPa4T2ZUHhEFnXHK WbImy2jjuKi94Uvass7AtGKxD0aX3xYA15QeNLMET2HxEOwK5PM459xvMAjJf6ssM211HTRnwbcd BrCpGRPAY2cSUIajpcUWLgn71nwBqJpwr9w2gILdBqYrwJPmOXz2wqBa4JgxYzsL8TI+H1XQCpbb KtUn5nF9LTUWNToVfvC7/FVxmJMRgdO7rzJTr3sS6T1Llm3/wHaQEcZYQiT1QjPYH/nt959fZYE0 eYgd1RYoq1kHfU+MI8MC2MaQgfVejXBf2BgZOEWLaVez9lELT0SBqxvurI3D7dtc7kQuSnmPI7Zg 8bvprj4LQr/0BmBvECjzSRMpYOKUih+r5k86/UsXM9/vjpbI9Lvd4dv3Yf169MmZqx5b127nIPqx 4vDd3mqRpi8ryVwBYwMjbUON8j+eRCdUI2HLFifV5ilVBkTh/Q4me1ocEeMi9jcK4AAz6j6aysO5 hQ/3itmvrHpWKFHc2is43hxGtT2uhnEu0RSVXTa67hvwWQUiCWd42F5ay9hUY+2t8seW9w597KsH E2jzks1Y3bF290q6Q7pvDDbAXsqulIXPGAfQ33mW/m9xiDzYKSwYRkrCjRAn+vpKcc+qq4ea3eLb o241ZOwpsXctkShcWGh4l7Mx9rjgD0r+mw9c9IvhjOuvJS6Hcz+oLpCr3B7byvTBkeuvPIZFeTAO +BdCtzIBVa+kUuaBwLYPe/u7hkYW9v5fWpADQXRoyHXWuHglryAXTYTgMpzv2rb/5O83iWm32Vyu rRZ7NUToBJ0hE/gC0IN7VriE5/zcMWmZ+JyHeOsMv/zGgLLIwTU0UVd0zGH1XaKdZMAwCi9O4uC/ GEcWEPxUTVgzHIAokek6Eg0oKhiWr0pIG5x9hKB0xQ2xeK7mxo74dhVelkSZYTIX0Y1dbyCfODzx /d6YX7/J9fqmnqIMjJLUxKAdqgTehHySYzKBymuYfbplTGDBz4eGfMB1wIbc+m/tSnek9q88TEZw 5p9P/V25uX0Zii/pW1oHB8vwekQXHEsV0Vhc3wYmZMnKcfynygYI57gexbKymssfB7KrWZ9s1mDF JICHg+0A3+wm8sGJeyatDsYOBRe2LuZi/LPxPoRoQo6sMKaTjEdWZRMMyllhtYigKoZEgYHrzeii m8junGdXn8zm3ZKRVEvSoj67ohNoO6eQaThN+JupWBQGhg7+7YyVQO5qt1QsZog2G7/dwbq1kLJQ MTexKl5KRSCkfgtkVwKJf5tq0f2d17TehpUtFLsqpVsaia2Ac1T9Sxo/vvLlH1nVnGtQbi7GmQus 2c6478KeJMYItRyN0NsDbgHaj62IKsqLehfnEojZ+Dl0qcg8U0l28gFXxBVm+LKhE5SRL5Huchzi XtUtkOa4le53MOKSgBeuNtDFjmWImWmHFKhrpHcaovB4S0Ni88jeECYsFtweEZVmptaNmKYDjrqE ra5t97+9LmL+UlFMrQFxo7IKFQWnTfccXwY/yCJBtv18Q17oJfsbN8jgjGvbSDMM+k+sSCGfir5C +6pkuQjXSkkzvfDKxHuOE0VICC6xwEYPwVgedikYyPZTfWYxsln2V2Hou4NQdRX36wqs/9U7pSkt NgrW1n527NO/7bpk3mbwDrJbgfUX+nsvRWokpKt9QXUAnTIU9vuubVS8FZvalcKmcqG7KMeickOH RsWwsX5vOposHw14MarYLeOaoQMzwWINMQnAbF44v3lHVyejG1wB1DY5PiQhtMzy9nIx7098Kg/S NsuGCQ69I4hT1JbOJ/nDMtYlGIMSW4zVIxBjF27vc+FJcPUj8D8V9PD6a7+zCCah3HaTvkkHyPRF i4AjIcoHYwpUDstWw5/3MZZsFGjGIU0kG10PkpPe/pEJZPhmq0m/HNDffIh12dDjUiai+E3kOwb5 pA5BKRrOTO6LfcYbxLmoSv/gciNFqUhtFlAqD74u7cUmV462msY7vZUCRCcRPclPZ0Sf/i4nakGf 6j+KvSkjgOo/GqgjzNoFGSo8kZ0q7eJja5uEd1h0q5gA3hjn3pM+olrjwzSPLOYjC00Y6ML3VAC4 Wyu8rEtqluu7BoZ4Abe/4u7Zrc8sW1u3QadSknzJfHGTmKTK+1F54vy/utw1zQxSl4ibQ9CsoUFF kPZCrNSHk9kYFh4DW/HaBpGf6QS8qs0jC6E3zHnMlRqvwGf99OehHg9f852iO2Gy0zD8dMAPX7cD 3ovNTkVtldET4ccAJM4XxPelD9Vkt2ZOztqF5k8hnh3OkfAqgnEkN4wHCzmaLVAnNyizxiWnd2K8 SNhkSaFCgKg9+2gIEgSYGoKfGR4+P6kEP2XJ0BJxlecg/YN30+WMsRcRKTPtwIEKkVdI6SG+2uqe 43pfv0tfvAFhRqTTR8LmoJeB5+SPWp31qT30tlpfLwL0kI4IwIuy33hUV0lAANNsDx11XhxNNrId Hx1P9uerQBCBcju6pT9inRPl2znOHTvkZJFDaAJHj/u+CpoFXBU53KOWYPsXwTNzDgG+P+XVsMzB c8nDUVNJ18waRPIbZBBuf8LgARH/J+AkGetynQSdmY++QDh5McEIIADfE1BXHco7G5rgP1PeR+cF 0eoPbqAYB0Yo4PLWdlyowcomP/CnTO4wLiJgmXa2S4ifss2F+RAbagMMtT65IZK1Zm71/qmIXIFq wH2PyQOc2LgzW+4+gY49Px+NYEPbIWqD92ZDWfPSMDa6x3g6E9H3qgdB5uabE3lY70D64fq4N5gp xpvAErJiz82wA7kDhz3rRq8Vhc7nFRBR9MzDX7p0MsQqbyN+hiOR+uu5DHCko027Cbk5dpZXbi3L 11hbq6OO44S0YsQzy3xKJpTpF6qqmfBKUGoMkR4f8HRXkMHWmoEf3QgOr0KkGrb/DYvkZ+TIcqO/ A3W/770db7tSB6prlJazIf6np0rHlCGnBIc7FOdm8nRQcFWTDG4FnzfisZIRUnQPovXEXH4KB9/1 ceczvAFMioUsseEv7u4EeKhYUxXuCCp1gmTGmop/yw/vjxkSoLv1iP1Lg/a0AcUZDr46762uo6PN eISceGh1ZuJjv/owzo0AW54LkWwMz8SiPdKdgH1C3QcZsfSzQED8bpRsKvGcEe/fGziojtVspN+X LJiYurUb8CUQIFFfJouMRXkZeD+9BcJkUXy/U0pcT4zPzyZHixiogvn9/ZdrPGHJy7NRZBlnlx1c xyZPR/5Qpy5BCP3XizPuqSV0RmVbiUg5vnhVoZpVgv5ktpOSnnGd7jhGbCBKWEuK4Tt81+ZVWiQO V6pLjgZyda7kdd6JsNVVWSfpZyD4F1uw1A2oIjffkkiQ6XL4FjncMEuGjCbG99CqvxmLh3iVHliO zklsuzdbSmhC8QxdBsDwb/WIX5X/i192SrXrANrBXpw4p8nwDSsUJgizLhDKUyKp2ndGS2jShiMY MJbSJdZ5JjfMRq2iVc2/d9V70e5TJYWyUlxxA6egsGnH6J8cJXKgrxVpyVDHyYsKKaxYeE9aNiEl sAH1Qz1U1Bxz7l6RYGCvi0XTgFfPmx/LfT0yNj3kWOglORY0cKBQbGzVEjp4cCPBpI6vsxDsD1cF 35pEArZDYrwgBssIBAoDM3dKsnKFrfytlC4H1CJL3fhtJPjXm7ah6npQo0CFcRhejTlZ0Uc44bt7 /oxcDs9fFcePlljgWTzmWaN0jUlmZuUxN0hjnlnB4pSFAIlNaBQo5Ot42e0ycDPlP8SI+kCIEcUq Il69bgX2uBGbhHPTZSwAh1nG01RqotuV/ZY8TuCDMerR5p3Hh5E4f3UxOJ9xVgCOE4jNNwgR2dCb g/AQoG05y4tN5KPxvr+k7OYwvG/SiJkc8NZhYpX347k6UrZxcotAjpfidNcyNfxW1oOmIRYWT68N msQonAoQ+nBuhNg2B6E7YRfJzlZljVKrolWc9/oOIZqDTcSSAhehaJehD/2XTknZSLBTT2iK6aPd sKhxzGJzPNg1A7otJlUqD3a8LcxeHknNANntRyzIEvJ0dsugJGvpVjTxp1nh4+Y9HoAAGm8uXnyc Opev+OFQplFglSwL7ty0mM4/TBhN0hkQLYvBBb5PGBSrWqT/4piMQCXIIvyiww/WhjTGTqa+rPEQ nZVey7n3xHht3b5V/IDnq/D2vXy6bS8C2Dxbzw+FwaGxj3p+6HiSI6VPVKmcdEOJ7rS1LdhClAp/ Eq1simRjbYTMPTQoO+Z01b2MqaBNID998uv4693aUWcZeuCht7oabVnKD9SXJ1Q8xZ1CV5+GEiEI LzV6NGJhn1u9EzL5YcfeL8lHaOZ4k9WhfMD/Ieh9KmqfKWJYmq5MyfbxYmQ+V4paltmmIDo2K/gZ C6+v/nGivW+nOiGpNib0ob5S95tztpPmII+c82SmCH/XKiqjDVRxAfDwGTwcq+/rQTg0PmJHD/kk YdjxxHWktPHRDGAcSgP27H72vG4aT5g2LGX85wY+p44vDm5siLAXvX7lYkiwlK+GcLiULPZ50Z2U SYXeifspNGb6vGwSq0ZZsHRXcAp3Cu7CA65H5QVr5h3fUcAybmCvGFLkvi45zC5oaz3wNMHeDiZz 5JHi83cBkPzU/q9N75yAtFqC4N+Qq9A/Nw00JEm5mHI25fze5IWT4cHwsbM+YeZMPF3k0gBVMZHl Gqynk80bMV/kAtQJlxOwWwZ8XEq2BYxyuSv4qJL8oaCjWamPWBUfnwI6oGqV5NTNIyO8//TBhmB5 DOKusCPCk7dTIMwum5E3K0eKWlEidbLjExpyrHSdeVeRKTnu+TsJ5OyQwFs+9/WdGlOkB/rDzkKF OsopCs8tvps9t0akVxCJY2KrQWOk8UPKzPSRc30Yd/GZDBJ1zk619jBJNVq1fdyRMEdYGhRjZIc+ s+euCM0bB6tR4KrXDcBNrTzTL1eJoOmJ/yUtKLaYoi8Brls4joCwEjGOsAhZiGmle3jS7n5gGNH6 +e3/u04MnfpTeSJdYLPx8Xrbr/mYbglcZFQctKfgxVGTRO67iFHFQpmwlcUsl2xP4wzPKcBJoDzZ /QbRHh5nC+DFwGO4IlyBVUIzP/3QPTUXOvZ4nEH7atjb/lZN2tEzrFUeTXV0dChfrVZGwYpTVvuD EVkcDAKqszBckJIZibxU2VxYS89fE4trXk34C0KY2JJqU47LR7jfhH671UtVzlW0tTcRCFayq9uG QkQCWvOcPoGNXgt6MQ39WHhY8fN5cc1CkdhXO212pepDEM/M9vS9lkED/i47H/V43EjOijTQ30bp VXXcacs1Ua2LeoaKdJtys4IM8AQVZVigBUZKtpU9czHLuPGQjbRT2MkpHmmOjw01DATSD2IbrhiV RIn3xe4FyN0iWwO6mcgrc/6I5D3h1Orz5zfGlUi9bCpiupDm5sq1pr80w/JTSxPOhSFHsAy3utGk EhCaM/uMq5xdWZNVOQ9z99NRQeQ96yzp00dn+W0zaxku72NM3pLfDyY259VcYPbOPUkJPDxzYnYw oW7yfFp6fsHM2yxQJaeQ5/LFq7racRupegoUmOh8d7qgqBF7AJJC6UGvQ8VkMTfxMqZX7NBv6BbQ SyLrlW2Png+FTfKrvrRVQ9Y51BfJRMpE1B//3gR8rVCc2iOfGPx4ViuHu/WiIjmP62B9W42LlRBF sgyYY4qcRgxDa7kt65nWd8FjlKTz4ngkSjhmC91wtRFZoSS4DP6VIY5V/QN+B7/O6KO1Ax7m99tp 5aCUgnLqr28zMNykVkhNGfEUUSnJkVF4a9HR0Uzgt8u5n91FkTO4Jm0otjTEADkeAAP0xwnslECy 7aM2nonHRn2PgxRGozid38KNV0GV1r+tixcu26W0taea9V977lPDhBcgAafhx2gnWgIadJADTwlq HDHMS0yem4S8DGrhqGHTVo/hXIso0Q1EfWRLRG/3OriPoxYw8turPJ5ABNSAbuIzTo84+Yr744UH 6HmBfOPJako8P/FyduuiC3+/0DG1uFGKcj4STm6h8bFd6ih6N/6PTZ9SdGrcObiPyUGqKO7XuLO/ 1YDJCjrLEnqNN3yPGD2wpeUy67IeB1dFnqQD+65eEI3aKB5CfSQU/popozN/DoUarUXRkeEFV4/o a/NYq1RjLBkBoJQs/exiw8BTZ0vyJLK0e5vFzaijcfQtEl8XQMwTTm5eB/wYbZZF4iim4UOK3cU5 o9CBVB4Mw6p/Qsyeum0km3/MTVh6iFzIJn3Nun+G7O4KTAItGazDudLJ9yLJz/VBZZE8YavkHD2a +i5VBVWHrqbTe/wmvt7ngZBsAiBWRRBH9UXzVj4FXVj9DLQNbuVeFaNXP8bqGrdP7bzqHEytOm7v Q11ZAlrAgqTwnrx/fRUj/x/p23CZbp3h7Ye5/BYPLQUCxmGAQ3+4h4Esz6NeEeXyZIOA/0s3QvQu YG5XfC0LD7P++N6HeUdp/KbPqD36Vg51iBliAlXITPsApgzcECVS16UDH40G6ouOg96ee6xKjdOR xyZL8cKPuFz5e7GdlCyEjY3veYt9BbMTvXa0DojS5oqn7ON6sZ7B2pGOuTl3/xfEplZ4hxYE380W AZpH+dPUtG8zh4idstybANPXwJmJil5cqb58nLsoTHPyTMsStNvgUjB877USpicR0ipEDGVMT8Oy +xq9tY40Ug1YoMT6MoxEeFSDjS1KhuKRGqXrUZ9uLWTU0++uzRGFFn+TH7cUQI5dEZklPtuhP/U8 RtbZqsOF0kVLhPIV6C6SaKYOkMescQb2sTAYLYaCBsW+kQ2ifOeerAlI0b7DGP7sXiMJtEbwigo1 GTvt1kQ0DBKm9hXbITTWwh5RRJDXd3ZxEmIaNUOINQDdYLM3x5YgTu8ec/3FQMRe7ZNwOLvIJsjz 0KwfwO48DoBECEr7QTH4x71K+aw+sdEoXKQ2uv2ArwcH94yzURaAm9TlMuQ2ntlqRi4Jo7nYScFB Jq8HUasAzSrfaykonb9bh6DHDNvg/gYPBYoicRw5+3iulqnU4NVQ1sBLYXbm0hIs3S3HG39IVxeR aRszHVfgVQfji2Vr5vZFN72+IifWNDJ6UgHgURV6lbEarwiXWlTmSanHCvJAzvb+zlVFkJFQ/doe 0CIzrKNrekWbHrmG1BacXA4vU00CgofhcqfdKvxkp78kc/FVhSyjKeRsKai8R8i6wa2MjysfgFDT HVDV9F35f9AuMRwbnLkrXPgEM0SvpapRCMzZV/s2dXjySPhTsNyFuivvEocDP5e7wFBANQNhU6TW 7tb0wJdKoeM7Am1gpoK6HXEPuwhIE6RJmbBWnLSGJTl8V8uUUjiS8Czl9pisbxEiS0cMKucQozbs eL0XfhhEoPO6uF9mdg4WSGI9dsVtDFZaM0aV1O2fxkywOEuLSGaiddE5NQfIFS51xIfwMSnD6qPr 303Kcu7Aa64K5nePFKz8rViFnzmw6UAdbplwRBZAnDm3V81R2bRPWBdTNANHoPfwoqAUwrU0KzSO zXdJdSbMRvXwOX8g9YS1uR2ZWnIh/d4jXjy7XiUP3LQ0J5tLLUCBBW/9xN3wte9jWJvdaAxwcHp0 2V6beX7fl40pAjOhv4yT+otfT7YPb6uy01p3jFFlmCCK+rpGmyqIjK2kDZs/8lWAxEtuIiTlVmTj QcBmx3aagNspfFC6W70XMZfG6chHt2uAB3JvWNVQ6j208HgtBlOcxcLU/x++A7gGHzY8ZSTFT+E7 FuKRT8wkC+uepQxfaYIHOkSs2iu0Tk3XQNrgSjkoRmYrgaJRO9wInvch7qN8roi/yNegF7cjRa0a FAIsthMV4AuGzczcoiwjykwEjgMdK/2AB1t1wzebcWvonrVKoHhyG+oO+oaN08sL9buIA0FLYeNx B9VyaXTDdF2bUvU/eB5GeKA1AGp4dbytuezr9+ABDPAfMNG9aJBVgYC81XJKhqG5RythlqxlfrdI 1chAn9RYH8xwf68opIbBRM9JL7qdhUUwSiRgFHVuKXGxIsFQtGIGDw6pH7W/NQDncdWI9W2n343s tt/6z55EMqc+0FA1hkE/OEMdqTwlXP/LxEdY9WhsLUdh0S3vIOGqWWotIP2BQ96Y3Bfd/9eK5QM2 c1RiOTUFJp7dKyeDsuvipr2QKcvw9YEctQdieVQVwa56zCl4p+jyjQwvCBXd4lBNUzNs+bwKHHCM PbOCFKMPxiFsNud8VyOynpzF3dZCiEqV8pRiZs8rL7m8gkfmoWBnoHeE7W5W21f+FROv7zqUaoDy /z1fwOON0aBhKtNA3p0KJz8i3c37mw5Jx4cm5B8hHEOV6jHoG+hZqyFkKu1Zt8DQWsXBOMBxGU00 E4MWB+aPRlP9VyH0WvrkTPTitjXM+c+eGRhFlyPr53lGaORgIbsv7DEhUxH/idDL7vAa9pFxXV8L qPljU5ER2oZLU9x9uOizF2IiT7ma5TPmc31FdXD+Wcd9584nCUL14UQcPxFtvWuPOD8+VZicuGzh MEX6g++7GoIgxdgf9c2lJFJt+qlIDWDr+7Pvg5Xjfz4OcFE/BsNKQ+vP+Hg1KVSRnMBCCGGLWtoz LJ2WJMyQwqy8DkHcheeYTlnTsw/TzgeBosmZ90ZY3F1lZICt6hdx6HKyWYYWrDXw2lsQb5IpUxQl e9NAR3Zo68QvDvZQ/dBRXtwIlpWDtj5x+JrCbJmvxTyf3Rxv1+1E87s0mdHv50Z8Ehd4pWtt4Xso nvsxQAHKZLUXdXko0O0xPsuk+g9jzkFlN80F08BGSGd0GHevPKUs8QnK6wRxVRJFQ6LbNG1SVvWS 0N6bxzhS2fSyCRpthp6YlWpSNO0pQoZjNenEXzTL1rqlv+BgG0zUv1UQeAXGofx+jYyHxKeJmP2A 1LWG0eDxyDTIbThTqSVRccMxcQUaJ2jaGChCajFl2SIFdxsYOVt6tNmhLfNBtnyOJmFZ1CnR/Hma Cl0ERmKTgPOJ+cM9MawmtqG65ALO8Ny88Gk2O921jBaa/N5TZSc97kSySfNBBMasFzDnMQz4AHg2 ZWC8GOOy1G0VTc7mTmmz9Yd9CdmBDeX95+6DqnAcMZIBjxSmVsUg9QdiiCO7r/tXgX1EX/yI3JcW KRlyzJz5XI0ivXEv39Zfg5RdJpj04rmWoidqmLzMYYHBCsn+kzfP0KMoE1mi/iHtLtBERg/UcRGc Vt/QCHvn4nlnjVb+bpeVPYszndl0fnHkE8ypLRb4THfAeXuhE3YUzfEAWaN1ROWBeAofIpzEJeT+ QmJckYEajIbtcS5LNGyZ7ynzyBmzcUwFML9K9VSZNydy/ZK+v2BQRHoWEORQKdeJe/gte85rDnWz FcP67moFyucx7Q1lGyrecUoS5docCQfSdkIVQkIk3541vq0PgBy6Cl9Md7gBowKdLM5jEiyCNb6B NREywGGtczA5p1sFtj239JQuuGDJuEhGGZjXcU7PYoBMM7tIRMeCJpYhcjORqHIUUnmcpMmU/DwH fKpPSrrWGEqnmyVI/Vm9zGjSQSZZEqQlPcUjNlbd4SX72Kl1RTVxoCJYYRyyq7LYLKw2z26ZCcRF YHp4wKB4GasypzdnLVXyCnAZnfzEPqq/tJefZCFL4BkMt05PCfBVjWdkrTRdEdX9Vy6cswYkTomF 53ZR5NKpxw4DGWfd7YPrUUwLFCii5eehLdG8TqYbrXS5atD0728+A1h0unxiaUqRCcWB3DwabUAw ftdNWjRHgimQAlcHhrD7EnvYWe0k5k9V7KnwJLn9xvF1aQKbnQ+wwB6A/1GsyI9RoM0zQF6B+WJT cOOUVYaQvmfYmN0Y61Ap0onDC3CNTVOqtXT5nJU1QGtNf4tq1MLbTzML7wWiCoBTrIT8L6BdGS6w 2xknlFUuiy20R/umme5EStet+EP+LzTzegnemWZFAC300MUIC5vaERnMFWG7BlV0XDpgQv6l2QnN pD4Yp6rSLCWvCD0iAugNlIdL18sdWDF7ngYSLz76u9Y1rfudh+8oEO4UJENiSkvrEkDYQGCkyFL1 eddUs14jDrAyv5xMfv0hm5XO4AtEB9ZdACdbUopILbqdNdKl/FnCyynviUlC62pxX5oNGCYDT2aH 72AaQuoM4bEBdPj676ag40zZfB2Hc8O/wmzF0o/KCEZ6Jev7/sPVTKdO7v9ttXksUMpWpQ/XoRNq Dl675cwML1TEwmB4YGIUqJVdAWoXHgLckqGLuKrI2rSr23azxL0SCthrgAQyiuig6eb/3S8AQadA wnIgKD4+4F+1p+JJZ/juM3hlcEfA4tnMAs9kmsSPeUjcyATdq/vh+PsJQAi9ecrUvWtBJTfEPjfG fZ9M6PusX7dVaA9viDj7OWYOh+KNjlvTZXQj0rUyCLwhTRkw0WA5dLivJ2HIadvhEGE6+fL1DKe7 L+eLsfNoEtrcg3tcF8FsGq/kzZdg2N86X3X0ctVJMCS6zIPnXqsFsx0ND+gHHzCrxA8z+dHBLdtc ZG1rMHwNpEBD/OLiFD1RD0CbYrY5t+92psYR1r4zDEbasMwSX6YqmxDh8paFqdblvDsfIgKi2RDA MRVIeWl/OIUll/mKIcgpgXp9rIL0GygqoKaO9pV/aGdEYnqEZNZGTb0DB0kQ+aKhjpDAYgxPH1t+ 8RrLsn71CDC1BJ8xy8CwqUHW3XnMcGymggG9CX6LyDxkRMSDI7P/kcD3J4KhXCNyAaT9T+owTR/S y8ajFpq9nO8Oq3UmoBNmgDx6UW8xkGOm37EDjhhrRmUuRe2CSyC3ztYWQZ6i+grgi0qwYit0GoRw qwktn7JBHolo5kjXCaB/q/BFbkbmEOxTUrB2rRIXPKLOGYIyZ7/sdlml5qYSANNjbrk9rD+r6oq+ 2ArXL6r+1pfkvyj4M553nG30kKpypTGhqCzWX3woq9RRmkgX6cyJmvEdvYsQ1BMX8/OLsrWB0umG 73QnV4oIKnLBWFg69da1Bfg5ajAWUXWxUc1CZ7Po8aq8qewT7Ddah65mh42ci5EBCMerQ6IiX/X7 GSY2YEGYE2h6WKP7clk9+z7qqWGiOcu/J01X6uYkAWvyuVDhGu6+S9CV4pf2LiXMJvTEW0+Dg+9P qHoIDnhVe2P9O8QJR7jjvSvC89s5r3B2aC1bIAZl7+dHAncRfIInSyhyn5MrejSUMq126l9ARavQ Ypd9jG0L5WEUmloeKLnYXpjNs5LwcmpmJpClWKjndwdJoz/GaPxeqngTmCnDV79mrQx1KLqOz+bY mF40J0luYFdpfkVuOfSspdvYz6Z0Td9WWRoKi3FA/KYYHQ/ORS8Jnwrbw2gLVmRIIeBQzc+Kv4qt LWbecW+jzwfTfpdRELYMAwdJrGi4GlC0XWQByJDqFlZbSYN+5FL9E83Fxi4njZFlWdI6GyWmkMf8 zbq/mzovEsBXKZdqm+83Zk9Z4sMPQre29dYL8FqE5cV9OfYBjrFaCGxG5O2bLuXlmUMLcLNgfjty y27IK06KGKAeAwL/nf1YIdcjGwIA9qYoOxZwbqgE0kdqvpxPTF6KUODANjlF8kVn+jr1uMxuUzl/ HFoOX2W4K1De2Y33O9+TOzvyIlY/M1AuoSRraqpmtrC0e3F5Vc4wJGT2+NR8YL1kAL/G5pLF/mrF GX2L6bpIOWfRUNFbYrmKK3ykj3QHLUw/lgsQG4Cl/yFhX4LH2YIoXG1WAYE9ZAqn0KSEs7iiYP5o CbMy3VXZoDWgcqoW+njQUufppbgfzfs60w98eaC40anKtX87RvcO608uuyXlNi7B2p/ClVveKlVu JPaBTC+XWIlpPwsIp6YW7LJ+asWJa8pAiGdEqp+wmmVg2zTP0WQmTHkchNuLXhJE3XfhFlx4cKCB vXSh/FJ3bZ7A69T28YIhhiaqYLfrVTTxPKWBtMuoKazNiDNTtk3WuW2/GklFhkk0GOGPGqvCUvv4 z1Zca8nMOMZ++jM1KPPGftMGllNoVCTtznI5CbxOlm29l8v82g6cPP3iyhZFywgoO4fyRtiSWwSr L5041A0KaCjhmqritVabK0cDorUXmU8MW1Zokx1otBN86UuT42Wl1eJqtpFi2+W2mwPUC+Jpwd2+ W7madiW/rEL+475QmEcOyjXIIms2luJQP9odqskzUWJwZbRPD7Pb+tIJwKQggxlMo1cVQO/S45I9 qu+LsnpdA4H91jJ6h6ZYYoZ5QUBgUKKkM/V3VRfhYdh064ZJ3C7le3rLWTg8uSK5y1+xBS7Z07ht a0gjoFPySmhsHUU1UCzBnoIV54N+mmLuoN7uWTC9inCqnBEDaT9fUMy4DnPlGldR0q/AG/Rnbe3u InAVZzMLYP4QPoLJjk0Xp1LrgE76H2OvC+Y/GXXYu3bCJzGS6q+mjTElVgDdLTQ0lCcJ724H6Or0 miz/aDtVxz81jjn0TcFNeMyaPbRmWvGCjyrjqV08W9PG1yjtoSG95hfLN/oeiG1UcdcmSe3odRgb 2BVQKWlIps1+CqTBO3RFr9SAbURZHBcJpqNHbT07nhtuDnzoHuufGMlqGGg/dZT/xROcNCHb+2qT FHaRm3IFKfiXiXS11HuNj1AvdMWmyLNKXGZQq3RlvdR0o9XAhfuJGa5XKdUl7/Vp2Y3q4umovPv+ deEJ2neHrm4UrOD6AwUtTAeXeIQHm/CM/1tZjy0dqdfCVV0ddgrbIQIeSTmCWveUpS8oF+Ss3vai m8LjCX/eGh3aJ/PB9QISR1PPC7RDQQde6SJ8061vJMEYDSFA//x3ddpt6x9coGr6lGQ8h53Xr1K+ U57KkkAnVFAUejSZq2Qhw11A4McAoF38Yu2JR62lwr08K7YAx0l/rxABj75dM7mWHbwuCuF7D5G1 1z4HCZCC0D8s6l5qEO0k9Lpgi96Hy3x3+Vml0vOhe2m2uHdI+WspfZLTzQkJNj8VGMf0rNrp0HJG c4T8NUlJ1x137/W817RVmcEsMt9EH7OKd9huBjTLnMGt3SuvMUNXt42VRbsurISaJbof8bNHC7AS IZ293VRv1q6yqmRBD/Kr+b6Pu1A1cs+jOPjJXy3RD/kyapb6ckWKKtPuxFdflBclRL3z1i2g5gqO akjBXEgx4RiHmC/3NPlRMgY4tsNdAMegOaLO4jSIoP67xO5gvuPV6QwZ8GGbOeANtqkreZr6KA5o q50oJz3n/84ykvUFzu/pVgubPK9JAnwMccoFRdMUD83ddfbNB1yA9M0dQ3k5iDnVi0xuwg2NqmTH paDHW58YrZW/EkK/qOKJQoE8Vl/dz10T8Ej76UmPrdfkRzlRkmMSmohx8CodhTV+LUurbEJsP38k uK3MA5vtLtvuXv2qHmqfePwT6oynacl9Q15cOVOWxHqa/hMU8dGLrYDOjRuqpadWY35r3uXz5zjz Ys9SnhQCCe5gJE7mFgnlSLta8sK7F+6mtfRKu6m3h+XHObHfHSAh3tbNC2JuFmmaGNM+DZkL+xCu we0RVXB7wXOnTQOBilBzoqBqphQ9BT/f0BIn8YhYy649UZo+udDv1i4fDMjm8E8Jl+RyAKUxBXBh IYcg3m4IZRk91wN0vCeSAGn2FqE5dg/cggMnInst8R99iFy9Udvkr7RP1XkVLQrrdT4KzoM50wiC WcsyBZ2Qv1wX2MRz7Gv2hnd8qmHsTSpegXR68rX5q00OMQipkkvhrRQErgYFSQnBmfivVi/O5DxU DqV7iE2bAmWig7ETWhUblFHD+y8Cb1mMEGMj2DCF7pge2wOIIXwwn6Sa4aXiyvjnVg3GUV3qHj/Q G3cLv7TDQLmp8B/Ku8VT+nIfRKwwKxb1fPXsaugodc/z8vZe3tHBKlBpK2s0RMY33DmQRTnhlW9P 9MZiiMXFaHl07bGRC0ppphhiCf46Uoto8xE7KWXEPzJ+CZo7cv1Ws/mIoWZ7ao6I5sXd6MYkD24/ eS9uMQ0sKw/ZfZnfYfJ9/9fhqqY0T+7mcLFQYRVtxY4ogUIbuw7kKpVmUgqgYK1f0/mI4zCAr5g7 xc5kbMmlVI6Gf7/3qOUAJ/0Eyod/ylyRPxZ6IsjLUftc5Oi8l75aSbcWwskT9MFHd3wG1LlyjSVp aav8nUoUzgMaH+aS2RMJVQbDvBECbGGbhaVEryjG0pCL042PdXKvQTy8pKBMLrtTY5llzoaaNVXL 35Qa1f26IMra6O2CNpf8gdehrFxsya/kL5qfYGmtiSB3H985GduP7pi152XdfeiyF9vk56xgSe/i JiWFT6v8gqrVWaSxeEQZNNsaho5J+Ja92K988VtScndMe+rBGbxXFT6MvoszuG2P8nsbePOD6K7p mqj1gwIzd0qq2yOq8zDWj7gfZvD+ysC1u7WBkWkCemoBVSgQNyrMhvIATO4ZoUiBOEvSAqgA3BaM BlBgUp+AW1LETYDO/Sq10dJwwUdhlrCiJjUbnOP8Y98IaqU+XgrgWN8enQsJeTF+Of72uOtymasj PQK0fDzFSHsQ7gUWC2b40BgOUUe74o5WIJ5pzrergXtqpEB943TeTbvBqPg5Cre0ZZkP7Fw5otHb MbOAKSVm2VUZThIH9DM1e0k6whTI3qJx/Pmhj7DCc7yaIGw7J0MMdGkKhmfF1zlyzQmghbtBYuy+ vzX9mF6UUiEpMVASFnvtWhWK1MgVfUePD8U1pR46NBs/Goowjbzy45I9kaluQlmrDpu8olNp+4GX oLBwtJNEldd3K3TTMsu+vEcGl0EQ8jOHgfaDNOHRKsZH3DucuEs0NQzRwKKnqMvtyPbl69IIMNHG Lit1kPlcZhqmy1qOgyk4nVEmKtq/HMiS34sVOWfFl5AhrFeKvdeThrMwq7XS3mkgDzJVCkBj4p8C 9T6HokSH9/5V6SAoM5tu6hoSLk8fUji//pXXja8N8qBv3ZveEYirnPCud8LVfq2F8aQxWGHBAGhE b66ySUXL9bWe4T98c9M8sSP3gVwDIz+3vSY1vG4/gatrlDMxLQNW30VjypTAJWOz0cf3Ns3ZDqKE 39fuJIqz0EW+BDWHpZqRvTLZFxg06cew8nIB9ZCpCW0xkmZGTjOj81LjQtSYw10hBUkDUoQpGxHX he1oplMMhv9847zNLTa8JuFi26Opd0NL7ZYmovVKO39CC0Tlgp0+zfr8sHPIf8YjDZ1P7L4ek28r z9MdvhkaeoYZDaVMcXr0E72dEcnsMN+QJdTgdvWrUfEzODP05FzyG5wqOt2ySlKatyok6HuzgVJD khRoGB/YeeRzLxzbH73ub9YnUAxL7++2FHCxVANBnR3qgOm127M41ppS0alHZdYkYmHLVgU0+Izb rtcB2S0525LQZe7v8M7U9PLyuxayJCyjTF3jyiwLSW/7ar9qbqBHhUaPe8sYGiqoZAp6KCXzSkKn 5LdGhz6zTT45zpH0T+Zprm+Ggp+lCmNifxQrRCw+YvhN9yey+u1AXp3hmtfmaK0Y7T1fdKqPW43u l4v+u4EhLKLb/mvM13CRtCCv8odIhB2rtd0Eb9Y1iAycw+bPUnMCQoGWLfD8Tgju6yq2fP2bszgv AsUO+tVkQjw8v1yWoxz4/v1CKyos58XkV7WsNxAq4YoecKXtPCPYRjXRQ0yeDA2XnlieTiCec/+b OiuxHtXNGw9FxSdU+SNdjWJp3SSgPCwLQSlmo/PzbyI5ztrTtKfy22OKSfA2tvU+1Hbyli2YHRJs s20LSiJecAp0G1jfD2BJ8yRvVUf9kjNGBw7ASij7YJulHDQ168niR1g6XvS+pWSrmGf/dpjR/tqN Yp31wdDIzRDeiDla5AtmWoguitSuQYy9ySmlA4DRZosXxlQrWHW3dvkw5nvQjrXaOb/a9fe+sxQQ 1OPc2lR1kgiR+Ysp4rsX4yCydKumOJ2ptUGdBn8QSG2Hw3C7dNuc7bYSxouaVXQg43qSm/SUM4s5 KJKdUshrjS8cstzO17PoxPGkGRrLN8e5O7pTSjkZMrfOMbH6PUoWAOH/sV+K5WVFanusWYIWLpfz IfG00LrU2j/384UHAPUdFkWvOLivw0IeQTz3a/vLvdiwh2SUiQoStkSgAE1Z/pATcsVsEImy8Z4S v8aW1ITy258TaCAz0rIApzTWn8p1KDygiYp/rk7sUXmWFLF0ktudVr5wkxLGeAkI1jPimAXSNSZi Sg8r75Dl+K4YqODEcfdZQ0d+n7zW/a0s52rVtzLN0htaipgRsz8Th0ZQNjMCdmJIKY2D6Yyhprhd 3la0JKvPHpENToLoDjJOyfZeKVvLT4yW6Nat1PXztbbnhbiFFsSznJ28u+Z52/tpFYg2OImVf3ZP 1yVb4qxt5lvnCFMCG4N04y/s3WBzQaiR/9fAUlZQfF0ByY6pBn+QhtT5SoxskEoffDUGqWvZwckA r4y6XovDqGuBMHGi5Z1MSRVmxPyAadtUzifnlf+NyjOu95k1PB8g7OCbSbu7VLSaDdVmc67oQA7D NJQxaPIPYvx/iS+RCJUJZCbliwB95S+gFZRErpuzsd6GQ5nNbVdnM59WwKpkzvmSJltEaibQRqey kDOnrjjr09SGtg5zdk8RHFQWijPSeE8jrjvIMrYZ3INTAy2M7UhV98HexP4GLZWmyeFSbGS7gIV/ /pv2w5wQb8iUYJw7D8yyXMYC7/kGMcvle8IMAT0ss/8KwcKb3Pta7QkAxQZuHWAFWkf32P+47s9z SnPG5XZMIZS/exGB7e21awrUgMgYlF3Ah5hx68ncqRqyGegD6JklgAkjTOlO4C+1URtKZxUh1XOg 0nQ5Ae3aP0imgMTJZfdKzQMTWUJ8Ieb7f7OiVbLJqWAl1GX1OkoBAbMNE/iwc2uurfD90908QSOL 2z/+GsNYMSjVEqw5NRake5rtQXeSsXa6BD/+Vn+1n+uepodJvKo4JzFip9Y2WiSWKs41ZDgw5m2i YBZkyu0b00bLzdALI20lbRygNfjfCvCgVoVt9xp7MGk8cjgknQwYcakbqzPlfS8hkw/paTA7DC6c sFv7yENoVL+gARD3eX8GMg0JSI8E5Ow4fE4BVerrDZvlCZ4+HErudqRAxEOOhdlNixcYMLEo31W3 CzdgQAnYENvbkthTmsrIx2vjIX7gyzcRQptRK1LS6ESZ4jj4kXLF1bVwXXe8tgwXwOi+hD4ncI00 eZ2OA8QHjFaM5rR//EGrOGVtYdJWhW5jqVrNcFWoWyhHcZsvlYpKQyz9tTaiJRjVU8Z2hNVxBGt2 2DlLDjM3aj12ghGbg+wkiKfTItIsLUK4orfCb1VmmwBuSIZb1P9tvXGjaQI3ZCLpZYCQZLZGrXdC mazMY13Zz7Fr9K+SsAaQ7ATf3Uh+FeP8odJoLhiq4JM56ZGIl110v1a7FXXPf5KIWEzwRjspO3yO osuYsurGdIJ5lw2L7zQ71AFfL6pXs4jHCypFLm4ieHNVSlMCPG+JMbDmdMh/t+P3up20iqZHUJiC 15McVF+/I84k7klA5xc6KbMKywwB5ZoTyV2it8EzQE3vkXZys8Ji18KRxJ3rnTiI/Tg9A77S+Wcq L/EdvpS3LJQQj460TXpODIA3TywuNNX+1ZHYdlgTGkYmAEw+uyn3HEfls6NVwpG8/p2FdY3Qn2Dw Z5zMQmZArJa2kEIfuT8/ltg/JRbppqY0VgawdeHzTXSN4ewwY5ivDjiXdw7jTFzAa9g6d+UYUKgm RRJi71ES9r8x/sVk4CJQ5lWp58AC91ydvUn+w1ChIcQF/kysYFh25PD4ILHm3yz6h7JA5TkOwKH/ WoJvc0S+XyBZIapaI6xfxvIWaSCplZURS+Ikr8/r7PXLhQnbU52EEw1ja+EA3WoyLIiMRrYKZqRV UeLp1tCkI5p178JpRuZxuW1RzC90DOAY59JYqFXwrWjjd30OTo0ZYsNkCilKykoE+0JSP3unlN5C zDMak0vfW9kgKmhkEFO7ge7APs40WIu93h26dVRXjHlD2vEgnms5KzBYrEjn9vJsXdhTCCUP18VJ 0K3hb82RfoMmF0fbeX4CR55i5rlTxaSY7Np8K47fobV5nxqE+Dxt7W3u+fogdh2l6xAczIbsSmFG gVki114VXolraWYCf3t9GkH3wMh1eRjy6q4g5b5a2arGJ8L6QAYI8fssperQm0Jzs9mvYsG7yhza tykya36cgOZGesk2Zp2y+x09oamBBN4B8y1y5UMmT+i/1Bn7wAsbhW43Genj6WrPUj+HPYXfszfj ZHogL9lWCcHbIescKpo7wPL3pTyqcyAnL4FEeloqadhS6LAz3qcyREKk48MxYkrGR8RASBCauxmm rKT7JDuG23rs5EBVXNPSnZekYgvz/fnJM08uFvMNFN/giaOqk4g4ZIUBSWrg9QinsYeh7ag7PTIv LIM1ZAbwR2wwFhRTVYa0LR6QT4pUyB4GVYmW/ghRTpkif8fl1WkcTiXDY/bZ8Vtyv3DHWP+s8Hy/ T1C1mg9ax7kSsfY0U1GLNbeqb1mDywN7IyQovq4VR3m4vDUB6e1dAbMPra27Cp045meZGD5sXDT0 Dp8idWYnj22ioUrxkz4HsE5knvwfI1WxDqDqbVcbHhMyHbYaJ5ZNKGtKMaljLVTJpKWxT/beajx9 Efp8bVbyhzb3hWhkX2twnW+JR57VvTDMZRv7/kdcYZ1O90IXzVMMfGdZG9Q7k3EzIZvrQ6yZ0iLF AF6PXaHuX8ti7nKZDZg4SZO8GnogtlKAP8q/9mASHFqTMx2UBCTT7mGcDYWs2nVXRqjODzPYkJUL s2Z02AT53kaNfe3p3oSp9c6Wv3OaDrCU2cw2j/68h7Pui3mwz9WQNAq7PIQGa07Jh7qnjfH+kpaj lE+gr86+VN6HQhnibtUtFhbSkJcwCGvxKd0Y+6zOWPKkVARXnw0hfpgLnNnd4SF2vn5c+AopGsAE +99eTz7BLp1hPNMb+2dcMaOcEnZX34KMhhR8SYd8rdsqLhlPizg8WAhMHs0PXdpDd6h/ZAkj+vJk vIRdFEXJseO5ThGzQugHP+I1UcZVdIj8uGx1eoOIVGmBBYjHM8LkzvEDY7tOYmMDtm5jennoDtPL 1gQ0QiQteMTutcqX1uQJ31ULUB6pkj0wjj5Wl8TjtF9IYyeOLfsq+AJgdPVsL2pjIFPs8kC6NwRs L+6HT3bfbAN3LJqg/5P0ZRUswTh3pf5slILkwcONV9VCfD98Eh4UnjA/jOeDzFtzEjDrTYUdZ/FB dGjqK+vjDBH2bSqx5Bl+g7mMZQVzze3x2Foc9b/r8FWHv8OXB/FZ6j0KceZHnEl7izlcuP9oszJU ylin3iZraqBESL74WKwXXn8826wgyWX4F6pPXVLtNWrl28jEsJRqfs5y7vKt3an3R5q+Jm+HdHbD nsr3RKmPHnwh4Mps7PUpEDR6cUrOLuZNaGrCydpPX+B+d4RtJrkVSHm8cNfL+7N/7t8F1NXrrvD9 leAu9GRFKt2QqARE70mVhsVqcO3aqH2LedJWMj3FLaZO8lfvYnEKIFkuSImWqoyAZmIEcfjmwRta fdG1PgmicFqGoR2kko2/n80F/e+WqcRAASsTMbDLNP9sgyHKzZy3VQcAm1WHQt7bMEaPxojf0ZNo kJVenFdu3IBLRvd4jN2C71bjDiwwkaxJRp4NmTRTzk2+ZNpFEK/zq0hRvrYGSXpDG4OMDbMfH1PL TNkQL8pU1L4N9nTs86YwNSj48qp0WW7agiKAg/jKJeB+wGb1ImFbudsPQSzfMPfdxQ8MR/Wgi2nq GHKjQIcZxRgZ5Z2v+T8R93276SsoTv/5vM/bgRTGoXGu3kmTkH4/NqEOg+LQoSzKowTKxNThBy/n Yip68cgIocJMEjuQuWlAFmqQwAlGa9uLTzD97VyjylAd61u0BDuITFpZnamnL8nvEsJqWuURR2ln TMHFT69W5kcxer4iNbKES2Grqr8MSafxlL2ZVUKl1H/H3GJ/dsp8+h3OdEoH+qePOCEUcXVuAiMH 0QxEHF0xd7oazqMoYLd8fkxFIArnzGjNIYegp/I5oFyOijbqNBwEB+o/dAzntNujY1EUV8h6CxZ8 OCqm7azKY3BBqtau8aTC/RrzjRZiuM+whR85IUXM+M98xPJ6UwZOmWug2y0hxMoS2HXUjeBqkdXa AS6FEyG+9/2SszOoPj1/MAfQnIoZTW7hPjO9ZQtd1QVRtUxsdC6XLKAv+D/C1QrKlaRiwYzX8olg 5fS+a2xFwUbSaAnxpsn5u7THLlRyaFOezjomcb54lNnlaH/3QWWfV8SQC6dAiqSK+DKU2zB5Y3i0 WXUt/WxS/2tSbaqmk3DcgSzig0x2+2E13s3vAXzo8y9+IfF0LMRNhuHahHuvqCrR4uInuNg5kDoV PF6HmKj/BGZ0OhB5Mx/R/RFBfZgOctunCukw7yXsPOisIbxO874NxTVc2HmZiffwrda1lHuHh4iy bs/FDD07XFASdgk01hGvzcUhf29xZDeTuoMne3A7f/ftexTaByZtBlE+sr7PUzg36iRuc4UUZ6fC 6hGVlLD0cnsV6QgLUaU6+4nhlLB/lwx8v2l4QTcL2Srh5CpaYVXS2dIbCamqg+T91EZ3D52uCZmb 7EJzGD5/WpAoqqCtjsUOA0+ARoHNSjFLRFGa8z1V2T5tVtcDVU14qKF0VkiuOXGs+EQXVpVykskD DCNjFiPUoel+1/mfAAhRdRinJyUvbKcrj1o7AI3HQpvBKpZREv4XMrigSQ1iiKrBp1bnKKEf4utH T1HZBHZ6q+TGe5Apd8pRcR+9k3iRqfbkIHM84+o2GHw/nVykL1s9jPtDeQ0EEoLKvODsEHbzIPiP 3LFtKAUZvJBz7Imxdesmz+/tiYuYvH0vUAIjeAJn3P/I9mQACNH2AKzc+fIJe//C4Zi+belA97Qu KbZ47yYgDnxFXeWBLdShom1oua//yrp++4yH0yiZJyLQfIeGBG+cYbI0/jhinKwL2VpDmK20qkys h2gqvXBg3Zd80fDmI8yoqyhTEdz8kAtT28316agAQ+8h9cTxoP4HJPxFbPNn2pHds2ZchYq+EXlC PwAZzIa87Od86ra+fl2y1yiGHuC5b1vikHavoGQwJeJIZzCvdrmCwMiCL5BpdUULWx7se9CUg2DN /Fv64zXGRlTKBoiLZ2UFYjmEZmd1yoymfHHYLyJCDHLQC/H6WSpUXhdfuBcTSxjY+fKpw8cxZCKh NF9k9JUBpKf+E/joG8Eu6RkwJm6g6LrtsZarIGQUxVIbcrujELYfOjTnvLJa5XM6EbzrBCAd3ztN z/yTpr8lJM5VGIalSiVs0vX7tn3ygGGUYIWH/Pq3t6R+B9X+shX9yZVFUYCeU7d5WmIOqa3H5RDZ iyoB7bdnilEJaA8OTcgBcXTFqW7BHIVZFjlNbt5nFWo62fti1E+izxHbnqQRDMEqYf73oZ934Y5B gRy7l6w/CyIEF7bzNwyeyPid1fkoMzxdR72xx5JOG3wRagpplgHyVn/QO1ktlltsxLunVqqk2fsz tKW0mygl5T6YNc0cfXVgX1pM6syJo5HO0PPXpF9U3UEadVqy7dR0+f2U7ojZP8FAKY/sX9BM16eS hpLyT7zKXFXjEobmdTOYJeY2dEZrvnKQXZnbQp4eZlpDIO/qENLvl8EJcGQcyzw+SIudUPyzb6CE AWbpQm5HZgXAbzQa2/sJIbeia2cgGV+Tx7o5RI9SwHgQYahdu4Qw/IWsGCdKrSm9+bG8nEqL2E1U SkR0LOtt4p5lbCIN68qjp4B3pAFf1paBb9N9ffZv8KflIuwddTTV2dszSqiQVJkHpKFUL6BkMqv1 3XxFq0cXYECNx89fkcfr7Vxj1yFVM/Fg658FJkTUDd/TNXpfXV+C6nNKjWVYlXuyvwCmquBdEZNa EkGhGKSeR9pez16EYeglYSkBoVqYssJu75NezNtUC8RYcrBO4IHJ7CjJA0uNH3R2LJYmKIEC9rnw vhgUajK+q9osWLC9kBlpCImYC5h/MQKBq9uhkiVCGPNRn3RKff20WBTlzwNJ/xos/roTJAIfmp1+ ovUGHoXSIbM7OuglL2XIc+QtuN+FToDiaYJESVV61BwpeQD8gH8dgF3tLR+zs8u5U4ru+SCvr7+U mOolvUj0bGMdRcoQw83tQArlgwzp+yxKEq9AyjgtMpXy17KXtnqVzmKmH9aQfQFAXsLHx4ESy8MT QN57j33j4LAbCBvcc8IVwlM2mh67ipUS3pJt5othQGRWeCJFNhiZgagZ5h0d9b1e+nxqBYlw+vfr B1w2T10EZ4vwG4JxsTFPM7QWJ0XMMkJcXZPOP7baa8Ozhjh81hl8eJImstFHYtk3Tjb4pNxCWKK9 npFiDJXQIgkmaCZj2zDj5Ghr/nm9GfQbtNCSzmJyDNpUQv0ODdKw5YN6JM8rkFjy5v3Kvgh6s4q8 mJz7iOwkukkNbjwrRpLz834QMQ9c+XhVl0h+dUnqc87j8w3NWFrYvWoB+AMcGmmZip6P0JDWCS4U EGevm6L/43S+AQzWRA08hUbsf7zAQrtdVqv8JO1Gak5d47yS5CBebexeE0t0hf9oEcitbr6x01YO h6r6JK8k5r0N0ssF8TTmzTdOfo2xbAU5FNOiWvyfoJIEG7fk/DPpH6zeMUCyTVY8BejRPDC9Kunx mDbFsg6T0q6xBoMzaQRL383CIco9VeNKLdEFFdOmbH80bgE0lukdcg7O440ilYChFAcatXPcVk3E ilAxHb9b2+aosYeAThB/9KDFt67wPaIUOd4AzsajVMJR51PhjNyjtk8EraVLoFOQy4u6gjecbIeP VKxIbGpkGE8g2UN0x/OazonRn7rlZ3aju17j0b2SiGsKrJPc2xTn4m369XmQhltTjRObhZiG3Eos t3TXdlZ99i7CXgsobxIpTA+Bo9MTVfX8Zn5v2M8WrWDoYPdp57muSeFLdKA6BhRPEsU2PWqCQxgl vVKIv599Vy8s0w2PazRn0OjZODu4VZLku6cv8rB3TT9OgVw7+GQyNrLkVaR86wgOuqjzx/QUazGC vsnhOLt+P2Eot9dXtFTEj1mexKnbAbgAUfZ+ZAOj9/OSO5xqGhceSyrwrKKOkeLjqfjjKyxNtm0a rPFqEGR5CbK9EsknpVogs5DEYAKiomL58Y1kZmcn3hV8MuXR+ZUUWjZbhjvIfMdfUNMcOeMfBCT2 LGReqWjOTYXUPeE044qkLhu0dRnpnw3hOIcGV9hKAshtx/DY59igTZdc1KCUmVPkMzFJ/RNQPl6B a6y9AzaJQeXB5BKE+Om+Z5gA8pCcC3T+wZyprUCUvygAl57pvNcD0NQ4k/FXDbp/aIT6Cuk2aJQY DVd5sT61SBl7tTgro32oql3lIBLWMgwzkI2EqtPPupGcrTiBufoe7zVFw/1281HrG/4DmCcFrJjG c52wsxafK/Mf4zlaDy45YRfMV/D0yuP1dHbM6tyeT8zRnuj6GW1gpmPFCzhzjL8LXKqF1NLtIwCF jMdgbuxQicoT3PNljaNqANtASa+yQ6TvROmCTUlgFq01jARKHxDEZHfxanx53Z9MHiAFDD0SzdBL ZFUstS/kxFREjU8JSSogW2ps2NBTBOtLobXzHdJXrcuH0B1LgWzBgUjPR5yHExcBEcswj2yE83vM JRWgfzcttah46NEoveWE7ANEBVlYsIJaPkdRBETNcfkrhxCbF+7ZP8sJfwqoIEITeSyMJ1YBeHtS jfj7drSdH91nIu0hF33mLJHVTykT19jxvjZfWfnnF6haCS7Nah+FWus2uhpfKiLzn2wMvfeDLJ9n BGVoenkt8dlLHqgfwlpltDxzVj2J0QgyA0YUY5A0mEcp6niEdNxIF7qGk/JhN4VZnCZxiM7cjEg8 1sfUinEg3CdJSp7QjlEjh7ibrbqjkLswY+WkQ0M7RpWdTyEf8kGOVv+XWY+zqkZg8vaK8oyJB2Wa 0pOdOAau8xutBk9RYvgFPEVxidLFfi2q/hWY0egK+3cJ8rCNJmVcp8/8tw8pHgEtyCewGdAqqIrr EYZOSNvLYGhzU8NEdWfchuX9LuM3b5968eQyRdfaoTHoOqwB+HIwXJSZyCoNv1XCJt6kjBcVqfSH 51WLVRfqoeHQHVodIbk1sdAnTEp/UXweOPwF7vWkXz6migv1XaTi8Y7X5txgyFnUXa3fAR0YjXwu gjGK3DCCYSMDsmRCGoPYauJyNbYWaUAwBE25UI9qrRKV+0LO6MtE4BaqjnPz2dxBEro59bb5KlnF 4wIGLakmWzw+aI23c1rAcvxs5x1RUbs/M0yApwY5tGOGPOCW5ISazddePEg4gmo++25vogQ8PM76 4w6yBC5KijbSFxlX/VFV63cKS49I/9lhhlXzMeMU2+qt6xtJ5RF4QtWvDzomRMTtd95pd3Vq5yIo tyFnIunxEybeFUA9a7Jb/pUihksRWdbhX6ehiZYU0A4H6Ffo6KUVI2C18vALWmgNgqKUOmGN5kak oRZbSIJRqeEfMLJMFycXFheVKg8m+1/pqZJXTnUBc8domfc5Ll3q/6fbM2KGS3KUyiJowySwZ4XK k+/PfJltWeOeS/OTZBUzvZU/kJOb3WYnx2UnUBpXgcfwLFbCuN71xu/j0OqPhSTgVjQmI27ijjHq vSEKAcXJTdcPZrFTiC0kv5O7nSnwURp8FEUtlYqgTbhYtEcNWERFO+aadkI9R596sUc2hGpVbz/o mq5UgPKPyO/Rlnb7o3rGfV4ZFwSdzySjPgnNC95yzXSWwvmtvuYXc7JA4VItuT1Gh9shSWKcuvho hKRsxxHJntmHn9WYipmFy0hv36MgtYOZwhbzppzAUoOVFhKgrwn3D6UQ/FhYbF68L6AUEApYVthk dKvHgx9yf/bDY/9lrAZqi+cRtYsAUuS91EH+vt9Zvj/MeE/c8ciPHhyZvHgR8jgU4jQlnp5b7rip TUapDKaLGWa/exs/rpSh0V2V/b9dyvXUBFhNp7WH6tAAFiy2HSwFjWDeRZa8a7FtQjG8Nk9HQvHi m8CIjfJV9l/XuswwG63iQlXn2STNbdG0XJxSt18OipnqCFY2LgNaTgofSLWiDdh6JdMK4nMuw2hd 02d0qTQsor4Nl5KEvktaaSVnHO0ulMGGcSuwYzDxHEGoXtJe3m/sE4A86JydmDPuExhUzGSUeU6V XTRGlL0aX2wCmRRyauq0hHJthqNSOPh7cSZOiOXUZKWrLQ9heEsNc4WaC51VDz2q4Ix9/HdVvSmc w39wpQBd+MlsS6hYR1sdQUGglGchc440fe2tZehjzFZqWvIFsGPwpmYPGxCSf6kcTJXjCeQGxeeM 6NiaWQ0zErtk7NHj/aA653zSAaaTKUo1QZUEk8ziXwwDSwzvvHebUZI01LroEwzbCpd1oTWFcWxJ 8rAL7MQBVHC9Djx7FUOkTywJ/fTgkljk3fSJp6zgc/pn1Z/d3PPFZE+n1Asx+9DZpa0eAnAfWBz2 IcjwGmTVV6hPk8F4huFHAHjgmjtbfQ5O+r46uiEl0CEcd0lgKAD2LNWdGGl3qVHOZiYicvjHCMN8 MTEmL6xVf0MO8vVoR9Q78nPPhGUn3d1LvPmR+6kScCWyN+jF0BE8mPUq29DrglWa1SjR9TL9CJTS /z6pJBJMxhOb3692MjD4Wd1YR2cxBQDTD9spfHMvjPtkDh1zELzsvX5wdVOnNmGHr2KWi8guVJ+X Mt0xCCZQifY+s5tHzuaeDANB5lTLz0u4VhNJdPAe35OWDLp20S2w7VcKaJUgNuNZYc1id65wimJe WR5Ilsg96+KP6jMr9CwlF5pXU586puIQ/Oc09DuGMuaAjx4uPBW3K3tV7uSMCDKWIw0lP6uFeFfw Fn2rjCo26MRRnAoCLWiaDY9xPe7WvXLgzdwfp5rq672bBPIimhWzwU53bHrHrpWsxCJV829hoddF 2pEVCnHi/2dx2+noPdihDY/m4q/CVOP1uc0iMUZAff5bI6EPyhAWgsVKzCMBtS6EnCFVAxm9cAbc sOGjJZqxrLbgfCStCL1zPJBDeL6QvffLu6nftNC5KXk5395J9W0LeEvFUH+E4FTAXFqkkbpretsO IMbChWoQfI6BPCs/x00M3NfvHWOurEKYsAKw0kefeIyv/xgIf8Pl1gwJ7EY2sRwobNykMnP60ZM0 WI/Cs4yS8x60lpD7O0BNiEJDlqNGrd7epTyPvlraryQ7sl+zewmWyHuiX43iXc3R91SIe9tHZbmi r+x+wEMeM/d7wd+XkOckt5Bz313tY5nRcoRVfj1eCeE0AdHADBcDGeqYmvJFP7lTd1ff/GW07Xst 8+7dX3Njs7Ku7y85xHUi1RUeDuZXEmeoRkYeoo9RG7ExnE6vMiMK03OY0kND1+p297R526WaypxU JMu0ncigQxEbR/nHFIRdhqoOrHDQDMbNXoQh74pmGOskhq3m1GCOWzrRXXGOy9E3x0hpUaS80can rW56hc9Kdp5+u9Ws59EtE99hMoGP7d2Ukp+qakgaUBqw8izzuVmIOmU4XE/qCXH4Cj8+4Mtah6Mn +rElXnEVK/r5s2axxUpayXIBmtNOdPnCiixNVa4wSiGxBFIwrWtwKYfQx0iHsyWIGgniDMOpNAY9 pRlM03hFWszWY/CYAoqCQ9NTXEPY44ZirSLul4VRb8lQV9w1v2A7DIm3O3C7NjnZ25A2baFEtTU8 P11vx/knGB8YRNwYAMuBjIQ40yms7OKNNSXJSBSU06+z1IiUNUZnYv8q5woPn5KUF6sJTvsxMUp0 fkhFVEtCgIocM4vZjiM9InN2I8zqsvyKMzzVB8/tjWtYLieOWoa+LdjjauMoaz31EUcv90qm4/7x 99HcvL3J4L5FIgnOJzuIsXHuJQsuIpNXDye4yLJ5Pf3OaWMzzGPzKfY0FahoKY46ICELVUUOLseU Cl4oSV7D8FzSQ1fosa8DMln1qBNbOyLhLPXeG7OlWhCKkQXR/3s4s/BRgpsmQHns6a6tZ+35S1ju wQwa7HhM0AnTn+v5iCn2CNUyjxaDLHsiHi3qnb4qah8v441u0hn8HeouJEm6O0TIhYqXLFIF+vCB Xe21nXEFidcGADCtZMUv7BY/ccQPmJagMn3fLDN7Th1Ule1s+0lfTnfPL6+PDTD6s268k2dTz0Cy 5dKw9kl5j1+ZLAsm4z7k6MGSBLf2kNRajVALqZkW/XHsvAv5OqljOMr3oe+eSBaKJNxrtJwt85oY YeOdAwpVvE6N8hlqHARPMTDmp0CCe8N5YjMmlR8yTLB0mVB+CGBtOqiBDasc6c5+0J0NDt2VQ//b 3mcoY7+l7C4n2vvtPS2OSps3Okh1rzRBfIRNpt/hQOEUk0p8ZLPgjgvR03XwZKQcEPzjHV8zDxRk wOJb8MpIIv71J64J8YLZyJtg+0JGSOl+hwo9YpiUIQILiMtM6AJhtmE+4J17w56D9hWSr8fKo4Cy gfJgVxGzkmEQ3NT3wdCG9/mQIlblQHFRljjGIjdPoltJbk9mvpFb/5QOXY71GVSXcNENrzSaYvc8 CWmJ5yPvkOL4Ayt7qYGjSC49DVlPBTrVMGf0NSbkrLFdDl6aSd1R2wJ9iDe1K86FdeV3X61lXWe3 aGqbbeVuqOfcxy+Y0vTjO+I29FiOr8BAzAYmFPq9bUTN0ezD0zX+bjXTi1l+GgeLXFsi3F8JJ6bt fDqeG/wr++klCHhA2tDpHgZcbjeOsmwgGFnSGhwGz8cgow4bVZ9//djn3E3SkT5qM12UmxWvsZrS H6PKJRYhbj/3xEgLxBYP5bYs+5g3oMjbcIIWvLeAS1RhefJk2MgqlQgm1VteSodnD5jgAsHA80rM AF1vCoMfnmf6Nb7WtXyRKFM/Vczsh4AAkrW9gTXtxzLfR6gswiHMN+j9NconxSsFaowrrRRT59EE wgwNf0SwHmPwFhb2tgVMVVqxNmlxyFc8tdIDWcRarDp0vpBIioISKIYjp6/iOrNH2euoongFg8w0 ysDh0Y967w0CSCBFbjDMyADJ3u7ppJBDoGbzwz7gq393wj9OisOjgE1hDMZb0IDbs5JG6oNhl0MD pYUuPEe7GctCJqhVoayP0+fZquUVFYZyGHjJutHmVWd07GbuCUbKdGcMGI2SgRuWrNfT02/kJ33G x5J+2nSvKpyEcHY6Yem+apkXPdv/DVXW8cItzPWr0p1PlzlYBRQ+egupIhWPPOz2yfEa0Y027cha UUs0K8k2swYgtcobUNuHKmpfS6CPVRP/KvtyGXvPB3m1fbXsVKDSwEb32EVH3YMvCSWxA7q+tDRD ySy+3TSjiauYXGWMeDFx49pckzRp7hhLR59jYKGE8JXp/JPVE80wZSeEmM38Ivu6RT8HEgp2ZHze uQT+6dmg0kl9jQXbXlAXVP2ez4FRA4ARRm5kSfawDGJrQLoLB42pv5yVWToSdTCIxL5hG9EgiYAx 2PFc8Vo1LS78g0LoTj1H3LlqVb992ENFky6Ck9oOoQfqkiiwEGPUiiCHWcynrjFNWktbsKJxF1c7 wRmWiD6C/fCZ2C5NQ2PurgH3ktsy48lzPuK8fuwkgtWDCZTnaF+UlYvHglw2/VKFnEpnSmcTKNXD YoUZG0hMPUVsYTRguS6jeCG9P4qzOyw5npVQ/0ZF6GMVyfR8kwZR2I3Mzrx1dVUWFSeEzEQvVzrC sAkqYOau3p9WCd2LIp3nyrLv+lAt4wldyNdf5LQjX8D8ejxm1S1jpUe9Cu7JNBy2DR3kSnO/5HCT ZrfguIszRup1n/w2n8sUlxYHGFRkN0VTtt7WIlrqy27GwB1vJi3f9EMHal8jT6auzhGh8IidqhsE rpgj2r0PIhnEl9kWdbx09jGu9DsYT0PCiwOQrf+UHGnYcQojszoEjlLlIk6EGpZ5z1r7F2OqfbZG BReljprttceg0BaTPJQBEzp5h7SQQCEPruH0QrakgTee3kqPB6ZbX3+o88aFnxVfC2/mEELHVNuJ 2MeTNRJURUBoP8fpYWrC5oiaIaXof+PycIsZymFXwQXQMUerXiYtLf64Qu2nWL7ZaQiYetRY1ZHQ SWZJBMBZF425HU/4CT/x+vJ6JOoN82o6Um4HUKUDZG25fEYEikO9oqmvHWJCisssP6Qip6BQ88/3 q0szDjOTSw9eDg3eUzPGWleH9hnGStQY+x3Ochmmd+zRoV0aA8qhPtdXMDhDvdR8qjsAKf8Mz1Pk 2QCnOJFQ2schLbOYugovYJO0WUBjyV5/+bqDGZduONncsaH+ZBNs3usremyS8tiIEMgBb0WHktW5 KltfGGtWaNJRUt3Xdf4PsgXba7P71UXGZbWa9RGqO2a2f0hvCKKTL6yPQGc3dV+4IwrZt2YVUzvj yECrkYF+3rQfzHKsJy6qw7ZhYFRe4j4yTx5R0afyeKS/hPOjuwFiXQqVV2jVBB3oxBd0A8vvgPqO erOoqE7s6egCQMSKPU7Eshknx6/oWjU8CLThjku1abaBnZ7vLnTQLIwtBYU+N5fcaOKdMBoCpIRP a8MMQoO6uNmRftVqoZkGX0T4JDMiPG3tbUJ2nmkIZh0867aEZuVqFeAwMqW0NflSUdsXNjikU9jP 3PbBF/e/jpGNlC/yTue4osxlF/w+6y669m5LxRBWU14BPGZ1tiZ2IYAjvREIb+X8RhOeCd0AsRfY G7ttuGioL6ZJX6TL5ZEg4pdC8KrBOFR3f610X+UNcp3bwYJt1yd8INQWOk5pmB4+TNXs0Ytmm8k0 mp+OXO23RbnLqNWASW7WuCmXF2uw8RyelT34Fv49P8lUDHQ9WJWPfPlNonFj9p8leZCEI5p6+fy9 1VUJXPZr/Y0239ykwGxJ8AkFwAn7ECZOxmiXipm0G0y20323i4YpvSzXcE08YYMmCuQvb96f9ILs PF97iHSeRyRW1v4mQ1UGJUKZDjBeZHOqv8WBNnrVo+lWQlzt33JhEOapLIL44hMpi1f6XI7h42HW lIWAxFR+HyWGNewBP8Bpw9IXJvrciUdA8pP3ta0v+jB9H+JKujzCh4I9BJfwfnz9rUB2Rxdh9TgV FCz6d5p3mNr6ZU6rI6YTG66NqZg70DhHRGQ/g6uQIFwWqNcBTfDl1snvv90uqLidHllzXesjjC34 Hxcz5g1v68bUjgOdYARP/4S+PQUff+p2R+H5naB4gbW12wCS4Jl9XJQJVM+c6YoTB88IAS8aRwPS vToOfzy4A6lpwEedF5BW7CWnU4FZCX96V1nQbg45H48KxOpvzA9QBOPNtOi0QDXJSjGjr5Dh4dQ5 AgX5+Y293BxVG9vB1XLSWTjOvwMbQSx2rc9XOpkKeyCeFOwTTEycD/b0WO8PsDFegqsoEq7ueinD 2Qq39PS0kU7lgE9EQ/sC9/YPzdpWD8rJfUXwUTcQGC8d4JT8ihW4d8o4TTSNiCb1AGmuuC7N33vR zqfNngwnrOaAR4NIX2qvq/F3Kepz6K2lnufdCWh5GuJtcM48ZKWvHr7euedeCIpH2bXb1ZFu4rC6 BcD/O2L3U23F++wBzqrJeCI2ZPpbQf2ua8LbhWV4ualaCc/T/ULoZAdnklVWhefqNmHyJrQ0iXkn obO1CT2w3v9OZDt3sykgJTw3IcPLqAXU7+j7EbJ2GKc2Hb4ZacbCAjolQi/I6mE90+wBdVhuLzsU hcd0AMhgl1nBiwinqLb/W5dzORQoDBEoyK7FAJMGPUfaCSjRPgdI3HBRFmzdd5qDJFF/S3xFoLn2 PC5ETlZtfAnvWjdClSKsBAIch//LZDwBQpsxlln9F/WXylR3Uj7SHPgqSMHw1UVP2XVu1RMzIHoA K1xBK54qK6zSp4r3KzZg3alfdNFQVOJTCdDSeDWCcg9l3hSFw4s5FiEuDNengpTSmAssv4ww+KB6 sN89q898p2dzE/CR/g+N5KVfMsVVlTXDQeKqFLb2C9b7jeyz017KDg34Eur67X01yO5UEhPGHrpc FW9hAj7kt8leVUEGzJAtyLTdSGZTpcBbcC3/0NaTmPXPHw80Gimx4OCmyvs2Ypr5jQhWsL5PXwIO ldIYB3ehCxEH7f3MAXrtxt1DbIUoKhIUVWkRIYey7K2A70zA8YoTlX7amQyDZXJE3CPfJxlHgQqc zc4ipWrKyzu39Sc0CivY3Mh0YG3DAPPmPy1wCt18Fc8kzqw0+XYlKUiCQxcvfDaI5LyC9WjA0Ry3 /MU6VtsFKnFGtN6gYipI5nKD25t3nElviNc6y2W6C3XJq3T/o8HQOF2HwEWd9gDClSA/6SQy+oTa q7BfjfYlvVhXOfzUznPK+f08jb/QCdMYZdgro9KE1eve+KRkVUnD6CocBdAukDw3HZk2QniF+gMk 8Hj6ADCZG0BjWLUS1v4QwJQF8oRepuBX6oGsMySJhRMs98J0NEVGU9MyOFR/q5jI3OcN+awQM34c L7DdVXf519wHpHVnPGKYxRpiiF7iMBO6yhZQLxh91vnu3CHsW5WO1DERiRr0F77qdyyK054Hdq7n NEdyJ1kPx1qd75b5nbHix2mfa1h6gS3YHfawNcgqTymqiDXpkJG7K1l5D9JE3vKMUHWXuyYM4mJR kwgy1Fg0QU6ssKsvhljtae4enOk6NHvB4K4NcmU8JOehFzbfUOldvTacBP4/PRwzs6cNfDH8Y2b5 8C2eqgqzc91b+qvVqwEdC7ZR3zoActV1C3e0owkSfiKiJF0yF9EqLo63j2YNPXNLQZc5PKdMjSlA WIYel+liDaQL1T3tQ6pykoEJ7fwD3suZ5qeBiNvChw6tRGE790Xrp+vyR9mhFHrk1l1q7fE518MV QAbSanSoL4YpDG29i63XmqQYLjHwk9rCN74bY6MMWaoGA7kpcc7CNBeWqGLu2LoLPZtGn1HIiDPC 3q4ckqX9QPatYSSDiWP1mHZU9rnabxInoGbN/qykQ0WQHFydHF4FA1QMeQcffeplKHKsbOysHTkj oz0aokJrxDN3W2YTBIu9PQ7sVD+DF76zj2ogzLOs6AuV90vkHNqgU5kuqpjJijtY1kXOFNLUvIBw uds9AU3M/Kc9hdjVwqeg3sWiEVtnQdWPEbNOCOAEtnlN9zoviNNiNIxilwVZdATm6QwXclhhIufm NoklmByC35ZiYuWosuouJXWPlU8yD9SXOen+y3sInsg7fizzFrEtbyISDFq0MLdHFnON7CVv1GKD UQVA2hZg2q/t/ghw++Ift79xvb9LPQZEAGXZbwb6Xv5hSmsCR33HDPVQwXqwERp/pNquCXisrK4o igs5Y68UFUFWmvWtzgMpjeH6uogjrSGt1JNQYBEZOxQ7GAvuIufHnQfUoS0IUO9nod/6aW36CBJw htEQ9yvNvO3So8W326mv8IjKQP6+y4seWNF2YiRmGD04pGtBEw1aoWp0lon0ALqbtOTWsfV1T3zU kW1bObJ1YoKqAVYbrvu/PS/YE3p9rXwamX3uE2hZDK0le44Qf0qKX+50P1BI8R15eZ7+GrBTJUa6 DiGrl1YbfUZUyGNph0L/KFINWzp+MdIvzq5005mKBgh3Z9vLeYf4dRL8w4tLtmO1fFJWM+lsVsYt /RpdFpkDUynVs7HArLF6d6vVlKetEvVIGtpi55+5UazazMjkOJEJr95wgtz3tiw0dU7A3sJgtNQV FxwFhE5Lp11tn+JqBN5WrSfrIkBTCDMwcPWEKuD/3/YiwYPkMyIvGVoGR1citlUdt+ddC+k9Vd3p 0fVvlXYfLULg1ctQa3Ex6AAdByPAFIRRTTvuyHnSEzpPAeV2A1cPbjxGp8ZbAOYdKhWHDKPlbqhO QunuhzPvPHBLNjz4w+iU0iHHvHW3sDRe8Echa4UWnEWC+P1pKC2LiQwktryDLKcGGOqFcRm9B3PN ni6NpMeGRt7Ir6KtIYUtLWcCAE5rNThvB2sxxAzz9dd8HF2pLkKlGlGqODLv4ixNm7tDAwJMlOW2 gep91rwvbG1m6M+gwK6L+xVBv/FLjR0L7q1FZFAKQ0bfxTd7W2g1edNrbFIln1U2m4tfd2NqzOYn byq+OyZKKm3WOg6H8bazeT3Nlb43NggYjjIY5qsda/0DCunutRAa+Ll6LYmHAYI/44eRagyIvdoV XN2J1vsvOpDAXp/y2p2t6zfi8EJeSzl5rRUvW7zImDGaSi7SkJf5ahdk0jZlbFlfTfRIjyMdBfbY HQhRRD8a7ODJriKnxsLNg75xKP0wNuXTSoc5mFoiU44GZ0pDcqQ+n2bHuy3ygO5YoApMhNC1ZLNF ySz5bD20TdGR2YnDG/td8PD/Pidk/CC1VccA/sLSLwD+CwMyB9Sw8HnJh9yspR4vUZUaJ4U1H0IJ THatbPGvmS/vvCYo0W2D2wMJ9nXNgQREin9F+cd5nXqWYFsjGwtxm5jmAz2nhXtNc55raP0eBfKk RJnJc3ZEyy9biIDPETVJySgmrYTL9cF7Kznb9kuE7kzCFSTS3rvuLsxXZmVuKhzPU9+fx0H11Zl2 rMVpKrNEo+TNYDpu6Lr35a3Q9BrPgmMeSKku9er0HxvvI9+9lvLrXiJw1mMqMY5WWbMJOqtxEWsO U4pmM+zxm8k0gIjfKSosKFiGM8aVSi7BKVRYtLh+o9Om6WYgMutcN1hxahnX5CGTtSg5gv7b3lSs vbZ0EqrVeVHZ3KD+qJHZHYTQR3qvca0M85i2LV6DUDqQqvHt4t5FQzsKrzgvDCjaNVhnLRIqGjwS 5pndOgPUr0fGSx7kKVm7fxslAvr6w78UuKsdTAByDEaj4yqfbwV8FpDQadir+3YHhYjicmOIQIqK SNgi7aAAXhAxGBNwVRwd7W2KobDybjkTs1jH+wEj3XFR1ErKSde1cIX1zcAPb32CKlMvCvs0m+d5 PO00WqxzFoCWOglVOv2qVdTuQ5H/RgFsO7K+jzCJAqvwldsNVOg51QSitRLyN4eywc8BmdKbUAGX dQYdVDJILZXzCbzjKF3Paqwphj7TazqxcEzr5Iu/HnQ2PGeALVxaLmOCDcQaQXGNOA/diPi5dwcT ua93EmOWMoatIhdKzSZtTEOwiOKSl86Bi23D2pKW0YD8AqGhgJxm7oPtTn8EElZfpUlBWbBf4gex 5xiwVF6O35ZEFrKu84658XCIPAUHXc6tdSemYORod+nlhJrauPD1pGDICpjpZTuF8xEFwgFtIDm8 15AjklJyQgoOlxIW6rg8pnfGY3qlM/depB7bKmjVUwrK44cpBW8orZpuemCd4JU7EHpdyZYA+DPi AK1yqHe7BtEoFRgruAbMLpE3wL24IORfk+CC+gFbomoG23XNwb6Fk0OVQwF6T9x/6hY1UHr4SofR gGN3d5e/p4XsMPyko+BM+sf0OW+dNZYQP31OeTs0Dp/Hx2iFkGnfsqJ8n2n+c6ELtHYBaNMK/x14 PwuKGY+IJ/98SCkWrtAu+7GHnSOzQ4aGbv1C2Gz1Hx5ePy2vtjoQWJZPn/ud3qzUed3QSYJp8JrG LvTyM6u/o75TubAFCC9qe11ce5uDDDtIi4EziGILyuFPNLzZoTZ431wknXmZWdOBLy9Nls+XNfjj BZVhSUKKyBtAYpqJkUpl09bY1QJr52dfm5Cx2a5INtlphzoBoDmFcGUDZL91MbIKkrHK8MKwItpE VYrFsiqOuRXZf88uo+yrZHSWGGTX8GyDxCPuAN1O479xkXyXktTfdTCSEzbcjbmAItH75SJDHYY1 yyiEeRlKEqwwax5t1IU1p1lQLBNgBPOPz0COJrvwoaKeHyQJhV56gciehp4/vz8XgEKVDCGFabA5 SbSZjdD7PufnX/mB1MRg7XxTTFCEgyBUcE3bKq03UnEA0PrAbknjs0Tc/n4Jy1ebJ/NkbPrFFcxi UB59xM2iDH19mgTIG67aoAAY9sFarwD46hiwB+hJ8+D/eLM6gBLgv1/LUT6UBKMieimqDB7/An4m I6EASUBgR4GYAtUe7Xp4+0PoE9y3UoM4ZU5fmpdjioMCGoh0J4l9FKKhbjFuk24vrF7YHyqT0NwB pZTcphm3Mha19nlx74oXrdaAtAJ1OLxlKB88cR4PKqRCfTfN3Nu4hGxEiOmGU0VMlve66vl5YYPw SzNIaWg1a6h8xuJSDsT4c9uPioeiTG9cANeHWeAwjyCNH6qEEoq9Z06fGDfQl12wbdEb/zi44YxV M286vboHdDoC75LY5BLYkn6qPcgVGWGjjALFrVGrcmmRptsGtxsrldsL7U2RHkgT8mon9STm+bek jZt1EaNCsP0UoxWeIjH1nXBm83vvmL2SRv7Kk0/iX0KllYXH+6E/0s1jY/CsffowkWvJuDHqxf6K fxgfNU4OaTB7GD7fJTkoMPHEC1UXuTfiuqSEN7TWgQMIQN5uQRa+AvtQHIMQ1SWN3HwfwjDSaUb2 xdaEt5KSJO59IxrlQgDw0nhN9JvJgFRinad0lalcJ03hAIEZOjtIfA7U1anZmSG492+vHCg3293V qgMIPXdwECTu/HE4sgEGzCZKf8TWmPqWbJPetD4sp4Hja6Nj/6RuyrahzWKHGuLrx8tBW6AyuIIl JYufktlFwGxNQ0gHDY9ul4/rLlPOftbRENNCPjTArt7VHZHbK/I7dpnwvlKArbZ7zR+Vpo9iaBVA p3IPGHhDYUXOWvznBjySsYWsIyll6JMxIzZLYiyiBP5oJg2H4t34lpJtcuVntrkzH394WY/+UE/E Qqwyj/TUz0Mkl49loeyNx5pRJmkeM+BDGLl0M9BwV6wrrNN83ZMLLOVyN8uJh/6PsGwkkMsJs8db iCUWXsqUu4QL4N4bXoFHvH92WYlo1KnxL7q83vbjWSSGnc19oasb5Ek+Qt2HWtdeoUNe1NfJn1JS vbPiYEgby6D0lsVWKwuylVg3T/tFDAtKxAvrWmcaXWX+ekuKqBlPZFWLHekd6Co3BdVyUbS3BJQq 4VwlXaPzGJ+v00PlR1ADPcTjSQ1dfQ1BC32WQdT9K3GwIhyuQkX3xdOB9gFB/kcP03YyqYHrnSmD VyE0jdha+24eSacB4wYPeX3lmypNFqy6iCDrNaAUILUdtgs4fuO/6YrK9YtxbZ9VHXSPVGew28ae U10RHX4Z1gLNcSL1pUY9CVfQbce1Ct83XI6GvDUhv7L4yC/dwzIcUxi1eqtNAp3FtVFkuKOJBW2G FzlS2Gzp0pPFy0znsCLoRGImJLlQkMmNBftIM2Iigg0d2U0Ct9dfDbTXGmGQdzzL4wCixZ3Yu3lF /AxY3FVX68bnXHwR5Folv0sSy/x/UTY4UvX4jCMZK7O+VTJoqeV4b0GoT2Y7jBdXfVaNsy5cvXA5 slUZc68wc6qJUnbljyf5wk2eQsw/EJUFBUT0Zjb0qxbhkTEDzzj0Pu3dClaRG8jdYsIX1Bebpov8 YgK2tDUkQgbUOQH7Lp8UqrmOHwfNk56XCXKZM1II6fNUHmk6bzhqix2x6kylkuI5w6i6sSFUbyiP lemG2AtBkkMdyWLybNzHK+yVduzkXpzaTBdH767IFkdsCPRBG0W3Rx4Bs/oOj4ri8x10vZMTN6t+ 3VxEJ0CgkfT7lvraIff5mtqAiC8CJJXeNpfASJ6VZby8sO9e/hWKqZajjp/LF3YEunBz1LiA58mV /imDSozdN8npgHhbwmD2T1NqgYNwAJqZOSPgru31xTSQglj0h3FEUWeaGwjcV04i1KU2lA1HFKYd uc0hgRR5QjXf+cNYBKKQags+jW/B3p7QFGlCMSImb7ed9uvotlJY9dmOC07N4gBvXE1YfZym1HyH a2cuMHeEUwX4T0DEVahqR1ZHRtAXLpyWPyn7eWOHUObU6XjT5/DIjYiQIZ9ihqDhvs3YZ8idO6PA wN//jgXoc0MPg3+ApDNz3ckiVlwz7NlhLnOAMMJu/b8svh16b4FbwKZT5Xhu6ixMtA7K5IELceAy 4DLmA6HDiM1R+xI7Cw3c4CjW/q8TUe14R839/g0jeloFpGQwi9riWOkIf/yk1XN0Q9Zxh5rJBxJw hmJVtCtCGMz8p3Jk42bZViccEMvENHmWWiirUYTH241NeT5CBMYEAuGoRiFifyCIa0Jl8sp2Oz+x WJAoLNFyid82kH9ZKqfnEXy7/qHrtjm/eo7bt4X1FkmoqUGc9ZmbRXJ96khJlrX2MxStoqoSgt9M CxPN0PDv/vR/EUStR0ul+LyUVTwcdBmP/Rqx8XoL0PlEjSmIvAdK+xIhkbieAnhndxJgv0nrR2kN X5YrL2nS8ULWdpLdR6LfjROVvSSyQYtPIjMGn2LbZJVBQWWdenhhAZN6GIUyN/zJlKG/CBsMKrf6 MmQ2pN4W1YUB0ezAhGY659wLyvfPPOYlpSgljmCsTIWNbdCDmSCo29TW7fGF9uQPfZGWbV8ef8Y6 XQZRGgMUBjz7BndbtH/c/zH4Xs0KLVCiv+V7gdLRlIsxqE3YHmm6743cjgUNpdG/95N2dNXg45eb n+aZX5cLSpmGnuu/gOBO/QnCV1/buNhkL4R5EsCHB4dhQsrneZuej5sPe5uXC8Lb8bWuzb2m+TyN 2SUhunSh9ML7K4ixjxntwSHO93aVDCvq5rdWGzVFiPSuJ86Xy3WWwqwh27BRQTMRrxtoVqFshJdB VKzS6Ja4bd1rEXwSOZSJrKWuX4nR/t7953YyIqGnuS3ZHhcAVUZEswhh90lqMI0V/21/WEFMX3re 0UJpeDi3tSALxV9R0DTrMALgzxPH+FHdLFt/jxtSSQ1x9buyjDfoKowjlVf1/gGxwEkHT5KASJ75 /j6MQjR7xlBpC3q0M8KCv2rldKC2xUSRqJh/JEjy0tFLja3dsWuKKlt1b0/ubwKqWY5CS+E7FK/h N0DtuxY/lV64Ree3nU2oD0WNX20tdnLWBX1OYDxHrD50ucT020S7M8RL56kebrapsBa888rBz8cX wZ7vwZzYmUT9gkVKqhLVzGP281KElJabbu9b4DGGF1n6S+YnT6CupunawhsKc1vqXoWTquoM6pSH evBoA/VSsLcZYlC3B0RZyHvZO3t5HjWSErr9UIDk5iwvuLnMsSQuxxohiY8ARMQsetkuHWObuHCT +Q+/pSyrpVliy1HyFnam80WesjnJhSCtgYViwHeKYeaMJBMSn72DdCMYK5JTHaky8mBniDy/yh4z e7f9f9WYKSJH0z/CfvPUSp09KcMVGdAthhN2EVdJz4ltkPr3vehIjPAxrQRvqnAD2fIkIOvbocC/ EHasKzOvIoyo8u/rAmFCGAviIqw/Rc4ecRa5lJ8A0WRqgvW0tUnkKvI9WLwq1nAoj3Im1O44B/Zo rxKTsHIfNRgQYepLiNy5JkO9B8hxTBgOdZ9NI0w0ZE2IatsUWLwVSCyMie7MZxlVin79RJXod69l tT08CIOqQ5sBoF8FC237JTTzKNe7y00IiiE9k9POv6hgfcZ22hggk5OUP8KCFKdIdFbv+HiO26k2 rZj0VbQm4iBiaNPZSXrPvc2LqaivGzmwxOiXmCLtbtZFCbmfiUH8nWzIC5aX2GnM7DPfEFu9ooJw 8aewTXiLYst+9fyejMbs7wyukS2xM/+w5TBHSEC3voBfplikkvOdMOkrDRsBK4j7SU18ySVxN7Cf dQYuvtNd56tTaGYe+xriUPIwiD+JAivZu9B5bEo3Ul86v8SH0LnsSoUhn7PVuFiQ/E86jXdT/vNb LC0WOO689I9JdSvBC0o5fdPk6yzYjnwmP1fQeTOR1rFu4cx/+hWN8ICouwaa44spq04DcZuB9EbX yDy6gw/daato1E3hu6cI5B/RQBtgao+es/Mo8kLZ5W3J5DHCNcHGmsDtFuB+uz2d3OvluDFrPLoc wpxibPj3HdgSMAJUDnxKxCoP7Noeenlsga/QDMnBOWLKn7j+03TNY4j8OQyB3Hm4FaOY3CW6dkq3 msRUQTWa2/yAFeQK8fJm6rmc9pwKolDgvfbX1sHn/OTtKXQ6i3vhTzvazfz5VE5nDC71LtEBr1cq hGg7odepLUYUqbX4IDWpuIszS/+l1ByKnlKRxbMqSpdgCenZ0Uj0BArt1xv7NLx6dWRjDUToc2Wr aPkSaHv3J4Zc3woocJswXke2uvxlWRJZdXE+F1OI93GCI6Ho6k+pmkALbNWYEgeRdgtlN86BjyJm ZO9prZYOOg5ZcdLXpm/Y3627c4DElEJCI1E2vaBSZEYIgvhckMLfsxK11183/9ocmi7OI54GvVRu txp8llXhMWj5NJJqR+ic0R2ZMQ5mwkH2dzGmmJSTdMXz7/RLJ2pnsvV7tv7tAqSQl9P/7MAhXF/y k3NBeJSJn+AbyAdOH7jMAF+gfD+GNxbQfE7XEPSySgSIiJDsM8aLLqmV6N9jazwJL98K5cwufarA irHWizEg4FNYtIgL/HF22aHNJGOJVZUyhqXGwU8rBkmCaRRkwHrXLCd1drQvVpt1DhAQYtesv2cp t4xZ0YsvwL8ahPsVUFRlgjFmyjS0UddkvO2/TX75aK2SfI2TUu1/wx0HUYKpy9H+3W/mQ4iU8WDR KLq4kv3t53vaiOCGjuRHgZ+7e1WkbG0k8aUli+IsQRX0RAdIwJVa1m+zUQtSzD0jL7vYHU1smQaj BDHeVJoZSe8J/TveWtKDqdJL2Axx0sKAKsUc2uWXcpa6u/eYpbhcKsbnh2kclCXwnA0qIrRl5cKR NdBw72t55qTKMEgRGWJiSaHe6+JqtJgJvHs6FNqxk8PVMQCTumenmN35YqRj9n2byRS08KuQQnUf K4BcM4HthUzncEThX7kzuEQ92Sf12dgRgXMLPDnBmArjny582lzUo920xUc7pPhepA+496P/uDdq ueyBoafBRd7eOB5t0j/xjnsNwK8zhjFrJwF7VU4MvUFYC7u3uyB307UW42IwO51H+8B0ieot4gGd jeQLw3J8DjIm6GRU+PBrXzRu8lCRp+cI8YbhUS59ebSDkKjPXVAGrbr8Fa0QBFu4SYBm7bZMlxxz zGbpvRJ/IVZOK0eXzTHgMUr8eNkTeBT9gliuHmXyer5gbLGkxYIFhkEhYjUcdwg/dma256lPvsGB GV2bmGdi4+UCf/rgAqOph1mZ9SsT4/esPlv1/mBqdVLEpzYqdFT2UnzbRIbPmsyzjCEvv04ZXlbR jp6RI/nL+qyZwQ9hW6ILxlI5DihAfyvNNQjiKni6J4XyjnG68/qyQY3duZ0McaY1aq5BTa5P38b0 Mooy25+3kWQ+sbOzVFAlSd2wkRLhROD8fAdUDlT20H4ZmHz2p6VOCmWXbjmYXkD5oZ1o7+0VQPw4 LEOuSIrAOlt4D4w3KVO2v+Vnkp4Zu9kndknVp+RqzwCRvuG3/Op1FHCr+nOp0nyQN0rn7nRudWpV dSHjqm92e6yqLCPdNNiTPT2nK6bFHu7BBSgSeyaRCZoUNt4rBrm1v5DNuO6UP+6zVFALO8ExHmd+ 2W2kE0bKt90A5Mm6+NZ/68yCeXwDk7Wd7IPe0+Zw54DllTFDFuWerg1Fnz+Sx+rTOtWcoRnyUv4n DZJwhrFnp7pI3YNiWKDSOAGLneAt/EQ+5TcqtkgYCxyde7aGgFdQdqE2BA2tUbXk/9QCRgp6CkoJ K51IZBv3jdnc/Ikc/jVixOF7YdX3nxArpnZJnMFZHQzf/N9lN5why/VwJsGcNcESuYsWkcOLDm/b Sc+ZQv6Ugq0xmg777Npw3CByhcYSkwGtdrjub7z0UxPIf0e4T/j2+xsJkQeLImDhqFIadDEOPCfg IsfDYD2t/V0ye0PcV9tWdDry5pPmAEyAYASu53hlzkhY8XMjgT3Mnl6HwTrokOZqwdAXNI19DWaG JySh0/euLsl8IAi5xC9rVV58vvRr0UAbdGVw4WdydPSRN8y4VHYw+31PPQSiM6rucl90F8dyA2qy h0RT0pVY96UhtwuqMnxt7OD58vuViqKkljeNe0BiogretpE8jG6H+0S10p+H+runWr/tlElKQiW0 AikE9tbRJfuRDoWQMFA22bCzoHV71QWQtSy7dkScstMyuOwwpNY5emUhM5QNpUd1YwxTQ8n0Q0ew zHA52AL5XEsGmRBrKCZyD99FNpYY5etbwBhX3if4lR6M0X2mruk+ydwrFdXEXtgVWG63dvkyuVzk 9Lu9fEdb0lFpmG69p868SKBGthGNCzEZGvBr+dZ/AeHy3uy7VG43ABk9ZDZSQTvrsLMQuPCt3HaH f69JJiZA7zPzLiRJPY1wDL4D8yMq1vCrh6EMl2R5OLAU6zq47RoAa7QjxoMJyVsgN+vKcZJ1KS9V JhFGPYZnTcSycfXJdMUu09RtyI953Nkf97K1ocuRvE4dkX5r5yrsqD+qvT8ElDGQx1nzh+j4lvux DvB6OUIzn3DD4QRPtagIhyQwrEDrzwqf7IckWPEQ0KV74feJMgLWjUKBi7+j5mScWQphvSQgisen fKbPKU1NBFEujdIpKLkMcnM56mUEVyhZCI78yTtfiA9XW5xMw/v7Y3qJ2BhLApwxc6s+mtPEx9xU JyctDx0Gol3xnRXhAnz3gv62FrHW38yAk1QFKcv4PxwmNQNWz0ftHKqz016dCxsoAZl5l8pjUBJj DoZBQHTnHoDYo66raLY5R1wG/KxlWJzxhANjMRRycjYjXc4XehP44J6oAlxsjs/MXMwQ8ss3Wv2u yxQ+lKxLXZWy+OaZozgE3JjQ5U+qf803gXqzWr6yE4FAKl2WKXwQ1bSZ9IhXK0P3ZmVvUtuNtM7v 6Lb99iewrY9YPhkJUk+WCWmwQqLrjDZjEZDDdbNs07VVB4JGAV3DPrX+dDTNo1c+I6GokkYwOWo3 k/u8ifVuQKn10q9D8R8arLSQxjzKKrwhLcN4SdNBlJ6a8puwP11Kxn1SELM4/rcQjYloz0SLSNR1 ZCfW2QFTwtoIYulf0pcO5YWd5cr9Zmr+pKnYKou5yc1ephJLJpkexvU6ids5tedD5Yonxi79WuwO LH/jcNqQo3uKZJtMtw9j7PD0HXeEidmQ92lxace/JqHEGg8pe2hlUhR6EUQGhgtWwxuU58peT0HX v3EHuutgZp9TcWHYysbgQADIY7hozRtMYyykWEmUMMv1vfAXGdlln6t+odWV8R2230nOBqBuvQFT HLLOCAM1736aKlzlXvShzfQMukpmnRS0JKQhGD3CRzLxyyg2uf5UxubeR2jiPDcWY5MoLs9DEZ3l E6Hkrn/0p0b819AbR23efZ0+1Woz69IG73RFWHayfJlWyH0CKq7YR7ebqOV6fDyH7nAC+q3sodrR gHrlLPRZ2IefgaJ10m0VMle9d261eztLQC5CywNav8zxSPtZUZnPsLm/q+fDMnWLV5reEs7dGiQI bANgWhg+XrxRta6v1B7nyb9Anr2dWUhJ6E5vMIoaCID9qZ2CexsnIV0TZHUsHyqBb87IZ40NrNXk xMPwStt2bgS/9DkhfbtH8016vnnXwjREAAdJ0g+8DO5T5sJCGvWAeTsknj/Hq7/X31wGkcgIU27K YJoE/HmCA0hcxJlo4qTVxb/C2BTqvkPsP1NWt8TRo7cYZZdqoD5LEM2WlEQ/pZGOO5OEQX9TiseI NDx4U7UBvcFj2bc9b2AZYdMB4w0wXehwg/5x9uWBMgzXtnJou8eughRWw8wF9EqIZbpbW9mtaUiK ufX4+yCi5RHuG5OrFmL2ja785DZ8zYUUzlkWfE+hJ/Z3w2SAID1M6aDRJi0l5pe9KYZiNQx3XH6L VKw18vS0nJ4xYlZ/e5IEjWpNFDTEJ20px2AlJGTDHsYW6/CKRuofq2g3/RSrKpr5iqmWkuHH9zBQ r70R5kFkt9lZScXa6iqbZV6CMiq7NOkuuw8G3Z+TOqOBMHwKDbfyA4I06aNZMae2TszalAt6djax 1W2ZyNYmGOElvBjErAEJSKHCFUpsQcZNdPbHNT+wwfwCa8pAC8GJ8mSSIQhl6QpsCzT8gZvPFwyw r7xuzCaccIemgR9FPInH+kXYHgesuHZjNu01rk3LKjiLG9eMyeg5ZWQ8cGmOoc311akv/TbPqL/I mI1SEt0rKZ4759qDXyhDcDwRP/fjFA6SyCxxvzkRytlV9In/Iuo+EJiu1HHzs0uIttkKUmQ/6Qbq 1NIuafSPZZ4jdX+zkJdjSIbN4Ws7HiY0M4vnzpY7iCaJhIR1lZ6+Fd097OKIqOnqlX80MCB2uj6E Ccoh+lUHSBGbFnLP0+RvPQSEexHymg17PzsHdK6lzBNIZnVX/GpYbCuJhVLCA7DUgg/SrF6kf3An HrmVnHfKxG8jtLryj28tP9JKktNLmJ7DAp9BrE1i6aDSoXdF8XrgiY0fcAb3MwuLehKdZntfb3Y4 PBDeA2kJM1Vxoeo3acv3BZ7uJXi/vVLYzwc37kUUwlgbxn5bYzGtaRRK7JiowmOTw79B9v3MScDS /9SRSYHggvTH3246nrOdr/BEpDzxfLoxHx0PK8xjDylH3ENAn4lvgzt94KDhsX+Wc8bRr8uRgbYd IGo+hYfYzivsBYNUaCZ/NK1qbk2vPo0SFvcdfMZCaI83l3nc6o3dVxqQAu3bW4Vfk+ftYZAVQNAD rB3feVF4Zcpn4m+UCYoa0hXv567lQa6cI01AlxQFqkCsmWZ9hrReUC4ujpo/ekCXu/Jz7p6G5JCT RCBFwZozhKgdQ4r5EoJsaZd58PowL8F3a/EgSDdhfnd7Bn5z+qe2LuinF6qhVtHUSWlde1a0FVwb QUK0KV8OIJEmIQWperaMEcA86W8T/x8ibScblvDMsLy4fnNJx3TWA0X3cY+489roELO08dUxJ7So cXwAmNtGOWjcT+E68QGN3FMzkvTKdJkSPY1q/eW2XHFoP9o3VDm0tqpDZzc143S5O+avEzeiszXq KoH8IiRvj3vGaUi4DfsDP0X8VWbDyRA5O1033r0Il+dcGaTZKT00aXrvI9vaIrUj+lDyVLBOrhMJ 87JOaQindWETF5nicaa8in6znAQ6i77XcYapLY1JTaNtXO78PQYq1HP08Lu3w/HC1nBszVejZ+WS xWQMx1qmBtWWHOhDSYkvHl7F4uA4Le7TW0jR+EEKCNFqEZmravcyqUXC0TrzVtMJ1ZVt0TXSMfiK dV2fDLh6gHuJMF9lWNNqgfkYqIcQPgZEMhwqRXB2ca/rasjjnQYdJIqdjZ5zpm/FK7d42VWRjGAJ dNh+O41zg8ZUzlr3OQfE3tnCPUW83SldoJUdayVpQD8QSg3C6k1GlImm262kbJ6aHN6o0625ygts 2nadGnLqjpobZeAKMEzxgn8wx5ncrn4VkYyknyTIS+Of8dMdHITz3QkM+4A5YamLZeRWYtBuMw9r ucrfINEQsussh44Y5u0wdpZqxD2zeDeYMbfjerlzklgP86FM90xNm4tgbV4O1k8D37OlsFtrYzgS pHq24JLAOHr1nVNGw+X05M2YzJ+wzy7saNfuaQ3843SzC15rHlKKy2OreX/Pe0OU37Q4AT3aG2J0 uyZeO6kn3tA1oLwV1DueW+1TVELSPYYIpDBKy5GVGzLhbfBBBR3effabty+T+Cb9CwsX+eqNn7HD Dcy0QtJ0tddWirLmQOPZzYaLHymQUbnS4qpumNCnHfxwebFioy20EROS4Zx3hs+7FrNqDs0Lo9bf u1zwldWJFRBD5ZrAy6AtOeE5YK7lzZbtoiqw5hNgajG5z5kCs2Ub+JzTXnwFen9bys6XBAikCOcO ZUds5Bmx7aTAvAd4tFG9tDA0wPZkxBIvEmbT0yzKLY9SaO5ouFfbWnCe7qpU7QuOYSpzY4udrQ63 M6kfYhMAH0diT1pw4kQpeILgW37XUEgEKChREw/kZuRQHBQk6sk+tz2aG+Cja85a8k4IcU/aaEsv NIePzi7jbdQD6KnNkgGpm91TijGgaZdToRHvzNUvVfIsG6mcDeQZ6It2GMljNx+XtQq4hAMfYA/T +ITCljkQSJH5kP/PxljMfybnX++OJBFrH+GGjI71tn9tmCQP2SRYvpupVonlcEkc7KY4PYongxSp G7qlyaX8Yt01LYmeEzO6bV11LzpH235zJ30zBVIyhrar4sZMVVnPv6DwjDrtZf7UIyUMi9Fgls1w uFG6+XMB0DD8hMnjnEParZZ7uf+3sgsqfzRbyJs9v/QAgJyyDY/rV+0IYBvFiJLGn9/Q+rpwQx57 /mmf3QAl/d5ntzlT8776tv0vXOUPUvfnJBz5hu3R5WAPnagvde8z3Zt2rT5UJjUL4nLok++g/nxl DF0gIb/kSKbYMTb/Dd2BxnLZgjYr0NL+xDzDa0yWIWkTAM0Ha4MGub72KMV+wiaqDUr0QmB9HreM 2oaivk2YamOCmG/lRgq+BWwDhdx3Yf6h5dneo45LONfLP9fMea17FQDCXDy3RxAsKTIQm1AUdZQQ 0gZDA9rxnHIo5AMc89l0pd5OUMwQ+TE4IleTU9UWfD1LQXDuhzM683gj0FzI/xrWCnVe76HDrnuw Qfkz1Ov9aGMFnaOhAHcD2MTVCw+3wStlAOMm8nwINx8Ia4q2dWZZtSoIU0PlXjJIZaX9XCc5Dddp UW1uswav/m48NyHZQXQXQrC9Dkir4c0Ugv1FAY0CytV8PVU2Rez5hfF0U/xxUyZvsVJfKVT+/Xsi RkLOHa6dWVLdPnN6BOMrJXvyWu25EuP71w/JzbIbUJVUNKldCxZDTEsWx5wpoHQNnhYcTBZH5geV pv3f5WlkNWxRzAl0bCE8tL0bq2VMMBgfbFWTW1kAzb0b64gtFeCiKjbLebCbBiXPl/Q35ok6rDIn dRK3NCvrgHWk5BplU7PhHRQMo29L68Zhd4Nio0RfK2kHYjYRyRlv0rhnoApdfEUbd4hRUMAzf3lR FJOvNhK8+WwZGfk/XeLIkTaEqfmZ51yRFQ21XBoaZs60UoeCaWoxl6TnDh79N3Hgb3cT73zxErRe l0omADFnj/W46OUdJ9NEdWn6ERjDwoo1mMdF4f64AycKJOIg8Az7B+aTGA2xP6CQNzhPE/l8LWLm 0eUw8AuSVuufKPTHny9PCS+/zVURvN+WNZExT/vBaXDiwZ3FsYi17WBdgro8tA+f+/8XYp/bti5W Ab7SjQBiC2VWhWkXN0pShtdo9mg7ahQ7KwgLxYHtZ+NYu0lEsqvcBqYyAonvoPl70kwyqPmYpArd is5i0KfJGG4Q0SKc8JHI5mxroVUzyzCFJ6O+wG6jFec00g23fXnGM1S15QL32EwNSa2+VSt2K4Lh Nck4O4u7PlWR8PNcRCT+/mbdFevxzsajmVFbGDOralSciWK2+fA+DCgNdfCu8bZXyYpVxiE2cTMr 9PKlpi7L9ZgjxLG/Qi5ejW43XxNAULxDrTjfp0sumhQjDfua/DbBeqvbWqygB9CPJIMUX6gXvNLV xHDrjGdO/dV/I41807gxm3vmsDPI6ZNdsgs+8SFAIz+0OJ+mFLglqpLlhsNJsRSk4sRmaqoEBNj3 4pJyo6U3DM511p9zSJ9i7L0CBARZL1nPqfi/6Y0sDp7GyTiJr6mPlz1mxJleFFfHbIk/L743T+2a qMxz8VYr9ilCXJX1M3DUhwX03hODo4LTD297XzGfooZmOWr8diHkre2HDNHmjxwFFKXGyIGclYaj hXI1R+taiDUML/LqA2EUpr0vbQwvOSnS0+HWMNRNe7CSZNWtNMsQeuk1X0K3RY+2SZ1p3zSvSP+6 PrKGyBZYt75ljMxxUMffN0uIn7F1J6bE5K2HPT4kLMYJCQ4CDxhzhnNWWJ5yMnHx7nCzQxLL8zTO PIMZ/Ta5EXdBwOSEiyOxLRoFqBwrqV6/th98nBZSy9Avt1tiGbXmonzmfC55Kw9SB4y1HZBBaUgh ESaJhHK/Mtm7ec6SU+p+l3Vps3FGBCCdQVsoh9D4Cgn2tq+0d2uVq+6VNZ5/Ju5RXA5qDbKvaG4G uurG4lWt3vjVs5KBd64GPKwROPi7k5bPxJaynCatWCTbAb+aymBUvnqnP23ZVZFcexiwLQXBvZwD vZPWaYb9Tx1gnFZigNcvT6D10AVM+byWwHSq3yUM8jKEI7ECN2leVSmo2qKkiUwSFMM1rK8Y2jr2 Q/TD0MEhKaFL1gRvB7p92LGmyCLAZJQtKMUUaI00v8y2Mt8yo/1ioTRPJ5XrYUjRgdL7GYAWlVpt uZRq0ZxLdhJ/A8C41DHykPGjsJO9Ube2XQ3YpmvPuem3k14O1sqXNZ9n/Vpl51D/U14FjtExp4+m hzFWmmTykT8IrSn/yIecZadd/jA5UyaoHqcTYlUTbM25rDUJMk64ZWfmgLK41vZFj+lw1NfF4e6y fOdKYs9FubtFIJqgDhXZpSPl2r7uTKY811/yMRNMmkJWLacqFZ27AK2K7vvZJVOeqegj2mQzCZAq Zxam11EgC8OCMm3spd9SV1dodI67w4NmKGY6X8H9KelGzGFitzhcXtPRzpArroDmi5RD2+hWhBtO 1xNOvqaQ62VlSX/4WUjLhhlIlBDIVbAfbZY/C+Nc8gYsRrylPpwSlU7JJo8jrhIFE/8bx6+nJilZ yULyJX403nV0Jf8xx/+NZZkYHu7t6uWY2t0oBgOy3HIWOIXKcqERp0gE8heth8lWP5h6V/HBZAfE hKML0OGgtlsKvqDvWPRUUJrlSAWXjM4QhgnxLSgKZmI7dZKLwHenFaB80pYBk3ZTogUBzzG5y65V VlRBnwIrzGtEhMAaJhb29TZhqM6r0P5XXrCwJZGj6Kq/d5XbCaHlbyIZew/Qe7gbgyicPPxrxu9r FP9ndve8x7F/rWPE8Y1nuMz5RnnPdt6UGagje30mgLRkhudE6TuyRdUyfKDrwJ9nI+k8+KDHuWrW hf25UZLYKEjW6/9S/9/e0wEBFS/acwSbU+yMkJmpdrpTML1Dwe3iQIKSaWc8YmBHIRcYSxLpjSoQ Q/SPVJ+D4jltArSQMQXs2HOqNLxf2prjWc19bRtFpEZkDb4CYfvHbSJgS6Vz+g3Wk5cvd5zUacgR g2rPH1oYnL/n9/AMtl+gTVID9fOu3hQLoUOz5guzocHtvhH/Bhov+zenby1mdmUdw1jnq+8XvSO9 z12BeOjmSKf/LkGp1ooaB9FX1X2s8IoTZiQ6hMqt/PwOByzWP1InMATMSQ3xJ7vuX74zlz9bh3gN fRvhEjOwUmvlsjnEL/imymkZb7RFQNdmTY9Q+z+81nhSIKNvlH4Zl8U8NR74yOWC+O4hL95EjgFu xLPMgqVccFWEjKC22q8PQBJz1jH50H+iRwcWUeqIgdhGYST/pydfVXJHaV61XrJBem3s/YbNOYh/ YisBDURUlJ0MtRMd29EV1Xw5Wql1vKt22MMQkx7UQnMzdxS66I+GnonP3KAxW6RhEPDHjsrNkpWv g5tMbpdlluGKxNYfCv9YKeFzJGFkZ16CRx8zFHWq2itDkK3kxvhHdLYaKadAIC/TA+n+ipBO7oh5 k5CrvJngepvjdkRIcbzMWTE+IiTNcS+1IWYvCFEgoLOfUzZXWQUrBdM4GMLaVB6kKjdnI7+vrwWZ PdYbyGb288NuWZHgIeN+vZofYacw1rrhzry9ksXXg7aISLYDr/qMqoHdkb0sLMskOd2bj/H6fojo ZTGbVYSn7JKd14/MzguyDapI+EmPzSnRJnCGx3nwXgy3Z7nicxV22ALJyHl8VjiQGnFndBnTXROM rt8JBKMI22PBGvizbSG2rJOe8azZedHdXyT6dofmsh64ZkAAIedk6uBWsGYImOiQflwYjJrIpkML mU1qWeUm+St18VpT9YKBZ6V9Ms2g4BInraEpFFfJ4JXJewuiHGgbhpmOpd04KKzrqCSPGfyAe7lv Sk2HuFaV4m6r239624tNFILhc2x9JuJLdXMkp/CyKkWzHPrFlmQE0dflqKxjEo95UXBf5cICn7tr NXHFgIrUDG9DLILRpBU+WOPCiEApuP5+P9bIU8u8x0Aaax+ZxRREQ+l2fzp1os5DUXlYwpMX9q/e qmT8Mt1Bf17kNz7ixqVFSCQCIgGbAcr7cvD8MvK1ywg78oCV4YChcBOFxM9SM71bm4WXWzfGw3cJ niwZP4THNwkZUwnqZMUS3x9kZ7EX/hse+Ut30lhkPc7jdtW46iv331vyYZa1p8zGOA6/zzIyvbRh hkwGWF5QumvueunkmywfOyQ5wwS9Icmmb+fRWGmSFuMHbfYH4GcUK8WqU0ZQuwQNU9J4Gzwgfl09 C9M0kJuFuw6O2/G1nYaICrbPkAUKpv0cGtJxk9Xc+6dfVZJq9RbpQhFqyWUrZyy55vIiWgFigNFl EDxGWRgy5oLFDc7h7Z90buPR0n14Yv4LnUexficxzJCV0uR+sJOGhGT8O6eMeKQBCJYPr5vO9ifj 6Ro5nWN3Hy79OIME4cx84WSeEwflhL/pwD691YVlf5XvnrbpZPCVNSQSRzl3pYtrL/VdoOI9g24d iXIw8TdG6YTQ5DJzdzvV8HBzcIyE8ENvARyLR7dfmYN3frfUEpcJoiNxKzvaIQajAuPQvsan1irk L5mvxDDIcFRalwpYLm6vKGJul8oJBSfhUXQ1XGnL+6SS8Os1u+lvUxUUqYmJ0YAbmnMPgpE/6FpH uqlgKeq78YrmnB3vE5QXmjy8/CQJM3buw1ZC5BjJijOLHwUZvDbNiUJAgWqYe9eC2uqLM3zFG3cN aNy6fGjo9ZGrjBfPlQZCYYCNziIw6oyE5RtQQs1DEO809Tq+sIeaVdJGcxJ79ON1oNVFPg1XFcae bUYHpWwaorEX3+pvkonAKgWSQmYbZTgtlRfkL0uWqT7k76J4xgpBzEOjie49BzZtLiQTehPjg2+1 y92QZJe/1qk8FPATRJe6OCgcdU/Jko7iSw1G0AacLDnhbWivoivqsal25Dsv+8hf8mTsFzOHFAIp KTymlXkXFWVd76Mufha/nxTM7nWimrzoNT+z/BoibP4QUB4I6YG65sTNyddPFkIT7DVcolmOd1r7 1A233wD5y2aqwd1UHy//gDSO3hQIbsEoS7s1Ouj0W5t20uVyO4L8Rn8d8iKc65bPn0klkYqTQc0k hcnPQGTSORX8mbNAwy1FWqnFQoowh3bvo1Wof6Ex/e9iN7qkakDlwpkEusY4A6t9bLpExPdy0lPv yHABmM3fHY92AU7BUulTpp61cuwgAw+ud5paPJt+CcYZTwNV102NgWZeXgcsrVB+YNsQWL5ZFSwx b1tW3vbpzUHlHL3FT/skY6BUO26JRUyhm0dQGneRFr9MWWBB/H16evU1WGJterxuNzl9zr4ViK1q BC+7dO9XAFA7JcZ1lvOqDU54yiiTpbXU3Y1lmz1P37+tv8JUKfBnsLMzQUKu7IDRMs9YdLq51UKV nKgvT5c87xytNkO7S55jj7Kzn0v8d3wKmfq23p3+0fZawyV9VkSa7CUQztlTzj82YtdavA/GjxHZ gBfGUOSoZ26P/BcdXzjaozXGyt4S+1ZAuj/FBy44vV4xCK2aTh+gAu2w/d15Uixl6g4YeUDo3QnJ ntlNK8X7imVBbzVVPW3Gv7g20GNfhECl1LMqvrqpXBlnhwbAWATFpEZ9vjjnuzB8+CrjwSp1NRa+ E9GmdppUVKT1l4u8NJGJE5saxbel9GycRD/8iGn4frqIVmDDBYafK3PgzRwFWy2P6BzVynval4rg 8NKbXHRzCRUIbotTooGaFtDjDwZx4QNQTH861tl28dPTtJ+v4I6JUrCt4NeA23Giv6wYbkHmlbEP SZelD/wSwdmAW6OsWX8TAZPKpJgzh6u3AJmpkX2Lg/+J4TLMu46JwlBJ8Crwqig1wtG0dHPX+Seb Zg+YgGzTgAUc9xYT1lFTbAHKG1pNy5YMJ9B9CXvFpa5ergRNP7GY73OgdYZvfF8IiXTxt6WRB7Tb 8j3Yohq/2FwWuXtdy1M3XmRDiNbRNnJlhH5E9X3eyn6kFkDt3e2kjvRQunGoV2zXzmZRa9Hq0Ft+ 5x0+qJRD+ux40JNQsw4mXdxP2zT+zcWtoGiUqenyuWXgqwJDxq/3AtTlGDscnUkmYxI0rx3tOzhL fmjOEIKMXkaXWK5idNtbqUgjVVZGi6vryBOsSsjNFUSKaPLbblWBO2mEVNa0PQlItYOEX9H0hlB2 nSp6pgfDAfbl45W7hWvgXzNYOTVwAKc/K0shg6X9eCHhz2qA5DvFqxYPKrzjcggPgk2e2j7Y4RS0 yakj/lg4+Y/1awIS2sHiJQSVMxFG3pSThvUSZwKDaGBk0/g0f8ZIMMM1eRk+yyeBd5885gdoVBqI JYqqGHokNPMZpmJE8+A+lNQwCk94vEjlx+PIVlar3pgKVzivQSMD3hFIJaCVe31f/doLNm2VQQnG R6RGi8W0tmRrbOv5iXjTfFLtf/E+suBJ1iEvGKaFuQVMx9GyL6jw1fq27J0/rcFVUAaXilFvdIBF OSL+Muix+TdXHmcWDMYh3bRS8SE879RolWVIRIo2aBi/Y0SYuXCBWCutwE8qxFxVUzT2g30mUgZ3 SgtuIl0GRMMIWGR9whl5Wr97w7Nb1ppf7qfqb/JhPqbKC3CUyqqMFlJfYgHrvZp8W+sWjWlo1H0A ANteKR/hREKWBWMqbGJwYsxK3v3Vg30ntQn81xCNOzJ7uK8GTc1weyUnlZzNMMvyIH+Oip237Jxl u+8j6LYGyO2yt3wTQ5LcA5RR+FlWOQjmgBZuvKK8T/mKNqvCcMXhTHuNFD+ixPxLxCtPOipefb+F 8mzVvCQgw44aRCJYP/oz+/n1qCWOMjtKGUEoZ32gKDsJe9AGisddYz3Lm+UFqotMY9BrR10apSjo /w05xY9Ogmdmj/zLrNHIJRZfBkrmcZQfmB1i2P7PF5uSQaQzC6OP9nDoToLVBxQsh6+R+0QyrrEh 90x/gKXKWxTfhLlAWh4Ij2IcOm4xDTz1JFP1czw50tbyffW9V+F2DlXdZxh1wjpznVXA8DW95Vj7 4T29rMF7ypgqiDouwLSYhqD14z0pCB5fR1GyZLeYTyNdPc+Si8kUC37z+VTayBWCqYFDw50sc4Ec 99c+D/JKdRunDH+b2+S54NghqtNxZpEN8TNHuJ/N48IQp860t7NhM/ndbDSsodz67STnPS5Z6K4v 8iKoKcnLmKRiOUHaTYl8iQEw2/MP3takgTQ5no0l2Fg9Cf2y5Xb1HL/zSKRi+oNccW1fVOEg0vaD fqu/O0CQKSFonPTswSE7Pzol2wO7Yw8tGgO4Q0o+tKMXNqD7DDO7QLqBa9HUHHAtIb8TsacetxTW GgtXJvENGY0fnhnKCvpMlKl17Jbl9No97vpxgqzyOFRSTPPcrR7SDm3wkqUOMoo/2sgVLsyG88ye eBDJbfQSvDM6kIE6FY/T6G9X9X6Be4+1wR/25RUJzNl2m3TqCicDucseUh80G3IxHCEoHMMkV/c2 WJbs/ajOfHSQh4eVBh+SfqW7ufUrvfqmiDdJlJe9OINLTYCWJIFhAbgH75a45rfjv4EUqxOASNEs iTkRuDNSQLb2FiZtYIegOpvvGH1cW1mmahZHW2CpRRT3hmDYpX6zUp0aYvaNKLf93tJXLz/njT6o Xdm9o6n1ACiG+qZdEd0cqub+mj3aR8x9CFycr1mvn8zc8M8XdHKADgHOWWCRQ//4UJRLhOv86hS+ bROKE4GvQkdAycuZ39HNY9F2My+SezvHEC59ZuVGvqZ+f/G83tsxKIc0B5SkpjHfZmOCPvWmHErs ndqlgXIXgP0B6313iPTBrDx/zvO+jvPvZ1UGFn/+CqkCiLJDGluWGMYJ6vIU2ecZZ/ahOu1cyWuw VeXMLMFDPNFSwJipq02sI3LTiN+ygCs298v7mOHRUvd4pjcGyvg6svwsYfhkLf8GJm2lsARRSRj7 zy5W+QZBGesmTO9YxVmnV055lIvYclIaxNgIOkpf9xV+c3gCcxTFxvu9S3xkAg5JVIQRfxpUqtii s33lFEqZ/X9EYHkX6Fr/Uv1/D8mSRhaet28e02Qpinzgn9Th7qXYXEXiaN2YRQqUTfQ6EFM9XM4W WpLT5HunEKYPzsU1nZeaTlblCteWS5XEpkSaUQoW8WiCdtzfqQpwZIabaAcDZUvPwDIavaT6VYgX lhP1kD2iEQJnUpDDnem6lXSNecvvn7Je8ek2zseLdgpdP2McMX8bcSqcPCYSzH4psseTilfVkI0t jWXJMlV1/6YYAixFF40hKgVS1z5AvmI/SsMW07K1heKF0XfL5T1MhBchGicASxQP5zPNcvvoPDiW rhZMqCefALeZyiu+bg1g3utUeDdjKMoXcL0TKTKvXlgoQwAYeoE+QQG6T2n+OYVj9U0yzA/FpbAG 6AAHudrCh1+3JR3BXK6T1NfR10nUmYxyl1g24RatTWeO6LRfjK57q9F/ROI+F8ncxoUl+6U789HL FSKjH7B9rP4HCq/C/8VLv1aTDD+RxJqOoY/xnH3PYLAOBJwLIRuad4yTzMakZN+51i3NO/J065Dt H5d90++vnPmquJUynNdYj00XGjMj3PhMS/Jioc+g8NS3FyA2KqLmCOc+OIo8eG7dPjEZR8SXpTJT gyWtY7w8czl4SNIlJfr/fOj/yXbisF4UaY74DlsxkXnFBxo1msxvkWqzzC6VQwoCRqw/WeelNZff GRYyMf4NZYI5ZHUjVhErQm36rxNbswqy6enDES/ml3CQaZbx6rans08k278vbK+riL31gzuASWX7 k3ieeBIea4r8pO0oI9FFxMWRQOv4Ge1GWO4PKhBR9dGbB7eUd3SinNZ1hvKScqODNAAd9Pus3F7w RpYX8ECkXbVbM13llmv3Pax79S9eABmYHvrJi+L50TrIqPsPl1G95BozWmfT5CIlHytYSMSQW6c3 rV4XLBsaOU/9MgwJVk8EYx4Eznkwg7wrHgdr+zIibqk5IUYNn9uF+qwZabdKDKJp+/Y6xzyKOW1U 9I+CITxsrpAo2NPZ3Bvt3mSi+QP3rrktRU7T4U+EQH3dJs9hws03KIpASuZo1g8XDxGq8XROTM7e wWtChh0wpiBxoS9RtiMNW0Mp/0GZ3XVS7wEwpEVWpwLZklmr+tCro/lqatNDKuACm/khiedVq/hj 500KraQwKZFE36FafKmtEJsgtaVvgGbjhtgYT1HD1zWJubLKXCP6fd4UyrJGJx8ifY3zKovNVuAx KVjZbodgZGrmyLcv6pirkIjGE7iL2E4UBadLeEZxlDwRbRcjcCMeP/ZuOPKeLC7FGKsjq9TYiD7r N6ilxg/ricvPaHQq0ZlqNxxwDA1Aeca8WuZy0puMrYeSz5lm/ypxE7WFNGSQcPqb1ZoqHHpWe9AH oEXMjZTiY78G/leeWYcFNY+Vux8DQSolNchwW38NW4nIGLVvGOPz3M79QOvHzrov3uv5Bk177Gdu LTk79ofrBshOZOBGJpq730yUR5NdJu1Lgezt6AArqEdq6db4kDvJ7wmScDLw5hYwcLjp+Hl6fNS5 MgtS7NiiDdyiEpqT32elqeeOi+38nqNsPZOdV3pYIxQY3UNnFRDQcZmcxVhpV/r2MGDlRMW8sTXa zq5JLZrid5iu0sWzhbBwy+YJoZRVLJ/AtKLJmXSWAIAfiQao/piujuX2MI9U3Pt7d6v6Aprv5II6 VoHT2+GXb3eq7BGRx6D+yQikS1ZqfXIFs3yY45AwY+B2HVMsOdC+s+Vx1KF5cISSUJL/D6bhra9L jd+4aGZp1XafP5es4IrIz/KYyl0t9H9zkAmLSXKfaaoHog5TZrUqdNxbWDdxOxHcvRuC5KqSEU1t Gux8D0pRevCMCMvdKu5724nErRJ92WzWxJzgE4872dzIq5yJXfTixVK6SeYe/4yUsyCV/yWlLBUu AkaPsO/PJI5hH7nnjnCSsOwmfrJaLt3j8eNK2TMLXd9zbTLsOmitxZ3ORH47qZItyQPhuOGE4hbZ sTAxX1ORJ/kiLpudqfqCyoMuEdD7uXphsKRf8BVZ2RokRXjK1pacg5moktZuZy9FmuZfx1O+xh7t ph6oqZz29bMugdEwuktC/GVhtWC7XmCoacGpJBMr9ngGVI1Wvn3mKT3GoSwmVZqGJqDdmCpLbO1v uouSZeECZdb/6xCTgZbhvxUg+npM82U0Lczdh4AZfyqNirvxe19V1+iVkQNx4gBtGKXDyuEzVh54 l9bVsbDbe01x/AuNysSNMgr7SVcCUMJgl6oN62zZdnNURskP0iBnWTgToXS7N/537ptXleGEg6c3 k+6qIQWmSVbu4ZXIUXO/sVhYIEvgF/4Ul9otOC29b9yK/aj+pAnX12J/mxahlIIXSVbPbTjeVoAL U5lUbtkTbcD9jAuTXvqkiT6EwmzZxorXtcBvVOg42AOH6v8r9e+dkjUNogV9WEEbod7QEA35JRxz 8xXUG6p73ibv5BiPMgrM6wuLGgXjXaP1Y6beSm+RcayPmiB+NVfaSK8YX0kGvyd1mLbE61UkLcv1 hC/1ocTRp0PgKMvn3LOZ76Sjd1WEvK8b34D7WSSfiE3Hm/9i7VpLHlbUAnNZBopsKnwlfFkgLh8N qKcrIrFNnuwy9L+ogefZpexQH7XrNLjYbfVctJXf1QMZNT5VS8bV7rOmz8VuZL3UBF5h3hmVfnWK ckYfeiXbpvgErgHnJd+9U52kpplC1lMsPrf75kTraN6f6SePhEeyxirdwcb03dYNccemdXUd83eh KpY1rCL9fN0q3EGae7/Oga7KLFwK90cOEWIaZxBqfswOcLBAO5m3OT0lTFjnAOfRsgvpxG2R1Sos vkUUS/AWQgU8KLpWsZa6zzvaoGPB74C0BpnumIO0zK8pqMQah5LnvP73DzDpjv9HJ9n0T/y0D/H7 AmV5Qtn0AA2H3IaDZnfoBBhWynXnkrCyH1WA+GB/yVEuYBrq8DrLiiSAw28IWygJuN4Uzn49jthY YQf6zlC7IjTXwwDcN5YW7BSZQNZfSNZ7QVzrQTwvPZALn77GbqlEhQw+DVlj78E0BBRbKRM+Y1ed K4E3ehehMBpwoZ2TdKw1JxgR5LZie2lbnIc+aIUJMVCit6mS7dRDYNZtkFqn8X5rO1i9vtaMD6pS iyPKBehPUDxDFEBcdngnvykL0EWHXFbkKpdx6X6FNB2F9jR+M+0xfO68Ym0K8SLbxzMfHcL+jTfY lZmn3ityxE0m03p/vCOnxo9TceAL+VTUmRjjsHzNTzeMJG6wdEsRSB/bpa09lz0SJEF4aXhZ07OH tLoXBj3pCpAUWMYKgL+H6Rlf15SrrCGfIqJkKls5VQ+zSvq57HDEGOdYbdxrnAmIgMic8Lx0dnh3 eyuIutNWXln9CzrmGe6k5/KM7LK3FhDuGWpaPsC1Pd6HG3KFIf/AsLKzewxbuIONdITvFBH3Somy LSJiFX1dHemWz9z6El4sCitqSxVHySQd9RZ4kVnKkijCWBXAmDmEdYux37M7Ci5HGUawrbhcxg/6 7lMUoI/Wit/8To858g3BX5yqB+hLZvV4yNm8P6O4IXAgqMYekgLXjmzNk+LvkGT/fmSesQ3LzPYF 5IWf6zM9M1X/2Tb+GTrxDUZxU8gTQRSLBTuq/r9BUM/jQXduyGjeG8qL7/dMTQYhVx/gfW2HnrLJ aibo3Qdi38YEZ3GbTYAMZKZmpYIAMEkMneezt3Jjf/3KCegf0/t1bEQfJVJ5riVEuC5gFIq3YypC sJhgBn3O2vpqsAKe8j53P2ewjVbkMpLrNDXkBeOKoW6XAgVQBAbQxytTGlj5UpfQoBYKEfhGb+qr kR3POrZIOJN9/fkTudBGHpxfD66OCFCXWCx0errpWq9ZYyvRO/SvvIQs7m/fqSqEN8DVG2Oz89Hg dSUzHoe61hE8xfNR1wESFwlHKv5s7JnBgns5oyDWJARyjfvKaHKjPZNDEocpqCVgOSjFlMWcKztN r3OsHUKFcGxt4iJirCe1VJ116tD1+ju9CqKBBE9wFM6poqvD9+AKkReNRAQmxA2cx+D8AI9fZLo3 6NLH0dTYFBzd9Nj3IsxVjSYyXViw40dA8s4fGA6+dOpyBvP+52TVCoGOvHfygbDoz4Pxoo20XXki 1be+pNJNs1vUXlS9UtTliYj7QINV+9reRoIzz9lIvtqlnFhEmYYSOz4jrPSTplrvySDYy9ZcC6/d MUsL4eawx6sNQ0+Tj5jgr4SgRqet3oeu9N5g6UcINPgfuhEUR9UZ/20Ou3Q4/VBW1ItzIGbdIhmD RBRaqi7ZMfuq2qBAwNrPImcJYyyx/J1Xwe5l3lSlGutp5lsS9E4DgMFxvWmc5qcMNLLpXJJqz/7o LD0rm+yJxYcJBC4qlX/5FQtjB3r3X5JUNUPA/XEbeBGCFHhQuer5qCFfPF5n7KZFdTSYGJiRCu+w T+Ic7+r0Qjp/o7a1sWNNY+JC8gNj696DTYaGbs9IWn15FukNsLxHStnm8zBFXtVx5ATEAHco1iaF XuJKjbt/V7izm0IQmMji8zUwtptgKYMb5Ha6+fg03U5Zc9Ik/9n4Wl4fF1iunz2KHU/Gd33QqphO 4DnTOYtSit5eYINZ9gxmB4u4gySPughPl/faZj3xSy1jVQ7o7UrfyCvOA3gt3/9SFb9zZ588Ahtq 2pikdBcay6yO/szHUfk7LwbwhIup3EaHDXFsv5j7mZBkAThX5wvdiuDyv5oOH/Y6ydMuuGXGz9of w2iP3vXs8enZlD9DOAUEZ3TzxQVg4YvoGTIrz83OUPPXmzxzxq38Nqno4DEhI6MsntZOfjhcxLbC cyWfyyl0WeRwO4ch7lM2eeIg/n5tWCfOjjPW4ksQTvlQ9KqjpnF+HCdLkbtIc0ydGHsgWs+N/LgN /WF9gAWnLLFlZ08iPWSKswiJeuVsIQGWCh47OaNKlsXC1IvXfPFBKby0wwTr2gDcWqC/X0Yg/lxL zD+Tjzb/ppEXCus7Upyc7m3ah8pZlzcysJvNLBUEyEZ30emxS25tGq5BSnKAOfvXY8SfCK4IzH3G +sEv9QY5zt4PjZ5LbTHrpAjm/ChjJ5VZ2Of7sIsQV1uti7hKRLI2hRqG6sjVJ5khyM4+DXyrGVtA CSsl/eQYDJ1XU1NiSMY+gb1h62slR2DLadnrXv8lA1TnuDnQaFNx8XzccvbgxfuQr2+Q4pz9AstL OeIi3rGIcPGu7ohQBSwXmymQigCA+bF537XObwwbbfbQW+DjMZEUDn4lOhVGKI5K/OeGnsV/WsAZ KzR5u+T4NAQ8foPKE5LM4BOJAIMm4z4Y6eWXL719fE9svJ5CQB9i9m/YWZ+jloKyodrJ1CYj3+kF CA2fxBTQUtvhc2SQubgVfYonHXkuMGhJHNZtCCWnqEzAlL8v5VcbMcWq0aB/wNHEnFUXMYNpR5SW KAmH7x8SaYVoN+pmm1tddqVYsobl75wYHksIUAt5/l9gSjN/KzE95T1qH5Uz68Jn1CiOKyPohm9N ScMIkydT4/43qsQu/KWqtJiiS0BjHbbvX3MvoEpsDcGzZQPh2MuUpmqnp/K0J20JzXo69bXpS+m8 XtjIdyn8trj1uyEDZiThUIPzGRnGTWdJiswmsfc2MT7IMznK6RRqSRC9MDqE5TFuPioiTwPIKvlq 5Z7glRKeYpsTEXs3K3l/sfvZjf6hHMaa3Y0RM4jfRZ8fydj2dmmbK7BzHsuT2B0XDEcUqikhzz6j hs7297ta+lA89wDqlYcxBFhouVrotbyXNe3M50zM1sqYRKCzTsapFsFsveB/ZPSiR/9ZhSL/rSvv lXw0hzabP6hpFO3m/IBmrpnW5rNc/Wqv9B7hvezQTIwouEqA3Hp7Q0Kz7v8KKhAxASFlqUqvuauB vpyvXdQnv9mIM+YkX6RZTwLcWAu63M1UNDX+SSX60EO+clc0V446jzeonLRQwmZqaOZgVxHuyvUP sBazGJ05wOrIjSYNLj3xpYsD1sp/Lv7F7Rby1BhJElLBCMV/BjRhnSYMI5+SX5dRXOZp2B/4XnKZ GvBXSk1xn/VDVdmHvrrWE8HVEHsRiL5l13hLwEkgqRJvSUsYso1eYNLqHkbOEptaS/0eM9PA+AlM w46X0FhvIQicdV86TBc1pJ6NFO8iqgOy+0aCfEQGmFjzwZvZcUtEY1Frz1EnwWkQ3Et5x9mQxj1y pdlHdvIwcnAeMJL+LQ2H74vLtu+2TVZBGsD9BVwNeUT3GhWjKmeHqLrP9v1DLbTHL94v/3UxG93+ r4Q/FkozND1IDvJXZX+1KoWgbwP+DKjDZdagMw9kbKAHaXAcTjpvyogXBkinIG017nmU1Kjd8Qpu xG8ujRDVeQjY8PTEmC331pyMx4sgdb2Ubqcb4+58thasHoM11ZM7xa998oW12tO6Wk2jHWLpxBNs NLdiZU/zpYjwtzUCJH+3T7gvRQB0ciVDA/q5Hpgc6+WdcrZrYUC9foj1IploEWAmbQ9eYhVMGrfC tWdvnhcN/NU9zT6yIOJMKFFBHqfam3tp5tnAp4LvgE74iDR3n9IEMI7lLBg5O+DazocwvRkGrr3U geawn38bn5iVEcJMv6jAaccfrIPX5R1fucUQ00/9VtgiQDBRyndpF60aWjvzSYINVU39AkwoO4TU JUz7lVEL30AoLukzgB07yqTvTaxF9F7mTaV2Exfvu4rqwgyCupZ1EtuhA2/dxXXMLFiSll8QGij9 6/G55joZei5Dld3HnqBil9jExCsAVIJEOK1BlX4g8Ga4sabrfIxRFNj8/U/HOrIxofOhJcnoVTon w/jHPSxCP7rLgb8nxdfq24SCKmXQ53fMYgv50bVGDVT1FdTJSI8bUne1D/wRwFGRzATsE+VIlkyI 3vNqARThSGXJ2EFvAqwy8aPqbm4bxJgsPSjyU1X5F++HYhME7tVS80dQDzBlzpsCJfz5b/v8GYdN aNA9sx8JSkDvsMZk2rrZymZWWLIJCeLbw2mz/JEUl05SZNBVg9oJJ3XdZbQWlj2MNZJXYv/AgbFP TprgImyJvjMQ9iYkJV/BE5YboXRiGxzANPDcaKVl5pVoupgNk61Xf8yM0E5qUG4RE51Ur0O/Lksp 7KHx5HW0Pi7/IQVtRxWqvOm5Z8ZvxyMW0g1vYCC03dN2K4McKna4AR1dpP/sM4n9GFEdxUbCes+7 EkZ46RjPG8SH4wTwiX95mzekReLxOH9oZUhISp+HDyLcEsJJE9KP5R/dactwTng6HMZaHBrH/DNl SwuL4c92lDfcWmXlTqlvhI9j780nr9Riafgpi9hzhIkQxO8PEUL6ge3ircE7AyO/eAq04x7K6x68 aIC+ksrc1bBcXpaqENB/l1dg9iSkhTBhVUyg6DJ39ejtH9Sk0nyt3uKzNT3RZ19VQsTbPZsPFsvR A84FM2kbX9rADqqG+NisBcGSL+6TuYLQxLL7SZZplrcne8vTfOp+5KOqhxUvyUbAbz1oAgwMojG+ r0jJTH2QZ1LJu/C/ralb6Xxi4x5SGxNIesT016WXpW3Zj3GGk3IZXk4cK+XwqTKdByjvzIguEcEO Cwv98kcXY6bzFTpkI4evh3ouVNa5/eLNmOVGLNC1XMT6RAH02mSg3hBz0hjH9zB72tekWTmQPaql CyIcNn0W4NEMS6LRfjaK/tfn31IzNrkrf+qm5mXrcw2fj+z4kk+K6Qk93BVMJh4RZ0L0n7Bfv5CH yxEbHMjPUOVYyF3Tb1AZ1lk2pfD3FTa02CIL1NfgxvtnHrs4DvxSLfAy9l8cAX8CHm4lp5leESdx QiTtwsz9/55bwHud5jGnOJCCVyb4fz2ItIPb2QQPUgwRBKJ3HfTiHGYhrTdeVKmc/bzW6dXcK75H n0glBEg5CbRtDGDrcKS3IHf+O9G/4BwctQebqq8HsUecL6GF58WrFe1ZAVjfHw/4xd5JIlEKTIIL iDnGQPbwAUa2YBUMDKVs2bK+Kq3Pyj+KQT+hzepv1THPH/bwWHrtYxpFT71IsejRna20QWeMRJ19 50+a3i5G3qmIYV8UD1y8D9jBQXO3naWB84BWYdYpuVlnbVB6qItnVDnYLU1eskMiECaJAn2/QcG4 /0GVgNMcLaHV+FCBje3D7p4bQSKkGAxNIQipu36pnT0yYSB551mx9W7rXRbeoEg+fMXEhiVSV9X3 BQIlIkZ1AW0XGGEGzNS57E6rNjhe6HmAbJe1Uk26QHEuqxM7RxQfnXO+o18FLq3qMaqLiBraWR4X s0N7RXbfvFjguWB3Ru5eKZCCTZZGuI8Agme+M7KVpCzoGzKX7myyogu1ftCEsuOidzG9ZL1WvQAB 6+VqM7VaCfBBFSAkMPwcVrawXRQGB8tzA+ROJLqxahoGzgHwmGanbtacwDTFHGrIkboiG6WS7E46 KnvbvV9akbiS8g0VK0MZ3oQMiGScTVkOeC5S8ttkvk5vJDzq1QH1t819qynZLf42fchaQ24wZcZZ O5LQKUbMKdVZuGQcjQMpVEVphCtVY324moDGzkntxaK+Tk4U9fHu2gq3and8RKrWzDD8GV7b5ebJ tlIS4GA7YrPt0R2W9OJNmIXtZPrhV1WxrOa5uRYvqpjQwN7v/1Bo9jMCiTzs5DNCTkkgkD8dYi20 SysOqZ8DMK0rQhNZiKQVOxqs3EHwPhUWcAlgdWAZqvOFM5GBwPxPxwq6qFVrvcdrYQSZpd6ty0hj /4yfLmFNhSvERTr4BMn2qR0QbHPVZSJdCXq7mkDofvMHQ3OxmFdkJ0feCdKQ8b+0ohE26M259o7d DY1CGFscwhIKRHJ2lBIvwfdkdUwbegLE1EKYkv1SN01gaA4IocSaS1wRUFNmAlRcCuWFajhCdXPV OYWP+3jgLFV2s3SI1xBd0IoaK2B9wPTAwfRLF9X0dgbVHWCnpXYvwCvSsEMqMgpY2Duv22btZqPN 7W3u+AsUAKhpRszhmCPVxTCwtah+REJOXOF05nyGoSF28KHd5x/+EW1LDEa5WysoEl2rStofTwkK IjTKAxEITHsfVIylhxFcLFcoSCDTby28pzVOwXIMf0sfImVGA7dLIqoVe6JxFLCOLkF2O62cy+Vn WRQ+m/vhy0PX8UmhtiOwMbUp8OYYgy/w4cPK+EpGyyc/epqHpNSgzRxrpk2aFIZ6rmNQRFkrDYlt nIvExLgeB22W72Q1EymvksnTJ9M7QFRYICdEjGu3ntxY7YKDO6fxkIkCzCnwvLOuzT8r0/zzoCkL 6ZLPiWO0efMfcYOlnvCKs7kX2fkB6YP5ft7ZvDCEzTCkHkP4NuiXiA2mVePFfWMO/ToiTqJXFLFj J51Jn1hf1uNElY5iWASm2yvzOBIEVLmaVCw6oHa4Sz8CnWuF0TiNHdL6tjwA3TB2ab1Qpyj4zvgY YSuWHl1tIeAtWfzrcRS5Ve51PUK1QHL/mJICv/k4EvriGT4DoBuMCi/3AvOyTBMbyvV8DJSdlVUF OdZpi61sYk4FN04F4EpU4jUSRSNDHOajqNp9AkRXHt8eQkwogcgiHAl0VztY7v+N/0ueo8dqLq2Z tDGdNCF4MYlu4NuwvfAVvDxAk5LfDn+lmrKg4yssHeCT3PObFpEcJpqQm/pb/OdEi79HUpUml6pu QPleEXu+qr8V9yf9HaK82wpoNuZv9GMokU8vGP4q+HTF8aglX+XaLGqxN9m41KNUYDsVDKa3lbOK blrgceb/qLuUi9nfVEnqaWVDpOnI3tUhg/0tLiBve6I91i6qexuwDaxjQUEWMlSQYluySjedJPM6 dsDGxGA2GVgx0EZs4uoQVZGwuEUeMw+xOSeAn0mZb7qW0NmJjPj9yOo2HxUZPWOBhV2oIxk14r3k RuXTbnj2UYTtR6WyfSiiR340k8Za84sOMOl1FLSBRJX7OUN3HgyPqEdvNMyHZEEw1SI5tbQidJX5 O1gdl1V91ytyr8/EGuOLtZF41kOBV6hnvCFGp7p/kdn1EkfeLg29JIGz0YxhaiuBZwGoghvN98vt jynAc/6kOHKYQrSnOV01er7rzKvQFpqGY3juqbZ/nIuYM4qCmp68Vvi7T/T1BfFlht893KpjYKup bbwBDyHm5zz7YQmc5ni0y07bFASfURS1I67r5viKrCOSV7kEep4Fjo86w5eEwjUb04mQfEIt1v8e 3TeLmBOsChh1nw7hBwQDr2WEusKOMJ+/SK93vRB1YBBKQM0SMcRFy+kOdQRX2ezivc6SUCf937P/ vbHI/1a5HJKTsPNVUYqEVWBNiZ6lScdV1dmUQSTjD2MX3sJJw93KQmd2d7mj21+F3cBIaENXR5DH GcqyapNdNiz4rL+rZe9dtoZ69uw1QvW9fPecg+1Mx2XSq5/WZNiA8l2c0uT4KwAQX7tfoKFu++MQ XelV/xtf+QurtCknP47bB+JPhjVzMl6jk4rWaI4UaNS5AVqGBm4xGhzj2XwWO/1lXUPsQFAJfEX+ 5eHUo67xperMREqgsDJMDkUcT7Z+/loiQQnTVFQ4R7Ex8Ou4XWGRxNkocPxZZZbwal35hWFbwA1x Omrf9Ds/1jXurcbwzZcXBpksX25V/dzXSN7TeMZSnyPGPIcXPeD+hp1AskAGtcegP9KVRXKeW6ck BI44YNrUx5ZF7Dzv0vY5vNh58+dbrJy5epLOQ5CV9H9LBKsEi7MU8DunLAiTemhw9joWke3lao1v YpKNJ5JnJ0gI7PYfhUJ7SUW5l7q4tpusR27Bb0vXB0SpdE6AwA5eUE5yqVnM+onBUAOii2Zgfaz/ nDKfd3A9XBp1zSG8EcewmTriN4vsckgtX1JF3V2pTCArVp+MFzCvbHXq3rZabg7tuqhSAs6CHngn DHhMLH4ex5AA71rqe3MXR3Oz389tT0Qxnp0Ti8hJ0jxcjnII+7rxdddyFGbXDdknHAplk5iMFK1d pkLyUaF3VzfulJkR35X20gqunNh94LE70ITUzmKt9xOOMRL4YuZa27XCfBCmS1T3XumEdu3tc5ne 7bOp8LIuglaIPjw9ROQACAaWcneF10zs2axarmthDXC3lI/jZqPW8FCp/TsFDNpycdrpgnmvO67l ilyjkdJ0uvRRFWNTaNsCeG2kLDlpSMOF6D7HwCC3c7OejMNkuviFQtqLCiXgId/raG+2r7A94k+9 A21AeL6SbE9x3fvn7wImBG1MCifIIsTJQeiqeApo8V9Dt9DPsj837isvZ6quSPWsSrEM0MkQEjf2 nkS3mv75NBVf3pwTeZxH6ZrAFTMPgrzedtZiai3hmgz5be+B9Tn/L15Ijphybj0V3ddZ3rj0ZqI7 QEqUnOhHRdLH0UikjOUIFlNzFfEWbmcSGWgAkPtKZ2Di6hSnzrFQ4kUUUplwGlxOtH+AnqRRJma9 sviiuegFvR2zmMtCnpXHCKEcny9epHjhkLrVRXb2DIgtRa+Mth839QtW67QXv/s6zGItJIaBoJiz DNzhhRSuksP15DWUoTN4W5IU+MV9TVDhGgOVGXdeVea1YVNfGMUQP0q7oU8LYN7qlHKh9S0rCUaE 35JVblBisxhkawo+DUWdh8+klZtIhwQYKN516pAylrnwve52bSrUr3cUXXNTyy0JRRYcNVb6dhDk u+a4tLmxYS04CnHn8qvsY2nCEDEVzzA3cSCF3hc5pP/TYXG8jxhxVOwqsqshUFrAHRsW67piGX1h 9h2ZasurM0yJUVjFpABe6drqgXp0cMXyjfca0Li1Bejf0XIl8OaLOydSL3PGjF9pMToHJGJT37Gh PjwpSB/sxv48TFUJysKu3CMoUCuR/Y9zubjKfiX/knKyAMAxjkfBthfA4gmk5jydn1iSS7sHWSB8 0ZgozcztsjdKfAlaNoT2MtN6OFmj8bVcNMopWwtaubBWFthviy4UNAJYnB3Y1A5D0glIx5E6729/ MztEK37yhlXCZ0tQDiuV9gVuyv0ilU741IFS8qAKQN5L5QpKgZxsCZSEagea/X4w/21dsvMZdy5B X2txQeC+BPePCbiDTXkCODpB4+LAEVLtrOdkbUyq20OcVkJbrkjTJL6qwKINdJnIEaXZol+kEajw bYwIDxp8K2WUBEu8ZFVkLKZhh1nx0TuGA3OhvVy4AKFut1EAvuEn67uzJNARRHpY0qtFSbFRuvg+ sOIc+VuXRShDBQ+m6gEdwVF5Y9P/0hbqrK4VfuRmVGORWv9sKYUs0AmPrQdC9D2ELJlPh5sM/tk7 dj0T0Wprm0gsPMdcdHD9ydlKU/o6jAwJSHOk11EErOXF69zh3nl/Z3ILAyJAM4uLm+iKk+Fz1uWO WXCAGQNR/gPpMnq/8+x5F6wrVy4SF1A7LU8sz49qHyIYo3QlYcwe+r1LThZP3ulQUXR3L5Un10m3 9Y/4FKBoZVPIfMVhqjGfpivBFTS5ey1CjvunuD0NnpRpklm1l67rynxbG8gkjvu1SvtDzjrIr60F gELFeQ4g/qajmaZ/ZjO0mwuen9YhYUYPiMyOIL/eJBHtecvowGvMDG1GDyBAcesPYya8wIqmemnF pANjJY2io7No5SYIN38WTna5LcdzGDRBgYFQch80P6DM84Obdf1nLnKVyF2epWdFpagm357criTg xfc2e7sutq6ryCm25sjkGJyarhxNHDSqS6ImxKaxGy2oxPje/96PX24iQv+bKT8EUrI7r2pDElb0 3zkiFuIfmkXLOSA6uCi9mZ4Tg1DPySHpBLvjx0qB/KZyHyICho+l8sQikojRbydNwfO58hsipV9q FnX03u72L6gUhRNVcxi3cPA9inrL718qIGqwYf4vHTk6jLpUOW4sRNYpViNQSNaiCvSSo9jTTF8O ipufHOTjGuzHIQr3z6iPRvvIbp71NM+XH3Tno+ecOCnQV2nPL/mxZQ1pXojy2VvPCbWpxDZREuRo hTJl3BAxfSw+NYmkrSU0alMRSx1ZVNE3yIom49um4+XIJxjYNrGaW50eQDqccczM/FwVSN5LYHAG 9iVmN57fT/dEydpQDcCDYhEhNnYNGbrY8Z5+ctg/5NpxLUu9yMgb95SY46fFOitKUFjt7vRgcCqs 3wQ8cjGCUTkQ3KEI6Y5NuUOvOLIfhmOXipb73UUfQP61uKS37q7poi0gY8gg7ydG7KbWMsIJzf/5 cLxPGHniMyiiWMRu+GEnApBa0AuUnvrE0K81TQH3uCXc5Kyl3vZ5UTZF+mdM+h2QXA9gAimvdVh2 CToKpAClEF7zpINkWiL/IsY0zmi5QGpc8trbyRnqe2Zy3iqiXF48Is69YVwJP8o6L55nQ5JQf/DQ AlaS/i43pF2bAi4Qc/HnXkIbfQCL67ej1dP7YoNaD78b6wF+aHbW10DyWqKi75sV1upTOo/poFLl KQw7Us42a8FZKudCn8A2tkjEsvL5DOdpV4GUzTxJhJ8IzNzAOGLUqPsr8zK9ko8MP1I/PKt8mK1c cj3jgvyO05y37Ybw/dBNu4k+x8o2OR4T/ZL+AR0g9RTinnL9jzTx/DaQYId/YQY8+pcB7Y7AAV7e rlEO7lycVVYkfp+yuUXUP9qzger+eJt7QYyAxN6L9pY+d1C1nsufFy1cnEvNFO961I2nRNT5IHIu 8xxEdcZoYNhQC4xf3IUkZCv2yOEOuUWcIFFcH/L+3CKp7s3PpFzmFVtSe3UYGQGcGaBmeMpZxekm hU/EC57vurGzO13YddW6ECIngL/jkwQoLkT92e+SmTWhH9G5Oh6hdPYT4PUR8pFz1t2EmSiQMRnW fFDBoxqx/fO3apyTpQ54RztC/oJKeNeJaVoRr5qfORsZNJeu96d9yf39too4XSe4sX9S0PiSUVSk ABYIDIG58jWmQRU+6Rw5gCSG881yQSVA3DNW5u4OcrNctoGbY1XmBcA1UwhnzSTrmOb9kpYz9yzo 48B6SxZJbWIMWabSKskBA8JjXzDXeGLJ0UCH/os0n5Mt2IAY0c5skRpnxSYLvIoqoPTUjmtpXiAK 8VDnyns8/Cz16K5k8in7JaGbe7MLSHywt1xJQvZaL9DZvwKUcYhWwQUEXUCZP4B9VHEV0jjRVPTa 5pXDI7BK97CYQUVmWgEjfOcM1wRpVk60xYTaN79JCNX0jwbamHX8UsQ/ZOdy3qq/jpZkJKxs1ZMi mopmY0xt+ArMAjvGUGf034WvaJd/4WlseEHgm+WtP5gBh8O2tjbUVhS9dPHzYahhNtSkt7GN3cKf aEn44ko3rY31ot8OocmH9WKBX5PrnrWGzSKTE7nCZSh/gcBAg/mV18OVy+F457vy36Jhz7rU0B8C 2NPtY8n7udFm6NOy95mT4xSfnIYcQiZYUsmUQy9OUM3KSLERGAHMtLwDUyOXbNc4gbj68R7CwtdQ +pTzof9F8nEIS6eJ0anUssP6RSFkFIfIOD8grExRhWwrpDYbRL1t9pfrew6+eSwDYxi1qj2LMGII puwry+/fpVZyRlI7x3ZUJbYYEoZ/vZUXTFIAw4ZrPuyN3XIkLsJJiNM0GZcmNsZhqGxD4xAEuwZV ttUWPK/23Uw/p/NZYsVThYONjSG/ZXjVoCpf54+8wwZj1tIeANkcCOWJ0ZH0wvMaCxUOeWd9ouqV rkk0sraahOnz67B2mKWpKbckh6/ZjDQu5OVeRx6TNm9SaIEDpZrObMrM75VwxXR+kaE1FA7fZtFF zpWAQ7CpxSwOPSpfl37gRXCQyNnuWcSWk4MHgA7n3SnT6RjsJPCFrRSrpZZKrmM+GSoIz68HVObb VI19XQTRTLOqNMWSmPXpM/E3/LQhln1UuwRDNAzNKWzC898qDCaAgjPeVG+6p0+BqxDsc66uVsEz HoCU5QzP31sHaaQZUWhI/hPrKXHKCFc1wln+ltqteqnPSqiR+xJI1gZEwtTBut+awJQaPEWZtq8I 3lwHWl5ERgOzVMBcO9K/QJfo4a91NCTl3XBgR9iJveMRcLX6o2VKn+00pUyLCGmJEo7j891zvPJb 5z/6QbTYDbaFfwQyhfRb2lD1Uk+D+74fucqvMCxOdQkPiMQcwVFe+BkmabLxOPIWkuJOdiEJtTKa rLNuIyaZX6G21lj0PMUMyY4HMFZGw29U0lGqAv7cx/Bc4f667iyd0lkt4HtjCNWiM+2M5d7Z2d+3 ZX6D/xGYFRdBaMx8SevSPbF3twsNPgnRxeusepMpoMn6SslQhdFW3G6PHBZOS97Zf0FCV0rVUT43 seIp8xZ7SDplW6OCqRrKfu6CgpgWR0wqZ0l2WwujpvCfwJW+VfPmg65FHIMhweHVxwMIGxtKbMHk 5r1vNcYqACHkAt8mDefv2blOiJwkbtK3mpP9ix9/RkFA3+/gRS3PJeu1qGzpX39X7wLYP1JgwJ91 Q5Y5HptFQ633uL5Y6LZWDW31pT/avsPhjEnyHhk/Ye2Olo93NI88G8os6c3QecCeTglVldkiXBod dtufmdkKbQfgJiaoQ140xQPPL8IpXdaOSpbzwyni3z0UWiBQTxUTknlkT2TyXK2ebUz1cqlhv+8C 7FwcFpqFGWnx1GYYgNs+NqjPKVw+ZKomnllCEeCRCoNW1dxKE3+qH8l4ECzYOqKFlZBan014RwdJ 1qr8TTovdSILrgoruMVE4/XyOsWk324Yeo30j4oQYe/HS5X5IqHzBOY+Yr18kZrmtj0ZG9CHhszK lTAjc1N9EmfRWPwvIxAcJ1dkvbYsPZIX2oZbb6FCosETXFn2LhuvX7SlqBxJlFul5DFSHdXed1jG zBB+KlxOlJQ6gzTFDmoBGnXdtQsB6NBlGUtidA/ydUX7hU13HKu199FRXoV0TAkJloEf3AWSlQCw VpKJRiXy9DwzUZMNJ/W8tacPYXEX/5kbqvaEzw7NENrbk+AP5MQlhNoN7X6PXxNqnePYaBkLX6bN SXHwioxz73s5ToapzIniupPp9x6wofViqLid1C3bWSnO2hH+2R+sXTenDVgnaoGLeyzAFjtjF7Le dTl8HMDIAP8S11dFn9z5+Ke3fe/8F8OriVp2tUDWOT8P8hyiaXrkCa6xnZvNdnmXzesXhXpkA8S9 vV5RBMvn45MBzNp3+Y8xkZWI5owovSrOhicLAlDS+X3AE6PLCvUWU6EwDgaSxSVQhMZ6I5nZ51Ru UVtQEB03z/YBuRW+oQr3qSU2SdPFQgBoioF1y+78vLYRYhfka8AKUCT8Pt+jlfh+wnqACihjWtBH BeShDZTM06Nu4beAe8uu+0HRf9mt0y6kjwkpqMKMtKokVjFFA+chgi9tRmv6NydNDCSfi+KOBWvM LbUHMFKZx9Zd7tYhOUMomV37NkH74iVVNrEHjL064d6i1QdhP5qiJPrgovB2WINy/ntrhl+JpQHQ JNSc+LcG1WyDp9SiPGODHCYWLYgesHW0VNzvIH6uu4J7mIDYmjAvI0h/46llGLJNRniJeDxvyaqj gxINZzvID+Ta1Y2iY7YFbWNRPc+GpTNpWDN6/0p7ZncsCJ+7asFHqDXSVPDxNl7chsigwTQ10CsY DfYuI3TEinIY169tt1JMgjgmvtQFyuAvmI5ieYfyS0LU+XXxUxbR/sr7zcXIR4kc80KBsTaygBA3 VlhgV1EFwjCst5Jj0x4Cp5HKZ1rqbvNg6q0h9k4z5uHqDoR3SvDT6RPMJ2vIvP5k/NSXIFcAM4BA Uk/IoKgYW+JB7t+AtJV2LJaeZoV4WgGeKF8ZN1sbhUIMZuUl/zWtJn7avKeYqLDdZLMeWSv1NzcR nG7hzV2/0DJ4KNNTTVYTaA610JYbNQpyK4A9uzAYz1fGY+dX3dq8deuofnlEEruT1GZ9zXGKGnsn EzdweoZ9fkcB77Kt30HYuRGyvJo5AyWRRkmsDQzUpGFPNwdUBwTVtMK5JxZtHQIsYIAyY1fHbX15 BXic7PCxaXRaEO8v0Xw9hb9PTepdCNcGLK3UwLeGlWrzq5FilJmHU0toBzL3KjGQnJhh4CGNHrbf PKR99x9Fmo2lqHeDHHS+tCP//knNj+BVFqXGQLdEuT9H0e4/8WaaXAynuNPAgajfqLV1ja5/I13M lsAiaJq20O5eboR534n/gKj0W8YQjwh7DH5DkS/QB3zY3/a+R0tYvMZbALflsE8FJyb6xSKkoJkg vmV0iU5z1JrWMX6+93EU5CHwpLF7oyaW4zO4eE4/vHhZmhQZe+HaRsTEHCCpA1uruNH1Vm16zXtf xcgjoMYDPwMzyAfAlR/OYz4mbnUPmazUnVNegabxuI5cKuhfHiPJ0YVM+JNzmXWQ/852NFcseyXs LlglmKkohHQ7x16CgnnEKLNXkX8vqEX3STbXgJnfUtUWOLah/0MhfnMVhPtkADTMCVvhyVJw10c3 yuA9mg04a+s31tuc/6xvJkLYF7xt0YmsxhWrrI0EFU8h5LEJuPiDReRSC8EGnde8jyeHC8Z2iGuB h2+0d3Ffyb2Qxcz/PgLWrvSrLchvx/TEZtTcBAy4uObk3nvz3bnAYiZArGhREFAikQovWuYzu9h3 8lG71Cn28raBlZCPFSUQRVN3iSeEjAaNzaliGxq0id4cOsMldHTpiamknv1IvbFZtU23a0PeX1Qk dW6pWclVrZnUG/m4uq10Q4igRNH3OBzxzt46fsvNUIilxnlONWIbKh7x1FIWDq+l+ZQQpE5u/3yW muFPF72T/Q0EBBgDTmWy9NjApH2H9QrXQDKUh3Av7HOObGiGlIRdHR3eDiGGU1cvuqNAd2qQy6Pr PsW27jX7aS6gKL7Bt5GaZZKbDgXvvtSVGdc2kEW9PMQxgR1Fk4y/0HwYlNuHHikwQSd/DeJAwmga cAv0TfCx9IfFcZpeAz86ctEV0/XTHU21KIHOW9Y2cyQp4OQJhJGCCCGtPiernC7U1I1KIA6B1OyI LNnTOZfAH5hLYrUmOL/jNBR/ofB9sF6DugPDEgvEycnadWeG6TgutFGOF8Ju9P8LhtBoy+1skvCO wc5TCP7ddP+hAnUx0+m826sNJSqz4ZMb3Cyat26Jv8dBT0XFtBiGLLnwAHa7YW65WnWBm6pCrVfF qlA/nKygDpGBVkA3/F0DjagV+KK6urVLIc/Jnn6ZFhc2dJABJnyTQXkj5QDx4lTS4s0/hyYtlwf0 1pW+YQzT+YCxlOgYDZJaWtva/RGZZb6xK5FGkw1ioYCV7NTlGjg/YeEeD9Srn6K1UQWMF/Q41y0X uozY9os+szGPyIkNSLwnx31Cm945Rk97U/slHKIk4+gHd+xNhJnDh9lc5rmKySSo7ENSfJmflWre EuAbVMA5GIbOFYtyotpZKtFhZBZUcPFXVedWMXO+J1FdplbOeSR4MeCIkfB7oBvNT/OsahctKonK G5711MwA+3DSfZ7kseXUSN2aTZXvDE3zjRyFzPSQpZa8BnuypA0KJH2IuiMDPvtFUQ0wzNEvzYyt BnkTDRwMXktMKsTu6hA12aIH4KjqwwYx+WSZ5DRps1HPuATAwdfmcaAonH/L46PhkTAoLF1xY/9W OeuwIOPGEuh4pIuqbo/4cAMYqYCy+5gNmja2VEAe6iVEdB9MsA1f2sCIWBPRkbOSo8pFXSwdkDUN BZmRjvLwdp5qx2PncH26fusZBhto3HfqvadueAJYOnPsFwzxSdkmQxvvKQ8o6bkSxYCc2GIX0hgo JxvItRRYzS2j1v2vhNsZ1UOZ/I4J8G++H95TU51mPS0mEf5R0NrNkWgPxTNTE87VZ435GxiZFZjc SemNRutOF11AXxjZYTR1UM8NnmpI39F3Lxo2pVcGC6c/d/BOZgxk55oRh8n9RoiwkjYuqBIfWL+r RO6n9uKF7j1okUAkDKmKphELctyr5ut1qhXF6jppvv1ofxltVgfMWIjDTY3vHS2STbLZBSONn5Bn 1HvCGKaBpNdEZN0k/MFDzN/wOyGbTIYNmdJmsVOYftmZIKfpo6Ah6Yz6k1yx6rqLjFqiG79rxprL fRO1MnIBfBxw/i9MiqRNSGpqVc3UPJtw+iyTI3ID+zyH3cn9iUhB09QrCHQCWNRnpfJg79qnd6gz mZ9ByiGauvnHqO7yxLaagV5TeoVX9/o/2UehsHcALzXBDp4GWeE21IlaEKBIJboVLIDuTEtwnz8y +l0UAe3YjyC5OiKTKMXNznJnXqvrMZJMof+VwZ5g3mQWBkmmwlmId2A7+GMq45caQ8RShKJe4A7Y CVJMLEX34E12Y/g58utRCFXkGBHM2hYjiROxM07ry+WV4BlrSZJIfFgQnYZhEtMf9H899pd8oIW1 LYLu3kLUVEs1pQX6Z0O636x+wWMtI4NTNyLihTiRtljsSsRrSrpHdZiHS1TbR3Vsnm5wnhKMpOKx pm2FjdiOOP4/u9v7HWrtE3L93CLC/VR4Bun3zQHt3BJoT+j/gAziGcwwpfOQaXZCE2aJPz6a58k5 HYdf/jUmZelHZmODzjUenPIIZoytGO3xyIPt90KyeptvKqIBIpt2IWlMLxpBDlPbHZuoM6KDA09c rCg4fc2n3V/aU3HprkFou6+Qfm3939xFdMATxqDAg+O5WJN0G4BzLBZBJO08eNUqAf/QK082ydZH BkA2KUk5te6HiEpzZxzypqVA0dDxNm3skIGSBjHHXU8ObnKYw/5G6zSotg7VXJ+iHLYVfwVSSICE yIh8NZ8kbKgj5BDe9Wnc6fDRo/52+wWGvhtoYTT1aoI16WgFKU7MNNZyMciXUBcPYI5s2yZlPlQZ URYODv1FBrVQFTVOEc+ZkPy5Xt+/il+JtdzdfEniS/oBKVrhKus/ruH5KjiS47kz87UO+RfOTuKw FTRTGJGVcpmCZTuEyuC8q9nZgakc0tfTwZhTmgpip8Ok+lh+yQIG0sSxqgGR5aI+H2d41TDPJndj KYiaYkZBCkYGzmSEu73UZhU08PT7b/sEmuzsedy99cqZ+adT/leYU5p/l7IsdIwETK08eiuoLlcY 0XkVW//w/QkrHH3axG46e1/ShCqknQDnQY4dRuhdP7CVtIE9n3x9oHKZscAZxkbEGwOsNMjDPzxu Q2g9V7hNlRbnGZJrt9Z4FwS+30/qpAkjaLM3b0d47VjXJxaYjyHkxQLctEYehBnKrk8fCVX9horG SAiyhri+JXyfqILnZwGAMMrUdTusYzpgG3Yag6mMELOxCLzrOin8EaOyPtsvcTvOnFzdjVTB+ED5 fxQoG8sIUxv6W7zcQt6fhLSxE1rga55AhMlGi+bHnZWM50zwVuJXQaHR0Qfnqu7LjuouoHp/mFD5 7L1rPCIIbpYWSiGY/yRocpEqPncimNvjXKqiHtsVctqEBFDfCUlGwSdBx9SVTv359CSOBnRYOc3C 0RGm7DE4ekbQGuHFeUI+DofgHE4FyhI9GfSG1rhPjocxVCKO6UbOp+QTn8ucg9tRX3wKJbguz4ei 7bDNoGYl5vAsZxQ1nW0c5H9PnW4yu0SnVcU/eUcwz8A8cZhClNFFYWTtBztKSB9z+wLyjb2096Fg lEaLwW3e6y6lqbp9fY9t9C0hIb4YEgLatjCptqF+TvU70nvRK1DU/X60wjYAF2x2Gwt2+rzwLccH yTA1Rx0fJd29NfiSDkniWI2cyI6vH20YoqtcSjU2EVDrVh8CcYqTb9LO9xdU/zaeiMA7WOlE3YZj JJG+sq/DN6PHB5923gvC645JEtGBkIsjzdK6OOh1mCZn1hI5pIiLGzyZ1NQZ/zY6urgERL85nZ6v eR+Pb4HmeQcwQmXk85E8N4HBdM85oASeBGhYM1JYl1PTnhH7oKFnIdGjDuAv74DQe98KPtkdCxvv 0igvR86kwjHEau0Uey0oNuWVSD1OmRhjcjX7k672FfLai0Any0HT903BwJa7HVOmdJGcMUX+VKeD /UC0vrDP5jG6bbAFkOsjd1i7Ic3kDXlP5xDYMDZcvohXRO5gUDI37safvkDwVwFVUKiFsqj1Im5Y hI1QiPSAP2ywVVc7sp7bUiN3gphEYcNqg2dMHXTiVpZAZMdfQ2GQRJ3fHBQ6vsliqyZnpjkN3Lra JtHtl+hV0gbWXG/4tb+FYSIPRq08+yeTDdbU+aWRIT0iNmeKZC75++Hr7sVHnen24Nc/a0P9o3UC 7QRNhbjtTvzJYjUW6Tyr0P1oSKJuZ+rSXdzP90169zDSmIZePf4IbEioiOrB7sE2YH7CbsSfI5fx +91LklY1BhKQ0iwXeWb5gLyZgB/WLVZy6w/nsL67Js0ywxh9YYMkt6d2CO3ilDyOhEVqAq1wFkzj j+RvA3mF8asjid+kA59X6hIDCG0C6SI672mhoP/VHGDDmhYJN+RZ2VSFuV+JkLBf/HE2uGawx4Fp SxJL+/ybauayVNWqEjQzR6L/r37jukbh/FjEzDIpIbYYBT17o8wOAVZN4dtVNmQ5futiFnCkYPHS 71m4JeA9t259gpTHXWE8GU1C2NTSfiaCt6oA1T59igJmmoYWR7Qn/QV9+JZOEAj7hDsBYlfFcBvR CK0BM4Eu8URiy+I2IuifXrk1FPbRrvHUDoEe/c5Dc0PikVX7u32JZEMZlR5Ix6U+KftdgKYoIVq1 HbQHLXWO6jnmGyyjAiSAnr+QmRLbyQnqa6L4L21foueEaeC4ZDamsjYCJ1PeiGpiXBFKAmLNXSPA Ijjzx+OL+m1YdivRhOlP7TkoFzO17YR+S1sTvrcseIbT4Im1RGkxY70n/RAuGGqxGVwYV/lGS7HR 0XQ5uNN2vU42zAQI6jPkNKN11C+vlKZoq/a8c1K+NUdDH/CFG65AwtSG8wj9153OYtJGGDRYAptk 7wYP4NAI7bzwx6Gf/X6Kvfd9Iq6Mfm5VZ27l+YyBctbh/W8UyD/fwBN49Bz1OZ7JHrmA4nMbfg3h Bqn40s+G967VB3S4Uop0xYdTCbpSqTpErDGP66y6/j4ziqTmadaPd4OkqthNolozJRST2TFkADhT jqHhg/Bfkks8oZ7RfOqHaSg85ILTCq7CQmTCR2c3QvsVGMZgfi5WnmctwoEj29niL542rysR07qD gpkjqnkpGq8qqRr2zx8wtLCbSe7jvN2H2yPGHmEZl3tm/EaAM0QNNG94HMQbHVAsG3TgQU0mR5LO kAklDOfeXUzr6z7ecQIFGGWEqxmlTqP0IIOtEfSm9ERKavJlREky4w3OJ0Vhu9iOiwn5qGOBCD0Y 6W+bf6l5YXCrKt9FOkspsXL10iND64MFLTqhGPsTgDn6B2cTDuEJWSv8b7jvOAqWZ/MQZR/1m5Bu +UHQ87Ghip4uQzVusuVfq4sLLse0lWUTg7U/A43yb/0ouV8obwLg7iWvD1/Akx9R4OzeabF13omo shYzF9OrP4hW/ACjZPVWG5EOsojmHZx1r7TacYsAzdSFERaepXRPPt5YZB9D/0wLlcIKZGw2XICK eRty4yqgbBfxAuFlGDrUVwoE3uV2eeiIfkl6oDKLDqfwZ7/TnwjT1bLLVeCXDuqsv8Oyo/XhM8RE mpr6F5RQpSn2gagQQMX825kbR1UsnFNo3qpH4zyyN7bmhLI4egR1XosrqRgk5k2JfN/UwEmSOXUn kf5EUicxsLsTreFM91alIOePyKNjyqOsVSYcE6ry+eG9H1uMlrBgfcznliwmJgtCP8zhwqXA1ehr Nxd0HQNjtT70BMKmwodhef30RQtWiZJ1GVEOIgs4MKiexLCPtYzUyKnhRBi7RkgPikoJ/fXCsopL YkJJmPVxcuB+DYU8K58C4tGPzyNr5ef0gPepiOKFdv9H0XuHskQ3k6wal3u+Q+oSM6WjVNdQrfOg F0eAV2JL+K14Ei8GbWPw/R1TlXzAU/ucneq0TTbOeD9Tkx+dVjKrR2tNdH7QUuH5h8hAvKCI7Yda hT+2Wr3VN8UGYS1wbTY0qX0kKG3nee2q+w4HLh6rjULJnbNqgcoGkFqceZDiCJMC5KlQaVOoPn4W S8aBTNa9X5M/x2HaGgPhbk2HVrFTpwz2kRg2g2ispPvbM3OryeS1j3Y+7jXxfpv8HSx5m38YpJri wGdn6MQ99Jj9LdQbx0oY7fLdij8kp8YX7DenPx2thdEov52WVwS71A8Gt/0+OOROIoKM9O5xWLFs JEa9BpJCGmhkVAsne/kDDjD4t9nnDs35SNqigo2pxilCLP4YpBeyzeJd6daxEJdEeKjaYf2I/pte xPUPwObwb0cnmQlfBBrPjs2CSgD33jpc0zhpGelxmDeCaZnAk+w02dJGAaU+cfdIY35YpeOCHiNW 6pMJ6cv5iLw+f/Ms3WHzQfecrmOOfDMaf/4PhTezAoX6PHsrnohzGDYmqfRPKFlsMTULX1Pf1nAB Ou5K2hZTItpVzY4FryDtLqbR65i5HDpmb2eyqR2CoB7Uvps5kgBLpWJkkG8d/0TRVTuPEHI8AWUt 4bP30fvM2Y3UipmKMG2ApM8BRCivpsxezH/qZQni8dD5iFtYebrFPbUJYo99yClC4BBRY7lUetsv uL2dmy0+UAxqs07T2PaSbQ5EPk7eYFldNRiRLHKFSO1tVTIJgaMi1bAplspKfKAfmeJRPTXTWS0k 6em7vRTe30hEdG1s8tMQmceum8z6+eKvQvHzXCDyUpbibVotytLFuKFUpB9MeaJe4s3WoZQyvSaO MsX26YhbAuRPmZ+X6Vrb8y7ElEUBYfusGXOQFFZtV8fO5OEBcWmfzvJgecyGhFCdRaWNfPOKY+N5 AyA7GTUCpIgUHq6o9ZwGDyAh1XYkr+oAeoK9ERrOQB5J4ets6TdwpzUBEDgLshsPQ3OFQs1b2c1g VxL+4KF1WEmi6HXVX1VZLstVQ0iPLHx9E7xe+bnpEN/I+8sOCM5PY1mlln1kPquf0gnCDs+Mhb7h vHL7r7PjLyEjdrSFEqsof+Ni5WQ9e/6RZkm9hCFKpben+1Ze42Z20cE66Vv2WgRQuPLmM6inlqS3 1aMR1PmRR5g8cD85+dhwB6NpVYypKcFYKXsUE17deuCRMO+YAOwK/8avAniW6m2MfQ+bGFiSV/7M 7uZteZXjocDWCNvXbfS6sJTnkzlveJ01/mO2DM/kEMGpUjDVG7E8wIYvXXDWdhZ0mkFBEFO2uxAj st5OSVyJZJRTwsxFrVkWKZXhrFHBhl5Tv0wRdlzc9LPiTYvRh60eE18d8GmpdStHfO+xY1HAb347 PvTMnJvs9yN94V4gBE+nuRKtOFQLdhOeKX88//jxdc4TjZL44IEIAU0hiYGe7bfB77EY2QFpBWeN apPExeaKeXDhbFweXTfxYseXZw58Y/rUdcZt1pwhEHx46oJ6lE1OFrNp9QQ1CBpTt9grBrXJYJYb Z1S4X3+hZP0V3bPbR8rxZ+qtAUQ/LbW5qajUoPFZHL3sajh6bAJ1kD+P0V1ieh+6fGH6bzAzsDgT rJxm/Lz5j6JIxwwA20nYxBo7Wmh00V4QbE1tLZvoVOEVPeLHPifhKtBzfKbi7XXPUWamCQPU3SiS t7fb5CYybjL/H/OYCbHr7E6fs89PTjwyAh3Za9FLAAk0RqW9Oc+q8bmC7YJXs/h1A8GDfJi/zg9A IuLio65q/LJTowrFqJ5HscCF2i0uG3FMTjHOWkOl43mse2GwxxvdL6MLRKeO/8FNHKhDpIIKbS4u J37SFXH7kAS5JHKyHsnUyq9kRnMkOQb7gKm9EobRTqjp2k830eredFmEe8KQW+OJkbOSwCJ8O1ph zpS+ePEt81hoO7RQxgeUOeLk0aNTZRV8TKzu11c/O5DkZ9BGXSXazRvD11CwhToD3TC7ZE+1NFVm qvwG4pfdKDjM+wqcEV4QJxmLX4JqbgkUwu+TVWEA3hF7Gv32WPU2ujiY4M3Lomp0JcNwKHXjfXdQ GUWQI3XMjoeZVMAYUojX9aHD1PfOwvji4J5GuHT1v5XGOrAtxKiVJzwW1xe7Dgx0SP8dUWrc2Icf 3VvbmVn45V/0DFBHRRH9XVTRnoUJm4kd73/kwqC2H9BQOEvohNmlilCXDvsXipejDTm4brsHPmf2 V8DGAv0dUEW806HW40JM7WBOSABith6AY7M+1fnULcgdW+zKecJoBS/6xQdNux+6VGccmv74xncW hHtB5PIhi2PuDPa4jJkj3AGccUSnkJcQydfC7635EE2gBG2hNiVjff/qNaMD7DZgc9ttorjhAN9h UofZA7ccsDPfVVbB3hErhyTFt8vkkz2wnF5OyYu2C3x5WMT0MhYsTC/RhJTaXHMEJd2dca1u8zyc 3a9eYiyqkr/cgg9KC6TeSGTqtL5dicbcvvhgqUKkSjIioQ3gFLElUGWTb3yRn93Ak04Mpfst6VnY RU6WTSgBKUISD2KjnXEPetkvSvnv6NXr9LivqM3QDxRHqMmdZwIJoKKlR9ZvTlb5XNFXFGZn6dDd x7S9i7lNBTtD3bEuQ6oMou/nJ8xFNckPcqWSJEbGplCfFtugz+0Tj13u684aTGP5g2svFT5rjByq va0j3/4jBKhDEjAiRG7LDmWWYeJ2HokUD0d92E4ZpE71qfVbC2eeq/ML4S6AsCV7bhC9fGCI6IYR ZNmqTdRXnpV7Xd7MPc9RgIPMaTpG6aOb90W+p7aT6JUL2ZRVNpjbcYJ+tuhI/4i+iRx5TfLNjr5+ /0Smdz0bSg95CVePJ/d+ThWPDU2VO4SEiUX0djl1CtsT70AqbSIg9si6TxUuOe269VcIegkC2nPq gJYEOhMGBo6MtoHWcVzMKk657BYQOs7A6B+wof+koZ3E75b8uo4v0+Q7N4uLBorxgehUDsh7/NlS gH6KnpYXJ4+gixK0D3iqvyySo6TckMUK2M6jrBCPyRr3+FG8YV17YclHA7tFH1tiJctT08j97qbx WXkr4hrjQojESkptEW1Xth93v+QX6YHsxb3Np+U32PXsRjjOh+hfBWZyLRhDGezgCsZhm12NgiUI eBM7Huuf009MadvoqmNfEVaNAnIWwhk2qh7+wK+Z1bSF0UBrQ8YTmj9Bruh8IQBOSKtMJvec95qu yD/Ss9For+TYO1PjGyP/Kpe6B1WPGLoLPReZvHUhfuuFSsEBUknU6kvT1If//EP8pDCJJCEM7KH2 vhj3F+/QjCYnF3nh+9fUiTLEBx+2O01ixW46ws2lgBhfmZM2gQ280B98sAtDZnGV0zCt4q+QTTm+ nnbvYZ3Glyvbu5XOKKyBkqXDBebVGHw0fsgVzvb1+ZJjcRnO6pxIwPHj7YcTcZW4JzSeeMZbJYI2 OTjCQ+HR217aydxGzungK9lPmt9DcPbhOf012D9Ki5YUXb7T+PINuGJswE0J893xJyU12diogzrl cTjj3Y5OibYszj40bX+JQYPiiyNVneiJqzyOyRAKum8jRVvSEMN81lW50/oS+1C2D8xv1eysEWwP QqbK+KJ7zVdyClRLhwWVlNjyhfdHRer9L0GyQ5T7nzS5cyienNijvAV3/lczhkd/1N2MT5RoIy/j YiFHpdUtpzLvHbY6LUuuSSj723wyCcb+DLO25HpP4w6zd9w7py1lGbAHutZuHN07NDMho9VWhIWV yaWVd1+2nuIXqy8nSDSkQJ9XmLKB9JJ/jwUvFqZp/iy3eZmkf6/nez+rMSAHJw6fFCzsjwFufW2U AYn3JIHIW2+EtgVYLBvtG/4McpjtcrY8Xc1teYa5RTyx08lPqFwGDIQChxlV07mA39liUV1qZtP4 2x/5fxjrYcSG3ckOG/Tz3EfeKuLDOk52bpirW+vunxdNQFb2P6upxboKmz0EOTFG8Aci3lGgFVnr OJITdOTOYZgzdU35gH1MjKUS6r/cKZs/DvD+96Om8gJPKI8XPFDaMdLo5ysnbOukYd6r4cgtcXtr aJN9w+TTkX4EbyXLkS/m4/nUB3uWaKomfQQ7DMedGX41CXLqwLEhKImrPGWhOYbZYQjiWA5Ayv8N 7FcumIXIU83NDgmQKPBF+qOttpoH7WY5nbtBp3nhVwaUqx6jvXxzq9pi5w5VPtN7DxndZriq451H uucoQzmBR7lz5jzQmVBoarp6fc/Uzk9DXbP/+oB6MhFOS75fyZyuzJpbOtiJANIZ1FkcnyTYn2Uh UWyIFzr9CUjjw/nhYyT1fvWupyKaZ+DyN9bwyGGGPeWxEZ8t2hKDZJiLGj/hWtSVf1xqlosYODol M/eu0v99GDTB8fJvSS5jjXg7A3aoF+PrwLyCdseNPlYPiL7/4uYtmpYTNpU7KOhKr/fZe0kU5we2 4oLkG/T3iuIlDtgRFtmCBmKzScCG1kIesq5u6WptnLeYu3LmDdPqdwSe6Q+QHAAZSZJ3ZZ12WOPO w7ZDa30lcvbyF8MFdxzBHPdqZOi9Rsm1IRIvwgMcFvjCCigkNtSP1JP+MpnFislEw0YhXXawBRRA KCXZAp+Afjo8GBymVib/hCyl+AVffERVxazVLQrf87bG7x6UtUb3S6ghyLolHPafVknyDoJuzDGz ieoaZJUk+lbtTj3lAqwm26wUBvXQRAwDjz0cAFfH0xEcl6zzIPIrHiLbiKhBQyK9+q7rjCJmK39+ f1uiIfHmvkMwaUU6uFngK2rwA/AScwQZjZjLuCB+oiBj8hZnFPo+qzx0nJ6UKSY+WyRcW6R8P0f1 QMBpWjOtXx6GU9s/nUrTiwvjAj09CD2VBlispeeCahigdqUYl93wi1v6Ysblz4LyiudMk/4xcayl MDsilyKQn86LGttRZLsUEh7G67J7/b2ggyTKqsXrL3sgkswWhAWDWN1Sf9d7IUtIldvVhZLQftBS 1qnt5Z8mlsJmvz0f/j5yFE8CdHvWFFltUjH7YZ1JiTC6sgHEYKoa3QCnj3kPPnotC2Ket3Ct8Ken VmsTDnti+jwGBBS9CCKIWoGBzDPI6yD9fjTQZCCVjX5a3vUSVCpITM45wh74hG1YVfBVfIEkZNMe 5EGW2+3Re/mA0O604hDK3XcEs+aqGjYM/njB+MI1qnQNQ215/71ptIyEeb2T4pip0CCPbJnnU9Gq c7HfAluKxiCJiF/kXTAF6IJo7XoHaCiVcqzNeCStfAZzp+46kewGr4fuzpOmGOxsJi0H7KOjorJB 4FpRyPDdLOMDrzKtJeQbO/+JJvIpqijEFGMe/QfNVm8jbiai2Xo6YOjqUEJUBwRjEEvide/w4m+O NKek1/rjZmGCSJHBPXKK7CCQ+CRy8Er9yso9xbATkm5+640lcgDvycHhtkIqvZAzd4rQZVowXp+B EHTGXio2mc4iy3rm6/u/DII4cauwu141tck1IwyUz2y3YcqnxQif1bjJz+K8+5mZLye3AG8hPenp HpoPe8qvVIUs07Qq/erca+yDR44P92R5XfBavLRUC3EFKGd2yQ9OARbEenSsor1Vcf7TPoKkXzwD qHdQECI6pFAiiKxOxlpwrZfPu5ZfiTl42ogRLLlxnWZ/3sCQg06dyE5qYAlnAuH3lPBIpLxU8R9X t3I0X2x4rtGysIvmaGRmMRrAsnCF3PA+YfIl+DI8L5ZEwRmASUNv7Q0zDDwxSTngTc10M+xr34JM Dj7X5VQtmZgRX7MG5xATbHIeqWznOgvn5bxlrb+uK13x6wn5aRrKBbDlKpqtrLJIH2B/vdVHFAC7 u7aSFknSndGDcckxuuW3UB8LEjxAu0H+LQRpJb/8/UEnmUumIWtVXTSTQ5L2EztAiIs5Jp21wkKE g3Q4Gov1rmGZiSdTtDFstSnlMoLVk0kFaVjacno9Tz251g6UotyXmaPkevybBJJq90B08qh/CzI6 svSFpDaEfjP3YJamSfRV4aPhCvEOKZEJE1XZY2P6HdFyT60j84vq5vXPyP4/gu6qgIB8LgDVHOH3 iwp8tk4psw0zPzPnS+/y3RPSTb/S+F8+4pE8JBIumC46FpD96INZV8YN1YxGVYLVfAbscnN7wJ8x 2MDwlf7F8l3DxB6PkFFb4WQxRDZOb2j11fapKfopggEmaaHcMvfoOrktkEgSnv/WcMJgDMPWqpVn dnwTae1KortXLtHTMetVR+KhcNl++5ewgF0+1o1nIyhITDSOGeDJN0V+FIGsPVSD8S3arisoi0tZ FJsxDzMItGiKuS+kNwIXZ1RPpwVPR6kGJfXKLn1b/UUz/noYscKjja1DyXWKwz9SVGnkFQUv3L0e x5t+JR0EvnsBKy+v2GRBMjRnM1EUTSpJH79s6e4bZYcmfQRXUKyBrhoWu/MfdHraMVIc6fGi1z4x ZqjAtCxItAbhqrKq1ep81IvCn17orc8vUjOE/+yvCBstlqtHeTwio7+mLIXuOMzOUBZOb5o8iTfl AYRIK+MLf3BXSIfaj09af6X62Zd6aEqMxPh7gosamICmla6OnfjYa2ola6BiYrXNjnpWxEFRkW6C ePUHfxEdC6jlbGPvMTl9SmEbTuWkjN6VHSORmZHsYl/mtpzFyRlcU6/nONYJoZqDuAeKTV/U6f9U /MuhIu2zU4sgjJbd3zqRVFfpIeBuNfS24+9L6XPLom6EfXAWwYmjdA/0dV+qNePQHa1b7hlt9NZI ieefsHgfa51E/r1k+f6hD71BhYIxuO7jnJPRRCE6mokmlqxbah0NsO0k0jYNg91ZURbEwusKm5Nz NL5lU1XHmUuME3wZkiu4RzSHJiRsCCR3XgeTCDlw+/a/ekiloAJJ4LFMSCfad97AIU5K0AopIcCM 6ABbFSEZPCav9EWKPL0oY5Nj34h1vwezF3e6M7zjSND2aATtrKsx8N+GazlbfIDemPLsT11GdxGz eBZBH+XXPA//hnuvhprAi1AeBTLLD+HJlSzhpJCEnY+RGhAP3a7xCznwlm36moIaTs7iMUxDrr7D Qklox/GAGm0zdXmFc/HCsNL7ao/P1QIzaG7Zfvydzysn8zmxFMRlYACFFg5CVlNRubCNPrX34QIN KYx6pxtieANeiZVQfHFU2sfO6YZDRwB7Jbm1p5OHDgjim7vfDKoACVfGlhOSC7zDZ9cpTl/XKyNk SjIZillIKGZYyK1b5ZXVtj7m+rU5Ui6NSBtUEV7HKg6Gcwz/5ceLdJli9WobG3wWDovNl9VP4nZ/ Hu/dVI+K91plNGpevx8Cxxe+NemQPiSBRBQEJRWYRkURQQsVtFwC3a1aM1rC9lPQajPoSnbo/pwE QItB73HWPIXkv33/lzQ+R+/EMyU6LMsdQxgvDXZuKa0vcgQq2dQOD4qJTDXZhI5wyNXj4EfH+pV1 AuXywTWmeR3DHxAhYQKfwPJwW+mCw21o98QAimE1Oj8xf/oie18ox4a6d53mf011vICXTlQABoKB A81eZBZtPfTirwzLKhcKI6WT+mWnRbPLzKhAe4U2AD/VaRRFetHlRNOZDq5ZUBzqtA5mKr5MVqOo /TaxcoS7q7AiOAf7MG1wbbhBkFphqt5QLk5oY2XG7xOs6kqIJjgc8GoHRI2NrhuVZyxtztWWNSEY ElP0kt3NJKG+7Fe9xQPVwRlx+lsEMY+fUxwM2r7L4KSp0k2J007rGWwH6l4Z/vre85PbIjxWpiCv t2c4cwQ4FAd+AZ/N6ADlE+Zh9zPIzjMggy0a4Lcpqmb0hbaakYVP1tARfMHl+eVkJ+0Faa6F0rr6 S4wAdzzYWsE2cNe7TKTjG6/YRz3Hpyht8FEyYZbxH/eBWRelffjuqLJlhTDFYKkaGodtQ1Ue2qfm Qrhzs411eLPNdx8hwlnUhzt1qm3TGeU6NKRJtF+COzAzVRU0l6BH2nfxR6yR5tRdnoZQb+nky0nu /V6uBeap1GkQVD2Mq3rYca0wuahYtwCVtLsxZnGwrArzK+Ph9Rn8v3M8X/HgexXoHpOkK8R4uVdC UCplrV/FuOIh15kvZdELYRmu3X4+bwrSAuLYbuaMZJUoK2y3HqSEB/hTni93CyTP1oMfNgmp34// A8/WW3xsRSb7LGZN31aAeimcKkgHsDtvMepmk1swtN9gSdhgH23GCfUURuGOEZScrMxgKuYvfe92 uqttYS8gWiOLoC7dXrFx6ByZpSX4iReSZ0WPinnvYg4uh6UZ27p90zTCGVFRPml6thY2KYTfSjmz ymPcNAb2I+5XT0JEIDwwEAE4D88AyHKi40aRNdW8r2pnumljVvO1xTSdHL1+jFi0IbQHUQSPRgfo AiEtbBywXRDgs0k+63wyBBVjoWUCv98Pk800S4cfel7XRgwUpPT0IQZ4l+q/kqsVATPnK7HdNrMd KaTVWMH2XhtU7t4jTnVH5ACP1eaD0+ntcwBZcq6k8a6u8Y/NE12Qt9FkgGdHKcuIuj2CIixeTjJY mgfyLrbfmO3lXgLXpXLaR/o+ZIfJ3p6PDZX6RUTLerQ0Q1ZGlyK3006jwuMGM2p0UCMtZIXYjhcJ 0fQrhN7i5mLSEAKnapOKx4ccsrs6e3hLthImHG2OmjDmiBl/0fM3x3bcel8ebYR/NYgXGPalgr3F Kp0b5eHp3PDeghEba2cpEuwEgfSutJM6jflBBiIDeI15xrk87PeXPdx5N+NogC29elaYk5y10Jt+ 2iEVrJInb77/6GWvJx+xDKE41/p/Kh1PdKYvbWjCQNWptv3mdcVVR9QIJqPLKJF3nqUrggHD3TaR 71DjFTZVS+dWUiS40knNdHg0bil+M0Q1jIoIIEQI7cnxjDOAcbo8CT2FWHPfjuqBvgKxLQoNNhwB jjFx1ztvbhp2VaFvJlX5dpO8f/efaewHxnhXQCbFFNOqZ52dry8mjOfwq5YbtOUpSFubCxl7oW2a iXWESAiKsz+yF7xrMklyIxwAzyDTrGTBROvVpT2LknB+IuYgVXKDNdkk36OZhpsgWXcdMzQAHCH/ Ju3BSeJOeHBpgbDMSvZJD5/cRA1CGPFks+HACUAqjHrHXWe3jIk4glJOltsvKSvu/6N2TnCDBXGN F+aUGm+hz0htZF3QWPi3x6s1TML6N+UfYI8X9/kDpHkEBPPr21x0QQ0P9u0H2My4cY4Q2/1dQHJa kOYFCA6jD3XnX1mm8m5FoJrB6OUOT6euh9GNYSeAZI/HwV2moJY0y56wU/G8uQh1tTDgdEPO3HBn u5u5LmNNUdd5pThhWqfzHSYDl2QUE/ORXxopYqIbxfysuGg5J/nj2pWw8cwEva8IMltXHJfUMyJq RLy3KNymdMVrrt2Shw/2bZD1wJZPra/QxhDsk0Gi6eAzi6L6vxriuMnv6v+iKoHg6XVgX8i6JqxL Y4u46JiO9irUE8b35dUsvkrJ+2/qmhlv5LVukCw+/QmmDZLaa1noSMLRtLs67nAAO9qQZtZT/PJR uvUObB2tDv/Y3L25bBazc36ST42dd4cTtG8WPTIqI4iaql6GtLtv8nICQu/giVXcm5Nj3ssCiykf aI8tpT/1wnSJj80auL7ovVTYPo1on0mTGG4P3oHO8LbXIUXWiI98h9CpLazb/ICGJsbQKf49Ssyl ni+Az7AhuuZprJAfg7uCGPxa6rqgcHQmBRKkRGlKumwrAw3+Clo0ZEPMdRL5JkCn3NyiqPcDYqZo Ku7/7+G3yxR6HwAkRhG6peftN7Bgf06UDTVMRznBVw5ukH1HUTSg3o02tTs/RTTFi3CdmQ0yP0sZ KuVeRY+vSEWm+QBWnkGnpjS5b0oGxZ15necihJRrmq4+DLqddNva7QypEOBGzG5VT7bOlXCGEU6L vHNAEW+FxfkyuclcLTGG4RvPKqLrPij/PC5hazYofZ2dPXPwqWNgcADIrAEtjT9EqN+Iv2oY4buQ bFWz8Bfm8M+2tsyxlO96JNYwmWJieUzPjAKwvWh4uoRgrvHCeNRN92vIvHoxGGU//92DFKbB4EVr rXUfv5giVmQPvESYBt3KTO69uovIvq/uekTkD9Uoz57U3GuUX8PP5OTUHRT0A3ujMdgxRoAnohk2 U4doWTOrejkaULv9W1mzLRIXSrIMAxEyIK/UsFej4+anhNSGjbvmq5VPufXE5kUJivR3jx+aVXJm Wbh7qVM30vGESWavvxZ/15JiFxUwT3UpVhs6TgQHgg5bhptfbkB6ZkB5r4L9Kc11+hRbRc7zkKxg 0ZF/sf0RnNn0k8X6623rN9aHdPj2LkXryuFM5o0uVeTrcaGaBqWzZgASHa1bC32P40EOMAMxyXIY ft1mdTVpdPAoYyEJU6+L/ccNhJA/9mDztZeFI5MtqTo82UJELfFvGnn5yb55KN4x4ZhRXkfC10Vw 0fvwrja3Ui+RO2XpD2gOndmPhaXILhTJ+HdJWJDPph99XuyNOjhC3RY4RWqmkRP5/EEVx212pezY qN8hhZouazqMPUFMOWAuCpMPE7qBK9doDwj7SzeLtNESv4HZXqG+reZovobKMQtU1KiEgrPrB95R jKhR1noyMsvsfBnFLaypf/CR9/g5/6Ku+DDZ6UOkK1qvZhuOpeYedjvZnQG3MqDIa9QOv0oZ/tyk 3J4dBOqAdaEmVi+WPgTB0nOh0BRuL6dONkwyPs2JVwBhxOYUjCMqBf4KHhq94w+7xIFM9EvxE0jz Gn9YHGDeYeGWXgDOTKb4uYvns+Dww2M08AcWIBxmmvSbXv5GQDI5Fqbn+WciaJmJYp3rO8lYSMYf cfXYpP1tE2cZKCmklmi19lpIU679uLIVrXzrr/tcMKz9eY3862XaTYKJ38I6cxQ4rGM0FJRKJHYN JVuTNP9Vk4Q7lT+LTVivYNyT2963IgQXqJ50EHOC/s5tm2eFs/Jl0gNAa6s4nVWNGOJKRVS7PuDZ hwq76CKxJXXyg6tntHin1nFYrM+DgyCF7jTO8ofPlFIwwhEFpIAv2nT2HFBo4Y93WT22GbFWVE7V 5eWun4wsWEzHFULp6xisiU4FRVPBFacilkr7jzJmbV9kTTFg/K+xxIKyswmEIg6zdWEahOrRhHtU Ct0tJHNRtYlGiWsk1797lsimwmtFIqn5OdpXT4jHoJlGw+QHmak8rIW1+KiwzNLoHIVNI9K/pYjd L7s0T7fH/frT1yUMFRbHppCiYP0rTKRNlo8MxPCRHR5Ii+s36swxAVM5sd+USkjbLOXvnSw85qx+ OuvV4T/Dy1xipmIF7vPpt9NTPuB56Kj1/hK74aSYiC2yu5O2xH/iuRFR7nGaTNNBrfpe2xtwtGP3 CiuuNy2M57c0NIrKMR45Ltva+ilrpY40CmF5IGWae8YLgyWBOrnCyp/I7eO76bmO4jqWaGsyd5V6 0ob82GKVm7FJ7F7zHLlMjw2bexFnEsstj4NEkp0X0GNZTHbTv/IkGzcSrhGJoJdThSd/EuGyUdrk gD6D5SLF2tV9193zJ/pF541EuSP/F6NeCtg2ndNVSUHKgSb4Zp6x1NFy8c1FU7xCa8R+RU5xisWG oovxVqkLz4sn8ZFbXIv9lK7xwH/2iuPkm7tLUx6/V2ppFbhBG7sYKYDekfD2pgcHYbJ6Jllr8/I9 a7knUajjvyXymqcRPCodLCDwFujyfTEKHK4iTgpT3sht7N1+vyxk45ah8tv1ZwcPbF3v6VB3q6dI C8kUo0zh0mUZfmrc3ln4VP6tuiLwn5kkTMofHmsXyhh7EB4ZEnftReahL+mj14Mn7/sICd4/jYau Ur0LSqJxGjDLteU6Xl5TOcb2Wtt4BT4Q+depmiZYQZZ8qWqE/XPv3ippZEzeyTi9mmKmNmEbOsRr YOu6EzFgHx0OGtesiMkyIAY/mwyNGec7De5PKJwZavdjapOR2xX4s2mM/b5Gw67QCwN6dSF9TlD+ ZT0I7FwG59bqwgAq4rko0H4WGdBEp1/osAEmNZ/UVaeRZZuiT6lGWxvTNiFe9tZcyzy91hBP5Nrr Pso9yWzmAzpjr/XLHO58FkEdEoJFoUYHWkWAwEbRbxYzIzKUCzAzppMArjofftgD7bGLECTP2Ce4 N/Nu/MKiF/nmYval3pOvevTqtXhf1WmpKMB8n33HbY6/BhJoI8OalSDjiZWc/QySP68AS80vI8Dq WpKrZmH6gmaGfH911OIBrmEgbKypax64Y1R8Kb8RiZNL7MS1AngO9TSPqwLv7tg+uqf7+Dmy49rQ YEOQyLnY4/hTPFPyZ75kkWV2KlYf2Eoinlzw1owcduXJBn4bDk7Hf255j+wZMsSMzD3thDUrlJDw iPPYLnAcOOe02Lm6dn4ovt2z0KZtDNOWEzPV4XORPNQa7KlDE/Qh5A0KpTwDFc8bAYvOeoAqdTps AzJIOE4wPpmHUQ4N5YiRm5SzU30J5frGp8lVumY5kN0UpoFTm5IPg1SKFdL3/KHNZiM4UnR8wx+8 X3S+551cAGF1ofBRfD2wO5vme/87hjsXSFo5ivgPr/WdQOLsa355pGUGl+MaL8BXF+8RbzxcmUIu hnj/q/jBEMr78w8/v5IiMv4ed9wBJfquw3RBI8sWqAKHNp6lzW9TO3F4Cl8jqGK8w8IbVWKbg5u5 VO1C+vDI1OsTK6/UBR6HIJYJHNf1qDAjE58cHSoDOGJb5lxg8d5bGv695Vbjk3sNcB++7OT9wjCE RSSa/j/W07zv3XVRlUOP0nakLpfHwje9lGG1/PBTtaHWCGy7yeomxFS9n8K8Jw0wto5Ad4evbQvW Yx4G2y31KOJLS3GHZx46z17oayqxJs6KbQubmsj9cANz/88sfQ2NUYVV9JebDQ4BAKjm46cabsz1 5DZnWcK+uPIHGCNc4FXaC2QA9re++MgnCL06KEfiK2eYl4I3mtS+SS3jAG30go/UmcYWI2emg+rH oWOvBntjl7vKkYShcwaJ8k4p6C2ofJFpN7lgsF3XQ9Mw+tw7izfETIkv2h7mNL91+4/2uJfF4nPF TM+ZBR+YJdzDRDYFKp5Q+xZt1chYJBNuqHyYLsbRUY8lzVlAkpRg9sCt/Uk7gqOX3nicc53ztE5y FjXt3+YRetP0IDM/MrPCg1eBObd1y8IIqs+eCiE1K6kkz/O7p2TFZlDpiVc9bgyMvYxjXBQkNnte Kao1fxmfmHSDcfZ0ncbjmEjD5c0CwqumhEvxfWPUJCR4BMdnaXAyYJYAz5satxZ/nd+J2afZvHmE kUosssnoi2qy8hNbdO83Ajhqwzul6NEAAmSbGWuTZgVjEWLswgh/MTmVl31fnKa608PP3opDknks 6dUAMjUbtgpe1sgSbAGi+yqp9RTFerQn2r9cg6OZeSRnnL2DFkOZSBDOCLSZM/xMCMWf1BvrwCtH dGSxo7RwEUVOIsL6//bIUUKC7DfGZ/Q3infuEpwbgLzhgoRrj38UKFqkKK3QFvbL8Ltx5V5+FwRY fvUGl24l3qUbdiK11zy/iKj130U5gCm0TeiRdTP6uRX/6cQSSEAupttaaIKh3NpzeKXpKnlNd8W0 3hHflM8igN93hCAK+/q7DK97EfMFhbOS+WMMHi7jsCrWpiihEwn9pgR4hCEPO8zqwwmxOPojY6KM AievfTqFRZMtE/gM0hT/nhi0ulVdvyOQhANM6aSvpGbiE4h6zea0eZKJCaXWcb1X+rYAwhBRQo7g 7OjNwfrZH36mEglluSs6CCCw2Svea9jP+ZUSUujJbk4YaTnI5Nb7CxM6AAaZNkoWsXE7jECzuZCs lUZ2SUAXT+uPbxPRrNHfdCL97eCyBpx6FYpc++UyDqdm6VJFTAmibhKlYWCNcYq7GUCj/Rt+Jnhn facRvvjIvyZZYuZMs9Z97u3iVfNUrnhl2rMAah+pJg7pGjqNQMuFWOmVW3wey/wCOe6QdACAIoCz MiOOBGSBt15QTrXAbu//Y+AhOs+jX6LdE7SMiT5/NCsTTnTyVSAq1s/aB+KrwRTpM1Vy1gGNfxBO rzW3SDcNmT6emHFxMffNeJGUuGz4B3t3etTlfqAkIua0WPYYtOjT4WOAcVSkzUzKslJY8tG+J0kP szuCm+9hqAejBP/vTkyL9eYtrVRfitudJ3ml1U8T4bp/7xT/H6n4d4Y7qqx/WwadM+56VP0aVnlG YJbj+EWdhPEm8tlsC+HNhECvWCP2mgOkgh+2UX2rpSqEBdJJdc8b4ksqLVsA6HDflMWmqakNB/kS mKpn9/HhKOUuUPjiGrIIBVRy9Qr7y5yh/ga2n867CoTBVNCsQQc0WGh8zMtmnHMtsyYGFi5O4o+f AzEHnAXcnJaWecZ7EbWQQO2B2S2Nccp4YVMImoxQe7ZkKV4jF0YABn1MwCfFHMI2TFbXgX/L2/en dE3Ueg9WT6yFkjG3mHhA+PieN7tQx++xeiFlgncsKW3SWbX/WpglhDdWnyVpIBIMbYvrLdlViCBY 7fXkzSDth1xCrABrSo7ubSfF0QE2+IH2m+VtzjeYQKR10sAN7sisUy+ceG2Hm26gwoE7FHbmjzou SyiAPxjCk9rJK04MedSo+Wcr7kloAhGwQpZ0XZ5BLA7Mv/He/o4+2pHzdkzFkPST/Ru4m9jE0dMq y/c/N58EskdqsTmlw+pjV7ZU2GkBviE0pXd3ucxa2UVphuv0iBy7M2eWh3at5ieXv13JUxSDFRy6 RxxbLnutfT7EfYn92Or4D79Dh6mc9df3FaY/KUNICdEJvBtLtRrk06GUv/IahRYaYpExVowIvZvy h5viFsMyP9GKQIWnXBXh1O0hPunW0NgWdAPEVgi0/RNOzzykmMgAgCCtviHX48ldB4Zv+TrmdFO2 YpV9pZFxtOKDT/lhI0hBX2CKVHa+gbsuILbvw5khePwnBNlDmoPl3dBabStpyVuQOTT0979SL2eV BW9BcRXqyQ3FrOnX1S/W6Cl1BxRPMlvDl5Gdjzj2JhpftQvBxvE7VOTVvQL0Mi/dTF5aB9dm13ZB EzR8lv/YG7i7yj1nb2U9Hb+5yEGeApHN4OYPb7/BJA58tB9XvPpwTRmM21rBrIw+cu2WjJXZIxWi s/DW8cGrDe1a1f6r6pLvijeJEksl7+5LnIKJu9Kpo/dhUfwMG3JOs6VjsMWVKIalP5LXallzeK51 /Guh0g+FUYgRk1j5m7sll3GE9H+7nsu+SSGXbH36i53aa+i6jOAuuh98hIJs97wGh0/lxZ6qbkCU koV0/gs/TukKcjULBQeMq7OpM1yA3lJRG7QtDuAUt4wQH1C46okAuF4bo6rToU/YGKcTX+kxerAd BO2MuQgDDE55lYrMrM/qs3oMvoL5acDVv/8UmNeTJYxgegojAz54NOTiFKAyNd2sAF2As+kbcsBd h4z/NJBTXlxi/uToJViVXjpBkPjIUeHPfnQgZ+OQ/Oh070Fbdg83G+1kMNFSR5XD9ENxE5uJn6DJ a7XtLJ+L6kJSspx1hW+EO/ql6X97BgiyfLMzZhnlOs23EoG5EAbXtubdp+kCCsoMZCxTE1hw1KIr yD8W6o2gPmwu5FkjDP1EUFgOSAdlIp8ReHQG85w3FPhuJfo+AmKyFyg9FIitpdyKupCH/EN9X421 PO6AZ5Fr1T30gCYavl0jLRLid8xMLCogpALYiB9ewPrGbnMiIPa8lvjTx+O7zUCyKFh5FDNGaolT 3/A3IwQl60nT4xMBhG+Li/W9gVD+1QIkLDaegHYdnZ6D3ZmXCRzqNKHtQXNtP/rp+rpZvl7OkPn6 O9LLjPfYhPb9fDwj54XvbuZ66oOSnXQ+LAUtX2xzIvyjU/4oPP1TPJ5/2H2GEfoEn+BrshSiwhNu WPNr7ya6HRZx3yoGqCHiJDYqBDdV5IvUV6ht1ixgjLOcXvyLZZn8/d1SVZoz1xTN1Mt2kxTOtPY+ MgPr4g8PUjCWL/R92F9oWT9IKB/7UUeZbzOljlBY2KQ7GeKck7hvqFHMQdFR2QEW5y4BfXWemPwu 8NlnLnZlNamZklwJFexhwNWuvVstrXObdQZ7KHwoc8z2Exi9EL9wxOEOKY+FOvARZ8QyRi+Ya9sn G3Q+xf6oZUAA3JrE39e36y4wpeECMuWvqCfKVEUgWHEzRo5GV5BR5P1c0dphnFoFcdTXNufcs5pY VOdFzl2oxOgC6FTK+ef17aklcJlxHB9PK/59vjuZ0sQjwwPJKbUuTR7vsVdvplBvLOCA1JXv9P+u j2/8ypW0Qm0/XzeVhtORJ/gGYoSLKU/qNQn9t3OAh8aFpI8VBmwCWM9t5JiU0bSFAEDyrP2Xu1Z7 XsbHebxoFwy0uYMRZsJxvN2sodfb3DhrxhigVbJlhM2PgrkPyf0kbxqpEXuB5McUXJTMweE4473p nk5cRSdTiS90gQkqWdlSDTPooE5KdIdsLZ4/q6lXxOql9U3U1xE0uTBu2QgBDPZ/c3Q/wpR1ttLw h94/f53Eq+0mIMoAr8qZYksUIQKpziuna+pZEGYRyGQQa5A0862kNcL/F2eFmiUtUdJcRMbL+2Yr nYxNcVZW8UaHAmGZGuGj9I1dFeiA90hBUMXn2itquqe4Ib9Hi9YCgnq1I2Na9Qeh5feWCa9xhmm+ 9HXAYKyYL6QpctsGmoyfHLUqN2JelbBQNBNBQiZL/+l0olmysS3R0sy6JL9/RtgXzVeAt6l8g3EH uvQgwFBzw8gGIeS8frVGnE1B3w/ootmYLIoGi3CONzIjgIx13Ek3seyfOC7TMM8JbUEYHxmGIJX/ H6GTk7IMsQn3WGcL3MrlBeZwkeelcTBoEwcwTQ/jG/+Q4t//2/pSt/L1zSiPxcALFIJp8x7SwfN4 24kNPcJgxBXp9C+MdDJkYlmrPDuVxbPE7YTJY5r5AhUDR/a7iLWs3C3+jgFYpMI/eoYz37pxmiY0 Q5JiyeKfoTyxor/BIKp2TdYLqezFdGe+PyXCaaT1HzHvSNh3BlFBZKw7ZitDRXjkEY/ihG/GTKUw Ebt/tHM1Gq3+zG/R0xTKjdq3fgC1Xg/XtGeW/k0AiTZI9NCH4P2+jmZEWebzOdCOz2qjOuhAQLUC 3dAq6DZv2NAzkV73LuTMes7rfMpdJBVMsuvovDTLWTlRLTuuT5683Y2TRiulFP4gzvhAo+RnL/Ss ozPrOPYTsA7Um0Cna/p+r0n11o5/1YKwDdBCl6SuddjvOp0QPpNPakdgQ/P/ZHHriLnauEQvpNgt 3bqdbQM5kZ55mlCnR+W4iF5Xk/RSepEkg+Ozmcly+PmbjuU9gUlI/HHsJuKm+VtvmxzUx8fS8e+q JuCee/c+tlxvUDRlsQHKEnbMbhEECEGLkwtJ0p9WWVNpW13rT5jBUArNusQvpo6HOW0w64CDjOak qL/P64p1Jaz7be9EBQgrbGk3EZR89YdL25hl1zJtP+/pJ1cmwBFe4gcRwx8eUZSOjOf7fq5VXszu xuBaFofkt6aqUk8FRty7gTpAmW3ko3GC3cHBeD87znX7rzEnwJgoNsJV/0S2I2wUlTu871WRpXiX LOFLD8fTQy/md/LqKRKHonC3OWpWrusfEE8s+Qq14imRL2m01jrUKNIE3MfsBL1hqfW8xFy5YSmp gvd9uKXSU76qQL2tRbW3bFVjOGdsL6Tx2a9//i1g4pjIhvCC8ceF5Eps/csp0JbRSvHJvnVsLg/c 3GF1JzOZJebQR3etINMTq77/WgyGeYj87pziS47NWOQkuYA7niMMtT/XGMqwlyMiRIIt8lu8ojjS cMCF1YQ/9iWJkgWxjpxXQaZEsFVSJ6xaqlfCyj8NqGYE3MKrbmSwaPMbjxvoq3139GyIYtqRhmXU GJRR/ut5FvA6nQywuyCLvoT6w6PSgXiEa32o3jQdSBPXq1wWQa0vmOn4ekv95sbCG3BzSwt4Z5vA sap73QVItI00iKGhef0xOcbjCgr8KQFC/OmGxEZupvwgOO7nOsa2zxbnTXQsSd/eKxWgcHOUxACb Ueyo0dyLjR7Nhmk9M7Ov4BkWA9nK/q0FBMfFHmN72FbepqFfWy+EHrYdFvKhX/C59PyfllfpdtEi Le2Rcr0g/w33wzhuDxvBE9VDNtqVbCNGfYRol6D+uQoUMsLHE2cq77xx/17CRiRGPz023fKp9wYE zVTo4thRDpe/7naoUwJmy16QJYt2ZJOhpUwiW0HtFZd0u0B4DlXxwYatQvgu3XDiuGhijYNvs4r7 nO7TLUaChyvdeYKm9HeXEXCbKlz08oerwgxBa7T/pJNJhmlrOx7VRtxDX1JK1XrcH7RaKmLKheKI gNXq1ofA7UbKKNXdDp22RB9v7nNeptgpwtZQTHM2MfW50XsLChMDGtcVLbWQmoHjoLWF/C65Emc+ 8Tywoz51swolCJTs1hM+tyKJXmthH3f0edNmjHih3LltFub/wJ+QbZ5KKDM436S8mbNQtZsbgRzG pIW06p3SJ9HxXBhiP6yg6XpGyaJUMehZrQ2OYU9+ahlXknHF+0ofw+D+IvyeQGdRMAqQMbY4CEfc wVOKa4xiAvvA54NHuqdXPqqLGTnKnT8naxWvdiuCedkL6F+d4BNsl/sNWp3awSO67hkutSHKIWAc qfXRwZJOl+ARwqy/xmePVNbBMBmaKIPx5lSluUkaqV0BGWCF2OQQyXo+aLurRfoCJq+GVEh0Uazg 6YcHOaOrIebvRoXfDaf+vGHacdBjjMbG+HacnJ4HjQf3BFOSbgQqmsEVMj59AJmOZmKmqnSKtzYA rHudp3P27oVluLCAvzrgCuot8cfsm2VV3atBKJdsvI7nmCwnMKlYO1gmOlbFVZrG+93ZWjTu8kb9 AlNq/DBkv9curg73jMdNk2Rv86Z91EAA/LataLVaEy5pQ/n9PA5GY/YRD1EGHcMAvDIChi5kDs6+ 7T9hK80c6SxdNAxzckfOLcJ1kVC5tSNp9qKUx1SZ6+8pNtkg5nun47NAeIU7+fjt4JUMdyhF4HBI a3wYxBizTM7ahMOjqh0OL7zN2eLw0w+UPwjiRxXZmF+xWQ57yG7nz306P3jjq1bLR54eZ5bGWp9L H9LOKslxhGWkNbekihAjlZVJekRNo5HtHGykBjjIl9bW5u5+EM03vztU54k+6SHZ49sOWQoiS1yF OxVk2ECybAx+mWEDabw9UCui1jppUlemlViNmfIMdE3zxbsBAoqZ1zGqoaUiRjowAzjcsbX/UKDz 7beLWsQHOP9jYrypI9Vy21qd7BNfcj1Ju98keu326FQs6xb7UsjmCrIaXxqTuN2aRlvpoiotn/Ua yWLHJ0ut2aGAfbe+eKBkEAYT7/aUujumIvi/9JSIcjqUadZ/iK41zglaXf+OBxMMn+hIJZZdWN8J INjcW3mzSrmhOlsCCV/+qhfIrL5gpjpS+kT8R/ofa+MrTyPEhIqQU8rJFCM1tFm+DxYAUIgmZrxH PALxjI6v/1wTjjTZt56ODSU1ZFSFto6Pb43lidJeybCnkwl665E1zV620u6KWmZXDfBKiC7lEYs4 qkldPLZOYhuy1G1bneJ6HmyAK4QmkzbUOtwYkq/Ws5GmydOW9+AYOL+i464sub/lOeIDIaTqOL/P W9e8fs4QVrGPe8S56vX8FYJk6AU5E0UKukyKbJI2+A2iJQYH+aU1hocVTSTG/yOtR/kRIgVV3oLS FELzmFRrrEU4GtSHaOhajsONiBeoFeHK9vXot92SpLpjklpkDGLY8psQrA+3GNkVReSKImre4xs+ K9m8nietZH9M7aZLQIN6t6eavV78E9/94aV6ChgCH0Gpjh+jSk+FR2yoHehxyo4xspNeDEBtu4PW vpJsZsZpPVdyaYEvH4GvDbWVY1chbwdBVCbrFYTKXbo3wIyOiPzu2N3Dk/aVlp64FCLvRahb+cne WSCMrWTokth9kCGSOs0wd+rQBGWeEOs2DbVdeumhE+A7+/q30p/cnv0/bt0ZHC7wcJuufUcEBtsg d7wZMmFwnD+Gl2A02w/vzIwSYol1cOBqUehNThOpiJNURC7akmfYMiKKNjzbOtkEIGv5ifgQZa9X A39j9FwJzpXE48m9eTIuD6UzNUG3WSEihHQrF2p1b4hAhS6EWq6BgjgZBkWW7vCEOVXbDVoI8rFO 5rytX57v5WFx6BIDuCmyiTDk+M2h2ujaUwopeSBdHXYrSTlktC/k9yX9v1TugV669+ng5yy+z0n+ Ynjj/lne6TpduBK2+e/61EdLwipCUHiPwQogzIhVW15+JqYxaBogodxCU1wO4xHaBfz8ELdApqFZ 5w8OTUkd2oOGmWk8E9oZ8kkRQrJwJ4pe51thN7xocz4kn9aRV/tS8JMc3lZaDsx48P9sJ5Sbjyti YIsHdD7t3qHePu+9OHkKI/konIvvshN/Kh43ccP3VXlMKnE6oB9Y5NaGzg9arAc0+HtBzJ2oa2CJ ku9cIsa3/QC7ot9LI+Db8pfguHgRm4Njl+5z/gjdGk/U9lRdVG45QIxjbcT+5E0UbIEt7WPnPofU uynCh6S/CvAxS9jd93xH/Ed10gul6Ky0VqT9q64rx2iOPDxLec2K9j0ZcvpNH4f8QdMRfWPR2T9d Z2SivkE5kDbXnRjR4SsCr1JwkZSDv4Ts+napOV7HJSXyPw9rLXH+LnoNc3HzIlOfflHX0ulmRUZx 7iLKI9OoNs2mu2+quUu51rd/GO0Jz2aeJQ4sA1OHAyl4J1j8Vt7HIU4F+AxiStPZHrTZhUVITN+X /0bBpBwGOZlTK0In+6pQ7ob6Pptrhxyej7GkbqH8zhW7ll1Q6eKfWwUZkNmKH5OCUzk7RXmFf4RT 8gEGMmxeisvTGKpDwxEzmbnjc2Nb5boaoVdNJ4+5JgAnzB8eUszmaq4xWjUklk/fAfWsfgqH5Cqz jzFE9X83mt1g+bZK01eHyE92jY8wjQIYbGIo6F4NzZvbfygJedXbvBbRpr6VYxVVYH8P/u/Fr7V8 Bgfjp3cF347XEMYOwenoYTwPbsRgesnfwSgakXNF2GC5V/A59E4wvTtBELnOHDBGddunKSDuuqY6 YXDgVLOAtLlp2VLGpywCU47hepcbv5sNAUkDZFp1ualPcCZOUIk9MvHFNgcOG0XVccalJr+5+01W XKUj9GEoEIQb8apneJXv6oUl48wrLzeUKOe33XiREyEt230lfxJ4619s0jCwC8ItRdULlVyHsdpQ KKDz7USf5CYpOGhN3TTxF8ycEeDcKmzl8HbKnJrOCGDbQbuhUnYMn38AYcT1CEi0G06cAGFskzqu vT54y82JzQxykDwipuwXnEHBd+ef031EKZef8hFz3UjLlNIQy4kWLb6E2giYfec+8O3Md3Te2EEN Q3XqMJzaUDCruKP+RYY4wtwK/rIv94FGRStB0SBLZow/E+eRhVluwKwrxqdhNvIgKNUxeuQ9A0Vy 84/6ZgWoas5yRfSPyYoSyyzxRdTpp8H6Mplp3PyGAypgQnQ8+CD6vhHnaUHVR6U3rTt3inMIDI4L qB+QsYq/i588Z3DHcs+x+NAVIPk0+l0aPnmpidwqPsczj69Y30JpNB03nsZP+tO/0AOSBwD/CRQp L3GSrzbxXpILO62Gz7JSopRgMCtY6SH1+3Uwu3Z5Zbs1xzZ5xunXpcGa3VqlHvzDhWbZl8tPb+eC smu+qXBuMSRCj1OYnx8+Vc/j0hGmOvbVU1oVOGz9TKoUCkmoy9PvVZvli9oztb92lAcxPA5PUkID dvIoA5JhLio3LdXoAb28OT+Cs0Le/Vn5JYXQZEviO9SkRxX+OO7pm0WfF0rbQ2QJe29hw8imyeQl OzfzD5ZISENULP0XvXaUTbKV79IRpRnhLNVqthvuVbntMpa3VBgSNW9D+vyEO8+/1MTXUyMaWx/u qyIMq3FIDNaETOw05JmNL7YOtmkVn1URcXKeuAiZ9Eyi1UBY9Wdih0G4DtqYFP/RZo5o0kJ47bii +ndF1Ivjh0Z9cFSC0Vv0FdaDHKe+CfKQEKOg55MpP95SaGQnfw0gDQFs0Q7uxH8ByWeGnaq4co9O Dd6YkII50ugdUVxOC5OaKLMSwTbXnAxm4ndFHA17l4ZRh/OaWwSJlJHjNRKG+xfm7bza08Qf6LB/ 6nFTosz/WRws8mfenEZT/MDk+L9LajTsit8oHfse/srFkIfq9SMB21pKV6RkA1TAGQ21MI07spsQ qNsTbBKyXVhOtTUxLTPDvl0nRqwuTqiModsjrj2g4FRXC3TXMGp2GN4Jn2aOFcMu4665JXGZnuCQ NnUimB4miCPEC/ZNvK4kv9WSR/lc+pHt2Al2ipRB0R9hlDTVwxp5GpY2jkqeW/kQT44bSJ0nfNHz QM0RfTkEPpXFUDCvpu1sMHf7b5A9EvoXCKMf6i3cBwRcevvSGdwWsghf+m0ppoPabDPLlaNqLQad HlNKk2H0ExLJqmnx6PCLnwnBoBWdKvsxviqcpomALew0i9DmHQMgBSTWWRvegrstGmMJLdHWGv7P V0tIA8GJCvCVZLTEkRSbPhkG9Qghkgt26j9ahwCu2YO/8wvz3CS7JwZClmgrEP+/kk6KMuJBonOR hIkwdUAZUoRKoFUih0/EoBAaQboiy85BOcGmClKgX5tc/01CnM82htPO6/eEKZQ6CGQkqGQNKbIt gHXjldROfzGMmyxtBHXUiRGUvMRYyZM9F4/0YnhWFMa6JmNLIq6Ko9yWqzFo5NC0qpM4KhI9c/Go 9OeTrx1wWJq+yJkQNaJm1Y22h/pMb9z3ZOqQl7sQIvOAzW3w4aTcXurad54FUdunItqnQBBv8MMV 6q7Kkna5udcDT7bd5lOdb4ICddMJMWEspxMlwtjthSoLQilpGBl2ax6ZldnMF7UoOy20zcKUttsR /0J2A3dLFCrnNFHj1zPBQtzTLXHmNf6mvj4YRgwwplD6nN7DYkGrKhOyaxeCMYW+N2kr5OwbPhYz LKaj26P2xmoxAgJRxypcWteiQ8duEkLyZDY5u5ReuLQAWBKcvYMeZgDw2RD6z9BfHNp4TUraRSM2 401rtW0JtLLT1VMPymOXGYtur699azi+p41xvWNi8r8R6cHEC3Q1L2jPPVbThgBjmYj7VGCtjI/h 3mK7/L8CVRgMijdMn7Ti5qeSSj/5O2/xNoZA0ZxE6zt6xpBHSxRlAq/YdEXSrlFh1icH5/UY8Zj1 jSAwp53OSYAzsUdW5/G7qodGnigg1ySWoTfTZkOeGEEYtcWzGDHZ6f1SoBZuqlsYfnbHUXqDzGzq JiBd47Zqt0z8Wm+bvqT1v6rVux8jvvu0di+3RoK/TWfrQxZnq5eN/Pq3Ats+1uHvTDf4G9Wba3uV FkKShmRS7PK/fq3KlE/aN9+YLl3EVFBS7bJak3bRAPIB4L6RFUgOOuZrLIiZO5bMUHaAj/Fr1jSQ LrQHTIVp8Wtgm+LfGjCtvIORg9mMOkzuAiYAe14Mt38opc6yl4AG3Uc97bIQebcU2kZPq76PE8aa hYdQGtxSTq5NFeyf31A4+5U/YCJxQui8B8aYg58UHIhvC+b+spH36NIcaPgwb1+tUcauuEjJsncd 8LSC2AbVZXTUo5qtOYS5i16uXZ7hbIgsDvM3JJ87c+2f2OLdQAqFKCy+AaK81jm9tcuzeB3UuNVW IljpbwBTebuqGJi5v4/S3yhZH/0wgs46B9l2RB3d8t4/puz+jmhXM4K6DnfsIDQLVwFoXU+04hlU 9N9qr/x/BL3kfACZj3p4ft7rIGD0SyLViM+GeQ+ZNoggADM4WuQQ7ZZRNRwCmc7dCnRmErosYPuB f0lJ/Jfg+sx8UhE71gl+ZAuJk7QBJ1mlg8BneI7KaLR2yVm5eToalmeCpI1wZ0FI72YPfxWOaf7Q KiSq5+2hF/rLdG5FfYVTpeDv5Ff/AAITOL+WZCS2StHbicEVff0Xt9xRtfqzEvfn7q5Pmy6AxmhM YI6QPJxWev7nGy9gHq4mdJee+zaTC0TVh+x4Gpu11uABtlMROzgMHtfG9MwCLnHR2HFgwiu2/tpY vfjGmnKGYR+qY8JedoVp/o1b1Cgb06LZbHXr6Yj3V/LK3nDHf+6HjEA6tESjxNQZca97aI8Bkymj kknWogr/oQgyxdQG5ohYbcAIgrfsqQe+3iAXwqAQ+p68w/zunt0q17Pkx/p2bZWRUHDV9YB5V/FL w2em3Z2Wx3e/pF0H7Lho+jguoA4V3oOGEqMACBwoz81SZtYlWLMntkDJIwKFBKA/54Wy3Ihgbxn+ CF/SdV6285Bh3LrFNfMF6PBpTFhiZoAtSS/mf/fTD8Gb4s23rFPWO7UQjAajmvLHSKuZxHLnd4Lr Zc9phHP1Jf06CBiqc+hH0fPnr1YSFRRu+DIOU7fMXQX16/IUtiRjCtM8cnZQ7Y1aEpL83PjqMaqb VePtKHPKrqZw5Et0j7exe810i6tR38ATP/UmhdS6xx6/jJ/h/xjtPwVGe997194MM+/Iy20RjglH vFeg8YIBOwNuRKTQNvns4cgpTK5N2RYgd4oOb3Rkh/JVfE9ZTMTq2eYRXXsOVzDdz9a0m+CxVlFd LKwcF4zmIjYpAwVXajkHgiaK812EbUPjoLSp46D0ZVE9UUj9P+V2XQaHh4jtNZR6i6UCQh37Mp/R dILoA8U+am6fpKKDE0Y126cfnGuoCmazhFx/r6WR5FXM1dNitr1mLhk/SVY/2TdCbrN0M3X9J4m4 rgIUxbE7ic7Z+PcpxMDloQIdlltvZ7l72re1czt6Bhvhv3/t+n0LrszI1TMI57nmCWoeLcjlBhvv yroR6zAA4td/1fbKBkzEa4CZBdTr4j3SB48sEs7oU3BbMKYPcT6s28hjSEzVnuFaDPOIMMv7oFfS 4V2g2UI+O3c60Z2T7UQjAyYF2+ivdshlrOYjMZ29re+hBchb2oR0lyjO0yKRFN8tyxM7Hh69tL8j aCw137LYTmfTEs82XU5obz1UFjL4P+UfRw11BVYF5x6FdQm/qg4MbN75K2byUER+2/zG0Jrh5U+4 BG1hV+0OXrBCnvFjv+/33vNd/lr8ibsAbZouRbIS8yBmg+MLBkVvxZ72kplW8f/GgI1SXsqbLiJk lxMHkUHnJzZsWegln0i/k2ZaZNzMbIbmtK+UTHV59qRVOIR+OQlQV/n5xaA2Omr53uvarR37gth/ xmQr7Swp0Sq3HSGtfAFDQQuIYk/K7gft4pcTEyEL/mNl7tun30kHelF+abjsVWgqIoWQF5tr6asU 5xtdQWtYG12+9fgOL5J7SmxVjxy/Pzb6H2FiFP+cS2zLC4jwYAuji/CTXEsepoCsBTHrupksoWOM dfzyhd/S1/JbbSogyfoFHYIwKbwqnmh8aTDa47sl4Aoer36Y2MrO19tMNCRaEZTxI9rniuRXUDc2 SYnyWCcnIfdGSACHBIXtx2EdItMnWbEbPZSFpU1EvtUkeHyFLsDxa44jCV7kc7fBaNf6bu/Iihp8 SJp6N8IcTawu2GCDgzVTCQkABJZWJXCb3ffrF4nBiW7h+IuVV13LyGtkUoZjJcV2GFxUOAQuy0gx nPlsE6xGiU56OWMXQg0E+ghFOeLwq34mZTLIN7+EHxNdblancN++ZB/WRVihgk6FpwJXlcvuDrB3 9ejuDcjwbuMVaT87H6ox+xCKT0g5Yb4PUbKMHVu8RVHvkqfC+JgeiqwXDIGT3cNfay/4rvKgUKo8 KMDQ6N1g3+/xxxTCRka6cfqCysqJ55gIbz+gNoeEnXCOeYTzH2hnqJitku4UjJr8NZLZBW3KP2e7 0qVfvXeIekfl8tLoflwI/QgT0uSyKicNdtfP7gJSryuSrymNjA93J0PAqkH51XVo803WCKtF1mGx 6mPysvComBYGC7/9+vjnHDfws1+mIqLpRQeNHkIhIanx8j4psdN0fPVFAi8X+0XuKl0j1KOO5uuP JLAfdlphun+Ak8CjWNRmVNVuENBpPW+2FQOEttcG96PTQ0+I4FQDAGLTUcOh11Mrhbt0y9UspDsL nr1us2X7Z/lp5JioPG0ROgp7LICcn+1Lom7cyygXJWXpcupgZ+vZUcoD8loJGtNYt7i9PqH99ZDg CSwHjBvj1m7airaNSzEfr0qLUHlURc5F9MNaS/15VIBm91eAFRQ/vnkk2ybRV1ajNwjYgkUcMnPh dF6pcyH6VxY7ZoNSdvMY8KSP23PiQw/UpNa+LeDso4vGZNfH9TtZnabHgqVVxVh07MhF+vkIaxAk pH3GB0fQW6N/lH+WfQBUQcWDCwepm7kElg03Wqd05cHl2TEWJH5B/pvKu8TuS2dvgEcky5GFYYeL K58SZyRWg8fplc+6UloFkpr8APrzykIyTzJe6zbF6Oepzs0s0sJwHh8pmpxctv/gKWpVhBb06UJw vPPrhuFxp/e+btgrnyGxwUa/GydRBl4GfxfHhZktIOIZcE2wy6B63s6dfP1i1elZ+SSNpdb7bRNx EaBckDHW1zgmPHdHD/Sis4itShJHtvuja+vsLaROR0Ij4menxK5CPLCF7sPat0YwQupnB3XX9hED R6sLIc4oBjLy276hm2vMDiivR6/Z6JJ2tkH2Qqq9iNm8UaJv4vAlsENKa38h3NZW1GkDBkwcWpq2 u51m/Vc5wOPGnn+cFE+hyCOlESPup8V/B+N5eVEVi2utkt1Uq2NBvbjv1Qx0MMrwVSN0m6/DX183 E5WGI1phIuosls3P1HehJQXq3/uMHJmh5xbR5ZewQNi4kRMx7vompu2fE1MuyEHoqwgwM0x4lWi+ ikF2yxEvRUpOh2WzlqbFUfAVsHAtpASqhc/yvHaAuKdDvppELEVztM0rSJrBmKV+o9wmapJ9lVFa 8Th7IKeCprGC/i/+uHmPKbZCyYkeZDG/VwoYFwCdQjDdzdlNDPOD/BpL1i7Z2JMyCEaIYKZ/fE0N /ujagWI2cgfEDSDs+l1ZOP3RYqT5JRN2nJ5lfMAB8KhdftuUcNgvnb2D0Fi77OzOKTGzjInN8x8i PSa7btmHqBnjkrt+vgMJyFqGFrnMa9jlIpnsi6zO0UwFEFLnOXdwMDpWbaF5jgJK8xDZ2qDZ04kV BJ3iVwFieTGYHiLY/ETvvVsbL4HeTOu6XbgpPCP7QGE0Ra9sMP7zqDCohtTn+9etwT4T4g9qOyzD WemVhSz/jh1effxa1ucfeFVdifgwbYuEtoKoQKR+oMcZ/NHdgl+ia/6NgBpoALySjVZp4pTUg55y v3CPFqsCKpQ26Itp9fxhMcznnZuJ5QRxeCErPphMtlsrym3QA6Bc5dJ77U6zgmaRmBrvnIaDS0k5 jdi5ozPZ+Kl7AXbKzm43Hth05kuhXreITADN5rstV/RCM0hLfbmydVPGaCjRi8jqW0pqyMfaa+Ag CDv/xo9VT3xItHy+BXXXA+u4KXZdjXkgTYmt+gdHOxvme3Lv6q16jNaLlLVjkdGb+oNEBvYGxgch oVzVsPNO6XxFunjmYI++SxdM61ml7Rv43R7ZmwJj3d6fuf9Vsfoy/VbyjEp8wdg6A1YlJfzFrBa4 rh2jEX11WskqQwoXa3Vm7Do64eM2Nn2fylwZXLfo+FTjdpk0gNZaXAnJ//JR+YqhCkq0kK1+hVLD S0sLwjd1YqTT8qospmug3TNnSmjjjKUkRGQcLSLWaOfkMNoovPXclMabizUznwRMrMGvgrfOWNOZ 17128PtJwUrHLPdqxKLH26qnMdqbHbtXB2/ssN1P3HLoj3QlHErLuEO4MuWCpLC8uc08YAy+voWk F2Yrga5rhUieMzw3TF26N6e3JMJH0OsYYaAhgN+cAZaCL6IglWrrgxDe75bBu85/4RQeQYm9SNnp znPjC9c3bmPuCvIghzsKNonLmUqFSkSAApHqrGdAyvyUPoU5XRTqQi8+2PxlDQjQrJifrajxKmcL CHSiwbmoQz8jT9PT6P6mUD5h3mM9pUFpaXo6lnc9M3ii41hzVYLjg/q0jUeJVt3lefybSzvw1caF KkqJopAdBa8UZkKqIy8LVgFzmi687wVmtd/v/wE86+ebQynL6j/j9z4/cRHy5UYfo4+2tHDkmqZg LxBIjQePKyPC+M6IPp0JmrdFSe3BkqaetQw5NWOW7qmMDl+vnykHWAb/MkB86Zbf5oiuveJZq13Y qFlInjP3gBBBJtGCqwnl2aBedqlV/S3OPmz791QMX8feWrUS9Ju/v36c6tJvHzVB2fe5h0yyJeSy 6Kcy9q32DIY4xw42e0DQeRFoifGjd6BKxNIhyboAyrA5FhBXUCgZ7laWvST5AOfrgf/b4cyxh9gz kH4CyNI2vDLRtfBhqi/hMusDMdAzAtNefL/b8IL2/2JQCqkIZ8dNwJFo3906bE+zdRqkj1xjpWvv hayJgpGJ4YtcR5aiboWQqBFPN8auA59ivQXGuN11X95Ha1NbcN3Qu7iN5Vr8Rrlu5R8PTA0y6TZJ OwKTDT4pJ782nVMCic1QXkxlHtzwKQeMOYPksL9g9rgxw05XPNrey/bTJnHRk6witZFHShosvMt5 FiTVgp79Opjh4r502nX5yR5sBWGvCCOdIB1KvMXTHrQCStLTXew1aHCHS5B5ciHH8aWZbkbhGwlI T3Qy43vn0XGlveH/GQ192LqSThb6GgCuIAUBiq+6WG8U9TOn0P/GIYkvKxnlpAxV2035l7wBfwot gWCsTEwyXalbwYx9JW4bOJRsGRGOXij3MlbLELhunXOay2oBT5LCfLZS7Ae13WPpPTKBA+Z2t4Qm qdFjaIWbpnQWjlL9bylStnkAOeDB+gRuDUnQ6wX9NtqKp8hOopGao4LNPR19NNsimQsZACcLFXlK ZWUsGUstw0VdsloBZuEpBLNXTqjuHuPyglSqodNA86QxKzEAyGNTGZZFRCpaZScatoJ1ZwUfChPe UB481485zePSehhbGGrIWiWQHQYtABr6wVGNXC6XOSD3Qu6iW982NDw4y6oTAbbBkOXB4uLQmViO AKQ+xEUwdq9CLJOt+Q8I54EI6KNJdHdx+IkT8hLuX4cz7mgp3kv1Pvkhxe9gzYRhL+UcSq/p+C8P kOindhKNyspCtJ5AI3G8M5e1Ske50MM3IEZ3Ujj5ytpzvzYs1gZ8T/n3DG2lOwCWPr3JPoZVrkj9 S5x8nIE4d/napg630iuf80trKJPS0AbpXKZFJXeUqZ8Q/l15Y5M4/LKag/JEDTFZj5/krblLo++Z 5PWD+cqKr+DCxhNy+av5s5iqiCKUlOg1tvGTunUdLzvLHvJ5Y9p68WJG2hhkwcVgGryxCV6kYJRN sz1fX/oHr1SJ90HK2Til8LttV0IsgNjCjzgt9sI13usKHf52mWtnwR/GWXmYx1DdI1bvehk9hrkD 37vZBT5SYTJ3D5+Fg6bjYUI8+eLWdfqshlaYUlBWXVTcQfkk8gp1A1KX1OI40vg4BoDglAxl3Bo+ dJtZXlFi/1i/ZZEeE4NUmIvbZCZV9R/+8d5TwjpBTU3UeOM/UKOARrlKZTnj194dQfNm0QgosR2R Px43uGjATl4o0V1TaLs0hwrEBZSaCvXEX5CX2FS40yH6JAUxjj6dCcG21ZTwDZJRGiILD/L9Ikgl vQoZy0YvLaytyVcFB/+opqDUeKmNjKjmUx5yupOBlBgvbPGslyJEnqUDHqCwyEOsCoAvp9n8UJrv ehlzTAKjf4NuIDUWPaN37XzjJeTco8lrfI4iydHWNclbHc9zAXDCNaQlaRCaJpd5va9ZyzLQkH6g F9Rr9rEG6T7jO/Unu7cYsvMnlcR/DjQ+FQshjo6iAWAKaq+vdOU8LgQRaGFET0ZHDL8iAEYCNCdD 177gGkO9M7HCESEw6HFp6tIWdWh6aSoKYuq8T0T0bBKQctM9jd6GQbckROLie31heSdqpeh/MkcO CIGI/V+gnCX5UnBxCbUFiR2ZhjtgQt/76QP9O7rYcPw0MM6SZacqD/Rmm/59y498AlGkhJgUOJ1P jqtXm1PBVnoRs4nCq0WiUSLzCNL/ies9RuEOvLbhnfI4OIuSBpGlhjiMtUGRmz96ywRgbPcdavGU 8oSevTL+nSHihECKbKlLkeKYJ9wIUNXDMsWhUuwIWTaAucjnxgQ32XuWnFGPoa5dJWA8cAY1zRjU cWBnfSLmW/phYUD/PBip3OU0CEheDzGYygWLO5y0+9BjN2Oes7o5NGE/3XH6aKGTKwzcKaT15LR6 jeCTFQZ/a6P2fOHGwrqFuQnFg1iyz3lsQyxDD4luumavnwrzpc0ytgpyLHnQaKXxbMmMLSOPom+e 7kANPsDiw0k0QWoYvY9p2BTObn5teIHxqA9NjP8xc++eD5xfq/eJNCCjEA7XBzo0CO3WbnQfmsBG Yh85+Fb+o+tNZdra8426PSXnweTpZB0PPvi/aDQcIxncr4dZMpgzx4pka5+T0Nb7K/IK1Z7vgwW9 uE++Wm31R2JuluQdSxG32afsrz86oTKIcOSa6tUfYCKhG/1grw8bEd4JWY4qGNYnpIwcsRBgNUTB XCmg8oFkw2OmI7aUoIc07vMZ7pxl8D0M+7r0F+2wY0sTY9e9jqACL6WvUVwSRMML0kEdTlm0weaY gM8jGC5bc4h7dSiGjH0Q9EFpnFLn/xyiwOx3q5kZCsw+lxPz15hgCl8PjrbPZ2JxjzoH8lthy/lQ wDgTGselV5kNX8Lb0Y/RqvDDe18cRm0QBMxcS56ppgpyE93MHGzfGqFc69LTusuSy4PruaMnmJWU rlGzG6mw4/lwtzu7YclM1H535N3PSqcp2E7iZaOl3E+35fA2NoAnpTsV7rshXjRrpsKkx2FObLF2 Xz/2MXylQNjb5PokmdzhHSC/RT5o18SwukShIy6VoehTOTopV84NCYoy8XHpZhd82MQgqnFG3+oN luDywxgvFj+dmItpMCTPuLQwPr4jNv8sCtjmqnGTW874VUcCInZvLLJ+1rk2O7U2jrrZ7zB9h0aB ++0oAM0vynVAZPIANqKqpMDD/pIMqKSQPu8S0sXmNhr5unMS1m/e+0So6a5oeZc1eKzVnOiGrwsq QFn3WXMVGNH2eOKKcOF1JIHuarOkMkj9klxUvkn+g8XvBPrNHCBWYCuzBW4Hp5n5/LRENu0/ynKe ULbhOsBu307Wv9nH/ifWXoQaVQel/KbHSKwODIABJyDaVq/XbcG/z27YvM3EjF9VD+0WPmmyma0R PjueC/R5fGNPcMq6V5PgofUkaBcNP3Dl2/0GIhdhN5462Tl03WZyLKWWzz7XBourpNcYiGSNNj3H 0dRAP+5ZNVeGY9fYldYJgQWUSQP5Mv+Fyi+sHZ/5uZ+PqYR2WBF5/EB5fh+v9BXtLmyRJM90VEYt FvpmpuG4hI12xD0YbccaXHMJJGDOu9mp85zX2sIoKdTvTw3cf0+HRyOIwUdQ4TxF7hj9Mh+4BiG/ qMOdMj+t+OqWtojDq/TnaxgqhNOMBKy1aiO/nzAfCUiFAIs3pRpYwT62tHEuFzbEcmj1ojCSexoH 6xlMlwOGF+3oL5orzcXJqX6qGZyw0JMhx3JoNl+QVvDWSDRIT6Bpn1mKr3cFGRCRI28NncCdX/cM nfJfhl7SR6/khdUCLqNwvjAi32lr79T5YLddhdWsMoicM+PNpsNwXtUXVbOaz6lXXASSrMwBmdPJ /A+LMfX6XOiBIEO/OtMwIJ2/Q5sMdMvntjpAbje8Es1THfJb4mxBAdELqypWwd5MKuo47v9Sn7KN II6QNLwBPmkS9advM0Qt7D9ggTLos+OUgI0xXSdXyNaAVQGj1Kgvm/x+bqsnuwxl8V+oYfgNDKug Sqsg7YdklaQFYiKM23MZg5qiveSymNoWBfP9DE7U6rPymyXVHR6EFubPV/syXShUFQryjGyboahm ARgm+6szvFyROlRNtATacanEp8LeYpnySXRSBTIj7gpUcMu5CwHv9dKce8Bum2dX2KQHxy6AXG3m VdGUH2fg+n1LTyUJ92LiOJUeV80n5P3NvQZj1bzOmoVpHHwfKF7eCWqdlFfC5gC5zcuSlEM9S5b+ KvnyQMJgk/5sQoDVrhnvYr7SPyxgHrBavUvjBHzqoSwHhoCsKP2Yq6VOaBYGELF56QOHYoretkic 82bSAeERQwmXbpFLxPZyC/IbHdLZbmwPpCXt4i0/W8DYq9pZ/cp1+ySCHOhp+FSxYRi2b2Udu1J2 ZFJSPBoQ4owHfG9Qh101x945MInPADdkP+Gm6T2dWnXcaqomepALBz47/w3dV4fz0i45GlkP19E7 jNO8f4FmaZvUuNhZ99zdaKbenFvcnrgIAJgvFkb3EoT8CHYPiyVsi57B9+Bc/1PRn/D89yM/cz8f 3UEt/oP24olyc8MH100x2/Xf2ZwUFEJWyBj1vEdwE2BB0tPRfwCRP5wVDQicufzA5ujyyKsectb/ SGh5OM+RVFamnlJzPGEdjaU52FM8lzwwDfgGV4eyH/jYZhY7w0Xm0xBJys5nFexDVCwNsm0AaOCa 6CSa421zY6epPqHKc2YwpxkYrVOGzfSTLaZW8uovqcSsSxgxfmbSVrBh6aa8yFiYMur9uJdnNYt0 ERUdyeYpprX5AwDnY13OFvtmaj8wftJ2wLp6Yh9uOxyDsdoA+voYkWYXVKpcGCttZ7U17FpWJ0ZR 8tDEKSGQqA2a6E6llNKUl7bI9TtoTFLrNRlHlhj+CIei4sQbQp2TlWaLUkvoOmZTZJXqVZA2Cb1U ZCe4cE1/G03ve2LAyYg2UTq2O1r15Zg0oVVqnOKQ9AO+LATX5av1P/RvOcsy/cRElIT2cB+DbXR1 hYRADBDKVzXvy4ceM2QArngEfYiZHpLavA9BPa7IeU4tR4PiE9bhzaqMBBvKR4WoT37lArbCDWML tb9r0kpG31kn+0T3SFD0Ah4p6MDROTp2+D1YHn2kVNuqBP9wKnbOSaJ7JEJzMuJGMV8WaLNDcEyX v6ujIckc743lCVJcpPEUzpT+ZED5EgtUe1+32zn2A0GQN8mA3wEyjbAbFC9mZzx6v7Az1gyJadbl 2a+nv+1HNJwC4+f90XT6b0odS66QKLkfTZzaJloBN4gHiUMUbWzB+d+1nbCVhH3SWmW3ZtuF2W7n DjbiELxoUpFF7H30hEm8J66CDym9Xh1xrqksLmuA5aLwKi/1ey8ZDBupXHjQfjJMJseniYIlyHdn z4DAgwwkuOwieZnxmK0CM1k1EfcUNDW/QgBv9j/AgN8sPjK9shXZkSDOsnpoA99Tap7JxUCS4ldf y5ugwC1pRskIEdtGAZmpuO3bfePbKWhNswQyKCjoe4EMro0VVC9zdAQhb5K/KeaouZLl6y9RPdRT 6m8uMem72tdRkabrVIQflWnnPXPE8mfWy1MSZQoz6zeYm5th0QLSDJk8D+88o1LDjJ8wyJMFm3Ql ZpSJS4q9VzeLTn4ySPZCNvSe0LXlW6p5f81HejW9C4T1NyHHfn0/Pr4ib9Vnh6lEJT5V65BWDY8c 00A+cHhA1CjzM4ve043+ORLR2jLwo/+DGM2qukd01QZXV0ztdhr1JHCjc32qmLMo2X5Y25FUHFQ8 UYr8l8gmISY577IVL+4E/sQZgjEF6UWVt2wSnnIicLin+BY5Bu7/wkDvi1ftNOdevkr4P/d2n59W dEBbndVFjWTbQ1ZDVon8oh3e7lJikQCvjzkt+4bTGPbVRHwmvMtKiEZPbIyVJJzRj/vxJsEkLWtL Fe7oaOZncKeP8BedXrvRQdHI5NRPlPEGHwfTriEnmJzxni50Ztq0kpCii67yokRiQAL4J8lmQARM fW/9pVnkpFla1jYfZemaABnIGsvU57v6xmnfGdVvprJy1reyBYmqzdlI5HZtGHBmwDlIEQ7qxnLc kmbph1j0Zxb1WvGb7rLe6Yt3wuFnjj79lUzIb30aXxO4CGJF4FYJwkkUApj7YInJHCmapzOV5Kaz jy6zOfJ8VraBJkVU9Cso/D7heAqBsgtCv/7rBh5KNR0ThHMg/eYwauIfPsm5COd+6q/gwzIA14po McQRiD8vmFN++fSfBvfe2NSW92Q9beBJP9ABAW5TFJwh5msq8TOpP59Vcw3wlcDbyiIFVw7qvKDL 4IK7KLGXi0sCWxbWWXilI2Kk1mQaJpZE4BK9UJOgDsPbykg5E75QDXRSkdm6f3bM8q5b/u6e8b8v XwpJ6zzWcctFGZFskddh9O/SAjgOotzfvdA2G5N+WnqAuRoFLJ38/IewYicCNOwzE2d153W//w6u KiwqsJDTALUlt+NEdACkbELLGaxEf9AuCXp924bAhApbKTKkPtKtISfj0tgqq2Y3WRas4IGOPnsI PxGgFqsmDpxmedimchy+ZajzxmPXqOxj3j0Juju6XZDe/doMwzjLIC3Ool0FM5PJExsg84sM0HqG GsRNCseZ0DisJkEslz0+0N2HOopcqgmM3uIziIsJcLuZsnlin3Ng5MalH6BEFAbmydzsqGYrQFY3 iYZ/8B2cRSxU1oMwlajsnIQX/Si7axD7DCPrecJCjZVsrTdU42dzpBlsPP7p1Iui5z7Hu7xhRQRm xWJFE1NXmDrfHvohkkOqgMzrlldi6RdPpqWnFbD3nAULib3datFfKSPiDVn4cnt5vD4rCg2C7BFn IQtSIQbWbZjXdzQMjG3kKPpPnk94fj/77n43E0vnNhhpSMEAlysV+rVkmMkoU+amEG3HcHkfBeW8 VlhIydGqweBvs9/2MDfhDD9NbabkX6E7LoUwFGR40qyMDDzRUaVuceYejx2ymM+gO7yEyhYe65kE FfJZchwrH641xsVS2Yk2SYIAJL4Qr/cXZmLjQ4S3QFyosZPyiLMHUMFFmyC7pweSbJ3FBQSiMLN1 yw+tnqdJhIaf+kOLFXAyA4nW2dtmByArOh7RLji37lPMKCCm07XEtpjmcGxgwfsK34uYm/9M35+/ ALivzLxeeghs4Yex+u19lX4gkFgFdBu3mMHRl1Aeeu5CaN9vtdBfOWj0NTNFzRi+LcTQG0oRhifv NX/eYdMScpomW5NS47Tu5aRS8scQMXtn8ox9Ncc0O7i2S9+a9JA/pLy/xewflqrHwPUjIgqnAPwN ilK5pNyv0YQERQlBVfNWBPu56Y3skQj9g1VlmgwsTe3WwjkkzfYhLUuKOMSoy7bVhLFQSEGhbjeS KRm3CU3WEjBdfBg/vFmxwp/y0+vfOvIVsYRX03nK0cWC8IlkcVVR6i7xB4Pm08Lc0f3/LhKVdtFh AGp3ypOJtkzY+j+nk8tTUHo2NgpR3BjhgX46s9BAf1tRtEjQyX5j9fgCRqbalSWTJ7JUoM8BJ3T7 JrYz9pZ2uLwFIFsmI97GpFaYNMBjruc97TvnjGBUYv0AXZVmVWmwEU2FAFga/xMoRgT7KXeI3Aex hDxJDpGZGEvPZ8xhJqA9UbgQdyW1x39SnhviAuXtcjkL5is3rEKviHZg0Wd69sJwdMkp+3q3fZRZ NZRMkt0d/8u4Tx7RNGXh65roXZQCY06fz3CQ1F33IEkzR56E7Pf4BSjn5SqgzM1Rsp0WomBHXHVL H9F5Z0y5SNcou/SR5BilT672itm8eq6OPiAzegZaHAjHwNYvpZ5QfCbxoxIyJgNtj5ooYFvih3hC 3odDnl5zH8KRS1/cNGNWb33UDVGtAuTSu8EIHPJKIcealeozStafisf0uQKy37bnn1ZKGHVadyUU Hp0wQIg2AEOt3RA0cYs00GLaRxcA/TmH7qpd5LmM/DlDM1ZsaRAiNiqhqJFTzd/+O6056Mqw/Qku dUQ2nu3/+UuLMzoGq1U4xzrMj91tv5uEYVCJW0jqTIvzmsOYTgvVCoLDSuQNst158EsCL5dB1Cdc 17egQTXU5jH0alEdKNrIr2EMXX/M/DiP71QFYcTHcz3zKqdktXEDmQ/l6astQOQeZOGYkt0cAop0 zzxI85mniEx39Q3HJU/Q0rUVL3YoRE8AjilBiEx0LJJax8VaDMKIOk3wPbjSrL572Sw08yI8CmGm 89l75HySuCNsUkx/8Fczm+0fjLzAvq1BqyY8zaaT3ZdX83x/oe8R6ZqQECEIv9jHN1vZK3I4Ei/v oRys7I+brkXygzUYDN7aWmlLFlc4sEuDaNa+fDazRcXkVVUmdM/Iuf2GsZgHyaEKNr7ioiZcQFWy zJlC17Df7kJwBiKNeYZG6bxhUV7Du4a2fTsJot6p52Vcq2IiY8yIRYzZk4Ee6pTDycgyjsu9nPmq VwmmxPJskv0+Bq49YLFnQaJxyNRCFHHFU7CCGBEOQXeB52/73nVhyXdCiounxpJqYWGBQqjJauUm 0yC0kenvJbNPuLmC6lG8mq1M0w9rFMi4pD0UeHUV+9+VkODoavWktlutlptLE8LxnHFz3G7mUAWw /lLi+FQRjIb8PnwBlceTNER9jwL4hOXIyNI/u2ha9WF6b/r1Y3VoYGi+6NY+8N8zJ9eBlwLY/rDi oWfVmRcSlCSky5gNkCb+wXq+IRV+jjBmWHQMFsjxkB5uervbk/caYtRabvSAj49pBFUGtk8JpuPC ZZfJ6SSjtLUx60WobBI8Ad3ILWDJ7ipNbX8hV/2C2m9tZ0tHVbLkcLbfmbVi0xg5poJA9F9isMs2 gOGfuDQk+zIkmi4rlC63FSDUSBb8ypz8NaXZi+uVEWq0Wn/pYzQsUAjlrCpBoXYc9AhapoptNhMr PfKb+59SxhcPt4FXQjUu38COIVO7D64YpwBxoYlvLPjbkj3eIKlhdtQrwCKaa151nqTF2g0IeP/2 iKhTXLsoZgGYsVetHAy8bn8RZdjFzfSRXZivbfcymUXy3kkGfmG7/N6ONWeMXirbTREI1qsS6OWg 2Ua9SGrnFp6zxbUkog/ue2VK8eG1zCURi4EHWenf3cH1HUVzc+RGYNTt0l1ZNZUG7ldDieWfx7dc GCoULQuO+/NkXAVRLmIwOk3eVlvQ5ZpTfIPro/kUqr9TuVuZE7Bhe9dGQvE7nxrRu7kAcYsnLp99 j5VthuX8+cksi6ZPGgGfJUe76das2U1ZO3CrYBEiNcRR8CC80wF2Ju3p27nZLwP8rTFXmYgxBmBv xgBVRYZOa038t4My5V2Ha1JMwPlvNbNn8y7yhJitppQZfspc2qs5bTf8b87jZ+soNGduQy/YKpvJ 6LXRY3kJitxgXvXRQR3L8QW3YDvXEy9Z4VDx5UGrgXuqroRLmi9wYMQxYYE8SEh3BaqsXD2Bxd7z lfs3p+1H+o3nTK3tAzJjK3nn0c1tv43bKkS7Glw1N4ZqGtZZyA5tKqp3ZMG+ujnOjksLdbbqkXIz 1K+Zgp4d04QoshaBZMPoe/99DhsDqal/XZwxzyS/FPcWoRffb0UFNOVPXcd3I5WxHrSPzYZLpJd4 04mJhbE4Zlk3EENOBwSF9c/GdXoobp601cC1TZWqKkvRCStfM+LUiVArbIAtJx6obTgRWU9myK9R O2xsrPcVXwmz26h7fc2bBzRarg9kdhTOdvHcN5ZemQGWiH/A1nYryklkt7Ph4CoU0cKXxhbAIrL7 xcgymr00Wjc59z4FIkqsisjO1n4pQtGjrZ4/k3DZ0r4kEQ+tXlAhY0BISK1OqWD/Uj8k9zfu++HV Dkb3VoNJKYcOGcrZTKOtWaj0NttjPoCfZyL/3ZpqiRLM8xTduKbBfqMewyvbdQhTJ+iNLuv32vSy fmT8w3K1WxlhGiDrkBLdVE+jzepzKDgwovdUl//rRQJzRx9uMHhoKBXGW30nHg9YYkrNs2EP5dgO ls2WRTXszoMfJ1z34oloJMOgqqpT00xlWSCokit1i/oV1QTS6NpxEyJkvblErYB82JfaNmqOZwjl mOX12FghpTSOsR7cf62n9fxT9CZ059X6di9Y1d5aujsJ3MyT8xGTsz0B5X/BLZdH1DYjui9i3LJO 7DY8dT0sHTOd3GY72y2NeQqd/44QiWufkmio3MdZ2ewybAYM/JWSyodv2VbW6CI3koqsFxzvdAjl HU7XHOiZpJVh5aImPV9Fh/ovF4bgAgQHvTr6CPB4Ubvi+jZRsp/txHJL9BTgN5207yAwNutzsBgY FqaAaHrbCG4l9tNSwUIomD/9gEyMwSNR2Bgy3S2ByYZMi3pPl5Wpv5dAZuksmgA2gZ0tcpjHVzF1 lhk6b1eiF+6bZ4POw+wWMU/lqIzu7M0GckTfKeOUSCx6f5KkbmRRij8dsLE8LGQqm0IQr1URqy1R rn7GsXFnqNXinLgNf8cVoBRwEBqPmY0klP+ukDMXbLdK1OP90QbWKi2rOvpwgOS0oiCfcmxK2jQT 2NlcI0jESP3xAT5c4UcpuxvGtmkQ3mM2r4IPILIfTX90DsZXU8vhFMYbaEDPGcgcamvA8xtj5eY2 yu3Z0ilp930CC+Bq7nWH/Mmd6ISUpb1YeBNsw65881oQWZiC2wq1ZvOnrwc3nJ7nhemrVgM/3hFw xbxvfmWJXC2C8tIrQtsfIykDDYGAxY5BktgahfsSfLvDrGLUP/gzIeVOA6QLiDwkyP8Y75t5jcbu FWMJTdMWxmIhz/XDr06hsblPXGfK0u0HdXfvp8DCTLYlufwdcQc4JE61LpXsW8nedPdXLi1TXYzT Qwb/B0oRWc6NqPSNiefjpdcwsaKIX5vZuUlEZ3C+kvN55ufA3UL0bbm6sesk/G06WJRYMvS7vZY+ 7Hlck/+B8PH8mmfzMud3R96QTJVXgJFtSZQpJwTEhFpxopY/AI0QUXFfUMcBO5v20Sphln+EHhNb 7EpX7WhAvGS4d7ipt1U4dEe0jP7VkU4RVz2JJ0TDkyykCoDUyOyeu8QwwdoCbGOgIIKlhV9PaDSo LtHx1ZE0vAYjZT/tl1ZuC6AdHySnv26OqmS9ajyTCUerTTCJxwCtYEQfajoUWKU/v2qz4KX3PF6n 9maMkPKjuJsqh1b02Y/MaU1fMzP3pFFrJzqHnwPXn/ZUMwL1myTLO+79LiKz+L+/zIE1aLp/xIcK A/FqEIyMv8V7K0R3Zam1hHy/7b7cu5PDtDv65C1M+8/GSNyer+06rOUl1C3egqf89EUnjUf8+xXf ZPA9vxBkoxuJXL/FnrB56LgTyUcKqaGCWR1dLfDg5zoTB1QsozHffL+Bb2v9l7MJ67NUlR831V3E EEWbaX0fnQNDXWBF+4qBWKRS+jt9OyrHuhAtRRIWmZCfMDg3f9Z7gGAmY5pLa8xQkfZ1UrFxFwUl TyIkCDomrEMdZfWZ2s46G8hObh0BF9N7r2ijoFKz+Fa1B72yFdejYcGSd623lxEgW9BTg8THFJxH MyS/bf6kN40jo+bJ5e/Gg+Uw1KAU7qkPJBN8sxTp2BrgE5Xf2gNX1nZjZA/mwJCipdx6AD1AL3Yh qtTMKqRcBi1tEwW6yipbbhXIQgh3AiRXwLCglrg+Cf7Pn4TKEMtjewy/zZHXIwFnFRScVnnmtb3G XKR/u40Pu57wHRS7F3UNT2R7AT4VlF4Y1CSfLCNoIw9THCcNv+X/Cyr0cAWp1ZEW9MxIy5FOxEqT rx3grlzM7VL8Pb9WaGszejx0AkDYPwaNa/JPAun68t+ymtPiuayrF7Cu4dpKrK3iP7uQ+3hqLGYr RRpojnh4L++razxKKeM/RHU9BINIKJpPiSiLaH7rSh2K9W+o9Z5nCcXK2Ql2Kshgnj4A6ujCGwTI oTo+ojCWJs+f3hl5utdtHMoc/Zn3IoI9D7E11WoqEvoBJRAX5qMYUupitwx0ECYqAdvzY+desTuJ ajhvchhGS9YG2TQxkdPYZyMkj8gkmEsYUUI+edgvQiw654PwTEIV7PSKIr2p8i3sIUdNzx0h3GzA aAp2TMT8IIFNLgqAATj8b4fF4nVmj8GIKyRz1szsnXpDSKU2FpiQaxnhmTunfQiWLxM5y3FWdWHs mISto+DHA1RTvWhJNgmpXPnkuFsp7atQl12N2/b0B9cWT/xgSLu9wz9zqe5eYvXGxnQ/+BkGkOXd NWOeVc0E9LqtaVyml5hi/Kqvp1kp/jo+uDTvn/Vb8d05Z65SxM2UIEebCu1F1+Fcx4QvmvB+th/K 6ELoZtCCe6p0ZJC8a/pONJCBv3vEEycOEYTSRRxhZcgtn4zgUHOWJXsC/Q34MfIiQ4CpyyKkpV+G 8Ey9gqGi9OwFwrvDfPXtVY4BRTz9p6wVFBSw5UVdDIK0PV16UyXHzSW//iyUzUvflnXQTRGD+fI9 6cwe631hGcZ2s6nn3TI04CeseQKrQdwFezEKd0sxoLjLZFVPBzmWJG/lD0JZq37hCasOBw/Tl0bo BG2YCIzKSJgRBiiSeLl+xVuACKn0txfPVu8ScUxSpIUJl/rgIhoBQ0tP8g+FhEiv6+YQvtPLWe/C 7lnw93dExeFskR7EZtIeu1ap6E6ldlr1JKi1P/dCG+hD5gU+T+Px0zxb5deVS8j6GfNmlSNXD/f8 Rr61PAVbYKLgDCZI/nwIJM0pRdiEnQzsx5EMZ0oVVsWM8uATuVX03SUOfmeVbi+Speh/qKlRkopX NcLWsgz45VommEvhCtRksy4Dgd1kcZJ2QUtbP5Zm4oqSgIgdIAneEEQnXsJbWkNhQrprdAx/bbv2 LOFXDbRti+0BDClJbBMVcdrIauvnAFZgv8PDcftmzIDNWamVUEQ97p5VPxk3s8gzc34Fx0cr4eQy YspxbHb6xiZt7g+tr0Pd0vAjTNW53xNgtFR1DQqzNvTdq8Xug7hxBxqeUu6xpINnFJyv6xNI0eSc JEvS0lRjmh5GUWPgD4FrWK9ul4R8cxEIuIC1QBa+RmyU2Vh+8PirJXLQq4fmip2eXAygQ8tx8gno K+DlLlEo4R9s0GdM6JAqD35rEDNhu6VOuhyPnoi/HHtmBzNsjPSHes8kmY1iy9OhtpygA2qbjW2q JCbdPw7cOQJdV66gZgPLWN0328WitLwMJ2Z3/wxKzAkxzw9dR7HvJ+E7dcqL06KE++Rmr2CJlKn4 RbU0R2oA2MTODX9s5okOK/ZqDsB24bXKw6cC+UlMQtTcnaOOfb1YQT80MVUckVxwSFrBpkgJgQbN BLebvqzjYPYoIZK2qDa7sQ7VM38CeR2JoAhCiAYpqOmXchDcNrlF3cA4wC/5/xLgbDJCyDaxopot c87hewlwBrWLHl4IB4Wm7jtOjXpDL52d1KXhLTjKmjhIU9/+wTupm7i9oauEeH9A5m3IW22laaEI ChkKZ4G3vMH2LTG9vk+Vn2K5oVdd8oieqviI1V3OEVEoQgo0grHaxCIxeSngZQfoviTvyMepNFby 6dcWRqL9NnMik0tTpJhzA5Hth34A6GoByklhsOG1Rf/GpGWF/d/XWRzt1hIJb4lwvA1mjhbAY54t pU50P/0fgIL9rAjHYFqxdhBnlMb19FRzu8jCC+1tNSj2qN/D65qrosa2ZafmGde/M/ueFuRAzeqU HQdoW+8TjRZ76m0jwIFSNp9yLKI+zO2Zy2tzRW4iyDfdy/fI7vVR192DQQnkK+rT44u6YM+4JDwr A+8G/dgehHJUh50IjMaApMe+A4cSizATyH3gRPhFmumNSxo0B9H32osu7dc6OWUPRmsH9t7SLxAi hWhous00oNlH03mypNb7V2zCNq5VnrBl4hH21CYP0R0ktRx8CLHtDDl9b+hz8QvnYa+XEfr4w9RV vsaPqUkbesbkKgFWrxyHLKjpE+OgL4R3ycj0t1kxmxIe9JFgx/RFt+0OC2ZIDrqDyy0vKhSVK/vR ZIwB3jOAQXxS/gmpPVl9xBm3WTF9igCS3SRrqFujtdZU/jzJg5ODVnnhAkBldRya8LF3CiRDMK6r 9FZfSGfUsl3SmoI0IVhLVHA8gu7Cmhh5G9pM4XHxOlQVcBf1ru9x2bOEyJQmh12dXkKLDBtumUfy yUbPoHmuJ1LqZYoIFPk0V8OPCs6W2A6jwNFc4K9VvpzZBZs+K0Sb1obYjZf9K+8pHGQB5yfP64lL PJBTK/O8Vmp/f/07bAq7JWRJ7K+0puU1elltNJYMToPa42coXzVk2Jq8u5KsPzu+GiCcssaRUVW7 U+1WyzVvYwnpj/bWv8JYyxo8XOepFSSRPO/6NnrcCnloaIR87HtQb19cVUX0F12No92AqD1AcqRV HtAHqC0n0369gKxS3JCC+GW9TlbXLRkRAszb8s9J+Sxctr5X/Lg6UZhFwnDuux9dAmiTyr+qPENM L7BLsPJfAQUWygiugSbQKz/3fgls/hDX73gLSUwrr5zHHkhKprCCRI0KwGlNwCMgc8p366kEo5ig SoeGgrs3+tkL66usxr7CFOUx1BsM5jXL3BDxCtSEo6cGn/Ko17fBCAlQpbhEPsZrT3/Y0itsdmv4 /QrgdGT2xOIwdpkOBX+cTQA0MDLTmDVg/Me9REt2i3HxFhfwSOom7sz6unmzbquoe9tSKUvFvCwN 0HqhP/z6U+OKsUDXmW+LVfjV6IKjfZ8sN5jXdVyNx7cPb26bjafDjw6sHmypiUgeo8Pn+663HKyd IVnQKCuIWwDrUHNNhbEktJtTGPgcGJ+sGIY9eOyhstF1J/aGeFoFPosmq0edv4H3oc4767ZdZLv7 aQQu6Sr7K98l4N2cqs+BklkZWdoSOMT/cFUJAX3Xkpm0QkS9O55Re5zXPxMZFle4nUNCgMocm5nf hZrUQZh3fEmu2bkV6r7TVru7UyZa7lY/7KcnDu6kgTCozF5XJfCL3EgOmp86Ron/Ayj+NuHgYpkT c2llcZpDvOCo3Cen/D4CeS7awOFn5eqRXmHudmt5fY9beSf2B+HOfW/bEQK/YxJ/Os+tNKc1h2bF uFoKvXTD5/Uq40tgiEWHwiTVXW8XleJ70QlJv+xtmjkIuj+RHlIGx7kUBpDpEnwQrTIvR7aNecTf phVrNzt2lGTYxOxyZ453QybX+/FjrPo1booVydOsqaLL2/XNxQ9mYpaTuzyFh6c5QCRmSdm1NWI6 APLaZB7W/oN9a/QiZ77PYn6GVkxiVl2vwzUqnCJQxRCnh3boZRchbFyniFxdBPgP9IDN21sgH06j OgIrpcmFIeshyr2DNoi9EAj/lQgjAVlEzOj55ZjrTtA4bzBlBLq0sDFAQqyb6MWhTlW5zn8WHBOP 9sNmt/Lg6zBRlfbRTFUoV1JRtCbIyIA5UG83mZldp3zL5/PEHUwySaLaVzb934DcOVIwFT+K1ZCf ptT+HAAg7KksXMeCvQ4mMBRSdXTWJdAAzl2mXO4bnWG86zZf7pRs5lKvYR2FsvIpy2WIrXz5JC/1 f+/8Nc5/rWVCtGYkGIo7Foi58L3DO0u6lbLVwC6w2Xnhwv+o+gmNdsdlajR2q/EykfTUpF9Q/cMC Zy/80oxfo0LvzrQhgHe70j5LvJPWTmcbXZUkT+jKNCAVbaoNiEuCeL7HUgFf0L9ft6/OORuXD1BT aKcIIjjpdL12DwVkzQJXGsxaXbZ5pAgTjYm8jpNV8fMf+dAp9UBPgJ8S9FqbDDOmt2Klaqr3Y1Y9 eOf5hgDuG+TQe1ssBEPYbkkq6Mz+bL22wS4AyqZxgGPJKtc5UfN4H8pN5RMXlBXf3OG2yOqXoJzZ Nm/0e0A3x6Zh2IjgLFjFmVe1qPx2tFxGR6tvQVbeb9VUoHZCSevRF+aDszPibp+MJa6DIjH/2xl1 qQVMnr+UJ2xbK+sr2DUH7aMJ4QLz2oVc4f/dYoNHFbhX4Xn9E79AAGEGhjnU2OlO2JYf2wYgTjZ5 K0YBCItp4LcSGs58Mf1BEtCRpFOJzGIwq5F8fZYSXAnspr47HHecmNhVoEyh35pB1klmzcEus+OP Ee6i9pf9Z9n5y3SAKuu9Nm6kXJ/fDbCqUhYroIKSx84lODLMu9cdleL2oglRrkWYSdoqBmaCeTME N+4QnCNzAEImQcm4ACQfBYnG6bJcME807MIFDQ8V5U/g+SyVrW/PqMzTbSpIEsS4cdmwkERsUh/c jCa3rN7CELy2LvrQKSVVXmXJ57xgQbwfcQzhyPWsEIpHXnt3ut8BYIXDsz0cYfQTRy/sUKo+CMWp xpuHFGpJ+j6ewt/gR//AOkj/aqpAPBrR3gUGsxpBiVND0COac2rAc9lQpm0uE0iFfZMWM/bEINE+ 3UhoFUYKBTBti3p/OkYLyR1wr94fVRdlSkOH++dKwTg0DfmXCENTWzZHERv+nbG26Nf1wpwC1dtb KZkFhbhVXLAa1jqDDMzGAFQMiWdZBVRs6sJcCp7Y+VtyezS+uczv8l8LbP6a9XiW/BPESLPhdleT ACi6qZ4fEKNG0nP8SvqmXN62YrSSyI6YVu9eiAnCuWwuyrG6lmMXGB34d0ETrSW+6X1P4fJ+wOKn gYLFDw72sfr5NH0wcZqQZyLo2OLftG192zqutfR8uEGotW6DZkVtBbJ6WajyniZEKQCQ/FtUKYrf JjFKNSariWxSoa1cSEMpTgzE8sv5S4uBuhTbWsZI4BxoFsqKysPIXEmyU8v5voV5LKaeZcqWTEYb 2aCjmrkoWIZG6X3awk5DNBWmZdxS9sJ+k9ssEtBaJO+TOI96ZsDmpkCo0MjyXvUws4IToSWA2SOq OtVIUH93Bg1WUMcwugYCSZCAPWxezictlfxPcvqEncGgJjB+0myR+YB473x8YqwdMMmVgQkWLL+3 QFJdNVgaDNIzhb8zNekVAZUuL4fK6WMV3uciisuhW7YGV5zr0HQqqXe12jIeOFFzizVYcIiBtbUO MiRaHfQqosX4a//xFoPeNcXdg2of5cfAWb+EZfPEqitaytsyTbKNpb9jamqOuDwl9UcGCd/zBrvR af99z1G26xsT/+ufmGvqvDubxarNn3qbCN8vMc6fqXeaQo5lQL2vyKt440N0nkLXCsycidWuU7Hw L1FIIcEJtG2CW6WkVnrxwuoQoOQ5pUwZr5KBsb56lppjMYAwwke3W3mV3FJGQHOohYO0Vy4HZlCp LLS9BUUGkLfoQZ0QVO1Kt0rC4hew9JQEE7kyOagPwumypJwEBzrxinvw+SOgTMAzAimpRW1MJYzF 0fIoBGClKWy/rmKuDKIKQQqPPjZJT9KhYyeJmkjMHH9AwhHxJZSEES44FEDzBINALtjsJiLAQPIy YyCKb+CzhDwvjVoUPGlz56t1q80a8GxyA+PJnXdVM4ljJFXj/evnWR/qnP1nm5EzFjYMBjwIliz2 zjceUNtMQD1FHn0qSnRghjw7WoEjoL36UpxlYjp7Ia4pFfyUEC+Oz74pvuuzGBfk/+vrQJSXv8hd AegOHwNy/RJPdNL/nQb9/2EMIOO2JhGxvzUtOEVnpUwTsuls6al4mfVAvZLJZEs/p8/xgjraEDvl 5LSZ3C5c9eCQTEBBER/NFuVgxKeh+ptiKaoRckCBnpmPJ8VQ10IvQxoWuQBU072FT3Tg2sXRZxEy rOg44OYd83aNWg4g407RBPsyqndBNpYBaFDXNpRJo7OPXcZ6BbzUMki7ytg38sGmPDBpOHwSHqcQ iPQxcdhW0C3iNOzQY4LxGaiA570XxoWmo8KM50emjD35hvmq1WFJCQwZ8Z6tiZnD1zxozINfPPX5 syw5+BwlBi3NJEuZL7z6H9AOBQSizAQS+fUHbDJlbxLgzIgNyWvDLPfEeqv+RWzRLK1W7SxA5wtA 5V3vypZe2J202I2/oJepYPfFvE92XOXo+b7dbYEmvqxFv70A+fIIIYb1WOIMG1TZReTQveMsBTrL QENsnjjQPBTwLRyBotgaWvVxIaq78yyzWujGWb/6AX7rINXfdq8yQs+ixcV5Sc2nbR2D1q1OQVP2 mJkDBhyxHG7Rxp1cvERFKmUPGUQvKMmT2WPNmA3qmn/yQD+8GxFNWeCzo/Xbplfvu/I7D0h+z9a5 BX4NSdHzmDEgerCeFx5VVP6WZvJ1Ij6ew8ajaiEysGip29SNg8l/aGZ1G/B3G/L6KKZvwQ1WyvAG BkMVngXoAm2wHGJ+IQkiC1T/DqYy6i3t1hcbjAFPyCTDgBk/vB4K0/VtiXTxk7RKc4CGZYXPoVPi +A8q3/9O91eMTG7S3LNeGhVCgo2ikSzpSOyzI0bxx1+tbaV5SmSbOhXXIK82rW1LMlxSIG839YGd HtrCIuclZ5FMjh0HcvhxCh6sEsEjh5ujFiBp6cv84XzP/NCgyGS797JHt0vA4SI+y7l0342SKytj xWjk0iLLoqJv2TzyuwsWLhYKTKgo48w22O2PN7GkyLXhBP5huoLYvsfbW8KRWHjaP0nDB8eXvaxb XvuMnR1inG2ZRTMSrHopyO7YDcjz62EaV1RI1cyLlooijzjOUH36fHFuUC1fbaeWp0o25gveDKvq IjiHgUBouORlExJJc2uxoY6OEJAzG3BHwx2/aEcRwHjcmSChjHc7KS5Y8Ef5tFavPgdD0NJ/2uEP gyB5y4jwFbOz19HVd4Fk/otw1jAlwZTKAPkvjF69/MrseGuxW2bq6/04K0OnPVjfYM2WzmLKkPKT /Pwn5ocMhz/xBco3f0qRgENpLMJQLAsSqE5FrEolN4NE+nGXoSqC9y56fQXMpXjPS6cXUbJr5opC vPf/Byi9j0Mjn2bf4qzYGBwYl/Be9G3aHUx5veBtlQcTYIOhjWuiFIkgKg34AF2gDaMEE4Zd4xrN WsfJtXUB/MeeArjmZEO2SYWrkFJtYmWxyUbIsAJKzCCH490f3e2GzvILfHTzMm64c6saUc6JiQG8 Gko7fo2k6s3ixZKvCh7PjoWG6pRleSHZNY56vkyofoFUy2XMw6uL86K+H0wtqdMB/m60VbBgkteQ OmlaOKskMUq4mHy/q4qKihfGfVlpCb3AXSkIGPjhHEz8V/zfQTsJG5PUPeGArl1w2MuCiLStYmDp tKpAEqR+ZCOqqgia9Utf809XkrHb7Z29WkbU4BZVDt74vVDtgZ2b2bc8wJKXRgaM7gb0ucyU1Ag3 mc1OTzqpB+JMC2mUMfNew51sB9XZ2Ru21W3FtIVhIkLhrxPK94+UE9InfgfOGsQj10WgcSOOAt4S W1AZ9N/SJddLtMy3K7i58TF53ubmnRI+55hpIYhEtogyUlkqHmzWAN65kTMywyy3G3eVd3wpiUTQ ZIBJcPlpsA7mPDSewYyq+eWzsLfgQGYhfEPysNwqWQc8bfCWhIIFL4qNvWeplVYiE76q7YPa3F/m yvvYBfUbGDZQ25Zg8wKizcT9rz09dpKtIEFcX7TH/VzqjrdzmDrejFct0HcgD0snAKSsfWscq/KS FrV6i7aZDCsbTCiBYfLn9rb1K6V2m35InTSurvTHcAtpXNF7mec/DBJNfgaIF9oOPfjtaOR2un7w fOJncx/wQhzJA0cdfYEXWzb4Wjcc2Ykcy3mpOKjLvoi/YKwGR9P72IrLA7/RFMC3AP9a2tuCrmER WNQQebPem3USWGnOf+NxujTM4Hz5eQ3RPTNLgPLH116GFfYXUaH8BSCwvtoKAWu+1WSs3hH8iBxG dUQAd7lEfz4uYA6TebhBe8H+B0/0A2pppeHpVeIlO11fqbHvUOe8AZl2L6ZStEKp/2TyhlpUvXgZ WanYTbRfg7UPLmW0YDggw38yZbWbZkad4PTBVi0/HaDjnVawP8uZCn0xS4SPqeGibAbVO4whoPn0 NgB8+VODjbghYZhh3Ly/fATItmVAnJrMmVOi/PUfihhWVFkjT8FWRANgSLQUn8W5uwNq9K495g+Y pCtL5LsHK6Xh0tzBs4z69bC6LJLESuxlSmra2ifz+Gb3ytsZW8zMXwFeZmr6k4G9t04+d+OS+ZfH 8fqdcmjYYSi6IAA6N8HWKDU5HSlVPaPbgXJBD8rcjUalJeFNZtgcve2BE8ZEAecCiIaV9jJddkrX 0stg7dtJgeVsLO8ZfxWdz9bJIUYLcjdhc9RgK19j2Ss6ombUxHf/yedTfc1racfSNAIHowyx+j/R 7FW2XKAF53/BoY/e7YvOnCXKKEPfs+LnsVb5yhsqqPRmB5v0FbhXSgQqcwC7T2Bc0kGTKQaoAV6U 2hQ6EJY+TbjNSeEaz8jsNxKlNUKWNxiyMj70wiwcN+jZ6pD21jpl2H1lmJX+xNMJuvsL2m36GYxZ IURdnwicJw6LxsBvhWUKS0ofVWoJ18ALRvOUT3Ntjhaz3xyBw+t1NR2Cz1ru5yrshvDpweJlh8ko PLPsgKNG9INeh70znXdB5tany2w3/ySM4EEUQaJogeflLZmOLDS+bvz7FfTMFckBctjoJQJs2Xvi 7Ccw5fJMurA1qt3uvf5wod1c6dPZ9B77GQfCQm1zzRmShELF7U8oaT7HYPCqJdd7PpCitekStY7h K3xoLEqCCAnfAclzSXe+7bk6TnxGWUlAh0b5v/quvw7MHQenUgjE5s2L585lDvIoT7V4amGXx9rm 0tNIpm2TcnV7NSKaK3/HIm5i0bP0JsCLfSrGOYjiFYiJ7KIOAcnP1n/IuoYQiM5yu6dXO0QwSZeR NUKecrf9j7B0+0ATqmhReWe6pG05k5GLFoYKwj/zaDBbFgNHIBxMtKg8NXP3WyFbuOXxXVJXRrl8 oXfVTTWTIyWVK7VIGGninbEJ9R95B+Ei0dbSdxjFqMWnBk1OqmyPxd/MynqA8hNIt4ZAl20ri0cd oV4Xwo9Az88gR1xqLSI0mcJqgwTlnqn/OMFqvNZfndmxv7np5mDcTFs7mNmFT3/utB+/i8P1aRA5 Td3vMutFU1HHXHFtROmtclXoZESh2Nz5ZjonnrhEbnjKHaitsNmN3CSQ2iz7jyDoKoAeCHr0yWvQ RfZlZ2jC6JkDZ8ut8jN2bdkmvhIDO5by5kaSW8hcVDMPVg0oLmliv2KxNWa2E4OhMNwnbBKAgPbE P8AmlBDDFefyViY5PhSFOQ0kBXT6ve5FK+7mWBOV2t+JZqEyOQ0XCN6edFCP0QNkmXUoj6rGH7sI KFFVnsRvaBY+1JYFg5LuQhWNBfpdkLn6nxonmeNJk2owpk5zSjJSvnSiqAPYxBGYUCuwTi8TS2XN RxkCylF4HUVxzlpB0yDa52rTRDhqhE5r1NYr9j6DlaA0glKuUVOFe9Aord2mSW1R1IKvkykGH963 6c+jqV2/SAg4BWYEESErloIUA46s0RvkKeOL89iH8zM7QKk583wFol95zwqWBz8Gs3E6fGBvGvB3 OncWCkHvNK7a4Fluad/y71VuCwJA0BLjkfNKH8FB8cuTpm8Ojp1KPX6kgj+2So+Q6hi5GlR9QoX3 nY66ZyUHPjzPTU78jw14iRa+T0Qf3FqhKl98No5zaKnAbThAwIOt68qVAaDu8OJXtG07/CmhEGg7 dd5qAM4O1pQuVlxw4vX9Zl4y3DEu5AnLRK9YJv+C921zNZH5W+4R5/x2G9kbGczdGgq2otutdPfU 5BC+dOmCtF5CcwMPm4vmrGA2N5ZoNFfROHPQ8YBIBsL3UOrBox3+J0/XAe3UAZpeLp8nff4mWlWz pcFAQxyVsLg0q05le0ZvyPRN9t0ON75qLCU5ACXC7TlqG6IhsSWHCy9MI/BmZx0PGmvMLFi7+Wjx AlfvMRNBLEgXjCeMnmw1ecqAa4GK1XQxQu/RWbbZsx6h+lleAJW4XnxyJ1fIxN+2IkoxSJ0euUtr szri+RFemsq989VrltisYmkw57J97w+oK6OzAmSILxtA28ePE+U3HaQLANbo3f7LD8v6wQ+T30P5 rUmgrut1KjkeGSCI/csbDk4MDFaOQkil5EuhSbDk0Xess6e1kHGfuAk7GstAgXAZYhVlUZ8a0rgW Q8RMCjK/rQ87KslnORd7M8b3zkkYbMrtzEhhebCinGSzT/nnRXsFy/AjNxu+sWY5ACGXb1RfvM5h HgWNUy8K83KLDs61h67OhqV0EBWurha8CGGHNIiIlyEwCUSKtBSJBV66UM1E4jFcJRzbEBcJp5ol reKpuu/MwIUJaQPThoYB85Jk5KEFq/M6M+hs82A2UYdbIeLlifRhtd6ccT9OOtgUtixr3a82KbbN Tp7YttnSVZUEnMzrtx6QHNnuCiOW8/8StMXs1i71hdCrm/sPTH112YhdBxxpevgrc/i375mNlVaT RL5aqD0VlFXRE8bNsSWg9isr9hliQgkj0F+gQHnpAzcew+BEtfOI/0di9hlgFvkqIWLkkPYixkLj Ke5ohGcrtoCnkZyMy9/3huw3jLQF7kJ5x/iuNuLbSDAVpNlx6nVVyh7FWcLBlgkwe1oBLxugdBKC RLoOiZujdnZmfsCCUt1GwDUmHGgwItVRmhQGwbasG65Pj5GTUZYtVlKQwatwF60qvY+cfGWPdzXT jVR0pPQj1tdX7JjaaraeRft/g/qczJHPGMPw/6izTJNexWywmBrrZzMkFS3grdReYA0G/GzYcvRM w6+3JsmeIcALmqqblGoO1s9tVAUdda+hSZkP+4/P2oRUZlwThkF59uRTHobCJuXvgCb9UkE6gKqr iJXeGBMvZw4AWt4j0HE17GMLAH764bxgMdJXIYPrwJJtaBJeNqpjSeb1DIEPADXYtSe4BuDv6CCR L8VXfnztSJPtOMYIrN0tZtpfHNVCp8GyUm7gT+DvXSOn4lgRuElH92Q+b3QQdVJRJl9RGjx4JGwB K/d25Yi2x6e65cbhRoytnSlwo3X/mnKPgGdPLklVe/0DYJRwvI3SOCxJF3NdauIG9wemqaxN9p/G n5AZRvuk4YGGFEHdrzIAKvvhSJYGZztG0PQ8e0v9ZJ761FSVvTAjUrePDwsFFGxHWhYhwwQ3Hse7 zQXq3NxwleqJMbajguGQ8qAvT/6fmcVplPPcaLA5CPbXr1FTJYUNAKCvAPskP4OfR/fFC94svbgZ skPYPG921lO4fhGDOguZdmpBZelEVPTIjKctJS5mIXuCmxuZzg0ApQrEnG6XTSrz1BjkGdtycHEq YOXV5P1A2iRqgZBVL9q20OM7THT4gGSwNa4tv2+nHc9m4HfjEcBwmyhQZ1vi2OscdEu9teSdYFhV yp/HkttPPYhuFUtsfo7Rtz2mC2TnRlwd2SHOkRkQEw/h8VAKq4ZpBrPJ6SBXDcfcnld0VQqbePGO smfalQPhRQP529DaxpD8ub4e6VNALsoiAwJHxbKAiifa7vCaw6kM5BmN12sSIO7RyD9voOV0hBhS W0bBfw/+AiH2GuE3rvYZx/QU0rzNPXHXD42Eslcw9KBAjzN8f7U9MBqPWGexJDjHFtZ1J+cafUxV k2pc3s7siG5T+qah1oIKVOGFilGn+HHEd15C40rpIL87Lwl7B69MWZ3jj7o4CM9Zn+IdQ2hQlYMZ XVjOFxFASTddsNF39EH9zPWnKuz6srdKx0kEg3arjjxDtFtjRPLQqU1bUso+Vumi/1QQH6Hxo/cr yyZ3TUWktX9LAJg5+xDroN34nHgqhSoLfNL0gjem0UO0G3bW4sOlRTS0HYbRnlhSDI0QgReXO1y+ OpsgiWDqMPGuDwatPRDGt/YQt6f2UGfMwrUr7oy413CARJ0aD14tERQuxC1VLBra4UdAfguqMSVl V/1JzAD9aW1njbeDt2p2gBggimf6i8zmzXCLRXwxpoE5QN0Pb31oZ14l/v98CXqiDwObmqswnL+v eytP4Ii6SsZO6ibLuCnElCj0CEChBVdv3QWS2DuTsP0Ctp7q5e1l8B7UxofmxJeJCsphFKRA4Ge3 TWInlAGsHtz/iROTaG8Lna8r2geaJjUKYzhFG1+0v8HrZNjPmxNljDxk2+gx36D2XSWwxjp7cjCE QcEyd/4Zpj4j/2usfdU9z6JZTiIIb8NoyCU468LmwGd5FnnAPGlYiGxSQ8/8hRX1U0DYhbXj6CiQ bg+flY+jDbZpCbwodEr3HC7axa03uBPjZhiAK9jCHpM0797BKvpCwFIVZ2DNzlVjb66sUEpL0qWX zoZmVQmVjU+HyGm6n8l0C2LDxN3veB4q60bbAfwKc20b44wwa21crKqOfSCxA8TkkMSOIULQ/WUl rx5Ko9shJaC0pSsS/3oCbSE3+41GKvD41zeONi/3RtpPXgyCiYdpcIZHqr8EzO+HWEtAxTdnHqOt DNiGUnsUz3wpmm4TwWLmPEENvCl97nkwPdBiZ7xn0aqCc9ZZ885UbfKGujElJ04+2Yzs3YrzwfUn ph00i1qE0UcKMzPi+Atll8C+4Vsx3AIuJkaeOVJthpcLCpDrX0wZWH33K3zSu/SQ5n/ASG9y+Rwd 1JWYMAQWhIynSzjFM/O0m3yZMgdjEx8RAWwBgViDZr5XeeahIdfeJE0pvuLI/VaMqy8HWxhZJj2g TmgXnS4n0OE+Hgn8jxhpk2AC2BqNdiiLWJsSDvEjVpXhz4tgZu14XZeJirJfKoZzBg4qQU0p4v6W J8hXzoBBvSK0iwZ4vra2NI4IKL+VOzxN5lHuUP4lgHocYxtVOhXkAt/iSvqPG75EYoVb+yVl1JSk TNKg9GQ2d6x21zvgltrDXI5tUwM8SFpLZG0dzJrlRIIEqim08Ew2TN0+jxOpPDe08nWmKfCNgOzV 4x62O2O1/Rk0vgqx15xjHoo/4yGtgiBnupxAt5C0FfXjk+rB5a9VFFBD6VfMJOzwOUf98kYhE7ei /8nzAeQ5zqNekORf+3GOk95tKXLjpHhzZgXISDeO2XPpqO47FM2VJQVM8T7KcYGykR+1tAGvLNzC sz4WjwYSOUicHLeBw6Vw/eB6OnPJUrMnELLhHchoH5mGIFKXeXbHLits6MLVCdlUtB8TnDdDfgNI QfvuvvgGyqPcAFBGJsVB7eGEBtDwJOIEwZYRbkZgRvRmudTKaeXIOT46d054sgbjIkQIlP7KUBYa NuBKSrtik41n7+nlM4vQtMXJAKaQUZsEQv9zgjzU2rH8sdOq/rkq/iuQVeySc2VUpuvXB1U1Pnsg ghhoc1XCXnDYF/A3oqwfvs4yd/uGGIQL18osgfUSGEwpS6UL5v2IKrMSHJwT+SsnJstAz8kRqwKu o5Uo1uWehp/O0RCVKsUZwa5d9DNvPUG5OL/ph2gFpeAYArS2BfdVLtRUl0kRfhdTfNEY82/HIXdH rOmmHHMOL0wQufFJ2b68vumfaxfTK657EJda5MuXv68iCY5JwHRRIAtF2ofrIvqcs7vVpt2wdPTm cdrWQD+dOPU8LCHwl0CbDM1OvPeSSj8ZZ10A0U5C87rQOHJ1bk+DnXY4xCa8I8FXiPGv3j+Y2iQ4 rmkIXRwE4PjuX0+A/LQwUA/BB/j/LO3Z1smLAh7hTXuGse4urbp/J97Nfs3swi8kX8DQsP4eeMZw aRaVHaOi3wO7Xu8Whi/VF2i8I1MwlWTS5hXo4msu2X/j/n1c89nylSeXgaIYhbqJebk065SCL/T1 n7Towl+SxV7w9O+Mtgh1GdvEOPPeSdUq2ZU9TnCS1BADWsqTaQFdQeX6cN12OM2WTPaEoKgU9eEz sDUz8bX5IAz9bUkV5II2nGpKa8lXvFdP0V3aTCTBN/uxG31IQdlv73IBdku+sxazI+DAcpWa0IQf AWvhYl7s7znECV7fCAZFyl7VpRf0ey7ML6SJ3qSyeU7Mw4rL8twzvPLUJRoKbYcuoLRG683UQFDx khQcbLHF4yEdOjDViwLMVMjY+ZD2FE77k/U66ZTXyI4I98EOiU61ayyXnh6fNuLJpB/1TenzSTZ1 G0CodfIakTCA2hhmq+vIqIqLVqZiH8ib02/nD8IX1KacGSvpIf+eqeYmbIJABbQ7SqI78DwIUzKM FGBXPotkUZZig8qrsM0gsLnyYidpk/70uUbCQ+abBrkrfeJNSOK0KW4EW5PF3kcRYMuUZo/noULc bOOvICwm4CrRe49k8ugAV16ZXFkcqHzWUG92xVaR54+w8Pp6ptzEir5A5Uk1qyXnmxmXNrk+aoWx 24hWvkvRQUdP7ui+FJcV4E/Wp6Qid9H+lkcAG6TELF/m7Qlveq/paQyW0X+NR+XnfhH5D/qLnNqU pmrwjOWV3FMtI8JSml8hn+DPOZqaGG4O8PD9vyrgJ5aAxySkMHLr2rsW7F3ITwqPiXVowN3kwCbd Zae44yO7KRiEyLlQW69Zxscg6RjMBSi4T+EzMi/UO6OXBExOKUWk7mX83/K00GeNEBYCT4HkJRo3 onHiAR3xEr/g14uvSu1x2Z5gFJBZNaT2iS7CecJMahAfmvwuXckvLmrjink45Y0KDuaHx5INSl0J LMLKjZaQD9MB5zL18RNCz48BY9FhRce5iQWlhtzv04huCb7bM45+CArt7bdl6XmHbeFuj+MdlOwr FN6/7JcnKTacn6sVHPEWfV82Z69J5ZYgvyEWGGUn5Q1PYCTlI1Di7orBCTBWYhFTJ5U8r8Oy9kmA WaSBXyRBUjNVZAlB/dc/REid8XTA5PJXKa0HI7AO0q+GzJ+wrsETiIGK9W16Py7lpIGZ9ePg1JuI NAHBB25gz77XMFvF+CGTskJfg4lUjoxrpD4s0Gc+AIL7ty73iV+5g8N/8kQyPUQmYUPXbZ8qWPFC /ADNwt11QvprsML4RVxAF+XunWwUGzUMe8wqittpg6Vwozwo9kKUtyFZuw35EAvSOZdJOe0Fw5/B DSFtuIJX7WInrpiU+VCDgUjO4gRF45kGQpyNMLNM4az1qryAcqodvAkRIKSZx4n2WGle2nmE4035 zahlh0uLYESLyLRWS6k/qNEqJDp+Yx7FzYA0KvB1q25k/YtI3N6JHzpX+qfEGWxkO9H7LbkKEpg3 MS/kSH6vi/qYSsDWheQfhH9iXwPBpj5buMRBTtbGaqghIZQkzTelwWeeTHEUdTtgd1yjuHT72jyN nnyE82VxD7WJfYSidSR44VPY/RnLfkLXH9MWmK31DemfL5LUFc71p+q5z8PhmYqsPstDVoYbSiBT OZI8H3FijrWxPaXdgAHca9PJP7VgGaeJa/imQUM9+Zy51f8yS+iXrAsrC7BkYex8iOamKavjN36e 6ejmIRaa9MfJVO9MnU3Wo4nQXbijDouIOCgyQpHnCuYCt0U8hOL94yBfPx4oGy7ZlV/QY5wCIVr6 OqWOIK1B20nKXnGPv165kD3Rzj/4KaIim10BGsc/DHAOPKw2y4wB4W+rP2T/8SvfDkoqi5gKVZcs Uq2l0YGwmmLkuqyXLUhAw6MJLTkI5lDIJQhHo9Dl+qrjRSi3BORCnGm+3BuMJoX/+Ew0VJ7ssjry gXEs/y9otQHE2LZckEdEHEoIm5+esXi+mrZxdAAGR14JMPO2WgL5AyxCyWcG7iIJy3rfyeyf1aJF 19YDUEBUQuE+xidiElNI+rJepKV2+PuatpqlpcsxkoUn+UjLXAfFECNn5QmEn4TNvYSFua644OB9 0UGeg1X8ib0Sz3/rG6BgarV228m9uX+maUYJooLDqlg7sVx/aarrLHSamxRZWwd0HcifQXWH8fMi miJw6W9dJiXDJ6hKytxLStFA44BauO5fCMglIXqS2u67aa1Cjb8UBR9CM9ww4XfJTYuQdFIIq+Vh +bjIYmJQ7l2yaKJ/Hon27UzdzKUoF+di3hOQCx6g/vyhChtZ8rIVBR/EsGKmGuSCvHhBzfqMF/1J hpC3r6XK7o2eRlTQ6QEIjLuYdfgn36KZb3H5J0AfTMqvskMppjk9hlwO8SfdLAss4fG8FUR9wbMl 7Z9oEBNdUDgxPK9yoSEecvC86M22LhSi6HaKBv6mvQLGuhPNM5mkMHzjtU/poflkgYJV4G38zEj2 wYTvgWeBDElPpPivsmxMOm+bsXLvn/9o2+lM+uRrx48FUGiba04ql14Ym7Cug9Uo2BBoPwWEIqgE LhzRdlubWop9u/QukIuQW2if7Wy4BQ0ltDRqAZa/ihbcl48sgOiwcaYw46w/DZonFT+ofUgoi9Qb xX0vZxXsfHpbY36O9jaIXXHzjrIffwDo4SBa+YOsKijKhZpUkT2ecSNQkr/zH1J7yKoYJt9w07bM /Dx569PbGQnl3SsdrO1n2wyDqStlCXHZrbq4vp+/mZEDwXVP8BuV5F3nrRwFkXKbd7ZR/6YB0NRf iajKQBCEXDqVBhDCCE7tcleCPYuPG4V4hiVieQyuYE0dCJ5mTjxyuliUSFP+3W8yca5f4dVd/8Ri UgZiUBzyPmDNl4N/ZUUZJDmUbibwZbNkFhQWbg7d74naZun3RYleLES+RZ5KaQ4ZOQ1U7HCUeFek 0dYRf6LLYyChEHp6iI2SDcTmJmTPd3HDROWNRJOivW2/Df0+MZ00wmVlMFgrX0aw4gbcyY2ROrtB BEkan1oZcWHSdI+hS5+Ar7Tjhir1IXq1f4Zei+Ojoqok+jdxuas+4I3Z0ONLn6o0bzyfpBlbFXWZ m5mXqTPw7YnX99abkUidigldk5WlRTsYYW3VjC5Mo5DTfPHKckc/c197L+nrjEowhWUFlecBH5DX zYCARQetNm+jl7rOplFUOvSOyL69c7rQyZ9YXzpjOGLX/bQvq9jOmPP4y99DUIQ7Afv1UcodPJwt TqN3PM8kBRRPi42oBJBzVTRAlT0XGJymkLjHHDbmyQ3iDmr79HjZL05w/rWNp5Q/ktxP3T2zz0pM tv7UpYiM/uCDn/hzTeAnB6GTw/J+uhW8YF3QrZX2yy7XL09U30FgTrueN9EG1c804umpx5ITikXl TUe1h3eIF319xBpXKRS4QBqRaetkj0vkCW8CTfDObrwP9tZgOrWVwINOJFvVfKQnDia6JP+pWZUm L6rjOD6IiA//dpi3mGfFVNWyl/07iEn4nGV7Z5IA2Fn4+rvxMxVNkPSY+elbx2xbOZMOpstkIEPP cc0FYNzmnow8tfIgZpkpMu3CFcurf9RhT8KycoBF4jUZO9ZJE29xJmnayhCvHMg/awj9aLvT/WZ9 gGk2Ldj5rzBRLumPoRHRgQ95J8LcPUre5dPA8BYTrC5NsWI3e0TSisfH25DUJ959660hXw0TlHXM Thx9pBmNLTEy6TGJ6wabEQWF9oS5FA+sCHddwRzI+SLCvGb0Fblye96XiFOHDz1aaoPWQjtnFDUo x9MqmWnmTQs3j6SScn2vsGae4qxaJfmYdkFRaoq4ZNh9gRk0UxYKOVXgzi5IqSqHGgH+xRZnBUN8 wABDGOUSE98GCX6A1kNeh3Yfa5bY/GXit20CAZ8mZPqpSRav00aIT+qhjia1Nqnkg3pxZaFUN6Ke 2NnP/TniLcHqk1ePnPpRRaHaqMsUZq3fEX0HL/J/dkNB/3AuA69uq1yF4hBRmn8EtBdDaEqm9lcd z93aybAFCL5n2cV52YL5nSPMeVJ3ITAcxMspYLj48LAWuin9+G9elP1bdArHbyHJIsAVSI8EllN9 mY+hZFagrmWZQw+RPtvvy4VZghWaJ6ASeTbrjdEvCXpvm/0agYSX11WaiEvqjmN671gjJas5f+35 nFPLBguFvLGphYRwVwwCxNGbEQBuWKSGI1fYrg3D9t29GIDvfLWnDP1ulBxjcs0sREKOpmY1+dgR O4P419d2/UhwTIyV9eRBmiLCimg8G22S+ZQVu9/DR4qQPueTujqHm3nonmNT2K4nu9S1lCPDtjlm Sr9GZrEwRbSEr7Il0fuZelXL5ITY5o8IuNK/Z3hia40chfk/gPOw2rpku9juzUBVue6+JUTvG8R/ MWem+v+O/qZUHlM7d2zbIpu378Mb2xaaJ7xEs/Ufy7QpYWM2RgLZIciIAVSnU9Mic9Bnt9iXVN1d 1DPh0BUI0bhmjpI2MFGVsczxPQBk4APPytI1cgdRUzN/qZ+Vk/hgaHB1iwAfqYX8+1dj5YPisCmk 565uzjcLUo/7nqI17foE41/q6krNf/djVngYqQWOxuj9RGCiyBiyIKJxMpuvxOgRkWuaEg/AxhjE Y3g4U36ORYYbomNChuL6qK+lAHSsKvGmEa62nPv6KHXfDLm8tWcxAVh7F4IeVIssbSs54ueXiYo3 Rvo3fIEXQ7mzx8GQ4yzeAWN82jVbgcWIvQYnWqeL3DkyKGrvVbPDJHa4cew6yusECj6vq8Ebipt7 yBV0EVcaYBacWs1SAG7uInj5CodkkjgWUBYLca/UijorxS8Gzc4sRRhwQqPGEBITgNdz9zsiCjDP bKEZLLtD8ScHxtReoDuDPbz++ch56cXYAUO1ZKCIPRtqZV9Adsp3bZvC4wVZFjb6VZlxDrBgLDw8 99DZrT9DwZrFB7ygyAIrChpG7gqzL3etetDUCnUQSFPJD3iRI7OLV3mg+FFU3MCpGoI9p5kv+vxD zu2I4C/wEqEHJdbsW/mTSVTVSOuKvEAEdxEeaMiESjAV9Z6YYP9iprT11K1LxwZW7LHxGvAZeYWj 8YBRuCB7UrtHH6/+eBcMYsNZ28uYjVRacB3hW1urwkNuFkJxj5MJrwE7YbUpJ8dYxMo6qblPVbUk u1dfTyB15Fk2WhT8LRtREZxHoVOmq6hrQRR4Gmz1/k2PAuci51i7fE8ORoDxQaHWAT9ZIH1t4CsR AXsSHicxa8XI5LJZEsGiY+zle0RFu0TFqmSok68LN2E7D081ggiRIrgblc6kQQXluwiDZMDCii9i hus7ycfYQsv5gDGzi3hwmzcd6sH4lsN/CY7Z97kSkEaimB4kYEiH13HAj3ILgfh2T0uBktBDCP4x UaDcklUeg8zRKb7slu+9ramZ6USLAalRpw6EpFi9Pzi0ESXReR9OpfZ5W88kZ/jl6qhdAJZ01kDa LaGS7l0v8WxQKLsEuMbKn8dPpqlf79dyLbHfvhkqli5DMmwuI/KaRTLUOum9oVlZazLQbeD+j+oM 5U+spmy/AXQtiPBTAQ/TAiYQCBgSVchBdfv6O9d5aBgpd4XaeAhCTUyjRWnlbphsdxN0KxPeR86R KR44ZY3H+ZrSihuHHIgfwTaIegU19ZuC2QcC7M3fO5CAwQSpT2ZYRpOiDPLJ/K7l8vNOhdPZaK3G WONfrK3Yw9RMNC74/IMMnv68caLhYPND5hlXvcpposS+kAjuoziQF9/cccQDditLFEh3F7SGniuY KhbfuKcq/7WK+GF142oSLFhN+CbLqzMy1Hrj05ltRZ/wL+Wp41bRV0eSCj7H/Gg3L1rNbwVGsB/i itpwA0HFA2WoeR8R9LonIJV6VW8VNWecVxReHlQTgKbfYM2kZDp3aP9mwGGh9Q6iILH+F+Yyb83b 5xt106IaUSs9F65vj/EczFyAQ36Oxh/lpiGUXVKhgfNgjeDcG3X+Pt3Jan107oybj6fqmJ+oAZSe Lce9VczMYPLI1ncdYICl2DAkfG6byXPnJ8ywNExJ5mFe9w//Vg2nLDasYG0MFfLyft4rzc5LshUQ nqY9GxGv9On9VZpFYGcqRv8K/X75K0Su1kdD8Hchj5PxX2lHtr7iwmRIuEnyaGto6aH5tznahnBD AyuOpDn3/4tdhttzNTfDAwlbVBq+RFV1XSuLSSYg4CVV0HUzP7DqqEV9XU1jKjIwe32rBfu4jUZb IrIZAcpvv3ZiT2chvO22bxRjIGnPCRuqshr7bXwtU96Dxm7HuK3HV4Ji/mrwXdcc9jSraDuJr3C+ A0nt56U9GvQE6B8BB9usuOVO96szKpuTj/UP7gVM8pDY+cvzQtm2nyX+mxJ81CDMhHtI/yDDlz6W x70oh1Dm47wdI9Cm/oklrBGsPCCQcWEvO47eFjJzOaSAGdrngW0jYBakBRbB6DUjkzUQsQZ9h8x3 85TQ4RdXFRMYo61Ic9pqhwXxWUpRVOAjH81Yki/zlS+bgCRmGaO6h37bzQ9daYYiNtqEXJ8MkzdB J+PjzlGKhi2Bffd/9mmcCzxYCow/28/P1ZeKj4UFPjNUYTs306I5AHfe9KrpIbARVY6H8KM6lF9+ wDFRmv5gq15+bqWXTaURPTrEWBstchUIimHN7m9QBs+eKi0LGv30K5kUwBxefisfytXriiBXtAuV G9jJu2da9ypg7h+PKwQFgWOWbmVEaoIMiOtJY2OBixFzQqZU+i+aujAiB4kLOFYzvEgRq+E6y+ii +KgueoOjlf+DketlQUlfpK0za89apvj7dug2CBjNpm3ltore/xDanV/VGoly+XkhCFCPxGygrwtk yJwgkMTmCPEjfaObV9WGYxRWKhzJXZQfJmdFjy8pbxxBNrJqBDtiir3+LXygxIV/Iy6W7IHtieLb vpa5f0IOI7adEg3jVQr4SfZQisoeIiagPKcbrPFQiWDNTxNjjeWg/ck5BW2DTxQIVegb8CoigBGE Bv22pdMvIiyb29tTJluBhJaoHCMTiCtNbBPQCrUo+st9c3AaOQtsDBOs3mZg9IHq5NxXd1iqPKJp VsEcsvPEy661mGrK/CC0torgZNj+Snqs7pdBigH2WQ57aSuX4jtCQ5QVZ1yIy8RoVUeDWXaqlF2P yo0VBGFKXfm6vaBBegzt7I/Jidgzs+YE0JL0usaObcl0/TKJ2/ImAOvaZi7OWjUsvSvpc5jyvCjS HlCyCyvN0m0gdJDFQboxhf4esWcRFyEY4+1JF7ST7mcqwcp+u4HS7bVOOpGZrLSOu7+KgG5VlsjV xy4NxZp2iWcLJyAgNRSYbb1ZLZbJVtG4GPMFGHEl5L0pbTy9JqM5/ES9DL9mngCHPWzzpLYgv2w/ 1fDSSHZ/wvFHIB1wcLZT4/CPb4O2fuV6n5j7mkO47hlHtyDHcSbN2CAls2c23+jgJzdwwpOris4I MsJ2GP5J+jFSc8RwEnu6GBa1iI2eidpwKmwasryXWxIYADcjd91mEGLWQh7+LSmw2xbtYXXA0VE+ sIjaTyLnx1QYJK7r1MbrdM4OaqEGGibeHTzgw6tsHOQ+rU0ijQ8yfNUUZqTtE0X3G2Sbh4/m/moq vCHS3n8g6hjVIxMM4af2D/tz51kGKSME+PkV1EkywhSmFizdgPlJYTfewqOJerqt5OO+6fofLv2L T3Ep4zKWc2o2xuu+3kqSlJjRR+ynL8t5CpoLf/c7XML/+mvfxoa1bNds6EG4TKC6qFQWAmwX0KiL 9ZvHtpNglOgfip4TcLlI7WkMP7OYuHRQvhdRN82IEs9gq6ZFIDoJJXT4G1newomQsVIa784cJkCT QUxCapiMRhhCgFVyPc9W5kr17j1R9ter6Db9CvKDxgf48TxTCQrLIFc5+UctIsmtPE204ebi5xPs 9iOElV6162pgmmozHEBVJlTOTbv02OpdSs2Qs7vqNLCzVdzZWvlEKtKKSxgKPw8gNlSCHl/+m50B 7IELaAOZIPzH4yNxeqj5IT93GtqB9/Gs9RuEpDKjv1AuW3ABbRXPWxAYdWJ7tK5uQfp/YBGJETiH dy6uDqx3166Bi5y1/pfklxc90qeR65+iGuHbJqsfHraT99+NABSITkppUxCYcFaPBlEDYN7HjAis E7vyPIRWlijpvu0VVwwcxXZld8jlMDo+aRJadS8NYzPVzQVufIMhzCHISYzABBuUDf59cfBDgqXS rVR3BZhBmdTuY0CtLBVUbATzXqWggSclnlTMzCRKEGfB4I6fZjpH8rl5GZSd2OaoY1cLc5V6JQuv dSowKujOOOmez2RdT9yeFwTTl9AmsG0lEX70UcO2TM2lOHr0R9dWrGqpSTHhAq7+Da1fD73Tl6zL 5fxKdWmu220lXxQXX79UQu0u+8GOU3ZkQBu8fGFdtSQcNBT/J4y8OuJpEvpyaVOlUCKVLiF2BNNj DwWC5bJOEqs/95YjBiyP71A321f2hs/lUTZRUWFG3hQ7mzdR0tEiAPpll+8172754nuubAFFCyWy sXOtZ+BVGi4AtW564PgfwEAUH1IM9XDKIUZpEC5PPbPguAhKex09Ttayw++mXJp92feEzmTmlOZC r6CboNWZouWrsJDt2vnt7T8Y6mjQyuy0gogSpgZyRqQSWKDwHKiZE6l/lJRUdN2P9evKRwtyrbKq QMxCoOfx2bmeX/qWbYwbgfGc/y3hrDvrDPhPjshktjTKPuexX14QvJmRmWFIvTLyZm5/kafoGD5J xZRVHLFdKoF9sbpxr7tk87LBOHpcT1+v2ZCY/oTjBf6S3bHhydHZQqyU2xOH75U6EC6uocZWD7gx ncnDJizO1SYriowrPjDqv91e37579kig8xlloCrqI6n4UvNcHpY0KLHO8AJUuudYf0zr9xDWvPGV iupddnB4QjXDlIW7MrySLfXToBnXjxcope4fpkASjhBIKGTOfZfD0yI1lnUsZepVlzLJxWuh/Lx4 5ffRKm6glm07jahxM3/P4W13P4oE5IRtyKeeNC24Qsmyv7uLWeLLridsbNdTSiwLHFjYNvy8B2Ud BDfsPwp7cYgmD2We2khEQQbs08xthU9ezqKYzIpxcRxVerR8TSfhOQceBgZZ9LS6jjNC6A16Mpb5 HkZYV67KCoQpYjG2C94uMSnFAX7KMttLQlcrbCU3VDuDHTlYwVr4VxhGq7mrzIa51WmNP5C4jDfZ q45Iir50DyaK3xGtoN5h42SOHn1R7VUtX41VLMhdld+qwvxXMSN6smEMWTJHk+pHCIiH6DubKkxA 96s11q0oAShLCOBHcIlrYvVo7JiOrvaHGeOcEUby6HEHV7jee2jz3hFhxL2nir6mVcm2Eo150ZA+ XR+NpDqYmOmtdGvIci6HlMYW/AFYQ5YXlrtmWvnPN6SBVB4XO8PkJlkN5saqPiPpci+o0zvLb8Ec uwmwhqWmlqVQZEodRcbz20Ziyr6tT4S1xUje3MQeKv4M0NFf0gMRQDIQYyZ44l6CPIURbujTCXPe AfCvYvQnP4t2JW0Na5kqzfy2GPK5eq5EDsWGSxrFIt55Pwq6aWNW0KFdAhhQMsJzazsLjA662+Z9 rj9PLkUSxZ0GqFpLa8ibQv/M6LCH+qrr5fnXdv2RjIMwgkx3pf7Y/2Dnv/EHhmdzQVqmkxd5nszB epXa1NbwuvfbfQiFR1u9ViRzErw4EIWjmY+fOVTbmQBF07G8rfiF3BFnKCqdKo7lu61InM77h5Iv ACweo0qtE+hP/Ftyh3Uje0BxlxZInDXWfgLF4kk+bdhIesB0tRqoOqP+wajgOEn13p94nQ4W6/om 54YT93DJBNQgDbCvYSxVnAaHusTfyHo/Z18PH45YmlQnTvyHZqwPEkGPOGv0C4yVW+PqVfSIHFg3 760QpcrkGqQjW8mmsTyWR4hsJtlqYscZb/yoNC2iwjH1MEp8lpwWCQsAuQoL/DgVGRQi6NNNE8eW 81oju4c4wdbavfW4zDudgNgj++ODbZIyKwzLZ09lB1KpRMzDB3OJRYJQTA8WYngpa/VQteCOMRyC 6U6gldiBHwbVmAlak4E/9Jbx7AV8dk3Iuhak5jrWSO4OuNESmSFLAXYm6WW3AhABPqTRGxQnO8CF 5NBdZ1sZ0qiKfGIRD/Xo1XsrLC+kRcyEbSPGy7oWyLi6jlvSRkL18jUE2rHzjLjuX3/AmNbLPfeS RzkVOZFmN/lqkrDLIM5TfUfXOi7VYUCO9a1W4sPzgCD7O20hlAmnCXOcXG1MfORAeTYfM77zJx6Z TYSFiWI1X8k9vXVdoeyXnHtN55oUEmWPr6jMZ3frvcdstvJ9vlsYSk58UY8owhvPlvA7erm3Rp/O mJSMbSUZlitWIVjkhEtqXYq+J8/f/v+eJgup9MUeE+Zf700I0rvIQKytix2vtEunzMnazI4aV2bX eok4aE1TE9gKCDvihHUzRH+8WOy6lKItGmzwynu+5NyzCQJuZfW53OchS3CaIdFGcLFO+2hDaluo WjgHLEfYq+m4FwRcBNMpRFVYwZmLzGkDyo4UQOTSm8Ap+z5ILKYzRCZuxF6Pd420kWeNAmZMD7JU ZoEIiB1lmbElNqyGuI7QVCkqaciNg3hxRu8Q9qrziqTsc1JY9dqb8+FQbOpTCakgc6J6Kny0VZ04 87hrclgzsvnD/sfSPbOdZELdbY/VpoJpi+5YAaHag5h3Xdzxk7L6Z0lMaOW0zXsR2k4syUFmaPt8 K+Am1pNKEQQ86FTSUy+wF+DhmRpIcSSnQ/tus7xmQR62tzl/WmyarB75WVjRc1GzbpeZ0MhKbT9Y jYKQ6xK0e7ikgYuivUx4zttIjHQkBrZB5Z1joiZsQ6N1HcrkSDpHKAH1VLm6StZPvDhN3VGBomTC OyU3C1GihbazGYrDrZecp2ctuAk7y9Ly8nrtD0qwAOmDih6HfP++UJOKxp8vFAqyhoufeYhPT9dt BBjez+vKHa5p68uT1uVfAZZ6wYzLRJt3IK8mc11Lxc+AlcKlu1FoZE+8FkYDiy3MGXF3Luvs4t9g 1B8qllTi+Gf8eW89p0owe5ri97aZNjv/sdQTS6QZApaJx36eXhCh2P8bpyWSqH2WhZss0KSp3AlG fdnOlBkN5LmozncUgfCuaDPYxi0S/MfGOHwjcvpRE8ioyEoo+WSc/RQ73dvQ7uDhAj+2xrisnP+M 358des8thTwb6Xsngz56y15cQzllhTaMYkFDKKi/o7w7fm8hxMx1PI4oizhGuP9hZJSF5f2Zfc4X UcNpg1Hu9h1Oe7Y1exuERd4JOTqO0ifp37Paq98twfq5nYAwZTc1Meot3giXetfQQuopn2mHH+mc bsfUsRK/USY4hafxhiNU53WinurICP1rYeg2WsDp49LnoxbH0C3frLxPAa3bzmwlhQfNgNP4pCH2 2utzI1fiMbAQ9H5GRtjjDmjq1Qq9HslNmPgsc/q/Sv6Sr1EPIM4Me5BSK8+8BFWMKGG+mRxHozL8 gJgGJ4ryqsePMzSm7dY+1dWYmlAC6iupe7Q4fxhZ7YYJlq4ZCfGVTfoZDKvr3clrs+sD93CKqKIC KapxsM8gACG4Wvxb73cdF9kwYu6PTc3flzy4z1sgPK+VnmwUo2MI8vSC13YX1rSMB2uq4vFHyKVO CdOUJ5ebITTSj0p2f3Orlc/s1b5hNUjC1bxIWs+0EYb4J76DkJzT+eMm5uhzgUViJH+6UqXxhese gh3T2gEwYRv2Unb5albjAfeNn158Yc94piCniPoW492/hEra5ivGS8HnD0LGJSAik572+7ONa6kX oDmPiug3cSiPYtO4LMDxqBnYhDNPwzBGPpFVcQ9zOSLtOQoazlRbWBNLYU62FyUZpiIoKQwtNHkP COFr2NXMjJmQTKAt/LfL+KAFRLhmMlM4UpoxYIC40I4AXuVj38CrG2Gf/vp7Gbcp2Zy0t5M3eHOn d3RHpwHwfqbuPt33KIN1hsMZqsH54X6IDV6fMUGwjw3gEsvCYh1ArQWXQ6bghU2vUZHRB2bILxG/ PohNa9wCaZnhmc4wkyjvrvdTedxrxbJefJ8l/uMPq09PNV4DfKRnisRNNjdce1cMi1qC5JYc7IJa hftLhUp5l0FXMu1r7xNm4x9kes7EvgSISP09mU51VUdDxQp1qHvwa9Zrgkv7ypRHCfDYl71VdATw F3UIX6f3tI9d7VI4SIGkCckDfBdcPp3kKAesSyAAYNyr7U1WRFG6L7p2DJuRbrOMA2YELsajVWQp QxHkpin42k+aXDohB/YkuFkPHiXpisFDMVg2ikKi6QhhYuDVqAq0yHWhlNZzsYVfCWDA+/9Le/+d LefljifI4XZuzAFVu0sThovlseePNOCjnTaczFw46Y8Pfw7CLTf7Gq9S6TMXV/VDzxmMO81Isjvh LFmNPA4Yof3Xt7VDi/FVmdEB8HWKyLvc0rKuYNvOx6Smj3Qz17dOrTwTMRJxzyFerbLygiazo3WW zdYctMnDgmVicTg+oWucz9u7isTfmRDTSJkW0TM9zF/+eUW8ygrjJs3ed2rv8oYKR+W2wP/sZxGt WV7JAxC8RAE1yO16dt1N73uVb2F7c1fiwBBJT4MbAtNTCrgBeRIugOniDx57u03Bq3VsmHqy4odB Nx0+kpEVublvaoNsGlVEYjoj3bhBNWr2h+XlGl00+HZ8WPo0RKCsFFlR9x8yXjIgFQ4ivVhCZeR1 2jy2F+aRWmStRUHM2TFKuo4SzoIiID2AWkm/QclfHdVd7L2P7L7eZkD6lIFfsiraM6ZngerlK7d/ EZBWJ/ryfB4HLBcY650wJRJ2MwcGpB0JOP2H48WC+AAPvF8nswxKqtkE8CKKdOwho2PLOba1d/EA Y6zLvYuoKWRbB458uv8DY0YX4uqv1KTad8q9stFGwut/+TlsYQ/2R+QYvCXhSHRX1ptdTFgOXSqd AM5HySgLK7RksN0P6aS0Fbmo2i2WMqYIa1tayls9QvKsUyL80qieANhzsH+ZSRaqgWPOVlNzoE4q F4/zJ4EKJrQj0+5W07N4kTBVemmAYMJF3dJi5pPSUah9OAfQUTCi3IwxuEH/u153iZwmbv2b+vNt Q8xC87QMHmOs1lWDhnkNApKdpE2rs0CSn90pBi5R+AjVB2j0e4c0Xm7tJV4jNwEYsoVv2open1gn B3RXsh+xJ0q135CKLWmpSURoRq/QnETqjkIPxa27m8gVxUuS9+/DLarblMSglez0ozYxILqmnD3N ik4xcrBnxL4qrxJpyPIgLcQTeHi/tyEBh3LZmAnqhvoT+Q17bZHBWJjV7dl8kLlCDCQqyp4ot5h4 LLUD0saRwEifIKYZ5k8rReecjuW00pxUUQUhstAqIR/ilj5s2xN8bMoZEKwwyYEIyBC3QIgH1YUI OwVNkLN79cRfr7TU3Qrss5eJSSHGZizIrgyhLNGN9KGHVMGmOLeYZmYLDyx4kzKKxW2f6qH+cUrc lS+GmnW8UKFURSSqEa7cMAvWpFg3ihTx7UQadYZgssqk9EJ8sV6SJdwhfxXMacF3VgXUrHWT+LSu GMASF+sZlHsOIPWFrS/O4tmEbGAiCHCMafeOCGXG6hjadYLYthdF+nKpLfgT5oEKpDZMjZ/TbN25 4Bq/RqZpp3w0soqUfqXkPwI1rF35O4b3vyCiYc+8I3OTRX/c7As31P3pDtoIdWctl5IQpLvF8oaA LUKUMpVGWuXqKQKDntZjGL0w1kTTSnXeyuUTNNDNjozihaIm/TdJMKZru/DMTqXd9YWfGTE+h9BW GpGkGDulNp0DtoenYPW3c6IhYcANZ2MfkuApn7JxbSidRNNCKWLE/+XTFKZBKuPMSzZgcG+dSDmR Mr+XtjMV3vkbOCP6UpORfGivCWqzKIG80wY0H+orzs6gInhW+bPuOe6RINny1KUysMex/fyETC/N 0P/Li4rstOnpAhhDkJTdDI4yIL1GnvQflNySGz6M0+QCwUC5C9hBG3Ov1/imy4wexZaKWJq4S65S mKqDaZglOm0OOzBBTErFqGAwRLxw/6rURceedFsdinqi+Q2hZBIiK+R+f7InN2l5kqxHNkQVlDHR uygusDOpB1FQJfas3N36btjRIs7ILWDppC3alQQF1EKmXehAg1kwubb73pRPgfBPGd6bLCvTHyTw KcAhmtKJ/mFYb3dw4qfYTIkjNbUKr2DT9rEISHy4B2y4nRK/7qV9Ivb4JxXWyFqgfGiKX5Il4FXR sOszyn4ZQjOfOPXR00TQv9ngqbjbyYcxMKVMSRWKPqKWs6MriLLcWj06WxT2Kxbw7M4Ra7oUOQ/a HmbYz3oFPv0pqYtJiZeSHrjAYLrav0EYkKxoClEep4r8HJPeEkgVIV6qcG8eKaTHINRQLQO3Vy3w R9Ti3lawaJNPtcYXYin29rwcAT//6tMhUIT2sc73oFeB0Ftij3PznkG/OU0hFbnoC3IZuNXkx58H PlT9VlO+0DiWKPnEBiuPwwLUGydbV6HItdulNWTgU5r6FnVdmFCDpixgaG5CFqFqQkgkRPuyGH5F ifWC4eEuPRYdX7jebh/JU7r55CSSkL4ku1kj8O+JzftfrhbcCurq0bSPb/YXxwde/MOhHv+jQqHd cwDj5UOb/D1Fvx86jOBX6dhmny01Ywz4L4XURQOVqleLV0XCcA7uJZj3l8WTh8lp0rHARhj+kefp Fsbo2e5exHOSDI8nCpopw9/UYUPRKAWobz3xZnIiXRyKc0k9+/rEEG3kaUQ6vpN455k4CeZeFhyn Ax9YR35G3NnStprUbUFKShosKkwB7/3PNre7hdp3N0cief+M5TO8BrUwi7v3dCLY8LiEh/2fVQEp 38OX93MPG/nifovtFB9wUJT2sX9U7KgfyineFPSoj9XCnUvW2Yr5Kr8cLlGI0Tc+xfPtMj+H1Gcb jWGLS4jj9/Xr2RgEz1HMqTK8zmzGlm9da2LlDjIFoomZjPc4sgFl0X6ceR8OEqrnUhQUyQYkfWia j50u+izRyIQ2kulB9bTI23oiwXytKuEFlnBI1zM5YxOk3J3nDr1Bii9/DkLHXmUs5X3SEIOcWg3w 9s+KRamB5Bsm1fmzsQlJXTatYg7AhqZzv71kzwwMTHCZCAVuf2nfUvtp1CeExYCi8qIwpeexUePL 3N1X/59kuqdFnx+gF20Ih2l5k8ZF0Pp/Dxviy6kH1JbVXduLeMd994LoIBJ/yqE1IeIRd0Gb4npi e0e7wEd8xEQLBKYCO4mq3Pvry2Gmdftg7FomnO4F0/MVKq5CDoFm90SXMjS9u7qrX9lkYgohddcA C9wlInE95j3+xq+EveszomhQ//3pfwmFufb3dJRHXMRUMIHfP+CZBJcfxCWFXBE5SWD0pkX2tOpT 8ygQBRmVwvpkyS8fQmuK0KJIR2W+0FIZ2dwnVKY6aa03zEuQZ8SYxl+oJm8bHTaqI7xBgxQmAwFk eIvmRHhroZxBmV4WbAJJFxOnPIsYPRMDa+jw5Tv4Uk/FCnrk7xCelNhkhXk6sZAPtdgVA/OBkEu1 FNWkh9v5zpqh48CrfLYaxvs49+uRnOduRS/U2QWNYDcymQei7FXGYRWCIJrTOuWJA6THL5b2lAMF jOIsjCejrWyMlRwoYiEvoDSEYl2oEpOfO+RXaIqF2L+MyhDc34zpcRKYaOY592OUbzmVZLM0WKOT jaeHe9EKZDdEZdK2y+lCVtRnjteTvEfEiGlus+L1JeACFcIDCnhO6XaCU2Yuwe6a1r9W5gQMsHeM VIr+8ZQD+MryL8zFsJMPllOBm/S/mcHsdSAAWq6yezYz86s3L7gy6mbyOAazNmRwomS9bTv/0jbR 0aL5pj0PRVMOeUoyBmdhPxiMuxhpqgDVpraL4be7wejzZ0eCakgcvSwjrXshgjDOJXIWXq+Z3LXO Ec09oxj+MDoZquj6sSWtlDjThnD6tpey/60/54/8BbBGAJgilWabu8YTJpcXfEc6d+x/9mp6xV+1 uN8mxdgyrzSlpgdZSH63KZrmndmilwhWQ2efF+n4cTUUixjPsqx8KkdH+2OiIkupfstA/rBea+g4 kqjR9GsDPxnPQugmke4Orhi3CV/iIqXGOEQthC9XNC4oUHaAASsw0WURc3akHwFFMYnQ3m/1yere 8eTDGBr3TnsT5IbqsF4SENbT4D7yEx96Slh7rhU+JnTZSuV/kRPklDjRvCBrm4Dlb8I4teFCACpO 1oSot1EOW1AB6niofudtArIeoROC3p308zyNAIFGo/EhUlP5zsUJskSzw4CrD5nVjeFpYdorh/En QBwzXVsn26cwv5rVXCNgGGEBxiIBLx1Mg1FhJZw6DmugIgXjxFCPSPlR/Jb7jil4YtvPas3I1TMT IQOfC31HzcSm15TZHtVQtBnrXgtQVakoWgddkp1KL4U8OPnFqt4Z7AgrhsFtDBgW2/CW5WBVBXN9 z4uo2/MektgZ16vpxBakAHuIvcuqQHM+cUCKqncNz5Gs3XRX39yjYJJM+bGo8E3SJhvWcGkxreAd 5JAYaPFx0jLkfjXFMI0sZce7I8ZSgdhkZzn9rHkY+H+6B23DgMV2tdy9FLncM2yFFJmEc3C3GXgs gMmLfv2OF38swE0HJgT/CJ6+GFHN4NtDIM+5taiIzjSVBTacb3yfzv/MRBfci8vha1qJo4HkCUT3 kxQru+nPRc/hnkhpRpg9xtr5QhuYRVcEbLDNYfRzEEBDiNSajT6ltDbQKPSFd87CvTTn8WtAfz1Y 9AMA2ZSTFUZwOTLzlTIoDSgnhaqX229tie3Gi4kgXv1jivl0FvLnAKsx75pG8IKcyrPUxNfQo3iB sAuWO/qiU6t1/DAdgikDpNiiucanZlS5x8JVPVThDdrDBq/AAx9KuElnTV+icOHMUtZTwDua9UuH 2xyTE1tbAtb40ZKS2z7mYcBLc98G4QWLoR2t9jKD2XUi6dORW5dqhWU8ge/SDYwKGiEzYLALGni8 D6iYWaJFkm7cXv4IKXuPx2dM0MsQbtnXeBHxe670bLVB+BQonGDOZq9jj8ZmM7wNr7dM2XQiPBq7 0/PYWoOvv73IDpr1wcUIJWjfLJBfKXgrmE9BBECy1aBKj03BzBsOZTnItA6+ieB7sVZZxoDJQQ5e g2vRfnWXoJRp8dtX6JpA5SjHoCCPQvVEjAnRReB8fIs9m/HQuQ0yTybKIfZk0T1Z+XFmxT1Rz7W3 Hi4zGMqmbSJs7qWn9qdv9SJsBO1nqI1KLCt3fXOiRAyidkdCW5sI/x1okZsnJPGDPmt/3AyeOIaS MQWuounATbJEly1yty1HuSESsskOBnornFFSGn9GArI4QyWjhXaSFb/9D7OONXr2eQ2BRQysQabL Sv+ORxgJeVUW1yStY3tlaPnOwiCczRPNw/b2seXRsJD3OCMZQWn/oadkStISRRhmy+jukfwZdAIK jeHCavQkcTrnuhFBKu4se9SIKQxRyQL/HZFskZK41pcdmmgKTHEYqo0KDsC9dozV0IMlnV5V2AaO a/N1aB6kjek2PE7sQjjbIl4oZLRAhV8hJh2sNFB0ImUfeSnuKfVelnbgrVaCpRkB4nhizi5eEIK7 5NmwNvyKQPH817fDiFZEg8l0G/3TVQa9Hsg2iyNdcI6XebZ+lbFC8u8ffAhQ3ax4htTRIX/5TPIK VPMobkQpTv58rMT0rBBWKMH84/67EM8Kh/Mou2b7GZHaaJ3Xjj5QAVjh9ta/TD48YUCOvIEvGaOR arj8ovUeTiiIOcdvt23V6Ed/nE0PV8S6ux/4DZmfOl+I972zN3zolbkK9UqK+3mXiGRg1pmpLu2b xtiwlW/OMjD+qLmBtk+5amTim4F/xy8sl3k29uOibm6k0jdxaZNeZxAVGQCugeFdSAm4/S95p8Fh tcRo5aR61YilcPGhdaiDzKj9McWGBAoLAkyJwPYbGj1y9cnn4lgLRY8yAMsmiKzXsDXvmSQo+uBt n1hBvNV/K5XcET9nLMsokKVCjt+RD0gnM6y+P+4C6eDros8mSltk8/TiQ30LRAGWZ++I98/x7DoM 06uG7l3D9IlPmfqgm1Rg/+gS/TZ7igsA5wpKsjW1dWHWtJLouJCfzOOVTapceOOlTCL5ghc6NYCx c7CbqeoPO3ZLQKS1CbitrCI/9P2KPaGfFJchM7i+kOeGR7ehcAyt49ea2wxAJSk7LZQzQJjECpfX Dgwc0ryG5/WRiDjbIecfJizhfe6la4ycm34p4sGt4CzaU7gLgT0xMrmMQcie6vENz0iq3AtDNy3J q+A8C76FY7B/7QHyY1dpg5s7rGoENRG/uDycWHniwahQgdkVLN9XfMkfL5bB2cf5w7KS6bjeMOtF B27pyUnGvQjlI0zJc/4UpfgkSShwkhWmj557Tb2v2TrolydTOTgLKMEF6lufjczpB+iTzpa/IeSZ 7T29fJgY9/kD8hZ7Bm+EJ0+wrlgVF+CmNl6mG21z6OovrcVKzGX3qVw3io13VpSQkEiH44URfHuo dK1JjabO/Q7zPNcyhiGRwlDgmVnLhv68yLIKsjuw9ZhA3faW5jY1izJ160N9UfZ/YKBJwBRbg6QV BWpUx+qfR90yOAlmF+Gd3KQ1LM2rC2SGr5gxUdCRStJyATYaD1ZV0zW14N4lYR9W66gVuF06v05c WWzrkhl9zFuQONHRwFdpLFuc13D6EsNXy7vJnfdCMJhZntUQ3IDuBrq6fycWAQHOGA7xHv66Q3VJ p45oA7/Qb2Ce2WDjU8EtG+nY0f/LFvnlFh80ggCZcCwBQBJZWZ+aocUXNRmRjB5MSxaAPcRHUF2I yW/J2tMq9VL7je33FpQCxB3hjCrBuKNz8i04tfB0AnZJT+D7O+e6yncYCSroJXmgMQ+St4Tbw8VV eBoRYNInaHi8CLzOVtkEUSJU6kLoyoXJweJ4+XvcgJWvWkLDsMBNppba8gAGRlfGJEvkr26rEDhz 5n9ZtUtYZ+jfp4PKf+fRKN4qK6RSgDRjZfhZwqe6BqiRUZrUftzUNeNewtJmg4VIqbUNWmMcom+z gPESyQ3itiaT3QIuwOqQcUBqz6ycB2UImCeFOCAkL024t9LQ33nMlh3QmFBiLAIkoiLG8Qtt+A2y xppZvJ5yi4CgHTztVArTBGMvwKok16PsKYUfLdYOSgtuF3YXp1g1YPwkQhMbgezGyWjYHNfi2Z12 9EzAUdpbMUz4kNKidrcpoKgyocZaoMdQukOnYFgKR2cS2osy1v3xpFWsCEK8p4rg8jVBTMMIbryG hZbCIpczR8qsLjA6nWhFpgiNUo8mQUOUOtYWBhSoxEmyA62GVVeZQTejuIEjht+Xy/STvIKl8p6f xxCetF1kvLWwC2T4L6ED9gFICOh6U/i//VydKwebGWi60BUvD4+c3NEd+l7cSDAKmezOY3vUKrsD +SYxg8iIIapAHUd6MUeYUbNC7I+wroq/8KCqN8BJagdTR6tdZmpgkU4bpCjkefLFqKqYDwHB0bQz vcCffCG5IyOpxmdyOpqKvfeXxOgNij+s3qBvtLOd9XLN3fMkrW4lR2WeP7AwWW5J1AgHmq305hKj 2Bv30I4zHuiaxqfLprqhAMc14Rw7dxnmwzW3tMb8yCzyq7nbLsAbo1ZUpbosunvi6ZbCY0ZmNDyW IkINKRmrOUg2NQiRp6Yp+mCnpVXlREi9tIr5qjt6CP+x/duzmHMHXi1pv5DS9b2/hSL9nqMYihrZ PT8iPePirgup/Ck9WVFr85Fx2s9ptWapgboLpizjDS7HxjqLtnlGzhF3/P3iq+ipcmgLD7HgdTk5 Wd/gtIEUGEloKX8T2uUq+IA/EkBeXxKUQWewXmr0917dR6DM8A3jPedfocEUO0c9SizW1p0E6A3m ko3D9N+GuMaNwiwht6g+o3s0rJnKVe3uV4hufoVo3W6c+kUcHa8xgDKSjCs4SdZinKHP6kToR33w LWYzML32igX22qo9QIjsnqWkL1qbXChFS2N4uYi2G43bCT8zVGtx8qbJ07f+SnuLzpK3WCw0OCdG ixR4fF8BPgR1yJZlbsqF+ph2xoGWaB/kCrhC1NnqoSsEjcJaPsr1jXx4LB2aV9j1jpZe2dXv96Ud VIiu8dDNj7sLQXPdDnjUq0E7mAh1HCctwpDYJf43yEVCuPVs9424vUCL/AoqGntDGdol+LkRWU2n YBgWqV1nHzBcVB+6WXPfzTeUB3nafogSz/A62/3MGSdUqaoinI821jioRuq5Wt1MbXk9T18Bv3AC lGpWyL+geg5X4AubuvY+RlbNffgD+ATOQmpO7a3W39MdxmOHUHeIa1CN9YFfkDwH82xnppQOOeri Jzm3r8Lsse6QxB/pA9mYREiiQxGzLh2juJLVQu8n5iHxZgnl+Y03HVU84WSTWGdIh7GnicS8qiZ9 N/FE1InTvNQ2QVXNWGJjdiCKfSnhBwPioGcLggQEM/PagY8IbIQnie6EnkWSnHjY85SDWXo1vjip sP82PVkrY83QbK17WhxQ//hD50uPaKy50vswGtk1+JmYfGD8FexjAY7kunbIGa9fQiZjzBSQ3/ZD gbN8Woi0OdSDsjngrEmT+tQtV8iIZ6vsyBmoQlh8nc9kekoughf6S7uGwubTgyku2QeR/kzMZpW/ 6rBDbZzlt9TxAXYdokVa7rhFLd9y2pgs558ikgBJ64Jl6oM8FLCQZ7VMNsLthuGnr0SZatgG2gwd LnvkHJcp1oZC86zgUJUgvPLjkSMd+W9PaXl4voImUTJOdk70JN9wEVNzJqMm8oRp5A8aPZcpBWL7 wVVRi5+iKjRcw27IlFOvIT6MyGEmOphdHXjJ49oaaHggJOdi/Q3qhyl0LDE2knO5AtUfZO175H7t J/R4S7H7Ye6KlT2XBxkX5KhvfC+x5m2bQZz8SyvSIqcokjj7tqetK3WIzQHp/e/H3yvUicTz6ZYQ XyOhDcXMSnolcxMOlaCVsk7Udu6VkLCe1eO+tJmS0L8JdVyX14+1apEuii/hidXig7VoXeBOr7/g n66s4txHQlEeieE3E/T+Fxbp1YNcyRYFaQFoCdOC7M/IvPNqtXCp9kBK6DZpKV5rlZrTQcbO0lf7 5Iaep2d71HybY8s3okiMX4nxdE/Slk5vmogF6FhMio7RpwmCWJZ/LbmMMxq90qbmM9eBNsN9YujV ocDxb0a36d0n5Hw8kRB1kDJhO6nEGVncJXS6Y6a0b4WRiNdCebpVDR8ic9hdebaYVjatxVGg+J0m DMITdpx/zzP8DkiKJ8UA2sE4YTf2Mqfvh/AFQ4nFuxDVWj2EvJxWOs3tXkZopYCpd1ixgdhqpZZg +DyaVHiMVfBMMZfMRKgyLZ6HUZuOWdeiUuUboGDu1reSqjuYtK7iPwixUl/ZvTVEp0m0fi84ISan pqtwos0MjccTiWUXJiymMxHceKvqbpCxF7c42sZEskd+DbGJsfPFfku6EMHgmhuJ/9LHmtK6Dyg4 MfRNkN9vPsOogUMVsSU0xP3epfkRL4/IKWUQiXxmWX/q1PsCnu3irNQ9fmEbR3LMD/bBDfbjWnuQ tZQrOr16Dqod0ABCBUNzQToR1hrzwiQELVAwMtzLph1VltAF05xp5w4wWOC1TsWcNUFc20iRNNnV Z0shdgOb8XjdeyKETXH9sSoSGdr/J+1UVtTrTyrunq1PXOIBXQyxqOxKCpOLuosuWkF1+pNN9JGE m3yjpWmHhRAy9kLez/YX52nmWJI+3zM4XxKQvS7L2yhQW8WdztmVeDWi4Va2J4oqqlRIe/GhcgcQ /sf/mWDYBF2IpguWF1H7CMX+eX5pt5m8qeuYS7e+0SPrlYfCjUPJsymmjqNlQEM451zGccbKqLnu z0GOCGntXPjx2rxts0FMoZ3vGar2OFsv+CtP4Al4aylWCALYLIjmGNLbE15JlYUZFkssaIAhm0aw 5OB0MYxGsMoz2ao6rDkBC81VJAVZfgUwibmAqy2qgJ3Clyf2Rqrnv49O7nRyiSpTnj61wlgcb5Oe N76W5K3HXzdI9klNxva2kV6LN6fNYd5zrnOBJLYQbv75nuuFEqu/Hzb4NA5M92hcTIR2JELPm6H6 bS8p1LnBkeTTEQ1eL/lkWkWejwoTJCcJ5Gu5OXUGsmg98K4c5pDWN3/Po2zctaDadAgogEosipxm UDsKCVL1K1sX46eN4MbrKu0xYMWHWnVwlrvxmGnzH4J1HyIMsPRM4n33danPxgQy8WFy5baQBJRU BRyhP8Dbm6eZpimH8EfF8EQpJXzN5BuPLgDWE0PW3I6RdAW+US1xU9JlPRNixeq6YwrJJqMdSEuG xM0FtXQeND0YRPZ31cI6JTb48dSZrZWuNtuoB46l7xT6OrLAaZuVNGEbDW7I6jzcOHimsjw5UmVY QA9bwcy1V+aOC0icmIlLvprpd5cLCeV6Vr66STpj0o13f+gjdUoRQcZ+sh73zaEUN8dJ2Zu9lSnD XjMqPD9YcdvA8ZeY/9kbAGW4AbQTTpvOGtAXpPihwktlKIjvuWVtha36A8ADnbdtlVILeJiLDPsm joPnUJMxEHNuBRy8fj5ULOCH53/+XhURy0z/+5EqGkdooGCF85c7YugCTMID5xvnHnV9yoadpWZu ojZXbOlKG5GBmD1/dLKTSLBu1ub74kHxKQiz7cVYTH/lzQdZh4SpeHpuLyPP+OvI33vEwlvGIRm/ Nyi9w4Wxu5ACZLviTtlBSdfIeSTzL/F1eDFo23mAoB3aUSHBgsB2eMAfNGgXyOVLuy5dORI8fICA w75DZIMX30jJdX4Yzru61VOV6upLlKtkj7dc1qvuMC2hEBPYJdwj3XAkX51Tc4nsc03X1eQSPSM8 c5akEWxjeoKxHjMDwU9CS9au8h8JSTVoG5NC1tipkiTvh/z/l9uShAe4kKOZGGTetQZzxNi45j6A 6W/4feG69jkU+MlNgjC/jpKH0cn1P5ieqvwnXvb836948Ye/TNki1jMeRng9peeMQXp7ptO0jbFn jML6BR0pjE29plblXeINUP3tPIO19E1fE+I0dVtsGk/2CQML+4gIanGmcV1IH8j94pJ8T1a3NvSf 4SuqRwpr/ETBqooDDDhTbi5JOg5hdqxGIeK1brRHcoQnf+Zfuz341uAWdlE3SmkElt+xChYPuwHO UmBtVOs3ExGzVkegfxmc5ctUph4c+xkPppGBtaHksFFE9vZw1QIYH5h5QrJzYgpp5N4muZbMUwiM qRL+5Bt+6pZsdln/uD78CIaYFFRwgT4qeMTkz8S6fPziYYw6+BmxCAeKdp35gAfkUEJWYgUmklX7 r5nUSPColjPP3hQLzqqKTWLw6/QO7IT8YWU3IziMMeALTmi1FR4u26Ihz7gm7HW7Bvhvk8w3+7H7 qGFEBqfysumXwQaG6JCO6KRaXizfj7drs9RRtJwiAR2svhzoE1sagVIa3lsknfLyPXr2A4ApTPpz gQBAVCLyuffg2Um8O3b1iAcV+1RvI0GBsZNKe0d5AcZsh181yrc1hZtYgCpHYxoI9fbjQt7p1nnN 7tuAlm4E+uaWUzdkWE5bRv9p4aHOrN3bACfvI2h2D9sQj0JVWgycnKkYFs94CGP8lbWAjeE5QV8E 7P6TWuHd9S3I/TCFOEAYyHYxky8Gn9Y3gFTr1204KeVbZIc+srGUAvNINuCCVNDNygVeoIEy/KCF Z9fvH0taHFEyo7GwqfL2YtCdx9kdM4IilDTjMNGs9r9pbiaAq2qd0gpOhcNeYf9ndlxWK3YSx/+a NBzK6v4JnotdoOHxeKNjlg+o4l1oxCq4Ma/TgNbCd196Tu8OIidBsThTuOBfP4B5i3KoZfbg4qqq HXXQr3ybEkDkOP/m64qY4ngi8yw9UaqFuxRVD30K0aM39E6GkpBkAShsZwW8/w2Vbv1CV6R7mjx8 n/YsAlP5Q9GGF3Sc9VIBglUAcxIDcf3PvDmMlAwh3UuxT7QytKkZEjXsZycOV0bHZHYITOUATCY/ N7jRqGGXxIy1LBErp8o6dVRkob9QNaqXIPCeYl9rK+lCFEuw4qBsUuU4zSfY3xDtq+qxc9vzncem lQtsxmaOP4pCLiysID1+5sHIxb4VW3zeMH3XCzALsEeerquYIbTdST1EdB/PLLsGQJ1kBM9ZKfKa HM1drrjhTPBtw281jFqUoZHhiqxO0/V5yvsFNpp4RhRPN5GtqU/Lg0Z9wEPfyFV7qZAx4RjaEGwP nxliZQkrlKMZ1EO4fodGtmxX26a7nvdTh/L1WljmqPYyrcw9taPr+x6BakwlQH14lbQz3tVo0/9s WFgv13DmBA94VYbomg/I4y6QuAZ9eRLaYJloLl2SD3Aj3ZZjbTXZixfVl3sj9cdz+N4zfQlgyg2E mLwebuEzXsUe2X5d7ghBe8hnVYqKhYKJ1qj+KudBJD3sb55ZkB6VL6d6vdSJuRpQxvUR+/z6/Mqq oRoBTGcHf/ZSX8cAHfFmsdGJ/fYMzCcWIp+9Ap4+YAQgFBobwIwT7gsQE3xBl3OGxDF3i0y1UHPJ CxeuMRH39xCdge7mUYUU97wOrjWIRsodPeRO6742qcqpCgNAimFh8f3Se9WxV+Xa5lh6M2YEgmAZ h6i5rWEU/60UiwqrC8vYEvEYuAuUeCGYv3Ekzvu9yxJ98xaxlpQHIDXUHmH+Rn/j9XS82yNEDBzJ Zg2dH9w/jslYyeOrUEfFpxQlLw6a9lXLXxDXGdy31EKElhp0ZXIq0XHO7lb+KfqfTSUFmJtZHS// +WvLgbBcSET9fsOR4LSAHHTBX45Bc3ooGDRVy3eu7POagB9B/cXE5whSgR6Ky8ZboOf8eJXTG4N3 +tXLlQNvBhNFqbAvPYAcG4dwwg5M1M9qf/seEoslYF+qgyk2n73aLg2OAVW0rPfiQzWqNMbKcl/4 RhCZLV/a5BY0+G3RU8ZG258gZiRzMTHYeQle39gPD1OICt0b4wch3Rwu4zFOa5bMQF/n2pA6+ThC HybXfsSFBPvc1Yvg74M0teXz/tTVTYRpXxPRBLDWKtJLFGtlSrLXWZ3NIoBFZqUxV8pm0uWmXcME YmxzynYZ6TDV6P6x1oXKzD6V6MW68XjwGlqtIkkIVVAF/WR84KbU9CY+23UvS7WZ8Vz7Ll5vicXV 0Zb9iJtYR0NfS6bn6lqdJ5XacUoZFvAk7jfQBN3eAfXwZUpPh2u1JC8gX23bFrXmHdgAenDgaP4N p3E1EOpk8WEFpCsbz8PdoyLwOA03Z54XAi+nV8Y3E6nSTbBz8zV5ATg0Ic9VaIzD+20l5WeuTeY6 voKk1G98wuX2ohur8PMUzRF8T+oW25mxzjCtj0wNwtg8RcKoWujTo6YAo2zO+y+wsDdza8GhA/pi kUn9lmcclleSvaiy1hn9OXe+UHWByOVcuf942/ekIBmydVXXH1o2lac5nyh0QTNclagRWl2mYg4w PEewjhUC4JfTKEc7UtTcYIq0WDH280j79pxv2mAhKNSiOv8yBjy8xVEhZj87AZ/cgD7qea7ZwPrK fXF9A9Qo9wZuBicPP6e0Mv5WXgbvbxbjFjsnWL1UsXNgsT0rfemZSlVbPiW5uV+YTXuJW99eACY1 ONAxPyuCP+te8/hN+GbZhJjw6sFzwtOG43v5+9NBEL3pHiclOL/ROBdT/qj2Vhxrjd5sr4Q/jF2V U02Q/T04p+VCh5fw/A1Jvwl4l6OFCgSD5aJYRmm98UllR7HVr1DN6FvFo7evsZyhLe792ipqozwQ u/AhLswt6WKk/Gg6448Dz/+dACb9uJrqB9/5jmXema0xNHEssuH7lx0sS52Xmb8ZJxxO3G8kwiZ2 QwLsdZkuYP8d7x8aDUWTQ2Sjuzukp9kxAuy+AMHs/fsY3inZI+zD9oduk0Sq4LTPO6bhwzgdndt7 EvQOPtsN7n1b/PPteLZBw5gUkzbZqqYB+yFlSa31cgsw3WG79Z52tZ7S64KX9NadJPjI3lI6j16f zlFnWgcnsMmDg28D8NZFi3pkNCUM0BJe50df/9FbHTfVfKAxwgJ9IQ7+To0kZkd/hfGIh18C3IW+ JgZPkpV4WbR2m1cV0cKDxttKwccbetOa4di4zz6ZxuSzKmsakbSYadwtFwMHy1gvZ1OwcvBqCxIH 0jUg0FRDWUaMmWwh2Gu0k03pYUUVFB9IbckaWDpWYqhmFfeDLz5D07nw+A68oru3GCsy40qZen4c Sa2h2iBJrzsXmSKQn4mLzGQq/jVPKf2MRF+9rv0378YE55v83nWhFrM6GHeEVfbidEz+POQ32lvr //SwNqwTsFkwjUkFmz3jX6xvb5adA1zZIR7QYjneHlvyRWCJMuXoBrrXBoZVP2tCVdc2D+AfKp/U fd3kdCJ8wIxB3LvJY7nD1Ry/dL1jet6QKEJYN57TAubOUnsU+1mXSTGwURle++UlIglHf+AZ6P/p bfsW23CMr2twfDUbeamqTTUMzOH9UAAi7Qqr0gE0AlY3QPtePuYK7V5oTz5zoKcViUUHSWMmzQFt pxDPPR1gxa/6pLMw0/1nmPqxBFU8iTRaqxhYAdfxWmh3hQ1vxl+K8eh3KyPlsdWjcSC422hwLSHh ehD1wigf9x2HNQ6QlLXr63cEoJVBF6MA25pEqK+kl3M/P+12r0C4GKK2vpY6I4IQHEPm7ZEo/s8V MHcvx6r0IKawKvRa65ABhSVb/VREbN7fVXFqWEOAg+k5aMOmAk+ZP/rqnt1gnPzpRbq9Pbq4g5Ji GDodd3TxYTJFZLhKKEdlDzcH6HwvoPuGxSv4nj0jB3QJTnHBF9OJ6F06KJXupWscoBdYJNYJFAr+ aE0WyQYC643JhYOzWf/o6uKCH7X5z1RFlwzwedjH7WBhZxCl/RlXTRPjm2Moaz2OUoy6+5EJ6JMs Wz8otxxXN4lEYImbvx7DnkqpEqdv8e0H4ikJ8svdPbDWaJHG4YLKiAMM9+Tp26QdGTCZWYyrvWko 0mugb7EifjHAaCFXhfBTuPStmt1v4wEt39dAJpsdIhkMwEzUYUc8PVJtuWUwEar5tchgPKApYFf7 49fifUrzhEVu5cB0I/3uwN3Fe33Bt4rJnjQa5jRNac/h4vOvmcHzwAzzwVpBOoE4YmYGbI6gS5Rf m0lv20kTtx6Zg2q4GqeGYqVO+hhEaFnOcLOhosNIJ/yZClTW/Gqp+GbLU6SK8xsbTZGC68Kadf13 Qyxc6fIuxviuFQr29Rj7x1ecnYwR+DcGy/P1EZOEELkGjve6R+1YQ9c0UqVw3CSNosTT++LFQLrh 2+BITO7/omV5oE+r0wxWUyGNPq2zbzImmkyhN4T9rL1eHVz/qpiZ85074jyvcNByGT9gukabxk5S Ko9VhtQF0J47mUgB91rd6CO504SAzdzCGcQtbKic2ALaiKE+Dx6lgfKqHYaefvTX0vtABbrPKZhv nJGbwB95e+PYkzvwknvnlUw1ayrxuJHA9T0Ds3sefaTD2yrGA2+WhngMVhfmZRS8M8xCqpo/ZYfj PmrnN2Og06lCjd8nREuPTKgLqKPAhChdMFFHmM0ir5vj8Nx5bxA22I3GjjhSEkqvfRTmOL0LpDtt WQOUOebNoSQ6G4aCtXcxZdD2gXOMmJf1NbImVcujG5jmPXQHedirlikCkilPPenniyEE6ZZfGGQp BnYPNEEKJK1A2j0Z/QQgwDbkOUwzfVifuzdq4894w3qGjKvihfnCuDIGyNLiS9Ot4YNdfJAhWMfL t1lrrDM7P6dGjiUVqPS5HiLEdSyEgKVnM2vao86McFyIIu+pjRO4jP22VuAJLD6tOp6xyH8w25j+ uhrd37dbSEpX8nk9wjXS3WPrrBtqxoxq0fMH+TvxX2DbFmIx7WxSjonBK9+948FZiqK5fMthptUb mTOXC3bsePvnNnvyhgr5ppfxgLfXdEscjDEBswjYBIzwU0JPbP+SBwERjQLRSDwJqIhQrccQRZz8 6tsidoHQyuqNyaKxJk8ru5ie+t1ZLUT1Vy6UB+HQSguf76cA86cGFIDEgEibFWbpovs+duJkINSX JLe7T2uXt7UQSHuQakZ9pXyVCnkzbwbleSvVHdEj3FPDfOsBgXpA3vej441mE8JONs8xaeLx0mPM awyKC9QcB2BDLp6Cg2N8phFQj2uvCboJ85X6Y+4FtjAJfgROvizTB+uTHAvWgtKp2vLDKwrOMtsZ K0g84XYkOFe/Ir9dza6dLyrCqYjHMFj9oyw7uMjQg/txlluuz4ziuDWu+hYrNwmHsrAngxQ9K6xm OjRtZF95uNrC3wuRiH4Cr94hKlxcXzcXVpxjbTDmCUw5LFDJmj0j8+tFqrnmknAiRJufhVw8uFOP Lg+g3xUEcnNsZxHYGfd/zLPOnBAzWS/T+VSnP3xCqggep2v7ygE7E53YBm25FA5dbxpBUR4EFYvj /KlW2KRBWh6dUJXba9T3NE2dop2DodDCLLwMpqEE5fBOiwZn1CL62x9qTyqQHg4nfb1eMkHPTJAj 4VadrHui6estfH+fM4CtXcHs2O9FTjgS/NFsLu+b46o5RbtWcMtq5kAKUhX/JkvFn0jCmxkQPyB2 l1Fd4qIUbqf9xunzdBErwzFpp4vjN/LyWdHTuSLinuyyO5Zm6qYRFAO3+w71vWaVxzl7HCsB6zzF 7bV+gD33/guYFOeIk/3B9OUyG8n/eso96xWQo95+Xr9BAX4mtRBg1PSI8Gm3kQnB6c6zlR4VjSPm uas2srhpP3lkJ9FuZnCqIMbQEybdAvoO/IlS0WHljpj87pF0MkfDHj8AocR/PX2Uwx1a1kjm3OHs +gbFR9AAhzKHj2B2XxSr2L67aQEnt+eBIh7JPPwtzMYg39ybBwiOcKd/YdOmwwV55RGKDDaVfNzs 2SKBqXViaktiIjtwnE/C6qFrcSSMXHSv0cYqX+/IldK2BsK07nbC/9JXYLWwb1GDzVESPXlm4j6I fqaD5Dy9pdQQuUzXG2DyAq1L9vIXMnOvWPQmTN2lXC94REz8fqyP4EsfsEZw17IS9c6R3dJJJHqV /Ga3rVQ1QEy111JpZ1TOV94iwzWAH7lciDG9wu1OkE4T8url0qci7i25b1HPn1X2QGBDd8ba+S23 pFXO11hYo5OnxRuRgt2+OrhPD+ulsJClB1T+5Y971PxBJBTKJ9Paj4pC3Ou9qadcfW3kXNUqs8Sk wZeAFF2s+mWWcbASx9A1HHvPTJ/doW6SG8qCtpPDUduKvFBXue4uDTPnXD65v/xI37ascmqLe/Dk xGr/UoKRkm4Tqz/E3A6nU7x4WLqdKcTQ8sTP+WziDAAClsgMSARswnC1bvWW9YXtYB/0nP0ItHuY Zf/EpbQwkaM1PXWfZAH1p7dzpe1Rjf/PjM+flHjdlv+znDhnHWLo1PEvwlVCKbToVyquA2bvly4y ldvqVKf0qDZIi5mlpeZQrZfCIWmkpVMqz7H197b0OQ8vmf4HtsMp/BZ74pS2W9NPFZEmOSekZ16B BlBYxMd25cxt0MYHs7q92yHUdNuKBj2HdaZVAU+bEDBJuh9ZD95UD9lP4j7xljYH6wWny8VPwygx jaiyCUpR2Bvo5jWujbXXzOOoRbqBacNOW/P+iLouPuXVQTXLWBRsFIpxfks6oipG9yTtAv2n3eW2 skt+jtPeJwXNZOPHqqOinvYVO/1F9CSx+30jsDM09dXqAWVA/IXZJEKBGq8edSSwW5TOJSYc3ApF 1hhJMWHL1/AxPYLQQ34/dNUBij6XHYliJ3sI+B4tHJ/4GUVpdccWHQOx1OqTrcNZKbmFHcqQQFrG bq42TsCG+bSwCJss/gNVtSMhsz8OPA6NE0lbRA88P6tzzWP04tGuSwctLBNtiuU6ez9VZzDekWFX mzF//VncFaqaNaucznWFF8JsDzgwl1zxYHQP7cpWiESHeyC+5TCQ/zEZSpwOQ22l9Q76+/P9kEJu iqnw22ojCVFjHs2TOYpaKQAEObYS74sMVBixyY5hEBySDUU1gH7UMoXL/Ce7ZbZQ1Zq/DvKmNF3b PRtCeyWE9opxMlm0rzCC9/jD56wYz7Xzfl6llFe/dTxceIOBF2pSAjpDmBYqfhUujKeoMnp0jSSw rLNYDb5irv1setTM9S2bKhgQjcC7qWgBWpR19V0PDqVX1rMmGCv9rQAEEfZTpuH+W94U6upn6znx hN5EqbIu6gIiVpznmVCjN6cDPSwzfiolygwwiYrQGJlYeiWwlqLpA4OEylY/aF7+3vpaQHOierBp aSOdAyR4A/Y1VTk0vHyJ+7XQKBbXbvEbr8aSGCyU14eSeolaIoayLwEc3wuN5G4B+Z7mx/V8fPXF fYX3bu5NGLLnRAn4DVnnlwAOuBO8tqQ0992hg1Z/rQp9tIZv8S2pNNlYJ+WvV2HOEZdJY050UUZG uideW/+S+l2bTqGbRQxyYbD0lSAj3uoOP+NDhkvoBvQvcNjUZJJb438s0uHFkXtPQJRoQyyow8GS VltveNvXk5bvq3A0GpoG0u2dtDgc4N5ATnKYuU8HZaSHDZVCdWepG/+L2eQum9fLbeuAd5b1Z3oh XhMnivNJEvAFAtzqcXcBYHmNEmh1D/9EDkBGC37DFggdNsj1B2OV+c+2EiyGj/LKu5UX+2j0a4ET Vfd461tCBcnb+AG+KfADAfbPuwaYGZNdNez8vG7segWAUN49dFpSs9ef3zGwEPVNcWlILVeZ5NGV ZDykrMUXq3sVjA9vA6iFaq0PueWHr/INm65N+Ru/GAydyYvWhaieL/gdiTuq60psL+9TWkr4ggzL DDqSlazF+5NTUcSV4S732sG8vrMYdigWKLjybi0ji9Cl9zUOegL/NESkoOgn1N28k+/0r19VDu/u JjUL6bePZHvKwEUbSh2qzh5w4/+21oPgz8qzs30iXFUpMKchl+tGiXnXRS2SSKb4ZcIkIvrAhSKn F7zUbteatCFn2BbWTlLERxoB1YBBVA+ZNwYROdzx3fuLqTvsiUcS/22CMkCnUcOd5x2I8Gxmf/jr YQ5JV6XBUwYUZgNCGLf6Gufiini1Cq1eGSOTWpwKwXGIKZ9pJMRnUahIqSDDQbjndO22y7uMoyps K5BPGR2NBCfB3MtAvThvu4ylYpYKsgiUdeJAkdeqnSLih7LPgfrs5hMw75l80K9hMioTT+CTsxQK N6zH+GkBrisPMZ/tHStu8DMkUDYS9M6T11ZeSZjGXHfaXA3b64imU+ZdGiFU5QWhGP5z90RSLTFW 3UQF/OWIx2/0GuoyyL0Nric8o9453fRahnlQq2SyqmiZ3rF4iNS8D6Mu1J7AOMwxYMWGBlEot+u2 pZys8uoiLrNGLSV/3Zheyhpf2elCe3/30AibsKWCrXLoZGzTWtt1mDE5eBJyRdTQFkKj3Rio6qZB 8kOyaarvruxl/fkggpUDsO42fmrpei3zyjg1GD6EWVbpt/tkhNir1OtNOZljJP/AR6oJvwM/3oey RrsFhx9a6dTJbSBrTSu4KoG5E/6oOqyCnska1Jv99B9RRjKvGsBP4r0HRJ1aJM+gFqniUBIPprFw KYVKiT09YZFbG3Xjd6gfMIKj2S80Y4Tcx7oH1JMGUu6hx58jjigEH0AyiGNdRuZvtlE79J/i6K9d rMYFrQ38zItBjIiEq9IwYAXW/T9Wcyuao4bidtkhqt60RGWrTnzniMOxj6tv0pzU6Gvwn6e3CqhT udB0Bt7vXLvk68ij1B4zNlixDcbYDPNQ1Y7Fw+CG2kWDtEZgFzqyCV+Z5byRrr8YhJji6zZ5kGFl bTlaAw8ZOQEUoR0YwwGDD35Im4QbOuij68Udyg0bPsCPRbRB1WynFn/Q//8F6sNGE3bAEcnHUcMd XRdt2F1wfhBly4SHpA8L59AeuAFkcaBYdxlGCYjAACmuQyoDxvO7yjvHwiJdbnZkcIKqWXS1lmWo g7t7QLn+qM4a0tmKEXQUToFpyRjBaXVbY1hPmL5Jj3SeLPX05OLtKWuZ1WEl91G0TWfu53mWNCD6 FpFJw54kmjHmc+ofSwtRe7wTdzWrMaRxaSXIVte3WU3RYI3lak4b9laDveq6WA4XWeIwcv0cq5HQ bNH34dDSQgOsmhiwOsHRFCF2rjTXODcrLhCV7KLiazrHrB0DNV7QEnDR2tlwwlaAkCU4gSQVRgMy 8/vHUFfGTr7YP6mFoztH/79i2MZDjqwbeTCGNdq0RLMnci7pJdcM5IqlPkrvmiSmQTQO8nDjm2p9 t4KRna6H3gwXKLfgW2WIZ82Ptf+RgHRIR72sO5RRF1Ruy3MEDq1XFHD1tJqWi1R4Az/q2ahMm9dP 0Hzzso02iIthYGh75quZDB/2TwYpjgtis9ci4TBYAk09Vo21Yi/Al8YKlQZOeX7/Xl5N9nijZxog dkxDWFb0PUGG4qCMiB1oiQ0/cwRTjJog7jTpEcLrq5eZPUGgR9W8OT+iVFUbRiuZ/YTEe9ZZf9aZ blAb9T18hREGQXxIfWXy2fV4KaTHoB4KDccUCQt+IlPDSKVEdncIUzpezqkxj/7lNgAc5H1/G2H+ MvizEo7qhuMM/SHogIMtf0LyMpZEn8BLSv9hlAWoHpH7kIS6lmQcXnAKz/mG6/4Rirtc0V/db0r/ 8WAKrKYbAShS/F73X45SvN2xISItLdVWFcK8BInx6wo6VOwm6cfArFI3jvZCWxJdqCjqdUIkZlGZ dFunXK0tFevtX5W4nOO/dEqm9rIXwRol9RJWAvn6TLXJQpLHxKLz/xHg+aJkWqSHLkv+Be7aeOn6 UE1gEAin5VGyBKt2aUMcyhLEQjD44we1nFKW9DWfJSxPCE/nuUXo7zIKD5RkA81MWAcyHJIYzN6l UPaH3+Za+/VyLKJtLJdDqEaKVSkv0dzRffroMmG84WR7UoeebaX13101s8/qGpAuoLlJxJwOvwZf BxBGVbulbu4/Gm61sdOLnATfDKiHfswmOytkvvw62Uf8CO9UvG/1LclS+iAHseH7a6IOGU1dx9SE tha1HYWS0Ln2mGQczSr/MDiFgJuTRQzw+JpoRgKTNfbX04tQlpovYhXOEXJSTLE7l8jOCX4BCyf9 P9eccUqQUvmTKb70k+AuS23+v5s6/gW0rzHC+mk0Z1Y9GVd1YvntBF35B6b0eATf8HjFdC+pliuA 9YtETD0hKB31+CSt6e5C6w5o+mEUMMclulgyC/w5v/01K0qDUBqDJLjbXwDf6zeChYonx5+FvTFu 8nba5itcFgSyjTcLG88RZC1V/AttibdF+i5SbUwN0GZpTca8+ZfSI4HbeAgH7SmQdREdP2UZxzyZ CAJ/HjsTLNwRYR07qvGFw4bVvmmYPUkUrmIEyo4Llc8wpqdVbvmxIGEtRAKJ+U8bluAcwbq+jh6D VdNsOmvdqeOPoFDSRV66adZ+kNm/9GFbANEr0AouumAeWokh0pJ9uKuSroASNVV6to4ermRDLmds eGOQxwhbCJhLmCRqSQQ0Papz4JhjxTg2VSe+hduRM/WzICj02pyfBHJkIkZcfqwA4XjpcWL35uz1 iErzyLDcMK4zfJJa9Nn/nkTwdqWmMyiI9Dyn2dNR9aVPfKTIdKHFVFmN2cIW9R4uLsG7ell+YAjW m7uE0vON5Ptt/8+NWT71I2MvTc0JtpQjzw7rdQevuhFxYpTUohg+YsqMtiOEzLCpswAfoa5SI9T8 7o4NRgbsggWaJwBZhNP9czuEvsQNgorutXp6IvtlbrhTeuZBtFipl8rEqWm5j2ncdvA9vZZULWq/ ahAC3m4u0MzvgIFRF2538hIg0cpvAg+qZsl2g+0NGqJUgP7M2BWTJvQzVYKebslBAY0eKIAlNLWv JGM9FYppJiZmOewvlnm2hh08lZzyJlQ9qhdsgvrSQ0GT52TIti8dzjjeeBa1AAIXRKRI4tmYBsvU viwn/eGOh75PsYDJitbpdibAV57iBy3HJxlvbVFCemfnxpC2PTDedi6FVIzwgyG3jVBkvPk1+AHM NZ225RMJEcRHaJtU8khYmByWKdX8OVHwV2JNUuZZAyi5VTyVxkWHpqfVbetaaKBAZjxDrF1q7TOA ssuU4TZMf5sKHiv5INd2XycgwhDSQ2PPtbA3xz2tP8fF2R/FMu1k+fi4IZIveJacgaqVpbta/l4V GdritFdWzqADxLrvPL0h5+SYKp1piYVDUSkOZn8ZTibjAsSeSFQmfUVOJ5MnRPF37IgIWd1f82dE yDTTnbH7iYXvF0WQz7twdrElBywAvAWcKqYk6NZz0yUiC/kJ8EkcmIHPRxJiEV8sCSlsi2E5Olwc giwCqHNCW9bqk6YVblifMfOg8kqOoXbi+chm61qbYJRBF8jG0bmaAHkQj9Kz4uYRSMmyeVKckXSM VVohDyAP6iScjsPpQkwi15HMudWo+DNygoymTfXqFKXlVOeDTHuLFj/ASMoKxnVgEp0rBTUAN47s uyz5rRbqojLxNFAFmmLYr9qb8+EyO9fQAICsrNVB2tUAC5xpYHrkSTSq3bNdtHIX4r01KYt1eBV5 V1M/EA43kfbfMbTU37wrakmKfidy5un1Oe2u81crVQ4Z1XIjz8mlJ535OuPQXiaHFBWI6cvY2Xnw DKYw2M+fazBCWZxL/OqX7SwDwNFAZ57Ii+jZvTEFCEbrDP4q3DmiPzVpNZKtyvzyImdz6cDkaWu/ wC41vtKYU5UWrKn2ewbrNrhnZrX/wNTBlm+UROMo8eaCpyib4DsToWbrHWAt8JRorhcxdTCqql+c HoktmG6o++pjysGWZuY/OgldO6IqLJ3yaeyFSymdt9zDzrYGRMShxJ5rqjhuldQ2R+VhI3f5pZV0 +5mWEZDjAd9DHUnBFLQ5LAtMQ0xpNaGGZ4vljGSi12mKI9V5c6jLJ6GPLtdDZgLlkq+xUl2tI+5B gyXNwbe4W/gl4qDSBZ3ZXuL7AjueaY8InxHktkJyydeZNFhJSkejR0jUSXWJ8859tGtEReVgg6+A NVEbOdKMgMiHLs36jqrNkvons3nHTp/IYZlzpZ2D/DYepqWNrHIEGiI7tGSJI2WIz2GRO2KwsAja ALzFKjm2K/AWBUaYL3Ep3Ij6iBFJw4GCYIDSMSydYreLfWGWOLRoIUVLfQiGKmKCE0/GJA2KZgEv Qy6zYd/4NKjZYvEfNMVxk0TUn6k5+7kjiAaGg4sWg6kcsao29W/GV1NG44G1DAEP5mWKPiBfPFFj 8WxL3Q0xdkyppd4yUoswf6WUYlL1ksfNyhvUoazV14mOwzhMRoPX5tj0AH1bmCQzefc14LvA2yLS pcAKUS+2hZYQ+tJZdpkbWyglu1nE++IlxG8qJT1OByVy+n6krBa5ELhdfcoIaRfhm/fGILzJGr57 s0Q28XXqyVVoUCh9/D+RkpSMRhavlH2rtBvuhI7YPm79FSOzVMJq+O8avozMZJZr+DmSkbcjV/vj bjtMYraz5U4CnXpOY7AHprCr7JW91ROuBvNk/rOpiaq3LVM5E32ZaW+CFnQXYvKNqXFlx168akd2 oGETDpzEyXPxthsdRe/pRJjkJOjZhT+xawtDz2R2JPEOT07j9Lk5DuPWrmSNRh04hLKUvAPNIUOW +WKKOYL3wVpLmn7D1yXxgCmw/8YMZYGV0evKQvKAhOgqt7GKVs8YkWknP67kthFUNX1oNvdvv4wQ ZoWb8z4gU3oDy6GzDMGQJxbMqozypKi/VGf7ghFaCp3necrVn6Sz8J+ZIMyrfWMBABwdGNByLoig UMeyg115cWlOuB2bDOfKkWKUUdRAZTRkDxJos38nGuNkG+9gFEXksdE70U/R1i5WopDZYEfj+8no NWvMubJQdqApwD+6bB22oFW+GQhxCGplvgcBtD/fx7Ud+j+XpJWZ21plLQaDrPcNMvd2fDKktjLU WVh2WgRWHmvX9uGWkFjV8YHmwgwS2SxZfIGLi8gC0qqWpy4KhBaMjpn1Tv2HZcZ9LLfbbNq2KzoR 8+1NY0IAEtf3vyWTt0iVbb9xQnEKcTUdrpdDPAw+/ACInlzH36kxk0GY9BnK8mu7Audp86y08RCh TAsjC6olUCgp+9QB3aseY6MJ8nrOEase/DT0cp2g3P07HQ/K98mnRSRQ7Vwl49BAeMA5S1Y7nzrL 9ev/CZ+kSkWQgAcu2tupOV2oKGpFCEC5z0bzroJGCe83BR2Anh5He60ik7DmCGggY8AKMVymFEKg 0qTDr9zvjgACrhSMpmBrl9bmpdEYp6sZHkUiFkWVtytduSEuXiS7Ru4bA9r4N0dh0W/2sOwjeVo6 PQRq+6LT5vmzZL5F4aPB48TTYcCaeTJGzzbOKP6MDsXoqcVXQlQY0lIA8jTtU2BL5LIUxaNM8seg n8fz0UxNA69Chosy+5t/Cu4kyx9ygFLiNgjhOIeIIEl6lt8ndDdLrxbMHIVjgQGFxss59z+HvhGH IPWC5CzwadyQyL1LaPDh46iKjxfYW5gGxxgBSnoYdmsEnizvpru5cKiLzGsPcSQDnQBsg8noE64c h2W/E3W7OJZeygLgLieNCupcXG5za32CF0tmH/84+ywkdNk8xdFT5DP7fmJRyg3E4/IqbPc9jHfd cDSBkf1wMDL+vPsXNSuWQIMYMk98UNQmlsf54C49DtXue5pQRLwlc9d82GOY1ahxXgBGsxrFCVTM aqH65mvSHyNrWn9Ogza2LVxNiUxHD8uUEi6twJAazr8D9ouyiMgbS/uFHPDEa75XQCkgMd8NyEpo xYcx60dfbp4OlpzFNwblYC7dFm5GQUbDfmkMLT20GwSiJe/EOGTFCVx8XlD+7RnEkvqPC9wGAY1M HHs6d1kEV9P20XNvjuc4N28i9HEb5OjQ0NNW2MLBBbyl7+0VbP3TmaBXnqfDbztMbrQU0+Zcz2o3 +ANPZZhlLI2Z7RQikiA7uZ29PPlq0ak2zNixdtdrzxxazbIUeY6jjD5zh5mBWC/tJjra7YZOtb9j M8yMAQWyWAJ6kqT5hU5yj6OnPWSNxqjemkZkEaGBj97CsdZr7YjxH6Bx30SHN3fxGvzTX4FxOokU e7e+sCNLknhorRIgtrMGrc1hQwbxeJpjosAimnBjS343JDPd4XVQDiQkrpliS74ZjEveWVeLNWM6 T/5unjSfiQE1hyh0yUe9p1byuoTEYGn76wDoSHlGwALniopzZoVfA8J/4u3ld43+KrOUXWgE/34c UBSdAJ9e3rEdP64888wShdvBYpccjdVqdrsSjO5oH4JxsQ78GBkEnBhzTPFQgvAS8Kk0S60/cxm0 A8qcaRP+VZXApQ6ThJlhZ109su+M+exWGbZbI/bcK3+eHFhhkxCLHbLA0CD84hQDDjwyKmlqMUGO uIFYIM0p/crw4JsiElMAta6clWt6Aiy4YkJbSPBoY7YVPvABtlCs6KbrLM3V6t1er5fwALDIyBs/ +A3yNzYR+/8IOxk2EYREVxohio4taI+ZTFbamqj5rwgUfqNn5guYxiIGRgJQZDSDUG56WW30hLkp uJhW83bSqc0J6ybl900e7wAgakha11FSo3sji7M91oyymZ4mlnamcCx3qkQLuAsRqTMXYs9tUa0Y Z9K5GXSQj9PctCewXWCjCcygwUjBvDFHLPW/z5mMaHLgPXPmMBu4pYxALmx8ZuB4rik8tq/C+fJU k67/Tm6MhuNoiaRdzZ66b/D4kZBLoGentErkuWNDIUQGGquVLB3JyD54PjN3vFenYLU8toCsrzG5 3Cj1SFw3AcIi7EgHj+FAfOCDktCvacbnAC8aK6AoQM6yIMroByXQ+rq+XbvMvZzcFA6N4bLP1teL 4EpRsXX02IY1/xfXE1BKMIW2Ln7eD5QXP2tpUr0JfBOYhqNb/7LoveX7rP76vC9fp/dIPhnGkEm+ +EDJ2oqx5WQhZohSLg0su4e/oEXLMuxAVqpYTFZO/gh1Xf/5jOys1/7g7O1d/8aZuGmZ8BcJiyFk /twbJUyb46bqj6NAPwK+PaZy9I+1U5/KK3y4a9rxoTNnQITTihTso6GSQ86H91ChxIWzDig8MXH5 DGSRicpLa8NzLaWYkh+0FG1cQ7NIrd/k3efsXdyfJ0qI/KfDhsYOVRUgkfOKJbHbZHDJ9fh+Hpex Swm0odiXz8MHlHdBK70cWBNYGfVUhwGwtImZ1fhttg6qXs9NbobzFlRqdD4ctjHDDSnHQUe18a6B mPuNJaEvkV0OUIv4kpk6sMvqUfJBDZVAAhF5f9n9GKW3nhLLfq1kKs0xt+CPfo3a58+Hsgch9ene uTbkaMsw52RZE436o0HH3HWlrXl7XKnpg6Zi8kKR8zhdmOeRkTSCrWTDvcZCj5mIzUKa5nIGBVmk kCuPdhcxGxqoYAqanua1YknNfw8Nk3Q+9szLoKlyYvt5c7+Bgdgk6LTS6U/tpftMhctg2s3rNziL IZ4UX/P8UWKrYep5ss0PNXiT8c9KjKZcpzZHytPQ3q3cAtXOk+Iw1GgZXFyACuhKAiuCFFoj6mx8 k4LyYbz4DsjVKXVZU4BIzUhXcufEb/uqhDtzNZL/T1vwPS08h0MVdlaC8O2wct/8pRGQQ0iMAAJA LotMzxEidoQ38fkL6XWdbiIoaOl3vPZ5v2yMlaMsIEFXeJiCN8vd7zWNbzw6v+mmiLKKD2bixSYj B/Lyl4D4WBK9I2gpT844bGeUBSo9vCK3M2nW0J/LDvfMoIh8MLv6D6YmcsvjjMCLlr9wKrYvwXTo hDALtk1U61Toa+XVUkFpZTfNubO6fvbjKsXQRiS4CMxPyV/YjSPdLAI8jPakU+f4SwCu1iGAwSrV ldOLT8VEcNJ4Y8wHr01Fh15+oPTws6hp9OL+xXVrruHE6KnPceOsvEH5U0S2SakFtxK0IRMfEQTx /PerqoAFwzaEikddVtD1xLSkCfX5Ec4cyynZGCBIj6Gi+aQnaWk41kSprAVZFlTHWZmNVIa+C63q 3y0Id/SlP4TteDaUCfLEsJ2e0BqPDiGOWMsY2+s8bhgkG81VXDhaTIs4IEq0UR9/vQ8wy7VXfK0s FXpFVDhl0/HT3PZXYSEIZFrMATMltdEndmKFLMYOcE6gEuvDGPXPVXBufetyTnp66KO3Oo5WwxoR gnSrNdDqYpUZkIPqp6O65WJc9mFK60Hze7ySMJdDpTx+mNAq/C/tIY0eGllTUgok+gXQVlYglxuZ YHnYlEZHsoR+oBlXt/fcbFz56Cw+M2Jbxf85m365sMn0yER8ikBXy1LjIcbepvIPiq+rfb71d0pH bG/Y93N4SJCBdIOMEb9F7qTfXek71dCpdgq2rZ1AH0XofXjzBQyLeSDgdJNFAJoANRwLvLdP9fMG 7yU60Su7irRLdDA08nZbK4OS/WjmDT2JyZD/KcE+hXN8f1gjk8q+y0zG8J1Fngh6aeyBf7S8R9QU sw0m31YCIBNeJLZLQpq5nqIO1mXIUYjzE84HWidmZKSQHMY72xW1k3Bjm3oT3Ls5CMKne635sJet /bVRZS5huqzwGaEIfGuMrQNB7nNldTkraflINnZDfbLcPpiU3FZeh5Jcy0NhspKq0+yENgIJ2r17 6zCJEATmo8EMCuM3WGiir93RfjIQePzqIXKeQTv3RIROib1UzFmQY9rJ24xGqm3is8cxxzjQ0LlE 64kqVdWCb++9plGABKQV1gjkmXkJJYsATp3MYMu5qn1rPAEHIORm+S1eakzwy3ximmx016GicRZb JB6zw3q8AoNKzIvAF7y14p/t3tLCh53XtZ2glmlaU/HolwT4u6U5ijLJx+iN2S0K5bjbw+HQsoXE DURv6ObNyNaj4Z+X7pwMUg6Yqz6Q6mlk00X/1Kqq7JunV62kyT14u1g2eAEhSd/qRFzDz6XjbLK+ PK2iupuCN/Py0mKt5BeLPgTFxagwnqVm0+mbtqI1JCGuuJUiemann7QfirzHsBg0EtV0+ojP/EGW XQavnrDWq5Xo5YcBFgHellR66QS7r6yOcG0CMRUQnPnNjyIzrnLRhmOFmD8yKfWbUnFMYQUfl61A knvmhPzrusWPnrnbhVlBsWoJTG+WfuIBpLDyWLKc35XMpuqI+UyBcGxM4HJZjXWtEx6s/mvxXVGc zcw28YFIsSKTy8v+Z2N+xeQZW2MsImIA8UMCaDbRUfYXE+L+k3lSXjqeQYYEUaN747vCUXdO2cXv MsgMqqAqjNmEBLkfU081maTByEBmMVTl534/vxz3OXxE6pWTTUro1yPiONJVtktEfnQ6EB6Od21m VgeWTUEpNI+ZvHJNw6DeS0rCk4I/azcHbhXry17D9k/kSfMTnHf/NBGtiXC+2DXscNvHH1chwKeu jTB3yLLN2lRdTirN0l9qUVJbyaJboxO8q+zKvIIgkfZhUcgZKwrKrcKLO5KX8gfEYJhPzJg9okoF d8oFMbWmtZiEhg8rtq8krW4nUInbAAQSMRCDUiaGBAMFCo9v1IZITsg+VIi/yYIZ9i7K0+FjgEyC QfbnSUanBbcZ1tHh3QKTQHEEWbau3A05y6BNvY1xorINiq6vSEjtSrrSeVCuFM6CCg0R9y7KZtnC F57EdfD0JjP1C8sypt1o0H9uFm1po4/+j5Jiw6bf5rWn0pQH/nuaSjSvTHlp3Bcl8hO2W4Rmagn6 VweXtaVn28gE10vdEev0oZFObpQFfaYCOJ5onPoyvbxg9MRZvVrXOhJOA7wdY2SronZi7GUGHcoH 1iaJbpkQ6ah0jTw+Mol2PWn4eusngAICwqTl+qLFZ50aEniVR1vt3k4/SVLWNhExNTeyIqzztlFr KZ+hzv+SS134jqvlqKPTU/GmExxxsvvp97kmpJcQdYgzWQonx8b/nEGx34fe96+7BYBkymP44uJ2 gLsjcwsa9NbqQ2WEMCapO8XgejxI25gcgd3v3otluJi52QHQsEz/oOjX4BtpL92kT7W4t9fuuIma SG91eYhgpYmdJ4Zbu/rVt6QG35VVaw15IhvIGEFnL7Bl7GE0ahb4L52K8nDmPx6zai4MZDhsfN6H 6PFEXduy90cGNusg8yXrPQsjT8R94mUNVM7aU/LEf1ohWjHdVq3DLdxLb8zMugHRnf7hkl2w1Okf MAX6mMMnBwN8XOUTtk7QFJUp5k+ddRy+rcBc01WWgpXdc6Yq5Wm366DtMsFxYMCjBlt2xefYceAT lQweXbKCcDM/GMOvYRa0Cx9pAfiyfOz6vTIKICbjmCMq6chxl/QtuxYkOK7tbHCg/oDOGkvB2YLs PT3uKPI4vJE/oaxn0zoDXYt6uRL3XvGvJhJrJjexxOLwvSB3WWZmj9MEnz3RY0Yc2bZAMo96HKbm 8LMkqICvb7ix+uypJcwHVD/RsEpPF7O1dE+7Mi9YYeeGv1oRb8C+iAVCYkN7jxeAFQGNGTP9J1pl E+9B9eWq9italggaR6R4QVjputFOnXz71FdoeHY1rMq3cUF7MNyklBLlMMGIFTqF59zx7bjbn3Fj vRb4R06Gj7P6Yo0g3nsoGjvAfYbVTXuMu0xrnm7EXF3HLgiMrScm9+rUgp2ADhMZoKSpgP4oe4oD +vRgJgJ/PX4GrTLqjKFxC4r8ZcLz8l7bwMwxIQQntwRn2Na/GcHznv/7S6hKnfayFJRzEjLeYKHF AsX2GT2Qzz/1F5qB+ebHYlPBIF3z9et408zsmslRC1fUBiUt6QDus1mf1BSX1JcN2fAWBcCnJLTj UpHTgUL9ZyBO4CRpVDcZByXQ2D0i97agnXXCNkun5Y4aYPA/eQxZGD1KJisVsdIAaFgyu4JQpmi+ AJtmc5KkjDSy6erazwy+Rl+GJrwWY2H8MHSWh047XS6SOmUoW+mDs9BFiTHp5KAm/m20cVX3+IRV G3qK6m/zutWczCtBUYmWr4R5UDMF3w0Qei12ujAVvA3U+mRvsjdre/QO4Wg3MTwj7mVweH3HO8wF ixC7kyyy+YkNiqLNZ5WGN/CVYpqW6nLIjThPXSstyAregDYcymSPXbkWz80yvVk2/q3vizCpIkcv FYvTod36Hlmk1Wi12HXUlN7p8iiZNsmjpZ3w488xQr1RTlv3OWI53cPNrP1Rf7RaXqkDTmKVno31 ZQzIIRVQO+wMKylYqrCVq6/uo/wgkrPBuP7THIjZJCudhc0Zl9C00sXCaBcxnWMpb+i2/t14eX1n FgeLkXXzPEgeoVE9rm27K+cai4qT1jTM785XEvZsM/mhv24AAvqaTcgiuyh23dU1CbB5KIPgdwhg jhZbNhkgCmlIMWXYSXakbIFo4z01gIv20sPGUibUzQ7BA6G5s6DPsUs/aqeXRC59bnkl+JHQS2T2 MnLCL2rqwbv6nrvpuihPEu3o9tDVqg0tr8LaRu+8riXvrKVqNfErPS7TJXfzhW/M2ikxrs2xmCJh uadq5XaFU7B7DrLfE1AL8M5iK18YCpwmwvEz2wF08BdSicedIi60lp/jcsZHSRHG7a7pLGukaeJC yyEBC3zvCd7lE5mVfckDV+FAcIx0wa8bwKoCU9pWxVv7KUr+t+spcBUnkltTIauECwvhd9FMBlBo Tv9lUBxOq7lxdXmYhSl80jzkLnCpbxvUFhLaQafR2phLVJ1e7q5SxpiS9V8zj0clorvJQYPeY8zk MtA3jLjeE1QCnKEl/uHFbIckpuG2zIklne6RJChj5poo1eaxitXAgYDNekWji5/NrQDb3moO/xr6 m4g/v1wA0yEJQgLjQLUbbhVtmvZ/0rPg1TV4wR35Or7Mnp9mO701SCi6jqcvrGKvOHF/nV0sE8GW WKPCgTIIPt8A63PnDt2dRKWlPeaqBUZ9I52KzNy0Io50WEkJCuN4CBnV/nZuYaFEzxzRqmbzdEI7 aSX0Dm/wTlgqwiw67em/dbMk2S9rC7K1TO8r9jX8Fxmtj56yG/WmGnE+09GxwnA6lvTBaPc1/3CV k+FJnGDoWM34bYMouac75WRmUJmmMwMNhlNHJZVTRa5H1uX2Pcgj5LDNyzcKOgDdJMkmM4EnJeMk OGb/sZ2nQpVQJO/DDw430OhpnOualbzux460es2uImf0ZI7LtjcsKEQ8csycQnSi5hT/IhAIKmWs r87yQY4p915XOYNY+iVZDFcXhnBrEONrlm1giBC4em8pDR3FCW+8wTKXDFgc4hDSKcz3xa4vqDTD Fz4c4umwBFAhG45wve7KAA45adx3nIQi5u081PLpiFS7mcIokSVPycsZpmiEypiUnHTFAZXwo5Q4 hSCwxVLLbOz6DPj4euZDGyLOCAniRQ1qjisO8lOiBE5U9yP7GUrO7LaPe0CwgtH0szR4yJPJaDnV KVbsbDxC696fcgUIcDcY+PYLafEx0kLKBGQj8ksXmdiLlWXgSRJ3NiSKrmyC67ytegG4xaW9KpBi oVccFOD6RiD1REsfWVFn7zoRy5D6hoL9MBsY+aHn/GwiW7FrlS8gP5ggW9lw4fxzNhRAqmTJgJ1N EEgNrtcHV4yi44qEfTEdacFwtba5m0mYphckmZvuStABik/SsrOSdVleyFN1GwFsXjllRLAi2J/j IPMQhdSyGZ1QuumvG7yo2XTKqaymRL80W9Lhd5c3g6/8Wb7MDdbtMydLcPcfpxlbEC5YLmbe9pjj UHh4/z+AV/3yX50oQ9YkPqcKiAK3rjErEJOoOVOnhCKn1iGnsQwdktsicfxElREEliStPzYZNDTO uGiOeYHuMH1PofEZZTRgu3orpHZ5vlHH8mePNKOMn7lJqUH3pGRE/nJ4nZq2punasRFcfbomB8SN ArddeVX78lIjohISC/yR9QI2jbFgqpXTrZdHoQwfgQKwUXuBOI91CeS06yF3wIG9R/CtzvmwCEqf u3MHpwgKhnnVDPhbBzZLUIkcI8lU9pnNtHEuX50/fNlRCSkSEYDsw+CU29f9l8kkjA0P411YWpeI YAb9z9K+FXzB4lmt5lrAuqfGAsObQU2pT7wgHaYcRHyAP3cwF0ia4qYv2kgdRkbFhJFo+1Zbk2px 2SqVlcXC0pdhNRTknrD1KWlDFScsDWKLBg/JF5DOBctCBLSbgTxhTVUaAjzzWv0OWO3c7TmFTtI4 dcKkSQ+JLkkeHU+6tEa9cRJAJgbgNmSJZQaai6ZFt50hf6vLgfSkkTECaBfuQkp3eeHqTi2g9Vzx cy0hOgKufPZlUsTHhL40mPX1gbIacsfqa+bWYMbPQl38jf4XkgLTL3n8DJaltaUp4XwMyEJj5XXU zy1tjSewONZrpqqt6vOANzQGhFKCufMmbgaUpPPriuM51gUtsiuPPVEyHdDGdY7Z5LVpFbvgGpQH YBDEo46O62IMrpSaKgJyjKdI52vL3Kyp1jTFHs48O77ulObxl+burR9nKYqDFIax2qFXAil1QFzT ckjTlDJhS3feNM1suHLXAuYUSmPoUymeHKg/B5D+YgNEpiUuC/xOF7u6fgi/MVAM+63pw62rF34u Apb0nBDXH1pCw3WM73aWv56iKvJm8+Vrbnql2TNV51S5nOKiSpfGNQ7T7k0ivKbJaw+UYH/NnrLq enqfP1kTAfmXb2XCePlVxMEhnlN26uXj95UYWgfmUp/+f9WGL0m3uZ6GqU/B+KpCdGXFxkK1skm1 Bp68Nofg8X61fp3JoSkfZJ2HnISdNVVBLf2xr3dm3grw9D9dT+drIKCe9ST5SPaZ0pl5CwMxq8Qy QWceR7cZ0n2ChrbRGtYPSUXZVqitiMvwr+hO/1Wfsdg3sbNO5GnsZedAzsP8xxQ4t8RIvNOgIsth 5+Tc5BO85miM8jaq8IOQPzOSLtQ+0sISUDYvbAjhNAbpFjfk1FbQ9ERWsYtmRAfo3g57KYv1X3g0 Y6xJTd+WTBsCmgUkTOAPdPUR2tQp2VSRrDqQb1nuR6sgL5meqS8ZjTu2MYLotlJNJmAt4u5MdRAp XNJUvSZfuXL4oKe4hZk7TCkbLgtgBzxqNgHCnvs+87s7G5zU34Wg8HQoFKgsLpPe+ia3UFFhGTsr qneoP3vcAnzavvKAsMjKwG5C3EEc+747ia+rFGcSaJSEux39EyTEgVXmYPrUoYTEkXporWBRfACR LFr9MlaELLFNuMYxGl2QOgDNU8Wd+0dlEKxZ9tsVD+kFIwxjXCFzC8UieNv8vXJJ153zodiJ9/qE JD3ta35GqnmQ2OGk80LdtT7JJP2/rgQnxt40ikvR6QysmNmjwOyXKj++PuHS3TbgqdJRbfoy3a4Y IiFW+Fe0LMhnwCEdDtXjaDA8GfMQNASkZvX9uw5Qe5duJXM8PGt/JPAvkyAJXcEPIhx5Vb3WK+IG wh1DaVRsAxvn1vz2iALVLnYXQqF++2KISTRaj3/8OUtv8OE6hhsbnPpvwM+4v16TqXH2XbxOHb4R bivDFEesDxIHnkkES8q501anJaPBubk0qh+r2XvDH7HiEzM9Whw+lht7iJX2ohjFnSWg32g1nDZS cThUlx3RRndg7FdyGFnNKrzvRYLrEoOJy6z2fh4FlWNtYP0gKi//vtfmkOX1YmbEFCM5O8MJJzXA PMO59PGyN55RdNh8nwASC4hTvSrEoBjk0u72NO/4aMWr55zVEO9lg9qtRCoQaUfCQRcHoddvcadL 26+qZoNTsw1fBS1Rl3xEPkrpCtMyiKZtI2yzwXjqswZsTfP0vzkQVzPLY6lc67U+rwMGpZuhNGXS 8atb0MfXSTMD2hn8ko2g8ZRjPaC3GMqlOlTgodaMzwqIcx4OF80454caFuT3fk6AZEESOaX3jt3s Lhtf8s8WqusS3yio4vNVZhNQX1DYSIxuInHPCty6kN3ok86pvV+mygXKEGK9V6RicOX2TlFnqbP7 53UecdAKm6FMkpaB97/IsmbT1if+4rT5fwdVg3EX0kwYHexWasBFkc6lDuRq6xlvlZinh9GR3zh/ H2sMs4Msfe9yat8SaJaUXjLzc06G+RLwVJV1axFK+Wsk72Hjcap8/DT7NVWLhtOZ1tX5D1px+kiJ obRJG7Re8OWHZ9lW/cRrTYQXYSXzhZw638fahIkXgna8Pzhb/HVdrzlTaWI83VM/VtXOQj6TJb1l 1RLL5S7hR9f5UM3Ptz0SsLqhFxJMh20c1v2BrpF0U+eeLdQZpZTkEpFeLIF9KRQ9f8HuJAyq7HXT WsnpOgLhMldrup8NGDZQQPvR+eb45kchEi0/Q+oNuc1EnAWGeXDqKEPWN6G/2XRgzhsNFujC1jGx +Sd62Usg+P9IQzzlF08mWbT4ho2GQlrGNE/7KzQCv1p1AYvctU8MuyHWR5hdyxmxdbPZyU9RtX0v GmAbAfJx8ROZNCVtTYSLPZD74+XZCpy7nVaLOlr57Gazykwmff3U1G+wTbMjqQAQ0PL5UHxwDmfo eCfwXtB6u4MrRGy1dLtT9/BRjPBCAux5PPf30y9uWwgQ33pwR8T7I6SxPYXPAu3QH8R5UPt910gW YY+bLTTkB+OpRL+A3ai4blRla4mUATHOsS5Uwj66xUNR0SFxvbnN4epLdxxKBjjnsejWF3abg4sL VQVYZNeQpCx6KQ4jGg8uzfcfZMiJf1VZQXkTlYQieLpFFdWdZaofY61j4D5TC0lIro4LLWFd0fCE mUvtbKZIpYD8nKw9MCnGQvmNoSX9PxLZuLbQVGzI/QA5cl7U3QvbFhtjNf0JWj8HC/oDn70f2NPF uRdbzCgoi4vKwlVMHHeP2RCmpHfPRC+0BzUurzHHDSQ7+GxjtwFe+Un04tHmve3nhDUPAno2qOWw qLCce22GLMueQwPw/PysTs/ka0uFmVch2Xo5TI2K6dNSbY0nod4+g4Zt3eOZVT3cfdykcDpY9u+K HToLzurPXUzeM8Yvbd0WNdAkrjgiew3Wy84YKceid3YUxC01QL8IISDSttAWQzRzWIV1Q8f7DktD Ennj9Sg5f+HUbhXRCUS9mwFYAp8ZvoIEsp9if4z1RV0WzPwLe91YHRpP9ZTeKFHSvRDb77HKrr0p Nv6rZaRMQ4xTfDetPjojqfvuLIMi4BMEhF3QABsGjoPSs9zP3n4zmv/w/DvfD2va0ABJ6pVzuIxt CkwmgWd7vb7vsUFnLB2NZvxakb+Ct0AINYsfH2bKtmkXm2PScwNWdlGU1W3BvGI+AHc0o29zx+sD NWB+WRCMSHCnUFPWAlko5L3xGhNia9BghGsaF9vTaLPQZpiPp50fStFIIkZ2Y326g0tQRt8JNWcS u+p+GWRuGY1GO/qEkk8W/oZMv8Y68ssHbFmYmmkHYTqRVvlKMfr79U1zyqpQtDYraGYzYKVW4xKE unRANo8G9uN/VnR/0T4X6GDgave/ST2w3rpD7KP6BdLZ4VBz8eot83coNuljk01pztQrQgOffkns eqzD3NQ0RzAM/q35QGOxSjOq0ZD28tCzPX/6UGq/CGUaJvCJ6R4xSXtYzcBh//antfLTPIah1dw7 J9zngwpD0kBGgFO6c6zP1cMKj4wThi6oGg8dt68GTlkPiYMfd+c1LCOgbRuRzS4ErCDImW6lS3oQ cxCZ0ogzMtoH3LNZfo8Ku+zhvLqOAoMDkEU5TA270I4USmnt23xawylIfnUbSaqy/+YZQ3EWCdfo XQ3EJZt8tkCPHhGQEHn7Xpe2gAhJos2K57fD1nj5/ateUHYrYGnH1KigSr4ZM5fnuz9OZULpDDmX 1ouWoxYf/AU1jTViP1w1KXcUVj/amGqKvnOKhMTeDoVcbJh99GqT1wgCfO3kQRXmiJq5LLJ3FPUi 5dLz6PXUfYK4kPqGDk64pEVxAF9Pl/NCEcr6Zi9/PbuRB1EEB9r20pFdNXRo9iILPIY7czzerIIO uC2BXBOjJAWcmDWjO3KJS8OlG2V7tpxSVI8ekU67GEFGkOBdRxr+MpF+1DrijiR7yNshuIJRhcLd LqWHb0e6OGzPlHbIF0xnwP/TPuYFKoPydvkfM74DXODNIpcUHAmkRAVa9s0z2sE/xFN/Xf6mUV0F fXvVLW0BiMY6axIeRipFFVlaS21WSZtHqp52JCdIr16gkNyfCI/ClM+FZNHOFXNAXwLEQWqyE8NI KhSXkIttWLe2ZjvAMRHI5c7IUP62ZqZ5Zh5bkzwNLjk78j4TsNlnORG371fVxOyQ+AaS1k2S0c/Y zUSwsAjckwJp19XL/lqadoH1r457kYEtgu19tONpysQxvIFgtRG21kp8FENJ1glclNpgj1wGgAwu 9MXo3AhiksRTPcGlJ+kGXjKenWuMH+6zu//SvkCgcHYoeGmb5IjEZppYl8UdhHFJo9/D+aj6JG9U l8mkleQoXn9oNpwuuD6oRp4hIF3eudUYW1ig3BEgMutz5GxSXfkEesQfsMoDtOrsZ6RXrAGv2FfC j7vmxaZ3MZlnOYo3MOq81eiHTe6vfVvwN1wGZi4D3nbDvxUAecg3Fd6FSFrfTuhLimCc+e0JPdIx 5CthmEKs2ACI0A/TP15w6KSvTrv77wiPa+qk1r7NDC7CNj3K/iAZ3QjI96be7Kbf85PnNOWkr/gX xpwRtwJQ60l5MoQ7RLB372g49OaSy7TWqs5/FbxO68at6eeeQrmCyDZzk6ZK25v97TmV7S2TTeLI QCp+NMS0+8Dh3gFlSyxDxTlaDTetT2TQNrg/ugv/wotchYCOcDKQCqhq74I+MBcaRKBwcuFJmxg1 QYhAkz2GZUowJZJXnnds+UC1rtToKUUNZP1wNUYuj14whlFTUQeHDH8gj+8UPNgMOMhxuWr0P4cp VuW6Wc/ga5CMtPFtsp6hPz4lqjBDsZWM0g97R+pYxpcM/dV26pE2opLSM8z+I6r6I6O6YtALFbWe X98ZKFKQT6bNEg5trIaBReOmmVyU008OlGsgxRFU1B6VUIbOm1VTl8ce4Yl9Tgdj7Hkmd83IlkWu 7JBD65p6zXrctTgG/m5V2rjHxdjmMS+YmJ0wHgI/3ThvlAMo9mcz+1dYfGQBRi7w8+BYX/E/6qST HlVOr8L2RfLcWm3Fb2xB7yjd2Xf26w34fuoa5ZzRTHEbRaK1stlv1uyUhllEVhoNSczhOqzPWAwo FlEZEB+wDQN6vfv8lYUgV9YNcnUGRIItVTlgxDgs4t2kmPIZNKncjk4fDi5D+iyNZVaLbGQXTG3V xYJoW39rKswMlze9+jOZD7q1dBzdTqV83MN7h82vs0NK1RFYyl6VN68N0BhSd+vZqhUFtpFm09dM ZLsmj/10Dsnb26BVIOX77oYJGS9O9eUKWjv5yV8GcpaurH2EAtCAC3YoREHX48MBR8pYX1o1n0+X QEHSM3OR4EX2IVC0wN21H4hYf4uq3RZVRxFUi//mJshdA+SHiQnc5MruWgN/SIr+Y+Iea2X4j8w0 yTSu6O5KaLwkxErrMSHpDEmvam2+TFkWpIM4mCA5BEh06RXbUhfzBN5OTpCnb0qd8oKzV5s+WNJe KygZAD2q+57qXfhT0oqZCQeD3ZqPFy+wWYaJXiXyg/8AnO9KOnnbGE6O+5VgIVzZ/0UUABGhAy0i 0eRbWGaZR6V0abJvh6Ta9nleTcay850jWvSq1PhC6MLc4dMK/CC3ovSOnqhB3cipJlxGgVKAYZbJ XvTEkot5bxdtaLZvVApfijaEbyW2OAYMV/N1lkF9YVnml/4/l4sszE4FCVgFZ7u+CxYR5wm/XAyl aXVW4NxZyUsiUhm2YRL6bQ78bT6xkAn1ydh1uJcOeCEgDCBMXFgQD8uPktMJk68SvWSwv8RgwVAk owL8+wmT1w+kYOgScbEhLnS2SEj128mYThJAbKNxdQD0DWYWaJz+Nl04WCOfXnfMro7BNMdgAY4t ito0CHNnEZEse0gV9yH7f9yHOSR+J3WMFFgQY9r5p5DdE8fCMkkSccGGY6pvrL+spjogVTieF/8H PxT4VxcwVqI8PzCoohNIq0C/jUogNKIT/UlCYdNi7VeWY2eprHuxl9xGy3mzcBMux82xKPrglKSe vIxmpLPGmfgBrspU5+uFcB5EcQrxO9lfSaLtIZ/NzTxW+4BQrZ0+LKCDXdbN+xN91HAPelYZ0w68 nT9nQYgYYbkUSnV4fXkmnvTudzJQcEHfejMuHI/fgj1ZS2uGXRJufw3Qj80C9MsrlE0p3P+Mioab ytPAeFcZ+NaV+yv37qacLoHmwXlH46sCBlqmgtM7RGE8PPU7r4C0KITU6JHHc/I4pLj/4cqfMH8B kD6h7MfZ21LdhMvNwc7NuhXQ+RRZEaclvp9IYcmvrT/JKCnoIEDrk8vGOyoJJYyJI/FVC0FZZgG7 E6HxP/F28GDK08ksRIxO8lKlOQyDe2auMuVDJdRJEouLwISt2MzrLO8r9yCTfkLeRT8p++m16Aw8 iKnee8kaS9o8jOznX/pxwCrN/gfeMdfGjm1Q2OXxC+YU7Tii5TwiqnQMNjF8cExnz+gV5g66/+Kj p5ulYmHNpiAioyC4X3dVtXmB6eHk9TkSOCFxv8b9u7ESWGCHGUW10Z2+6fkzpVU4X9UU/xCzo/tu NOd3GXvX60jJOqSULEH6JEMn21R3kRzuebWNjP+jB0jO7mL/G4J1SpYFWpEPtk7yuHU+OF/rabea DwnYWbEFgGpbRxyIinJgc4fzzw1RRgEqeVuTVlquF4X0M8DPCP+5pYrliypuDVGezl3nhCoTmmRn +W7cZMXeu9WwsixntdfUvzxn1Zra0NhOQb3kU9bB7fdRFzszXe19SviXFC4/0OHUxi3mENzmkWaH 98Il7Y+6GfUIgLNUIdAO4lneML9GiJQSFBSqDtrsm9vJaROwnYKuq2ncI+rbQb5QjA01Ky/BWekz jyApPm6+t3gUSUPgAWoYXM+80xhn/y49bGP0hxQPhrGI2i1FyUZw2K9XZQp1C44+xLmGO/nSW4RU Q/nNAOg/ni4SquEe3YHfrh1VU0N3MjWCaHUzqGTIZvIwSXXEFaZIPDSCc7Bd3N2yQwEZyjsLLbyk oH+uwIHKMB+rM63Vxmj1iDvJ0X9OHy+V/9SAIDkLkn6K6D0jn8ciazNqjErWju8Clpih7Lx39Msk oBx85HvFfzM7X8m3Sw8Phfmcxw2ZWQmmf6hsgAxNnG3xP9mIAocghisQ0UmWV0v0suUXP2k29sdj HqUCEP3xQyUzaNQ/oBPjUwZhH7GKyzAHPGRqURDmVHM/bIyIXD56bhGQjy4eu6/ChqJmINan4rGA hWA5pIt3qIJ+2S9REEYW5kEEBpNuSaZ8XWGXmyj6Nbqim+5q/LDGZV+AkVKgwDBR0OWZ4/eVFJR/ DjENnVY/hWnkX203S1b+eCBvqdEPrX/nBt19s1icv2/W+4ZyjbaQF+93lk8enTNnHazCeATxIiK9 11R571HouJOxXZkhp+Xlo9AyAmclHRkeFQCwMycTXmR7opoHEKuQz7KWJabdtANn61y7ObWp754W nq8tiIb1zQlbw+U38rS2LEPFX3ycWTLlzf6QBWTLMDmh00kqFvU3kChKpMaSipHLsIRcZ+nviv+y Kf9TudvYh32u98XU2FTj8DV+mfaPWATeotC8HeiK6727+7ZtsytE+IW6Ibk9ChVVz2N4GBBsfqE1 hdXTQt/91VuKAC7pqOS3B8G7Bd9jsewLAH1Y43KppdHDX9Pnz07CX2nr1jGGCR/0663LnPqYdku3 K89fiKymVzWlJHO4M6mqVNSAQhf0aNR9oiHtOnlu4OlNXWti+pWXb9OnXk2O3ZQcXyCJ2eg6tKg5 jaVzSYPtb+p5ki+3zv6AnfHFw0b2NlxgKhV3j8A8QUxUl7nRdQA3tiM3I7CDTXz3uPUy67+pjU1/ XnKhPqu/kAGHZcBAHyZH8FZL3iCZLSyyYGeoqoPBXGWgpmO8aZC/CYrOJbfRPsVpKu3hLJ6tbwVD PM+m2xKuBwQ0uGZ/KxQFhEtPPcTuKW8acyI9uMJHdy7TkhUpBKPWNNb/jxjo37+PON4DG7cS+qeJ 0hA3SNloKVEjKS/AX06NpUvXWL/AsykQfzpRImXKilWwVRmT+C0JMJZ+IJpathFEyOXHMMxkensx 3Qb6BR0hHvoZLfwCRkJWahCF3QKNoCQGMgOxprGayK8u3DpPWrICAdOGzU54utjN0LdXhxPMnTN4 Q7HQPtT7YN7AbDWaSMnOcobLxzf0PV0F8UJF1noM6ZtCeHWnDiSPIxRln7FQajGTct3ZqFw07Sm9 2CH3ugn+JcGKALbr3BZTVFTh0PXId356U/lMENC/6mFSjEAckvw7Mxcf4jFhl/+15lynTnS2Fn+V oU/BI4sI/WdDRl26PqBeYQWtKfbB25BVZ+gaw2jVxQYSv09nWwA2/brXPE+loAT2+ovsavdZxzeo 0dDgZpskbeRr0Dp/Ozxt4MBjXRLo0HENu9zCIqosEdwPH4IIwaHV30dp+t/Mf0me1d8/fN5l0Jf4 O/rFj/2aiPFaviylwRT2vGQ7VA75AxdJaPqs8mggj3FBl7Db+ARfPIIUtYVjDgN3kvJIgizQoN8R 1JpW7HX+kG5aj4BH+eSNj0yWDq71XnK4xDxREpyZ9Y1QS3AvTENujObPBAmsrhvJvvBuzsw4M6av Dzi+f8T73qZZcJtTxCD/3Vx2NJZRnYwW6sfnX7jRZy7gFa3yMl+xPoJF6ujUUcRKGvPJoJE2NZqS 799YpvT0VSaTkrPht8OSY1tlEbNLxr5FI2+zok4qkzybCKVXejo4JPPnfasBahQrzAK3ir+Ks9u8 pTccWZmyoGja2r0M1hUliNikwnAFtGt0ewtEy7Ogk1BC5QhN64sJ3De99N+06u/DwHlCAVpDwQyU mfGEAaShwkQAku44DG+6EQx/yCjGYqCWYClfQ/ZIfV/8aGVX8zGKgBSs0HiyQCFr5d4s64+IR7qQ 7KwmYO68NbzQvm1uqYHip+b9imTbnXsduj+PG5FbyEkKWFfQe73tGxGzEAKmFM5fVtDVUrNKUC5r ZttDfH0pvj53JEmX1R2KhOt6m8tdYrrapXG1Qn8UsaqwzYKwmrg9HneRxkxeaptWa0romGDoZWfa 8WP0pQYNxOC4886ADTTNuCqnBZPVmBWdEJvXTK6uUgRPYiyM6l7pg1rvspYPE2FLE1ArZ4LHzVoK CJ85/eL5bqpYYKczmu9yMTaLAgPd/p1wPkolxK8sRxwsta2dGK7lgQ/pMEO2P2HwwKuLGWjqK/po TcyDsgWgE31uhC9/mI4EXb03PrFth9ZGt4vrK2WCMEabfBaTU1JMDivKx7t2ahDDGy0dJYbV/253 WdOlUAtWz/Ct0wz/Ufd5sA5XqLkI9IHG7rztYBC6JHgRliUU+aaFKNu2b9297EuntKpU0CEgSjlw LfK0+lHiST7ZoM4YEJsq62M45D2pd1JK8Fuc1/EBkz/yqXiFrb9hLLW6x7PBbWLFV+Ky6OhpRZ7p /1IW/PAqvSixkDC4fSO6T1hGs1ozW7aTJTICeyXgXFOgxkdt0dlrLxcnUMwM2h7AAQOZyBB3N33o BlFI5pcivoHfSo+Ap0IRNWn9KeDLWMYx5ljfq+2xG9vyWlR8cB7y/5wQP+5SFv0U1WuUlmaiKN3U vkxD0I4V/XODe53IGyB96oiBY0ZwAdCHWHi7sCeOPdGFAeu+/NfLceO1+oW/9vnIJ+bBXLZ4QAFQ BmztjKz/zBM6KQdkix6dofXs5G1vmnej5WnNve649qhxw6wiKic4WajfvJ/TyDWIsJoZ4pYnWKv5 g+7ycVcG47NNEj7McoJzWwpVJxiGrv3tZjd/wQTKcdyLiXXZYg73swwFOZ3O1L+QsddKU0Y0X4Ux Mcl52cvGY448zfsauNXaE78muUrpXKnYs+hYaIv6u8LabdyQenaX2OrIwcldgUwfkfRXOycjeg7q eqVmz9ZlAlAoT7jNI2QjkSuwE3BiK5LECbDhMYPD3xmO6qaLnTpw1r+7Y/tt8haZ5Qze2+WJ2Iea OdrZ5r+hZl2FScxkDKQbUjhkV4gS4m7TNj+5sD0LzRvZtJgqhhNGJ5/XR2u+dv2LHGh2U/hKu52o RC7I0gbTXqHUTGr9XtBwypLTGnoNhWoBuK9+PSnQW/7Z/Z9ENCBaDFlnusjrJ5BuORfuswfr20Y0 0vgY4MfegrGjdj1fVfS444gt3bkPtd0LtGG8Y01Nt9+NC8KGqdA2QJ2Eww/x3MAk1AHkJbgKlFmI dDLeQxc6I+WxGFfiV3C/qFrJd/jlgQdwUr4wHB89IOR+/BRoNuuXLxJXbaVcVbCk2ZNaL5zHwiGb DBFku4rnr/WS6Q6Wly6HTHWgeFFqTJ6Pqmeo0M/ClsgJAKdGFYqlpzi88CGEjcMpkwDEsSsGpqn8 wJI+Ilyi9elBVwwHk0EEeBWHCZvKo8sZ8qCQDDLjM71n2O5LfJjR6k4MLMH3EgyBw5im57+aTZg5 9C4Z/8+yQf7ZNaKPK1tPy1wGxVM+9ToBdD2shabSYyBz2L7HZ+0i4VIdTthMS/KO4Lnme/38jrnH Me8nCq9B/Or1+vGRgkk4urtd/dYVJ6GAoT/6MasVNa/e1aa7Dvgtn1NrCz4Nr3O7oqyeEMkVPTBs UFU2bVZB4aoIxJLqLIn3CPoey4HLVKUe6+XCnDBPo8cTyrF4jtvbDv6QJM3wYOoBfpNASiy7R4MB svnrK2n27YZu2pJpk3tudwwKp9RoUpYYEA55gouBwoGW0km5JWgieHdhfFx6LnkPIFr1UeiAqP8+ NawsD6FC0JR468pcl2rGX9TjSqnK/Vm929TvtXL8crM4bbawWZOwdB4ZfSbLN/bKu9TgkYeoLcAN 3XE9W7hceMK7/DI6ufcB0mpHqZQ+s4F4U2E7HbKu59kxECm8BoYQU1pvaM2MY0p10ag1fB5Vhlfy /bTW/XrAm3sIR8BSDtYD7YWsj26Hnsqt58rQSclIffQ0ieRryZdQXw9etSZokcrY5/F2vj8rM7Ys VYVnc3tUL5yw4SlOaYHGhc9XYkW3AYuUsdHmngylGnfPdvsa04nAedxEVP9NFz5Q9vKp7laSxGMz tpoQfD11uZFfoyrCCMfAjaHRIialoln1PfjiykcF5R7VnY8mH1tp4SJe5G5VuiUkgo0DTGh1Z8SK VwCEqTw1XUbxth9Wy0lCa0yWllI9kyPJtNQZj7+o3hTTfCPj4+iZmgtERWICBLjrMezBxoY8hX2w mw7DQNNCCGv1dGvtAPhNdOUCVOmNmeQLmmcJuxEiCc+4xAZEoy1lRNlY7FK6n7Q+5JYf9yuai/// 3V53VglwsUg0dFSth++p2iCp5KREG4YbNdVwA4EBO6Yc/62A7LMk41DTSdQtsXc5hhAK6JW53dAf QBQ7qw4LYsdIjyx0K+Z00ivyLqW+PK9vwHU2cuW9ZXqQ6kRtXUbZy4T/Q21Oo+B051ms7EIZeJPs zQgnd8iPpUWMm9Zlk/RNvqhXFxlisX5xLw0YglBhnT+Y5+GNRDMmSflviWI4b1pKh/sqyrtIP8IB R9xGpL/pdQoqALSYi8SvJ9uE9309EdEpQi5YgQmzzlhaSBfYKXpJvP5VQ5h0F1De91uSdGQHgYTs tiVMw1hh6RYPCgw+UkQMNxSrylpTT2nZIQ2MCCd/kshWoqSt7Id65dI0MpK7TuBjE8c/oPVcTUjf RqmFLBabns1QTkZs5ymqQMGAVtJbZGti9SDoJIwdIdu4w0rd+do5fb33HFLGEAl5ub6vQsOstmyA PqKH3CzSD4X3LljDw/o9KyqwWe72ULm/0XWpMrMhaandpLpcugyMplIIYe6JVphWrtYoCiexk/IE 1qAHH6UBoP4q1GTIbsv8czzod/M8SFipD1U4e4xA3AHmhu/WibreCoE+85bZhG/CIWWYJCUH8xG8 acQ/GL6Bfi7wfLCZ/VWGehe+WX+AtdWNl6Kz+ayV7Z+kaq0KxnbLZWSL8/9ATaj157e/GGIRmjuF ls4zRtkxLIUGVQjnh/4BRtas8D8W7Kz0lmsZ61bZ4cI8y/4LRZSmwLh3e2gh4pSCVA/WlCCMl9Qe rOHP32Afpvjf97waor6RV9sCZyIuSTijD5E0dpJqD6bIbvlPkul3l1C3xMh0Sl7yeCi+sAWrMjC/ KKWAdpSTNLJmnoWfPuAVwHQOcwICrAoPOnhbm5Qpdlz8Sx/mZKtUFRFsyA5Poyb5CyCRAtEdx69r hgVh5xik/gvDq4Gx0kEVbZL0m3nXUDiwXJoGQI6HE10gVCI5iDlliZ1/aSBS5wM0WvKVfh1uQnDW Mk3FHwumRqiG+VABDv3i81TRxyN1YLWmFZgIv5PCUzwhSaZaBb2DO4K60A+nUdbvEQcqhnEfxeSt P1I40TUcC4SfrRYHkOPkSpeoQicX0rdmsro6lPZmVnZqxvlDRrZRWS6X4tso5odRY8R7g0RVo4WN ZaEmFZXwGlfdDAEbhWO3fm4N1smPhxR84nue+HaTcUO91sAHKYfNMDzH9ZHVjJH+d1gFQylHFpVV HKOrTSTrMUFQ6HJa+dy/7xTPx3xtNEsPXtjagoqQTDp/V6fU/E/BIISmYcZSBhp08PFuC16mE4/M yCqh9lN9es3UBhmvICyJPoFPRYBoNk5kmODa59CtChcv2fGDBPEaJrCVd1bdNKHiT5UKtfb6zJOA 7WDAmocksfi34F52A+0L4Tl+R+u5osSsWT8JvO8sQYCJIqbqp5zwQdpmmCMd4XrwVJ013Ooe+XG4 08IW636JUctyBAxSYNkV+e4ANxlrc1NHPAC33T4MOcgETM1NEIaCWv2XRYtS3ph0XnYrDFAxxKWD JeJ7s8LKMxIKqnekU5CaktvTbrZlYnAXSj+xIkUdK/FeRCC8l6WnWZPkMtZDhBEXTHgcnfkMDByH qHYXUsVssq42Y+/gp2GsdSq7jMnslw2uybTdkb8dT5xCo8QVMwMTxAyO1OTlNBLgjgvwQVy1m+fq bGeD0JBG2637WD7hktj63GBTyXc9c2rzF590Oa6cfXJdwrw7EWBh2nlPzplad/m9DFDIRcDd7nQr hRDnmvnjE9Mph/kufGCKgU9T8S8tV2RBkUqNnQ8hF7izRoBZNYlD1jGoaCjfCItQc2qGQca89eef H/2uvrFSEov0QE3877jycD6h6j6zXIKIZcsbCvWBgovKiZmXlKDhe8bpgWp+/uefP1kdfGncujbJ jOWRk2FdFrjnsC9QO4Grg1VG3OXdxLW4BgImiQW35w7ayRMp+ONbFT/deFPoql+o9uUyvuINkaWO 6fx4z75ArejfMz3owmXfjiwtfTgzBWafQgETWjapZ+22Jv5LYIAbfh6nyReQDOsv9gznxLZC/doC vApMHL6nvQKBOIE46KoxVKMFFoIYte+bA/rf3si/FThrjBZR7PStvSdQjFfNWdaefR9YXfhBd+WE tAyF+1OLQMhD7BwzrkGzRyf1Kxp01RzOPOFymywIL1QX6Sah8Nm0QQr1Y2YvAKiyl9YD0h7H9oEO okWsWv13H/nxMDfDBmsFhJY0gpgwc16BZEZh63KezWEUUigBxkTZfRa5v0rmBBWeauKnXXVMjUW8 ZIq1Kd6RyBaqlqY20/eikc2LcJr+ueOFUxlQaOeZ9IeuGn5T7kwFquhVXMccaQhPIMZIiCz24Z9Y Wy50TUyuE6DFe/UUH9TdLZw7tzyem3KUZZ2gISJ6OAhy3dVKhI2s8lRUixj9s/SAZLMGryuKtmoM pGaWwz6MR6mP3i69Q+Z4v0+9pRHf5qYoraZJr7ii+8e5TkEVlQ9rvnbtZAPlvaaQq6wITzvaYzO9 ut39MLDu86dikeAf++5NvFvO9qeo1hoYV3vztvnvZgU0RytFBcEAmGCVDmaGjPFAllgK8v2h5CFV tfVgwyjzOlH1pkoaPopP1IihpI1E6Z2vb2rzhQ8wrMEwbyD+QWD6akjJBEmf0D/hbn9MV20dZ8uE kvsIxgN6qKgv8aVfSjw9jTIDWfOVB6CMl70Z52b2qvJXzqZA93ZnRCqEa5lV+AF9bLo0xc33tPsF KNDH2WFy0ug31qjrx9vykrFLqwdi+2UBoQeUZMt3ONq4+fd74i7SIZIYRIFnbM0nHXt3ua8yuuS1 W9pVUUL4O9BJdKEhnQgpFXTgH0APAMoLXXyTM6xTQdbRDSy5Yg7oRRaT0YUKdW4Dv7JNKxbIKKQy 5/e0X7ESD0Y8/gfl2cHFTzOIQolr13/h7hsJBHGg+gJlKQ89Q173EdJWAu1Y1dApLcfuJME6C+MJ dlXXzN9YmL9CKr0Y3IyO92BDv6JP84fouvp5Eu6F5l5V9XwOGffA+Ot/NKIeCAUEWPkQ9RuoFwQi ToFcO6jRYctPjC1jBV2e7byMqV7KKrOALp9GXtzzbBkqOALUUFQFL8fXb/g5SPkD/ko8yxW1KQZp 6W9vt3WXBPBJCWuyhAL6nMtps2KLqcwJmQhJbP9UQKTTrnwUWvEwt2fD6cBhQzEIBMONbTDtvcqM ysh2V2kuYr+tb/nMEG7OlKF74EdvzokCRUXxjGRisf6VUBSONjh8E8eS48Ohux24QXKTy3Owqkmw uQ1UFPgE+gFglv0+AlPffo/nC+aAB1bs3n5EbE486TMqnWOkyto36w+xKd3PY/MJpN8BTvdYA2Cr eVUt54sF6Za7YmIkXel6K2pTu5vbAL5OmW+ZDZG2b/L5P4b246ju7zZ4OxneZL/F0HEFV9RyVak/ oA+QRMImo1vD2PhIkd9hlVjuItRWyWtjHnvl+LnNXUgD3Fy6A0Ol284i1WW+PuA2i9Nl1MiU3w+M nreORmKh8phjuIFg5WvFu2H7pWzpU5NCWQ8v9htuLffq2f7m3JZfdVHMboSLGiBS4OGEcqQbK36H r+0AibcKtfVKMIJPxoQIseD/lJV9sBvYMecGRWdlSxWD8V1l8JHpo/K+p6IQt2BqLhMVVopf82z9 6woWQ5+DqWirdFxYFQX7MnEXWQgqgEX+7TURj27Y88toA4P3wtLFFbdWHMgBK1w7KmER+VWvar75 byXebzRmQUP6CI6BR7Jr5rcLVSqimUjiv5cnGUwMnjCsv11oWASOHWNM/Pp2yDkdjpLBDOCtvgJm Vpaul2eWf583Rg0QusW5XIrOsnf1gumnPI4aIoq7EaLVo+NOQTWL+u6f2JsY9zASCnZgQXVMgp5m b7NCxZKnFnBo4J24txVmWEtSE9YHUaQ8oiP6YFPbZfGi9k8L6mwb0QNMO06YOp4DjRJsEUmoLu9l MZX3vYElBPgUMmDuCgNU2Hm92sM3WvT/qLp6UDCygj9IhQgJNRA+lQZomRJxqOVhrhIvdANhMyh5 FaQXD9VhyVBpEVD+XtMrYs4m3wahLJLO8i+EgoOCrv6d42wwlL/mCFBwr5TtF2zpm+/BnmkXhoCY wIsj8Q4b0tzj/EZo7ittpkus4tTxBtW1W5QQkdTTebdl+5cwREmWmgta9BmoS396d+rj3eycQp0/ l6sfgfUEaMmiK9leUIiWue/OPfwR/sMIGvNP+SR7tcQBl2/IsMSwqCuOKdW/uyvZiCLF0RKCa3q1 IdJCgfPzWk3dmBsYbyPS4qb0SNhWkU+VqsRA7C4Mlfppn/O8IMLKC/0r0c4Ktndz5DKYj/gdRMGq 2DCxafjkNPDObHfkasyoSkIFSOpMfaJROgVbfy+LLe/A4dCdjCQG/b2gRmn0ZVte3BOIuMsVbfXm tzkRqRlKLva7pmQ6f0QAwfeNwu5Y1+AFChb+cOiOMeN1V6UySGAosMWrpB3YvbhGVoOa1S0zpMt6 iKxjA0hCQ3XsNfpfRttyf1qYgFGadk6Ss4DQyamEtfQOeXe+56xzUKL86lIECMpHzDkGb8BZM8LO 6JDWY0EOr97JZm8/BdUxV28rpAhkpSztvph3rooqzrHHaS0NsvmRYzcn8INX5mmKR/gr4tQOAVfP r0q6iHvLWJAQ4l02ZO3z4Q4p5gRwwpSI9rnHFdxLxd0AStt2CpRHpI8htJawqvUkxoXMeqFFIWRe 5NfhrkWtVWeAiZmE2vQTDMmiLikJM+MwJq+gnddr+HR7QffbsXMzuZVHzFpnKvzpw2+lqgOKib5j TrMQMSxwx9cz/Sm5/ZLTHns3w3XsqP7Y6egpkz9KhxwM6pCPVmuhg/McrYBnDQFeJxDVvSjH0azm FGF58wFN6NQppcdSq0bMZCxHqrBctx39RRJolR4pca/IC26GENKQJunCet2gLrC+u8ONKcprQRix gLniOYMWUbEwruihm5THi3UECffvcus+CoCuir2EhxfiM+ujzcZOJ7afPV9GjZY6bLGm/vsnRQyL LriZlCSlHcExuU+QLJi0sKCprKK7OoY7AKlqoLmJQyrF0gXuLgzFssNz4FfhLuvHj8YKi3cdHwMx 3mcnOeS19SyY+IT1LxYPLS2vJzE39Oyz0MEe9aRXNb2iTLkSZxAtMBi6t3BppgiAQCDxsIQ/rHlI xHba3GfCcK7wjAIRKe4FYziHzccrh/uA2JguE5NOzshb0nKUGO31QvOWIjkE+Rk7xgVGVbfTvqfN PzUwg4XYTTL3oH4h3ug2yD5Jz8q5x/eKqhayEsYl3o5aVCNwRY6yUbbOxkPuibmObaep51huAu7y dQADmv1Mk07AF128ce2kSEKMJ+agUXBvGB0eC24v0lpJq05YviMN2cXEoaHbaCAoGGYdI+V0RXl4 yXJ8ZCarjHv2pDY7btGJFEOUJtvi9z4Ux7MpnzP5br9N54yNjDylSnRjrktotH3VTAq92aBbyP1u NZVblem/OuEoog9NMPXgUw/KyOpIFjw/kDpbOjgaSral28W4ltTfX4RT7ynGdSL+PXDutM0fEOrk WAqfTgty1qbZWH9/DLyuOK4hw7rutElrnyGbCp7nZ8Qe9Ql71Q+f155aTZcyQPpYhlBxFKotR2LM 2b/XoMgS0t8DYUc4SxgYmTB3Jmk5vKVaRltkEHXV5NQjA1Kt2DxubofhsZnavMusKQcimqa/cDsk 4n/p6xnRZ0/3/hbT3NCZPjnzsIlwEqvHTj4KEMAYd9DUZ8PuEJYlQlMEhJybU3zcrpimztyF2E7y UhIWXns8TnYGsSSgX3hYKFkU5fQWCckctviskd8f170wUClfm0UMxvGqU6PZLcVlIBeTVp7wsgYE j/KOhc6/L4Nl7L+FNmeOCDICOsrnapjBqMrGOLXTP/ISG2bn5FAN5P6gIl9t8v+J3fZofk9S3He/ bzAZhf1Ek6lCImn3VWyURukVrb8I8N4aZQrxZGR33/JMXGZIqEEO734FUUEFbjcwK5XGRpPBmbQn 5uqnUHt/A8TgwgjzYjr4+nsrfQREFo/hj5Gvh9RYv2a60WbW4qVzQF71pQMOPzdE98cKLXfvP5X5 dAuS6jz/Poya4ejKAPiMW2I0HFBmN+BssrZ55nM2Sxi8BZaeZHilsFpQesAaJ/wvE3/J5yUKnwTC D8TFf+QYNGT+koSKqwD8DgkAmix3aqG0qjAo4B5NzyXJW+siSCZqdvee6GGUiZWzGROouJNuP5UE QJuOo623WaqkDBZG0/veQKWww6ZmmoChYG9QKXbAK8MsIGAEXGV89jxFC36/AasJ2MYKv7mMU8GR IJWgfoIVgzTmFPcW3oc8xZzG2kx96YXb9Toq8DfYwk7tlQMaSxLRv3jasondlQoA+zI2Qp2JK5Q1 rWsbflvYr5F2J0u1dtOqXPYKrAS5EcEAUNnp6KO9OU/ZRi8hjzls2wZXHT1J/MVBEUpR+/4O/dPr DjNLsQnu7wQvPbNzexSAEZwfnJg9QNULx3/DtyR/WLzeEwK5J/WkrmIhW/PjncV9F0gT/oCqhaIL b0AMlEsGgY0Nm2X6MFhb3YghYXw5pSoZL0G3Kkyf50v/SVVGYl+0DpaJM6uF8KIND02k4uaVPlsm t+ckDjPRu3q2Ni7JXP4exGpqgN3CwNMNRjW/cYKmCTQSyA7IqsHhInxoQT78GY5r/6i3AP2WeiAu fV98+JdZ/FldqDO0vPuEXhXWkavG9pldiZN1f9a8LarqWAXoG16/b7Qz+gPN/zUNbN8AQY2G/0H1 PaVXvslmmlSlJvTK299bUR1yLif0+VePz8vyhl8YhszxG6USlurgu5P6i10qjK48zFxyn4AtbXGu ZXyMDATm3TC0SQBhdfUCa7j0s/VICI/ZkdZEdMYdLVDQC2Ob6Nj1ddkRGNaFLproDLZVTCOVv7Fx PlcdSGxOQG9SneuHdcrVMGYjKbSHeeeb3M33v+6q1oa6Mn60YLSrieGGNZSzNano7ep+eN9n6HDK nCkT/2kpxuyoL6ukUBE2qslmjsSOggG8wVSQXO3xU+2B1wnF8EBCOjQmaJc2VKNQKz0+EwCq4Hby O6Zj/ucJ1QreBRfY1BLEHrcxA/mcyds+tD3FmX/5T6I7vnviKrCa8uXIQ3qvIMztX6rkQUf0CqGc Y394o6ABtwJo/8Q/jW0ILXHnGx+yAJHUT/0O4JU42ar56cFBUNFT0M9ZR0h4kfq/WcdDngkiQ3Jw Iq92asmGZ6QjJeUxYdIaKaIg4RPv+Aa9x0jzKnpf5NQ3bzIVQ7D3g+to3Qiz023HyiQa/viY6Qqe xgZOtD+3j44j/7rARVl+g/+kPAOReZ3cdJOxZFMwgSD8/TNe8ZgS/kFSqt1IIJ+/Eno6t7cRmzk+ JgWnz7xwJwprVPDIDKLdMdyZ/LzUhbvoqK0vSZNZTA76EAr43FIPsEUbFHBzKL9Mf6xu9tXvSg6D 3RY5C7HWmYoqC3QlL4fzLvf4pKq+/OoN+08Ie2SGc8YZaP9mA6K+HGLrbcoppQEsAYY2FLIKtj/B gHal4C0UlWIjjttwNPVkE9uMcaXiXbnJqQQLIcp/X/SkzSQdRwTrVajxDkpZqwFymoVUWmTDKBCI C8wbGChzxB90VVoozG73f9yrxmDmPZguT8XOAHOA2ibjAn2IlQ3btIBXVJS1o6qoaMstk/zGFPM6 VbmU+d6hukf6Y2yyhWN7Ql8sL/AyKPWbTowUYyxwYzOgpilMJNt51ujW7QvurP5lSLisyaDhG11t HDJXwdMw0Ms37PX1/YXYoYmA+p8RdPpH/FS9j5jvHPr+NmlZ8yfjMBTwRtGqXhAov+fsShjBiEnV Zih/N+Ulh4Xz/zpzhED/pZR5xZgiPNprwOpBeugApmhJNNwQefGENMnT23WMPJFCYtrixwAIUF1M 9+93YrSf9Vrd7CQawrxBJhcRYo5/QHhqNVGEUrvHFo8GRipsndhLsjgO262ne46lva/6czHiSpVR dmuRIFGXFg/9jkdAF7aD1omXVLafXw3uixVOiUsPmJy0MlfLB6ncyr0w/Gu/klIM9M7j5JH72OxO 41Qy5e4/NpIL/9jOz6wfMEMyysfxlPRaVhN9JC00jf5dITB+5B3bhuVrVJChNaQkcjkQ6hhc6Wkh qomO2rlQLTq0O8554C0UEzLzfSo3vlL41egScKP0TT2pD4TVnHQUBzGVheVnJrc55g27TtGFg7HB P5AXV8A+0hcx1U5rGqpkPprtMChYpAYwekrSfPK2w0w5Md7kli8YmxPQlNJIh1QkPQKSbBd5B/XJ S0WB9AeNrgRG52CimZJ+0TYI7O9P7lFfHBYUZKGdXpvap3Y32MBBtVHGJrj7bn7b9sW/OPljuPi0 dZ9LDLmCQvIvzoYHV4IVnJ1ORRncGqqHYcDCAwbmCn+u89QQwaISLEx7tJWw9gS1QxTuycipesHJ LVE5iyBUxGwFRYCZcMt8y+oHW4hBjy3q8nYxaDVsvRU03YVtEUDR/+kBnjLccrcaZS0uxPid/ES1 SHORfPenps1oKtQGvMT1GDlekqo1BI6UxJOOxy7iNlI3yMeIauCparD8zsUM+dBzG4yNDXV5vhlX 85/VSIOx1OErwRe+9wkQcIPcnw+ArJL3fIJkYCWmGwXuU3O/9fVkvjhzobdsoX1BU6ai/crfLguf h1iHDPnb0God7khCCIdCUZHx40ercUbmoF3E+0XW80bH58Fx/PeagrsakASua+jNwlJQFVdlJY2a yXnwjYIUBndQQwsMZgo5iJT6Kp+jkmYq7mQKUas2cnlg4JjqkLkQtL+CyLQ1okNB93Cn2P3i9vdE MjsjdFxTRaNKJ8lnQAF+PkXDpWCHTbGH123dqfFVE9e3LSXDSe8pYzgo4uK218qB2Ei2KVTEp5B9 UltcWp6UZVEUV+1rdJ7Ql/MaTja5aPDjhgLynjHMa7MlHoj4/Xh6kpWIJTdpsT3biKB20/LZ+BrD PmS5EMgmb5KObGBYj+FRCwkxRc5+9T74HjhyCmt/Vt+1lVFotOT2X7jXgKj+x6Y2sLUIYWfV2Xke GLV7bcbQl0hOf7vqdTV92fly45w9NS3yxNtmHbLfK3ELU14svAESQSRwQrNW4HBWxON+KNuriHkf Cvc1ZNST53JqlZHQo/ialTgjtyW6Lh7rEQCikiLcOEel2OiJJNWbCnS/VuZG07T2v/S3Mt3xJ/mA 88rF674E/z6+MJiOwTfbRICdlv29VgrsruTAZB2jJ+d3rNNBBJGqtxy+zitct3UbKLihCKX0C8HN PfzMuKvO49WmwURJ/G7j2bs7+GZr1Kk5qvJ2itr5GvgERpfXwAnosxEkcY8bqAVNR6fbiAabzbYm hqppWXUi46jtD2VlNwQkFAlrYfkwx1P/m/cdi2eDgFFyOdWuMv6A6ziK0F1s+A+4TzRUeEthzL8K AC4W21JRJcTfDXDSrJzpH4xhLhFSHoOebeJESsI+8Uj+t3/1sRZprvGtgUD4aoOksBIhpFA782qS dSkFQwpIL4JSshIhpRFdI4yf1fU1EQlxyzRWElije5lt/sJtEvI6hkHxdMTVmyiZdp6qPNEaBa+n SASkZQPtOj9uzsiS5yKSkp7fMVQnx0k02kuDUPSbX+d2rPqMmY6dhJ5t0uuUTKxZqOhu7dv9Ue/2 izJG1x3RkFXtC6n83rCoWFGQ7bWyANOT0yapbw+zVtCy2mvj6SGDdW+fYmuR0qh2bRCfP9xuvcX5 96uBvU7WGuoXUs5wuBfiQw/UR7hKlagKFJmQPicQNQpUa/5CHuGV8WK/D6aQDHt9s+z+0CEkO32W K/5pAoJEXwKKxt4zzA/whISS1B8z+FCkQxGWYOtqxIw/hG+JgVffevtJzEWWCPl/rZPgY3rofNQF ze8AlMwww/L8l3VHLoDwNvNUvm/D6pK64I++Pqd2zy997NfngWZBhZN0eDxK9HCYDtUhznfHd5Mi jScJ8bMUFcpZ3UfsJJPOlMo2vuTmUWa0ne2bjM2/E6PkhgZe8eY8qrr38VUDkUB428+BY16mhPmq nDTGpDl1eNVdi8i32R840jyAT8NPnc5aYbTACROf7kRQBVZKaaRKFF92bV8cPaV3yzCKII4zURUN Y1ClzPYdEuj4Lkufapl9AlMhYpigL5mlHDjuCwD5mzs3GzSRFePM1ScfWdhyGUBWgQ42XefwdFnC Q7mVOo5rqM2/WEODzRX6vbQHw6v3PMAluTmv4nX3Jlka7gVOpSod1tBzRzzHGx2IlydQ/xT53Wvf Ri4BDRYWjzXQyJjFM2AD56O8oUERsm9GLTrlEVzd1Qp8NQVbnQAjcAkTCQWQrkLjVUS5hLnfKG3y EJvpb8Zxxn5zDTQlp+/VBM/+e+LEaU/GhtCF7+YavYtJdKZUIZAZSVfxLQ2N+Sh545KD2hcWO+SZ rLDSy8qZrhuVdNyB+ZyFeotvCHzXZM+lUFBZ9F0Wyw6dUX6TLFWpL6Om+hKhjPZja9bkg+SknvI7 33qfUMVEeRbqUjwlgcwC8U9hD8bRg6Mz1yM7De156OeB5WVn1e2P1DU5IKPcYzZdyu1iUMC4OFGh qfAuxCWSIDK70T7hmpGuSpzwJLvMB5vLAJ7833tGZbrEXbuVRCLsv2WcxgotQ+JaTQ9+PRIiUgUz AuSU7ZJzEHxYeNyBSsSkpavHivX7+KkBQpVYv58inWO+vsvnPPZqwrv8XW+aVHUKelLvNxXGbZhD GgZrWGzsRkEUzDYxKrh1kXQkN+izRKRCe4Sxzz7haNbyu9temOoNnMdqQZEgEY4oOm3N/yVUAJER tuX3NW69q0fUp9KNQLxy0bhamaVNICQMU3qAGPffuM80OzRpVYhOPIUzaGOdN/6tVhBR3W1yRj4g USvXaJmhRfZQ3E6UM81xY+8ROO/LFfn4van/3gpcfGXSTUEXPo2gKxi6V09HlSEAnZw8tXlCalO0 tjfxyugzcy3b3OPp1NNDVYoMUHPUhj7ajFwBSiHRGugwPbn3Lr2AsOhUEvNsvjuzV+PIQvfm0BW9 YHvnh/ItP2c8FnJkQCRm2h8sfpjQbna0X1D9/sQ0eXL+43yAers2wsCyb4W+k0nLloLUJbks2DmT PaeDyv24Ax2+X6GoZxkzOUQ+bgJhDgKZ1SfCaEJwkvKaKHtP+WaTyli1EH05a2rGf48GIU20nwo4 EAEHERobj6sgzcoZNXcf7p0wkcEX0SHksKM1zXJSbLy47xXZH8Nqk5h9eKTEbSxcR9ywPinsEGyd a38lHp5eSq8aXzTzLGd7dYd3TrJ5o5Ubcz0x7VSWLdRP3aj8J4givpj91LY0v2+brgXVqHvdyuHz JeZ4ovyyWyDjt5KjPCrPfPRIhNLyibBb7C5nIcVT2nNA1dFF5K31Ds38DZdUD2TtjLHwRoI2cZuf yBGS3M+UklRdFB2tFzi/BvUtioSb9MB0VAcNypiwSimqVWa4AzJHM8R41km2OxUAz+DEekS5qJwJ VVfEvI1HoKpVJ2mwAUjKR2nqGQ3rb2mg4NB/Lp19VS13JosuUdvaFemf8IwWjlhcF9XwhMQftoWT Mh2E2m4idMbJ7NrlF6j2ihduAmU2T/XgBbCGOOUUJlqP+oBAlgiLilYOc8xzYgLhmIJPikFzGfWP c/Y2xrFMduUIpF/d44AOUWpXwdRXt0+LRk8GC5GIQjXG2U+pStenFCn2VSoJk8N3NGOoQarc6jKp ysyN8P3ks1k37HITCSSGP+XniyrHFq9rhup2zgjpbiL9SAv8BoyDjFcJ2QwkE0mbamNfsL/yxAn4 1m29c/VK8Y+BhHSpFF5u6zS5+FJPWqBHQoTgGDwx0XjLvQOv3K9IMlUVEM/4Tww2pVonpdeMIiD+ 9ZkbhxKAqd2h3j1AE9H20sLE9Y/JjWlQxePioOLSOz6xjPPn2SzK62QQsZklf/HIVxFIWS1Ye8e7 AjyaFNxpP9efqpsvMDVcvvo8Gm2HYoRUVRnE410ymBla7b/R+fW4ZYRCyoGwJLW2uxiLJexM+yV3 Q7MPD2UUjpv2kCLG5kMrys6egDvoVlPV+LwE2d9JHe3J8EtbAh95LBxa/uCdAtELTeWqzrHKF+EP 8P+hgfHHYJ/PxkWnQtbO8SMIiSdAaWwrKl2JxdTosvNmWn//prJ0zqCBfiFUHWNPDtxTkgEv5CAk TCWHzzEJDg8fQZtwqfpZaQOHwMc1Lf4bMmwVM9VexS9V11kuroXXpWkYbYTv7Id1FZ6BsyBNEeMk 9jhc+JQE/okWZxvcXQE6x1gZqierJp2g3fOcwoHoC/5ODwfFpVaeBhVddrUK48Ts534sHX7ZkmQk zSivfchysCZLdkmW0IGMDGJXrkinrKIRWDIJrIYQFO2qeeiplR/6xt5r6aK6TBSZdQZWUK4ROUui nfxp2O3GjbPhvJca4mePdJshf/6qHPmJDtR3On6RcXJ7wKW+IyMj1i7wCIAAMVUXsIrnVsMdzamB JKKJGuNHQ9eMP3+tIRIijayY1ivVmyt4ekz+L+P2gRZ//1Qq9nkeFaMW+6pi+MV5XnCqk8c7sdvA tX1tcRnZJIEeGg9gwhnbwaEQUD2GNcQ4h9jv1/rn6zO4OJsnjV4MSnXGFUw773crVx8b6J8EQQ++ 5f80SXXQMZneFJ5LWzzgjb4AloESFtUKB4fROi5ulew/IINqjKwwiB7UZwpIR/gswOzZpDZNwPT0 XxHXTq68uH2Ii5H2V2u1czzF4OT1VIzsrzrl71VhS+meiwYtaLqi/5WQFPjh3ELJx+D7Wy8dy7Rn LoHFtkDY5pkA8docwBLRUFT1fcjiLgyL3rrCaAOJYV2dbejKJR6KhBt/tPPQrzN9gJTsYUwgAQLk A9pabADEBboV/uVZ9H+OFA9C3zzy6sWCXwaiZIe2hrXGhzAc50gJM6of9oiEBZeFMmQUhFBJWOyf zoGf+IfIFF04hThUNOyCcC1uPFhsrJSDTHrubdKOQEH7EAK/6D6XPHAutDocxbVcz9b313h0Le+c UNjo1NrxBntvWTsPh3wVYXf7XPEasw5C7c8MzGLMy8y34cAVTmVq4KTX1ctQBMsm1aCEpzNRpqPH LvHKtmka2vcA3nfqcLKMN/Wo+1WVaFcPCDhYNp2R0K2n6PwJ0b7tx6bnnfM16J1sGBTQJ8DprJTD wSl+4HvMeCKAF3k3HT5VVROB7Ez5Lu29NLavR4/JL3NeS/sofBtbf+FrQSDZsWyXrfPwDiRkm5VC 4CRXv6YHIQgyWT0I8ZQqrmdrFuf+JzWuhk4xc/ZIkCRfIH+7kS/DQcaibG5yk6/mQYzCKEpkrfJi Gs8tgL8xDibzZyhh0pYoeff3jqRWuX9fDlrZefQTABSrPsl6vILJhlW0J8BhKvmUmRElg/SF/vJP 6hVeQq95qL5CivltevY7xwVubnQJx2OYsYQ3qwiUbxQB/4mDOFKG1HyVb/K9abyUnsEmRegC0mOR mpBbhkkq8M7KZgjmCbdG9KOkMraminJ+khmPSpLcRn14ToTldFx2cmBtohSMKz3AVMFHrsC8o9Ad xPrr47hhfXIE60CFP4Zb7qknIg0h5+ulVjsIzY4oipvLpLe+pPj/9f1Ha3MwbH+H3qsZNRs5Yg4O mPzFW17VlRklTBzWmk2fX9dIEf5Ou8Ht/TJ9rEFD/UyoQCFo4x2nKJO3G4fH1iiCHQWyN9hPPrkF Cmh2TiOuSFgbjDfF6XUFgfdVTs3bE0IyJNrtYFB9kBienLDw0ZRIPA3ZotUcCscN5gG/XBTTSGVi ohwsx/mM2Noh1kJSpd+c6ZCOan56MEiekuKuhtCl8c9adO2t559LK45ibqLmFtad5Cw13dKGHQkp b9kI0C5hFUKvfGI/jPBN0XNEdUR4A2R1RM48U3c/hWWPGoyndq4E3mzIMITcYgf/qdrlCD0C15gy /MaE1U2jJ3cdDJ3g/4ka1JUGi0p7K1RjjUqT7Qwn0fb16IyWprRLhAz0Uf4vfT3D9m9xxCzKSTfO uHmHzAUjolKU8B30539grnVWy6fm2m1dsNbFTMDdOvRsQY2GfaX05h1iO0lq4VTDm2xFLPtgsd9Z m/abULTHZb9Pm4mOI+u5uqbX2qB+BCZjcVb8+lS/tv5gJDCHpxfPvKXbQsFL7EiEBqR33qZAQLe9 BmqIBEZTjv8EiAm3jU3eBZjcDn9zBktZ/LjfDKiQv2PgzmsOavvZiST54uj4v4hybJltqWOVyZ8C 04bJ7dc9a9XDK2uGWzXHgH9ctuBWhNESRor5Mix0k7lswGG0g5QAKIW4sh+sOC/UXEPRJle7+HVo 3vspdl4cwnZh/CjFuC1nCsHNpXQw4nSiZxQMIP/ZuR8Rp/WF25o3/CWtFqKl8/mfCuiqEMsZXa+T MIv8xGx6C1UEGlwks3s8mxYyvX9xhVu0kcqu9cg9tLPHwTJWRUqKMKraazp4JY1vBwbVJJU5HaJy P4ja8dL/ZsA0r+mWjJyWVHbVonfhcyFjOLNZXBeqp3fFw20Krunj715Z89BrJvSykF09YmQkK8A+ 30iyHSNHFHqULapw1PwTtlxA32oHTAvE0k2W7brOQKeE7P97tnKlk7EA9cAHOIX0GnNnvVcN77td LmeAlr+UzkrHcCQm5EmWdEf7/7COmevvzNKy8cLmD6HWz33OAsZLjeYRZQCgL0GsCXPs6ocxhws5 Ce7auXPrPeaffXahf4P3yNx7iRowlW7gJa2l825hbu9mFm7wORa0Eot82XaxQ/BwSwMAAQbghWLd 9uxwYTnyBVE57zAKo/SuvhowldI4c6tqxFxpXKtrmLSsBsERGmwqK45oW3OlrvIZ98EztsmDVAoR UGYHq13WD4lfudPb06qHYShmLRADPL7s90mTM+LA2AIBeOKeqDVUc7nVcIFdk5jucfGwFWvYazEQ tfq4WA1FVAYdjx1YcU81VSPmPDFiOFdnJtDZMbYhlp5j0qIoVjMSMExQc8/P9hFo3RHv7YTkty1a JjngGu/cXxV8kNnHRpTeftTVPWl+aH2zWexUf5Z9OZmEJWKLW8rlWA4OLKv/OR8bQ95ywEXFwPnC T3ETRTuiEtjhjw8gSbjsuYlbFH8TS2gEq06LkyhkKEOdsEG1WxUQ1PnWJXnqLFoQkZ28RzY4y2ak 3Fm1qxWlkbMl63bpL1ojlJPX49PdL3dIFVN5vNgPLT33QiwiJIib1hFNVsfxCPkre56YRkZCO0Qp oqhK18HMxGVVtnItqB8QrJQiyeT2DdZEUWeGiAS8MHD1Ai2Ks6HwUUHWghCjDDXtd/UC/cA1AFsI SKy6ihu1JOZYoQUfZWd5As+FWmIvy4pNG+ZDYAVkgV2cH1uJIa7GIvgTn14WGbpAz4wRKbWo+qCS Qn/bBzVgNGLfrwuLH6S1wmR2QQ0KDDrN6KVleC4ZBhP04vqlMPfcAamW7AGKvP7s/3awKMHou39p rMi+TMKoodyNlJCrzxe7dLG8bujs6UwZTMTLrGAi3Nq2hCFwgXAN/mi2hQyynd0M0DVyDNM7bcXz hdoFa8npTDA81moIfjuSq64/Oxxfek0FWn7vWc/QGTXndzWOAIGbEKLy2jAy3Gql7D6u04qvHiOb WsznnSeuDmlz8vZAS1cAfecfPt1qI5ZEu6ZBgGXRGG0C75kFTRhmlbxCOUqfp7/t/8HRzQpF9h1Y UvkRrzGdR8KsCfqNe+Ft90yThErVwjUanCrRFBkcD/y5MPgxYr3yyeg4PmJP5MsM0g7LnG9asff9 PY+RmhGEoy7KJU3+NwOuxvy0bkX+iVSnhT5FJ+qgL6ULmPcg3tNJE+Q6pr+E5xa6nUG5prjpaq0V nMn3Wg1O66z/dFAxnyKqp0TAA8pmfgvrD3JCf7U/xtPJZv/WJZ5P54zPO3oIQx+wz2YGdgKVX8Jw DaxzsLR1W4nLNGRBV8uhC2Bbza8Zl5e+tvXWuBHkvwWne27cfVOdlea9gEqO2I9Sex4u+qGnDP1X F0Al6D6ULxC5bRbUj9RPbPbhVeYqhzqbqHk00Y0/j4tllXv35sa0s9nxeLLmzXyVAYP4mpFCf7af olw0w5+yLp3ft+a5CQ663d5rk70u8irGoLIgwR1O1p6YEJF1U16yf1SGyNuyl0ZotbAIvvnoEmYD NNSf/qB5jhJjpG8v2UjVQmrObPQjh4DhenEQgJoA2Wq3TgI6L2a5wdtB947CO4zzoMqvg2QV8Y2e 7fLk4DoK5Mb5M+2JCBAO73PLpDw10btwLxKA2kz261dvh6r7fF6EryRhB6z96zpaczvzqZfbBsBu gg2hbhIHF5IG2kS/8+w73hqpw27MCJw+8I9yOMUCiWygb+pEXTR9Aw/ZZR5t83PjqswJgg6CGYha JTZizD1wg6NeWhFq3SphkTsI3rPQ9wJiFeGiS+LrU0hbrhmKgnqLCQJyofk7xyHa5BnhHDNgca6Z lWVSduLppN3D1Y02FIQCC8RB0FjELBz246y+qunXlhHoFd1/5X723uoD5bTeaa1mAhBzJgQkA1xl aEs7oPoOUsn0NQa23OTzmVJg+kRZ9ggLbLaIWHZLlLQv1eTwvwdBOMMiuSYsCeww9hfnzLTsPpfE AUp9CWDT013/yaqK90h2Qc2hj6VUF70MmVmhCOiSnNhEBGm8cSqPzBQigFlEgr5Iubv4zyuQGaaR oeqnCZQsmW5yaipooVIYNT3fT8oWJiztzbHBYgQK9xzpLGFmoFYziedjhg+Th52RmV0I8HJ+DDJO gJ3oK2omwAItotIqAIYh0DTjEF12w2kwXo6FgiaryVVyQfFfKUHeknU+6bJAdZxroZASVJ98rjrA jRuN6fS0bhcCUqnUeZRpdq/rherkvCrdnrGQTgdZ47s/eCtnzmQZLPpeQMgXnoM8ZbBIBKPQ6A3z 9HpmDsESBLVn5eMOWc9w3fXui/6woYsl2vtrs6GU1t0F+uj7zxk+1CnnFweMApxHTdQ6QLdvWGR3 tpR1tV76EiR18MEwQvW2qWm2Cr8lTDHB/Db2toIO/D4lytyRQs8ZzPHnjWHudqR+sOPcD9PThWV3 AIm1K8lxWw88CVXSLqfeMg5nbLRsLdnn8z9YlHgXsTQkCnm0sTJFiFLazKxvgJ6uYhOLnRVxYWEZ p/vjidOa2/+D46sq8GNYJQwNSIkJXPOd2XnoaKuOCGQOZMgieO8akx/MtnbUPVi+u+hDZqUCke4X Eo0ZT9+0RkMdfxz+NciZfkZ7Bsp4dBzbjfQgTc+oCeHZE5g6omQnjGP2q3g+F3yogmdtz8SS35Vn XlmIxCDL5qNDQ9GoTyYiFqzn7HNZgc3LdNrbNDyodNBAKa50p4h1eE+nFR9+OzlAtzddejprSG7K b86vEE0zfsH0YBgK3xVh/cWEEl2pSju2rqn3rtApoqJfq8W0Rl3oBhq5J6qlJV/gEf/Zr5aA2rK3 Qm9SW9VcRPtzer/wp5HFSrlf18Zcr9+WuNIgvttfs3H83S/wOSvVvrX+zBHq1PO4U919jra2HG2w AwEapuC328ZEBQhw4q/5PHglYCJY5H2BiUv3m+oYH5y+4EuqEjwwD+VENEw95Z1iHOMbRRh9O5LS aCzMcna/o33hEUFKRr/1nqLU9JQj4ObJG7yEYZEDrWAmhxXHGTDxnQaxs0T8rhIqs/VbJHiadZ82 MdrK04BatoY8N/klrMN7k3oFaio9N+gJHD/qdl9HL200s++JXcLJElrWjCahfv9R0NPAQcmFx6eu fPQKfP0yaTH0b5kQJK2YDHOWwwUlVO7c6HK3XpvGSdmKm0TaVT8RH0hhDs3YFGLeb8sPM2CG/2ha qAZh4LOtbfcwdy8OrG1RcmkutUAPwj1ePsBWKC66msHHNtCssRk/sbNxVFTIihRhrhAm/6hpe1c3 AlFqv2pWQkuLpYSOctu/yOPcU8GEA9pKC94beCPKBi0dOpXmEW4e/+BYiyutAUhuCxUHyUdF3B+P ak59FiwT/coSup2Sywr34MKZsfnpmuT9oLQVuJpMmLXSBv8mp4Rivn9ka7i83wX8ulCdUlfnLnZ1 xqoCGfZwAamw9IM6XRZp/9tC/CQVH93Es6G0Nv7KKDn8Wx9imp2JQDcl/D8hqbyUdM/z1lT0hi4/ MxQQtq4swlnGzM7C7T3xfxB8AiS3ZU4reU8MCdCZWtjccsLxxF0Tm7LipDPKDey9uK6tV/786j4x VPIa47T9zwDmVQR2dc6zHcjy3Bs4hxkv4yUX7FEdKxWMHG6Qk9z6ltfZnAoFETkdONneq4Iuw1zt 9aVng9OTa4ymJuQ2hsQiS5F4161FHNR/oLvIETtFwvt2F3TxyidPfQW/drrlZDggHu5qyS94L4W9 eCpJZmYUhGViIGLRCFMw925kGrnw+5R0JNWL0KkoKVaK6aOjFLzsyl3PqSomwMvrs0FV5yT+uhoC GFaKnqWEQTpO8ra7uVAI/UQC/2DlAH/9SZQTNKg2a7KFQySp8aTKUyciyIRg4SapIDlJ/IQEwZLV 4Bw+U1wRtZrke84u9AvmLghEb5+ZJU616QwVKAAZJ56Uzy0LSY7gkJhaOLwfBxEwEA8B6ZMhi17T nG7yB22T4C5J4wFyRcnDKxaYXxFrOdvx6zVKWHiQVVyYs6iB9EkjN4Ox/yuClW1VcJjN469oQjZJ PU/dtpAtYVfPG5BnwU3J2w3y/opAbWExXQMgq4DsVBqEE6uiMOdc9N4VKOTo+vqMKt3zpscOsjiu 5D1+0VyN7dTZAjpYa+q1WYh4wT+eRfoTaJ28wQiwoOMAOR7DUO1rVWHjuwsf2WG9FvV09fQy+9BO s/DdhOaOuxx4+7DVACuc1FT34Sam7QyWqH9pSTtT45WXJoD/s1jSdj+iJ/N/JMNG+cOJABCQaFuK 3O/W7c+jNUm1ttXFRCZ5L+jG//aoEhl6cL5UnyS0Rlg85c6PJPXybb/vnn/DTZ2g6285QoTQ1xBn xrg1tdDnQau13h8u1cFVm0fC/el/hFKv5aczqBXnGYjgybg7VbWLGgqDjAGm8N7kO4AoDUJ4sE3M bOVNseafnE+hJdktJClVE760RCaT2RdowsS3GvtlMFmb8ZByz1u0aPoSi9bw11H3HveH5gflrHJA 6LmNEwabNRg4Z7JGic4+zMH1CrcTJX8RxI1RPgWpHGK6hQ1s+DnmGMnjJVRu6VGsjxIkBdqTQpvc eL4JPyfu+T3j5CnB7YfKM0ElzWz0mw/F3KWKgD6KsZmuIPnmT1Vc7d3zXfAIAwmii71pylcqMBwJ WQSFCWtv8cCez/KUiJCy98LbShYLRGyRz0OAWpTYO8rEsxcG5ZF47Ei/8X+CdZuQkfLpsxtW15wP oV4OIrVVkDtnDgYiqdFj444rBUd93WY8A8ytJbEnRkVpXD/L5bvht+IqPKf+0HRRPUzxlEBXhJmL R53KLGQJkfsS7s44KJxuqTmAoXtVEo9o8O4fbydtNegwP9bE5jgcW16deSEoxQJEhdUmgr+Q+8pM 1orS17CD0NkVya1uot0/LaNb8l+ek77G7NX9DHwbA2LadCDn7LONw+5GPGBsueZSVVwc5TxStJnh 2oujngNCVZIN17tnGxMv4fibxj6cWgwD8AaRulbFAfhbG8HR18vS80gdaH7w31dXXafOIhA5N73q kn9nz4VrIN9zSA+q/pw9OhL/jjxoQwzpF3V+5cMr8mx4ibp8HYeGsnR0fB2cnNkh8/55lclkx09t rdHuCIRJCMSx/w0kICTU2MhPd6O1agH9PRnqsA35gHn9VtZOreUQ3lmDj1nCVyapwfEDgt9KyDjW 2+wqCA6iw79QshcjnxyMXnGqdKJmFg3Wu50WetdbcQ97C3uDc+h3BX1HNDRgf39ncxbHiRH/vtM5 V3hIhTEsQLc4dgDUqP9sDyVZaDJoFPYwfqJRa0/9CmuBRMjhByrFD7LkdqXe0d9Bisla2rdm3jV9 TG+MnBJEZUA9aREBxSF3dpHn8aB02sfyo+fkybdeiY3l+oIKDCgYjAWcmx4uBh/4Cnw0+z8k7Pdd YOcq9j+zGq7DY4dJPsrK6mX3c7ADAQ/868qyiY/hXXFqbE4ODNUNVyN1dhibyR9JgiqagME8/w03 ACJTZkHO/Aj0LB2rCVSkLIdaEVr2eg6cVk5yDuCvrCrnWG2OpqjVglpJqnzlxm83QpR4GU4VfV9E biSRfTdSzu7hQ9A7xpD/nwZbOrikxfcHzkP5t8eanP9I5QGgryrjcdRZzWcetLPnbpJTJNbeZZ47 fPkuDUi2vlAAVe4REmUUu81gwnBeM7NxbUQZlokE3lh7di6WLNc9WCH5fdgwjmP8AMu96TEX/e24 5L4urqL+2ke42m0IoQbfF+SLIdxfHFZd15e32p6A8mU1KUwgbF88rX27OsfinCJzIb7RjALEoQ/d SEIAK9W+YtZo8RJcAzjjPjtB2NALZaJ3vjR90srO1MsdfsqBcC6RK9daIBBokxO3iMBVbiLzTN/2 BOi6vf5wRt19BRxp6lajPjzfBJdUY75Qjd4oxGMENhkGvuNj+sUePMndspae6ifZzXvNyqarsMaR 4c0CqNhmFyZ63m1JLCBR3DDp7K4ZZxrfOjk7teF1EwIRW1GlTlhJt6LZqVRWu3ze/fyhQAScz+l1 aGIgjTwKLeCgekSzmTyffCbfHYgS9hH2r/z0LEPqzQGrkKYgN5OKhsaqc0s3jprFLI2aMLdMO+QX hlcbdlheP/f2pwla1UbegIw3aLG2JDdQ1HVxtEMjb1sOsHJDVz9/jE0OnGL6rzNcKJLxKgfPB/zO Zom178H1QPAsWwpaowaHKYzFID5SD7dA53TorrvPD8PhGwdbUcglqL8sSKZjwS3zqVV0FBGsmeXU ZhAvN7TYz0qFNikt3wQlUjFO56fv/7PDpjkQizNivMjj5CYrSe6IUefW0F7AhLdCh/S0ewNpcnsW EFyri1MbmMN+uhTpB05+mbk7XuuUTQGbHqY+dVmOFDuFivGPuOk8vdvEA1yMcM4p7nq444vimuvM lZ/QdJv1snjEdowLSjUAd7NE22zQaSTovTibpXCYIt/zDuTDzFQzL+L197jsvdMs/yr/EMheWuts Keqpx0HVPeld3UMqz0qHiNHY/D8fIPz/BfOKLCsJPkQnNAzmVYvIuu/ND8H62VmLvTI+qFvdjfw9 GZltxw/am2CWvQS32v6exMevvfa9D1atiPWoUsZodv/0nvBt6e/fmqLdJXqlUeQ87hr+OFO519lM Yia9TIvq2j5YKOt/LmK5HgXY05e7MjDygAFXnUkFI8RvPx6E+OkJIrhof18X42cmK0dgt646JHd0 wsawW7C2VHpgE2y/58FdwTE/EOV4J9BVtiTnl9SwlLgF9ob1XdsP/lUqGR3TXyfSHfTU1oA+nbPQ J9/7DPIUtfViX5tk5Q+Y7n9t3rBVh0DX6Y7oDplK8WrU3CFaQBSLvirok96qJoK7Q4aGIkl7I+gG Qj+6QykfwrsA6bbebGbsiDOr5zSslcunTJiePTIJE2hjY7S6Mvudl79L5moGijpB+j5wAkfHE8oh bR6mPUkSOA1Uy6AV+8sNfdobnABAi960PgLjbfhtgRx3ALcuePfREZVPJaygDKJUHSDFPQUeK6QH PORjVAn4rxtomT1hMvHTaBU+jBJXPEUQL2wpGtB1vXju/rw3d3VYAAinfSxn3Wxy/B8HkiZEy7M2 x+TeIfcq5wN9r0R1LmTOLX/bdQopB3N04Rtjj0kXc5ExY+MoW6f/j4kayfunV7buqENcjRrxSsib N7f5h9dBVY21eWJH1PSrQtpUg8c3ErYpFVV2n3U14KRsE/FVf1Lk7uUOFxEpU33vISisRvCOcgGg ttW1Nz4XTxxgzkznSiKH4/tOt+N/rntAww7kvNpPyQTNWppw0b1J0XRYLZKqNqJ64KBpuUTpnKRk eeeBJ5TbU23ECTnkACbyXV/+soDzqwPrsgOXnSRRGhDmNuq8R7sA1KuehF5DFmBYoRsXeMwwEHEK ip64pdtQWibLQd6ATOSLuM2pAm/HKqTG7CBAMSIjW+Qb3ZMV88Bug8pWe7CKT+lLmgm7M7PyDXbO Ngzs4ncs3/xbk/p/rPMEIMeXAy+yxrqf/clmrSeq/sK5Mqf0r6preYBnQLbe1p1GPCnQQsqWXQvp s3LLfgKln+fds7MYmRDKK/8oQnXqqzlj29LYqLIY9b5/+3eblniu9cApGdy7k68XNJf+0ry/nCck Fl6/SQsGj+EpGru/Ic3D+llAS5M45v82raMD+HcvdhBP76SKq8FEibIuoXAjbkPfXn4HhBPa4eAr doAuVhMFlPJNZoZchXanmE6NwKz7L3DuBoY8kVuxzgykpZBxEHmltc5iHNSBV6Qcj16hBtLPJaoQ YKbXfJ9R/EUIU1U1rqIq6pUeF83Mioi6RCHm3vb0Uc7WaWthjhdiMpkEyfUjChsPYM6JW4IxHcQR gAaKZS1Lh9t4KoSeXiJtaLKAvlTiMeX9Ozs+4qSsdPH/Sbn7TKgqM8qACYlQ2JmPhgLapXy3oQAh /sQ2W6QQLQRV54uW+HxOGtK/XifeKtgnFHCTnzkSjUzn/GZrUjYVZvuTNUFuF1FowI3NRFV07svQ TSR0E7q9Zpd9eOA60pw1wEPmi7d69m5Q7uRMjP91Kbm5MxacxR1PqRBP402q7A0UAP9cKA7Evi4M sODSYw6H5RBQxWVeGIInf28B7DbqC2T3R9Fecw1F0rLNaF3175xv3VxozFzf+KHXzshKzJpUv9dn Xh+hv/rYLyrqOogbH0ehKvZDLXBcLrwFMmN+VBfh4EZRSsbC/xkrQBlWHXVPZGGwqcDNbMk/p0++ czP1lvw4GdPZhh3ykpmwqpTkgn3Q+oDRf+ha0ein6jqgaY+/nGt638li086tEWQLH0/w1HlbXk1U nlZwuIArtoIvpqBgnlF56tTsPKOZ+nyNXPdnYrApRt5tvJa6SCkf+Pmh9Q2QWrVopjBn2N90EBGw rOSSeV3fVxlbodn9mKEO4ZUoWo5/kkghf3MLG8poOfvaYP7qF5hdNIDrTbr25BnXVtleVnc+mAVS b3pWx8tQGSYpDOU/R/exttg0LJGHVJB243ZGIe+eVqaYKqtqYmqYO6qBvdQp8svHYAIJ4M+r5ph4 6hY+cG5ULUzYdCfj4o1BxZsNU1+fpzgY5Cl3zVzxcJBk9ApzkFP9RqNqS8YECaWtGHJ49GPFLkFj hKX0b/+7P7YTUT3nuqX3Ft35kFbbxnanygnxnyahB5xsgPksbvph0HtmGAAQOcvTNHsY5pciJ5CN +Gm4Ue/DQ/zb8v6LHPBWzROvBwNhT+7aAX9L1iPjPR75oy61SaNl7rSBiLwmR1I7AJZeLRcNH41Q JIGOZ+V0MB5UcKT9K4a1f2GVdtnXm7pkxbOjP30sVxc38BhaM6qU6Ff1iy3xqufsAcxVEm4vQyLJ zZ/X3OSquAuhP5WfgEFnCveGWcqWDlGeECmE3YCjLOjZtf5mqw2CswvYYrjPEPQJQ4wPVy0bRdCg kevcgTG3nzEDI6Scvev2/28akh6bEZ0XrQObg/x8+ijtDWhvp2qVPcnawXIUiHBSnIUnh/CYNvUz L0tvPhGYH2v2wBphDwUvn28Kz6MHH1p7bOKSA5IrZdfvIFcTyq6pBjsPveLAOlZHJd2F9eJ3xzha hsoBUyqO3ifnnq3qvZs5ADkllBaiGk8fAyB4kk7VjhtqoZ2blhx9JLKYYFy+Hv21vPa38GGN3ZmS m820U2le/2XtM0aSppJtj9UgrRaHyas4p7a9pWKWD8zg25s2yji5apqx/1swTibKLZA1ycv8qgAp iZf4EtFb+HsRMYjzx5XoCIjcsdwM4q5y4Z/kNTCkBV9luYMpqagRrb/xiKfWXsmWXvh3Yatjki1z EV49Jku0/bbCEy8ziAXcEKKAaTmbxLH4qZvRYnGtx3vBPJzbao+598r0YxhOij0PXANZ7pD3GPEH pbmjq7Dx+TxzRpLFhs4vkSophoY2ceuIvdkLN56dCs6zlL33Rpi74mhsVQL0wvRWGodBt5iA/c/3 O4VfdJTdgpgcCZnRoUPcJn57RtUslSMIz7GdTX7DH2k5lXYQpNAQCUbFbHAETbWlsaLLj2HQ10pk oM29m+C8cjEdV8oCICx9CEpXsi8FsMMZ2HxJffjh+4DlVoshsWGu6hoawZA+p6Mk1+n7agsVc62+ sRGYB5KKMkg7sBOAO9I9DD/IUkPWUPyQuzCAqP0ZgIH18hraV9kdnS1hWB7y8bcLfWZAPH7p+2gp nsh5znzNwYT0YmWReF5TzgpCZNmvpcKKXJ9naYlm5hfI5el0ugkHqSuHO2Ap5a6zT09z67eWKWzU us65pbbUJkh0GmJD5+7fbrpAqcwRGjM7Peqb7TaKvMphauI+j/dBraI4vIQ4NXDnh50xiXHywepJ io8hPJpmiZzW0yRfjE9h5j9KoqIYONTAx1tCaUYOvGD8kxO1vVtZwtRvpY7LaQx8Ijbgr/PbCitR s/FxMKxUYOQ/J2HubBtg1lWpptVfNaoDOGTY4tcXU367JVGWhBcIngi/6a/s1JWhbLJ6n8+V15go +sEJa204u4KohEPhgiuRhjrlBfCXt1QZxXmTVlhv9v/ClwuPEZ9v1khVR+lj/6d1qH9z+8AYDSum gz2GjlveuND5rGWvZyHHxGIsrJa6XVy/9EylLfWipkFVvjB2vx6Frq7sd9e6+wNMqFwzgbAuzYr+ K4yTooVD3Ra/MhPJGEz5sEC2h42Tr2WgUdI5EywkzW3M5w15qqED+eOC+CXt+SVD5KHb9iHvwzTP 215eSTa31MASs1r0zNEehuNbvQFOCEXMPj/SHHrIve8LCBjRqLVohhLl5s1L/I3vmB+p+kXpYYrv xLLETOkSeeX+3hapBQxi9IGA7gswS+GITy1ruKRWPHBgYS4mluN0LfooUHuxcJ+eCmZn/V1mVsY5 nsmQ7371JNz1EjtTlnpDvoAD+MuJ2DoE+YZeAB0eGgtiAAO7cKjE3pXIP9CIUc8yLF7ngsXxVkU1 2vqre5H7MRlY1hBhMoPOTQuTYe/4x3PVFzxleh9LsYhKG+m6vCGCioEBjKJpBfvWtHvsb1/8sJk+ aAMQM9ozZbRhNmadFAIU0oaFv4hBS/OBWUNMz6J/wVVNIt+Q61/wjePF7+z3FsxVXPWEnNd5aSBe wveo/CyuTe68wuOG4+t+aqDcxfYTrjNKmiiN9wWvd1gmL7LMMSVwG/zb/+15aXWsppfZPMPeWQok xmmcBMtO0JJnymIF2A//2QTdYjKB4CVwYWVVTuc/2r/qy4kphNEXeta8N2T30wajgVup6DNqscxa okNqWO6iUA/16FegqEjky9/hO8rc8CI1Nan7dfE68kSKVNcZqlfvHrxJsujgZ8SMwzniAnCo6x7T DWHvpx7iM7jLPdys4OgQ/pmqt6c5MGxJG7cqFIDWwhs3J5tSH8TVkQc4D7EvvDahNZoqXIJHlSPV aB8xgu+Wy8qvV/lT7ZD3H2+qaJqzWG3Bk/CulvzGg6sQ51g9eztNyJDFIlST6RK2LaQJPOfmnmz3 9La9+teU+2/8+LNXNe1M+UjM3odolmdxcue60nCs1kEgq23O7TrWjNA638rIeSa7Q0e8Or/IG8J6 nCLjRdXTuRh1l4scn8Wi08BQlmJQxEolZcxES2U50L/YRoOFHvSBe7asdLqpcb6WBtxJJCLlRyDV 8v2b3sLK9f8D7BWop6O5UU1A6pBFt1GWSeGpu9pBn+RLHeNbc1o4oNvuuag+evXl5hjWuIdgHr6I tAMDDJ1CFsGjiEvt+9CpxHVIJ53X799XKfxo5uGXqTd7IZOVx9j9MNXXE44se5b4fR2Ucv2O/w7H EPYZB+C6CkPuvflCUOFQDoOGtsESl11CBjslouNM6fsVpEaE8FwJgoASwVdD+mgr0QvoMyKwHlMP ka4mE6N/puurKSjluMy4Kr3H5z9D6/y75PIDZRC12o67v3pP7PKjNXl9uiQkpMhExLlCd1WCOSmP 5JHJ6QI7DvQW5OdZ4oMC3UmbQ89xMoJifNmvMtsNPbE5r5hLXMA9NEuq8wMNeuQaGumQOK2j991s /X/iwI7l5QFXFkoiq5RdB0O5WwXsL2yzSbLEhmmV5aV4puUDYT8bPQqi+9c+8gje6xn6Zcw29j2N 8yTCjMpohjLA1YdLeAnwzInqIRvWJZm1b8/DeCZ2XrUDFj/2U2t1oWGzkeh3m4ConFfNokZttE/s NMSmOSOlI4m1e7r8k20ms9Qqciw0Qko0qzJukRRjnpUIDydaFr1Ymkl5r3hUM5bLhpj6znEEbMQT 8NiH7NtN94r+2Y42D3QqKHLtEan/0oXYr8JQz3ZyRS097DR6LAfAcuPh47JZ5/YJnzLQCtX7VQ7g f490E+bGbZQ23ss9C9ilgQvC/m3OU6ALqBHTG0pmnwgIJWTdLgFdds2VOwq/hgm2oFdikg83PVQj 6HjvBE2Q6RXb0yhsYcPUcE1geH/K944LtS6BgaEmwOjUOVSJSDSY9ojvPLPm3TGpOt0r/PUV2xYU DoG9y8JfmnkO6D6bAndY3ymduZQy5rkLAn7Q36nGFqD79FZvGpqPkzuW1CyCrhSLeCNILqUT9QkJ FQAHd3zfTo/XMvUEEfYfhXmtGq5DKMprOSsCWt2xFRaOuYfqbotVxqbXHpsC3gLZIBOMIvby2TtX g7pzzmDGrd3WBUhyVUmImgr01TKzyysHdnu+QmJuiwoDw49jYKT0lKynvWbFB2YZUz/W65PJnB6d uPdgfnZeFXQ4+4vEKMLJTpvRWD2aZjmI3aNpsAFQT00Y4bZssqdUunavfW5eWiZodXjQc6g7rz3w uEkKWw1sl5b3kgF0YOkVe0lB+g6aXeMdulr1tGGicJ3UqZKna/8FfbH4kRT/3fM2v3LJMgCMKitD KSuW0HV7OaMgkhkVN66fGRSz4n2MB6cai5w+/66675Bgkd1c+fi3UaZ5Ec4J0tN3LrKQ4W/1TSiO kXKFroyw7OKiBpVVh/FqIkUcCG7UQm26up3zG2Rx022Rsx7XNNniOQntx6O4vo2XorTyH8PpdMFu /L8hZmpwfUqiOTkoJfVZSFeZCCKkZsvcTZFFRviiR5uqjGxlDpPpciCUgiIUe0Y68CZ02/acg5pD 51SnYztx+ACcLZH1pO0y0PCAMQMJihELlSz6/I6yul5MlDVvBfchuCJa7F1TBqBDQIBTL6ZwVGOQ bvptuSMJBdbY3Barshrq+Q9ZQLiOmEa1POvDpDPKY6emU7F2KrGhok7Ssy1q7bRb28DuXH8S5tFm /0E0eiRh8Zf0Siaq4r9b7tYvUc8wPvO3/VVSEsFp1Y7SzwXDStCutPdVgVqnJjB1Bgt+XmKfPESJ +EgGEkYKu1meVlnQdnlaXm1DDKlxW05AQ0JDXUZW6elysUnGwso58h9yJIx/nB3EddMjrlYJbqRj MZoRBOl8Jyz9gKYsTUXZlHw0PCd/WF40BX/UzvzJlHRDv1pSuxjlScdWmdRC1S7joNXgrFtdvPkb 4RCVlApB3ftFiRBPwLUe3frJ//ADIOtvTm+kJ+UINqswxGWVL4baHdopR2Ugm/E2oY4gMdUDddj6 P3DXMlpBUbM2tsNr7zZqs26PXdH9RdVl+kzmj4X0ykI8vINxXDgF3GkBTteNC9UK7S8KxQ+X6Qy+ tGg2ESagvCMn9bY8g/9dHCwugVJWmfyS0Hmg39vnUvJp2TLL9U2D3W8G7tkvSV4EAA4HfDHc16Li IY4f1BSbq7QfTsZOYxqOrgJ1suBRBZAlxt3LCH3ABKmRPpo7Zq1Qa0GasBQdCBWwdESffo3Ih6HD 6BFPLFV+rlV5ai8Wl5U1Bz+wrQKdjEfKVOaNOuX37gzN29PbkkM0gRt1OMvhBV9rLaj+qWi2Uj3q N58wPStj6Zk+FH4Md3S6nzBe/gEN6vPN+qXHuCs7kXrncM17muofh7A6Oc4HAzIemceB+A+kmGT6 zYuRhWs8vXb55xTanKHlOsJQ0DZuTuEEz+GZqkp0ZltyPAU9gaQGgayu7y4tI1mICSSn66lOxs1f jmje4y05VPc8iZvVNJ5J25StkiIMWKquwZJSJUJ5arH7/z8MnzxVOTA6FrG5Ad38LBeySLlqV8Sy GPVPxGFTGLmFVzjZyIbL01FwCueoPr3m4VUogtfpU3FbyXKb4twKdUfWCkVv3niP6rSX1Wj+8mBv 2Qhi98BMl2l9ZuXGlYbV5at3gdZQJZ7lvAJTRTSsLZmZ1bThrt6jyq71gEYDJ3HS5TNCYrsbvo1d 8AUKo16qqC5UqybLuhc54EWrnf3Hg863hGsu3GPJSe3W9FdT8Ab4/0HosJqyBcnmTbz5W4ztsY/7 no4+8c6e4CPGeQ5ZYcWiXsnj0HHVGwTT9zzBw04VWmEPbZO/UwFMBtEeYQedZMn1OVBaLSJRRP8S O3QrNZ8jqs5d7jHI+YGFalg3LhGLn0ziLbIbVUzGm2P3GqSJJ8eNsqOw//FHWZPF8LVqIwsMXMhD RDhl/6J4AouRVuJTqyO78eHCTKxEFDZNdTkGKWWoDHHDQLB4O2iEMB83v82vWcpo8Fev6lMxTB/c e15WTA5t8QLkJkugllR10lHH16rN4aDFIc2vWRnvXeFio8D+7NyVbiHC2MwBbu1H7e2HUbwtQhxW 3gjUseQhGQwpNaNfNYbc2Q33yhfuJzvJ0L62owTFSpmO74Vn/Vzuk1Y1yzSg1l8aXD0pGekrOMt0 ycxuLAvvDkgmeTD4vBGTgQvZg7a4w8MrmCN114gNeyo3SACtrZ9cN68ag5UIxUSirJ2732PehBTx cW7nOu6Xer9fKiEuisoMrlDcE5Jvmv7beTD6PMQ6obgAiN8v0gmv2fvcvMKTDQ4+wWIzgicPo3jj 1vusLpTAwmD5x/G3XR8T1LLqNaKm8T2cYIpUz+FhShF3QOc+/TohF7RPpeI1Ig2WpzLjazY+awJ3 W87zmjIDP6LsIC0BqV7VfflOWOMKEze9TlF+UsiwaJcrZSqQGrxSiHsYTz+Qepv9hVR23Q72Li1I CYcDFr7ldUU/0fEula8vA8gmis22k3V64bCrYZko2iQje+FPDEX9cTZvtWBZeAGxcYy5vDV6YRZX xZMuj9xzsXvprP4IytBhrpi1tjAIVb1P6CRggksYNatSfqbxjyvBXt71OLAaGVtADQ9+fqrh1yXU oLeowu8YAJaOVyMn/jHaWBYBKZaCNoG1Nz3P2b0H7HU2YBdmTmGr3B1/sjnwuX83w+Q8AaKI0PCH bU1zBcB5nwxJO+RdKgCsOtU6b4kL/kMyex7an0GmOtSpsLT0b9zyWjvdBmGKf4DYjbgvryCObYcS P4gKFidjJjV0ar4SZm0lZRDbHfEHnP1N1MLNFJBU7TXL4g3D3iWeyEcEAxkVkUdweYWSMa8ZdA+E 4DHxRtHx6D6YYW5m0PHOEJ6JtmVXKPBdzny2vh5+PqxZlRXrRqUi2X8T/ak2LW/GDrPlVKXn5GeK A0PBlNFIMThh8T8wlkcrNE5WaocfOq8QqzVFqhTYfRTfNTTtX3phjsbs9znSOlKme/IhiEL0QlCF hQf64CxFO/rDwqV6+mGundFrVKXpHvtkwJpuGshHdUTbMsLE75zf9EszGfXktYDKEBjmMeX6cPaB 55uyAd/czYuH1OM97/DqV7pAsUUrbm8FZd9u/gDRQWZ2/sVkwSV8an0Z6XVGVCWffI5NmsaveaRP Dr4xLuV4GBwbKuxpHkfkQRrWR2J4PEUnO8DbESP0J6Oqfq8y4fZ6ZnBG/p4pnPPCkwuNsJq853b3 lBjWAYOZbyNs8gRQ0ouQu7RlUmmUbkjE84qvQJQn4hnhzy/Q7VZoh+76wGpqKquPoCN94q9X0AUE oEFyJ1oc829YzWqUm9yT5ywK2E2jGyThOzgjmhxZeKw1T+XPQRikAioGBODIGPbM6mOsg/0lWtmr iS0D18+ozsK6oGuWCjptiZwIjRhuf7U+UboghFrSCsxYHAtNzuuHSvlnIL/1vkQPTuwvyCf+myHR epWdUjTWKpSwXc2G6EpC9Z9zDiz2aS478DZjLN+yzJOK87wZsERAPgVQhBRpZPqM/H1DsgTr5D4t Njdq7lITNExTqLD27sTkQ/4i6apzRGdnPIQbSAG5BelpAGTts4Orui1hxa2zMvbIjSXIJSfWe/5P Xt+ht4dr7nqOG3cau+7oNKTYZtzcXx7jTdQpKvXxdyNIrOa1o8cRsADt5uik8P9Fe8fKxyU2SEy0 ksZgLLr7axLh2AVE+3KcziglSBQnp7e21i9wI6C1CuKE0l6Dx5Ud4VUq0OOJYSJ4OWhcHRsxd4L1 FXsyGUWRXE9f2sXIlDIhRrCQp2Mym50movEr2rUZLUOY6oNQ3Akv39ZNZHFa4LTFiVpdFfxJcvnd twVYDCfV4RkfiA6jN/TIb7jr3a/Sj/6gksaAc3tZq83nM2AEXZSmGBBmwbY3FUSwxHair+5oPbWt cB83mnGw0Kx0FDKfe4xptH9LsNXK2nB8u6syBMbtTXnOjUS3NBEMnth+IFOKqMtqdif0bcTMmId7 VADKpWv891hQ4SH2dbtDWgHoxDZis5dK3yDGajig1d3qNi/N8B5QJUr5BcWcVFnf2NHWx2NCeLqT Z07FsC90UIFlRNQBh+vUhON7lpPC3qt45hi5nVnjHi1VVULNs0QhFp0snmaNlMSrzRlq8kQoU+nC uWKwUJNdTy5JMmCWE5WWl8rzdzhGgz/e0PSc6f43EU5wBMcGsKzzb8bngsQmE10mPfZmm+9M8JC4 jkeHdOQFGkADhMjDJ15cCSHjIhmAeo0LVGBEt2uO/U+MXGSdX/7rddx0AA8sGwcAxs92h5ERiXpe +QJgQc3KIrwlD4n4Zv2cWLbLQoRDKOZkARjnQ3bI5XUJa2jK9lSfx/hKtHlicVsn1WyF3klNMiHf cKRQ9F6IIxfOc8cdZG0OQ0py7rT21t65xklIC5bEc8VKdLrxPpZJpPM+KoHvKBQiXXn9bAWNPq1C lZV+XkRvB4JcvMTLid4fdXBzp/t4KLmzXRgnQF4SndjBfgsn6OLVOly3VzXEKm0VMHzUm7360NUS j/QNpHi0XQM9pWHyEMnlu+Wk53PQb79MbzevdhqiLcw1ISaSQ2YJ73/WNUxVaoyLEGqJ3ah1onvF FricSmMqH74c28lOg7/4kh4ZdENN7f45ISB9A73lOFNZMhW6gi3Y7xaZhcjuMSdrpfNJi1BxhUob laGaMZ+Kd6xvMGzwgRrpYAd3PEDFvJ7AIezbhTEaWp9xv44QpX1FU3woo8AXX2ZFXrQM7gr3+j02 isupsca3aX6gtficxe6npSvx830MlwxjNFkeXY0T/klu2zGFNebkx1An+0sqmW+pWPqvHRKSQEV/ 57srX696WAuGmtfEW8afl6f8zh0HuAV8jxE++r+eaQiCC6aVRSZ453m98I29QeG7tRMwUj6fMsWb x1/nUJDpqhukebobta1TbDNSqIUE9ZUhZAeYc81lJOZElCYGDTA1qioxCVLWhocKfbHVoCuA7h4c VVGYmktESTjRGQR5vYXQ3Q7hZoMM8CKGzGaWYckorWBh0MzbZvz8AeEIQ/SKLUGRyVDePXhXqy72 JfywZTP/k35DB4x6pRqlr7BBletvNtu8zd8F4wm11NDAw4sISw9knfkXEHXVWtBQvwGxMBnv2TST 35qKxsj52W9+5lLdWIFcNlhekIBjxsBTjT6x1j4OVQOUlCzDrdrTzCw/M0rB9x/YyWK5KVb9gRtC /aID2J7w4v+lRvVtGeLN9ZHJH8qKHVir3Jm7jb/rJ53UBv5jGiqZNNk2XxINHXUyyvkWrNFjdfAp Gg2thZ0xhvGCQWZzXQMgOfUQEhIMjJxr1j12oDML8cBJtIcpSqLsJNTvLaFGIIW15ly1Ohl1dguL L5ztDGt0Hqe1bA2bt/Km3fEblBGw+QZfQQD+FsSpo+Wt19iF7cCgUHftHH3TxH544JwkUME5zRPx QEDWbdzy49Uo1OTUcV2hUv33gpjPdUTUHZ5k+EYlPoXcxyZ0wD7CXkMJd9dr7P/MwSTxKHMP8d8o VbeD5Vs2oUW+M4fUngwJzdGq0yIhOYvX55zrxtUZDbPeMZ5txl/Xv0UVjZdyu8eMXUhUU7ahLnqT 2X7ue1i9q+mnjdeVoUHxYIfYoOMmmAqrf/Em4m2HQkwetLit+0fFtHdizTYEaIRc89tXROk/hXOa POVbDMEpG5uH5GVMRKRXYmWaWYJPcacDKsmrGVn8PA1JV1c8QlwlGXmqaDOPqO6Yfr95UJx21REe aXlHbq1IS8JVuLkEbAc+ISmw3E2PTBM1nTsaoaN9AyuSQwbRb1zpjW35N77ZbUvzz7tNiZdFWBkG q6feICA2FJYg5SEri2+PKEpkMN5iLk7hfV2N924RmLsJ0pd7mwcFiVefV+CgfE9pE1p1oEd2JPjy SYrO2axaf8WJYXJI4ThGZI7LBiA1lVVrijwZFeUf1xd2fV9WyDzmTJ8atasFAVcjkU6ry6ijpgcf qeCoVcVauCL1s0UonxMxd6SSwcFWYQmapXsl1rt4trTrt6+JLW6RVltaDqkokuXrP5xT/kN0skV/ 5aQZ4/oWNzyuOODQj7CMwjDZMfBbqpeIz/a9/RHvBPqM+452ATqoTAKoXRDQvMKr7QYkwOO2Vhpa /qj2sHaFtsvguIY9htJVh975ZwBdy190EbJUFiNTahC0p6YfZGM8FRIb0bDz7u7XlYJLuEp+UNUd JRJ8FyzEKRonavykXos5vYud+aH3srxzC9bAPDywbiGuOkD1de9IuRkONVQBLEvM2VrTb10lEG9w 4M/sYioVijWgeraFj3MPClfkCy8A7Wp6njrZn+JTjVVAu6nPl/5i+ytfif4oTyFgAfprTwHi5EJH 0Lxbaieo0pjCLlWBYaxDlrR8ox79vMeSJe0V25LHYOTsMEwSWkq/cKAfcrQ6HP7sCEyCAiKesMS+ AdJgZ+u46cTbUi3Mbxz+mo13RrP86O5ESTzrEmCUeoQvxXBlPsfceDX0s/Y4pjSkSGgcWJlmE2Su qU2AI4j3pPjusk+XwXyRyE28dq8PHWo9s8gOaG6ULBPJJoUgKStqIYNlPgjMsIpO3XquiiVBlH7E vW/RMBtkYeHVrbBjCZ1vK73fsd9y4XaeQbX5ERYIRbk+Z7zZO02ElxzPHaxtkn1+ar69cr6yiQU/ p+HkxGXLx9CcB6w85Wj87BO70k/Dn7AyPZOG7YGUgcHyJcS+dljNb7+cePxUe5Snwkd7jUaRi1rs U58uyu8yCkqe9ssPLmUcug/7ZUiOHz32vF+zMizjFtrdzg8VwhoKvFqCfZZUzsn2NPXqq9umpxqa 8yck/io+1UCTrlIa31oaDFwgBpum0qchUXQis4ZAmqPxBpBSFmd+4QHg8ljK7aIikKCFpv6J/lEN dcHblNSQBawFzQcHWCvdXQgNxphQDpGKuoLDC6MEeeGTlvinczGzQGFX2z/hUeEKqnEsSwWHZJ1o pPMM2zNUjt68dkuej2wI11s3ePydUWcvxz1ZBz/fYlwkxrqUfaPmj+PnU4iQbECTYWarQfrMG1dJ AUyGAjkz3UqPRtna6h0wEF5JCMavxX+v0ff1T0RZ4V+Th/eT62aGUtoiLOcmwLcer9fAZkc8PMWJ E+UxfWu9ps+bHY0XOHHEgmg1PVJoilu4hSAlrqm5EAqUqeKOfvqHjjl1y2VuNMshVdqDX1fe3l2x 65jiRUhSX/EDeF2DoXaI7x65GPCsMOoqyg4DtDwvmhxv6GMuGFBKeYt2EwFjfr4gHaPT+YHpr19S Ate5R9Q/PXo69wvWjhbDr5ijGx7mXObasFtpOdwr1QAfPBZCDppd8od/VPUyOQh5uZEGiOXB3k4j fycXgEG5zcfHU63ud+ISwV3L+zRzG3MG8Zv8Etq4DnIqSVTCZi4a67YOKYsNEA42K4bfKNdkolJk +x/uXmKrPTaf/NgFUxXgXSkf64FwpA33g6YS7E1hBANFruw/oiHwWhSEUYHhWagPyWFcu5w7W2x6 xrd7LHgTUo3W+Ij9bPDGTAGE7AVz3dAlP1DNGJFSUvZnAeJ4UN1CyPe39TgXge0QO9nFYQO+QuXm WZubHq9jrU762ofWlyOW2Ryy4V7EUYCqnTOxcE4QTB5V9e+Q6/ZCIMehlq/brg79HXdD+kSgOi3l Mg/YTrvnMAoGAupq+EySA58K3lQhXqmB2C2prchL1tqdFble/YeMv9/mdfgdnf8w2oQDYuj9TELJ PgdVLpoBeNwJAlOSotoSh4k5lLVGq5kvjan9JS9QAlh2yrJYHqEt7bl4Vr6jxeL9JDlmoZG+fpVn DJ6ceDZub+nLDLjWtEH+JqmVttRNCpVQrTDvfugwkszngpq/jVoglQONnL23eVwnjAt4ivd8Q4xI 17PMmQ1HM18U/IZ3puezgluRvc5XQhODHwQNB0MjJLsJQpTm4h54FOZP9SRGT/KE3DQ+Q57eL9e8 SrFXdS2I/UhqAwA5vKy/5/DO0JykbVwLAosYkabY5FtfkOXGMZVozA9V79ZLgNuZFpRky+fVKYec JYAX8gDxhE73lvozM2dI1eGJxf4AZUN3R85OMZJdSHu1eA06X18I8g7Mqgm8ytKWLKCq8bdm+rnc oVw2542lSO5ZYoiNas7CUtFLhLagzgzczeygc1MCmxxQV+if3EEbfdpA5GQxU26J+/1lJwtGBKFF bhias2fXU+tz/jswd7re/aYsdFPOCrEtfR2JGWlXlpxGW9UekVQ7dqnBGiPBnkvbeBSSUVDPc/ng TU58HRnUIf9FqnpZhRgMFEoNuTk+GxbcMuXOWCLTbv/JUzAQ++14knj34v3JuvxrrU3gZ95/QdvT Ouk4SppuyqWmirGs9wZFfhJfjy0+/MRv61CGPPUy2fSxI8KcjxpB4IqX0U3Kd7uBcZZaUVvhABuR wdHe4a0Y0NoBIqeL8aRCXbfMP6m8ljTya7utZywi79do8hLKYAiVL+mlXg7EzSlPK1JA1v1OCJbv 10N9GqKubbsODoK1YPjedqk+Po0M7xqaPmoOWrHWWrJhlEJStQGTIB2weDSOuKMMz4a7GKPzyQBR q7pok2HbLBOLqAMOazjwUE92xcSKN/RFcBp4ZTLQIZ1lucXnPESjJFLwC8txh7BYc2r3dr7IkcKJ WfcuT4CfyIL6GynvZWwjWj0RoV25owBghQYkIACLVNXb7NXrz3UvCxBk2N/KizqTj5FIJ/7r9hYH FYZ+YcHMw1xE01zvUNBq3nSoY+50RfC9Ed0g+/+xqivT/Jrh/IvEKjvtN0EeQLNAoUAkWPpiTIsO oknDl+aOFaZLtsaeHvGmqO8/VNpYW190u8XvMpg78kREI60vfy2dbL7llEHB0BoiUN0q8vc80gpQ FeL1OYGhKieJ2Ez1ebW6QPp8EuRa51kMA87O6I81+UwJTI06dQl06pt9zORJ0j5UM65qdvbd1JDP HZHmXQMsC9eM+ZXeauFcc1cd77bqMUG/0+glAP31eYBkegF7RUQX0pjwTU7JQ6RKmCTxCOANH3oq gg4dn84AtoF/mZ+S6eaEmV5e/+ZgHxgA8Fbm8+h636w4wdfn3XLOtQYKlo5MXjEVFb9ZaPU6jft/ KncTD4xby6gBI3NgGD5JeloEhQGsb7xJIOEgHiZHhuDkNpO/pqofwkjmxC85Tzh5AF01FLoHaAmI ZX4aC8fbS/JjtZFOJUfwjdXujx0ZBZo8aZ1JhMftpF3hRnWPwauWascTO2qUj1w78qeydUkN6/8C mIxsSTQrr95Bj/LNBi7/i4OIu5NdW1j3586oKHSy5eYULneTdfnAsdvqqyxizkOjH/HK+5f8TOzf k7j8TkjF0sywe5YzuOHXDzDcdz/J86blr4Aijg+6Cy3wpsoX9Glu0mVUJAo6UoYsHH8GrO16WqJJ ckjxxiJvubbtr0lduqqHa9AwDVlxqHj2+Otpm9FuYs9qU801lSTwxDLTm7oyYgi7Mf7Lp8FXIoZK x2OCULO+tj8SPJH0DiNGSLshBWvkVitXgPob4Vo1dhontPAQMp0tJH7tq4wPN+jSU578/hmLC6q1 VsMbW2wBoGygrc2VaxS2lbeWVsrEAr4pxXnD1YlN0EHns7mP8tJuPGtuKfBP795/vCXqeedK9zs7 koFlHU6DMHUguga8z7L6uDBrYnT8lKy/ULzQFbdbzvO48EcBpaJTU33y9adABp89Z0I8+PEs7GJt D2vi6owwRkLclbl7BjvvPUd47hmvlb/7YiteyP4cmrr/KVrr2vAa6LObbVmn1PsJcaAp6i3ojdYa LmCMMRugpGX2GITHQ8k9SxqGvIxvzf+OtaV5UNoCGkCr0EEmCGhxpOEBDKyykHlYxW0getKpnObj 1HiRSsT5M5ndywSpRSaYjVp9kBOkF8oUk6LtCtS2PdL6BDWM2MR+e+pWf83Lg2pAmm8oQkh3T5W9 zWqUijqa/dDT3Md1SmaPycyI17aCANKWBV/lfSsF4ylP+XHCBuLEd14o58d3OIndmnQQtmq1hr2D ji4rj9xtZnO1phHA9ISdaN5lrpdWtlTPpoYBG/HLMFJawf/4TTrd/W8yaxp5Byn9hlz4tsrXm3bE V9fhRlHFsNv2XnK5v174b9kc3IbAhMATTIhAVvtRx5Lx/5NhnKmWxKZFJnudaHZ6WG9NAN2W8Tkg BjkeEWIfEq6nkqmRLimQpYoGEgK8iBT0F89eIV4dhV6WZOu9spV9jk2BZectGHonX6V365tK0Ys6 CnJAawMHWcRTiWa3Zlb0W8eWfPjOFBlABu1jVxPcuFE3T9+RlZpQYzqNZ1/igHYPkAySpIWn6yKC +QJqiSZXMgWLXGDiHoOSlu3KFTP/1LGhAg3ABhHl0Xvpdx7TX27LldfDzo8u+stokfSs3E0Oin/6 4ss5ue7rKrMJXypHxXtKjOFa5iui3lHqooCgZVE9ba5m5cg/7IV6FS+Utb+WRCxE6FUn2quO/TcX tVu88wsn1MKyxUrXbRth92cCLprd9b4/uZ8nDtino3y7Nkg4C5mRjuwYUEO2LZqzW7sQBRsjIncM E7zxh6Pw4z0B7X34ZXOXH91gxQeLEeLCtXRb8OVnPYdHk8rLegyqwcF7rexGv3kgttw9fWSxwvFI po2dqNO7/ys1BO9V8PU+UjZSPCJXDLaNiLV+ZzvC2OHRUYMFnIyRsxVowJ0HNoAsQ6eZfzIEnWl3 2gnYMoYqyzyA2J8bRoxgriCcdjOCQv0ThpjKfBGUWudhvKiIdD5AlcBTQ3JQMs9T207Pd6C3L1fi mR3VwyvYhqenzOxN2nYgn6pxj4j4hlr2LRZ1Wf/m36wP0+0eFDggDnmOCtxAGNgEC38n9Gui5m9m 4pZ1duhm5gyv7MXWrGLwmIc1h61RM9o8Y7LskRX14wwnTq0Kh384jRoT+Q2FAYD1STmY/FkW1bxP Wpf2awLSH8Yhz9oHIprL8U/WZUtp73wUzfbTzifOplgH1drcCfGKFfAhw9KvFRY7la6Z5RCbr8Nb 0K3Aw7Qeft2X+IeRZvna3R171llK7s8/wDZVAZNBWbO8siZsg8sOQ25OAI8InZAfHOLp4p2ryC4y aUaK8h8OePWqOo0mWNjcIWrz8OqCFOid0QJjXoIPuuI7TZ/n0DaJE90cdy3VenAQy0BO3ea5NLjq +V32MbAsS77HlFP8cxR20DR2MQ+sJAFrG1QPSanzEK/q5reKrYcY8lSCEkVg8Bp7rcOwBkz015mb SQEezzth5RQupoBuKgibvzc6K/gG1SscI6csux5LPVzDyl0pb22LZbeIOfi22jJE74ODPSOP7ibb +ZANbOMqrYGlWyh+QjtS5WYafuRABvjIX3BZ9YiVmkBDI7KIlOLY5mRaz5RHq7g8mfUq3DKQXGo9 eP8Y0a+ze4ABuHWrsPLIiN5V5SqkMdKHOx3D5TAxD8TQFsULzKOR9J9x+NXMqEXpbXyaTgsYSF/3 E6kOjaRYJ3hj+KeULojNFzP+Sg0vBKx2mLBVtw3EJFK1CrqLXgXSJLieNTb2vyY4gHydloPRe2oI pGGYe9LQSqY//9CAhgJjeG34kpFvwuK2iOjNSHUvr5zPayotra23mA1cwTb9mulDeHgvEXcB+dvF y+yz7kPisz3CqTPJ/oSfaZfpkJtsKthQrmR30sWtLcNJ68To7/S18kHRIY6FJaSVGvp/u1lIoPiA Y46SDgpfyCuatgKMia8JmAGeBNWC58YRRaFKimY4GE1KjvgisESRt4Rv8sLrRLkAWJLLq9N4+eTU 2sCKYDpXFx6fiQursDxvGMBRTjSq/LK2SISmRNSMNNJ9M0oEcWBZ6xVAMyoMPiV9OF0aJZYy78cc M2fpRjmQHX89Q/TtYSn3W5lAQ6F4Ez5G4wUXMEh+oXQ/Ejj9T/RqJxPrt/1vUcZvmDdzy/5xElYH 8nBvsoEW6CBWuFJ136RR4DckccxZ8yOZUr+KpzakzAXhknd7o6iUpn500BMfAocC6VFPVYJRZbZJ 19YwK8v3LpGpYrHyKyqSE04cwaxLZs6ppLTFvCjDBtTO/Q0lIViCnYnt+NnJODjCHuw87ZjgcP5b p++IdKOJKM7QWiOhgVHcjvWYMwa0mOLQMP+JzkJs0cEefIL9jAWguxl99LUafxvx1d8vx4PgBORy TGUCAAJwYWDWLPl5v5DZOPQLYEldwhx8y8ieTACaYkhYxFFqrjgVjSCfsBvn6u9yFQvs1IEvMLSn CTAoB3hNawMJNRrZDlcugWXa6J6fXnzRBFqj2tROa9APC9aHx451dtwqCnfH9SPZOVaBgIrnXGmT pQkaBBO6EJg8aEiOA0zssSkX+Fw8FE7Jt9Dg73UgmiCaLdhZ9WBzeU11Tw7eCdBTYwOyZgFrCOSy /S6sy39XT44uszAEbSJ5SA75NBZ4+rsqD+G8aEM+ofhXorG/aBpuW4oz3hJYQTMYnfskkR3TOXx5 +4hunnWZiikylJush+Dtj9yoKpJ4hiwr+CpIWk//DEdJHivyQfJGWUqQQInvPpikwJMFUecXyrfp h4tEUywb12gyHNmZn2Qh7k/RWsR0hymVxpV/qEECGSTiMAHOeMf4+gsfEJZFMtITxu8l5Dnh0uJv AZUw3ViY5iaQe2TDUxcO/Gv0NLFZm5mSJhjjY7IIQKialE5AWELB7oX2G1ngb4Tj+7ov98MUJFWM kWiw8/xVwgq2tAW7SFjjuduUGiUy1GHQ4o1pve7djfwAVABJM2qWhB/kQA2+75qM7f/pZrgCiPk4 doHmbG9GCUKjEz5qnlRxD/QWYAWtrznr8iviA8J06fo73Y90p3rXulH6kRlsLyDMGcs9QCpsSD/1 auNST91Z9eXDzQrebotXo3nG1z6yue3182TU0DzGYa2qjQnYCIrs+GnOrTLKeWksQHUMXKkN6DCL vpNBHAcdNTST96dx+RCBlLYkeodDuV9a9OdzUZwTAFBq4p/Og5vqk7jr7FPy25R2sYbRa52cmOsp 647/ENYzwvVpD1aY7/u72IUfEOeWY8V/GtkaUpTDrFcE6mDpkI30N+j9ufD5EQu8RvsTkx6D5Wdd BAQHHoN9Bp6mLuZk+RKNjJhR5lsyR1Cmvq/LgLuNsB6gWz8UE/jag4Uq6Onrx1sdaf0ljAVruD4z wLOCMV43ye27X4a/2qPK7rfc8B2w0AW/wr6zzs0c4eERWl4udFp7W+nkT3H1semyeYnE3Cm103tV 1VJXI/aqXNRqDsUlWuzsi26+U8fA4DNaWda7empymrPtZWc0qDp/1TcmRlqIc5Jo/8WOZGwpTVXs ZEu5lTBzIDa4P7pXF00kSQKq/6ObvphLhZfRmX9Ac4hWS8XojrbwYZSpHk8e8ItAQud0BzP65N8G 6wXZ//JSmc6wnDmzQlZEcZK6VNTYm1pGl3NtSYTq5PeoC2thT6LRgoyIsD/wDPscID8eOzHISZQV qgcfAiKn5P2M0zoRpdznnWbee3/uakdmikMhAnuig6rEZCNz5nn3iCwI0rx8c2CR3kys0Xgx9CLd 0LF/EKiRn6zWipaFF+Pr18FDahkR7eojLWkzayqlij1y2npi4j8PtsielDoJ5qdB4MteszybQXDN 9TRbHMYpHqkoQp3OmpAUstO7dS2gkb1ZbNN0bJQ6q7rVvvial8OcGC1a2zNoOswvQLCrbU3GO5cj p2H79fu/e2SbGlHtC0oSsBkCYwafYaks99NfhnF21jArdro1ctrnYii2TXw99D6Oc8mexCjkm8Gs 7OasGnKkdkvBuMONGX5yOjKg+B+MiFfE9YlgY0H5sfPkDKc83qzYHj/PDUlv7YLD9stsSk7vKTAC xjtnwaIgxzrFd7etddMYsmWF+VPae9lpUcHRcdZd9JSiT8apajghAAtNj1XiNdMRakiv4hm98JZk Tbd+qFnJxGs331sXt3sVi5WxyeFWD0oGFdPS270BGVGdD38d9dYNPoeW9VwaGLzMcksE9Iwx3fUH OC7+/F5iftaSm7Q46SNY0DC5uyM8Vzw4aQ3m/+uLZzfPr4BCyLftrUbcEtQs+mu1GjYKe8jr+iNh s5ogAhEutamEBMsZOTP75jzgOD9KGR2SNWNqMOcPo1i/EuN49EyCfqZEB3HceD4iZCMQC1lMoEth rDJ2F+XcK2XpPb8lFBOFXuO9y6E9hDLa0tb1T0Eeh+bHE6GFtVFtstcAZAvC8pCV+EOrJJSZjPki WmFra6e+dhT5T0zJ5Cw73OCJ4qB6yreke45KHjo9sgO7moTQcnbaFw5jdz6ydmL/2IJUeo2IqOtI bc47QzXYPqJEGczanPWeieYC/3bwALMCn6slEGsKW14OzAL6iH8Ch+8s7AKcsLVpWSSBRYtkyy4I nPnYxEP8se924ADgNkT2E7st0OLKbJ8bge4Q1Dk5mmKg+K2KgPl3l/v6Vh4DEqGmYuhHoZGaIh5B 4ED0OoRw3ebndQquWrjdbftfvQAQjRgCQeW7+dk1ZTsR6H/clKBjeCe7LcaXRKoA0Xoz3DjTF8+F gRvwjHjexwOmpwCpA8CRFa+oIVOdjSVU/xhXgqJlyzQqwACOZBoRWM92C/jxyQ5yU3B3C8c/whk+ EdgCLFdFEH773A3Hqrm3XRU/L4X6+IHlan/sOJ00PitoOKJmh7zV5poS+kt1PfqUPr2vRiNt5H1h icurkGebvNkhlE6pFPRkJePw8IUjk8ksoTHrzhe8fuAaEXHyxMw0Hl4XOTC0OigIt16T4WGWjtiv xE6kUBy4WStrtacIHYa6baPmtql1FDNpUDU2N4U7hYHB8nrtrroPiCzYeFzND6rHDHJkJ5zaMkYk 3h0+qpli3YTdqxpnL0daaaVwq/dHMPqZy6pQG93kQE2pBH6S84UYrAgvh2A93wfYCvTGljgiNOAB ZwACxyI1UJU6dMcZMu7tcoRA7k/RpcdHGOgK+xarjvEhZCdT+v4cfFTDqvtwz+PCVTr2tV39wCEC mu6rqgH5qlXEDZEfi+r3uZMOXUMVojA2Ge3UFqL7eb0ne2Jpzx7vCCKe0gh1zr7qjnBeLWNHtgX/ Gni3+HoGkZYc105GnC1ZPSc/Ol5i2QPrByfRvsltaYz+MwxKvoDa4YeNPUr8QlswlECTGiI9pDJ8 utFOnp6yYqI+z7VojvPJPCMkVA/I4DiCWGRr9AdRIW4OlO3blO7zLMdLDhNvQ/JPVvg6mIpqZMWe NRGz6DApKd7VYPHvNHUMu/PPwFulUk4HY2nKpcE8IdIxvgboMFUnhvtxOxm6l9t+JL2NCZEDkxnK wI6m4+xm2AnquyDiWj9cA/0OVYahbnqDiWgMPGGxRn39D+Tpe3GVzk6XDT0FnIymAIBO1R2UFvvV YZt3iwH1x8MxU1TzUebMQB2dp/xC0GIzNIHEb7PYZRTp+BS4eaP5PNzx4cO49KQoz7h/63Q3vPmJ r81nby7CAMl4qiQLC7EsI1W10toti76Kv1B2QhCPjRyp1a6SPgOF7YV2LyB8WC8oC3tC5C144VWh Orhz8/9WF/6jE0vLVlA2v/4YC0MUhHt4f8cPXmeEFzgmdmV/JzuRv/5VQQu0eLecT7qCRRVbT29c N3bUl3497GcRFYYAVU7sQVScV5J5ykeBJjcJySMUfq38hc548zdi0ExpRn+gK4MIY6SiOZp+RTz2 NQ3duZmowv1jxDXXDwaex821CXRG09c/aIQGoCzGfm7ukUjchLC9pTmW5jtPw2QupuPQu6NJTHBz NCjAQdD3sVCM/WHQa9UoS4gDlkkvqPPpRouMkFtsXKluxjMsxnRN1KH1eDkzpDJuXLTJBU5pyIW1 gD8zuyOIALZHNmF1bDenQxwNJuSwxTN9sVcyc5y4kyNuQ5gHFiMZ1rEDF+3ayR0YLGDyIa+imgAO FYiTJ+gC/9MxHn6IS6cGSm4wNNw/Zkzf2JJ9FdcrCOFg/wM38BVMOhYfOUJUzWc8v73fZsNdprVL Ns3f8Jz7OmyNfpHCeMpUZiluE9dLRF956atiy0KUOXqgqBECxsrCHQhL0h5n0KfYsqU/0nzgk9c/ 86vHLxqKnQrgj1Z8J3wbXp/dDIY6Wjbksg3W9YJ2J6t0K1QWMZoxV9oM4ww3zqw6i+ElfdimOiwz 137xSqLASUfCvCueo6X8T6Fu0QqgXo4JryeRe4jvDg+/Fybzqi+AT36W3yUuiLHdX6ymzn/2XuIT 2uYOutfUAOLqBytUK+Y+XHW7sOoJahXzUMDG402T83nd7tQ8NAp5+yMl8QRavl9MCvfs9qyoXtQP D7nSTlMtcDGr5tEsxHwYWVZr9hm8FdoeIyIwucqn/+zm5Pq1kZvdaCPwhOvxtW0YdkTDgq67j9ma TQac9JrNl74uuYixGyNeC5CGZNszTLT5ela1F/sYAy5TcqNLw073ePX0EzE2kPY05yG5rEFSqtN2 caxsdmKCOCaXFN5N4bgtFkcLAjLJRT+W15LA1URWhcTsdQi8cebd42fdbPwqQGJiF4f3CuaHAhKx evz3Gnyi6ehC2DinTSpmDyZ23+hOQ6LF4yjaHMoDeKoriXTvuWWP28+1tq03CMVdpvQs6jUcl0sV vZTK/85UHCq8e5dalaOHzkfUEywnSkeJ+bk4DbeVBDij3qhGcvkHXOPfRYHEzkfwSFCOVfNAuYQ1 xyBhU6cM8paNRS+DkLi/GHW75V7umuyTA4BT6bEOCmcEyUIqujVTFjjbmhu8zyKRl8SKG37mP0LD 0dTUeKePWv3VZjHPkQnfKTooR5ezCaoeaXQmYcM0cttiNFh46oKSjxXVqjXkg/a46sQmXNYjCkMn FWdUclBsYqmfu5N1w4YdZLNw/YE3x6JVmTn4H6NfThW6Fwz0rc++yOSwfyoEt7fWjTo1PbcucXU+ zSGqG2hFK8EE/ONP5PmVdH0S11xHxnwjBH25QnPG147+dCgO/kBFubcObAj136VLVGyi2//UfZlw qjxeckDJ+RP5bw+p2vaezVdTZATk/DuItAnvHhFGuGj3MPQzwLBT9Vgp1+j6uSENMToaM6ayLxxe R+djuVKIFhU1LadlAGBx6Zd8cp8MnrWv91uERILyHuYkBrTx2MVX4MKDNb5bxCKxR3NvfP8VijEn 2bg/INRHP24h4zZBVEjV4ggAuKhV6ylLjKTuwzG+WadXRF2DHHQS32rZl1mJv7U8L/YV+eU5xvX+ 3nrz2ILRyhRAc2mXJbjF89ZMzpCuUiPPFOE/jGTltlviHwQoBobMiTpfcJv2IJmMpEBlCqJaKOB5 KH8MV4rVcYAGGJz9hWJu1rnCTyqNzAM+DGdkrxn5gh3zCiaXeoJNlhs5bcbu4bc13rPpxqZ3yVXk xzOeE3bFtwK0LvS69PLxKbE0in6CWDHIZ8On9yvAwLserlaocC+gHYaUw7pWLibt84ZwMZKY2rpL al36XEflOxbTz9p9ub7fciY6Y9nrczfA9G7He/c1419bSmh9RtwCfyQB9ZJk50Wo2muLMyL7EEYF +bcUQLIriHy61OV6A9zDLEJQSudq4svUX0Fexq9hGeBTd76zzvrTHV+dU5xP2R1YxfSYKjPb9ZRN 2uHuHv/8brnPtOIuBwqQ0gFiIYnXR6gEeMQ32OAP980k85mL1RJNiodPE0aZdij3pEK6XbV65Ah0 t8H7Dg4vteqzmDk5faSgVRXyLoBLNAGIg1+t+3szyMeROTS128PQ0PPzVBr7dKXIKPG/tA7l9QZf aye5n4RwHLB4sPFDH/DFsI8/dUSEokvFUNUh5fs4pObHovTFX3my0UsDNVwh1S0XCaZbnwe3o9dn MyJb8oKTvc7v0pl4AR/m5V1AgI17mADTQNrJmrhh4d2u6daXIpkPnmOvFHz4m83tI0gN61cjBi6w S1pyi/CEK+DOQckymkfuhZgdstjfsmfdds4FqqWeF29ACpPeML8G5yCMt28UASqqQBkaXd7Apbyc MuYvGhLoNFrHNqhDEebtvKdL33toxzY8qc38lwiqZ8apPT9OOdeLEXtl5UeNiuySs/Csj+d8MsBx h0KgnJ70haPn2YspHkClUKcNU8zbxUiQj0JDFuz/3aJh1scUfIQGrZciIz+eQUYCjvQsnLyNJV6x 1mTjLmHoJcwsJzAlgU6AbXp2GCWqKmOx+CggmZsW9s+AOVWAU3HLNY2J35gsqyMOwFzBXGDUqsdv ZeXQLLjkaNKbqgOGA/9mI2UcJyj6mZS+UfmGu+Cfhp6H+//TdlIW2iRXg+wO7U3aEWph81z5ZTBR L3eLYttbenlzY1JoXreZhmBZe+May+V9dvuwwhxHzeH/cCG8ujz7oupkABpGHkTPnZK1ny4r3OI/ dGVS88ALKZ8nwZcQfkut6Ff8wtG8dancgEb3aMGLA7VgNNfgMypa9fHN/ND/YB4ICGMZ9Cumjcs6 6961oY+b82b+/+k9eQ6yKXF5alo7i8VlSS2iwb7qNXm6lhhaX0Ram7AyMbjIo2OiAhNes38mob3t NYZkORzhzDech0Q1HFYKFZxZAeyFs/zbNqaH2OqHi1WVAFr+4uWdHiyUWxLvume3irr+aS/KINQ5 kESlbgol9bH3PIxQl9SSp9WFw8xrEUNDQ9NnVW4HXQ2K0gzUUOsTbA0iXFTrNGP3S95YRz4BO0wD OjgsXudPY8RQ9qPQ7AYOvm1W1esazvz600xmTXWR9mBun9foxAlmWr7pUqOL15DK57V9uIODWOot vQwbeg6Hx328IaveECxoUOyP2YPoYXnrDawJZvggvDo1dTcgSFwePKEXGfmAziMm1faP1cCfWqw/ bwVN2DxXTcTW4c0ogDqApQFfMo0mK1q6/8zcOWr4MmQGngcIs444HkO4BiKSJ4qu1z+WqdVinYje E/tZB5lhciHFUzDPr+CmvncD7K6J/ve4c+lbeB80r/ZZDuu0XqfdHBJl/c6I0tUt/JO+F+v/uXxZ WPiBZrS56VU6G4oE0zzp20a8mjrVPSbC5vJr3RDc1bou/lHpniNqqUb63qeQkX3V03BBlIVhhDVx yGqqHlZzsYUsj8OtUsKlWzWuL4pfLC5gJjtuBYvyFz5c1pmTG3tbEmwRaOYfDI9Yktm/CX3mjKfV HDDaEXcK19HqyE9K8JPqhpaodyGrLrjqn6Woh9cjlvanfGkHkKrVslVu1E3pL5wi0NkavoTEjwNU qIts1uvutOiY0yjPtsNN9ij5H8dq951l8WJRiCB8jw9S8SfbC1335eLopTw4aL41QgUyBKXp6t56 71fSIeh68sKeqBbsAYLWKSoO5aJlHy/q01J8FlXsV2qI3JRoOzzCID/8yBqIZ/xZXxkiUIi/SY5H Qr0SC0HH8YNevGbgMyMRmeEBlu9E90iTo+lquV6NwBKsSpwu7Xewa9CCTpAFiciM9QNzitQUiH1k t+6j3Jp5hxrRupqsTFVWm7uzcJST0SJYRvXOYzoXeyB8rEhpkAJeA3JObiwl+UnQy/N5qH45vwo4 oam/TxGRffVUFA42YXNXH/jF5jrBmONqDc2Rma56ZNJXkI3p54Brr1Uj7Paau2Lc8DyYN8024sJM Y+Ci8wehRfxJ6UG86KCfXcKNY9Ffqye/E4whPB2mDzZyknPWWZfXRzXdx0bJZ+QEGMIWyoRuDARD AOiDcjmnPIOx7sw1wxLSeeuGN2hdBQ/BfBuAochLwjwDVF2bFSylOak53e4tvexL/l+vPx7i7vRM Bl2Zg8toQW6eS9JpYL4K8F0c3fXBnnpFJ6k0+HSXELfBxFbSQbCNKp/X62dW4eIOFnkTnHMgR0z4 GBqXD4kLyeH7rF0BFs8EFeb97Ar/bBjyXIlJREJX09gaZOIzdQs1+UDGjwHUxsM2o/Ka3fKIxVJq 1pmxaIKm3LYaXnWT9vB2dPzWNpwmgA1ZYfjJw4F3BS+Lgyhd/rUT62d/1OXOIGaGrR0PneIlDidK AruVyVzS2TyyPX1fNVvlaru1y4wYOl1YXY2YfHc2YazFFJiKbESZnm15hd9AFcbFhyrzdYA/QuSH JMbsOc5p/+DdeBtjOL0CiklqYgONwkakQerCxyRaJx/qcgqH9x3bq6a7KJ/O9rx8PX35Iw1y6lvm 7cxKdt3I6dFU2wojrVirdBM5oh+ytraEL6Iwp1VcBGhCSZazaDYzLQwlxLxsGGx/J8QhsmoZwQmA g9siqhF6g7f+2113iPcAlPE2iQXSrHx87WyOpLikoDqD56siZ8UVNP2w7xvyzXWSKnoxfeXi/NPs Df2k3WRJOklmujeY1jNePwf8vxT3SbyBB9Cvu+Zc0gE1g6QrGWfO1WPX0AAjNHk6D3mFRDBqrFZc SOWDAdJ//V2wJdoi+Ty1Gkd3WmhOElhAbN5bFvrwvihVuQFfzUv9uYdFl+//Hxwj2xIcmyo5MDnC vXwhvbknEeG3prmreFZ6SVMvA+OpedL6+WeAYFivWK+OSZUptlZs9angcfalXE8Au62Akf+H0DBK LNQ+vhYSNLcqYTpNoaJH8Non7xt+6+dAjRr8xsy3mxlLt8R1XQwJR+hXVK+Ky7jVGFay9gEZVmyK cCEG7qdEKW3t7Zjr4PMl8qZcbMp+IBKwEYDAgTMxgVQZLQx+jGvylmaT8q+hX1GbPnttesgUVtI9 TsXAwrd0y4ekPP4Hkz+eljm6Vt2RRDvZ4EKaBkJ1OmpfwII/kZ6kcI71e1aBThPVs8VcJicOIm+m aTUXdASIDA0T1KauIzJ2+DYgpJ3Biy325hc781qCnqaNTsL/LX2mBpgs0VEoYI3rUMmNRMkLJLqc SUKhK+F0DNGtZC3yHgsmXeXSiCL9PnZCiD/WPKBFPOkl87xbuCyzBpdhHqh6kSVeiqaWA1y+vfcw fuXHRK7vBt9P9DGd6rJV66uLfEo85efvRzx31uDhFi2G4njgPdXARc76Ql4OUJNeUQfBMSfvZH82 HMoSLFGMs37zfmmd/mrPB5wR691nLn8y7G+HpEYO5y6M+V9gQIDKpxihHVGDXwuo8TmGEqFTk1sg RRP3yZlDNsrTydQLHtkryYX1AiQMAapl9NbLxmKYy5rcqmIUmp+YPQgHmDRcA9/0Yj8E1EoEVjqZ rqfBbyGXJ/GOQ/mYF5+gYE4Lqa8sC/ZY224df0FthKKPofVVjPeBxGa/hvZyS6+x/5FZKAeC1WvX 6vmSAIW8hIAME40I/0I/X1JUgqlRHg7J4lk80DqSweF+M5v2IsHiqq+I2xv5CN2sF2m6lOt7Ilt6 XPdj2wsZAYFCHk3bnLM6DuIIt7uTMTgwHjjuj/IQ3cwD7yRhCiSiilq3cl9MO7ADShXCQRAZchQY U2DdqeKpcY35xH5ELDqMAuW0at8l5AnMgIckFtql8XACHKP2F5OgACCwlubKFnPWz19backGMT3z BeYH71og8WRSU1GK5KZPllGuuJBHZdoCOWIT3bB/JXO/14jp5BXbGMB/u4QeKhNDdHqY3geCS7yD auQxpdtuJMb65uJMlQijmwd56BQCgN21obYS1XF0NPmwNZ6naWfTBsD/xJVVufNAhAsG2bp6hYyE 5fheisOoyXPMK30YPomNh8bPud1mdu9QIq+HmHCx8gwZAMxjTi5Q0Xtsijbv94UCg8Sx9Wv1cYqO FiV25zZGoTk2vB8KQMo5m2XuFw0IVXxCuweDP3C5jp7fgobU4h6sSxYWswwmnwjZliwfoKNZkoY+ JsQvR6wPctUWJ1cbOTh03ZhzMFCKlzg8Vt0/m7VB/uKKGlgoYh/0ROlaaObck/4qFrRFjmWGhyXx swpvZEQ/Irhg2manFXFUV+W2rZl0uKMayJtWZRp9zNB8E1MiFYIJDTVsGTIfToA/janc9j1cOGr8 aKo5im/u/6yFXgnPACCrt9jnKtDM6hAOimGFcKEoLdTlF+zTRopr7Y7nfBpLHoUq8g74sPyV56qc QTCulAJx2t/dif7sLmLOazGawNDsAdQuI+6cGPFGGRrM+dkf9zDo8mfChhp4C0DvRvLjNa2wppcu 83P+oY3SMePImO4T3z78Ef2/OXMYzasaZgzx1Dz4ZA1NvtBcSuBY3IgIyOUQnzMz95y1Pyn1noEG VDx9dK+8sQL+ShjxCopz4iJP4wVt3Fuxwpp7nr70fx7gTcOpzYWKLZKMPg6AtDrOtcEPpecwsu2j u/ff/4IVSwc3/ja7Om7FUyJNEUSBmpBMiiiPHfIsR/cWmlUHo5x0n6SaKoefvLdtcpEAX7ty6sr7 pvQLy6ex+9rEAmvCiu1SQ+ys0pyHRxYsGLgD5xn0OWdsTMCG/mWxUL93driQ8fx8nKpmgoSOuBy/ qj9mmaqxivvF+FxjyanmVEeJrx89uMnanKqFp8IR2+tfn5nATwym+8/U4VxnN/DLR60rfsXDBC15 YtrUeCPHXW2WbYBuEGz3uNiy4hl037wGjCONPHL7ns7vuWYlVt1Txvqo7h02NQqzozxJZEO/W1wz fH+zQ4WCJOYIQpkUYR58xe4HqmKKiUYQ6v2eIyUkTzXlFo8ecKv3TZtcZVP9Ucvltrz5reJmo+FH 4jqXBabZG07b4P2Kmitf6uR7BJ/92Kc9zEFEOVtlQPWq6pxr2wc11MtLjvTe9/QxrEjnd2lbOzfP 3BO66ASwbgDdM+AD9PIqvTnDk/ZsiV2Mq8xpqwUU60Pw2YYlrmX7W7irG1BDudlU5VzxbjDyx+HZ iS7dVt810tR2qHzNjUWrfroVpNlTcxcJLWT+D+WoawHCJRa1wG5UvPy4WKmgNZ6ahdGfAi7BRNAL xOeVZQ0j/12gw4anrG/q1fdByAp4WclOxmhIiWHYkNppKD5j60pn7TmotkyJIKAVH/J0/XxdZgYv k2GBu0OO7TksD1rzvT3aCOSUmDyT0bZBjqKI1k5tuIsg2w31lE9BJqxjDXSSs/nLxWJvXSDMILIq +KLm9sKZjXRSSva+8Vh2igY7ZtiHFv4vaQW2t/r7GOArh7/BUBvpapQit4o7LgyEG1EvRs5OtUxf Pz9XTjztxa5+aX27IgxlVI4SIlyUA2Yd6bbH4TwLTb1NjTlQMPw8lotSRH4nhFcpRZKM7ZzAK3VC 0on3SHodvKPBe9LRf6dS5idHF52fmlBa7trVdq112a+zl6amrTl0dzfDWvVPSkAdiWWMXSry0wWs vSKur7eFWgp16WMprC9yiFki04Cc7l0LjyXKR8q6UY4o0jXOqEqmH15J0yH8mnTcrmywL8Gi+BHV psDnIoZo8Yx618LROT/mV1Lqi8MQi9lTcQ/4NWlPF1ZMaJ7nRuzIQzsH9BfGt4awl0c9yF6kSUH5 gr5uziSzA6KyTWdq2Z+CdewGaJcYV7QuyNDv2nTsZvBN7XQs7fQLQ+5siCYe8bvSQJ9s8ZdaThOM WC4BKmZ5fXJBNQlQOfO46iYBJ64f3FO5aA1ok33pXfOuS+lDaLiq3fbqKxz8GGrILYNpP63Wx3PJ a3DQWhhYPN3p1sexfckDDooJUtMc3fH68d7Qr+UizSe4M/au/igGSvVkt5/IYNSlSs2EoWxcNjkv Ol0qACPlDFg++4zaAGZozTz2WwE+wbSbqBIBif9oWfjwCjNlEW+JwuB/VvwSxedFIIsv7kJ0tqc6 H4iwHBxlVYdVhvpXBSoBvjhqV0x4UYkIlSx9a+GqtNvLPisBf/6h3M5vCv+4b9uOFYPN7B5Ceo8g QoZcru6Mjh6vxvyaHXYA8oG2Fgbx1REDveR5hvo/wbiqulmzlO3aHWCpQZTrwULRIQCGB1nyjPaF GU/o69/KzGH2PLg0CtxO0LjJYulCZb0WVaoT9U1syKPY8KABffW+ZZT55jU0B1huAYmtHp99+L8H u/Q7s9fxojyhS1ODzR1Mv5gDCl851cFIedtVKJ+Tz2kI+7DgoatXhmxt7j+Y1Phw8nUQ0H79XNiI MpHKZ5gnxbFnpcHEUc4z/EpfDGFYQKbb3sZzRtc30NXfwXKbk5PWDugRJ86XJfYy5JNlpEAyJe7j 8CXbYNmZVfQ9dsgULx7yKtBCJxW00uwN+yQfDwXqKE7CVyeIsard7sdgdG6JhkPTjWS/GEo9db7+ YJd3Dly8S+xJo2iw0BAOiONunFpvR/fvaMzMgHi//HWJySRnyq6QYPTknXprFdGthrMot56x7j8T dQUi1Y1tYJvx4lSEhpSkzyDRoMDv1tOVF348VGguHN+hhTaQx8vRn+81Rol+YmibsGDDyJJrmFPn 28TP0hdPrPYgbDIvBGcCqdM1qpPDwJOHcNL87xETJrYIJL+fzSx96PoyBZUhHF2AsAT9pqnCHyDd 2h6mg27Z5VzeEpsDzCqT6s4WzU/jSQ7/2JASi9LvPSUJGMkj3WseLkV/rUW1NrmuJJSSZ7/jhmy0 lKHiCFZPR1y2ZpVsLK8bUnH7vJOtQ+cz+r8++jzOKio2hZbVI6vWVGkKRep4TWPELLARldQe2ZKy P1mKq9qloK4wKUr4KxuzmF7fzLmF2mw7vW3Nx1SnFMNnw4JLu8fEMyXLhEIFCYBNQ63CQYHgNUrX l+PxuE9JgZ4hfDmnwKhsJmTIjZ9aerWFZQUupPFSG3wn3Y5Ri2MF5G/BzDKSVFUSB+pWuBYAlIgk 27ag9i85ukXVh+hURoxQF9X0q1vbgzICLbgD0x2cqvfaoLkWYFReWANB9SHAF2DkpHzaTK1L9QBg ZB+frZCFIU9x2E15EvVJJIhHCElgCH/qboCdkO8+Sv6PmrJb+hQqWoE/lX7imUU6++l2z7WwBMpM Aw2hM3skJCfXmoDJxdXQSi+6Km6CLr7d9ZPEEpSF4JCIW/sDWcsd0XSWYlPQOJqyMSQoXeU26wnC fUxSnUJU1CzOoSUsh5BjDOLQj5FChcqMa3Z1m6cA975IXNwkGJsB+ftBY2w6ZHBzdooEbE35HgWZ DctAUgD+KqRoTdEDoAbDCAgL8xJV0mPHimQ0+K0ec5y4BbmMQr26HOT7jQQzA/oBL2l2DNW4wx7H 0WHeqtY2QK5InToU/WXl85mhUrzk5eIxf/3X2q94aUU4ZeYTFCalKQFknIvTbNG57TmYR9lra30s YSp3mGIYB8uv/XQcgY6sNvhaS9Q1iXirQL0b7NaBvxIwTWBU8oMC68msYj698uqG5KPDlPvLDb6w xGHCPrUaKU95TEwC3ctPUt3EdxMMBolxeuGT2iuWEUixeJ1CEPMmRy+13NFyvyvoDZ4nQmqX+dBX 0EcEOG8JAHAraHuI1dkdzi96EOAqiezD7PWLzR1BEt9OZpZzjrg8cQbN1S1B370wzzAQoSr9i4/p dSwt09sTquJNktVYMp6K2VK1OO8v0gIPfB/C9nBG68rYD5gW51Cqy6WmB42mneLXsqrOHpjhwBor EFq5LKPr+Vs7DxeecRZHHau1MM06WIRPnb+Cv0yyK+yj8/GDD1AKb7kj5SDdQHmNVwgNZO0jYYlM rzM3Yhg01tpTHonFe8n23rfwE0Y88CqIpze4vdTH7OHhEhBUIhRu3cD8OPnytJ6hbrjMbFVu+Kie wzGT3teF8OoJ3uRRKKNvVhfXE5R0JpJ3ImHlqv1fz8f3AJU33tWudO9q8zLUfCkcGcFXccYK9jbS Q/RwaD3U+ETgsQmUyIeV72CTIWaaDoU0qy/ioqU/QcqsBQEHbIhXZnWrx6Jub1iLFwrRBhW4KCdu mQiqQR0CwI1l0yZB46npovoktdA/XiFE5BuTTtQ+tioqnwFJGoT3TDPOGLBIx9FzMdsyVk6U2ID+ FtPXjE7KT6U7/A8Vsl7Li3BCy7rE6lLrn2CXDscfPCzmjutyh4WWlbwHdg9kalyqnisbjsFSyL1m j1IOJSyA7FC9BTOX0w03BheQE2x2ZsERk+BiERppudBZ7VVZzq4Zzj9z189Tw6c6U31BM/mReUzd E7XWcEDNu92KKlswSjpXsACnWbR6K7OPODCQIIv+nJvM5mWDgSV4V7gbsPwxZAoUmXitfipF3AIj zVKWhqjR0vV6NqlX4OO7JzFhX2mW6Lse7c565cP0C2NtFhXOhFnnRs/G7UcC3xxO6SfoRrwXkwsb ngFq6J2N5GH9YJe0Yz2KOX0vtL0kYm0CMGnjTns0tv6srgFx59ka+jWlpkZLd/J0sjR9aPj9TMcv wwKpeU4qlG/XY0ITQu73C/5YFPml7wArl8GsihcaV8tazk2mT/gNEJNK1prE+FLOeN367qzt1yFn AvG0TIQPgwoloMGnRFEDaWBjinHR6j0n2+BtCQDUFtFD8vv/xcOgOSm2374bsZy4pFwVCrsZKdWM dRtU7/eqCGqKWeu3WEweR/kZcFqXrKr8cZsvONZOaGiz2wP4AK6kfTs028omlUf8CaIS8ZCZIXYz l2c6SaqIE1HAK2U7fKoDQJYfZ4MDfVHvd+XNFMgOV0G10s9NYSWiDi6/sqoHu6SpahdeeTzYAbcb ekAlIlAWUzZOR+SbxO4aCWSE2C906y78XDETCC2TP+XfCa5Eh8LYRFIG92Y2+wgvz4tf23s2Hwmn qCMxpG831o8deAghrI1S/JGodHfXBWgDLcGs0lirlS9iD1x077Cgs2jMLoB4oYT8ADyTp7kqoyMh CaicwX/QLy3oFKFjxPrArzCct5+WdpFZYiOG1oqAFTnfw3E33Lv0wv3kvR/PA9lBv80mdW+baBUF B5wi/DglbcBvlRneu7fritl2crwI3s4PSJ2yZyxnkrpzxX/5HwCVgI5W8Y9iBHaIhm2xNx1exjKM D9zIazchamXOKC8hxdvmjtVmC/764ADFmfIM36OdLdWj9xaW8TxteeOmdW29tPVxYXW03H4X8ye5 YKkEpqTn6O4d/YGBsif52GYvLo9oPh+/Ni/Dq9Jee88LtYifCNL+d4H4wi9lE/xiKvCty0qQ4TGd wKjVDqrw1+iPIe8fe4XfGszX5Us/5k3yYgaOUJE0vwV4sf3eCatEjZr0nAxzs8PxEyKeNcaltyAT nkvL3Qy9fQ488WIh8OY2hSinzIdDkTjpBTdcdjuQ8VtN5xdFGwSs2YV0H3KPO/gHoS1uOmhrIi62 PhAaCi/1j62hgsbaR1HM/EcmMy7t7bGgHsCT1K6MBEQx9ntgXGcOfAnq1IOFfMx1pbwgWZ4LQOrZ cCaH0Rx0gYf+JlyQ3CQfVnUT4OpbP44D55gbKGy6gFChY4ZZTkrmoF7NuL/5rDHSqXs4tR5g8Pdf xamsfE0gi8+WYeRkl+iyyBN/aoTK5/axjKrStMxSVvo6kMiKJUkNO4DDl9RZqMZmFnof0OhC3uDA WhOxIc90sWXPD1AxU0o35lRWNtO1UFK3lNTXL3FUtBdIGm9p2rjyQ84dZMnxWhNnWjKqakiMouHH Ve+5OX2IPlvihK2wq8RTi9jAxjw+XQPlduGwLBOxwEVrZ03G1buuGvlouYt+xLQzIn1WQsXDNdy9 9ZBYsyMkFdJXr0z4iF4/iH8BRywLEofp6cHJwAcRZGJoR3V6y2QGDDfG+ItH1uTHCSnSVbRBtIR0 YqY3LZb1Tq8KnAGs5A79wFmtcUuw6Fwbsp/xIt+TFLdCefBN+Kz5gqCpuVDQB8YDiLos08A7f+Lm hALpmtUrn9aMO8eetYyJExYIBDjYmnBaU5EiRQN8l/D7hAH9Fu13atrFrgzAMWzjfwi3FRU+P91S yklHv01RkdMkKV/OKSRTgZIdTMatVoiVZvzcGfUq5NistNZIi18+AK4SRr0bT1FMex4w5Oatu0ws qxuPV5y0TORAFsYRcsw1/j4NeP2NBDw7dLmx/Ngu3jU9PXzcoGO+iKpWhi4DEzo2LRYZtXW8ZcGb YeE019trKzksyO4R+pEZczkf7gVy2Ua1h7sJ5T8/cuwmKhSfI0O/T/mwftyYU6gCM/ci9LMjSv+r MnGW2UtVZ5uNcAYZ6DIQmb3Vr1XxZEDy27agI/DZDZoyZr7GtNSA5tQIbChox3HlfOe8No8vzz+x aA1UZnQ6jwRxrJ+pxs8cMzT4MUJZRli/W1rowhiLa1uKweCdqKgDK4UUmNTaQaHkm7nnmykU0CT5 a57NK3wXN2U2GMgvqaMtxXpdS+SAxsqIsqgv8uqJ6CgPEcHOOgCgAXxNOOP1v8eN6SKR6oGgNsQB 0fbPfFu+BrOuNU7fq02312v/V31bJvKtkY+SEkvJE9XVauhlLX3RWsRMEM+spbkZmmOPaAJ6yqlr fAZ94QwJeE1+hyLlTGVDQ6xWtfeSvw5hG5+PWdmYRZKfHfn+EC8iUTE68ilabAlPXGAIp/7gtxqJ 4eKsQCja8fcWXP+XCkGq47MdXI3xMu8Fa0DxDPYy0nkQm0ycMMG8pJgA5AKe4XHQumAxTkNCz9va z6FlVcRDvGAjc4GrwTlS83g/0TithCk3Nkx222xg5xp9v9tttRE1qdx9l5ghjJPoC4cvIycAXcdV UYU7CIjRdkDeMKFQzvGvz/ZRU0KpYPngPPAl6vEYijufK33R6PkGXweZh6i7p2EWynHNLc2ouBZ3 jxsS2lE/NuhiUjBLR2WHGg6DMG8dyXjVKX007HUs3Oglx3xvrnN4aFuwb4WaZL4qNJLGSr+BxDuS YO0VcVKTM0OXXFVn3Nv6OmZEHi9hVLSrlcwStrtBCiR9dSb/tGJ3z784461W8FXZLj1AvaqVh3Nd KUOwFQFJh4KaXZ062n/KClc4KBTlVkQmyLF7qpFoejuGFuRFRhgTJjHIxrVBnQHSnr6SUwG7c9qH nt4Di/E36TacLZPJFMpZImtUniQEsDykewfeU7bc7dZaOqeoUz/Q4mUYpKg5b9+ipuHbQD4GzRC2 TRgWVWJeYsn19gfptJb3JfQqG4CVx6BXE8NcZcZsoZkbEPEED8Hmz7XUjlL+h1j8xs+2U9n10BI+ 3syTcH/sPPY8cXIh5yZVDALvNqfCQjJwVwxthxD66Nd7YlSqoEeBKbFt00l1FIbU6Yj2nV8I7+K4 OXbZxrNOzNvCCYkP+l6KinEI41UVGKlMOa/6/rANO+mAAH+5to42WqPzX1tN5NTd5CyBDV4zQFVj RD/yOi3XdTAOA8OHOftugdGooBG/2UljSiY5afAtuT1G1lkFrGUcBNx8V6fEiz1+GNPLHCul5ftH zppjQz4zyqsnBV5mX3zwG4ANMKmAIPyj5UAl0/l5s3L/G6aJF4slcq0qyO+vNE1BJQRd1QtOTEtQ /Umlb5pXFc3tmilhKSlh176Tv5H9YqTLI0OqdtSIXKqmqtOgcCQe/K3bTls3BBVXJ0YvYEsRszUj 0ue9IsekvcNgJi1ncwZeQKLn4jWuhIdfNOfpkdatjkYZFtWf1cVQXar4uIZWkL7oiWawIi8LJpJC +iL+y97nz+S/jKcXEszA3Jugs1SdXReVMgKMTVPiJ4xLasai4AgMAYNgWZkbT7NF4LnZafhwqWPS OxrdyYeVNI6oc25/aG+JLH6gfMiPWqKmGeEeM1zZBp2eoB8aS/Agi6flmGfGQIV7Rx1XToVoUDHd xf+JEfwvHCOC8+5AR0QsUvf7zuE1CS9ustXXhK8hf27SmR+J9QoplSvIJCiVC7yvM35bSQh2ZA7k g2SCbW2wR8lvqL9UMOMQvwzLZP973jzOYSpwHun3rwWhzt+Ai5ky8cKqP/7m3iXpNX4xF28Ixkjg /hdK6ce2Cg5XNtdztB85f1e9L6fyu8CEUAKZkAbpPpy6Z/JlKd6gyovRX5cJ8ndp5F0mAWCv0A4u lBUBxxpX6uWKluMY3zXs7DTULTchlo69wyK1/E0bAn4YBTvhD194peCCMFmbSYZiHFXwMuieQpqt Jm4F25HzXI+Qy8Odv7QSZUyDSMkP8c3mrK5OQBQdL3Wa6mKk45+/H7vWLT6UDQyz9RehCQPtAIGN pauBy8dhAsM065WJKWAgLNkSfBf0z8d7FW7czL9QtIWdxRA1av8UXuwufi6IQC6u+KO3rmZyp4R4 RQGcjN4auOApvhOUlVZtK1bBzH0TQXeuJmNXmzC5hhiS+VG4ndVVKys3WrQPp+W0hhm10B43/YpD lggGL+eMPgh/sXQDD0eRt/dAAKz9MLZHyL03tsohpXUu35/5exr157q+Tjia5jitxKoLX03v472O tNDtOblmFmF+STus61PEYRGeooeVYIPR54TL6ItESEJHhDtXecB3H3x/iGMzcwoy3UIP/BOWcdMz QssIcubTE1BqlGVZEPMqXGLoxGEWfFMekgKoGjB3cRSNDrbe24MMnVGPB1nV4OMarRBXFdxlLkap dxEcstx1b8u3MMX956R7HOobnNTII7dWcoRfzh4ksTsjCPfPCca+7zTj8tFZoYjUOFLo71C5cNgr KX1P4g0KNxjF/b1OrlG5hWdoFh96TNlCaqb+x4SNwfs9lgLjc+6Th+tENm53hOpEzFu1JgwHELIB xxCACCzAicynYmxYemPusjBTWOzpQIp8BVGkGcRNv/XGW+c5Vj8qnNkLCNJqbAKy3wiMigbCSIPF EMXxPiIGlv0Vq+6tPDb+AM64oJshb4Me+l+/HeFxldRVXmWvOOVCKsMqA5XtNpIvgMLyf07YhXtZ a1CHunfuk0921Gyb6TPmarF7DlCxcRNVTs3p54pG8ZeXzxPiNQ7G61h1Xe/0YhWEcZxdF0QtZkUE bpaeO1807LjZAnFFTiUym8t+nOwd3Cw8s/k86DFUXvEOwaz1pjP0GmHHOT5puBqIw+Mq+gNS+HR6 u8j1lpcy9NjdRlCKfgZI6adg1vuhNTVoGxbuOj7lwa1ThZ7W0MftvgQkCLjdydsLUO0S6P0YFNxe WQxJMTKCB35nh0RsnkK1rMM50bJ3DENlHcTsCS0WNbJ8bi0wKFj8hAs6j3YTCLJbmpinLjMRotqw k7HsSRxm7pOZH/QCSfp7yjaRx5la+1VpHXWAn5PloiR/4GRpG9w0yMxrkjTYc44gHFlfESgbfMpz WIFNmA91QbZTekQvhtkJF1J4uE2AHhuZArXe18XmM+gXUfaX6W0r2/DoLdz1idhABLpIB2O8GytS Nl30txoIaYoTo31Szk/a+b8JsnUEIKFX6GkH1OjCS9vn2CDPUO9rVQ4w3zQHsM/17FUalYni75pY qcR6p8rs5Zpg7Gw5DANrcv6GUFJzWBtxJ3McfMD+mFAvqZrPkglq+X2IU87pSP099SDOHwUe4ZS/ B51WodwisAlkSCweUkdgfg4kWo3uMLcgXHsuVgFQSTc1kJi9MfPYrrBa0Rsk4WdL80Ut3KPZAvvd rmgEzEevDibvy8cA3XmnYts3p6Ou+p45aGfAl4X+gIXOFMxBVZiDoIX/TWsMDSsexzoJsclSLVmo 9HtrucSOrGTtbLt9AHmsqblfXNGCYPyDPfx/5ekHnhEQ1uMHW2vyGzjn8OinotvXcISopmukLadb kRNFSgwudOk/wnRTSdn5zozDCA2DwUusHGH65qJuMvFRFqTuEGSReJIYudenOI/GhEHn7c1ddiFp pHinrw169Jx78R+LL+V20OvBU2ux1LXuTJ7zX8GJDqY4oOJl4xp0zU4tvOfdJpZb/AlLEmNk94vL YQQRkZQR21giIQjVYlUumJpBWZfFnhX/5XL2XezNlcG+9SPXWVlfOxhbPIwt8LR5NluIUheIiVss KbqnsBz31YqZS581iXIXJkYUL9RL+7tADJEr+zlJFooTEEtXmULY14NVBvGGpGqhB1jSaZEZn8h2 BD6EjurfZ/kmygSfxB6Fzp7K+UNAlirQ2ItXR/Ki8+RZvwtn1BBXvCc0aW8Bu6uLU4P/9lK+N1WC 3AWs+hyKusya3eQcgmgNMXns+gIcUKdA44JJWPv3KOCH8Ngv17ITyVEcdDQEKazah6apP3OrBfNK 7H7mlX3Owo/WUFYULohHZ9eyNUpuv54d7LNq1AKlQ20zNAXGeHl2fshQQuhuOA5uv6Do3dSAntA8 I926s1Vhb6eJq5omcHTMSgx1+6wfS8xA7Fkd20OQsjLz1qnt+3Yrd1p2z2IkQjFruqdSao/k9cY0 TLHgAAxBsXpjHTiSzit6Rvl4aTj/G3gSUdwX+75eTovhXiIIKx3gIiwoYxI5Yvx6n6avssD4GRXj Gy1hifUdlfT7MUeHd7JCLwAwJF/7C6oX67NFZXx4zdIx1WezuBEZtKpjLAJXSmXRLMksoNnxF2sG s/z9A6sH8IT4jdXB7GscZpBdyMGfYNHqWj2LPMKsMkMB9/HSBemFTWVd5uKGc4dax4wrjak4EGBo iEpvkUTIgjTSvO5IebCW227evP6SBuMTQLvhq96+JWybzVZfB83W9TQTft8I3yW/OPHw4h5tuwkv LKWpAgAHYOaZ2rlrY/W7SIjY2dL338WfnyrVie3BkRGL6Oa5Q1TS17lHT3EBU+cCiAK3dWzQzRut pTKoFNH/BnoeOIS9aGGVaEqupQy9hicHQGXrDQ/sNE4fFZotmdOkMiVmLOqXMShRWLcXrFbtmrtF Yf8fTZuUyDYjGYFZpBPqj2mUit23H357+du9zG8zZkAgIca63R6JbQgXMbP4x97N0Rvr4ZxYKaEU MWYH5T/rLXKYnd9tjpya+0b3PZbCb0RBaJfo47IyDdH8TTwoHSmXXGkvEXRcGSDqpF0H/qKDg5eV 5bhqlrSTXIYoEiPa0mT22VVpjwweFuNmhaRKMtIWz95c1J9vujJRIgMCQHWyppoBTBLGhlXLbd9L hTQLcxdGAaKsie6P3YrL8A9nAlDgtYlwTcM9oRNzAGR7ulP5AH583sUOdWNuoAwq2woW8QK57O2D llFos4in8B7+3xE55zJPfMsn8LZ2wAXXqodrAklaogvT6i6/S0TZi2rGd4ed+nZsgSl0ROgXFnUh 7QFPnEpnn1DS01v6bzA6n7cmRugXPWdaQeMpLKKP98b1zAvcPDZtIuwib1B73NDAlV1+wqodq/xl gsVBBGAb+KwRzHVTbw5P3BXKXJcXjdYoiATx6fVpTwgD56h9J9K5V8CusYGxNmdvGcpimWsmjrqz zwgSEDIGNHx95HR6y+K0hdBNKoSZS/+m+ymgvcQoGKEmASwfOGTybfIRtw4E62X7b1ZwP5AeC9ZL mzEk5gF4kSqPkVEPQXxvmctzaGomKY/rNC8/RKb97SA4/J0EPZq8x4hQB3qnItSqj5RWZlayAhri 8o1NpJZKcgwnMKv/pVaaQKUzHy3FbRQtYVvQkiD/Wp4rRV2qB/SQBhiyFFDby+wfNIoLyj0b99l4 kRIPpNI9U4DowI9F/X3VIOMzc/PZMjd6Y2EM8EvqTOJtJbPDbTeh0TdpkSn/yWpdN77KrYdowihW 9IQcYCKtaDwCY8vRExGhRG3z4XEBvnNmnhD5S0rEl6Tl1UY6fgKX5ilJAmZo/Bc9ptLXG8U+F8jU ZbEwThxg+liJIC+fpVg6BVxdE3qNCFdoBNbHfCNTchLRlBCTByjBjRRHjE74n11YgqcdutPECVIB BxYPaSJLcoexZTjCCxvXKOBZKam5KYpS3Ey898l67o0BV23sxsCMPfFVgzr94+0H5eXpslPaT1cL spgU6IvLCN8vA8G8v2lSUv+6FO1u0uANKc+WfKftXEgHakaD2v2582v/rxlWI1PuBw2JMweRWhEh 1WhUnnzrTjFPhuilZslVHBHJDhOmfQEc+WtqzJp05rwcnwM8hGVoDwdeSZEXWarBpSWnKJ3GLXqf c0uXNb8zmNLw0bU5uQnqg7yHuluh1rDHDQndq6jB/HpVwpzeccO6crunk3tEoi3QHs7yDVmPjOz0 CZUGR7GzuUtjDTFhm3o/jYVf/4aITxLdTF+Nb1Xp5jgcnnqcxZpWxpFCBjPdx8EGYprkynsO/Qok b1k461Z2YMZ7YNOLMNIdgyUjrw44ouSE37GUKwfx1s/tBuePpaFmquMRaMAszZbySZPVrYfWqg0S AwK9w4ZZbbN7upKS0oRiv1SU5JB13GPGGuXN+BRlSQCRSYHATRxDS70ketbKijoZOJ75waSp2kmM 9Jpwfkz10XyjyTcs0MVmU5lqyvFbADEK+45YaGDwIANExatg9vHFJq/stAmHjp44LpDntMvIjDoK oBBWfVpuZRbsZQYajsjY/VPvqw0760Q3GT//c1V1yvcTxjQBZl+2NwSEWkgOivKTyAT8rK3Bx76O FeScBoXKr6/+NzZjwewe39VQ1sjjtQyIRKPAmrNQO79cu8o6qqUt+FuE2FlY42i6tdj0sNkVYg45 D/AIgInkwssY7smU8Ha/anje552GU1Zx9mW32tF5/da27eby4BByr2Eig54L2o+7TCmYrzpK1r1L 0LQqGPNMu2LJS++w2ZSHBjGl2VXX42Lf9ADPTZf0Cq3bX/fkUpS+7C1yyEiIe65l/NzYMfWPYmsi 2qkHaZ2R39vNVVcUuBPrompU5YpkMHuhnBuovPnXSRbMJh6ReLEerNC+CWUbDpWJv+VzYbqhH5XF bm8BdEA7uMti7rQet1/MAcp5RIcH5CbERlOmiun08dK0FGHRM+YdP109LQ8ZXv4JjZn4uAoQff1m jdmhZSL5D8g7YxCR5+dPV/CDGt+MbduVL/JvWaaAdAq5vwm/eqtCy6tOdw/u+xT/7Ew/97Vbam1g FcL7fPXhx7DV6uBBId6TmnOTIoR4z7cQQ1sdIy0vIusz8dDGMBiGgUKPnHn/IislowG7CFFBTbJf DbxCYb3ut+eFT07a0vC2magPhcly/A7hpfZ5CxLjkww0cx8FM8buCeEFA4mv1jNy33qyj+5LQOxM K8DzTR9b5Z8GFBwjLx7MEIZw2peOk0PpWHj1Coq3U2KZvnb0TwG9z4jf7zOK1mXJ/yUui5MsN029 OC53SuS4VpOyJGyzShnl6xNJtDxBac0bUKtbhH3w9PAFT0s0IFVq+dH/J8iP2T2EByyll6VpR9On 1qRnfDk96l8DwT1RnTJ6KpOOWt1FiXoTbx1r7fnig6T7+pSGLXrBnb+fHQUrMK9CSX8xNVe6iJYX 9KaPqJFe6Jz6WeVGAzqWYkVCB8hcJ0rAWsO6Lcki6v67ioOvclPLV/e8ZqZCXhPj0XB9DQypKu0p JYge34w2O5ZyLqfGfxIAU3U0IaVlYHeY4CsYSVTu8hC5GSUu//ILRXJq98j7at+G9MQMt0M5IIvW VjZxEFgK16Xd55vKSuFnt+P/0NSjulFr9oLlQGFQfAMxJVOb7gDxMemCdM4X0AVEnWez/WknZoQg NAZ65ILzPBHg+zBPeftjuv6cL9v/m7D5zrMs9JqslSO3UtAlX4zvmCHx3UYhLTROvd+KGRLg24XV 1VTOjADodl2iZOs86CuXKUfUaofCgtnzla6+drb5quvn+A65EYkm83s7qon10uzrRF/dSJzsn4LE S2RZj3mXUV/862L6AJ5OqQuaSAm0utu82vai4efYSTRmT53KnhmkJ4f8axXPmTHWUvVxp0yNOSPm T2EWMnxgG+1FcPEt2j8zYCz6KJAIfN1voAo7cykU6T+8N3MSrvTHOnAoR8dDJGaUmvuofcannFS+ t3gEqCOmf+atYzN1RjVNaa2zybxHURQCBCl9W+kSpSHl/Y68wPezrjTrhatbd93xv9TRzZLA6lf3 VOtp7JbHu4UCqkHyEgDwoHpe2NmW84ws+cXSWwrfc+Rha/RLvMiKTTlop6KqAmiCvk3MBCBEupOY 62Ispp4ih5KHk9yi9F0+peeDxsacDxsq3mVJvY+nQ/mtWylJXhgamQvo5KHTEX3VBn6h+Uz+Aodg /tf2GaS5xGH4BjkdGrUte+0k6auYha7EAMdyNTc3a3xYqeSKpGo4TjTXXi5TMFcZdBtvtms2XKmi fFlh1PaZyBZVnHm4AorJzLwJz+WoQti6QibEzRJfy4dzoLefMVdo0C+Ktze8r36/eQOic/BGob1v GrzXwQiXinqqLujEzzFxjLfKHBe/10LgWsc0cHiDtRJr1aOiz7SEUu3NTSbct4awPywiGESWSCNY TbuOn6f0dHDtsmwPC9YTu3TA2W48Zioh4F/K75F6d9BwwrIH3ww4I6FpNdwQ/SUHsgEd57LAMJvG AEd4kahSxnmLGBlV+Y+ed3ftCaOKWtkM/PQv+Ub4iiaaaaLpletFqGSlAx6aJff+MyxiR5mKgTLZ T+xdC1BdirLSH8gtIQCJ8IJM+cGGb+djAVg/wOn+n0v1D99+F3n5pKr/y73Kf0TbUfGaxobopMVu McKV3cYtMoM1wHn+vOYfuBPRV9o8myyi4l1j9KFOXEy3ZlRBn8FELRtowIKTxT3Jdae4zOUiYlYG dg5/RQSbyyl/Sqluy8+O3C4GEtaGH47udKHG/ISf8gzFdDX9JbzfUaMsEgXIbI1vjyg1vNcWUrRs Lh8t6VEi2gbXRatQ5QYE0NLHcB1KNmAIPQ3jkjeo+RSi0KiMZdV5Y6cnch4lHcawJm3Z10UyNJkl Al96tl4PWTRxkf9n90o6mfHydU/EGNy+WGLTCRZ+en+f31+t3w7VsWTzPipV+MKB/TtaMCsuTySL tGG16lOL1GrJll8bfgi/bfz4683RwSkgp3wn7fzIVJB0+GYOwy4C1WEyUQzvXKZeZB/gPHFzbn7y aq+4CoBqxwXtezAPwGhtv6P46WI9bQKFc+U6CChcXuLGCkls76p3yrGC5Y2w0nheMnFNBEpthnMb Jj3HHVhz7xczxVRypXk/3W1x2EFRx0Ib2lAZwm+scy0GC+W7yr22tURRK7OKZyIpf6lQ85ba3teB j6MlK8zBsByhfiqWAmUAMPap0BdjLBGYF+01TpL2blMWtdLj7yj4/dOCLX88w59hnd7D9j8tNe5Y whPExhS0kh3jK/9TI8OmrAHx6jLZOAtmi5ARMGb2CUbfk9kvD7++PdEqMMXjE1XrQjdb75Z7dXDS TcOJcmjbogwUDj0EVKkvyhv5YDxsWlTI84Y2c2nZz3Co2X+9S/q0y21M7RoSnYk6P8HRBljtlE0y O+P/XoAwD9uw4jYAKuOp4vg0wmXqqICGlOLSglzy769llxM21G3c2E1bck6dqZ6pPhmjaw9j0HND hpp+OZLX5cJcWS9J5U/sUulCUMjhfE2XdctAhqLb3tRq0mFwhdCmd8X3ROKevGViSRX2FdtUhwRE 1J1fiUiBy28MXcydt0HBnS3U5bh5axgX/nxUXfMaaZcf8w3wJx3hjwPVat/rw7BVt9FH/SFZURgy UwDRLzx8IfESunlPQbl7ebIUxtFM0XZ10S0gan6al/XAVC7wopcoqfitXCvsu8VL9RLmCWO34j2x EVMNN/6n0epaDVk2hszcfhG8/IIJWB8Pd+4vGLzor6nHpqOHmaMpxc8NFI5Jk+GJt2/qS+aYpOvs s4LS7bHLMbs858VY3knuPifkXKj5Gx+bWs0KR7rJJ6mYsxwvsKX3MhjAfMopjhbNlG9aWWg8tHcb xY03d+BdQTDYsPlCzonZE+nBaQ26RLqf6277WdjzVAWVHhaBwtJLsZnxHiBD1fLZRIWLDGyAa9ih QaOz6W28rRtFsQELSH/yLAwlz+eZMkifXvkjl0M4uPxGU3cNtqu3v8MWeI7yeygYSsTNWPzRvXcd UVqbP9Wp107BjGjkJ2RUE0+MiIIObsMwRxK8X8RUA1ILcVffEdGlPbetqC+PLSlkY8RgagVM90mv 6LXt5WYKURy2qLTTtZTQDjxDKP8qb/NEx63aTiOSZbzDqHh15WcsrZszwSq5/j0A52s+cDq8hrxJ 3quS6bvFNlCp37AHMBgOi6L99FJ/WjuHi70aYEpfsQYIfCx3RmBTM3Bfssj262cR3SLyWsKmLZUM gqwIAoCYgSZ7wBQSdv5RkWbkRoLmfyLbgqaKhZmrBB7z9ENshG9qkkCzrmdGSKvIYjdwzc54p5fG 6j1iNWGUBFeSAoxKgXTtvVE0iYohlYWXuF9CfMFs03XTQFzgNGzokQpxiXXgLAvGpjFj3s37lH+x 7fosg8qMMXlJr3sH1eFMpjqWR4jy/CYHsoBfOOMIitkDiF/1Aw8ahJhJum/MQICEYMaY8knUeKbt xYAyvaNs18GTKt/drKRkbBA8ri3VP2A+o4DqhxCMPkABfz5Zv6feufumijbWHYbAQVMHI0vdlZPS pYkyX1UCq06FcN335B8FliJbU9VkOfOjIVOEoITu8/9eos48k+IjJ+plQjEszUVJj5O+xqRTnJk5 laAyTCjLtCwGdOD/TqEdp7ybSy1VQlfd4uSzadzl+IFJB6WhL2f/gTmrQfz/kGWh0z6cezFLXqeu dC9Cc/UdNgfioVAS8jKdR1VDPJH2vl6Mufd7TodLxEgveLFC+pUPcU5jgW+hK8Tm+EUiwdz3MMIP 5y1QVKFV+h7fDdlY9oyMTzaNNuCjF/Fkdi6XbobH5+kS9Bk0u1/FOeI47fWJduRmwDfQM04BReax sQUHCgoc1CtrqBM5sEBV5VVbM1doNjsJ70jkQQFAn3Vae2SWHFN5yjEFZ2T8dJpEmTODQGvX53re DIM/DM7Hm/G/cVuz/gAhY9crOxGi634yBE80q5P0pI7+CStYZ9d2HggD1/S/3YcrpUG9JrcOZCiw k6JfyF9UGzTAoCNKg1ukqrPWKTu9kDizCIQbntfMGyjXfNIfwkIDLIqTLrgSmVlgOZe1npoK5WlL qZw1fAbCtjZqas5u0L/3KcXGSoJiALqhxFETcGDr1YIlY6iff4wjDuje6sD0NM4vOYr+pNG1G2YF IYReuQGVcyWzvhVUQtZg8ICL7HoJ4tbR9Kh7ihE/ZYE+s084G6AkQv7qYxB2ZIFzHc2nFzQbm5sG u8qQHR97RXjmiUBf778sofNGlhDWr+X5kd9jd5VgmED+ehRVrOnsP8vqhTlPmE6+Gqs44yY+OvjH NtU6wRQ2oMo1ykhlvqahZb4Qb9e4hMpMcObimr7zc2oSATm1X5QYgwrhO93ueU1uswCLO9kanMKb yBn6Xut+74quwNJs5V2NCUrSTljHLkiho1yDyzoBML6ehdGKW2ftvgSm16z71H6ULTZ+verNHfIm CbQCuxAiudD4/J3H3yEVvNIelV3Ao3nz5/73M/oMCld81ApghUh68ZD1VJ8ZiilTyw7y+e3QcxN1 5bRsnyIoZIGoglRvm/k7g/MslfpEh42sw1qMzD+gYCMVV4qzWtiwor6hTvXFqywJ7IzNmhiDvRRx 1X8fzaTlpVnUoweodYqqXWWK1wJzkdsb9mTNBjM8vL5k4YptgTjpHZJwbtLZZ7JiVJ6tXXR/7ZOC PDhqK4uCKQjB/g7LnPcxsNTX39BLPm4QrurO2cb9lkjmNkyJVaHJx2AxiHJvA7Ri+rj2/atxf0Nh jY0ouogyCUKFz2z0zIqsrGqOMwqQVEH1dB+sbCzLDeVGlfEAJr+tlLj2lwxOaRZ5KJnY20+jSBEn jGvJPlRSunuSLRzJIa3cCvD9snIVwd9+5wikqPdZyUYjY8TuLeOwAEj5YSfbrBYom2PvvjusdZy6 xsUtojt1dQQ5zIJKzzVGOTb/TTOM+0XwoE8d2ViPBbvc6vbuWh1GokA987Pwlsdt831yr68WNfKR jDrn8r5a+TCaz2Efj7Aw4qKQDXrxXBdMKBwKFGXH69AOoD8rOCgQq0jFla/2scQq6g8ApyEJBCgS VXfuwj17O3CTJkARZrYMiCBxOtQTC7DaGsVAKFZdqZhe41oXIBquvTzE03Im3+59WAsOT+z6ctfD k7KWMmwS79UpKwQjqDfTlYhwmN3BPB0w4300Z8X/FB87zKAG0aUq8mzSHTaRvPNnCcfAErs5hPb5 tam+RW9puLgnOlSkyZuw+s83uxtEMtF85uOqsta35wj9/yqKTcTiTuVearOOcIk2tBnKKdLRlIz2 0MrqtIZzBE0VirWqiSiCLq2xQvHhVaczCul+7bkPktVx/fySY4csC18UZhC5hjnOIvghecbi0+mv 8idzTyUSTBS+dkhs0Iyrni0o/b7J9k48WfF3gqZUPCezXgwaDaxR70UA6xyi2H9VLCCD0c4Jo0hD +qiUFi3fsClgX0L3jN/cC4hj9mesvDz00elrpMAVeYO2S5wb1GFZ4wI0ILYJYfNzpPaBRE3Fq66c 8qsGXFZ3UxnL0r6YF8q+pp2kcTB0uEJj77TC/ku/h3K8fegy1bU4BgVWgxCn+ET4bbHrR0ACi58Z 5Gek30yIEmdE2wzi27FtpXyuqqQs+wMnnAK/EhWWAqIvxsocF6SOJnNHI655LxTu3fIdep2n4u6N UD1lEk6PNDMfID6uBhMfV5v35Jyyrsw3UxXkzr9JEbazqMU6Kw6MkugL9xU14js1zfRjYS9BJJQK fXIvL6ZFsvUzkQqW+4/Pb08Gy+QBtoBkHSofm5VM2EYkZSfY1lzNBCpEFwqouTRPKwkwFQGl96yr fKv819NnlvY0uUrup/prpu/3ooTBhUvHXVO1VpHrXWWSEBluXx7XtAI2DfaKBI5Vo8GxJygJ5XVc tH81a8aBNV/G9+DvwZMSdgbAXGs3EI/1RUZCg44GiaDNU2jvd/cytvbmVfy8gctqaJ7J43t7xBlA 4LIP5GYIyqvHKliF4JhfcQ5KRT2euL+5YmEUIOeTo7xGdxgo6D5+6PnsrHG7F7LfDFW2s+MvWZT1 ln3vHJvTAJVt2dzInVjH5HY0zNjCY2AhdZ7vrDgFcEoHSsesnLnZOditUvyyaDS4kcrHWeoXGqf7 WJ3tHFIG0bWqNDUgY56YDdlQbhRnOdDAmihbkzMT8fPLMaU3RLccPt8yEGmlAzplSpalLdi91tqQ GJffOlaFx+t1JEFW8I68Jc5VLtTkgZiOU/dApoF++FM1HPmMiCF1v5vuCnPlwCOlndzDZM6WCfft zqWKukvVumznCbTdKwysiNlbYjEqa/3yxePNPD8s5wkuNueBN5Yaaqe9jscPTxeQlImxr196NDyU /LMLsJTC9pViScN3Vh3fJ21b7Da6mAnvMW8Udhl3HkJNwckqn+pNKtDCskoIsEJ2M3mzntyU99mh h5BKmxs7z0MYflR32pyFfw/R9+Q5YnqbTuZNiEzAH2OkV2zQ63KMhpNOYR6PWl57bCGonXhLtDB6 hQDFqVrDdUTPu0ntWlqf+6Z/H/BG7y1R1Nh1Lgoam+IfWcxi2lk6slOiU+0zT6dRtb8eeXT0RA31 9zeuAyOYVXlNHvKhQV3Fc2Pa9Yhszrz757Zv9t+ixFP9Lmfvvpfe36Z5G40ifpEBzCmRtagTP9V2 dwYQeulHHNSeQZM7Wm3v1qMbSEDLUOX2T2wtTQxrFNEmoWbKp800rOrogQY/gKE3KNWcXwRosyx6 +sx1azYPM7+3EgikAkPjH4j+z9LU1zLPdkCbNYWRM8HAB5qTZ6Im5vk8km2ZOtEdLmcTl7rlrSyQ dm4n0u/bI079LXvDrH1+y6XROpzCtOAN3RY768YPBgxwyHd+70NTyD4/GrQ8vFndPHrPUhFQwP+0 nEcAHxjilK+vjrS0zOopsVpG8tmoBH76ElbinLfZldhD+Rw8FLZC+SzPuV9R+/uYMvV2mu+vT5tj MoztyBmx+70uDhbzm+Psimgp1au3PBTVTqg11CiEBO/Sng8XMZ39vUimCA84dBB/GMW6wnmyNzOd Pbu1CmaxhxEY53T9UuXxmO8NItryNGWXAu5rjt/CIR/zLQTeue5L9F6/2n2PvCdFZGm/itvjVaCY pFDMdWNMr9kcSUs0q0Z/ln3Gir1VtqAvGFxldlU+gMsDQ8/mEH/j+gtKjBKddJ0ELYMDmFFEA8Kv Z4clkx04XLdUeN+HEaLWexNWJWkH4HjHwKpMG65NEixkTFguHnqFsAvs6CAq/rnApmEd4oMypFl8 4hpn3G4SyOnFjxmfwffSXBiRQFjc2o0UoYMPMvjXZ7Ys7gsWGkdAPwSjqXvbjY7nBLsVipCOJz5i n2G37Bpf8tEPCr5PIlhijo+f4NYYS64yWUp0YYp9CDb/OSwqv5+3nhdDcAHBMvE8eQvBMIKtgqkC dDBKGrcV6cMO57dxxbJinbZw+lz9TYQo/0TyoM1ZBUCaSb12TM97mVz93XU+cpk8KiuWx5swso8E F/ERMC7jYeitRbDnCrZUbkXJU/jAlePXVJ8gIN2Dh0MV/XaEwneLVTw3CIhhlsbRBc/NcibRB9Hy 3O6iUojRMbEv6WvyutGYihbIfNfo8RMTDipqLWA9o7YHL+NIw/mZTssmtE7HcESC3hXyqBuJKqUb p1nfyqjAbe1oTdSap1CYR1m6ouWFuE4Ydhaa2TQM8B47+sgFA8LyXJ+DBlu3rf9PGtSe96pgkRnF /+G2ZW5bXC5WPjTqvt06kFSLmcyl0xwwLVTifD9NgnZlZefazjmx9HJ6vtzBeF5fYkv0+gSPM/vn OFmd5QtNBT948r8uKt2Cc607hQSZ87vcNyxDl9ppzEHVlf7rP64xjdHWXdM25xLmbo5m14HIFzGN PsAsI95FzJZEGB+QdpgubCpBT/JoyZOLmcSfEld4FemYX2bDMTCoyINA9Qq6CekyFw7erTplq67H 0u6HuO106uHdlmF7SX+W1kZalQnZje12wDLXDVXq1ioSEs3aa3lGjB7lkQQ80f5ZeTdws43+pui9 Yq+Wvo3IS7tk9osYHyOqWWvVI3D5ESdMY6YS4/SPi28DROOAYjs6gFpADXEEqI73z84cVya9R57c 0641hVOx8YRPtl+7FwUl99IaeMsOHRagkGKf3ciOdhJA8d7Vq6tEBuwc4i4TjsbB9vxz/AyBCpTW e2wIJ1VFEyynXzifLqtc/xUJ3BrkePGFeV1uwa6jo4H27D98D0AL11244wX7ASQVRTuGp906q4m7 jj+gHNwJltyOM9X+aV/9DmUmhn4GPNcANvNO4c3GA0NOJwthdhn5xxT9la06GcCBYXzMBEMw8pUQ fzlbEzKRP5IWYZ4BxSGj0zj8YRTSK41JQqtrXjHaxCBmng9O+velfgbG55xsvyjSsR4QXqOcdVKR xpJjynHyr5g0aK1spdcsMeLYQsBEm6vGgcN3qw1hCzsSkvLqer6QnBcQEvw2Ho50uuGJyTKWKrYh TH0xxZU8Iq1FkQr9JeSmeozU/vySwv6t9wjTpaVsHGi/MtgIx5PYRRQ7t/CN+7AgulFuQbGaTwI6 vtKB/qLrx5YGbTUn2cI/lEZqstmPQa3+qOJiiPMJmOZBt8oOAbwbjVKFL+FVsqsIMtUTwdthUZLw bM+EJFVM2vfchH31w8e0pQKmZhBaXQ5/kUWofZoa5ccc4cG3PkWgttiSrl5dkgtdoW2lUl707heE /o5hIOEdJcQ5cr18UiJQwdn5JpnElfZt7hkBhKUg+PvevJ3rSa5WPmcZCYZt+xZ1gQ5y4qCRfyry ExDt8mUS7xLg+ImML8TFwxJWi4mZ60c8dL88VzOBvZ/+dw66fIb3rg6e3+MWxoYnb9tzGY/1+vdL yLvapZ4Wjvq5H4aSB7ltqKO19gMPjjsItVyHHaA3CTGzFVIFipOuotmeLycYHsqsIx+uq4tniUe9 8hFOVSVi43rMkrmRTTygJPmc0tdTt4i0J8Mrxq5hhI+I3hLMIPBy8eFGb+XziVTgiJstUTqSdBVE bcSqgDRGMt7Su0NIa1o7g/I9rJpG1cOeWODpX4SsqsAdPwwwOeO8pQ3mDNNAPYwIV/nJJxt5880t GTeqLMoj+XUbwFNuVRSEH3XxP1G4njL0QxtQIOA4Cs+T1bqXTJJaMTy3UDIbGmR9v4eBOlDFHdfg 65u9R8Xs8ANZoq0VA5yka9tH4AkdfUgXB5zrUm8EjUfHpvj3wUVd/Xc+cgnFintorQC5eoKSRLiQ jDm0LZDBLuLIf6WWBE6ri5/lBunR286PMlZZEgxQ7F+jD4Bjpy2No34rwSyi6V/ryndtzAjoehkD AD8ObxiZwhyWGwip5ik8Cy8WnzNC9Y+RFSa9Orxa/E3YhcSjy3wi9Fs3OvkcFTQktBpkKlGIokJf W1gPse3lbiDCztZlnkWm+UeA2bcInnUtY7DxOIMIWu6MNV10rSUPZxog+DrU/JGrCkUk5mvD9lA+ v+C8/S65h+HboZNQ4tZ5uX+PVet6REvS+tQyJJzaJed2i025ph1dam2xq9EXh2ftw/kk5kCn/ZRw Yi/oCxkdeXLFk1/SwkGzns9DkgztiatTyExQsSKCu726BbbTtfC8X1jBvZ0ZHcNEF+1Ow6JSQ7pc L/8aZj3IV8Uqb207VZP48+hSqH4YlVTEHF7z3SjN6urhrjSFSzTGznqB3yBdlXaULW4LR3hnHT9P q924zDDZTWqdU6rYS//utU/UDYG6MGSdRAAjCc3JJWRVxSYI8xdb7Z1IfattMBejUu8eQiotY7cH Q9HbsOaNjNAhpwSVQUcMDjwvjdTHGDJTOzHH52N004a6tFaKU+MVCJ9g1msrsa+44K0I8C1oS+WS a9Rmm1rkBbQXyY47vXE9/jc/aB8x+PCQdvATa71vf7zSWTQj31791xLkptbDSI5vBuiDRxADwDQC maMC2S7IVclqLURiH4HnPfMWwt/XJnsX3SIHcsnIaCRDa6SLxRwjVzQ33eT787GAy7kly3bfuLlv Y+VT4ozoQ02a6FNro+2dQi9iHsmFZSAEMbJT0u0qiIiGktUSWfgc/SzPBohq8tCgrMcorar7sm/5 NfIPa0/wg/gS3XxYUOu5OljMUvpw65zBsnzmX503IKmUTcXH5a6lC+euPINkgz2858EwnTVThfnm c6h3MvsZPV0CbpQioLwkvPhY978trMKtvdda/tTym+31GGrAmMks8vE+6i4OKdAyoq1FJhe/heVm TBrthcBqHxA15sHz22Ei/SGtXNRTNvr3lmhrw+PSB8w607UuF2VDQKMgeTeaoBetWZtluYwgBuBy phFxYS5ZsGTQMHOcuH2KXS4QOiWVFlYu7CRVBy30R0gvTwIptwPJ8S9MYmpKGfZt747RlFV2Dcfy P5sGtQMud0/tq5DyI1lUbM5XFnqR2Nttsa8hww3vQHJYntYvwxmS04743sPmBwHUnJyAXm/oIgdD 8cefMZRAlIffotijA1NtzhpUk5OHn0oO+nrrtLuiG8n8x2zSSjXwm8DpeLe8ZNH0DmNNoCUxO69V qviyAsZqw3T0Aop9YaVG9J3EJDpYddyEJRTKRLpnpJAPkXqaXgWvKJxLtaNC1vP+Whl3kiQugu/q V4kEY+0ZSUKT8ahmpfYjqY7ZMNfDy50AuxzvD9fkk6T3+q8gk8qzZKAoHWYUdkfjGwyzyrb4jCx3 E/4QUrN+0VQZ6L/ULr7H9LKMXCLP9oGUM0AegsLbtbzZWm4/5tV9BwVC3CU8xoq3Tmai9B6anqb+ yMGpsW87HVdx4pkjSiqCGL3fXzEtnFCkgxXZ/LIa7lXqPbMznsIDc5adSOUjwW0maOfSH8gxmtIp L0UvNmxmdpXAC9Zo/SCPXq9aU3Kx6a1K+4oC0fITlXrRFyxu6r/XSz+w+YRrDECuSnogQlb+SJQI 1USie9MuwI6+tRzc3503YWrMsfdoHoafpzRRSHA+nhyFp17X4bphCRWuBpRvp9eIG700oIVRwyg/ RUNnPSsjR32TMAaXvgXo1pHOARSNrpB7mp4MsihuDcFMrjtez7PoEqJmVu8PtBUNwEZnVV+e08WN LJjL4Zwny2PSbz5ipLmGr5IRYiJkGbFcE2fVlu1Y0rfu2Y/FTDRGYB+1FFbGKPNYw+gRYSDrNu7G Sz4I80APjqwiVHvbHS6U37CVp+rHrhdsFpNO39EJV8P3/Nf5qUfpc6ejLyZdde+l7nhCTYG76FKZ O6viGy3EylIjrhrsTMad2nvUcG085Eq7N9Q7A582Sx2tqK4nAPzMMsgj9oJ8gyp2+ksgc/80Cshf hoB0qOm27ui9J5PNzpk7myygU3fsYwpMqQifguVuiaxmBgTm/Lw20gSZAyTjVPLldxWSscS4J6FI rZ09FCG6KQ0FaH1OXiP0tBrwWG6j2akXR+HshshZ/Y93nnp1XebWzekeG518HnWGsuHAM5rqvF9/ EpMq0IcHCi63N7mgZ5ntgQbVsfkqkd2F8OMo7jR2n/rBk4n5r7zGBHcnhSE0DdtXwp9bLjx6cLZh FzUNcOZALSnU7o4iJHOoHso3sNKR02FAymVXHUPJWABDb6vJS258QfH0uQLt9twGoYW4a6F6y+hj zHroE9W471dWBwwWMpcrxMzN2R4XZxDW1Kj/ANfkQfYh5vVlNe/6qF+Pimx2guna4Av4l1tGE7b4 qFWVj/ZdhNk8xZF6pIxKVgnTp8JHuid/VI5Ai6m6gfFF/SOmXD5ISjg2WJnZjkfJHMLSaKMYjX+6 GzzQ1yYYJT7GSJ3FQV/wKMetE64QXFEDRx9BaLyDAxRQHPTddV6rB9aPGIXzs5BBzVcpIKvR0YyU wbyyBQIhMKe6yjpMgCSpitvedcrtmRWCRQRW7Unnf1gPuVl2qmLxSDa3t+Z1xsceQyeTof8RFtGV ksnpooRSjYQqLLxIAJQcOn8aDMAlnaigUGExnB8UBygSsFf11VnyT5RMOcQzmvs+Ou9VO9zlE+zJ 6GbUxXWIeAehRgZgT8wWrn9VC3yf1sDhSAehZSCSopVIYE0K+CUfDmnZS/jW2AotfILDw5Z8ZNZP g8TYP28l3s1R3ottUmrZ++d0uvhLn3DCjXKLuGHeEL7r7gGT755230/ZTQ9N69DYmkFNbojnyWjT oC0UoUB0ZyF7jfFGlQv4nXQ8+l0CZrn+1ClxafB5AHEyl4UCheNQ4ad9viAzUflZ6XWkl7IP3qDT 5NNo4xQBNbKLcTsW/uYmlKgPf3cSax6wt6ymOL6VwcvmEjl/C4qZw9BiI1U4/xzuP8UGH5lEljZS ltsBQGKeBKJ/w8IHOVaNmLC7hsjh5hy3xXqLnMXL6FfEUr0G4xcRbwCdh90AfoRTMvfDFdQ/oJYt hRs09Ewxfj/xHVK8Rm3Q8xPEGu1QDtra/+MLfCIgnj3KR/bcWpXP2Y9Z7XeHkEFy2f9xoX/+fLUc O0tujZHh+dvVGwGNFEaL4V70wlhh6r3ISwmMV/RcpiJZvxBXU3FgoD/cUgIY8UHX/dYNLTNp0h+H FKRxMfrd5jLG7tx/w9i0g7aHKyHePedRYjcd80luxagLD6SpZKkK1qsMxHEMwQSz6pEyPs2xHDIw OirBJVpCbSrs/NCrb4d4j8wgQcLguo6E6BMWCKr+CGhk8zcff/DCy7wm6b+JNuJVMX7VnXuh7J+S oNG7cqAywYloXdgHh5i1QEaDfTypKYIZ67rFpr1+dmlquiO9daqUgZ1/Dy8GgJKv0QsRG3yrfPmn 2JuPIPFpMEBiE/b0z3ePXNOu/Q+72tnkbRTFJgC5mh6nAU4Ao4dcG/MPswHhaEI2S1PDtqMf9LgF Smg6dkTuNjp9YsvySyI3h/UhUth9Io1dNySHC7+LMyfPUjHT60YTPGZeyeZjQJGlZ/OyrPonfMSD 9DZ8TPOFg8oF5hXZRP6+nbaR72mx/s16FvZlNF0hGix4+VGsMnwyVumFM5vQsIpNhO4AtGJ5RQKo jyg9gmjxVrsdmXuykaYnbsH4ndnB6b2YsfCnzwrsf8bDTbIhI+meN4UTejOtwSNSQGw4PakWiHsJ H6o5CP7GqvtcZBp6a+OH1h8fEweuPwXFiDG4zIQFmGDhpCr+XSUoc3aUCoZaroSJVpuTWoS4LeoQ +06ZvA+VNZnlwOqpoGm/NxfTR3gr+2DszLCdplt6yyjxo31DgJNcTJGOyxlB+pn7ra7xlm7wUEzE LSDWABKvzLNytUqfe+Mem6ULBah5GGz6biJzQ1wN2XnTCzZxYkzCIgPDm2FkFizeHn6v/xB15HYe OcdyoCXooVzz2ZSn3B+VpYX/8X78GvvJ6lHhOkvKzxy8vSO0P8x83FJ6K0e0w4nk1yrq6oTX5neW uTfHfcXqqFgm9GvHE0HB8jWTDoDHppHPKbKmeUE8m9crFmU1Hkybmlhhxa/WteMXXkzK9gNX2Aaz +urvF1jA+9msrnh0Bj9avqPTelYH/Dxbgysyxh6q/AdpOJyG2AYZRdmsCVhD0ickEEMgEZgUyXYA gOQXPUj5c4ij1yqqTpLvo2deEYA8Ul3H28l0YLEIqWcVz2Y197fTIwrOk1rokhcxSybm33wUZGmG 1w+lApcLwG1ZkSOqnARmbaGdeokSTHQffh9PKuKM1MMWdGxd52SMocrOofwsKDvluWucQb9FyYt6 lK1AXfp5r6Asjc+qk+Du/aC4Sn16hTzDz7PatH1pzIjLtPnsAO41EBqYjSTWgnEkA0div+/e8pvv 9xgSlCvl0OLDS09lC74pLP9/+EY105wmsIniqnLxzcPUfy/mjiBqGX35ZlrrlXX7S66tWBdy2s8w /7TC8RzJUWpP+66w8pYZP6j3pEu2qcwRLWFf/miDAJX2EI3bFcxPAlyBDPnnN+XtiUi0/BfvXA5o 3IwLpfPErnXLGfgLQM2akpKLDO4t7TeQdjctqx09KQ3TSiPk6n/VxQFQP1THIzgdSAredweCJjA+ A1pN4Qy8XPhMMy7BmkpRlXnsEHVEl6sS6IzKYFDjGLcWWUwkuIkHwAWjy872rZiOXHel/rhh/xKM HgMXd66aNTkMJYGSycnrj3MbWnVhABtPvWCztYiCrKn8O1WPwk5GDzFfAlMMif7k1lC2KpBTpmvP y950ZiO2GF8Y3S4SSkM8qjmfiWdCcBbtrKzTYBg1Y8h+a2oby4hz5hrI8LvKqMXWt3bSvvLewiCr 1YwH3Vazdf6MBFAzX+CBR+c151bhE3rcA/ElqHgg/2kdKNNz+52kwceULYdFgZK0cfND4XaqSLwM mJcwmt7/cXJIea9uw9UT/DOOQcPN2StfNOlsXoYzlYgxcv/uzJGxVD0a3knQ/Am9+tVinR1zQ4rs bk/1SBf0vvEBYMFJBRZtEzzQXWOrCw3bE8HDflaAxw+WDZ4pBzPGCR11GAvajR/YDTuK+dABdl/U qbYtAXvrwYjEbmhNpLyusaHTiM5uV+NY49m9zC4Xq+vuTeV9M5xPR0AEjUg/3YW2SKTDsWNN+l6e BKBsRCU+9+kb5DKP5uiJrTu7VUeCV1WxCFO+PqY0kbadZ6CmFdM0Xh8LKoinntzCjLNLdQiMdK4y NMVlHBlquxbHkML6LaTo8s/OZ7TpbYZLuZgfzrfPCXSCsWjH7RlPg1VeMJL3p8zKzdulhytlzptt FRIQ/zrCJqaVZXYYBRTiif84bywRjNIPACh+77lp5UQi0Vv3UuO2mA+PO5IvgBv6LdNVpXiq3zKr SEocwM6EaPoUFtEOBVe6qfRans3I6RTkT/KOOY/nTEBmO30g8VrtELEXVARD3J6dH2SGoieIx6RC AGevjulys8FMgCM4lb3D2zp5fOb7uK4KJVCmzKzZ0DifbZ7zufZrqglddOf9d1VgvD4RC5QoOnk/ 4AheXzyHClb0J5VqxFjJCj2sKIimwE8T8ez4TwTYIgIhW5fnFjucEdABr7XCg8HOL2BmG1Cyzi39 8vFCromlZ74OmQAeTxApeBCrN/4Vn4OA2lzz2OgB5WBP0T6CuK1Do0zWetgydX1d0KQL96m4+gyO IWThMCNMqqkjK4/YuviGxiYl05ViJIXpb/h4xtmmpVpGoTwx2wLommpJ1RdTzXbS63ZYAwuCVn95 e1UZ3kP3vxMD+1ZqODq+mez+1DmjkvypZvSQa5U7ppG+jDxx8Xs9yf0W/9OvkHakCWNfJQFEV1ek TE1YNex7abB9o+RJYbAoi1Ov61xJacui1Ecp5eXi1it9Th0PrmM2eDkLJeSO0ai9Bwos/FLzPP3B X/qxBHBu+diyB8wIulrYZHcThQ0KpqajwM6/4pS1NYSkx4XATOwDL3ZprnBCQZwwhlEyHiX2HiIU xwoBw5SEWv0BujXqbj4scoIdIoTe+XJRKI8+vMLeEbErvpfVgDtcg/LQfsJgKQhlA8vqTCEB3qyl Jgi6OF+e9HC3HjY1CjiSASaO7D8stKOzXI+AdTRHXXk3D1M0r9gXwaJj932BgtCnfpRdtClZoM7N c+RlIk04KsYdh/vsXxM3hYYxjV6cyu04dzghDO2/wzhx1Q/CZu/4mK+6tDXm4VfJXyj0iEk9DCmQ D1gqgm4qxZm+Kw39sLjqLj1bOkgw35ynya4suxMUwsLuBZR/xIo4vA0FyV13e+Xt78KoYpnTBL8O TYVpP79iWDintj99kqBf1kR4CVxljoJ1lJKIZj2DvprX3jiQxVwlMXSwRm3CzGRnYYoVopiWzU9m FYjRhUWWNrTKALMIuA1/EhiKsKsJSZTCYVQygvXwwGCGLPjNd5PMYPN8k0PifyB56DwXuPyNgI9a ErOfBM6Af/llkaD8OnwO6XG2Pggu7nQIEjWpyWsplu7LIU1adooqClXGYkydYVWghVDfB8Y6X/Ao TAPwKYmcGq0YDWu3+2Ddt1S3dvq1yUyEWpQLpq+XNh8NdM0oXkpx+4r8PfoTBpdHRj3r+srgyzqY XLKmgl6boYdZzHFMuDlytqH6D2IZMtOdTr3yp0K1d6Ph0HjQ8yP/R7Y2SHc6O872AJePAHymIdv3 KVYHRWOz80SiZ9HsQWnpzI41iZXg5BGzcPNeLmrDT/AgqcXwz4gjvqnaxvE5mJSZrcgXf3cQFqXl tmSqYRDpAUAn3Qyjr1sfNyC0O12qSzM5UG2oj/adr+948CaNVwHeBpICbECZw1Y+NjCM3tgifu1J ZegQCo/WUO1OnP+ECAWTYUWiG9XA3BFHAiUhLgSazZDN+ceyFOpYxvL3sT9gML2pupp1j97hTd+6 Rb4hzGbejHjdeNtYSju9K3xffVGER4SnxM4avcD4aXSeVfcx/3DylTLDvRVMqVsNft2M/5Ca5yE5 O5oQduVxHpgBU7s+/M//Vw3ZArPOSgM3wxH4Wj+DxsjCU7PZlep1MgtN1W0EgKlqSqSR82Vs+l6M duOdmaiu8iB146oD26pDd4Y/CNhGXtH4CLy2/ZhzVx0FpQsTJFCRp7wgG1yoToiZsJQn1Rawzem2 PzhfQ49Q7+GJYmpWPpC1/ksponLGsqvnYRdxgiNo6S+1wgMh4Z8z5TH9C3MxVGIBE7B72Ws/Pw+L /nkEDhwqR+t3pwqiUgnxP/Otzs2+d1ADaJlACjGbSuABtHgaAgA4vYJC8co4X/+9tEFE0N7Co7+f J9NdbrUciFrSJ49A8BkZ7DxIfBOf+Gwrg1D7gOGfgUr7n2RgRxABqqOwB0qd1dNVU+K3J+SnB665 CBoXQrnh9OEkQ9xd06ulPpPAXZ3klDNS/vmMCvuAJy0Ri3+ZFeAEs2O503f3mEe9avZ6FKQK2SIn CHTrDxJ4Nwcvg+leJKVSvugH5+RFQix9AGrQEeXgbitsypR862ZToODFQhdsIE19+mKdT3jMb7C/ vI/laB+o939JIKaWninaOU4lXbIxDJnbSvJX6P214urNRqhUdoF0h4DCaSnISxckPXQEuKnIDFjX jqLR1e5b2hJpXNaevKm+/yvUAO7qM/arVE8GxSFFuzZ3y4ejEeawsY9vKagYwyeXfZeBQtZdbjbU NkKvkz2FZv1NBUHoQNxqBqLxUO2FkemCr/pxlCGPXDP8S1ogBc2w/jA750KwzylpdUDjPkkXC3B+ IFg9H48RBe2Z47TjZQgULw0saLDaqyMVETEDaMDngePe8+JKeGKwEZXn4sGlRZpcG+llrQ1lbdd5 k49gGbhQAW/PM8/j8K/LLPy+xA+rArwo9vOXkrnISwIm6wsHDV+txR3wWamTDgy7LFmUd8sRnknI DOwZeXh2l5tj9NMB7WWz9wu28FM8ZBLzwvGtamDsRPzWm2Wqgx+dawnlKiun8+7u4+/TUiRVqGt9 4Hv4mvdihLdr+OeTe2fZUySMPSsyVf3XpQ+OS+ymg/aj4AJUYJylbAnUu49txEh5u7l9K7eIQe7/ VWApE2Hk8lnxXxYPy6ZTHkyVwef+Glp4i2HJuqYvbX43rTGr1Ht9GgaRxFbwE7f9sxvzUBweInG6 ru7oNXG2DEpyJ+TJteVTk58PCl/6DttwP3+YD+nLJqAVHQo4VQFYU2O1gB2GmaCtIPuCX7Pviu/L gmLVyn/nv4tQgMr+qzNNSdWPS1helnDdTsTvaMolb8NXBSvDFv3w5Rjsx2X1tSlgieQfeasczAhU 2w/UHtkMfHIRlNC/gzk9d+nWw8PK5m8McX0ywlYESO0WstEzVhqB4goD/esXoq6jn7egE7Kra+XB 8fo455w/sq4LGKJgYLlCZapmasmATpr9HL8lYWzxOpTePo//nBeowaxFp0IJVL+3+6jA0kHaK7An 1urXYLmiSq1lHJeiGkKH/Gg5QBopE9gj6phiHqXwH2xddjvyAXD8wxNHfX5GYAKAtwyEVZ2zJgu7 HY1+UA3DX3DmNYjFWin/xkvcc5FVd9p/irL484LoFhGiuNqaN01ZABEYGmFj5OsKdRYjfT+OqvyJ CDhKVJmRWDmdRrpcHRkLVpeZAUYA/BJT1tskLx5sW2DdOsQt3/P5n8BDgd4pcFtltjuhZcwIS/v/ C26uHdIyUq8crHwYwyZc69FsF7s0O6p7CMNkpgAJ/XVygijWTB3EiAmP8Girw39OeWyZKsTgJqlw AiLz8XDoOtVHUwp68spLMp+jKXrix+G3NHTXLSmvldAys2pMyH3Lavav5qnrXpZ4APt9NkDUPtYI p2/5JXZfB/w2V/EN5xsM1S2GvX5zN+rmAQCnLQokoqbT3o+q+m0ANqu291nuyPu7nRETnUIpdRJO k9l26vKPluIf9t9QSie+ncgpga8PK44ZPkU5FawSsC3RvX4Q2IVfpm3CKGDTG4OedK9Gld5CSY1e 2OV2qrzCvudbsqsgkHc9EyPaXLNxyUWuEYERVUFpCWVuw6QDzuGc6ZWIqGSaoGrVuBlPimTLe0di coUHB0LvFKQlk6XI1Hy/MDFR2QCF274oB60uXCypCIO/8LSpeXnZGVmOSnIxnXkMlpL4RF4IWfTN Suax+LUVBly8t2FRRf2MYuvkkFi6nAIU/rr4Ei9Qz7Nsu0m1CQI4jZY6M+2ByAGdsq1Y8sewyssW B58xgp41jJhQ5d5LDax337cwnw4YHYRbSbuzYyQEDRP5OHWNTRzVZYtFED1TPRr1c1I1s6PfrXzW z3IaCExA5UMhWt0s9Dkk14KAi+EtIlHMmS2E8hE42QYvRw73PF3YWGwjerUEy/HaWCahguQHhypf vrFu/wXLt1VsROTltOJ66+7F3s+7tBJkSuiZVx6nwba7+ccHRL9RctRsp08P/WZvbgDoauYtmm47 iLnRLYoFbJK14oqCvuLOiPD1JAFS6Ox3hbS+HN+bDZiti0OgQdDpsHufemeT82MpxSkBRARse0Vn /rm9R8TVxbv1ylYtPVQamUJtk8/4RHoDjHF5uzQVT1NXJzA7ykkL50lCDik01ylRnSkgblAxsLB6 gdffz+q8gMtrnh8dFu33ToBxiExYbbTySG/FusIGGXeQwRA/q5p2IThcDv0b6dKT5ddWvOaSxF5J F6GjUWpSm+3Oyxwd3T630AnJuvoEAzYagnbs5/j/tAXJfw82ETMW+ZhtvnmvGW6Qup4lZTvp0RBx 02i9oZzDpuyuOFWzjeRCa6ksEHK6hy4JTzdj1wCqhdq0DeIJ2zFfuSgbIgi0FsFlHCDZ1+81W4L3 dx8rFEUiygoJ2jsEE8m4jL3us68j6DmWi4Nr58zLucQgiqt48AGtJ4VJYQ8HiVoI5wGBeNbl6218 jDlQK9R41bOXANaLFnVfjPw/qKC5dyhWqwmk0Hc/MTluWaUYKWOnLR85xKb1V4Dgrt2m7rt0gINQ GuF42Z0W8Ou31fvOGNARANTNtt+dx0KD6HhQrDQi9E6SoQoKPYro3oe/eUyOJNzEturwALkXY80J /+z3SaIyuZzOCJzGj6YyNYTO4E5e/4nkItgbM9Zxn5oUCR+/GPHqBcCOSypUmSiPCfGzm/8djtvG XVzZRXgIgVzCUag0U9tF8G/vT2OsJRHuRYPZA8FlCwYO33bi9msQHlsIGtHMNSDE2rzIQrE6C0SK ztQxoyV0xEWoqk8/irrrGAVvbRkDvtcBjIrDU4oABsu69HGmlvrdtNp8CbeEcOuQQoTaRz9BvgCI BbGAIIhsEW8uGMIHmFhf9n1/8hx400HKIT4jHanltSsr1a9d1TGC6ozNQl5AXj9MkOltr++10Z3A hsqKfgcSQ3HYd3KKqs9dNadIvpO778fdQ4CMP28/PeaF2P6QXrsfXlwUlNTs4SAcp+slAR2xRpFM W/TRncvrtGAkRqUSXQ9e/yLt5NRCMM65YO1ccFTR3TNrAC1kXS8A/+i01vGAXt0xIATAbp91qcpG SaX2Wb6WpogZbtlteFDN4CqAPBnZAGDD0L0p3351x0AXteUuI5dMFPN9vU1GI3ZambwgTNaqR2m5 4yPsLewxSCFzK6A0EFc0veWY90kkI6+bZ5OdgT307qY1tOQLmYMK7NYeVKeH5eyiMCCs312Xq+oG MvzEAt5debvjMgr90zMJCzwPUSOsAJHN3JuYzVqADb8/Wa/REdlgXHMcjkCLi0D1f3adzQz2sw0J POp+et1XDoNv42IDW7JSmJYNBLgd9ZVkLWKDZFbPGTEY//1NRrBaQFxsEDvI4jpJJGaArRJd7jIA 3BTbdlde3Ia/G5++foCfubst9lHeLncu9gOs9tQO7ODGewprJLATpo2QI5Law6IiX1E5lp8qG+zi Yp4T4dJNbeFR6O3RJ7Y0mDYCARBUzRSdz5L5IQXmAIkCO2AetN7b9Dk8KzRoTiRJV9TbkZEDffHR p3PmDU7ZUnuuV8IKhxIqJNlhPW0zlcRUg2BHIuzdQEAtIKJodpmbNpJWWbixEln9tJBiGninOC8H JUI+nyZOvB4q3EaeLMpUOgASTiEZ0DOJiy2z3FQ6XG5R6DBKRL92eDY+R+pgOT0+dX9lzKfWbTbR yPLCXCKzvCT065Iu6TUkr8+B7aXszROm7+SxB2nUthNdtUNfrbAQyjR3FvsHwKpVeASfh1FXJkRj vnPNsB3q2xwfVrfnsIEyTWPiZFuiCwiEciusXgXLoXSOXHoswt1R5wRB4xBYERg+AUQJpkgtOvLB iYBj1dcRIW+cx1Rcf/qheBrENB/m73JEHzIz7CyuoNS/AWehd17QaMGY5LmgAkcw5YgEef8k6HCQ 1BcDKaKQoHLZ5cDRCTCXGLTty9AK8gXNwi0iWvpXgJZuQBsIhcw9xxcGKMI9UhYKV6fMTCiDahdO OuBuKlgL+YH2oDBgaA4xpV+GIVlHFXOC5I/rzeR5UeYMOaBi//xcmVNMclwJ1lT7FqkbCkZ+K2hp +YYL4eyopbOJgCSle9961gll0WdP1HX40RfTc6lvuDVnc47U0qRpYzAnFXRl0UgtjaSsRJRxaSu9 GQVCs1F9XUqdrGQt5obattM+9at/wix+1YtpLYkJCOrXZdM04+erOy8Ey0pru9yVclOdTxaexQrI Vw4FBxrDM+KXI7D112RjvAitG6By1WDivTA4fEKY1Hx+F/BLxmXUlWPwfSZzDH1ZkE5pkN3vZafL wRd1BEqDUZqaiX0+s4E8uqKDB+rGo7EX/Sc3I6oVosQQkU5pt5DWv7LHTRZBGj3UpN/Q1oAonqMt v3DYamrn0VKmPq2zC/IcgRxuK3iv3NvkATiyQG1AsY++NVsp77ayf3Ma5lCUa9WEDs3RyGPOmIvY kBTZR7iHrhWQm1qbKL5e3ByLy9lMgCvBsDynLpkc40n7qHz1sIDG7S1K3pn35QJA87HmesoEU5aP DNnANMFKpfh8/B2MaLuahjWNgttIxAIxiEl77ShO49KCVJ+oPqf19ve9dCCnVMqlDObXPLUhnBNW +xBhyhRYcfOlxlElDKbDoroRcviKd5cdd77rEsTQ75QeMo49vwBw1DZH9UZxT8have/8BEeOUZ9h 8937xoKlIMh3us5valIvtWU2ssO10vgCHvMrNL25cwGRMBCQLtJGdEcuma7MKnNF7p1GxpXcXHsq JWOGbfrToco0d4YuU/wi1CsbiFdh4WGy524iuAWwoV4SJmMoUjIr48MpgCzMXfB/bagz23wPcPqs NWjy7pffE5WjOil7xkeYoOVxVe0FbDM5ptrj4lTnPEI/c1eMu3Eynn1VJkLIn/ki6AuKXgYW8efv 0scul+E46Jswv4GSdUCp/phr69yG74e7mRgwUR4YiTFTITHRTElv6jPutKjVRa0otII76OMykjGd GoF++N/5HsMo/vu7AksnOSof1leXERrAchTTEkmC3HNdEnGL/NBF54cr2PzXSl68D7obZFhV1VpU Els1SukV4NayZG109Zd9sYCV7tZkdQwFsQFKgXDLvP3f/FDRw12HOiRysg1Z41ontoTQSSYpKZpG YLuCsKOu62RyeI2Jo+LV4zMsZvltiGWW4i0dA2apFgk13soV78j8lRNVy3752ifNEkv4uBkvrtBf hcvUe2P5bWthZeCNiSDWe4aA0p4GGtYJN4dglINoDTm+kA/lFgf/KUzaKyJEjcDoQ8feA+X9xmQS ymHbzdwk7xRKnWmXNDCA1xEyM8rc6Iq0LVbFlh4JvKWjvrhJaMQvMe3qfY3/1Yb48qhua7fssIVd DkH3wTCXcwTr73Lp+qZnpZxCVZWacijG8WZApNMDgMyjSHjHb3hvi6Lsnufo7EzRwyv6KxAT0Vjk gE61eSRLMA9SSvj0Z9XSIp0c12KOdjmtAMbQTynfjKjAvIB/xuMp0GoI/MmzAwNowHkVWZgLCMhL Cg2gCwTi6l66BjhbdJM1xwo26KBMdPF3tuVr0w4HgEhZrWAnSZxKtqa8pUXs3VeFf5oFuGsooCY6 eEP2UrYU9gLiZrAitlHqIo3DMtu7JAqulVM6ogCUzNJV/LO3vkJD87JkIp7oHcDLaDf6G1ptipeE OdPrhfcYDeFB5vi/Kvnnyq64pC8BKN3hpA17EjKmEhxuqkHXj6Rkb4tQc8h4K7JwyMPtsdrWpt++ cVhcAJeUncTKA3QRnBtA9eAdi7pLvFhL8y88wp2pweLDxUnXJZLvEQJoLrQQ4DfAgCch1Ep3mSuA F9J0ZNoVCJ9xF97PEB2iMjXvuHOLNAsMWuyP4ESAMwh2db0JaIWa7xHnCWK3Sakc49wHk0TYhMe1 yfhch7jKEvGl9rY9LU+QuTKVK69r4kI4N2YMKg+Exm+yKqzqESblMqH+d9yCyFaJ/+2caIbSDKyl OcPKHNgeJMskT0uGdxhHV5tVuEVRPGC6XJTtU21/9dJsOvaJHP7DRVR3Gr1j5QwLrcSop69Qbk9S fs9dQi3mszTSPuD+geLiiPFNZU0aNRoFKLodgAParH1fgak7A+SOOEV9SY5n5PzrGvKJew6LnLRG eSxPmY92tHFuVJKx+Zy6Mp0FEx7sctrktieI9UMRc4sK+F77KX6QNRcdw5UTDyIjCbYvZLS5QqvR mFdq3HkPZoS1BAlL8IcoF5G8tK3+kQGFhHW2fBiSipBHbI3s0GX1f+2JrRKliK7nNvs1xs/1CXFH 9aJs122rEHaju1FsECk926H+u3YnHK3XJAhEG6Nd2GBozM6d58bF5H4YfUAOfxXhfuhIKfim846z nojxcwOY5cuOLdanckJpNxYSpjoHqCsL54eSYOEBXY8k/XhIt4Y+V29BMsDR5b3LTX9YyFCodhBo L+/88sIxrL9ZX6hf8pMdE37zJI437AzbAvHtnZosXRA0ym3VhzOUF89yGWkr/BKt7AkYPEg6tT/G ftojvnUDuk5g0qJS801+yFspRUd/FJUUzpWg05G0TPm9AilCqrjoVdZw6yLnuV9M9iiUUrhKrqRI 2ryBSbrlclarqsjx4gsYtwbsD3BjaaceRnNkOPOs1odood6oB4ENu2REDv1i2nSNEOU+Ip0tERO9 dEZlN2DbdkZJuFTWZhrCGUQPbMI+aNae82+ICdsQ7nDpggohMmEV9XmDK9yINn/nodqaIMK/2Lsg IgqwwTyJ7oOi352JqxLs50tqzcMviulq6JTsBYss40o/QrV2f1J8p2xVUZs5t3qf8ov8zUgL1DmN nrh5XgYoxgVKv42vgKjeLVvYE5XMtfwOdUt7QzP+a0sg0AT+Xt4ekdBckJW1T52RcPaWzsD9/mt2 f7pe2/fHfpSYjrv/UdjyG0hsy4WD14Lg7UBLJgQ9wUIuwld3jxh7TfLGhZhez5HOBh7zC5MNVdMJ m4evCGAtuS8xWbsmAFUX9hYTEvkANghjbGYEeRUayTaexF0Jnr88Z3Ehuloq+gk4lKxPCO+lEbZi FGMXWZ6uUsEeQsr6Z2zhDLjOr8pw09Vid7VkWZTlVgeincUXcFv006+xESjqlnfbhBNBpoxJYXm6 GPi9D9TJqjBgJBjXuwmO4ERaTmvsuZGbvz5svbcctUYH1s4ZyrtR61RkclEvDleVQRxbj5i2jDcd bkxXqFf5DCjw4yqVfVx9yo/lgWu6d7WnkzZCsT2z6QUDjhBrNq6c4aKN4hwtefHGxXFXWcjEKJj9 7HSHHuJ4JOiktvkvzAaOm6DFIpdfeh0QGQEQBOrJ23Gci2mCbLAAKb8XhRapWZo28EltMXyR9XrU mWsbmVnRWJcjV+jGyIins2gthUYRmHK9BDrbulBrmkoxgoV3AV7KZKBYiLLTccW6nGNeEky2Ur0c 8cuiTcM+BbAtAAjSh6sEXJKZzcpIDP/B99Gy7WwFDpkyyChH77ckhCuDseTKTG+m1NSKCx+KrTV/ a2m0u1/ving5X5CiTyULr6Ry8VLT5F+ujHQU+eJkDHzWxo8nxMR9wuwr0dchI64DjKIyn5C+iDuJ N+IWtq30svgWFD3ZQT7CqO+9IxeJlbfSpmmYahq4NBQu6IpTTHrbuMNcay2GKW3GfPlch9G2iD1Z 8nc6d4u45/xqMAxiG++4dzXwRRT6w8QHk8lwL9b+2kRuTYugeDGXMtzl0ASQzwTh6LtbdL1pvjfT W59QUu2D4q5iQdDjNwkUNdcGq/YF+VJFjJZI/S3gsVjNhTRxG+R8hs8yysAVd2TTnJEsDC5mwonf RM0ykVsHZpdhkjC9wU3B7+8dXv4Miibetvyz1hEM3P8sdh19PTQ2EDQai9Fq6lMEe/4ta+1r8t4g 86096zyyE7vmEeJinLiU+eUQ0RVIPgqSilrpuKIbMnn7EKUQV9+RpkanGkYQgqwl5TcHFFtjp0XR rz7uBinz4x3TGJOMrRzsg3BKiVsvau0+tRqAREPu7xEy5YC+8A5y/4vPQh96lVUUWnWKFSR0USiv /F0Nnm06qd7huREr6Sp/iXt6GgnY3mxO4Lpl0z7SNMqLXEIouuwSRb0fpYL5+1jFAZEMZmIj8mEG xQL0QQ1kloXVWqJNLgCpM1jl4mnjTMZZBrc2Yd8uNAvci6ZH9zoyvtBU7DXZy/Xw6zEf2tN9AlPQ 56YYqatftx+s3Vc7BFQVpJ7RhWoiQE6KrY6emkjMDsoAC3Jd1C9S3q1Wx/c5G6OGkAUyjIu4vhJe 7/LghPzLH7jl2O3OeNjmQ1d3oajdgK0YCgw3Wm2W8drpG8NuPweVyYKk+7LHuHBQfsw0hIEbcFQf WgsRRAhoL2gzt0HgPLkGJHYIS+6tMjmWh26xD3br65/5Rf46Iko4IseJMeEcp2tStUw3bFoVkEtv wmqxuN9OBpFKGg8Wr+eAaDtRWLrKf7SmIzXJcHhs46n6pvcasxafVGiCsKnOSuu1x2C0jKT6+Upd YnDApiLfuGZgSn+IzxlOHx/7EmVcIPFrfHLwxgeue2fnvvgvuMSxb4NonWkjj7GpsIHEPWn44Ho+ xiUdE2WZ5NbsYD2iKtim5d5ouIZQGu6GxEMj/zmDmDpkKHvmYFZAPi2Vc7/ldPXfqczUOiv8yVl8 bKsYuY7rexIe/12NSl6hOKd4BRwjRuoMqvoWygLuaKm9OSm90ZEEhao/95AImSCGtUa9VhDL8BBB X1UmsstUfO4XoarH6LojN+cwrt/jUA1wVIh6gzOLEDZhzomkI6LW2VibIr1ycFwhyg/+r5dHmGq5 mlbGK0Wrchec82gjQlPVgd/nnjO9oUliT6leJYdOPQeNWM6ebOreyi9ZXyx1Rsohas97LdIktKxa dILES9EiGLGoD6pYinbqsBPoT6Syjg3+cYlb9/QmZDMwKNdj9vRNyPhwzVDwGjdABOLKNVkxYIRV qf0DyG731+EVOENhJZgpPsqLLjPjcVVaLbnpooZuGClGiwcr+0jBso7wnWrmt7kB61nyEq0dMiai R19y9j1Zj4D83Mwr8yCYISFy4mFdNLegHdRve7kaVN/KGfDIzQqucNaUA4oX5q65VaEEk8Rivyje 9CA1YxM6I/m79M35dgBKYMnRPXab9U9ttxFu2rQ9/qkhEDpvHhl6KjOT2o3Owv0Gb+spb1JtrJ4d UPBJvdIwTSSkJU1AAtC9X2vMdDhFxVH/RhplUOEBL/SWa2jFPkGGhLGqVt0VM7laNeR1/EtrDkrT uM4TQ/tEf5t/OErh5NaPtMBaZ86xPhlCGCwcDEiOhzcq76nz5X6IPjXZ5q7pBTwPOAfoh80aJe/F h6/TcxV3MQq+9j1AIJ0GaXKqbud3Z73/zs2BvlE/kQjudQ9xCVJXyKiP5MzVo+QuuIluk6LAJHA2 qtHOjlmflmJ4F7J5eE/YmWMOAcWxYt8Krn/NG8zbL9HJXVyxHqC5evFkkYv2cpjX6JBosQGfvdXo qJ88dpzl2YWm32IV2zrTAetaqWp1rR6gsUHK5hyqEbN3Msn+JPwJEM5FpoCDLq3+hLKN0Rtv2y4m +FVEKt2uM8LiAAAQlVQWNH+jqohHK27I/ChsM9phepS/j0bAtLyJHGplmUWFOwcmHWn6nAe/31Va C2J/KtZD3fPK0ZbfWjoLHVDuL8p7aMR2OlX0+RhDmkOLEYhDVgizKwLpiFgTRh9/+U3x3ntn+j9w n7ujIprTl83MEf1U3Mrysfk4xkOHnt53n2zZDftjKJG+ARNcL6Dk0z5Ig/pD62VT5XgRcM5O8Ch7 0MV7azzwzFqGE9wACFYQQj9foy+MaI4DjBVPt6vBx48t0F6PH+SlfCz6XUxhbcBQ5mH9eaz+Argp QQ5QXNVrhxPcLAWecRflXSGM4Fp2e5vsekQTZ4ST5A+27/dttVlZ6cwWINxuxjdeGb+8JTGC85e4 kxCqmt/Vk5M6DxXi84EDe9yWdOYdBmix+iI6hge0SCKxEh3skZ3loTjxSgjxJ2SaxTBPLSEj2KSG KumCVZl1UKSW+MMefhOUXNaslM/mKe/2rjEsrSId/2cFDctzuXyzCu8TbNhCU+L7vEAv5rM0tWIV P3jb0fVAszgG7NAn4BociDWP+rCHLc3evhdImIYcq6wrdGfvcaARYIQCDPLUGdMbinHlMPus7/IM 2oB1aI59PKdjvA3cNAQyAa57BvTUbTR0foNbqYVDuqkbG5EUulJjGnBxIr4+XPl8kXmH2pawZMau Pt0MkPnMcLcW+BLpHtK1vvDtZiS5A3L2CLZ5pYULVzQKLoAmVl7/HB8MYHFlO4LgaRv4+mAu33Jy nIDZdCuPGJSGxzYI1JUyZis112KPyJXxzMA+jzyA662fLFhvcnME1vsaQlU3IdJqsznaMl8SLd4U +UciZQKdUEGzW8ZWxf+K1p08Hic1ywwPfL/UYHOvhuRy82Xx5qWd09hTlY6bEW0Q5YFvsZpAxmoa 4M4ilQt7wUZCFzWuPNqfEqFl8MIJ0bbywfqLd3gOYW/i1QRkZgKmqLkQawEmG/wH6dJRDWMbJZu6 tg3KHhGUyk/Jaxe3WLXFAolcn+xCNG/PStvDUqDsMni3L1vvnDdXgZ+LbRKGaDWrDAxJa6khtrUb gtLXqIjLtOJhvzTTAihV5TkokJpfQpGII20NhCXqqdJ+oYy/le+wcsukBaxBAqTnMm1fsFbFiRYC qz6EBka0LtYVySMRPj4XvATOYzw1hpW/rTdf/QGEXnoyILCLRLHxEInHHHkvAQvYFsNOQ7q5QVCv Y4Cuunb+i0jQbqQQi5dSUTbAXwzyanTBDJ3WOoyrKTO8rjYTzwo6X/EdnKr98ODZPB8WBQOMOmgP 9XAIJynPbGbpdAaD0gUiXep0tvXwxGQJfxU07XtaM5e9bSxSpcV2G152xCFv40/f5GQ8Tpetk2MW 4Zfn1qKoXbFWJFPTTj06fLr9Xm8y95CcrkthQFbxaXetELRsUeYodl5U6dOexdEk24JShGaQsBHM 0Qn9OhgQrG02gwwibLQXj72R2IEnv3Rz7Osr3ZhbrMsYRz0cbU1ejFwar1qDqzkZqVRPWrvH6boF bgP3qbNVfykhYk0rV/vfgjWKY5zs2UrhrRnSOPCclqFL0Oh3pD1xqJkMB5kXhz2i7+MVEnfW+/38 6JqUf3Ytb0+b4zfPa4g9/s/Hx6J7kmomWBuG3VLcNn4/ridbiZCKgfae6ijPSCeAO4ftZQTuhAZB wE2Ffm4yH+dDSHVwQ+6ozTBR36aNjv44hKmR87G5wfokJeoWI217yb1MsvUDOXnvaYmI/2OqjwkY WMp0e53MiTthLq803njpkvc8BzCLPMU9GbKr5GyVwQ188dIxvpHawHACTHmJaycG/PwO3YCENft5 875jjuIS/ZsLf//LuIx9csZbf+5Ui1cHpXBywNFICS9YTkDjUKGqvq8m/1oh4cPDoJ9I96J/QO/M X4SVSPKKlH2k1E7/Gk0rEuSbMZMtpi2saINRwDA1F9ZvSf/ZEKyoGtPjiTvYhcBwyNdZ0T2PdOD5 Kf2QcYNCR0FZGZwWGO0IvzIY0QtJTdNUZEGHyDJaN2m77GIIPlzTUlq596xbEN6lOFCtuwS2+DFu uEXXclyoTBEMU5PS8Uo9H7Y04UHmde+3wgOIpeVDS2gt2wEoR4lAUbLsAtU/T9J9d18Pmg+DgUKV GKle6UOsGaRA1Hbew5XZcFaA3f9685HN6ZSYIlV8mNVZWdOy+rw+mErmmsXSJ+L0VeWo1NYUJaRw INWrDcGcX7FviqfjjcM40oAxITHr2djvEpozTWITaqlG4hl4fmo0lcEUdA7hl/qdJLHu/upCijOG f9+khl8SDNzC4DNl72CkKiKgfRrIOuCCYZDMv1JK3K9ibkj2tt++OqgVZ4MCkoGZQ8dxCe9DSc47 0QyQX+Pcctl2Jmy6pasfBmZP+jil4L0LOh9PuHpd3iI1WBAZMH6e9ayiMYX0llDUInO4mbQVnLHL sEiau4JZJaVkmquJDJxizBmJ20b3dYYSFpomtJoKWgJ/7z/P16/f8El76GaIYVfJ0tZY2bSmFwrG cFzPMvFp12mh4iQnBNkCI01vQ+1IItyQsRFTzmP1FWtugfxt4+OdEAAzEckdp5/Zqze53j6OG48o LWIZFf+Ix8iJYayxPo4CnKUJ3K3uy1LLzerK7V5zwum7H7GdyGV9MqT0Urr9DQFd0d6tcSGzZqS1 I19PJ63iOmMXBeHjaaRad8/zjBMMhLMwpqwOTEcXSZMXtnEl63xUyLZJO/oxwZEIh7LR9he7eK4p RpIEY+qkZ+Xpn1IwmjOH8+8I+JJ7trTinRS6u0Evh0Q7mf2KzJbNvSGK49sl9hJLX0QHnC+n9NE+ MVPuqW4E1TE+Qb6KWlF7ZLD5hiXhAYt4EBGD7ulYufmWQXrHl4G1D2P/Ft/jFWOamKhTnXLGYtyP DQ8APqSYb/6loXHg1hKzaZa070bZd5ihUSJ6VN4FVSq3JhD5Wuf4jXQX7WtA8tzRs+2QUJLoPYgm 3f7rG+vmN9lgzxoRkhekz4xRQotdVv+OYckEDXtxrlrI89P2HY14ap4WurW2gd0R2tqWO6FaKLaw ahtyElg5/4Uapzap3jsL1BKG2a44/nF9yTWDjHtrpQ/xNo+AMBbY8ZUVTZJZx/HQ1u3yxIVrSPRr v8fPXPvUj/Zj5IAW10JYXCcAd9+Qn4vyOrpL6hlKbhcs/l7RgF3k2d61+epsoJWifNjpom3iNC5x 1puRDbUm1GGciAHEmCHwK9u0s7JuTTdrJsdiZBCx/io1FQoxeq9T36We67DMycdP9bp4XkKcBhnw 5CBjVasb99giAGyF67cAFm+MIQnFgmxcbVfb9PRyrw4uZ1gBppMOTTROi8NHd8ZCY/z6rwhDn/Z7 ll6vMTJEHeM0TI7TggCLRD30+vi/vUenACOHsTX+TH4yDiL7vwuVuQ2V84bzC5zqyEEeH2oJvjl0 jUvFXptWXM1v23NsbZaA8KZuFlQ/NyW9q8BFQY+AAUyUBfzZHl67qaAyWYEy34nQiqL9tJ7TwxU3 Qfl5f+NxjHPNKsC6z/wUUaKHcbhpQ5DPjNPycvmP0soozEaMHP16M4+E6CsTt6AE3ZkfacG0LD4B 73u8ZqGpu8/CJGMlHgqLou5J22UtkAVgv54kuMpsVRfPKoErWPcbcFai6UFidfyVRir+ma+bI7Lk pb995F8rIvKSVXize4+McNDOK7p2fXTg/SElaXtpY3xjhdn1D/hanAjZ1T0SzWRYKnxHnxBU2HvJ NJq0+CwWaWfEDn5FcdTO/0VHHb6veAF24EMuFcc11vh5OoX1vL6UQXZp2liXi4s/iOiK/qY1nYYF IlB18idsXaOeKAOpAn2WBWcx7eNYmtjN5jPn/78gVU6MOX0lDsRGPXtfDY959g8SLg6iSgP6UM8Z +5LMA5m9MSTE4o6mzqLoH2w0TBJAytWjadOdbKJpq9P62hoFajaR0Prwawz7qXGDhW044n7q8mM7 jadTu4VzUt+4AxNwajFOp8gQiNpBBoWq2J5EU3myhUgofG4BH/25AvYXFfbHr+YpeNmmcoOIpc9Q xVK7xDSoVi3dozpfuHYZVi41mby8KAl60D2Kdnlmb0E2XaywtaP82/Ar8FlJGjBINMPXDQcwIHEq 8H9kKECIhJczufTFM5wtRDh3msfJoj/dAA+PxyOF6OjyqHzwLSX5M2tfXddm0yxPavWoGi66/w7d T5dVB7ztPhsnJDuMvxeDR8VvBKOEz9SEtpNNCdJxvwY2S2UugxMTYS3UjSR+T24r2SHS9rzfOJ+S 6rEfBMhX+jNVusQC9tJqyqPXFfrN7dmNs7GjJSSEkwYEDF5dnr2oHbNZs/yTvCJdyQvfMNU3Gi4y 5yZ2WmyFOiaNdYJoDBrM7aUzLgm7ySHPoyGSzmCZAuwHFhWS7HC8gaIJ/PbfYunrCalVV0xEDO/g ox61yR1kSUfxk+WYd+fD7zFtovg1FYHf0DAl9q5CZcIknNeLtKBAV8lHtHpgTwy36WF2B0aFxmqo Me+YNCSjVPLBCnlzTNJykVVCVXpnurNWqcq//Z3Xaea5OarbBBlObX0F3ziT9CyBKmt77rH5W1Tz 6EgYyNTxV6QABnvuOUSGYKY5N2As9tvf0nQdxT+Ew6F6ciAzHeGLHetziF/CDlraYDnaVpvKJmPP axlH0pZmT7cuxfH0NM0HBl98s83tECBssE3sA7E4nBTLqgVuM8lgvhY5qe3mSqZaPiUCyL3wvTBV G5ZGagT4wrKPis7TipQaTuEYfCJ368PyEBQcOqJBj+k3ZLXw8NbB29wLO4ncbx5+FVeJezb9eh9z RcMNb72NoLuxZdGav4+XJDCFBttfvhnENUs9G7ZXfSjaEJx6D7Wzb2Z6DRNaOvBUgRwHiwW8J4dW r6buTTj5CQXBDJF67yz70MrZ/0gAfgmSkeWMjHTq42H5M4y0aWRj3Uc1XeBaD+RXO1M3sYNLsZND iIfsymZzwENoMfPmNf/YeiRlWG1uT6usqewQKFAE5Br3DQ6caF1FEPhLdm2bE5sxFdXyIjCSfi0Q UGAs9CH6bMumJCcMWE4JcTGV93bkTonKrS+H/5JGrtyOyhvuXR5U0miGDzp67cOPiChp8uq7bJI6 UeYtzKacdT63chPj6RvwrUO1ePhHPtx3HfqG3yZLzIZZzK4OBjrBKoClPzzbM10boTGQcrCqyUIT O8bX+gTWVbrsR5ggIXveB0Eu4/DJMuIaeOoV1NIGpmDBKfpNSxBgr4MesAYp7/zDwCrI5lgHPS6x HyCyOnGd/Ft4IF3jm3qiVPG7ap8AW6zcWY/xS5DcdyBqAclNCDzDTeyHAbCrjvpxYe2iQEeiEvC5 DjNSiCD1zVyU3/yVD5Jmrm2xm4F0QY5+dBnYyPL68VL2E7ZNgqz2PiFbv/yZ3qzlZ3q8f109j+5X tSPCK6Ut7fU6no53Kb6hoV9ZGfQgXAYDW+sC/O6jdj/4WlAt6RonMatDTcY+Tg1RQ/GgqRmGgpGz UszTY01wSNya63bEAZHknoe4RW6YVxJZf+4Mp+cJq6Xqco+rW/0SAnfz7oQmaC2P+WesTokzmt5V RBtFdMSVTRMhpCaTAsx/Kb6JUS9bLPffNYBPKSqCpKQr85qsuhgQv2DGIa13wkOAi2QdkCsrQdNM RlX7sUdbvuvA5CEgIwoJ6T8W30Lt/sYaIy1yG1cpJYT711jHPTHTzmiSrf1POWAKj2W29g012qZ4 3u2vt9/PjZeLPC52oIGMDnEtxZl1DWBsxFrj1ltiuafuZYQnSKMUduOgSt0GV5nPMn1NFCcXOHjN b2lchIbzVo5XXMLd3LwhWtnqmqksI2m2P/wDtsE6TCZbYUm88M4iENAiM921itxQ+chA+tf0wVcp /ZepgOU5Ew2gI0XUAyq83uyW4XhVj/FhjNKJGkPwEe5P5NNFScNHuV8tabOtalMziXZB5tpY0K+Z q6z0Z68+fstvSRpslv9hM4sAC3aThvswBlNlLit6mx35rkEB0M2Nxb5snjrhz9B+rvLrCDwctl45 VcxgRLQiq0Hvwlm2PzJ4B5I/1m8JffyVI5EOEmznlenhshmvZVFUxKUZ78+s+x58zGs54qiXJeL6 HrQwtVp04pRVI9ZYuTo5PxepJTpF1DFQC/PnhH2ZW9yqdkeDOnAMR1fBrWSkIohaNABH7ZIIwPor bXDJfdhsH+oH+UzTJj+DlgLquvc2BWRdNZbIJ+17Hjt+sT0AL4C/eW72FEJpslicx+Kn9rmh20qK MIYy4utc6cq04fgNVdWycCVWWdRs2aAnr+t+btl9saK8BJB0lnocnHiAQf48SyxfUgnG7LFx+eFL EhK1Y7oHsXMXBllmHsXykxr2iOH2zysxI4ekbPFEyEwQB9CxmKsTP5UghnVTVQXV/3QB6mP0k1t7 m848J6oRRLllmk4wVIYnqRmhCUBWHVBr7jRGy9xaVtzYxEWfwp5zqMifm5YUSW2uWn7ulkvhGvX2 bAfF4IQANbCR2yLBB5xzy9J2wXwCfBYWdA0wAUQcDVzGq6NCb7/u0kwOvuL1+OnLq9gPHEhq7Fto kFRnvI05b3cNv0d76fFk/tzyBfLYJQy/9aRYTKFs/jzM+Ss23S8of+vmxnjZD6BjDBblAPa6kWKo PDb28apgKyK8HAx5JvBGc2jQtG9MVfMKvTEG5bBdt86WisDZJnSnKJ9ECp+TeBk8lfHfH9B1ynqK zK2NHc9uLRcRD5AZzM2v6nhwhgjHIWQZcgc9EOZEm0pnul8oyjouHmSwgJ3tZMLE9IbZtaWD51hC TVqC61wI1WYS4sIxcAJzpn3W8yIR1g1g3VY8DXovn2cP3C74p/YajM39x8K29u6ffJZ3iD40cqKo j/BS1sHicLcVrjhAmn+qavYI8MfX2T4Xp5NTPRUUH2MdBfwpIWwCmMh9thLa/9H40NQGCqN89P7V pVMC19LCYcXOq0al7Fl+FWUL8wVra10fuVxwfwxo0BPg2Dx/f6rF4GRWSBRDAqd5MGP34OM1ahG6 XPXi42r3VOXCebQ7MPzhu+nfJGEoPPgMFcTcKSWPYJUs/ZNCJEWnKBKWR4jDnyp6QrBeYZO453zt QQvaccTBkqHr0bbMWIl6VRQ73cD0o2WyrDezaSBE4+0efoK8NeQFzuPkLq0ozLB4WDuNtLj/ZcxK rRbConNtxbdcihK6QU/xoHUcLtip90L6rilWh29us+8SaaeR8R4OplSeUDKVExwxKs6ss892pFul yCl9U5H6XqbI3SilXcoA/dRUJNLKIXhmbwQBaRgMQq4QTI80Hb5YtKr3xTg4BplYVJr50k4h+gPl dLz8bKZKjkPHr6/ciI1gR6T016SNkUZaY+QqLxA+D1BU+Up4n74MZmec66y6omnnmstl6uiQNk7H 8Z6Z7uYf0IBwBueOh6CgDl8OSAbIr7Kept7RjWviYkK0bJO7mJrOdblRo7mX2N+4RDGUALPVNH1o Ox+nwJz/xjfO+tzzS00afPEH9FgUuqiK3bW/FgYdOAhCNeXtXTtLdlsf6kT6BKkVsKWYKdFPjOgf JbgiDUkPt8csAYwIWZV19lAIQOW7zjNknSbFqohZxj4ORoLUmWheIoy1coLLtQfDxYd7Ovi+4blN YKqVP6EOaZCUiTfpo04dHu37vbepS6WEFoZj5g/xcXx2ADxTDMHhVpIiX41XtVK6OZ7KcIWtCbz3 zTqgp5smBeVBLQttyXC/Vz/fbUBTOmFs/XaEQDMQIY/ZMg8OtHorR7gV+HcIDTL0FFJAo4G4wEiO f5ojJATmQQ3mTdZhTbqSWi+zDfEXrnk726T58gAAA8lL+tJb4hkaZ0I+SSowQZ+9mjnHppD+zqJe tvWO4tSfNg3u/j2Xe5/KNaavprZBbkhJsO0wZK3RkkimeJ+MaaDV7TMLLEMbIgCm00tbllTYQnl+ xLVSYFmyQ+pSb7z+rYiSeq6wYBj/0Sk9SUbBi2+CXQVbUZTWodEAw1H1Lnv4hRdp8GgtB75010BS UldPJlnpZN93fH+Z3qv1tJqht1BF+3xxHvKSPrOFfnAv7CVpZfHrPasmItPNjQsXMqNYwC7/ZVYO A77q6yG6cBdmJLUbbMfEgI+Q4Xu9bejpfOTtlDR6zlutFS1AlQmsz28m54BLeqseDkZzjW2gLRL3 LH2nFpCD9goaN3PzqesrDxrdJ6RLx3klUqp7a1OopmWUMmS240fHWloTR9spwyji698/cpV1UnsK GBBJMPLmB4pFU32mla8E4MXkuVVebgtyiwWbv/3zYS/TAEnnx0eenUo1epIEdiWU6zMa9f5m3e7G jEqw7Y9MygSzczF+5VMIvcE8I0p6FVhAL5F/070trXwftoAf3EhRauMpEUnGT5fzD0s1Q0I4mU4S HjqmQXJAYfR5mhwH6c7YndliBDeHxcXkIZ6m2CPgUQZieFGz4+tPmN07o1aJ+sjc7mXC//qh68HO 9R9m0XU3RHvTdwDO0eLytY5SE3y0Jq96hazz9AOjGufktqslatQZ3qLd+gzfv9vgA6iZH3R7IrcM RNe6PPRIfw/fsAD/dMesBRCoxn9QYs8wzTEq6ngspLOfjzSpEKpp/PNfLq/U9yhcwq4bJnNHEQx7 8IUecFRWxNyQ7M2zj40OlNpadTcM149M1FAAw0KX7641UWD3qWdrytgS8ALnUZYijDPKhtVwgx8A 9FpaqlMa2rKDi0Xoe5p4tstdh/I19oCheqhk2MZ+H8rJCCgmq3ID3F0+1PfnFNuZCKtowzlU+3Na Q/1I7voPbBc+AKn+NFmI/WasIjRPDYz/FEl0iXk+7wKo9SgaSLB9LhHLOZCPaha6sZftqUuHXJSR QAWxOC/3kq1jBzqxlN7LBA+jqE0lw5hIWZsM/++u+m7HrKnLmwqnVtSDGV6rop0rXCMkdLIARrSm ulu2gS5mBP03HcXlWkm0bZchJR9A5BkfkYD04FhIqVsXSsBnBbuAYaqMPQc8SY9Y5niEDLTiwE93 jjX4pH4bvhnKe9OHqtkNJghMUvHXAsC92mVCb1N7OvdiljxvdhdFGH+gbg2W7/sCRVZxB5hAmQcw tCMIz+EefhIrRKmqzBJVdGHdhQp0BkLwY+4HnVTM2eD6ErlagmxhbDtHlEHnAWwN8HTFboAXUFYz 6y8o+XJO+eLiNtd5mMJqiQkY/7qgct8th/wzw41nfv4AUygMsTSN6/ig+zGBB4k4yFl0Qu/7uE2x uI9d1SU6Z7Jt4KNUKXudX10jTCF23KoxMgI31LLLwayxFidehKpaESa/O4rdZtzIIz9vaf1vV1br CCCyLkclgGZEYa7/2gfXYFbc7ykl2PY0eczsdjoBkfiRh7XksQxCuCjpv4vo2ur2GgYV2i+L+6hX i+oATj5/Yp0Q0xNRI7RYV7An/m02w29URn5WWvcKQanjVNr7aGAe9HvlBikUZVSirDxh9xKN4CoI lzl5fipDPb5AXiyhRVYCEa21+lvcev+jDxNTEt8d5hQJ5rSZ/WYSokKpoSUABW+XNg0yrW9DmSdY zTvUKii5s4liAR/WRNpQ5llCbhs8i/yk0Sh9ZFhdOIaBDNW7XqK5P/hpqz5cr7/dqQ0CHVDreE7v yP6srkZCZFtSyXr0oHC29HeGeygmhfZ6BxNh2Urd/0FzTKJixpdXnfCVT55IU12Sqvygpu9Etn+6 igTtv4tRNZGQwT4LlOYOxj3OyKTrOhaMB2IRiJSPn/rSa8PKYqVq5jphHtBsjpnI4o6fqpKNH4gO UPMMhSCQEwlxZx9e4/lH+18DzGGEbwyLfyD7oCVOyPRQZRLJbcqyUbrh52byBIko25/LQShhOvcl OeZ49t/YXJgDYgEKnBZc+/mtRkPWBx/3zaMQXS08xjNVKChi7th5CNFVw5WHXNQ0FzSBh+u9kbE4 vlEfuo9Jc1s6KOM8ek0NOyi+iqERz8VBOeSXB/4fgEqVDDPz3IUcbJu8Dosohqls5L8E9/E4SkTf zuXmbtC30YGrCh+RrSlXQXEYpcgiB1YUnDxYHtbnljTyOSF0YjsueiKBdK3u5xd07VO6gz0Ay7Ox pSKMbouHnsOJHhrka+Y3aYiS6Z1Io/fu+ja7BDkYjPXi/OqFNsvhJIaeGjpACndp4t08QmluQKTs EHKOgqmIyZvNVmFxBx5TxnX1pVUQO6A7vCWHVd8Tk76VnRxYmF0qo9vCms2FtenDTRBzOyzoFPwW cIlS16aP4lJQn9P2jGSNV5R/RkWNU9KnK4VKH7d7nF15uKTYvS+dISjxX603oWvFUJysrmnD/Z1z T7pgHAqs77EeMR+ybreMYdFh0p4reiAFPjzBkEsavIlPPIFm3dMEUDwEsntzdSZtz1sfuD25vz0L obGKCdJejwft/dRTt2+l7FUlCJ+odLwrUQ2lbL/YSh5o3oKoKzoXS8zEbEpPzop4sfBo4OEpNWND AfL6ekoNRprm/kAJn/HpofaGUZRAVrXUGnlXdS3OkR96G3+OWrFk8dttWsFE7zn1qRRb723/5u3l SrSqTwUYP9vZKZ4Tq40fA/P+2RBmB57KzvDfS2XN0yIpy2a9JL6xmNdX26HP6+b+QqvAZYbb2kGY E8biuG8DJzZCano0se94rmaHz00isGbf4b3CzkhNDUds43joKHUPMLrcs9moGLg+WVJtUYu5ApAI PAKWDtrEkQ2jNtxlewp9jFY2BgXMeWViDKpD6VSMIwCtFRGeKgKCS+yWhIZQoHjIF47Xs8AXJgfK CTD9kr60bLNLL3+2ji6AMc7/nuGU8Dm0Bq54+/xUN09v64zl2RHchgtyThETT1T04Erhbh28oi9a ZEPMH3KreSXkm7cmky/JpsVVENbVmfecqZF158FgkE82PIuKChvtZphnpFU6m2kiCW93qx+MQ9Dx DYCct4W/qQY0xWmTmk+j5cTFFqcCpLBJlCSpV1REGtCT4NDXLB5hpR8VQF2Mb0/jUXnAXYdj0Swz EM5JKVg9GCWA5LyMQJRMIcv50GTsxfygzR7X4N/s/rGmEd8TIDdfjEbznh1MAhm1hgTpX+fqMUa8 t9VZ8WYz4dO7wn3esFJY+ctKiPYYQTZOJGZVBapilMarIC/PzHZ6txQw0Tlga1A84lbXaTpShSFu Ud0E5piM5Kz5ITtZvPl5gnzk22yHe5HfQ5peIWbC5Bj5ZQ1sSkt4A7tLiPB71Zm+HtlUXAO/FLLH w7Qi+CLSFaeHhu1MzIYesE55Q6Aj9yhjDZAHgZshIY1gQbcwNHbiLqQ965BqADtUcnVLSVJB/w1e VpZ7OPTHNaqOe3vwpuwchOvmG+DBH3PatdHHqJNvIGny6457qcNPqnZhghfD6xWAFTX5hKAwtvDa y3KY1y4w7zbdTVhB2EiVPucsQvpC10SHI/TpdbXQD/Zj4AfxCGsHUSR6qf8mfSvSpuJAoh2Wj9Dr FHiCyQWkZvdgj6EpDCL8IKreqvYnmIYE5sylYjPF+GUkVTGHjkroYsETTE9K6wDz0CY4pWN5HzbY sp0dVv0symwj/ug4D13aK1aAM3eQ117RdWjVYAX+ij+Sk5vMZryWVQ9dohKmf1SO/IdlGjYyazkd 6W/YFKeEvqo/7qzW0ydyzhaqd2I8oz3e+lN+oW1h52xlFemTg1aZEGhcPhg4ls188RFzBW5HPXbv lC5ArODgWCOZe9mbkuL0Zy87ggsd5VCanz3BfiErRPYPXcjxPtnCCdresjS5pky0FqovzCr64pjt SudSEDx/8UihbdlVJvV/G+kxA+0+HwaSphGuLVrpNjBuNGXwZ9pT/ZZ5bJNeXGVMLCkDRMrHvDQP TmX6Sx1z7TlIOkfatvJF8oVEtb+WSWWa7+URhnoT4L6DA48kG0+N7QDP+EWwIJVG07Ji+6y1/PeW IUUVJfk5b+TJB9raxUNm/1DTVDLAOJjrRDlLnnASnYVsfMQzYmTLvPKSuiYOQNBs/Y3vFJ0A3Xvr BdlXNSz3eX9s513QOvNQd1tgeeSY8hMqFlMK5Pm3lcj4uz/r/dmY87aAczc0LNeowa+npMm4qw0J pbVdGjtyhmyLiAHA7UGNXmHzhrMaZTNWEwm3YzwLXAViRPlgF7llyqTK1N35ZoqtDydFmy4uohdL k7whxoorRywJrJsAeQX0F9Z/6Y3aXEsgHN+JzbvlMlpyuJtmRPmxqXVtiPHXfWrZu6wWfuZ8nAoO GDI5qnwniNn3MlmNwjqeXxU92VI+znvDzI8XDU0Ysoyy5KmpVbowkFpktJ2rupPbk/WO+OS+Ofzm FztK070atmJP7h60kJrulAL4Dg495AXMcegL63h50jLMrWkluXxtTkU2266QxFTjQqbWRnu1HIt0 V8qjYBsgQdBGDBtGlM5OUN+z8CbpZr78Sk4BD4LmEjSvTwF8FbecsJBMBMN4BDefY5bnXToj09X9 r6a5YoGbPoBytRaNdjJKQxrrVIJ1kJ7LATKRBw5+xhuKFCWxghO5DJmlag/D10kkYeA70bo9XQ8m eLshu4XmSHyCtClACocfastSC80LLtCStRxzQ/3Xs+PjuZqw5DxoISsV0vAj+8MgZIXwOLnsKNTX IoQSkjgXbXjwKHZn/5+bqTZFY8P/WfvDjvWTJSEgBtxj/ENjlLem/H5eNEYKY+tSmD9P+opqbn9M tJBwFftpqV2okCjF1nTvR17JEuG2YRV9WZdKBkNzXh2v/x6v/+ccf43Jb6TC95D4P5BDKW9Dt9VB oSgBa7ASGSEAdPYdnMbiCloc1/+iZveSsA1TT/at+6BzMO8Uc5CKfnHoCag0ZR++OzNxXGsgn59l sO+9BV/Xqnpt8KGlB4pLwfdDWQxJlqjfiJ+KfbQu0qmiLP4SFKCbotDgFQYl+9s7QXclW3lmJ1o4 Uhz8XylPyZYSVZR3nITMqqf3hIahpZe8pMsyIh/Xz4aK8XgQu7V9QhMxgzANzqNoxHWQPv8ZPclg CNUqQCjVCEi55+6z2kSWzGFuvKcF75QyKoFjNChJen6u9Un896ou069+EFS1BmHwK60avThWON88 2dGNiJw4oS0Aj+Ca3O9ymKa86xII0L85NJVAiNIafTewKnukyScjeGYfI3QaTVlUuy3jvcU8hnsj yRx/PuQ0A/9LLXGuYCiRNbScgPMs2bWJF2HTLgyQGZ6fkU38l0+y/rq2cU+GAA/6MOE9jJst7jh/ UP4n3pNdftK6tdrfdOwAVPVrU+BonomdS6AMYbD2FXfZzccu95rMAPDbx6Z076i+FFTpMSU285vb 7Y/K5ZhmLhbXmhU34IFmsQ4OpkbSWL/bqSmMhYaxoZeMbq1O3Djp3+n+TCuEx/Ip5zWSfVABpXNR DIO9HmBJG53vJO4VIp0iRVq4ZhCx8b+9uWm34tHPnwj1x3x0RtkDcEeGhRAdemNoy5vpYuklATdh Sj7Ai18SZqcQiW11FEALtuYZI6Qy8UPwzSxAF2lsuYNBw5G8lGJWIzYgt2n6LXAIqHn7ciw5YW7+ 2hL5BtyA2NSFzRReWu0HIHRjaiRCBthZEILOxxeJPaz0/TMH7t4O2prbybIZFzeP/9jvxqGuaHtl TQwV3FjA79atzhczHFTtpKQoKAHa+Sx7o5jz9tbo04zX3CB9AFn7GvzgiG2XljbjDzmSWpqsr3Ca rcfnmUnmMjKKGH3Ep5uO2S3czTGw7KDMrS9ngA3oheTjDw18qbW/pn+wEZH/nP/OES2SMKMCT39d B6WzgTe4k15ThYbLKe7Wr2Cr0mVoe56kIaC7i5wpjjICnWsz1bc82BLELJ51PEvDlTo0/CxuXAXc ACxtHYm789kpUUeUBvO/3GHMBIrCI5t6pp0OmP9ISpgI9i9rHzFA+MHuvgHijX0XJjno/JbLXMob TqEWaIa10Azd/5+5s6nZDH+6K1H7a2ksXsPrvcVyOEQ8KA4eM4Pe0OmUyu+ntLzkJrvQ27ntELj2 WEpdQJIElsJOGHhWSG5GQRmMduByh1nBIl24d76SD3I5ruRZmoX/Pp1Cv7JqEfabJMYhQRUXNrIi Bg53ZzkMPfxT+m2UPKxbM2Tpp/jHSE2r9Qjri3uX+F4gu9yHvkpzYBBnj6e0uRAxIiROjxlcqAEh Pf61QnQmWfNHpNJqAutXutL9j1IWYCgbkEive57g8/VpyLKcFAFwQpshz4zjAXDSzMHpU6GEaPim IKF8DWPyGz37qB8/4iNPNg9aqrbTBPLedAX1xU9tuxj3tA1fZBTAOg9clDWXOQ/UlOAYTqMI5li4 CDh0Y0xb+OjAbnLMjFBAV7SvKxtr8UMvOO9DoyFl3fTzoeuTMc+TVtPEM4YPai7D8vmkJPldp73p CHfvJYsIGqOD5VrJ//J6ypUmUQPLRC6sGnU1LiOGze//9Y58RFXrcFYvjeRfBgRzkqoYsvoYSvBl QGHtppq66221H/MSuuVSTZsN5WX3JI44LMtonjPf5YZtp04dscSvzf41Om1q9fcahDgksd4MhXLd QNig0eON++FI6Rxs1sSq5zU+QC26Cf74gLClpjRQRUNAYAlYCW5YhvcyGPXJKnRo/yJf+Pcwc4CN 432/kAR3ldtrg+KSsPjxvrgMhNOWt29/9js2KkzuNwpddU+X0sa2eOE0KXQNW0lzQmiQ49K/7SO/ MdHSQu9qrSuendXjWJePLntAafsJVBtw9KHsljYKSwt7E7fGiQC5ZufeTbv4dwnf3zaDwIPJ54Nx sdFCmbS/4myTRqJPBojtPi6JZtlk57vtTLNqMLrwwLmKiEN3tRE/mGnVEJHxI3TPPeU/1yxF4di3 aszuGe6ciB7WpFK76Mn5VOq7sVlFixxtQRvHCDnaDKyOTprX0/11O6n4CX7jkPNX34XV+gI3/cGW hIob6DhhEnXIsl+xymrlAjMAPBJO8oRDZ+ZnL1BJlzUdj9ULbBfIAWqkKZhWJv4kD8XhS0vOzlpQ jFR/XtgFeO40kBHj19aqRelrmciYimERALBfs/VCvdbdBsaOotEEuZJ73W0PnoqCEzKhdza8iMw2 M9gthTG/RRNTu+5EIRsYRVa42bJIB0BAA9g3rk2bXx7M6RXsxM6v0yWl+sv8VgQmrzkeB6C6CmyE khzTbO0rUmSRPMsJTom1z0d6OOxEddWomJLHk3qMrgDBG33e0AmQ6vKBy9AEWXG0edq2dyupLA9+ n8sDaugfPz+M9gDwSxtfAjkwrktXyRlHOG4F0BVpM4bylSAndWT62fubk79O0CDTleGb3AgzF5vB JOqB3t9DwecB1UQPfkCRWzyDelXcuuo/hAUC12gdovpNn+YzGuBeM5PApQnN9QwDeA3Pvpt3MK3Q 2TvA4BLVwIqeR3hfglK0dH3koNtobeFGF+RTRONnFRjXO4pQlcbn2aa5rsJ980/KkFeWx2UZg14q Tq8XzUPWE4kijGXF0jDl+wBoO4kLXcjvwb8/iH9IHVbPcR6DHzb+JS6N1HiXR/i/JhD/1gRFlcUD hCvv7ycHXWMq2M9A5y3tElu9We3ABSFHcFKBFlQeiElXn66AgaWd74VuussZGuQ6xD4uUv7pwCCF DtRy7eNo5igN+ZMZLrr5rBvh+BieRRfcEtST3GwlzziaSRTkQ8xJBdZpSgU8UKmwmXVIMkZOo2JI PsxMszjwvS+FfiZK2oM41nQ1+er/eWkRt+LtQxhsV0t/cNDNjqh7SGSrfgFHGaOWf6DxuL1eO1Li nHve4QJ7vM2B7spUtEUOAeRoWet2Sd6Ac96iCR3zrRUGVD5UwsQCDAs+N1RYNkK/jbakcdK1Bjt/ hqmfRYcTrEpJINbo+p1Do0vm6XVOf3RfjKFVfYV5yIeXNUa/zAjJ9zG7wLWwJ3pKqcbMUPNLvRrX myeefqV8QP/A7arfGQxven/gbMwx7mO2z+Qz+9IKmgy+2FvL9k3i9g0kvM0meABeEgHoGYITg/bQ Zdvr4QHbEjwr/n8nI4Upg0TJlHeqpkVfdTLMBkMgc4cGaqBdxFNNlIDLRrgAWP2kyv4RleawNBLN iKJt/eIB7wjaeoshzEnMK/ua8ZvpaI0PpSfHoQ61GBxItpjWUPz39bUH9wmcE/6MFj+5hlZwaQXG KaYrvDWg5H3hQe2FBh/VFW/cX3poSI6OpY3eYF/D+zgEMBoYl10riRd9cWN0t7BKppm+U3bIHCC2 mS0cirhjcnT+nuERcCuuTD/du9Yknr2ycKAOkHCzxjI2x/zNgWjEDz1EN4D+YsqnSqTj6kdHZlLv VDWOlM6oB7OfKyxVP0UaVtHIjLRq6s9AhLaQ+Ws47pAEzhYxR+ixdbcV8smhXRVzjlmED8yL4yj+ Ul9bGZ/zm/YaOI3okCVq/jn/3rQxVW3cQJmL56nUFUuX5EwsholHs05eba3SwlpQ/Fr3GvPDPQmW w2ZcGnH408ZElSrJewZ3IGFIySTXsIR0yhVBA9wEQtNvw2eDDMVlVGdIUVr+xsZUSQwz9gdjdV59 cHtiZCke+oVaB2jjsQuMNwBWIztH5slzXmbR47hyhScSvSafPPgriJOg5D8rE2RQOcBs3ntpsXO0 Efu+P8i7GyhgT/CdTgHYcVNXWRHi6pUAKa4ZlFXkBqgJIsn1epf9ROUh0X4bCEgLXQ0P4ZG7tgmw X+O3MOuSsPqw1Dhw84HJHAQ2/1NB3idFoLNi7s+kVCOT8S6HDMw9ay5DnlMbea8zH4yto8YzFI1a QmUOVQr3UhtEEzLqcw4qJORPjkR077dw7D0C0HCvDAyG3bUnoag0gtpjqwA9Df+VXIr7guptLsT+ nUpZG8W4Cve5fZZT1SOcxZTZDcmMWbaL6mlzQ8CXRxjFoMVdtO3x0R86B8EybtwZeW/EbrHiFPLh fvnBkhfu8wP0GyQhSxwr81y7cbWNwlkHBwl9OojQO010Ey2ADh2aa4Jk6at6QuO9FGzUmbQ7YVEF NmOSENHmx36v8ZV25ARSJquG486QLTXe4GXkE82N90AJEm/pzn4rmdRdMfXnsbGfv/zqh2vj4nQp By+6ZnFwlQsR3nRUh1Y8dhYzGU+O3GH/IIEjuzQ6ssvQkkTVFSNdlWPXpJ8yYqKGTNNylZwkq2rZ QhZkOjnaH785jzgARhfte707ocCCd+qjU4ebCzr0gmxr7up9bs0UoSDtabQ+aSLc4cqim2uaFOYh Lrqw69ImF0cdoXVn3kChauHc2uk1qmxfoaYnBh0J2rvc4r4CHgk/C8NL6DjpeXMMMbSs91hDDOq3 YKzDvD63IlXWwHmv0HO1ZhGORQwdEXgBxKI44CjS/27AhP4lGIrM2SC158VKh2n+0tqh9Bp4M0mI bs2sEjQiaRj7PuswAHfUsmQUryWuN512D5f/+TN5P5nXulwqLtP5aucNP6KdiGuqeP38kFZKaBgG l/YT3pcFg151s4pAV7/rJVM/qawGcrTq1QL+j/sjIyFhLxpbHaAGz9Tztp5q4jPG8bVdknGuwQdi OlBNERubFIywoljGLQyApg2Uek5uc6ixQDwrr485IUwZUkaRXEraxD255eBN0OB6JaQovj3XA89U nr5w3iPKd2wAeAJRdJdUVABii5Kn8O0NzBZKRQSGEKyrzvV+W/ijUgBaqSmDKW2jEshtL1003DFf twXeqEmD1p7kXNm6gsKiTls1oJvM7kE5tnNI3pKDpd25koJEpSg33Mdx3i6rPSw0kXZixLkulLKy kqirY7Q06+zeCHEwRIvYIiSRmoujnsgRk6bx4y9/5qKQRjsOPxUOMeWHf6ESeVA1lIgo7O5nj0NS VmPrk0j3xyoRyeneQoJgDVkTchE5yUPVIjwHe6+vH3Uu6XajAtNJi3fj/OgLk/bNa6okPfkrx7AM FCCU8QjP5PyJWSv0J+REWWBzg8t/0yQo57vGf8+//I4MJ/7Q/nsf4nytSovlZTvUucSaRFqXS2Se bZPFxDVF/ZhAXGSpbEiMS/rlTNj304H+dzQ82sO/2785PW7pf7fUQCjrI+1oTBYyZTgLGKI5G/VE T8p6O0rIIb7WglWGuX3Kk1hBvYkGz5ACVM9xyzZhm6Q0BkwYqC3vneaPryIuM/GPoupFz+h0NHl8 /5669XiDF890iZfijDpCTNDuPB+8VwgEM8nGhqoKIZal+QWXUCj0gzV7H64ybEwWgKUQUQujmBQ4 os0Ms2t+p35SbgkQvw8LpkD32lWRVGPXqXLqOSoT0Xrg4pViavYsKXtc0t3hds+OE/+tgVGdBeRg TvK4nDjd7/BGiIt4lasnXg99dSnuuH2T1hQn7i6QiQdyxIiNQL4ePM07hAJnBp9JNyc/pXipi95x xbk/J9k/s9xflhGE6b+cmAWvfEySzQjaL3FqmioYtA6Vw6zi84kSwZYS1QIt21FuA6HRGdqqwG67 UaiEEkRQq9BpTtMdeGPbqYMYCfNmd6Er8KulF9j+eJMJng1Q1kYuiRWo9Gm4y+Pi9CeiQQWmT+s+ kP8aA0Ab/lJHfayz27zCstwiWFxfP5GAHxqz6kwZcajbAPYNyL7/dhNngjDkrGSuhE0CvfEC6dbr s01xhWjxx+7gLoymqVI2BTEHltn1OtKV2+QrFL/GzITdDzszpf/SW9pONO5zxcd9KpQV/VfLe6Yq CDJLF4ROsZGSiHO1gQ+XxVVj+v/S0Y5FY02V6rCvgG2DEqnjTcshVXatLIcdH/xaG3SuUNjrBzBR 3eDSNOtVnb6dgCNZHPddaLDVyVq9bwRSu8VsxBv3HGjOXBqdviAljNeucqX3sMf96908UBrh9KtX sdiHrKIl1oJprMQCzv+wS0gBq9ms8EVytkFZS5PKQevwFrDbQY7jDOLyE1rnUALyrb107EThzWM8 mXhr3btRiKf4ukIDb/+TYzKGCqpOfUTqT5av8uqBio0VL+Uhc/66FiVMnCfUAvGyYnoH60i65sMW P2IyrdqFWx8yKcKeSMXaDDpdPciYVIH7LH6W4jRh2NrGu/ACUuacKzOBeLD+yK84UnyYa8bCGJQ9 RGquwq2+jG7R3VMzTaTidz8JSMcr2COXLPusgConM+3d+okSJYrfhxp0Ig+1uigJdiMSrAenrMm9 BpcF8kWlZ1ob0QiHzCHBdxcOe3Jj9d1QKbfp6qxDXUQ5SeaTxvXUGGRM4edTGt7lipmH2BsjKvuh xObH9JLSAOWb30a97G9wKzF5Xf1KTkLQDwDxzBnQctc7AfHDg0eMHTC4vg0sVs6cO43jV9sGXyam ycEGzQPbgLKMw7wav5Ial09kMoxpvgPz6eFRnVWH/QeTRfgPxof4Hc8bIFJdyekO8bb1XY0rN9Yx 4WyAdsccy9rok8rz4Jfo20g8v0cpJ66U7CTap3OgQCehqbWcRZfHhp5i1Mt3uL8zrzixVGffL/YV JcVytw8jIeTNdYn9jMWqesk4vpW9cXoXr87BXXMAZblLfJznzmVwhH8Yz+VGayWpx5640bZOX1zi FsTL1HojKe+ga2DluM3Y4PXFlSvtGupx7p5+5DtTJVc7ZllGj4M9GQcd7cTPVZIcyRMfGGNQRB2y H/cuQ12lD8XFYaJ0jb7p97NMb2NmYPJJv01fQQzJ0/goXxemhSwuewjDRNNC0EpwrONsCug01gay u8+xiGJkWYVfem7feKjl6UGQPyzfXuDxN5smOfHUfEFctadaTH986woqO5Pq53m/ssyCrY/MoXRs Rc1XWR0LDq36AUv3mxxED3IQh8C9BuvnIr3fk8I29gRugbgLrd92VHgWzqMJeEz7oRn5etSnrxVH Hjw83wNsZSIH0pbyIedGB2q+bx6xrHTk0OKLT+OBOZvzylDfsSTuY4WFXH+MIy5yB8+eqXAYKr9p C3zzCJQpoyN8HfkV27aLS+EiwTN7EDZ24388vqzy/WVKetyGkNrfxAnFaYcPWcLczQZb2BZycQRw FFfKJX5T85j1z9WXePmd/sOiv+1TopsQSr5gA0GcdH+ozwd+1o+ZzLMlfYwOzWIfX2KOt3lkrB1F wVWG4PnB/h63vaNtK7gHqkfmEqTZvcnn5u6v9XrDeTK9ymeUsjdRHLzNnRGf4/Stg8ZqG3tlaB9Y DdoWItGQs0Z5UMm4pAiUht/a9xHnLwH/qsjQ0KEnsQ2kkavsUlgiomuZsBslLASBaZcK3hYImoyz hYavZPTZSZZBnNxmYlGlDSEUwgj3eSdCJ6A3XWs3qCnAY1eO4C+iCt1XfuxDwnmiWyq0E8URyu7L GgyapVzERCq/7eEsZ9OOQuEc2HQ5PKH7IZnFbRQT+pt1wSJ2Z+brynfIxRgMxBk/K+ZvwX4TXjT3 0bUOZUpnISzXjbfZ9LAs1CcjNVnsbpl1Dc+ITx8tBA1zQ4WNHidycmLxunruwnqwedmJC4mSKDh7 WxbdnT20N1SO19OLeGYgi8YIwo6i4bxAZy5eUsRXrLzoJFyi9OXJJclw7G6LxhoGjTsxTvUigJPO fMP1rhlKmHaBpFtW0Di2aqBgbSJ1Rc89QevJoF8r5Anx3WU4uL1hawRUhtnWmcThYgeC/hGHs1PS a56tHHmg7tOgfutu13lw6biPiYOGUH3F/Ykdf6AtlcZThBD3CmhgktJl5iBnBNds9MDteGR77sP6 nOCHJPnjdtDicLlO1CHP4PoNqOsuFV4HGvR5neVd3PdVzGLi4VKKyKK6R/8d5g2ayVBOPd9VrkN/ h2p46eK3Z0q4gGrFyEQMl86+Xg/ynPHUP+0FHpNneY08W997mZCVqn+5eVJkLOXok7BDLxoSeDmL tY1iVYlRkmXGp79rupodujI0glYdMDJWNZxInl3bpSpAD1jnlLJbg9Px1Pa7DCD4klA5ctJIOjKa T1MFqKp2RXNM6JjcEx2K4R7Gh/gTiB7spRNK7AQOI4iMWX1lAO5VS32/Qsbrer4IUbiHQEQokty/ slgsPfND/cTxNjNXKyiuUZ/TcJf1cZqB6doHBOv278kbfuTDSRBXL63untroTVy0c8sXi72wIBj4 ifTzqUQiZcDjgLjRHRJTrhuVG3JWBvxPwktENlFf2MlaIUeaezWRMKaSxXlE6MEZJEnzV27PaTRf OOE0AMKXiprcMQiI10i9G/jMMac+spPmtCOfMxqxiTXig9UCC+ZxqVcD7V7aPTyT+N4gHyx43zAx e1eIL62UOcuL6L28rzq/H/neSHBkH6tZX6hZyppxpclJvo+FYGnk786bkel4ZlobbAti/joUIzO1 NefXlO2OuKSW1m340503r8saRUzfQqxUTMMllRcM0GtiNlk0W2iHcriE3AM72P6oklMMjdn8c18n UGJUC7Wum+EgM/shgTojT1tu4J92uKXohV8SOUczKQlahm97qJFahda5qJMlvfGMY2A5/fKsAJVK H9yT5eMBHKmFW4clM2yItsP8imscUwO0jmXEiwccpoiK3EJm34FCp+wx4ymAbOnJ/CNHwIC0xG89 0vCXWc6JInDV8SthrGDVJi8oDRrohCuMDksUEZxFBDn1nzWiFj27GuhVJ3xkYrv7NtEoN/5kgtHA QO7q59V6+E0uYkUOTSCraPbJTZJAm/OjT5PBiB/RSs7cSv2Q6+gs/pHxbXs2DXeHmqfc5Uyf2c+i WEaMq3LJsRtulOpW/e9Tib3G0kIYXnuY7OIzhAVXZPmdd0ADA32ehz1cZgAAk2gri7U4WJfJWLUj d8+xkrhTv8f44bAC5dVCg1VfzA5tPyyDP/vj3MUbOXgs3/w5DuffiyamABe3VAku2Nn2JpzIJni9 WfWo9T0J4DgmMYiyQzwEIHTmxGxZHoeKYVvxVveAbowjboIwLOXfomLeTWWSDkAgR81h5+PipYhw O7eLy/EAFjmdjVFu09V5ePsilNh/WFoEBgafc9F+Sta8L6tbJpXm0rRgkVYV84XpHEJ3GkAWO12E xfJXuqXXCPEIaVo7ZzvLiLoZDQc2AdnA/KN1VveTURJaEdLtfo1pK5QJaAQQt1wAZomqi5ZRavO4 r85fCxMfjWCiZtxsMIXGTgHgjQMiGqaGl0STzG0WUL86wZpmol71sevGD6xDwVODsm9SXTw+e42E SdEonk7jK7sUbTyw0Q+SFjVfi4NLpxJ184y026i74IJFbNUmH6+jqaAYiVeTV3V272+oC8K7SVxF Y0jP4kNA8RBswqUi/amZs85z57SctQpCscppLejDF2I2EJRNWkQxhASbMdX2mFkCj86Bxw7g3qlW Frn5fUSLeZ978Hh+dHQENoCdumtX4EOECAYdZnj9TGEXVyEEc2jO1T61e34ZZx035xTUnoxZETPc FtICFpUjy0dzXW/n9skfH/qhlTtGvTB4YvgPDH3mKiaf5v87q4l+/To6GJejNIF1juM6/zMOvboF 6sSo8Ahyp9EX5MPh56Zs1AnuLPAQd6Ty5c5v38lVNNdves4b2qMtJJbN3r4fDM2aXopJMoZ8wAH6 LH5v+oLTHUMQ05vfY1tjARqezK63edWNZHvUF6gTTxUAyDFCt26tY7/sRVMiuDPxGwCe4PetqpMu BE3Qg+gZWwlgyh0Et8p07GHIhV1EHD+XlvXgmpxUR1gFNh+8x1aYcVyEtjN58hfmyI5IshgUFonT sFg6b+6PJBdNz1Wr3fIpJvO75+8vSwrxkqF+WC7i/VLfUtCeTRoEOq9IrNttIGXhgUDjD64ZVGHk twcdCbmsIBIW4phrWUc7t/HBtZ/cMgyyiMCyHl5tzRhv5pZtklXg9N49XnYxs0BCNIiHDkvjWZ90 zfAvMffBdN4990l1us1BHdVu1QBTifcVkLdJKnu+SPjmrBYqqrmAEoXrk1XAWq6WS92ziZdprPQe ptg6IvpWKy8NFLSfHiqDLbOCyM4OsY7N1isKAugcimeUwGjkLw4vVzZVAPMDO6e/V3KXWEyhF9BG cs5dXPTN94SlA3TE377N4SQnIg2SehJANvjwKXMIJuAwkOaZnfmBmdDAzQgcyEXaEEjfnO9xqvKs Z60gyBQFnOwPwnWJIYhWy1hHjdIHO/H9t2uNAztMczMZASMPJWY9oqOT+zYhlU0rZ3ZX9bVI2wXo ZpAL1cZKoDSiZ4Ms6lQmfDIUsAq7F9dOzRNrIpMPbPMwb1I6apsdmRypzcVBvZy6Ob0UkdUxblHC iXJhXlJxJK9EqXbiIuoFY+Q9IvKZWQEWQequ1xJ97vEOQjcz7DK6izXmiLg829Vz/mITL7SLPGdA UH5Z7oASNuxWunkXHacgx7NIZ6M40MZpX7A3PiHjUljbGRRw9seFrkhw96fmR2TaNBiMVWN5KPJg +DJSGAOrrGCnVJqX1o4K1gONMa6V5Zvx5GR5OCfzQ9Hft4NkB4iTWk4R63DljA1nO3mVjUnQ4LZW Xl/4Ly+Su0lW67lv69YT11wrt2Mjk4+lCKFrXsw23KVHAD/LGmEg2a6tAVgBzlO5jrsrD5C7K1ik DDuKBoNGQIhHC/kMf8IQdyl586VPpxAH7YjaJxn8uQs4MNKMj6QUzK2AFECfjO+ekF/hzqqBjAQB jbDsybAbGbEO8Kpqs8v/VUQceLQF/enyGBZdESzb8v1CISZUrAv1cUoVJRlsSndOGMSdAK3+qH1t l25X86g4kOJSh+OIN51Q6HskwKSF1hhr/OGPOMYogeGIWgYaHUdmOixi24Z7rjGauJTVMbEvZD9Y wdS/ZerQwB2f4HFaMZGnm9X/4Ii91Q8fMFJXlGeXMusqoi4vWK9n2XwBmNN42RUzh67+kw1vnGm6 l1+i07Vhmxfq2StwgpXGE3fcWdI0hO+8cIWL0dr7iKc3rEtS/OTmDqRNYf/TV/fohtMtfU5KzviI b1izbo/G+Dd7N+LHzOcNV2wTRkCY1hC8GgZZo9Q5+OZj6kSdDtGGjiHZ6k5VdRqzDKlmA2eI5Dqr fNZu9cbgZBJcaf/yJbYWmIh8r04yokASaagACN3DOdXjLDM3OQ7sFsQybUDjAin+ThEtXuf2bMza HHTzFJDQINkePVf3/tUTEyi2eyR5CtdMUTBDCCwQ0r9QFfGan7OBiD0kNqzk4qhzoEzvCdGimMKB 7p72cPNeIDSPHYJEY9R1XtFL1MiDe5UCmlanPeWecpK7bFg+VvUH5h7YM2f5+EVGk1lv1YRJkY6W NO8saLs9OFmBEfOsL8GN16PERw5dtvfYWsXKGhih2EYpFaeYm4N9EQ/3TyWoITIhLKP24wcebB61 wXomM1MnkRFxcGiHyRKLdbvaDAZV5Pq4FJiSj83hIeiQQeX8JVc51met6Qakgs95NiApcvPZSgpW rFU4L4XtTPSks9zGMyjStniwRzGxQcMZV6O4mkrjyKHqiFyQLWD9Fpms9DBq88TWNRInKQdKPGL6 RjyR6B8njs6a9LHykkxihlAroqtgJUc6rt/aBQam+7feFRNb2X4sOPUFhMMs3ndWokktM1UriJT5 WCJOc0fuPGyKiPr1gAC1I6PiRegwwfzgz1zsp8OTF7kIAdhWLWIKTOEW6LS9KlLbm5L8Z0IXv0XX +an16EC98QSoEmmbRlwwcnBA1tiJrFqhbu+4A6+74apinoYNnmqukxt+4ATQSMtF6LuZdYq10MGe Ccy+D0GPeVk6htIWFNe94ywcxBkYbgTG3GJjSHRPMcHFiBhysJCjI9qv+s0OYca5FBijsrXRDoRI sW+93Y9ddFhnRMgeWs0zDhoBH3aPfCQeItZV3DdNOk2JzDTwIGae4+FtHteix/r9L+UAZnWJd7WR oqQHJp8+Ns5x1IDjO1N/ZJyfhbw/RaGoL6YPk9r20yD1TEh3ewGXWMwCtnopKzpZhq/YRkwQjRAJ TEerW9Y5u5o4Ef8g61dn/EIXVg9SnwN/Cy7IApowshxmDBUuzUelA+9PTFFk/WSTFQIlBNfwGQOJ jXLQYFH0jcW38ca2dkB9p4tQpmsEbhgjqFQBiDHK6129+YVJjJVYbfSguDGZgJ0z8qMKP0G0JZ4L oVNsLegoR7zyDeQfKhduQBngWDNaSGyEGoUhuk6woNZv3TIfNuvE0uzqhapBAs74DHT2BRVqPr2n 58DvNuG7HzyA7n9qomj7AsTtvXRiHCWIeyE67h2JbfR4QoartedSDmWDGeUPdhxmMXWMFFI6KS5x WULKxRpmViwFX51fJuHhl3h8EpHeO+L775FSysP9OgjfounDeavbUFrZYwbz4WsA7A3pCMZ+pYts ZDWCBX3krb95UfiLCSUkm/sw9vOuy7Qgyd+R68ZdA8SRNSFhdQ6iz1us1UIJke4ajhWxH2kPzAXb tfR60IYYVMXHwBnkoYCN9hUafr1wdoCrrBVKJ41qGW8ZqZHlkvJUCwCwlgDPLzHzLmvsPwXFOlEV LhXBhBsseAkHSM1RQ0K29VS1JKZxlQwageXWaRHAd3VtHl/P+kDhT9enJSjoh+PYZufPIh7F/aWD YLYZ96Tr7F/B4V+JuFLyJT1v3F+5tlgbQTJACnhW4qD9M08v5nSZpMCW4Eswws8nn4sWhgJ9ZX+X qO2SLWqCSXyQi+gsWmux7d2IIc8qJ7Pcc/T2aLZfoE2YOGMjJq4EHoIg3b6I2zFaudEr9vzE1eaj TQDptSghMYRQLepV9qT50lFl5lJdPioOoDc/wBppH16FEOJ+fF+m0eMc1x+dDmOo4l+RmZnQabrW iaznXwfm0qCwTR7TLnduxC0TD5TPpEnRZNbTzCPCeY59YTnZmiqApGfph43emGc6mXWaF+Ufnh+U wHOxZ4g/rEI62CR1plsudGtjuAGCLr9MLuS/eltYDWvxnjHa3akUVWSh5ZDWMarBnC2jNY4cUaXD HqI9PaYcGPGKfQGFfRBpyKExV8XreZBklPeBRQk0ESaSLvQlKu+78Mf9rzHW95yxy5XO9doHgcy7 llM9cMNk/lnjr4IbZD/QXI4BbQx+HyPv5cG42i+tZx4LA5sGxQbL697e4PeFSpZk28/DGzWwN+Rw P/oonpQPMdV55cIBP0c3v2JdpzHUP2QzGd3ociSgDN1Km/6jlz2bNSIxZZqtBfxQHOI4TVA0ezWw io7Qn9ZeXCFC0bDi07hjYLTHQvSamx2lfecnGkT65pE+Z3nc+Dqj8d8W/JVskgVxdLXJe+RrzSvY 2ucriz8HeJOE50jNju5d65Yt3ripBebdGyzOFDKDXRlE6FTWO5yxO1gsZxXd1lFW7wEJKQ2sU3GX JiZuy9MrD8679+GymeqQ4/FHdMZuqyIoMxhddJzYiLv8ltfqzoju78C98y9lPCa45xuD8+fgAYUQ WTJJmvz+kM3QVFNAnVIO7JvFmt9IQPMFgSWkdwbn96RHPIfWLeNhz0jqhkzWnjY4do6sEDn9Ih3z b1NVQk2z0uUVlNTdAPutauHFnMGGRpZQ+Vvm5xJIGXiDMtaC1vPXVsJILtSThyzaJ5cUdRxPMRrA lN+zh9yM/vHIqDfN7iBQO0kMcUzMVZAnCAbRp3qE9+dUFhHmXDENH7iwabHQb+22kL7gyj1AF3XB gAhcgY/cYTcLZ3WB62sRCNV1cfHZXrbfpSD1t2lmVaBjJ2Yc4YPnLBQ5K8U0tUtJxWG3mlijYr6o rWACGy7BMTdnogkQPJXx0EHrZhAN4QAIUqVEm8XlEsgp08uJwLjx/wk2vfCnsSP835Q9LwWneh9k GzsmMLMd2YY6rSzzptKKe4G+EATtrCgE8vnvQRH9SlzqocsCiHglvY5utu9I7D+em/JBY1tBUc6h njqtpOBW39zqTBdoDwOjKd19PnPqXSt9mQwOesn2l+wJ91rziBg9updS1h19tKZibKHvSlWihxJL eYV6trPuxcLoRcUDLpViTVF7xJa/f0sJDJzsrsQ9uk6sfa96Hke5sVtJ6MAcJn5i/+uhm++nR+g6 ngMOEt/WQ06IaOq0swvXyBdaq2W8U2XSQGKIrxfeWttVIjVgxmjSoiptn6sDwU+zQVXUdYLhkY5K /Eo+d2c5oaXfeKnJ+3YsGZ4/j17ocwns/Y8iojPR+dEbdnVoahzSYSi4YA7pVtavc/fhzUU77asG b1Q1roMArF+sAUqdPa6Q85FQyynRLh9WActCHCTGtM7zyRLyikolbou7Su6kjk47Z/zej3PshGaj 14lAYSqmR7OE1hOq6+qlh0woP4NW1wEErpBjt6vP8sznj1wFgY+SPTcZfpp5Eka08Cx3q6BpUzFs 5C8b36kLGms5v79habU0kzR6ivApOTgAJMLuGhVh190yKDjGBDWHpVXjTHVOf3ZOv4O0F9Z+tMn0 5mWAhHx3KrKW1IzcO9sgBijuUBb8s28OG8ezd22aU8GXQwf23fxASeitdRJb2mpCytt95j0hZrx/ gpCd1tSqzGkJNXiWFfIb/OxM+amns3/BZSyvRGca1w23+cll3lcO0W7QQrNzG5BgWzCHq7v/qJGq YQ3VSRTr1j8pREv5jyuUdItiWmRKUniSSu7lUpqdUltW+Fl/pNpE8WebeS+NvD+IDbg1mQQtl2C3 sFsQbjX/TAqYztwv6nObVGamhVWdcl/L9wm7uomp2ZqmvGCV/McXN+Rh7Ea+G1RqFOkdqdrRbhFm 6aop40mJPwjZVXOiFTFo19VxYtkaI93QzOXx+X+Upb3WbjG3vD8G8IRfBZ9Va8sxT7nIGOoeUGiG a9C08deCpsg5wcAN2OsBaOCp2ZlbUE9vuBqkyWQFIwBLZCd0LKu9eS66sx2PHTorwOTmA1oFNgYA GrqtjK2fKvQqNEYC1GDyFGJM5vcHBfmqHxk3VaewyePLuHj3aZu/NVEg0jHbrnZAHDzGFq4x3tXn 7hyVBB6u70sTHjL/SagkefAy+z86YaFqjlILfDXemZ8xG0LI37ZTIuzB2YvB8ZieHVgLgpiuSmzE cDK6LXSYAiUeCMyHzgBU53wS2fBgYMFzS62FAlz9fQLxRLRz/ra0TlOkEOlhbWrufX0ZrkZJ8vwf /1TqrJDUXvS4D7KlKGsopZcLJpZsoi/jVN3B1sOloKwaOKjOo8WetPT4qBu7je80Xx6pB9NFpnuF v3x6bE4sC4++xtT5YEEwLpuxuIGELcsPi8Shfht1ttt7Okr4gUtuUQnYTedVVgASsPH3ZnbFB3+u +hN20cafWlE9lKUFxCRYqsvAXGKnxIvsPoXAjAWQ2KVMyxtHLJN/vytakD61kVKa0zcwvngtJSSb eXz7eeUrXOhfBR9MNeIP1Z4e6QQ/uwS4AGW/5KtNlZW/5hspMD0rRiCd/qZf2bKPe0D9Jf05FDk2 vAcZ0aMYiiCYFJsYPKRb+iKGtRkHrAkdJsRwUL8eh91pq6gpntjBm0jx7SEhrj5CNJzbkwyTW4rY IUHK7y4Kkd7Ccbhbvm3HPGaA9NveDF8c+NAfCzuqP0cjLr8D9MjsK6QidJ0eAeGiM08jVmaTVdl8 ze4pJa8e6ioclQ9YW2Q4YoxgZQN3EqFXBN+DS2jYRDQKBdkOBZrg4WboV8fO3czrZRfSw89VxL/z f3ABY+QGFea6gmWI2EfopLvIlPMff2q8dXOwubOnQl2o9N2yCMdbaZZ5fEYlo/v+CnSP/4VL60Ra pvd73ybi2pmhvvYJVFnCmFvmZaLBFa0g08mtRe4qmlpXh1pfEBwiG2ROy6zs790ZDgQtKw/Fj/64 9hRHM4AnhAzvyZzjKAHckiJ7vR+XC/JjaDdct2sgGYOGR0zm2Ey+Aeo6wwD2h+m6zKijEN+ZQ2xT 3nu2wdOeeBlvUnHcbOT5EgsNABL52X98NM5aFnfHLkUPoDdSdrVkk7hmJm+8HZgQuQH7J84FRH3L t06mn6AKmF1xVxcfC0hBa9Z08JCYmt+1rnSEnMCw/topQAIUL3LOkGlJ/jvjCcZAnfmcyu5cNA9v DjoYG27AgZjXjN4dLFdWSbSyIdFDW9Qn2Ue4xP7Ho3/Ma60c0BOvdMFftWwkDcPL6afgQb+mP1ic 3Gx16hk+PqGOwojcARFcBRpeqQS++cb3DxcG+FZUK1rNQA+1tbB6S9Xo45V/K1evF2DqT3aJaVVK eYEm22wU6XeJjBp6Lh3ECJboELoTcNn6T/uVRFrvnT3kMi3E0hc7eMa67IXfULZ5Mb0zqcdLv5gS 7I1VnI9TDCNffclWNkYqvF9+ptrwAs9JfOT8JL2o8mODztc5qMxBRVCqUNnpS9Chrgo8bm/A3nAT x8T8zdMZWUzJSfAc5+Koztg+mULiV+Rg7aCri9uR6Q97rdc06k4hPItLozsTo5VpUdR2SapRXivd qs+C5bZqKa7gaxwCNw61h644lnGjRXNDBddFTh7K7lSgDUbLGrA8ticR5lPhP67e9r6SNMLd0dBL m3mYwkwwABt5iWFpeCFf2Rknqv4bZ4nC9dYXQXBt22+NrcBZwW+4951kNYb1ucNeuH5R2NasDU44 sUwrDcvTjAww2/9KtTmFAswd5dwOUSBYo/d0/CG+aS2s2jS9mj48OAP/3bcVp1WGu0yQCqkZOPJy yl2wMDeO8ahZ+NHW4ch9x+lze5ni2TFU+xm8mBHLaDHhqFdknoMp/ba2P5xjcV2g8i2QcKDssfcI M3PMC8E+JirQtMvOmWjfEMQhUMu7KJHiXDLUopWWuqkSYBQnqM5EtEidvqoDlOLTqAJZNoqASP7V 1U+Xdq1ljY9Wn68IttLHpMXwAQf28w2+ASxN3M30YPDem+PTgY1ifLqwTDCV2N2MoPlMqTV28HF9 a7bdI4TzNBEjq17GysEt/N7fu+TNXt1vQ0sWMpZy6H6cqdMUEd8EG8Y/iQgMJooYSyyyAea1JJcl /UgOjNhkkkTpQeXQzdS95GhyO1AtyaPdwueA50Qh2GLDBQdh5fCafjHfLbscfYC993lRiif4WRN2 duym/kCMYry1i3ajrFVRUyuhS3mxjD7+WTPyNmM7AplpVGfZMJ1ssQTSEhpuf9AScCIjcepQYJ5R FzYJScqKbEHQKpu9ZRZv/N5YMl35zWoKa5IizWO/8dt1q8pqVmSpww+msgNZmVf7V/9pNaVwS0nb 8BpT44OVIcBjCCTiH7BKbGvFu5f68jqt1s/h81BvK7HNfz2qjG2PWhejQdyyNpGZFlAjn7cET/YE AwmIaghn0kvdqRh4g1ssJfI0bh6FRX1UFgQ+Ix2655zCuQNNt8PPfyWtnHDtuM3TCg5RGTCSVz44 mfbKWG5V2o6a1Ajq7bQoIhkONKKCTBd1ZkUu9aqkFelMqhpLJlRNcqf6oUME8Qap0wsC9lIFj/4V YZ3UegZSIbFlt/TRc35xaoigBrq+pbdwnO8KLHUlpqM7w6DsZhhrR828W8AGbETJ8SCRxDr/dan9 vk/ZDXBCJisL9fdQtF3heAfFJF6MfCQ5MrqI7vz1Ux5HDYL48W5XGaKuSnIpZKMH1uhkc6JViU2p 7lrPMlKRV2Dxz8lhvHK3r51uGmkjn/1Ui4m1NRY1oe+cvHOsipuZk0JGKH+3Z9fIbkjmM7HJEHex kY3r+VqLl5n8lbeZXg/mZNPnBgYXwhkP4e4XIa23aoFPnibYsuqBdYmOn4x/ILJ48e4DeZwoqbQF dazK9QgxHZOJATIUp47tXtTis+SqLosnxLbmvN9XXw0t4Rmy2vlqomjAancAKgKLWj8ne0DIwV4U HG4L0KLrWo94Ws/0psoWXHS2j4vz+LyvxLkEYraqRMmaySOwG9e7vO+jzRC8yV5hqZcLGxPsib+U oDoYJrGRtwqFufr95WNha7xwiguyW5kI+RDDMGuy/dwtOFcmzOjuAs8YoMVYAnIdE8knUfUD+Zmr Il4gaf1qJ8IfN/EZHd+167cz5Dc8KK3At7W4q8plhFSX3ytXtRmGPcCG+OOpVXFtY+Dj7XHL61BV nMsYf27FlWLrX/wp+3J+MVwsUBQoI7i0RDY+fhhcbCFlgivZEdGbB0/LT+xxCgjn05gL+INYphYM GN4h9wJqi1F0oly5Uwx2gka2t7OAP8fx315nC6ELCusTy8PFLAuLDxkJF4M64QlGjSPwCp92fKSk OorVyXtnDmgp0oyYkF9XwsyIYgYDS6jQml1r6VW4lKELjMQTt7qcqof3owmhmhhHOkxAgrNcE7Rq 9wkVQz/Pz/UKm2Wn8gu6efMySFouFryn1DBoqD3xp41OA9oZtig91/Q/wHmF/yO2Rzp86yYds0x+ 0tF53ZhQfMIhQ+CUo+zZvyZSlM07DxCgfgdFCdrFbwtodAw81VmKG6DavNKIo2RRM4rzJJzKUuE7 PN2ao/h07P8G+epq3Pn16ST8cqEWmt1ecC1jf0PPPVcnTNDCi+HcoA5cUjlyNUh9GOuSgC6kSLXU yiCRgmySFSlbD2JM5jfPkyZs1tc15VNJoB7NRUKRrdEh+4l0zKPqQKE3ZHApajs3HyPAQruQ7Jt7 6OiueRRjEjgYpYgeWOEBsBGtFNJPBVXnIVl6tuGIc1YzGZByWqBKpDcN/akjyIcIX+2W1dqD8h6q 0dFoOVKrhzFA2CfBU/Wx8SqTzz27BNhca8WBkd15hIgLoBqviM4cUHZ5QXoljtyXZQE741c+s4du qQjAou6AksT+EhLe8u8zlZlFOMFYYj8Vv4Pqh5rp7r3ccP+EF5n0MqswXFa8KPli3hgeoCzVFBbn aXIqJiFUvI7Br9xcEc5KwJ3aGyz7VKynNasWrkCgXAsNk3dMyAqdj89VTHjEm8dS2pKSLyoJk2J7 Y53+A8aqUuuKwnK9G3OzAd4NV+JD/BtKb++H0SqNy/hlUbw3YIdPGXNtvxD68d97JiuZA6zjB/6w 2EcZrGA1/6SiM8yxYdg9c5/ehy6u0Ccx1kc/dhLS2OTMR3vd7sTfWOO/puj78v8dXEzGjRAlVfq7 T1yYaDZdoV2SwW88fS9DP+M0DFx08M69JU1Uzh1DoNgoGwkB6kLXtou5aU0Rba0lvXI2zzqIxGHE ITF4KN/EUSuuncfEVxbgnm4sIibbjOmoOscf7kbjZzRdJM57u7pNC8c9OvA1KiExcc23e0+WCf/F /x1A5KirqfxdSwEg1vsspR59hcCKKD3riwRYO+HvlHhdSCWL39N4Oi2YPVZnPEHeuY08Hfi3IPSS pL66rMf6Xtk006dTPxlf7hMfjZRHFDP9NdtqFyMFn3Zd8i1xXau3y13kxGcx/BI8jBiM2T9IimXP h/08tB7KTaJnSSRAdj4J8CNLmioCaEHMfEL9BO+llmOx4o3V0IKWMdtXw0e9wccAfYVd7B56o7lf yehA1PsRg3cPw3/P5dSXrc+gXeHSYBxaf9MWLkV433dyLU2+D7DrF9Ns5wO9zEySIhVPKfFH+Ygb lMUBhqcO/VXq2EJ7LGSvxXPizFEbznow/We5LTAOc3vSUC1nlUbYjSYTh/JY8Vf4C1RZJfCglwmb t+NilZIqjU2wHISksn2zVqbktHr7scsioFvMYnmMy2Qx/cIjDBulmK9RsHPnktq1aw2IGVL9vxda ejn26r9ARWGc605qclHl9XO1hFxrcQ+mtD2wyVyhWOi3KAUMi5IIIvvTKVb6fRgWcLsPiD3v4nvu kpRINN4Lu2DYyLOcTLai07bvFbO8aTqgvcxTZ7WLrlNmwbAZCZ25zAN1E61QEp0HLcsl1e4Mfqe4 eXEmUIEahBkrGyEwC5l1zOmVDUZG5kTqTdqxMesxEA+As6cg5FhJCCn4d2zOKvVsB+TiKDA0ybV/ mXNySfdtRejPTgBgr6DKi2N1iRMkSK0Rh8CWU9Q7rBG5cnb9/Xzt0UTWDGVn6gSc1Bgm0T/orm3V R02/AJVguKqGTD8pA0YXnfLPc+BzqwAkGchPmFVqgU8YJBnfgeV++s1Dc3a2/rhVe0xZDaSVyDLf f877YED2BcGE2EmaxyfqGIf4DOE+YQMu6fS0/I9uGJqeyblb902+2syBYdaEH6uEpxLTAeWRZHqS J0EAZhUdFJ2VVXTGiOT9OfaIucKRnBhqQl1JsFHSIPRB3MH3XbVWk1UjAVVl+pKz90LBKJbygwAV kDrzhoIXCwQMSyWQcdJ1P6AMikJYewqvrNxpl0ScHKknZMSVuVuZxUPRYC/i22Ct7LP4wIvsc3mG 1EmyZOkDUrYoMGxWvfw81/5zsh1R24nUvLFPK2fAsF4XjFs26oqI3PH0UQDMBWtp2FmH95EfXNKQ ld8EIai4Jwg1iqR0jmBA/dL1mxyU0OeMCFki2TOFG3mTbJbBn1IafU2rpq0bSWRtxrTriYOwphBw DdNuliQfSsu6gpPeqDeSvh/adCI5IZjPbeOsgdEajHGGw8nZU1Cly6ZFkms+FUI+9Z6EnXRTD4P/ PbG02ve4sER71MSmAkZ0OTBrB+tdsBQ4OkgEUnm3tYLIkeOvnmzmPo0eG6EXoUOf0DGm8PVX0ffq ruF2Hhwrh8qPRirfSxfArOY2myZoU9ycVcmCL/AicUFn/4ikGh04po1cL7oGmNqMTGU7Xg8qBO3E pPZMKha8g+NUARlas5T2x1hEBphNTfpV/R7xBxl7/vy1khHsSdM0T7NOOWorde/DOvJ4GRt7sIud R2mnAJZV6eSB9PkPdce27HinadNQCsLHUEDrijx8y3qBMtk3aM5nstlyxwr48tvtO1Xwhg/UkDms jFZck9ehFvKrmz/M6jkV4owr8D1VbyF8TC2fj9RQr8O3f/nGFmpHhh2Kwn65PgJTIFvh5uTbx6QW XmdYpL/3iJ4RwCWwBimyLyCBwJT6SEVZAw46u1gYwmujKlgxhSoxYF8tQfyKXYRLPLJWZtD66gU8 YaUR/30Xz/VOde31Z8Rf9Uun/oP/EybtOsFEebxV30z42i45oUA8S9QhN7DYfHbh3v6bUCs6iLJl 6epV8J5GV7lUTn+a6m63qXrzvof1FEmlehEvN2PS83qSfFSiXmVDm1yRw8gXALErBvfpgZp3FSJ/ nkW6Mlo9FXaTv72//HOHW4WOYdeSVoG+P+JLzXZsiFhoOPEYM3Z/V5ihmxCBOsST8ZFoWoDQ9ZyU 9kZcYPxaxvAB8YjQJ081mQq0KszuES6L4yV7kJVcygR8hv/0HQ/KalhzNtmRUnSt43S6mjeq1suI AFFzHCpDmLb7ezEoetjv15en4syYdbIW16Fxl7z/qNXBDAjkOmzERxUGg1KSGrI3iefcg0Wd4aCA TRuyX5ZHiAv+/du6wL0LbVPoFB7cSaBeYogHfFBMluU/rqmHrClmlfIWClLTvTbMCcOF7W0B+yWF gTi7obyahMtN4JogbX8Ug/nBicdNnPe6mL2N25q8EGo1lrSryEh2icmraQzNkihAzJhlalwsKyxO lfjlZoM/QBfOcAu2D1EsRFmiCzJ/XxZ3AGTDDjwyfbE3HToJ1e4wo3i+fVwoeV3O8AVhxuQm/W2j N1ks8rcKExX4tAjt7nVrGKgN7kQlWvkr643aLPq7GaqSmM7TVdvJqDIuXkRMnpbz4hL+ByWEpAS1 2yNKBLa0ZctIKYeXvyak1LdImgsMss27Gk+usgmxY+EYqvWFh8XXJtmVv/a4JhjEVDEQ4YbmtZXN STTBwO/EqeybK9YZNseMDwRDFN7mAx/jMu5G7K+oFAfDwvO0vKPlJJlxmeih3ZwaIHSsJk2Iqrxq I+ndRllmth28SehVJDPR/VbDQ1Y6kZP3+uU+KJIp9W8JfScV6qvVmcBLKVDF3vh1qJx8RWDDlMmK 9WqwOYh1ZAMWDovnzbRx5MIkGihHrbCW5fzsi/Z9EWubB9gdjEQSOGfTlFGmB/67LgsrFvdftXN2 pDkfDKbTF5NL/sqnVX78v7MEtce51xtsYrmQ4DF1x6x+vQcnFI1lGKoBz0Yy+rFPquLEdPVVbq/w OXlag4+U49adsmLchMhN0VDNA8xtCZofBAYKabjGEzySscgVPZOp3vTKK4EjLS/qiUVuD+vsi9k3 bhcIWu4NGdo5BbPVakf9OwL7VGKAokB8lZi1qkYJ49Z5CNPTuLvR2tqLAoF+kETHYKHS7/m9QEQC IRXKndjxIZmaAxeeFOH0RYJv0IfCSVi4lQhowlfIUkqS/BgnL54WAsXJPX56HTvHapFtWxtzM4E0 N8a4Wl/xene1s9PoeFL4Eluj7e1MlC0Q4l/V8wJYeTwRgAhCqhvM21QxRv2ycJ+ax8a07LioNXKI wupz9VHszxYlhiPm2vWe7sOHf4KxQOUqrDiYwQZZH4wtMdbatEa0XLihCYS0PgfXfkxqLMlYPXx5 S+xMrF8ZcQ2nDmnnz88LomCOeba8zVjmslGiLknSLru1bJWO53/IK2B+Ywl8vFwQa3ki11AYutmK 6nJGrcQD3yIeAt7YEw0YRoyEAolPU0qM68PKlW/40nEwMIVySgYDZBzGj8OCzbGzxP84/uLspHql GsWAqjCGa0SzDrk8k4cI0AUhV9m7Q0ggcy2yyx6Fu3o54GHkHRVWp5UHyjmuzxWR+Fe6HzBgOeEo 67U4Q0TS9H49Pe5JyIyVLQ3PRKTHdFLmaIIDjcDExmiSKjbzJvmvunKkYw9e8fMVXMqsxcdloQ4K RiVE+Dgf7PGBIi+bzOdadvMzdwHyh9WiyClxHlirtTQ3uefttz6xHQebH5PCH3thQVClk/mP2AWh KJTrXsX6L41unq0ZMfv1t2B8Lf2R+W9Kxt56tQRI3T60CagMtIkJF7oLpgzT5kzCPMEwSO8L1KHr +r8wER9vIz4aUEzxpQCMxG2r9Rrpa15y1++8V56na4EnnMo+UeheYy6lprOtuUfRN+b88dZ1gnZR 6MSE/KjG4vuPUbzou+3POT4un5LGICFiUSdEHbhTLy45zlg77//14AfkNp+omiSWAdxh49Kfk4Se WkSYG/MG354MkpoOhOLFcSD5Ggm98SwL8KxQaXpmiwuCoGEfyVi/vbd6eLC7BaCc/7H7EMnPXQQl o3zfAhUNnP8YhFimkE108ucABisL7sCGMxzA9B0P8ZBEGML5vj94GF91duOB6wx9VrwX/qu/NK7q b6UG+081cwrAxLFJUSRgKG5lzDfgFqW9dNXmML1fmXPpB1rUBGYiz/6Kgb8yKlbafrkvxNdG3d/6 80yPBI3K6Lmlj5WgC6gy65ibfBQr3GQqvdeuynxS/Trxf/IYpzY2qk67Wv35aw1nFGK/Ctt9jq4S +8F/Go0E5N+wcysrTNgZzDd54BAEiCcu0V4c//Bj8udbLtHoF024/6yJjLR51k4dvC4zBFxDo44v MQSlIReyvQ3Mvn0rQtU0oGAqml+eJkhElF5JjMHsz8i7bFB+gPL1RbvXEBJXUqf6V21y7JupB+Yb V/9q4YOszAvGiVA+c8kOlTRTT+YKa0ok4WYuXRncX8tzWlpCRgyarpoClI6rrW0VnpO2bdsNYMlQ tRLFYHd50S2BwLjsdeS9Ebyu/8MjRvNVMTRvjc+5yPId/ciq8YOp80eHlyNCRCXq+oDTZqkMbPnZ aammWseXBwESWwbES5w4mttxVAiG+0Gq9JR93wuB5j2vodbymhNeYbEwTAThZEQu3k16hmwzm0aC IVDYRcUz03U9BPZEHpO6FVHqGFttAaIgHdIyKoHOjKC/gB4hGS98YqOv+dmPw8bYLH5NHCQSWC+C m4qtEH8DImMlOYJEzW6B039E8NInuQdlMXyrUdYZHo8K6TPuRJN7szWe8jDsgJ77vVFDQo9z8zTl rRiPti4ErUYCaPZONqD/aqYbiIIuliHmPeedo1yPC5vvTTJ4op+vWp1HRg4gibO9gyl5tpWkq2Qi ACRcsAPYR/oRPaxjfskgfhSbNtWg0mHHTBYUWPE2hG+58NCFRBR2jHan6qoEaL/oc+Z0H64cSRKO Bs9H/Cg33i99DbZYbLKNa6Gl+st0qS8bQLrZ3frr7WLQFflm5W3YRmFATvxQhTvldmPWGED3akms dd/KEzGS4q1NXVVOLt5KC060gW40n9RmIg1g+48dKEoCHaLLwFLgHEhJRt5TIjzydE0YJMnZp03Z zYrHPDkK2QRZkoYBuRBgLo/XDh/oFe1J4SkX6KzJ9sIGjltVYcQPsUMUoSWXHRjGPOij3Vxfm5tW UJzqpRNy4ZHYEYcEKfvwPYu4YP6M8x4Oi0ArbQIOv3j+EDKBYmonZVodw6aF2dFtvGtEZgmCnyy2 lw6uEzT+IXfzNtG2oIeFpSt5jmLBYwT4SKsuvyA1uNV+Ks+x7rGZRJ07JZG+qxxBSmLuszRivcPC xgv+u36zdpQWLcX7IX0Tdeef36mF7aqiuoRMbBGt7jWkMNc1Zlu8V4mLnSrOi3BSzzn48J1biWOV 3M9q+yQQQd+M9Fm3ORtpOQAmYlK6HdGHckih4lRYvWBR5A32M+EQlft3OwbOA78XtTrNLbAhFybW xvXXCOhbtAFT/XYtLJPFHvPqgNFcum8jbgepx6P+Mx7AKm9NNzDsFt+tVwkLSypoWzVwW2vZFskv u+wY90mWJBsu9VNROKhpDIAXLIedX4aVr+52KhocI06qiS9JcHiylmimsI9FSTyD7GSP2c4FvpQh aIoEymNAecPG+W0ilW64UoKb8vMTENpMRWvfHVbPCULPgxhDruMeKBJfPbcru3EHN3nHDeCudRjW 5kp9zhyasg8qfeGCrmKN8y7sA06nj0bf4leQf+wWefuDDQxJd6Z2vrFVEfXJCDsPdBx7Mq7Mz/UN wosjoROK+2CLj6Vwe2bL9YJXf4ASoNbgz5BPgE9YC9YmkfPBsiKPfhy5x1dmEoe+vv8E5rutmqOa fHiSiZ7TFZzDN16Db2/dAeBI1am109VJoXGSYBcoosuOBPESmkOx+diGf5hBBx1DPM9HtdCbQWe+ 4t11zXxjl9CKPEGf4rIvdtGQzGstOaDNYG6DDdOVRAN0J6RoSbKeAZDFZ6oiVfxttx0v83rX2i/E h0XEPKIgBjv/MptZCy/qGStFp8Gm9fxs5PlCcZ1tnOkmsae8ie4STg3/mcijBGKbRYCNE9VjWIY7 zm+NU+4DfbXpf/w9/EO3IldTyvnXWNSiUCIMrRyMYYQMlwAnPVaM1/4nscRjhGJRweRXZ+oVz0hG KAyFtVgCBzOw81lvCdDr+Vve9qKvgxJMv2Ie97w6KMJFN7Uds6hqv5EQKlnzabTfxufvvbcYtYIr fwSljOhG0PcfS/woM7MeozFLAox9NtpMW/RFng++LvUcnhXesC53gSWp1gbXGwcfyNMvMk7R8DY7 c8hVoyxOidZbFvrWQXu546oeLd6RmEd4rq7SLP+ejOlVdxCWfA9WYfB5AcndEI+56G747Yv6N1Ud 3TTbt6+cBkZwuvuDJmtZcD0cpQbLx8lCu9Adr5ycJZiPz2/W0v0hmzCQQ8MsRSt24+wvA3yczhWU tz36TGV4GFGY77GDLJ98Alffu40UD6wNbOG5PGIhf+pRbwP3P2991t9n97FOVb6JtyycfW9tKM1U +J2EWmCgyvL/Otxmo8zm3io2c8N9jIEGIU/b7gIz6qUK6r7/of41ylQynB+JKnf/V8pfmMDVJsBs rHhzvWLYlgdm4T+tKEgH7h8RZdYheJ2pQpVdBjVnZcJdWJDSOhyqrmwnapVDz8fQI0rY4exWZ1mO +WVjs6qMLvIgfnps2t4eXH7lOkT9UZphbxrkqoibnfChtNQT+Uxtc/l2ati1mNlCzZ7SPulzbrr1 bMTKvNqbtTm3dHp5ZWxs0wDvdUIRZxN1Py58xfVsRz2ih7USSnstpTCTOrQMKpQplcNHilVhj0Jq lX4WBj1HJ/FH+zpVZMT263Q1wuWdYR6rSDSztaGFCWr0fkT7hvvEmldT9uLw0IYay9MfvCxCwQxO tK08xkXtVRvV02shVAy6CO+Xuneo3sPRO0lc+dDiKhS1pxwOcAm0/mrqfAACDuQOLFlYC+o4m/hk y2oICsUmsVjC/HChr8VV2vA4RkGyKasEZ0QBaZSeZyJG3hDyK8dHJjcDAnCBD9nM4wpWtnBYANtU rtMaj6XD55sHBUsriHDIt9QbtsdjiU1Oc5Jmt9JHTZhZPXdQVZELs6lcXeTOuPYRw1rEIIpUKoZQ m3ljPbbZoNkurB21dowEOtyXJMkLUktTLU/oink3ApY0VA5Z043BaFHbYGpR2wFUmrDD/DgJmsme fR6a30yB8ftwANrD7ca/Tmwh2SAcU0V9zjxTI6oev6IjUO+GdPn3xDO8oOCP+rPBhdxtZY9DO5m+ 1xmEHYDS1MbbR/SQlNspJtKVVd8Wr1NSvDKhgxN3qKQG2No79nb5Ym13So9e1IPrav2c/hTEkIWu eBOBpCdpRRbNqN9xqJLj8oToSU+jz1BeRQMCgQbVK3e3eoiQVw3XfjBPFGgcIkvfomZrlYFgjWB/ yePuZPMp0V+aUPD9VBv7QTMnxDOe9G4VQsliBdxSMyBTHngHv0Q/SC0BVxkwnG19KTF1/6eTKXwj 2/guJVwkqVRT5Ukw4e95TyCmlMVfar3t6vooVCXaEtXQgvUpMqwbiIvaRvwUnCJoj2GhKNDg73Lt vlyNdir/MUskaCOmDlgSGWDKZTnvpOMR0e79aBDJR1XwI/eutrfJnkBRO9mTEJBDOndzc7qWkxD2 YLPVaW0m9a4myWYnhpfJ++ZkhjuXkKik3WZuQLLoELnAtWNdG2yk/sCXyP1nbY6+zXIP1POU7mxE CU7Uq7ykAxltHZi4sB+erMlIpc6WKJ6/tL4oP7ciXlCvaZ1zHi2J8OeNqFGXZkBsqtC1P+zphYaT Yd7yCCIQHAWTIzyDLPz+K1OLT+NbfBlslth/0GwKy8v7yMmSK5pIP2WnyAXDSGA1HDGu0GuHR+5N PDLANhS7EMJaUx99GVPj5NRY2Y18QdwzWOx7R2EJYQUI1qGyJRdhBs3KKeEHWIj4TTc4oZLnjlEY /sudrr963sqVD9ltLuc65gXMJG/731jMJ5ufjoxgxeE8XBdiFtWR1qdB7JggXqAsRjReZFlqy16X wlzEql+KFnmr5Q6R5s+O5U5sUHmPfY01C5JR+1VGFl85q5fOXOWpSS1DuAcJDzquq4aMpGo+LqOA MGnTBk+F0KDCjme/Jby8TmapKu/6r10EhgL9MFPKZn0ysVdf0ZpjhnYxIfwLad2xtmXWbgDy5pUb FcZ6AjUsRup8AHmp+1YUS42IkNbl7VW8QtaHoiYHgc10i3Rjlymq2eoh/FxzgHHlP1t+gXd1NSdH T8kvQ3dKSX0sMwhGmlPAGiM2z5FMDFc0KsoYdPbQXpT/7G9s4LwJLM8d3qeFyTt+blP2W3oxInTG ggtEXw65jIv1aGMgRiGuRrsZTMcOrnMOzQCjLuu6Tw6YH5Jz3wLOBVzDm9IqtryLoPzpLD5mkCWo /YrQovF4NGdpyeyfi7r2gdHaUFwwWecA/7rRu1Tmo1ADhmRtk0NDhmrvgdCoEdBFp+ofF5oInfIk eO9dSbxI+VujYUVod/HZ1G5Q6jjvQJNXnopyNa46+rO2C09y0tqgZz5vSgKpxqRu+9PXyNaCHqiM yGiViXA5Db+Nb27lbg6sVWjWa6Zgdalx6qoIrA8rYGan3okdycWTGT1mv+mo2l4r0BasJXueyh3r 1m9ZLqc2ArJJfeXqba6lzBghKgr0oNA90VAISq2mWwYa6vSYAcBkE1R7ePAgjzy2Z4R+MAErURW5 tzz9oNh4uoPeTayHLQmRvOgH7uDPrOUev07MSTn8tHLt5mA7jINSbXgQE/Jge0dEcQ80oY5r0fLU mAZyiep1UQnDYajlRXvZrcfDagnwv/DnqNYXDudkVyu+fBWn9Y4vlJ9PZpWGpzQYBKQ6Id8eUlvK rp0Au6IXB2QRApMTVs2LhXdRxALMaS8W6fK9InBncAPUHIg3UH+ulDnA9XYdA7Tim5qScjxxng3V ZLsArzlHyzhzVaPSFz4XymWpyPorn3T7ZbzgjFh40SmE1iVJqueV5bF++XsIJbRiftgL5rNxbR7I zcYzZkyXALFmJFAwuhtPbbyfgzVWqPYZy1tV8MbwF1nhuj8gZvOoymdra1w7uUeY8xCHw8xXUHlz hr6VUIp6+w3nzNil9q9eiVxrh2gRldeEklgKyG9UJEuhcpijVGjOV9Maa+l7AW4qgMKd497qUeiS ZIQHSnsCi4dEyRqE4GZ6iqjuJn+bxTOmKeXAuxU78BX9ykIpfiRrlUfuupWEbR/mtc3UwVvQ1OKJ nFUv4IinZnOkJiUkYLLrCT8RlWtcdhAhaYhMZzgAW8Up25xJXgiN6A6o/yCxWiyh/c7n6Kh0lA4X KXI99gKeZVkUitRGiSjSHJkMUsjweQrsGBEdWFmBrrGRu4i5wD/KrFNQa0HrcN5M62GPVsrmXbmn N+A23NVhJJQMpwDfQckX8DOViFre91WXNEkn8ACV93mvQZSeE8+GA82ZV3Lylyj5Qox2eoeRxtnO jk1fndlaZMNplDXnmfQF935ULlg+1at1cKU0rs+ps5Y2Z0EU+3/br1w8klyY2vndi5l9F+if5PM8 FqIiNjqUTMip30rwdoMMsAuetS7jWkM/gUCVQzPIlQAGpBC20GfcBndFIUAl9dhXH8t5sTqIb2WS 6ybHW2+HLSZsUEVZvmaNwRCLhUWZpylmeX04EGOlVXIBhPLUbZmhzPUPFTl4sDJ1fF86FtEtnqMU U+wsK1kd1RrERDEBI2ceTRWL0HT5O5AqAlVR4nxkEd8oSLCZiuppUquQKCKMdZfu9XoCagqB0GQr ywEK7U3l0gmBlfHAX9bD2GREh+Xg9qkp+tBL4qVjc9ZuEWhQ+p2kSXCsnqJJgQUJQ2ejUtsH0YUE XZuxRPPyHPYlOfpfMQEwXNFhyLfQR6o46SR41FyBJtZiNLUQ1DUqnPxUp3JXHnL1pXS75bP9MMt0 D9YtSQN5yyOMjYxdRoQlBJwbNWt32dR2gplZL7jBIerPM4VK5I3QbRpPDqcY1zNXyTrT9vRo4LXn MzbXQtDYSFy6AoFbZ+SFuKF8ikllaCKiepzlmS922iK5xmpU8Vx7onEhgvV2qDMIXrN8mG4xqB2K fsX5jXTX4H+pZjxwzY62ELrlCH+1yrx60iimX2V1j3VlIBUm2G7hdGra+Tv49ZycHWJwD2XrbTwc 9FM62s8A3ztIk8J0f518EW0W52Jihd9D+bJpUULu5pufSsnUsBaeaTKVuraGEGBuikKRtNhC7pA1 LswiEsxk3+DeNOWnagOJE5fCPO+iORgmXr1eG18Q1/PxPzTYMXSoaSQgnIaseV7IQmKcBY/bjxKQ esrZJ0MxiBMSfbXV/iIzWWkJ8ZfKoyDc8zBLdJmI7hOf8az7Fs7ejiBJ1N8UI30cZ99QzZSt7117 h2xrvB5HHnQXiVL89ydZ3487Esi1FycMWZzYHLtEV+FSsSn2lErCgcUX2lBGV/ftoPgOTe0/6Zpe uZQYVf7/5Uo7TsUL+NZpJo3KTEnfsl+wn/K7NPvncyzXjjIVEFVQFFbrXba6U93t8uTG+TvkIRlg zNUQGVqRUmIqmSsIw45wTY/g92iEf31sdZL66wtSBG1dmn4adRWKa6b8ECSPiXSN0RCR7nmkDFxa G3LOmzG+I/BeXbccC6xcNIatrs289Tn1MMVPGTb+QaDevZXybIgxaxdiGv7ZmeMKdSNvJzvqCltg w1D4i8phsZj6RD9w23S/wxsYFfE2EzUeDop6O+SJOoWYWnRP4cc83e7UVOt0mVzvsJGQqu21gIKd CpfNpUCwCXS4YjTX5R+ScWoDgoXbICY/CG9Nd/jBsE+fPVsNl3wHep9U1b/tzh035SPiRyYNaEzc t/Gjcpuu68ZnIcRwqaxqa7ztjt5YBr944MDoaZCNpEVxz74lRMUR4kB98alLGtOrdBx05xAnxXoG U8n6/gpYg4JD+xV63doWWauzaj4JPdxTAVPEbFi2vqMVtSAObWrQgQ4qt7KxHzEX87EoZ4g7dZ6S 3mfFuujo/BoavsY3KatNzkbRi5H8VQeIv/gZdc8TExljHsyeuug2hPfo9Bhaouk1206lKZkhYAgW yL+eVrPYAYonsBrFChr/9xNm7ohkNZskOo9cW1oZ7n16fAZGAFTtFkzlgDRpqsGLg9IJNnH0glyG qx2Ch3shE5Vf75b7llRgewZvvAzP9aX68clJukbjiNnTUk0KWyDfhcpDgN1Z5ZVFWon05jGLv9Ez 7OrKnGhu3vko8Ojat0yfocFCwa+T7DvndEtBYPwceNnHQ8TuMt5W3KPmIZtZinwasI5I8A8Tg9+M 4OJpdVANLWVaoro2PEh0FJB/Ty1QN+r32X/Anyur4eHc5bF6E1382JwFQkQFkMEt1ZG4gkMqgG/a NxGyaVoW/SDoQLvMOSIhlRYx06E0OJmIfszPxfvHXV98MLRMHr1dUWm8zqTCWeDFttdohUgzsb1c SdEwweJUd84JqJz2OKVU5aIjJ6Lja9WIKMB7ROxCnSTfJYy2rhtD2HAllkAKFmX6jBYVcoqf+xFl NOZc+fipr/KND0j0Cf3OA7f9GQplSvsV6x3lJbpXh6ZSyapkldu3MPrQq14A2tgfh7jQYvTuTIWW CCGQJ/PCZ3HOyltL5oWOG6C+LtS+oNgczJ1UH5s4cWlbHmJipVjSp9U39CX8NHRbCG6A8scLrol3 5IB6recVAN8nl6y5dcoG9jWA/7MX+Sk9EF1dd6SAw6JEuC9UcX4bg3jsbjNKdkKE9JoamkwnXSbc HaZzM1lxKY/wd95OUk9tjz72y7lDwc3NSEVY/KmOqY+tYbDzCOLzmjVEQUjuzeQftRmuN6mc/yEz kC5Rzv+HC/UxeUFeMrp61LBBvBxo1cVZFyVrzHHPSiIG52ca+HeMVD3407Rwt1+aG6FTc10koOB/ zBxq2na/+WPvP0YtHqQVu2ZV34ptW4ZyZP0sIoJvXY0U2IugLtHbXUMJlgz44YAeQWHXTk+pYWwM L+DwkE7nSPKIKyh15wDSRW34KZ2IuKGb6hvXTsEVvMvJhQyty6qsq0tpKTjkeyLMkEpW0BYbhZJ4 tpleGCaOaPNaHLEdpX+bBaExz0oOy5Q3YkYf9+1YLvNc2kfF8wHNqyk96n2UhHLHNgGJo/FFxOJ6 3F7DdVH3duFRD6aAKsPMDHcrbgXLKgTbiZVWOr81pZXalAzJmrhxORBVWkL+01XvlwHw4RPPHTp0 jd2GprYaIOSX6joesZjTBEmmp9pvNQdbN7PJaTUW8MdMW9NJtYrcJ4jIBIGsziANzSOdl9//bLcs OK1oU7dXDZIT0PPrga4ctTUWylc5oq09JH0HIUJYV0fc4OV2cpJ5iJ/WSG2XD8m9qLll94shYpj9 YYYcNJ+oUSIRJP7iFNKNaLlwaaLLLYZuMm8wP+yQG8ngAzod1LV7Ffgu9vMFuLgrm6tcwwsvgRto mk9+1xDLSrYui27v6wiljQBe6D9xRBO5Itqfd0YXphNact/XtufFTWqPiiDSeKdi8zCBy1Ch94LJ FbJFw9XvMfYEcd9bd53QrA0UJEG9fVCnImvm1pt/Tqocn1z1KK9qnt9Wzx6TUyk6hhMA+vVIOgbz KZdGzIca5fB+zadhGEkcq08MWMSWJI4yK/k4vhR2TIjiniGhvCrb4GazvzFEATEQt0u4QntChYaM OEqKHBydjeE0pBf7KZRFbt2yffce2zWIseuuSKh4C33T9ykS/tt4xKpnLR9aksmckVBSR6yLjjY0 35ysF0V+bHT5f1oW6HEvB1EsEKJPCXmFez1o0lEElJk4Ox9mfW3op51FlfEyQ6AdpiEaWByj/7Q1 CH5B2Rlop5nHKDvS/OQZw5KTEPEl46c+/tJqI4jK2EzLOPHyJDXnAy1/rgaGkEB7fQfds2W1LjW8 arDq+jC+0UknV6hac7ZAWe7UCUzz2F7BTLa7pdeR21d0Q0WbVs0lOwelgGx6ah2yjUjprGWdodfe mH2jrz767L7x/3iWbmNpRhoMwSSGmJWj1DXMQ8fs/bDt5Tkf5DMYFX99dvgj8LoJ3nxQoNB0T650 /DHUB9oNHRBn2NGVZtCajWYQRHT9g9cCKavodqlJrYHaYGEDsn/Otk5BSKsI59kmPK/wvv+SClcQ teZYyVCUdyMC+39qLknTOmYRIGcIVNRe6FgMXss3TrItviefihwlESM3OTiYkTV7ibGJQ7/x9Vbp i57UdIHDAwHMMiIAqvMbnZCtVlArzmzpqApK8hTj085jQqxx5ifqigJNrb4zOINV8I+LED/6PRxU hV8wQZdvQ0gyMBh0QA60fp8o8Ps7QT11iphuC4Q/R21aCJH9teQ3UxcyRrBoCLgQxssC0yRriVjQ IB57Un6O6WJRv4F0jLtEBc8+3VhigBio0Nm5UN/P1Tm2mM0gM0doB6J1DPTHKZxVz3dxq8/lXb4K 4K94vTYh6y1bdBQmB0ZgbN5NSJCwmPgHu4i4fxzEJiAX/juV7Oq7G5qffhQXUEX84vLYnSbWmC6e MT5RGY8k53EWCjXNJtJgh+Y87gjt8ywyyzCzn8XWAsMJwdrirWclNPoVVkMoCtsWmfGRaYXhJUzf 8G2/Yig8yxnrvWei0CQawV+HKOmMUzBdGDaTpR/uqx3r767BsO/ElARyGSWDGyvAsIDTLA8cLSsK utvIYFL47bIzT9SdHK9oloUufT7lIPl5LmxuEvk8XdnH7oB3jKSbaI+VT6FKsz8nSoaKarF1py3w DIbw45SShipm+oSjuaneW3vgr8fm1bMt/QVqrCp+dnMbOpKMkANAQ/ELpOfONtjYeikxXcqxg6b6 GPpgofRHHIdwtyGX/SE9v0/5NK+kvmF08pIasSHIwufeSXGrQ0U2NrAIvdPQXYaHjPImKTY4S7X8 4FTla1fKcWmVZ2XC+feNByEteO9gt5AbShS8gPoCmVGDtHjFB9vLoy2NsfsHJqo6OWphb1bKBc/h Lm+H1Di4+c4OSBVDLgGGI5TTpiWdqsUEwxNmwtKJhtrql0VJl580Lyzu+XMkYP+PHOmFtTg0E5/z fXmubvFP5oJER7947JMbquqtCVh6Rclpae/jB2Hjm+JCqMSr8woA2wwz0siLyFht4QQQIMyeHxT2 je1EpNR4ec/Q53IxA3ZsOBBKGL38yRyQtaKr7mEtVGpMEAkwVzeAZhq2aJEHAFGtIvPp6kMJKDEG 6H463dI0/ETbzXCynVj6oLR7xazWSFjNCzV/dlQhip2srQww1NBMpuQyszjTcgdz3mXnm/a5gbq8 QVYVZFqGFmCJKB5fmBqXjsnngZ09M1MLnXRBUBMESOJ2LJ0MnRNY02UCPnWb454cH5ALTCAP0kmt BZ3/A38QlB/c7pmUbGRKO8M0Bado97W/2kJHA6JTw0isYxiuO2tN3DhJVh/29BhmTA/sF1k8Xyyh 2wqiIZy//7UbR1o1SZyIY+QmSYsCWsKpicbED2gOBFTp502rXQPMzdhnw6niJ5W7NazgkRG9cd/c Iw1ligm+x8p06jeCHUoW8h38f8IzhrxgrrrSqoBJdALPoqWWWMOsHMP9drHwDmO9Bb13Pdul+VuW BbyRmc03jJgccbgM/qyHa0w1phGz850+O9NTqAgO3FL7aEJ6budOY19C663wzKhD83e4G59iwe4u f0gWI3a5pNXus3cWbYwASgZIMhlAdr6bP8ZTCbqWVcFvBPrgIH0I0tKY+V16cQ5EidPpuE2Y7/ub cjCmjwQ1HF7WoUekdedpOYVA52DTVzN1FFw+LwXTHlHnMydipBkeIJz02H3MHJS4CeKU2xw+GEGv +LNnEx+gg0JtWoLZkw00V5XskKHBYu85oierNYreGe0dqMsIZ6fPuVTKfJ6RcK6FwC0iOaJYFFK5 IuqknLQoCGSYdYt4Y4eTTN5wqWy8Sc4pOufyLDK/IYoP4Na04AouocRdTPeQiYAAWRcUvxOSgbnm SjortD7h6v+STZO+NyDygsTbTwXEjY3Uf+0u6ifeIEx8TiWyndn3iqNP5han9dF7hR7LktJE3yb4 lGFCggEEkS4vLgDfVjGdjLSKPlTSnWgGIGJXfjeFNn2y3m3hgxQVf343OK7DQb+7sdCkSjRiNGdB k7kLJLkwKKG6TkLpMkIYY4wjGx8UorbAT6uvlhs5zLGUjJHvXbpvs/N34Uhke6+1AsWpsRSk23ut qMPI+vuSBe0Ik1eKHCZd+8H0fXOlQiWPPQPGbLmSJ8yt6FFnGSPgo+CB8jUBmeLOXNqADF6BrOI3 2HJUL4+ZI0deoGwopifVfrsNPhBqNBncalYr8yKn4Dm614FlFA7t/ggVeyDmHk4hDEQb0fRigCas UBkE9mhzBRB0XDKBZZoSktqrJUHPZbB2QPGrJzhijipcQg0DrQ2H7sNAiVGCUyT9cE+tPFZvMq6q GlmijWLqPUZ9ThJ1G5kGWWobTydRAkUcctAf/TBuUzV7tK+ZDXKhyft6Rgd1SScIleB/2KADxADh FRxER/nXpNiVsKhmdIVVF5HyYRCZhD8P2GeidiDXRJzTna9LLgEcYKBk6pog0Zw+9jwgGolxRvGL ze0HOKaVPk+wuQkdiFIcM4QZlIi8N8OqigDP8+hfUqqmVDAcDMBz+X7DNF2RSD+0P0jKgLE3Eby0 AwNHhDO2H7lIxGR/C4roDdnRry09qHrPE3s4FPEXaZ1cTpDxrIFlRMKVXGDUGA6BYviN1AWoV1rp gpTgyGS8N3ramR+XKgUH121ZrbdhSXbMcuZ7WQqY6dVB+yg6yM5VtyzmNh9KF2pBy+oE+ImhDauh 2KyCi6cEcKCgCMDs7ONb1dnP5ubzrjw5bmQ+CkMx5aMNN9WokpHtSZMgLeplMQ+YRPrZF4/fxQnK Si0VYPLhHOISDSl6Gs5OWX0FYHL10ocW/agjNXWh+aWYKWxsHwxSJwucAs4rv1vUuNCZutwpP+TS rzfjE3Xj3aiij8A3Irqm/nx7qGX6FUzBcwv+TMej4HIW9L07OGgoYhFtkKma60VYrX7gE2P872VF NYhi6YtmI7NXJO4Dc10F9p5KG10xIOaZ+YzuyGEq6g36mFHlf7vDoWl1uwi5Ep3mYeu4vBYi7N1B eb/ZFM3SGhsnie9uq4L4tFu5E2bV3gSdFvFszKZWwB+2dX7XG2wbnDld13jFUhxSd/Y/akgxX0GZ YjJesZoHedAZwbYGWxHTgrkEXXzBcWBgaYOx+1dJipqwy1onnPAu5N/wMcwFr1FuACDFhPFjBYVO LzUW1NrG3ZHtUyT+WqTu3kJWgmcp2FYvTpeoL14cwTOwdr2VZ9C3WYje479jp4CNFUO/IYrRPklN Y5JUJjY/T3g1M0frkYZAogMqzdl/p+9Af6pG/9fc76Kc2oDGFzdvOvQhK6/usXVo40wAjrY9q/Ab LjiSflH/TlqUq8w3QsRwJ0XOlvmgIveh9d7h8/jzsPtZ+TOmppCSdWEpgG2TVfU+jinAeTV/5qk5 u0OhgnwVVCbdFRr4reNjA+HxOEXCsoBTb6XU7I7AG/gjnYGOUmcjdubQvKz2AfYSQU8ynTfQL2Nn j01CFM228Yxhf6EKALMY91AMnad4o49ibaW5NY35Nf+hyZRhB4+TdBpucM5E1qzFm1Mx0YXI3wSk 5GomcgjiRAyC4you7H4kTZTRSHqQX5Emm0JKURQs5wjqrnmohz0MOJGj3eLvchEEVWO9TZdloN9S kRA743v53ljE+ArzhOslDCUvcVp1kS3ZVPVum+WdP3nmBNVzZAiwITdS4ZJF2UaGoercepQ1Vkkb TbmKMq5ZGJru4eaFHAyhg7qA2oh8ictz+xwWyLl2I3v7SxvK3DpSl0XYBxnG4qcq8CRR2mBnbaoE 72TvB/MGIBGnSMvYNWxtF4RyizV08zbjl8rQAT1bfciDmYNR/JoRyKKDFvkI1EwW0vANvsC29jQm FIjyPqxVpq8/hc/6K4uFNjxKVrlsT0QidH4qTaMuZeRhliWD6XatcjBXqTqIgKJrBp9on1JQYabJ qdI+nXFYPFGDv/F/G0hJCg4urm9Wm7nWYAOXxbdiXog4PrLiAwk/ZnINU8rR8LDeancmpIEzfv1A plrogOarq9ycPObCqasQvLY2M0DTCTUEpsb4GWRNa3kGA1pzkVt5FLHKSNsFrG2xwn10zyQm58Dh 9ogF+YVagFmYW497qz2VLDn7Lx2geZU6S4WYKie7NK+7ePxBtdy8vgZg4aopnbvAyr7aPUtylkfe rRFOWKI9gA6ItUtxu4gzyag2AXy37nQ1ZI7RoyngfJKGtYGENJ8vMn46PmKDmxAAC8m3Q1YDZWwz 2VwlvkTpaGJZDPXm/eBnN5T8oVrXxdkTU55CLnfSj8g4aL58pdULjwdPCDRL4acLj1qi7n5a9U2z L6rQ3Qabs67SDw2MKrOkPit5cSXoQLja+c2rUFDtH0TcpOqpNozZiJ2wwbVvOp4Irb3ToLSYIrEc iU1mc9QmPPpojtBVjOCnlK+kRa1gq6gMC8aY0BEoaTO8RryHh2sCA0CbvygtntUb8/ppSrYfcibq t88JzsD9rnE3rCb2ssi/jgKZCX+xswExGKUN/FW/Ba0jNUqdtDs24u6zGdck7/nJycQpyRLt0ixL 2udCmXZOgBy33DFcbq5eU3W8FF9Q5hE7czYzLQUKBbBIV1iI3v3thBodMLZODsVpoZ2MdtqypEwa K2SiM4FeRn6ng9pmHO8zf8WOuQbD/0juzH6XalGZK4VLhHoes24on5iXKo8XfPGlr2at8OQDqYRP hg/UmlaP0ylvm46d21HT77E2BnpqgNpq998l4OCFOhkIY+VXqXSC2tgV+tg7m8gldjFVsawWSXLe FNDeeTB6AP5Za2X19a7/FbnLD1dgUAvC6VQw2pxuvSWgOcW83iORoWcp63U363/lP7W0cyHZ/X0A Jy08guqwrbWnonOra13Rr2MLr/Fc2g+A3KEzMUMtVjLs0YxL86LECMzvXDeADffB2nd/vTJLYr+i tH7OjCLUzwXLD32SVkvZOlws1D5UMlil5wdzoGyQwdZidzV117g1Bl0E4DBvni0W4oFbFNaohr5U vveDIA/UzemndTZ0yMFoaL63I4qGX5zkrmbKJuw/tdfauCEdi5+YX5vVh1uceD1dDd7zhohwQhoB q3eW/6O5VAclSb1UNmQoqo3438fBeFkZs64H4ftaxCM3J5B8D0N2SfnIxywXAuChG1R9kQZfDL9y xOWnwtu8ALgSotZiy3W5B9DEwGDGSwZ3ZoseIcmoC1q0DMCrlPE7y7HxVYyILFvQdLD4B/3C0/B3 WQDLBij5Gb1fbDN5tR7SSYnH/khxIxI2VhLn9GDAQ4HnhYmSxh9G10Eo+iQwR1N5PY7DBdQ/HL+n vF5K2EKJuqDYwqXRZ5w1Wm2SGOgn12ZNdo0pa3BfaYUYAb4i+nRKcdFdiu4FK1qtPyhbHOXp7WqL qow+o04G63NS0baWJ9FZKx8kzs/zec2IEjBfCXuFp1/o/ZdVMaEfBdKcmFbxzLkG5N/EZhmcyTk5 A3BOs5CX8kj6Cyk/yTPAzHCCQVhZ65A64PNXNg9rt7kSWupPezntBwgitHD69vN1UBNmB4yVXUF+ cE9Fd86UUw0bp2pXncvuk8uQLXoLIHbNiQxvIWt8lS5dw6WxVg4AwK1AYEvjqyKFecnAQN3sou3P zMaIgdGK0TUPbB6WNJ+xw29vqR3gCh8zqyEAkSGkiBUyFZJHwdqVGD/AzaA2oggv6AYJMizerlkV EYH13Ohwycy2ygCq05l0dQ47JX2WadgOYxXscN5T3KpRGL1aMgpmlJ2bBJ5cVuv4A/LHyrWVny97 vTH8amQStjpzeAvrN1QhWR4hnWm+WYpkEB1z6erdUi7gb4qqaQ0Br+haOU6NvZunHX5NQjIHdp9+ FsFpWHqdiLdo8Z5pP4RjO/0EPCSiuCMN4cjnJwDplIGjjGUq2x/wc4RFGDYsTA5/j1jS4LQTwN7n cPmF4byUxpWRJWN3Re7sNxHjGhRtY3jh3Uvm3qmWY/FEeBxGgmSLY3M0rSCJscy2GmuBq/8nUQmv LOXL4n7vBV4fhn+Ft5Ba4b+WiAhamDYUGiFMdWUu92BvoY+hPe8LGco7c1az6CjqiR/+JU10ql+K YWOf/l7BrZqQjHImfmbEdWfBrjbGg1FONj3gkwZgr+87TQKQcJ5PsUIprnN0XAVfh4WtMXuedm3J BaoJiHnQzkTWzGickpxnK+r3Wux8sD7z0kmIIK+zbrHb9ZzxSa65V3mOigr6NEWkk8TYUVtzqOxQ ex0HajkzXfuBqLRo8x3OBESauguJqpyJV60+GlRsLztiQwgrS2KaLScPlfyo1KD2eTiJQEFoEDcn bhcxIpSFSlcwlZsHjGUIoNT/dLY2k8ABRbW19uG42PSyfy3Zq2hgkqnmFbSiw/tR5xquTRViCIlW rbZ3aRAqRcR1hvTWFoviWa6+h6mELRVq5GuN/I/BveZMW9az3k1r3oHr2GKP9QRWzlg1j6YsXHux szsj8GdyELmrFGYx6lX5qw8xr7C1GL4UWhFsU2sn+W1WpVG0/kVOsUHuh7v/8XNWsjRhJCtYH1iB YeNKZpL+De3YnOKWqHc1W8ifbtGesbjl5roBNLyQH0lAP29Og3lhFaSxBqxGG0PDJmqyl8bH9XLO OXlLRQUBQ3E1ia8wOEcsNxZ6fGGv/FHgFxWnBNqZWe+ndF9hOTccT+HgkyUHISqxsd5Lbh0zLdcH HLqJWjDzseKB8PREjh33lJkNm4Z2fgBbG1kP70PBgT9Rls4lfbMXv5hgpI6AVlQwB5taFWOcU5Sf 30J/15wbuKXZ32sseCmQWV3oaY7xnYD099QeN9ZtS+SncraIuBJ8/hCQfROzBXWppnlgOApYkOX8 YhU8EgOLYBzwe1pQAy2A40kqpyBMS1GGkRmJW00MShJ012P41/gMyza7vtXqjYCuFrkIYUyMub6R 0Hbq8t7pcYoWiem41IsKjoQjyNRAJFsHUyHtfijK2ouFimCLbXCsLhskxXLPbdMygm5KiLBhZzlr zag/y+sMxggX4NcQbonROb1n6bZymJ6QXd7VAtKi4Tl+9u7mfUc72aYzO5jW1l6A2zPnIZsXRIA/ uRbrDQz0x+EMpQBVDRuviSrUu569Sz98FgVAnjTNtzc0SbeR4taAp0V09xT9UgAb3S1xV80ragcg Ep7cDNG3e/hNrbJQa7iCiCfpDzBggQivIF7F7hYDMDiE9kIzBST6723ktMYHBsy+pfAahsSR3v04 FJgVy9DvPOJcV1sUXYIlOKxXs3c1hz0FROsAcR3YRj6Z/0DswvrWiiNVZUQDz4Bn7o6gybrYPSUU VH673DvAQ6/1C3+dsl712j534FTL3JvjbENNhx+utrYhYDFgW+NKPmpLyPwSm5BRC4f2Yw+tf+oI 3kOrQxcbQmf++Gru+xviaUBpxlxUo4Qi+O8nBOiLK+9K+KQJxTgHWIuKwaa/BGWRv1emF0cvA+71 j/F6I5nKDCU3+Q2EP3ohLxX86tV8bELjLWJbqk5YXA8e0FvMC4OZQRazdMSbrmdoMx7oS3VvMVje V+IBpDJzbKGMq/IJqpIprqhkXFu5H8IwPdotXYKDBLnMdMzCcr1yyFvXxUw/AFD+lIVZiYlC9ECH I7+lgezNBE1Jv3m03fDJzAJLxEzcF+jLP+9WYmX2ZRTrhq9APSG7IDFysaS1tgN6DK6t5KSwpCm3 bGQXTSWX9/2k+DlbElFi2wVH4LhX9v+lcOpwoDmIa99zgYX/ok2ROeOWrePwcq8L+sspD5wosDUC WAu+l+r2nIYf9rDG7r2NqJPTV+cePayyJvA7zSoCgnCMybAaGXh6OAsG9NQMPbgLIHKILaEbdIXW 7D3jQD2poTruJ2vQQddIZ9NbwYT6GZNzjrSyo3SVCn+VdVutJLjD3ocyiww9ZVTHSbP99EoOx6Tv hJZDHmQbBDTyofotoCS8mcJODG7KlKKD1psCG7ydmievSezdlI6f26tv5SfcC20b4qXVDgzOB76J j9zg9DKTd+Kzok/0DrONlSaYf6Xl3lutRmmuWqgp3C25tYFML8eZX+nsxDdhurIGRfDlP4T9bmDJ /36uKS0nC+IYDEn3xZy+j4wTrBX52hbvUK9Il/Q9OIly4KJE1c83TqtWQuKEYtcVfrabB3PMa3Dj UqKBRqYij04TnZJHh2Pu3KFUf7ajAA/1o/wPGB+wsrdRuqysb/K2KyUnkGa58rAHeZmiTj6POJVG MADhlf8Djzeb/jmzbtYIkAv8+arMr1DIuRJ4/Kxtzwzd27rl5b5tMDLg80RlEr3vqMX9Q4xZm2m4 ZTV0ej2BSHrR2Ws4juZjZ+KOgmp2AKpO5nDAsKJLHyOfTGeM2Fxdvl5K7kzSgeiPPUg4GOjcoUZl UcxOJlVpT+OSyopz3byz6h3uohCGRBM3nitQKdnYPpQH/k52pC28yQuiJAFLXVJVbaeRSMFE1x4S lRXiTMIl6L+o2JFjv7Ui9i/zs8+CJ0sb8IFnh5FshlrL7RZ0zkWtDaO+lE2jEeCkTsllz3mfq3tp HOT0qfXiYnzEZ53PuW7FEKpjHK9RZusQ5LSgaezFSjekH5LJltu405RmZuNif2HWpjIwXSAQ05Ws sDhGVKuRi/F4TTPmNhPUXskhPX3ZojKegqgd2kRvF4Rx5V7Y7LaDOyeyy62PSlm7priDJ+PXzgi5 CbX4WkYila+2NhOHKmLO7s4ZFFWZMOrswWY2NpfcqhfW4pQ3vIQsLgpov1oafDaxBxg69n5yNPTL WLV/eeyQAgHP468PzT3Nr/SmygVZohHYDZhuK+mbqEOmXzwpjFLVIgb8LYWOqjFzEvSJT2EVvQom ktUBvUc+4b5vk0VB8r9Hc2AkxqDmmrIyxQylMwdd/RlaQDgIPbgW5TAVRF0XD1B8x+24mn1h13mB UMJp+q3+6it1s4mKTiocHhFtIch8vP7OGlmWeNoV7oPTy3Fbo4KT4HwLdxtcemK1WAPNXRwBfc8l 5l4173sdiKUiKdUfGvQfT9rkzeS2adG4d3LiLnR1d/tEguJ4t6/QMOgNPSbrpT0ZAHIOFJSnQu/4 lbfwkI0LaodoEoSAivf9kPiTXj1l3ylsekwCahjdqmxCLrCxrI/mw7aUSatpcdKAGq0xYNuJyPBq 6aF73wQsVBMbGp46zHYA+oZ6q27iTYYsK8UPH6iDtXyUndGWpIs+P+CRtl/yOU1rT2LJ+fIbAc6u 99ik4rBtevOTvQTxsfYYEMrN2mi8LbrPGOLpmvJppYe2bFPhi56Ia392XUGy/wCJmVZn5LIo8m0u gM3S2btKUx6VpDTusOfuAQ+BAuDvHs2CJxGiXrMtGR3/gqqEpDo7fgv5yA74erey2MRR7mNC7Rek nDKT7afnuuJKZgSmYtDUBLV/zV6OudT0kF/RIVmQOgQPUV6t2YWytt4s2nzTRZfPiBBexHM+hFzZ i3ab4DIwalnLly9XoPjNNnIz8KYYPWmhGjuZjrNrnAR+RMCAAeAdd9vptCy5OT2AOj1sNhPRlXej m+dAc/MhEKSJHhSzFS7+qbt0byBW394io0TptpuPVs/lXypC5UueV8G9bgOvvSIY3XvJEdk2sZkH uF3/KnkdIOkLNBRuebSBVd4CQcpsZMLOf+GEUu5fIMuE2CLailt9siqKwrs/owFqWik3P2Aluumb 9AZMsSlo+oBlLh20T7jrVlaE4uo8/79uaBkgSz8CV/VXe0AsUsT7ZbFFuL2P73pWgYGd6exArsOS u88W54MZil6vxVMy9LZdfaIdqdRE3DBOe9mNbAfFTx8PTrhD38nZQvrVfxClIyXI1r9Uh7RyoEPt 7WPuhYBBWLnchmuDjK5b0EVICbR/ruiuT/u9uErn2o+uc/K1SE4Mh+nigYnPd8tRj9Pg768erlIJ RNW/rw9n5mFntrH2AUCMOkZorKAkSZC48W+9DiJh8iFTU2SAXbPVSw9ql38UfM+vVPwxXNHnIcfk gU3nRjunAFO8qzN9CILIzdo/v8VYuPK77YnG3ygpAVkF5ZIO6WN8yMmv18BlEcqKdSQUyR4qbdLY Y2LD8RjYIghgJ2IzNac1v1cu79BNrlbSO5V4OCwMWXt8gdKZbSKnUFgrXNQ1LkrRciyijQMup/Z8 M0nIJbvjTNbT6q7qnVuxqjmkEms41q6rvSQ0Y7lHrQI1ss7HNQ/IthjP6zQ/qRmLisd2Ab5KEc1V SjhxEgRfZ8vONJ6x/i3/ObxPLehfFH4kelednbVcn9I2YJVAIVMJXTvF5vQfFyahqg9rxbssBt5O dBXCpRZYaqhe4zRWzWLYszCkwbnG5pPjRt/w68v13rtwmZRzvlcsE3yD8CiBM7bKadOtdLO2OsID KyuvbpILUpbHqNl3+dKoSNfQQpYzjtK3/JXj84nZq7OQ1iDgd0dK7nd80hE4uK9aMG8uYviJmh36 L9Sxz6P4SeQyVnPXR2elcxuQ8WGRlTgY2O7oTEGeGLLAJFpY+uSxBXGgbDMJQ9uB62yGOoHnXn+z P5+APyq5pS8vclsnAXg4LgRmLOGxR/etoPrx2V8QRQeYLwkfBE/10WH03m+xIhZ6My9uXbDTi75A 3WuF99/M74OJ6wQR9nSG48bgkYSQ8Qejxm4WBaaqvjjEc36t7IUdShmcy5sp2dOqkM/FDmYByxej 9eN9wcx3TsDFcPfw4+zvwL4aNIxGqgnDpE9PNr3AQHv4gxYeSXAP8BmCbYQYwuIQ6GyeU3VN826f 4rqttOn4//y3vaBcjJIRU8MJ1wgfBXOEDKaMgCaemLFh0c/nZxIZLzTic7ryy7fX9+41tlgGwLCT jJMduqO/CZ087eTjYy42jnebhzPecXNc7rCzyzefVVmFhR/EJx5xnYniqc5DLeRdJdHDfpSZAdya 3vZBfuNj189z27AQ4VGx+SLGfUjg75MSmIvv3TXy+IOFK3AJbwysIfSeWEN7TpSC5W/xlneswkYW 8+MZ1aogcyPi03gUcVTVWf7TRN4/Yq9uVPWJnX7p+4VO1OLeIGrpg5eumdPA9wgNyLLTi5cPTevH /CKU0u1CaYGVQQYYNFKQTw4ISOnWyzW6SYaMqUWO41AJV4bg+0Phvkf6jRL6YnOKuRJMXimyrtTk Rxftkz/CCxSpfIQqkAX8MU26G+6NGZ3DLN0Dbwbuqd02mlPxLu9/9+XpvyuoGmuzp7qqU9spPEit XVxRx3e3+Lww+w/TV/Qvgm1xVlvdkkQwV1uWn6k27bXrkgshM//0jFeMKabzOq0Jp1lcJWrx1sy7 F7gACHievGQfPV7PRwkxnDijIcZaZkWZoX83uNXtaAXm8V5+A0Bze+J1FSNPck2scFN6oPl+nLj0 qTgjx7m99vtQSyntmqHz/TeIk0CtmTUJc0EjRToR0wuqmH+j3jOQy+lltrExQXwsDGNwupX5WSiB bMAHxDvPRPfhXl/6gHsA03F6BeOHedBZJvapQM9qJh52kAO9TsO9g2ssTsty2Y75AwlQ//4LIqC2 XUL9ihwnF1ZhVyhkVon/9GIV27tLc18Hus20TbD5P3XbE5SU/K1hrqUXeiR2DW8vuG4ka3USnkVT C4SH59mjeUbkoj82LskBKdughSoC6mJICZA0zf93/pT9Ksd6dMfJVM1XcKJVWj2d4Y6227gtJhW6 pJd4db8ImFqYAwIMYk56+nYVcpYmRLDl5Eq6MdCWj/J9cz5EeOniUfuGbXJ6GNKQWEO4IpeKXVLs JGowbmrpjH4lnHZSwaYyjfEwvpURmY2mKJH9eFlIGHGWZeIrPZFjDSTcmYWQu1XHj4DUP11jCrMs V1cPx78q93hGb2WI9xxvOi1gVNLbZs8WyzeMbV1zPXI+PR+Zda9vCzTnBfq+yVQloqRZJ3Ddigz0 3BqQDY2wEh0MvdQS5Qw86T9mzXujguVdGjxtxLVq7AYgO/0tGMp9RAuuQMWMm7d0PAaVpntVVSLg k1pIzPDrgwHTD97MBrH/REQXaPzjPTmYXS6wwSn5CE7p9s4aGsyJ6P8AStQIwZW8ccUooxWgSsvN 5YOijmKj6Ri3L/kAlgiEJGXm0VE37yV3JJIMRjVHDUdaXjikY5QPRpInEbwMxpE6DAH38Jtttp1M N8VBm66ywwEotI3wakV1J9/opw7btVOq5CEsT6B5EJVtXPC7cnah96xnR93eCF1FBlQXyxCwvO4g r2ZezGx+a7DrSjl75zb6g5wCdNotSHmZ1Je5JZCY6BVtX4XvXUXvtwrqf+NflpG9BKo7EockpnOd lDmm6vI4qcevLELFPi7WrV0uzzZO2hs2rxG+TAvCCtL4Vbmz/ifU1WqCjT07st7Sxa1R5eKnJOCb CnwMrtODN4hvWCF9gMgGtNO/DnqIjNYVIh3Y3SpybrSgxBBsX7oMabl+xu8ktcu4WHX0tLYloaca 6YRxuIWGbpG13PXl+W7yNDj+865Hq8lAMFvDWfajABk9Tomuf6E4uVqi+8GO96DYdK9f9dr+jzhU siyf6rn4SUwRi3QSacWTrhwblz3j1Zm2gR4nC2WTPdoSWciL+OejtiaEwR59Zrr1wqOBRHWcvRb6 zpreXC9eq+6luTpkrG7qKLpAYx0h6uuKJe9JfLs4jmTlXKNqhCuWZUJwEvWWRzjuBJHkbMUBVxxp xUvfY+DBsuFzzRX3YmypCdkOl4hi6Mv8R5Oxu0iOt4cc35eCqxh3m63c2/Mv4P3gH4f/O3w4RdZo FgLxCljw7oMEpEnUNam/4IdD2QlMFauExlvQTLs1LZ9auD/lMOyc5evVjXTE5uMWSidYsUHt3ONW TZxnMjU7atq6qsLfys2g0McV6W8byuMOATePNhknZQVcXAQXAs3uCDSA1a2+5V82AcNfqZf9dh6n WplV5iJnFul6mqpshncNWSSCg4/ie46sCrF7Awhd9L6vf9cNxM6WfqF13aGaUwQL7PA93UZz+iqM wT1WxZfT13r6utW6lx3vFb8tlI2o+bKlWH3Kav3Bn4ZzaP0TvIu/Ke1/cxT/d9cDBXqJkjGPmpRM 5LPTIKMVhNGlV77r1VYa6OuOCs2VeFUBSgI4yFoCmrDWBENvIMk7VBIkSu4Bv0uZk/s6AMk7D4kg HzeECmfWw04ya0IwKc8KVMTgEoRexl6uOUFIujA1pmF4Gecb0YppwSF4GS9HJlpvb/fLFQfIVJ5m fTitJQ9DcJnJZm8L81uMkzU/5op2KUgWYr+10TPhF9lAmHGmLl1hxaVrdscrOX6Yvk9WD0sIQt+N A6rra5VTrRAVn3sHuMS0O/8/I6yoOOLy8JgZ6rcVy5+gIfDDWUyS8SwzboVIRbzAcYL1bRdX4JAp lTlLgu/RRS24TVjkbdS5Dwgg8K5hXC5FiOVNVFW5NW0gRlC5Rw63Vypf8XftoH5xPcuR3V93fipI VMxofjFtoiCQ897bllbvk9fcasQ6aI+kh9QaNYg5ZOg92SNIXiOpU03uR9iTWARXysnbCCXUyQY+ 0XREmOYStGKBJZFGZJ1zMHk4nUp+9NsNBEdN92w0MBEX0aCK+lR3AHqhmJbj1rMfUUUSHxmDSmEs 65djWnSLGUGG0/fbnQb3S/IwnVVcklgO6rI3RIS8roIWoDJuUetkDspzlwVDls+tytNVtKYiAUmb 7hxlR5j3RWRkkHe/bIizcwq8BHgDvydjDidarEpH7GSFlAxQmSDztCUNT/ewWkc0Y4ZLqIJNEHui 6bt516KOKenAGPx6wmVMLU74yh6oaipEdIctgKaYQ3OyiOiHnXLBTpELK7/+0S3U5UbS1ORCgUf5 vu+6016gzTfT37MrJbHHMaehX2WuieRju99I48EHF+n4RkR7H6jwGjfhov2PFt3gRTVh7RI4DoDn DoKktvGJ/fNheR3qZAoqNPXb2FhUX9wAqfYSi832JsC8mZ0LsvO2GhY+1xGvSKKNqemrStqIQLgv lrlvUGS1V+UesTMg/+tVFUCIn5XDZzJDOKGCcvUAjqOVC/nIH/kFAxOPQf5qgm0edBojtCBa9BUl LqBo0s+RrnV8VlMKpadyQ1/m72El26e5Tn266jz5GUOY8PBEfKnFkoycxlQSy9tjPgyAg1se5kWJ mBKsCAHyYfP1Dt5BTxKem/VoKm7yMfg80FkCRsrbFr5PWYUGdVjslLgDGGj0jL0szJQPtyX4EY9W 6fWDFkDYNnS+3ZSD1Ie3A7JpJL3JAiIwIdWLAKXM+8gj7zzzCOLR9+yQ0sM4+hc2Om6oTid+Pj0p SzhCTUcvMmLYficptbJu5ATtD2Cl0Q84hRNUbHXohOIv3HJaXD3myHCGIzPnDuXcr99fMnLeAobR jS72c64bCLzlu38ilF4fOHxz3nxLKxKaoxeCCyV0uSYCjuRv3UD344LE1YqHRf1Os3UVF5oV5cvJ U5p/o0xCRcxuIW3HJXHDuHSVEbrRGwNkEGKHu5lfKiBHKHxVxkdRub1h9KvOdniO4leCd28BkcH0 6uOJdoPMsMqi9ZIiMLP+2M3mCXevHKqUemHZ8l7DpVvrmZFGu+ZFgqSgxzVEa0fp1SySrEht2OEk Gv0ZJtJ/C1bVH/56lyCiwvUaHQvjc6K1JWbKLh6i6UeUVpxZiHZKcwwEPFNyQMFyYlJxuTDm1Tk8 1wFIV/S+3qgB+BZLSiHXveBLcAE5kMNd0XPYRqi/N+UyoOiunsf+VfoBNoyY2239FyQDVMuy6zMf P+d1yCP/TPXs9YgfeJtbHYt0pdiABgJstSWR18sHyQMiXW6xbzcKEtVxaVhC0viEuldix++LPOR6 II5mC8RajGXY691F8Dz08CKtl/0CcUB0NLNRfdd0bW3T5VHoHxLGjjhWS5a3Z7QSvI/cJEEpmcMO riDqGzz5YOdaOFxncdiZiXLteqyrzWYe6BTrilmSrzw3v1zg5po+2z2sIe7XH7FD2phwEz1PLDv8 BYaQKHcdjYz6Fpdn1FCHcIj8LDJnT3gKfRu1WDEGtk1L1S1uPqC6md74Ndz5zhcHCYUF0Ry28lhw u1CJJRM7PMVUWTnKG4ssHXscaTTsmHhIcKzz0JIDFjidZXdJEzQf3lF3SAfvXAPG9drn6+gga2/c aZUErUmP6gciXHhSrZmxbB1nm/Ov8lXvATpHEMcXDJL9ZiXQls2d58+QOB1NGaWf5/WIBB4dQV3/ 1aVQQN7fpDqejSgF1b2hd7OUcfxdFmyGrXjCckgjM82vV2/K62ZYmMpR7cWpRVs4C0VTFC53d7Nk Bv7V3tcMsY7mO9FNTtyhDXoRrM/J7h7YS0f3amRNTt3x8kfVmQm0By4+XsNGab6qECL+E2iJkpmJ MZ3u/Ch2hPZh7g5K8BeXijEoi/UagCVfiKatjKpOpSDh9r5kdowgf1yVhpCsA8W2KAKHeO4SfmJf l3kmPIHSXHmvVX9o1tXKaNw+MRFffZnjgV1wG0RolETdyIS/wWfkDbz0zdYRNm4y5zptsw50H9mg hjs+wRgX/yn1UurglEdilgVZ2vwRiMmd15YWUT2Fjrl8ya2dWTfR8ModqW6P0MvVFncABzoABjj3 T7A178tu2oXeRTggwbtewYTI+/+zLQ8BdLIJK63U9xsjjZoPnlqsRe9BCDayBA0Vbhrggbsg/YPt +iHhlqFpYfanV8M1qy9wvTUdiAgUUW48XhpnZ2iIVoEkLh/SdVezRUaLjD3I6q5M3Ybgn/QPaEYV qMd3vi4rxXoyJTjXrezGW34S6F6rlLkcIvDUQfeVrlRBHbf3fn7FemfhI8nlj45ZJpKiLMCrqdz2 sfC2hz4JKKtkOfAZViL4lalFUTSn3gdrN+8EJWKJqwCZV/NsHbdFGDvzshu6k9rfkowQCxTKXxA8 DSSEKFBJKt45l124ALhLSSZISIQvDMJ7bARYAyhsotU/AO+EVXmYUPqjU9UvqAsMnJcIsBcQ4Mj6 9Wj4/HTzUl5JN2XcnFR87GXGdzogml1RfGYj2nSuyBMuNOWCgRwtK7Cz8XJ+urqW6GO1w6kjQaBM jt/vwejVJLhOgyBpSdcr7qNs1xy1x7gHWTJVjLJLlhu0rsKp7shQyTz+wBBNrtsWDiTKz+MfkPLU vaVzJJgpd772JmqGzNR4bL40zwg5ddTOUH3LYIL3gQbZmDh9i9eDSHajU1+t5hu+px8klQ0vFd4O OTA9FcleBaAKwOVB/VSH9WQPFDMEO2oaSHHjZYVPi5Sg5AWxpGD9dVJWvSxXSIDMyudXDgRyHuh6 v2OHSjx+ywStSa+J5ToonfQ8AjO8flpv4Oakk3/lxBYZciCZcbXb54cTtfk4ZHQrlFYpyyTzWiS0 IdPXVLp9aWy3Rv1sVgjymR5XancE4vYwcsHXeHiTBU4yPfrL9e9MouUInz/Q3TF43f3NjJ5be0ak K5tQvcTjokYrsVeHSxALfTP3RAIQV7eC1kLMROwc9G2iGvQ7tJ9TKhzjfySU3U001zAdoJSY42pD 0jRLLZuUG4EabWH7HcPiK9HUqfy0IDGWJjB1TaWycZ+mHOqbrwtDDTUo29RJxqmJ/dRz6ED2e00I /NvBICd91daLpFVq/JbhPfxfZPyO0DF9Ns6YCArzchPFqhhGOWunmAJloq2oAzKDw1ngwoXf83V+ +aQZukQoPMDE7T65tBxMLOYlSFN33mae6nMxaEaHpDCX4PtRlDQWBhaEKVbO/Nr52AxzmwpPv+yJ meeuqVHMNyQNVhovdy1yO3IzbKr/LfYUX+cXRqxwdJ+hKYgEmTHHO9wcqQQvlzTyc2gZuhK13HmU RyDJrmpDQAsVdBGqvmP+w5E7Qsl00h+YulrV+KsozwWRnbU7nMcANl0u7tBU0xssVHlIYyADX5Y7 mWytV5YCu0HQOSErkJUKVInCJklKMlouRtOCoZuaS2QASDJdCrBaHgQhHjgRnBK4pIVA+I5xoZCt hoXFrYEFVk3AzGeNKQDn9/uuNQyuPmrnaiM5sgRS4kLRV6DqkxjvsEoaMOP5LQs/tXgdo6gntZa/ otY5rWTYiXP8kbe/XwGNnGCOK9IF3UAZtJ/PEmKmk5YlZr7+4kcX0TXpQ/2iakdoIFB0uTwdeoC5 szRr06KUfS8xRhaXWZW5x7/z+UZXHRiK693qxmNZfPUP5UnfxnNyVeVG+EKNYJLVegE9MhZrPkjF XxA3ojVwPMvf+vPUL3J3c8L4FhZkiQ7R8L/3PkK5pQ+51PtuKyqrzZc+8gSPmKtF+224QrpBF9Ev RUqSq+J4SftakfBr2gnkzHfhIbglSAvea4GaVmrEXSQZhEochOzpxw9bkqrfky8puQhuvsa7ckFo kRRAKeABJGFRxRZGw6gbyHPBEoIpCqoYLrmMra3MFosaVUFi96t986lZ/7UIVXLrrjAFbFmRFQ8Y zcuY6pkH9ZRVUhbxoSCcD5HsW7vZsAwHNxCUX481gVAnFStWSDL0Zf2EXl5Q3H79h+o7WIJbLJ+p pvmN6VPgsKX6tQ4WZjrgNX7teBOTweRhcBDBhkSCrHAt251oGartf/p2uTS0lcwynrvZYA53HHZb JLoxYIDkZv3m87Hy7t3bUNGx9qw4fPowFJxsZpP5id3w4dGNATlACrfPBHoQAu0YblJdVVp1lORu nopxD1W7jRkXwAUTSMxDbKBPndHAamjfJY7gg0Y9LfJmj0vo2Is9QLsd7D0x/pCRJ5tiky4ulRtv +kdPO33O9QY1nzAQLD40c87hx1dRlptxicmcVGkSKv2qZ7OtR2jvnfBgH4OVjikzUatVk98PlOQb 1oDRTIpfWrBLYs11Cgbg4h350KBVO40c5sbAWARIh8G0NoI3LWHOakWgIxrVGKCLhbcsY8LfUeLf zbgvhZoL9E+Pg8oSUOsRnj2XYEH0l7NBD2ogNgGA54f8vWZ6keBx0feqkbEs8c1xABV3/JkLSUw6 KUS0/54wpeWIfxsAFq3RUBgs43vAhSxwxyMOX7xNEJeqHePYsjUFzQHQX9bsv6o5P5Chd+ZHYClT 84OCwlDLn1EqM1bOsAr0U0PqQItCWmRdSgYSWIcNFSmCaNAU63dvSLceiDdhHfTjIcbo3PoU4H7c Ix9lpcBcebVnkJBPZLMifRPDuwEzhq4kRC2Yvg== `protect end_protected

gpl-2.0

281c6f762a52afc987aa035edb6dbadf

UVVM/uvvm_vvc_framework

uvvm_vvc_framework/src_target_dependent/td_vvc_framework_common_methods_pkg.vhd

--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <[email protected]>. -- -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE -- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS -- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) -- -- Note: This package will be compiled into every single VVC library. -- As the type t_vvc_target_record is already compiled into every single VVC library, -- the type definition will be unique for every library, and thus result in a unique -- procedure signature for every VVC. Hence the shared variable shared_vvc_cmd will -- refer to only the shared variable defined in the given library. ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; use work.vvc_cmd_pkg.all; -- shared_vvc_response, t_vvc_result use work.td_target_support_pkg.all; package td_vvc_framework_common_methods_pkg is --====================================================================== -- Common Methods --====================================================================== ------------------------------------------- -- await_completion ------------------------------------------- -- VVC interpreter IMMEDIATE command -- - Awaits completion of all commands in the queue for the specified VVC, or -- until timeout. procedure await_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant timeout : in time; constant msg : in string := "" ); ------------------------------------------- -- await_completion ------------------------------------------- -- See description above procedure await_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant timeout : in time; constant msg : in string := "" ); ------------------------------------------- -- await_completion ------------------------------------------- -- VVC interpreter IMMEDIATE command -- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or -- until timeout. procedure await_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant wanted_idx : in natural; constant timeout : in time; constant msg : in string := "" ); ------------------------------------------- -- await_completion ------------------------------------------- -- See description above procedure await_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant wanted_idx : in natural; constant timeout : in time; constant msg : in string := "" ); ------------------------------------------- -- await_any_completion ------------------------------------------- -- VVC interpreter IMMEDIATE command -- - Waits for the first of multiple VVCs to finish : -- - Awaits completion of all commands in the queue for the specified VVC, or -- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed). procedure await_any_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant lastness : in t_lastness; constant timeout : in time := 100 ns; constant msg : in string := ""; constant awaiting_completion_idx : in natural := 0 ); -- Overload without vvc_channel procedure await_any_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant lastness : in t_lastness; constant timeout : in time := 100 ns; constant msg : in string := ""; constant awaiting_completion_idx : in natural := 0 ); -- Overload with wanted_idx -- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or -- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed). procedure await_any_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant wanted_idx : in natural; constant lastness : in t_lastness; constant timeout : in time := 100 ns; constant msg : in string := ""; constant awaiting_completion_idx : in natural := 0 ); -- Overload without vvc_channel procedure await_any_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant wanted_idx : in natural; constant lastness : in t_lastness; constant timeout : in time := 100 ns; constant msg : in string := ""; constant awaiting_completion_idx : in natural := 0 ); ------------------------------------------- -- disable_log_msg ------------------------------------------- -- VVC interpreter IMMEDIATE command -- - Disables the specified msg_id for the VVC procedure disable_log_msg( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant msg_id : in t_msg_id; constant msg : in string := ""; constant quietness : t_quietness := NON_QUIET ); ------------------------------------------- -- disable_log_msg ------------------------------------------- -- See description above procedure disable_log_msg( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg_id : in t_msg_id; constant msg : in string := ""; constant quietness : t_quietness := NON_QUIET ); ------------------------------------------- -- enable_log_msg ------------------------------------------- -- VVC interpreter IMMEDIATE command -- - Enables the specified msg_id for the VVC procedure enable_log_msg( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant msg_id : in t_msg_id; constant msg : in string := ""; constant quietness : t_quietness := NON_QUIET ); ------------------------------------------- -- enable_log_msg ------------------------------------------- -- See description above procedure enable_log_msg( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg_id : in t_msg_id; constant msg : in string := ""; constant quietness : t_quietness := NON_QUIET ); ------------------------------------------- -- flush_command_queue ------------------------------------------- -- VVC interpreter IMMEDIATE command -- - Flushes the command queue of the specified VVC procedure flush_command_queue( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant msg : in string := "" ); ------------------------------------------- -- flush_command_queue ------------------------------------------- -- See description above procedure flush_command_queue( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string := "" ); ------------------------------------------- -- fetch_result ------------------------------------------- -- VVC interpreter IMMEDIATE command -- - Fetches result from a VVC -- - Requires that result is available (i.e. already executed in respective VVC) -- - Logs with ID ID_UVVM_CMD_RESULT -- The 'result' parameter is of type t_vvc_result to -- support that the BFM returns something other than a std_logic_vector. procedure fetch_result( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant wanted_idx : in integer; variable result : out t_vvc_result; variable fetch_is_accepted : out boolean; constant msg : in string := ""; constant alert_level : in t_alert_level := TB_ERROR; constant caller_name : in string := "base_procedure" ); -- -- Same as above but without fetch_is_accepted. -- -- Will trigger alert with alert_level if not OK. procedure fetch_result( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant wanted_idx : in integer; variable result : out t_vvc_result; constant msg : in string := ""; constant alert_level : in t_alert_level := TB_ERROR ); -- -- - This version does not use vvc_channel. -- -- - Fetches result from a VVC -- -- - Requires that result is available (i.e. already executed in respective VVC) -- -- - Logs with ID ID_UVVM_CMD_RESULT procedure fetch_result( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant wanted_idx : in integer; variable result : out t_vvc_result; variable fetch_is_accepted : out boolean; constant msg : in string := ""; constant alert_level : in t_alert_level := TB_ERROR ); -- -- Same as above but without fetch_is_accepted. -- -- Will trigger alert with alert_level if not OK. procedure fetch_result( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant wanted_idx : in integer; variable result : out t_vvc_result; constant msg : in string := ""; constant alert_level : in t_alert_level := TB_ERROR ); ------------------------------------------- -- insert_delay ------------------------------------------- -- VVC executor QUEUED command -- - Inserts delay for 'delay' clock cycles procedure insert_delay( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant delay : in natural; -- in clock cycles constant msg : in string := "" ); ------------------------------------------- -- insert_delay ------------------------------------------- -- See description above procedure insert_delay( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant delay : in natural; -- in clock cycles constant msg : in string := "" ); ------------------------------------------- -- insert_delay ------------------------------------------- -- VVC executor QUEUED command -- - Inserts delay for a given time procedure insert_delay( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant delay : in time; constant msg : in string := "" ); ------------------------------------------- -- insert_delay ------------------------------------------- -- See description above procedure insert_delay( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant delay : in time; constant msg : in string := "" ); ------------------------------------------- -- terminate_current_command ------------------------------------------- -- VVC interpreter IMMEDIATE command -- - Terminates the current command being processed in the VVC executor procedure terminate_current_command( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel := NA; constant msg : in string := "" ); -- Overload without VVC channel procedure terminate_current_command( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string := "" ); ------------------------------------------- -- terminate_all_commands ------------------------------------------- -- VVC interpreter IMMEDIATE command -- - Terminates the current command being processed in the VVC executor, and -- flushes the command queue procedure terminate_all_commands( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel := NA; constant msg : in string := "" ); -- Overload without VVC channel procedure terminate_all_commands( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string := "" ); -- Returns the index of the last queued command impure function get_last_received_cmd_idx( signal vvc_target : in t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel := NA; constant msg : in string := "" ) return natural; end package td_vvc_framework_common_methods_pkg; package body td_vvc_framework_common_methods_pkg is --========================================================================================= -- Methods --========================================================================================= -- NOTE: ALL VVCs using this td_vvc_framework_common_methods_pkg package MUST have the following declared in their local vvc_cmd_pkg. -- - The enumerated t_operation (e.g. AWAIT_COMPLETION, ENABLE_LOG_MSG, etc.) -- Any VVC based on an older version of td_vvc_framework_common_methods_pkg must - if new operators have been introduced in td_vvc_framework_common_methods_pkg either -- a) include the new operator(s) in its t_operation, or -- b) change the use-reference to an older common_methods package. procedure await_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant timeout : in time; constant msg : in string := "" ) is constant proc_name : string := "await_completion"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_string(timeout, ns) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION); shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index) shared_vvc_cmd.timeout := timeout; send_command_to_vvc(vvc_target, timeout); end procedure; procedure await_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant timeout : in time; constant msg : in string := "" ) is begin await_completion(vvc_target, vvc_instance_idx, NA, timeout, msg); end procedure; procedure await_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant wanted_idx : in natural; constant timeout : in time; constant msg : in string := "" ) is constant proc_name : string := "await_completion"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION); shared_vvc_cmd.gen_integer_array(0) := wanted_idx; shared_vvc_cmd.timeout := timeout; send_command_to_vvc(vvc_target, timeout); end procedure; procedure await_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant wanted_idx : in natural; constant timeout : in time; constant msg : in string := "" ) is begin await_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, timeout, msg); end procedure; procedure await_any_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant lastness : in t_lastness; constant timeout : in time := 100 ns; constant msg : in string := ""; constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers ) is constant proc_name : string := "await_any_completion"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_string(timeout, ns) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION); shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index) shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx; shared_vvc_cmd.timeout := timeout; if lastness = LAST then shared_vvc_cmd.gen_boolean := true; -- LAST else shared_vvc_cmd.gen_boolean := false; -- NOT_LAST end if; send_command_to_vvc(vvc_target, timeout); -- sets vvc_target.trigger, then waits until global_vvc_ack = '1' for timeout end procedure; procedure await_any_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant lastness : in t_lastness; constant timeout : in time := 100 ns; constant msg : in string := ""; constant awaiting_completion_idx : in natural := 0 ) is begin await_any_completion(vvc_target, vvc_instance_idx, NA, lastness, timeout, msg, awaiting_completion_idx); end procedure; -- The two below are as the two above, except with wanted_idx as parameter procedure await_any_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant wanted_idx : in natural; constant lastness : in t_lastness; constant timeout : in time := 100 ns; constant msg : in string := ""; constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers ) is constant proc_name : string := "await_any_completion"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION); shared_vvc_cmd.gen_integer_array(0) := wanted_idx; shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx; shared_vvc_cmd.timeout := timeout; if lastness = LAST then -- LAST shared_vvc_cmd.gen_boolean := true; else -- NOT_LAST : Timeout must be handled in interpreter_await_any_completion -- becuase the command is always acknowledged immediately by the VVC to allow the sequencer to continue shared_vvc_cmd.gen_boolean := false; end if; send_command_to_vvc(vvc_target, timeout); end procedure; procedure await_any_completion( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant wanted_idx : in natural; constant lastness : in t_lastness; constant timeout : in time := 100 ns; constant msg : in string := ""; constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers ) is begin await_any_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, lastness, timeout, msg, awaiting_completion_idx); end procedure; procedure disable_log_msg( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant msg_id : in t_msg_id; constant msg : in string := ""; constant quietness : t_quietness := NON_QUIET ) is constant proc_name : string := "disable_log_msg"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_upper(to_string(msg_id)) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, DISABLE_LOG_MSG); shared_vvc_cmd.msg_id := msg_id; shared_vvc_cmd.quietness := quietness; send_command_to_vvc(vvc_target); end procedure; procedure disable_log_msg( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg_id : in t_msg_id; constant msg : in string := ""; constant quietness : t_quietness := NON_QUIET ) is begin disable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness); end procedure; procedure enable_log_msg( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant msg_id : in t_msg_id; constant msg : in string := ""; constant quietness : t_quietness := NON_QUIET ) is constant proc_name : string := "enable_log_msg"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_upper(to_string(msg_id)) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, ENABLE_LOG_MSG); shared_vvc_cmd.msg_id := msg_id; shared_vvc_cmd.quietness := quietness; send_command_to_vvc(vvc_target); end procedure; procedure enable_log_msg( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg_id : in t_msg_id; constant msg : in string := ""; constant quietness : t_quietness := NON_QUIET ) is begin enable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness); end procedure; procedure flush_command_queue( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant msg : in string := "" ) is constant proc_name : string := "flush_command_queue"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FLUSH_COMMAND_QUEUE); send_command_to_vvc(vvc_target); end procedure; procedure flush_command_queue( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string := "" ) is begin flush_command_queue(vvc_target, vvc_instance_idx, NA, msg); end procedure; -- Requires that result is available (i.e. already executed in respective VVC) -- The four next procedures are overloads for when 'result' is of type work.vvc_cmd_pkg.t_vvc_result procedure fetch_result( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant wanted_idx : in integer; variable result : out t_vvc_result; variable fetch_is_accepted : out boolean; constant msg : in string := ""; constant alert_level : in t_alert_level := TB_ERROR; constant caller_name : in string := "base_procedure" ) is constant proc_name : string := "fetch_result"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_string(wanted_idx) & ")"; begin await_semaphore_in_delta_cycles(protected_response_semaphore); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FETCH_RESULT); shared_vvc_cmd.gen_integer_array(0) := wanted_idx; send_command_to_vvc(vvc_target); -- Post process result := shared_vvc_response.result; fetch_is_accepted := shared_vvc_response.fetch_is_accepted; if caller_name = "base_procedure" then log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(shared_vvc_response.fetch_is_accepted) & ", Result=>" & to_string(result) & format_command_idx(shared_cmd_idx), C_SCOPE); -- Get and ack the new command end if; release_semaphore(protected_response_semaphore); end procedure; procedure fetch_result( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant wanted_idx : in integer; variable result : out t_vvc_result; constant msg : in string := ""; constant alert_level : in t_alert_level := TB_ERROR ) is variable v_fetch_is_accepted : boolean; constant proc_name : string := "fetch_result"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_string(wanted_idx) & ")"; begin fetch_result(vvc_target, vvc_instance_idx, vvc_channel, wanted_idx, result, v_fetch_is_accepted, msg, alert_level, proc_name & "_with_check_of_ok"); if v_fetch_is_accepted then log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(v_fetch_is_accepted) & ", Result=>" & format_command_idx(shared_cmd_idx), C_SCOPE); -- Get and ack the new command else alert(alert_level, "fetch_result(" & to_string(wanted_idx) & "): " & add_msg_delimiter(msg) & "." & " Failed. Trying to fetch result from not yet executed command or from command with no result stored. " & format_command_idx(shared_cmd_idx), C_SCOPE); end if; end procedure; procedure fetch_result( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant wanted_idx : in integer; variable result : out t_vvc_result; variable fetch_is_accepted : out boolean; constant msg : in string := ""; constant alert_level : in t_alert_level := TB_ERROR ) is begin fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, fetch_is_accepted, msg, alert_level); end procedure; procedure fetch_result( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant wanted_idx : in integer; variable result : out t_vvc_result; constant msg : in string := ""; constant alert_level : in t_alert_level := TB_ERROR ) is begin fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, msg, alert_level); end procedure; procedure insert_delay( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant delay : in natural; -- in clock cycles constant msg : in string := "" ) is constant proc_name : string := "insert_delay"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_string(delay) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY); shared_vvc_cmd.gen_integer_array(0) := delay; send_command_to_vvc(vvc_target); end procedure; procedure insert_delay( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant delay : in natural; -- in clock cycles constant msg : in string := "" ) is begin insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg); end procedure; procedure insert_delay( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel; constant delay : in time; constant msg : in string := "" ) is constant proc_name : string := "insert_delay"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ", " & to_string(delay) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY); shared_vvc_cmd.delay := delay; send_command_to_vvc(vvc_target); end procedure; procedure insert_delay( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant delay : in time; constant msg : in string := "" ) is begin insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg); end procedure; procedure terminate_current_command( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel := NA; constant msg : in string := "" ) is constant proc_name : string := "terminate_current_command"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, TERMINATE_CURRENT_COMMAND); send_command_to_vvc(vvc_target); end procedure; -- Overload without VVC channel procedure terminate_current_command( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string := "" ) is constant vvc_channel : t_channel := NA; constant proc_name : string := "terminate_current_command"; constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx) -- First part common for all & ")"; begin terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg); end procedure; procedure terminate_all_commands( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel := NA; constant msg : in string := "" ) is begin flush_command_queue(vvc_target, vvc_instance_idx, vvc_channel,msg); terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg); end procedure; -- Overload without VVC channel procedure terminate_all_commands( signal vvc_target : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string := "" ) is constant vvc_channel : t_channel := NA; begin terminate_all_commands(vvc_target, vvc_instance_idx, vvc_channel, msg); end procedure; -- Returns the index of the last queued command impure function get_last_received_cmd_idx( signal vvc_target : in t_vvc_target_record; constant vvc_instance_idx : in integer; constant vvc_channel : in t_channel := NA; constant msg : in string := "" ) return natural is variable v_cmd_idx : integer := -1; begin v_cmd_idx := shared_vvc_last_received_cmd_idx(vvc_channel, vvc_instance_idx); check_value(v_cmd_idx /= -1, tb_error, "Channel " & to_string(vvc_channel) & " not supported on VVC " & vvc_target.vvc_name, C_SCOPE, ID_NEVER); if v_cmd_idx /= -1 then return v_cmd_idx; else -- return 0 in case of failure return 0; end if; end function; end package body td_vvc_framework_common_methods_pkg;

mit

684f74181eae7f9aaf3dc23f60a89586

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/shared/flt_utils.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block dtAEWEOKqOqrpAmeS24y1S1B2YfdSni9G3dTaJcUjsm5nuVfmZ80PljPbQotMCqF4yghJAktRIQd EF4jlm4dnQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BQche4agJK9R09JlnuMDIbXNwyi7gnTJ18kW+stpCO16U7NpqStyJ7Yuo4pmvi94XbJdGn+5D/ap 7uwGZo3EzzbHbD50glbbuq/2LeGyhzVQEWnBgYVQz8CEttH5yNQdhDPX4XhElfzJDfTstdXo4bw1 JJNooIzDnP/YpRNBT0g= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block fi+h7WrrLuJ2Owx1GTJdrlFwCAzu5v+tCXktXeXNprdb42v5GM+yH8wJMt7YklJJ4MUUV9yYNLal nFLDMW12ifGNSPv2UY62thapm8+Pjgix1kTO1nzX2+UEB4/Yu9DohtPAyHx6Iw9wNfmU3OB6C9t4 00JDeR8aCs5yfPCt+XKC8ue3j9fu8o0a5wAdG7UPh+1+EOGWjO4ufEAaVGG+KINWzTO46pWaduz/ a+wM2MAQkiylIFfsUMpRS6/IVXQpWFFp4XQq8OHH5vO9IQ/T5J8mrT/WP6bbudnYeNuDYySP42GU TtkN7fZIp3/Jsm14CwBUZn6o6uLIMmLGN4Ks4Q== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block JdLKV8tnJsIVln6D/7B/uFXLQXj5gZfJ0aKTpyyvV8rEdJBDtZQNx4M1BAw91lkFkgIxSh3SZzVk z0BmlCySvT3gSVrkE9oQWU0I8OdXBUgpIRHiHFcS994W4ZlM8XUi9cLLrU++O7omHPDeX+b3ebgv dZA2WDIjHz3u2q85TDE= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block JmEV7vD7VtVBckrH/uYo7jX4KLyHkf8CAQr5SHyak8vd9QL7Pccpl0qwD8HUbLuDDhNAtZvH+n3e QCiGhaEIJlcj7fNib28BlS8G4lKt47kMu5xPMwjWyuxxBr9hf8jFYVFNcU6nZu1mgSopPyxAXROw RaEiNVSP6DNecLHWHP+XJElmWDxUvuEjLLk1PdjmebgKBI1DZp58Qt9IiRRfCXrRHYC8CL5sXT8r 6RWAScN9/6t9SnFte2xv7Fq7V2b/TfCqj0iE5Mq/H+dx03aXCjbycTypw6/Ie+PUm3XDg24Poffy GU1K34EqUUY2BhIBvvZTYoSK4/1jnq6ys/2UUg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17824) `protect data_block aqmtquevzjuyvwXJx5Xqu9ZXqoqNh/uNcuHx1jMRgAyWZ7RNVCbswVqa6PhQwRmbmHA2dSMt9+Uy FXlJVpYijp0E+XGYfNCCASFwatJaKiLpG08DwmbY5SrL7/jbhhd/tK1doFUwchoP4dlf1Lw/sR78 jGPsQBL48K49TuPTIPgMmmgZ12w60sopcQ6T/UnWbNS7PJbbJtLMckR+Ew+C6tCGw3tLKm0RuMOy 8LHJ6AHln/wuYO+H6Wkh9wMqFULDtkph3Hq1UlYCS/RWWuqFfsQzRoZljibKa2dmKC2u3AV8F9MQ EPD9X9Ca70LZm6+Ho/tWtKKiBtpsgxI9a/BUHgQ4UC3vRXEASf+jCaAHncrrK591WaFvIBFjgdx0 U5+UdbfknlxQXDI81dIOwZteWoMOsboBe1aBGSDFpQbvBd1zZcWmJr3jDZ8Ksq9haAC+6nshnmIz hooySqPCNS55TyaPh0ZCOzEGy8M6UfGb8+r/NHcEfxB+YJeKWmv+Xcsci/Ui9yfxL3cZkGdjnjLU hhw9cDIS0wroz1Dbf0KNPSA50HrQvOwk3tUH6DIrCRZeehNK60sk2f5TuyVIZn3G1v/adbwBODLA GPEUSsq2ya+6KhWJrjaABkPKk4alSF40m2DXapTBtnKFKAIDEScl0dctmFMn09zho8SBLa5fHXi9 mZ2s9pEyn9KInMqgXRHpljQls5exhSBmq4Y5LELnc2GmVDyBVxU4aUceVp8fRzDK1bfZHJM4V0oh z7pkbRG6UNM1WRkV2s4kF3pKYCbVdhzTp52yosUPH4ppA4pnvtg/x5gSWsTDpiucktTXPdEOTSDh rhb+/sIGmeeiT/In3oFahjguAY3D9xneEDqfUcHPGZ+/j3XoK95Cgggvynddu/8pf2Igt7iS4/4a ccXba/Pda5dglFNE4Qub69M14F8dAXvziBWzpdTPL8zgyPsB3F1ji8QPmB7MVU8UJg1C8BixiiWG PEe1S6mygX/FcEFaoYbJ/yzBz9vDJPlF3HVcIaDXED1qZZYrLyiwbA60rySlK/VmFiBP8CCWLPtz U+RNBSd3e+bS8yqThjcEoxH5iikoMH2OwKpGqLg3QkR9MJaYCtvD0Oc9VEcgDxJj4i3PFqka1TdY k70t/OoXZn7kitCFA/TzXhX1UVNfIn33zpoeXyIUhnQGzUx6fLSw3hoRnBtR8mBDFB+AsGaiLbhr RI/eWRmi0QdfR19rSeVMg3Fzu3YbkM42DjTUochvtNc8UAAFTJDZQXIPT8IwiGFKh8m7CkdsXqDR hGG1JWPTLbkynwvKB0nGlxKlZyuy1jwMeboz9eZf8Gzvt/TWo3k1UL3+WuZtkf80QFUZZHSLhjk5 APF4CTD0gtqeldfrvZyZKOFdfxXpxAbrEwHvZy9Lqzw5oAx8eURc6Xe9ZppLShrXfvZ2m15LOnN9 hQLgPnOR6zV+mbd5f1GWPaCN5/SR28e+rQCV43bwDJ8f14csNvHsbs5SlLXMjGAB9VGBuYw7kYEY jYId4/JiJjbsPx9MiiXSK/04L5U2QzkACu8tWLZOx1qggI3RYgmr6WobN+HhMgzFfyciIZxQZqMi HjrIc8OnhtVnB7o2WRDZ8SOQwMvcje9WZh7XLjgZv4obBJkNy2CGbwO/p1UheXhWPxn0BRyOmYJz b8Cu/3T2C1P0BH0FE9MPEdVVauiv9tsXDYoCknfPUKLNRzQMinCoJkobgyau1yfEjKeg3YF+01ba jnVXVk41JNKf79LL6m+9O8ZHXI2bOeWTIALIckj4jKOTQO67J29h7L53337J6tk9OKymv63gYle8 Ku5Z8IegyALv10WlBS1z45YPEfKblkAuJwrcqjYw+gB/wwV/ym4EYFJRNReq8dErV3Kva+2or3D/ Rp2A/CFOHYEqym4nArjYpfdO2b7LBVb16HtJuzfJY5wQROdLnnsAxGhpbbn/6HiSAcpDG5YIHMmh u/4zvJUColot88vOhV1ZnnMQNoxyUcvumz3mlV3A8Zst69PfnfmBN1ZZCRgGGYA+ijZXuWfzB3Ee 43JGLlLRJVU1PkyqHlTm6G2zzCy8hbG4o4rFpLG6OVJhR4ewBYupq65kInyjVT6ySXgVvZKLVulP 9LtBZ0zwt1gtSCmWCDq1TMpLz6EwZq+nMnwz8jLwIp4L+t+IdPjAzdf8GWR+NgZegKp9gqVuexdg L/xe1ZREpfkekqBAex8gPV0CFDOMwEYl77FHhG759aCCKVuRviWGPAf5LmlfeR4gUBrQ7VaQJoCL RAgrqFauwDEBG2MKxbGQNLhdD8ErZ2FjXPUkfrtnoZ+QoEAHOFJtFqfSAtmkXd+liLIldp20Zp6h mlOAbf9atIxMTVe9xJR3tH3fu/hGhD6F2QLddw+Eo+wrWtjuqaXr6QzUkDJRl8Eh2wjuWs/XnuaB sa9R3biLOW5q9VfMjmEuDe+zrFSQ5EONc4yvv4wjZBH9NWLU1n1yTwVji3qAx3JwZUuKgk6mVSc0 8mVuUEILEns9Q2R863LNtRWLe/2/5n6MzDqUOwC4wJPwmIT5rrSKdRV8thC9+9C6xVRcGK5LH7tc xS9jpsWQ4pFfZZBUo7OkRq0smvyMgSjMqGTxqZIFfa99y/AnbXR8vJJiC6vweiep5BK9e8pS807U qcTho7uW92MGvb8Jhb+pccPhZIkSMMZzLIiRPBr04M75Au6050jNxDh6zgfV3YN2JzxODRWZBzrM MG0NcDJPBjDVPYAkGy1M29vJyN+pYJIlYejWYeJ3xYv9j8gAyq/Op3S/RD8pTmsx1CczEG8L5ZPg nwgTOFBMFJraHx8EJPZlWex0dTgz7fTkHwhkqfCGB6c8njxbk3j8m+ijiMTBvEQ5JpXGbOLpnBs1 wyKnjHpQ/Pgj2XMs8hnBZ/WAcvbuPKr4B5ilfQFHL/JoD16Nt3CxPwrT1d9vy0zethX9zpe8BOoV Zgbssy5r1seWyJig8/hwzQ8mHgqlwNUUDjGEHnG6NqRQUlDOE1QHFTUkJ3gPhmxpyqQ1+C8EVpjx SxdZ+tnpdTH44/KrtKAz/bpyyhgFXyfO+xSTwYh+mwaw6TqAkRopWsaECA/AUWndn2eTM3g89z6J 5JIZy5Glkiwv1b/siQtNEWJ51GNspSK6kf8xuV+CjnrWyN1NKZRsj2BQTpPTjGxunp6V0KbrHwS6 9SqQga6KgiFt0mai+GPOTwIkYi1qJA/wS7QdEpjB4BBMw1bMgrL3umzCt9RAGzsvnQ36Tw19aVM+ Sq4+PHkHu5nd2B5H8IXyCRF7xWPRjt16K5a5geHfQ4mOHfSDoFCSH+RM7JP3TiPMZddo+TZRYp1U 78tUP73xqmwGfsNXnEBv74/C79fNz0Nxy7yh60kQ3o1Xd4GzKMuhlf3EP8w6CJtEQ7USXYOX6HzY 9cScx4t+E1gMraHkBiRExXUXjcS08qH10d6rA3sQQxJji52P7NUGjuzS+IGi0bGjpAmVs/VyZjug ZH5cjSLNVuQ8znaaB9n72sKXQTuv+ncV9SijaU102KWzsmunXRPJ3iYtKXh+zhO4DGAEP5py3pmx w1gNsKW805KMzYCMLd3lV49aqqHqjavXzZRK/SpwO8TgZl+yetu5Y87DXZ2tqA5nTkg8+kqVkN2p qaXJTuAub7dQSu98YiS45Zg/ZzZGtDSw84TMDauobIH6EY7zgsFeGCcF2JQPOlTQA2EfxQng0K3b y6CVVetSG0TSkYT5EjmIc6zTWe3aZoCMd8sVLmwdwE43zi0e8k42nYBkYLjpELHVmn0sf/5t9Zyp ztem78XNrNywOzclElN+KeQO37kJcKwTnhIavQ3FG3EVoE7L+iLKX8o8GOo30pwNu0PhhwdYuxq4 +jOk9XPMKeiqwgSlAIto0jAMqM9DIVpe9zs5+6D5IVjNler7MX8rt/wsw4iisTy3NwKACNQk94W0 I/nKPDSr7gF5c63QTRq3kL3a4QvqwbWE3FG8HN5GL/kdq1WFUsyyc6QCUlLn9HfW+Ydd9V5KnC6/ wwGaL7ctBxsoCASLesSOcptbTfEO7MuGbsUFRPvSnlovVNwsuo4Sd7WKH73yl3haBtsqeRQMjzsX CQdOMTUMrir9iPWVRZ5kqVWXUitWWzv9GvdbytzKL99WZConNEnmmdBxxt0+ODTk0ER43xhorJrF pduXSF5WIvGtKuFCV8mp8DUzhyWKw78NyvRcY+3JA79lf3ypjy8NbDfyQKjmire37yiQp8ZdLy1B 5UDDwqHj6fm0sqn/gOwZaF47FXb7pf06GYr9N3dMQJ5UtOdlIHJ7dDFXdD/TkDrmgbtyTpxeNy0f vKc6nszMh98AosCMKrVUAXCCqzr9c7hmAhqKdwN3+XvVw1oFywpHXGON2vyk2O7UbYsQuhNnJOSy JtTA25yV3SKCzPy7bBu6Ru6z7HKJEGSWuZ2JgR8FsttMZ56Lvurb7HURyFwRklfgCslaCVJEODN2 eB1TcnnJ/UtkEMx+afuZT41+jbsfBAE9/furEpjMKO2o4s1u8jt/Vnkn/Hg90V7OOSF6kmcpwacA jpNnlgl3g/uS8lQr6BQGE7Qzb3saxMtSqO/8dWscK8MZpt/v3OlG5OZJ0Jw6bn6lX5sZxcOx+sbk 3L48v7bdn3Wkoo7qKji6IPlfB4Lapwdu/0Pk+5KNJapKrxuQTqe8osrOKWVvUAI2j5PqLLDlCP+2 IPMyk1hd/IpF46UxcvJGAfy1ltUisBUPkknUiQQWQ8V7ecJdlgweqhD7SZ73wSaHSz5QltJ5q/Ts fOLQBT0Bbtdzi3us9SWMbtgCd8hgjcIe79nqkDFJ+nEswSgCb2yrZmeoNZHPC9MpsWzR6VxFWiBu f2F48x6ncGIqPy512k2ynoC66XWYyVuzYNRrnVKrfRjcAXmVJMIe07ZBTP5TXlNu3tlwIMDtTWTo rselVzCPstr1HCglo9ERgNZiiWznKU/ZRqkvTvV3mR03+rGsFebNbzOZIi0QHv9O1LBoilTiiLds jTtRDiK3o1AbR8iKjSbx0WcVtTYP5tRWtLH3OfXrMEx1/aJSoHiXoRx/h3h9xLSjLchC5NVxBTJk GFd5qLCUGGYFvYGFugRhtMR1Q/S2gW5h4+mEHB2T0yJNLqZDMNWkxN2asgkrpFYqwFKfmy3YQWcF hgE+8YLfDo99wGq70+zlq9wopu933j2bU2CIuui5kE5TjohCMmXog3sKcOsZ9qF7gdl+Xq4cG/t6 XYEB/hqASr7BE25epCBtUlYbMfmRyjYIZzE9cR6EB/0KPZuwYYwv7WD8lSQ0AMEY5EqW/RN4iHO6 JpDgsm9BYxjPimMPt/hWcwzX1Am4xc6qldjv/6y9EiwPOKf9xv8/mU2j3dUZ2Fu3kpEDIPzqu6jg itB/VSZKmLfk1aNHxLomuC8a1e4ODg20Ipx08yMTfaI0BqbaKrML39X9IQD9mpmFtoKVABZYta2j unuG4gAUZ3ckXXNuWWjUI+roYOtprD4wLyO9KmgegBBPiydrdhavHU3M4ndZjDCZQncTZJVVqAqU 9PHCOaFTxP9fiK950/dsRl8RKHZL1tqIRRQVMLrZuGvOkKDuMs9fCe+qqINdN25KMswS6ohNELXE rkLIfBJjAhLsbs7J3f2itqEwROFJDoUsqRXjwDmlrtzzQEpA1An1+8VrdPbatMiHDm6YhyYX0a16 Q4etDvcSbO2PtN2XRZnh/kLe+AmO8X6NnvciymPdQdblFCxL8ZOknHoSTKK4bOoHXnxX8lt6Is1w 0VuV035JIyZyrhcUweHhWITNGfXUbfOHkdfIRNBr1oevicrcUK4CxwDzVsfOAESB/0tJ0mSk90V/ 7qxx5Y6ttxA3ZEKARsIqi+Xfv/A/RNx4Q3s2alm6gl3B1CP/ur9fAZo8659rTH80pxxsR9mWpN5u e0ogVEjDVNcWvr9B5oxS6CqhzgRX9f9Aa13vs0Q+ErWQOILDR1zK2YB22GdwHRA1siPBFbPNwC+L vOSY1TATlL1yeVKj7cZJp2OjaDT4YZ62vMiNBlV1a0+iHFDBa5pi6CT2kBdupjhi8wN2JzEeTRm8 oVJusZyhoq/AW7+qXdlXaCxNdu1pXDlGHK2UfCp8ZVYO5Ti1Aa+/bpTHGdjTsy419VBl0cVIw0Bw AO788I/XzdClmY65DbXP+ExZSyeDJE399HPlwcIVZumE0jYHlgBdE+YnkhC8mamfv3KFap2j9OMO I5YkrqpB4AFvvU8yDJOTWBjKCc36cs8hjifDrSBRUP6bnYI7S//XW/eRtXKJhyiV26h4pFrEjdzU eCJgPWstxB7W68vdrsH6cF4Ny7uJkeGAe0lCG2c0y0qPqIrCB5n5/XvU+DylyI8c972f4e7Hp+js P/kmB1ERUqzGsRaX6BdrjafY5H5u23RsAKpKkN9Hkj9OUejkYlSThDcR160mv31NE+SVGzHY2DGh BfD7OrkjfefL01exfrCXUqBQwaixFz4cyXDwqYxubgDERPHAV/yOr3ufA4upM21grR5cwSGmZZjk M4WjkDQCeQgxJw3koJEL+/yVSADDIYlN/gEQjnGdpWa44onLoTmFjWpPdP8ym9xohf9UyDuQQZ4e 3IuYNrHm5nloNOtwhGC1XloZ35iLNhzhavJCVriOtr9K2cN76h5NnudG3LUusjro6tC+VCGAPcSs jv4Bz48MGk4aAmHSznJsUdz031PFYnWSVx7xQMC2zRILwytdRuy+T7K1anvnlAFKlzDtVwnLAm6J ZMwlO5t1DjEnkFAZSYfl2g9wuCTvc9GmIIqjruCLAGYjKAZPutWQxEZiibRblNzPKVUO82NGt4QM RPlEr1LVVsMEAscSTy5O9EfPDrpbeg5k09zq6igET0Xfq0iegYSvIbzRgNSkjbeqljJJfnjrg7xH wQa7UtO23tQninl+GBvQBGNUbj7p5HqVocN6+4acUxiKT/7pW+b6pxKaYyWkg758oyP0dw0GVJtR j/aRa+4nmVpoh4jSTY2Pja5kHsC6FloRVwBS/c80DmbpD5kHN5KwTmZkXZ5kQqSBRAVD7nLVbeL8 twfi6UviHbzwvXCAwkjZNHq+JaEelapRMC2qzjEH2ynK89IGRIpp3K1R3npbrq5OK17ADjhD1pD2 mxruXzoN9FsTQVJgBSnlqrdBbk4fPaQeoHjbjQ9vFTnQbIe6vJp5WtGt/IyUJ82tWpolEosJncSB aK/E5LFY/2+Kma5N5zj7cS9Sd24+Xz9O17XelQgkF4SGxAjtDiOeTuX4ypHq1pSFE8SUnJz66KJm ryh4KqQNq+ZKY5a9Cke9rVPuODWFs6NTzeGIDtasNeoLZ8Fjwhy4ioMQmP0RVV/C4EzpiSXYLu1t TTYEJ5k5tmmSekEnTkrEGZn6vFbzoAW3SJ7hM6a986xMDkX+DX8H0obmyjtUKrK0FLRdhEH8EOp4 +o6n22K3DoUt3rXT7+GbIT4syVx9GJ9iP34gMX0MoyApp79ky+8n1KhHidyxMyE5P4UGrh/CD5fJ 5H5U7LI/etXbPQGSVqA/dYFMJ8dip427ovEnL8fAlqAsguKwFMK6vkEuzWUSPua7Ng8+XNa5Shtc MPto04Z+PXa871Tbevk3XZ1eg+7is0G/2Pwx05Pyw/0e1//byOj/B5JhLMCw0J8x6fRFx0FmXBKU AXOFKl3pdHZ3iJaln4uNmTQ3BZEAPNSzQmZaUXaVL0rUFsvr73bo4GMliXFIraouJE/AYGeiuNfS gTl+yk/eLw8f4d5MqsGslAwsnBZ7U25b/oIkj6iQmmvwemTaglKmbPhrXKbd/e0JiaP1MqMREuh5 iFHouUWeB6DKCBletb0BJnEJ1KsNrtLNPFU1exh0s+HdliSqAKgHSpOQ8caKJAaeExyZurgpBZwX sxjka/k+bHlo97XMha2yoAz3MJX02bOM5ac1piJ6+pP0nos4AXMyR1wij6MfmNNCBoKiTTxevrGK RxAYMWr4lrtUzT3qUpT0Ffc2kwNQPcpr1y0oOb0FQD8l55dkqKD2G/AOugoMH/Zwn8VpQkS/I0h3 SUfwgc1BGtnFcY3JYI/fELE/3pbVVk1lPrL16LM4Qi2r/p/H/H2jmO/vuBTCS67ZSHzPpZYfViV6 BkiDYQU/Mh36BbYEmCiUdJ2ND3eiWkq0vXBxl7fTjBidCoXClgtgIjEMJckeFj0gpAEDlv8+Id2h R8kN/UQhZfdf8ce+/Vxy+iv4XSSdkM0pNpeRXfwt2+a63bwG+biDUsa9kY0qpBU6PAih9LmHR/aH RSxciGli3WKuledWxxdjD93JZXq10fLcyWOjsr97I0RPrHde1JCyoWrCguhukezHXnniIL4zG0WC pPHGnCeabDnTHWgCo1ibrcoS+sz4ymAT6ZB2WiTy2XOajUmfreYAm4HTpc9TRswhSht980nHgjHW cjF6h2lR4Add7cuAHSv4imYsE8Y7H7TDHcx6+VgXotpP8G06dqTIrV8f2h0xAq/KHdm/vEd5z5v+ pTQpBO63uBCFsyekbn9KFnJwkCV4X9uscu8jWvL8chYqj8b3W9xWA/ubK4g4VxBaiTbhBqyI6Vwb iLlTPTm1/ghcmXp9J9eQLKoIePwb5yaNeWYP/ZvDR36WZbg7ybe6Cc200ZuOJY55b44X3DllgCb9 uxbwBFAzhzec4ZFFBkRLMgBp6vTOfUb/aBVTCDWuAy0qhvWcSKAlCnxFdAemL0dK/UqqbAVvCUuZ +Gon3rmwmGC/sTkDLAjjaRgyVSkRDdcPN/BD+LQi5Nse2m9aR6cnQb+VQ3AKJGVB/FrZpJoCSnGQ bQnrq/4zwxuCBxbynTXOGRxFAmBJMFmJf9H8p8h++yxtu0rtueYG32wr/mn78GtPQBfpXUyFx6TH MervuZYifrfkjMFAL93lE2rDWSNEKUFMiHokRts2PE6YfQRE8olgeXlItUHDbseOcOGJGgccTTnC fhbN/RYLBhGYLgiYBjU7vCvQooPtMip63lF+21z5JpknsvalTwJp6QG7KW9x212/3v0FrhFfKRHy +7aGvhws2VPW9nQKiDZHdgRg7Cm1LBvUIlpvHJAfogA1yT7FarEkf87SUmfNwosjYeWl6B/b26H4 Oc1AMUy8HEAeBj6SGtVXBYUzC8J5OoHNlbEfOseKuaycdi1y/oFS+Fk/Je9d7jKB56VRAmz6gYAG VmCSBIC7NaXUTgiej1ux4xRjhy95UsHt4kKHJD6A7WxCp7n0HXfk9Hp3e4uJD2tSTftLrFIaKP9E C5tYUbf1GlDcT3N3OEXNAE7WCgG886xaRX5KztPbAJQTBK1j+PFiK/PriXvSuyifPHVS7vgbhsFn MpSfinzBtqBeVXIENlEKZzS2JLqT+RiTsSEOCpzVBO3da3jFxFsAycGZR0dWdBTJ2lc+gKk/ykYD 7yOQ8/sxFCzyEwQqkjRFQn+S65uBgCji0RJWv9EWJ1/+/stGUeCDDQ74V4tMyg9D03PgIcWBMhIy vH5OgwfzuC6IQ/5K2u3HnLNWf+XdTAYD+qZo5/9+6nFVB/NCCz/YFJP63kIVXoUIggC1ADt/v9ce gRnqmea108PmSO3vv6RBWm1gW3Dn2u3d28j3Ul3jBUs3uDapGBombLAcbgaFVpcKxRh5U14DS4dz 7xRVZdCz8+rSLR9oUExYDHpDuX7XU7kgbiFgQkRdzx8TOdxcbg2GTfGUZTfUE/G9oHPYlO3XvtbN zRJQV85rbOmz6SH6IBquNuRQDEmprPEEerVpJGPu20SLUgx4F5GOLuSEf7YftmnhAbWVx4XCoBKp R68m2F+abfzLgZbL+Syr4L6FYJz2u9Bgi6xWvcqCDXCG6WnRPM86HLaIxf3VoAF+f+1i5IQnTZfc S/oYhtR4j778hDLcAuqKi5P1uOkIGks3gqtEgfYmQv/H5mmFnKTQyj8oTWPNzv6z+27MrmK4yxOJ p48qeFBubMIeLGS6eRFg2D/FPQf35Bej34F9zbw5QYevlwRsE7m5nT5mbPVH0w/KSUP5wOFCoOA6 a1w0FnGWmw9GwPYpufzh8zdNQqnTUkpKWYhQ8+FbOWnUYXZcol/zIXs0ny3lqZrJNH6vQ9JnZoQj FYmsOlF8nj4cRxDn/zdWvdlFAY2vf/g8iqkSbUPCbQfWptTowGm1N+mjg610N9eRR2dUEkdoPBRd iyJ3kWK6fKP6oFbJqx0S/mmfyA3KF/pS5TsRp3ivHXpKiNJlO+1Ya1G91eWniB3lP0xCsfDH8EPF V86qahk9FA7S1P9pddxCfN9DrhqxB3k8Go1+OASemuLyLBLfU6Rcz5HgHf9F8kzHtVKdIFtSaxqL fEo8mecdm6rywrm3QLVb080vuhY5UsD4WM1Ac8XR80CUFuz9zKNQ3ilvOD4TTM780KiyeaszctqS /0j8vTAUZkZ3WqeB4Vyte4qOjHydp9TPYt9tOF6ve2gf4gjFCOgqCa+MB1G/oRZEyHxvuf0OxzWY YCjPsRVf335dDiTlZQU3eCAAsiPpx6G5mOUqIcW9ECWnQEbQTV0y6HtRzglWHrx36vy+tC1wWE7g /hjEBAOjIZlm5J1drkLbAAidUrz9zXxOzOtBbBHBES306ZbkQmeChS+nXa7isHcwuTgWhF2aIkXp p3TBBZ7zMpL4+HOG+7+zXFAAvBl5rnaQAP4C0pPSoYq0Oc1eYU808RWXARcExz0PXbJSc7xvtlUM xNzfQpKGhxoI60mitU8fWYr9lBeyokf20NRx2jByupTVzEVtcG3n2KmKEVs0xKq6Kdxizk/rcsw9 Anm9EGeTvD4dmLjwgMQA5st7W6yRBzoA/lv3b9T+3LuGhwP6I0RDrqwgJGL/YcElYAmoqtmAryOC e7PpMzdLxU2U7vyUnp/m+gYyaPranYgKJUPs/R9iP/zM5wuH3BmvH56bw0nSsOz9R2hDiTZ+y60E ifsnNV2Bd92F9pyBbfZvlFHAXal4byh16ITtczjsQJUix5oEufMUpAeMZakswGIavnInBYmOlMth RN/d9Bgv1V+Izd/SCx4cPp4EFn+CJlm9PHliyVjbU1jJOO4H9efg+u4NpzimBToQXui7eTrbOfE1 ryn7x5fGxYslLd8HHX0U1LarHZ+1MItlss69gZlajginwKK8saQPE06V+Rpz8GY7lmVBneAneGfQ CrZ3wGPci+BJl3QeuNi++z2iPOaflYAjdObhXy71WKrJSASIsLn2FT89O8aumqVc6X5zlulqcZq2 fiOeo0+QS5ndEnRvPvvjga1dwNWLY5gnPjvooYhWfve9oO9/cAXX3aj2f045mK6Z/DumnKBOf1Ue KC8sKe7XiczJvCdW69F1/iqOcvzfo1/qNdZFBM1jdYr/2g6ls1416PlnnzkrByDKoFEa8kk2nGCg fYWMVSWqkosqyiVNPPnkvvdASLLrXCQ/dkMa3P0mixBFT8YEDYOKLnMc8l/wnzAZIPCbMNgE0njJ lAVksfTBLxxkQQ1Si+vuJzfP/XoCjelkFkrtr/nf35OboNYAiB2oYrpty7+F4lwQqWujGaZ2mHsu aLluyKlcgl6Q/6P6MHdlLYwGAi7R/E97ojAim3Gch8pl3DsJBLAMWiX37uVPXTXXZA6iRG+bYdNW uPv+R2H6oAE98TPrwNKvz75SmqPcjjmfzmC/vVfTrR++JIu3Cl00SEo4DdpY1af0nQk/YICD3vfo Yt3ZLxPAPPzTlUqAJLm6qtgeU5xILn9YpTnKN+BDTqVZ0UbODm0GL1ztGt+/dTO8qMOjZACO0YS9 RFBb8MEEIZC+w1hbThJWi9/uQ4Ug3hzc92fUPCtjFbB2gMSH/T2L3rxJTY/iuvd/OmFrZSNgDZX4 jjUTt1rwGvvBRw0zSpCIBF0F1qioLI+M596kDtx/GkyigLLGEsoOZEDGifwijy5RJcbfo3r5y+Jc 5vv0rpp17Dhz0oLEWaniuCeC28Ww3T5CDzM4KvlqBSNslv9FMWaFNk8pZ8RPoX0dzxkuouTFfwSn S5XLnS96LUKbHmtijlKBEefuGCdkuv3mjnEvoRSgSIGt2txlBpTmzWPSs+G5Qw2v5PkZ33gYLmaz q0qkYXxfXtCPXvii8Vpk7t9012wXYBMVL6ckmYrYUth8LSuWan9tbQX/Y4bNvaNMvGrSNII/Xsum E/CIMg3NryGBu2yGLFBoy8OlMwOBG4BlM1MkVyFDQ1zGIoqiW2Ue376zrRdFsSlLGg7MKQ2MRIeF wmxrahdJO8kVHGnTanLNJUNph7gmNt/Y0VZBNG8Vm4bHKfzwlZPKcKWdLWZ7urlEWBFme7Pzrvie dBormljUI7cRVCaRBqdsetrdK40UBN3xHwYWOS513WVJ+7OnXJxmd9JliTdxiIsIAzafMKrQiwq7 CjbUyQRP7hdabSskfvEThxeiYlY+Eup8kfzqbgqZ6znLVRWDtMxSpncmAFkD/RFbBL8xHuJzmzC1 +ZsYgmIOO14gpgvssVcMCsdRgGXw1epudlJgi433OSmSWBDr6ahvgJDMfcWKJC9vmhxWiQc2ljCq 20Mtbh4rRqleRD8aI3yetLkf+jlf8hs5YmNh2x+QcW2As6I/pKcNLPL89XTFb/NoT9ohUDomq+Zx G4ORlGTwqIogJSAfcj9bwUO1UCBOWIMt3FJhPTeofweD8R57cSyx0BZn5/wCeFo/tMhR2XBcXaWi I10Q+HhYWC7xKJuvmhRwPiKUIUcSMvaU3U/RJiXcyS32M1EwYsbT1zyCAtmx5cw/+ZR6vefPqLN7 HxNp3Ehx5JDgDI/e5Ltd3xoj5xMiQG0mZVFmjitmYU7T8HQpJSiUeujLVt57G03F3eF1WQy53gHr gdpWQJaQhymhMZD+NiKbdxzJNE0x0BQ6Kr2r0Q6LOgf9y8mbu3/ICc3I0yY3oCY6tg676H+G9NPy 2OMggP3zX9jqxaTchpyZBOzKAhuRldpMYUKtm3FSkY15gdoMokPI6QOecHaxICTjP5UDaIhJCm1G ILLOWyuhaOtrBue7/XS1SD31SgP5G8nv7brL9QkrOO+1MydlzS9Gg45TXXkMsVSp4rxEfF7pE3nN 0GJtEjAVcHn9gLPm9BIGHTIPRU0K4KeG4yxQt+/RauSoDDDw5hPWjL3ECATYvEtmwuWn7977fKvE UsGl7db5Ng08HL52G/HcEqyl0D1Co8OxnKRNmYB/264xw83o18c2OY6qQr0DaBG4mfGayMHHytP3 N434uwfhvnmvlQOzkLywitAmJjGQRoznImrd7+ymoXho0zrd4d9dygdt42/j68uZaqZ0kNslRf7D EGUxY0jaEMQBpRqAhjXWzr2xPpCqlVXCa5JitWe9d00Cx2m7uaAZ/Ih5ctXaB50O+mvGM2zIWKFu xgN/VrsKd3/lsFRVMqeKI+aJWwiijqJBkbGoFVKL5cCY3q8Sg0R3062FhxoMSdAXbSaSNeae5tkk TOJwtfQsiWfSIO6c5IRd2LWpPasV6dZ81lh4w+OKhR0IuyxRsEheNFFDHzdN7tw87PU8i1+mWvMJ st9AEomatymoC1R+1v+q/BN/DP3Gya3e8wOHBrMvUkfiElUueICw+wx//gYHitT5ihWXdmf+d3i3 2HhYNtVtUuHF1De8TTaESM6gqO8DLrU42Kl55xsDsAVllLJu6fhrp1pGAvswBXpLuqBc/mWDjMha bIWzRt932nr3KTbtziavybp9+dxtoKl4wM2IdtqzVMN7DbZU+qcgNli+j5prn2ZoJ6I/SqXserLH JNbQxyq+rnGnwJfCA3TWfZfpUwL5/0WQ52Sw7eExUgI8WOk54DNuN9VpalCSCHrniHwiZ8oRm7rL lxFRwEQSLsBY7AzOf038h+X+2MubVhJwz0Fo8PGuQ4WV4HpQt75C4OnEvW1MNWZk+FT4jyuiEl5F /8NfSf6+xRTPkyW7ePC144GiP0tFXfeduK7FsjMyGlMw12xr5+bH8FiLi3v2Z9JoyopvfJ3JHhxW LBoqksX7jFPYKGY/EYcYoFnEtrm93qd+Etn7s3NNHmaWap32xYYA9GKhugxBKgDHm40MAULhM3zi fhcp5k9kGGzB/pY52bAxCx3HEapFDE6tnusn7wLTQVLHjg2Fo96crR+lsqmd5Sihz+17T8D9MM8m Ttbl0Ht5tXuuDKMIrdtc6ypropcjxiZp6qn2SMs3MtBuMQhGb5e62P6ob2DHfSzx6gZ40iQLXQZL MOluIpEcqVteqb8JsUJZ4eNGb7AUR5pRKR9c+XWybyFe1u5Zm8QuDUPaa6c4XGvdKNSmopGnizev ttXrNOhOb89YKn002exuXuxDKMB/RKXsmaVJJ9I8qUoW1H//jOCW3PkEla3n2HhJey82Qpky8BR5 5iX6GQ1nGi/IOhICs4DxeaNZWdaywxeRBm2f/eeQbj83yHywpVg7Rnmps+cgS94n/jEb92R78w1w 1KCuHfCZvlPgB94lj6XfBFu8EExfoRjVQZlwHJcC+o2mN1NmuxGCVuv5EW6UE3DMsnaAdMFSKele F0kyUte0WGYbbiQVs6xv3+FwZ9rRaDBHGnB7roCu1xrchAzfVOaE/C1vJgX2C7iiq/ZmBAScPUeo 3QiDopMSP+7HtGSUx7zVNjAKSlTh2pbpccbWmKNzS0ENh4UJqlYAnyak8f7EdXbM9QFxDBdjjKnJ qvqR/Xii9JzsPMTrCHykuF3ui9Cb7XysIFuIl21hOst44pw/aNWF5s/AVrigsu0vthU+cfSMES1y hDQpfc4XWhssSsVDqFhBLwyHBL6r90QyqpURePSbaXXZcJlJhs0RSMFr6ksheEyuMTq0W9jQs1x6 8IR68+0B94WVm0V1BTz9yWhfq2wjGebavvJ+F5oI3nQISP4+pdtaMvXQB93S1bTt5mpSP6cBb/4x YxgTMNlaWYZc6h04tRPIdv0Zzr+fzKsbjBJl9eBGRPcxKeBQThfIxwjz+2INnpWkZzYkOgkjF0rK oXRGYIFy8N9aERMZQbJ16lSs7zvcEnEjZ9ut8drs47IrAbg79Xzms/viDcMGKtu22YiBj2XJU0bB 832DvuWnQ7V1zalg/YF9KCTcmap/l7NqiNsKRdmT4G9Blt9YxR3CSmlKDoNQGxg4SvDiMQDybWZa QmhFRXqq/ZVyGLznFBRdTMIhNG/BS/p2YJiskiRwSxjIXKmhuzQJVtIkP26aklzYQGdTvaNJkQKr X77IPzMaJzCCjgtd66KqC9ZfGm1qzwyv8pKLcoSrzEcugEhx3dzM111drcYpESkH50AkFy922qVP aUitHaFQJa05RNpTVDKWvBU3sWNZi1oTswYNryotn+YPolxbA7yuRj8A7w5t4f/1Klt6XliIxjPD 1Z+w64uDFnNtQoa4I2LEYIpmbm0w0wIFKvGxkSdHagE87hLM7nuQXRuGvTLo1/GWAHvy9v+y3aL9 CT74LuC+Vvv07vEYBa1NuS9LBgoPi+j1esIWKRRjKX2q/h9lihMTu8cUOrEgHNy8eDTx95nI/y3k krrta4iXMqLinMCDwLJ0NllTTZ+9Jo0jNdQyAX3gnGwsbfWvs+0GQVFtGl9g307Lo/XLjUjnYVCv gqJ+RGSYHCL+ZPUcxdDpA30GLwsZm9rgYgBztUMZrU+X165SwlM+NW5LCIaH5n2puwAabV/ioYXc tEAuVFjUXuB/lQwgj1xFCCcyd2OpdlhAUK/M6/QsI9KrBhQh1yvGqwvSKN1C3NtAVCCslOlH7p1s GN99No9sH4Oy1W/JI0K8NxzxBgX7cvcvVhbSNXlDTnb36Wz9KDHlreWfMfEQk5BYvQc5yZrYYPxb cKXu/32B5sJoZtBtyB3vXww5OmPh1TPZPY5ganP2REhTQkP/wZMXu3WXY4z1KKxWMvatnv/j8MSv ynY8ar0g0IT/+QCOphse60S4mSRcT79qXrVZydozXlS4ZJIn6PCFkXzHWPJoUw/qsdDasxoshIiQ 7Vfla3Oz0gZdjNG56dWADQR7XloNub8t7HCHXXs93nSBp6MUFiaKKS+gRnQhFINt8GjQqRETLiW7 hjAIrNw2pF/JmHANSoPRIii4qOhgeduwxWTy2lqiVn3ViPD990mTpVKyn6bpUlQuAtKoqeSMXpxG 737lwC0nUEANCnrm9NiD3Y8Wylu1vrrG2XS3/lqiTqyNPSf2sQcUtqspcHDz7ll1TbOOLEUrMzPs 8gn/2Q5jezUOsZy9T+zeiOGXyEwfSjdN1HQMt88mIucTRVm+8y15cGbiz8UH3LyY2h5bnspl4E7Z VtsIkvHMfIHFewy4i2rcB+ocszTgEbT4+NruWNkyFqk60WqefGbwjzPPBbm+daJEFtVTEwMvXKSu ITgHvb4eh3NDCFcBWpbxfLhlts+7sUaG94KwaRtkyxXOzufu+0BoiEcKE1W48IFhssywofaRPumq D3B0W+5M+MV9XWuIBGTEhqCIctp1yowYANuAxVgKG1TAQ1r6Gr5C18/8W6xKQTjrYe4hScnAImvR 1PGJLAHGENjdhdSP4pqAtvmTghY+qTGG9n539WfqWxMVXkRgD0Lzqza5oJ0eLeNWSyXARLe5/7T1 WsD0E47CO1VR6bwGIjsit5MCRLIQ4nLrKEfPz9g8WqliJdWxnUjjU8g+AK1QDl9Qkp/YIrxEvLeV GY4kzs/OhjthjOLOfWewaKpOQ6ikAiuPNHDZNP1cwiXiF4JvOEzYfjmyuJUdyXGPoAsMhhQN/CN9 LW5KYqsFedsppTLOQYcO33gzifEvDbiMG8Q2TAHsXLjklCWpo+HNPxvqu63tq6oMaQ4IWBIneGSk R/7UZXG5gfw2NI9wyh+TYeJWvHTXh6sZHCp6bPDkxyI/5EFC7UeWe8tdKUnwfyFd3Y1K1UT4YKtZ SONmhrpznfWHbWkCrDqsbuZ3do4dFK3ErcRqxkW/xmytt7OC5qraKltSAbiRnjjdbebJGCd3ataG iVqdOPzrnttCxfjUSWoyOkl0DUTjR8n2goxqSjyjC767tGe4w3BMDBJMRwYa4KytbFJwtV0lj+gX YBUFCwOgzIh+z5rohxtHrQXnTcjcqFynZ7KCW/iwDQR8o+5JSZ/wgDKKoOylKECINhcIBErND9Uv YpehQrWv78+2iNzXTdOA+yhRHf0rq1Lh+Rwgz21bM4VGzgt1Ew57Xb3VjcvWDI4zjaKlGx7bk6c5 G5A0Cjh7IO/gVMRzoLXvN1pGKsNo/IlikeZUtdI5gsbp+vEDV9vcQFh87KSKZUWN+ssBbFEA7V3+ rXkgAjy4AKIPVibcEdyWB8zzGbsRsOohbmPGAnmZLe0v6NooRfM+r/EdssP48Q0kYZeMbv/KIhvo JTo4NU58cvjM1bA5R8MmRZdgWL5lfI78tS9xA5Tirw1bO5V2J7PQPaLcLyeyngS3Ls+c7xHvvnXo Nl+lsOOwXvjTgP2JHfaC7hX57RbNS8MKAVcHe5q/HIZ29A28L5gPXDIElaHq+n2XVD0TQ7ZsPO2f 1SlC9JO7thSP7Ykz5mbUlyLbeGJz1+siWa401wL5BEvNUxSgSot9zmm1VRfxVe1qmpKSVG9Azs8q hkXMP58al+mrxF0ipjfLIml/JR0k9uCjGYvco0XWt4MUprpJ2KCo7/ke5+XoLaB7fGUk4yUnA94+ yJcpqT0QpwBXEgVaqOL4aBA0P8TYninAK2NgMK9aAEPIQapxoNuU0CLu295YzL6Ff1/KPcxa4Nkd NTiDzjcsKg7RIPaWPbg8eQB009nMPqxOD/3dT2s9hae8BQyl+TZ7fFEOIkYY+jwD0trbC/TgOmrk 41MJE+O/TiPEuU4sFucUbkFy87S9eomUrZTRutekHfjspbYrMn79594LlcbqRJM2KcYjMF0nsWYl MrySe2Iy3KNhKTkIwrjfEan9FB1oqVQ+0G26StTXc8Q9Zv6W6wHPs+IY7xfpMoJIn0CEf336ljwu gZ/L4tbVxjhMHoZ/bqKlqZEaXZMaZINfzgGQyIcOKFdY8j6piiqUJ8bDKPkNjXU6BDCR4Vn7fJAF QxxQ0J2JiR1Xwi40yPK97UGBL+vbSv73jp7XHYtdjEeS2Uk9FO4QygCIqDUatzeU7HOsPQpUcTu2 teQG83uSL6F45ekh6IeXy3BHOd6vWZyp/+xKzbEx6JhKlXRV9mnCdTOWk/HmrJKxtDQt9OhZqdBv Yr5lH2/+bXEOkwQ6cCIc40zfDBqvFPzBcUJ+sxNLug56m/e2iESFU4aRIcR07V581cU+n2fA0bGM FOOHt8dQP94aHkMK40vnMa0D7ZYVdZlfYG+6PBFzMs/Y5YnUaQY8V422RdkaboTugNRN0k8fVIu7 Tg6YgsWvjtMyQRlz48Pq++aoyVtxnOzgkZQLib7TwCnx1o8IEh4FeZsp38zNKvC4SJhCBUxqaPFF FjbX+Zxo4sW2NnVn4qykbADleSNv9jSrB++rjd4JXc6Hiuni1femCE7SMUqZjo7VrmlZoaTBi+PQ hMRaNoSrDomNeZ+csdexyNj4t2cVm6cwmaOs19WGtoTz7YRfU+6i3R7Ymthxq09Q/odiX8ojRwac d+6xcpQB+ST9jzjMLE3yGY34OAqcigXwPXgPaOX8SorHXmgS+G+URmJJ3X193qUfyKXV3wSoZ5PA 1+/A4hUW9On28tEUzTNjPCFdn5mNzGT0sHnvOk2YtKL0MNTaP7/f6olZLGBuKfG8ctR+oFKGNZWR StBAmf50n0ffVphDGHh3kC+ZgqJaI4kJ2ESigIaAfoBcFdJsl1erP2Mm7h3ufXE3chDzHPLHgcFO NMimSo/MkHYpO/kbVcMVHqO9DeWZlLROMO3g65bexEtHEZ3IIMQOuyi1TQ+X/NiSes7Dyxl77wFn ym8qt1vPY5O0L6H1syXy0RPJEA1wvghyt0eCNmdGepArmNoFDO0RGKERTS0JkwOMaZg5Xzditv1E nKdB70JZ0BgiyrUvSRz4+599xw2DSPZ/amJriPQtH28K3fU/jnMrrcVttPfkDO2oOgwIjKCUW7OL u4u9cuRDtEXmE7JF68bEG4hjFK7iMbYZS62rFruj1Ahycufsu5VmrdIVaWj5Tz1Dwxoa+w2pBzHX YMeqNLJjgGwiwisJ8uW2kjHsMuABQ2+jLv5WlrOBE39B4O+9saHYvANqUaxf95FF4x3zz9NbleKe oK+7ba1LzHuBJdmxzQrqqSzf2IlQLUgWBOAWM2yXfEnQOErUE3iRzgXO508z3oY1ULGaSWwJwrYM si2wg8KOnIaMrm6jLOUFmG+34O8PXodSfVzDeGKLbOXsrwesly4MqHKtXo5ixbtEaLT5zCsi82H3 8MT0A3opZquqKJErgg49eQWaIUwzrQlpcWHUKj+o31jDpMbkqa04I1REgRwoEuhCVfMV4fxyTPqe fhGy/tPjTR0p4URQ2kIzr+hSgv32bnuS0CwsE0PRLjj1VNiELgJPwMOgXxHc39aEF7chn7CsjfLQ sg0ObiQ04vALRze5XytegOpAytgSKn1fnrRWi0l+MviqAIrFUloUJHzF8Ie3yQT+4XZDQVOccgz6 OXp9zEzSBTn8qEspFnT1lLUYKH1BF/3YxnMbuhFgOYIVzBYS9TVzfIi4Z+LpgLiDP1bpnPvzRijF 9sdpX/VKHjeRczlLouzHJPSsLjZNQvigusEdGmH4dF6If7T6hKt0cSL4/nPT2dZznIWQnUpXGsGw cnI3AJha6svGMNWgToNmCNYZrAY/MZyVM7fEwNxWuN6oktplpsMvqWYesw9w+lM/6s7d983wYpcu 1x/uqODGGGcqLrqbtWRPUrgxxrv7A7XQE65tTgRTOUYxTr/eKeJERCoHzaK+JkLzhrLpAEwgE23z T0ga8tTyu9YLg93/DqLEVL2BB0HMoS4xKU1kcnLJRhrcb9mUTkazaolbJWihS5ksquwVZzKq6BeU zBbB0ldC1GeX1S5Q0klVM0x/XLGlDUgL/sRLlImOs0IAvCgtZJv6R+9Z+4o8o2ZgRMDgM2hx3rEl P0LzcFlR7Nfb3DODDSBDTbgSF+XU74aNrljtK55xbWGxaII529XcHfgocDC0BI1/xFRO5PSWTELj 4JDDsV9t3bG08DlN6GAnccKrPcdpIDIXJAVwo++gs7benXFj+mCoQjED4Iaf0EmCrSnNZJrbZKV6 3+w41K8mi6vsi+7vSbBDeGbC6aflDZRtslJeQ0DU+CO1RLskwijEyu3WPEscXUs+YszjkL988dGQ Juq9cAkY3xsn0tiMls4i+T8iyJ3AfJvqD1Zo3oKw08Oh1Wh1V3IrRJ3TUOWQksVxslWTNU9SMzIC kx8gnUsMXVHr/jjg+/RmA6DdAFJYtxyHJ2nkek6nPufrWJ6+W7YlX7Kagg7ddv1Sr7YuXze3C8j6 UW2YWza7pWAjCEis+wXGPF1Mh2an7M01i6ymP3KOMBeY2uI76vG+uU0bKV5h4vKfqF/k9s7UQDOE SpEdeMQDT0bJU2koHU4ejgdJfAA57zOyQlvQqCF23S6OWTBgelnATPvth5GM+eks45YxBx8T8dNr R8aTO0/47W9Ct52cF2w1KVvGcb5HgRtYVjqXbYd5HWfgktS6PwDFBqpX4p93BVVXBekfR4bkx7Xs cZEt6sZDyt+gtlyU7trlAWifjoQqegjlsGiN8qQzJcAkxozl5nCMZtUMDntNazCdrI45qSFhYX5b wLv0p7o2vqSVUmIyiRj8G9j0Fl85A0jDjXkCk5VWxpWfTJvJVGnU1oOQMF2RFJBdhLT/kIdzSSGW 48tjaaifYOBv7bEyzW4gr5q7VhqTCs+qhDygQ2ctNRYtCL2SuPVZA5WmFlgNzDA5OoIW1HOcf0Pu 8rsZ4IWAU2dI+HCTqMq935LX9dXC886ijsvckPYlxQTrNJ3W+EDNtVBJpSE205Wmk0Y1jaG23idO Ou4S4RyGRznpeCvtWktG772W7difP44vrK27DM5xX7tmh/hhDA198G7b19wQiNy4y36LuDuErj56 5TMEvNN3DOB7bffBhhsKG2eyGxiphSzsk3Yu6ctoT/wRrWWL3VfqABOE/Y3DBOuZF1nfWg4FAHEy 47STjSyhGsGBa1OmKD7/2LACBlGB74x2s1LR8oJGrR7VD/J6vHYXbyAel4ITYRw2YhafMgbB9S9y 52xq7uSJLu8aNCumYqtKUI10M2/MN2IGhG6XPDE5MFf/zMqan8GiE1obpazHcJunPo8kObcmaTOz 0sVj9nBTS1CwwSrzdINYze8e4Tg/jzOnCfGW3gkc5Bdzvn5YnfnAzWa2P2M/5F3LBbSkbrS4GvJ3 WRKWRneHsh2F41FQpkV3XII/jJ09/PTiNe+jYLGYp8Ax8As7cSKHgu0f5UblVZ+9TRsNIRWSpoKp mw55KMPdnBPwxRzd0OHI9ZcUnulUPviSr2VKwd3LKEDeQZIIRQZaz1EQjf1zhnhjHsE5bZBYGqG1 xg6e5iLwDhhFJzNfufLuiqQbN7Sq6th4RGVDWTL5TD+B3z/edS2mcHtt5eEUbFfOMUqdi2aMJ/wu loIKnIBT7wzGvs+MDcTM7VrHlkg+rff8lsFXZM3G/o5NbIoOWS4nYlywhhK9ErdpMMSJNUaQj5fJ RfZiJPRglFubRhpfTUXIgL6K0vmVY1BsVhylw9E1R4djFQ0m/Me8Pe5WvovXdQQJgR4gO43DYOL4 Q+E8l3RbWYe132LH1gA1jc0EQbjoWpWIL4sHO7ERXX/E/APxIuPjppgkyjh5WWSiLB5qgu2gEQ58 5zTlTdP/MxMKKsBETg9SSf4cV/8R/Bh2Tswl0jwgUmhoiT9f5CF3ZZE6MA7mVGYJTar92FRS281c 7o2fLohm/CBjAzcxO92zKOgMxaQFGzSF+ZVkoGmaqPfcObtQiQkO6WODCQbSzV4RcJubLzjbdFde oV3mAd+jV38zi9B5k5YeBhm9oeby9yXHuxr8eYCsh5aeAx54sB4yQ5pEPiJXOKueve2Xo9wj0n8w ExG8xI/uZ4McDBSuiwx6dMvGM/nG3M1zdXwZJHZx73hAkwvOy64xAWdXNi0f/b/noIxvszFGXd26 ggdf/EcD5ItUzGMUQYqJziobsfl7DyLtxgI7e47U0V6QorNqvqm37V5EoNHJyIv1Z/VJuCeaAs98 5xJw55bt4CfV6MwGhUDMiGg8G/pV2Je3bF+YVKMZeHBbIjA1SoE+rSFZ90zFad6fe5ZyOg4tMMuy ltKlExkvRpa4AqOVbyT8/2afHYBsqLnIgy0ulc/HVhDjbFQpYKO7t8UD7bs3DKSrgDwVlduDuep3 y0Zso3zRaNnS9dcNd65U3hOKYGZmW3ogFovAhHAIcoFnrhRLdHCQVVbFPYOcTWkJ9LlhgZlPG8Op hjhOgzy3wNQrAFuvrUHHDWT7V/eiOsulKyuhz5D02T+mg3Pp8QT4Qi2fSaIpTgw0Q3A3J0tlo0lc JRVD4lQQTqlIajJogH8S5BbOmbQ1Jp1uzCBnHLe8mALJcKpclRVY9BJJDxOoaLtmMmZs9KUo9b9g 2MOmYUTk/ApyHl/fHW4LvxkUa3XSTw3qQsr3HGhKLF/7oSwrIDFsENu8ZenOX/t43Wn7WSUTENUv ElJX9YJC5nKjJOBPwMwr6zND+jGRR4gAW/kRxpx0y8PGdgF6cdEem8cJ2U5C4W/wT2jQYHBtYdk7 KgVdAW4CniL+KWGoDQMTWOTbD2BX2V4jkCi3HDwjN71LtsAhpHLuQNwFLPrvnlpTU661NrhWsri/ O0z41ObZFabkfEH3AnJJR/QdyD5zLJfOpQplaQKeAhTmkYelHxnl4YDhcykUxDIGRuQ8G6/tQZrg EmQk0ai01Cg3sRfgIPWO7gNw7/KaDTzN+YVa2k0TaLoo9kLEhvBz7OOZs9pRK+B+1HxSEnMnOun2 D4jEvOJ33j9l5d07L3N8QFzEFYpD5shWNLtCPb57zHk/WGe8MkpZOEQk4NH3yt/es0lKnGx7Aewa 68YfOHJgHmE9tnOXc8ANDE6JVAQVi016xyZYPCVNf3i7vB13kNnpLWLXubUt5DRg6GyKUdkvYvPR kLPxfKU1wFRhQKC5u01iFaUFaKXFaCZuXNWG5oIfj03svXNWqX0qky1sz88RSkjhJ7s3Zz2chs1B 9JMIj91W9zOCMWQtZWqqyfoydQDvLjUuKGAWx7DxtX/PqJcsRByZIx0CvalswsG+N+vKbEQ5pMGp TAtfGjC//gvZ668X4RyS0R1zkQf7Wxntf4KivWLm0KTp5c3+oJ9soUAHqPHWDK5PXqfB5qDsege+ DuAfYroN2QapyBAuai8z279159nOXaGtbGExWMP///lZy163pVzYyoa9xpgWJa62dVMHpnvad/oA UqrphnJ1lh2KXFEeavFlrrYB4oX69haSsMCHvoR7NhxeokVzMDYfotR3d222zm33yT0+btJPVWC2 C0alCQsqXh2ZPf8O/9fjpJnXGXmhyZoSQGR7fWUrYHCi8/B0YXiSeTENTDRCm6rtIwE2Fk63dQzy WZ0LIDvANKXbTcEbfj7gM1+t6iTkHn6SYq602EJqECIQtBNTiRIiZvA1YlugTZxADhwh1rVZjPjV eliawzPE/OGrAt5nlkThdii6kSUd6APpEvzLMfaGm+zirvx7AJX5FnBhGQ8k8NNO8RxRvwQosqW+ MMX8GAKXSkPWOhduM7wRAg3nyczhQjPtp4Iz0BvKIifMy4iiEsptWA2AwOEGUyVYewkFWNhFE/0n N1w+K89cgEy2NoT+M35Q8O9nLq6LpIzGpQmIxcr2TWFmZLihfOft6Q== `protect end_protected

gpl-2.0

3138f61f0d2a619c39e77016ab9e43f6

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/shared/compare_ne_im.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block h2WWSrz+D0TWLPOzP7lOTCZDI/eqUIFnHrDzDQ9v+JR608NI69bpXqoV63l0SVjAuzmbclp7XJBs ysWydDuWxA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block R869UJMYRO8mVLLNHGSzwGZDZ9qgRHUifful5lYkU1DWVD+AqZ+c2nQgt8NRrBHW9vApUzyq6bXw 8xEjzZBjVl/1uCB2FVTI+VzLDfg0omMmTaDQ05r4QRdwAuVyWz7h5qxKKrrlra0NUBKbbdUg3Ocj BxU5IPAtaFgIm5dNSRI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block gBsF+qw2d8x/ccbw2S3MiPmTal2ZtaOYaOwfh7xyo/wWmIHTdVMt+DcqXnwX+tgr/pmEJ66z2mFF XjRqmRiXJGY3uEOrsF+ziw5Axczu8CBTne+JIIwvxDXzg48XEmU62CVY5sJCwzcSgB6q87k0+rY9 5jb3T3/imgA9kdtRjOI0HhFahNwH/FrgREwigRoChGJlAHUTaNdqIsfvKzKYuE2IzQQdemTirshC Qf3IazP/ZXEGfCsCo3f39RFDvg0cX1/IOC2xIHvaWPmRvCoK3sAEHc24v7YDdpJpQPEVaW2Lx2PO mAppT+eYpciY7zd9xnZk7gx856oKg0750LM4xQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XIrODxiST7VMQRIE1s0vS9fYU3kHdTTPkI5KinLmaC+RZtKbtN/+X6QJsk+DWKFyprRZT1SffHCn RsqFGUalBiZYEI1SFR/AedXEnT72I0+SsW+BpbA+Zsh77yE0mXZmlIXkj2GTAYf9ktImDkDrvIs4 RlFsG0H+sHxf0jopuDQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Kz86WAqS4KgiRahR7qZvs66gcWZfEtOyy6TUVz9LJGmATBQ6vebHZqpbxxobuKlU833xcYR6vyWf fzSL/ef7LHlP+AOBGvZbiG/EA7Zsn5AVx9dz/l61cqp05v5jrs4rchlZXJckcMP4Yo0PjAcIIwRM /rNFTABQ/U3LccqE8OV3+WyoT4nmGOm1+1KfKjiAcGoz8yqBPBjG6KfSOh5WOtX3l20nx10lkCnG yx1IbFE8E899bTQ2DCjHQH4+WUemhZGLIH6BKvRF475e9jiHNXOuckc6B/bbrbsIPvrufGU7ZpY7 FCYjihIaE27Ik8VkNmXEXP00X/GjWwWA8XZ4Tg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7696) `protect data_block 2D99qemIBj+gqo+uOTOFwm17OEq3H5EcRmGUcRQk+5BWmTL2MwgsMvASZ313Tj0FVh6X3rlZZGRf DwF2OIh7qhGPd7rcpbyZKO5MJW+monGRtd/DRU/bTeZnlB2zIPdgL8gbviR9LSpGVXUtQalPUegP 5oRQqee3vgMVnc5ChaySFvsbwy12x6CcZ5dSPnXzK3PTD3GIj8umRa7I+U5Mw4NHEKzLTBjTT341 uxaIJjwIvel41/2t9tRjlNxhfmsKX6Qrfm6t7byqimeTAEUOJSZdyx9Or2kvBY9MSD7NSES9Iwcu zlGxj3lX1BKav9jn2Xu8Y4Abz+vyq6i76KoQjGP4NUk5J7I025R6N4FOJLaZ0qMPRV3J4NgpL/MV 4C60RDVlQ39r0AugQKesg/JVI33hRrQMww29T2Sw7EXJlP4QLcz8l5Kz9F4pVdB3+FJDOvN6rpdE rz3EhCPq0I3A4XGslR05JtofweVk5cEo4n00TGvlJwSl5EmfT17gaBDCB37q6/6Ns9iyYyAaspEH StN117sT+9QoZetB2uHHc9BeU8zEK6J8lNtF9aRO89oQSdoSRr/htfJUWLUFwv/d6Fdt5hdta5Uv jmY+I3z8yY14DbMdmNxWKGrJfspcbhVCSkRTpcEu1upyev4nGy/KgmjyFItZnnldoAmHWxjfYQw3 Tf4KcJz4/m1sNQ8bBaFVkEuIA1IBry0Y6MzrfuWpROFtbaLPXeRJdYMcMqhg72GRXalFXh4vFFcX wFybV0lxRf7XjGuaF4MPCf95PEJwdwE7SCOKFot3MS8rkZ1r2w/ZhehlU8AnA95You1INuWGMcZn 5866fvZnN61RCjt4eV9EC+jDpZCAva1EIqvyiyfMXqXJ7D7qBI7TDbwTd74mB9F9a1Mo53oNmYMG vq4n+YgZT+Xw2aQasHJzFNT0aMJ98p29RW8MjVlnQUe4p86a9Pmk3oTgIdulobekf+n46vKqY7/S HmaTGzlJp1OPMrBQ6kESr90/vjJZQ/vqxBfEM2sV2OwWkFGjhwOku+H+J1QjRB7Ah7uMr0FmHmll SGSNBDzwmSiL5Q/ETQmwXxEvKMpm7oCMOo6cAUDtHCZrVlGrGiKFT2lCbTGGLdEptQo0JMQU6eMd BC5lvpxZIBo1tmXenRWFEMgOGJKz0zT+gtrRYOYYTwuhy8kllVBtKYNW5nmHzt3aqc5uMtlMlXeq 1gkTn0+GPXlZBLUhOSPWW5iebbkGfvzaajMGKFEWCUnVScXYzCaKjVFXpnJyQTcgouwxs+4wpLWB Kexxd1Ml51D6bE1rQn3Cx/BkJTqv+O78G+44+dOGPBFPgfPbolHEzE7CdseSuEOs/Ndmnp4pWTCG EhX/rVauRzzr7ip0YGyXEAnmsWYyIzD4vtXRjVUkT9pUp3+U8oGXpAkLeV4uCt74XpuFbAWm6McI +YxLeKlZ2Fg9qN4VrAoet1Dcpx0kndsd7D7OgFKEBAipXcGtT0PdjVF5V9PKyEjkoEBCKampQ9v3 Lg6iFtXGaYuNIxtbPQMs9IeMeT23PkBxGPLVbNxNTDmjTbcrEPCtbo2mL0U6iSzpiPW2g2/g40vG bIb1YrPKHmXzithrC6dw2DqUwDzbbycQ8TmS/j6ur4Po1NnOkXfG8zz8XIyO3vmwjU6UfzSb1yCo S9J6/MSpNfFBc0QOCWMyylTzLcOXBo3smgrXYbMGRNT0jrB+aCE0ViXQz/xFOanL8mP4dWAjSYuI IYWkOM/4vpp4ebF9dse0dkIVAByDG/kUAWz2by4crPCZClO30DknR0VTWOsgQkH8pWR1muNY9vnk LxXw2vvepbQpSmilKJDDJhYq8N8391YdfYiI94n1fgxFRXqcuVnekOQMdlG2hE55B/1AUD26ZRZI jfLNm3tdR2Ko2zsGeZbv/833VWiniaIz97gxHdniJEIAr2+BNpEXPsGnQO75B4a31xmhZnCNSP5b HA8ge0Z3ruVmVFpwdgKyhAp3n9XWpWWBs+UAsDNGjN7rM7XBZKkeeFTyzPYy19482u+v1DNiMabB 7fVPPLPoZp5yzax5dr3AKVuM1SjFHmG1XzQipuklaB1BbiY5X3zwN4MOYP2BYOXEAihVEYvdZjSg 4gWgFk4GxG7szP1ciymzN35thZAB8vn7dL7l1TES4fP4PG0FKTTmGrGFZHaDZHLTvg1QafhHrd3j ETZ/XxUSMj3lBQRK17bCvkqcz+5hi8WmtwW1gGi031PVYO7qCL9ms9WJvIULaDzxc2hjQgm+2DnX 5QwpyjgrKyqFC3k0RwSFBYJnVPBqeFdnXni8uMhhb9o+tWUEnIm+QRBd3Sv1Fmv2qsAvgWjOCBGe ZCBNDUzf8LEuvvc6Wqh0ZY/+ZXnz3HYniD3W6C8aIWSP36pp6zCKqIWruV//V/sUd7EZHnvcq88F dZmnhsRaNyMFDgRgA1CvVeOH2d6o36fdmytFK3llnPusDNUZRGjgQmH67Fz2e3FDvzSom79Qw4Kr Akq+tjFNLjFqFKIA5vvSZPq5fr5GffSJYIMctcfwpv5oJ3hDSN7U5lFvT9vtBrPScVp1B++Gy2AV RdiqXN/EcrFyS1O+qw8yQdcG2mUeZz2UUSirFfzZRfJ99FnH4t32uw7upesXDCj0fyWCsADPC8FE /u1NNhcexzPSekN2OrBmOwdNNnh2zw921zLAvLelMtJ2HvaDmrTJKgaWU2BnNjbsUqVZldgl4LDu aB1ROAWEmLlLqk5RurJp8vE1r6M73SXHOERZnrbQD+ZYFhUNpL0bkCZNA3KegK8H848hYynlH/Cs e3cXyxo4V9+kON3RiPz/ZjaV6NYo13Z/fgDsektSSFam7S84R/s6RXnjE6i7matMYvNEAN7XLW7h CX6aSsaMucOn8m/cI108FUGDmFrPfqvu5NDYWHdEN454bfIGGi2lNILdYOM3Dn4FO3PRpkYpcA1n 0yRwirD7yVMRxCjzsxsmKP3+NnJnzGFS+LOnfZdC22R0FImZWKW8APdS6hYi3EuxKnwgzXy6MwGr btnzyOQ3ur/vQCroVD7HL/H8qQx7h2m6ajyV6OU0w2rky5hqFam0MiU2/GCAm1n8gG2iI9AW1CGS Zdjq7DPudsGc96gEXcyf4YaLbh+zCzG6dhl78AedeLxFDkNqlzmLRhfPt4/LzXVPfgizV9fiE7UG mXRmPGp1AHCaY6MLNB/kXWwKMxXr9U+qMounlUTyd67cAnS090NPxeWnZZn+hZJxx8WD8mSU3FNH EMRUruPxg/h988TtBRlLCqmj/90KH4i4tcfD5JgkvzWdrzJFHCFx3gFb7RXtLEZJXZxTkJAoAAEP GNKyvMGkr+rgChpf0fBlKcedf9rb0Fn2bppakcAJYFtXDuWQbbuFuIzpctbnCG5nknE28Xb3rdZl VYAjx8Gc6+icbL5aK22y1OsKBQof69vbyXrbv7MA0xmw/5GdL2PxSY8WqKXHue9jrVVxm+xVtF3v II5eG27MjO7d6vG27Djs8k2CnTY4EU9flxnFn/mP14rHSArvkPZ7X/ul9vv3q/7BGROGOpc0S6rW 8yKz4yYTCMsDMADG+E5h048ix+fsfrfWNKgQvSxgnUyfZXobbwRH+yIPBX2Sgwg4g1R6WIXDQai3 47YPVqdsBMZ94bA6bK6ReoD2bNOz9ajLX7z7E/EVDxs55Wx/KzHjciVGrKYFUYDnq9R6QB29MJ6V 8M846yiEtedTSfqXZteZl0XVhMfPys3DfbCM2Tu4gzlNlqRBLGUabJsAPLx1r4FYCbznYhunacMF YDWsyAFMKgnMSGTS2S+ekUleXW4uMsDXRnH7BC/Y3Fmi2jCSd4DAOQtahwchcBTxJwbuWRVSlVnX uV9ZK4SOqNXbgRYmeyUuld6sxdU7sqBdI2HtEHKgiUFc7f7VMVbZijsLPEwGGWRb8dgn+dKcPAqE UegAmHu/Wdq/sdw8PxWQooyYD3yy97eA4QtcbCAiccIXqTUlbYcGrNLke8tDEEXPP5yhnTx++1gK C3rOzVg/pzr5lZe03CdXT4GmL7Mlp/jjf3K6lhb3NwD7HgGOOBRJBrHNZlGcByfB39pihWN7ZQjF EQh+I0+u4nnPozCxVHNhfE1wel+O6G47pMLJ7+oTcjU5GDxYvWLp9Ql5sfnrsVFbxxQfSOybRfhW NSgn6TXgCzIb4RnB5TyXM+29YKh3fb60j6VQkfBuQ1aZrBXfSoSSc5lERndAo7AvbX3Cszd3wP9M lX2VEcFEQAWHaj8o/3DomMkOx5qSNXSbVn6xWZqeUFWFMOVIh/DNYD4QvPUqicUxM8fHnof7f83y 6VfCwmd848vr9kbX2BqhOxDagD7VxlwaB96Z8dS8ayQdIvNtZhm6Lkd7C3BYCu7sG49lvubtPOou HWdYhdw7l743ppki6YpNaV/ttTLx2dwkgnolHYipH+tozyfZhK8Tog6J3qka0/M6huMkSPqGHN9F tZpgrYTbYTpwlKpZEbfkrMwiFdMq02tHo/1/PdVVlpM0FF+Jd42r9UCfo3KLY4YRRhUSherYTUL8 G7Bak8xT61t0a8u2m5vypRZoxEQkqMXhUM+ecJ6MZPVBQnKEBm5YJhH7nw5gbKtqt/1ZN/IT3m/a dGeUm4e4KuYVg5INsNGJEPruqSkEGpjsJJPjiyGokdiTAh0VTLsAJRE6FjRwYrrp9J6oXycNbhp4 3CLc0+CA9fkErkmSQw/esEgl4iXUYLG2iPFot6rUW0IznRjy2elDHgEJAIKui6CepEbZrzOQp0W+ FNciC9Uz+6HXAXvmg0gVH9IBFFfRz9cyIxpk8rjiQuj2xxyRYtfFUroDeuZhiBOjklonIgO33Hfa uIb+uYX8cSgVq/Mal13fNMJQV2DfIGgdeYUZRmzzrPYtG+RiPYVgTL1bDf9wSXm6aYIO0Lxrw8IW Kncimzk5OfctVXz4OtynLfmDeU41yP36fFshJhyh8iNxrPcVYLiZ2wBiZ06rL29iThb8Sapuno3d VBxR6ndLnqI7KVzeo9M7+u/asFdeXiz2FRnkU8105bF9VFPQCxV11PlVv/vr/emMoRFLbUOBKH3s pIJvK5AVI7r8Gfscm+onTz9YGgzRZPCeKVg6Gb3Obsk1K++Hikqj0IWoyPVxDY3CenIRlwag/GNQ oQEyb+IaTzfsHC/uBGuSWgd6JOBI4xHZJ2cLfFowvqy65FQ8B4ju5ZTM7tkZYROB8DZSwyyvYUG6 uHHZh/uIMBTrLUhOCx8CfqQ+g8Fo6j8M1+/1OynJnmG7FDSxjqtwCgQamShIxJV6tAAOcu4NRJGk 3SZWLJXWO82ySYkrYRBth6CNPYmyOFw97PuLPzJhtvJUWjD3dQR1KGSlYONNpDHn4McYyclSPGQ2 IM29+XcKXJFnutZQ7qLlngiqA6jVDACwyvihICc4o6f4YNTD5ktGB7iorcZ/IJtKb7C7HKsH4kVI 0N0rzRrWCa60CQcNNMN1rS/8Qansqgh04HGN0pEfE+kTdGBOhv4R/mR880PyPEVK5h+dGrQQZNV6 YkZyI4lqqksSzNSZBCmdYf1Z1giinFV+S5+uXqDhd2l9uYUxBPbXuipUtK7LJytu5L2xlhM0UfSW 0mQWOv34WSQRGKV+r9XDUGuEtATY5YOZIea63yZ6UyqAFxDEIvdVBQs1gzczlTbhtMNFI6kSQ4ZL GlwyiC9o+BEiqeDFWo0ozww5KNEg4sYxZi3+i28Kkp36V/GMWKDogcLTXdk9qr3Vj/mcCIcAAaYf MwIsUU6XiBUGYx0fqZecaJqYfR+dtgfjSDVDETpmPMYVNNxpcWmi1zZKTX4lCZOXLQ/wci5OE5HQ 3psl6wMQar5x0d002ooMTa8MCMNADENUW955tpZp6jtzsxWYvzcAq3a5F1iWnBArjytYZdxK8Wyu 1yJXJeUxB3FOgozTKuD1gfSNU34sGyyZKL1i09R4yDjI8tC36yWJnTKG9TjzwqSGIoJQFefarPjA dJtVTjsyDnZXaaR/Quyu3AUHX4rRmt7jLYOrm7dusI5dO6VBFzMGHyEH6lZRnKlaeXv16bynajfp XES/LcEhOiL33thKKmvTx5FIiD61kkaq+xYc7gAgE8bAjVzJ8LmG/uCxXzv2pFfcNsU9bwJoNerS pnj3DMt/X1dNfdSz0LWfSYIIj9nlNjTtPbPAEpD9tZ+bRbg6x80X5d+PdC4eW1R+4GE1UYMEJOmV +Kig3fPclWFEbd9LsYVFtLKATVcmoeQUVpzOYtPU6YGK7nQ41gTvnwbHyw7OB2lTaGadZ7UYZS6n wbi8XXsjJuMuFE7SVQmzXY102+RudV03kROrY3fMwevJbADKYOKdJBGSo/RLlUvXXGVYF+dTkepi ukp4xkx0yq4nii0AkSGZ3kWejvY9L+Ir9pUdLJ09zOy4K3y6j/v9GjMSFgxRQnFyOcO2vLPgWnoI TX3Qe5FtENTpGAdPlfy7mLksGEL53+xSLUXU8VxnLL3+oF0zYGI5wQzITxM1x+EZmgfpuAayXym4 EwI01hY4kHOMQSG4eyQv6THVOV2jCPACW7OQitilOBX67OUh2frcYs7w9FBuL9z/TKDVlgIpESk3 NxREQh4SfXzGQA/gqObg93s1fpgQV6Si7XDPXmqZeCGg8H+FjSCyZ3aOIauX+YLTT3nONyHRX90e V6pT7P418bXf+6uB6Tja9xWuXBkKgW4aM0dhNRMGIqemuGgmQN2qbplS0DSMc87zDloEW41W6vo/ FPRdH7ylTZnPUNRb19HrF93ASDwZ3JR/huKKkBrc49Zw/PfWqcSg7WL5Byvu3uyywjf0210ct2Gd DCHiQM5LOS6epe5ATOpXyuHu+VhWXxudbokiVIU4XEIZlqk2Icy1vQLmF144H3E+QuphJbKaDJhk 39aNz+eMmeSJNiVW90hexzVyVi04AUYU/rx4aI8IqwAqNWXjekgPpByg71+1uXS1lASUV/BMEJNn BRaKMEybCpseiC7Iz9kFEDWqQeDSDdfzl6CcNlD1Z98HT9gPogFVz4TXT+1UY/znc6F+K/KXovzY d4dW4xkUxE4fxN8Fyf0IRO6kFfSUwjWO/NOaHJpsL/y5BtioRgK3SiJ7Z9W7nHQQnB55SdeOutyS kp6c7CifHKDuY8n7wa49LZYVhFSuAOVVEkH803NgazbXQibQ5pix3EOOHOd+2GyRIutmEQSkdOAc bdpoUBDPEcG7nO3rWpaEWy+OLPcmpljVDAsKbQ9JJmToLV7+3isEMpSDeME0pNxhIQj2o8WtsECh 35z2/gaPypensjGikajBrdC9kadXaihdmgAzTgvTCnrA8M+0LoI356acTR4+uX15ucN/3qZ+9zu+ 6+exrFyTxhfitELDtkEMSSXUg8SeimXbNYK4tXtleiknLmxXjlzKD8GJ8TKrVQLNlfgjWkcEzH+y Z0PSHS+hl1WJlexVigmu8KDhbur2NkTQN/YUfiVPfvnFSef1LvTAiuqCDyMTF9SHs+/bQvDr83YP IDAZFAOtD+fi8bFEfOyjehMEJbBszXrSwhcgy8Xx6e01I67NzViMis65T1DAfKxZUxkKSGaA4TfA F7PmyoX59vjRv6bRlqVKdNKeEttm7b6Y1J/jRQwbSZNquN0JZ49TCYd9XzqHvhjJ+V/Mt5EQmwbX nbGjfq4qvgtw6HYPEZq7mzsmpXXaeD5n2hgvV/xmXMVUswbWdhJIajbI8qBNbuJq0m21OcsjEnTx 5TwVOzIbEk/NymaatCzPjcXOYwGZyR3q2b0u6qmTrRrXBxg9nQ4zh+ZtEUesuwU6ujWytRgGYVDN Ba9d1MSft73+b69l9bIRy8jjaU/4O86fR6UdZ5kkikfaV/jGkxU5LUuupracMTHYQOmEddeVrGhd BbFEJz2BMp8MRlFrUEQGtON428urL497A2CnvKSZ1TqO21DyCk4GTqKoeLr37zz04fXJoDuNqU5T 8ahslid0WXUbc3tEcpFoyn0ta18kYyEsDZJJtEwuW6+P8aMP4Vka/X14+BOaln0rASZuSTGgt4Dm LvPR6ZL5EeCDYy/JSSsIOB6fk4VFLhRoTeKmJE1Lek7iTUCXM5AzYO4nlOQmQsonIDsDdvctBAql J6fCBSc1xKxHuz+xhAhF54WUYbCxh2BPY2YVEyyWAFzQWq3IeoaPu/q3Cowp8Jygd3PgIPQq61dg lNv87j7jOd5wGjr/rSmI4xMNXRSG/I7VuLxdyOpHZVOtGXVF4VlAoFchOce9HxWp7BC619vKVwOI 2jkwsO2RZ6JVE2vDEHMLVLRZyeLWh775bA+km+sDhjZJauAWagRFXo2tJTSfsDUAk2bDk79yhKlC UIH6ax7PhO1AMszlxOy0BDgywOVjTJZt2DvtTeHjXnO0aBgYz7ihPA+PoYWFQl9ZW+AArsu6m1EA 2cTp6ZIXHJYhRhqH2zF57O3DFjlnAQ5DWuVh4j0A2tD/kMXWnecVoyeltE3RxkyPRbU4tnyTsCGD Qmrj/85JGpRnjXsMsIe/wpgjZzPWW3Jxvvr9As9IOvgOTB975JOoMHgltlzKkfI07WlHGeju0PLk AVT1lWGqZSNmgmCuTIFnrdopPuWviuFDzApHE82gIEQ1Nw3b/6Tl9aDvibC3RVjwKgq6iv4O1/Hd EQ0071CPPzID15M14ULT+PqHmZr3rBFIZnIqKaorHhvXWjMmxgTJHRQ90D4cqSsP02zhfJPJ4veR QczEeY61RBK320puudhxeJmB7d8OvSgtsJsxQXiH/yyH03C5SWd/RhXyy9TjenzvTyp4Hti1XvXZ brvea1X7wH0Q3uDXTM1cFT1EpuTxsUv1fscyQwFWRHhbQZv/VMwf5RE7UNja95LmChWd/d8XTlpA 3yUwR+fesAsVRiFkH0h68sjn/qqnP/DWF+qGtcA67+fvg87/raR2gDdIs0qCk5h8HNAlsc3bD/Nj Tg+JRmqSk7grAlgaQI7mTujaaU9711Jii3LC7EaZmfTsSaG310RWtFkBlSsX6llftWJwwLzB1s+a d/ykfQbERYp6cFCajlM41tEqJtV22XDpLwtr1I5CMYsh/f/tQVsYzTOi7Hye092v7DVBGbxUROYr jx3vks3y1CpTy2d7EfGF71s/4re/FsOGK7hCMUdUfWuLAIGp3LlsD+Paw4hYj+baeTmSrQaSe8zF 6RDxQ9f262IpJKYQxm8JZD2dkrBW/WqtERSh5uUjXmK44JMEPbmZpL2L9fNN1CLUJPf+ktFw/Ou0 uddOCNuMuSupg6f1ivFJuOY8e58Z3ACLpQ+ilgDYpXB2+ZORVu4rIdqUb6A4s76HYXfMhqnh0uji GUrCjQ5HzhWCxj5iyfKWjqCNZTNKZANIa9KAbMzGiB/OFZIDEjOtcxJXwNVfBSffWN8O/qs7gfwS gREauqgmhj4KubhZz+/jsEgSQU39A3dnSm7dj9v2+DeThQBLb8glSLMSyZ2+p7t4TtTAXxKmV2VK rAVuSjrcccVeLyXPRsTAvz37BokuXnFzQEp6+s44wHQTjg4vb8jUkeuXPfpeLw8MovAQbcsKjIDl I8A+2XSyyR7IPf5YjQQQV5gylQjEPHDZWDh/tNBtoLMIWJu9puyJNpE/NlWck3Ut6Xriv8NJGlDe aRFEHF+Ccu0ImwpVlWGuZvoSHOVxfj3s3D5GGEJdCSwnBu8kBJThtsPl5iSDX7ktRAw5JxmP7dYk yYc2fZAFt3l7Hhflw6zcko51T64FJSOIWrDpOmT2t23LH4aG9/hlpznA0TjOKdnrLmXsaGETk8jG 2I2I0XBcS8xnbv7nFo0ZK6XZhs0OdCGLycTMJMoBtDddIAiAC2GRWuWwweyluZd4nh0gZYVS8/3H WQEWVS7dGL3RLcFUOtPl+5zUI/S5KgoRXcU0o69OngxlYLE+4mq1m7MWDb95iIH/vCw1Y6xBs1TW Pyc/587tngNSkmnRgA2/xMSCFbxQOxUCZM95PWjhSXJZHVFmQLWxO5RMSaZUeWEQyaR/MVDTjYfE LZ3jBiKzAL92xZ93yA339O2bXutQ6RT4PRky6DeDpJY3hObvWcmJSNcDsNdqpdZyzscFGmaB/7tq +TsEMdE9i8djkS0529E1eLA6tBJHGbMQskdbV+Tx6SP/7cgTte54DLz8P0DU00PU2wq/mc2D3gFT bYhnNbYPHlBabum5rFFqwNcv1UJN0NhL5QeeNcWY4CPa+XzSyd7G0OHYDu3YzP2mNGKey9XV56gJ xQ== `protect end_protected

gpl-2.0

4deaef450035bfe6bf078dd0c0eb77dd

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/xfft_v9_0/hdl/xfft_v9_0_comp.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block T6Z81atZH3WOqOveobw9RUtN4ULZSy0HAGM8SJ0+HLGbeAMolR7H7nRLtF/3AsEdpScViF0V0tAL a/lQ5Q56yw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YWTHOmTXluqu+6gq57xCRFQDCdYESIz7jwy8Rr1ndOiPI1ZZCLSqhJEOkdVQMzpSGqyyeP7Ardpn um6Nq/iDuj1MXS1d8QK+zEFgtoGC/ZYamA7BEChVc46GBvUviBbbrev/QBThtAa4I65uhE1TbGcN J18kgBNFWj008rxiQFo= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block CK5VKpuO3UF908NAO4YuG1XlcRGp0Pa//RY/LK5JCtHnKK88GVVE92ltsJpMlxA5Zm7C6BifCuPC 559cApHV+/gIVq7yapyuLcQsKHAiMMzDkwJ02iJ5u3+vhGbOWsuJ4BK0Rwq+eHgDgy08Iqf+WHRQ 3Ba91wTWiQd2Nj+OT2XplSZmxQPhq4h1hMJpKPrG3wjf7TQnW6r3Ga7Mw+FbJaUEcpPH5o5P/w9i tG4tIw3IpIh9l/Nh/Cfqv0JcM3i1onMs6IOfi2zYl+LWjYokNsdANBBaoMtWzwsbS+vBQNxcPX8s K6Qsh4r+I6HyJxI7nyq52SxNxvGgwX8Hxr73aw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XuQ/4dETtH+4rsRzF0yRD9HvKSU6bqQQ1D/Nfl1bQaSXm2GUdN2pxdPVE8uyvBKo16EfRfJsVsGl t8NcsxgQostXUXkTH+9ETsNBiKDoYXrc4X4Qk+NYKlqO/m8W2X7K8bQI/D6dS86/0T54mwkvDrmX Im1A7ZObJrD9osHZBGc= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KZqse6mPp9o8OtxodqoeMvTtl5sNhSMWkvHVxNDd0UgM8HhLnn7+k9Y5Ye4axL9mO5Mio/DeXEST uVdIP9v1ee0De8cfU0ET9cl1hom4MQP6cgSimpcz8aevwdgHRBHjTgitDOZISjymnHHuiF5j6fuE 6Rd1hBQjpNF1ealdItY6yh4XFWW1pXQm1ltPOhXNtlXzlHHarJ0xep9Z7abRy9bvjJO16zB9ubRo xsjHrKxk24RXy/XooERkFM/w7pyJ5zlQohxIYb7dMlFu6Y2Bu1QY3PkvTG3Dc7Cm+Qisw1HH+Y60 iaNA5972vmkEu867xpWzwwAR78CTjg+fVEFgtQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9952) `protect data_block gDqRrPN+RoIGqlVZLqEDfK18nozFrNBBJZYSqeZxYhCLVdnd6LuDIsu9gd6rpWFzZKFI3BcKHusn kZaMAEsHTVCPSu0YKDFqZ22BjpfZPoLFjKzYzkRrKAP9LerlGubAUy5OvXMOaGGyXNj/HYA+FeDn L/g3QHQNn4II//TwMCj88grI6+Yn1k3Mt6yIRoTvVq7h/fBhLjvpj8EkPRyK4vSJDAyir08OwmhO MIg2BQ/EpKOp4JV+N4xPw5YbcNuyfjjrNBG2PR9QzE4Kux4kHnO74tFy43FoFw/yupMFhv7D2V1F TED0EX8vUOVTedQfN5uQPLP2GJaRJmMdwVazHu+G57eNgPvUGVgqTX8tSu3lA5NMZUb/w51OTvH1 EcEUgPbqma5Fpmu5zXjuFCKxkZWXUACf8BzH1mgTkYv0sd6sEnRLolYknzsMvZ3Xs5b1kKrTlpCT 2oVBI0ewLS003UbZ3lXEzu2EbRjvsFk6o4z458HaX0Q2dpCXQLLamDHfS3RXy76FcfFu+9wOPeLd Bgra1UWrTnE58vR6EeWdrmtkiV0zjJ1mn60qgrO3PjTQCwfr68X9azPws2twifK8U/c4kHKY2Gv9 KPSB2cpkFly7M2j2Sbq9rp26xIJklaYbUWV3aCmdmi8N1RmYJNEJApi+fJGAVG9uKoOQxfQNDhgJ HSFIiIujII5QubHBTOWgnXhw9lB0kOvfC1RhO6VaxJJfDUUb8kA3tkTbMEtyFMf9XxVvdnCJZ/XX BRj2JNVSW9aObDhe7sCDpMu+9lBvplQsctZiDdXGD1ZSOgJ2Ig0HNp94wPUeKbKTyCijBOQsZywF 4eb1+Jsyp5igqP7S0JxSfOyvcPnD8Weyq0jkV4+B4mER0BWzRAOotK545Y97YChMmxCotyT47AsZ XmTQv6W4QEGshscVpgLvyye/isgcyPbNzuvA2nWzXKg0Kzb8KdRbAKfDRnwEeaXzVvtwRbPXwdlR uhccPrbWpigxhalNeJ5W+NuiBrqPxhauLkVQB8qZI/AzYsF9Ryirjl/ZPzF4ub9cuwJNCW/pitCA xv9au1dTZSlAUF0KcDmF694hj+21OBJqf35OUzhtLFPm7hdqK8v+Kictwu1It861EZMWK35RBF6P RNkM8z+Y365C+YxaQjNuJyLPyCDMq8vtDCd/WFYRP186ezNXE8CxEDpd9vHEncODK04Yp4oeUEVz yx8iEEQdXRCu92SzYvWFmeEqZI/CqmlA++BNg4/xbi5LgIbe8z8M81Ba9e7D4TtAzc6jFefrPi6o vgM9lv8+L4zy0Cm6/DOHBra0zfr7YSqzhyhyzO4tRcEZ+6op1RkSchrUV++uDuGceq/xpRk15+gh FNPLTQQkBB17kGIrTCqj5zD3GDryj4zIfIrQpgGvDoCR+RrA84Qbu/WEai4kaMZO9lRNSaVjKmgn LXLoWcYV3Riyxzw/1tvKaF9My7j3x4FrRqm6UxStiEQMOulNM7akOqKNo2+o+F+yFH3iKMovjJwK 8/18H5VNbVmEPIHm2ARSJUe6huA+ygqUumRlI0sAcdo5eMGiXCqnUvnLpWR6hPdW3FZBQ09J3gvl BAgD4EeQA6uMIwadHGvKaK2+Zk/WjLk6bSTvcqksC2+XImhjNSVHEtvpT+mPatwFRGbWctdUDvHw hhPyCTZ/Kixv3N0ssXpKqSmwlgsGtPBpKrzOX7+I1gQQ1e9wwaAPUz5/n7Lm47hi7/npsQy8mpS0 S8onZX/OB+NAlQuEsWh0WaU7XUQgEv6gkZKKgMcdgW0zniCnWFMMIcAf+eiqcxZAJ4llT0LU2+Uk gqmF1dPW7N91OMjckjwm9QFTqpa/wwUxWDPymU7XG26NAV5r1RrgSA2vot22FM6bmcsLAqPRXxQJ iTuvv3QMDw5Kmh0hqxrICsbINbbt1/vjz/MiGcvbpToMRg2ps2TOJjUttqx3UGrYwRuHeFXO3f9A lGnSpEjH1WS7M1Es/cGDfoHP0UAsdG4gmABJaV58r7BWisc2ypHVMKdKv9Qfpa3+bP4OyFd0R70O wrLqsyaX85SNcQ4u13hoGuTseW6nXIYCzg6kjU3pvq3UB0yezP/CdsIG9mFz+7a8Wze6+s9FZOdV kKLebo3vsgws3PRGVChMEhmpZvx95RE4Tg0rHr4968RlAWBK9cqpoum+o3smtyKt/WhCm/XtPYCO 1Yj/G7ibQ5+QESjzgLN6Se2OwR8WhEl+8HQJiEMayZ9xDh4CWXiNf0LMrkYR3oHf/p5CJ1dPl8vc /ihl/zJ1K+usw7OU3RGjXXhjR+hI2nvVfC15GuY2ToDmOAC2xzI1cUyGWQnQonWPKwRPwwLUy4nq MG3avWMBK4SR+mq7VXXA9DCfRFpPaElyKYac1CUORiwCc9kmv01xb+GXIL8vsQl4jdAsn8jCaHHT 2aN9X8UiNWzrnR8pc0fbI8dO4uivQUDpiAmjXPCgBBc13F537IAMyqtwM+39gGA/N7LpIUGFLAQZ krn4qpcCihNuxZDf6z3LTtSbDRWhcmBFYDTQ9UQfXzk6QI6JswjlsCkfq1Lr8Bqs0t1e0jh/mXdc 2aXUGvhyvzPqcFu6PNPrSqnc2l8yeAA1Y09Pua+J3Hynt5VMJkVMWsfYVG/+SwCBetMmvnaiQYsx ybSL5bnWX84V2hqvqpxL34nuDa0qdukkqAIuZDDnVrsZRS4u0kr7WWaaoTZgM8phgc4w3p7D6GId xnZq1RS5N7zeo8Cd124DTm2g+R58iUHgOO4a4DqSHrOAHqEXfBaIeSGykUMQVK/Cv3blSQbGWR7A AzgVhpTzBrHRf8lPFs5EQXVUKcqOhILOnBwLyaDWhOOz9R6Y4xk8n+ru2EBUHTTbkJ5z0WVtfBLH zc5+t4Gyjeybns8q7msr0zhLvEhp1ZXuQtpPkeYVK8ipdChT2FiXJnhvOvLC8NW2dm4HgzL74zbZ LvfdMbGS+QqXNxuBO85M0pBWxwXLkbhAg0bxwkVESYVG3IQYSbcdN/heRCyo3DGiGqxkW+jK59NC KpFevB/+fqibnfBoBC4Mo3fGannYwu5fQKEI1pKOkJjvpco7jrd5Q/Ch+13jsdu8Iii9B48csWwl 9+3sj4Aiba4uCA8MPtIBLCl8aaQy9gFeZI3GtPHbiEyRnVLvyQ1f+fqzgNqkDK3xOyzzKAI6+cTx mYd1uipFLY6puXNDY9xTM13daw6VNMp+baugEd4eNlWaaaKZGK/Pl2tcG+ZYviLElX6Mx4lsxoSs TxDd2XlD4WhyENV/ZAf0ehBzs5UQ9urBfXMzEsl7s8MsrZOLAiIAihlwILFIWqX/Vub9lf/gNWHY 8WLK3RidHz62OsnfjU88BpZbOIF4hBjxVAVRX1zxV1Hoqa3W1+5E0L2rFswpstRHTHCo47BkSWaP nu+zddj7fGynyVekJcw656CBQJGDwDK85ez7aj3lMGUE/eFbFSkoUfjNhIVw4PlBEMgtDbd7BAMf a/Z1QMawMpPACW8PbXLo0hJKOtRUj/ken48GRzDqGWDdvjLsYVEjcdjkDavFPs5AT8+WHu6Lk1Vb n/1JgOudThZreShYu5pNXG0xAW2rc580Oak7z0mFlQQLuTYfF7gaFXJkVBEefNq0Tz9+YvenqdD9 AtbP9ikdWi4T0oDqDgBpIZr3uqzZpfXglmgnNgDsh42pjwg5FmdT82kXpeXo2GMySffCupMG4A1w QoyOgn8DxefkoRsTye81Es7GypazgK+BR2Nhs5y1VM8pXehMCE8JGrMOWyDw/L/J2SMNC7JrObwG Ts2u+n3+E7X4J7t2J80m/YmE1y0IcnHby3eedCAI5hyrCRd9q0lrSE5TpN3jvpW/Q99Wc4l9xv0b h9KrfBPbET7Hk7oXR9T1GNC1MYTAhni+htX73G14amp/BYIWaj7ngjpBxgTNltYFVVV5v2CSvTkd vtZ+qQItwwco4jjmGDtfhwX0L1ge2+qUK/GAP6NaqkJxZ/NwYVbov/m4WrcshWSltEnOys5hJ34g rbNFwduRSTDb0UNlvjIAFkG9kqgkUE3c5P+0TSU/cCP3faFnv7AsaCzPzRgzrTZXne/KtW0a2glQ ruKPtZqsdOtCAINAOP1aBcUiVjqPuI7mOxdX7s92g+xd/YU4NMgHdZCDDoKYMsoMlh4iETlLY3hd 3ppqP0fKvR3YDsiRXQRFf9TTU/WmhgwrmBcDFyWRRAFACPW/OpLAE5OuuxuxFBgKNcwK6U9I8wDB elv2wfcH8TndB3/C+s8apJhe4YWbJCaj+zbrl0bpfMx8CrK9s67a9Oo3MoB8fViYw9N5Kl4Pk4+r 9gql4vK2BiVg2mnYWt/a3yHIjZx7BcpBA4cyy2NgNHtWjxVslCpXI4x2Hb51bhC1uiSeycGwT31i j9lf8NRmBkGUJxp/GwXPcQHbWEHjQf3AcaiuEVo4jEAJhHzTwiIkIgdqFQEmdgGlU+1KjdSA2Xgz VinxlVVM1DxsqJhefBI7GPejqfnMwQKRxdmCgb+eozGK9mxsJe2dLIAxRuJ23UXHwre1wx4xFZwc spK8lwZVG/FaZ2MJZFDmUr+9HM8siddfe9IW5Ba/DyFTuhkMddbu3tRw7kEFsE1YA1MvdCXZQXwC pjwZMJLFjAf6keJ7IjOh9SN2zjGnWxEvUkzDMLf2CNaZDWkXlF6JuQOOKiyCf2c+wEcEXxQKy1uk 2jNq/xZCYHgL2OGMdopb7sswaPDjR3Jqn5T50PnnCyD19lf1sGfrE5kaU3AFwh8p14YVYLJxmj32 owp0vZNZ+FYkQi7q7DpjpMJiWZp+fvC8eXp0zbZ1UVsxo6PWbxXR3jFtUacqoM1P3goiO5RGB6eA g/u8uIKXusAx4AIiorm2So6mO3hdBA0dF9/f+1gm/Hj3XeYKZZAoHKCyTbf6Vwtgnj4JJNJ5/mQr +syEYmO+/+RYvYVbzbWXilj6jij1tdvS2nWZW5G9yhpfOlXSrX1NX7AqyqwJpYv9YCcQRvF9C7oe aB0YXnAsalSY4VwhIT8CRm7I5aI7ggsGQxgoowWabgn9/otdeZBt2kX64q7LbKQWXWX5vci7KlNV 2SO6sxmXy4Y6SntOmWmPc9xOfQL5gx61JX4oM/D4uFgkiSeltUhFazdEzzX+NcKlzeyJQK73Ks2O 23thlBjbiK1NI15vlLfCIbhBU3orI1a7ZuDqNhVC42tv5DI3eWbI40ogoL2PfJOZL9tGVYvbGhFX KbjuYdWadkw3jOoil6qL6nYdKXHvVcXiA4CSIHTHGPLs5+VC4zhcTKMS4oUEXJoYXLxf2au3KvKg XwK/gYVB9KL4NL7udaijP8aQ+19Dm9IfSZWkIuckqRuSmVCffrmP5csfFUxryJ5NKEWBnauVq4ot bF9ztQ73d+JUC3N9Bpy5bxmIZH6V3pf8mRTWBQqeKIGw9CVBTS+bOKXurilsPB9P7MULOuvAAiM3 F0qOQ8Rh/SYsi6YV/hliXRAw3Qrb4Qo8CBc9iYVKuCt+F+e8XoGYVN836e6g/fC1UZ8HGsPyREyF BS3JBRMKx/5jmZjL/aXsa+YcOzy1qCbGmbvZQ4MwqhdDHIte+WVPzXVjnj3n//e3u1QIHzb3Zzp5 i0DnJX6eVdKhmEnQqkjx8l+1ZHBkxJ62gbGO6nnugLMPzFLgF5Gh/8Ldb2dXfe2XmkHoeDe/gDBo yLmFRSxYzXYrqSB71M+NbW4mq54ZvF7c7sMgS17F64gStXSgX9b09ObynZKdZ4MwoxePWVKnHgAx oPZVxjssJpJSDU5iKJHl2GBrQey1hbwxuHvmV5UtUIKwC+gAdE9wEMZO0ibeuK/IqBbWVHVLu3cj +phnGaW8WIuv6qCB4ldgV2hxA3VIw8vQdN4W6bzTLpoRYxSPcqutT6GjFR/bAZvxE6bqwFu64MUx 2sWf8FkiZ+IbCpkitM/lXPX8VsNNV/O4YlXOKxtMM85AQEErvgyr8BA0QTkdEmhwOZwDkD+fp2t7 BYZro5dnZ7CY0albMX9WPhjYeTOCk0GtAqtPtzC7f2p/CwGmoOW9SNMQMItPmseDqyWeJbkXP9Wu j6Xyv8Nbfic5ej7fk4xiiqIh33r1Rdo9R+gL/YwCra9xQqm2ndxp6XM60d+5K+uf5lE6CObuweVv kLQC8rd22wJCYZclhwPLD5SZONzspSxNntdzKbTgzaZT8Jb9W1iNcNHXCyYlo/si/lxEqJ6YhF/S mCFDiKPh+GUEl8XRvK0egEKSjsGJGXOwVxO8LdJCD+2yKrvAYnkfFLawdQP4TsJjdPC0YI+eqPng Dd8WoItWrOl9+8+jkg4BsFWf0qEYhvP1F9zpFrnrm77xlINXlQoN4NGQfG+MjSPkFSneDQ0veuXC vBl4s7B8ZpA3aijBWZ/gR0+l1KE87H5sqNI5hgHgxTGG+G27J+xFfY28FyneGfHWAvqa488UIcPZ KlFjyGGCvjZyJjgIZXbaCUYInJFK20J0QTG9uE+4varVw7PW0xly08Rr8ri/Lzc3JR/yBx9OD33h p03r3/D206ml7sxwj/OFIGH0zhT2OYMhNISl1hfpNThXKTUFY+7nOlkfsEGn8Fo5YCQq9cjiUoms +oAZFwsISR5vEfqdTnad07yW+zpEydBWXFqrW2V4urmkjUstldvtHB/uJ7u/SjIqWP2sn2XePcK6 z7l949vLX7R1dRi7YEcfyCApG1p0Zw2P1GNVBAw0g8BjnyOYNMchCtNavuQWuQcxUJElHUs6uoc6 7kBaHv3BT8c0ev4kW+x6eIdgcVof+BPrnKcvM5OkwCuE4XUHlkSWuNx8k24aQGr5FeebZFkLRGC1 6FubrNJZzXghuYE8H4EQLAC9zhqh0grUBlCPCcEFL9z7YNMYzmoU0RV5Vgo9sTg+88noTW5MUXM9 998yNmDlGiKKB+i/aeuGtITSCWNMkyk9qXGItdGnVlw1alr56LFsccSVzAXgv7MGehw5hn5/CGwF fmixuiVVIzW4WodgfoQeMaygaK3XYs6y9OGYXM4xLPUUx7JUI7BEei+nUBF7ZhQCXlYJDf8ajfLX Ui1jre4eZ1gcckZ0Kmi9Qs8z0yBSipskjTy7UwGkIpszv5Qtc62Gc+P+GWxlRLB5B89HsrphwqAW 5Y63qbtuIasfm8f8mSdl+VFzANKFbD39IkQBFAciTjwVsps3zLG34dE5U+MKD7ZQZG0BsVgPxVS+ THmTFTFWlOjD16zLg+aYfXCmHcdr3fIZCHRPc1xOR29WoRHVyrhWMv+iz+VNaChINLnuyThLykLR BC4eBQ2C3UfrcZd8GmiCf0r6QtBR/EEmJBlByhrJKC+Onu/d8ZB1wA5B2H0I+G6wF7JEmjmO+QNT DlLY+80VgkMlnX+tK7nrEn1jgorlhJcphA1N51Jf0UB6ar3SmkH5kCBmZ3cUUS8dhmDPYfKFwwJp /Bnaia+eYoN2LaA2OhD4/Adsj5pL4eAWyqB0svYG7ALBJ9fvT0tJYdF6TUiicvF2bOavk+Rka98V 76VWq+p9ztiJwSeTuRpNJOm3OWllnDld/2rI1QflssiJAyyQ5RUPvcQEydtqxQcV2Iohfco41Or5 el70lkf56NyZRMPiAMTB9lR3Zphc/AI8JmhM1qdZ3eLuPF06kLchxFTpY3tRxePwMygPgSy7IFG0 FiZq7LBuIzCAukeDWKsfNZjI0X0kR9LbAaXEbveSQFHaLcDqirQC86gDu8jDBZnhjs7o8GQYgIk7 sIuAjcRBkUbHhGxAKNNTxImWhQFOx5Y1mUyrvzTSNwWU75UcGf8uZfdDZRI4DaFCnTpR0U8w0MiI X5KWMFCYlJcqOQGxZNZrC1Kdc3B8pAtdjt3dqzS7GZxmNC3chlLfmB0/MDsZSMvhglF0FjW80Ra4 e0FZIsdMVR34FIIqVIiqeAyXvmh6TWR01dm19i1SGIeh9svCEDq25cFpbJTWk5JnFeQmxSdIMImK 9bigZx3WAs9Y6zADSxF0khKG/aofFA58v5PbCuNgqBTamGtKGBVGJ8ofNxBoAKh33owr4SBLyDkB kt5c55wsa30XvQmjQRkAFznRB7eFs0XiaNCNW5azCF5DXYysykxSwrMN1s+Ltwv3y1q36P7Su0We 6Gw9FGyLXkDSM60v9ek2fEXRGvBs3ocW/q2wbQ8GRAQriPJy7UtRwKIQR+6JA0Cn8+M+cRkH/OVH VdRA+xnFp4bbVWQatkewKXRgjiUrWDiGbFeMgDodbHtVVOIvYSMf4jMgEkVNlI1KDJ4UX7ijUFBM fY+cBzN1xwZ//xJE51cOgLKZ7auKa6NjYiWEOhXo+xUnyxmHOVNso2f6flKqH3W8lvra6/Lh3KSM OpG579DVaEVKSRdpZcS99SBlQUW1GC2aO03qaxT8a3yLlgJrmSDnDnZf6uk2yQmDSy65UzGhC6re Gq29Ytlbn5VDaGJxLB8jX3lrFu0gAFkISATRnb9netlPVYBHrkGOpL1S4cm6OtV78IShFAKh6DmR lbM6QIJuTY4XUAhyYbPU+iSBwybPoOo5t1GdAwsWwUEakeGblvNyN6spdP7jTmq+/NxGDZIawzYK HAZi1tlAsykOAdpYWA60xdPzEhTyL5HngZtAcpCcFpPpS/2fRIIR5EoYoAJ1VqtPitnOT4KvjoD1 ToFkNkhoA/Fs29RTSfDE1kqSUFdpZaLjPBumjgVhYSAt8suPp42RYp8MKAW8UgrYIWtXIUz45JwI vQBD8zIle2/eHHJa6DQhtkZ9SwgzEKvYkBIJ2y69prRcxhWyXs+1eN2hx3hJRaygWtPpYRIb+ws9 QGE2KRbO5WM17yn/jrpJVlpBIzRRWy5vOOwZ5ARcwyLdwtcqfVzCUjGsh/Vx6n5MHYsKLuvqEmDd BmJ0egZwW0VFugDyyHt3/ACOXahhB7nhGgsHtSGTiEwOEaE5b/PQ9VI4D1kgUdUn2zoAvF2YEsKA tKy1RZ/Mr+HSGGFAQnGV/JayBLzPmOLe05xhC5wrTT5knBddYG+kpid7Mpk51F/FO1sizx49i6hB C89L2phf3pBZphmHHfgChQHEviUGWlIC4ApE1w1+gab2Y6gmPTdYGsL8VrXPjMAoAWix4rvZZr5U bfUy3nmiIRU/RfxTOj70qjf7pCeRL9s+CYRbOQXHT2QPKnMbeg5yVTYEQIXzu2sONGislY8zAGR8 n7umLnHr4Jt3TjecxNr5f7D2TT0+3a7Fo2aLK115uiTolcxnb/4kDK2VezIBCiEVZqHdXled1umr 4Q/ctQ1x/V8LQI9Ucc/f4MtC8QkhRyQbvz/Wv+qz61mEUQULuZPhqaNEoog72gxyFDCw29USsec8 c9TUI9P8/AAYMGAA++KIVN56PxCq30gpKNbzjSHNMwDguw3hjR2C0G8e45oaluZXoYusM8X8Pd5E kIw7we/vgKIzVBzxfc4ZsW4c9yIG52Nfa5iOpLYgSy2ravo8cybtBzMmSBW1oF24/yqQK5oEHYV9 6B8DiiXA04nJN9R1/6IZG4g8FKsyh9/2aU3POsVlY7dmfgnFa6JMb1GWmtKUFg9IGZvcQmkFGGIP 7h/I8znEzRIP+lKwFA7rJG4rb5iab69Snow+8XAtJOoQWbVz9mRzj44lW8fJgQ9g+1X+ty18bQv8 sxldpkq7/+zXelAQYyi99EjICwWl4sH7+ZV2buMjYJXdFNvf/sKJ9IvFBsqrzn10tU33M7Vtvnfi I9vT71SMdBJXiYIu70mOLpbDGY7+at+LoZD8SBWJJsPahFM5zaTCu0len8CEM3JQxNxIo5V5LZNw tOgs8lCw00/JXM8LneNPINBiSUEP9HqYm8JL6RFfICpqjMDFcqWEQDwxeTmVVX0ElH/+hgjJcYy3 TTqDvPi61we7podP34yqbSPGSBxTvHedsWghux4Mj+gUqLUCqrNYp2/tNgQjtUvOrkMbGruJLxxa ZsfT90qtQ5y11gS98aKLH0pRrD2ypT/2O9prUQjseRSScv11preQ1JqehUo241gyRWSTXqRp2z+F VH0zMoiUE+bD8s/0otMXjVmQC3jXjoakNvhYEXRH8LndRGz5Hq7kgmxUgpTPstsccaAa44vOv5D8 tynNhxqRYf59u8ILmM0+lOkUCc+z5NGU8jJVfgJ77PYEAv7e/xtp8C1F+7y9/pyLkhK/yqfp1J9j IXc0IP0ytQY3Bx2tzCNNM8b+2R8q/gc9ZpWGk3W5XaecoM2LdpBwz1GebIPPEz3vjxrUGqrakEVi enWPLBPn3dzBYSqpNo9cMs4mEltfWgeQVzhQOYOAwta+/zjzcelY3WvvXxKJ0wIffMOucKgGEJQT Cn+Q2JPnefWlnGzqGj1LIsg9mJZJBk2deV1G06yO0EKUcvsXaW6zyxmFZ6uHvQvw51SJFtcAhrGs UI3ROV2/dTldrq4f9j0CUx/dFQ17Pt9nOtEat3X5AWDsXtawSgrNUlYxL5hcvUXhZGRP7uazEDbg USbEFaazgfShF+sGaFYsadBt+zb0gKTzruQ5xA0lzKV7065XbYXRbrYjPp5OOEE1ff6HFh4v2sn1 8sRUx6Hj5QpRXpxdtmJk6lnpah6bORNOzsoyoBPgDPF6LtgUBm4go77K9iSWB8D9uGGjSwEd+FC+ HPUXSJSribHnIryDlWB6eHqjeMLuITgHcz8nZJIflTDVtepxl0YbLfMwAF+AhNytjc8pKulW67Um 3VsaVCW3q4y7oWUXVtnoX+SYPW8ZN6la26mQqwwgUr+ToHTfWm/xSvxORt9WFMVfwhO+SUPAkodD 4ZTk3ahttBj+i7hMKaZhe7BVwMFG6ADM5gY/9E77N8pYkOPoRqZzzBcjJJbtvpEXZQ71rCjeaYqB E86Cy6x85okouc7V6s072kr5ovtnsTH/+tEYRxDaZiIsOTNs0WPq8/zNiFgiDRvr9gUYDWuIfJwH XBb3HWGGPqEEJwSxVIzqdd0p4TZNjsvLmGkZWZCyZ4nFL6i00LTg8B8A2XnZmuWUZIMUJ5qsoxZE xy0X3yBVe0SXqZEfUFjinJVDBdCbhYDbRerMGfGl0bvWJ/MeAH1yguRCkz748OQbzsKA2WyVxWnG gLp3b/Daq4bauzJli6kxlmAwEhVWQ3reYoUq8zwD5JT7Xv6/LyGK2pFkm/U7wMhJ8kq3CgGuJV62 4Daf7oNbudUmmsWec1CJa8OdjeyzberYZlXBKGxUDBKHzV9K6i/ox4P68L+B2X/I6FgQLhgWrJA/ 2uN+2cR4YMWz2y5XhdicXHV9dZDI7rsxZsUPFwu4rNwFqhtOOyaaLj4CNuivxvFBVDp482//ftpi mt415BOt32jNZQo83j8rfss7EEvVEWz6FdbpXVgZHINN10avu0f4h4xqOzaIi4Ap77FuJ9KXrrac w/8OE55SnZPpvRhH8kU2IOufj3pT+tpZanm2MHohtoRviYJV9qSCdvBmURjmm5vIU4jKbvvcKWGH 1c01B2PukMKJ04MNXd28knkiKeh/yq61Ehfo1r94vzkQEG9sTdCA/VwJwI3+GVaKkeifwhPoMjUM FtHzPP5Zs3UJX3EiFoOeyAdkZcJH1OlzsimymZTD2vL8FPNT+KL9D0NKKwiyeE8pCU/YZVAmz2Ou hjM9cRSkNT5mW3EtmJhwm1nz+QsH9v2EN6eWlUmZWN1cZodnlHJBtGgEkfVcHh0NJVz4fNnz2rs+ p8cI8+3hFly4dUrqhMxQNwLd4UvJWkQ6ao4rMpF1mYCU/FfgJetOZXJuemQ5u47jWyKVhaV7yA8Y 8BxBCG7FA3CIowjaoY9I4zVsBTiU4a7OWnNqcUYsCEcye8CEto8R0/8gJPdTkqS84s4rG4NHEnpL vmhBU+5lzQlOeTrpyjg/xreqQYXFZ3wMU1twJnwRz5zPwzAqA5vx0j6O4/en3Vbnb+b7fF3ew1pp QhQYRlFf+1f0wYlSFFkXkTfGQC4/ok7umvBdT4xXmX2AuFYA/MflpQ5ZMYYdno1lUqGf1O81B01X NK0Uqdk2ZqXRDlHwUXErRTL/lDuP8VmtzDr+VYRC/00tGzBSLYKkTrW5RomyyoMS7Li/qOVgaa5c zdURwH6Lbed9yetwxxwqTGWQIrhNm6/CYwx/XbiiRaElm9JolJdIUUyapkur14AOBWXGmC8uM7wZ waxEvBmp7evIwwKTBmPGM6C2rSBaHcGa8CI/+mVsY2OXr8d+5zPDMpBiSxpSqsNfUYAhc1FN1rjP WVSYQGWrPmBsSD7bbLW3Iw8frB5K1NaqfXX3GvhnnCiJePq1xnUZWTRJf66lXstayGNyse5CwpLe a7PIws8g+Vgei10Lyb2mVSGfaMCbg44u1fVuFyfxc2Y8iB61iVvFugFIY01Y9G/CFVeD/5DBcPy9 zJDsUOur5XrwQaA/6rD1mr1E6TPqItWB2aMGqMR2Ery/CSZb8+yINarToimYSbEd+CqEvMMtw45h gbZY9qot8KudmLmF+O9C1hRgfEnz+Zq43WQH1PtROHdPtF4gSrwZ0QY8J1ni9ARC+nYQ84AgNnft UyrqS1njAqB7HoS7T6tAE7tidPClWWZQq/M9cbizUQ+opjyErL0mApfR0JELUsciWA2mjVCSh4aB iWxXi0BtdxEPtvdYNEB1zRYp2/cxRhUguuDc0L96rgRQGXfe/Tv4QOd2BkKpSUTdm6yY4X3ubuQS nye5xv5RV0QXfKfelovoPdccZkxLsd2P+qfG+F1XX0ub7oJlW2+GDNLajNuIq7SByHlmp65B3Ru7 x7voZaPQDJNG/6P2iSV1I8PinPmvRcOTCVSRfzwowB6lMV1e9Xi9PeHdUQRtQecZljTEZbEqOw2W 9hdoLxjBS919PCcSig8ItRhEcDUgsr3qimBla/atDAF4YStM434zbTSW9BwlFG0MBE9vqw71hyga u/WBbEPqJj00gDZBPnOCPK3YV+FYyH16Wvub65qJJEl9X/Hf8lU7VAshOoTwX7emQljCaGyD8Otg j1ojMCMdOxb7XA+bd8pj0asdOZXvnUGzNtneK2MMXSKUrZeMhZK9xlXl4KyoxfbcbZCBWXTUqF6b b0guYVDPKypCxF1gfOExne89caMA1K12n0cDiHq/BTK0f3FLKjOo+92FMEEh3BMHsX/Jbq/oTr1W 4kQnobc8SEKVxoTtTs49XwPSI7I/Xbp94GW2bZPpA072it3K6mqOwh2R/HTdK2yafPGbOLS9haTB 8PaOWiQ6EwR42BCHBPAL8quGAl2XqashsLvngJSK/PqoBA== `protect end_protected

gpl-2.0

5fed4a84f0e75d28dc3cd30ccb62554a

keith-epidev/VHDL-lib

top/stereo_radio/ip/fir_lp_54kHz/fir_compiler_v7_1/hdl/sp_mem.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gIzoTEV0U7zygZh9b+wio9pwtaUzgpY+yR65xakKuXfq/RtWNIQqwkRTF57pMloMrzQDjt7EeWEm 5DaOvHyeJQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hCQ0Y2qdLtGU6UtZ7SicbUgIalOoYNqa0SGOMuWmBh7iJO6NNcWaXCVf3x/poIEV2RBvym2+Ii4+ Mahjm+/BMy1R8dRB5k/DL51qx4+YrYZzmw7zZYHGzNxIi0oT6hWExRHbY2nJUVxgU7nJmaxzuMo/ BZXuOlGx+Gohe4aAjNw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block f1ODsCLrdVCOpgR1ggOTaFdLYqPkPgw6SRbbUk3v/TiqHBvRrGKxUlAJCO6m4az/MfT+hBQTuijx z24pJAL31/wLPoRW05/xqDfUQvF8sFmwOwmz/MBAeGMkuyhHX8WjP/6gbr/teoHeUY0DvKw6CqBh QaPMdna8V0GAvsCc7F4ZMvUJ+BwtGlYvquogfc1acR8IjXHyyniI3ditG1YULZEAhNwJYfjkdJEp tRUIUINtgdD0vhg6V9Mq8SZPPtabDhHxZjRDIofzFRDJnEIjoXFrxhjkkeEsbN8wa5JBgqZ/656x AnVJtY9KNEucq7Qn5uK4fOd4J8+uwjtghxxgsg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CgI+eAkg37u9TloWpSBCnlK20awWAdq9SiNs8AOxeijCDFWV53+ZPno4aGGBJCWRR24m/IDsJKXb AgvEreFwrm9L/GaUxb4ru/paRhGs2SKbJtFUVLYWCqvoeU31VN3/fgfiVbqMcq3kjOp65E1r0bj5 N5ls2hI9dspHKCyAVyM= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GuyEdshtUqnkjYdo/taO/UKZlu1EfZeIAvz8S5CVpGvvtQnGMB87+AlKLCEy5X9E2L8AYF6tUip7 brQSvs0SbRu4UbjDk6U91y2YM0skMxIfCdfHYVcObGQ8goZimeKFoq4Lszh7UfYgo674BnrcQQ7R uO24QkzMX37H6OG7mf1EWOttCZs3kTWrgZi0fr1qTYiJgdaJkRMQ81T7bJoGm4WtLW9OHgws0Bfg 0IflB/eBIan6Wfm7Z/54LqGT5N9bUetfW6Tzqc8kzlWR9oEQgtrzSFDzIhShkwRalNqXJWVZ5VD6 VtAuVLIznJUqSyZ5j25GfRHVMelqSpCQfLjtOQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13184) `protect data_block cx8C56/OwsypdD3yQYuoF48wXLkk6BjaPjuhqXqr445ElPQ81Bjh8MYBA0yZalqejgwZhHZrJgSw RBz7j+A6fgDgRbDU/0+fzg1qncdk/0vWixHJ/CCFvUwoetfJjiMntJ1iikqir56+6UhzqBY8xO1C TlaweP08mFkTxqapqbWItKznU3apegxWa2fb6EmYkVwzwU4iGYbE7RntJLXbSSwnY0X5kTjd1vaz C57neuz9bb9f2QH7hfVmLQ2aq5/Q8mrvDhrpZhCZK/2jlv04ON+Et/lcrIQFlckZb+PlZD/Yn+j6 hKciYXq+OAvcjNhDzvBe7l1Bw0bqZ3sfQSt8F5z0vXnuI5Q0yhwKMOwEFoq5PvuryDaEZ9dQYA8t /WEbeAYPrDbCPefMeQNZa2UD2UaXxf4ARzoxFMW94Ju95b7ULtiEPwvPVuDgjvyGbYyXtzmHdh+z KXDElBoluIcAc/borv2qYRgJG3yrbYqPITXErT+J+xbHQMDhKc6gM5CWp7ufHSaO/859BB9bVYxZ 41WohtDyol04geuDObxZjhr1jLzfpr03s/e8pe6l0Y67uWJuwy1visqQu2qH9+wV2u2wfmzPHfnX 9GR3RHSmdCuQlVqNNOUQ2EKKWgMJJ/IFZ6vZy/WGGIDHTHfCK4KRUswnCRbCJ207shpWqijnLJJ9 FVgDrJyEBedo57oeFO5R98dWXCSPgghv/hFdH98Vy0VyD7KT1Q8DdUu9S8kClkLFbW7ndxX766i2 rFHZMV8vxRq/MgJh+aoMWDb7rtdGT72M1eq1IJ8Wp1JWUiv8MRu42V/xv6MQFKAf12zJXBXUP0Xp nupuWdzVd39r8uzTikNGbl3gEtAwCBhrj8YEKRNatM6yuRqmMz7LRHkDAwukpzlF+5p1MqES08wn 7Fs9lEJHfw+/aMTKAgNtV69cZ3k+UUwJBBJV7a1yvy/xYa1LXU9iKeCzMD+eRgVKk2sS6m/P17GQ vdm7n3INAKMtWj48YqAKAnHhLHW00BEm8GCbJJzdbeqtaHzvLUevd0yahgd8x5jqt0DK1cILSEcv xGEwp2bfu5FBjN/gmXq/8NnhcvbuEQOfUVqByAguhsewDGr5p7tQk5vexfORce0hxr80JWtTvDu5 +4wWZ7zb8XQMNblSWevCWxM+czv5GxSDjYqEZWGjD0jc28hbwhjetiTV6mMOEF741pBQ4n476pry qZZ25BVcHyRXv9iXGc6IbKAcA0ioWQottUZmFB23/ieala74Tbb+MuE3Te6Ke1YwHSzj8QrhKPr4 YXFN16m2v22yFr+eb4fRKWqwNPV3nRl+HROODP0VY3DgOtq6RWGkYBY27l/f8xZHaGLgb+CJKTuW izWnB/VSuePCeKQ+NNfj/jBScwpIR7GrYIIEtJUv4IIaskEi6a4GpT68+/qubBsuUhBZt+P0odbc m8ljn9Hjou/6AzBfUxIoy9xlwVJnyfE5oBDhA0ibtL3YpgwABtkCs2/u0bZ0OA6MN+0zB+sA+E5+ YlumuQp4ERqpPomcp8RDM8knCLFPFtlJkyB22gFHP0QG88MHp5gzHzNk9N75vJRCFXft2qllu+r2 TaH8qyXbiQVQu+zaNLJhSpjw6ErUQnjevVsYPklZMqx4IVlAEOGk6J6glI0a+b7zYkF6uA85mGz+ bTDYKoq9+un6FRAr+DMZupvLtNiYe3bnqHqbSq6c2bCzYzxsfs+y6zZV+aPluGG7SW7SjSCj5H28 MJH6M/vZtGwrN3a5ysMEMQeTbWBSNlTY3FMuiNvXtHtXcHyT30v2GzhbHm109x/J/pN+uqgYx1Jo mLVCFCUrIlPYi67ymOQ0GICDWgaXiD4r2I5e4Fqhe1W9KS66MEaFI8YD/ImIoy9LSmWcimwQBX6R Iv0TqbZPBZQA6cxh6EGMGlhWEtrjaKLwnTzETx/J9Mv3UuhWdI8J1NnxHOJRZJFGWE+gc75AvRlQ JM5LzFUltGkzrxFk5KkeZopdWQsKlKRElxh2LUL6WaSVEHXCB4NP8w0dwN6ROavu60+zyvF/XjoT zbUCrSUN75WKDVykJVPkb2wkb094V+1RAvFZHYDLQfNptnHiGCnHo/cWjXhNQtTKPB3AaBjxU6N+ bW3MLBpgVgJqeTpUxnJVxXUowiJWdemteeb+kvO+4kC/vqNEX2w1byLHLvdlKhdEVtlePFxe7wNM DhILN1j1cugA8QGpFi6G0cb2vKyKt4jS45fico26SvebeRP1Tq5MLCY3kdd2lgrqzKcbBaCgP8lA 61nfed7zmc4dJe81n7mF1UnNm7hjMlFMPTevBiSYpnBSUMQTxbckFwg1ydIceQ/pkwmltBIpTe75 SB+iUeHJJ6fRzQRFgBgdVoAm3v0EpyoHckYa/+RMg2pVHTnYHIA6L7QERE4laArdqpfcoLtLegdS 4j6ikQblZxkMvA3rA5zg+OSM0/FQHF7AT2PPjSOrmcZ0fAcHu7sz7Bli8M19k/wuMi+Fgj/3Ms00 qZ/KSsdHaatCGq40BADmZDnXX9LI9qIh14GtHQyx7/3OLdeXBj3j241a1RDzFF9CFv0D+E403lgO fViuxKaGxDa2J5otP8vYGFxeCWmFoPGFrIMGi1bR97rN1s6kHKpZS/LVvT2UN366nYFmcDF3zhGv Hk0RSOmxwuXptKD9Uxy/zMdyPscva0WJpg0oJYKn8HmhURgC8dMNfLY4lb+BvrLQrNeFNz4kJnli lSciHPgPd0ISoSfAb6DyREgQlw0B+xChPU4NSzpoqI5ODD4DKXSM6E67/nQb0nREtD0RzztUVIM4 0sNavAnXQ/WQmuTgpy4YlxTKYR6Mn0XvoSaye4CO+nR+kSb4LrHAkTHhnz2nA2hs3EAEroRe6qwf MDxw4niYaWqXCdkdfG0OUMhRs5vmRvys2OWOwZn+v/8VBbWWGXbeBwDeEP4k86BTJSNkyWgArfGW ienneWg8FjrOb5pjXZAPcgp7yueWRX4N+CS6kfN9YyoipjKhVa0ZXJ7Sr4lo+hYJFMDEWda8Icu3 ZIw9imsPlMdBP4Y6lnL5NV45lWI5DbNN249pBsKifBtrkSaAEym1d8eBTFMbisiWS9Cslg7waNx4 wfgZfNBhrcOxR0KCgMCxhB7p9hJWrNFFCJu+uit5aWin1rrp+yh3Gu16yyqKCJpaw7hwNT/ag3dt ahMCIgr9ipFgnF0St9wpZNg31iQOwuQ+WSR69E+bqYWLGpEdtlbEpejzODpz84ANmxeALFenqUtF fUCS9dFfNI521ckDqjsVzOzPRDGCXMRZLK5nVSx2WRfOKzzObFfrhdk4AunvQXSDdSAi+Aa+S6ZE lWK1js2rwJOKkh4hxSDHXwtPuEiy0/7TP2Tuv1goneuknMbmh0ravizNlCIh1IcHPb3Ct1eIgK6E x+mjgjbnpR6dKb6uEy+0yMK1LJFdRBgu8AcyxJiaHAyRlnBqOMGqlM7pJ3V0wi6niwLZZL9hUS/e dRBfI8evZJautWBslaCxol25X5/tejw012e9W73u3+6M5ty6KB8JNxjj5XM55cm3W/mCcUI98Fld Gh7opC8UN6wPX4IVULy5lbWqCs1cfWNTjtjKLI0dTdLbSaPRhPpMESq4X6jxTWbBzISkYZFCL8NA 1ZT3iQ5k9ynjBCmUQ8wjcX61Oia0GUPmKL6FaIMFEY2Lg2moQb/O8rtGVUdQ3sS5LpGsZZ5zrbYA icNfkU2QYdZXki1YQooUtGnbnmwq1kwMoumKWMQJ3MgJwnh63BX9cAnLIepFBvwcSoeCehyf1liH 8d8cM1GzYEcWe15KwTNqlxi5JWjTu4QSldFgeCLSPbh2lCnkOKwjO7qsGQ/vrrN/4N7BZNE4E2Wa 8cijkXd3l45juQuC1AooWdVfWV+M80Du6gxswIkeq7jS4uI8ZhefQLyqUlFOQs7ALx91xA4qenoL SgV2eVQz11MjC52ixOOvue+mOex/zg/ZJ0U0OR8AKqlGwQJUgOVAo0HAJOKmacuX8NG9cYupMz9S gPDASNVscbB9tgSH8aqP14u1BOotGroY7ND3l5uIXpQjlz7JjwLdcSk1zJgd9Krp79n0vXr2Xdlp 9Nz2lISjN9RXmOKrqMsIW4vHI5n4fMMPfobriZNpSr2jwKdYwdqJSzDmN0D0RxQT7kiNR+ow2E8d JRzNs5LVlmtUM42Kida4acVeh5RMyptAzZ5WBVQqwj4YAQ276J4WE9Av6xsqcnIjMS22wjkXg1pb A685/3rjqdM784I4+jiO4l0Bv1oEQ2hfftJZaRV0fMODj5ueEegRthiLjojD9dSfjAUgp3ZRHTni BmXWfgHWI7pn/jsNZ1VnVvV8YCO2ojlMNO8hYXmtv7aNN6Lp+Su1N8ZARbAiAQyxNNGV195//7Dc SJwKCSvB8XotpNZs3oEt+C/I2PheKnuPZM8dK1CiVdcnkbkW/69uPaVvAhHxc6htg4fsoaItkVpc MWBpQaitshfNO8wrpakwSBBjToXGl2h0B4/8m0DUALxotS6T9nKu4u5WROLrmFBdzhZ4kV3FjKOG 1lrOVXqTGD8K+lX5r9Xch//RNeaPXWENIqbbnParzvOLuuxjSvoesuPV0Ubduyb2XUhm/51M68+z pZMAnLHXcl/jy5+y/NrGbwImrUTUuYUP9A0S2QoVr8nJ5Jgy5kIvV0ENsrulE4QA62uUP0oaaPsV uGaSbwZRRP4XYGNd7wq0geukEAwT17/X1iLPx9gCoPQLmaLaR6mf8jVwWYdv1Rvs6qqV1d7nAEdU XxVb90F4k98utlYE5O7HMCbhDMQB0D13prycYhg02jwwzu8/uciPjIXdBBgryPl2EqVuY7Mf5iDO KjhNhjf04Wyg1ejv3hgp6oex3Qiwn5BtXcDpYXTHed01InNMth94HplAtD9wzGdcE6WQlYRbAAyS n2r9uvrOBCg1Edy8tOlt/tTVH4cKkhAGWedgiyt6zRA6blfQf1pnlhNiq/aAqi7w6k7+kkGUH80v 0dF7ROmjc0+U0MdF7s1aCPnuDBKyvqVk77oRslYVV6Nkwj/2ipWcf+51WDU1Fr/8MQp3f7xyrvJ1 gz4vBPhU8KL6e3PwY/WDppW+ZWe45fLR2AWuB2Ddfao0NgbpsNfsXjjki/JhaE7nmnXLXc/lwM7/ rDcRIJcXWUadm7qC1V2WAI9aaRIW/xCLQAvrtt+MULWpHu2JEkdGx7Soy1vHBpd4rcwrDBvAFKAN MnJLHph+uV8hYgvxeovrYckXav5cOjPEdpkLkWVQyq2NcTgj1ndr3guYI46Bg4d/LN14zk3yQ0Dw 0FJJtQWfg8+aZkeAL2AdjxGFP4nq6VnUtmQXxK41VrDBX49/OSLv4s9/alhbvMoDVibLCN5qUSUt xHZ1l/FEsJU7sfHSKPipiiwoO/ltS3OeH9C/NAaRch2/DpTNG5GsT5gTxkGelqnOi9/YA0WNiRfe ygkv8aoE43Pwtx1qHv1riXenqD8wXdREn7QlHe9Y70WXkH++m8/ilb9IpzK+IbxrrcS8P9HbwMF4 yrttQVNGACu0ndP1oGrYg3t7qRiEadpArN85+EUdRgIJm0JHIoYRW5tqjBvbwNCExRDyr586pUP0 QZVLZjycP9j+iTq6RXv6fVLPoOPqPuvgaUxcuHNhK/zK6mw+Z+8bLMpQeBLsLbr3Lk5nzegNIGiu qwfRRF7GoUgSh9IbhRAKDSN4md+eHTRxeMLIavG6Ju0IDjYp56rBq/mLzaZt10WadGGJlzsP8wc3 jcRowaRfZBXXzYMwOvMw4TOBeoQtjFs2CyghJTKikbRTbvT74E0w59xJUoG1Olop8+gAJ+8pM1VL RQ+Y4BnhejKzKlvwCx6xVnNleuC7ZARafH2FaMebxQ6hnWskVErWvOMFyr6uDPd792luk6MHvaot KeAW2No1nFpE2R0Ulr374VZY8JMfXMqCV/x04LaOkNfhsCnUM9Xvz7FEhzyzhc0taEdQpmMDwju7 RpBql7S51zyUMpdSRCKqbt/cWOk70K4Sz+U2K56869w1uFHHwraaWmE7Ll4qID3PZJRARsgEIGLR 2JETEM+AJlrZls9kpO8iKqYo3oL1Jr+Fx7cGINQifdMhESIdu8kSciefOnmdastgpFE+ei62n90K 6SMkonK9Fg2x3J4sZlJbSAcHjpz29r1x/iW7U7ujyddRwAR1WmlfEgxY/YcYl0UGZHzHOA2I9Fgo usiEIkBouaTPvqpHKUONxoniISepWfuGP9MQMQDOEWvIyElKS8ZYVkZP2gjkskSjsWDdwfhrGbsQ xGrKGrU2Owl+45xln3S3VLF5p9F2TifzeiyAcRr+ccZTb9X4qRazBN/PwXR9HxjTm5/A1802Xe+t dy6xSTAWTUFMWlWKWAks6jBgY2dhufKmQUDmdEreG87C3hcfzKssnoEoC4yKE82gTUFK3Ji+U1I/ P3dSmKNkTFZmirokq5zB37GAJQ/P7psNx721i8u8eaJ0Lb+31da4LJ8npWqKIqjjuy95CWiyxNsa cuME1AwXT8OeceFndoyH0zN8mMo2EXhco/kfjTlArmjVKrGv2L0OSaPQ0fAm/dbuCYKw5xAD8Mzq F2rPxS92l/BrMQWi7LMIcoBuXKooEhnPW9XRi2+6MfmqVsCFLo2oQreGKaIjlZBwQJ05gI6eE+S6 knRtGp8Qsdr6iYTmaK7OMiBdfDalZLI1NOgCd6wN+J8LAJgPR5tjwWMra1lDvE1v23ggHHcgAP6X CYksxYIYfQkSGUQQYbjjGtW/E32OFgVf7Xl8N86ocFXDSdq4SqZNfvdT5+GDtXG8xQ8hYTijCIXm uNdUjGUQgNwlpJ861ulJUXJsyyxc/R2uq5z4WMXEKLr7zdjIcmY+sTw1mwsdwxNAh+cNVAsyPcnS DUep4MDJjqP8OQtk0lWZUkxpNm1tv3Z434ZzFdxqPoBSz4vZBvkIlLOIg1fQn4dnteEVpXkn/adI 2BvSPdmcpJ8qxMRiqGyhdQ9ax+4OOTBEJ/wBky81MyPNJli4ARYM1eiN2C0rHzxIKON67YvUkXdj 1knDfcT5q2DLusDkzHbMYAb0Ka3pMmeO6EN0DAwtTo8BnlVk8YsL4RG2qh2GqCOuLOgX+HBPf3/3 Bf+90a1Fxmdcp1TdoPzL8Ietu89DqEdB4iMewJB2SzLIwR/HAoZaarTs2JTDm1Ko1iUAExhEsjxb mePCvtBCES3/2jB0RLfbdLcrZczH/0VHKI67MZNf9uN78vJTMUaLBR0Fycvj8D3cM8+We40KXuyp 3Vp9wacupnMos04b7O57zI+8cT5fVbYBz2akRCZpVARe8AZzNWH/KHegTTCHfspqfmvrScN0d44U cj4+o1IYqaHFMpflitmhGr3mDcsru5OzkhktcQOI0RQjLewvAlhr6a3PXWxZgCkOi2b3NKXZ2nIl 7qrTgtOlpwPCLOETXpsuq/ZsMU/9m/C1gU80v9NuLi2JqLxjq2T9BRX+o3Bym+QFjx1U6kXXjnh3 EArEoDAb2WcZKv5RUuvnA9eS6STHjO+XxObC/B7Urv7v+UO5neonJzMwd2QE7R3qo2BWe1x4BLl2 emQtyLNBYYFFQCIvNOqJmWMxd66753XW0glqhFsGFbpfNTAIe0R83x5+5coukmjUnBzaV9a3kK4m eC+vp+Th9YhJLeMBx1v9HWgKtIcdJsPkCMZLwnVADfZKfV+xOzsigxdmHlI+7YZ7uoWt7ypk7dOg sBrmKdtPWOu1xWAtMovML1pdCQHABxUABiXj7X6CpuFqF+2/MDoMr/9ct9ME/q9hQsplmC5Ym37B EwGIhws9UkHiPxMI8mtar6Je1t+J0FJ1XirPuTyJYZCPlhrZqLUEPb2QiGTeeWFLHnZvtF4yCEPu 95hG+bQ7jDSIsCaXJw+z7/vLEH2JHd16LYMZjpCYFCV2FaW8cgOnSkBZ1t5xkS08jhmITI7a7mjj pxihQ3vTYoB2zFG98lOD/Ul8l9ksJFsoS9BcRCwUPtX8Q1GqFh410SFUOgZrO1VSM5GuqzNIvPFE vZns7husmMu5nj91veAWpoWD4ietGCxi0F5X3cU/E46TLS4KOXUn6hbC2P1Gz/jQt/iLyqAFKS/Q kvhSSbjyRGzLrEte6KMNZEXAKETmXjDBGQ/MNwbsR6RhLq79pckz1GkOcgqWKAIEwt3/5OYkcO2s VnP8XJL7uzpCR+nY0o7nibR1ifA0oyaLDLk4ZRdjRiXMOoDxkzWhDQJdrljMCmIaMxmpUsl8mrIT VQddIjv5JLxAp16KeEB1kFHVUdAtFeamS5m7kYngTAGzKo5oUy+wuT70myEA4aK0nv/UKXtm0AIE AHoDYAPYluCp4GBBHrQMWzE9OPPQBqP1bfFMpLO/7/wmCur0CzygwCLsOa/hkA6OQVEvNfxxSaKN 38HYCV5x4sIRKqH8b5SHNtf1gt1VYrt4/frlNdTXvaXQuhJVL3kdexX8EyKL1pd8N56Isrq2J1DT LawtiM5iAJBocn3EZAlM/yeLhn3R+pzct8Yc+Gv5Rx+CSpabQvJ6nXEkT3KzhVKpoO+rAB73gRE2 uhvjZPyCkJT0DIt9Rsali9wcxqZO0/aIKybHNYWE7kKM4vABOoPFNLFmsWUpJkimk6oLk3cTd2Ma r3bhzDxxOIEZZ4+zN5XDx4fStoAGUbmqOkSw2may/tPDB+JUR4Rs+VX04SAKMZ66Fh45NBjpawF2 cWnpobkhVdeMup6E6rpqzAIXSI7zi7GAW8R31CS0sY3IZWXfpA9E0TTsXRnFlZz1F8l73kzKRIAe YM2XM5cXdgfPSZch7pPx71jRXELoOA+ToIpqE585SAqI7vc3hAdZqDsRG1PhFS42s2BA9WFFly3M OtqetIy8TMFezD0RDXqqBCuNqsYMU/Bepbrh8YcXVvt6EWYfejtTUurQItq8hU5N6e6FklCTGlvg VueIM3YapgngDR4PY0bI8ibnsfvsvyCgJE6+49o5+bgV5lg9pqfFYB3QSc7/nBNAD4LGc+hlvThH cXeDEp6YY+g8uxY+Qs6nxKJ2u6dUfkWDvGFwcbCuZNOuF+iI8wR27XJMX8dDT9LS3lKs5baUSBz9 k/yw/ffyDEsvuv7/J0TPPH46/BzK4nJ4ecGy9VMsrRyYxElB4olpcyLJHYgg2JcDls1seBQ1zF9f rLtfjXVqcGz4w8cwWAB04GVcjwzHnMdPIPXbhi1lSeMfW5F/5PQo5EHPa6wlzPRh/8L+F16a/ySP 3vD/tgYzkChVbH9tsH4aK/jYk8XphVjcIdq3L/cSCcNzdljz94FRQmFUp13d4/QjHlWXhSiTi+1Y fu93HFojQBD2CaOxYTdVf3r6iYe4hXKnB7oYN2r5W/hS2xizORTQArDw2uoxCbylgn/wLt6aQImE Rl9ySyWOq/sgGgGJ/m+g7wGbOgKMwLgzECtW4/+UUlRbGtuK00/NAIwlMtXYTJcqKQH3S77+vonI /GZIVvkYxuIwyDaJ6Ikcq9m/R6QK/6fdqRmENNNh283kwsYuQd9ld5XX3MJgXEMml7oIpggkHoxw xRsFGTBQkvuZr6dDH+WIZ9X60YMFyCSM2FfrGDZwpeijV9xiaZylEQFO4mM1PQFdkWAt/sRGQg1y /8/FrygQryCXKsnsmKs5TUTNrcvVpkLNmghd8bU4uzIOsYMuwOiBvxKPr6944sKOIz+34it+XI5i 01UFzjATHDRmuV21Yg2aHiKoL/2IDV2V2T5NJgQ4iQTnsiql0ahKuVYVoBaUBr01XTGVtsFGSjtX qzg03pR01gl/VhMNLGZw3FVH51eiujNTyX7qs2Sn6paF1QHx8QeixvZvZMPAv78Yc7UiD334y4Cr iBfvGGYs6AhYLZcecYNBwSezt2WfwVuVExNPgApoDcIa9ujuHjbdDXlRVuYUfS+jQoqiL7hcUs5j 1+4heQP0+erPlPGjj2HjuS5uTICi1cd0ip/7hnxV2jt8fHd2h+JfQh2LSZgbPXe/RALbEg8Osk7C ZcAknwa8UIj7ZUfefZj0FTjqHxxwaJ8dDKSKYklV4g+ZBcJXs84NrjC1HBLGreL/qbR6P6WsM0KQ rkj50qn/zVSGcinp7+Wz55vjkxl1NQk2S8TerpbSMfMWlKMp1UiFfcWE4lDCK8H3qQhotTDUacV8 xwQgV7cRXupP0UddFiGcYF+5DxVvCIKsHXttbV7Kv2pOWr6fURI9jv7s0yWYCfL+DDE9eIOkmysQ YMRpU3aJMDC4ZMHHQC/iH6UxG9vV3FEjmiHgBrw3AyZd/q+n/3P6FyR0aGERjgxcky9KR2pONE2/ 58KXh5a0luHIC0E1ck0lf8JYbGNu+MFu8JwMk6p2JlsnNM6ssPw0hFuEMozbjk7bMyYbzeZx+RrJ bRUKj2NFIsoXWnlf26bO3G4XwCYqO0lyJcduecNupQGJsefOt4AxYq2rZV9XB2m2LZHWx77SRRyA 5GC2BTiRxgze3LbKfAKnmOvYNtkjULH5QKcQDdnKFIGVa3N5ibbfNwQ1KiZVHLvTQTgz3JlOuUr7 vZW1xHvWDtVwhjrpdTOPlqVaR2NfheiK+LFjeisGJRxRMPIJgPggWsKe9VqAbcsetC/qcj+LUG8+ kr/O1pS9iLu+VuJC9/ccN0TdBMB1c/6QShs2BsKoUC+y/LKm+O7/AGIDrWO9WYAjNs+T7Tky6y5s ZFq4uIDUlqLnuwR8YlOoRcaYw3wfshLTzafpvw+mN+/PCG2pUKxiesg7Bfl3mq4PAaT35M5+Xpw3 3Tdght3Dc7GCOCc9ZV9UqJOf0kOJYlzR7irWx7B4uIaE6BDW4KQ7ZhhQQ5D+o8AG0qp2hxptWMXR 07V9nYJyWTeeJZ5Lea2ssEPsiYAtQg3XIaQPFPJvt0SpLH5HMboMLy228Kdlu+sOOU9Yzoe5ME9A ZqLo0f7zjcVY7GENB8PiXdZCF+B8oT70zHBaJ2TOScrH8DvI3IEsUsBcAeD0NzZ5EJwb9nggvWcu 2HBBQDVGFgnCkc8ZEsJ0Q73D9nXscdSpRj3c4wxeBEgTyniY2sP/pStC5u/pe0YWAPupTjMfGpzq hxYbknMtA35l9MnFR+HUMEhB5/Uin77ZHZqGYNTlVwxwf0Da/oBP7j8s5oevZCXa1+z5Rv1PNZXD 58piffnoy1G1KM0wdJTL3tdd32X3jgF8sfgusbKjsp6WfSf3J1CQX79bhju89C9eM+O+7CGuYG4F ydVLfIViSTnK0OSDKb4S96VzJPn6p4E3+otA2uxJGN40am47qDD6hesbXtncsi+sUYgREkA0ZXTI j5xZ69+0iJj/LKNeAK9Sca+glzUkJTlgW60EQjnvRMMHYqguc0rewiMYrM/9WsqZazhqr+2Stw3u noM+DH3Q7KucvrCU4YixNHV80VHMnZB0RDQlSjA9zcoclNDo/ddWrWNeSN0vfMM0c9HlrGF2miFn Yorw6Mg0QAm2wzPHDCrZB7qzCPsf1Asp4VoH+T6/vR4IIRzngXLAICeuV4MzdooHBPB+/le+hIXk F3oATN8NyRLQxNzci7bDz0ugxwZM639fbvgE4B6Hj69gFRbPDXBa8T1PT4gUszEhdhJxNpbl9wuZ 8sZYgBZEjyI7DbOu7ZRhxzARGZiTJA/EyUvxUq2f1SgbBq0UtYYjOziu5gFXRydpNV2SIMVUY9TC Qzc00ZT4Ps84VYpeqOF5Dpcn47mE78CXMXvj4R0kQy+uSSHycmFpn9MDTRyIPZPgrCzbyMZ6as3M Sbo0iAxK8HPJ5MR/3Uw/2ZHc8Mkm563oeFqCt5oleewU0orRjrBPrXRwuvD4rYgAc2LX4rboyGrr KbxFvQVpWYxeXkX1/9s9jv2Yd4FX6QJvSANiI6PSV5Ha9iLxk1lCEoSh+sAVFLhIWFmBfDhyxLWA 6JXGFqk/RIppfz0hZgO8498U29daXZnGXhvmEaUj7r320kNL+VWDvok59lBDU9l3Peuw5flNwUkA Pp3hcXucPAWb0uwuf+zV72xo+q6ewyzoJXRAlPhkfbj/7duwyq6D5NOz9TwhhsYq2zuu180kvAux Cg2QgodYGdry5jVxLwhcuUI5yYgVJJGeqycN9zOpGxjSWqwJLOf0SRHK4BhS5DnPl+c5W/7RUx2s +97hU7jsi8sQrvHKy96vb49OSE+TJM/VqA8IgszkiUpLtCUytlr198VId1wrF5opY/UIpQlGZHQs R9cam8pRcw6c3r4iMZUvRAvN9yiKJhgr2s6ZMj41YELk8fT1kyrjL+eoEEAQX8SOve3TfrpSNIX+ +xN2AdKYrgX9Ngkfq/d5WbRKmcJj6dWaRDllwVu+x5fXkk5jSUFDNkpEZQFQULGgKZr1ZVKqRcc+ tLhMIUt4l5D6v9HLxRQE4pgHHhjVa/xLXAEulFcGETm4KV5RusxLfR5IdaYv+hRpgv+ihqW/tYq3 SUETgLXD0pZz+mSdzDojxwXFmkYGVNwl8b5IqVItQRfHlhYv/QCA4bWC029HR7hEMfohzcd4BAHa 3j3FzS58GRSLaas/n6BFTGtjg+h9e4RxymcXsKSIcFoEI2WoMA6NrG7Q6AFACpqD89cltSGniEtf LCb2raa3A/rhFULRt71r3IzgpL9hhW0/En5MOKnMjG93wPXttk8zN3zyntGUm3YSyLQzVlyntHZh VFV4DOor9QKaJvHrJcQGTey84PaFFxyjCRO81qKrabjJhZ910PgQzyyBvTsttxznbtwtXB0P288O Erkn/Poq26ehvNV35KSzedJzA+ketYK7Hesb/P3MpgEMNjARBRMJ1QrEK2kYeJaMin5fOi0nTLgX E8aie2YvD3Rs1yMgyLnUxoD+eY9VGvITZBr1FJJv4dS3/3ZJmGEHkXeRl284ylg6vZZgL44jcAK9 G+EumghcWI8NBSg9jBT48FPfSU6X8lDgtmUuP/JV+DekwWuuwbTVkdhveAahpp4JZ4ufSFgih7Hp 4pDIXTnPO1vvfJlz8T0Yo8JRYMlNI4SzSlmNuYrbf/9WmxelGaD5aPp4OyHuDFcnpdeNkCGuILqN ++Ata2tXERPXRm2DpQY2GbnlJwc3TkGzNwVkHb34vJRe3Z1DA6bFLnwpMc6+UMRqqWgbAOuVXWoK vdBZGiHSwW6P5Xe8yzaXEe565rqqZXgiYc8AJIuXJi/lg1xa94Rm0fnXc3ZEoQ5+ZwaWCWHiTWZJ E61J9VM/3PbWF/Yo4Ee8vnf8gcUwMMGdRCmpDxQ/yXj1Qf9OpZWSXNIpOwKOqRZPePaTxrtgah5G sRMOJCXSBzvuQMAarf0+SFBlSLnIeN79x0YPEiLQxd5LUO/kcghIbM7pP6TXeOpLk1NCFMOvAotk 4flKzLjC/57MAmf8NgQL7hKaIPiY5L9I8YFyWDhOJhuP17FS4pMe6R4bTvMAD9DJaXKl+7tJc5pF pZUzA4Hk//Y5wuCpytYfT/w0PLLTICqrwaprB8yNWM9QWbxUf25SNBUqPmXDc6jzBX2cAsSrh4aX 64xNOHoIAGCtOgBPSGUgrp3l8ufqcxKZhFr2Y1IlXj0pte4Ew3tCRdhin4fZYQhsrPB2JuclxAPg rCI8Esbuc/bzpfdiTCOMiP399Fu8o2GSLrlN/49SCsVZ6iOGUC3WWi4UV5gIIK/OkD16Du08OB9o laESkj4OTV/CaHIzt3jhCdgl1VCBCxiJkdm7z4BV/2LimEbwnEdC+G2cfjHbxZiplxBapnU14TDd ql00KrCy2nVqcqNaXiSviA9dCa17Dub0iqJVT4lcq9PcthHmsR9CuwaJF23v261N4QN/BMFRsT3j kzb3V+9HtPsAGuADSKepqEXeeQhvz+iv6m4vtPA0VKawzG3UMTIr1iGE9iVlbd4MUpltJMDGxCvN FgwVGvMXEQUPdP8dcAqcrYWz71ItE/vfkuV6JNxgfM+mh2Wcv1WSE0+xlVkNE5tw1Qz37OPFtxI9 vjFOfJFLxc0Po01alV3iStylpaaDluneiOY+1aH4zISI6x3p6d0OhMv6qO5s+fukVJDoPlkBMed4 hcpE15PlipsvUKO6rTGDxuDSi5s+4PmADqOyYC6O8t6nln26jmZyp0llGVLA5q8fZbw6Or5NOcP0 4i8ldLoBXmTa9NrS3i1AXlNAW2mXB9RhLof80MCEbv0aSFILUtg62e1kmBJ4Re7g3lRqP4j/6rqm Amch7Lr3UCk5EIp6cowdR9nQ7GyQHQRxRrhgd/gxaPH6vpITZT5WwJt/oF0IBXdHhN3K90UyquY4 9K3AXUC9v/B18qn7HP2q9KEnA+fycZAst14E4jp5AEKmmVi39Vlq4nP/nXF0lCdnXVHamT9YMggu YlgJxUgk7xTWKbM9Yo8FFrqlBVo8In5+8NMg+6gq3OTK9Ie9c7w8euHzuMH2K0MK+h9wjxuccDJJ 1JZhowawzYRuo4yV82G4raz6E3LUuy7GpJfIFTbU1Ba2ohAkmMo0Uu74iLPN24cXlG0RqUaEQiPq NjnV8R72+u0I2jZfHGGRLMD7aRSuvZdnCRRlDM/riijdBZM61paRcOJysT1lhHs9KMsjvzCL2lLK LbTKB3cXV9O5al1vUWqvyPLBU6Qcw3chlRKNaLiEZ5W5R+iBrjFp5KFulwk84Pv4YP6CIaFuqXrK oMbWIo5U2XAq9GOXvpBJhDDTugkI12uvKKF6TIBZ2/54cT2ITdHZOC4OmPrXHrYsIlcpEbSkXBAp i3K19x74FJSSOo4yRBr55ieLwupK/iDx8nTrkI+IKnKHhL9UzO26Wy2dYGDKNln9wJNWM6BtH7TM ynh1Nv3jkBTO9P0qfFJ5GhJy7MzV8IBHYM8uAQHNZ24MDTRz5hFxYfPHitlPWmSVJ/bQbYegkWIo R13IjtPpmo05FCou4pm5oU06GMHdnD+ociwLFgUU2+N/BtYmxyQW/PYeHAuH4tGCnMCeUAC8XGVG LJ9MtNiR10uuOh4/eulc5/hayEhjvmXZl51qQ53BQmeAQ2ajW9kWbMEM2O3S0vXmsA7rUbu4QCtb j80ZAQR3s8A2pp40riOB0rltK94k9NQVBzK/N6/2GL4vRh/SLHt8lnKaeCxJJJdBCNbu4wx7PDna 7laP11kzLL4ZfCcX2kAVE2ygo9DRzAqPrDPJ3fjinxAM9tIp7RA/b0Ov6jsYbtiMMGEoq/A3GkO1 BU9ogF+r+m89bjCusZwC+Fh1jcj4V7cZXG/1HTUOWc8lXME28VGNLNclPZR27fOWbvsmGwflr54B fIB00STQdOSScAkJk7X8y2K83kew98bpG0pulOLIFz8rpnD9nsu43fcxACm6KfIOmb0GoHAmq13P 8j++K3egdpPYMTelp0YKzONnJz9qCVbWr7unWZs/WXRtvb3AYhd4MX8CZVmmBWaE1EgJJoKnFKbo pb1FEXItTN4wWAiZmMzVoUz/NTeRrkrveqzmDUZMHJl2uq0rpkFcr9oEQ9QBtlzpyMsWVPBAEM6w lpsGIfx1ymgZE6M0IAL9UQsun+fkq9nA8WkHzDcyWzmCtkCN9PFu/fHdjrO7jdhEKXtWY/7yE4Ho /t2d0hUxOBHQW2LSJuN81tIojlmVjKVJRw2B9tGoK4KzXJMw4PLMg8+l6+Eco+jJ3ZupLp/IUz25 +sTwXmQgPO+Nv+BcdUyciOxouXuftqQQ5a79TQNGxw1lNSSXks8hvn5SSL9F31TfLHU8G94T9+tl udtDRs2a5v+zilGbyiMFWxZfr66CqTYbqYEybc2QYcTJdZEuGPMypq3dGZz6u33hc4yF+PUNjrxD MgHWaWOioLUSVjyPnzTmEQO+vYD4dJpTJNDd0+GL9CqDyS7Arn9KnjzzQ9SCH31gtoQ3ivqFntyd MJXN2wSRqP0AKazjL/rwrPlWnCp1ywgy46A1F7/RF8F/0aawZ8xmf8XdXd0OLTtmNE3DQwv9YKmn M7Q4RpydttIxHrKotiejUQfaGmHi1PPXhHaWf7afZ7JgxLQJNfEe+wxE9Ni8zGti5YrBjNJVjL+o JxudmpFRjWAIbCp6BteZr0vyPi2LYb8BRNroyI9SJ3+dNu77mFPJojJl12eIbuzHD0ufsmoy9XI/ hnxKTMOFREcWrvkWyB3u3oJnKbiBkPLyuFcmO1c+2yWxYBUByKsTwLhkZzS0nDenOqLSbIpQF04C SmcX0Y4jJu83XZYl+DBl9DfRZnPrYOSuuTOIBSyOspBL6Y5SD3J6JW9nUM2wg3RsgvtcUOCcKmAk WkomoBkdMTEE89OzPa22xD45S16RAQYFNWi/ipLM1TALfcLdQgJJ0XYN3ocqc4Hb9WpzeT6yx4Kt A3ILnd7SxWFGiUL63x/I02BoMOWUWYO7WxHYk0tWFnoSdEJRQ5h04YP2Es4xoDV6/FSNGPhnUcL8 lMFUFKijO+a8VkxZxw+lwXRWAw0wRb1B6e1f9UsY6ol1vi+lJCYX7QC832UnLJypqr+vO98xyIkn uqJyN/GL092Y2QhXY5jEhJOkkOu7cIG3FTMWnGIzKIqCFlW/IkBNgQFxmpweEhmcPT1Q+oKY7jmX /mo3vuH7/+SiXegwlstXs2FmUtgk8ucoSqGCeoHUDg8GlDeS6b3vdabPFyUhxs5MJdG2TFP0oQ7K MfsNViS+xkvviAaT6KoIdMPWtINe0cFwMHEYfp1hmRe++eAB2ErRLmuOmLEmjEMjTP75xBjJbAgZ 2xmmWe3+HoxqeeI8NufriwXplbx6iQ5pc/3vurWoHFWtAAUMgcets6NDrfTsyj2vb2cTW0o9xIxj wp2ZsZqgmWnu+X1raS3UEm/jRiUKA8PriKsVF4wsjyda/JEGAO6vHKyhXb2Vu4YS7RKK6AoIA6Pd YdZboUYN9AqHHgUf4O0n2dL+1pD6tHzGmBNXq98B1OOTpKAmRNaACwDmgNrtszYQzxpzyjWFM2+K a1AeaC378FRqV4eXat/CkwDAYEyaEKTN6fs5LcSKsEbM/yOutFhbphZPFMyDBpEAxjcQJsIuaX+8 n+vyoKjOzXdGyX5Oy/uIi3m1iYXR/d47Som2OeugUCw+LT+Nco2icI//r6uqV2tcPpiaBaEdQ4UO dbSAxl6P1zqli2P7HzR4SWoydCpjLEHoBzTw5LkrS3lZ4MBRCrnrMK/sGRsB9Bz+oDYuFvVL34pQ ulUT8JAyqyTCAitCnKI+vgioJ+9+9S3r4WTxkkCZLZzsDP5eNCUEo1wZfZAfyi9HYvr9u5ZCs45G 1OMt1cJjiMLt2Z5fguaobIuFPmBAjiORT4TdUiiOgJpQ4I6+B7mqFx7y3k+aj18VZXlLT0menA2u 6ycBXymPXHqK+BznvUlvZb/CdNwmyR64j8Y5ABpPVEaFhRZ0dZATP6qAs/rwtHUEwqffk8DVScKG NkVRI2CX1dwSuREFgTWh45JShvWookze/FvyJ7ZufCmuXI4Ge5HSj62PGb9FsO+gukHW/R4UGC5u NsMmpYFPhmiJlTzQBTNGDgJPLV9+ZuBjssqWMcDErneUSrL7ZQ7XndFrwoTbzoiNf5IBqQsO4CEt m4vFQtZuxv2mInr6d3PUXqU= `protect end_protected

gpl-2.0

7d7f447c399a45ac9d6872e259edf6b5

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_to_flt_conv/flt_to_flt_conv.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block OrfJfJKbMEd8Pz3wlara/ZLrdZVMve16qt1GIFknOlfDZsETzc0jiPb2ZLN+bj/6/1lGo8p/uhPS bugTtI5qAw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mODUmGnb8dY9RkGR7yX+wQMxn0ZVsP+CDypyDkIFtyFAd3tOU/9vvLtksCfoC28ulWlZ4lheBqTW w/7PxZ5QQhWvMyl5mQ4N5P485hO442Rn4vKqEqIA6HILubWoFpxv4hHLTqu3nUnsxddaiNU79itX pVElWXOSf1gMFNRT53U= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qh0ZvVh/hOQ3NVABeb+kjiIdTFOU4ClKHoxogmvzoyN4RBFavosirS7FUNU/atCx+Kj90jXXYIUH MpnNrlU3xC+YRGKYN6CzD8DcVhRpvCTwk0wlG2hAZ8aGNn0IAM1C0psKsjz9yMuW1qilK9FUHcJ0 zIoDJmW9VThaC9wTWhjTSINYt6i5QKNyqlpxvL1H3TevmeFl/c1Y4AHrhnbFQahfp9WJWwEKnYf/ 2cpAg24s8PdcyMVNvveBDj/MWBhJGpjdSqY06d4FS3guG20Oo3B21DN9lNLNR7t7j8b81ax4z7bv XhjzxiiC7zYXtjJJ+/Xf/5ahn7lnSw3fyPP+TA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block tqfcsGy21Lp855i+j0HO0i6g+NbhHVyptUTYghVHzQ6R5Auiy5R6+crkoXmSPLXlITNBy7ELLX52 vOhO/ci3acy9JVPvusljHrdjAv1M8ZoAWiOwY1aUrBZLNXwyw3HLtHZLEtbUlFNnvKFac+OyPpSP Xq5FUyQsXsSVOw0kAHs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block NvTo34x1/KFmah7dBwY1nJ20AmzBmvTK1RtNCB29pD30E+wWZ25Nktkp8A5SDpSaxwqw88Oo1qsL aEL6xWopNVPPUR47PRwqSbj+jSoVaW+hdDZSqABxlcLnO2xazsrsNtZOZRfp7OSxUF/+XWecNbmR d5R3h+20kGEML/ALMNFyPtWijPhCYQiLuGDlQFSuAIk4+ettG3bMc8cBHMHRU3QPTBPuUfKbLyBd Bz00lvR2XP6aNVsl7d07Cw3iHhUgMKjuARwfTEyeU+BWjz9ojRB2LpqFcIM4fa9CFhjvWnRN//0t JZuldPMn3VPxQxj1ZuOVpfDdQBcr+jSm/k8pgg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14816) `protect data_block Hr4np4Vv7JQro3a6CUkbXWAaEBIMWGJZVmvYztds8gkeKmxqrF+i/chgSilpZQmpMKC/T7rkRAhC DOzejRpCMbSCPQ/COnK1EvnLpEidRk1rFgTrdKZzF18QTlzt7QjslUhpVXTQC9Ct17KASr7USWEN dU882FjyGT/m8F66Xf501Ha4cGGiohYjLhweEnJtZ9X62XiHn3D2j/6+Qy9YNTFmT7vNIEOCX04L T6UD4b7vbQIDVcr9q9jGXPAVmWhUEiHZZ/g+1c9u9Kl5Ei1YVEqDDfbiLlbhmBI2BYAYdbkeeD0J CpM4oIeCEGC1un+1ao9uOWPOiQdQSzhj036rAX/x1OY14FzBlewzz0IRhYZYgZ9+OmA3x/3N+WkZ 2yqwrFRwM7/ZpVPBpO+iaduso+I1bzK1CrVdxotzEf/iq/pJqkhfFHSnSl+mdhoSVci+dIS2hopY Sc38PvpMx5B1wLyQFpk1RATlQ0fXQSkrPWRR5sqHpR6YnNjG36nLT4a+D85g7uIIew32Z3xvAVeh cAAdb+YqWQ7E3psOIda5Cx7pc3Nvzw4A2DMlewZwop5Xbzhh3Z5gLh/w3UvjUrMCK3sRNRbhnqUk euNMpH4ZDrDehynK/yhnLm9tJkWnfFha0VNjoMurRK3MotjfMLjbtEREgs08abYb6OZkClnfUkve uOEOHsDj28OOEvmrtKzvF7Ih0NxKNunZTH1m2T9i4JN5TwjzMRRpBWnZZKdvQQd2NbBiDdJCyFqQ NSSqTfNSVRs2CoJYCXcway/ydMXRl+LW7uovuv5tdNI/qJiYO6q1Jb+cqmXK3ZifEPsBqSUm2h8e /6lwMvsP7pU9aH7XZeA3eoVB9C/KrilB++wCZQz/bflDyCfXwtfFRUswULPzpScnf0nZOs5gddYf +74Z9SQf/tXr+xpLACHl3N4g9N87lCYWvZiQtlLIpHCkt6bEuzTwst6Gy24DlPeqEzDn6wK7w5JT 4U7IZeRqc92wFjVwNFgFd34y7FEPVpX7dVD5S3YWoHi1BGgIIjz97XPWJfx5uaxlMwulwlPCPe90 Itix/YD20vOcRJmVfYSXZCnbxUH9msOD3rNaXTQsyoKObVFGIu5hbHg39vUBZXBALoNxVvgBRtZ2 Baz+ZiL+H/yR6UHyeVp6QmuYJPWYn+JBa3fdDJr8uLAOicHBo47DCZ/6IeI0aVuT0aDEEukoMH4n HFopdgkiJSNwFgEoVKpoquehd+a0t+VlbeX+wGSmhAn7PbahzHoTBizQYg3XpbQYkoidkm6mvOvR 0mIG1wbtTke0w2xm5qh8P8w+UAxcDGZkuj7GqnMcmdWo0owOwGfjXYNojIQ2a6pINOPERif3x4Uw mV/iCMu/CLFqzKZszpOx5x4rscYDrwryUMA7tq928j/gkW5dnwE7/nW0oorLWDOUhOhWYIq/oZLB Xvih5bCQSD2MVRbd9rY4wS+/VZb3hghW/IH3SNyApl7kHQALfyerfSd6emgNcmVE1OVXpnuoE4c8 URueHe0Vx86QSwbeZ2bBBnIN+jMxYNKybTp2urYrNYwMRekzLeHI6qtAd4RDwaXZCYm/KdLeTPXN V3C/MjrP+lL+ZHK95f2VcnGeg9l2u5sKiAwk8EJY0MKinE27rN04WDZScDauErIkrE+mqqr6rgLg 1Fr8fMMFaKZBFkNNUDGok7bOVl4Q3YtVXoX+17wyBdlaVyZdVKtNSPn+Weo4+uAjnCeYjpH5ZRIP SnZO1raeVjgcNlkdnbJR/OvbklTceJPzJwRcl16nTPT12iJOQ703Kibq0Rs0OveFAtvUmdlbrUJh yQjAovs1POxIOjgBlwj31pswJ1m7scLniFZTpE4UpVEk6GGQI1OPVyYx63IHRzlGiVw+PKblSszL edt31Zx8JGWH6BdndUhxY2XMG47uNQgY1sv+nw2XNJllID1eBrm3A32oldyFCXFQeTvl069EgwmK 9CKyjVCDDmqq0mIz9uSDtz+XMtUS/aMr6CDERK3SK4xWxBqshM1d2Ew8wIhxzuOmTDrmETo+7PSf Ncu3CfT0fhPOjAFhylYAO38rR6y8RIWYypOyHPcBCe+ZmhULKpzBnu99OO85iaphGPIqtsWBLlvJ 7R4+NK+PL5vc7pMG1/Q9kguH3BGxkh5izpAhBe4S4/jXkrCU7orSrvnnq+y/yIzMuoYOwLZ8vREk rBC1BCTo3HlgBucsIrDV7v6xdtcJAEfNHas6gg36xFD+Kpb/M1MH1OXjzumWr2kaRDwFMPPvLSME ZHcUMQtZloJw2PXyNZMuv/tf3CQJ5hHrhjR5Ob5TMkzFlZHJgY1BTL9mpE0tdV4VSQK4YwCv02ph 7Ru8Z4kBJ1av1Nv5S3IA3Xj0uekmK1aZjzNfSxYz5r/P5RhiljSdXfyEehSOYDjvSLfzj0QoFcup BoFTNlBc8YhJC3aW4LTJ3TkGLo/V+l/paDHwCwjrLfGqxc+G2tzNSEqVFLZpaFMsUp8T91P/XhRg vxusIy43+a0MYLM2n5wjt0I6Y97p9TAP4yBSlRFM2xJ+5IUfe2R4hckEq8emQowrmlMb7PY52aSj 4WgntWVtTw1+v+Rz4BjCEkec0/6cnpQeciGMDZ6Z0jFTQoLLJ+EyxBO169SUxA8Ypcqdotkqh1cR oY4FopgjyMsri0dHZEjhFRIq1qybE1KuhW1WOhQ/ljQPljYpHduAFEHn5j41m+TcWtG5CbLzHBJ5 kGO/9fi5hXGvY8Wfb5K6dnDIWfZl/M+rE3a3EN+LHyayBx7Yx/ei693UMFX3LayTKb1NAsMD+71r yZ4/lVeVtiUo3XgdrFh+/ctSrKds0JGcovUi8Yh8VNj55fT5O5PQl55TgVcJPbmBc8TNTlj3a6fN UDpzfIrvlQQYpJKqGuQlM4rotJaJaZCGGtRwYEJkBotrUI3Fz8CcSPRyoVcYudrv5hFI0RwC4QBZ evICCXPSgeRcUseT0VrAby+mimLBSTM9FaUSNrt4tsg0x8AA+EzzL53go4dQ4KQ2fYBcHh9aFtuB vU3xQop2W9l8a3BfNws3xUdXXYehAr4uFxa35tf+HcGjNxPvre1GQi3wdXHYJNniPgKT5/AKY+d0 5FJXeKVwkoGt3Y7QZ1tWsF1rC6Pu+nH0uqoE1Bpo2XZQqq+ueOFQQIU91/JPIZBWk9ptCR0caZVF oaWm+O2QIPnSA4/Xp6juHx42Rl0TjPiJa8xq+ZW/RWnIU0uK8VEyxlkHnUuven7BPRlXNaC2lMML awe4rxoUUu5Nxd9KhuHxO5N+FkqZnpYK7toc9QAAdSjdOimObkZLrEQJyvISJMAK2noo5D4zuX48 g2YIHcP1z3gdxcGv75cDP8ukVdZI50FTmpr4qnEBArASOydOxewpk6JZysSAI50AimnWWXH8mkJx Rp6BwDFSe+uhCIZm1w1u/0TRzWOUpcZGt/ZyNKt1vMcBn/Ycyt8mVIB3IRm0IpKcdcbLo7XW4+Vo q0l+caLg1nk3OWzVUHNjECe53o6SsRSVzJxA1btBT0Lrc0ihy8Z8Htbu5myUSbBqjyIgkCnpUKz2 aGERnngdc3jUhxaSIPIGrijg8FrCAAi7xjNAmadO7vUmSuz/hs5VYZvtc9rFbr3WaZyOvQiPo0Im xpcuOb00CwuZsWr0gfc43kifgaK/K1Zh+eO30F6OBGEdxDU3GN4dgLwdG5ZtXmmMVISULZS72rgY 4RBmfuU9CNFTY1KxW8OHcbWgpM3vOlDiDknaN+Mlb/alPhvkVuCG9C78V9rJm2IaH03DMMVLGP1t WIrHv+XZiF/xCyaupnWkgvFzMm/nUtEk6aAXsuv2uxnKfJf+wFMIRAQQkkLV9pNQzK3ff+hxOoCt ROi/lcwnZOE0RNMzvzxPernbXJNjbDWRwX/oK36/VtMVHj3VXRtLyk6v1dFynmDbRcj87iPmK1sB B/Oo4eEG4C4FbUjq3vnJHrdLv7dbqlS7WLNZn1ZOYLcMTQMLY9mkugdxzswzJMYdBUNyDB4dPfmy /hglgJ/ad3a264ogKK3CgMl5nQAA6LGZlBYOZX4SGa36NFM1oeqHS18r+IG9xWuiD2/8Tv9UVMJx hDBzHtxOhvpLaIRa4FYj3YQib3r/s4OLEYx5YTKVNneK7h2LTReJ4YWD7A1X0WAFy/WHD9107YyW m1qo0/SnRjg7NjN+J5tlZGar30vpqh3i+Bmiun7BaqopVEtwvIsGhDHwEt6rWpAos5ar4E8Q6r23 Y6PstV05lDirnBHDCxbVa5tmKZOLq0SvSbVnYKvn87EmGV3dGUKk0TuhXVHPQtwLMnGzLpvTwsRH l3XJdfyI6qIH/0qnCKPnEIdbTBF2T8ZI1+ojcto2QX4paIo2H8A3y9IKda1Asse4qqiNVYaKNDXN zaZhnsUyfEz1RsJYruOULFptfon7Nr8RwLGRUo0mf3EcLHUQApeCwzFN7uJQQDRe/Bm6oTkcL4fQ B5cq0XonglBnrloHBMbn4XqJNa8jhU4Y2b3EpIvwajiqH3wheGH14/7tbrUyIA0Rjpebg//E0Ebp X6cg+HAS9rL1v/Dr6Ths5fJsXnxxXV/sMUEFcPxlGQD4aj7NPt+27yxdubaJq06Pc3ZZeEedc8VQ 2qMu23qtYEgQVTriuF36r3HsY1/qktLugPUIHYts7+kewLbNbCR5Z7DKMhk42jc/CPEmyEt9WR9D sXJTrYvNnsxHdRkNaBVtUvOn+zT70rxtXdfVYtSY/ctUNpLjyWarxclPx5++V6qqVGVD6Mevbt0E vp4R3ZCU1hJyp6Z1IyfsJ8YbJa635sOl5oS4GErYbyjJmoCEcK6XdqdbuBGj6FhtwLr0GmLWKDzU 8jOTup7d9GJw53Zq65YVfd2iRgoN2SY3ZL+tRePHu6Xy8LY0qJA+4XWcTjhI9MJRxOHW+kTbVhsq Yp3/B1LNhDN4wiflhWXkRabGtknNi291l3jBH2JuDE30wQyODwfSNfcl5FZ8zOSN8uqdYjwaicmR Y4hgOXkB8Zdw3HZmD3GqbISEep48+lbspYrL69oMH3Vxj3dENsYLGeVpa28OBRIwCgdZIY9meegT z79+5OhHiW2TZNg78cQk0N9ytPeZbI8uaenRZ/aMI4fZaHTp8KEeBT1tPNAGurODVWL2xdXGl2Fd rbbPoJHoJl6C/6LO8BoEt0SMAkmSSAt+gihKbYz3gG1trJI6CbrXOJY9ZbDK/1o+MX+CmeWZot6p CktNCP7CjeBqhZjkmCUXybdHXF2j50uc/GwUsXsg2x7L3Ll7fdIOo85N00Ok7geQy0/wySceknEj gLEzT1C6eEtKx8MN5+jjDlltIeb5L8+mrCAH5XUcCwqDvLbPqdTkDRomxPKQBh05hrRxU1dmMPZR 73jfRktTI6yipi0Y/NFCM5Cyy3B+ZBmT2jsbzCWEXqDTl3YMlEbGgSZix+GBkb65SbtT5pogJ99a xTboGmiPDa9KtcNnlWSnEwik9gIVrYH3K23GnB9DiMwg9mXOurmn7n3d9m+W/gWFWHHGFkYFqcfZ MMk5CCvlj/B+JFi12qVJXFM2pIRpT/DU09ljBj41GW10hfNFXr7y27V9E//CSinstjr/dbsFxOKt /6N3V671qXe7zfhO9lAhLywhDHF1KC3MDrkcWc98etFyMsqN4Sr+tJ7f8l3pkDJY3icprOHyfI40 xVk341FJt0TA+D/M00ylALaJuoJnAVY9IgP7aewLCbZ6Jx0b0YEGE0+ygxPcAIasvbtWgx7BJ+7w poBZqNWtflQ2TYnR54VXGp1xy5mo1c7UbJp97Ceu0/WHcz90xWqGF49wgV3yW7qlBZcydKPVuQGJ rQGRO5iq6kW24oHKCKCDqiYfZcZrDA2dHXcMBfZqmHVvDpEfQMLmQxp8EjsLy9dP9RnaWn9K+R0M d6GW/EH/brvhwKu98424ah6PvjtXWukK6LZSq7d6U42+RVf97YpX9Kvi4kBpQYYZQugoijI96hZN FECg1Bp8pHIzyH6dxmTflOsbeYAgqs4VUGxbMhyXDeg+yKGRoP/8w2arrAFHNyUsVe4V9JcFcrRC st6fcWwof0EjG0dlUbyjb7M/51P/dd7fFWUzgOF+Jkwb8dCC8GpFupmbt/d+0bcDZoQP8EUb4eiM SY07ILIKBGlHlbdnL87eEZJKDn9TAkiqt4PbunHtWrSZBynDpKDEI4HrM+SMuPV9+LOhVk4S/n43 PRT7ISCIyCeipI05OorSo/bbToAHDnkCL1XKzcDCNrwaxVUaXyzJFgf/MLhFXIg/Z/sf2u+QxBG7 CnHsjK2f9y/5bWU/nX9+vpJwvpCB+zN8II1hQL4qzComgCK8c8rrdxRAaxHa/oDsCqIExy/w995Q 2Lz6bHlDrvS4j0+Ak5Y+R9sTtvEU4hB98sKF+WPlEiRMMStZWSCqkAMWsPKfrtuHBHRX4SugRMXD SHm9anxXz4AoHqOlrCsWz1i7aNbg6RQ/JSFQzPAHD+RkV0zQisacJGgLC7rqJUUqEiCTsA0CZ0TF 64tHcIXjwuH+nU6Q1po0UeRK4LTb3zERX0KhBoczcvlSltNk3lpdKMt3+5XLhMyr3ftP+V4G0XrR 92zoikK9cU3xXz/3YGSv6c0CegDSiGyw0EQLd1B2La3igbtSDs8kYniWxKL0GWercurwxPBD5Ea4 Pi5IRyYUnfdidkKlSfdRT2uvvMT000nw6etc89/jiTkv2fwcOVz65HrmrVVkpgIMETQjEILGEweB a1SWHjBZ8mOgU2XhCWT7IqGHOBGh4zT7kYhxRqoQn059uQNEsQSsjnzzJAb1J37kK/qY/eCXjUSP 4nlw31eoL4o4rFhiGQLtB7HqT/KZ8fKBtyQnU6aMfqALVaxlBkadVrFvteuXpsSO4klZ6Hpz5Iai foCQV9mYKL/8ekMTEc4VgPkyqqZuBqIQLUOfCJFHYdUCOmxIZ6G6sFmdVBoyvoMQpsIMtQDoAU+/ G22b9SMrYgaCTGLkLDH7hFm0tftL7HRq/e103MJeWl4x3TVyhqqbhP5nMNnaZy6N9M2547/skTl9 v5/7WeHI3zKwqKEJhvjGSM9IcjZUFUVm9/1N9IiRkKrRhRZdmupvzgEsoM5PLK9oSa1VcgXo4RqH HZlJsv0IkSZkePnJF6HXmIMCpUcs3VvUefwc6NnOsZOHEpG2V11JBM1AkvEOPAyPPMiHhYCR6Lfz KrwW+8U3vhknP8buhtvIidHftj1nrOdVv6+1S1bZwYmAvzLD3NR0KUKeAbH8P5cYQNsj1ikWNfm8 /eMSxxuVXRNOWdcX9xAL76YXKscEbM2MCkJG6BJrHP8Q2iGJqIMulvnbb+prBaxsoPVEnNdpWi/o v+tKKfjIzZSfPX4IXdxl/JARP4ikgY1LrjqhcwsIUWic4C7IQGnQ+oy30cdBBDIe85fQecBHRP05 gVKNZdvdZTUt14MCfteH6810Ud2JPb9+Iv4VEheoangsLHhR/x5HJVvuu9t2WNw72TWDkNMYDxJi 8dSw5te8PdMOS2retsJ8UA9jST0BZijoR+VrphXUFQhEGMpNqGDdZTImvuYLniDUdS/9AJhknkFO SIoRVE+5Dj8VPE2iEMerW2pgRm1JwDEwWJshWxCCUaBrhx03HrK3GEyIsEJBdgUrLNs9ZnbwLoud BidIa/5pGlToE9jFVm8KztQEaNzVBdJwPUP2xXgxNebULEpZKM08DFtvNddoREWeI7/YGC+Lay2/ tO0fvadgSfTc6VlcfSA0LO1+Rc1AQyl2ufzQKA+hfqbjGM/p65x0MO4oO59qVNUaBlOa/k6fUIkY 0aV8X07Ggy6i5xD9xUSEGX5MxPKbGDXgKfzWx4XB4zwhAA1gtzpIH8X4d2ChjKGcFxVcn5K4ASwX FddNrKsGOENv/I+Y7MD8mTEzidcWRO+0sJjHKh0G1uOKKfJGdWDZqVzOB7Hd7meRHjCj8hfCZeLA YVkZj5iOa1qJiSQnGaetqmzZX8JmOOrjHTr1c+Tp/RyBYRBtDoqbD7NxA+iNU2K94WKlmiQozrJd OeHiDBsqFty8SS0q+mWAA0GzFfU97PWsSZGe2A5RD9agGTiAHf4OqtKg9ZhAH3XBzsmqIzE5rQDo RTmxeU2Q7lX7SaO8iFS9CfoAr9zB5+Qk6E76jAmiDXSTV+lqt6qjtphDp6SS7iD5dwjYC/+4/O0O LtuRIyLYgU/4Y1OQdLrasRmihEhueE4YHu0ycRzx307JwKAW/QCuVEFHynVp/OF+hvZL1yyWHGQ4 i3WpYMZQvVL55QQFVMnO2yvLFNigtxZnoH9WoMdofXXRIbM3muUc9+JL56qRfoykndYuAnlK2/Qr yS+4B0qlmXCnyO62VUlQ/20C2OVFabDgkG/uOjO9FyFKvxIAVDrvb146fezgm6UAMFPuh3PBQdWV FS/LZyVMXTaTl8FIIT+TOQLO8/w7WqLVpCla8+GyDTcs6cunJZ9bBI+AptyYUvGnfk3rCc0b8HoD i2DS/tnadAc49Ao3f5kIyeobRS5YuxyNF0u0iczXfyEDiDRyPhrVEhm1XhxKBAk+zF0V9KKoisF6 dbbiwOAnDGVc03RqmLELnHPtKojEDccd+VfHy9XPDY7060GLBt3cqwP2gYzVF5UxK8152/In621v uMrHMSlrxXrN4aH9q5XavzMOGuGN5sYw7zAnYByf4Z4WxF7auYLrSk4cQPtjxhazD9HniYAsBL32 weCC3wyBHpLr5yf1XlvMzibbyZFTjk9Mopx5rdBwuMlApozvPb+OmA2UsnpySJCtNnNnBPJbrZeY kurea4dP5vpUhvZw/wK20FIKZV8yle/jLpQ+iyOopjZfsE08JvifNehiUIDQdzjJxuiBQk0PkER2 vFwv23uyGm6fN+tr9Qgss31WuWeepvJhInfAPgkqakZkxknubxs0XWvtz9W2BjNfsV7yni9m6dDn RhPxg2iTmmk4HoOrN8vw+rCgzkw0Vt5P17GC8XB4Xfnmd6M35f7MfIkr0K3OFitldVwemGy7s87R NpNLRYgibEUgPlrf4cj9MbVlTZrAjSVpsACFLsECFV8bkjoN2PnMA99MJIItWP45pBHLl0fjEHnY 07Ghn8OVxTic07fMXeY8vzhSqqqDtQCOeNzKBEoL5doOEU44zrpKkPswEcufXFch4wrhQVoIYQ40 iQYW+RBvF2j0+qjTskk1e2op2c3u0P4FboiwCukjZ+2nJiAou765n93Ny96eqqV3HQYrXeWcBIyQ yVAB3TR16n1uhSNIu8WzzyxJsOm6fEqBMeMUu4c89bX/GRQv7RejpIClfOa+PJQ2gcZDfXjoynCZ ZTJ+48CTLqr1ueq8yTNtRtLWBo55lKSG9QM9W+XE9fCQcZH7ajCri8/WsllI0VQ0IFTXiMy+qkxi phGLBwfvXC/U+2kOz66fCmRqLSrsvIPP1TnN0ISfXt+iRuu0F7uRQIbAgeM1iEhP2v7zYowBgBMr EygYW9mWGI+fd8PnqUElBg4xCHJCxdUqfMCxj+TkD1Cslig7y67NHo4A3wi3vl9rqQe9sWJfebjR lf1Bslgv8C8kpRVu5gZkK0Xp1ruKmwLS7rmfnTp1la+eEDzjK8Q4sOUHQ+A6UXe9zfCcPHCwMB+D EckJi8cu5R2vyzFO+pMwEnmX3pIB9oDv74ysBFsycUtNzNNqATv4Wvn07cykKeKwykr1ywZoUSVx vwny/ATC3UyR9d03qlMLRGXCRIJE36mkpe5Vwe/tLXqH8b+6fhNJnHm7J6NGRr5pZ5rc5wdb21M6 FVNq0pXgI+eqGoZpW6Jbe7ZJqd3FlN27extIkh8qMoFv8pak5M5bhjY0zfqjtiP1h9Ju6RbdxZAj oWCKAS3/dRHFfTAVKMnE8WECDgLhh9yIJDjpcG8ynJ//HSzJhkh8FJxmRfVUhousrBVWuQIthBLe Cige2YG3tlEM89JpB0SUaykcnb6F/6h56Q0f/uNzJP70s01RoRdkZ8rVYts7vfg1yUj6ftanishT 3K5qtWr79MHe7wt6ixbMYFMd6R8lR12jybvM7yjTjoIkPo67IDw/waAJ7zdaKn1ZuM7pG+YfzBnb goMRqanbKQnZa3y1pUepRDi6CjCqbHE9XCYZUioCUFTXHWvkQdE8eGc4pvqCbjG69l1mGW7tVn+x oM9BFdtCJArupHTcFFbwytedbMpNX/iT2Y550kedzhtOQbDUM0YuBpAEw+wotfp4nFZQApQliYNE 3bW13zvNaL593Dn3TV5/S7SH5ZPJYw7iuAzl3aS+FnargVqzfOv0EnU9VxTY4ByoSI54vq+h1qmw qTUMyeDvInU4nIhU1v20t/+M/dchRDVa1m9r2e8f6XGS799nZH1YIC/rzvky/n6ufHGpHh4JmFUe mC7re42KZhfk3fpTKiG65vGQxaMFo+9JLJyHCeAHLkHC08JdG9Mvxsg0+60m+n6lBdxjPYpeSVyj lkSYjaR1ke432YMiY/74WTsTy3xpD9a6ambcadXlJk3lgUx6OLhhlJ5viOHHu3GQJrDgcVetumV/ 1rdJb6PkWtr6J61pzQyZJbUbjWsVc+KR/dZ00CyTPB/JVRiJBO6QESr00b1KnsgFS4D4bGTFzNGP Bk7Qpaxfdg/vUxKV8oUdi3RqI0I5aeL0XfQlrBycmTWGFy2chCeq9y7JBzQWRSQRfUHhoS/amx1e tnsL3wCRiUj84pRgkYI5LRGB/mK3upLD+l6gtZeNxoYfvQG2Mt8eKhSPpgQcVYxgM6hRb2CUnAlx 1vSd/HJXvONQpKjcl0hCgiKA0S+oQpf4eB3+UmQvgdScPsw1k1dDTZBPvI3U8E85hCjuLCRPkHA5 hZowqzwNA1Cm+VrzWeoiksenvKTGpWXWXfTwW56jW7IMKgRSYhvHKBgO+EDvi8lujgXTalpo1qTo CnVuOVh8QGGqc9GiWvnJejv1q2M+HhBglPYcm0k4IlyBT1CNwJnCUqg8cZqqLZ88ZeTYr5uIdGo0 pYC/1lO3vgBr6lvPlvMT8HQEEgdMb+6KIMlUjXJE49PVeTwuzwnDcG/kKz/c2qXn8yJVPVkCfLia TcDu1a8Pu8K+Y3WAG0BnjPWmozjjYdiUgSZ4ZYFRGOswNYdVnw1JfVAPbhSKuw8DPRvgL1CQEur5 tZdIioWLySZie8QMitIlrIaIiR3g39C31q5mlXmNN9fiMWUjsHfddLboKh93gUIrXINdmyTcxdGy ubLosVRcA9smmzocUqJvUx02J4a+Be1VCwnVIB1AuOncurnjeEtLHJMNv0r+A17bVsTOFISswmMz ovYyi7ixJWILYXBgWVm4u6r7Od3FPt5zIEj8dD7pckT0CA+jBJpy8CdkBP32V5oOzGXL72Tepqan Pl8nvuSBfkctOD2pZ12yIu4KmPZjTv9KtXPufOQ8twieXZ3T/jwEZLGDdjg0SIowpwIjAQEiEGOS FPcVIEGNadR9eN+dmuB1Th2U2CZYIu6NIESTDtdWSSPOCV/tvEyLbjKaGas+KWmqRVE8f8nso8kg mv5EYOvXuhWsBUDI7Ds0VpxcqPPx9BynBjpk+6aGWACPI/lGMfOeTo50D4jhAFXkH4mxD5PLhwYE cnmI5zQx1O2LdVvjmUQbjHXPkp7zITVRJFUEpBYFiEuO8p5p9oxl4lfgHx8fjUiJFainIlU1dHae hZij1EKTm65LG0QIHiYihrbRtLFpjMpQGX/PD+AdX+esaxsOGzuUti237VlDmWtu3oVohSL0qF5w fPwoZVTIMUHUZIWk3QNwUMFbaPSWG1ZbdwX5DYo+lnvjmn6wCo4AwLJ4ZfurO91rmPTGSuwprDiN Vuve4QEUzGJSE3xv9XAOSxpu+0wIahaZzzA7rBAKuvIk+oymfP4EPRD5w3sZ7oViUfAhn017B3fV FoEjD4d8Q13cf3q6Irz+SHqLDiDvFxDKIO5KQFXOZTsrNdFwxWpukuP/G0WnA9SrmGGPr7sn1Ib7 qCNJO5iJGvxEWF7oDThl+H2JpM3egvcx9qHO4MucexdJayMiFXJTSf9MXQ/6sDyTaOGrb9VZuWLV BBMmvuIt9ZXw8nNm4WpLVHyMgpnrV+Gu//D8ZW7ydyrYVe69TTZpjJBRyQo6e4B9uVSGFPX1MI+u xw8r8/0mnQ1BYtI/ikx4FiCB8exrdIZjDkzb1yoLrTtCNtP2jAj9n3NVWKb9DtF2i+HtkwzTiuZQ DOwDNukNyokdCa13pFzsP8frT7gx0+OTLmMkuDgMktxX/Q64LBkC23jc4hvMvSft01p8Chr9/G3/ Av5rnToHOWXRC7q8IEXiTvhYWnWwVQMGD2+Q1SWO4o2T3/hxvTmcNJ7NVCv5IwMtABv9ZHj+O6n6 IRA//nm3Tsi5dzDEugQi0YZCpfI2rOYvUco7xGSm6fgSl9BNmth24WLgvGE7hLlZWfrbnDOtPFSK gUMdZOu0uHZkV/5AMvzEy3SCzL0A7C3G/1dr5NPseOkLjpzRli5AFXinlRc1mfKv7TZakYdlCC6E AUOJG8WDYEtQKmshVoBGoI3tSNuJCqRiCBsy/r9bIXnXJHK1Aa7Ji7cW2kCVqxhmeUhzSwzN0sT3 esvMj/B844racusTffqZBD6G1h2VBeJX//h+ibAVsraSxyH3pcGwDTLMOKu2pSA6voxJ0wg32V+Z 4noICOl3dd3yTkRsK5acyqdwJABDRR6QsYM7G1HShDLBAr+Is1Od9xv9pddxahrKDWs/YngI+JsT oAy8W0U6R1d/2IdGjbO9iqm2XDJCE4z7pARuDyQcrJO+dTPGJdbGN/oXGdyR5ppmmuf2mcDaL5oB Q/JlmWuJf0kxqDFxfCiSrsi019XFzaoU27SeHq+sMtPzQwKxytM5kEv081+d4aRvyItc1R0YZwWI Fr4x2540OnictpF8nggTDkkzBq/cLuNcs29yem0sq84o4FkFSJ7gR3KW29pBO4REMtpq3mTMYyp2 vTs+GBsX/IG21dNvVjQ0I+/I9M+1y19a0vbIju1y1qE0c/lkU0+bb5W1nsO+Ulwm8edbCfvYe2F6 T8qaOWtvEAxO37P63atfpcCuWWIgg0H/8pQgsPTToMIRkzdpRSGOjZQDbC0/WgD1WHTVuvQ/u2M9 B6AjSB1TPXlja8/Q58ek8wjzszwZsDmkesj2ZJp/KrZzScqwA+ZmFWQFrel5x1aCaYybp/Hr0Aok k6LoWAOHiz9Qaoa9+MiW0aihSWli9yvKWzPj3J8iAffypiQ+n55JM8g+pEeo1Va/keu2CRKPA/1Q /ByJV26OJw9T1OOocJo7SrqSaKWgp547H8BADfKdSWr2Z/m8vxfskeQusvs0JenLJRN7pPOyvcvG RxONxrv3Uxo1kuCwSMitElD0q9LGqPzQmQs/lJhY2TRo5N0yASsVkXdX1QwpGwtLJ/N4iOaAidll Xgkp69uE5eiA8HFnrgczUYPz12jfnjMAC5bUYvqtqb5VRt596SRPMI8FjkEB1m1poiW8aItKgmni +t4O2FGxM3e+LRIAq4qcVkcqwvqPybcXe2cMjx6CRtbkwwFSWYfdY2fUHeDG7vIsKivy4GtontHR iyUMp4+a97fFXULkjSBox2xX+P88VDtm0+SuGjf/DoYCZ/H9WRoTzGhGIP3uGWc6Jwyx+rWwEiAU +3vvypAThuRGLqq0RNjNJ0sT0Ea4JryO+2L3hbZxiEGRUIT7XTC+l1Ld9SqxNVZXyuYgjz9a9jEA iPxtSR51RMwW122OIRe+di0yH0B6usumFE2wVquVA3EUHiyVH0KUGLbkzCMCU4yBuPhc80r8uzgJ WkEhlHZ8T4IGr7sWlz+UEkE+58FVDUmIVjkOmUuLWxIBJA4vV9i9M6+Ojv9kJLsfccWi4q0fodN5 syq2yRwlXFXvwvatQ9NDsMQq9t2ckg+fsnKPwzbA/W5swQKZSqNJzvpldP0Uaeardjt9o5cB9E2g aiShHjqoPiK8FF/fQbLXTjgMfQHKvQLC/+2Tr566c0DgyD8d3ZL8vGubZEB2Cc/M9LY//02OpTlw yV9GJ7jZ56ceTClG3zr59yFCe1BsCzIdA1Thl/RiuoN3rbW9JW26vosl7W0iXbX7uMPuEmrXoBmn ps9MT8gZN1BLDXpHGIHQiCZQnquqU3GyiSz+C1pzM4dhOWBzunvXReW/SKn4icN4FPxfJ/27Ow0H xmzMThXtHs1MTWjjCPj6zBZX884b9Pp96TsP/jfDF/jvoLsQpqCwdpYrvul1QAUUjbaGzsoAvO+H eD/czY41GnSp5Mq1miJM8IkuPecO2hBGb/rivRxmtOt2pN/GBFeyMK4bABpSJijPD7umArl/tO1l oXZ0oNfp94P5o7agOxAi0xRgz5RaEdDBo8dFoEvPEor53Kxa1NdWVbeLY6cysW6BAa92YKZZPRV7 bkZHSaopdsg31NwYmwCDTJopCwv9obvJzoAeQ5ALfHKi7ZcHoj/rnK54SSDh0DCuHHxgCZvnvGEP tHrwVWzbAMdcOFCGk4Z2gt45xWFX6mCenwsU6Td4yW8+RoNOQDJUu1m9MkpWzHpDwOt+9mJ1c3Bs ropQIHntmJu3zvTphCkT0zAk03xCKbUgP+EpBmH2q8YWvkBN2DuWb3osNhjvQhXM3GApt+w2VV82 W415aWdRHmTC2akjTmxaK7elPmqU45cjzBGtCFhAFE3PBCsnWquVSI2ltxLGrUidP7MkErR9fYFy rwl3GjCTIIbpmE1I0UH5zJ2kgKbQ5lInge4NcUHFfJSgeQsfZyANRyqw0gqlwVNr2foKOmsn8YRv 4RKYQK69A+JF62M7iWszZjmhBU+qQMPlevw2fzbwYqW4WoRDYqAKDeRAZnmreE7Ap9DCcVsGwkjA 9XEjzbUUm4d+Tkbs+b9lWpNT7jK59Fj41ggy27jD1ESdTmGkjZXgUe9CkX9iSEK1qYyGz4JKtZXP TIPtUxxCrGVMYF/iBAiXRkTY+WkDIGWoR1phRpgv1ahMg5WaV513l2CdtkShHfEJ06Z/9BwxijtB ZVyG2j8IJMuJVz37fj4A8o550398pDGDeZfVBH9aWWiuf8fjHrtCQ6XY61Qm1qyU1Px0AGhv/bQB RrT2I9pDpCcbbrF8Fbcu3P7cbKRWDQ2TRPRSE5A0D0r5TSPH5ycAPAAEnxN2Ib8aYAyLk+pi6xSH 5Gn8WnEhESY0awW9CjRwReZuJnajw3KXNRJER4G4KZMI+Z+E9KSuIqwt7g/Fuw7FAruC3zOOsYa1 zJeTzB+DJ1HBEua1mCe20kUWtCjxGRMXBx9GvFNzbptJDnVaOlZ3mVqhgCyfA7Q/hpVEuc54V8XU TqCszAL98G2/XH5wi9EnT6e8UlNLqAuDBPtkLVNnqwhros9KMX+ABNd3x2wslT1zcgSLFeK2TRSv Karsv2kN+duL8eMRqnt3NAbsxUD8+y05r4WzUiADdEfj1LaDDGLIpSBYw9P3yEmsZ3IAQ2aujA84 Ea1W2V/fcU2j4MYnmy0ED2H8PTlJUKy8lo5E8ANDgHEWTGjaJoooJT9CBdedy5e/AbK/lm5nJci6 l+Aylr1Zd+ECMmI3Un7OHWbD6yuv1hAr4UAaTOCJw3s3DfmxOv0QYZUWGqcH8fkpi8VhrqE2Ewo/ PtHSqIj5NEaSyy8UgOIHjXdVq+vty2go9LYQsnpMi7K/51s27Qb8PdKbrZ3b0UK4aCp3zHI7JtJ7 1/y1dpf2pv+EantBxniRzgo5vHsanh5yGG90Ezqw+9dz57gpAcBG3RYafBLPVZU3XYzDV0w/bjky Mb86UKtB6QzC/fbYJaBKb9mvdfTw7lM7Hp/EtSwflP/nkh9jsaMzJo7/I3T4uBJdEsnGwq4o+1Lm /bJxGLUoyQomwJSUYWjVusx9a7uG0K1keamlweYtwtORxlOFV0PWWa2WD+9vY8W0mDRwJ7cJTTBp KHLTk0vZZ1CaKvK9X7DfJEkeKWYJbCulkLAaNu7ye7EVftorTmbQnm+QpUXst2SqDJ8323Z+3HW3 lNid9A/OYNqqdimehIwtL7sHccnnzcEOxz+CGiNlgOGAnKmxXvTV6byYQ+Ka67hOtyC8dEllvbgZ 1JiY/+ScNh+DI1dLi5F/MsLkQ2W0deHyr4KkNUCV514fbSrVHMGctCEw0O7F4N879SshAy+Imsfi nxmioSKq+er0vSvk9Ym4OKiEfdyxMcd5Q0WFrYAnaNtFX8Y2lRJanxCdrN9WNSMslqvZGd/uSK8z 6Yv91GmxQY494QWo9xDrHSj+HQiHMzF6ZNHcbfOEmhTKGAXJPX5OChcGKyEus4YELBA9Ys3Eyzi9 j1wn4GrjnYULHGbTI4MXXNCPSCSpev25i4nub5W+4XEpGrDhJIQdfZ0y4LW4/Zoj+GnU1THAlfq4 P3ixKgbnqMo7jL31d1YGgac9Bd+bujnYSpuagW1uUyDpOn6fg11iAsVReciXbdN69PVjGmSWSE/f +TYkKp8nw0QTrQy+TYUpQxFFxPdnJ4PbzHISAskhbMW8EvWXQqCGBOjdE5HxHbFCCGCzZGTx+A7E YaKAtmpm6eXEZrNKFcZaw4ANJ9gkpCaKymMmtMBMXcyhfPlEPUk8cWE3l60oLOLiwfS7R4x6YUc6 YOjKWSEG4ISqrGyXDQ/pnC2QKL9AYQ4ZTI/SW3NyoIZnTNjaRxxvYUgwlhhWPyQCD6HyGQ+/MA5C wAZlb7gEVE3ycoNhPpnLRqALmIOSk8XwRf7arFOVWxc46NbcC3m+pXMqxa6eL0tscg/yR+KlhjTx uMErqAs+QwWa9h5X7XufJfwQktdsA+/f1S7XcYByYKngfv8Q954BNxZ+8m+Nj37ypAfJSm5oEdLC 1oojC/Be8BYUS28a0hiVi8Lxdn3PmtHJRkLJ2IIGCrlZGkfd7u2VlpPqtN0M3NTSqL2+nKQnTv4M PdQ7gfVdKeWDPwcwzB3wQ5yhWQ3PCQcSJcr1mCpmyLHZsy3wHU+n2qK5lbf5f/EcDx8HCRKMkhLD gdcNZ7JQZ083UZneOvzqX0ChSvRYlghRgNYQWwEFuX9m4XoiHCpBVtye6EtBrIeffMOHM+dT+Pti CPy02+jUJt0B5q6vgjSeofkj2LOV6Ze06r8p27kax5D2+crvBBY7chL+OqAMOCmdIWUFNIcBtJjm nvxbJ1I0Ptf1bW79ma8kKK6/UvEaQitd3F6gk6eJzrIuWtapA2CsWQHeu3AlZCMcc3zioVjQv9d1 fri5I6zv7Z3qldIr0onXUWjuPWHCnj1vQX4mBvQFLTFSTmRSfcdAp2O07lfpx4b5FnLRBTQlgmIN NiEwiUorORAS+liwfB3zTbkReLDJV4zLdp9W65Ai1/Qk1RMFflPjqrE1HMGhVVeUWE+jOWrNJsDo hjSxU6XlI1kPxQ1IUDLEvnO2+haSlY2kUCmRVe/1x+k9lmi2bUQ5I3+qA8+guJthgcLu74hDlBko yl+2L3xElTy16gr9MiZ32+5X8EghZ1V+7TM8/8haPxa16/mDY0kobtLVTEeFVeeWS+WgH4KDJjTw fqoUhn4Vrc+BasAi3T3XZjJWWK72nicLbrV4MdFuE9ec29Gb70Vdr6fwHozsF0iiA53i0Ukj9OY3 zheTxGA7FtnuSvkKbkkfU3ob+aoOrXHHioVCKoeR0B8/gPsnB70QoOxBmTqHHadXMpMXO7/Ik+J+ 1On4opPc70v5aaqgJfc4fta35TBVy/V9zDSbOUgnffepLYWmV2Rcm2j2Mk3Hq9FBzc2Dj4QU2Zly ysXVtCOE2EkaQMjWRyzY0FVFjgOjx1FEddwofKJ9qvqhucWozjK/zH/oN+8JY37cKofUe5iQ4tYL yPaEZJJvHLvZm/SIULn0GVqD+hT5UnrKiNilz5vQQ3REkVUItjMhfz8A/j6ZAQlSABJitmvIzet+ n/5It04xvWRBKyIHy3LmHLnwGLRDUTH742s3MWNyh/lRkBxomFUuSVOWtpygNWuq/HeZ6vE+RT0r nvMXqWE14C+gXzGHhSC4IwKHdnKk5MzJsMK0pgWgm8HMlDVHUTEEfryjWkEcRgLtXfxEfA4qfcda SddiXBRW+P2FgzGnXKOoXhV9HzuJyHSS1frllQbGYA21lg9eiB+bAUWpzdtcbROp8UC8jQwSn8aS OhrkOoiurt0Ct93cWU4/Z9PNUsf5qp9Nko95zPOXoyOdtHzClG3a38DiJkx9aIksv0CPw1GY5Oo7 nWM4AfQb7UoBK+KPZ/SreqZ0oKmg/6l4qpjc05+AhrZX5rmgvcjOAo56w2r3Rft3avEacmCGj3Lz 7oDSxgr5+rFuVkkWQmaXfl3FNA8m7zutXnCCm5QE2PNd4jiGqBP3s83dGUS87gBSJQT8KOl0Cx0G P5POqyh/bVjc2+TPd/Y0BT7eaSsMhWFqUSlQ8NiJXfWrpswbZIyu1iyKkqr/xbOXJmcqSCYthYKF B3fZVeth2pAbOWssW2+Xy6C6ulYZJb0rDkHC6XJ0ZHlWfYYPXMbzo/AS0sKNzojJ9hJU1/3fpVdF Rdb/S9E5uD0+Y+tc6VUP3+7jBq42MvXTg6nOuSnkqQdU8aMGB7b/n5+Xm0MwUihgTGoTT1hQYfx0 ByPMqMdNyAkxZb0zCL4Pus4sJqwfue3JmFeOJzdBbwouTWSEg4kfSygBRJP2AA6mkbO8sT1ayCBw QEy0WVnszcNG6mFB+Xm/GmE/2FqfPBI9FbOkciuShjkfM63h7Kc6F9O04OuM7FkfcCZMm+a3U5YJ QRuIDOy5R9BlgH+Bbwq0/KOTJOLT5ukxlRSVyh6W3bcsxkoBv3SdNeo/QNrp3MApGDSaF3bzQYO5 u9BNULCKmS1QOmBSq24JlnsdYPoNcIcQnXZ2r01c+WZGbn3XNdOAd7RStq9VXZZtAjUQLG8HdLsr Yf84b0gl8zNifan/lVvyqUq7QSgUiuXH++8lfy3mJHs0w6YJi6OdLGV0TPgJOU0GaOGm1WlTlEe7 +2l1kUAdnAX6iYY28rZ6SiRHesODhL2Wi8klfP5S64FutLE7Zp1SykGkbzcor5JYKt0Hj4VXxjDT Q//2aEIdx0gqZ6DN4pS/iKEsurPQflZLNyWP0NmV0vpaYY5Xmu1dM/NTHAcMGXf80HpnDi2pzHq6 bjpCHARcIZAdYlHsOVm00e7M7DXhQWzECsw8HOt6bDiQrSds0ourccqESUcYAt9p9C7JbczrY7bB qun56x2ol7G52TFeHC5gpIex6VzlaNcqnnvVf/P/J6ZBsP1Y2RO/uYTGWD1UI1q5w9I9uskNMi7t 279oblJM+Heoa2hZkjrKa1CA+pItTlymRRn9ChXONTVZNclznSCwSfNz8REqxwk3rvqRX6XlF+pa ohLlUpaOBCQZn+YXdaafFmdmVh0nqAh+GpzAOa5JqF2y37avVQXDr0yF0FT/UAnAsR9zUam5BGk0 3GmSAiDSFHQVosdE+kBmzkx/Wdc2uzHpSALWaAsZ/ElRnlKSv1A97+ao4E/PB2DvmwGJYPxgvY+x 0QYUt5eIatkb+N06dRZM7jXXIM4NHoTz84i430NYCqCNf3Gm8uOxiUokxVTzasNJawt1/oK7zIjZ QzbP2Q7M4L8lsymQMw1dnY08h6SLpEGl3D5sdQDgcrj1yRiz4lvlj5ciEI0iXvToKRQJiBmox36q PsiMR4c1k0eKmzrZLKDtmlYrZucFwiIUkJnT0M7mjWY/nEJoKdLpEnAB5sbmKo92/jvsPBs= `protect end_protected

gpl-2.0

c4721732ed17c3380b3ae5ae098b2c79

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/floating_point_v7_0_consts.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block jEaotBaoSsCEFeyAT7WxUXTpI0Z11w/1YWBfojaczZeEVfNS0FXNDvsN/4Gg14slHqQN/tEo5V09 f781SYHfcw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XTasdvdudPK19YvvUZdWbCysm33KP9adXj324aEbIQA7zYe7HzXTyfx8PgMHAZvV9Gies3BZ6uAL tkxHMv+mceA48r9cvf6ez8e7WMxDO3AJa1FAIATyiWwap+4YpD7HBJ5S3k+xmzvcQycfgvKpFTua FocT3mLD/v+KbQgY5os= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block x2jm7gIK5Te4mZD/UKzexQF/H8We1HxKs4qOuPMiLXJLVZRMUIkPfbNNhXBdATh32kQ1FXD+PgYS FqdP1FlSdw2MpV3lCr7o/5NTmo/hPDiNub9K5kB1cZ+ytEwjx0IJPvPfhQcBcL3cjfLKP9awTviP 8zrloqcnyBRxE4ebeNr6VHlqL4wpTbpYMMdmS37yplE4plu3UP3hIyk2Oyg9E61BbuXPcy8OQEHP Ct2HWTqTfFfi7qCI0K/6l99MzDH74KlH0oYUbsIg+Hf4hsa8haBqmJWs9ou9vknaCwQ9V19xIfoN RtXGWx3uDXnNesKT4G3aFboBOz2n95Wu6JTJwA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block HbOrU4nWj8XBoEKoaKkDO4gfoN5RJru7ZBFJhQVuy0NL1SAyhEABq1POjLn6y9EMmZugZGiix+sM onCLmhmUU6ZsZnX9o/bMISui1OPSoeugCaNBbvvJ2DuWwHzJxegm8NwG9NvH0/1W7oXYBc/yjT3x iw67LWFkuFnSIYMqYnw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Zr/oNZpI7ywjuOLp8Q1rt7fJEwJKGHlJraPXvonZPB8O6oR0MeUw4tTYg+bUs6wSwFqqCqm2CpBa PqZdJAMLw6vyL5AZe+gQFwvIvkgA+cfXKEcEwbAJ0UPrniuJ4l3c3YaS4rZR8GoTQx2ZW7SdCdHq lQ2t3a9mh/cJZR6EU4pbMbZFjVraj7cJsfr0zrumXxgEqEnuAvtx59+x3i7CXh9c70JqJtTE8wzH o6XJbpLj6CqUF2yTrJX4TpxHIavq+rKBNroTfPURw8crL9RNNUwjKKh1NmQsFlPp01ptb2eJmC9/ zPdm5Qh8AduXX7xmQNKn07WtC56KgKT970s3ig== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15280) `protect data_block KUCpZIWNMVDXSeHir/Dza8jaEWffGql5zT9mn8uvWhCNASzkjEzDIgQwK4Hhw2qUf1znNximXbFr 5IVhvmgf4bhzyg2aAXtDWw/29j8ytZdrVXSqnM60uD2n25WwMz1HzCk99XLFZ+p0Ytcb3+XIDqek B69hzGWHU0A6ptFLkcz1tALE/yT0w49nTlM9ObPHePPKtRX8ItZj94iEqbtYmnLI0IBuBEE2R5Ym p8dM9pRAyT6ANGrCTPOTGrlWLzKGmfJ2G5HL4yGcvAMXtOrJJVqidQQ5+qrQEnEt3j6lSFFktH82 KMt/K9Fdoje1cEGZNv0/w+4nGMokHMBwqr25BOvaYSUBldK2ZYsMTyLO5omi3a1USvkwB1q4ljvF xRyc6Fj1rdOforAOrv7hskst1T+yuwd4DG/6SDVjyzHvNu6I371S525xMfTe7ezb9p6nSiiJ7C/R 5ZAI4lDHd9AQ1ZIzdTTaVBSGz6PUZ9VSdJhrwy8dZRq+FromhIv70vvPEkmrIO2XwySDMtCCgVgL ldCVTOGOxWFvK9z8gG9fD5HjjINrm+EK8U2k0NbMVLzx6qb4pD6bPN0IPIH7hVhFlX2kxBQAOaW4 3pIgKqUCfcVE0w2KE1/9i/ve35Tq69QO51cVEOW815ZjkVC3A2iP+yEZixcQ24jIWZFpzZibCjuc c0Fm68VjIcH4D07K3V634wEooU1DgLCKhqZC3ZtXf15bNgYG142EnCSNKcleD6zolon2E8ccjh1o ld3NYmzbspWIXrZLS5NeJMk7lRUjj6MsY882AHiIaqCFt/cBQNJbnD5WYiM1N9DkqqodM0jsjyUc ByexfqdcRS43fp6mvLBo9ZNL18h5tlCYC9aWMfG8TL0FLyM2CmQqViPw6LgatOKUBp2arrEpcO5c +PJ9jcxSnpkn/ww7vVBlpRUw98RjCKN6HRmO6IPM+z3laeOiIdxnzq2sq7ngheAylm/s38wg3YlV PBKmUFQUX3tPWORBfA7GfaLH5aC6bRy11UdatlZ1DM7Y38xm4A+Cw7zjIb0PK52SMbmlnh3hH0Tj /sI0ZknRbOyYE1F0FPXjz4p2M3pus6vqZQa/Hmfup05gZjbEZgSOXMPz9ukchfpZh0SeR7Xc/jB5 82pM4ogIHa21QclpxL9wvm8QHtNuhhW5cJLSqx314CSOjB633ioccArNucdcSTTjJd4JdQXNjnIY PGghQ95fLau2QQv0QAhWs5PLdX+7UU+4V3chiUVFsMY8MhocJyBcnHr07PgQ0D2Me1KkqX1vUk+6 jD4Du9JzHuh28PUrvh87P+lDlo2UHl38rASJytVE1ypOhCjX4C2Q0HlhKmUjWv/UBKE4YbArSTd0 Ohrh6i4FYFjdr5DmBg6H+nfWKOPyAXzEEgN/QKLeSuXXPvMOiwVKGreBo3BYmKHXILD/yXZQSbNK 0igFY+H/y5c9LjnUVvQ+0gcBwtbV/MJ0W7a6gR92apGDSfX/LkXULKLYUtRgH4aD75DMloKu20f2 vGw55s9Yn++NpMXiMhe8/WBlSZ9hY/IHS5SeaOvhqx3fb1+BwUUYbEEeUPFQeg1yB5khq2G7PKK7 tomRyWnUJwlzeqnvJy7fK0P0aRo800JAtahhy2tdm6N9b+isQ/04Fc9gqiku5vvDvP/dIvfrsMf8 OVUNHrVANMD1lTPEeEsP+VpNyYZ2cJvbBbhp192B87bMBX+EDQwhxzvNJfHMLPz/mw5v0vSePXPV BjdzVjX+gnw5se2VcyK5Rtd6pISaMMWX1B/1pZeqFtLiN7YA2kuSK9QzW7BsTtnty61feYE1W9VP QJsFNa1ZQa6S7eZwHCWqn0YLWDtrpz7b85cL8ESN7drY2k0HgTJxYfS/+F9lE33qK+y9BREj8lXC sghqA0/MZDUYdsYN7al+1xPNgrsRwSyGX/uKFlBeqm1AxNH0ne5/4pr/LfIJGSF9lutERLlwxalQ q+E3g902Ea/GWIk+n6MU/pu6ZBm1HmixXhepwO8psQsRvsxX69dLoP6DNgH+tUTHqHpcUPMVj5fh jDuuJRjn7+SctK8vzbJ6YNQKCLBgirLsT6gUqCO+0MGYrBJEcVvS++f9ue4aQcYhs/dlHGnUjzNN n1HGgsBLmCpNi+WoL0PhaZRhIIr9K/89eFn689j7C8iHSuZhOh6Rx9MPO9d6rXtR8yJzj3B1g8RF E2eAn+Wk4DONr4njXDqMCNGmBY4ieoFnQXqgl4UarxBUzrX3S/XJSFMGdiwofdudVfKDn2qwyu/J KGDIY4Ky73rHg0u78YxbvvrApQy0WJ9m3eSTioao0jdBzLetHZc6B96sTF0H5WY3kYGH+iq9ymUe kLeFTWSgBOUjHwijnJATxXcSYeRpWKXvE1wFAM3TXKjxcjW8eJV5H0YyTJpqm/RmWjkP/ditA068 Ap3MIkWA2WdZYm7FIXiDrpQ/qKmj5IuQBAOF6jcFCW87UP+hbWRz0bBMEadBDQUNl69Em6VDppIT CQHhAiDt+2a/8HAB2LfZx+7mH2T1jzrdrbNRVn0aOM4fxt3OxKY/fj/wg1S6QOa0+GOkQx2kdMAn z/x+gq7QonHqsYz8NJKiCdmUSiFNsOozhGTOEBYTpYHjYlqnaJwipH5T3QXU7shyXqpUH0gBlUjy h3VETdnteu7SiK5OHCDrSdIfBq22wFb/ShAI//VZ4yO7sEMDfL9rCU6f9rpzbP8NBs4MOzGy2LVR Q3UvHpkL+AYkX83RQv6a6uwoKmcAJeZYvgzfDPiZ+3AI89eX393EanFQ1pc2IStMWNF+gtL6c7Tn YRmtcsJqGGyPC5YoC7Ll2u38SSgoDo9RyBDio20B4Zy+EO5InUwqWrHmYQr/p141A8MOstxoMvbg mYmcnzZqPPzZO1QPtzx8QbT3JMJjqnx3LFlUqU1zoXd0s38fFpqIowg0KDcCIZitLCTswlYhrhhG pkc7aK5eVMC0E4UA+KSG4s4MBzyovqrNpcYE2Uob2n37TjBQEGHhIhHVBFAhzLywIzJ1cyHc46M/ QwTqNZMXrHYK+B5mEtsrN7fQpHy/iIEdvDQ0Ep0Ot+XSSxifSPjOwt7mpyyBsrRME4lIB0j6tr6O EMGeHXKEXaktNzjfcWORs7oYq8onJ27pRjXy5HqeNTTRRj94rw9SbvkP3DvtjsYI2VM//a9qvlpm I8q4v1DRQkd0tTGyg814hyZ5gDWbn+kJ+JFdQPaqCsSNUmlBZGxLPvysRIPLAl9NeodljplRe/Df 6BDhpUnfYZjLeAOXpPgsyk/N0mWoEh544IjAcipvb5kyNreDZp06B/jS6PawiStB/0veiWVR/fNZ 8fvmrHRV8D7gV5Gp3V6IB4t0XWq2cKInl3aSRWJfkfpLINSM1o2KLcbEjcoVehRkrrJ4PRs5J5pK T3K2N+O+M5qk96rMsoWq/e4ZTSDr9AtHq3cXFaTU1e1DA4xgzCF9egm43S5PnJ1TXRPYV8ZxIcSK +6YS+l4hvxtTLEO37pwhyBYicBLAfYLLuIssN/tb3vePMeMiJfdVmvklmbTTYgXtnYQhd1HmRhoQ lrlxGhTO5fvw4Fqi5M5UcvGXI5zP7Ufx6meXGgaWiWtQ3d1ackC76wj5rOz0U679NK5GGGofnW2C ALK6iCU9pqCXjrgnkw+PmkIvGFThhtGSSxEOhvBCa8ZGwRFS/I4Gn3uAN9sPCpdetVuqsTOVLfP3 ibpKgBrEe2GhYQVH/pMCwcfFM6ygtP/D1pd9fQ3mSObXF2fSJs9cmP8AlsF6iVbhB7QJjALaE1Cr UC4bGHEkZy8hym9028OvtTYCv8shuWRpK3AvPeGxyFzg3jnn1napUnSq94Oy9r54rfVFdvdxBmQw rVy0B9iRIL1UsUs8WP+uFvR8ul7zBijGE/+13lJ97o9OUkK9+CjTFWnxDMpOp5zToVI1/to4iO33 QG1fgmNNrDILTu7sBw6TSXRG1qtgSdeFvHdey69bwxUn9/2ZsGa4lFGSr0zClNwQx15uCUON0SXA ki6eXtRxl+mlKU8SlZIuBPFS22s9/Ifiw8cHtfl/JSsPOTSZXwfyNAvRUwcnS9iG+w2sVYGh3djR Xz2WwRwrRFgKssy3lCTsdehezSz/YaZe7nCruxLfKA0+sj6Wrmy1uq0gAcV1pdo+LR4A84whyQoe 3u3dhcKhbxvepo+0SDmDEVA+OAVMcFLe1igwmF7hK+rtxUC4nGB7hYpfMHDwDZh9b40DSuF5AhjE sOqWu28FtSuMK1iTqnRHU+YAxuU6bnO51XN1HS9B5yGJzQoEfuCvQyVdiDPI0jjFhCP7pAlhqsgi VDA4qxzVbQfkdpGnAAoN51eAPqlVJpcDf9Fo3VAdc1ytnquznOXZosWDv57vCxeEbmIRRC4LEor0 xMiE7UZN57FJ2Zyp7CQx9ZEUIZ0E/I98f75XuJ9kx7vqmtEF2Sq92iog9OQYuTIT0e6zza7VhH2V 018aqr6zrligakdxZzIwjg9i+Oicv070zSiqEoAm4CuvDLj958NmI4j3/ImNkDD81Ztybu4q1hPV FaM0OKRBJyxlfXxl54GfoqG8Zuufjk9drSMFJW36w71bonSFMni6XA5QOecfvuJE4WfFp5QXoh0z hLQZ9aEqmivd7w000UqTTz97FXIcJr5ZPXXvaMtHYJ2CBC+QhAMyZXwOg8AKrDbVmi1Kb3wywv3B 7XTuLOaYIObvJp4bni5t0cE/8l9SfWqCIyaxPBlUsZWIToaspzUF83U6Bl36GW76t0z01OiK6JoO 0BxT1n+1BXxxbjiL5PFKwE/CgKq5E4O4VvgDY3S1mH3f1yTjm5eTySWGHsmQIuI3IUu3AGEMRJUx 2VBr60035RB4R3N+JhZwDx/N+N3unH+WMCMGFkwikSm+B6vXkGNGiaNXeTJz50BScwzL0m3zz613 gY5zTbVJeUExAfmmRhv4Laq+9MUmEakQ/uoySkB3bnzGhfD+BfB8AToVXqEpg/4I0vTbHkguOI+L GLNgD1DYCBRUA/kPFVikdZb9QNctiT2L11eHGLWQXFM42TOqa66Wn0aZapvjV1Q2lgg+f1l4AR+a dIShEQGWNS5Torn2ygZ82TYdWWLe2mNbvZh5rk3bEfMQwLYQG/6RPV+SWJ4Le4yWMkdEodVqsam1 mmtUtBZEeh6AvUl7m1i4x98LOFI4gowNQlsLn7QxVHNtfv+FuagqDeS+Ui0IfA2DXTcmJ+hdu246 p79CaXNubFBWa7ztVVfGA8EionN2+ft3tEilLAQxkST5b4TBGIiqxQGeqGBaqR55xormyHzH4Xmf vcJ58KDhH3xtrhOiykEcnWfRSGkRGvTsaFSFVC3Ot3eklSnvfXlzvxuvlU+JN9Vri93EnTD/Hvvj CmdNkwTyc4HCGw/bqJuSLMqLnJne2mU4rMg6LWZRek1AQQxTtFY+V13WzZkRF4Z4v4bXoI/rU2Cm wL73FQxhkWHz7oHYnlEyh/74OuvhG4RBTqtUusd8lqc7qVV1ieeCxq9NzrMsTwYmscqwYU1jB8P9 SZhftt7dcAddSZIvmXjA5GT0nowYQwmxZ/bN1Tjler92wzrxm1KVEgC0yWRQWD/xKyyCdht60g7k MtmIIAXRzvDhrPMHxgNfc17I3Nw5pDkU47CWX4xLSpxVJ7h15chi9DqgySv55HTsqkLSsJmjDB5h iYlYPItQAyUG0b3jle6kQklkksRNKFKgrk1h93oXlPH9tjxgYguLbDIih6f0G5dKYSg2mXSstKCO mQGPmEpD1WnapLHMI0M8b0IwVtsU2pce4Beo8qoaG9E7Gw4ixoS/WqE38RLKHgKpcLswbAK8SzeL 7z3eIWUKfoarGQvqcu2qaUJrxe74xK98wnuEWeH/ZPHJdGAyX6uk4EPhMD6WtSjXrR5sgZ+1HwTB CsJwnmnuJie0I5D8p3axx0k10NJK0bExMWZnzmAmiYq5iy0HzMwchl0hhN91KG1/Zt7Bd/UR+O0H yl3ARWFy56nyyy3yH66o+JdU8sC8I5e+mm+I5dXKwRralVK9NzxlN636Ji2K4JTqSisl1g3XH8k+ H3pyzN6KYJmpQXtGOHIsaeFiDC1wSZ2tfJZV07ljEigv3nc942hCWJyGaUezwvXgUBEJKMBrx47x MbTSwb/W4batxsBib7FhTTuwfVUkGX4bLdH1msq2NkpUxn+k5jyyRSTD895c9/D4uavXdjV7+Ye/ 2u9t3zSc7k2U9YzlE8G2XRUMomI5CEeGoNlFxZIwwmWy7u5DY+3pm2IW1rtVRXVlOjkLiKlASQ3B I4YwP1zu41fGqGr6TOAJe2xrKw9tCdxR+f1QeOSb+mIxhxDYC8/Ze8RpG24iX2+ZmHTzLRDl4T0o 96imdNFjHJtK7C8oRjG/kOA5U5h3DB27Qp/gPuAlIZWlxEJJ1jeTFer6px9+zrZjNPf3072nZyCU a6/OUqQE43qkb7nitH42TOLbrjQCpG7jXNiwgiQK3UkxDTSyCprc+zu7icmHAM+V/CAhCQalSVQe IlHJGTbts3mWUdVUXDvYCP+7ESbWCONQ6KQSl0f7QJ7lj+lsUWloo0Bz7n6NHrvmU3oyxSiECS7E ZX2N8rEdpl/hly7Ioy9XcXCChTLSXDLX6pLYmOV/aAdd/0gzy1ZGmFwy7mh4cXPztaQVunrDDh/v vvxPdoN/ktnkT9uy0T+WCyzvcMhCLJ8V/p5nAgbjFFaDhpO0rsFkRqygOCOy3QNLi3GiqQPHskty dRg3m6GNAmTahTUKk9EyQrZ29Plv+lTCYUZ7zjQfMnmk/ZavcVpSDLbFZIvsOTRdDBWxPkqa+3gx 0ZswncbmQXZHNdiTbw2vZzaE6K3t5rrDIfv0UeooWZYR90nxfu0txykW4Zf6d1u/bVmab4d4/Ejb CI64SDrT0xV9kkOpaJTiQIA2KmzlzbdBOHg/c+iNJU7kXt4KzHOTpevEm87AAMKF6fcXmVG7Swuw 1Lc94HMUdSs7uL2Ia8QF1xGpj5yyyMcVNp7YLUwexTFx3Xfg3/gU5M7imSlXfUeIjjZ43jUoXCVy W8FZVNvJyb8jQlrWye2/ENOoXQGFWfTlyvKhYEonm+LCEpSl7AiYqKkSsNvQrMd9fSzrcaPOrxwn +iXgEmI0wxtvVUkEktONYJNthjo8CswcE2TDF5G3+YuFqAz1XGhte5BPfU5niRH0tba/Bzfn8ycn jWinzsysb49X/jADfkmeoxqk2uZ9sEHYLyL+CsRAJwPyYWJV8j50nmGNJlLKfURVqrRAl8Q6rxiN MZ8BnGLUlsOMeRpjcd76KR+JTxfpdC0Rx8XyDnEMzRrZWZX8Sd3uvpkGt7iOPthxyfV3o9BT6VoM ZLv4zVSoAzu1ixA527s1hUYvKpjuGOiHSoC89vhplsytFLpqfs//OkH3uNRKNByharFgXKnY5H8Q HhYOEbgU5ZsN2U3FrPE2F2VuKQBI2eVbo71qPM2XZ0udT8Q0bpUd3+mG4kJxFDiDUIboInH2urSv Uk+x+odV/uDCTmJGUFzbRZtYUK9x+pN2z4vxmPb1vGTRN7PiKk/LBHnYWgQQuELPSMRuCl0XB8ec +xjWyTwYLYxiZjnBl+AgTRGhHKnlUXp0yV5A4hR1w+DdAXDSuhwpn93ECfgAU20nCHWoW9xDgnnn 0yPPsEdt8kzsaYG+yaQkOTxiLDA1uA/zrtr26jCUMEBme/bteZdNPEOryxVaPVVSieEvi4rUy31W 6F3O8DBwtX9wI6tq6oD81Nb7xsIVHMxth6azCBXJ5JAGf9Dc+4Z3hI7g1yjGaSPJkPZDgNDTX067 HhE+UYznKHNRlgHIjUovtKVnxCr3NcvswWr+FLhSmFHYBCyaeU5mctZAsXgfBFAr/WZZ0gqnyWUf /DrTenvyfv6W03nf/1I46tWMcIJNMOiJQVMa7nuXZukC5wC4aobd4FRcg7UMuNowQ7Bviz2E3bsy gKfAqqcILJigTL9mfio5SqTS0130/cs6v+jeO3qlfhuMV2OKbD3etk7PtlX28iwUxVA4+BTGKbRi im/05W9eGJkXYCqW9lccdbMru2HfJ7XtXAT8oudr6NyTl9agKQgohznVhL7OLuC5klUxCyuJJsnO u/xNp6ur9yRfuREBmRO9d0zfxwuhrkpLHv06jR9PotZ4cvwPgH8tjf6tt1NVkRLafYM3xW8QIRXy U5HVew9j/POn6unXHhVu03iHGnxuQmsPxdc4XsxvU5PYx7l2dj4d84E3EAeMNm4zd/vr3X9CVKb/ e+xiIZfWDKvXTSVAtE3AhUCMrTY/W4Z5QJPPaoQAdhvIlElOxWkOEk1lSwwPfz2PmhjePB4/9lEP L+PwL8fxuF99LeBugqbJHANcllSdEMx5z2tvBMR9xWdgsRwT7Go0Hf25h+0SkQuc38xupLP4cPBB +JpN9pq4OZQfcMERUJ4XPTY78lPUQ7/fUB7+raY5m4qoPnBtlgvNTD9Iyzy+Kh8hKzvtpKlo5dgc 3d4E8eGK0V8bVwxt1cJCfo2PAY+FXoGvDk/wzgbZ9LTsADCNj0N75C92NmKW0EF6Ms4WbsCeiZ2a XdW8VlVjIc9Lf38iEkeu5xPlVH5lGu0YMpV2eeB6FnWdwmWCyS8P2WzmXVkAH1LBewkku/0vZq0E +chtft/6ycy2RzTvEWoqoHmqqr/SXbyShfyonsoz5nZ0uk4C5hAdMDl+Bn5DZYo8qOWgG7Vas+// xEKICl/dehn0BMCDELUDwmmp1cApafLVylyVr2a7H6Qd64XH7ASKvjUQRvg7Iccq0Wqp4Rf9Ydsa VYdyONgYYqekjwpq5coLJz/y8KiXCxrUhK+9NFw2zLDR+SKImOFHqHbnyTNvZgu4gOGVWTPYBf+D aJ9dpcH++74PzbrhDv/V7+cVMJHiA7kKjYyyCQ2zV6OD5OnMb58yWx72qnPnZHdImEy+PTPFd8DZ QkxjhYD4dx7ZMQkwXmEzqFols8Puo7GwM+p1+haaqvNF5MFJpEHCB5BilshNsmzqZFmuhFo8x6Ad eeC0sxcJQdw+NDv7ZRjNtja5VGq7gapt2MHJ8RRVY90VIv3CMTokom9PzY0vPPvIkQQjtpB+73I1 TxBorOl7kkeOj2L1jJnBG3e7xpcB9G2eNwiOkR2tNReOqkS7kb2Ny+H4vD7Mnn/OJMSZv4kjF9wa NnTzYvN2VB890lfvZ7QH3tzFZxw3i+7JpRvGkcFe1QCzRLNhFL/duITahf5GBJtATwxHxdtK6FgX dR5c/lyAo6ORDKlQ7GItV/iVTEN0orPcU1gRXfVe82eMzI+tMwEeeD1N9Hh88fr9/ztTDZyvqurf kbt8Ym6APnYRlTf0oZdVMBZwT2uGgh+3p3X3ONtZfWrfrPqBadGVaticLzlL/NqD/Ee75i+vg5bt OU0J+4MdGqmllHkf0xI6VvJVO4trnnrZFMELORs/hiGesNUP8N4VvoVZYTUSXP6MKf7Feyn91F0o +0mb0UWvB9AF9b/fcilgXb9lvF3vJ+0EBvn37Gbok58CdqyExW+XWkgAZksOikVoX9buEtAqMhsd 9cTarExb3MP9fvt3sraaMNAsO2a5mgfoWYMJPLXpFbeGiz+6iAf6A6X/nys538GBhmOLCPkR0kyd b2pcLkdFpYZHBAiEMj0xXtwlrp9h1SxRu6oF3sn4ZjKkjnlZLSBPIYNo7r/sgCt61eU7FIysRPfp LP5081ztp4KmG8p37ExpVxygmsR3SlKRIgu3n+NyDjSBbOI7WKD1aKiPSbyN4W9fq9eUxH0p4cAw etYMrjazNNiG3pDSeuRRTV19xpBqiEEbgIUdIKeopUP1YfXHNkFoSs7Ipj1GYenog5QH0zK35JcT Yi4KL7rp+Z6HzzHJnAdjeVGUkVQEPdfr7e4iinvQ5Oi8B8eqNtt3CsszJsOx9beAAZdnbiqw69Pn e2sn7o0i1XS/duV1cfE9nhSPtikFrtEzJJg9NyVybySkYZKxIxY12xm3VVawCXEoz1IlZ5sCmhj8 3+PJtuW7Jb/serw7SjcsbYD0SrAzoYpm0jEFSFHyTiU9J+QpQ6ocxnfhu/NwLJ17/UWtF59xQ1o+ oqtHyP/wk5WyyW19B8M1+nPI9fVSlsxOxihA/XZBKyHe1gVR80Y9kqOpmoA/kQyfs6HvhcmLTAO6 fCn2BrP6fs46806j0lwdmsfzvlgHoNVS9vKhV/LOb0+gf3xjBvFqbO4iimaDtPz4wxogqZQAZkbB EO1ZOFFhqIntM7URXvrm7Q+zY5gBVWfz0ZUubqoANkCI8DM/roZkNoOnbbaJhzlq7bRJgu9ZSXH9 5v6KHcXGz4b7G9+OaToD+2kR9mHOV6DSo1aVHCUPQTYkv85fNDBBH6W08kdTFHMFtVT7SWOCyZ/7 ZPzR5S2J11KmgEz+LCRnjIjgI3nAivIP+ooDPRTjlv2/l6UjBAydbh1Bs1QX+XdrXPXa6EYCEZOF tSfOZM6Arm5hv7k5C4q3S5sIhteOLjtSn3OOaNHxGd1ODF89p41UVyHsQzqB8vRdajm9iTOJfBfj a5zTHOzcMu1q6O58s63DPYMjqlSgk/4Iu+kzfsLrOP7e6zgbXQXuekwcRtDXMBBCPzmNcN/yLi7v kV6tp5XP2qEPODtpPV2z4YUeW3nSN+9PC6oB98RRVMIQ1eBQ0bcDZTBF2ctxNXd44QWYEbGumnyX uMvs4qqW0q45MMx9d/7E0I88hdeCfCDvAgpntE38A1U8el/OK0A5OwtUA03p84gAoR6roUMBq5ss /45N3TbPEMyGgvBOaF28hJka+Gbb3lJj05SZUZjhtTbgmcvdXAy9Rw/PalBQAXFAeotwFr95FK5z U8ZVRy/EJC/gGAgqLu5fGs47yqHszXEb43gpLkyLZfUk2f3LJ1N99doN9DwpYwUBh0xRlKyyHMCq Ao9htSFbtpsEoU4Jp5YvfR+3jDq7W7VxyWVq8ootE31IeGuYFHhU+XoqaTjGMHheJOSVnuwAwf8H hNP3HkF4giMq/P0cPI/0RgqRjco1fOzgL5DFXMROh5NjaZajT93VZEyymtdOkG4w7sNA3cxTWErP xACDraOHhM7JAZuEj2+l8so7gOO4VnXsFvE5qaca+ZLhN6Swr2gF1Fk/3Ua0pPx+od7TxpLXjKvE n5vhh3+v8bfC4rFWdMi9I6h7VbldMwAongn37Yu1jpzdwyHDfLkc18O5YvnA79khcood4fNPvtjv 8BHmuTvNkc6Tk7JBh77z3NsyaSFJpGIOX9PFFTnar7B1gkdpFdx8HyddGQydV9GsOBI/5u1rVQXS ML81EeE9Qttn89wEhYXrTsi/emLPxa/T08tz8klrZzEthjrkaYn3WqwaCcGivFEJh77NHh/SvCTh MOvlc2LfdVl+w6ASCNWYRjloWucIe18Q9fX1FjjYrJmYzwCOSmEZ16YaPhCBfYGYc63qzk4D2EnP OdQMphMeZaBmmVAocfp4e6P788uiDH83O/6nHJwTb2ym1wC9yXNGwTB0GfDJkfnTt9XUxxkat+t4 ASmv9SrymPkifTBVPZZXVaQVYVUnu6JQp2bVTpEFkNZ205RRvBg1axMi4/XNy4qbOo9liqY3sBDt t7TMCS91n838aCrEBnchfVnWoMZBDHBaXQE0I5gO9uJctqr8y6UyHIVmWXjiYnAEry8b8mxcbek0 ihqJU4lhPJSK2abUncOr0UrAiknkDSxJnf1nSlkxqi4qOLgTl5hPee8Sv+jIvvT9AnrlKv9l1nhx Bz6amPfPD/FBILVqItiJalYu8nm5CnkWyzgcCIY4n7DU4StuncJ9W/J6quJNzunvZfdpSNhiRlr2 W+Xizw2liuqq97iWRATOsHVlDwiaQMM4pkMlGvHbQZRPPnhgZx6kheksffopmqCipVIS26/um0tY Jld21yEUSKBNFIfysjU23gBoldmYRLZouEJdzgiRG0XfuZCL+eTwteu0XrDb3dcQ29qvVd3diDYb 2bqW5L1tpr6BgAS6QWzrbSy/zmxW22Tbf64M1xQDaDLt/V49PdDnacTLrVxyN0EN3Ox2ZQeN/Gin VXeAbdRL5IINYvzBecYb+WaI/y2nMvBLpG8BJFveTxFvQTuOLC6+NlKldLOK7e/MAH0r5skZud9V GXA94atsln3l9qWKX/kqhquZSki8vqWCNWwb7uJGZUrrW5zX3foKKw7XtqQ5lCGx9m2mh9vr3wC3 nYziCJGNaCJjTE7ejy/KK5BRk8sWN0dMcxcSSqtwBvMR4UFkwBRrBJWyHZ8yzX1eniUpPzsnaMeS yrn1h2nbZQVaih8DvWYXyL4hcG4rCv3daXSaySpsuMLfqGhgbTifBF4qo8h3qbyWiTBWn0dkeQa8 rAS3eZy8va/iJPZOkj/bs/DkQU+TLFAuw1Zh4x9/8l3FDZmC7EMmTN8Q06S77nh8S8jP40i9Oats 3zGG/xIt6MSuOr4Fxt4hKoQfysvIgnYt1zs7+F7hzqQqaKw24r5oQPHcCyedWuy3dPvRonyxOgml cnf2KUTb8/BinnHZ3Q4ZidfmHI8pzbNcxkhzB6ToWwHoW5CAQHDak2UqGzXRJaqIWrqkZIi13GqG lECd96rqbqjGalt1B6xMNJ+wbr10H/s66uKow5ADbNOcFAL7YFf1t+rJUOWp1uX3b7zhWtMYFtPs VkND9+qcvC13FtD8t0zJYd0Y5bcizJQowaMe/6dEoA/f84k6ykS7F9BfJ4L9v90c0GWKdRXbDyiC CEFEtkQxOve1uuCLYcyCOzKFOeKFrPZWfsxPWMEiDXVnL3Ib7/6m+EWi/NNeYbMIFZ44QDaaN9vN C01Dlm/3/xK9HDo5MCmuwUtaozQVo0V8lidABR45QQwfMSeqTB4EQ0bokUZ9oyA7PdoI8E2CH/C6 CCAofOcx620YI+gI3UV9aE9MB+2vxpiQPTG88MjXmelTxKGCD74cie/SIFkVIsHiGt6VOBe1al0I gncMgu2hWIF/3jfejIVuKpeKxxKFalxSH9TOCR+FjjQOGtHvrM+nY8B52Kui+pQ48u9QzScci5BZ h8wVGs3qKozoiwgvO+7L3OsPY+orLZXnXQau+ndZf39uOMjqBNvnqCXMeRCSZltr2O+lQcCJKhai jrlLi459T17JFzE70vVK/apT7rplDaujSbHI9hDhWiCvwVmMd7cPOnpTm0BTgSr6bQJYG38Fz5jY xUxHgYGyBqG8pUBaHDl6WdAZf/F83RzuzAa/+Jhb5SVO9GNjZ9XQW6ZzhZThrc13KAmfwXaKLwDc LqyOp99ArdCWi5Qm9XBCxDmZ1HuP4HIxRQoBhPrZsHbVOaBvZ4IX8paYhv5cNAQn4u8ZTT7VZt5V aMZ9Q6L7OnYTLM0AXm5ry5BNwGVcGTePr+S2gDH7WU3hLG9tYBc5H1/s5hh4jddbO7TtxejkBrNr xUkBaXby4IKxlhh7tnqjry3Uxgz21EKHEcOEDOAliGFk7qic24yIQT7AWNHfhbs+RdsdSc3k08xo WHbuNZlNsG/LvMxO7XE+Q3qzNkDGXNPbLf7sCmVdh/Un9KHlVWSSVF0n3HBRLl769nnBMhRXza8C UGcaz1oA2Ec7b/LazUNzPzPDIeAh03RZZcux4g69fiv+wNomIivYI8/FLpgx7vb3pbMLEDelRjKO kYz8zxmqVSSffc/CUxFsIogI+UFTXqKGs83LLbLhnAoH2kkAgy7GFF47vyCO12mNxm9CWlTjqOeH tgkp4CEzC0zgFRtlkF9cxX6IiPRztAhyVUmR7gMzK58lqqjt7qU6pZbWXljwvr3DsG4FcpCu6dhO 38tL1knn5h52PgF05NZgbAt3HYwnJeh+RgRmOo+x5G8ROU72slKf4sT/j9jJYvT2hQ+yZmsHy/zV ubsSNkfUog1+ky6EDQhN3kwFR2oEh3cagjupjQwtjjso4rtibfIrQCIe3Em4MEvztqU85OEqX1g4 0hD0a6vPb8KAk6ti0cDTvlCN8duX/woA31mW0Gm+RThGfRozrYlt9rPFW3lFzvcChmt8785eJaP3 pBKhZc1vXkLJOIKBqfHCKenneVt/pDz3+v+6UeDy1vPXDNSzG6w5RTutBt1jLUdQbOUo3ABP9e24 Wh71mpHdpGn167MluSf+/2eTtDk4yzUT+Ebrq34s3oqVEy5RC4cvTyD1njsnoIty9bNs107I+3b7 wdGMjDRn0Y9ExJYh84Jt5KfTTJ/eXllghifFf3IspRWK0nqJN9BX+PQ58oWNmlPXIHEHfxZyY9xK qWr6GsbwzlHgBS3wXbZ3uSy5XY2vC+wOzMGOtlwf1JsEIq/pNBYS92EGqPcwMU2gLTw5dHMYpSR0 QVEUOu85f4J20oGuMdjSGyBHTle3k1yw11W6YZy4VdHS2d2ZDxtaFxSFmg7im6Wzf4ZNd84zz2vr /2Cg2wDrnVGGZR1wwNcWP3836o3+M7bCcJGq/Kh8X5RyKH2zMoXpFEaYHRftHZAP8AVfHBbhIwiX xFn/VPB9li3F7iWUOIbjwcRw/z3vx+Lw/8yVCYVMywrklA4abOibUArVNb7IPoqHKfVIgdeRH1Z/ xovUXjxOqp7Njm7Y1a0AVeEoOs1Zf1EByuM512fPveTYD+0OhiFgVjTU06+iOl8vxJpp2FSu0GTm qtWPPkDX0MSJ09od+okr91KlIY0HYLspG4T318qM0Gxqn4J75Mhm8xPdWeJPZGC+GqbE66ixXbvA WsEseSdKdMXL2s3CowAno6Ue/VATTPgw/XG39BGobfTY80Lu4XFMMOmpcXVR7T9g5Gux08u5W2tk jC0QBxb/ktVZy022yHq5Zu3WOGCxpacwqjM4dmJeqMRPR6WgaZ8RCxPJ61/XUoq8rNQpbJ/LIWyf uCtO/vTgJQ6CZvuL7Mv+cfZfONhmO45lZkUMhkTY0bC7ooD/6hEDBg7e7mM30cVpusT0Xu8zEW7D ztDZWh2NTQ9pjFsIIGNgwe9iVfChndmxzQfB77nrWJ+Uv9XC8KqDTBlnNRr0guAJna5+QACz87rH m6FncIItgQinRaPt8bFfscuxQ0dUnFH1uNiPJUcVIJZE5i9n0B/N0OPbgLEDeM2cd9bI5cvUH1pT 4gWEo8sYVTs+I1L8NXh7IsIa26Jvwkn0e2/VVqVoDn1VwOpYpDIzp3v5d0gvzXTZRzZ2rjRh1EnC UJcTSnT0QAwRBVN9W1JNpFQqWykScYFPfeBmMszi3JPc+o3fiMYV2nNb2N/DopFY80DuvJUMlMYt WNu7GRTuSjYrahb0Lgo/Yb3OgVq+B2FWyr7rknPYz0fqtmVInVJ1vBdEZuOknzYzZ/uSCMI0CdWu LrhY6KxWjr1cBhmR6lYefZx0EyADvd4x2HeS0ytfzgywke2ejM9J/rtc6pRCeYY9V1NcQ+YGQz9i guiCzSl/DxloTckiuL+bnGjDEMvPoz4+YU8nVvTrXkjJ/1hxPc/nATFTXVOAo7IGnfojwsTJedy0 ehMpFQ8oWvn8wsNmf5EeeYKggKTrMN3FaEDwKLjr+ih0WyDvx01hngxrSnWELPIoPiTaB6ZYotXZ +/rNDhdYE+heO3/K6GPSAiTPwuE+KgrTPXbiXszLMQxT4kDdeJfm0o4Vgdc0lgAeJkE0mxScsegZ 580wekBGxyt2k8Ynj2auQSrr3ROh70zb4ItVLOGI7pTSxqjsOZ0cW/A/hOKPKgN/Kf4+Jca9Y1O9 e2Zl/7R1LoFi3hqxZneOLkmnfnjnesYGUHmTqauf/dg41d4LK+AMx0y1mUm8pWJI/4wKlar8np1Q fvmGp3IdC47lldsz4EYQ3YygLBmCGDisamjs2pSMxMXXnngtlvfj9HuzaE2jmpDfVH0Rb355xgwt rfbmUn1oKH+qqzpMyMlVQWi3cQXblpTBpdxcOkPyqpGJOYFyEqcU7aRBWNgLGO+Xwu/1OOAvE2lI 9UK4oBmey0WrmN8uHs5cmRvABuZdG56bOWlhRIc4dZHrDTjI642CwNFjJzETLUnMwLpyKOqCoDA1 vUrMVzusuflGuLDM8IwoslblkfgYqjN3m6a1zt8dzI7K7/t09QngvTjbUDa88csrXvHN95DPMh+b RS5P5+KPPmNXqvivqQNaf69lEHam2Nunl2QIW+jygkS5FyAmeBx8L8nzgdDW/HE8T4EUSjoqdnex PMK+WOZ88EU0awrbUaPf9f0OCXnvrXxPYTa4vPkhLLOLfrfW9RJaEP1Q0HNreKAQaBf9c1cUXYlr 0fdO4MwPEiiAMnXNeAKAXtyfTmfCB/wS3t02PD3EyH7JEqVlZFogRWESkkhI4GNgExMSgxd5+nAM E0BDaYZZ3Fq8BOaoHy8b37mYVYZMlwKQIpAvMsVPmuZ1gsKIGbS6c6BwgQoo/hQlu58q2ReLigLs 3fcHvLCtdiVvCsdoVMjnTueaZG8adAkwBapTFXs+UsXdpuYfXxyb9wlgzx1D/3rnDrmBeBxDXJsj 5hT36SW9jG47nVen8fvBNDn29oZLf6qJYDefWzHRjz2v4fIArQtzoJmGigSaojSBVH/lT4iMByeh t3pehs1GmJ7tmWv4lCalb20BRcGtsox512fgM9t4Nmt8dpSSI4cu8LQZga+dRH+++9AyulMEwqBg WM3CLvMWhJPmeKCSt52E8kAWFRIDCl0qEOyOJz9vE0RQFkrzbEecdtrc0sJ8Yjoq85oJd5ShLu5u mW05JEDjVsCi/e2iP2e+4vIDGFadmigzC5Cv3EGgrmTT4cAH+5nrg6UBfQzxunq0xC8OMUkP2sD1 keZFdBUXDCYwHQJm9qK5oQ5UTBG0rnLhOz2eG061iqgPhTEdY96ter85fa8imeFSGVg+yRxzY8hi VwLVE+Ypwa6rK+FVxIRvNWHgz6Q4Drig5tUhYOGGWJuRl5R7edXrD+wPgQ9oey/yz1vhQ0p3HVwR WaNmeFgneSCML6O1WrhnFbAtgcuRX69OrhJd7EwNh+6bcitN4P61xlsksLYH+x7u5Kbt9fn64Knd YjiQ0EC7q/sdDoODYa/XRURnH/9P1pUWTXDUjEEpHXBamvEdEU6kPW4A6qrFVwYVnzZz2fk5JjPC EPCf5BMFE6C0xJG0rSl3QQ0PSSm3W4lWIWIEa44kuTpvAhAWpd1MVg6kJAWakCSIAkWHl4vuxK6a iqz9e13e32mxke+L4/eCxcv4txYcagbPK9tFmn2AXZnq5M5fd0KeREFCLkKYyyfJVKbfX1SgFO+3 IODLhjj7CYACcEo0GPLemWMSGaXhO+LijTJTkuDPaL6YNejt42PcGoxsHN8+YWaWrcyOZ635ym1+ QU/YQuJEjxwi2wR+G3qIv6s0V3spmSyk4+KmMWxKsNlapE3hsKmcdNFcQH97CasFZ3ijhd98ZoJI PL+51GbX25qnEZeReGJNos0vFBb5PKagzE6ImMy6k/eXXXUNoKnrTCztvpjUwlboOqGcpvRii26i VSjJk2PrmP9DD14Qi+Hxs4trhZAfbeeiQmUpNj8RWMcG6d72m92JeRujk7UmoAue5bXGtXEYsD7U 9O+Gc3LpQJCTdCIZySSpmbXWCcjo9KVAxoVoOIRycQe5oNnTKCACVYPdVL3LHOv3Ra+spta8rPBW av+AsIsjzK3DzS+sqLoQQoRN1BvrsDFkJErk+2Fa5MwzEpXlAPClpFve3UUDaRDT8r4FujO35N4g gasOcoaK62GtZTCq+2UV06WFskpW4db2J9ZjdkYg4NrmfwXQhsCs4DEOIhgTxB6WvCU7QP3JTu/Z 5K3NQ4+9QQ5OIwWp5RN8lK51XNO/YtZFm8wk3V/BTxxvpqcvSwfoR4ywVs0DECdFYMotAc3JNgaM sUJM9Nego5q5LLmgqePcybUZ51WLxPc93qYjbRBlaqa0iT3wtRrM7I5jUKXmVYosOx9On81pzBRZ 5ZarHS/7AoqPIOxgBZDc/LnmzMn5qR0Y4GsXliYtACa2/MUTXvsRfcapc6DfB4+IGzSxt/lsckLf OxBvzuJeycCzY9v1+OvDCbVtqcJAQGR1iKGz6ACB76yjdKlRst5AA1S/BHqHOR6mtTlYP26Sk/mX ARlOfN2G5n2Fd97Y6kT3bGvEMBWdZeK0d/j4JCC3nDtl52D1hvqK8s6lBiQ4/XljjTrqvK1WZn7Q KZnaObjIhNO6VefQ7QZT4Gtm5jeOEYS2w2GfsqRtfgIBkWtNQaFRS98mV/vU8SL11PLynnq1bi+5 HlfDVyOcI01DYmIWIQ6D+u6FVbLkuppt6yReVTKeKq8I23ufcDW81hS8wIFrso5GVStJis8pcnLh 7mM0snPhohLrOged5++HLfLtDsZghWGfqXbIUJh8UgXeFZbljciLy9Dv6u/ekpoJpGpH8pu36usK AdWnTius12Utts3IiH7ZN04hBl0Xo9LlwGBoOZEc7TFV2fQxktrVQpBV8MCVycGBzQ7BxflwF/L7 LiSzZ76bPmeuWN+obexpxXIF7uT1X8O9gEP9vq5+gaG3Vvu2vFlO2XLQIgw4Bhc0uZUUNncwWW86 ZVqzDIEr55zek7aH7u79SjFkVG4ayyMR7ieCelOQ0nbk9lQKpm92FKKYszYmdSDcSxz+evpf3Dl1 QvVPJXjmXGwIjaVXdaq/HS7zh0fL6Wx8mLaMT62o+f8dCNkJWv1PZC/JIGIQlx9R4Y/X6D0WwG/i eYhWfgeoopE+zseZC+WtZw+CYRDwV+5waSGMcyuJLruRFwujv410sROMkdGbMOZqjwm2nlWgqbnB 68u7KIbIOz0CvT3m50lL4rwNyj8GqTr/C0ztuI5QDX0sE77UnrBCGaj5Hv1Gu/T/8Y+K8T74ywVE qXAdW0u6uoGgI4Gm03bO3zFd9sQnXF28h2LD/NwlfgIz4KrZTUvqKjKMoXBFRk9cXRjMnbf69zNM Y4t8YfixC2NNEhJZP4NfB4XywAsascKUpYlUgc7RamKVGg3EUIB8iFbNSt0VLdUukBjiXTNduLa5 nNeITCFerCHRuGmjpNSdowHwvBcDQUf48A9YTig2DIT/x9oEihFfe/nBo6jslgRwa5oQDddxxR5t Bvu2bmq8fhqRR3F9le1nXXcz5M7WRSHr7rC6gq0CTOROSZdeTAoCAvh/ufyZdWcUB228HcK/qrnS 0LYjEV+SUhqIm8sbjeC2CgG/OZ5cyPtSRZhd4zG0rmkBd/tIutl4mKmXEpOaypa7cPN+G5vkRUd+ tw9CJtGaYz33Oi03nDCN3ezaoJrDqAy4TLtmNRin5glejZ5b2e8dbgQf3DKosAeFHESGUcWjCFMm ixa4n7dMb5eQoO54wz+hjQ72ezTU2es2zPdHtkKZYDyELqLcHbKvXd6JzHUyaQfbN1Irst95ddZy S9VJCO9MusPf4IkcIROTTD4taJNWpAVo4ebSJkhrIzsn4/VBe1dD1unCqkrdOuy/To+kEu9/sAGN fvfoTLdZu4CdBWKtrttIoSXiG0BnNCB3J0h0JI6IaCjTapjFnWVe2gwChGsKVL1FP2Hrqq2NHawy uhQSxQPnSa82WLfSlnqowRQU+snKHtCoQ0N/Tvdvi1cntf5I+PgJiV2M9obL3oEL5OVIaIZt44NW UFfQbsJ8ZXCNY0A0VVaqE5srsIs5TFPMAiXMMPn4qS6hS5mMh/8iKAyF12HLkufcrTVQCUywslPX qpqblMGToO9+YaZj7Bf1KrMin678JyV67giHjY/v5bDD3aBRvwM4lfQ56eKR1JYHfue/QcqjteRD fF866/ByuJsldpjxnDg6o3nX5msfwLtt3sCQVYDFZwPkAcArsu2mg1kvuGC3ASEt9inPZWd9LGnT EVtxrRsEVXyJzrTUOEmrJxFewgAM7cuDNlpA6ao3Bsig4STjxJogLkkqnG2CukzAjO/z10XuVsvK pREFP5L0xsaY0vVxS7BbCsZByuaEZ6ZrKTqNnPJXpA5twKzMOWm2+U+zeMxRlYnbvtD3O9JAp4zu Tq86Kvcwf6MFsquK8CaFgmOmnlBX5Qll+V829PB5Csd5g81G4JzUoW+XFuivjXMPbFW861I8bxAX Fmd6Sstpq2p0/SGNnw5JdVzNpNCONX+SBi2WllT7ysPuE7bZ/rr0g2387NSFGCa1yBLpjaoROHmd bi/ex+altcdGgQLc84BAKNTNZa1l8zDAIUKITB2NLZ1Dubje9qaWStFWu6xSGHyRtM1HgbS2icok rnUtolOiOpvpE20bMji0pVsOlXOoqyvaR9naK0QHr+Q3HlbpryVCAJElVHQtK0vLYITsnrQzQ2eE SqYFftyLZR2mAFM0t/tyljADFADBkrNn58txA5A5rhyGRsfQm92iElcdprt9GuM3B3UpYw5zB+30 I/VWaA== `protect end_protected

gpl-2.0

8558c008fcb1a925ad7d3a62ef6f8c35

FlatTargetInk/UMD_RISC-16G5

ProjectLab1/Intruction_Memory/Inst_Mem_Dataflow.vhd

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:32:58 03/31/2016 -- Design Name: -- Module Name: Inst_Mem_Dataflow - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Inst_Mem_Dataflow is Port ( INST_IN : in STD_LOGIC_VECTOR (19 downto 0); OPI : out STD_LOGIC_VECTOR (3 downto 0); RAI : out STD_LOGIC_VECTOR (3 downto 0); RBI : out STD_LOGIC_VECTOR (3 downto 0); IMMI : out STD_LOGIC_VECTOR (7 downto 0)); end Inst_Mem_Dataflow; architecture Dataflow of Inst_Mem_Dataflow is begin OPI <= INST_IN(19 downto 16); --OPCODE-- RAI <= INST_IN(15 downto 12); --RA-- RBI <= INST_IN(11 downto 8); --RB-- IMMI <= INST_IN(7 downto 0); --IMMEDIATE-- -- --OPCODE-- -- with INST_IN(19 downto 16) select -- OPI <= x"0" when x"0", -- x"1" when x"1", -- x"2" when x"2", -- x"3" when x"3", -- x"4" when x"4", -- x"5" when x"5", -- x"6" when x"6", -- x"7" when x"7", -- x"8" when x"8", -- x"9" when x"9", -- x"A" when x"A", -- x"0" when others; --Invalid -- -- --RA-- -- with INST_IN(15 downto 12) select -- RAI <= x"0" when x"0", --R0 -- x"1" when x"1", --R1 -- x"2" when x"2", --R2 -- x"3" when x"3", --R3 -- x"4" when x"4", --R4 -- x"5" when x"5", --R5 -- x"6" when x"6", --R6 -- x"7" when x"7", --R7 -- x"8" when x"8", --R8 -- x"9" when x"9", --R9 -- x"A" when x"A", --RA -- x"B" when x"B", --RB -- x"C" when x"C", --RC -- x"D" when x"D", --RD -- x"E" when x"E", --RE -- x"F" when x"F", --RF -- x"0" when others; --Invalid -- -- -- --RB-- -- with INST_IN(11 downto 8) select -- RBI <= x"0" when x"0", --R0 -- x"1" when x"1", --R1 -- x"2" when x"2", --R2 -- x"3" when x"3", --R3 -- x"4" when x"4", --R4 -- x"5" when x"5", --R5 -- x"6" when x"6", --R6 -- x"7" when x"7", --R7 -- x"8" when x"8", --R8 -- x"9" when x"9", --R9 -- x"A" when x"A", --RA -- x"B" when x"B", --RB -- x"C" when x"C", --RC -- x"D" when x"D", --RD -- x"E" when x"E", --RE -- x"F" when x"F", --RF -- x"0" when others; --Invalid -- -- --IMMEDIATE-- -- with INST_IN(7 downto 0) select -- IMMI <= x"00" when x"00", --$00 -- x"01" when x"01", --$01 -- x"02" when x"02", --$02 -- x"03" when x"03", --$03 -- x"04" when x"04", --$04 -- x"05" when x"05", --$05 -- x"06" when x"06", --$06 -- x"07" when x"07", --$07 -- x"08" when x"08", --$08 -- x"09" when x"09", --$09 -- x"0A" when x"0A", --$0A -- x"0B" when x"0B", --$0B -- x"0C" when x"0C", --$0C -- x"0D" when x"0D", --$0D -- x"0E" when x"0E", --$0E -- x"0F" when x"0F", --$0F -- x"00" when others; --Invalid end Dataflow;

gpl-3.0

39b91c17e1f60b4479849c84561c39d5

keith-epidev/VHDL-lib

top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/so_n_counter.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Y7CBinoQ8dJALrR9HIjKrQ/mVMM7y74r9Jo/s7sXVrUBN4QSNZNqZE62wzZe0HGnqeVHxKTleUiW YLvUobOg3g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block oC9jps+IOTMwX6ESvNFcDjBwzovk2Cy7mPoJ1sbS5OOIN63fwf82upZOEIr/3kMSUYVzdyHSzK8A ueRVzeSy/t5momiwjGAG1jd8xVjaSRtx78ubRsk18zJDaImTUReL1ItgAKWlvxfWuqOruPSev7JA mGFGkPu53WH6rOSL67M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 21jdtrKJWunM9GBVoFQUEADdMPV7IhUkLVPbnbF7YOfGBzXxiaDZzE4+gieAP7zjZwzhCg9OqiKh UsERnVsbBVmjMd86mOdQ3ojbMZOIreF+ujfxdKOudWpDjzjqOVhxundpJ+JHx3I4cR3C+8abWMA8 0R1bjezw3ZGJPSwbmLFQlutkE4xMGzNEpYOntM7jk9W5qYDDSjJEOYv1WbU6x9oMbnqLnNvrxNIY w+FeQpvXQkJJ0LDIpJywdspXj4kcySI77izyXVlwRxLFhcoFHukCtgGFAoMz+j9muPFd6VTx3Wvc Vi9Ysawb7Jvuqmj6PQa6yWsHzUudNW6T4eNbIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block lgyTKbI4KPFMAginDIXZoAbHJmwTXqa0o/b85r0jKKBeLXHvJU7cpjoLjlTbbZqpCG6VxHIsxrlF NsCIWsbrEf7E7lJcqHdCGEkdYBZ+8PP3ZfW7j4WEukmaIdecVD8STpiRXx3OxvRGXoLQs/K6Hd+Q hoUCXyPb9hylQdnj8Mg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XVfnukUCBCSscsUIOWGEfjQJqs/OvJni9D2/EbuQauDOBHhIR6jxZaNaPjRNPZXLZbr/Bs75vUIJ KlzyNguxYQQYLd/PnxbTLM1F8yddIcL/ndCrDAQmZqxMgiNB+BXY4cjmxEYZe3QrDCMtQBjRwJEe sxPXSKYnpxALKAlmN4wMkQ2brPuJdAPuDcThDjimq8ndeb6+c16p7JwlFtWJHun+8yuHq8Cw0Pwh hjJEMzFzjUo4UuPbY0oqXZyU1B8nNahbbs13lUpDoyu8VeCy3f/BDQmDB+Mhef/igbJyPwgdSByl x/pwHWiv44FmkWPFYrcPN0JQc5z9rudy32TH3A== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 252192) `protect data_block FevyVqdJqhWmCuqR0CnQD5lStLZxYd1PXMxx674B+5/87xImFpBrjiariYS23c+pwPXbnLkIGFC/ WWwKQ+LEjrTg7uLEXTX/kqWDf8liY3oRbOeXcQdDIj859OcNMEgZFsyahHUpeZAHi76MZZ0Mp/xt jC0OiwNIJlMbbziQBYt+UYvu5K/52uCQ28w0jBip25YHEjWl+VlszBxjpovyCGjfB/GGCG5PtzON Fcjo7rXwpEOd0+Rhnus8FEAaB5vXz22azjKT/S04/xL//IXaIs6IrYRhlbYc/UNYL71GfyMXKFxr 1EMg8tLGxZEVF0yzM0jBdvgRPPkZCyvCrDv0yVJ29eETWs4D+7baK6QZUmvzbJmb/ydS5IMY+Cqa Fl2o6GmTmueqOV3GwkCMn2TWSwt2clGqQK1tj8DN1kfBw6vGTEmltZQsjNb+ahzappgVyXV6VZ9G YDZ5dZdiZq5lJeKjbmCON3mfFX97RtnL0ONJ3HFAJfvgI45ZZX0T19Dbcj0ZGcz3dBB3b51wxxvM L34XYvHH43CXSfyQsLBVhj42PwhGJ5z25d4VyrgLNCI9XW5msPI8Hmhr4JU9Fi4QhMvnw91nvAUj t6JNxlLECkimeFSTUL7yIbxoWgxZ/KUstVU0I5Uoko/zCkS2giHSLBZJj5N2N1kRmmBz2DICtvvp PRUxDL0pG907/vHf4wF2VoEAklgEuurcLYyK5f4n5Yxj/R2naOHVOeJ6oIM/ZZitvUCQrVzutzYp MkzEE3JrusYvGTTiPDgxo90AV8vmM7tWGDKaCNAZ2vhRF1uex0HUUZvFkDMFucgT93DBfXmfY6Dp 6w8PXCgRgQ42mrwiddG4zzKQUOe/v7eDjL68YDSxvpNR/G0RYy9QoQDltM/EGSmNDdhNfPmmlzeQ Xh1ZJDrC78llUyz7W2klOHRImF97e2Lbaj3rIZ7WqL9XgjI+DL9Fd4Voy8Bf3avliteec5e98hq/ 7Ur2/lKP50NYX/fGl7YKw1ezJhK2/J27VdYBA1eG+wir486F1aqE/3+X4Kp0hPqS5aW5c17O2qLN WAQhqJ5xKonw9ESsOjnUr4ak7csezsjFP/rTkXYCg80E1z8Tzj+lbMJyts+uYuG6Z+reWiGSvvik cR7Py8DsYJ1tdRYWUwKc/u++LAD0NOmlBvM3y8YMnE783HzvOdP3tvFPVDObAC660rNM9HFLwb77 Y4pyPe00RL6I5zYhcd/5smkXjUCjwl6OKmI/kO25upETOp0POVqoAZqLq8TC8DuwcWohtoUdrCaz Y78y0eYnxVuAxuYT2Q/YcW/0R6rcCJ1GCm3gBQPA2GA0eySyOqmffqC4Qus0iaaLBO/JMz2npuoA JXUj+FEEEnHwTgPePg80k/4CRmPQP5qUAzQ1Xe89kXaj6atn4BV6MU50Rb2vJFLcuwrrC8yE00Vs 03WRNhTjn70TeV3U/Za3GAIEbnYALdxkGL7+ijFk1vmLuUc08RdreRBMpN8OOuYu++vxbR/S3NON 7QOjSqKwYDNvkJ+EOvOX7tnI3Ckv4QAa4odcL9tf8vLPFWWrhOXJA0NK6kLg5tkkU1fIAIC+uAHJ bdzLtwQoHFxSRJJcYgCTt+ciPNhKqD9hR8H4+5lxFVBTpQHR1Ags5ff4Tnupt4A+Z48L3U9B1p2d ggmCxlaVsmjDlJ1u8KBQ9xjFSLYd7pCTQ4Rbm2sIWaF0RmUb5/aYyJ1yhEZBdoYq7WL5LmRCcuE3 ZB5hSjRTGljVOY2WU5XofSJ/KKRNiIe7lNb2cXuRLDvz8HZinEbhxie9HVRMIW63eOXK55By34mK 0sRdTA4pGzIGMM/qK9Fpuzcv6lv17RBVzBaUqjnD+KYD/cwNqIyGHi2LqGn45lNAr7GFk+AKO776 neVZfJMDT5RV8BWggNWvpMMCbvKenkCnfXztAgPOX5L5BkiZBVS2O+MF4rYDVDsGIUiHPeDxKJDW M+UjfixgwxCOvYGtl6ZN8RNEqGs6k9CnGaT9hNFRyqoIK0sNFrP3UXHO40ZLii/GRc98pmjYYxIk ZCCnubYWGBGTyP7tKArc/Mfk8bfj/y+MktltLooKFPvbopisP95/Y0e1xwLj8bOfypQkP//X6yiK aG6zdfXrEXybecGe6uhkhHyMrR+GxusGUe0zUe9C81+WwNZO1C2LbXdxSJaZOcxPdyGyURdkTYhf gWRy0tgRraYOR1PYp0VRdxmu7xruvIOxzVDRrb0qFiHicNVzsGoSPwyuHXC7wBTXDYGlZhmUcZ30 gGqFd5w+Vwqerip8InwI1h9pkwRtDbgJRSFtCFpxkdaAIS3NrjO8rRLOpt/U6/vL+e4t8FJIggIX nPGi3nEX4+8IeQ9oROXcJlSErJIP9YJ90n5zYJmiO3gJhYPnJAdEzvGLhKAMbVLT9+whKHTjM17Y W76IcbrChbPECGcmpcVpS+sACydpnb7EY0ZZAs9WPXnXZzdO8sTmif8npBCMrv+BRuHZ8ieWNfOD fBEb/QNzr4MjowGOSXROEJG02ezk8QFBFOAHB0F+hWRxPZ9V5hY8cZ4Gd7l2KDXCjksj1QgfCYQM EvJ8PRvfTK461Jwh2V5tTftOH7DpNpmAgXbZB3MGlLo8871Pv21xGwqvYcHucuYeOTIi7ZviejLv WJ84JqnlMYG/4SD6SQbloCbv47HfLn5sFVLShLESLPArduTv4MLbZoIuPzSCogRCZzRXcc4Exjlu scHwoNSASz1g+lQM8PTlTLIFZcq3RlqLCrLn9db5AGk9b8z712sEKqhVgMDI0Uq+BMqFS7BgaxUM dp5xd5Y+XADfCZAtZbsUXDUp0CJfUPyjkX2mTGmRKYAPwiMePIeOTAYvbzxY+vcO/ubJdSJP6xuD HN8kLwVxpyOhggOg1PJuwv28QxDdx/LG8XlZxxRV6DkbFzgjT5KJ+35BglNc341P/VLvcg1pr/ue 241pOr9OY/QiMtl20iA8hyXCrsP4fIKNhW3sGUpCWAogT6uxko7kqw6KgTW7WCxyCLV3kJSM+lPv JCz2Eab6mkNgmnGlsZ0RoKF+XV90fMLgospFCpz84OdTORhSZjvuGt+jFqFzFCo1W5CdinieJDAi 0n0xDYtnKyPjlznU0o2XA6Au3CamVcdJ+WEcGGZY0Hvx3277vhVKMSw2ygYn76zoYc5DRf2CGuLX uppIxUCmXsb9b26/1qz1qs479BPRiXPBsSwONVdjycn3Zs1BrMEVA8dUWIg0sIMhVpyg4v1V6zvl fHIvCHWV8qwB9KpMT8P9tURW+ovFI+wCbw3k9kRK3fGO2dnuAgsVRV5Y0+b5Yn4PqFB4MqJTNfGP Nl9gH9a2NuivtxlgpR4HFu58PTZ7DiccjIKNuEKKwJBn6S7dD9YSXCjEfqyCTqKhRTc8koAp3Te0 abVl/Hep36IkdfhjhO4KwGfPoOUy3/qu4C//sChkalTQ6JDux8XJU0TJVF8vocnrsq8oKLW/ebkI 8XmkM0YGHVUaDCnNEUSkcTd99vH0o9rhYWRvQshVxkjCHhJMABS3LSV3QsY6Yb0c9YtifQazMQJu c1pHb4aY9L619P9ldVYOihb5zDq+7mhwKSZ7AgG3lrLg/8udtszRR3xXpcUFlGuzxg3lpAMyuvSw Fq1Kmk+t8fO0X4sRd5lfLccgrYFUGDG5NEbUMDRoNNMprrkc5AnPxncEB1muqtZPNLLTbHvp3TXM 90ba0eXPCKyIL0IEA0CMZLSg1eVyS18GtRsDMI1PKGHdtwHqV0/j2XaamaxDrexorLL4ihLAoyWO 3hIcEbP9gPdxKuQxnH2gFchgz/UsWSP9PzAudDtoDbmgSJA9fgz2+EPkI822jz7D+5cTvzwQDM/r dVsilIP/pvLo9D6jy/W6L4Vko4FwolGqAK0pt1Z1H6+qppTQ3ewXGmawZn9wPj/tS8k79rNl3K/w h4IL0gyjIMHr6izcxk5RBfziJOWMds+Hk4sa8CMBhIeJXsl/vPgbBeGIP26POrC1+d/sMdEUnfzE Tzm7Ym8eYFd0jbccXQovFoYoljC+8J2aLZSUSOmCEeiWUth+kacz4EtRzXZjbyv1GelUzW+PPOn6 WxXrZr04ua7Z6xTAnskFg3obOZivJzUP1PGvRxL+RTsGz0adRuJ/p3b4+TQLteozcIZqwUugrFvv heu4N3ufVM/+lil7qj/w2mCLdfXovrbI0Z92bKDuc8LkFPbWaZYx0uGLRVKQNWjTHjGZVK84chlC Llhz18cJ6TBbulOmlfMZ3mVB9Llpp/H7pGYKLLyKkU6iwY3pQGAVu67+W/V+UIm+eNKa9Gr1TPLB af4QPG2bQ2E5ga0yKLv2tu1uJ+Xs+pp/ev/j8dAlK3/Ark13vBx1vQRggOQqX4NcaDuMj6xKaWHt BF+b3QX8jbvX3uR+E6JeH6yR0FTT5t19bE7tqUDPR3j33SArJL9fBnup10cRZRu+9JpVy8fPw/nY PtmVubnPjM+l1XX9+JdYpQGziz7dk0zLfVUiYu9JBPr7QATuHt2a67ubK6Gyti5h7vlQXHsSRyyx 83qAaZ7qvDVMA7uXaCtOZ0gOpkhQyYwcXDTJhGD3CeqGn+eqb3ZPvLRSeMNhQhXGzLvO+OK5LVUV rKQDUNh7OojErT75Z0A4NwSonDCgsqmEd46ekbskUg6X7knWKsHWvULKudGoznmxBhc52ichJmVG Q+hYstEf3rYLZZgTm4vAcSs4X7l/KOWt542niYM+Pz6ijwvPXhW0FPZe979DC5t528ZK2ytaccmM UBZyk5RykLjdVL54VYVO3Q16UXA+98S0O70psF4jFxP1WRxCylXBpHAdM4qXFVinQ5gnneq66JPt coTRHs5civ7BQlBy0fSYgvFdcOd/D0ejq4F8zIk+3C2+ZEp4Kh3Ne1IQAL4tnVpoKB2GNLWINZ1T l0/zZbq72z1lRsO7LU4HPTd29hz7u2utc9i29NbN6L5SaT46+J4tPYxyzIWloWRl49jfhfvDWDQO kDyXI/oXZe/vDgclUOme7RVIEj8X50/OPPUsTv8jWlttP4yX14N+lF3QqGAb5wcmZgzSFl/qIGBd CVtX7jOjHaLKorswWYLCaqxa6Ht04Eyuw9TQ34Qu9pE+8B6JBgVwZE3pjhGukxCJC2mHQVeMsqoi TyoLAZHeioBbhRlMcMvBpktekjSv8GuwKNBWWjfRq/rekviAFZLPFj16tU567oZhLdXY6RkOf81v iC2ZhqM0Riq7M0VVcjHmRnWjw4KmPEU2uOi7PYC7291VuXRUG2ViBayXpevtbBqaQQTnzA23p5+m pyEUWLk4vHyuCweVdnAMRZAQPTzyBhJylo+45ov8PD652+kJjKybc5J2B9l1j1JrIBZsRTap0XqE ux+dC4m9g/esPmS/xjSA2TNVa0mg3aUFTFHY5Np9cDI4cKR4O09ustKNEVxhWtk3tGXnbXjRjoKy gI5FWYLRZ7RWTzW84WNUJZAyfatNycfERuemRXv5KGbOmvY64Ktl2lM2dVt5oNznt+ztdBuc2Ezq U3ljTDv4XOl8cDPGC67Q0KEydepnBvB9hlsH7mtu9+IDUt4BbFdL8jMCgd1Gfjm+GCAdHJoRD3Lw 2ee4p/DqmFd7Au+hK6xgd0c91pNY+VT2x1sSoPZ+AULUFl+J87tpJccmvWLon65O7pD0NDdkidJh kZBHcvlNP364Hy5aUWzaF3mHQPJN8136ceoBGyFSmivwL6xX1hI0IXEG3jbI96no8ee0NQMFyVgE 9Th4xLSfxWkeDAmaFyP/nDUUpCkj/uz5johnnqa0uSKuFmZbsFDSnJnOPbQA+IrKd0mIaGcwKjwl mKCNvGjwZD15ExZTBsZPwkt47vahr9GFNDf5wVdq+u3Ua+RZqHJ4o/nFT5nvXmBDlWw3k85UC0Ow UlSmSEhRsh1affk+snnHtiYrzWwNluXWnrYiOKtOojRYuKZCtRl4Y0pvI85M136qK25l6UFnmA6f iiMlS2ycw4o5TigtuPQ1jDABJ2uqOQKP3rnCoTC8o3QvvOGYMxu+CBCfwbj8DFwubILUCLvcB46U 9nqD+1zvcXFiBUVJX3NuROq/+QG4Ws5IclfSnjG3zjG/XiOEp6i3lmUi1DikZLeAJ6nQ4dN4uhu/ GBc8Y814jNVzwNnXfThtYxQlnZRWJpVpAX1mw5Y2ctpiuG6E2Uctm1BmXjbCnRsVdyKDOFnyJ1hz qN4AqTG7+QSXSFF777itfw0/QnMtIQaYefR0JwGx449A687T+/sia2bM2GKgfmwa4qoRILF557pO zlbmZmN4cB3w1eLKlG3YWyyQGm1d2q/x4l0MQTR185IchhJPOy2dGPNppMoNy0dqOmT1Ndw/k6bL 2ZAfSyOC3eNF42QR+8L69n015BKEmgWTfnjkf2YajbaMZfAfLrVPtLxyM6oGN2pPaiKGOs+4GF4E KFGGz+QxxKHZHj7MZOX3MZBqFFE9/2jgCUgDrMvbyQDeYMGciE1zxFtskl6IPexbielrW1AW/lwV lFg3lJcU0zkg0sowaEXje82M4jz8tMv+hNntKK+RGNznPdBEwIH1tuWISJmSgi2gg0Gzj9R0oRDU r3ds1WNh/2AAXu+1PunYztMZBG0eSUedL797wlDK7X1J5kscqbbAPUIdN6zSgq8fWYzfVBt+FD6F ZjHAVPXJBTMD1bZMihui0pJ0/dEq/25YcnzalaR56cNP7jz6H79/43CV0HJTt3OLEZOR32iqQFFY +1/vzw5U3AdNs7duzjMs9xD8W0/fyQEr0tvcK0BYyiqBeEKo+u+FouQZGPmeIZYJRavSNbDiPIop Hkf1evkIpMQAW6Y1pd40f1+UqPVHMv+WuL642yxVyfWc5GYfPd567v71X6C4m7SgyfcXYxPg3fyr Hw4FQ89WPyhGXhVdHscCU6vzgwWiglg3vJqeT/R6uLUk6NtnmPD0ZctIyzLkDsp+MGK4vqN6urqL aX6GRuue90gTxoPA507MzpmG1+g0V5fr9NUhoH4Px3LRASvOkV3txcDtfms9ABV/ksBL7cN7JmOH OxetZueHmF7yJre0BNWRettCz5+Bwxk5GhrC5puWJQPqsF1kRB1Y21EKchiHLU8qiCRkUjD+FH/h pROEteYqjX4IKubVkGSMmVUCJ3wTEKiwXjGsIs1UZ4KHj/6Lmr9cPj3/rjP1VmuVJ3tSJWmJCGQ7 qBzUSuJM4lLwXL6+rwNsWjKXTvcdoGtJsdjWHgtC9lx2GeSPqOQspXfNSswaMWQW3pZE8O8WnEkO PxK0RTXxvCRrun8EVMxoChoX8LmwblVsYZoGE4tHN3ddMf9DU4Q9Swlu1KMYp4EHf5EcMSc/geFG QJul9m6ffTeoySUByKRKIWChiS+YXmwJG9fYILE2v3Ow9AJSZ5mC91X5BkYqUlQqM8z0PiXtOHeT +/6Ae4St81A0qBuDYppyWkdKWlFJX1mI5q7rpZvJue+TCGs/argNxr7SdmO4LVAhXxEnI8Dkz3J/ 9ggncM20XPHeAiCewO6nYORYfWU+s80qIQzg3igpjbSVdSgREBHvp0QPvf42c8G/1OGUWV3n02az w/3oKW+rPgEW7vjUiJttfTPkzqbFirplHpa1KLJT+NAQCYXY8mg5yzo9tMEl3nOgA5hPFb40YvoD mDlAhGe/T531T1D6zOzYxDfZwHD8qzbgGpQ3L1bTDtlUodNMghsiZ47/QQq3M3sH8bfeDk3UsBlC AOE3pDAP0Md5sv3tpxpKaiWnVrXh9xKKGB588br42riHDN3NQu4SxJvnFjKHEWoaQG0VgQp5NnZj r5VdEy+CkxttaiflTeQ7W4DHCg2lLK4myF4oc3pQwpNSyTey/hrR9tIe8ZwOEnMALN6Udu6URlF+ ns0TVNO+X10FoqyhNWGhnz30qmQLWebilNbl3H1kG6Lha12q9n34wibOE5N336Wj+SZfj1EWd/w+ e2xZejgDGLF69dXDZR4hWYyRk57oRT53uLUccmBRKOGCG1vRySpNq5OVrYYwwTUpSNTpjOANztER vB9C60vZ9dRLOseKtBGmgJj3XwIPXARE8C9bveEkjh4EAstPDkY+Xxshiq57DzxEK09l7aKIRP4a 1DfCY6ojS2MIARRatApI6S2pi9lm9sXhcIGwzETrBZ3hlncBGEgyIRRM80zYciLedEYUniNOVh8f FzWRW832xPP2aXIWbYpl2UyT8ldVGI8IrOfeiGUwB4HjaAdODvk7xwwTzyMTS5lH4XFLT0cT0e6f YDg+JzXFdcN4ZTHGn15CtEJvNuZtbH9aM2y+0aUAEDDAmmSd2vgxpGawyBYkyl2LCNdOpfmTPLPz b74O+ZGfxwByFDlEWIOKxrPG67tYNyO7HyZGWpHMI8Qo7kObMopk8iESsf0IXPQ9V2jn3W3/+4xJ c7+5iGwYEwyiy35Sk3xumIp/g0mAhYSV20gOxF/x1m5pbLBAHdyEG0mRpJwmxHznoxR1wghF30Yd vU7ZVJydyu+NpzTnriQKq/0hME4cQPMLBDahClDAiRRhomLJWpOBv5U+tAby0kgju2eAyOjXcL0m eT2z0yTvLxjatCDx3LcQQ1VVtsDn08Z0SSX+rYgmppM7/kKej5P9nXXjT0dhfxKnOkEL8dE23xAW Uc2hhsBVhE8le2T6huUOQvIAlXgOBIxbIgyS2mqHb2uyaCIzgn7PJxQwcZQwcWXiTFqukmNUB6BW UZU7WcC7wza8/tgUEBjBy34RKCMrkq0Cag/ESoD6/55KK7aYKcPhWH67q83hrtUus+pKRvuXsFpN owJuQUOlCrFRaYDStRNsLhExC4Xe0It6B/Giz/Gk4y/aPtLzNG/08tvWxFCz2lNN917kxznw6G9K TWPezH3giPmco20aykLeFo4oe1EQdBHFOptz9WV7FRGAqWo3xxsv5aQ0O2bvwGcIogC97huqWQTf Pf5teTVO29RenoHALClF54Tt9WEtwnTB7VIE9+l4cQKGCr5NWrv7lRxWQ/oWWaDQ3rOHJzHNCLOa Pupfq6hJh2mp18mWHtMzkJt/xTP6s8jI3Rj9a7gco1TOLf85+VBl3C/8d19JD/oO/dznCeO5lSFz QQlrrEqHSbHCDCRzHXMjyieAvOE+LkL5ZWWtCX2kTP7t3zRu9COHsmEagFDzAyD6OY73KCdbrCw7 4Xfczl21UU+T2uOxIY3UfBDR1+s7+Wu7jiWgHoU9FPh6n6pxNvBTsVQ0+bdiZYjOsoIPWMVBgc00 H1WU/xLsWo9Hoq5JrbrUdvx1j1qqqbAyvS3wzVhsCCI7yeJo+TnTWh50Bnu+MR06rCy1Eq4OKWeB sIChi6wMn0V33Qe/ZD9hwXikRqao1l2K3eR9hRAxRumBH79vB0BpySujN+gfwoL/NLN4GL8z2Fi0 eeyDsdW/PbDtu35uZZiG+2+jJxwXvhaLfbm5LKt6n0CohqJhZomUc9+ThmUFn6db2I+oTmw3iKkN G4K75Z3PhAr4huOVPSnBgfM4sEikv/nBvQ4FdR7HWj+cvK1GKNeD74CR6Hx5hW4bU843wIXIMxPs bTkMbSPAA2Pxi0hWBqt1QwIm03He/LX9wgxCz/4GX339xBEANLeX1K1T+91T1e+kIy31txgnqGC4 oRNnZD4suXSrFmbWp+pP1bfty6M+v6rQLvxPRzX6Jig1hxOFJK7cFR5a+xp5pXp0xPASWKrBlvYt 3LKDj4BXGRyyTV89olV21Y0kEPc/1W3Iyre+STUN6+VjjNq8ztHcsP11zJKV43pwgmcTMtguc40r lp7mKdQU15xAFVUxpirhb0PGhyxC3Rnz7/X3fbyf5/hKYIoJWRTnpajIwrwq4Q2ZKx+a8wXhN57A 7mRMJFYJ/Be2xTaaCvNj38Kj+mHSGC3Gru9zDyJ64KOfe2YXnNxWTvzhpsKeaBjhR9mqTd8l4wod TTptOHOnYvPLgDi4fiS4+7RG1xLdbLp73Repra0qmvmfPtSvacRUMxyUPjvQdCkzVMUJA83wIABO CKgZuPR9/jpr9ywAseBipm9OeUhU22+d9LFSlfoOIW8ocDbBlbXj4R3raHBgp8PJKCoKEfxU4wGk 5r3lhT17nXbgqldHng5gyHgYExY7C65QLoUzAsCRpfTuHu37w+wFT6MCvpcGBdMc02YHFOY41eBA Nru2fDvLxvzx79vCJBpbImlOLB0DZA3Ios6f4arPrimz1aUaIINg/jl8J7fIYofpJwXN25DTUL64 nPohRkqn79cddaw+nW1cbjoP6b4x2uhkGiLEhME/2BSZYrjNzvwBBsVfenciVY/93Bnr33qTliz2 NPbqfuR9U5trqwePEudQLu3+E9bSqXo4woMeFZKDD8J0mwZE/ZSPJ7KS0QBXVsk+bAOcPjvCzUio J/O3dE3amKfLLx+jN88SuseP2ZDvkApHuSL/xaoCVvPfD21wp1FJ53Z5q1dWyBAJzgFzZIl/kAKF G+jhzw1r2GkOTLMxSivj9cR5K3q0DsjLx5yBtxg5bGef1uF3o3uuoPZKZl94sCqt3pOFPbwBMQGm Sht5iU0l8JQduYQZCddsYomF+6CFT6Z3RqMeVjohiz+OJqLKiJ1ckVh7tvvWWugEjLWjZw1QWZfR 0JarD/CmtEhYRwBytMSOXIB8UtUIX8HhBZxirmm8+4NmO1Qdn+wMJRWs2HGjZtUNxHgrWP3HTg/Q /ZZAxsui1qWhlqlq2myxOFvETWVq2p44wUAGGVMJsP2QZvc4AvDIx1PU7nniECdPUtxev2gLJiGy tKbPEPJnNw/Zt8N3L8KyimYHsanLQIFDzhP71KGUEbh0skKsWm0/jfJ8U+IRay0V+9KMKZO6gFlU d/I5BW5vI1v7yE/TGkyIT1WScVO989Sp4rYS4HecsBCsQD/wJ2aUNXFa6rfP5R0ENOtV+pjuM8XJ twd+2avPoreO2xxdxcSR/xAv/GZ1x23trCv+pONd5rfypEe4ad18O542H0+O48oGG81UyxCE480h TAJ47c5tzGnQ1wEoCO6nqiPpXk69X6cEcVqjlUU2VUMmiFrQ9pXTyG0JHQRAZMbmF4XYrLK7vWYb pGVPgkamK/sht2oIATd/bylGuHfXQ3pFSBatSO1s4i+IyVw8Cb67RLK81VsxKgM0GCWFNJx0wBPZ RxOxcihzyro2dmtqj40QgBLTEt+8X5isfiHzVj0YsEgAcASE00VaEp4TGoHCBoRNWoVbfYpZtqVV NUeMFSQzzsGHKV8Zda+59YpO7UVY6HUyhQOoAQFhXNymLSGaAUu7Rs61QOkDSA+FhBW5h06tkxed lkSq+cRXlbyCo5ih6HrIbv1qe3T6m8g3e1cD5ML6ZH0ES0PAnaNj9I3vB/OowUPzaw1Cd0AtyiXl mWl27thVp7ZoOlhYZyWrMG1f1QDnvTtoN+PyzpveXby0MMsb8GYkrDAOnOyA4zZ9D1tjr/sDyd4Z 8X27L4TxDBpLX816xU0Yju3uGZTLp8oREL4CWL3QzXeHKE2DxqpbeIA+RlePGFHzaCdj4hblMD+u Q20YXuXetz4uYz0tYrTR4cAg83j9UtKQ4Nk90AEUVwz+BxEC0+82wTdu4PND/hrHT3qvo9iPddqU 5lKpGrk6gbH/zUQPcYL7kSC/EWVErljuYs/EvFIVyOKF6zgdI64N9ub/4OWUg086jly1v0pwEyd4 8mqqpYXec73lqsEBmgj93MFbOcwiTeoB2KypgyEhVtWihZY/gPJK38L23UnAKpXoERobAQyb5BVY iKgl0hdA/W6hqonrCtjz17qVixQ8vQCn/ZkEX+ttiDEXXblbqpxtClILbfRPXT5HJI/VT3nXTSHM H1WP0xxXVkd7DNYhHfrWz+Ib2fKeFntQueA/xFjps6Bmq4ETzAFIWHUCXbxWM5SlXyeBtC3SKkwc xu0ZlrATN+Uwt+QNrhSc1TgAYTNlQow1DVbbwrq0qi64JamLaAUIJxwcFncEB3zs1hQ1Ism1lwvN fMt3AYfzhuayVTBApQPvblhzb43tQ0DmpMbITe+BSLzpSqKULl0l9zPEJ7TaW7Gjn6vMci0Y+rZh 5gjHKvmRsBWG1wKgb5d2UWmIb8wHtYfPTEhnQf5KjDaxeVBdPZdD7pqXPgbwQnOy6wEMgcOO4cvG e85+SrcmE6m2UQUeEiV/tCgsP+i+fRRpPDr0C/u/nx2fNj06C4N7+cJa1eNISYQPC/M6rAv5L0GK vuc+J+q+PG6nYM2i1Isbn2aay5n4PR2gLqbFZBw0BwcDAvMNKSYuO9hUsXCnF9JsbB0RGpBKqokx qq/ePRC4x9bj/WmNtgttmcIHkIWpk3RS4zmAT3aTpAm8uQ3NUprOBl2DR8hLdeF0lesVgtErAcYM lPR2MyZyEX5j1zb05etBi9npRNE/E/lpZ79JDThd36a1d1+NOtn1togeEQs2TyojKte/O82ARIQT xBT0Pe0UvSIz1lrss0G3FXDw0clAZcykJZDk13pSC/WZwUQey/TnZKOObt1SdfN2UggvhV84S9Gt YlA+HXV/sYqML3GHZKd8JIp/ssRo/cPszI6Bt3nzb2QdyNQVyNKsV9e5koQVVzpjN11H9/6EEsUG u3wynDrqBfq8bMZ3Cj21/Rf02kFabtyw+BwdPyHRo4j6WHxqa0JY1DeKgjo1m6Ny+gXcfQ9m4EXW 50OMHtK18ZSnqLwGRiP1LjWJzYgIEs5pMxGFBYi16uqSZClGUqRM/7L8Aqfzwx1vnvB3pPROpNb3 sdCF36FLghIfonn9SrDdevXjvdD9YFVJBu1htqw4mg6C/yPZf2N4Aystw7QArzeEf6vbUVF3uHQ3 GwdQlQKD2lOoYyPMvLLfEr9vBeLBbZjDNcEThCTKzq+FgEp0HTpNlF37Av7ZyEW6nkMQ0eF8XG16 IrVa/EmP4Iy8QhEtGV4z7OzZpPI7nD4Hbo788tXtU8w7nHTw6UuHeHAkPyic2t2MlOymeYe7Qm8Y z8f7VrSYvFrJ9WXJuQo+qXbReIknbxxN/xRFRmHBtlZQX9ga2a+xkbZHd5DfgCcWAWG00kNMXGRH CltMRp4iDZGHcTcTrur/K0gV56Rqd8lBbEKSdkzgIIP4G4LFT7LVhTq+0M1cV1bCaOAmpiRgld5X QGgSFPe0y+mOUZ6gTeFTvjLK8KC9V/bA+UhMXImDGI03bGYBpsQIE405TUm9dbr/cBc1kyYip2Or L+fXJNB5zwZ3Y5nZFxkc8VvudHerqn9GQEHkGLFvSuoRGDa1KMj0/ifQcYH4HhTRl1iMqAvDqqIe w1MQy4K3JjYZRAvjGf/DyancVNt5E/9cJo8P53Yqd8bxvfnWq5+beNr0xOqusHMZ63FrPhecQIs9 vnYcA+aUsb3RPgRMJuokqBb4wmWZb0i1U6Y2x5FuQlqWoEKpR0C/i4VeEg5iLgsHyPFZa10bqVom 80pHlHQWBYu51GlXIpTopu5EF2oEadCBtd3/ImsTpLkPtInQBXfQBPOp6fxUXjpaEdwIByuFaPDm FannKxNHeRKsRVfJYLzvB4jGoPeL2Vze7HUO0hWG3Ccq1KB16XMNDrSuqgb/2tJj1E2FOjvcfN3B ten/aV2cq7wjE5ZK70YoyMyMKBtVG7XDf2XJKeZ++447TS+onL6Cjzpa4V8TA6KPA4Rb7SWmWd77 40nyQARCU+RC/2dzDeD2YLcLfhB9fCQkf1dOy8cZzm0z4f2F8nsP7sSVBsHvXDnyOF9cGEIWLosh QkP7xgWgCQOgdYVg6WA3Za3kFZZkxH2vD4enNwlli4NARiwnkBDjCdxvLvh9CiEhu3eIYsTvv5ru cw57+o6hKAs5sAYkt4EvpB5ve6NQzXLB6Sfy33HIau4XCt4lIj0mdeUKJ/RAcBTfp/PxdljmMxK4 1OkwR51/YzDZE1QSQGsRx57BAVfVFR+jzamw4+NzL1iZUmr+kszPwJghYqJ+SSVMRwckEAMS3P6l kEvJPg3mh9n7Z2aIQbQbj6Kw/0/RVjEbOlJnsrydXu5LgplYtleeRfeK1o1aY6rofvx9qoQl1NeC RH2qz56Mge8TNhdXyHRZPjZ+U7RQEXlbyNv09hdbN39+mueFcJDxLL9UgCtY0ZPpNO/qSfuXlJxc zx1eF5XPqEDfCMZHDu1CJwsPIjwIMoo8aIcW2kHLtXHsgPDHbxZ+8IWDYpGdU4UwSOEq9S6MIikM 5ZwxME5GyQvbTZTQPrzy3HvdZrTFjnkap95cThG0Jx6GJxxBB2bk7Bv9vuPlrnl6SX5gEUnyJnRS QcoaX94OkD4AiRVZPxN0miVwueGYAlluLoyw4wKsOq3R8nX+stXBAvP2IFToCcUUE+jpqSg7tHfl l8laT3bqAwNe9HmqAr3lob+U7+scNNvJ3IQn2mppfeJ//227g4IqxUrcAU8Hr7U2Il3zNK4wp4FH DD96zXHG1lj5VqcOUU+OFh2oFaHKjK8dgel8yCNC+0lcPvj9jAqJAJrn+SiunCz+3B8mjROaAjyY US/aFc4x+fviN3WeAliyqATCnc87dFxPM4uwPPqYQJyFHJNifK0aO9AAG83tYstMWCSel5uSoFYt Jczi2X5Yfwi5NLb4f4pz8Pkka/Agm/CK65OaG0XlQowiUfZhwGwe247GVCbFMbeUTGmiUtXO/G7M woblZGqSvvwkXooEJ6kg7CW3r0RZNmiVoRyB2G4peHIXudNJe9Q+Y/Vaa/JuAKRXhoR10BJt8GWT gA9tbJoYAVsnsxMr0Afymvo+yCr0mpcRhbH4AvhgF5aG6h1ZFKs2HRkNdl0TKcmy6L9JKtIh/P5O Z2Ker8wkN0d4VRmf2luypR37Kxpy/stowkiOQp5wyznbzDH2TtSujJHEN2PZuI9draOYwos2EHI4 NjA5ZJRNMD0xASkKP63MBc4WArEhEOUvm7ORfN6nzXqyORQ5o6raqeSk0Wy35Hw0bgE2QMGvT0RU GRATTYnHpQYtBhM6IwbYmKCfYoYLZ9KOpF5sfIkLHA2EbrOvGxACHuqFgAgEMlWnH0rUxGwfo9n6 rFj3sKn9DeUPFNr7ddDMYBYKQa+aoXtg080fHFMe9TTQP0T8ibrcNHSsJSxvfTZwYq0964ltYcYE xfKuN+6vC8E5Fx4+nka1ksa0VhRc993tvHnJIRqZC3rOFmsrwxud79r2Bsu/g9ONd45Vuzi44Frr 1MrRhGJIZYz+2qyhfqEsue1vFfPP4ovM3Hw5VyVg9Iogq4qKUs+riTaq0bFtcjSNG/RmjdcefW6B +vELxN7I9j/UazOwauqijMDAXdlyfkiwgeIM3zlX4pNrDuuNTgyYsvlSOIsT0AactVw+r7zd1Lzi ylFD9IajoCrgOL8eeJP5fqBK5uDOsjTBAcuXt4/r+ZUm+mXJ7ZZXmRBERNTqLjKkgI7mTCEfQgCH nIAx0qjrbhWQwvDQvLvurQZHG9Z1xqTHGq0235fwO162tUZ5/SP2ine/QiV8Zkujl9+YF5uQyyf+ 7NlQcoVXq467sqLNPsBWULFyJ14jHqmrUC2iTbFtR+qkW4gGKzyFPCSt/fVortHNaGsvK2tBQ8Hi McBHJdTy1Lbs+YWxVpiQFGMrww1NECH7XtWRc/TF1LI3xlxHJQsnfXDKvZNZanrZ1PsLfEZCUEcM qwOTdRDrA4vrlLLy1XduCIrMNVyj1RLRQ2NwBPCvE3gK3Ill1XftHUkzrcnINqI93YwPOJmAgCCm yLHnK6klj2rhE0i0l59ff7hDVjIChYzEqiuk5IQE/+x6Z7xpK8nElw/Iv9Lvq6u/GHzv4K9u6fpp lpWCpvi9h3tNr3uZGakkrXX2UaKhZHyNb3FaFTpJEAau3WOn1NakbeK8HtShEmJ0LLKcBtrhRqHp V9dMXd4b+qW5OCq55uH7sHb9kPBQYeefQhpn0Nha8lv5ahJIyEYI8E/MNa+peIPfldT7PksAJSdA 725k7WQjoqdfdk78FsyaOKaCkZu1HLOKK7wig5b2FJd1rSZdzQ+ddkvqJEbbmDPEfBNF7t4dT/eY NeNxDz50geosR2dgRmYA7fY8GRe/F8O54qqLwyScqXs24/zjut+oEqkYEZ1on+GblTlQPVrAFUC/ sBX5tLNgRjo17dkrhETr/CkjvMxJpGUuI1EUn0PBOEOePVzbfGRHHaD+V+OZvfYNtr2l3quJtn8o 1suVrEQPLaW8KiETui8RwJmsxa7hQyMXvIdGnCZr5AQzi4xV/l92GWInF/25gaMqh2uJDeCv66QH 8PwPGUktkWPw6H5ENX7B72krK+mJdUwdwZshDoYKuyzaX9AW3APgNwqqjfaMURONelDjiOT38v3q gFmsR1OB6UuI3UfC9cpFqjyGecOZucR5VT213Yc8Oiu+cmw6qjChnxo2tWPB3kl9jUYhEdLpaDCQ DGnTodRPcUrd3UT1VtpAcu8DAO+T1+fhYVyFfkd3Ai+nz4NsdXNDQalW4y0WAibUZrljBIwHEU2b d3S6xvD+7nBzhtXmsjiN8GwBLs4PpmxkKrGw89T9QWMNGDaHXYnHCfw6CyU7B91IAY5HV0KJDHiG tZxJA/2jq+RsoYI3YHs4GroqZuaj+CAAmGI6vlX/wisU1wlRya1d+DSzGEHp7USE3dzdLWCotJy7 rULKKUuwEDAGb08MxDw+D+1P3qrKByRh8ClZjRTYr/PvxnBuNOKzBmnWXET9BoQRsaUV9vgCmaJZ FrrtVyGT/gvssfX0WQ5dsqU+mVEV82EuRxoKUusE1VxzUvN3mQfGXhXRAc7II6uK5iDnSeBzmAJG 9dLXuXy4P+ELtVuM0ITHJOkr/VwFU7zxEpJdeSgVRmHxqUVn5CSCVzFZfGk3UEdN9y8sRN+5ZhGb u0213p5W/z3uy53ECK5MJZM5HDWIO6EOb7kIYgwMh4DdvpbZFDNqFiqWxyB+YKn4jMIIKIfC0qFc UGg4AMOhBlCeFeW3JSfADKK9tsD4lhB25DyGT4f8dcu02XhUPdBZAJuLO8wNO88ZppLE4t2px8yc kdMR3QB+9ax/UHANwcpk6YkTJXgPtn67S1tE+r469NOe5CbT7593vnXMyii+eIDofFhobqvwXgJa lwAWyExKyoRKel7C2zC67CvEzFYRF4WjM8kgwYivb2PGaZ1KS8BkZKWE7jGVOebrQvOlDMvevtE9 Pat7mmouyjCLWS4PVkCd/MFD4xRduOePaesgFPBnqguxLfzHvb6hLrIEIpVIovyN53NQ+uJ3f5vt AfhwlRen9X0BEGQetJpxZYVYYMzJiQGDU1rJFGLUpRH9E6fhzLc6cyK+0UMkO7w9LwkQPgmgV/pL 2PNVkP2VKdveR74JqvfogxpKhg6TB5PO39/iBuXuUJapasxjcinwkN73zutMKEIUwg1NLzmVH99r Hq2oC3BpOlyNYD1T25kgimxmsFvir4cPUcis/55vv7/qxYw/2aiiVNA1cCtG8qjelaXOj1xn4Z0q XAR/zUaOc6U8Qb/ifvUzgQfIJaRmNzwGFYCCW8RlCZ8+H1yHcU8t+uAzy9swCGsEd3V/OyxRGx1Z QXtBWBUree9JWW4q2ESVOiDKThUudbUPiJdSc9fnjpvQ4LD5dMZov0FNA8P9FAdwHqu+RD6swntb yLiXvXZYI1Ud9JkcD67JI+mMqu03831nxiG9gMMOLPI+DkkQeJrHSxOQkyL2pRrc7K6rWe5NLZod QRagAE8egxpyJHmt97LvtUqFqKUnCtCVPMqANM4ST/kPdrz/a0KZ8WCtXrY/Pdi0LR4AmTmGDpQv gVEiOBo4HW/DduYdQJPwAh5t83lJUQJYJEZQiMTBvGi0pz6ZORhpErSEMIXCFQ4aQ1n/sYj0wUtc G02iTy/tAnjLn8MYiw8vmysW6bj+ErGCql+ZTvdtusDyOum4yYorKe1fER8stR8+z/bBWBdHa1tY L5GgGRrlw4ix3Z4liG8HsO9MvTzjAn95o3QJSihSHVCsU8G4xo2cEiPNzHbLdAUcdT8ujv1VTtC7 uB08NLkwb7LThrJgzvlBZg2xjzkW6WEi4Ac0weQR8UVJX628zRvNTYuiSt4jrD4V68icJOYHJED8 JM2X3ku0mQPQNp2tqyDRjQ2+bBO6TAnXrT10vSF07i7AcE165P/5dZNhDKfYLD+x2ZW6rhukb17m Ir1Ma+gi8EKcwn4arnh4cBmVQMgXiP8GerVU3vBbg0T+exFOYtmcD+SRKYTejI+/l+g9JXnyqhD2 pMe+bx63Swdyx3FiZ7Kb4+58f9yXjvTHuheA04e9VBo6WtBW/HQbbcT7kkOLpnZCDdMTGUj+pu10 IiaUjdpXUsG77qyk6MWiNGx+VUeDujCKklruQMxDkoukWApLFcyFXKHkG+EsVOq6bZX2P6PuT0S5 rde+ae/5qZ8Z6AzUpSFRdG/cYMncB4Njj6uq6nxPhLTpXy/fmx3Ii+Vib/AvyTsymfa2CCPKf6Vb EUyxLlZlAWsIFqm6ZxzO6HqMUysn5mV9NWIxAYcCzL2dMjKcI4hYI2S1ieak15xlFh5Cs+CvysHC EtKPUydglszvlmYssfdZ6xN9N+eSWbtO8AwwmmPSIHcav3rtM/0Zg1lr14Mjdb4AwfPY6js8w68x E78juPn0YjpZ6Hc/Fnup+3FnTqhwyJt4pGzKm25qMpByb3oJWHUojboh1U54UaJyY/DlILbbRpOE spx/1sn9DOh4hnOQu24CPC+Xg4MBhZmzkeV826G6AoYAQHlI2dOnJxqVZS1rgP4GopJOH7+1eX/T ZGkMzEGjPK3W9R/ds/D7dADpQbjHHjqebcrnyrbXWF6SBZot/BKRhFaFOJyXG9vOzX6l6aVu8moQ UlOh06wH6RcK7whhq2cyCH+L7hFORLQvYRMKfoFe4pcafk34CBRu+g8Urc+e9jCpWQydTf0aXdJM rDFiPW2Zj9kPI1TCqBeGL59owBj4VaX9BTClMQ5Hkm+iaFpR2EwiOE8yBOEjZb3n6t+RjJfIgoXu J1QRjhZIgbM+RAqripHVwDrwbzYs/l96wASTDEx9w4TMPmzR3FHXmZwchgL+VaJ1yykPkuZMk7oM QF4KkBwpi2nCqFczdJKcZgMkAQz9R0iBDC9VzNnE0e5dLI8KQTu+0iwQ48/fnszEtVWBzdJsPVii vvnMLzdnGWNPed4wBrBaOXB7Vw7etENpwVbjaZrH8WrmyhewPqnusUgySXV5BW+9sEMfkBICT9Qt 6JtZsJoWJQPW9eTqjd7f7kGrskV4L6+sgZEeqF1+kTrCM+13w6nr5iGdt/ZRdOvZ8hrSFok0MZ2h +ZPLDQ+ZeXDf1sFGaJxfBQkYGmba83NSZi02erDomLPSK/Y7wim+v6044WIWjB8GGT9VJlhXGQuh JfAt/NCbrbG7ZX5toa/XwNw4iQhiqrJtVQebvyNBKxDcqpgHjV/9Q1wot5QvHyUhg5d3B3j5uQUk ZLRmFsjcSRWKfNn/2kGfbQ0C/aRkbdsA0lO45kYJDKY4zToqqNbhnrxACRYPuPbW0p8He0t4Cm0U 1uqwAbLt8V9NBxLfxrXsbM1y7LATsYq83LseKJ4JUGhZRu1sGv+XwgXaTBYNk7CAWfL/OnX9jDj6 2/aOMoiSRcPXNcn+7g930vnO7vYhk7CKNllfhgG56PNyKFhRwTARERsJ61ZBYipT70r6sPlnICjf GEkoRpYL5keLq03x/l81fozJOlF6CMf/SpP+cWddaa/3AjH0CHM38lQXPngiSS3QmmOCrLgth9QX 6PQ33F8ohTe75j28Ty2YinJhihlAczycmOcDiutp/RU3djrtxGoq1Gdu9ezboDmVSiCAXZKHMkgQ Mr24rgJrRw+l7y5Syj6O8mj6V88niU1MoI0ksUULgf1Og72b3zehDS8n/0WQs4P65o0kztGEupg6 vWqBwTD3X0hdDJkP6O94L3P/oyTS7cB1IR2wU8K7f5EdLPhWTqHmijBBLX81xEKyffo8GsyTEnbL aLCRjwDPHGjfF1wSf5xCRk1qux9HWY3R2mSjsKQ6H5c58TlecCX+TILXAtcF8H8sbWBiRqYjO2B9 tXjmMEAuWloTJ/mHYrnNlLI+gxFf3/IzwSO6+7cxZqHtUi5fvCZhd4vbIBIiHPUPY5i9roFP8MQw xWTuB0FaI22cEakUwWcSa2scvJi/WNtxPzWQd6zonxmC4EKCM+Opxds8MjLf3aEHo1rsTstmM/hg Vm6IA1k0jBE/6pwIwJCIJ1qaGKHsnav03gQmTPxabvHn7uhDe21OlN93DrtBYrINou1Sot3griQE OZ1vCIW7JFp/i9JfdAVkaFV5OA0LKNZVtCnAe12B/QKFgxvkPl94Hko7ReQTvqks32iB4sJBpM3a jHSpR8WwqZaASMjlr7cesBNPtvhp/wR3YneZYjusingSqTwrsxQOhQCqJmVWYIAFcJmpSUnc+US1 2OYYuPExCaFCfrNk2uIU4UmaGPDPOhGMccSX2CaFAJ8LhYBCQmCMeBWVm3XAkfq1a7GK0SMsJo99 zdkai/XbBOD4rixStIK9SMHeBjesRa6oa8xv0nm6OhH/R0mUITjdpfy7DJ8safyK6siJ4bF1REWb PnO8BmD1OkWhap7tFil7erCu5CKP08Vh/ToWprruNrlnALtJaoaKvrKvwnTc6Ng0XeaMUND5+08D 6LozdAsJOENgOILJw7KBUJuXdIkwpQ+tP/L8bKV5+vT7OLRDrzt3eTrWHGo7aQWXvQXH8ozUcBNe MtFAJ1ftKXx6aBhBDyV4LqI6zNDhhmTL8937mKvyMapELNUdvceIaMLCqvRq26lQX3xX67wmqupq ZC5ttC4un4c9TbOPAlTxierfBoMB8nTmRQBQCEijlzaSUTVVAo2mtH9QzlkbuOzyuRNdFEyQiVvO eGFBXTZGAs1PhPitZWdsUbcx6s5VwfrKPgJxv9XjAu8iSywLmla5eENAvnb7jvhyZwQAwz1dNmU4 9RExYfLZj1D2uqhYkma6PbiM0kp37V4cLO54QzptN/a+aZ0tDKUFO0Bqus1QYrC9rNxcUDYO70HN h4XUEhHcxonL1Bn1G0axZyi1CzqpLAqSBmbwD9oFpLcl1hmrjljKXruXg3mgfgBksoloBcGdBi9G wfL+oOSnu3iCbcpkHdrwEHvHYwOQ/yfG1pAgxU4exd1LaOIufeOOwtcOQzbOSAFXacXA1n2iKo5a y1zOWvmWGR1n3iWI6EwnU7st98mRAQX2XREGNesNw0QISjFACzHqpWEmN30zejUmWWDFyyqkVY4z fRexNAeiSCPJJ+lV7rB1fUbgdKQKftOTqVP3cBCYXeI/faG6mOTnUp4U0H0QRaBBrKqXeKgcKxbX Jwmkk18RjFpC0yoE2kl42Ejh8hvb1C4mD1PrEmw5hIu02xEMCdsUfyBrYoe/pncG9TuHZfmTYQLl QmQhqRW8BaBWsb+Q7CDUYZVjA1fz1OdphPspJumtR2+ng+KNHpsfPFZvRQVvv0WItoFPDxvTTpbE +dC3jMYum3uDAdbNvWHGDbGfvoLyUSAONMcQvTneKQGeXcewbFsQ14MiFc4Aka4ikeOyxw9nwtMp L+4CXtE+fISuugLVTsTBiemkqNa9mvHRHeLE3X5FNOJGjaKEOUfOw7USi6tkohqddeXle2MeMYbt CRlkQ08NIl62xWkStBJfwG3vf7/YJnkqDpgobzk7T5fCRIDyY1roG/8H+4L5x0kOzz7EexHRbEWl C4ZBXB3uWXWCz2EaVWiGSD1l8Cl3d51FuTiSjItnPbiQ4CLXI1fPPDDk4TRoZD9UYGDjbpzCSJC8 bIu/52iYU2dfxz+bUqG8vj3so5QPeA4ZTHnDvTzVanR+wC0dyvTKCMJJTotJy6DCXsQuuFRMnVS7 wiR7Qv+8R6LOxufqvtoRU4k76SvIaYOP4gv6+gmsUdoo2kj6DojylhPhGTQGN8zMt9spZobEhoeS 1WVEjQu6otL9bboY2C88R46OqtaS3XP7FwTqrk9uMYD1ITt8aqTRDx5JBHmlKQRO515pnT1J2qgl DPTIGHiiIDjsWVlvhiRoOHi5kRxFEkA/yKChgzECTDTAub44RSYUqmw+eEAX5YFPu4SpKu1BbouO 9WfMG4l9awCNNiTXtD/E+QHP//4AGpnOlClGvQlf6I5gKz9tWEbAMXzW5jzmH8l5H7D7p+74Yuzo 6aKFllNHmHFi9KMN/eFSbqKpbsDWzMqyKrZrsntzrQKrPmfgXzPCVZSl7YsWepdgUB8khBZBmqgT 2hUqY/jiuoxiH8nH2Ti0PaLsXXJoqYRD5F7tcafIlz2iM9EWboA7jnHLOu2jFUDaQOj45DTCJ7tI 8EAp3hxQyJBzo7jOu+PgWOOdPpevmhSfRNmG/LuYcDF4eClCCaBsYzNaBZF7fz5vq4pJkUaJWa0b dN76Ccx+Cf/clEeD4nO+8H0q4nYOCLtd2rIxf4aB1npxL6ByZumFwE2Gbm/pNa38JyU+4Bi5tV37 sxvklMytEUTYYBZXkJR/nVhsHtGdl3Qim4b/rJyIURbPQLXQ0wCgeAhX00LKTHde2viODvrMeJqi 5OQMGICaak5QMcE6OGg1N63FAMUbsDCam21tdHmUdSPdfubU4bhh/p2XV3e8cEps411agXvhNGY5 tFP65TPDzB7i75dkghEZt/K11Sd9wEdhhupLOxYpZiing9ZR6fUVUzI9EoWlkOE6SIytx8FTf1He 0cdAOFxSiTAbFoqlkxXgWjHggtKE22afjlO5zJ2wWg2xtioqLfKs1ppDd67DKOcnuaCTBkKlkMtJ R4zbatbOF7LFleZM8t97vJ2+yynPPSGZu4TPnFnCngYGRZysIBpUECriUZ0G2y/16kagymqTf5SP B/bQfClQm1qcI+ysk27r2tl5ogHLEmvoqZoIe28Vd9PDjT31x4/vwBZaJZVxDRfe3UAzcA0ytNVu l0fpOzh9kQnH/M9DfWaU4Ggs/vIgvyUZ59A47jtSmdTz63RW/ufVeVQgFa7APy7TOkeDF3CbXL85 k16sSNHsXySkpQUD8Dkgq90pSqTKVYe5H5jnoCSkhtjx9LYhdKh9ltwF+G8v259C3uDUjtoxDmm2 JJaEWxPxE94H45oR0ntO6ml1xRe4NqcCzGRVdO8iBwHZ7WAmDEdS4xOw1MC39RsRYQzfzstaMMkm gEUlWqcsji8u/Xbuk9tbTouPL96AXOfhh3UzSYmQtSvdJz7zMSrAJ5VH9AJkr83O808aW9n6f6mb yzRmrnWPNLAbvtM+xKtOShtLt1GwSvsHna0P1G2vzuzYKnIfzvEkL2D5ylru9fZOxsuyYuh9V1l3 qHYeCJXjg1Kqe90tqLhyWKedErtyu0bp5ygpkdDylzX/EHshzcso+6p2pTjPERg4IWOc31RpUvhl Ew0aCRi9OTelJLlVXI6yVvTJweqUu9X8Q9jwjJiHYeFfzIEH5oar5u5GlIy6v4aiKD0l7cHSNytd mcQMBZtPDQCED/wlqPW70cxCUQX/eepMabDoq9MLvKcv0M4jZTbf9sHQ/rEj+/ydlZwRovBofG3U YKY70HGuSQR8thRtXXJWH5fkJalwmVpo5YMnAUxho68vzDk1XKv2ZXvGCd3AqCWy0TTobp/FeUpt DY5P1wa8v+F1IQNCdAQQP8DLuuHWuHi4pYTDt1bdVaAi3tQOX/rUCcSorkPMKYdbg7+cZuPmdO6d qpf5zScjnoLe2rr21WpwSndXTyERT1tPL4uq3trmH0I+cuaihLhFCU3R8WY8MhZYy9PM7J2NpAJo rxHgwmVttkh04bfj3DDF1sAJPjpUpnTKHBrRK7egs6XuEN/M4+EOyPIERVYag4EK4Fq5cnTxg/rZ GWGJcmvvAsyg1APYx2fWmGTuHjobr6koKYxgrtXxYawmyGEkwY5nZ3mCmtG9oqB0LzExQemUZyv1 ulJkAKNhW82T17roWu0dBqJV0MWC3vHfNLCdvRGBVAQRLXYQztKbqlbaido41XyHTuhVEZyz3Su+ teYkEMTEp6GJYDRE78ikNS3cNclKHE3CEr0pbZcvJ9lvld+qG8zKCAHyKNGkAitZLsmBWEyVY3ho Fwz6F1b85vFiBNHxh/dqyspN5XHbHa4G3oke27Pcj4rrS9jVcPjW7yV2JwO4tFRP8flPC9KcvZjb /oUZFyLFET0NnX0kJ2SXJF7gpNlebhRAEkTK1jUXZBhWe6Y5Tpm+x2uHWifrq/Hos9Z/hybAWPs1 UffkpZQeJjkfMSUsq/jRXA4tmEAFuOalFO3xzb/xqz4Id1JDxAEllnkOEf+ZyKml1sstO/095Ajf AM0muvD91+D3Wzy10nvb6Os8mCwLwcfU+Xn0hQBnYPiZMhnrHQx92uLP03T4E48DuFLjufW/fJE2 T6Lwh1IHQoy0M9/hqNT+R4umsc7+CN1pevMkL46o2EuZ2dHT45I+Cu87dpOeRZh2tV2NUKxBigOq NaZzAUGMgBlmc5uV76skWf716WxpVP4Ut7uvXTbn6X+fYTQj5kJhqV0tmqWeaye48f5xXWdXBYsv gHr7YlOnkAFR4HKeO/AQwWhB5vOLdwBsh7suTklXXQozeTqcVYuMH7vl7LbfGnjEj9eyYPZuYgPv +7p7r9RyZn9tCmkGhHVZ+ZrsmWwITR6nI1mxb5DETrch3lNLi2NNGYaHM7a+KR+Zg2BDOtaYXz4y 8WUH5i+4meLJYmwL2PWSBLq4sOJhx9q+01M6rA8jf6pAxFGBNgrO5fOP21wcbiwt5d0ZE0l1dx0L adxL1BIySYz9wElFhUwqCUqAqn03l2wKsjGDr/xMBOLRbj6crLpzr1x2qUyFMB4wbkOv2n+kkj+u AeLbIXilHr4HsR8Xq3PitPNHkgMqvvkwgO8lZtYAL6Fm2grVQYAL256uVh6MuMpKWqagC5ChyYYU 7qUyoLFRqcccfiroLVSF1AWMAue4KYdAXJfQAdFi418EfhpzYTh4WEynshMzzTLz/Xz578F8L+aq R9SSaw5kjpJZt/M7d4qJnZoXzmF1XoYmdIJqasBGhYZO+TpGIKVkkWb6xHN1+QSrUJ2qIcZigiET b2pXpuiaHmWXu/CoNDcb2yvcyrCTrfYystz2/v/sPyE0ZHsfTG/Ao6IdOHuAmbA6B+2nRaWpT0wB TdReMZ+thsbYYoRuEZnEXzIyq9tGXpEAQl62a+aiyaD0/29BURJe3pvuGhpkWo6bOZnVh+k+hipF JLnsY71JsaLCvYduukL1gVif0lYgrS6KmI86TWmn0oXQRxYliTsVRlL/9v/i1ZJ11Qyb0lULYmhz ovAVnpQZg/mDXRx6Kq7UanG4vKUk9ko63Z9bscCaYngxSCFBaB4QXkyqyJhSkoUHTArEXJUJD2oQ l1qW3432NMsXiMTxQ3ZNUIo24ze7MZHGFFf99Ie3mO8nyzwWcatNUcZlDYxKBbQ9+dD//MjEjJlW nKkv3j61BK72ChywYfjcYque3onqfGqooNuVAlYfEdQyfBNcErt0wv504/VYuypBqM7bO6Es+Sld N9/i54WQXwgoj8gpGPS7NtaJKsRxvRD498kugNnWgpeb0GQx2sJF+lrYv9TyodI/DKggn3oJTPmj W0IqqfoSBhf8L8AvKJd73gy8caGdxQxcOphMfRTp++ZAL5k6AWM7/iRf7qlXVVS+UYeNYN9WI+YC YVzLBu2ORD8+J9l2OTnyAxQVcr8a+2gS80rcvRPehVoN6jfPcAc4XpywG7ak+X8oAtvsUEc2729H Cqfdu3JUSai9yUbAJd701+6FCB2UmU10SaYjak7B0r3liFZyjKSsP8f8yJGn246WxV5nqzo+a1tF FRFxpxOACoF0Q7KKWzYhW+f6ceGZujVRXU/3k29ImfH0idVFpKA51c8y4131DHAU1grWNrMn+j/5 /0Zz7VbDqb0nzq7WVnp1Z3a2O3XwiSeqdDTiwr8960Wz40np7ujOInC37IvjPGOKo4tMNiAeV67N h6E0OqkamIpzUSyhUMsfHdaISzmJbhJSBWLXNfTJGQ1oUUg1mRwXImX3rA1GKDwPWYj31peKr7yH E7KI3sAn8Ujq54BCs9E9/bBgv/X7ilis58nWcfRPPpL4Q/V9c6Mwa7TQWTMo2QtJYrChqJfzNK1z TVwMipm6r6LtRlHZT2Qv2EIRnXxcWEbwekKtij2inbAD1iRJsx7NoKq+9qLlriSQ04D7DKPOSOLP T/knvT+S2m676P0PHHn4eCz55+YwQKOsg85R5tK6ClU0a/fVXD4JGi40GepdWrv5HUIfBUEiPl4l l5wrfT+h0UHIZAcRz5gmrrmd2bTRSWghN129FOi5oc+N1nXRqpPsFarc5Zeo4wWqV4wltjZzaLGB r6eflsXolq5CljDDloa6+KHq4xAFEd8OPm7TUrjwlGvMNSG0XwJxIsHYZB5gSCJc2YFV+tX5/cs6 Lsc81AmiwR6/nzUr7Fi83jATEB5Pb9PzMwWm4Cr80c6hrWG1rKZ3hIU2z1HPVeara68nhnnGYA5u 4wiY+KazPBtjRm2CO0hM6OzTnbt1dRDEhykbN3c2iuFv70xO0wZpFpF//mMBb4Jym+6Z7UggElNs UeEt9UXf17rq5nMuHz+8r2EsMpAp/u/b6NJY/aHJTmZUaVASCY+WCMH+RlHU3rasv87W43/C1gxe A1ANDRchJrvKW5NS+AcX+/5izg4jvTvIBj1Q/U2skJrBCs/ZSz2+q5liMMnT9ZRNfJOZ0y8/4L5u T+LlrJkcYWADw4zwRCgGeFwKzqCkWrjLchR7IjJ1NVtWQ8LBRaCbVnmbet09jQwlL2STCc41mr30 c1Gu48kPOlCGm6mJJYHesK4JSAzCKg8Ei1mb1GIroh2b1dA40pqxeNcdXMVRG0hx2FzkHxItKWwA nfW10kADitjxjOZSEJgD7jzb2muu/xjP9tuglt0p4P6Y9ETAooWEma1mNk0b1inryBDUxvy/T8hh mYxnYPTL2NE8elxuGRuDLdf/+Vg8LA2pVzA+S1pjENApre0rsIS5WusrVbldBlfoaYsJQqnlWV2f KDcPXHDKuzC5SHfBx2h+NwqIwy6uKoJNBqR/biQ17GzxUXgo+rzr+GwONTy6RaRBIWTRag0b36H7 U8Zo8ja3jrcaHudjlU40CUAN9UwgYbOzQyw0xt60o6nu/JT6UXbPnETO7QwP4EkUmXx3a7vaVhdV CdLvoIXLCXalohnMQC6P4DxF1W3gxy8vuWh4US5ZnZf1wh0J07v/6HZJ1Y1ob1+qACZ0hO4cwo07 f1ojeiqBtIg6dzm9mkavfyxtT9cVsCtD38orTfIiAxJdpyjZ+nxkLZXqrYAJVGrYOiSu8yfsO6ky H5Qq8Sgrriq1p7IGde51KHryzpKnfyOuHf9VmR+VQ/eugZVh9UPQgTRxJt9uhaTVYh6DmFcbZmPm 20gRDHVnmSQDHcP+KewF5khoAGXYwBdt6HMtsQ/IKkvRJmbTJ0ckkmpP3mje4gL6zDp4qIBu3X3h S9bRr3GCq6jupOu0yhrWq48Wv8TnCGlW5ihfnV9so8gvKLqELib83QaZ/4lW1HTsGvZ0iQ0PauHP i2IhfCjWOXPxKIOhVNEx6JI5/SULjA+Ei52+/fkbij7yqzf7rRrZJ6LfO+ZJht8Dl/BdKYkaNV7O X0KsrTkbKg/UYIJby3YBnCxQkLX/RG6Dz2znfFzOV0uuUnAPedwngRe4eoKaKVKmwo3UZeegE+U0 ZD+AW5v8aSx+Q/ShE5LPJfewCExL7PIcJ/rq7onzSpJLHMEP+koj2I8WPxvxQuravlapzMXJTVwQ 2043JrWe8Qc9mxyig5csqex84QpD/osiEGQQQj5b8VlwS4c94GKvyOe0i0UYpGeR0F2sot6C42ag TDIB3/flOu87R1MMgqWllNwjFToP8fCQFQ9kGHXnJlMkiOBbyS/QuVMWNPXwGoY0mm/yqS4+g9H8 e4l6wMjANXfF4Ud0X1nfmRREu8x6CCJohX9LKXV0+Ygdvos4boGsvQcpbCVvw2wjxAdv1LfEC0gy pZ52o3vB7xPexxbzbMfiVlhRJp/pmTaLNqTsD0mosLmRksCg20YPEJBxL7eug7KQkxS/AXxHaL3a kk4p4HG/qrYV/ulXf5hZiNzJ8h0cY7OHDl7/lzFFSPXntntqExHqtOyUX7XJSg8MK697uZFf3t7w bJJDKOuXHMc2ak/LiS9Cp4GiA0g30dmmN/a8B/6X8s2EcEgUEQbwwy+/uniwEdK1c/ocoPowkBqT Q//55hOeBmiQiqpcC8co8+ppp+7zBB1HaOpnSEro3GxXyv7w3rt1j9yK26HuGeTVTnHG4cu3ryJU zW+gMu9smE7I+XzC8eVmaKA9Xh0re2lAYYIQYO+1uazKaHhrnKneW4DzwjabDj7+By8am8QOFAsQ NEcnUaTMsh7wsMjUABNpx7yMiZlz2zviokZb/CKtuXIF3DERHSN6IKWu0qibAWsOHwOY9W4FkBJy q6v6FXWC7eqkieLz0mtGMg3ogSRinbmajDagHQ42OefJBf+Hc37CHt7X3Mx0YDiBUkIkcCe3JkGz ly9cl9EbR38d9u1LJIlprkr955sLO5kIhau2DfTDZkWS5TzEZsqcLvFRIPuLqwKS4Ir6K9QDcrgW kGB6Gh42BsdVey++fLOiAMx7hpHKpK7U7u/xNbtstksZCdSLYuHM8ShDe8k4EaHws++vJS79s3Ct gJ0sA4/qOxCLbhfFoE4udgclA+l7zqNct/ORYbrkLF78dElH/seZJbluBwgz3PFZXSVx3vDqIKEM zzHALkpuCqUiaUMjvfd8QP0ZnLl0jfZQWJ2oWCEk/+9R2/6a3TOiQJlJuNDoO9upjfnxB3lWr7tl CxVrDlzeERJvxzH4ttObHdRIvOF6SngU2eJA0hEqnZKgD671Q9cAuSdPrq9QqlLfJlNrSEp9PMIQ SQXT+slg820WlH9sPA/+oIpON2jn1ORN1x9C6l+v5c//73E27Dr2A+w8JR9+XW2D/4mkJCv0kr/v sMpR9OSI90D9lE/nIRb5DiQ6TCf8MN0omm2NWNtEvTHkdxMuKTbWHsW93Yx/Nq6dxy8RQMqimnbw KJAg3x7ZvCBk0aiM8SCjcSaVhk5dUOZwmmsD5XFn6zt/0c68RAyMwAA8YRF3NCh6zr6GXvWafISD l/OVzqSm5WHzve17iK/tciBSCFcUX8gsOeuZwoh7PzfUONeV590KvfVxPYWCKTXp2rbxQWN0/+wC KIxs35rxasu9hXMIRtJV1UvIj7Vckgnf/226VCCFHebJCnCG3nnMGto13sByn4EcQzwj1Dp8i88A lEJ37TAgfQigY9cuRP/D1re7Ut1MhvpkobjbCVYn6XZnE0ahk5+o+r3WXu11QqPKu+vHS0Urfjdh gL/MKSNBwXibHkqRHeMQJ66FRszfsVZySa8JOiO6xWuiLwT/om5+vnqjGwEzSicqLnHViOOdCZwL p/TpdyBEV306KYYRbA58kLDqQUqQh5Lse1VjBcQ3uGL/yctnN7aZ3MeGXnONiLIeoQRxxl5fo5IL pvVX0N0zXuD1Y2ubgMnR/VwMBjyh9hRkGltS6a5GaxHw6KJXMc6cERsGoQD+fAxxNujWvcGNgCfO UorPhx1uxkHrueDEGY7J8OkmPLmewMxOT6zmPBG4x7f55VXfODOSOeT2/Z5R+r2qthJX2qCN6gJn fOiKsEwdrhJ3M2H1kJutyXTDr08iIfQZU69KU0kNd//HOeeNaU0nq4Hb9THoFg2u70eRMxqW3j2x sOdgpY6ZkNIZ1EPodwAPMppbXK2ewdzqutzuycAQV3vyOJ4QAS/wwK3Ug1O/f6TkQEPYd+6VH4Mw AU8pYp2YQXJU8J/A/tCbeXap0lKyPfyNEYbG8M8538ojrfC7Nlm3CDc7Msn0PRi3F5OTFLSIwYSo iazgfkirONHl1JD0zNm9FnijfXP2FEz0wywwA6zxlUSovqcbmAkUt2eZomurRE7cA3QKQTRCvtvM 1bceeXJ8nTGdC1v/E4Erq7+LGbQ6yrQlpx9C2CG+2tStUmsWudNrZxWoFXd6Y+A8Inx8H86GlSDA YN0BLbUYAbIHYfVFuSd2V5OtGNn3LmXj4mbylcRknoUNNBs2ErIBZXVy3pRB7yiMJzmw/9cSA5K4 mrTz8RRMGpPGL+es3kn8zMLFPzVsQrl3WNs1ygm5RLZA71uzGiv7vvwM4JqCH+c+cJI4rRVBAYAz BG5mRRD1/HrDGrid9pTFlEsj8Z03010S7Ne7y7G9WgRdaVFgt9oiSuQSEiU7bftGmXsOZsR3KDxE bm+95Q2vfh7IZRJ15GxKDN4MWKSRdwT+bm/evBjG+Vs4ZqcynbsytUPJq/TdEO3Sn0QBfaOD1eYp CeiOzjMtww6+14PSphYcT8JgzHPHXbwEjKQQyyUUbR24oB+nRZiT75LZ8slPngietmycKo7DlEOi nFKj/mtd0jUlvpNVk+2sqSlc4hNRgC96yn5WVcPj/xl24gr+5cqdNNbl4xtAEEdIHcDUUR5Vrir8 LIJdwY4B5zcUr2AzUjrcj+dDq960O6ndxQ/tF4mw+dV+uwiIVpBAskB1SlrCjc0u+N2lPZqQqg+x ihOy9KoiszgKKtaglBwYCHf6xpx84TZhJN59Xhry5EAbEK3wbmsUYQJAUkVKDIDrANt94qaxlvaV RVC6NrYZMPEt6nQaO30g19toCNwxV2kHtLWjb//ZKOqM5hHGTFTKg0J9GtCs5VRvQzZWQYf/lMSf vMtBC4BAHsrYTnEKgXNuaNe7f292epG5RcSbq3EZDnoiSunlz4AwxZMyednS+to99kXK7aQbgcON GimANQZwWTDghYQlePb4l9+2HgGrJ9Oxab13Py7ydBv/ogrHUvbzhYOdQWe+nZzQGDaUCbg/S1tT rGaUl0JnJTuxqebA8F9Vx6dP9uBTedNuTSiHNXIJ9gDxzeXADeL+9YGfzppsyQWopYr2JE0LdYSe u9lT33k10ZABiBrW1WmdUNuTzGNEhwdAmiW7tBJ+iFAkHbQ7GnzH2tZzlTBzeBw/i7yVu71nSbHm 2czqYM8PUrbFh7bVrdur+YaPmKkgb6BY7es3vADXRps9kH8via8sEwODVxj42CTkBESwYLweG0IH fcFCfWsPmVB705rb3pXAnoIW/tHt5708VyIZK15tOHvQU/uaWHD1sg7dfzZ0+2D+FW1r6LyfdJV+ hmCWFSf+Xb6fGC2jMxD2i6z8dM5eoxZxcPFczF7pl/e/CALvHvvduL4TqAmHCz4eJixXAfJrYh19 eJBTVhEj3Qc0yeR7/paTm4ePkEGuN+R9avW0LgYblr3mlO5q5fGD6WLLD8VM8de9hAEgt5FrogE5 OzYEm7XepDJt3zLHTtn8AnRoTk1rHRxZ9ulmV1jfCvAeMB8+dVYpMlFHC1cxTJD+S5P/Z6jSYGcy B7zUKZ5JZOgAUsUwV1HNU34+2NAm/rL0rDZ9LHIfUNO/JUXSMhGJ8fq40xu3TrFt3ump3+apIcjh 1yzx8ku24e+pHwQDT9oyQYcKARDti9swhp7l16mZ2HsRcTAN8xDM8PGx9occWdHvVWZqi0MlNePQ miAdHhNuNIqdAFRUS7CQ7ZUfQO4dIUftqzN7b1OU3Gb0HMJgSJInNREN5409m7+deBtfBcigNtd4 M7DNlPDUWEd5Ri+q7HP/ahKHSXvTrEiV7vcx8DqsthkXxE4Tg/I+KnjG6cJfGD5cd3JwCzGe4wLC uL3KyZh9q/3/tppKUWEKJFeF0tar6uSe/2XidLYDoV1bZOQMx2it+T+eAB7UCVLlXcxwSYqwSBQz T7/iJsiyFwH62zhn8nZ+XJtqoPKejZp5whDFJfHOKHXwutR8iEF1TBGg9BQVl4GUC6n3NR790N+q YhLwpVXrTdMgUFdWN97EutTKvtS+nJ+9JfQCxvg67u5tsz6vujoREJckQd5d0oN3WPJcm3t5nGL5 I/7ffyHXWq2Y4LISVV+daxsx6/+3jBt8Jkt0Y1rTNPvQvXFf2bhUjwncz3FFPpNpnrTXRe22LFUk MaD0Qwl2h7/zHSKzqQfW+9Yzh59QUPo1iGnnm9iTsgwMxfuDVEP8bf5QbBEwcoKWXjW70LSA3ud2 5fX6rkZYYcNr9mPzUdcVtBRPxruAB+aH/SFzRh7tpKCh8xx0TDJsMF6/OUB05tohynhv1R0IfnMH fdl5JwmK/2SQqdL2SGbivrGsq5Pl6Exg2x6BnxzXZoDonVFpEFnRqnuD2KXuDayiEkNc1PMJTwH/ ACnVa6JUuPnc6OcaRlk0M/2idI4DG9UaS6BGMRXJsQYn3uY59rcG48W7nbd4noCQDRpycyWSfP+W CkFfTn4XmaB69BN8Qa4qh3krZ9CpW3zFIGnQUwFUlHRKXMBWt4YrkNzBVuEvs5hQfEMI5bYvWB8q P50vsLboxqVTimyF/tlxGUQHpNoI3psjj7n//lrs5FwANVBNfrdErTV1aLlswmF1IWmjD7uatkj9 rD807m3bpZc36DuNCyi2YPy9GiTjOz956/jlpk6tW5xGkVd0U3aSQsgpGcTi4NyFjD0IgRZroOE1 gfqyYgmG2jDD1LFsQPQ1PU7/ph0jpreOzUsBbnWemJJ+tdkAIaNR6o5FFGzlPhVJhTdlrldB8MBd P1bhPQjBLzlpTERMfQFRl6DsalfXhu60Vbmr2UvR3aEMJhv1BJvfMAQrSlh0byd8lEG47ek2gWfN r+dNNafBUBInCt87ftvh4KKCwVchgQAZRFbXkW56f/9axYoPcPtyARO0syKJB2F6RhxXZw/nb0kE lHqRpx5Ws63KsS991yoCqvN+qAKWm0Wd9qJyFKYb/fHS/pPaszeG6sxe0f8wEtpTH84ErA4csaZ2 8lx+23OmjkGxPRSyrwzM4xqx+mZxREKJbPv9g/MmLVaR7sLr/RQKHDaqN1YYHhLRHzgAkdwghCX6 bOMDgucVg9VN6GpXpfSHdcYFuAEPu9qLYPpJ64yU31+UmVsjlTwtavJV90vRHuikxWU5/dwDyY0J APgqmnu50/ZATD2IDaM0dJuC2QOlOquWlAwbkjLYnLL1cZ346+evHZeH2gws3I/7MH9yGLMYTnEf mZabtOp9wqWF02hE7BrgSUQ02jQBWM6l6m4qu3tP5Df+wjYk43ickCDGInja0NoEnIbrffZZEjhj Pff1hmvrUrCGikc5nHlZE8RITPQqGGlnQlP7isBSlJDCTz/PGuSgKEGTNMgy8xhqnIjIjLo36dCU QnDRbEoMGPJs5KJVHTE1H1pemw0TASX1T/Psm+bokO2InzVF70Ahsh+sSD1rG/6vhdorx11SzYxa m6Rfv+yMFV2jRUnDXbzKIGnFasP4Xy/FYDkNDMAN1ucZbD0nfcfPYrsTkiAuv/cVl53+LHFbSE00 QuNEXNJfQqn7+aSmBDWGoD3SL5Z2gmswDcl4kZt+x3UTTHwQVT3wuh+RL+s084FtxcSvMIjUGHQX bGG9RWkRgDrHKRnooIPYezuARAjsif5msr9GSzzvGHw71DU7u0Xw0/Q94bHNVAd+2OAmBKRhe/tO QF+8bUqNSU0O1bKkBVk4iRgCTUlU/ZG6doEKLJmOxvQPOzOhJnMAdTX1DQEGgMl7iACOPpssJD0X NKEI75z2carCN39ilxn8LaVXyyFwGubCSg9vn6Xa2yQVue5Xqf6PHCFMM4f3IK2v3qNNZNqFF5EV wD6vCKwFDVSUGn1Sn2k0NWcDPa6vTvuahZTns4RtAVQiGQlOg8m95uUVH7TqDPnxZBE7gOM/0TSX tubRTrS/7NcN+26BowCMnN8FR31fmgBX5dtalOYv0Vnjkg4Q4CE6iDJOyHiYj9BEA5sMoX5h9CcH 6y8532dvHRIvoFhFCFUkmj1OZhziTvld/VfZ4TFvoBGa+p+dLYdh+tbRVIkZsv7WvmAmb7sbZSs3 qWO0Mm6nBvWeW8+z6OD0it+9iiFexuzO5cuYnPN3xU+YlLY9xx14tCT3z3xNLR8dkwf6sb61g0YE 6+ldOyrP2o99sch5lHc78HlzAWtg55FqVavcCYjK5U9HxwwO2Bn8s5TV0FbCmw/H9VFN1ZgM/IjK aRgYO+BYoJng6F+wQotUJ/ioWFbIUJ3rfKambV85f0oSVuMN6pm92eGdCKxGV0h35F5YkSctxnoU S+SDAQsJtbPOc/dRw/WakV8u4sff65OD4ARWi9OS91LWhAgyPS6PEBMWDAXkGfCrh4MdZFY7MOqB nSko6HHSsZRw1oHUANBRXbAzroiyF3yDRZcEhDsyo/lrJu1MDj/zAHS6CQgguj+zhNbTXFgE6jYx 5p1CUJ6j21E2fj0zeOG7V03EakqTlxJ7aDrVDt1NpA/+eb0uJFBK2YOj4mTV5MXmAFrLzSYtN3TO kBbhsxC/NyyaygpSOwGsDivJ88rzroGwj+Rju/B/htoOK5uq2chwZROCvaq6GgNEvV56+RNih9ab Y5j6yL8eGaVdNY3+xP4msgGdsg8hJ2wFOrc0hN/FJhPNotVlpz+Hucx41AE8NpnJEZ3WfqNL445Q DsmOeVNmhA0B/vFToxBFzW0JSmhCrwM/fje6V14PA2p3EIS0y6D4HeAhpoZeagHiNOvKbHsl+G18 FdDUlvUaQ8FG0OzGwPvsGCinBplJH4Y8w7wxo/PxGRHoUh/5CoGUYeWm8mfCTNTlvYRibDwQJ0bl HRvbtR404td8O8S7ELZeoJFRar9oNvvwLzXznvW004BCOdHNDQ/P46vzOiLdQ+98DbRmS3zj3YkZ BQ3HDfgkmG588zLUeUG4+sWS1SOkysSMmrrcS/VZNSmnZT0RKjD+RD80Y43CvVLQkNd5GQ13RKmm L04xcV6gWszcb7vecQIINLw2+sFQYIG+onSW0HmRYj0oULXPvZq1ib/lUYcbaLR6umBfBty726sa JsN/PUvvYyFxwIJzAp8YJ2THUnlZ1gwsi2kCdsdUBBxpJ8+L3XsFXS60AKKkzMZPUs5VYYkCvyy1 bq6+ipWK0A+Qh/Y79IMu1tNaAlDGBWn0W8r9+CiQY61xDY5aU7abtQZlnzPaO3Expc9o4oWTUtUU kJg8CV8Qt3D12tvgpfLNkBhMfjiXpv3WZo//M4hv5xGWM9Hp5K0ZlqANL46+shOzu2rsPF/TDerF lyy6xxWyQecUsnWVbJiPX+P4QBOoKvbxENsCvkqg2p271svJfcI3QUNUvwzC9Na6BPC/fFlY5pZ6 aKuP//15j+HVVcQDgifQHQNcvH2NQmcelHZgpWbShQ/rlYOVKIY2EktakVUW17GjF6Dk1goERAsG KarqKAVXKZRrG66fEZv7i59rgwgwWxiT7nXwyyTazuov2fh5crXd7FkDNy4cHIIinsJ9NMm7B4N5 hOgOwkZDZ+Yfrp6FTez57y0OUL3cbWCilka9KfMv/Yw1WP+z2RIiU/XdG3OHIuRdCYFCj5UuGmtr WXzGlh6WPRL2atSO5eNEg4myxT0Ukxc3hM8/p3/vYoT6oj+8i1hvt57KGUEZUP+sTg/PBXwNMEkG KhF/8vMAxUt6uQXWSnHJLmSh5PEJcoJdUaPbPcRzp1tYN0My5Xm5GAeSBc8S38I+xCIB4lkabeGN nKzXGhR8GHVXnPsyelfpKoY9UuH18qx0rPhpxn1h41d9p4pnzgYOFRt1AI9Ug+MwOWs0k4bNvvqb KPNxHHbcPg2MIo2Z+fKnZ0T0jjPjJr0JGdKQdAG3yAeZjeTV8/Sxu+gTBVPVPo4tbyzSJzv1cDPz 9D1MgddY43RSG5ILXkWxICIoLi3FI0g3c4C1kcyTXg++Fzw9IzjFUi2Pi4T7FEh9eOkf6/IG1gtG i0Y4S8mDg4zhAw1A1fKz1ErLnoVYei5ioR3vlRULgdTYS5W+aawgMu7GVuAn8pBZl7DcqFILgA7R OH6my8JFSrQHK/uXTNVRS9eIv3R998TegT+i9vWiRV2YBzpLubK+ozXoSRjlEzChReX+PNc+Z07B lVClRThbRPoIK41MnMcr7YhzhAdl/5fxfYqHxi3i3KAHeDpK6GAdzDoUDUQfiW0xvSWw4GrcK9tZ f+RwAvmIoNPNVhVMmo9uUTtFy+u5F9yiK4NzM+MFgU4/7oInvMgzezHevvRaf1xgmE6JrVhYcyS4 YJ1PZK3hgX1H0/EdCGiY4VOyiDLwP2IM+d5W4W7+dPljlByWOAH+13AtiDPXN8PS2GYeLaQd75Xl hHlD4X9zh9tN2Zb3Govg3dMGClJzPI5pr6B/jQl20KIJvGhuq5Fu5prxflJzdL3v7SpGu7LehQYK glkOQ6vSXKp0cucJ9zPwbx8NwECTBADg3/qiEXfDq4Nx123P0CUXKUvEJiA3pdzwaXmfh80zOJ0p Ep92xZLN8CUcRp4bAWZS4emrTdab+Uvnn6TfAWY65Bbaravr2o7x0I+g/obG5K+a6SxRYN8oh9E2 5kus3/Wp8rd0+FiBAVxO1gEpylR8myGVmXvgvxN48OuETGJYnLBGenE9qZ38Q+m2XwlLB9QbMZPY h7n+jold6d4AlXvmQUki0qqnsrG9tJweSGGHlUY9qC/pjMn3gImQUTHa68ijND3GYbiTHJdtVODb OIqVwXONu8xOk0MUO8KBrxVCF+giNDB0yDzSTgRcdpjI0DTmOyuafcO+mFfRG5WTfLN2n8PD+XyR ktNBpQFh3UBUuv7+HWB4NyJf8rGuOXB74KW+98wuNoUxs+6FnpD8HPtM4kfaw8248AbI6RTOv11g doxKBEuYusWnqDJVo/jyEaMBV08GGNfbPRIH8JtlPkqaDedMYoEBS3CGl6zWn1ZPpr9bXLUkpb1H sfpO4DseWVIsI1e947qvrXPQ0K2DpxyJTSSVMfNBpYqqaCqAAgHV0NKkuMwA1+8f3IXMIum1VfcD pgCmBV56wi6F5Q1i5vzBkvLs0Pv/9C+oQbHMyKTntys8C9AUSDt0fnILeqrr93mNgAugZ0gUVPoy zL1qH1h0c2UWActDLGwKkvMf6QvaDF5CfdChbNwjcpT7nLe/NVUWgDh17tsmcoiboM/PR79cu1L/ 9y1fHKHZxrB7dnWm/w0fpdf0geFMQwEUh4dR4iAWoeEVMiS18tAmqFvM8T0zUHR1RVxgs5iI8wXy DxAQz9lLSNw5SknPMN+OO1FF0jOp2kbcrFLW4IJw3orDItBjDcwvy1NEf5ztRrN2ggjZq+VDJJfN C0Z0W6IG+n9Ckfr972px0cUxYbp0t2lSyDSbHJ14B/fAzSOdIRDE4gvV0AqKCQktzzoCsPAKECDp yUUs02j2SkZEPzGANNPvpsktMfnCDLQfhCTpbtvOnQ1liWLrTakz9KonqLrNZBikAJFST3uw8mo9 NOy+FK7PosFSx6FUhfxkzi5Bve0hruSsoAzARAZ9PJydLwzm6H8LCWPYmSFkSNgGS1ZLyPT6BHhO gkOjRsnFjOR2dzRunpG1ZEVvP02k7DKfbZ+iGfpNwnG4B6Mzn9ut49JJo+8lVSFJwaMwGnOcvY+i yXk3YsOKEuqQVNVjkiULjPRtOelXGbTgyN9oPdBSYzzqoHlmJt7Sw31B+515Sr+qQjGVeQGkCCag 8tMnJAGXutH8QGbXCiFr9cwEM5i329bCzDoE/8A5znM0PEzG7q+JHWQNpaVPXjPf/oX7yYxrHdlv IQI7shvZ3dPZXcCwCWZyvDUafmwx73ic4HFqNm9JXMd788jInEpdjsEktvTNHU6WXskV9Ti+TMeW VAbqMDKTGVDKdW/f+14hgyl9py2OWlPvqZP1PMpnx2I92H5NRopAj3Xx7g5Lj6OjRWN73Y0BNIpk ri3e8p5ITexWyowsBNF2sddXnzvlcLBWPIVhtzTxYnksXP0bHNvfeCHya9gYyW0ypeqMOcmqHBaG wrR9LhDX5usKzHK917U5iJLwzywYiYpj9v5vxGNNbLuDGG0/BpglCQ/Bb/7rdbKXlCjcSkd9EL1Y sWzmanukEwzRcAam0CBGzgE6qDpXNS4QSbLOohrplwjl6GySm56nnZHPqAvk0P4guzuK9Hj3yNje IzVRs3oTnuqTSoGRnHK6pKJsAVKn2iXBiyjtQp37UY+FN8qX9B/UYrqtjcPAa83vG/7mgVh10IYT Z8tzLt4ckS6Z2vHVSeap2WSj58021llzLztqsIUHPGtYHBonROo2xlHQ6vRXFigeX0XWYWPCVP3L V33cbSY6MBFX/ZXZPsV+WQnYCFCAaDfVl8m4dbURWqpTSjsuhIpmhUDuclgNgvNvF2w/4huQX9PF 7PlvIflx9SZQAcKPihJsrvz5nFZq5+e9EHL1dPwp9r9/LuVkKE/5jP8KxLSTyLNt9IJ2ONymJSft j5pbhR/pU0xXhjeiRa4xtZ6nA6tarL7bVDVeaaNpXKjQ6WC9Hg+ROBxTTChCNdusRx1pVlyJmlpY Z1zKeEVvNK+grIilLsDlMkQ0qdyE7M7kuETCPKZh6etvJ59Pk3brs5pzb0XG4Vpcs4Rd1Ben//gc SzAAzZ42HEi4WEqvQgaiaAKLUDpRoh64es1vZgOQ49KFxd7F9C8Vt6qv6O+htXA7WpAqNUudYBnB loqhgMIG7K6W4FfoQNC8gAWFWHxI/91zTsMBj312TzWhxiZ0GNfZZ9IeHqgoLm/OYf24GnpGRVar SJLxhyP/lR7k73QObXY/Rar1jcMBRSXmZDrdJWlmBfctGOAOb3vMTNIO78NVhetufEGiv1vgChpn UURR8R9DSy2BNG/Zov5/oYK2CFqhRxZ8Lkoz3gWlb1ZWDe2RHvuEX3B2jKRjMZ4Um4YFd+qypzKg kXu0k4Zjyhj5iI5Ut0VWjpzSSb144K97VQT5UXUs0Ov6ReZbT/03DI21zSGskb0rTlDel2tQXOzB s2WGhToK0dbgyIbxPl5KQsixKxhLZI1zTPrh4kkAE7eDtOfquwrv9ZpY7PR1hJfHE631A0nlGhEq YMtlh9oI6vxMWMvbsQc1q0dQdyTeo3QinSNr5NZnCDej13rodTLj6vfkuFhG1g5NkQ63mTOLDA9K zdq6UjDN5cnv0Mlak1Bl1Fbg3DWWhN/HbL+5LONsV/nFoakXNk1qiti8+iaJ1lr3RIZwntlXLPSF X9QxPkMdMt9Ki71PR09ebDb90GAAM0YhqzSj94SrzpQPjdTfYxlpVx8JidJduk5lFCa/U3uZ0mlH X9pstQ9GDGdrbHzhdNMJrutFtpl3YfaMcwKpzpAF7+xW7gmQED2Cc72KF0tWLSUPR8TkeM85CMIp CF47GrZNblfdCNLjeo3s5UieLrR318LP0qxYXxujdLYsQcEm3/vbxdEZ8MUhLKpDjxw4NV3nqd69 QuEI6GMNZNfdHqWthONE3sUrxTxVjvlVQokBdBuWMQZ9uPnhX4lRrNF1ZzbiPml/lvzwZ/tsUYDP Au/TipIUdjUKOAN5AVAoaT/oB6OSBG5USfka/YalmwZTDtWRV6SWAoJ6gCVDF39dWBlKiwwRGqev eTg4d3fZWf2ltm1LSHkXaBPYexN7eNuWwBeJkp8IQvjQP1VwU5qRc192jAr5zALMwleyKt+HxUd4 yNpRLRBBhZn5O5cFZEQxjMDbRhOsHz9xV9GtkDS+sYzYU1ZiNJeUXZjhnp3np8Dge2Z6FTWO+GNx Y9RBa560uCX/ekoGwolW9VFMblCPVgcBNU7nGsGOzpS7Sv62apXtSEAl/qrHnb1k0YD6l4LcGlr8 EOE1mmiXB69gtSEv5rjmrxuI9FaE5FjI+2t1kS+4+8FQqqUIUcrRPALBweeeUcuktALWWTj+WOud QCDZwqOEmiCnAaVyqdkHNETUAbusz48ptTiLMwWBSKV6eTSg3kOqKsb6JAmxV7T30qHlzFfRMw0l RUnmKvgMjAQPdrzNsAgN1QZ3eLg4ASn45moAcLHE2oXkALK9ARaNVrDxf/IckM9slHmVpoxeCWkQ eow7E0R4hBsgENmQ7VGF+ntfS1pKrMQYxp5p16FMRWUReEB/roIYNty7uvUUj+qrJX7vFGrsrZwJ EXt+mNcAmDhVDGKE1FjW7Vri/ILjV8vbh7iGp5L1Z5oPKPjfIL+V2Zl+nteQDzArNmP2/Ha5Hx3U GjPv0wJBgEAThPZZq28EXVKmIy0+doHUlBvvmkTnklj4MllTSUMI5H1ybg/5EUmZAMOUa/H5g0ma aNzlAZ9xt+6tbF98VPNMW+yMevJieijxJtXLp3u6COhpHGkt3ES86TvEjHWBsKs68mwGbanoqjXZ jykCz2+utKzKVKy0L+sc927v4NquUooeydsoBuR0izvQWVFjCSxwhRmgzPKwOZ9G6vL2PAGoPgWz 4UhY1K3Tz8IYzRZKP7PgyFqyHAmusAiSzD1UtNZy8+sDW8cD/odShHbTpHW1fGq7LSpF7Idd1ff/ ISJNuOHY5DmI8dMrTIG6oiohhFCwP4prHqRyt/stFihQQGyXWskO7TrIjFvs3EmB4yGr6tTX1KJz L85bs9cySE5tU4yQdYtKb1EZj07gyYJoVkvCkD9dYu9hLCU31jzD9pRIq0Glm9VML+5QJCsxfDKT w1nV8fZbM++Tf1aotlilJm+bGwl46fbbuHqgTyRkgGSzZ3wf8MxhIVZ1MAO3ZgTg6mqigOKN+FjX BWLATfKoocw8D3oy0bS0vpuDrJfN/CS6YawMw9S9hbjluJHLUo2RGXuVTrZ6Yc645KhOsFG3q9g/ 99EBuT/oS259ZSFJ0Z75TlaQEKcm//KtK+N6w+GRJaXoY92mpRK+t6d6TOMxYcNh0nSOo91eWDWj 9NGP7+pPqunCpC7XGl/JqUQ0iM0kYW/sLvIs1G/t8tY3HiAOQtGWigjGHVtdSzq87ZE0dYhOIBPq IE80ud57V64K5CQz/Vt8Ekl/VRfMLhV/pKXeKdMZtTQZn+sF5VLUNWXEVzof1xkTp2rD2TRy6Ux9 B7gpOKMBm+y1YGAsTtw8OktPcDq6+FbaTikX59GXt9QLQfqDbiw07DAN71H6TylMJBZb0IgY8gO2 Z9NEG0CqWxal3OG2qPz20GqohG/CLjYGYnQnWgF4PDDKSwpfPIyFzpl56eEHL9mPL7yTI40PPSi/ LgOvnk2lI7iEYYp6j1dgw069yMaacIsmzTS5AO83YZk3XohYxVfkCnALoA0s0XHffy5H3hA29FY1 8OVitSo7XfF509WSjS8ueuAbb5nLswWsxzxWn1K1dJW8NGFx03pZhfc/DiqKVV1w2MIBC3Q5bGcZ kWuOUhUu4ks4n4R00ptOliIhUK/3hbdEf5xpGxmkiKpknt7C1jEeTuoORfc5SffFF925BYj8gQ3m Stqb4DMkSmK0r3RcUQiVj4tnmnKdce++99ZH1sKO3kBerePdA9knNKhcUlUU5N+RKgkILPaxraOv IomHcGUteP7qZOsuTHaAuou3POgip4CsPyfG2ddygR/5pBh29em6s/htAlKjas5nsNuIBzIsARrr W85IL25tke9N5Sszp5kxqAwsL/8rs0OT3uoh61t74YHzp3CW+4woFWQq5kubwuaCX/Hneup/Hq2X 0tZJOsTn2ePuerQ3yGw/6nUmtg6tY3bZWd2JshLhx6WeWADd4nVOI/pFJy9YfG/Vilqkogg/fngA 1Ow990t9m2b9rQ7MurqdhF1sWVpmgCb0hcEB+y/z0fCpPnElO/qMIGguC9PkVHwKOVxq+oB9wuv4 K3BAXnhFhWtzsbvfLiQ8n98fZoO6kk5Uq00ebgkNeNC+ZyPFPa/JReQhIHQMtEbTpS+Tb2a2DtoA CguTU7USKXCJDXIOB8JJWRWRHtO4kv42+SPQJWB534oWB+3qNNH1ehSv+36L6LMZab3VmZiPM9ve lPzx/F7KzYm/OlDF23GvAc7WFxpoBDLE9rrpRqX7HykEEBtg40Eeixcy79Y1gPRRKZDhMElAtso0 IgDUBid2f0hxNSdBcA0l8jhzBMH8sjYTboSdEKzQocCSKyJainZQvU3/9JVdy1Ul6btPSRd0hude CPyt9rRO7NQB5Hw2mXMgntiavy6xNVMEUZwHlP/CE40VfFuOW4P4euX/yWgR9trRrVv/TaVBgruB o/QkbZqUa3+e36xddtHCF17aNO66UO4jx77Ssj9gaDjfYXbhQhSp9F6rdGHQ7cPAAXE5aKqMB2ZU B07eb97bxbCvlfzw3boaycvPAYSyqQEcarw+7CKZC/hWRT5H1peze/taHUUdLymwVmeO3C9UIN1f sxtP8zWAmhFAjJOUGcYufkd81JIR6pdOKnSxONi0Jn45WulgqhNwEs/Lu4C7R/N47Dfv5Ej9MGBf hNYGAZ38N6zsncpx08NMTlI8jiN/feAcB/escqmyHGGKOJ5TeOdVL0C+QnkvHvP3T6UM/eKFoy4V re/Y0g2WLTq+d7TJ3tvpAsQ0r1BfAPhxXcBq2ro1RUxIM6qWj0Cy6YON+onGqHuhXmORn9Jkg75g sxdnilTZV46gVQKmPpm4yYwLQsg5A/MZ6JtHy26UlbB3BPSrZ2CMntZxfXECgp8VXaqaom+naUpP 2ICG+jiTusxt10FqPWv4PTlIe4k0WNS6aEk8FkXW4iGYdYEly/aOi/L0+yNjkFdPg60boaIZsCsp ftxYzzVbaBbX/wJatD8wYLWJCrNRbnngXm6PmA0a56w96DJs5g7L7fwWnKL3dxvoaUkyHDCLzYNg 2Vr0ijyHIVYLdbVsbLCZAbx2kkkr3DQ9CezdFVqnmhaIZHO0YVyNVsJWKgY6DE60TWr0zxx2U/E0 LDwzQB6+9ZehZ6LSQBon0wflJLQJxvAp0XJe8EtwIqXMGie+aJu6pChpcliHpKuLmZRsby0E9Co8 nDVzpNaeSL6pNlQrNBHUJv/2/IdcB3IwCWriLXpg8aaERug1a8UgiZXcbhSKWL6HAYTERE7C/342 20sgX7trFST6Khpyn+9YpsD4mUaKZP9bMYvwn+Vc8xJ/FYWkEVh6YlNZf7wiEG2m3EN9PtS1MFMa hG/eAcclxUFyLTKdEdfVOtFBjPbpXfIQfSgIyyerwJqTEEPvccGTNiQJNgkGDqyv9ozQ05OSkJ8A EcZUSdWYlt3eqC/CntG7GEwkRSm/6zHwkMaRskAh9++A/PM9L8CxZSdHXcrn3PRY/BiLXXkA3FOR Or+cYDj2AdGji3oHg2Ctaq9kexvrgSG200G8QTlMmC+jz3YMuZi9i0Ic5jSHApSrakGjaYY+PytS 8EcAQUg5Uqc2hvtph3mAWbOfxQ2/Q6qZlVDF68/Xd/h155nZXh8VEwBSUBP2Ar7Y3q72gn3iQzq7 fY6ibkkltKRGHLCHf9nmu90RG7hKVkcYaVrlHRpIJ7DZcKeU7C5XPiYgQ81wnNR2BouVTR6xZpR8 Y4KmBBKAv9jeeBn/8fCia68aEs4a5fIxQ1+mHZu6HSFGKiGijP5Thve03y1HH1KTbDEwgEln7Pfj BBii+e4G27phHGXEilavUJ6YXHguhc1188y3Esj+KWat29PGqrenvasWV3qIYProiShTNE/fn5Vq VpNUSHiB/BScs43ZD3+uqpRiR3lLhVXs51znZWzxr+QV/9kboOeVGRZZYZgsUJ0xnmq3YL5u969U IbleuqXqglSFEyLNwsa1NcpEYyyJkcdpq2aNBLvYH/4O+XBAvqK3uE6kocIS0WRcSEkiC2BaSiyQ urqUXRVMqR1AZiiNuAF3mROLCXZLKZAkLoNnqloZxN2+UeJZjdbT96Y+6R7UyvptLNi2U4ZlHe12 ozKsH0+TJFA+XI1Ry68OJWcgQOLlb+ZcrX0DYyaR9mIJ+0kxXeCTV8/AdVCZU2Yj1CzyAeZ3Ornx DemZx4eHBajpcR2a52uEupo+0OYlCgkdsXSMEXLmdZiAj+PjmUQEJiL1XGD7veCaKKMJ7eBNoCSL 1j7bVdYToOShvA+NWGOkqPQjguYe4vN5rQfbaBpoXZ2A5nhKwVoftlU3MLBN2wzInlbrlUAB1fjT Q8c5lUA9MRghb0BLVwtSnkdazD6azEfUgslL/cmXptGYpTTW20pv2wKDCsdN6SLAGAzCLvZSHKaM QmFWp/GS+O6UpwFDrtXxEZbmZE32iLc0+gp7W6wTnQ5vq/7I/HmmrcSVJc7mVa43GN7OuujmY1Ym TziG9Dut8KoBQjuQ/UCJIJDlxXj95pRwsyMi1H5zBZmlhVsrH/2+H8fAJQhn9HFX/luw1HEQSIR0 J4eGWKAF81jxPeK6m3Xhd+Ce3iBPrSwKbB/vR0EQfzK8ZwvC+CRLjAwIZ7UDdCAy1S1L9nxwQOY6 IKMGvaUXHB3QF8Fm4JEtFO/EGXDwiQdy1Um0bcxUYLNKy5PBD8f8XLh54/7AULmI7NhUAV+5A+Mg alSMgMHXGIEL0jY/bAkHsyCZdFIOk5IedyKdWWHOUey2U8YXcvqUq7zpRrUiuA10G6JSKrXLBNTV c1lX7x9J6KaJTMPqOUte5gOCn5olcCYYvjT4Xpya2v9YDUAo6/WB/d8Dtw5sjdFyNOJDnw1U8ulU BSXdyJ34xe7aMSnRO4GKWMUArN9h1B1Mxpco7f6v9CGsUT3IFAIdMX4+cC0r5ToRtdqb9MGrOCvX 5tImBGkkYKZfeFxaoqrsR283cuJkeMZy4LwDoYKnEZCOPYYkjp1ppng7Ep5V6yYTcG1DE17qd1tU 4iHZlCRPHZyOkKofNcWapFUetGKmUBTudevUfk/oQLp04/0Q9pk9fFfDCUIbaGMDKVcZUSLQWPlD KUMlq6K8cuqo1+gnZQ4nUxuRHHPT9kQwPgneWh3elgUPb5/2AZf+N9QCfacs2ZGQLT4YKDN0S1ce 3/y8ImR3sM3Fr71GiuBtKZvSTQNgsXKnDRK/kuZIThJYl5MgYB3xo5Dn1GC2q4szxadCtRTEENtl ZmbsyT3ILvG20UmfjYmj7TpYPHyl36c3L46csrBUE7TieZzWCeuZ3339eIm7xJU1xG9v1jf8aGFh uzm/q1czEkkYEYET7WwZg3zjhCCWgL8t9D0sg8XDHAuWOxr70SsFT7FRZ0VlqqWdMkhwJ/GSR4p4 40Pe6Xh5YAstk3HbsqQ49NYaOa32yx/4wb66t/MvGi222RjcuYEjw6jlINDzRJuHlCyDSfrkQIK+ qQffT0C8ECpmqVznCoyZiRWzqbCVyklWhB9StLXGoG4Jnf52DI+bsLQe3D+rJ9cwWEDjmllAyqAE 6lRASFrKlwlwuIy0FPlyqVuBQLXM0f800pOkR6HknHA/h2QdxAc8rpxSVkGiUtielLvcQh9Z+N3b Txt3d4BAhUMuhNtTb93KPv24GqStQgD7QYq6FC+eQT5JBRr3Wkhw1aBd/QLqLT/+acxsx1gH14yn 4tUukveprKtDT7hPl3N2qrH3kTPB62Bg/qMsrSYkF3okjMvPAJm3pXlLOrVKV3w/EtAW4dJ7820v gw5hexnjsEtR5bCDkfePGojZaGNCar9xFlCc0icCEkldxVFdW1dXWqBEHU5a9llyHaiqepAgpwI+ vYo0vf5tEFpX7HpVSiT+VVvnkcc78Bipf93j2kAJXfdjn/UnEOlMuYlieEgaXrXbrOfGKwvMcCVm I5vjMKN9Xp/hOWNcIAu6dLMWmVDWIvLPF4+aIj0MdtW7Jq/VQG4+rIf1RxpLUkA0uJT/aOk2I8DW Sez6nPF5VEagcF6g/nNuE7l77ig9zGAPvioDCyO+QrIL2Qa93/ub3ElAGiDLjig9oGcx/RcCheSL RV2gF36EVffd9vu5QmYlgyE4hANfMFYOhOXvOtnRC7NAOhQdTeAqsR8KWpQVKMCNbG2fVQDzWkQ9 JQ826rinC4lrbtF/ddWEOsw3gFzlzH8RuktunJbbMu3k9UvdLM4ke5SnXMAZz61JPfSorri9+Gp4 ZG4S5hKjFx03cFPwk2Hz+1SUZrCmMPmklGNowFCB0fIvQUXKwTNkyJrmBioeKXECcIc4CvDc/b82 jHOdFH5VkM4IGNGcDFpmV31UMss76ZGfHqtxKoduIWFPHFX4XQ8GpBtXFDXHR3g4Kgm18KeS+qfs 64gT8LTlzhVJ8yJ4zwbC04uqbUzx2+1W9jOF0TCiQKZdFTFwGEPSO1rQ3e15wKppX7nAN32FcRLC 1tGpUYVmxx4BGQjbg45A0n/D6fwLAhFIilWleuEu3Ak/GI07XzKYfVwdeN3VJfU5xFdx68NIrWno 0ZQ8N+b+7NhPzK5pw67eoEXEGdlQybLyqgwX+XXOLlWz0zxXjiP6WuHJtHh4pgyY8rfmVr6ACfYQ zOzUCmF7mw4klj0bcE8zqdurWeKi+CN6/LzAFYspXSezjzPKhR4vVRS/d1pJh6o0le0+Ds7sBHQz jgEJFebeDN/wsX8wBqsRO+4wYPjJLAXZQLkbpQhRJkRd3D9AwBL7qvPsezvtnwRwLI/EK4f0u/5p e3rpRE90sDSOIdka86XJjd/MrvDN0/dtT5/j1uDqoH4cMo9OWjEdaxLU4IKFfMhqoU3PIk1me10J aSiXkRjpsIrzFCa8+SeQkjta3dod4aGzW6rHRtnUgs6pYY1/XHXH7tEuCsmG6V8Jli4iq/qbPH9S ng0gB2tmkC3z8FsjtbrvArUbcy9BAZ/IVhGR3+XbOZPDCRUusENYz/x+HAl760VKixNqL3LWcJkd tBTbZuPhLuA5Q7mIldqMwmy07iU66o72pAUBmti0MUs55U/DGtncMmlMVagF6hMDjwi8savgQBYf WNtupsTznSVDoBDbUkp85tAgdMXrP7tEhTomq8/cGg76390nFRkLNqfV4xOZ5f2FayVT0qA80KNt GIBAw6vdz/mdLDmUEVOMAn+pgTIHU5CzorhXqJaVhwwbw8/S9mQ0g+pxdLM27GoTn8Ncvgto3lQo F4mSZ8tRUAjd3rltaR1JbeNcGE1CpVuQFdodWkwzi0iEyWn4fP7WvGn3F0u32pnlpua7QKRtYub1 4Ondh7POlbtVpbATMImTrrBj/UmmeriuSuLsYq9nqD3rHmQNqbo+42TB7ApdUrwJaQrp4oKt99ev zuI/u24DpP2jNwROnpW5hW1V+lpUd1LaKumUK+ELOs8CWVUtGPRL63YNhjknBfhUdEjPpY93iDK/ pdOKvK2wv5hOhut6puRbQ64pWUtdhm23el2w6mAvvPQy+QQl37dFTrGrwpFgLJXYLGzKMLDAKylh +6/PhDMjYvxcgT3jRS3byDBqVKR7B1iLyRbn7Ukn3jxbZOepQG13CiyeD+JgJhFbRu9Ld8zwXNYb aE2r31ESQwwOFv/ta2w9HpTQDzEh8W4juVHCTQzUtN3Lax/BD5RQUcL3PBeeVdsBnFQ34VgU6nXB HLXELJvHTATDL52fBvwxEDRDuP0EDpz6V0PuYFPKtrChr+YmjK4R0iAlw/6f3334jPWbZ/GkeQGL 9M4U2ovFNrUYeuCPqPbg9VgDUijTXjazkPNusBpkl3HZvboqhyDzCV76ccU64EpevVi2P7PmuOMM dNpH+zDGQGhGjJHBz3WYG9H/aLW0Nm2s4snCu9iq/xQCtyEIj+hPWzuJzfQ3z4Xsvc2z5R9VHpUi GCaGgLeporkhKacLOUFpquPRZF33zaTNjzEqtYa12hYBVjt6OCF6OdmJPlLeoDCowyvA6cAAIcPA kh1kol9L1vm6lK/WYFwHp+4fz9UUlzu4oatggkChQmcdoNhlxmJ9O9md0/5Merwm1UEj4FCfM2A9 v5hv6jWucNsjjzPLDyOtml4clpqqiZzD0KPpOC9XJ3Pd25MLIyiZsdc8JXiSMgzCIUSVPpxVJ19s oamwtpYHPwiqxItlVLFYjQt7lxL93NdrQEQKUyvXmhxMPBUuadER8AElxDXYAyFJqZ33YjxCF4X2 JSoSbV0vxpyjpjDe/AS2q8+4gSFtmnwKoO6mAES+Les02cTmiDWlAQsk0du2P18EKsUImetqXmEO YKqs06WNpRSx30rz9y6mp6lh6/RcNwpml06uJ0DZ0ePkujPAIyHpvz+8aqenQoS1jaxd9uSlIVm0 fQdC9kDoczGkOA/hlsjEvRpWQSkK1rOSYhSIooLHuPBl7gsAaHRcM7mdES5iGiEIgp2R9ve1yRrn G2XKeGgZ0JeIcoPF0ZCOJnbkC7SRejhcmI7rBoJc8oWEJYNensEO8PHfcLV0i593e88Vx4n6MUHx X7RRs9XHAsLv1HJ2sPkKq0+ibFfscf22swM6wxDQhwDV4iAqyfNHN1C+RL6bFbeBVrhn1QMCylsX xhTyk8moUC33pvyc1Dmj3ZUVKcH+YICnYFudhe9Xnl34OwljePQ2div3fCvAuWRjpLOtUl7oLuF9 1ldb0GfHJycPRkynJx7er/pMMJNkV4m9ELCfDx5IRUcQHmhxWm1ln/dZBTfPkt8ANAvTckKkKvAt /mqqgO3MUAekYA0ksYDOdJsODONbwloNwJstSL4JFKUG0B/I4aA4930fYYkuaeztCTiCUUO8Yz1s EON6JthF6Cq7o8gFcvWw0Wv4/3FL9Lv0auhcVqj/v9ofvkVoFV9LbsIlVfc76fUHkOesqyBc7zR3 86xGn9Dxp/HjAdNNDPgZ2wisN00PIVYl56C1z3sGyytxy3mdnkLac6PkNKdTosnQsEs/vhs8FNCs 3fLHojE8X7mzUcR7ClL0U5cPIHxhaX3NpE+yptFPUspOjCIEK3qSJJs0YqIvsYWgIikFtdD1yPSS /VZA2L7E5cdXnuuldDxCtj+JDfNWBjIgj89LgzgMOEJ2l2XtP0i+HPXd5l543bepuBkbu8/fuhX6 WrJ7KJr0faUmduhLK93PoVLztW+OZnNI9NsSl44Hu3tN4kffLoWrRacoC+04slp9lSZTB0mBpxJF PRwFs6i6vvfzVuVi46bDvIFsRr+7g1X7ttJ4jx0JnYExO+utVwl8SEYyX8TAxkWdW9bdDRxEdQBT 4j3FhV3K+58KrMVPGZnJyCccaMMwaCjpi3eJ4gcRcACRZbh8RHs2AQ827Ji89MdiKaDebdNUHXfq nhqHVUd6PUHoGH0SEmynh16zE/UhVoM/2eQqhXGBmdCb5d/JU7FQjQE2ZoCdpD7fKNUDEhBnA0oR n2jGPJ226qivlJBsAz5HYpnwWT24Vz/mvZXB4YAhudAjjX7deoYwZHNzXWllsNfSugujDmn86WIi oOeKjgMK8qxUrFFPVQySNitocnIvxgqpCTu430vJdZr74QermlN9HITT++iOYh+c3d2qzoHV3tjU YTwQVL5ZIMkR2WjogtaMeOsP3okrjk//SxaLqbxK+faHWm2Vn5FG5KHRNcxHjWrQ6w2KsK1vL72l 3uwcQu58paKJfsRiMKKBctTv58ewAyQNKrKGJ0x7z4PHOnO0YZE5I3Zjua+SikXyXZkdWiVSCdOz 2fNZtIDuW0XKbnPaW0m7+5sqDMjFx5//umzWwrH+SDtrgKHd4peGGSo87mDN3fZPw6IWU0sk1Jk8 NWuzw8KQaHTQBFFnZdci6LWIZLzA++CWRx0V7GxdE+xk4fmWYSJ45baC76QpO1hjCBzwEGomzkFg m6AJdDetyg8qN91jWX6np6QlVtCru6obw9J0iV38ZPqFXVAOsKA+ry8oNl0pGjLH4Xg/6rqEomkR ksGKRuQHN0qmWOTQZtoQ1ZEy6vS5A8mTfdb1oyaDHDLTQyzXDOl8AnkFWDj2PNMt2CRd3o1lC7y3 TK0nJwrw+Q3KcXWdT7RPWfgDpPAj84sGpT50Uz7um6Vm57vDgsLizc+n9tDZ7ps5LJbWe1/iXlXH NivC9B73UinFBClDE6gta8P1+mZgzwPc3QXbitvuuQ91k2xJrS9W3BMRYW85JxDBevB15BGzfHxN GOgj9A4pa1No3LJSeDk3UPB2GPjJ47T3D83/OSe9yDJGgRRSCMoQ1FAr289BwxEYWjBTmLRWZUZH cvIy7SVHkF/8N2OBJs48bfZo2ANOjj9AL21amzWygzGg+W5QGWwUsUl5GDhNgIH2IUfxx6ShBk/C Q6cLyZ0rx2DESxBjfX7bkTnMQrL8YLSEh9KUpl0WiD2KD4xDZSRPJgS/4hYDv7Xh4q3L4/LW97bU nWoiG7+dkP/x8QVNgPXk2jmL5vPF1l8IqMs9ocmat9fT1iD3uDr9ZosP8NoD/O+4qOAQVF9Cu9OU KiPvuoE5rXVf+15MU2piCjpdgAz3QfwSDd+OM3MaRGmr50IPPzNK3oUEwFCITz/+lfIPUzczHXZ6 2uFgKJ9GgaOEvhZZRNtOqQMQQXXpethqc97PJgBcxsu5oTQKMFt+Kxy/mGE3622eIgfAfn2678cW hTaGWeMlqEtr0U+3B5cHhcjegV0qpZF5N+CEOOxV1iYu29I7NbEd6+bLrnvhizg/PxcIpELIEAfa z6vVJOs0hsrJoDadyF4aOCuatadZ8jKDKHklasPaHNLI2JjYFrftt3cCw2PVf5WRmIRx9VEGM4/H XnGziZkhrcFU8QDVL0KUKWGmrrU4vsaA4RcRyI0872DwYjN3b2Q4aODXjT/wFJnSseomHutw55nD caJeud/vIbjXeHZ1orzPUYP85nvJR05j1PvaM7SRmnkTArNjpxE58FiLjbZWLaU5bmifoO4V0ige o/v04QAFnthZ4DEBLLOdQKJhnz8DwIWnL2ankeb5quOABQ7DQQZGHTnk5OWX9m14YTlGk/Bbqv1t uTIjd+nTtZ/IeAUcl1Ipwil4P2kywQfK5XFLwXeMskcZjK1OgEYpsLOM1CD4c0SxWq+9cYmjAiGt +eoMTgYMByU4gjvFh45ecGDFcjK+pz/fltcb/p/ILwTElg80A9kwO8xrHwD1E01LoTgVs6EZMqJP N2UTRWSjSlujKLKdgNqTOVYYX2l3WV4IXJ+E80siRX/O01bi+G2+fMVoyaj+eVAQYeGrgdEQGDx1 BidZH6xQa+2ASTYEuMFk/YV9NVcShHVSK9bMXu09hSrQdg9n/I0srJ1W5mpqhjH21M4rI0idooXL KKiD60FJ0reVO9NTvLzDbDn44SDSmE3lNkxkSA/tRHslE0cs4ThsAUYMconbnnZTCJFb1Go4H//4 LNpgGoF2zOueWspTHJQ243VbiMumDBfrUJEQXO2igzYXjwkAAg8Ilp5HVVSiktObVljf01GRuPMM EXIW363pLtalWLCtlBkZ8kTBHICjCCNDJVMgQS47mDdHnBoIp5U1VwF0Irtbu/OukLNdjLlCSSYi X2nSBTxYi5JVw/ZR+moz1u4lyk1MFR6UkCTJhFpIZz4WdbQYj0lc+1RboGUxOk6hn36uwmCx5gce aB2LBDvpb+zQzfUvNrePMC+0Hohaz+y5K3UAr3qqW0/mbaRixf5z2mf27w+KX2/Xdn82MKTturee fnk1RFLphLluR4yV1UCjoJFvCoZyRCDgsF0vPHxjDSlVsKRCovuKdYOK/Qgzhbtr5I+vFSIRAZkc G43Z5MKRxoZspZ2GJT8CvlovW6AspqhaMND0ipCaE+dHY34JWE+Gq+f7IbjsypuU8ZflSxrkofPS x3t4FBtCpl7sqOUigG3FuD0OUb4lSescP+8Ih2b8fjTMkYOCT8hssEcodTzha6cq7I8RDRTMSYY7 URt2cN6qFgtftE4yRpq3ljNE+zMekaA9hjKmXXmPeW5XmFSzkBjYp0HtpkxPqtoLAd7Gd0SkhPaz DiCxt8eKUNOkzO8c8his1s5pkFbADPL+PyyssqksTrbGdjH58JthqTS/akZm9SI1uRX3nHIY0rTx MSSDrodZ0+8CjbMrG2SkSuTEF8haa2CSdOLH8WvjbQes9StMD2AGIPJ31EA4NHH+Hsc951P4U6wn 7uWMHALwK4Glmknbc1Sempc8Gqiaq5ymI1152A7kLfFTdnuaeQK5MpPsUzboMvbVzq+IjbM41D/C fDEYKZqYf9DWwuPgDXz/Krqn9d9J+w8Hz46g0aZXYkUDOD8nHJUODHJd4HHQ9OYy1jnzI52yXGxD 7QiFVcn1hmPibp5xeJb5wtwuwsIWmIQa/ilLCP97EaBz5u0ipvEHq39BYObpVJC1dQn5C9M0Au0L e0a9fER+kRDx13dyKSL45upbSFJ1ueB4cZV0ctRh4rJuUXKvRQn3i0KFHfQte40urxvcc0uTVvMU ib6utxJCyHLKiVOVtQHW307CxpMXEE+2If4W5Y9/XK81YIh4L82ViMahj8otDglvAUh/vPgAKwJy +8rac4ulYkNj/gDyKE6z+2ZuSQ8edwFGw4Iiu386nrs6UsOv98n3BiOzAkZq8wGpbTMJ9iRJAG9O p+5c8hVmBJqjMwtcgWNPYqE3goWfAX2sdeLeRTYMJRXaKzP2+95aEk971eK3N+8UYpmnb7vuiM9m XT1RqTSR0HhpOVLfItsv87RsexBxJzqyXC/fC6L/qw6Z0nC+DvTVXfvRoREgbNvdAdcBuNHgdgFu JUVLrpub3ZMTdTXrQUNZFwU/dW06kjK2+QfkTRq3ts9CkZj4lDJEb+LB2JkEe3C/faOTsLlZY3J2 zawVNMjQ3pgD647hr10jdCzyWzDAy1U7rAvdEa0HdbrP7F5ctsjG2aI44fnRP0fd0TTPvM1W0wRj 7PR/8MdgVXyW812usUCfi9cbqeBZB1Fi9u6JQpXBrPKeOnqBBowYip/i5hoYj5ajzv32Q5l61C9D /EGiWzI4/k9PaDnpru7GkLgxtCzamFTO75HZsF1kdeplsoX2FBxC2pdWWpHu5JlbiI5clNLQRedE jXHPExRoiKOKTdIsi7bh/bLjyPdcN6kKNgttx1RUauH4RXDMFrTu/wSIO8eBJJfMtTKwnA5a3MyQ XoS0SxONwLndrnWVF4qRHuEdr65/n53EuJ8GD8IGod4YpjSG95PrP61rmss7w9FEMq4d1N+P0PRX ke/PthtEwfe0XQdagpqQl4MM4u1Je2vEY0Iegw9DCDbSMC3VhnXIO/mAKQxpkVTN0U7fzQyyGWXV PpDHUhkorF4e0K+2zGL1L1ljHQAbnkPmtgJeo3jUty1Qut42Z1QGAcOldIXeTs+cVYEMbZjL9VSM tet/J7nXU6vHirjcHsjAKs/4WNGHYXi6oO+GFW5qwLq6d37U2ngMpx0hzd2nwtaWChRdEEnaBnLt 2SwkxzPT2vyQbghqOVJNP51D4fCwajwuYGFg+p/+VGaxoCeVl0ZOsdZLsMMYYO+23z/6LzXYQCGc rWjOsBNTVW+0NNwICjgDyahYJWRLuN0yk1/siiVASQXaoHuXGYIKtvbLgCUwYen84Jie+YIUfJHd bd9IU3De77RmLDis79MtDTk755UoPlch15IpIgTS9AIXgdNB5DF+PpHyQm55Ys+X5sqzJc277zyK wTe8BAs7ZgEM3UyiuOmfhDCW6JPuSPzgd6IBGHy59AH8Vivp3Q1bqNHU4hN2OSP+MeYQFNP5LW54 Xk8rIe0card6STtJww+uSW1gCscL+A1r9NgLYu9wsEM18OgLRRXMQi/CUy2Xe//U7/OjhmpBI5IV 0225VTbrAf/nyHRaQ7HXOkIsBRb3MPYgYDcbopawIx14BYAdgKTovBeP0Hlz3aDNsDDv69I8lz4T keS/xkp5gBhrS5iUbrnDLy3M5gi0qDgRwvOU/H+EI6IGBMIF7rWsiPp15kNwFhqNDirOjn9oFLl4 MQZS8F8EQWb4tCr02wX98ok76ruN2KOEIHKVd3XyVIsBg52tJY2HdYThdhN2TyYkMAFXBXWn8176 CtMLUxjldeYHGvGXkcC5QGWQGgCr2ED6y9/BYI27H0YBOFJjBINJtk2sPoO10xhJ2vasAzjk397+ og878EkLRbyvyf1x8a4XhcX6OQd2fbIZ09UBDLXe/DtLhwGT8LGGMKb+vFyPMu7Yd6to9ktfXvye aG9FOjT4vSk1F0/fndiYzkF8x2AVAMbpVM1WoVTvdYBynlmw0PeJt8xEYMaCLBX4StMKnPzQ0rsL ADO6ALosasG9sNGMlbFHV/xfpFz/t98pTWcGSebsYafHgm/3XsRVLnpzsrUHb1kg6BIzSV7wv+dF bAtt0YZuwfERak0TX313GPa6lSnW5dW+XLtLppkd4WGYXxz5g1lhUpwIm6mcMUxX5N/fwnrASNqZ /3Ik1tptJRVnRTTIDjW6enHAAeK2H6T/UNB1OIt5AWSCwPVqFKZI5u7n/c6Hiy4wMf9ApdODPji+ 99JoSVh7Pa/xDtcRdbXS8hxxQcsLpGyHUNEqoQLF+2b7a8jHdoIYs7oH1WnXruO1+hdA9b5vpm+S xfpnNB+SFT1+iN4K7t+ZXJz7MWtuFu/aovO9w0KsuBCqNOZOloximDDB0AWmZICPVCBAnrYQvVll MB2OKQ0BJHNSA5PyDyZEyfHbDDgQfDInd7bGhbrLWgEcX1gg/gZ0ToNsirSL4qw+/As4J+y3RKtW o67znXURempJZkOKhcSX/TUaD4DMkuyJ3OIzGI9uogp2gnSjqR1Bi4WUh5vfDJTy3mxYKyh2BHRq MQLg/7zrt4vz17T/NsnKq07TkAlp5xniSrQJaf9TlJ1mXAC72H0sUk7jU9ZyTn6GFA5H175QcVE0 zG3A4R4rtJZL9jwDrqZuF/EJwoGwyFTLs3kkdQJx5pxkhBIVdc0h3lkFfduvuxKr7dox8VAvxLiA 9PFz7Byopk23lbQx+bgGQf7H7PpdyTpP31NIKrBuWQvFYeVm5Ie+HuzaGQfzm4IKkC1ixZZs0ybk OiFIeCuXJn1XK3/RGDui+n7Klauvgk6rqs/d/zpGrf5fNGGxOW65yTnwh5X7JfoyGkg2L/A6N0Vj Psgv8YepPKr6n/UsbzBTDmMwOeVZs3w3Hb6mg/Ondobn0GXxt4bSS8d03LKA6WhE9KmDTd2ll13T Vg1+NqSKCN+/hhSjdgXlMipWXJ86tSJaTPipuasrnaVZ/g6UHRkgzSq1i9B3skfjhZ8zcz2NrMhj 30Ss224Tw+mLzFqLIuNNZOIc8kQ86/83jaad+Bk9bASag9UeoBHIxLGBoWO6nT5Cn4ruwu2ZD+a4 JL+YCJJnvGUWTFU3wqeqkibZSeJRIWf5rX/JiHiNKWMIkKEO/pkoUgMlrn9o9LLTcLzgXRCUvIGr 5UV6ulEHfJj2plr2IVJ5owU8DHB495T93RX0yl/cG1yS7QAVXvPL5KXjRkjyG5dOB69sw0lvGs6p 0ZxBvbpjCVJ+NywQR7VDHC8eObtlcG+Ak/VfOJ25xX7gW6bGm7dFLuBwwUUgRZGYfeTCvxkVfaMP lX1XFNnuvcu9j43+Ork8u1IYlWm7HDk8L6UFAujDAJXEtPf7WJbrBKnTy/Ab33Ff4VjpoMZKIfCo dUfQMWA2wU/MI//6kTazZkWBFLo8v5C2Hk+89986tUnCgbeVZYYa1++F4gdd/J6U3RHGkNcqApyg 86fqHoJALQaf3R3gjxRXfous/Fpq2GK1O82SwofaeKO2bibFApFdcOh5OgZlxqGeZO+KX4z6lAIJ vrjnQJWs+fDRCqPFs/wvMN49ZTg4dqi3TOa9kNZCx7Mf5W0xF8rDHvtkGtsdt0ajxU5ZebgquUnd Id9bcjznMJ5cLacIM2G/wysHgO2WbN4JvHTOMnY/eg5kjJs78nP/6PknAf4EW1svK30Uzo8Y4koB DqRfS72zJ3uvu/KVCXu+LQk1ZfyyYJpmgQXuSXdKyFhWXgSv5fImbWA7Q1Hzzv3WRdv9t2WC6h1L 1gvDKMHTBrD0zuQKXWFDPLdRcRcmNJW2/e2J7DRUkrddY2xtH6UCKHBZmk8lzWFnkW/A6YEq5Hxa lXX5hynntf24sN2EqmFNtlcmewsyAvJ3bwh4/WlViB1MREw80d6HEZuoTwUPrpzWHUrg5TmqFhmw sSaIQS9U05JQTwUfT/jqsr6/DzNLkKnzEVXOzcZsfHnOT/72rvHef2woWTb/XbBfWChmL8PpYnvO DZ4N5sVP/1mD9MoAlVS53NCDnOWxVRNC97EtMMgDHUGn7NjvuC2iwzppnKdxzeH3eSEldigdpRXc H/auHti3Ce0bEsZZe86N+4K+Ov727W7Zo3K7LgqcDlOWAij/zqlfc9kfWEfAzP2rAFLhBDuq9kED KWKqQI+UtAMm7MfoMICtbPGIPiszyFtnGO9Ist1YAun9675freK6WSr05VoqAEfyHmni+fXH+bNf mpq7Pk5d9IV5sbvaMGZGPkjymIdaPtpOruWvGMUIjs77p6w3sCaHUEyLtLtPLU607X/4qA8Sq3yD RF+IagGxxIJBBbGHkNsM2tQ1tS7MBzb0IWFY/r5APRO8zWibjUnnRRedi446tt7lGtVGYj8wTtS4 Ntxw8WGX2Z4i1ZHiR2cFEHiAfqjSAgPriE2Hvstyf3Bl1FH+DYf2bO46n1MFEpHhTOL2u7t8vYj6 BXT6K2bkpNHAZGDDP3AbBAB4xSE5yCmWCsLaf9k4uolCRXZffdNUXxBfT35x1G2sWhVOKcAA4ET8 L0IC6Ov3gCi9BWl0NJ7HCqcYjhkA4flDgp9sAgAny0gY4fvJTF86HxsCGXSGHHs/LxdAVl6Mmlp7 wlS3GCgFhN6CSb12ToQSd6ddx8GY6g2ayE0LDC2h7EMySpGi5Th2epy7JaJUqUG4+vvP8fhGzum3 fFbv9wEBrklNA7U5ZEdTyp+5Fp2TVNBzuqUgGu5688mJIcGH5nylKBktm4oWSi+P1ffsXt2xxKBn EDPjmPTFZ3/nJZ/4kqh1xxxdqE75vkXO9Rt5wwSox7BUg3SmW7XDiqKx/Gci56NLtqN8mFCQfUGe iOu9D2h6eLJ3kvor+74n+zZwMdAnlpr43u7ICLW69DE305/h42BZAKNFZ0Ce9xeG0fNls7+wZeK0 UeGonlocatGIAiprMOx6PAUGuPX/xfgXhtzJwx14uIf7ykiIg3QtNpJBxKy9lXmjhVAFz9kNl1eZ KhbTIcapR4TErc+EXtIN4DmRX5nizj55btbrH6qxxm3h1YD8NAVJo2owe373PjuvrBYBuAQh5EbC jsexuL2P7pRZvMAziyJ3ZWubkH06OdaWIxB/h0XpuBi/0iU4b+WOWtHllQ2kg1dFQhQdjofCGp41 25CNEOAKEQgdvn9z1QpdamGdCqMPFJPgfND+stpxRZ5qfUvDr1PYQDnQTQvW+eAWweKwjah2HuvS Hz3rwQ+cbKPK5eUkgYqFHPX0+Hfc92oLH/ZmPPF3GqSHIYlg9s5Dzdi3FAdsFebnWahQIa7Qkyo8 Q+OT4GKh9FB1zTzwV/DUISfoPWJP9WurFJ6hhbgycWiU+lYt+SwSxHi2YejrWzAybHoBIlGuhiZx IEB37xcyU+egLKTgFYLnaw6/QmsDM+4IxDit7ETiih9RKtFn0rkk6kABm1pPRnY+RJFmLL7Rq0Pd GXvB6CTxqoaMJpLP32hxw4G99i1x0XpsbSNRo02uN2nAt93LXsks6NA8QeRI3LWIG1Hy5iydLuOb 8QuelJ3ULTociOuKjDrtToEaRBfJaMOX28uBJ1qKcDZViaLrLt4DXb6oVf/eXN7W1LfVajRjskmZ J7BVOzTd7lKba/Qh7FwnBUah0yMGZ7LTrbzur5Ip/QJlhrR7PRutpFaqwewUF1fHd1F3cJ+rx6RL EP9FTENeJp12tJCJ1Gi2ZZsh2/x82YQk/7N9C8sHN/bZTTfAAdTWQq1i+3Nu+kVMoAuKPNy8WkTV peHr4WBgoDCGgZspovcTrxlbeBPRwe37Hf87+z/a2HZviHEDnyDcnfGi9woNXGec6EbQDxEOEL9i /ZzzNOv/yUw6L3WZbsIjKGBBdhkGWaK9AS6k9tYTDQw1ZshFXTg1Gr78HkDJuko2+y8e6zt1cRHv 4v5ZV+8J90vAggUZF8qhBNoVCWubwqFGUBWcSU8AWFdoSzKlaVu6khsnBtJgXMtGXLTFKusZE88/ MAlcHhhdCfsRZeZB9+6Xy7EDKBbuUpRpUZR9dQ7lvzQczoVPESIItyQ0ARlknFnhmEKFENenRvWe cIVEoly3R/wjsySVTjU6rME9k/Wh2ydlF3oXa+91A8ekFsARxGxEkvgaB8pLxSGhKCmt4cSnFL2Z RcptHqwZd+E87jNOqn4zNRcOWPXo+c/gJlVrk4MIyPG/YP4vaTCxsAUJFAoTKJkWSr13LlYDeqe2 2xqUmQ4sl3u0++ogKgutYmPlkhcGsKxAkc3ilM+rU3aIoCjTfgTgIt/8v/aITSwc5ckulKAkMTrp LZkfNTJ5m9dWFm7duMOeYSwv8sn9yqeoNBWSKvKSi/jX2voUIpweshb360hVVOhQge1VxoteYu0J MG+3ojP12wA/apPrYMKTjXaZNtedq/cWC5iVYksXhJyQo1DNfoawDUcHcCQWCePD8oC1INpYyjdk qeB8Sk5VFYTGejgixs2qyr9UtJ0ocGH8++MgHV9YS4r0/JQlZGAKu4uxz8HmX1u7+3NmhJtUGbsg J/o35Hh+kGVq/dw7CDi3Otw/dkzlgUv97ORjpYdvsJFteV5PK9wN4LfGun9enC4n69G/+o3MueLy n6asK3qm5aUL3qO399ENhpye4ZL8OnWtgWzJz9msebDx8pZzskEq4J7OqnWMJz2U2FhxicfL7RWZ FnXsK4SHAK35Rk98InvQZrAgg8/5J64wQPOOm8cDc5+NLYFQ7PNPGWxXCatSnzu0EV0AbPoaBaME z8dV9OWhJ7SsKzgxXBQqlM4qTWhiBvhnVP8XoENdxqLSpevGkQpMMDX/+RpABF8ToAFWYrqwLKlh sJ2jyg0BgJGumow8GaMAV5T9GPyoRn5xvPOA+OGFYwoZmb1aM0RXEGr97gqCplZtOdroHDql4Pr4 PzE2HIbkM7lYh0Utavf2a953kZZeeYd0MbFR3SEcR/tncp/PYL7as1o7oKQv1E9KiFSnHwYKpnJS 3VD/gWOpX4MXZjuIOY9NRNxkV/JFoRKoxoWMUbPJeuPvfERDTXzm5umcxDR3pNkkM0UYsfPZPTX9 1WqfSodB+J2R0SKKMydL+DU6j2nHEP6m+0NZoBKv7r6iC0Z5Gr0f0hkDvj/mUMIGQOUDbdQJBxJE XYt3oLrC+rCaTPF5WB0fZhDtc0vsBA8q90mxHpKkI9TQaiaVEdqDOP5MJRXDJVEu/o5nSDBubanO O2ljVoIkLvAOCM9MRkUcjhBBjDfUByo1gmHbnLo55gkRpzxUrPuClWV8hATobUZ01GxeRsHSQoKR 0YktiHDJi6nBYuqaPlUEx9+tl7iFoIbRB8pGQPqgZ7KPg0t8qNDjxB9vZeJ9ffX8IjLB+cL8o9sq 9hgsJ0ndoOVkC12PXEmj70kahYBqYpsixnXvX7wEv5PM9m60eS1QR+BVGFRKqPhaTH/p1ytTrThc pTYx1Sz2pSs9yjsRz6qx1M1LDV7IRPU9/xnZ6v97gKrDXDVrCwZO81zdsRbbYGiRwa+WubeR77rR HZ6XwnA57x2wscfKYZiBls9hzDZMT7tLr8e1h7oQys47IAG1K9Zu2HWydNgpd0r9IlbiRjFTGWRj 41hyte8/Cf+cL7nC+4Ke4j/JTa45YFOPJh0VIkS6K3VeaBWA9bZ4CcSmUB7iiM5S3GgEXDkPEHYd zp5yC0Bg3sPcP7mUfAnKvuzMZm0eLhjrb9n0EIbnhtsV1hWZCV7kyxiwcu0cWoJAKD1ECeNVUbMh D5A+c4ifFB/4rIWXrIjLAvtTQUWQOly9j/75hnNC3DSta+ECpBsjPYkXoDzdcYq4WkBTT2Cf+tiL KMuZKrOOhFTgNcV91Y0vQkSwpEWXE8eUMM9QT+MZurhwsCB8gCEmHPm3q+i5gRtfhsUxAgRd/LAd /KxXt0iniIt8jmuKQhc+ioXIR87utZqbVIeQme1EMipMHZdgvGwwcOQp0Fd/Q6gCj5nv0bKXfwYP kE1MfEHoQAprGuTsZHKFSGCnsPXbHpk01pcDUreGxXaNH19n8zrgI6jDisLNxKLtAFvb/NpCFims 19o52U0Nd+LYnLZ9TwTOPPRsqLbGIVMgwBX6G0gCuRRLIKAC1fq2porOiPmItcnfnUO6LuJMTxWy 2yFIE0As6zG7yvK/6whc0z09d1wBAMmWC4k9TlVXrVpCfOUHpdc6dn5u2A400zkYKuF/BCUm08y6 qO5Nz/Kq1VVxdfwiHASU6+whkPIfMqh3ups66PXmiD+p+Xe7j+uIMjketjxfuEy4rMiyHh2hzsW2 HLKrpvKra2SANtxEZ0Lo+bok1wkD02lseK21CBIdmbEVu3ejosgWMSjEjdnoPFeGcxSYIgfc7hvq 26R6A7D1WdmmrhZet9YBnAVjb9RoGfdkyHHymWG7chZvjT8HNeaQLkYBGVxjolgkqHaAP89YNN9q oKOmMszoMZIyMruooH3gL/ZwFM4GLHGtoSwJfPt2dbYjNeOrM8IVoXvjX9OfUSRT3Ss0GfneA9WU 8jEgBp0B30s8d7NgTMHozZjV/tf/xCIcBwehI4CH1joj1ll/Juoxuc5Ubf9z5DXhein0DQZzRf/m wuPGuFTla8ntiS6ZC3/4ujw45KTgka4Sk7ZRsl0auYEFLEdxQIkIDn2ZbQSAb0o32+NYV87ybvsT +TElf9nii+Jhh6AMi4KPtsbKzQ0Hp8TlUkQbJk80ehne0g1REZkPWlSspJpJPm0kU+sL2sZwBTR+ H7QIs6fCQFiPtYAgXP+ynwPNAG2gMk3O5hxrAvhl/3bInVqM3R3Yd+Q4Dkx9QkK8k/898486di3V JUR6y1BAztCuzGG3jePoG0mubreEq2iCTSqHFokiY0xOmZi8kqcLL077OC5ckeMKRPX9HqG3U5yQ OexnHyr0UULL1ZD/t6bm6Coe2zn+jMS2/KwV0uuq7gZD+GXWZ3Ck/yNjKtpl3StZrxQpbfjymSj4 qzT6QJ495olBITdunGisNXAttUZrXcfMjUpYkridfK1RM3iWdyGwQJr8snuTg1kAOlJlxMvGTrVI Bk+MoESyha2OU+XYjYbMoWZmikKTzxRZeoTIDaorY5Ghdn+/Iuxi68gg7IVQh2+cCWSOlobEeUwU wODpmshWyKIqbs06/vzINGprNtBQadrkf+Hti5DJRTXN7rI51tVHceHTG/shV6236V2pqCAbwwVE QgVDEdVsXTIjq4JLZzcpsGKPFfBm5V+D4AeMD2MIb87qYTP2poxN3t6YkIc5lI6zTBCTGARB7NGw CCbP6eVIG2Yc6JH/rUdQ5efBB8abedmuv8xvlIUhm8V1rHhZ0Qp1BwQfL4sItYZhuWLoQO+PPAuT lowDaaL0afLmDCvj0jkEI+w2+xgKxaNGYgyCd2MHCDP1lok8sJN2wYNS5oYMpteL9qR64y11vHvg yVyVpvykaDy1NKNq9+Gudp9X7qwl5r7OKp0aAfq+yO4mi8Im0sdeXoMT1oGLz0UTwq/NkVBgcWAT e804Xg3RkCmkqX79zW5yV4gT0kU9nC38x9M58VHW91LgIyJYFoA0lKwCn2NxB/Df+7R4PcXeuL7A bxYsY5unLBGkRjn5dqsY7Q5Shwg98rT5tIgrNWV5IiU7pz6v/n+swODY0xChvrAkqOa6ZVAisxgV gAs70B199J6x1DqXJGjnZ4XaBoQ3Nb84RkrpmMPoDuOgJ/krx3h3/46YmoOx07Jze714jY9Apr7j l7GFmHrn/TWicrNM8kIcna3rS07gj1pUf+Ou+6rA8mxwD63I9mlVFMNiRQRnL+m05x8BWa281ETy RG6as8cNxKUsb5Prttdtuo6zzmUJb0cpmvUm6bziJrAWOuBwf1KGqVDeMqKKG0wRoMX/edCCBrlt QZWWy9KwRmfWtZ+obDxPTUta1p1SJaI2ciyl4fNaC+hiIwklu4P0qeV4hgDEdIzGPssBuEo18NAj 0E7hejYovxZ9ytNf3bz3brABjIWZsM/7HIB/ZRIbsNjeSuFHwJHMFjIjoeXV4eS3omyvvynyN34y jZsKT18dSjKT4sBGumG+XR047eDu2mxRmpEMgDHitQl/7cOQFaEC61srML3TP9x+k519nppeBAv+ b/oOsJWWt+4c2nsxVBGDJPWO/ibxSguRG9GTZxaAmtMPbuiHznCbz4gxCxYY/gGtTQpHp7QPxLv8 yxPSMxtuO7CponK4/IxuACxDCGfsVdMMG2W/GID1/RUUnkPoRaado6qb5wmI4Dg6JaDvTgtsxOZk 8fwCdKhyk3Wq8cIL0gq0qK3qFInxJpH5qIuf1rSUtZ+AxiHt7nIe/VK4cvPsV19/UHImyryevxHR WAsYtmZlRHs48T0oZqFd86RzrPgcilDS+fg9A8l4az7G+65vx4H7iN77/czmQYKOTnRFv0TbvXLU q+hJmwxeb25wPWv2U88x4ExoZSU7dRMQvmRJn9vL3AotdryyF/fQ24gkzPweFh1dChyvcrXO5frT kJSUm6mwv0usjbS11/c6vlWY2aUi/GkN0Zwp7smom4glA+LFQ+11w4qwbABTODAnqyzylpKc7LwS 2DyOM4x7C+glR1HOC7ShkGNKzMRLFNoxkjC58TAGWaMU1YKpA7WhPV4tsuy7KwCtlXRv3rTDO87+ JRUSq7oBdkCLCEJvrw0qcKUBbZochjZrI/xJWvJJrCVdxE68XoTPnpL28g9reFLyRjSdtqAtAxyP BcdObHNPM8hv6AneVXcqqHoRxxF4sF9rJ7bKWln2bbNRZ8E4mYKsjuicE/PnqAYS2HLajSAwqMyZ aK4PthK6oSlJ+gQUNVI+1YDycCzVFdiv92ZR5g1ATVhLtBvbKmqSzaG1XA8eiCDmNxUauvKS4wah vZLTD/FkA6pkxOECqU3kbxHi36yrl0FLhvTgELV4317KdSvNMk7k7RhY8N+yR4k26jHY5bRPkDHY +4fYy6euw2DgIdHfU6DMGFqlKbU72JejL9WvswpJaL0N8ZWypiW4cRi47NnPWXhkbn1uhP8avccD XjeIhuXd1SgKg4L8K8dTHimqEd1D+Xv7ZNYmiw4VSn3c2Qb3Pcoe02WI0UUqgSyE/4IrvN+Aa1XA Hs+/glf0zgpykI1RnDClE3JM6KV7A4Aob7jWEzy7nDOjRCwWRTfSFWgdkoTcRx0hAMwgGwSNZXBE qGIk+GH2pRt5wQI8AGsKahFiOfwIXvsjRDnk7NKZh8toqBiwugyrp/uJ4HEJQ4/f7PQDo6E7obQp GvENypYu0HxLrayZjgH+mgTs57Fd2w2c7xMqNVagBh+1QUFW4zAUUxoHqbkd4SDBEysr6vfXosjX nhjAbR8GA9iKujeF+7KiCp+8jk/+rJbLZ4te+do1myi/DwPLXk9XwzRSCK1usORM2yv5J+OlvK3H 4mMpSqvsrELs/89iP97MGjvHwk06asJ9dh+6cq7Ggbu8a+u7zN16g45Jxh3ox9HelyufHPrpIiix 4aVO8JLg3YhxbKocrZvV2kcOYR1ZxolgJ/fAviEc3svrqEWLWblSWE1mOwLmGiG9B7SYzUuyobDM aQIMjeVfGK7RBNjzo8Pl0YQoev3kY7bCCNPVSTvgTjI4RHUWS8rWkQ4jK4Rsn2DeqVy3ytcLUQ3Q OIZlGz/dRre0EX03Vf8WFn2fJUKxAzrQbmKo/EQrubLWJ9QPJTH1QuoKccar97Wfqats1ZhyMQ3k Re771k1tCxPARdehwAR0pqcnY5IMGWuag+Htk/Ebwn257iAV09W8v8Y1w4BUnYL6870DMrm2uwf0 KE9qE6Xe51SAKCyTGaQsezkZY6NWP6+oLJ09QYB5ZnWLsB7UYjIKvxNSwXGsyC5ypAgv53+VrEED DqG3ClZM0jF69aws4rvdzn7leveyM8Z3PFleVpZBTj/oOLoA6VbEI94EYhUv6MvORJvD4GrTZoSF LjsruYIxBLlgJnk5ipcHGUhF8I/Qt3gbF8lhW7Wg+sLAFP2wEc6hO3zebamqopMsFFhvr4ZgcmsY KHue8hRc15DtkPl7eVwIcTCEDRzyYP/Ioar9X8diyZ4Umj6tPssykGAvZXDffLgvI/2J2Ff7MWEC JC6pgmJOKszvhqTcrMy2tTRYwYE4yLeLWQNAKwn79Q6RB4guu4ALicJdyY+0/n0Tdki9ibTBxjWy i038VpnCacUnL1B28QYBrDaFtt6qNGyb6tSnfoSp2/h+rIdXk/vhxwJ/HT4oec8oQTImmPv9tpot OVbrhgjFWG6vA6MBU2kWnsZM10j1PsSAlpHU3JM425kx15DWa2DLlWdqsg4LZbmtUEYQFFAZMUsv gwNPZcAMwRJxLc7IY9VWRKMVX5I976IZzmYZfS4/71PYZHxUkneUk9l1z/+prBGv8GuIxd8byU3c qH66rhDCN0rWs1lC0RFBFaexD+Yl6F5P5bQJuIKT2kIr9wsecjThOVQ1cAN/a9FzB2UNBmPgqL1F s/LQkx3x1XOx7ndsM0KEHIT1akWD5o5AZ1XaY2kyIR+cZgOlSm53TU+wnKls3OTOgwziRFxXnSB9 iG9OH776tofj9dNNhdKdzrCYEEVl6zp+5Rj2T7A232rZQZe+Xz8sM/5E2/qrBI8GFKDyfLDHpUrH qoorUZMBN9MSvklrIZTyxvFuNzyUTfvLe7sXF3ZnMR/zXmJXH4Vs048C8jyPzMmCsOOmZcrBFzZr 8QIjrPATshaeU44PvbiM+nYiz7ogm63oV4xUNCHhJRQLhPUCvHHMerJ/pijINUYAtryIHFVJbYpj XY+LRRddmMPI/OKbdLoavj+DRv4frXeGldu2QPi4sb3bKgyoF9AxDTzlCKnQfo5pIXdDl38goIlS b0tC6OTyQRFH6SxBPxvzGKxToZoIhqFN3MeodGJR7oouoXmCUUElVBJiCzUvYRYHsH8SWM2s7zDm x+B2THuX1mCCVEUAhkkWRUe+R6c2tETFInbdLXI8LZCusLbM3MIa8rHTI4aDFXPqn9vURC7enaPG KRqdIhz3a8Pv0MnVWUhD3HYlPR/bzI5za/OMcp6kf6JOuX/QagE/HJ4WocUmDUsCCgRdea4johBy bat0pquQcf9nB6o77XGTobFZf0PMRQ1LD1RHaOw666/OLD/ThP/G7QjErWzOzW6kZgmdjCkckSYT JYAMnx0srdLJE8cTZ77NGgk27raQjeOjtGPTT8YiKJs74ZCUZSWBALMzouBFlvOpEuDN20FL5iuI dgNZXumZyToTI+ljJKRUuSPZqdiV+ImjY8AYhKnpfW/HeBUKc9HUHVIGN3RPYaN6vLKuFPk5R8MA ed88bk4PF3o166+80CLtVGw5qRuO0h3IL8kXplxo3r+jVI8l+NMljB0AUmt5kLtesMNMlqzHlIX2 F9dbhEraDizQUs1+9mF7nzSa4ORHYQ1Q8cI0nGZFkrR6usC8977FCvs9Mz+3TDfwK/TSzLOoeVNP Q/e0tR1neLrw5HUZqDi51qdDHqsSDrPAqyDDtPCBXI7lpq57NS26nRliM7IwlyiHU+66r99igi7T fiGHARRE3JNT6Ae0iUimxdQIa9S0Meo4srmb5Tf72szJBnKH1hus4DLamTWYfsIw+ujkYiNBv8pf 9uBH7lAvn1tvAIzH33SwGA4yagyhfsJtBkin07I5Wu2HtUPkFGrphLHCzTikHhIrdZxFUeQOwByl dYBeHHjs5wY1XgrO6wYllcNNiTun+xUMIWvjeJS6HeWnn3uScWlc3hz5VFWep9aQYHWbYQ5QLynC aICc5HEEUbsMQFJ4GfhcJDg0cVHGpo4qN63Oyr7YuHK3LzD9SsfTiEoNKzeFU6zVRbKGn/e31fkq Sc9QX7uJ+EO1bntMC9xWEz/pnxm6Z7Vwj/oeAh7m/Wd0/pytBXzL9YewWE16H1HRERivJTvb3l7g WgNlkVYDfMaQechijbCbBahfP+O8tEdc733wjegqepnsyvSCkxWudTJGJyZmS+ZA9WN7OcJ5V0UQ uBPzVwq0HqLov4CW0QSUYJ97BCSQGc+x2lf0980LRFCt95XUF47BAw1bo5g2reqIPV3ssWdDeg+m nqbuGeWEyzGcXlvdtVwkyKnE2P0dmeG5QdBvnCYXQg0FizfpHOGmPfRwvR/1Nik1ZXma0FzD9Vl+ IIQovg//nR91TULRa+YqPIboiwq7WWSo48PrWLK312Uf4gHIPRtjXqtWV2dIBqDMmsepZpyakA2W M+NXV4iehCyu8puKl6VnUOycew8sMlox/aTjtO2fiTRuT4FOKWTM8u/Yj9hxNH6MM0dx+CrmggqT ie5v5ZQXRTTrxCpoeWNFvC1NzEvHLmzQgg7ZcXRV+8lx+w43+mnszWbHekbDcsNfGOBlw0byI+7R guTZqfXyuTp+13GncMeCVEdOy4tZStG4yHF5UiiPK1GYZgp5bcm4B70vv0XtpaRhtgErygAfCz89 Q7dKFLGfGbfe1yscpPqG/HIM76fWNjnYnwFBd/wIKD/zi/yckntV9aSEE1IKOOSpxdlmV+I1NwLZ cTWax91wNjp2RdaiV9w6uhvE8474YcglYkiiesE/aHF4NsEvSB+W/XKgNPXVYoRY8SEaRURoQIeD xVavgbTj0hV5xiMnavDyQy/lVpnuZ+wgG4WZHjoM5OUtDVg7YRVku8zfWLN8jlzi/AvU9t6A4GRe YIg6BFDsXKxvRAXHWWWxzQklqYZl+YIzEDOdvCMh9jXd19nTPm6hxhdq9jOUKDor2MHl3S8K2W+8 A5bhzCMG0mYAb4XnNNK3efejsi0KNwe7MZohi7fIKJPqLjTXt/XRKKQYgfuZBwOMfOObShGEzvEV mIB54HDDDU7nV5xA6UJ0YkhJKrAHkgcc/N2SdWOA2miKpVZYcCH8n7X2xM3uJvipcsEZm/S6YDaP QNKntejxnUlGYcAGtiAmxT+K/FHpv6pa29fAGwnZKIs9Bt74EmUXjg/QFNXEYQOOZHxVI0T39tU5 fDUfLpW2EsWRpme45vy6P4NNCAFh1240s3eTVVjBboPHkcyX5SWgyyE4TVlKleSjV/z+JNiNVbAP jWervdTe8Us7dOkggaK85e9xvpiYrr8riPk8TSLaKP5SkLQ1HQVQbDY9qSIidvd1Legctq6CEQIU K9FwWSQ3/SHBou6ccd/iaZkzlvJKdCUNg/YaFpwLDKEKnhq25E6+rG1Pz+wxZgnUJTuJMoB7OdUb 7Jp9623c1L/5HYiBzPICumxxjtR5mK4TskOtpkmS6C0a5oSmzzHJ2V0kxXbT3+iEOKxF4+W81QME gKBwcxN4OLPjoVn50kTK+Azw5pwXBqvnzKK31sNN7eXFIVNJp82uvLgThWDOXU6eGhTNaLYmLBi9 EB0jcWtU6kzFbJZ+m3fFdf57lEO7ToXW2ATwXHgCRUQ7pA6C+YA44H2Mk21wsCfSpVmYFuySpTto UecLBGxhS8zGUIGVgytj1YGV5gaW83aArG5igdP3NnzDopmitCeY8BnMMlwtGAes9GJNmEUdQB93 4y55i6JRwo6AQOauq9yrbszPgTt6bgnL4JqPbXcBZLp5f8Y1ZgCEuHddcFmgXYYjsqwvYdXJo2ty FqzKJUMDcELJDU9HZmodS3Toj7oADlVHV7i5wWQgXQGaZfwdK6JIcsUBdBAQj+FuJzzw04sGDMuq XkY+RfXMrG8J13MecSUp/DBvke6hBD/NiBy7xrYAeVF83E++0F44kKJ7c3kp/y2vOTpyUgrAdCrn hFioA62xCEzo+iPrK30wH7B8z9ngMdjNuWbYM5l6V5y/S3AHMhkR2xNpK0imhcEpLERwDpOZzKtk VKC1sveVyrDlXDY7fY1ufnN1gAl3eMwNHnWHq3Fu2VtM3yZobTurjnOvjfC6GWt9f9oM9DpSVNED 8XByiZEIy5Mr9WWdU5zIMZ7QV5aDxCDkePwrOICGsFAyTtkpFA5LJmIUG4oAv4GYHAa1kRxtsRlu Ac8ygC4HFr0dXYvBJFFLy+RU+QYotA9cFEITtR3ujuYl7W//D7ACB4IImUv2oXRD4FNfEC/v0DwB UXGwFBH6CLVY3wiMrSFLlQsXgUBaoEDTED/dQeT24TPpo1t3oMuyeX5qTbKF0cuIEquwBpw0ZRcX VVzZAkEGYSrnrRdM5szhwGhIFB5/CYVLpEwXNjTQipe3VtgYVr/e+ONs++xFcK/hOeGkFP+zn1jg 3SQ8TMq808TYqdtZTol0Vn2PqnXy4bnBQX5WQZQleOyAcd/veH+A6kabebfiQjK+QnNdmio6F0Xu +o9xMPxfkEVkRlA6Tt/Ls+3AQpS/5074jJldSensoFQe+gcQSVj0N2OPiQ9A5z0DU2rijYpvbTQY aavSKAGYe9EXNH/ARdc0SCv2c2/Pt6XqiK+sID3+gNIJDkDqNEaIRgI2dHpK76GzVsLxXwVPWHQ3 C3+bxwzXnnW9tDJMZWWe+dWnAqBQ8L0n83cpPy4pSd0FibG8vQWqnHalTkWqIj/vL1ZYQUe/nBH0 SRfe8duRLf2rOBEd/VPJV/nYAdj0vVJwFsLd10hEYAXejs06s95tHhc2uWUckRccqOGkxkGf1MHi aRiG3gjFywPoCJESuEG/iQ+MdAhXPSE/81chI9RW+py5pZY5N6ihLkxZDBoQPc72tuF43uxmcET8 gDDaIfne2b3bcXSh6GIt3qvDlcsRXzFU3fwozzDzGpkGWf8mpdjw8Eqmp0dYfKxRRsZGaqAhA+pc 8Df2D3rFK+o4U2QTzkgd9CF0rgrDhWyCTJWGwEpLfecm1+udSN4E/6JyhABKftHvvlDBKYr+2/LO vRNb9lH4o4DE9qfiKfpr2z492r8U01wRIKG+lWjTDkg226npsbzhOESOjRf+NKaPIN6bzUe8RK3t 7YjLttMsmFlzMEdHAmNGV0z7blOS5KmKGw49CHBULw80C5fiSI6+ZRi1KkGP0IB6cnurBEQnaCJR qAabyrKMfYWIzCTmg59h/9dm00bexE06OX4yg6P0/Q60PzZ+JuVk6u6Q179saxtZknx1ZUZUGlow w8cQmqtpdZeqLyxYXGY1rKuz0FaXNBAvFbfWZ89KqF1xLzvS/3Mwu3Jzt3jD4PWYQio2ctVSwdFS bL7qrNALzH90vfRG1/Zk+YI5mM0vxRqS/JClzn/drxQ/co/U2Bj1+Inh22is/VfKWfZpNXB4XlOp +xNasGL1T7ybAbY3gi5PgF96Ba4KULFMO8dSGeS6pBUfYpW5iKrH1UszqoVJZb0JxFn4IDUNbQJU mggcPxd2L2E1uV/sIjbOSNBvQPrkB3UUJrXIaq1IwafBNycZLsHzszwVdJOaYSi7BDoym+tiu1/d ecIKtxKty3OG4r2ylPlcYbQjD+z1AM+hJHgt9yEBV3jD1IIBBFOqWMyrpVwsxhK3dbNeajXCNIEX VFk0ZDG6fRscQYVTy4y7iJsy+TDik84uLT8fax38IvBFVeq2MJfXeWtY0RgqgKWO7d36TJ5/VAhM l8W9JM+PM/HLABFNN5ky08Sf8dH4epDvg7a7jflwve1uJ+xY5hMNbZNzMiQaoNeYc5tChNls9Csx btsXcmc+16lIlhv+OGEvYll6aMiACi7VBmxoRd0SBoFmrYGmy9gRPZeQ/6kBhbHC7vbpHHC5yrjG MSBoFzkMg0IGsiwQNLHveBoAPY1SOYMgO2NY02ug44g/dit8tRDa3We9t79LfSbEJHljdmeyu4on p8yu1TL45VOA4cnoFWeeW5USNr1TcEyOj4lVEF0j7RllajQsbRYzFbGI5q7P32iwHn/2hleMZjFZ pQOWrD3jXYWAMB47uA4ANJSWhTg98NpP6Kj7KXgHyxCabR51dkrUQrr0BmyA1jQQ88W6KxGt3mV8 pCOSNRCkdrFNvjO7b3b4K7agaw87JzBfAlOaSp1PnKg4oFe3PDlM8n1Dw3KXTtXfHzia6uh9LcPb TcwzbTjPKymbr+l5dM2lwdmzZzc6dd9C3AgC2hmiiQP+6ot11mBAMdGULKrZSFobWgXhikC2zqpg 1ieU8zgL+8VWi/a+D1a35bEFPVKTjSXXNWh9XOGlYz3xmk3Oxk5fyGKe7JMpSTskKP4jWQd7ZYhV cT/4OnVHFluGQUT1qHh8zcmBob09l3MZFWa8dKfvnySBr/V4FLAfaKd33Wk2nIvGjQs7QXGD5B+0 F6JocStReYoBjM4LoTqwkMJw872AatAxvHYw2TUcb2KbQOTkSiCg4gvOYzbOJHqLk5JEkbloJISh Sfv7Nb87MTQNv/Sp/ciDkin1TjQqRx1R9hy6/MYYN40/1wFs7JtaJKuG+D82ILtB667dLCP8EyMz mm6BAzoBQ1UnRKv6C9P1YLQB6N7mScSxvoKibl80NtJCikY81tvXGmIoZiCML6YfqvTV7ltsBYiT lHnX1SNJkGPq8x9HuDuidgkcjayRT8VYKGvE57vLOTrpdtZgjR6cvfeZ7OvkprZSP8g0sSkzpHGp 9KYWFOt3gogxdNDKSQZZMD73v2YkZ794+mMpaOPViNbdVYgF8S8RnrFPEfpMMm3CD3j3IuACTWKP YeprWcClOmOMlb43s28OdU+j4s0i4UH181B8SY8JNdpGrkW7R9lmlPQZoVwHc5MdOo8gMSPqHh7i mbY2SnK7+zO+oSiZyckBYM9LuOG13+yeONIhlG/weXd3uUKSY455OuGiup1HiXxQ6OrUIb8wyCiy j9f9uHEh6+ibgTwdmnoU14+FOEf+U93xYjjILwjgcE4CBccCREQJcMh2B7LmidvktsG38mCpQTsi Ludej5zBRc4ZriOV8XLFTWNd05p0Cgvp/MU0W4YsnuqKuttlE6THmKs6jySlAfpF1G2MIncgmq8a OxpVxITvI2PqY4uJxB9hmjl/pxhcYfHshRjJF5CGjuyo8OoUazV1SWA7NRqdLRbr6u2VNDVBHNTw U6ECh0onwu4OpXsRyWadwmX6H6UmU/FCM7WcUCRzNhWZsJY0kAm3PqdjkjExSamqJdCM0BJjDll7 dx4fsKuSPCdUpWkk96tx5zeTTzvMyNlEh9hh52rrEiKQCJN1j/qlmpmfUzVa3i8YV4eI3u//TwM+ /hAGlRbIuUjsZtPfVpzBxEtH0l6NKqDOi2IDKLxGceuqy55R2eDuNaojCX6iQGCxH8DLgzrgPOlL eH89T8ksxITcr+XyCwp4FVFEDaNvDhX6bKsXhNN5T4QXIwuYq1uOSffrin7Wq9W2ATxh1dBtlGDF GwkZAhYc+zCthBqe6aPKcAIICAxKa8PZ9ywIK5ItdQLrrJ/XsMGTsK+pTYhBSBfpFn9H15y9SxU5 YKar6xCE7tS2BAK8Aeo2YcKKHmcHY9DAUh0EQ+O1uoBVdcUiA7WhiHH8IknUxwsklPrreKcQiaUl xl3w2Je4tkVZyVVjG4U136O1S/aONyF2KITjX/GhOPS+0Lf1L/isc2ISGJbbgVnhdw6Q0NCE9vKJ FdylbquSptptbqOk6LJkowNIuLL1StUpH/ANpempqHlhiq9WOX6Nk7g1Gh2nzMhYqZgBCuTKr5Rz 3le2yhm3ic4De7C68tUH2nO8xnjq5qiZ8rMcbKNENuR7F5u2o1c5EH3ri34u+hHaTXGwVrF9XFdu wXllxFs+O/syM20v+4ATBLrzHoKygnUtGqwgY5wKKxhMSaqnTpIB1lHdwGySBlE+5P4S1wweIQl1 IEw0F+PeunsnhADk33xtAccjziGvshDDZ/Eye3DIXALjhAuxdDSCbhSVzOZYjSkM2cOI5brNyX6w SO/5b/ZEzdU39cFy8UhhhStLou2a4ipa9fqkL2BmsUsMHjUesG7a3Qc6ctKb1jMuNLsMMr1tRCx2 qVP8h3Ogjg3BHcBguFLpWJTzNzf6GhQjwrJPMS7UIxWfkMDbF9OBQuPZABDHVOZ431pr9pmoZxio TWX5mfIcjZ7mzobCB7HReHUHb5rjPFDA5TwcEUgSohalXhmrBMc1qEW3QA7ZGQ/uzDyiNlYtwSSs LwIiuH9YRKnFIgEiDZ+4Fgx8atRG7bgoQIdJxLaW2/gCTspH2wdYUfwuAiMASzNg2eFUym6J6Zo6 j7ZEtTTh3e4/HQ9pYTu6OH6Y/hF+q843bauQyCp43nTZENY1pm+fgrQJq+Mm2LvVd2ov+YplV1wm rnY9vepK2veC6fQ2Gj10SKxsfHLdCd5HPYKmLDoZ+LLAkAayo5szCTFar8ZyetMRGUex7kDM4+UJ c5bVvkeGovj9lQeHEAqY/Pb3xPUusmPm/hvnF2wxQ4eBqmN9EeH7M6kcv2Vvm9ZRV4QF+lx9M/oO gYdRPIsjKmbZGsP709aygHkg4b8R3wP31kRBt8UGKi1YlAXs2LGTmpdMPxlXFw/CbYZrJNNhlPNH 7wkYqVYxKwUlQe/zW4lR7cO7/BWSaQCR3WjLYuRILA2Sq4inymclXTbvWTqVwEZ7W2Cg0uNW3xfC PN5+yCklcoO3HJ4s6w3hayKxYGpejfRcchTBjbdmD3W5nkRodujgGhTOzwBpwYtE8o5midQKa+6n DwTLTvnMdh88E55MhA2sooSeD61FW08Voc5if2we1RelMsSKNOKFopW39zMlSqAaK3qcTd6c2P94 5OG2/u8rd9bfPh7WeKHKhviORpnb9F6DOGNar13TApPl81COIMMCgVxkW+YFt/eGoZOLieRTnT80 XpnGMfrNtliuA2bJq4Tk3n/J/m2Ow80w+HEOGwxyUG4o5531rpRFHcwuiFumh1Fqoc8Y+shIiHbs dYnWuqMuCUyQh1uDcycuiaMGVQyJ7ZTxQ/cr/qXpOA+52inB37A9SIxIh3j9ATWq3fq3u1uJR33K Q+fw8OKZup6/xSYrA136N9b91wDMLQspd7rG0zX4Mny1Qd2v/HHX0U+OQum0uPr/lQBs+wnkm/en 9nZb8HiumPk1jI0DE01IDBYGuFQrFWHDW3FXIZ8FjYZBlDtj0uXBhZiC86BL8XMll+vRMb+8PiVd swGnQgb9G0OJpqnh5bSOa0IgIx37vqlCldpXiiwKAo9zL7OSYsTpphKJQ9mYgj/tb+mvTOSPNBlD Vl2YMFDjduMQvL1wwWzds+vfyh6ANkXRzLLyI3YBPJzdUEQ7Adqzo9OA1kHFUGnJXG0pzXiX1jRy iZ6fsBT7PYQ+Df5SD9XAAYUGuojTV8uFSlLz5COHsMkJ5I5sZmSlAPBrgG7f/uxXrRIZ7Mw81+B9 X/azYdwR3zryIk9LaebqRizugRkT9JCIxvKmRGwOsoCtNfJ63pLVeKg+OZKFR2RBVVvCmmSNG9SK pfkgcuQEW2FcfvH7XmKnANBncvalXR02xoibPj4t0jJkBKHzBfZFIrS8lG0/QxJj8Z4qKHKfKkGB NEQe+fn/YRMXHq6FzEtxNkHrdJfYN2fnQdffkpxYAQ2AeWJcJlcDC91/3DW//sNmOF7RvwtMFkBy waLtqMfeXKQ4e0M10aZtHr2TExbnWMtbm8+9cS06DgDNUU7qMqQ45s+NFqTC2fwFRc1rbB5Jceck jgN9W7t8wrxDOsnH1X4zrgsJGsV/+jeBpuzIxzYZsl67y8kzKBPbjMJin6/+fzRgsBxd4qczbhm6 e4E/U41zRqsV+FYwR+LHjvszbz2/49xq7O2qPqpmeS4XdmM8eTYj3qVHOBD/tz/VA65IsEQpyHUU xujGoibppB92AJeqXM8fWSXXo0gikjZybC0bbJcC4L0HSP1aBJtIDDD47Y05UveFM+x+ELhj0tWv Uz/CJFJ9i+5/1R71TNXwxyJJliUrHR3d1vSPwA1ecvNzfAmuqbVzAWsSl5UNw6kfmwyS70kmH4/l xt0g7NUkvekFhNETgAkE/rHcmej/Rfld/BKp5LClBOhnFBeJb9CoGcChFMENAOngry5De3iP+Ybp G+9l6wEH4thq3qxkrOvyIorpHnlXHESASUI2vKgd+CYtHEDtQ0cVWKTYXuMGgW52sb1k0/N78oAg VOuX07E6fTVcLW5AIdTR5W0zKTWYYwPFJ5yS0xGe5XOHwXXpePjMWuNxRz+ei0b4mYXJ9mCA1Glv gfhfz0f7pf67/SlQs8dRTNHvWhVg30+4ZWsmBynzReEeL99btqGAmUkWyc9ZFnjjArI+o/VUlzLi 6sY82XFcONbtChtmFReMtV0W20L1qiYQ2GIuOShk/9wRoph4p6z0mREPqjU3N7AqlUXQ8INn6MKT SosieNWtj1XWxlGTdI69TWMn/fVryxsDqzkLE5AjcLN7pE+dm5K2LqRPYv+0lTQYuQ/PNfVaYoyo KF7Wx7GqUb7TdNxkSRQr04XSZ0XXzESGnbuVlJUWBK5JIbeY9scEmjV1RwqMdw639oNZBvtiH54G izdY84ZId+kHoCU1RAWbzOX0eRVxZe05r3TWIxuTZnseD/59uTqkQo0TJlfAg8rpgQTBY0H3ckpI IXXLHfhT5BPL57cxn5EDGeGAsfagd3y0CLkffXWyAFvl2B9XicIcsLAdEcyZB59RKITOXosjZaAT wv7sXZ/2pLrdqRHF1+bteGUMzlMTgEGj3+Y/LGajBdszCSYmJ1KYz3ndsnGORiCCktl2Cv/5pNOY T746JCD1hGzPnhfSiZCIHhLbfvHL+KBEuA973oGldigc0PpnRO3er+V9EvceF1KWGS/cUUo7bvGD DzURETeQmWFDS9Bx7O4dqh6zCqoYWhdST9jX+U8Y5iCDG8oQdZ9NzUrYaAUVsf2Fp+VQIk33kGP8 kJrhpUFZZnOOQV+HfhrrQ4iYtmJvOtx1gqce7qIPPgOLqfsug6bRUtx1tHqBgJd/POgmZbwxiJj1 Sxn/4JguXoStE+4kciJw5HJvGoLmDft4t/TShbLcqELcCdzJQegRSpe+W7nse87iU62KFImmjTBW LWbRNRyFJEIbW3pHKNWCpoVctBdLsWJr/3tucvQ/k2HResnVogmVM6v9vjiCHVTF2NmiYxGhPxEq U7Deqz9qZcVVCpQCfWbCLhJgTygZxzV5Whh28Dwtsa1MHH/GKHyC2UklDNx9eqN4wsq/lWbe4fax OkydgSP+O/w6T2nRvOzi+t/7h/KuCrlyjSPfauhuNqpQGfqhVMpro/w6iz6WanIkMy2buEwdnnqR txNE5QNfx7r/24mhp5zhsT+stx/QiOD8JTOaO97MI0+yo0wzsctlf+Z/U+RFUCboDELWDtnbTq2C nB54HY+CNpgDwaRl3gevzFLDUys8DXfm8d20rQBvi9PqxyibosI8IyPdDq2h4nOavz5V1NclcaNC epqdRLADzcMSmC2wqCxG+RFt/DixmGveiHDw2Cjj0bq9/LNkGQGpk7UF8G/u+6VlWe6SrVh5kvHo 8fGDdC9zF+Ei26pzTDYyPtEgKnVLGUDlNNSfypZf/D+a4rTQCOiZHMGI5UP3fl7FvJUKqY3kRaZX +39rE9mTuFYowcW30yeVCCcdxlxJOnkz4rZPC/FMZg2NmfQQkdjrVCZqFxBNvW9OL3NO5I7pFMVI 6XVIYC0fvq7Pz034PidqofDE4ZQmJpPKOZukiY+V1pnySzN1A0z4+fYsX2sCQvtLgyG2qrTJ1vYv VrYpRzbvGbVfV2aaV9m9ClW/9g/cmila5CU2qZpjPqsdtqpuVIq9LXjE49fQ8/GulhnruYPUqwzi bjsSzmyNDav+U16QxTbZ49qbGQDO0p1So60Le5dAPRACrbeRtElxisNf8w+QP8QxOIG8S/Yk5e32 wVG70foMSXPVOryxaCDKy1vDjVSjChX+zI/9xvFR1+m0IVV+i8aOU/URJ9ET9eBUbCxtc/yoQfKr eX0jtWCHggKzaeI7IvVeKXiLyPGox4bcDWaRleaUGqXaZRvr6M0ueuZmvrl+3dxlWi/JSIGnkwuJ fU8wA8+7DEdXI+YRhtCzDxm1p+s0+4AuY2KThPIyjyQAAhIJTTEsv1jrK2VUb7BDcaU552N9S6P2 p1u+yuCoU+eaH7yazQh1c+3u2aloBRdxmLbqp4OlVTUzP4QvkLhAXksyrE0PMiCs+dxL2h/vNPm2 VDOW1o/FMthguBxi1Sjqede27TgdVWTisSxgqwy+UcKZ5AJxIATbZfO6YPwMTAXg/CZAW8HpTCij IVhbJ3wLOTVrXe/XHmAWejiWYj/UH/9uDjRajtTZLHR85SufjUn8816z/vcnfJr+LqaPpAlMPFJt sxWl7ChZbIQ2xx2vinBUtWKxm7RwowUjWwtVw1McU1umSWq9zCuVwM+fk3K0wCMVb/T58plWdTRV 0aGSg6QmrykKdE96qjZm2tZGhbOZcQ7PdehTut/gw5bMBWxEQckCHgQO5AYwaNtHFJ+J7Toj8gKD rLmCDEgGec43JgdLG+enYDqZR8DQzkPqOSy34QiVWnWPzJvKIELDakuxZc1FouGAzqcNIH39mgCT H2ZAo14LTDOPFbVizlE8ZPbywF5e2L+mp/sHogJNpAT60skUG4q01uzk6uHn6nhesNFw6cIkmN93 ZR0/bngJEh76m7blSinelE+TMVjw4shtKd0s60bkzJroNDJIohaCwPGPnt6w9MDwNQePlOJntFZb IDoiBs/DYtFXEoxbCiqM+w+AOce+HkwOMLiyzZBTFDLeDFD95e5k/9w2TEqYoVbCM6awWEeFZLBA 3HOjvsER7EME3CcunlGVjql0weZISS7zjq2oIx5T3zLERYJ6AOrrHUHOctjL/T+Y0QJdjlk6y3ib 2EQC4UYwUdosojQ6bqWNCc7oUM//ENvIdfLJTbC7jI/QkKhtlpADx+DAHkPOcUWY9YW/tbcEjNo1 nX3/pEPn1smmNlauRkmvZ6QQulnNsNs0qAXlt5sZvxVBH9D190rcD39SQTfo2sWeXHcBYwyttmLJ DPf9CgEhnx8hhbYnTwC1x+ct1YtNzKH2LIaBgblE3EtsNSQ5HvIXn7RfYZqSZP706d1wFyRnSnuv qfwav15Ogx7aVHqAscFOWfXCbAiriqByg2lTAbZapHIhM6oTP1VJtUAxpt9EZt8cxcRNeMnXlwuV KUJGXbo7cs39VOAvxW7f13ROXwdfzv4dy9DJMSjaCgA8xam/yU8FL4fMYRAbq0dFYeiP34YHHSy4 Kefpah6stPMUPWz+S8uzcWx7ywxiIbQD2oAI8lkdBe/Q0to7YiP4Qv7m9mTNUZdeH4JfBtFQQtW3 Q2+rTdjACTa+GauIxF3WUpwE00khpZ3ThdZWn0gHAKEu/muNpNPMzVrBrEY4f926Pzx5TCwFLyyQ lzsVcNWOQmCH9juEjvNpci18ySz1bexfBa6y0605XxLlWr+5m4IOvZYfCqaNn+yga50Tvn8GP5Su HM8EKVd7ic89ZKrTm19qS7rvfJt2GmJJF5ubQOnbDyZ+eOCob7IRMvJ8Rr0gVbhMxzueYbDJggsN TirattqHMjtEDw2/1zrFK+nBPtLAzGue6z7YerjunkcKICbZOliw/KrbC0Rz/UdcHuYpzSuPohk3 OaDu9IC8qg7cLNvQFTXflrXSo3l13H+76OK/4JRfmvI3KyZ24mU5AK/xV6VAyzGl1MvUYNYFTsEm hTXGK9gwHbj0+Ut1Pvr+ETii4m0aJH2NOCOnhI+kgNLwa/4WnRcfjhNub+YePXgCKifsLwUgtUy5 2TKcour8yO67BHCxaIG/81sjL6mRFP0ucNnOb1mqKGIuhCCTtIqrvOv7IldXcyHaXYZ087O1pyyC kN1tinYW9W4CFMeBncnTjQSq/TG4wNEaieL+3223TwTzKk/9BUvX0QpF01uASbVItayQvRzqAwXI L3NH57kcVJvxqtkPEctr4e4NNwT2U6gI9DdGQ5YEF3hnJS0mRYQgTGu4rI7b5NhXNoAHMMA2gbWg JqLqcQEO0NxOl14I1W0NPluGXln8KDthYfvY+b3AfClw4bQv0T1r+fp9kqa+mPJwAS4Tnng1ruc8 pA+v4+uc6MHJzWTA0A6g0zC53uVg9MNu+j+ZiBXCIUwBur8MhDgzGWyfKmlaGhwU6T6s9/kP0BSO yyUIOaPxE+GMn+POIv2pGaFmuLrrFnSHSYUgv5YOs61dsaNrb6VAQF9EWDbmCZdGjn+S/HldLPrH VJvP6WhpisD199oh/FKGHe9Cm92ZBaKkV4GTTNjM0uBivptV2FkuAbLwULaaQpa5ahev+x2LV7ba e87LfxXVhkF1vKXyGwU7nki69jXZyzfJ6zfbwEZyhT7MJtjVsxQjejtL3aqwQObcQ/ejf279b6fA NueqnZvAhtLSbzUkDzibjXT8U1xAvVYv0ssWuleG6VLUROvYXq2tTeJxZdzg5YOW/2OeUUST9kLe 9opK7xZMO3Z03fwU8Ezzz8xp4719NlEbrH3+ncADNYaqUhoxfaA1NdGTPpzDSWRn0/7eol583TMP ZisrqtXqHarPFTTlq2CFPzavcaSMfnHOhIyE556z8j8RAKeq/geDg9BvwxO1WeEco0ZQM22kkRpE zz6gZhYNJeE94HCVgWgP57TRijVqIXcXjTl1kAYr3IlgF34zLeZ1QMmi58S1tHNekKtnhuRbRBvc IV9Buemsi3O5t3/m/ZS8ggNZgdou5ItXaMy9c4jMSI+nTddBQeCLi2CJbEqvEkPbv2pJjCEKKZBf uXJwEgxR3TDzg2pc3tDrkubFEGnaO3EKcToubhIXCr7uwczNDX3rhv50vjN61a6zcrjwGZG2/ro0 v95UpdsrdUJCbih017mJGvKh2rGQT/30PuCa+iy2z2Kpd9I87dYrrWbr4JhZYwAsMkOuRv8w6aAV o4fDlhwUBipBDphHeopEDRWLpJUrV49Jrff+GNnVuTbOUolTHetDkAnl5INuyPio4X2XjWup03sL ETxksd3s9WO8n82GAK1huH4TZ6rDjHe2iczmxetgmsxLphS+doWdY4MNZMbxtt37+4/sZesQaDLN 2afGOQTwbg5mWib7b7/Bpub1Xm5ZEnp7xhExG35Fo9c49InSCz8YGXERj9wGNJp+7tM/Pffw2BfS 9A7ZQWxZmviQGL0W/PINxSrh0BphLiUFU+5HAmSbO/Fmt4T9PkxcA/CIzUunrFlIFJKzXqUk9JZ/ eI3DDucM28IgdEvJW6bVppfUVhLWHglM04q6NM6piHE3wfrSZ2R5PbLF2tlv0Tgf8mmou4SZ6El+ f1K3VVl8/aZs4TB4HNw0zBXYoutwlwiWhDA6ODd/i9E2pd3szzzxVCkYGP41WZQFwgCOA2Z/9bzr SypRdZHAPDW16a+WpMGiU4WUacCUN3Swn+XlAUO+zo8pibja5njmzElEQILNyRQq1tzFh652iUW2 PtZxzk/aT55xF4PbVveNThT7Kj577TTfjVf38AcvY/XCmEbaoaJavIeS5j7luCbG7PFmyfgb3HrD B5l2FYkW7PCtzax4e6y+ZcUOLv0CM+1hzuibJuKUy+ynjtr0VqZvc/ElXOvqJKkCazJ3gZvghSxj K+JFwlrY1+cUFZVCWYQk8YnHXQxfkbs6apQs0DMFbmr/gYzV7m8De2NKwNnh6azudqR30tCbcHSz +YQ0XYpBFiXvVAztGfzt+N3WQfZyx3yiQdL64xa4h/zhFUxFkNMAwOncNJU2JjTSmX+fhvjVd+jz omF5Xw6VzCGF9gnhN2IAX4RStYpQ0Zg9Tm6TtS1ICbYhUMafRNXI20NL8TV8Qnwm34XGlFQKuaUd TMPmaiGcNLueSTZuw+kA2FcS22/i0eJLhLEMJb1Zpm9uq8JA1wnTDlZq4Bty0AK2bs/P039I3FPw 0Cx8ATc+UmQYtMGUaplj3wYNpuUYhp0XvVj751DSLQAP2wHrxzuaKK9ZK2AHgihdj5YNYcI3WLP2 qbL8KJtGtNwTAoNhRXzZUv76GcRBSCk9cRVL+WQlGqiRnH+Be4jBBABJ6Y3YjXfEo/PQjxg3cwCS wN/Db5Fw7Jm0U48R3xi1i1iI072aZheCol2m6YImCRSQtrouHvI5HFkpaKCprtOOk6HmtIaTxUro DSbNRafiz6D/yaHGro0bRd1XO/lzJd7tJeJufhj8hv89iXvsDnoPY6uKCJzfHm4+8ni63nA78yI8 4yB+eXduMlIC7f4R7CkPNBF02wOgA9j93D5VoUMZlJnfZsd/r1WuP2CXnB+0Q+yQxlPSaPbhMzVC otLmM+BwaEIy6ECsTRLw4Ke6EgUreYUI07ZaFuyDTWeQLzD1Q/lu3ltBiqdgU+VsZrKue65ww4Yg HAofkcrVLbCK4lcYKJIJPq8A/VFIo7X+6im6T8oyHzc7zq4uVjZzjb4CFtLo2jdKXvZviYCiJTXb w1q96zmBS2v2MBW5gNf9K+F+2s/schVGI5j9nsrHoqw/yPecYcGyUPLoItiFcIjVhzp9ytaCyd/E NueAov3kbuBcRW17+ixB8+iCryFSyXVQexfKqwJa45iIw/Ns7A7FrPAHr17ta7RKUGQYoFc6AH1q oGQaD6wsA+5yYuHyYXA6ds5wbLW0Zaq6dzIyA7MV2jr4/S44+l5+GYW7ztvlAys97KgaGc8YPsBH Fev2/HLLgtK5HANndqY4lZYNvEuC3tk08dP7BNyfBhcVo0W32MNcI2IiXqcEgLtfFvx85qrs3B59 lpSyTfBg37niZWHwrS9mMiiOZRJwhiRahuOmPAIKwDax+ouJicAIBoc6P5AHZnKYFD7cLgFIYq6v AuWB/MfeZ9vyfJFTH38bI1PNQMFOueUw15D8hOAS11lj9JSy7wPu8AiVHATLzn7hHFcShoe7eopC Jze97N45xiK+baqajPvkDarasIDmpv+RZyD+Z61MIKVTtzH53il1rCQia7p+e8h7SSN7obuflkGW Q4maS3sjmTi0oHm/F/9OZRku/5bAkDrYbPjlciZEw3unrkw6ve3RO+WRkl69FQPAPWR1KEJRKuxE yY//jkKP1pHWfWvwm2z7jQp+MPnvUQ2hroufp5H6jYcp9aWTGY5ofZCASvcMd0cURdMK0iHb/IcL BsspyHE1fouaEluyQ0yMHshWVGfDm4E03AZt4yXQWPhlcL+2DcHyMeLzHlFYy7feqQrBEZH/6+4f bQPSM7FMQIe6ZQLhbS2kJeQ912IwLf1wcItWQy90rrExmNE6TUGL1qXy2vZvkWFZM/fC6XDF7bZ4 TxEIrSLKvXq7IzCBt4lZHGwRq/W6mEguMVyFqDhZWL4swv/2fwIhEBZbvlPtxmiaLVg9ACQb3AMr 18mVdqGc930hdZJ8O3aRxXbbb404n7Vm9kZTlwU1L5UUtGblkivGmWbyNfO71i+lZ7clNiYofV+X 0I4RCJ8nQ6OkDv9y4sPfMiySrYCbGIrKA9C4qP/sutyON9TZTjGIqkYU7ZPa5LK8I7g6eJyvhpSl BNcd5hvBRCAPenCco+6YLilWoZ6YpJS9/45jqEAgMnJXNgymztXTyfp+gZewzBTGSpIT5H5+mXKL e7Z2aBAG1L5zJ+iYuybDZt5wxtnMjl5I0EExKAurI2APmCUwLXfqnWddyOl/ZBI6m+YnKZnFb8jg NX1WL+1X6ixjdTdSBnl0zqc/Z6FYsQ3g+xiuYKLXQD851LaZq9YJOAzccnhxbT1h0KHMlWimyWJe oXQmuJJRwUvJrTJxdgZPVOvmPN7T+6fVgFu5pTM3aUOisjtLJwyuQ2Jz+rgH17Lbe+KmyAIQsqJR aRPSy2XDbeBOJtD+hBpCCdC5Xwl3OA+Ty3i2pGxhAWx3aX4O5Y/c6WlHPXXBy2y5YJLd4qJOJ9fO kTcxRdSR+7g1Ih72BZ4qm+0X1Z93pdDqORXYF1y71Q4D8ZbFY/0YPhV4e1kFMdLu9h2+QwqWiaw2 FySejnG31xEgA91HvvwLym+GFE1FVoUGjzDsR74lTkOLQQsC8QIbZaiqv0HR+XOjCLgm18tI4yQ9 XzhhqQioJMpzwK+mnnb4Wr17fj1uwYoyXc6PXqO667bEspkRVb/0qIefc1iHPonw7vGD4fwCtRbs n4HDHNan927bbn6Qcmnv7vssJ+hz8ClKlM+MmmUC02Cc09/BazgJBFUWessrFWdUm0K2qBJD4aCa Vj5l5QtaNV0CSPaw2ypKacg2xd+CZ+2rCD/M8u/QcXj/z0ZofS0eeQk0/tGLF6TUkulETM+WyTF1 CyPOMvMDZ42T2xivb/nghafwYk5RC9oxdbcn7be29/Y1nKDzfpo0z2wC5GqLhnkZZMdp9dGb4T4R 6W9N1Ds1ogdUUOktSGbYz2lvTBuLZg5RG83zOGWJBemvKlXEKCCGnQJsSNKKe8xXUixkGGaA05Ek Iv9Tp7QNmrkc79XXrIpEVGtL/eK+4FYLCCd4mhkTuGjWRYfTKM03sVcos0nXCQE5A4uoUjvgjt0S Bcg4QfOiXJtSU3yY9clJhKRcsy0HNAKoQo3RsonJQKZcmDy0lveL03pz0zEjQm7uDzE80qcb00Od 9FGvB3yLiN2EFIyt0nd/KM9i+0D6Gnf6CYqa3h749EppNVW4K5FxajBAXAtd13dz/m+nJzoL5Kr6 pUJjkq9mhlZLxZDZFXuRV7el0NlhpnStgtbL7YzbzaNN1JkQeZwjVw2osXRmg66bKExlX7IPI9en e1iltGbpM7hbjUSkmT490N3wj1Gx1xPP2zZMdlvyzQ5ul847UmHVdFdJDyFFZLWUKDcqVnjMvD1X UgVPTXwZLxnm/r/5IS/tu3JC65vvYeAAsbpynbkka68KRUB0X6IZN1n4LMXjGRYyz8GgrnAyUpmC WYPX9QpNII/DRDg3OHTs/a1W+p+GJrunaSNADeA40aHy+dU//qFGCi+RMDNakXxY4zDFt18NLIYv xnsjB7tFa61NI2IoF9hzfATQUqNhdH5HZKupbKjijAMwriIs1/MrigPVPuzNGjsWjuA1K3UaYlyz Fc8E9nZGG3B5LdupOnDaBZ7AMoqsr55Y9pIA+ACGvtezHQtoqGRgxLdfFjCAGFVu1sbyjK3MJQqj IS0yLNoBMTj/WlgXm96qsjbUOIHI8a1jozkorEJCR100xowRGGWHEUW0mbaFEgW+tFDbLmV+aF+i BU6k3Tu7knFDinjdNlinkWZmxdudrTxvKxzlfyZxCpr7bu617IbWg8oRJiiBHk9i22wfc6eCvOsp LBBaC+vEeZnWFZ/aQJZtZJvecILY5uwgKuQ3mEvCzC+jjL7oPPJQ9dHU/1qGorisS0iNCL9Pd37w whIoHZp8IIh6peX148sNCHByETiPuwCw9HEGr84Wi7vSxs8SZNfEvuhJj3tnR8LdtglwruaGDHa+ aQ8vg6FYYiX/S3K2Sj4CaPviGFBzwLLCJzuzdwieNeC7qYWdHUEgOWI/+EFugQOA+o8I+Fq3RHAe S9Vl7e5zAivM0NHXJtggd1QCMXNpKmzayvpCosUmrxvK03El1Z9FFJSn4Bimpw4xg6hlZITllJYn 4EtDY6mpbvGf2c2Om4/5EBch131CYkHFpL12rTZDkNhA8J9TIdWGtXSEsFEF6/Lf2dEf9d7otaNS +zQgMyaTcoTHRatlj1XIoLBmcoRurgrSNcZQ2Zua631lVSCSSvjf3CgJ0r1kc9g4GmeiKd0Re7He mDer5/do0O6kXWnhxzNzQ//2wxA3oYAKjdMnm3g8NeOGSvFlot9fOE1OCrpIhxfW5chNVZl022U9 AJGx0PjxGU+NX2Ei9VvBfwDy/NVwi0f4uWnzJX6b0DXNCJGHbPPXIm7p594CaMw8XzPs0KcoLW29 gM9ynbbnJw1K/23aL7Fj07ci97BfHcNYmJ12giL3SqMxJHRhkFXKA2LLliGap+EZyl5PJPnPP+kY kx9Cr7aj3aLe+cmrt5iRXpnZsdnYp/YDwU4UJUlUoufXFUd/Swa53aJ1J8fDCwG1ngIpttok9zOS lEuTRDOInLkPvldTQ5obAXv2iOfevuQ3bbv1Y/wejAn1Qs2hW1P3rPlzNFijbX4gjsaF7wm8bLRm LJyebTfGtV+9h08XvQrhK2GiFQvXgZPCBQxQk06R1BXTZov6/Qx4GnKCLTQseG5aY1flnNrsqs1a Qm+4qQKJtF8BIgxR42mG328qM6kSLFJPI9EkJa/gsL6t/HVni7bt540tpXKqNIHgwZk4FZTPQhfK LjRjwbfBSHEpk5Ri3lMB4Jvz8TNXD+qSEtKW20qKnvIw25Zd62OcYqU6fS5HKw95rENF3T87oTth pin3X6vxBjfoWYcM+XYcgF2g8B6f4xc1v1fXSPPtfW02afbV0y+VLUlQLji8I1e5n/TM+LrvMKyU d0mohb6sfhJFdxGO6E+IOUusyCMLtelVIv4seCevqF6xf7MkabeeI+ewnnGYGnIRkNcY4TGEmkCV LiDjh+7DtecHJhS9OQgbKzJpDfcAgEEsU/BBn9PXs+PXkQHcAITF6HBEqDQZ/Dpx/bhIJ7lD6Y89 NR9gaAtlRTJ+ddcivPeFGj+6U7BKTsmOexMiZsOPt3V/UEHJM4sP9VJ2zcTDfCLxixYILccIX+8m loK4ayjdieUYer+tPkeg7Xr2Z6ONHRlOOYMC29wNco66HT7U+pnCAXlihl0ouZO66oOgchWJqw1Q MFAFu9bH/oocq7TKuc+gzloTj3kS0/5MzCOISBZX4Oqr3Z7IJA4ezSlTJzoWaXjCRo88FCglR93h keouWUiI0QJ2py9lByjnMDRiEXsMMEoHCXL5o/9pzWczqIgOpFZPSk/GleYbIUE6H0Y0xnGIOwl+ Lasd7Bd+DzXFtkBvkXYvZzb69BImmHvOy1zrI2RwJFkBMXYhof0OiZxL1ikdTv1x1Uhcief7nD5b GXGZclKAp4tzaD9X4tUZ67Qj1vaTJUV2rbt/M4j2BZ2QQN02oMWajLdEaO67jyG87Y+gQNfCFkOM u6uEavtrxMWo3jCLhhKIxWjmriI6po65V07z1efgpau6SojyrhgslpdK/qRcqAH5R0ckUe0cFs6+ immfAqLeWCaw2yyqWhR6GnDdA0KuiFeAyrWnkv2zyR4hbfTX6wEuraMDAynNQFLd5rr68yexfr5G uxa+KaFJTIzd1s4ye003OAcTUvvyrI0A0FCilR5nOdZqMDYBVvq3Df5spJuyZsVz1lvAMSwRn1wX egjYFCcnYNafNlqOAzGMh0HbKhlSqvvWgXz42GWsTN9SPR9SeM6zYs20E2cL8LBTvOOeFDYQP64S lGOJOf6g+NCl3z4rwHkgtmXn+uz4QcFsAJNGC64FQFaYlGUBMydja0DNBRCcWGUs3rJ4xIv2/f/n JVkZWcW9PNbOB7lf+0vX/0pQAJhRkH7VsXxW/rPxJKNjb79uYIELFGhwBkbiQuuPXmHdDHxUEBdD l9IsW1ZGWmqcnIdeQndRA9pg+dGtmf0CZSiiTAEbE7JsUscxegCWreHkRqdb9OBZ4lPYvH9Oh62C pm9IYMVo9LpTOh4GjyH/qB7dxXhgc0mwTnZxSP09Y9eu6lO9Bi+Gw2DWJTGNDW1NcHb5kP1Fp0I9 AgkV1xRBoU9oPPBihnszYYry3U7b0+bC8Nor9EydN7j/Edx1tkOGwgQi5oGzdZv9w1Yt80FQvzaN tz8YKWIRYT2lLbn/6AfjM3DCeOmZUnttq4EB2MZivYxq9LDiIBCYI4IR04qu/cwNqeT7DAbaITVz ZvPsgisYPjyZ4NpcTQNz6szCfHMAmXw9C9WH9IOVQ4Ejtz5r9fj88teN3xG0PPw+NRuNPj5xKZir NK3zvT9+oWJ/bDP7OD2QOFKB1xywJ+jak+zvwd5ypr4FviIfgnRWxWHctBS8skzl8vWSD53oLaq3 +MuUmR7PQHOS9+b1nJpfJUGrXQ/3Ln/t8RVPof9hTQCpLHGl8b+sqfyLuiePvei4b4pSAUO0QPv5 bZt48suGQiescDcWUBLy1EGH+I8vCm4yoilcO/uC2cqRli5Y9NKQSA/QBnWaM55peQKbH2WHxQ6M m2vS8cLUw3HRG60N38ek++KS8jw9oTOD0j/ANVrQbP2s2AeHZi/dx7vCaKB9/Lee2svWcR2M9kVD BYQ+K+asX3mMxVumG4fyhrUonCLYUEw/XUNPLzFHWOIYyEL17J26xfRJB6z11RA1v3y/LYigyoaO Wt89juKpDj/QE9TxJwWVo7w4DLdqRXParszSNzbQ7MFI0nFa4O7Uq/OfmCIjfjQlvwaz0mgpWyE3 GUOogSUd1dbmT3uWC/gk7E1BKAcKy3fULUwm9ife6yaO6M2iIjiIh56mM+ojM5bfsiOdscjiWEo4 wbbpDKObBHlxhVAUg7sPSdzhreV5CTsI1o8in8vBizqlLFjdqiYYMRGTGqtizkb5a46Lh/+4mekw 2EPkFfcsUMADKYW2+v/Qiwv5xWzsibRKrM6zKsJA0qZSPZLSykAivu0gP6xAVUmesk57rrozxigs zSmBemAF6NpjEluzBauoQdm6ufd3UCHRNIfDJVYPt5IEbyqbwf4xYqd0XmG4FVWZpJnvM8aFfMJ5 QCjbsWjylIV65o3YVDrRdm3azkcEEnYTQiwLUTeOTtJX5qYYFpdtdWZW4xjqe/b90uWrUj97dD6T mFX63cALoO6HYVTKfg916a6GA8drNLMjT+y0rgK1lONg7CytJxgaOfaupguK0BEnhy5qLrdRS1g0 3vj0/ikjkbb4xbx5aj3lfOJCHcVv/mUDBQoqm9+XqOV+M1LiWJNyDQYWlqMZlAnfMoO24KH449CN SimYmO2XmQOscgb/gO4i5oRSncqpJZgspZN4xG18tm2LD8ISmsn0ldoe+48TgHnjYzM/noFKoY7R 9j9HeKp/3k5BJFKHk8UfRj005jxhn1y+wM1lDD7os46WyRIr9UCV5LxhtZqDP6XlKx9QEeeATSQa P1kG7wcVLnUZnr3TUay7zc6R9bmoMDhmQYnEZir5O+aX6xcTshq+1wWnMdEiH81F6EfvKU6Cr5ZA 9q+wHLS7C5FkZSQ0PNRBw/vbvtCF7ttkxUXVd982rA1sOrUaxfYzJzA58dlfcShxyWokycW5WrOg 7B6kiFmEBGXTH1wDa90lXFHyH8YBWlMEfjZAo4ahvItn0fTLe9RSoyl5W69chUMaL1r/pP9SoGX8 os7D0HPoRLDFNyJbLFFpAeRNR795gOrAezANpDuqSJRplabTrRtUNhiCHColS277Q9hif2nGDKbr 3BqEZ1kKvlswHeji1hqifQwzAfPt6f0eYdLS48UX4TwQnuh5HuG6YYUsLwe2jpQWSSg2eQOmwH9q twVQOUrmMwTzoTX1SJDYeFFY4TMJGfBjdmC+8PX3gEdcqXSXMH5/qSChbsYw1i9B5zvrZw1Vb0u7 KbpDBE8cDa37f5LrgkN7Rh4mS9mfnVeg361a+us7K5kVA8wFJ5Z5WbLlOa89ydVGxNrGFQXEu9RF e/BU45lVI3QhQ/+bW12QuFsIZ9ni01eDBPZSP0QCz7q2jySzkyB3lbzWcS4eVzxnEtZD/B5rMV4y BsoJ23eC54rpyWFgSP1Lf1tDVcRltmZ0lw3uxp90i9/DkxZDFn95suMr8xGdnPk9ZUAbfEBpdwS9 m3vPa2mGr8Il2rVRrHyH8fB2RR3KniOx75HudovPgO4+QmJL4gm37xB9z1ZvbvQp1OvFxVOj7ADG mdE+GIHze3iC5SEXxyqCLnKUxEvjwf54NT3/jC7duhZ+oJh7R9Z3a+9h4K80jij/wFeb4NY7QI24 iOhhqxdmLA9wN5EHFX8ZfbbsUYrFmIfv/LTi98obibwjj3pqzl9Ai55R0IGhiNYnW51U1T9mDIFz RQjDdhKZb/1yaHibm0XIty6W3m/BZ9IU8YVNu6ovddwVqKfz0rpfMHLWZ+bhKL5jxr8e2FZV/S24 L+I4sEgI5iZiSSWTLtjMBp27iS0DSnZvqSrqpzq3xsSf7TvuRsgXcT00/k3UvwEdqRu4ULuh44CD 4VBGKxJ/55LAGyOm+Pv2+b0Wz8XUJ6Q6NPBucvaealXzJNJqJmmXo23uz2m0+buXQ2L161qoAvuQ ndXqtPhQ9vgS9cgKIeaQw3XsPNtjSH7zJsdGPshH9LRQGhAJUv8GtEkyv2B5gGXqsyUhEm7ZLHOq 2Mo1LkRw6dPgQkrzZI7lgBkgVqg38IeA6+TOg03ESPHgO542gVgAWgwiqWTXXZGMyOt5JO31o9nw 7QAlpEfLMiH92oXiM1eLyFa2mLyG3fhWvM1mxDd8VcKOm1047jtQDMZL0lZpBL/OwDl+t1aia7Mo udgVkwZWQgh8thdsv7JcNr0ah8dAYR2TX5uY1a1HQBx2+OzofesFRFZcEttg1M8mTfEKc4/PBtz8 0wolT4JYJsU6+KntPRUhARQsWiIURgJqY6TpdmFXNMvXk1Te8p4M/Kp4RTfMfbxwfS4tDTIvi5rT sxrp/oqSyY+NCxc/MjHehBBMJMC8IkxzonjLUFpdtRcXnY8vfO/D5/4QilCtOO8SUZsAaLrNjn5o KP4RpOst6zwd3nHslUEMsXE99n7pytqo9a/+Bnq7bD49+ZoiY7yGXWHM+asEPG9L1qj7rXMJXnjg CPykgqcVQH1BBh5EACPu8xSZg+9smF5MZvrdbekOplZkG+krjo2igJTArknsuKxhGYXR1fOIskq+ CDi9GnPX4UCX1zDLTa7rygvEE+/Ig5HU1I3CSBeNROOpemrYj5PnDqfTQ6KM8Jfyd1VLy9lQBeTr fDH6MiaQXAdQvm0hZYXF58JJGIXsCmx8TxveEgWGNDfYfqx6JbaOZSPtpQjnxjF21z3QVdGGonU0 +GLC0pzMhvCJNeyW1ZNnLzpRGCh+VjYc951lJZU61IsyESgqI2sUtXV8gowbwEtlOZBaodHcDK3Y Ap5NR/Mc4qHiNyOKm8eoMWR8ct66wgkQs+acjD1/llhgQFTO0gKXPyxwOZQVBOslB25NgS8ZE6Lm 8l0xARFqLb15vtj5sbfYuLACBuxtn52uYfHpTgau87AqjfsuguzMkXypAszs31TN5JGJH2EM0sHZ kF4526uPJbhahjoabJTA6B2CbBwZCKn6Y3rNzjDdOzgTjbyZHcb++TD8LPMEIMSlIgQ2WDjvFG6D w+OXxD88hkRsMh+4c8wJmrwqtA9fi0Cus2g03a3TVM9Ri42zSNf7g4b2QTFBmSP8oSBLNp+w4IWA zYdp5REPHmZVs2C1HRYKsqNeC4GbXPY8vfUDU84CHgCer3SwgLZ9komZ+7ZUeIM317LLMH4BZAl0 Q5J66I7hkLqa76c7BkEWgzioLKwes6i5YKcR62UmHjf9asEe4YFLWzHXXT//jwPTtwG7XwJX50BJ bWTUO3xhoAbUr4WBNCOTlU333JxWAK/VehfiP4aAwpxF2tSrpgP9HR+/n6nfpTIMzugOerEOEbgP 5HJBwPm3obZjAc+4/qc1Bsyw+EfJelSXW3hRhwyTJwRE4PcIxhO0W+5xpG94YSkQENduTz2yA8s0 gewp2wmR6Dq7HrVQ+Mp4JzBXvgJ+7IeJYWBUh1BWBFEpsa3Oy8Z77g2vVSOewQwF9+UJgJiZ6XPg l/AGCfv+vBkRroN9stlUk4SPKLMfZRN4PDiwWe5Ov1IZJz5q7Y6pFGnCQFDhwctkSmrRVCoxpglh +sqtIy7nVpi92pbsgCc6uIfiLIogvvnxdMqfjpmFZrrmNwaFXvHOjo34Q9LF9kDubEz2aXTaoJhd NgapGlfMeahuvHvOxUrwyv4A/TC0MxWC8pTw986BvS8SCEDvoy8N0u8P9RrNQioXD/kM1r2qIikO ANgI/uqT5sISvdpzSqZeALWH5G+E2UUTG0E9qZ8ApjIGxhRJmdwHdZrsODqSzKqnlLK+JIa8rSsk +wO9PZYbK7HGn7qVzuE4QeS3wUegyhwl/6FpcMds3109zmDmSmLe6sXVL9JFa5lxiQDpmF1mwofG JtDyp9rb6pgmXKJ3d5rxDFvI/9tbxmZPjpPJi+GjFHDBhRfQkIyDtcaWAgkyDQevlnDVYs8qzQEU QpN5ST1pQ1TQYx/yrAeNDauFbKCP5Qa/JW6AB7qcILsOxnvDrjKc3PeURyznIrTDQH9c6iJVM0uM aPypMsOaltjcKgDvRSIRR4O3LaA2t1+fHThxMOK5T+HPtnSHcZmrA6sf0/u9aTDLn9sEnmcllZqX NjY7frEH2vWqGKfQ04cEjZ54N0BrvnBaoH07qcEyqYeiQNH+2KG5stItBRxQKeNzttSJKCgHEeIs J5vWZia60mB2xxuzXzpwK5IDHYnSuIl3qATlBuNsdfsvpONwBRsHbgsoqHoW128TKLK4LOkKcTPk 8lpcJL1KQ7MmFtlXPxpqPOJ66XBlo/HGOkhQMKIE3xez1qiMOHC7yckzrEdmncjbyHlBuU+0Ywfv 5UOQHQQxYbfF9wV/HLPruV9ziUZBQwZ7aWOayqONeoJTcnAGHwswBhhONIeaSCx9M3Jke4lkueNe 9hDcUp2kC9isjlfMQk8lRQQZXM58OjfBjlrO7g1k5A13yAgqIhLUl0iARPuAexeMnuvZqeZxVbqR WL/zqFoaCATxBvfexBrF9X8yJrOJhxYfd+gJyWVMKiUKYqpWcKzUZNNl3xzybX1NmUSOY2PO78N7 4PtVWaVaM4Nlx6Cku/idh5BvtkHWEfRV9ERKX7iebLWFE6gqK10mO/dQhjAvISnY+M+7o0aHoOod ziL/jyzFdk4aXXYiU5QBer6n4bw3s5atPzK4LZxyv25zqSg8PJoBEpohFCVvFNGoR6CLPjiK4QNV GqOJwa506okH/K4/p5s2c+P5lt6KnMknQ+0BPc9OXaWhblzifsV8QMa+wej7qPQ4zyxq3ZkAWVEi wbpGU3RH7yBfNCCwQdqgmQOajjs7DvdIcDGKi2b5k6B3ap3KFngC8tfHwLlFPjuVj/PvLiI78sy5 h9RgDhVphD7El7Vmw/krle2kuhBVtQUkoGWhvTu0/+HMsmkM/M52EKIpZ+ZFywv/2nspffWchbBP dJJeEjOsQu23+4r7krXkO28uqSNldbkvXyKRQrR/uyPvOZjRE7eupjVzs4RBdstJeNj/F5w7hx+s ducRl3LUINe9RXpGZmWpOZskidupukx2SEeWtGof0OsHw5PzKBtExMv1+fw17JG5Bm/TEOW0VfVT TmlhkEtCq8UhyFAWKS62STE/EDTrPwGF/zqRP4c3lGb0lvjvzApo8tHaVRcHXbAp2Zu5n3070cP/ K8oHysVK6vIiMyQfIhZgoncoDalG2CMDtSh9IiTLy3NryUjVkd8WO+g++oEGiaPjhIgQD2p39G8X qBYSe1cExQSFU4UCjkqkFuFD3UpqM6paoGcbnhNtjm5mjEUYDKgdxyv8sGutk3GSAncShY59aO/I 4PTuq394mXmPpYtiPRWr6oTsIugwXk9lWnk1aedjAzV0muzSDnnXxFFMRCKm6po9yR7fTliSDrKG slqISMzTSyALJYLWeZgJ0c6JbrwfM3pxUoFlfzbMn7Xefp75ZCL8KZTQu10OTnj5xjO97N5PwZPB rbnE292YxdYNNPnnCBO0GRnNNmtZliTeiE8TP3TkqZOh9nHTA6KJegoPH1rCjykNc0NJDcdKqQmo nfBGtPpiOkSpt51LKVP966JEtSy1a3qgJr+yhHY+7U8y544/ABlINkuZfeAB6AX7iSBonuze7pOw 17JpAZR464rhmFowIQ2aEcfvPFvtPqq3DkfbGib6vVOcaMmhKWYqwI31if7FOeq1oL6mc1rjP+gn qgT6epI5/nNDqhciljFwjAneB3abdz+Ul36ZfKVdqEtODnaNRxolaFH3N0HObrEV2oki4wpqnJqo BmqjnRVE80q2zersYN1g1/nZHjRTp04bIu9OeXkvTt4YHSWj0d4813VZgaJn1fxjvcS/qM6hFXVO jFuK156nikaPXm8iXyGxVu4WZL6jFf+v73aj0ruRpMUXFwXGy/BVR0+BabXz6lXTrChd5PZB9dsW s7qggfrv1XBTwRQhcTy+zci+IlthGyDGRVqdQcvjt4IIbQnVhybxQoKCKnVBvWGAzllMZt9LuCBz 0xOVV4Bccp+5No44TW7ZBXC8cusir4m9CSRcSdnOxAUJiHJD7wJtukrsJKBYbVx21F+RekG5IBvH 8I9nexCRk6/A4sLcTgSK8Oh/m2CNbcCiz9RS9WftSIzRyZcHXy9+ymOO40Vx8a/kaETUnqTVbV52 lRR1sZLLjb1xEpinF/cGVV9XbcspY8DuakFVWeet82vUxqvBvHqRVIRn8gdgpnvGiCU5v7pR8rhz WxqRCSxzezvFEgj0GffbeNtnle9YgsGGgz8o5r/GhCsExm3axHIRW5EGNUBc9raoscOl6LJD7fnL Xtjz1p6hB0KKTdqlPjA8LKAIerIxEXWnWgW2RT6Ii0QDH9L+DSFQeuLGqA/QBWNW+uKCpjgA8ZZy KRcij8aBHeLUUaMbdfqu2m75UgvqILqrB5/izRWchQ3l0PZeeKyQL4cUdOhplQSDEXntWSkBRSdT XFj7rSxDH5r4u+dalcpFJt95x6Q8jyqpyLpqIHTUsdo/cEJwrLdzzZjyACeHVyVa5SQhuAyC1eDf aLSItDIo0100DlqmF9rd7VVlXaBE2v8F8QutaAq6jmxedh7U6CT0a9G7DJGHTxxVwnbmFg1jKD3H oZypoUPzTEMOwDLk5SYRvMKqyUkRltay07ErFNXQmkvPxEDJF6JQqLmcJMGkdZOdzDmsZs89UTh+ D2bBE+IvPDwcp/Osvr9KkytJBkPEpisnaUFzvldfj60OAMH1I2F8f+olJRNUpUsZLJzg7uYErR6q +rbv0YY9hpq9Hv7Pb/NrcGnZ40THSNQ46Vj78WqRhM8U/gQr7nIgdQMAzzfOAOm1ObH/+7hitNJQ btXO9CK/N6MoJPpkw+WX+QOv9IJE2WV6jbeDfwb8B+mSKLDAO7VVntaBcleTqlrT8wg0ADcWfiyN 9oErbWMz/k6xVQ17id8l7AOpnpodrleKtfB7upvpMQ7ZTtNqW+1+ER3souJw89QBiYJZDkvXttjD tYVvQHl/Wqst7rgvrZA6w1zvhRiCBro6NR+PJiCda82qdpIdvcK/Dre5EJvCoilGDOuvMoLLVbtw 5RE2HLHcMyWz4jFmx/selTfVE1qJ6w6DVODNscMtxKyWXD1O38cTsAulOANuHsHACfW7UpwwteBV TeRM3PymbonrYqPWb1PPuq+kD5nKQq0S3F7qZR5mxMHqLEjiKSC6Vac95kJuQsflWOp9o/v4TCno CcbvkrocYzYIFS93kiNWKLatZ1NoGxHifzZzzz6RNq9zfEuhUpu6jV93S9seeK6ImMhiLomC1dgL 1x5QMum535SGRoF7OlNO1rrK4CMIW0auj99UQw3wvAdyXQHR0rcX2ncAJcwO8ZxZJHtXGIgXHgJp rCfseby9a0dwvnkfRwhYotOFwSXCTufHPV2lg/BwXkcGVhKnJwYYT84aaP2GG68iFExbyp0+a79/ tTykpy+6ypMcxr9Ad33+q5Kl9vDYPmGbuYpPIVQeONyVFaZ1o6qhrccL33vWz9T+ii20QJ8qz1Oz EczGJ/IDYWUVaHWOwxo7z4X+hSRPK3L1QP9la1Pd60Ym0l9zE124bbHuqpkg/e/TyVyoDoWvDw9V 6plwo0fw0j2jyWBVOmj44tI+lKt1M1aUXnHeRN91a2tRGVMDq7k4r0OI9dRfjhosMfjC4td1KWwP T9IkhlwuTZqLxIqJadN6eHyJesQ+YqGSEuJPrVOpk0di6vwm3mA101v5FAOMJqGfKU4Gi0L43OY/ ZuSd8a2FgsbnlvbylMoOHv/EL9MWI0mxOb8rl8LTuq67mum/hdyyCRISr3H/3Ywmqp52ntIx6RTn VlS+t5NJcOqmq/cC8ZXtWgD2OgPwDld/aSaVYYstXyohb+PywOcblgW+NgLbC1bit3uSL0Wk71rw m6w+HDBn4MttsMqVGKUKy4mdbSm2yLu3M1qc48MBbznw7cVhxzU+z3fIfgwip4BBZSKj8kYRc3pZ /QjxKKqBc1IX5Ujr+KfEo+8RlXNAgWa2IkggnYs1d7YnQrIJas9WfiuQgVuSzH2/F4yWJHKK7xdq Ar9Jv12+bUSSaQ7NsreW6ANhB/3vs+ABsmTc9T05AuReajxGL+YKuIFO1XQY6ZPc0XLBd2zPIVLT AXhAh6I7HzDh/q1G+F/O0RWbYCLCGhoiHcdys04eLGQkHcsdIC7ei1mNCSQ/067NnDVo1rF0HL9J iaBGvEJtO3q7f01hvv6EgRYiu137gI+ydRlaUjfbu32SrgWaJ5wkbPP37961Vqk3b6NrTQYBOhrD dowI6kVoly5brQC/6Q+AO0y/kzCpcDOg86pdg6rpl/f0ZefVUsCRBtGI81SVlXphfKvg4MYhKMmf vxFm7KB6goh/7fVyaMrnHLunNZ7dbweGXsjxJrzcPM2VP6EpXGa3bYWiGzo1Q+2MlapfLVS6sJTb EWoK0BkASJQVU+beXie0y7qo6KQLb1rTnIRQuY9D52gi1DMl/M/vFbyKz42w5okfi6oecNX2xYET oAbFRtX4Xn/QXh4XcIJ3az9hYBiwMxSNFR3UfA6HN9RdPLyIIoNVV4rQRD1ZdQu5CFCoKMfkt2RJ u44ohAh5QldG2a6BL4G64a1wyTS9MCKxakV03jUq8a5qoaGfP+52PCuUu3Y6+xu36JZ3rUzWihQa Y7C19bpZNzfiCRFZExO7NABPEowbU3ALzzduNoiFqcWdNiJqzCHsAYi9+HGFPdeb3QnYkdFqN3Oo uNkgxuq0ydb1nNCZeulOkFefzt/bjDJYXy+5y1H6pPDC/9kdwlBHiuzk5AcyIpsrSFu6TGpdvHpa OybcO4Kj4qKXJxXcvj3b2Yt6sDHKf/LOxfayiITSMeWg8kTBH5K53hTEMkeX6g1k/7LB2Lc35xA2 uTkqQOPfov6ySWJyZQtQUazFq8bsJxX6ypXaZDRn1HBh7Eh4/ZgRzD8etl4gtr6Y1Hjp+1G7/MZy PkkDWkxDrKqBGbXFsG+PDVVWt0ZGnS4c4PqwoPc36aH83meOKp+W7GYUBttl/G9PcUpZN+6el2ti n2NkAkbxEXfdlyrcEYAAKjp0w+34xxKVacwsHhRLpsQsmtqzUMFSi4ZRw5HeBC9rO4XFH1CNdSpE gr6HXJ/12YXSW3zIVy6nU0o/zpTRgzcCnFbgbId6KIq3GQ71PKG5lKFZ6F26/JcSsmjwrOPNogaY /suU1FtwVzhu5LynJiuy1OxNs3POTcEty+a3cwkqhWuUZJmkaX5N28fPKCOqrVlJJxLr5lAKinGg 21QI2Hz1Kz8D2tkdl9zKsLPGaIyO2yaFGRs1R4lk3jMJ8d6Ho9Q7L2JMOj9HW58NjhacjRT2oyDM pmukG2Uvs+a5nuiIaze9ul4zKvv3dBgCRRAwA1KtKuXuKzT7Q/mPkBLAaM2TcH7H9IHBfpTkH1k9 bN54DtsrkYKNoPIMJLm15sGMpWKukyJZgieTA7qc3IR8/LQplX6gIfeoRnZbeM9LK+9EPZjypvv6 atTMhTtAI8pgrAwcEMPNadhG8LuWdsDRS+VNQJ3sYInC8kXTQAO9S4+boy7Jdwj8R3+Mtes2R2Zg V1Sy/PF7GF9KmCll7f0GVpsUJQeLNg2RoI2cjCaW+m9rGuAvtvQaoz2SqdkWl5zwodXNaie/U3Em Pq9Q+5odK2X+U68yAMe5TG2I9mFvJBrere2bOwsZugfw6mvMfXSTle30jU++33y9YuT5gWofmoNu Gq3VfYPbwoIYvpiQCW1dL5vuSiOwWhesgaxiHfmFkbH7QHNd41fpBMZe7l7zwLIyDsi/5OHmp4sy Ykzur2DPlP48J2N/zXBF+gGm8HyxR/S3WH1aCRyCE4eWXzT8qmjnltJMoNTDxlABaIAJlUd/A+d2 Fz/UzcuWiGDStDBU0yiiRpEgPo0YiCDQuLSpNlveXelpeoRRq8emur4Us1NHHYYj92bMWKS1gHlb RdeN704K7hnpi3kAMcv2JwfIT+GoVq/OU+h0K6vd4dxQhmbmTN4vVw+jUlwDqpHGtHP40IwP8joN 0dms9QdXFsi1zp03wfJBBat0LaCictfe1+/AGGyDFlqoFGJlG+Oc2ZLwA3TJgD/igGbGTE7cZiP3 ND7v6f8AAplgxxErZopQ1jhQ8ESHABoaKf+wNzH9zOTHfw3vQbj38CHXnLnAkhn4FG7H8I51CXog xu4S3ya4mpf/ux+LiSY3wSX5ZHM21YZsyOMQn+VsfHnymsnqY7PAk8YM+XjFZWUrJho9Q+MRLYDK Y2Ar6kwK7nxMldCHQJwqutTAtTTZCju98XkRMdnAre9Ze/So9s3eCEhxsBXux9pSRRiRS3HJhEAu bpCCANvufJi8LYd6snsp/EUwepM47is38DYiJDElVj1J1iAkYkCgssHBHuBrKt9TY3eekAaHSqf0 +R3PAT3v9rDaT3D0W4H4vM76OxzVZOn6KSWK3UO3E7HkCkYKJKmQNGJwplmGTKjfRfNsvj0JjSW7 kAEqJEtU5hrl1waYpKG4WiVahipzDjCGKRf8HsXLyWAT5Qgk4liIYz3eWj40W/ALnwm6o49IkS+m r+91zDixmxXncpmagGQDAMGGsRDp4DdwEymUOxeUfLziGJGzNmW9rSciLBbRhrU6CPU7RVhWPpb2 5s+CAyE3Nrj1MW2yuHk4V5on7x7geBUM17NVBpsHclxOfR55902uGBKo7vFL3418iTubbvY3l22w mdZVtDxg/jsWDzNrwCsyTllVayg0TrvC9+/XTXQTbcow7zdGt5Hk9XKs1v7N9ot5kz7kRXwGGaHl R+aLKLZyY/ok9WJEPzG4G6APYZYrXT9wNS+iFkMoOgYzubKr1ZdIsVv39I157n1CUb/kjjrHN9JD QC3m254O0kfdvJvcMEq7xMISCzjfqxRKa3aEntSBYB6e0nPAU9xRmEtjvXAgzSnubiZxeR3Q0Gp7 bvYDOH8SD4BoA//BAJRBEpg3RYaZvc2ucM0t29Un8dxIv5UJhkQ2+qBFkNEST7tu/+Y1lsdUbvz8 roI88nR76NC8FLvc0E9lXcFCukkQPb0PE2WPSEGoW+j046YPChXp54rw7i8sImOERcQXRKP4NAId DuUK3RUErMrhTZ9ApsllYfFmVAY+kx0GhhqTaNn+5hR5CwJNfgP2Ak+gvBHZPB3P200ReSl1mfZj T4U6HFJIRO9q1p4DlhM4vafXZRXGCXXS3uPM4sXhpiMYnqpmELSc+tUbHF1jtWvgdVdyMghSVCFZ bwFoZijk3z6sSHu8Bhy4mWvAhsgR83VUrVEvgkCq+TZCZ3Olyo2nCvVaGWXdkjJucmJgaWUxooqF dVHtquuYJKaupdzuYamExfoh2fsFf3E0u+Chk6kUDLZIkzrE8zCJmDnkc4YBnD1ly8frCaNIwWjh mMBG7dEK+5JeEiqabsoa4sCVHeJmt4/SZGjQLCjTJt1GkPfop+AFpAKBcUL3CF8MPD0PFhdRIWQk ZpFnkVeU9Ny/St8iyaH6Ff7YA9vfAf8IbJ1OYk3mjHrFc7cBEuJ0oveT4UW8MX9ttQTMdmWzL1AH zNByHwi9VZJy6trd9QoaXcLMugMLLarCGMRsehPedYkYPX28XAYbtMSdmFlf1qrHzLpYmO72zkDW Tm5p7ANW37a9u6cPtp+VBqGXXaig0pl+K19Yw9neTA56ODEoRM4+irfp1jzGC0Gh4TLYHVQly4Aq FjwU+7AtgcWU+h0PCQKK1XPkewJrqWjXsGK36deRo+KlGm/wouEOFSEQCFfYg9/AVklXNWeMBeek ubzKp5JGFvWC06YqIZapE+ShqCFZy2MX7GzgrTXRB9CBS2vJTXB8UXFNlb8Yp1357MhH5xGqHGPs Fg448s0XVm2TBUIy+iSkb8HiaBYawoBdkFYntHmhkZmu0evmfA88tNLCNwtraJTgXcG5ENtB522x MpzwubFa5WdIP37XUHpvPv+SO+3g6xRdv0ifHTxImThd8zjzIuANPWnUdN+JpBorI1Jl90VhZ4aJ AQkdwturFOFo6emPfTfqt9NEInJqViJPlJewDNbtZBr644qDC3bXBlGaRgjtqlkz3rVUmd+kcAYF cRP7Rc0Oh+SMhHktgzOFxWND8+frrtGjLFw8twfKMtA9ixnK18yRFZTFbegS9t8OQORHBX1ElZ3d UGwr5F0wHG9WgwxR4Zsjpibl7eb97kx0a96v+sPCTqKNNJVtVOl+eQhMkyJw7MYeXo2R48dJ42Pd WNk8MavBEnP1UcXm0ceU0o+QKICXVLj3LeZcrLTjB4keKlg8YZTq4E8r6TuwYE1Td4pH4f+TGtpA Z+1YPLd6PZadSGT5+khnEX1JSpqQu6AfescldzSxgtiTGtFB6nLDLcZkh3lHJZsKRNn0fsAK/OfA 39Igp8LbKZoluNF7klTBIJJi5RKawms1HjTsDI4WJkiVs4DVZNq3zNAsTlpYESGTiJZswY9icMm8 IW/zSN63xsEsfxpXV1W9wlm2QQIdQohTGyn7KgNk6wQJ+sQ4usJ8FX6LpqtaD0PHw6PeL8/9Jz/a VKsbwrBcqBUdfpDXluxyrpJKuUOBs1zMKvvUu+dzD+5PRK6sK3lC7xAWDhLckY8vy6dir3yU+zqx XH5ipmzRSVqfnoiLynbOAew44hDynyoeUeqNWVX1FGjuJcQFvBVCXBpXUUykxM9XY+LKiVRgR865 5VXnL3NJRBZOQyWpN6BMFab2bHhnkhHvmaN364XKxHDKB7liaImNSGnEqtyGQ3+rAxYQ4hjx5mwy KqKz5rs/JmiviWXuB9ctY/AA+OtX4OnmfsQ3Cl/DrWzkzUhPv4+3w2QvToaS1FuSkvpgPhd+Zuy1 3dg6yWA0vP+L9BvakCDnKiVToVMqqpRXpwhid/JBO1NQIfm8QaI3aSjGWZYcIPBwprGkHIUX5AK6 bwanKeAyuaO/KY9ehvHQIyneuaEyVTeNSZnG8B6WsjK/tS5+pBgTIxjHEDirK/ZTUq3IekMEoDA1 87T33twLACD9y3LdnUx3+q3uO2/1IpCSl1Rd/GwASFWKxGyR/iMK5YLvnGV4WvP+NEeW+/JoevRu VjlkdXHn4EdsmvizprgriYQuxHPD5FcS04yoHjtJ8JWMi0CTx4sazHOP7PrNJSJJITasgCmO0Bxe ABOH4RYbhr155y0m0ul7S5s4ofD4WojqoZ9O5QVt2CjCLEvZTgbH/GPLfTra6Cqh+oalFJZCLuqw rDvqO7JTNHAgMCAOe3iFNsHNJhGeYoNRcICXrYUNmWIGrqoMOibOBh2haXs3r2MJuenecoX19oTA Q94/znW00kO8bWrBOu4QluMFtjaE5GsqYcLoTdTQWkw/YaSyLTrxEjKPPKtn9yV5S4su9qdYRLt0 1JHwsdifQkPaOciNegb1OPY2Vf2Y34gUloA5rzkjUjLq3RrHJoO1oYP1tT4ONAujz3VbfVE65um9 6hofztEwlH64fCWeXogyGvvMdxFiK2/PMbrIgi0osR5smxsvMNhnWGp1hG9Xyv/Z5v3OasTtzHkR ExKjU09anvxKQwpiMN/uv/Hkd8Djy42rPc5HScJ/qEdZoVBaKRoXF4r/89GWE2ETNX8qnJajLEFM fmqOh1heqt33GWs+tOkYO3QlpqlpVrs07cid7alUPZfAo8DgWATZnDIhbzWI982PDml0E/aTpyra Xdr25u0D1qYl89q22fedsc0gTxBPBiw6FENk2jh1mPJ1X/KLbxbMvdjbOysULfN6NS+CNqW0K199 oP8aM9F376wpaHscs4KQFu+OfFSZ6gr4UjhwwxNpT4oH1p3wCbOS81+tnmNWi8XM3clSK8g5VHur BfYtoFD6rfK2g2B+b4GLx758aSSomnvhADzLLG2grTo0ADAhaFFbFm15elh0FzmObnhrevw0pJGH M0xo/LfTikqoGc1To3wxqQMmh3LdxbGBrMkf8t3+m53Wdpd+Zypw8nby93JzSdENCOSf4B77lLwo ORZGooSYp/k5t2/0PJHcyrFV6OgEQlicVAO/xKTfQknBwNEeyMJxwcrRIRnt2ZbknKGD2/g6IqN3 yBnBWjjVFwToR443ySCEo896xiu3xz7odMqOHcx6lw9gRvNAYh9n+YRwbYTuYKcZ14QYj8QCoI1a 4p0GeYoPTBV2oZv5lV9LSYhfmRffCxCcEUKJoHDaQVPx5OgCt9bPFTyS4R2LVd8cBuhcziJoDybo OeOsaxa57THClwqAYKG/+AiMbIkNlxnoPvgsZlR4oYiwDtIrHa0hC6EexXPvNMIgnI67NSKvvP3N lxqiVx+ywe+QtQLuIrZp9AJNybCYsSTg7vGl1ZrrdbN6Fiscjql7sgZySeJVRfaOhDwYUg55Kxek nfQaAk0xoD52TLnoOdP0ipwhn6yBwgTZDxh7yGj1tnJsPlwLKU976CFbqoaWZxxKhv0Yu8HMEgCN x3n4XPICYNCAVHMyrmvO60jjQ8jXwep2dG3gEhehry+MCDEBshgjWDP2SY0YgyZ6oYQ1oFiW9csu 5tlO8UIDOTkv6TUCR5tqnzpCdH0N7FyBEiUupC3QHqo0i3ofmfasSy0hjzkpq3YLwFQZehaJfXlD 2QjLoBUf0MxwKvx2/jLQoyorL+9xxSmXOS2x3864hFLScOpT3WNxM4PcrUwlP5onPdDI5mGjDiAL itxKeMruW1RY5a0XpDk9bXQw5errKJ47+y+XnVdsG0C2THf9xZxClnTSuab6MU8gzeNIcdHaVXdk WCBXwdi5AOcyPr83jRaPnR7dyM5qgAolESzAjyD9V3bJREdn2YtkXpHuTQNA3C9sdF+Y2NCfYqko A9dmHjdR1S+efQN/Y3oITYqQRo2YymEPLwj4AnwIQp99HMa5TUqAkiEe5asT1WO9T7WUj/WP1rMF EFGp9hHT4vKmtrFKUiXBGhokXzrITjPLyPC1PTMpxxN7cLGWhDG38B3uB8tDOJNcz+vf1/GLPvNo pp9bY9UyhidI2VCz4VKljOlGO0nYynpbPU+vGZBGEqmW8lSfVIGosWczXnXKAruhVjCv3Q7MoNvW nQszw/bPGYPHSnttEFSnh+FwK5aUyDBSUTm97xhwqspI9bdUoSLrLi+5BDJ7unriAUasrVIzf6kV 4uUyqmkfHG0KVPqYXPvrbN1SjYC7bP1IB0EJxLQSQTdF+UPWSygGF7W3mW9mDSl/wAw/8Vl3EC1w LSQh1Uw3UHwkNt0S3Az5oxncCqX/JJ83iQZPHgaEfGvYWIRkbIWPGKZ1zjyGtOT9TIXF4TVLJboF MQBbGeZovA5W4xkT2+VccptLwDYWdLmqDKRrrQ0YbOQCGom1y+sU77YHgSB7sme2E/WlWaLKiphm vMzyAU9SgqpaYgf1EZVk6V5KPOIK4sIFES3x6ZjcTu5I5zwfwyOnd/cp5YsrDHT1LesX4Cbrxni/ Q/VAEimrDXicb90BgcqbMvVhDIN0wV4rMqO/CZXyyHRObtLdVR4G8gof+gI06EwUCWuE4UIv6ooc sgRQxtAvplVWgwR7NJtZJaoB8130zognnIU5o/8se5+8dEwLVMNe7+IcKNlyp8FIjLghSpwa38D4 MQ5Pv4gIrHch3nLUP8YL7Zary93uleAF8M0h1CwaMTGjbPdp12BVA+J7krexlrkzbOButG5uWxy0 9LXR0Zyp7W0PcBKCNww+X4Rnv7Vz/m3XHM1TgpcIUkChhD442AzV/2QUi81O9hoTpeveBzuOENdt qz+yOf0OeF4StpDqfBUTUlyUo8ZhAuFdfvxGYMqziooW1j1Kw9oNGcZzHmQ/C6KsqsQECtDyetBU kg/GcBLn4d7xMxZL52w3N6ICAmxu2YcFFONslWX8YbmGhUfndQf7TCy+Nw5xfC2+WXJ19oHkongX 8qGv0sKkizNztPuMob7U7m4h26PEF6dyyLKAxoDBcEnkkhx9F0DLMp0bRH1MT0XLcGsRtmYxiIJ/ Nz3coQE0iKArSJx840xNnD/Ym2ZCaWfIAmp6huCq4dKVVtfkJJFgY7V9DV5baS30AuX5fHVjAGS8 FRee8EyIl2lEEc9Je2+8RCQYn1+abYX9XzQv3vUDQgjOxhhHxfZkDG8hZeumcbCAS+rGyRe9SL/c lVnnJ9yis67Y/3KVsg7Q4o9eyCgtnOdQ0lrDT6JdTu1cNFVPgPsfHquysZIIul9mRxO6wOzbDxKN 9Kf9PIMYhdW4qjMb1uorRUw6zlHzREBqDg7hw2qzHXmJlAcbeQN8vBqrSAL/nwFzh1ryK+PhHAZl F4EQNFROWudHp6ArNqxl2GOO0hPyui18iFH+tSzgbcRr+rOI459E/bdkYlyyxgYqsCQR5DhNazNo RIo9wJT7WnvhAD72P0mWAsKHXmRgkCtfzAZcjmBY+b+3cZ/XYpfBkM98UBiEC2IzqvvcEFSOK0F0 9zZfNquJ4JE+QdKZKIWoNqckk3aUsK0JPyBmhrRUIHrb6zLqqucFEfsCZnnAu2UWF38FVFeY6FN7 MYGB26d0jL1c/2qtRHFC3T16aUanLHfM2TmCZ14HEfzvM+TBApnFJCAYNtpK1WgsSgb8gILJPH5X M8HlkBoG6uyQTCfog7PgyiB0uxzS/UoAC9xQAQYiABF9tgrU027bW7ox7s2c4ubYdNYFy8oK98M+ mHOpQWg/0QVPPEqw490295de/1gsufGuDqFb9eW+p2DsP5ICJ3I3fxNKicw/Id7UAI9KqsuF2VxY HpY34ioyx3YSp+ydekSFGTjbhMD1POzOXi9SdSqtC0JQUcsAXDYeBq2XN+t7ReHMhE841afFLP3p o48gV04WJiniOwrzYzN7Drp0qGlfrWGQv9nWZ+RKGo++Pnl6hF/bIaLgGoEI8IVAoh1FJVtqhBdk mbcT86Xjc8bv3CK3KfLhoYbMfvhj1/nalij9w49Q2qTZQRrEyGeNJf9222I/6EpW0buKiLHOb9so puRL39BILrUUu6OYIuwdT3Vmkr+FSSJW2MmWNVWCOo1gz9aOe8MZWePAnlbLUDSEM7gmX3pLjbRQ C4/WG2ymiudxsuKb7UoRphZ+sR0ofPxCspOTaTm9qbnvYZgyLTlVt0jd735BPQYsUHm4R47Hybug FfCAohzRVHbUx6GEcB4WAVDfwaAEsrL9lDjMwyvdg773qTZKQjl8n5X/xrChIQxzwEVXkx8RG9PE +nolWmjAWmhkVLXCVOnBvekwGKVhngI2ZQpS2Q/PjpUFOMZ+aL84O8wWDueIHKdZqWYe/mnpXx85 cMabxBM1QvLKpA2likXicGeuuzhBlSKfUkAjvK4oSMqmRL9+j6BvIxQK4/zRUitZoxBN9rk1iigh +yRqH6AVEBEjTrFybVjzVpSUAvBbbgF5bE7laQnqTzsItQKTQy+Ej8q4GIeVDszZeXa/D46i/Ir9 cc0aqXjCFHlG85Rqr3CRa8RCNUvy0Cg72eFr1NkwH1cJc1AgglKiCe+NR9Fquk340qOCLVINxMmC +qHCEDl8az4QVXR7YNk35kxTwpMfLYmoLw16F8wpRSVlWb9eq7JCRYbQcdjxMD/e3FHAz/naHyfP s71fkGV7JQr6mEeGdrE/iIczk9noIlxsE0pP2N/AYfYaqD7HPFycAqC+DGIsoOd5IfyCA97lQlxP 8pQx89xHEFtnPb8Su1/wKop8pcukr3wHXSP5i0CpNmOwoHnhM+j66raq4eVrx5BxdoIYdYu6RpJG F13+hy5rPZsCHWhYn3zgNnIKxYRmwyTe44UoEFN1pRYQFMi0DROP9FUBiZaC4wwhqrNzotojIQnS m04VWWO8wft8FELtULwPEQEYMvYpuhr/ykA6c+igGGeBt0E1CRZZ6yVcQ7S09y3TVy1bhr4dGfkL kn8QgO4VY0EWqHxG5GC49XJGINAnICMn01Qmizh+uR07FiiRY0fvsyPFf6PG8arkZV1nGF6vpsye +bw6hz+Po+Zf8iPh1BPT5Mebv8/6RFZY4azKfaduaDFSMMoz+vRaSBu2ilt2jPMxkgJqJOK6g2pq jBwMW8G1n5DnWm4Km6WcTG9z8A78fuODvadM4l+h5Kqmp0Q3OkN5dhhu3cb5TACXJHMHd9olu1PY ixcJSO0l2X3Ho8WAhf8JSFlNZdAUL7xAWnn4WPKH1tXSNA63qvO492Z1lSQmsC8IjmzTrBG10/T9 PMcZpVeaZElQBuwTZ3QdkTSui1rgaTSWyy3TVmXZ1C/YPTA9qLYKZeu8yhb8EemtKEbUp5xxrj4u kAh3AsSD21Q7YwmzKcgmkMM9pJkkzgNcKGqeZiSwilxymhh21TX21Dw5QEUqJGjVm5+1+BP7j74+ KgcVsbNQ/HZH6UTl2hNzTzNH8e2w5PzYrkjI76Ogd91igKgNTrQHOuiTybqXiVvMVHVT4aXeo70o LGgzPYyxKJ/eHdbwAiMd327HpP3vklhIhUYfGiBTZ2ZP4YjxVCPTCK+vkREE9YM3EtLkG/5Gnc+/ iCYWjd/Xy4KwftF0G30o03RohSljOfyTQWg4T/Wv6V/MWLrrab6a97lfeTwZZzbW/ZxCXxKWO5tE cI9/mRD4iiZnuErGDoQWP/nDiYEqxKRg1veuqMIxb5izxLQxmt+oX6i4lCF/OVQgKsdbmgHk97Ky VNNiRiWz6WTfbJko+rh6P+3Z5hJu2aMBJOLMKjL+KVsf32FhoZm7Rpfv2mIbTeRlj9T0ZIlG7z2W OsGtpgY1XOCCUaGLPDtWvn6pKOyQCoNQ7bJGlHb+wWaaVo2qqr8IWxEJCOWWX0DWlr0Dq1kQfV2L TjwtGtjOu8hs/a4NWWP2FQvsYq+pQ2aYE442faZB4Wk1graqRNzQhmyobUjw4Erap4A1vvxPoczy IMdRBCrAkBHDTS9xn180qN8yDIHXayMWbfz6LZSA5ya5SddophMV4RBkYUHONxAsK2C3k3KxRl4X K9lRHMJrdt8gKROZn+Jpb9OJKWecf31L99K16tx+DWqc7a6EP3ae8Xuw1vjmRhYYh1qQgZMOhekC l2dDqx4yyMvCBziRVNgkNCbO4MIiXR1kV8bfCrLkUl0TZcuJi2B/F2OdLKCNtVH65Hs2r9wjtpZw 9R8vcy9+74bcw0cP+S4VsFQ2zTJWsVOL+lvBdSuB3z1dZUI9VaOYMTbgeHtZGq6mM5yoPc1mVnGE rHJNLE24hkhzKcQKlow+3LjvrdC6OZYrfj5wxN/bKdRXFKHZWgu+GYLsSyYqPjQarHxr19ftoFP3 AxEqr3r3OLKzoJit/h8s/OfbzdnvwPYoAPWb2l9ukEdCoWjMTjP//uB1L/4sXPu8MWdZ3yek0Gql kLtYoqv4OhgstBUxMLion5j4kNJ1eH99TTpFBUbG9OtUUBkB+sqWaE9ZWXFSezTCIy4LQZz2PV2r KUqzueNgDWNJ1I+fqxg6zU0ASOLQ0fIbYskXMkAE4BYWhkDF+tQHwkM3EIwGXtJReg62jjc6GusV ummSdZ/7p9hhYCvU7FTZ4UWjohfKo5z2EFYY+ctxMTaASoIqA/CXXAL5HQMyyCRskpdRDdCcAcI0 cKxGSSKnZQ/b3649UhSO3fki9Jam4URYhdDFDnYeJog8Pq8koMi3Q4X3RnQsHKqafKOS1iCAdDnc 0BYtUUt5HYFpOnYaxWWuxF9X/skXb2aEA+eFQvzZoCUk6qAPTzPcGAzZ0rL0L3i1bCAwgBBlmvHY HlDbahLveg8JMrf50WAwI1jgiY3N7QQQZJeswG0lR25Vgw8iILbvzIupz4uD64aSBD0YcYLAuSSY miTYhzn8pEvhzrvisp07Ux+25lA5OtGL7mkVU5DBCTwn9MUW0VMpI733Rh96ORg+YuVj97lkulFT i52OQq64+NuX34W+FMrmBi0rKltVNwQYocfJ4fQiVb2/TuTWWKXij+mDp+I0iEQdOLtBF8BxkCs7 aD9ZYaM1OR4M5T4IeuyMqs75IrcqfaHG1FMCcxT0lv0LodHpV4OGZZKi2IhsJRyjW1bgePpccdta svy7qyxmJTg+sJYA6F5c0gPFPuuk9fiRymqvZYDDF1zU0dwSJdK73pb91EaFsPQDJVh0C+tzesWU mx75btFESthn7+DPhOfVj35h3Lj0lmx11Bnq5qEgqQYTAmCL9iKJr5XVB4cO2+ecx2GKHadza+TJ HhQ5aJCct+TvKP3CVpBfXBzn6WsowUUvDkexatRkB4RfxUr9mDrI5HVlEka7A2IO6H46Qdkm0Rhu dPgHT96xEPE9hxz7eyEyZuthlFDmldoYpX91BFpqRqXT4r5dGA6fi/uI6J8Iq3z0ggQZaTdqM5cQ IHikKprUCzWobEkbfIzS4d5VAbYgapbCu65TuOD3tvHEHcTCQXkFDXXc7BTeuvwKe4CQaHPSrXbA ajN80nAhUg6YR20MLat4ibn737Mzf/r3f9Qb7nHGk+ISxCfXfa5s8HhNN/pk9B97Hdp/2GrJwg4+ T+xBPkR8LgiF2NdCnylx+O0UHyFT8JDcEJis9P6E1UVW1IIydVjdUaUY0cksfdO9bUd/utzOrgNs tVhMbpgUCZfmL/tj7FWu/lNGSAOI/t9t7CJn7aFR3VMHVPtmnnRi/TwyrFs41P+ro10YL4t5J4Fu nZFxRdFC0rsevIRkg7v8cfdAlsQu3sHwl04jZWGOY4sBqb6atbe0eJlHtlWgvb+8kU0bUvSZersN xdPapCCLucobWFwvhyGPlx9nccygU9YhzlPj7KTtuCtBrqwmJ8nTD8E2Qshkm/OK+zo+loEu2iXd JDLFzCGcTDtfn0rkQAsVnkCY8MkgBrIS0c70KkmkcFIKS1+nRJRGM3KSftMsW08eSiIt274PclRE K48OHVig7VmxLrsB44SLqeEa3LdotbcYxmX9bfYZL850C6EvwhibsW7GReqKmhJ/NjC3wUxDhkCO hCHmJIVG/OPbseLePaqgNlTUd+7EIQ3qFVq4+wNiCS7dBSsmaBtAJSZ3WLclUZaxg3l2PNMKe9oN nKNCLMFgsbe8aMy4Y2AuS3fhG5VpXg+UxJSg+CfAI8Nygw5Yc/WdVj/GYnD0ho615GVyxV8aNiJK OteSJg8muraHxVY79h5EW/YPydxYTOgPdUq+Yb0DkT906J/uGWMtXS4fpzCkiNC1iywu6t3e8XfI K0xxYKwhgBLBMtzhXQf/PZDwiss7gESc3H4QcxDY0VSjbOVP8F2O5fNiZEHOnaVP4zsEgv2w4La4 Ir6WJaNygXHb6JTSFkDmCe/gwkeCrHaRgYwqpV1aCCObpe32CgDLVulnkcpGgGim9M4HI94LVRul baLPDehCmdQt6adaaJgTkTGtTOZRo/v8SSJOuvVe4swlOSbDu1D97gQSdXuAr6XfopuTOM/oetb5 8tclFwQjhFz3wETfT9UERf0ZWBDAdUxxDF4IEb/2f6PoUStNU812bkMfXBdZ0y5kREBDyb1aw+ln oi1lqz9Gfl1LJpVv6Bj+0WOp6JjemlUM50x9rP0c5vlzi7+vcrsMPyODJXUhrAlFTeO69J6N99/9 h5h7mkurCQAWoT90yNfScS6oXfEDgj9uCqFb0YbM0clhMq/0T63A0HbeDmalNt/6zpNvdxzOaKBe VtNP7Ps0q1BHnL1IGEaCtT5BOs043ied4tIY91xk9mRmW4iYD9KJumPfczY3E71FgrDMKy8HAJsq xRAns+aT4WNIZqVsqfaVzYRQ8E+EyW9IYLaBRvP9qG2HncbRascCvJqYuE4q/9/9kq+gRpND1qam yvHlNkwh6HrlUIPEkBFN2RaMA3YC56gL3066YUj0i7VESI1BaLabBCN/hR5eiTCzSzczTF7mEg4x xRX/LFGuIXw4jNYcl+uhw05k5VtX3KCxQkrzG5W7Yh+MeBXGmCaviRF2i3kXUI3FuDDqtNmBF3W4 sQK2fv+hIuUMiiOb8qquc2NbslB67ENha1m5OpqE/llfpOjsQZRw592zKOkSICQhyULjlg1EvEoi /EBNCtkc3WxslEISecVZicw8999lYT/USiK9kZ+Jydbh1w7NsPBTXuL9kdBIz+w+saSYivmoqzm6 nNjg/3fBHSGvC83FalafWvvdA1bCGLv2KNpP0ac4C2OMdEn8K4OIni9ilJUnDPBwls6cP091EsOa BBVNjsl/lxNIoKzMcQiicPIP3drau0bTJ9cKTWRZol8uYA6wHsJvfrUC0ZSrsEZJmh3pDq/IftLB WF+h5U4GFpYcvTkNTuhPNYfKSUDEEJvtUri2cJxMVXk0ja4Bkkp9n5m8swUaomxiccQWoGAGRG6i oKGrBLAkuSWjkwTGyGLNwcaPIKr2Rgk/uotCgmi3vUF4L0bgOAgXXnp5Ns7k22+KUo+A0LTLuKH5 flT1gOZ6MTG6a77jUmz6kvpeFKoe3duTPxUNDlDH2qkcES1SjLDrjiP3KLrGuaPfQ7qehHBPRopv oxSGs7CNqI1+Asu4LrAuW+RSbX6k+HIaQXSnIfkQ3+P39YQEZkYDtdMnndyo5jsBvHUHT+qgNQw3 N/TMAG3XeYlZQTWutlToY6ez1Siqso+x4iFPTggwYVBZ07WFS//RvR3sfQQPqi1RIlcwGwonFK9u ZSFu2MrzVfNSsa/npeOhS9rjPktfNU4iAW8W2E04hC6zg0mvxWNGqZzbofnD2eZkAvBhJ93y2PB+ fvAFowpcriSSBbzHS2RQHyz8Ga9YT9LaOK0BpYAuKAFy+ORR6gPuJ83bplfXDvMPAm6Qn5AAjjY1 +cpuqLGFxByAwL8GaGRmHjM2D56g33YKHnr/nTSSJccIFVM/k75oHls5AXMGd/IujywPFGiO0unE nmND5pATN+Yb0kjS83hXFJVH3fVBvyrcInYqyeVzj+2N6qIeGlOIth8ip+sieAjxgGmooGBvQXex BQUbCID0NsfEsNVyNqsojb1hBtW/d9wwHuEoBfG4JtlzZ2g3efVEu/VVH0Dexyg8NvywIKfe8X6u j5HrHwwMRbAgJMidVSBoY+mYtpkHXlHQDKaWG+grI5eCVN5xO8sKZLVxKi19WfcJI2QjPOcSL86c LUigBWJ+DLCPuLFR07f9qiglZI8dK0Q27HBHnrODs3XwjjKXFUr7z2fmMzv21Vk3PTrgGuTxC9kj S7mxsOBGc+29flT7peeczazgrVpV7n8dYSBNug5haoy663Ku40HgwTJ7XCs7hpQKvxTlwdvkrHm1 M2QQ/38zcB6EgwrlM8bUyNegDeM2UtJsGLD4+0GrwRRq0tuEFsBcZZ1ZKvtHHfzIrUZ+dLCyzm5w NJ2bGIIpPMfHma055Og+6lGzTkxOT2GeDDd7q+6NAQEIq5x/T2fLAI/HNdDkABeykIvbAadGle8Q +gSgA3ta6axgoybjYnFy39s1njrTuKKdxN4YAYHrtR8VWbAWZkBTjhz9Z9sNFXzCJH+8ivOTimLE TEc+/vtp9v4X/cL36RzH1cx+yD9XY74bwvv61zgJizW9dO1gm5eTUZaCbJ57ukxLuQpLxRvoqzmS HNUPbj//g6dh2WT+sEQZmzAc7HfCF5i7r4fTcQRxqXRcv7D3U8Qp8pn/7Rv1zRZ0tKxnkq2DOBVw 3shiCRZx9saQgLPe05qhHiS3Ua5NQISQbe/kX+iXpEigfP2z2LDF/KmPHe8wuOdBchn6i/FgK+Hi mUfeQnnjRukPH+/YNFlpLT5SBnKl5uYFXQKdhaidwzr/pgk5CNXQs4mqwcEfJxUrTnRtMHuNPx4c xBXBrnFEbntJFvyAI79g8woDwvxnrrU2yYhajyUZ6bbzZemoAXQpvsta3Fgj7z0Z12wRHshiHyiZ KoJxnBwpZcXYiXgpSHaNva/wtSOt7wkLkazjcimeLE3EWUg1WJ6/3huxvuhXOa40WCVczeBNpKbJ WkIZcvzbxUE04Gctz+ie4LrQuUb3bUoeR44V/7InMhQN8npepPq32GHSRsiT4Gda9/VFuOVv+4KY 2PfVHGSdtZfqFA1kGh47EQcHl6jBP/Q6Gm+wrRR2y9RG+qOdNig+bXGotKkdIT9BgUMDVv0Wrx7l zcT+pHqy/nGSgVF3gukl7I90gzSdKJl3iKGQw9G4itn3vBLET+98lGg4u8KpAqsXsRpqwd9oF0IR 7/WBTcQr8k954smPj9xuAvdKHbz7eeps14JHfM+SNu0OuEk8oq2RPHgscAryTrPnfLPjxA4v0NHw gxognZbO2fakbnieWVaHJzfhkfV1jpaBwuejpBn2BiVZ+1Y6R/KOmUz9uEtPOPCpdRiPFu/McTz3 esufcLYG4TGjnAEA1Axq/q0Shc5sO+leXL+vauhfTkXUSwoxj0fZjs6ODrux58yH8SBY3wF84joL GL7Ayby+D38Yl//k7TIlIxn8y5esps9vGXvT1TCF/HylLBMSsepvPIuHG6tedN4kPN03q5ftwrXb InDRXAS+BkAqR0ArgmyOcYvEHhz105y2wRS76w5ENeB2yRpc8K+xNlyXN6d48NcYOrBbrnBKvv86 uOL3rFfZspe+34zdPIIvGgDcTRMniJbsOQER95nyblgRnzlneTPpc/tjNhpbcZP1JWMOKeWoQFJX 7tftohLPKGrR3JqalyxwlRhHNIb/aizhdybYX7kr4RjcvxOlWewcE7bzI2zavK/SiEHecdDGCa7m gJnEB0ssQBPsyZT4ZuVhYe+mBU4Qh0e2NaHC7glR7syKcrpm9pPRAug+au+j4bq1i/kEwZcke9jz JF9gp0uNafsaR0KeYkH9K3Jui9GXc6Carzimh7gWKlpVklpDkH2U95zYanxaYEeHWX61gtqI811B kXwr4wA5HejgunWM2Ttef2cneqEJX1nDX3AoRk+5Zd7TcMTCFMJw40Oxh4P7fbK8+zE6WrCpX1u2 KZv9yUWk0oCQnhFx/jEJoeVOtu7QEOAqc2dRgZNDFBkbAmO81pCBSeYW5bNuX5QDzhvZNli1hAqc 8HJYLaa6nw1jNPfou0i2A6Eo5nxqb1zkaPqGSEAfxlg7qNNzj3AtjgwMTG/vVw9z8WVujaaeMvYY jEs579SbczQjwLASmkqXfq7WIGa6RJDcMI+Ip04Ngic7QfYXlwFe2S/HlWK3zpjXoGWsBrm3pMo8 47hbp1PTS7GdQ2IoKleSLM9WHOGxH9BviMODwTZRiewdwqJxZBSaj9G58qfRlU/vH1KC7vP+j5gm CvGfnOvk4kZ0QFI4SOcKL/eb6rgV0YLPDQ0Md2OQOjU0I8bNvYHBS+JDb64ZFqVf20FY5oujulAQ aQMTolMHRgq23oicgdYJ4ntJpZrxEL2ObgjNvL49FhfW/m1uSQmDUlEuYrLlOgssFS7Rx6JLFFf5 pwDprWimwiPQqiKKJz4jfcUu7R9t1JMuY3vuhFSDPCI2ki6JQM1ZEUifucqTMSn81Id0a6IKFiyi ExWC/XTdGsW6wQOZPcA2ImpCt/mBH8wtxVx67n6viYAJpNAA1aiN1Ww/k098+SCdlb/cHQw86sPq vId6IIVVbOOhSX+pJH4DErdrzMIctV2JNEIQQNaT7iPnnI0yoQMN3rvvcEyuAk0F0AaXNxYUb+wv 2SB9jsGKrQIhYXDY96RPUOxlh5m5Tp5nvPQAuXBeVPfQSKabXWVWfKs7yxQyk2nuUHaLUGJLZ69D 7u5ZyjxuzCrAk5RfoYkj1U1lTaFdO6S2mr6FSaVKNOWdeDpsqbpDkztFXrqkuDWaplxBnlG09pFP d7HDlCiMoHh2KULbzuyZly/LiRR0BSLzUpU8V1BN1POIRUrnBAexqPWfpo+qF1K6gZn9cMB6Vm1P VXqApeB4yFZj7ieAl7Z7LGEGzD2QI8+rlWCKQ3t59rbfGSHqEi10A84sMQ1c1mErz7IWBzJzi7ke h7Dn20GOoffkqEzBFxZbLJVZ4y7IQiuZ4guPkTqbO9oHLZfjgzBi1rJKjRYfoLqElwzJEj69xeJ0 sHUwB8QY35sJusR0i9kud0cqY28SoCl2RbtQoTX0Z+iPzIpnD3BEI0xLewVQ3ggmDyZC8gXN3khj a0pZUD9HWET7RQ8Kh0/yNBu5b+GTXzQmslB4jNfOf+oP15WhoqsevEqBSQ/pHKD5A0vjRZrMGmd/ Vwka86BG9VXJmg8P5iKLn3FiLRwxDMvU7OViBEHggr+UfLTM9SZSmji63F3a7qne/iC3uV96QDFU jvzNZ24BjlcvnKrYw2UBI47aq2OxJG1Z2kDP9Seev7vF0g3zfI20REAj1hRw9q3eta5CkFuGCsMQ hFQ5yU1gseLjZ+gLtQHNYIbgqHJWwffkIKj2jFfeH5PGqBuAcEkKfUUB5PpbsoqRyIEFFSAE/lIH lH0WJ4kMkqJXZP9/3fY0kZDDdihtwwElp5v7pB9mzKgB9ZI0aIwVMBSgCqT07cBsZntiju0XTLKk Fl1z1gqCKa4lbZiFCL4RWl+ldN+a+Rhy3uDTPJSec6p/2RV7HXrqA1/ek+SVGLvTl7iUNghcmZpR woYC5r03Lxkie4lylZmMtx872XyyjetW+c2/ReymHt82dr9C7RthEw1zAUfHj3WnvIAZK282DPo7 JQCyW9BL/eDyQQEpMEUowC2TFV8fpZprlr4Skjv4cZV2J7zQtCLa4mG2cdEmu8k3KxGwJRhYTTJO FZD0oOq1uxegCITIc8WO/wO/sipooHLTp+M5DixcAZOz8lLnbo6N4UGpCivlTnIA4wfzHt6H4AbB OgLheMvd1Qi1ClSCXmLFGrUMqlnOdVh7vLTNC0zk63IuYGTlj8Z8onPTVkklifq6GIPlG22pq2K7 8m9jv05VZbEbwhmglsmAoRTxnXyS6lWYLAS77O61NQl1KXCNT7IJZmlrXlElSRIJPr0/cNEbIf9l Q9ci6jxUJwBa9tUji9cLmB9q3jG67FQGl55N8GW1xHmNXWSvBHaZAk31AiacmbOhyWHNTESzEfva abFoP1hbsywLhV4ybmM1QVTjMvjrgAqMZfQdG81u5l8+XhEpCuJJoE4E3N+i5m7H2VuPZ/+VDr+W cV56fkQ0IHowMnTvMasrF6iqM6jEjtRTPl61ex3iWnJL4K6vYo7kbwQDL+O5wx9+t2eiFy2lOnAS oUX4Uu+C7djN8qKrp17p5aaIsEBEaksnQ7Q2r9DHHrAJX287pq6eXgtLws3y1Bo9SvAI4ffVX59D +GJqeQKcKs7TFOMx9aYVgkWu0Cxld2IzXG/9RLK7+vlpu4KnVB8ciFnLRm1A468AeO7w1kxcoYSw p57eSOEvnCAGAjCONZohJn+QwnOXt+QOEQL0pHS11JOr9DW30o/0xt/rBlJe4jjbyhOzxT6SHGJo 9yFVUQdUGZhYHTKnL8VsSL2fYroX8zccL6f5+kGVcHpIlGKqr3Om+fJjUGrVITGqKq6VXPAlK3pY UzpqyA8/zClSo2ZNllGA4siDKjvK6yiQKlY88tcjQO+ackM++ltnmXq4gw4cu3EfQ3B3FK+NGiQj KUEgOUbh0cEzkZ1QtDNGPBtrKR/0rcyqLVecx27Kiup8vlkMylgqHSSylTfxmRvsSe8qUg8C9jn1 AG+mgxNBdvD8FiSqDb4rpCvkoMFCpwAnkH4c/te0m7WD96AVnd/rFbryFXxhEoAxzEoEAhRAaPY+ PMvaIxTeIKa+L9k3y2UHPabF8SrSv7sNSZCoWbd2sifEdjwV/NlrJoICOcr3adRLD8NJNaW9TXyc wVJjH69K9Kd+JFRlCCV4dGeZLk0EF2NBeQltDUK5C5Kozh3qc+Rx86W4TnnAqxoPQO6ntch2hIzu N0p5h6r3meC+DyJSwoxym9sO6lBt2ooPLMnPr4gDDVVgT86SXYKpZ/KTuk6fBU/MfqLMCfPIw7HI nW1hglF/IvGgYIxgLvdRFoLOHOxqb04lRbpVzof7y2mO/qUjwByKMjFAeaQfyZ+wDD+/ZFQYE8/h QXpdN0IRQQDmhCEmIgDP+5B9sR9YfeaTKTYCmpBCKLNGDXwDp7L1/ZYiLlXogOgeoeVWs6r2Ltpw pmjbNB0NmWh1G/MRthqdilKef1KqT/25AZXGsQX5e/iAtRVHnf6WvMeOHQEsOc7xuMDRdP4ESYjG hz7DZ6+vHaqc6hJE9H5GoDkq98fmMNRX345wBFDqboSocbKQ71wM8qRlU6XG49CCenmp3S3EMiQR Txxzd8lrnzhI3eXQsyJQk94nUnNIqUVdsgALzjdp5p0Aoz/L0IBh2UjOE51bKv5tBZcNhYFzMLhm u2GCZY8hQCnMZz63NpY7DULsg4JYBACtOJtGGA9owAgQYGX04N2kxcZsmcISPXul3o9yn7NbctPu y9c0KmM/RcASB0/Lgq9YvOourPAO1dSdIwmulmhNmYWsCA6lG1jKxTXlq0/RkAxN6mmAQI5DLxVZ mSOxDRufeWkeZwNQjSNvSQANfrtGDSS6If7SMZIZa/P8b50d3LnKNf7B3SBvc4xSldCVlWXbf385 hxRE4DelnNLD3tA8ep/IXQDkS1TYhQuNqFrVoHr9Ao4TsJfYIQS6T3v3oeTppPgZr527wQlBssy4 zlZXOOz9Omjno8/u+eU9e5ap+M6JWhvOgSfoqH/cwj/tCT/D/3ROsZTZCK+mc2N5t4pJub6CQOq8 dK/zqTLibzwFcU+gEde2tTHygpbhK2nnSBh+iPQj3mPKbpbPz4i49cz8Ejqg4ZR9qYbhahow95r1 wwdOtbaq034hU3FBhyTJWRO6ChLnTuL+kV3gPxrX/DJ622GwfiYK44DZUKpOKsofsUMROo63NhYP ePi2vAf8jmrXC46l6psbtzzu6kVfLAxlENtNADw7+Zna+lRzg213KGbRwzssPESQpNPrmLIba0vQ wqQeX4lJ0rDOnWgHywS5fZTXXx8nR530VdMyo2PpJ5zAc/OOvcXH7uOWP6zQWsHxxO6LjrfvVXU+ BF1Lu0nNNGNQkYtmWUAqCclUqIPpvb9xk6+144YLBR3tR86C6/LQhjHBNrVLiBL2bOnyCHAMiCPL /3sZDmb7UxSC/CKbBCvRvTbFV2I332E6t5XkK+BMiQL2bfusFqi+G8V0REU65MwSL+d0hzQ2h903 VjWosfdWy0Ex+j3AfNfp2bGvNmSKpjyyxqqGzhZ2OpqfIEKZHw8W21iGGQExpkeGJEa1ZVbh1FZe rCLk4lmuXe3dkdF/nig3JGeIqa49i/F5jbS16zHINUcDH8svks0bMOZytApC8h3quhWWkfTgsajW EW+jDJ9yStOH3V0FCLkMvXnXfdSgfG1mLS8OCLBdv7dsTyQl7lW78MBsq7WKiX7LkRowyGrlbZSh 7x/DWVF22QhMW2MUWsbIZgj9IKYizQYhMfsfPcqiaHDofRlahQBEbDjFhVRRWfUgC1FRM0mwLp7n VSbeOzxRA+PrVKAin1+/88/Q2VeQSmoY48chZWVLVe3aw6pGvbrUk2UPdU9MkqEbr0jiNum73kr2 7Wh2EdmJMU5OVz6CThANmo+FCuI6lEiz5VD15Bcdp/Ekr1l9inYFFF/k48KpnzE4O5OObo/K5W14 6HgR8+c/hiO2jQc+PQ7q3zFXM9Npk/7Oev5xxQ//p433qfTHF/M7JUGko/NFYlg4/tFV1GLCs2lF Bv2UhoTnHCzZjuxTYiJjjF4bGZ3Q4QdAEnnwhigB/1I3bs8YQg/F62SMNMZe3QlJPOhB+kc/+XlS Qp/e6mn+SEz+ECRjLxusDMMt69F8BP6qYugK9W1m3MGnlZqTtsNVd6MrOeQ7TMSoYd/DF0JCf4Bz d+yJgCWS7lc/DlNLdy8LhjtEa1ipmVdk/CkuyLuc7q5aqj2VbzOwo//g03qyGm8Zc6wGhhZS/VtJ mMcbXVaWQCT9Exuud24MUcarLqRH4TGhgdGlu/h3b3ZwSzjqTV963vOxRfQ9EKU1VkSZm0Ky22MA e9Z77IlJDTkqaqxxMWvXD1V0b46OuhM3FCwR3fjmzbLzuZTx7sk2a6uIPlgOA8ibxAJo+O3CtmRB 8RO9138VSip2fo51Om5lgIHiT52O5GyQ5XczWXgK4qhZKU2xW6mkh+StG8leCR+Sr1dW9LbUW0Jg AdA7orxQJ2hjrGjO6Q2UiGb1btt48emu655nohtufWwTv/x+fFXDZkJ0VwrREzjrc2IRnn1F821n 7QjinobQ5z659/s/Jk5f26E4C67pb+ShH3c34mhGASwUv1Cxi9ESbiEgrzN4+JLgrCTPlHrO1BxQ h0ODHY90USUzXfzt3151Nvci1sRpPKW7nthoDe5Axfz6RhdxAEj5ECku1i03HNJKLeRUmmynV2OC PTVzOpBU4VbdGCRrzNpQKJPA75ww+ZLo3MnTp++GF1toU6GY1u5na5S+iNpJA0N7GJFM7RuKtTg3 gUB00Ak3BnQKWwMzJCU1bKLgzDmrDD6cYOxjWNw/gvagBqyDN9HpIAu3qz6EZ7w7Eo88Ifr+KOvO QjZTkDC8RY4etI58Eydld6AiGNIuLxO7KcSmeGoULODGxox0nUkorV1jQTp/J3Vids5TOgr2zN4V PXvfFIFNqYsf4dI2rrtk5dCJX6h64ARixQQOqRHd2bLsLoe4sjShwmSGjksxp/j7XVsTGgC+V6pa UrGRuJRgorw8gouc4ZvlC60drWpjHpTrkBByAy2j8rsONDHj9f30btV8cn6cTlGV+F6bfI69HFYv adbbrtovicsVU5B5N2bFcLqZ8xS8LoYwNHcAD4jUsw+kSef0kXMZJu9/wAsND1kUYU1pyYom7s2Q sZTsVPYXTyODfTNMnJGiFMxlYUj3XS4IdEsGXf7KMvJnXGJrFzxdFw8TX/m56OfIUWDhZdvi0MiP 8SbZRVxQcbT0PynJAweGSnX43DbNEiXj5rHa6Tk6NwaLXXC0YZJ63j7evuCWB85dH0vys4T3OL5e BuuYznnvphzBT5E8GLAK70WUXaGLq9IOGd6x+u77rz0n3LEHvIipv6MjtrzqRtsTC46oQc66ss6W U7gmF5M18/y9NE0MqQ6csNOTlqPgFlWpAGNzG4ZFQ3/bjcBFfcNh3IZlTByvyna0GQ1HaJz9vspg 7ZArYBYThdWFzsWbRhB2b+VCHQjE8t/hlaqxOqG4Ki3BO0yVwFsDhvykHt5Eov+QD0CLiT2n/tWA uIJSf3sYnDaXBS5HIGx4+DCORXsufrML+Ad8Oueq3Sus8ES5KS14+DT8sWCIEUmdn0BR/+PrbXOO dMPRoAY6wPgF+KDB54nyTKxM0wQO9L7kIJ2Gpg2adNLGcmz//97PaVAMWyT9pmOSg1uWCYk769L7 uhKvuNFzV7R9tNlb9JR7Tjms7lxDOyZtqBVz8PjtrIXdHkwKxvtq4iE0MlJIeZLsrGOPMESRfsot 9FDGxwo+Zk3FEzPKGYrnfdD6rjTS6gCy1zS5dfawgtf5VGBc3keeBXuioezR1qt/8bKOHwp6RStA osI97UJtIm991v7DOLOgUMYuEw6M/lnl5viD2dc54pVPOjIFFeiLJboaVFb27VEhZMVAPk6Z8mcJ BtOimVHJtNVXxUuww7figqpYiFXlvR/ZDfm5FfcBRa0unVLAGQhiu3FaExsrixwqRx7bkl4ciCB1 LUW8kuNoX3dHucBeU6iu+lcWUoOKfsDi+EHxXWAbti45P7MPGUi0pVisZ++32tp3x5nWyCnUnnv9 WdfjtfuU+I+4DG3HI3885pNGqOKSg8PG8PpAAHC5NBpFQ/aOTmrt2xKbCK9kO943Q1OMXnE589cY hKIdiZ4Zq9NOoQWfq6RA5XyXIW0zvpBJks7r70XROmv/Ts56t0hfIqElsRdZjnRq+gRRppqGfBhs j9ro1wWrN9awml8hB9nIzhmDwS3Boj0wlX1TOnGhXg3mNKvx9Uo58sRlTrAktmgSnxau46iSc2gk dGA4gmSgwivvQSs2qdoAWGPm9HRiJaYsQ/2FAtvkgHtEoHvWh/YSGRgSAFcPrQurnAGRrEeIaquq p3rvcM9tBB8ViIjsSst+MGnjUovdJ7ZzQxGYYdp25iX3pFalm9ehZArkFhrEUZBGZ+/WZ3Y3y4mW LldJAxR7tmujyEtcniYehuEKwDR4zc5owCk7VMEUwooOvlhzcy0I+gmMBn+DEbAI7KYrwmTl8t1n k1Oye3MYm5+aLdK6bv/k0nRJM3CmjcCzLRQzjsmCB0AiY6qvY/5z2Ih2Xqoq/+clyVR0Wa0o1/M1 fgYe/mOvYAhEOj80uBckVVSdS245NzRk4JWEPuGr5nCLxqxIG5u2Kte4eod7gKh5S9im/NIJj4e8 iAR2JVmEUL38EpmF6BpcomI+izUQ6ZSl0cotNapsoDURTrh11a3SOxH8ZJDpj7Pqs68QoPOk6czi l9Z8M1jYy2Nxi9kPMLyeOGuC6Z/Z8ofLQ77KfnTvw4HfM2iD35SkLbabxYg+5Z6csevb+SL9Cdpv bR4A8MhzVXF73lajXjXMmiBvFB2KdAb+bR4Z3OAZnDfnHLjN5XL5mCFUPAIG0L9P4BUzE/aeX3iu /VemicNaPpicBULphf/gDXY23YEtr/OI3b4OVuIvSRXQ/T+a4mEH/bsAyc2COEIdknu51Bpw6PVk cVBcLBOo1VSfqA2n7/VFJpswRnCOjqRP0HUzF9+t5ldeUf7rXbjl54OaHiwImPJPDNl5vIubR3uf SMuwl0qicVUuYIWOcTphtgWkIO+qhUOKTf/TfGhhv1rZAZYuC9iydfZT7stR5xHmoeZNJaaL8Qio rLUrVqIWeOxdz4pjWd/0OfqgSG0E7TNJQpEb3wo/IFMWr38WNk2VpEOoyuK5BreCeyqgO7rr9VET nhQVCPNL3vfkhaHi58R7i4X/vjL9tAoOqOdqEHJL99HU0t+BaB7O44ymUHC4lJnXb8Lv+h879XHT YlHe25IuanWXUol6RDCGh2QvgKxH2sMx3pCDRXVlG4+R9NzqUCpTIgkRcxHH5d+bv50oOl3/KChz spG6FVckfq3VGh3L0k/YmCxUzfhNqHcIlRxUYnihFZY75+8DzvnN9sE0UvQ+1JaCpSBUpe5yrLXZ Gm5rBY1f/1ewUKoOJPFW1RQPXQdcQqGoGqGz08NwQDKIINtkenkSRqPtVrZy+qr4DpaOAM7q+EKR LrS3AhTlLRDvYU/Be4jVbr/Dw/bfpfGAIKPfCOLGG9MCuuiKo59Nb7oyNm4jNRM3dDgFZg1rsNL4 IQiCFBj7pREUjzUGnDP0SXil6x2o40cegW+fS+rh2SfTFjRF0rH/xdW3SzxlDGw4ATITDU0pv9RM 3k2F+qaiyXDqq44dN3DLRLpfTbNRzzg4fwsd/crUKypAnnSS+tY8MD5d21oSAfv/7jiJNs6gasLa MPPRo5JiiigNWVoP0ndehIiXYPbyRv7K5Aro7GrIpe2p7f911/U+TWB29GG3yobpVrVhPSdkTaQn SRBNeFof26A6YGXn4oIOspVllmDqkgohuNhR5H77Vt+khGU9poHBwDiKAy1IaG4rraXmux4iSpLI EzzVy8LNW1UOV8uV/oQuVGqO0OqTU/370wH575Qq/mGT8H7bwm/LYIAEs1wFbvDddfs0QA1TjEzF 65nfim1iGp2WnWZPVcCZnwaUuvXvw+5d3UW5yYprmlfkGy8xlpB8nnbrfGT51j1tIA/vpDvgYk4u sZVsEOyH0YEujPl14gGKeFU99ms/Ncq0P24byH4XpynsqVFoLXLy/W0O4AF6fICEljbT/7HE237y jJiqREuVYLx+QJ2opvjPq4vqU1jMHygq9dGiGvaTO8qol8EyPOo6AgxkgNohu2RTlMR+TYCrcCFT Gq7DHK7APe3EPtchs/DjqNqY9rO+Q2t/7uAVHZjUC/l3GKrG9AYyggSpmeKfsDvfAd5QZmZm+Qys swkA3W7/9Hsks61rapFPYPp+6IRKMNKSZW/txcnA3czWTqNPx6ww91Uo419Hwze19JurEhWBy0rz BVw0BA4VX+9+bJC1j3oj3rhBeCK8/Bwgf371MrSeVX6gnz0Q1S40ricfz8ou5B+8pmJUlRdT2T+0 lqvaWFRD2nHt1rltHHlZpUrtW7+KPAYVwgjfFD6UNdDqShYn0a4fiY1+kkCxuM5xDO1sPB/3aJeP gxyB9UztEuy4hMRWdaQrGwOYtRfiVDyYHKn+Hohfubpi9nWlsPNmwMl+1qafG2g7BfIHdhP2kzxS 2wW0RycmpOu5BBSWyCe9paC5o3lc6L6IbCLFwZrLjfU1tFcWT0wuAs3LliUG3ne8lw37SVKrlqM9 d4d5S7DLDraaZ6/F94F21vpE/7uH1SFi5rF7yc42kDJCSurQyCxkmVrm2rt3KFju32swco7cJNV5 kclx7d0CStoqFXytNkOqzoDvM5yUH7EyRiW1usfLDR6M7TawZOZFh+fFftrjo4qfR0h4vYZkg92v WHiFHhqd/RvFoVIc4rQQGXncyZDAlMgzZVVk34JMu5BZEz58we9eKUdWCzNgI6UnwoymwadXTN0l NMxP8tm0DT0c6sr7X86HMJtp26OJWR1/k9j7ybkb1vnhbBXZP5OddOO6PhT7QOyY1505Fm92YPwc 5qsBLQ/gKUwXoxIUZkMjbLrhGlDSWp9+1QCouXcKmd3akbW/GL438B69p11KsZwoxND5+leheP6A PM65rPUTgxMjMUVeGfqGD0sUFqGO1bhkymA8ornPoPsY7p3bwn0YVnn7GZAyY/LKrcs2KFZ2IGxn 0n+noLBQ5NPg4sLqq8KLO9o941ydHrtlFNw/5cZDBLeLRM7UL9fYYSNx5P44uJEGzpvET8hd51WV R65OYMBMVt+9tY/xP9Q2iZwnL2LFa0srdjUQ3+Y6nmg1VuPaJ5U+YyNN8Yeys0g/XKI7Za+IfW/7 VjgA+82xflB6yUoR6CVQfOPyZssdsamMPWMtZyMpRasPYY3e4tzRdGcLyeU7ErQZuEAtJVCut69d 9h5JvVJWj/Vm9U31osVCHgVNyHzemrKQHQaPZ+8BR/byRJGz+/dqQNeFoCq9VBbwHgX5rNOx8s1D eOx36UaEcylgNwCIhHqaU6n/BuOaMopow5QKd6OlmqZejx8VnxcBe8AYylJWu1ADy0BFLVZZEeSa ri7HgfIMTkv6qZz4LOgD2upULvCZWuenfzBBhXAI+tmjxo4hT+ULuy2CiyGS0XIPInMFY6xl/B7s eAwbYIDsq6bB9OqtX6NPXuYjfXhyO+zEvxegTLq9+5XbpmSQzKMWszf8LHFG6h7xphJOmzQbgbZI IdtQMk/rG3VwqPe7DnW3YFlCXh0TtQBghUghFQN2stlnvn0K8rdSNZCJDnkTscCY4RVQZB2k+Bt9 6iVz7W7nWTtW3+ZmiurwKmFjW8hpRqoR3ML25d2XaukIfgG6QRWsj/oR5PAV80FWs97jGoF37s8X ymsOT5526NZTcXLLjU3yeynVSh9IzsNyXIsfTZ5BhVxwlousfmG5tuTaygJzV/KbLFDXXUrzbaWu oGD2tKaorCBtp5Vq0EOcy++/Qr0ymyA0NJvxj1TTQIFC+O3ZfFJGbV41eyh+9nns93OqFGJTV4eh GYpLG46GNj9PH/PcUSUpAL/dJ2zNpLwaHVdSMYkHF25biWh/jDlGIHXMhBJDR/lVP4FAzxyW++lT ukJWYzvEKbidsjgKpX+vDWS1pXRncv9GgJwtOUuM/nxYvXFHb6+VHRB4FgkKdFmPFCA2pAQQT2f8 b2tmVV5ZacWZdRelesMQkLqlZKzI9xONnAAf8ynYSLM/0iSKTQEor8OHno1Ae0UQmKJkuZSSyY/C 4XUyyGGUEd1aCAA132CdaXN985ByiW1B1QsVE4nsETFCtMRNE5YZZhWl5UiTqS70HPmjmAoZvfC0 HGHW5fgwREwVx8eqjEEYDmIKAFEVJMhpciFmMjjLnqays6ESX8QW3BvzeRrOmob3qVpG0i+G+5Xu b/xWglXKe8r3RV7wb9+NpTufetYNpTkHxncbbo0D29hSAS9psT3eIpxw0c/wkOFZTR29V8WL1iAS gx5TrA90wph07Om2/Af2YT1Jan/MBUtUj0cTDdGM9OWlq+pe3Pb1dtP4jyqw/l5CgwcY71EXqOzL NwlG9THMyxjJIhtrZn+/SUTT91bI8xb+cFOW/RlNVMYjpJA+LZppEsxfpVcf5z+ebMmh48fS2Wfg 8nGiFMdpRW+uErY/ZcXVOS1bxqm8J9ICXlSl+ZvioPJ7nW7ipRK4R8kKsKR6RYIjxeu0Plhle1BL 36FRLNpUjiyOhfi79fGlqU0APAaIUWmi0idzNKmSYpZWfFOUIqeGKDn4uzbnfz7HfIXoX6djxYQb rttcAAiscPtryt+0xr4vcIUA87xfAxYHI/K48/p/Frq6vfuvJW5hd6Mtxqql6A17faFLmacR1p41 4FjgJeiSIYxOSfLDCVi5bOSmcmJijkVbvg3KwF07skJDwF0sBWTvbSIHyEODvMZVqXklK8wvx1Pi qCWIXzHvNxVZNTgw+G42z5DqVHSbMbW306JLdNE3H4f6aABmWvVhhOakgZVl3dSfMRch+syxSWZG HLRtPIMleKzW0nHz0tj/K7CAM6mK5rjhVrYj3EEzDLOsgX6v56ylhtPDZ2QN3opAYx5uXjUgfPYF abl/DpZ+F0NKzGi8OSDX9DepIwQIJxkQAQGifmNuvgmnSKgnVm0QwkeNdeBQibtMcOicXU9yGodD 7RMjPPDn6/44/uYlEaWVUIvjGH5+cRVc0Kq0FguG/FO3NdQS1X4bShITQV84dNcdEf5SmGbF/ZHt 9RGpIQ69EPsbrw2iy1vT/ga3bRlSr3zZbHMpUCyMkdOdEFAHgLVBOnm7PKeuph7b3B1zx5AzCzba ufE1DKV5T5SUmwNXhv84mChkReGghpeRhx0+qPO8Vqex7s4ZVp02bOlXRXxDcMYmuLHD0WKjDNCL 8EVOUqjdaq/boNZD/ooFQX+STylBm+iiGwB6cJvNV17Yj+e/ChUY8DuzWvMQdKToaTCCQnega0R/ Zwsn/2vLOHq08RoUt1aKv9K/TJAgnLN7oTQ/kNQMBY1ewO6bfRzMsAwkOAtzJEdKnsZ6OhcAzskm vJSDEyAcNRp5afu8SrgoMJ9R+dk5AzIRXAzsSPweAxoSt6E33o2dr/+BP91dZqbs1PvRYGQzCSOL 5LoL2xtLsR8x4dardFiexm6xyaihQVi7kK0wPf/Jqmtqc6Ygk6u1M9SKeBLsA9SQfxHKtWikmfGP I8D/pH+fym0Q6XDIsLo5FGQ6mH8qEf3GSbjg2/COzjtxwlegRUiskGXiuC70wcAe1Ez0vh0ebVl+ 4fC9jyeGujlPBrlJxnqI1tKBXuJcfPQHiKT6ueH0QZOYXUAjg9aKhDZcQ4fMUbT6s4RvE5FJ7Fpx zxbhnsXrg3TdZlDlNbuV0TdaZn883zTLF3Y4fO+A86yK0Gdqw0F19w62KIhV22/anBm/rCyGE5uZ Vs38u5mZyF/ClPPKnWgnewtNJ0lvyF6liN3dleZ/vGpaBnMdS3y3RY7wIO0LpbJrERe9dxOo96Tc ppKu7405kFG9qUQlQ8lW8RCFNoZRaWq1SMyDtlMBaEP0JHckVTpw80JTgAlW5KstKeMS3kXvrFQK fcov8VdxRePgRl0ay64niafgd0t5iY6Ww9FPUHBOH1PTni9qLCGT0noJYDUZSoqEmthLtobkNoWT CA9X6/U0JPLw+TQK+oP9FmXVNJEBuLTEgCyf1LJ9iS/9/cZA8bxLptKEHF+ydNuqSUJrh6F8XvZG dmVlofoOygAefvg41dFud6fcBf1mWSDxgqmVKL89AtMkCjmiCIMsyxY9f5DUxxBD40CIFfjvVo0a sKX6cJwN9JRIBkIxytvN6zCXFzqRAPAM5bFaAM5TcWyT9dzZkApwaIhvI/zsynPJRvCtRuO7+r/w CU10Q/byL8HOTFdIAhjABa89dZitS1eObUZ0L7HQXiRie5TYsTN4+IOykqvW7mzTTPkBODogt3V0 Lqd9V5iQy/dqzaA6tQp7NQN2/xyxyh5PIzrnIsccVvuAv6tih5r2hA3OsTi1bJHZE/gpVOeqaUCC oEZrXVfN9FKlsOwAPtNEQxWmIOtnOeBd5ehaoHmnkvuVnEkl5CoPUVBsgkLSixLntKOIRohAr4fX W9MHWq98T+Z1b6okjbJ4fS8POSAHYGUSxK4N7p8h8OieVi1scYFFNBDAZpDWaZjuDeNk6GdmnCBV MQcWnwHnKerf29GNKIbQznWelej/UxBCl7LwerJkunCNIcZ7P2O6H6zyKpRs0bsUnvFcIkWxZy2X KeUUEnuOvZ42cyTsIDKEI1ZxqwOiWlUIuBq4RdjnQCPNFI1p6A5s1tlRbyXrrCIqaSfOW+iqRp1g d/Y/xkLfNlbxK/CH70wJlaU91w0qCBPOueSuFKO+7ksd8KrKGaECQpJK3stkp6wuARSq7AcbaiGK sMRMtRmngWB0X9rqFPM6YRqcg1bU/29qG5vlEgCKU5lhq2j8FwrRCpU/gKlNl6UtAHx9CQF/Ngo3 lKSmOGJ/w9Xb2GhNjPs5ZXLLPKQjtCqi/fhAUIUv2kiZRobwwY0fUuvtjYM0p+Zj77NMzmpKequV myLhoCjfhjkvHvd5F/a1jJvEJUfK/fffzlT3ICVOUc1uXETfSAcBD3bI4XII5aT49yez9igJVvB+ YHz5zIf/iniq8StH5BTknjTmrx7n6f5NWMn0Qd05o/c+5GCZQ6CfinF2QaK687GMOTrFTRWUFfmy LqvrlR5uJvJQ6+zK8KwPOTKRAWQ6JxAP+FhY2w4iZptKRHOi83EAdorNJHOyKd2S2t4T0cfelVkc FBaDyc/uaNWtODivjRa/wgkE1gC5RdGdzSKMJuI1O7HdOrZagH/mgTs+WpOsvD6GiLcFRDUlGp5X yecNkU11OvqJeCAR6AXp2nVeoVi5QFtPqlkXAir6lka6TiAekG5dDyXogEbrRlnyYAwKgvPF3F3r fSOWmGyd/cQ+xaixBVfL1bOGCpTSlTEkD/reMrPARbzT0sVNgxBwZ1GxyprsmXO5lQ/ezJ/kaeiB 63wBqVwgErv4BkeMYVfwi6j3hB2UcjTXg0vQpBA+RpH6EisJMJXwIfoWnaoM3Q91ZNOPnW27Ijig i+zq4ZmYxAM7evMYEoY5wrtNZ5MSSVo3IYPaxEQu7fD+JRatvl6j/gdI2s79x82Y8w8jTXSkNFRL K5gWVpIl6+F81qhFGRjSyW1XE+k+rhjB5MdFZYRjEDm70A6F63Jo5QoUwmN81YRGiBnPZIlj/Pk1 UFTWJL5rRc8HuUh8WVp4ZEdYRStsHepFV14C1PHMG/bqhPYnvhRWMjBJe4ix+jWjFYXnAH84/Tsb //zz8iKgFpvlYWZpcqcrm5gjyRlojIHhmXUL9xnK9xCneXLWRzPehAtavWddvskzBbBreXixC1BK YE5Z+LhaC/VcV9K04c2E41+P36M3Aqle0CCpT6zezmPxaXS5FwlnPj9I+Gz4oAb0Yqe/bq8aYPkM OrpejpnfxboE1QN5+pHWbUKh5CdPdQeTC9f2RFf9fg2KOs21KgH3htC3MUY74kAGJY1uIKsq+OZ7 /OPzBlx/mTVqsAZKsQfBZOPb5jEgup4JVMIyG7Mj44wqJYQX4YGWQEPTUhpD3hHv7d903axMxDPL 6X60M2i0sSCcbVmHcyvVwiiGABbi2M/7cwyW4qRmz3ayRgRlJjAk78/cX0aUtLvd7HQEpfYvKcPJ NF3HsMNkrQwBlHBH2dx8zHhQuOdPnWrcOovnYO6Igm0LDzL+ISvPBlF1pNSgMze8+b6dWVMm/FIV ze0X5dAl+f9KkQmQllcTMeE3hAWPN1n/tL/Hg802QCxFlK4tYAntHjWMBKIqf/xy4SIAkE7zrl7r KxXDRvPO+uj1SGcsrW+fvMsSYoaaTwGt2Ktp8eJDGQve86kcJqmKEYTsTdLEZUxsTn+uFGmbDQ3x k3WV1JjF/KmWqnKDAJFCENs8VRKr3uXANY0xFhyXpkGEmqsZP8/bmvwa717DQmWT6G4B2pdNZS8G 0Vyh0+808BZmrlTGJ7DY6o9/GPkYboXeb+/iJiOneSxyUaduWcKfiopR6JyW6V+pKkSJylzJK00X 8gevXokLKMgDkjBu7ThDwD+mmKTZwSyzjp2xQ55rIgFlwy6XerJeaMJiX8RgBhSEJAlSY2xKsJDd PAiivqERY45qUb85BT+VCZBXNH1gYKCcU1cKj3sfpusKvC3NQckWPU2tXNfIlu1vgUGKlpDUqG0l CTsx8mn2DuOMECmNkbRILDGKBLZSkfNFAcG8lAb9d1DcFrYgOIB++furrlSKt2MPD4Ipf3c67J9L oQrlpE+MErxHia42qjCntaXkoyeg+AJokMqDMuYNL9D8YfAD4+DX2FhB0iwkbqk3VYLinDfovEWE aUsrTXPnH23VNPutx3VOqWTigbsbiWXd5O487uYkdcOX6aCvtkT7O3874sRxkmutsxZ3W/kzd4p4 NjhI8mHFrfsno/ShtJPplfSpIZYiNjkjt945BUTsa5cgNdZEFGMqeQeMnTjcy2yZRGUUxBRMc3RR kpeyM06yNIscxJHY/0HsMAlgQwvUxoInd9J0VbK9tVWdlKmqaggGq0z9MTN+2CTgg6rStwAdwAFE ytdebdHpyKC+g6AB2IxJou8tf6gSIVwefaBmCTxB+QI9NM5tUBKgptiiDj83+pBs6hJceJWMHi4o dwCCd69SHlnQr/GCwpmMdFgJ9PH6Q3fooX66A0xToCRZcnApZ0JmnfyTL2wBZFZEIa2dH9xON6wV F1kfVlLDy0gF1bHCIMjihEwCmW8YmCWCS/o40PVFjzRiJSw8PhVniAiLzLVBYn9+1zhQOdH4HSZL GXVhPC5LVYlc8d66ouN8046kekhroW8qwlkCNx25pJuquNuL4QUcyCBYmBmCSyE9E832nSyzD+lW ggSyHzNx0Sw6wGMvlS5eZt58cVTJLnQxNuJOhGJuGlcnddQrOMjVDz6u1x8p9AAjkrP5HaD8+sRQ VlGPQrZ9iSyrX0msZ5v8XCzEZE6P+AlcbMdTt0wobU1hWbB+q5NuCzSYYNrvZkO9lBL2GQhTtS/S OpVH8DL5qGR+Kq9z3k1HJ3EYDrIcQO1TTYwBIcsFwspGNNfJ0iIEMd6F86wUAa0eDAhfkQRQf+VD c1m/IZoapnkUw6/k/8pR9xOgNbhKH6Hz97COMdsjcpzXc8icPfidMhcc4LPs91Nifms6DPI0/O7u JZYYkUjgQp9GCcjfga2PpJvCnngTAZZUZOmPFBP/wX0kNoePpf5Hg6d3u+adk4R6oZYlCufAkp25 81znBUDDg5lUhCTO+G8XH/WQQYh7KUBQ1VMqtdDqOIwliQoYo0/kYodEQS6YHba7L8QsHNR/iqrF DNxrM9a+4LXaDgajeqWchQ+f7JLQqXfuqbbjhR3tm/JaUkUhZbGsd7pRSPNjp3yPjGRwBm5fw59d hcm1pWbardxKl5a5K0uBEOmUgelRzob4PELQ5vOe+Iz14/mID24ACBBz0+z7p0drlqAXWvgXlJ69 Zj3DRPaMAn3tlwaMQsd975yH0BaGOKLVvdPPKZMTOp+29lVpFVDp6g1OHSN9CJGd2FoUbx1HAWrU d2y6nnbCkc2gHEc63wW8N67wtRpZYGV6nJptjmhG8EXvzl9juF0L35JIN24jCzPyWsZ+5dN6ISKk Q/qmvRzmjHtBEFmbCbHk8rfSYYJa1IMEuGOCLIkYNCyN/WvRPJNReOX802uAjVhR2xsns+aNBf0/ LskMiEb2n2AdBplbL0cPhUhiW1Kvrxdoket9aGIu1V9IocLWaPEn2/NGtX5+IVmi2JpsE6quvl7j Jq9ozwPfK7RIk67VYdIkHevI0Ty6tXHzRDyKaxtLt8Kr6MAVFeIp1iRI7YklhJzh5g2w82bsj8XU f+BQi2GUbj152NczgfJ3P8LFDs3cNSChoWsmd5NFhxYiMTWuvuRliBcQM1mMBKy9G6CvkmDWuT8r Y5NFd2z9JkFFtaItfOYXMo3cRj4xO9O2VRQzgcZSeBB14ynR8Qc3hWT5Ses2rxbgPk/D5Tu1LsTr MejuSr5DUr8PrBMyoN7BpmQD30l41DUim/sfKwJsesEigLvrP/mDe6lsvrKkhOpg+MLhqQB1qVR6 KWhAhVUntxbipwf7bST5XTwlZvqM/UgAw1ihHJN+yYXO5uJuz/Tey/PNMCE+pVxswBgd6GwXuz0f qyBcjfcCSsyeGAIBObxjnFf/khB8twAIOwJtGxk9xSHbdDBK6huxQN3DX/io6lbWOw3Lb2wnTHZz ueYShDQUh+WqZ0JNvLeLKI6Hb/vDge2kfJCIJUyIVVrIgnBeket4/UG+ASItP+euEXUlWc3q6LTI o/3g2jOGdIfk8f4OhHPpkEtqwfCp0zXFSprFqmTmj4l0XKs/0+3XjYBmXdC+kDuOD5ijF9SmD1tj WptWAwCWLPbSzDq+2lgxm9B0tYN3MMN5sEQaTN6NHnw9uu59i5sYqmMvl8NHGTLxpmcZ/yMAS/Wj K6fUvZ+MMGaDnTDiAjI0L11zUOrFNaq0fDuwuQDG9Dz9qg4/6cmnNJ5X2nURtRC0TG2QUFeMSEuc C7iMJ4vu1yk2vtGAYbjHGU0OdtdOpyDKfyvGgoGviSAwlOef02QA3VPkBbaTYGyL6LYlB0I/qpek B7c8+EH2Jpda5kcgHEl64QwVtX8Z4RmOFIFRi/NR6kh4BUil9JWpS6pMfAjzBbNMcYHSU3DuaxnU E8s0Ke4KdBxjC8YHJ5kPCwKhBmVcmDxwLvDYiJBWxpPwx62cAPDNUE77NjpmqwmKIXhtasYK1MYx tDYzb9eFJ2WuOZu4xLSAQQhL9WsSuHBTifIg2G89MAT5/KLz/vUoH0d6ddHGETAW+m5j0J/JDxMv 1y8bazSL8ZodFKi8UatF524Ggf6V6Dhl25MD+bJ6iw+v1NtIk5mC+7LXA8YrkqeG7dEgOBq7nMuj b75TcKs1lIQXPI/K4INtMMTlwZEGsH6v3mmb/AlbhC5nLMLQmOkfOhE7RBYsZOkjCvM7KUeGm5dc rD/8ktdMgzBC9FA29uOVvS9KzzHZ1V+hS++0Mkeh++8ODhHm0mPj+xrw7CVzcCggPmzojLGlUkTh j28ZrPhz/rOyGQM0kfChbNo0YHiWer7W1w7gOL4wZrPLSHHQOO0vTKnMnGTbwsY7V75/8bEQ/z9K nNmoUNOAk/fMCVRzhmEtVaEl4rVUOy8fH2aGFjQ1XmLyQKZz7YwxXfCYpBDuG2zsGjpKK2JzdOTZ QGfmZ4goPQxfygbWaSPc5P3Zy+IA4ecBexkVcC21IsGeIXJTtpYz8FWntBHCpC0A2wvIDaxIZ5Vp ZtpWO9BhI2f5dqOjjC0IjCqIBNpaZ9DhCoQfaXcycnfHOUJwxhTWf2qjXgAyom4hGZs4rn20eaA+ tApz7VuNrqhWiaqEagEQqz8fSX+wYf4LkL6LgO/MAz7vDb1q5+sFd4SYSPtrReoinSU1VwsEMTYq Sdz4GYiEWzPKvtn7uXFSQ5KG0CaVcBZt9ppmBC/GC/+p02t2jRhiBcr8xGk+/t+K349hmcakNSAY MLAojORa/z1dqlACUw9l8ZBamTVK6DRJPJocDHp/LcY5JA7Ic6rK6xx6mWkeGyXNaECFeRikhT7j IjRV/gjIS04xK1rqELG3IKoeeXny9bOCkx+Hb8+RhBX/R3pIn4XZpEwl4T3f0jfveD/wWgYwexTs GehjP308xkJ1i8LwYE7lCx8dDGxen1l4QQNRZfCo0njc/PVcle3YY2k9B24VWPK0xuoPkXQwB08l Ji5Kp1+6nBKhPdsiTVxHtk8W13NOLWHFD+Yqw61oPqJOtiYc2RwasDdlirbWIF7B6ANmW/7TaZFj ttpPyC0ryDSvuasjSuwcCy/a3Mb9/+GgazzoHCCKlDCl+8laVe56wfH8hV9SmL4+2W8x3XTBG2eT swDKIJPeVP3Ng5p7A8iB4LhzebNNkDCpMfsiJL8WYiC7OO7go9eZwEAWmxPXMXuhTKUurKniwo4q pT8COBFJaIwu1tXfZsxGqvteXUeanP/gH/Uqk8zhXbNUuboZcenjBaR12dRrFxH3THg5r2Mxqeou s2fGSC1lhU8Yc2nTIuIAj3kUyVB2cVxQ+w4edWDTmrwm6vY0p1jwV9IhM4LJ1m/xckQqv12aps2T 85Hypm67uMucOPlKGefFvZRymEOfU/D9AkcBhco1kXRD6TiMaxOmZ2KuP/HOdyB2QJeZQu4Jgnmy /hly/dlDCK34nCwahZXY+uAekiMLuMDhEiv3SCbS9H163K4xZuZ3soNb57T+7zsJ+IshPKveENGN vl8vMFpjVXwhQFM3XSW7m4pSe6v00t390gp+h/x7+jcAWBvipsUbGYitCXUUWLrIY90siGUmtcAu 8MZzAgvSCOmMXLqkXkW/WY0CcsCByvWEGBR00uYUMkezR474Z1RS7a37TmOCWUE1luv1deVLlioc aTLnPBjza8TyJO96UMYcI4cQoQxDHJOXkNb0KuD8CrAp5Jox023c28C/76a1mEZ57OUsY6BST5rs VQQTXDL8YbRSYgIdtGNiB7PiUAebleOmIxdq+nUhsQYKJnbheu7VMNCnz0KgtxQfhguqAy1Woemi 5Tz7G99ziWHA39zyl73QzBLyl/uzKHFVY+xkvMyAkyDGLhyGFuEz3Rel04T8Psur2ppdrAhmBk/i rQB4T6tzXDvK8SEc7rYVkvxTqwDT7Ec16HBk/9jkglb0/oOmInuIS3LqAjz+8ELt7oFs1Kf1Wx/4 utRBSB/u61+5/Jirz2awHx6ybJUD32AXQIruKjPxED5T5RVfX5pOUF+qfbsRMbCOleWQUuLnOlDL zN98wzl1ok+yH9GADazCCwEVlI1fUEvseJJMTf+oymB/UO1TROQcaQyDnrR1a9uumgR8GXSiEmX+ GL9miDDakQmJa/O78IM4kad33AX2FiD0QGL1TXcHP/gpoxPy6q5RYcmNj3iYA8mEBImum2AjA0X8 T+jo0lqvKl+MSb8+zHCUfX7n8tsjaegt5CMwj14yjg9Kw83GpEfYjTswKCxDsnPbMFB3jV6YPd7h g3rFa09LrIgTlAXYbj1qksPOC9vD0/A8rGdc4hrOuv+biTh7QbJzi/VjXnx0N7s4XZp8d2yXwryr AIDPniLaeJoJJeIdwUsiRULWiiTtjopOaSozbdNRNXSx1O2OX/Nv4jXasn+pZvRC9XmWWj89NTdt FMCStws4R+Ihn4GiGKQ3B7Is2HZt9yJthX4NkiUHhT3xGe54AuJGlt8RoVWVoMJ++DnyWTGyj+Mk EInnw/M9SJOLb0CuHmQbeqhMqNYZL/LnpD7ddt5qjntttJDs3co4xqgbSOA5YSh9q6M0uMerOToy yscOTDQ2bDBV/pRuy4YRBX8RGLo06hzIQmhZhHKyUChT6UdcKl42GR0N0XJs01605NkxyWx6/1gM Kd1XyA5xigaFqw1rK6wcu7ZMHWc5ES96sJCKzwX6pXjDRGVSSdzGfxcGSaN3y62Hhc92mbraLYPC CWvg6vrDIr6w3FL3zUBK9usMDwnXPg08sOXG943KNMFZz7VEyEkABSOdYaYygLWKHxm7HLXhVJ5r JnDqOsnePD0+NAcszhvvDOEhog/QExc+jImYbD08IFA5TcbTYyNtGNl3TiCc8UBZi6p1aoW+a+av z4U7+ecUkBg9AckW1E91aegLuN9gW4WH6z6zf+7Zy6ixDUmJnEbukuPcEATP9E57+NizCyyjFcHD oAsZvguoQbZ3MySx5i3PtcqixxR5bTgD14E7FMTzLNpQ1cKKYCZdQmzpP83ezy8OWIemD6FD7yPr MaZp8eOx6EWRtCaT8EtrUiRcR0lT5GqJ7Md9uIcTyQ9CV09MrfbgYhuTh3SxLXkAcM6zHdBY5RK8 L3sb4Mq6y1Po1cMiP4AhOuyq5/dQvtxL4h14gDiDE0WAYrLpHiqGc07X63UzzGwZTzSP2GzPEJaZ E1agNuJVBf0JRYYxF5AHQSuEKa47YrWmM1QyXy1JkCJ5pboeob+A3epw6a9BA03KzHKKC1httdtU Q9qRzW2LovdUeM7ADKBgs+AWGinSL+JEWNt3trzPOS5HtcEpZOmqV2IbWjE5l8YT3EEZmmxKcASW rfPDRfKdTtweeQByFHfZ8W6q+Ruz+3eCQY7UAWn+Y88+dkgCbPd5L7Cv9OOGcq91N8D+CPmdMvoI 8/kLLZb2lVrWMsWhq0ArHFt/ypKr0n1W4X3ASxwUU7sN6wv0xOETdsmCOp3ShJBBrLL/Al6GH8sz 4/+Jns0y6p2pb8O4Vt6U32uYRLdhyuIfMee7+EyyM3L//F50HrMVqj6OCzan97+UGJNJPql1BZe/ RO59+AbxoqWgVhe5Y2p+1FPkZnqNdrGCU+kTHFMQqzBGW6P5TrrC8jP/qekKVya/PaZX/pJ+VNwR zei25UIVf4Wp5QmgA0F/gjPLhbVQttpOrBY6goclXqZNhifsNR8+2kAvnkDPCkSmWr8QLEA3ZOwr D5p0mx41Ze8XZn3urJwlpQZ8S/5NvBMbbVvp7v89jWODWpMz2sIm7IQ9MoHo4zzOhjEUqqPF2pvb VzvUM5qf2aEIdLyQ45UCWI59TPu5ggOVq9z0k4CEQLaYIcmkK+nurpz3pQKHFL+YRB4V3S8F0ok9 BBS9sczLr9tEJxQ8Xar1X0yXKSZZZqQWK/Jw5xaHTboYDj2V97IY3loBMEwt8VItDPoeyf8XTTbb kzA9V7i7b7zfjGHh1u24IbjWQpZsh3nvGV4CzByItMQQbwEA+R7VkI7XahivsNoDnpVgLOuS6Vd6 wfbpm3W4FBQ+0sl5ZTQEbWY+FAH2XqGKvYT26ZiEdCG/xSRLDNudcsVpWM8F7hge+otgOrf1mqVG xiV4QGJBUHMcUzsFpqGOrUjjViQicI6LIpuCMQ8b3A8GOhn+1qGfM3hagszH7t0hR013bRI0X656 QuBl6ZaIxiKnjFatHQt1kX0f63fU9R4IjXaG3QzUKrebSmP2NA/zcTaJV5bP1ayduzvujQu3RN23 6tmar8aFnD/uk9m5ASv5gjL/qBzWrwghNvcg+4TMyhKqOCdhUJuHM7ahSDBpKCjNfX9XC+4WBIuM 1RNDACjF8RJ/aYXA3AzpVyRbI5+wdJvioG6Wy3RUIrRYQu8jfL81eJIlLdWZeELnKgkEtHzJ787M z4udGcGVBEw3Ftp4oNHSI9dasNwcf4c1x47mmRHGriMcoFOZg2zqJuPpGpv8CAMtIMDAqZrGotxj sRiOYHq8DqyZH7WI9s9e2Yw2tXO9ubeMBwkK/C7GNRZ5+GcRSx/fPHZ7x67GGUN3fxAlJlJn14VW HswyXPgEl4Oe1FYP6Y8NL6G9UE30Sm5CWNtAqVBYBE/peikoas4pIvgzahRdOcY3sjmdKDDeLCoi rc7cDh7q3XTWSSrTgLeHyqeleRo1rWWDs7O7anbP845BkHANAOqvPl2ATYpCYRotqpLwWYdNZlhy rWKsucxFdhvzHrtW1NPfEXqUpNu/J88Z3s2022Ox9yyjrHcYDk7ZjS7zsB9JMijCIM8orhvWSRuo D/bnOcCbsnlNS+mUUzl5i15qbU8bK3QZw4wVZU4ciyQE5tag1XNrjr1UoY3Kk8omVpHE2GeWUL6V n6q9GDQyJ5HxOShW0bQ9VDBDw5eDVRb2pv61ahegdbMxIDJ2PNvrJ72jIn2mpVl3Lrd+7aXc5lSO Ij1Nn/4VVZrIxPzQRubuLZFGJ7EGnXKnNjaIKO4ljvL+HxSEbIPSXvv9rMFcLfB3IdYywt8Xpo3X VOaYkTkq7fb4fUuuxIZHtv8VbwRchv3UU7Zl+u5YNldmyn2FnFAVwtzyWoUicE4FltYPjTfa04Z9 r1Kv3LoghZdQ2NL5XyOw9T/s28MUMYm5QkeXmKkaBf7qK660AEl7MFhNJtxgzvDgpYRm0Ghqnc9C ZsdAq9sdYHTqSmaGUl5T+EFOfdXCfsrsiesmaBiaSoNu0dvqHfRDWlom3U/ezyfButuwLSoly8n1 kZs5TivsXiEh7EY2BkQMwwkRngSg2ubLqN5jyOV5x61OB7DgLh0A3CZPZm+bT1pfytjgs5lbEQAw L5fRaieIWxhdBoRLFNXwhehxm37toea/UE/a4/9+lLB82XXiLRY6Z0GnNFnkLeg3SXYfV1cz1pLd x44l8C4WPakl8EsHC0KaYnI/tjfQYUj+tSE9gOtR1B5PXmOUR8+xXMMhRQ7JX0ncxIqLEaOJmTHD GajQgtIuh+lgcCgpw5MGjQF74QlfGLtlvORNbebhElCz+0dYxaB/vy51Jlhg1k90lWeRuAHLSmUm 16vQFIAqzy+6TRiwLRTdeSU/D/PLr8LRdsmX/7cnNsU+RsTbr/9TyAumYkvNZaTBYkmX0XExB5nt q1wCRtQBCkstlrUJ1qnBXjo8ud8hxzAFutvZWokDaDvu4XlJ3y0kkCjndMC7gRVXPVng5WwlGCP4 50vDWjuy8v9uB1vCMGrKrw0YgqTY4oSNPy51/O55VaW9O4QB7yh8TLt7Dw/S0uKaoR57zLnM9vSw fyZcqw7fyTbWSwMWM06aZcLQ+kPdtIExwp2HbVyZEbkjlSWnvXALT9cGUPpZmzvjfeG+AO5TtqvU YlcSiOYb5UrgSrTmva7EJy4QcfvWXYXXgWpUf/xWDRydth6jy3nh2N2PnnegFjEu11x5685N9uZb OW8A4CT/3L7tkY8u7Pc2SqCZ2a4CCjsWPqJDg8QydjYyS49g4ejvnryqN5rC7u5p5vV0pSkigEYv K1iH6k+JhZHQ1SVqVUBq8MbivPNoUW4YoyQG4Mpr/Ks/k0wmIHzVtFerKy+CYFxz9MdWObH5uAhw R8M78A6H1gxFh5HUKUh9ZoWBSYoCplX/V+ay7q0qPMZcLLu/lWPNEUISgghYRE2h97eT/nFPiqSi 5X50LlckERfUDLOIvdA7Ao+xlw3W7T87ND8/dlWzQygRKbY/ifXHSNXo4If903ShRpHUtDLhrcRR XtGXikedBs1mqS38YVxi9YDqCVc8uC25KYjBFBCvbS8DIuVYWMZBRR/oFcfGx7FEH997iX5wNigO k4rGl0+P8D5rS1Qjeh6MMYdxkvxzb2saRIgQxgFq0+wm8w2IIv5Xyi0TETifV0Qb3YUVrrNvd1jF qOuRrfcsMEqnwtMhrcy/+xkfV+nr1tMRCzvYc0I2XxqBm1xz1JDNLqBSjtyZrC3qQEBQlP6H2Dhd q3Qcvak88ok+5cAkdWJA8AfwzLSr2vKKTy+fl1MvGSq8ITfEohsv+jH8sZ4MnSWKgkwb0dIf9m1r L2bfmLq14WTwMa8s6xHRiblhPpGre+NWaH89VsAeFQBG65fmzO9n8sWNYgUkMhITgvBYvEaI8PcQ I2dSWC/G6KlkZrBZhK4xbcRzIXsHtkDdmTHmSq6CtC2cM0Jh5HDa1nSvAbghwtZt3nicm9B/UsY8 Yn/PmS8rhBre95+FEr9bniwsNHA6QuinsAYOaiedS9waZZn5b1zqw6FyWX/a7QhUFMKrZ01qe65y zonCUiMsekZ/ZM86goZmX/2k1RE1LK2PmzufptXF+02fXTGY+x+Lz33FUqX35SxQn//9GCYcVzqx 5px4BoIUJ9XWhkv/ahxt8D6IJ/SIzjjjFh3UQmIlOwgj9xewcRx00nwQGhTAHi0xqlkG0jZE+pgH QVIPrVuaWSOGPc3qXnN9/iOC/dYLXeWfVwtwTh5B+uxwJmdLdnBSXI7bZoZ3/B+B2HGYGyhxqr2X kZ7A8rkU3E9AhAHJVxgmmGu5b2j/+i+oIdorvXEbdcwZrq4vrMiYuRzuqa4/2mG7004r5wyk32Jn rGWlotEif7/pI7qjcSGY6e3ovT0/eiisTjILWTZ14okuQdskwS+hnYnWEnzTMyzGQU5Zuv3lQL4B im1dWcdhmrHZmJ+L2ZfLSFlkDNVQeySM1maaHeLw7cpcYEbfNi1iZD/ih0sNbqrI9IbjnyWcfj/h g/+2GiHeXYsOa9mopQ4l+ZaUPWfxM9SkiU7/vgxoOs10tSxV5bmerH6zDmZT+lFHon3K0go6/ZFv P4pk2mCIfAmulb7xkk/PAaLnV0hMJOPBjzpwN6d4Ctw2sAR8h00EycXO+pJ4qPYYCOt8zPjtiyQ3 LS6ya2eKoev7WIxuxFHgKIpB46WaBzuQ2bSU2R5gMqT9G/qJle2b30xx9TGePW+9NEw8rpF+yDeN 1oxbIJT9xV1v0rwR9ziqWbxycVDj8HXui7+KPBHlsI2HRs6kzQ2UMBDVTLqst58yXJpmPAZWUhDO xBwx7cijNofMloC1Hwn+K5qUNwxmc/T/smmVwAM/wq6b46/VpDuzz9GAngSsbQFJI6vmSlHiQ37E jq0pdh0nIqExlqOqX3Ct1gDEgMmJYvTRTHiMuFbqwi+07SfanTbg2WCWI2VnQlBLY5hDSA0hVozo NDNpAbeRdUCYn7dKufIwfqb9Suu7+YpMk33gnn14LodcFDzZRPT8nG7/4pbH9JrwtL2w8seeqtTt tTMZxyS+NSiJwgR+W8yspZHzhPVDlA+xtQ4n6/8DB0H0Csit0dquXzttoE275IZD3D/A7t6up8me ztaZAPqxsXLwo33qDMF6LA2lV/asKhD80Ke9e+7ayU2YJUJlGXLT1sJXhhjj2s6EDgpeOr6rlnLP OSiZOdwRl0yE5BVKI3TTBPJcXwKqqisz2sLDOpidO/c3s6RxwWnjYqFP2+8utSBNWzekXntXK9m/ HJMGoaqJan9PLX+Oz2hjI++XkkSvmxWTnN9VDz8jhmCIR1+wO15xlXY5qd1oeJRaE36fT9JBFZYD VhwmDOoK+gkVYCAZ7aBDfoXusTCfOkK8RtY0l9tL+O9gLls9ecz6zbpMAKxEol7OWoRXzsdNODdI jFdZ2wWQOJLxFJEC8qswwSE8idIlzxZ6TPyVkNL08cIHKo3dkq0FRSJbUoO7IVRnTiyh/z39jDV+ nMPT9dfmhHvDjFTcgwVyVizm6ieZiUjfGONYyFwNu4dWnefqij1akLaoyDrz6OL/FT2fLrID2xRi DULAJvL63bSjVVvDDqI6K576xYamQUB//WtNrnJ4kFveyVMVCvayfWR5nJoT1fmuvAfS26V6GFxH QKvk09ZYD7qPntMnjRhZsMBahisOCVwCXdFeOb82jcfqp3l/FNA40wPGMOdowzyAD7EpJmo2UstS lJEt0yl5AEE1sUDmBQeFrUhzX/ZKVfbUuSx+S4+WOI//9ReB9nFzsScF4o8XYdwxHHjMtcYuyYxR JvsMBWSHOPlpBJ1zdpXK2HozyBzpBDpj02IUs47nNL/ikJsm9S9SqI64EWrOJlVlzC5XUzA5CCO2 dbm8ihDuk0gkDqFwVmbUd3Wuvkv/iGNzcNfs10fyq/Z6uzfP6ZhXfCARv5hJ0j8sLUDTN+nRw7HH YeeNM3pCQ35rr0oRdwFq3+A/jgbT5+oRnrWennptvazy9jx8MDsFqVcpym43AV8zLzuDTmIpaZP8 OV8X5sW9ZXTYixHVPgQZizOr4Hs2XU9UBkt6cP6qEY6WrmjMZvWKIWFS9ZREBn0aSMX/R2BbpECX Sq9YpnuKwaMV+pB5K2/8BDES6RoJyisoQY4UdJ1j6i0W6du2X8eS2J4wsPxjHconf3/Wl94RUrXY eKO9I5RMX9cwlUVuGAtqjy57X4/gBbiZebMZvPhjbMJWyTA2tAuNSA8AUlb6zLT4BBlP+rOG49OZ 5KjRddx3T3WQbKKdJrsfuXwchCusx+XoBz0woQCxKErySkJwN6zcZe7fuYlv4Rpr3WsSKSXwkeN4 oTHwvlw+yyuz7rHYZFw7W794BIUProLYQcBbwxOr7inZRl78DzRUztSmdWn5cHjaOvbsYubAlwRK uqi4ynCwDAPdk+7J+wfiDCq+HzPEd4Cgh5ftfsMNaJ8kiMMYH+HGrhIZij9tq6zj61pKzv3nfPOM Ro3Xd5ocIgfRwHLnMd7TU7AlS78UfW8gX3n+3eClHynkh5LN6ChZ9GLSUqHdKQdzXWlj0hQFJrtI 8PgjMV7rYjjhtcsYWNUQrdsHxl+GwfLPzqUIiibnx2s07Mr3qHHjZzCT6yfSXUr3KbfouyqvjbtM a1DBv5VRkicvgXdLS8RepsC6gboGo66I0uP0Wo/uh9vXRP9XpEiDCX3JgTY7bER/GJZjZVkqFLuY cDLntqeRLBpVATlyiRltAtwxZRVw2/Zk2ba3IXeGI9PoN15pNT4+wpBtSI5vCl5GcNOAqQdtST5l keKmYEHMbYh7rbPFcbq/DN6UmAZFxfbn+WjChRbBhLpMTohTEDU4SR42u7fRYq7F9qloFGSWVYfr qWl9OTeVJeadnPdK6VzIKB2xFEaa6hXUhd8spmbDp3678mf3nrfCjzEVydahWRcCy65VLpt3SZxb NlhYdZRTL3VfCiXeHrKFoc/CL0BZf4VogZDoblpSiReoasXbIvRnBG8pjAUzhsC0DrffI8WUU5Vz QaR0mKn97vf7T7xdpIK9LokY+ffn9xo7WQ/ujacn1QsLLJLf6kUCPnunMe+dG5L+7R1oyktk74P7 4OR9clL35mbt2znLHQ3dmzM+wyPhUuBLtx7rD+dy4VP5dbhrdEFjUfFWhyRh3E8erWha7+OyVkld SNukeuJNMtvV99j9KoXgW4/yHRYtsyZhBePH3tCsSQBwR8e1BHtXAtxijUv/dnxOXE+f35FOBFEb 34ZNNZFaIjvfK8q2fkDEnajxPIHyd4HWJlQkntl3FIcYg3TFvLcpSbyR+j3ZvZVNx9MS/yCDQ1yB gRM7mxPUBRv/Ew5Y7lGASGQN4XARLx+Ngs/2UUQCuTkobOnN94SMIalD+sUbksyv4Y+Z2SgSNDJT /JxpJNGfz6B7zFFuuKTYrxm6DGrKUfwYREj/sf2Ime0TDW8KQFZK2dW1MS1eZi4vjxHvLi8Gj6iP key+6rm/PDc1iC683nZfsmp8EyzuLIOZABwXu6M0U+KazjruhfZ3bwIO9phq+pR4mPZWQmKUfi2t 8/o+idNd22F07Yro1gWBsPTG4OG5xZJf4/jEemAQjBEzR/Hzt28g/G5Ch/lsxHtSFzUOctv9S5Sa jIJ5NpYRt19cKXSglJmCDXAOygvPn+BTx85cPkxUDmkdDpcx3a9wEGSdy0SCdYsL+RhKOeK1UagI lMy+mLsfUK4tR0EooYsKT/oyjua3UE7tX8RyzPu9nsKQ1xY7exD+Rgt8Yc6/QYnAjsB8z82lAN97 MFspzZH/DZHhsp4oTKVqFhmLkyq4Gu7G1680p1AsKx5EqPAe7pvUPOsmrdlT7lPha0SxI1e+is9Y lzD+OzHzkBY7RmWRpnNb9gMWzN6dg1gE6BscXCVSC4+Rj6M5f9rMOGyVwX4yVTUxTcY6X5Xa7Yu9 riATCDBiII4nCM5d93wlT/M//Z2MXWf9pnRoPZCGpM65Vi0PvjewW175wqE88NulhBle4PrsBScZ xxGKDFcOPvI35B70riYXtBowVEfPz4NKPfK8wp9GdtaDBjFwGbMDGvuKqZg0ve9uo39veQjVbE/z Ph8ioaSBwJCxVciOKNsftPVB/0eXvJAdVTVKQk1VO7AwIls5S5N+Z3m6JivQ+xBn8FCGkWX0WByb 5qXX0M9hpq/yh7JaX9aBVRXqb9goSzMUJmb7ZO+OCGc/i95FagJ0gRBWXFaECQH6gAs1Fmf20LP3 QsLhl3Xc8CwWzaNU2B4STBiGefx50be/JxmC1FcW/izLhUmzzdmblUs2xtkefK/1mQpI0WYL/kpX DqO6xIUrEV8ZxmS72Mr+c7MTBPKLPCWDj+Je6X8/cPuXkpH7rtpCqQmyNdQ3UknDusLuXAeXfsKE Aa3lRG78xUfrQMs0wR4BJHL1iiggSLJX43An1x5R3Xx9gB5aFWy/mii2UU9EhrB9EpgB9BCtYot0 pRKZm3vTRcwpL02QhwSA9aDqjSP0PQpE8fpKOxvnokkeNqixuNMWghgBsxEGv3NPMZs6U1bXUYMj l5cqMoUTo/A7hJJmLlvOkNzNbtHTRwnlRySxnqHJA5WYQj6/ZRFXT/VMTQ4PEDJd9Br28KtnAT4S J20ggmTmKeAb2vPcOdDVNBNFVQZpgqOrtxOycrs9yTbZEv1fUrQXQnyAId+P4yo8YB2aVkNWQdCx dTvAKrqQUisaTsK2pKNr4V1k6DnlRXgNWn5ZkaPha8GA8fh+yaJk9P2QGCHOc7pmqHlavtFoKxxT cDptDPKPJGwbeSHciB8CaeV+DzZK2sDg6ZD/lasQN6VwmYEuTGmMsi7lBC59LcBxL+4FP2tqEAK+ ES2hND3gRYtZYOh+xqOmrodR0gQ/lm35IwPyIndMPB/DD6CEEq3w0dERSFho7g/JJm2rO6cWVJQp 5R0qtFzru+mtnXa2Fr1N/4wVlLoOZUZ/OHwA/ibgp/CpULtcVMYwSexs+b8AUhZKSjxN5+Vpsoq7 aGieyr/9LqBhZDuWeD9VWyAHHGegWZNM1Yb5BPUER9UGLy5aRniTM4VtrIfH0ZwUrs3A6cWTBpwu psLbNd8P7n/r1zjVGi0WK7wGT2LirPodqpCuMr6V4Aelo92fTp5U/ZN01sBBsY3Ba5OqlXymySAu THyzhRmScWJasTvmT37hxEj9yZDpDmd+W8K5aoCuXEB0ZLpjxzTjSlY7ZqsTJ8crgAQYX7pUXFVW LXyIswXtcqkG6ISgyaZj1AMmhvEoRRIzV41yoW22IRvZ7RqlFw6HTSA+3pRpjaiHPpd5Jbij6YjS 0WfLXO596zRPcYQh1vKh+9PQVJGtoyscsl+AkSyuzentPEyqR0xikj50OcfbsRZasmI+frlA3dZJ A7h0SPvCh8TJJLu9iDnEj0Ks33dFWwnJqa36zXSnXcFYuWBDEn2My5XENZi3bwVekED2Fo2yqb6a tZGOSxS8Td8qMwEJ2dTGwGt56H/EkZldPZ+hoGro8BwmdQ33n0GmetJNx2/DCQGRFmY3QEl8enee cS0f4oCLeJVexdbkDP5+zNSdMdfpa1XUjFB8jjF37Z7STYIXbjBQ0reNooZIAaso94y/pCZ0sLe+ /vPpHSSbcaCnvqFcjXJIl4s/lEVkuR9etBXcQipKBDWszJ2zxXU6WUwPSbMAYpSO18vE6JgtPGOP dgKR31l/sdNVM2yFi/4SDz3UM+3hSBhVOBGufUdS7Yl+7wPQeK8jX+t6YWG6UzzcZODVVxSuaNnV 6pR1bCWEWOS09eegaBy0h6BRpHMRVBgO/VXvkJaybQ6o45aOfrDCHfc8SaUihIw8TBtsoz3R776e BjUcfFkORdHOkhrjxdKODXGJAaLznzAMO0eRiNcXL4pot9DVwJ5q5Kenqtf4w9vWcB10aMOT7kL3 DoP5ogCfLfNOR/A2fE51FxhsVJrsGFpdkkTtxefEoX4mk4ZMWGREsAZrUldjVuoGMMxKXwTDL8NO jjfX4RbWvARdsGz7zj1jBV9PqSOug/tpdOOR5/fUAGoLKiQoOb9xLNlQgwwb7g+h/IkIu+MffKoo PYi77Jfah6aUaGR4T9Dhd0dP2xMzwm1alPKy0lZxON3/9c75nvA7KnbS0DuLTBbxPN009yNBEsp5 uWBJsNH/dzWHY0mI8yoUs21B8o3fwcsiuX3CS9ut7zkGNudYv7UAXxaz2zNaORjnfxYg7Fwi3Nm7 in44wETFCsvVWk+h5XJNUnS7nJhF7WFqlhC9zduUpM1OVNMO6jvQ4Y80UsawaaCNcZcXBZCqHKlQ kJjsILX1n6ZpYx//+YIQ2fvIQpNIyOnUJ1eQSX9Xd3+/f65/1/6wg5uB+vNmCfzyGvVcZc6EWlhN IdSScPiCFxFTYsSaCqEMYrdjWeFcygQ/VfpUVoTxun4FpftgNIm7UNKNI/9hhk/EiNHKZ2QmWW/V Kl+gA5ZFPwkl7bHEQzvTZU6+uL4RrqQELn99ji8eHpZi4z8I+DBqMQaFw9Ri9xjs7VIUtLFRv8AI wo/9dhg4dvZ41Ihr2rqekh5SRLbdr+GnNazRba85tAnY/FConI3yRlFuTdlSUsFiO1tCusBUIht9 xAB1h9+vAltsUtHHNz1E96Y6Eb5+9/4b5hCv/KCyvNZ0X3RcQiA4oRk9lSP5ibD3aHVyL9Ux6o0A fzjstTh+/NbAjNLROCl+7dpB87SUVdr5uxjV+TdbsgiaHbiTdIm3kNMcgcpdHqLt0GnlsQqugL2I jMaE2mOsth22P2OR6h6iOi8abvWc51EkqHI/WPrr+rW75xTjZ19LsSXXTjZq3fa5FnB1333SLbhw sOmy5TIQp1bitPiF4uqLK2n5EYg2PR/xLQZGiLCZz3ClFr2R+vBS4Os+QS0QOmZ4ce2ktVnhB0wm bnyUMiTjOVtBdwvYruOY35ckXUBKXkBEBT2wn0LrLPLfamOsLR65Fa1lo0VA6qGn6wqPT3n60bMO PgFmsJhBErokr0U1FM7wOjUzZalkE8iHfJEkqrr3B9fpVGDpwZcRoxRGv2XAPZJWbeqs7QDWsNvG HlXUz1ROEIBrYN2i7VGnWN3yC6g7kFLhwZPi8bu4rt5WMLAtxIq7HEIKsSbmjdz9zajJ/ZDWQ/dE ihtvByIRq3f6FqIuW5qMftDyYZf2oGob7KC3f2zNNpbyTnP0oDoQGq7wPsz8iUc5jkxhaERdQpCD bcm8asUAomOXAE9DKoG5h76mtMswnd61FNV96447R4XBNKqxN9Q7daGiLM1J66YSXBCQRFkHppZe R6AeEIn3njNjW+IQA6agFgRRhDWMqhEhgC5TfQpJZ30pXxo60kLqRDKFGo8XZn9XXQYJkl+alhFD pTglMrN+LwxSj9P3Y9OsbTMPtkKap0q+CEmOI9japgDpIj3/rH/xQkB6fFBxP/SFlAc3YV/OhLhM nu0xTKKuKqcJiq8w1i2JgXB4piiaAMoqEmAzKkwxXDQoHhWPskx2I1WjIy3yyDOqKhXbV+lefdA7 OgPbEfJ41903HAju3vzsS762oUssNSqc4sL4qIK5Jo3043QdNCvCO66CLREn8J2DAe2SQr+wsgay Kp8WcJs5evCpo9XmpEdwzi9u3RZTyNdmpBp4pXKgr94+Wswv4TvRdFwbWyPsWnqEFc04ydBGSXdi v7K7aYdvjb2o9xUF/Vovh2dhHIa1snKFBD16FczTGK9A5VE+e59qvbBPyrb2YO8BGRQTHbLF42vU VF750615vlsHaru73jqk/CtS9Updb14lbKikDppPhPAPfJ9MNX6vUzblq4NduQKPExuxbOTG3iDX 0ZKyz6EJQ1gJLsoGmlHsN0hliupYDDRtG/76gSzFFj3KU2O3ZgA5hzTcQzqkn3/Evcpu2mNxqgXZ cMHWwLXeyY29JGFKJG4ynZu3QWu2uEjjHd7nhs8CnzBYtntjoghxs7BSxTTwH2MUiCuU2eFvDAcy l9MJxEDINNxfYWFu69fvTKgi9RXbT6wS/btXV4tDGwfaG/j+W2A3V8OkEYoMXv0enwMc3GyKkQ6L VNe1drZxmHxF4QxgPEXA9zyXRqBVJBOJIRJXXDRyaL0xxflLaV4/yUZiOAsAX3TAqg/DXL410gyf Vf+sjWU90eRPuYkfYK0Rr5JX9RbNVqJDb8fG8W1he9tVhFb7BtFqA4B0bLiVk6odWVh/I9mvgOgX WbeMXNy5fVf5eFmApD4nrNx3HSqAoFThZ8gz1t0u43tAIad44s1pf46IK8kE/pTumQFYGSJLwrB5 El6DAsJNRstGgCuVXQTuoznjEGy0ABd+itQ6vDcBE4exOvyU4+cSWO5+7HjTcjnBBesSd7Ztrh1O tnerM3YJIZyci5uww02x+7LaCFY7BXIoIdhbOTJp+xXbvZM+NJyMehtrKs2i/stj4Dc3kglpTQPh xs8RnURo30FgkbC1kqbD6tVPmWER2xDRfpJc+Ps2jYhxj7ySKj4SlxIsyJMXAY2g2AIOiDZ35DWt fFXY5U+MWTfx4JJqZf2b0yn6V64ZWcxqdDi78n9l6XmbdyC0agKPXjDBtBpofw8FN7Y0WIdzp1yL y/Vz88SQe404Lp20oImcut8cGo8WjGGCiBYYXKnE44PUfCGzrGp3P5TcQQY65SASZhN+sypmDl7e tQc8If6X1z42DLCyH8s4Dd8lFhc54McIw4EUgkD1a5EpoBQFuZ4oVANYxZcQuDk6FrmeYFZEFaFh U5louhvJ6IWGRuzY/Se36/3Pp6jI9BZxyHCGU0wK9iaHoySxPESiIiXTPHHxyTPJR2QH4pqnDAPC uP+tZgek6SB/l2Ki3e+7Ks+yxwTrBiWfSsiroumDOxTLEIn/bFlVSeU5oqf4QAYV5YaqC2/j8rpq PdkS+NXkPbLz1PsPJ397/8TFUI3MRo5ow9rluadWZH224RPF9tUFSgg/ByKrviwowUSUIgOSJ2e8 b3Xra6NCEMj7hy8ETyBqUuoHoJuQNFsNKRijzdta8yOYRD+snTpwh2CagpMcEujGWRBQAt9IdCzm udPW6F6I3LKkmsmCSlQCTHRcHukc8H636PHAkXtETglSOkhdoVhQ7KDYzbCotaMkv/xMXeqIVbhe 8THvIKiUtEo1MZlmTvvMXm/iCHUrjTaEc6C9ZjuWQHYMdew0dAHnbr2RwJ7XpF5QkyU4s3ccCxFs 8qjaU7T08gj2crsqJDVNi0ViV41+1pOcYUZUi3cj58+Lj02ExiR2vok/lN+5/TiefRDIYfGofDeT InbgrrGN+3dnRr8BQL+NYLOpmXWD85a9UYVqYD8S+2pfvejkEmFnpumImXh7+rMdbMciyrxoJHfQ YTi103vgRU21ZUsBxABLziP92zWM/G4BTub4oQgJeN90LjB3hNwsPR2kOhu5yr4i7942tW5bq8kD NDG0S+91QsVSNEuSvbt45/VekqOCKN9G4DNIjR1mUVG0OV1sdk7fBcs8jbjyVyQJ5dsfxAJx0eAI pERN8WD/zpuggP3JR9drL9r/nG6+d9CKYm2D3fbeGHeuj3kJ8zctHONdohRblz+XtozpdUfN548F nxMoouwsGpWmrrSyJKic/dJxDzKNRfhalgByUJrgRzDCCWueIf6EDJkBUObcZUGOjEh2KK1Ukks+ x+LRpBd6Z5wRlfPJsWiVz5JjgDadvyG0T3k+LQBBsm0mZH428Td46ZEH6Yxx/bd2zz0r31dVN0VX glP5Ysfe7uH3Q8QfJhcikvj+/7QF3UzoZDlHN3PH5KfNaCjs7fYqtifFHtNhdfMHjjElyYf2+nlh lfCQdEZiDv67l9G4d2eZGsbI54SLCD1nXv25ECGCA27i4CYiMOmEqWIXc60EK96uGaQnBUytOLRP 9SVyrrhHCJbiFcsTUtV1j+t/HuWg/9ae/utTf/Rr21BFsx4xcE1VXc4GSe7efB908bUacF7pdDf2 iCWvwfHya2kp7TY0GUbClM/BwF21p4gCkXZydPnY7kC+0z66RyHeVOOHPm/OcXiw58qwwwgxJ2SY uPHW6OC9HSGfWKXYbzhmidvWZk3J3/nGhRPeMIGtuktvywUQjxJ0KQ77bEPhd4SrhAH8uqavZ+IY 5wx8ZOxOAm52WoJB3pkyBc/2clEXHMhLzfyCJb7nk5RUPjw5XvJtdYch+ggh4gate1EWUxYZfS8e 45Px3arMaVA7aUN3L4TZbMobxAbokT9qcrxzy0UJXs5bVxnMfzMB+2PXPNVLWOTIT00xs8nSV45B C3BOKfkGSOPDieS9gc1W7VVUnupPUcQI3uHpMf0feNmyMqSoRS6tgtbFUDhH8eLs7kMUYMAA89uo cxsR79UG9Kf0JmCyKftwkZk0K7an6Uxl4lTw24D71Ys8yCxzVVTeoDCz0wyhyXZ3zEzUCh4LSo0x FYBkHagtm3pcs9iol+QggiJDOcB53wLrY78Z3KILAp2rPy//RC3iSbg8aLuajSoVonMA4/+IhdwT bKwVqML4uqM9nwbtTnPS/IotebEXxM84TCh6E8MneMuLiJ5c0nEhmb/XOF7TM5U3wHl31s/Ta+R9 eQBAMG+6x7Gm+RMS3OixCRNKiD9njd6UdVvRjkOBS2l8qvFXyQQFw8R292///rM+0UkHOEvqtBHT nBYSVLEgVGCEOe8oK1WMjAij+elgMc6p6bREhdF9rmWTZXfGBh2H9HcEQj/TS7UAFXn6RVyDFfA6 DJcIXe0hDd6FZ73aWiiWd8CkFhZSAcO30PQSR9SMWA0LJhIVBKBg3o//efQGs6xe2mPnHb8tX4Am AbK5OKp8W8a9+tvj4bzU5Ja0+pYZ0/mCPqb2tbjrCoiP2al+lvblUC62Aa4TTdBj5POZDKzBPtTI A7bVaymRa1xOYPdaTHMf22q1/xudnVs3im/MOMtL7t073jAia6QByb2j6mr7bl++LT/2VFwEcTzJ C9PXhY1TYhIOGarPWEw8yEWzRga6lD2gb9XUATBiiWrI75eB6OvPI6MGrU1TxDZ1z9TO2PfW0new C6cpTh8vDJmTGcNSyuu3TARcNF32oGeIVhq7xJd3UA5Aw3TNupaWFRVF7ea7rqxvcJRioYHFbLWe R3fm2nEpNhA4IXA2Yalh+lGj4p+HUM/1LqlQtn/k2SsSKfu27VPnbY3K+GwZJ8LxrXmHVhg5jrEo aXTGNpSGWfvIrkPjMiW3cy9w3Pfe8d8xITksmqWaReAAsE6sXl2m+qSzLwWtmJHZlan7JkkivGq2 hw3/sV89iVldmIHivyM2iPGW3POuuaqXGBmOwl9/j8PaSo+Sn1TIu5w0ewhsoX6Phl5DtJu+tKOP nzQnna6IQlq5cWFFd9zyQMQf0ZXST7OOl7fLuCBxSH1yyEuCIcSG30gq0J3cwO7ZOgVZXPsgB91C a1F8tt0vJ1m0tM++LjShh0Wm9ikv8ftwU1HjTfitFo0RLRhSIHR5Z/yY2IkSA6TYxZnQCF5vsJ9t 86bXqmC04MY9shmmy7sU1xcmud2DaIVlEfVfDyBL3GHszTzoLk5jRnMAyT++D37LUDTx8CUXyEYX Pb3pFG1C9QRbRgql52OlX26b+P2lIS5OBnOQ+FrEF0abluiQwJlz2A2GbUcMPqltjJUqmdi26RCj y4b3HZcpWBgQqmsKOx5y+xxOjKAZYoIZARr+AXZ2OV1bBEO9KTHDsqoN52MQ+KSBSL++I4BMOcHb chZE8/zgiDcGflVAurl2G6/IXLJ5vTsKMN7MPnQBDy93AZUFhCJGlX8+nb46ocJCx2ZcU/FByAMG Nk4oI+ukLuHJusGxohgF6cb11RCggq8a7IEZhJ0m3WTfZmEfbTFJ8FkoTW874VTzCGo9o/pFwaMY fZMc7COqk/jO91RD3/ZaPSgGxhEDneJQZuBeA1JtYhE9JiKmSZfzhC8PQSASI6d2/uY1qfHsGXn/ YkERhkGVyOpM2hAcSRHQ9L2jQ/6N4DHC7UBVgfp1/xSHcvZNKzLF0Xnhjh4Zx2r9l7Dnr+t7QB48 ZKlxOl8wG21E8b6nvrgJU4isSMpygu47zoB157kAg6KLMnNDm5vU1bS0hNJyDSwnvH1wbvYIPQ4x FT64a7x7PbkAb4plGoDOaFgp7YHXBsTSoqpyftnCEC+2R27quJVURdsQhC7bqzp7HX1b4XW3JpjA V34ESKhqjduHbu0rV9060k86TW7774qBWcpjFranNEbVorxYLXvbNxbbpqBTHhvCenS8WT2/VdqC +xNslFOZx9e5nxAKUFC+agOdW1uICk4Q81wzc9qch+cQ0idJ1kAhELs8Ea05bSRbSyO1+LYBmmTL jT9kiDj78mNZB9/1kb5HAjIUuXn0GOA3SZ/JvGdU+wbq4AZlljYhpL/m6ByYzg0VEdLGXA326H7h q+N7ksv6PfddZBRkyCiqgABJDZcm+oVZRk7trP0EKtgbz9JT/qiFVGwavvrvh6hOuozZ+/RY5BNz CIG3CwMSusz6zSk98VJafd6L0/XwAahV4fcjh4Cx+KsR1NzxrQHgt0Os/CNcKOig1/JhxkDL42ZE 8XqM2zPfVCoztMWrTWZMCtV0PRwbhWxE/EpJPzQT6BtDoU0snQHGrvC3nGSQj0IghYTT1p9wLCV+ 9OxUEc7dOYgB6T5EEaNnpnirYMBkEbpM5a2EQMSz42WrJdCjFW5WuNX+a8HwjwkiO9Z9yKjk5O/E KvKx9yr/q//CJhP/VMTdG+OtbMvkQXDEAJfHtYlpQIzQSqhoI6LaYEC4b2UFy9487VyL9G+QKFPQ 19zLbjFrzCVHCHwSh1HYchmdm8HsAH+uuvmVscWsHv9gbQmeRg8oHOxZWNd4Sm2JnukU6P8AgHwp tUlJbtGtWD4JS+EFWCGtDmzxk9MpB4iJSvBQnh1lc2zAdHbAnf8YbVoRlXsfpm4bSLtkFNA4zOSa Ys0wj3T+T11e0/D2wz/0n5g8n/rgE4Pd2TPoUW/PlG/lLwEryvWrqSUPh5RxfwUew28L+qfhZDh3 gAdUZzY7ASzRwX5NC0xI63oNOU2v0y2yw23/QT/Wzca+ge6+LG2dXYJSSxLIC2xrZqc+Y6D0lBfC pAkbDHYJBsIp8Hxye6nA2TiE8H9LVYJCe46SA0PUaYgwq4GxRzeywGbfu+tbveJ+7S8pagvIP2dv CYIduOa5fXANzmvzGGZ4M53ZfmEA+YXqUROJASPB+pCYAIcQKQ+arhRJwb3KVRkJWe0Ql/bnWpHs Bds0hHTy1mw/QwM4DvHv5GiD21gbxuREOjrwvZaG4CeJE+SHEQ8eI4gONkvPDA27ZlZWud2zHRM9 FX4NTVFUYSfhNCxlRju3/93XrrlfX8X/bEkQmd8u0DpCZu/9AJXZzEhBUP3exLCvdS6txflxZK88 tY1QYU+Ggp8Zs/TwzEayvr+Y1lQ9Kh28ERPr5Y1AdoTgXEA1YWXWy5tBs6RSktPMZxiM+5xK0RVp S8L81a6jyC+ngsOHK8tHW6nwq+FYCVTImSYUypSgBfdQYh8CUtd1QN/k5pV1dXy4awAfI/DK7/yW 0PYg7BCtxMoTecMy9CmT5G+VOdTmh44W9Em45OxtsqgXzTIBX195Dpb8knwmG11CL1rTPHsn8Eip bk8fACqo1B0Rv+ubLzIqmZ1w33mi2AimJfPNn/wCI7Y+Z77VyLoHtbu9srUSQtJSx6l0Q0nLaRI+ TbShn+L+5kUAY5KnLty9bK9Xqe59K57zKhmWyzfmSmMGm+CehPclq5RvNeBNsdxUnMRylnhogSla G6GmT4JU4dr2c5KhH2cWOorPmmf5lRG812N15eBgYmOfUUIev/IL1oq+AQjfnGqw/cuuDqb7iIDu 8E1BCyXetLV+vkoZ9HnYHmLsk3Ze0loc/WZREy5LEPhH7UqsqFyhLCX3i2v2s/PKe5q4EfVIr+Cd Xz2n0GihZHJFDWJ3pC0/3MmNYFJxCMbsglAhHhA+1ObzvutCzrX5tFh9ZUWM6xg2aNiYO9AeR45l 7ZcG1Bl/awVYjmJAhIHCHRpjzHnEZeQE1LDN8WK6SsKq0v67PI84ftFr3PvRqhSRU7PoUxZD2sUw sdB9CWwDOuqAozNPAWrFv3dfRwaQVtnUdhWjiDs+wIsAiDb2utv2c3i+ol8EEQOqtxKqjD54lqG7 4qaMwmzEMfBx67Fh3I2a5UKGM372xtNsXSwb4GC/ErDF8ErgaQhLPciVbXwKMtfWQgW+2s2qb7HV h1v+s2CTZNmvuMzbfklqa/e7V//Ng0GU62E0Ac2i3/6HMVFAuP7/Vr7C2hyGLT0g0Qs3N2cg3f4p NN8v7mWP4jWRq0Zln2AUt+291/PWJNX36qquqqz3aoWjS2Z3bgqm3D2xiN1DoTeFcyDQSj90K9hz aQqkBbiIbgPTq46Xzz/eJ1MyOUClPfYAMNbmrDbArsr7gaEObiyxHvlFTiwTHB9JSvccExG6eRO1 tZppm09UcnKq2+rMzEEr5pOpdA5EXY2iuPBPn5kEkpsoCzBuXON8iDszxA5hCwOKWy+0QnbYIciQ GQunfh/ROa2fBgDHFs5QW5SzCPX5DqQ5MoEBST8vHVeHJU96d+dMXPhiIQUjBmNt78sektmxunzP 3+xOgoszVOOYcjI2HXQVbSAT/R4ovFp1zmCAPirIIGX9Nkpt1kcDlGJgu5JLuFZs521Cb9Rl33PP x2JTn9qX/gx6S7hCK/5yPbAlXEPA4H+Ukk50UkC1lmAPP+iblUKcTmlKShrrMdAibawiR/0Nukz7 5qKrMc6/HldWaSyTYtb/RFpaYKhQNhE3NA1DrbR0c7SZ3eYx4DyAsQoMC3DqCZLNN17zE943+36F P9+yHNEiC5clZ43dR7qXpZ7suMDXYy2cVcTHutHnLncPdojt4zZJ3yONYXBhpD4weUq3IhRwMjvu ediX9JBBxNUGXbWxmESRp6Es84XJwbgvDQ6ZyIi5kbcSs81qCE1xgIDRUiXoaFTuiRZK3xMDZYC2 qm2Tc1sRkZ30f/yu3Rbkm+For+XPY2YWnXFFoqB/S4y1Xf8igiOxsTBQqm3QylShcksYfmRLSWis yx7XRSSzh4ZvFJg7FOj8FcUYbgx0FyuL31gyxh3TmtfWZxVXg28OobEgDiti5HWQfq5u0fQqPOpX NVeHrOKG3HXywarvmM4pKRyJmx09/H+BZYMvDT4ZV2v2dapT9CS5XjR8UUrStxcgO62XtmKjnVqw OPdd6pADaJBX4J7dNNa7sTRfv29F4Q7VLnswMXZPyuJA5zps5KgkL/yZE4zZbKuI4iTUy3nWQX6c SDM383Z6s7HuMkFXqIJ0LOOgjzYW0V17IJYT9mdItIuGoaXBHqm0a7powT9HXHa3Hh4w4p3ik/SX NbMIPVCEj2ccNqNiX0wKIVhhDyGBW9YCU4zTkb5EkJg6YmKMf1vTBCGdguwArzKskSgCJpEr7Mnw n7QBTbPDJzoZCrlPl76yOBDKvOz8UYlO44bgaSQebs8zHFDlTMxsF1iIPQpoVGH4PGm95RL/Q5ZL 4g/g6g+XFfgvdyrIxntKTbm/PbzwTUcHsp/UADMf3u+6pXkvzzcS5ghcRgL6yXGiaJfEwV9uD3o1 /5GDoftHZP4WZ9RJ5gK6XiDYwf9eFxDZxppdQ7z+jXnOR0UhA14Mp0wWhDK9ONZCVKICsi3lI1SS n3ahzFgvxoQiS98Z9FAS/BL0lqtempkShYAwHo9PNfU290dwaDQBFwnr4ewkCUFOC2rXInZK3O53 e6jE7NHsWRlAUQgRwiPNJLAM9SITYbP2PWxRb9k7wP2Mp2Lp7pVR2x9pMacdAM/BStpRT+8xpjHT fY+ZD4mLu0/YIiJBS1bLzIHE4stzzdGaOfeAUuxz7bxEvSlpBCR/0VmczQOtyD+OIasn4dXnadTN R2erj4vlNcLhEeKWMdm3OyD5RHKsBx37rYkYIy1M0Mgw/pPzbOBky+qLcO5rm6ySKz8WCnLczuQU 8N4CcKiG0QPyGFGuqn7pLttC8gVW2zTYYY/zIwt0/s0FKwkDNZwdoegRgHaTmXvbYItVRqq0G/kR z+7V0tqwgCX3hi3ZvuN9+Ae+zH/JBiNc9OgC/cVqWbNdLiQ9TcZVEgKPMeo6+G9XpEr3NQ2IzAnV 5nlYMr6NjRUUtJnwmnTYjyL8ZknSGGGEIEEmho7tqE1tG+XJkDlNaAS6CmO8yc8Fvd03NKG2vqrC PHbVPlQEGERW/w4u8yuW4myIdDC+IWHx9EIH3HdkvcWYaGJftjGHA4Ndbnkc24zwWfR4NHzqtwLO +nbsBo/k7mAsZoBycmR+S04ZE/56dDwedI8VcqDgLeNRVTV4XF46qoQ2CUUStCG68E47qdIKUa/Z Z/ySsMN3kBk8GW4aKwn0ANEGfjeCrXzZLBEZQy9ouL5sKOJKw4+tka951WmE12g2uVmMlzUqsplp SRbQGdiWl4FWVvIeMRyePHbUJPH77de2ls+QZlUyvMkySkFliy36lyTmY2lK2XHnvSdTmq0WEGhI gAQFIPUIWsNUbtOwaAgP+70nD+Q1umDqE80prv6rAScYHTz+6IFJAagpUFouWu9TQh0OPZeUwBNa YXhlS2jGrkKbVjXdxkOlOs7N0gPTGr78p2wuBgYR3bq0rbYnNro6decxvReerBsJCqpplypl2Uhi TGxc9gS3GG+wOK009FE01UksSnzdQoedIgp1JOZHjgVCouOnThEd+wuuG6oRErD428bh8RuwuwEE eEJRLDqJammwpjjx39EwrAHWU2Nwrds4SilCz7uIBVOo/9WHCyi3BXwRNZrtGwhKiLzgSrEVBh+i B6GOrpM4fMa8237zZ77SlhiDs6gejKU5PtvOsWn7uzHfBZkuZW71ozJulFGBkQzUdbM+3HAm7KEv k0ROPVeXsXY5ZGuxopsTqCWAXhJ0+dTtbHB3DWLl/ykjycnWZ89cpxFd4syeCUKWRc9wGHb+JqJH p9/Hvm6f6YTfbAQCqVvouyiL/2Mhax4O/pzzkDwk20gypfpqjLfw/AFUoP2UTfx9SqzACUhia0TZ gBo7sOmnfbbwzL0pf1tlw0Lz0ceNYIVfuUHivZrs0NGQbKen5TLRX0ArfBYDw9fB1vGQd2TM6qR9 VqZmLDddlk81Q5IEw/fKR+gv0RgyHns1YfsWRGgWidTbmNOBohbVqLZgSFl8P3uxbIMpDWvBq1Lk X8WQOxHv43BgX4ezopWmv8XwqymTU34QUFgmXUp3WqM05kjmY4Xrp7b/g4gDuWsYikwyfE6lDdUy KwH95AtkDcUBurQ5/Ho1a03SagomdCrj/0J1KkmQrNK8j0Vou4QqQyDOKEyDBshkXfJTMkO+J6Q9 /tcsU6xAbATdPymJ1OVl/h4q2VhmC/5TX/g4uLhg0P1r8KYnq2YdVpwmx53jazPH868lnbUMLe6K +5D2sMoKfn6etBCjph1oOb9mCP5+oetBz0neVG0I1zqtLayEXLFd+RuhdWthJrU4ag/wrf5hfq8T yCN+XVHiA8fnzi5aIREm3Jc6yb2cCpQHElOAmm2kNkzq8uU2GQWR63l9UfBzaRRdmYq+c79AX+lf 07Ga/Nd2gcJcAMJqa+u4GbJxYj0KNLWtVPzNh0hz1nbLlx0AU8WV884nMRqD7wryUxWNb6BsI5PC gGdTVmaO8K9wWv7eUrzHcduQJtNFR3eTj1/5B1cXbJw44qqPBqB7gV8SgSpL3KqsFwAOd/oTEurS I9LXA9S9YP4NBpPyiM7nW2uvnktVdByD6hz4xt2ImHow/ZCPAId2GhhgRYpiQKCMUxIA7FcNYzYb in6aeT+htOh1yU5Wa/W0HqUSK/+J2Rb8awI9OSHJ6XSBdl3hFiqj/aQPl8vocZc1kx6YOCwfS5fF JFUBCcGj1jqps5EhiEEPHjKcCNJ4d9InNhLGlGOg9YHH7i8WiAZoDARsD+zC88oUVUvMOJSivHRX tzht6kKEqNRvUpZEjJ7gjadg07E3AWg616Azd6uSOlqXZzXtrQ+rnXoexRyf6XSzvntFDuFdj/F+ MfugcwnWdenzpZ5fMkahCdu29O2wKeMN5LqCpkERfA81ePKyFMgwMNQoWjgu6CBbb6YUfK2B3VWg HXi55WJ2k4kWRO4Q/g6DEhXIujYtv9jBzfkIt3OtjoeMh132EX9S4pKB2SRH/MBs5cdwSCgUmxOy cj08VjoNqZIIjjqVbOkYQB+ecfv+1MLUn4MVyXT/+sLQoalt1aKEoDObkCx/bj+h+5/4cR6lzCQn /GX+xsdBv/PxS0W4gZS0dD7GFr0cx70BXSduxn4RWyxb4N5TgBS86cIQTOvCxpxPN+g3CeY+IGAF gj+wVyTbwdw3CzVrMo7cxRic2KAh5b1rqc8NBPEj9aUIb0X9ZffkdRex1czcHrrWCvWt/nD+0Mhr LfQZaz9ah/RIbc8nP9vgvFM8rv8KnTUEXkrH/Cm9skI5WQNb9xs6MQ2blK86p4hckF0QR4Mi7k9J FQ25SXGOI7A9kFY9vmF0VYhH9xR5OZHglAfBkHYDdMLzFE24pXew58CG+4VopZ5UdTbSnQA32YEw 9/L53M+Nihqwv4Zj9hCNOuY+SGnWmHRKaXaKhyqyL2ozZpfTreyj1Jc+t+iiyIpB8fs2Pk++x7zv nuLrTKVqGSuZofksBfLLt8+O3hGooorfTcTQtIi/Igjrh10k3gvdoSGFFTmkqdTUHnFolP09n7dw fWooppKZeAiImTLqdsyar0i6YIy9I5HG5nrVCbfux8g7d3vH9BmNpgHSRTJajFGqb0Sz+G07col1 i2WXQZ0fukNhjySuRkypy/jjSWy8AmcaBmr+ACF7VYNTkQc40EKws+Xk+lxcDByH/Lz6pODxWo7g lYK6BEnsO2yaCJeO4Wc7q+EokgGYncSte9oOw8EtuiLR8ALceCZ2s/d7U7WwESahqnJOjXV8fXgd 0G+GK8A97Q7QjtbaiOCg9rzJZqmYYSWuN+CJpiPUsV/OeXSw58bEvvvPc/K3SV7plmmxAAcuRh2H IYMafr0b6mT0o2NPgx/lJMZq1ZnvLwJo0vzzllCQm5pF2sKgF1BZtMbxWQQyvgkCymyldCinIY3Q O+PDPswUtWAqbqyMPymzI5y3K4kxrrh/MFQdmZkv5m85lqEkB3s+vn0OSdbnz/ckPbDlBTBB6qDo 1s4oY71ds+Da4hA1TeAv0caAv8Ul/zyooC4DvwQ1aMQm+JOqc3Z20Q86lgbX+2W6v/3Df2iyCh+/ UtPUjHEyi8sLSSbechCpkxmbBcphO3Bzd3vklvEpl59srylgWACicAiDiuTbjueSHdxwaIvTOOma zN9JmWlnhf5AQfygYYLphE518D6KGqKxDbg2S35U5LUkkdr8vi0n9goE4JzzTe9YwHcUImzJhLFT EET18vho22N4LpAADD5cUlPNAU7sletLQ/FtaVfLVK/MMLJw64acets9Mz9GfkDuTfxCizSaakP0 USNo2mKnGbXsGMfVQ7/zvCONQBVaVnj4AItM0M2kXJTzbW2naFbwRQz6YdSa7gM0ESai1+z9yD03 tPR1MBTuIoAaDyE3SM7lt0CW2JjD9Zr+mXQhsoGNTMQnXKQPwYNK9Chn8GSsUKHu9DSoInX9TfD4 gX8lHaijnYWtVqAjHit8WHhhIgwNcQTVW/4YqL9I2QXxIDCQSPka7Nond6J93Xbgzn2ksExUo7d1 Ztv6Yt23QV61tfGUtgZ0ywwyE/v02xZgRtXpJkPo2kZLK1NUBkIRlCbTfsEbE6kr2Qetkdqk7aWc YPbiEexuh8C7tm9Cdf6p5o/NGR6b4hbpbOhHpDA7nCm30nNh8YWHVPQO9UZS2SgH8spZck+RLRJR fUriCR5fEfeUXJaXSdSflLlxR/4Lsgu2+4Oc866beMGDx0o35zHsFt9XHE0YtEaaXWTRgJG3qG1q MqfC7OtuQICQBsOVuJIWGarBx1cy3Or3vFoCCCYgE89ZHuue1qJo9CZ6Uce+bcCw+JScJroYL1ii JQT8vg93BKAWns1Dx037K9fduwx5Pvu3jVmaZSXBkUab5FH3JLgR4fchNyDHua8Dls+BZm81uk7P +1wC/ssILJB9EyEs6LvK5IUHJfRFZEOqVm8Bb+dDBrwcIHRY3FmbuMBSwm+QLt2eClg0g9rvVzGe Le2GRHyWe4VfXgkjr5NQhMkRSpF3BTCTUY0m3caEPavSveEq8Vl5KQVf+YpgharPWU2g8NBSdXxi UkufNDyp7DYHugsZzEPU/pXqGXAK64qMG41Jj1ZVrJcmkAX7GwZFxKbWwVZ0Z0WHZ+OuJ28SyRAC kchj11k0QToKwdysZiaCqk00uvNohGBWK+uVuq84xztjsZu8ZGYyjs2TTb8mEjOyIW73cRbUm18d wSFO8OvXvkj3jNyjb42SyEn/t9xTfvzMT5X3WjDhBv8Oikforb2A2zd0u+t9/7FTJLanknDZ7CKw oYv/PekShcTE9XdLGMljLTr3WygnCx8cv5uqzXriX5NZ0A5DvTETCUHrCMcdfHKer7MRievWt+Jb gaeg3RPu9eldSQ8/Rd7mGivqna3f88lj9ZY5CfKhQhbfjjJMNdpZt4rdSWw/InK2eWAggjhU4zo6 yKl9CXLtNfuJ1Mck6kX9IUNrq471hXuYKAAh97j3kWM5F/JjC4sqgi1aAHDBS6pBgWemikNIjax1 3YvJVeNxjEl2+mNtoyGYfWDYXnzUBi7fKe2Jp9f1ev9AzaVu421yJcoeKFgQCtDoyt+4h4m7omA1 ZklAYYFQq+jjoo7sEdtGgBkpoH0pNC/WqPIPRHipkVsRaXTX6JPnF/5sc8Da0+2FVHIiIPDZeqw1 qYoRhwM0wYEh93v4LIBQNytjrp3h3SLiYZzDEekdl5evTNGeAiSF+QUuN0dBQ6poKJ+vdiv6mN9L xo57+SfCqBiZJd1v8uadnXTj5U5AqSak9pvobFPm7p/cgIzrDFPHg+wLlI9ae6EWSeGPRAfKDy5o dV5nY+hB8xwA1d0uj9pvtAzFgXPe5QDjmdiJgyibZP1Xpyg4D9bIY4hzY2KqrSBExKpMGGvE/Uhk Ad9AvcQXj83iVSG/YkXgLSf54BveYofH9FuW+Db/VH7GJfzK+t2JKsinCirF1GeIWuZqw4qUGdlR PESi0OrqvFr2ZQlfYi+2eGfG8KhQEhAG7J/zkvzFFeTtSs7sQ5vFHIQQKHSgEPaZM9FhR9HpMmeN DuotAdl8YKTIzdmMSVbypaxN8BdH5augSRR4aw+JEF5UZZgRVHZ4fzezDl+LjN12bMet/DX9yphF INQV37im6s9yRyVSVTZ63x9qxmfmJUuh27zzqUKuXZM57qKie//HH9Mkls4MMzCpCFaQ4r4RS76t tpSBD6z5ZJ6A9snBUszQeZZXbS8vs87Yd8z1wnRaakDDUtdSBtZ10UNRifRpuWBrvz90tseAafsh Rt1fJp4cDxWmOY697/9CcAVl0Bc5WnrQmMXegO3Qj6ASLdtPehBj7zrRXLF39N8fXZBZDMf4pnk4 qZMt6phm8PblU/mpTMtANWtzR9bsqTMX6ZY2R9JeYEqCjDg5h/6kH8qaY+yVM5SXnUwZaDpFffN/ +7ce+yR/2TlVaCfCAYoNmCrkcy3+2biMSTtIFswg5UJ3AFwpY56/vnGMw/CiR4HibBatN6NVnACF OwPOpHuqbJUkRSlpz6+caXWIXyARGdSEYK2iCb4c13f6FLEgf0YAyzw0XamfNyvBKqelXwIaRraE rOgsk9FuCHtnUiI4Sipyes6wHOAG5/Fxuvl7ipa2KGG0DoSW1AHTM65yoPYaIMaGm/u49ovajJOn aQiHUgegfLl1ibAVbJidCNNfsgjF2ikmYuGiFQxgPfMoQncB/s51zYn1gl0zyNTiUCx/mwmASX/U cvdagD6vw6WVifu/FNiGOP6367ubnT6mMSrQJ6L1kglChXk47dcFhccQs5vx9puun4STuh7eLjSd A0V8Jc+JODLZO6NBsQ32RZhtWCanZuzDDjgkf+9hX08zzjgIDlHsCNUbJu9mRNXRdxMOfSODqnPb vdGGO2yKgi8IP/BTzPBzoFlCgTqLyvBSnXUDlETj2sIEInOfS82j9GWa6wgJ3bXvINNax3d9+OVw 5PWEG1D6RZlO4rqcWYgIYBfWGKEl5fQDhh8tmFpKWzy/ZwgVpdRrqXlRGnRcSLNV0kuxDm0j1N6b en/ADzfj5EmKdkN3bHodZH/AKdxQ5ktwcaFGtNML+CM89XIrMZtg4GBBJHljEAnfuGultLAdV3A1 D47rqkN/a9K9DRK5lKv6+sb9CiDJdbrrFy0PbSIHO7grmVS/juG0gmQW7oBqteCAQEkSa54ImZcZ W1r6HCPuzgKUpw+XvdVc8v1bWvCOuySb7N/2yb2m/1gh6Keo4Mb7+z1ews/SmxlKp+leof0KVFBr wqoCcwuqCUyzK3PNQ/a8W2HgZ0O0XnKImcPeWTkgRlBacXaC0Z8Bdfb6/Cu3ASYYAGfHRpwqgjje T74yg/1wSYaRKfiNIpR3gWIndA7leNQi5smgiePtrLkVME+4M6r5S07GT9Qd+A3WAmwTvQhkwsKe F33xR7n3GwxeMouaaaQmjF8/NaGQ36GiLRsfVo0grlmo84Up5N7Ebe4bcu0B3lvKzIPUQPnWOCNw lpK6mw64oTC56+3SHnbmwzV3UIIHUiRM/CTDgFHnUZi1DJBdu0RCIn/rnZa1s05lJgQrsRibBYxE aiA8BsgDWTOKYG8fi0Kx1gnZs/LQkRz1aF+2rdlTc4QfHq8apJyusDfNviKnXMLnQoI88jGDv8OZ ldv6JKUSosJd7dEawgFVMvdIBdRSHzFm5iTqXTMAwRk1qS9WgdQgmdi4kfHGfg1S6GXOvZaZ/O23 fkWfDDpWnolBwT0G7CM1FNkPYqgiADMxKVl1hVh9V2Z0OdxcMBTHqUi5OVg4UqwuSJFMAL24fYcZ Tl5nhLSxDSYM34AuyaMjHQQwce0VFOqBpZYlETuKojb9rjeWuUzuhe8w7VnQ+OkYA5ejzJka52WD /rmBoHjopTbWcssx+ZX81EwhpQfxikxCLEStWZWnSBtNjx4bSb/iriF8RcwiV+CYuRnjyVLWjbup TVpRbP3C3hw6jWrPtIWDJD2PXzADrFcpdyO8yayVrPPPSEd58PKxDXYo4Rqg+jBYouyvOIH1Sfga Y6d4+3AcLarPUB/uhBOapRnadRe6Mb460TRQvjpYypmQq6YtH7/hQj3Hn8QVZmJjv/lL0qptpg3h hgsa/GRpTlDIaBCOW9Vaniek8FeReach4dqOH/gWfXeWhncUrd+fzho0zMdnp8DAu7fO+TN48z9k iyDqOjoZ77GIllnXMxEaka0CUgKf9b1kTP23PSRmCaOxjCRfrqaf2EHjdLzXKnCC2/fyj9MQRcdZ 0A27v/1wKLjVcBTr+jC4RcRbJkdhga10DvP0SSzBJL5sRWEb0QAhB1aQpoBjD7TP58BldsZJRsSR v2vzW84ulopKc3rpzZEBPvCI5F00+yh3nv0PQBEusj+sIbBdHKaRTBU4STxVxp6w/8XJoBbobj0K +RnjhTNVqtsR4KXsj8bDSD6FT3xUgeSMq2ZM6jNmnsmCCBVCqKHyLZdsrgxiI4ov9O3astIx1nX9 6akUhpWFJZ9VJZ3BUSGCksqx2GupB+qBMWaDFw0HTtOIOr+hFqAPzhJLyaSiOBGkava5PdoW8l36 Zv7oLaLZPyF8c2sAGa5aotgSvWujN6WGhOPyeI3Xioo7hhW4iumfrSHctSDaDyNUlF1Fl4/mEFR2 RzL68LK7pQAoJX0R4oaUC0rFwUlaH8sy9dG39I7gsaEl6ZYgv7elzPn8YEMGtVlJu/a0DBthj/3j FLrI2XkasGOlXCgNrRaRuvgAcKLS4pLi1VdPCqT9gFFd124SUTtlvI+uaHa2ov2NN67WQNuuDWIi H09W2JoW1I1KcG9yFCBzdgtN8jZrmFmdBzE39qRvBXCNb2DwAMh2AitCnXYOHWR9i77vicnMm4A2 ag2UEZzW0mqZ2GCB0eQxb2QRqceGdut/1BiSKN/MIa8SYuAKnE7/efTOQcRH7ZIxU9yBDY64PbWl o3ib8QYKrFalRyw/3YS1yYnCVO+TUuUXvPliFnDdVtPt1/4bcXQbg9a88oramiWkEh+T1omaXTDH qqEnfA2KhdxZpUtIPax1mGeFI7cF3zK6r2oSwNUUXs8vhUTGEa7MUjFTVZKQnO1hms2QMLkZhUrV +b/zcqeCh38OLV698tKdIjh3sGw7OoMxYsUpxH6/dgj0ZQMcC1eb29mmEyh5ckKToULCdv3bQhd+ ENeuso9kXLxdeaq16ispffzW+7Y5cnQOqzKquoqBNCepHygDiiivllo3Qwv1JmgtXxRXB+i1J9e6 /XmYsgwyZSqKsrbaIe7g3PLEBXbMAIyDkf9GK5HvD/CTptXsAg5uoJlf0zW97fe3Hqo0wtOlBE0E wnsqvzTmJGxmDx/zo3em/D7Y6bIRdvsGD9pFSTyiU6+AoezrT844wD6ekVetbgEmCCuyEEn80H5L RBipujQPP8k+FHLgpCKQpZ36+gTdHesUaVCKwO3lrz04OZixJLfDecDeoudMx4x5G53RCLN5W6+h BRfGKweZ0/Eqt3+e5KwdqUMCojsU04Qtrnf/X4EpjLvXeJzGAKwojSAzmGgSMxpl9qSOqJvsav/1 EzsCyouv4hvqUdZtzE3G0NKMhh5oQA5evZbiSlzIAGBBHYVZLSGDqWXmwz9g6UK2ZS3G6MG1sVB6 IzE9T6t12hiQZ+/Zcq9mCVb68ogNiQf+N3bWnZzdxLxqsyVtekvHCdGw98BaxjBqMiMvAKrHb9XU FiR/gGFnQJAKaSGrXpbMr4ZkClmS92EjFymtYre0nJyilCTsJJZ1QvovW1qsnYiPTmCIRwFwvEnU Pn9N65/nk3FGsTUwADq2RLl3d0pCnYN7fdZKrcobijBv4eJAt96z6pgQMVX8XkoTGJ4/BhLmhMKH Qh3qiTLlvmPbdLhi+W2T6yWMRe/+mNeKXTy8nC0mdWEOXbYZpYF44U+KcMDV+31ZsUR/LB1PUod2 wSH41Xz8KUA2ZdtJQgK3ZXo1+u0vK115e4yOC6JH/w8glTm1Z5qh6ELV15Gv9Y1lBcBqCUY01c36 vIDCJieVDe9+JxkU20JulxH07OUTclRveaBWka2+L154XdW2Y/NZiSDT8JJZNYkHZRvW/6LHtMoz UPWcexzv8OfESoAzKpfqE7FS5XpUZpiN0swJAJ1AMQIghKk9AZ5KXCBedfTVtzKaF/NquOt7mIwY vLDWqTWVmOpWW9oJK14uCPnRgI2NYhRmmsgwViAaFiP3vhc5+owKoh0WQmji2uROo9n5k44RLhK4 tBRMAs7rb8np/Z841m1sMB2aCed01gTvajDCh93tywjqeEETmWSAbu2/G9iDDxyg8Bj0WlKZ8Go1 crqzn4Z7SlwNjIh46t9cVGWIfTQDgaZ/4wzepIxQvZ7VJidkZybU+8ioW5z8pz+12Lxd+nJaTpFT ioBbb6ZbA4XYg5OFsechaVGyBuaRB2of+5d9ba7Mo/hg3f3YPm2r3JZuSlg7NLZZab0Z7Bq/37NN HWffnX+orA0pezHmfjJK9nx2jQ0KZ0fhTxlmbfgqyUklTm29pT6frxUylcA6yvKTmI2HZIUxzpxB tE9btWimm4IpoeeiJUGr+5FDGJEUAXqCc2ViE1Mct9f8aHBslcU0SG69PhSMPKSX0Gh49baxx5gk 4Ual8kMxDQ8Zq6Vx3odGdSdvkoMWaMMs9vqrvcwxSyLRqgP4ljr8c9hATzeqEAEMaTi/kyRrdLT8 Kt2yH/aApnEYStCav6T8tHRVRKCmNGOEaEmUKHxUonntpOMz8cYwVL6su0NMGx4S7Ztin8hIL2DV WSZNlyFjZjvPe5ZbMLL08Hfj4bvzqKCzY8sLNMJxwllVSA+3d4dRQBw1Fieon+X2xILlBY2UlQgN WWdn5ENPmLqJUDSP92uW/FF1jieIEhbfcBaD+BiOgS4x3UTualviIj3oN6XsHPyxxIWTiWFOhue8 XX3QU6Dx3dUc9Q6EgJsylxFUQDnAObtkrFe16H8kpTdDiWP3LNjfzkb/glmzOseJlOfzAu5k/aN+ Xo/jqhEKD7vtTQVo68UJaEtpAPK+Z/OxncWfJGtwzO6PBaHzszOgl8JlxoGE7qedf+QajJGnjon4 UJcrxd4/Qpe1pYJkdq3q9dO+PlI1tOSJE9XjsVvz8gYbOTDsuJ0oM6lpQYgqjanJIejoRvN1Lfmh aIMMqsP9HVzwEKDoGioBD17+BTeT+uBjGte++v4gLMM8gbof2yVtilJhaakL13c7z9G+GtNQZOfH BBuP3wnTkyXKJu0WwV/nFBxknBMMHY/6x6MKFoRlnZQhQD30Nh5XqNHQQLmMFoTVcUJmsLALdaE3 Mpuy2WZkOa7YkySjyKBoq35s7wFF8ExvDUvhRTcrwAnnYkwgg9vDxCcy7P/JgTPi8AGY6RFdM0DC rICjWmvOE1fbCpX2mdqJVELyzQjVU69EXaBSo8PpgBhNFbMkF0cxDe9ngEfs3mECUxkXv3RtafJ3 GfJj9THX4bYhtypsLPTCIm6L21KMmkoL88H7sFNw1ZLwlbfbUQmzUULL2G/6B77VAef2jt9/1pOz D67Xuf4kjf8HNdzn8eohd28SV0bktePo/ifOGLhu3ZScIjr8AzPVOoDA5x9z+yJYxsg9XTiadCZ9 UgpXAZAltXR4J3vF2VGkwBAlHpz3RzAe7Elkxd0Rp6VnG6Em5/fiWnS8FZ2qpOyiXAoRh2qC1YPD 6XSpWOCfBoLtaOv3SeZd04PzVkxycsyhm7cyZ1CEFngpilG3JOpprbVvPTGVU1NIv6ByB25f0TQR zLExXTBYaj9noc8SjlNGrfYfUHXJmfYRmEC5uAODujyH721a7cBXYcbUr/efrNoCDs7nZqaWy7sI SnybfL0aSPTNfnSFiW6uz4zXH6YiAXUc7lv3/vH3UrYpObG0r62ctTUMJfFcpp0bCppV9SLMhj3z VWrCwCoViIm2scr3NTXldyPr3q1cwYxgiK4jpBHk46ntwaZj4c7E4K0TRqwGUtiRw1UZzY1xhOnQ fUuoIJ2YWi8KddSjdB2BVIdGEpdWd8wG4NlwJzaFItOzv36VoNCR4XGQaIzFOIGacClwGyPA+qej n7zdu1t3ZP3tB/2N5J12tu51uGrEMqcnmu32kVDBNHelLgNwLa3HiB/zkLI/cXWIG20BGEsPsdTf j3jPbxklEK1mhunx4noqadlDNmSxAo6cFI7D2uqkmr0kAVK3d0zNBL5BTZ8D6F/j//F9NPNvHyGO RGDC2aUZddMX/jNWog4w/RaXx1j7+2VxQJ+cNmvGYCXUPha4DphXHDINe+4ihmB0vR9EXeYU0V9A WgVtLT8rIfJDOVk0aEvD9aI55sq9jXVupb62M8Cmmst1rlCV/hpxfSkz4Dw4T9v3R1HWff473+3t 6NEIAPSS3ib7YxZ3lyHnkF3GMArru1Nzxo8SIvrauwQ5dlyhxsJ0u1DtnD3keu3FQZgRI+jGURsu WK121h7lXyzoB5gLtYYY8fFh/nVuuOd8abO6kn4MRfgO0KuW158si7aFHfzb1bKtI6GxUviwkVJt 3Qx2b14R4MqbVNc7F+ZtY2rBH4K5koYEYBgZTdPHOGnn++4r+q0UAO92kAyHmQWsgFlqP4xQEKtW xpwNZGFpYVaN/gMBtkf+8KCIH3Japi77jiCgRpCmjof8bc7RlDAah9Pklfc6PwHUffnbc9hyt40C EHmHGvVe6VGXInpL2gStT6MzFpIknxXcfd7v2D0yEg4YEeZXKwGu2ewj7juEEawWDmixvR5/Eu7M ItVNYdIHU0COf8v7b75PUEjJVLOlGd0+Zxzzf1OGqPMXDKmucMIbTTZyempzUOdiXeQY3FP1AfK1 wrHU5nUE9LxmDOSZzz6KbQxrpbos1q4xnaRBu2D27oCa+vPN07XqCBCmfHZpvdGEPtkf49Rk8aUx fpt3mJGrXoDHV//hCATc2rkBeu//p6epEln0pR+cuAhL+hZSUddp/mQbMdhYn1g21cE9bTw72i5O n+rww9Xme6+jdJJwxy3sCMGeq32MkLxJj/rHSKIpmzz+yq3Qwk+tPuwI8E4ArLxeIGjg0eG4KCUo dWsiHVR0qTK/1FW+JHlR3PKAA4yw/twgux3iI1iEDi5PI/MF0a+oQQeXpXIOAVLsgl/DZ/qnqqN3 PsNtJLOpmsNhzgd1fmU7y/uLOXDdPipu5G1RKbjQVkpG18S8H7901b9PzHDwdqGrFDCoiZbp0f7A 74o+8OmZIaBURXfFAmJeKEReoBGp/8fvP7QxEWhDGm1SJGRrI/Xr6RXqbI8zyyY2CMMVPev0ELUB rvkG4PGAYVrEbkV3rL1p9prnH1U+m4xZLGDD1JK16Es1/sYYZwLNZi4040FT7a2iDWGSBziAcaxO AF1NcHsDGAczpXQqk3BTENRXM6uvrWk1/OR3H+Dxb2UXuUrQsYa3cSPFcmkMenOA/wTMJVAjNZFM 5vqn6gc11wwfZ9gasS2e7RNj+zFwYAznO+oPDjtLuEOekA94EUp+Uh2HmhK/44mB75CrY6su4d9y 09AvqRUbggA58u9uM/9f/kAwo0luNEjLBke2HzNcyahF+jmJ7NR005+UZ7kei+zVuOhjfcngBcDj 7PscsC484e0TXAU7NTamo7aliDV7eJLq7wlIesLWTeO28mI+qqeoX0BdDmySag3BY0aPdHOXSnR/ IItDbwNirIro64I0GubxUnKRZmZ8bwfC6pYkumntIk0IMGUvU2Ng2Ep1nVH99l4LUuSAr7ToetAE Sm9FgQ7DyZELLPAbBE17ViCkjBakSFtdujH6QXosBDsVu/4565RdThJla7x7kVqlUW7wK4G3DCP6 +d+LtiDvbVaUvzBB9mqTkHNjf6T3lU0fzcCsIB7D338HXweEly/NQbhVQv+f0MuHT3GRHcKiKrNF AmuiuTRtWsS8Exw90d5XkWVbzISC2ZAuxsKjyOv2Qft3fULJM+p/TTblMbGGa8ImcpcXzOQVZ8fQ lz1w3gfBHnMqVODq6+t8du36lAtCrUFsFgFJlOD5uMe+S51yzSH962xyzd/Ufm9TlAByLrP8SqTt pPTJqgSo0SHgFPov1ucNiF+WYm+NEFiBJTO75KQoAr9xL4pDiRJPIsivAZGpR4WJ4ygcHgjvU8SV c6nm52uxebsW0wLo6BZ7PzDN2OstPRetKY6V16Ryx+CHZh/pmKZpdHfaeP9fUJOUL+cjiDmjwn5Y 9GIpwmdP7ARF46exgzwKoMFd0XVZ3hUpqByN4q+5fhBiohbVnJrXsENb5yTqHb6I4k4pvPc1QTev BiHXWPtKXAFdMZc6vAq7u4HpzvBayneP23yso2zpFUcq7Z4tJ5h4aAU9tOGPhkIkaZyQJK8MoUq0 yppjXbUI3B4ILHD7hrrNd5EaIPVTFISMtDZK3XSnZ2X9bMVMQ+Fqq0JU6eu17+/qOHR4zIvBv5wA E0tOhfIvoFNYaKy0IGLh0Ab88u70FVJ/sNyoE4bcHDhcQrI0KLt5gAvehAQa14nNG6+3m0HlCY+9 mWI5/iIS+oBlBrGEcIXAfNmm0xoVQn4RXnFytm/lms+rMCQ7Soss78NL18MpB9n+y4MIKK3mkPpR u/5wkczhXZLXxBvjcUMl1IdSVdKTXC2yKh5RGeQ1xNfn7WCA2wvGQpqVClfw78r/ECckd+CtmZNh pPDyiLE/F1i+A1bg/E0YNlHzn01CaCgUpJVtJmOwlF75A944C6bCzF/gkSdaMX9H3O+Im+yxaj4I mD4HTAc6yt7vGaOLhsLORpa+9zTKsCs8Ebwy4bVbf/3p1oZfTYMqNZyp7X8v3AX4+gjvGej2zVHc +Rn3VgId0gklc3ldv5YFIj89HuXJPGj/5SEqy2sLQWi6HTiWSmoREZuX/uIBPBGfpdQbk6Y7ys+7 UX52bMyqQGzos05cCo3+eyOGs8PmF2WY30TJ1FbZ4GTbB8VoXmM0Bzhu1LUSUkrm8Bbwsw10LT2j yjY1MtA219m66WwPWMw9o/47a+O2gXcaJktNXxxS0BMMOYMS6sGcm1qyc7+3weqYDGzbpc53fThu AytadUYh3WgtYiWr5ad/bM/NQ9EQYnACXE/+93R0wvpUaBw38iy2oKPjUnpC2Tt5AFJpphR7T2n1 GYJ9B5JMke0jkYYlcFmzEtWx/BJqyPjyRgJexJsPgNRpB7mjfADhCWAcrTY5qdenxdUR+tC/+TFT CqBUZJE+S4FMi/rid074Q5v1Q027Z9K+zHC66qDh81DwpmsSrpI3DsQmpo9gaQG+WUL+UjqUzVed FivG+vHDRCxNvdzMd0tJFB52NQQeSD0MXEI51wy5psyWo/sPH0eMyqbeKDhUemo5axMyFv2ssu4x 8mSXILves2iaavxaN+z22icXHho4xxl3mc8oGDpu3VPwDhhZWvao0vKMstbubG3Xt1kidRnU7SZ1 hqvyJ4UFFZ3ZJpKGYPrCTNdvPddLW5Tkh7rdgnuDXW8ls+k76rYqK5IcayhysK78fVf3J7rbOmxI WJIc1vQcbESNunDfvCm38MpEkDZ3eIYPkGMZRPUcLcpNgjdd+TrUvAxm7SsUcJ88gvLlf/OEZDX3 XPp8uBFj2Gnu4t4pobwgWCZrLEk3qCHppVY27drtId1m6lggKj3uGaII2XspZhkaXkV1GF8h5ui3 VXgK/ut5vl7tVCYALOQXxvxiCZ5iCeeKTRRMRf6nV1e0MZ8EFVhod8leCxSE/9kWeM8TVK996IPH 9GZtKEu7wv4/dWImmNKSWI833A9eC5xs8S1ClLySbMQCNNkPJDEDLYiTtLSHY2d2BZHCiekJzs0O WRnhScJIfqhnxQcwKijGc/3w/ELgM/3PXdO1s0/KLv3K4i5ZVwVEAJn5BNEMa3lopJiw9kgO45co SHQv15BZdt3gjT6bEw+jOIAHKWucGdFuYwVsMDh2g0y85oH+FMu9jz5TeGIu6QDXcWNhFPFMG1OM +0+eeouD79/9ghyJNp+F/aHjeyHHqBEIVSDellecP3Im6tIFzUqVAXTQg87dVVngcnvm1+gfbn/M pGHQySVX6Q6bieokiQm/PxWV66HZZLwOYTgHK74rrznZQrNf7YIsGicImP4BGIcQty+gRtkD7N8N MbGA1Y0e+IcDGYRdHOGaGeOpnAXQQ7s1tLM1UUE+3MwFmsfTP5EokPRbuZ2wNeJGSwCAgSH64smj AIJO10MjBpkELshkpCcUeULvCGTbfPrsPILZKdxFPrA4ItFLZvOrwA5DLNd4FTr8A+YC+S8rijz2 2N0sEw2W1hg1Ue54JycOTJNFN/a2yQ/X4Wwe66bp3BgLHGEYJGDvTwvqUNw4U+WAPxGLscxTB+RQ NYyvdWaHH8Z7RLZ8anAaR4YUTkukyf2GIZEc2eYsPefeT2neFWvprekJruR6ZRgsQywlelEwGmEX O9pA2JaM09MY+bhORZBNuL8IJqgZC1GG0g29LlOfC4xUgUbnBW2ntIaGdj0PdXRX44poXTTZcBB7 eSUgyvstwDXACe1T7rySCZ6IuuS3sH/UYKHlRB1yWHxbC7ajL4O8JccKgYlg7uuZU7wj10/ALpEs f4w5AqxonMBpuXLPugiUno30s9NaWl5HcaGtQySDCGF0leitnw/DOpXiKyboYvFkl5yya2w/3G2v 7gvEn0Jwgwcz4OoNZiGIq2guNm9A/BAUQCaU2L3L3xWeAOceFqQ3NREEmTe+iKb6kY60rYzW88aB GZlBBtto2DR1YVfkCJloIHsGIYfES8ms/erU044OUn2heyvauH0sWTGMabXmfuFqJ043Uqr2W2P0 Atmzgb1IdiZCbOacDA9a65KFdnTSgoIem8wYc0XhQSsGyu5CB5K5Qj2KVWxBZiD7GxlBuEKTlmd+ KWQFsOLXWL4C9g+fztxUBsyk4pe00cpJQ08g1vzQZpv4mEz91BcTyTMp5UbLD1CWZZNSzVrY/5Iz 5zcn6PVY/qbL4MD5/KYRvm4uJnF9W3cpnjxNeQsDyIO3kDlCbBgHZUgG0LR4xoSjpsK3sdK3cyIz g9dweukbZJyjzN8lzZ9sffBI9cR+P4A4WYXgpiMRtIzWENVC1TYDthFJmwRGu6G/4qGCR5BFgepe dDAM4rRXuxJTzoOnD8BgJnIV+05/SU8IJVm8WSnfOlIj5qMyrNTYYQl/HlH3Mq6rf+X+kT1QEpWa Vub0HKyoINq8oHxqCWzhJI1LKGcYvvnfYjcn6lAuHx52T8Er9A5WrBp4vowOCDTaf7L9r6ZI4zNJ O7I0q4tGsz5msq6GNVr6SvrY0om1VQ5S7WgiLD9BKHaGqs3h6m9Z3ICHcBUenUAtcj01MuoRmZpJ LyDJCRYWKQoZggg4EEZdSC+BjnQBk06ejYccS4/9vjj+L3kX2MJuom6w8PhHIoro0l1qYAnf0Qft WpnWatGVn4Pwod2GNCSPkGjg8QZ/XAVR903G4Q4cALdzxDRiVsC35N4O/XZ5nmg51T0i1SWMfOeb 4XIh3++i2gx6MY6eklwcyDpODs58APmSFeBLBKCBW5wUgd0QoI53CCH1ufOjE4SRiBten00ITICh uSAt4lDEeXBDoNVC1v+H4sFOo0KytinuGNCujqqlKiqJ919ZgfFy1LtCCYe1uosJ95X4GB1qOegk DTgEEwLD62eRzuyCxOI1XSjGokjOWp0V/OEMOjvlugOYg8Tk9bymU2BaKFMDE8zSpAIU3liQmS7d O6Irwx6lmtgX2I8R3f55PkZfyHNTz+dma4SLA6LyNXQRyVeul1SeThpqs20Ib2HCDu0iOUmXrHnc qrKKAyDI9TVoaYoZJIhzdgHJr1oLJUC5TvP6MZ0XdzJ6/glWbZ0F/eTw2emPcjqV5umnmBLMNCFb MRYRxPMJ0vmD5au9nrnHb+ugKtoEVfmBRhRCxiJ6VS2KS2+YEzU6aoiWkpR2cGJP7WunGFBxtrTK zYVn+yUt5q+GIEs2+jvxHWzng+a1VbI/N6UNUOGBNKJuBHDXVO/cx6yldztpNzJVImyc8e7k9XMt rGno2dfZr1QwXz7MBMpWejeIq2UW3//CtTaIXZUXoCOcLgWjpiaz7O/hQlGkymkeJnW2ketZIeMf QRBMGK2OW20d3i3+RF0H/ZWvode1Lzcfo2SDLnvjpCzigukv3W0Lue/7cZ6z/pQEfQMzp0qwA38A ublw/u8Uu7Zh6DXkS2VHXtQSM6rqC1CH5Jpf6kd+xM6d5lnTi0WeMNdH9nkfgftkapYpd8l53uDT lGfoIlonfM2Kd4Gp9BmCokao/tjlpL0WurSbu3jNP5zFgE7nRdwTVBz1kpwoqYv6fUHXiw9Uj8k+ i165+0MhYWQidNj3KGCAjxpDrEb72KEzw7BUW9m4r1HHAvKE9A9oLIeICHUpEjDuTvlLok8IVbgG HwaHhyoh8Diu3HJip0m4TXvHvidmrpK0+qIRvoi6Jw5dJVHGeWNFO7A/Igwe6Fyc8KGLY6h31j3y kVQyUYVscwYQ4U+jZYzFH3dPXI11HZD1bGnLU5uT0VGRq3jm+oHKskpCbXbTaSov74Fjt8YqX8eU 1I0F36zBV7Y8kfXvXPP1SKwbtHqDyebetENRSkiHvmIJcF77yDJSN3doORhSD1cEnyn2UZOneH4f 9OpohdILusc1Tr73m0e2fYETIeEVXp+x00AcMSe30NKA50l2lUec3yRXDN8hNJ+7DiNU3x75qjgc j48/9K86OYk3DTYkPPZijMHVX7IyiDhTtJ60XIGhFck3+69cHAyZKzOXsm1iLLyMOEen9rpeq8Xw 2O2J8kXPCZ44/wjwz0yoaoVK3os2mFCb0jwloWuYz9WjMFsUu8VVckbRXJA6/AJp7Q6d5mstySIT aprEGZKQVV00/FNpVU5A2/t9tXwM3OqOnlJDIn/7PW1jXXY3/W8yaT/EeYQNs36u4a37Arb0AXX1 vJRKnMZxY7XFsUFLA6H7S+T7e7QVsjtC53SDIe1DtxnLQS7VvOtJFxqyfI3OV92SrqT/uPwSGCr4 af09ebgP5jOeTwN8n9ql+Rs1NqlZF8qjUN56+8jbg0dv7E/qXqR9A3UGLTqGBhV1Vg7tm5PXaYa+ Ro9Cfcttt91NqmVU+1/4lQ+e39J34ROZz2z8pXf0DhuSZcjxhSwZM5waLtXq/AjHAv6XeNrsrCPL titIeWwTmJYowNHCaWnfAHTKbj6cG5+nTAVLzhabLFYKVpcPpuVdkV/2ZQmUkH5Q1vgOS9svyHds TdI07TXnHUp1CAbNfZbt6a2ykIAq+3/c/j2nFieCQ6tYen/xnAQZ0/TsXgICdGsKaCrLA1UKpdzK QfFqv2Ck0tAPz773oDh0IHkenyxwDAm0J0DWXzmibVq4CxADFVTOGX/ECwhrfLqRBTPB1/afm+ID YY8AnXeFMH0XTFzSdNzF0lFLFk5tzYaczdN5q65cBcB5uE1oDK9TkSb2jn1forXBs2ZgAM4s5jUC 5ai09cs+nE3lCx5w/Uqh5GYmcuPi0l6NXDggILA2OdovHDbVl4bAFnbHBXfLNwBX/3Wh0icbNpWq 5iJ62P2iarAyuRf0rg7evbxh6qKTKUnj6nd5GX77wrEpp7uH1qyRa3HrJgcKkp2NeNhfoQBRCdy2 K8cdkjVj3zLklEIbHsdqz3lqGk8uCBCBr8KlDZJOkPkA8IE2cL1+IK2lnaB1tnJM3buBCNh/VM/r NX2X9Zu0kYyaWJUrdVoCLofK/LOJC8Nrw3AV3T3hY33FYWZhzrbXi9Zt8gKD58x68ZnXZddLD58J UQLhmgkH1CBcbCKhSf+BPKQsTmuYFp2eXM6dPGGt7i6iWPyYCkpqpirDsPkUHqyQdvOCaGGtrVsK s3mj62jtcYjneh7X0eOrLh1SIEHfN9Rd84gKlTzSNTp7YtmubqCuiRyVaKT03dnkhFCt+lgXBiBz oUz+jHXypKXelrQGQumiiofZzg3gpjt3s+zerq+Bh3+4/sqdBpVvg4F8rd1RXlet7b/wGV6zvyoC 1pwVe9LM/0XRIDJGRqlQutIw+qroBTImlu1u7yDQyfSEOehYnIThiqM+Xq/lK3YjLNQULBL1znPa 2kkrP8CbL7xfoNbeQgPDRx/nRgp47qSTLQlBhd+eESjgjHA0ViryUrW4UdNvYPJkXKVXMdi5eJbh d73HriAVYeGz8bocSRUYMMvOgpk83KA9QESYyYwG84IOlIztUr35bWjPRIa5TMyJZbA5bh8ECnVA DtBQDM1ZbIhXUJ9GqR3latD+br5fy+fkt+rYvl8nEHJ845afDMZZps0yL4OR4XVn60haAHN0vrfV s0cFBNXYltFOPTkp0zDEU0Sm/JCdCIqxY+ZyKVjWe++fsUJV3j9N5JKHD+ZlyWhVVr60MDfWvvZi v7S6K88m7whOtFr1uEZsByeTvH9wcmDgZKxBy52aHHOMdzgt15wvuw4PnFo6IUy/Z3p8GKUQ0vmq nt1+oHXCl81AhL8KD28X33WxRoWvP8Gmea3mrShNPxzUVQ2psdLWbeeUv1w2FkhAHxG9a50Na9Zs MhYqyifchGwv4r/09mzigXYjwTvngXsPejA1M+egH6Kk0tH3mOs1vS94rWyQOWo0dO84jg3jopC1 0sGQ1On7acL5ODZN+gQEHYnQibG4d6i7Pk+OtqzNMdM85znHDCM4PCInZidxgo0lTRiOtPr80/wr rM3z3rpMQS5mXnrKSQYkK5WD2EyACE63gjqZLl0sB1a/dcCofXlCv12ul+yPT7Dybxbv2jGKiLkR rGtfjO1yWgaLnqeLcIE60G3SIFdOJJGVsYwdu4sKIUeUUR90dhSe4yQzf/C2ys+fidvHSJYbvvEa 4wUgYK6Z66RF6h9vVyOlLkNkZEMGcsd4b95YcCjePc4gjw6PsfVm7UHd0jMY7ytsjWyvGc+KeDkL 1AUpaLUgQ+pRi37qla3zu/+ieT4rG5ikztM2U4/xlZ9qVDNPG933vuqoCIdAyRv35YThCLV2ncCT qxZR8F7lBuc1pPzP+y6Eai91fPY+Di7AXZ9mpKA1FmrBIUbZrYrIPZzhcud3eRgsNK7W9wtI25aE f2TVYcfZ3Lu+NX7GAf/T2HyQ983NhYeMvGZO9ohVkZu3fZd+ssg7o9PrYRZ/+FBaWfzVzr1MIZQw Hxyg6+1eQ+RG7yXq4xxvF+NmzfxBPAHSedD97ThzuAk6QOpLMWI4XyQykbigXFRdvHhtP8XqOiZH VJ0f1WCgv5truzlTBoZznW0RKBlqjsYuEgKDNuiNBX7fIrno/qQprPVUviLqz5dE0VtdkJi8Bur0 DEiDFQqLu861kcHasSqcNqxb6bZqWTIc8G6mShtq9K3e3rF77QuLQGYoaiXZmlQ/Y+KEJs3pO7dK PWgjSPTs+FSdTq31PssEUZfLDzpEo9KQou7H0QirxqXh3TP5to/fOYndmxhERiYGYjLb6HvVhv6n VrXGSC3N72fpAkcEKuFEhwO9BrVwmlckPDxLOR5xUcGzPlrpQfC/5g9LYRnjxzmIGGn7qOFakoX6 648vKZGHBoDUHoh2TWCnDcFlG04lqaVChXdX7vfs9+9xr8oDQq+xGGXNfbP6L04sajsk/K9niPwo CPqhCQOPo5bQQNxv6exYI0+f1+wPjdyd33QVHImB0fcK0N7LUQjHjcjdbRl4n33dc43C+/kjoVgT hrfWDEsJvnVlagdOjo4e7rwb4sjO2WhKc5WZaLad08D1N4uofYxENzkEnK066FAs67UdjNyKskUN Abj7hkJIBY4OsPmMoQdXTJ9jNB0/4FWG6Rl6aqiAvGDwDOof2fb0fPP5TS+gjz+W3W7/aU+Sfchs 0yC98XhoPLJJ99HDHgmMJUMF0NIVW+GhDXjBLZqCY5qBiLc6hA479m5yGWW6WGpoXrHpLqzqHw0m qJdGVznTr92R6QGvehdVWUE+K6tiglkZaJ7KwNM7cmvkGmnPcIRaCJA67MeD2Plz/RNscygHUQGN r6z5ZdeE9N6gVb6ZGaQoqegkqhLgsIrjEIVzi00duHLpjW8fvYz1nAOD2o4bgvrdXKimWZ8ukpJl Zy6YH/C1TVCppfj2ivqgIUhqL0YcvYPYNXUKyCrG13sN9ULZFzfoZ8eJx+dRFiFky99TWzCUds8p n0vlhXIvoQVhisU8fwnUoWx6CtfdM8FQBnWoHxq77FqzxjgOj+S2ZPl0ACXLQU7ABasSxdwpNMCQ CfHI97YDvfhCNqZHRKhoiU6Hd9ataK9G9xrxKKmUAANzpmbhj4Pj21JEYSr1bvM1ahXmhTWIOK5o rfxpzahIznBWg0zL1e84OFZR9i1C9GYnFsxnmwd9lokDJduLmsZDDFqpiMdtAvjdnrRVQIl/QpJB +3Jty85Pg5iCJVALlugQSlg8INIwAy9Uk06K2APPBdzlpgj40Op1DN0gr8p+xwMp/0p9WMdyUCwz CH197rEGNd+NWt98n7LmLHKJPgC3ELfBA6sd1ZWy6uncja0aRfOpZQPLDkvsaVBP9ngkxn3hISUP n0AdaVZG9pKzLlp/Vqc/Ym8E9GAFxGKkEl1YHe3TV4nCQm8YEEFpjpqRtKRv9bgvfGU+si1d+CHK 3AMWMoEmLoa0vmvmjCNFf1yS1Hza6whkbBEXPEyxJyaI6H8g4HWc2MKcBRTYwn8QTPenIHBduW2x p6m1k/N4MsrEpPrNAtno0rBPkTf1M8qNRqd9N3d9yVisHKgtG62BorSxeH+UNBm2ZyfIw+oGZvCr kNqwi7H5yGc8ou3wOpV1O9BmQ1jUxUZzm4FcxETfobbgkedLArgSFpw5fIN1LG4oKsVAip77Vpnm pKElQDoolwxA5xe5uDZ+HGQ/Ix6uHy6w73Or2rZKpS9Dh6u6Xa+UXV+WDwpi1QwLT0f7wfBW0S16 op9+PYm90pMunhyYRpUWriv2HRTaNzMyYiDcfRGQM/QdjH+izPB7rmzUqQ8BwbDeZbqVGnMYR68s awtgFPg/b1TWHBjcZioFaOV/MNwvsXtynQEWFp+Rd04XbY0CmBEa1oQMPWGgXdGrYzyQkdQzoNTg vARUIyLDVvRiP3oYXpWO8a7G9ZccU2phL2ylNWAFpyuVLoUqhl8m9MwEY/qkkNrRURxR7GYHOXuH jcQHIBKbvS5W0EI73MtG5ngBB0pYgh/Df1O3HqSvu82CUF7L6rQUIIZ9nRzDImX2WXj7yV1jxawL pw6ROy8AmkgQXT64A1Yw7vwWoQPSXR4t7I2yrUdjLn6b5OZ+IPldhFUqGFZX0QIzgCGuAr6efFDO x0zyCHKiRXbQC9TmhrIWqbBImzMPZ+m/Xhpp+c6TgR0KnfF8++P93IrxZdwow5wcetwvC4HhZ2vX CriMX4Vz70lUcThj/BKZor4jK0GWDJYuL4Xa+eAEgMIqJ4IoWmldltLHAbr7htppHJBJWas5D+mE dZGxVhXufnqxHWg98Oju4m05SuSXXUnF9zBdFGvxwKF7M7KROw8zvz9kDI7E1q+YJ/sxPCAbrMWl OYrbvJ6BWQgNZy7DjCYj9niZZv/FCdvoz8iY2Z60gQ0l0tgicnnlUVTSa+99tV0/sf6Tn23KPVHk BQB4RO0/GYArEdo8FOB7tpGHqvzTqIaqV6O/ynT0IKqzAA0kFivWhWa3fDhYx0kZ4uALD7Og74PC +bNYtw8Zqyf5hfiY1KCprSTCZ871YOzQxwyDf9cnZDqaiIHh/ezhOoApqNQqVG1xMWTTkTQ2rP2P pAl0Yyz31gXgyzdT7AahSUIQttdW9dFy/o5Vv7QmXSEYGcgV8CvlMJbAOKV/gzFQJW+uzH6V8q1c jdiHaWtMjudFFurFt5azITeNoExgOLWjz+qnNBPD7LMdspCCmnFiChgY0tlM7KmAfw7EwoPEosJz cRWiUpElwHLkLc+zQPylCr9+nLqPy7R2+V4B07fsyLZmZ+1MLDDSg/r5NfrGlc8jqa4ptruXhZq4 /1y3nWPAAodOQq/FPi7Z8ImvnyfDpA1+zZgzZHvozJY41CnG9wdu2XLdmjDbtTLmV4/TJJx1i0au xV7pNTDbdy9Rg4aRJqjy7npWlUK0jUAULaTM1SWS3n+sRiL38K/gVr2Nvo8cPzMGIJmzcExgKAFy 0z0DkABLKEbz+XHhbiOJXyjVMOQ1AP5XSPRFTJa2YfqzO70ywFsG589SBVEcdAtojSPTHJiPhTMl hhwY+vdBND4BPglhkcaJsHmBFaDOF2EmC2aXewnhCRwqQkuO8N7X2iP0YGrbfhOy+6edER2TYR+N r1K8H1yP+o/aPFamuxdaFpeODhRagAT0vYQhtDd9jUbAVm1kjBcjFU/08ylb7KYFOBngWSye4Xtt fYDpY4InguJmUt6Jjn7mWGOkMNMSk8fRJV2gNCAEofps4e7dzzhz3XWy85sGQCxQtWl6glExQvak LHd/f3HDxCirG0ZqZUJNmc1WIWb1OsAWE2MI8ulga+k8rTbv1k6s/e0AnlwLH3GjuOkP+rwXHjta X29lKIwE/iQTlPM5ZJd0KHPR5wQ4RiAjqxcHCvwgnqmY8jHUaK5GfifPUQnMIOlM3pllAQK8MS/h 2jPEWfx+b/JhyiFzNMs8zCalXQZWNb+yT+FEVlQsF3tgmolUNGonU4TwdnUdwSXnJA6qVx6GCDvF +fHIq2OYlttOwu+YGoW8G/SbHJ4sld4Pjua6AstdGLJLp1clrBdWW5TAHIfQYt1R6r6avIl6Xbf0 lJLNTDq5fyxmPFRHzV58f1ActzS3pXP4Ushebvbm09gwOn6j3pMsgWJxQVDI+fsyh1lX0QbTXXd7 +INcaiMi5n93GH2J9y+atbvj9kH8YWX7yX4RKUiiEcT4vA60ASOSt/r0yy6CbWF5RqnN5sUvLnoQ YsVayoPZzcyK8cDNPfy8mX3AqNBkL9a4JPwZNsP9TM5OuA38Pb/uxMcNjgpLuqs5OBLFI/n6sgYG o6JshxUmTiiizJljoIKC0eRKJi3HziC+uFn1sOsuMl0ck0xuyAyK9SJU3QKFwkVxcbwqjr87fjNs el3z1wcAafoklt13kfDWmHZEC6jtZY26xQzkNm4EnkNFsvHgDXwvLsrWXWCIMqwaUidDscq+0Ewr +iExtIa1veuzeyYgdcM69AXPwvT9U4xLP5eFemZzrhRvZCM5Xqngl57NJI5puwSqS4hM4FNDWZJK fc2gX+AUglWFQiNGv+h+6UuTnUcbLzvmwxJosAe6W9Ug/5yEpwT2rK5DxGX7+GXgk9Lpf/8+JxG2 JJAQlbNGH7s3iA7wZwlFaHbu6EMaqb1fJPehMxmvGGCWp9H66S7dFqwtYDCS+yl/xJ9cabXJjPYM lQdtTWRQPWdrkDsngiZ06KSPoWT/jsWR2eedU0SCaERsqmp0/vWisbsGEPqJIT3Jk7H7c4WNfgJS nCkIe3LqRb4ENrFEHqYvQo/8AFGC4IMLqeWDmMHw+yDy/vS4WHvd5qH0yOQ6ImU92Lv5ADbe9K+p kkadCQaw40pvD1nLjDTq+TaUB7EreZu4qaHinESCVcNT+LE1/I1TBVpS+u57C1j8Fm4Mnb5iFjXP iV0t+OlQodgP/AlIr1oJx2CP8UOKz+eeGzSp/cWlT+cRAfl3sy6fpzw4sN1/jH7bZkVptjyosk+f 2DN9n9W69wYlvyNgdO6CKWs62kx5Wi8rDYKvtG0i6Gmy6BKF0uHOeMlHBqsUSofcFNahLzqFIA0+ U/jiabBEABVPskHbN4ANeBJ8D8tP2RAnMxgnpGicSwANsw/1I2XgZkuWllaJbJlvJJfFzC7cQeJq mdgtcc2g+NTwIwe3KvwWGQRL19h0ApwWdWHO3wGVoT7VrtSEdLNTRIllYOklj5xiLW8gmLjY9HDg iZfGny4MFat7eJ8N7Pvw0tYvBl79HUkuIUzM+Glva9MPThPkC7SNfkcEeWNNO/uCONA6Dw41z20D ZaXK3jMpJcnRit7sYHQKS3WwlFn64/cGkviw448RjTDELtlbK4+h8NExi6Kz6doVu3v7onyod7NP 6VUDX2PuP4+tGX/Mu+dlwGISNCoLzqZ+xKFUvmmhSG8uhMDp+pHTZs8QTdgwuHwazo9vanPIZ4so ZR66LrCQF3eJVKvkG7Oyxb5jvUScwaYcThmjRDeS1EeMnJNL48DofaWVlMrS7V8OTTwOz4J/2sQ1 lkvK5Wf442fK6IUpy1zGJGx/S7r7+vI54MKN7tPK30j8AOS8/CMUpAFFCeWYbDpy0z62H73lj+xC C5E8+hL3sxM+sN5UfHN9NcFVGSEfK0C/uBqVyQ+Tn39iqFdWVP+UctZIjePtKMjLsYGFFvry1/0Z Z9d4O7/YXKmYQk7azthpYgdLnHgaa0yXjYrsCjmkonaD2G/mvY6vatSwDSQJb9CYcCRUv/yiK939 5qpcD1FoEEvTrWzWDrchOIYGfg6OWD0/Ufx/8WsraNfz9J/WS4IYK9zKh+gqiumlqI1YxrzxWMUY 9xHJnRH7X9w0ubaUjVPlanlzbnG1jLkqWNa54uxkh8wGRGR4ieibbFgjB6pQbiPd1ZrdMWYRwCbK 1qiYVkYVzy57mWXYJTnWTtw2CP0VZBWOp0ISFh2mABvwNbp9poE90Q2Fjswb1RWWNEfiMnYbUdvP ycCkM1wqC4DYWi0ksszFjBWnArUN2+JLERSivD7FwKyDeNl7eHUVbKwpuLijvCVafN2vSbBdO/bj VaFmm/cjTS/IPGbTQeeO7cvKiYTuphdLWKicNQUfXW7ilWtSXnDoKqFJFRo3jofD2lPG76kv1+vD +MCc5GSCPX6NvYw9wBpjiG5WIgtB7nphU6jj2Oz1W+YFJRxNMB9iTnLzko/8aMATnhVq5qRX/HOg 3tMIejnEv0/yKGJaYVYX2cZ0OhB+judKiWzxFqBgHwfcanhZZ0DUniopWpFKSSW+Iac8EFPtnsLL mYjeiNNPwkHAjv76g5Au+afA7clL6q8PCpZqD/YdC2JgFUTlgU8WzQtGG4iUXIgZFg6c6nPofsJz dX+QoXXsTJn/tFh3T6/WHdRVaLYdXDW/gqBEPQ1U4Uqk5FdYFflOdSMTRMFmoI3k2Fd6pgVIlw9x ew3KrOEaSMrTmMILQXOG6HcJrwOVpmBTkZcekJ5XU8yXoDN2PLc++DZ4vQNE/jDrgXXkgFvD9VsP gRft8eNyhqXn1/LSbE87hjgjgr3wkaW3YfSVpFnr6XP5Anv0EJuVkm+zCQyulr6NU942f/3FdYjx dtL5rWcx2jII4Cad8VhRPSm8BEecfYSMHigyyH/R9DWXfRFpNNCy2fEKBoEQrs47a3pgXp6pg654 6Uwk9/lJkK0TR6I/N39Vgg5F0fV/znWlDTb9Bui9P8TZxH84JBIgFkA7aKxIN8Plg0OYtyEfnZlN Se0NtvyE5O6iptw1jXrbm94VYvn/0rUEEn17OqJh1H5hekXDV6dLDzRrcRpFfFphzTYOCLQdBxjL vyz/uIcI4YptAZ0q1aATJ3dzmIg1WoQPnZKvj/IeRtjDuBh7uB4tFLy8RvaFBQMVmcN1IZO8qGwl lPmagTBVveNVoEr2p9avKqY3UCuPz32vY9X54PEo2D3zEvbxF141a+GzC7lua5rs8wdxNvqfvRkb hPO7bBXN9QiNPySvXoliUYrrRRZ/NvPS3KYAvSjxDkPvxvhJHfp9m506Mh+BM09XXDgCX1FU5ISZ G2+NAlQLqYYZ4A7fG5gXGgWfcBX9lxUWZXdKpSqrLtbmzFqNGb/6maHLhiW/GsMUqMNj5WKhhpYr p+owDAb28a/Dw+nVm1mKHHmBo2iENwVO7AF6TtBntI6I6iDOCvqefOMPToehKSFNkJLWr+JxzXtt La+8X+JG6PXa/Z785AskZ9zCOaoivUKyE9yN8ZX8JzSAG09I6pHFeb232DgwhBdYvHnQg8Ys456D 52YOIRx+Sl5Wb7zntpKl7NVVt2EneWJMiEVyPuMi8zq1BZtgDdh1lyKK59dO9h/bXQaNjHnPsNtD gW/h3vvU2lID3fRiTZUifQHgoUYDIWl5pP9IvbyO+/PfWQEmRFm7ohWMpB9LiS8kxjTxAREKMHxa EyTWZSiJ+/J2eoTDxPgAu1kiS5bs/Rj9SXUZizHMs1JefDeR1NXjW9lbrvLS+7Sqv0yeMGwZnz7/ QLH2br/9kmrJgF1pn0wfMvOFvQx5MTs6P4ZHaKUxauP7mvoKmnMTLhgxYNeiMCbqb8YD9F26JihL ue1TT158zwx7QjjKM/6YPdwLJyx324s2N9j9PUJ6j5h/XGhzUZ+YvpN4c4PUXWAHyM+LSqsXHXGR myMClQHJ+94xg/TmobacRYpNhWtCpO6Md5fmXzf95eN7CizdjFtCXXQtc3GFJwMg5MnofdI8eC/z Ps6Hsy1Xq11i50K6ZOK427pOGt8113G42U89XxO0YlZ2BqDXVOduVjVxbKDQvyuYGtCB1qGk8rdD Y1QHCn+6PqbyNiAl2XZD6jEmo30cPFCI8NpScZex5z5OSsaOWY9ZNyZmSUMIyvgGwkUcvfnh/z79 aHb/HXeddPpQLXlqznGN0ClJisv8uikK4rNpHKvYozSg3iz3SAwOH8vhOa3/J/LI92fYHlXNR50s 2shIOxdiRPyZy7HBNWRcbuXcTLfcJr52KBBd7z7zSUE5MMYn53UTqx3loYcGzgVnaKQxNHPZ4Hu9 Nu0kecsbGJKWuES4ZNFKVXuh6hNioMNBLv0Ed/of5yr3iHyZXJWF9cI/2GesopPqA3u2s6sMxj2t yVsrtv6bmi/SZJI6noCYdDltcKjVkvE/7nBJIMZM7JkKP+n7qJ+c8ojUMF92pan9yGi3kZCik859 JrMCF6hsI+pT1O37IGACWf6Rmr4g2U/ay0l0ckh5GpmzedBUtpFi9m4448RTneGvzTTXcMzGT6vu hWf4fU3ifkdsUSnGXL7er4XOYdlJjOQlkbXFh5Fm6ZQNer4BqZOZaHOHpuzZGm+zih/RtZ9r2ndz gjOg+1+BbNErpD46N5FQk3OiORXNXZZjG6yx6qPXgy/hrDDL77bvKnqeXhRRW6E8jy+UV5WGSrEI Mop8D/fq6X8zRg3B5f+fxKfdpo1ouvsCuBEXZUxcX6T1/uiVFEVpSwkRyzUyyRPGPKQ3zNQh/9gP lgiUaTYBinQnfEI4KzXmEirW/adFR73mOfUmXg/muVVKi/Vk0rGLPNFIw/nneD0IF9eCy0uNU7uU ZrV34dA2vTbamouZj6NslpjqAXdJGw0TjWpiyTkEDxqWvvnpGDUmRTZ1VDIxuhhJPu3swROzM7ja BnwpnvYowCHe4o9S0zpBf9YVRxCLROsAp2qJZ2qydhgJIsJgKcL36h/khu4TEPo1Gm++GoB1o78y 0GPj7Fkzw+MwGZd7/e/m4GY2OksOiRT8lP9G8dX0xia5mN/IuCcBMp+206wgyi/Ik0QNROrz/RD/ I7HoIMkYDy1GpaIWR4oPzg/5QmAmqO2t+XSOdJ49liX1Tcj7cnmqaqiENHNB8qYA++X5T1kcgRJu /unQlXA0hq4a8Echcz9d+uhsPrk0FUKnp2njBU+7f+FJyl1coDVvl3SsLmpNqBtQA7CEpW6xP0LT EJlGdwo4mzYUqWMF8RbebVdKsR+IL7BnYXzvcXNv2vI+u9SjTG3XcnsGTCHfvmV4lk+r9KhIxtSf 6pdpLO5niVeQaqN8oszOfyW+LvLCZtxhTMNXct2Y6nNtTWIJETxDIFnSEiXsuKxCx0eId9BbVAxO 6/4p2TfpxNBW5wAN/X90s2KufuZHymaPlN61urLm/C0HTpcKCkPmR/Db6gk7RKRmm6fIPr5U+MZC fTF+JKJ61wGKP6jaeGdE2wFXO1wXxNo3EKtDkcNa8lS7d9ZpU0KB+AlWKALLkaJ4HFwW5FDDa6S3 SjSLuRffuchWXtRRk0ysaVdz7kaok8DTJTRG1V2Jm1Q+pgtSBrl255tk0QDKb/eajxCPqPnYYOxO 0wosRsadBRULTMCEshrGFH8KASQMzU3e7V8tPNQDQ3c5CxbZgw2UtjIWI7K9saXj2ZyGpEAuPx9V tXMlf1Rh+pKZNmbQ2WM1X6fuMY3G45muUQlQp+Xve1IAyLXCI+dQj6vyD1viIuo+GN2KsH1fhrFs qJwzIeCGuW8XFIQi2o5bz7pDgPtx0AZgJ2bGRbrPYQzRn3tGyffoqrjX1xeLrD6wTDRCxGw+9PeE DYuz+7X3gc7NahsFnfHJX4mp/qNpqGlq4GS5JKDMzfNA78uLh+JyyGBizABA6KJQmjcvg4RDg9Yz GpAUhKJ9oC96ia5xTKoEnKrR9/DxeNADSBBu/wpE0uFt7NbEvL6Z+xnHwB4KvFNsj2VxHvUYPxZd IzyiyDh4KWnhLX0fzvX7ixvirrFY3hQogaHMjqCWYrRQoljoHOgjD/LqGfbBarli4j1fAov+ezk6 Qn+C6M4TfB2NMcqOTULIXKxJz2rW5tXz6fbJ1algIjDy8r2mrRsTcJJqo2Vwphnc2Mts8qojuMUx KGjOY7uY+0ZHGJrYWni763jCiF507L6++2mhFn4cjyFhxSswjxTafVBYglbRqPckjPQsuVqtFp3a Nh7SExJK0toTenfM+TbEoxma6lGICHNho1orND0rR3FH2q9VMoCsNSo6XYHCd/BiLXDsABNTiDd5 Jca3V33n6zH0yPBVyDuB06Dz5ICplXATrkTwFDfeZpjdKr0Z+LmV5evOzH65HOwUHqlWq/qmzFbQ pO/QQVQ/Sw65Puv8HTX3Rlr57/B1tIVGqUPluDSIb44O4TtwlaB4XqiRG4mfDpYzvvl+aQwv6NTH UkmjEjmSrmYJ5eUsMe6dLlhvje/fQ1mYvyW3zPq1RrbuBPlY9dEaJPJpOQvWxQ/+FbrGa6+/Px/f uip6wqmPaqXa8msIBI6prG8opXR7ENfWWZ9rUIV/GfXo9XhD8FbmdmntpecLL4s89c+XKXnB/vUK DUH3wXsHiy0fRBjLnUTbtZxfDHTEK3BqAxoOklFjV7OHXTfE5Fz8QrnqkeNE3KgsxFyAoQdFvYcr BnbuqPJZSjTNWlDqPmToZmt2hKhVgXth9x0x2/65i67r/4Vmboft7YzdGkiAhIfkQjS6+Il6caey ZYVo0y/9YmFnSNilx6vbAfQF/AcTziZAeW0dFcyIkJTjwbMdEWxSN/P6xnMG1ajzvlxbg2+Jgpoa UvxQYo3z90IJ3VIT30pGk8jzA0pI90HWNmu13ML5xY0jPuDuDp2ylXSSctyKoxu9vHepSpUn7+92 94kaCV88NAo/vaOzhKFfcl0dGTc0/jTGLMF+RvNwZxu9LqdLMR+PxrIPMZ05t2TDEbHNf/PD+5Td qSmHPWH5A7ldzejaKJtH6ciNkCUuipBn6Y0PhcMVEW28X1IFclPv9lcYXYZl+5xtrCJrSq64y2bv hP6RimAh8Jzd5nHRxhaS2A2Fr8/XYd1ySNU24Z0iVI/M5b6xUlZ6H2gUW7t1qMOB1ihVpGZPcVsY nddpoJT64TyhKZ+ieCG4P9bC6kdDeJFU++NyTZjEXvwCKYf83L4hZnh5b+7kwwHCe97w3VAcjR1R bg1Myy2n44LZixN4yTyKEwqfpekLS6QLrQmlyTTkXBcMtBHfYDWAmd9vstdJ+2mllxsV3/EoOE9Q qiPYcgye+LOOBkR+JhcqyTUFn7jBqoSI13Wd5iAkgA/EFqGIgoxl2h8uMgCvxKDijtTGvuqtZYn9 a4wuy50voKshOb+kDwQMK+pcjgB90WSxfKbY3w6xVDSzIn39YqscSMYJPM+TBNmUmv59E2IoxlJY yXCOI58pdEwRbxzVc8UY6mzNX8jVDxozb+JcyxDl87evnc9blObBAHK1FFtQU/nrx+OSuBCnHouk AMRHB+U3nrrKgq1LKNMuM8xC8bhVRJKJYfAIqUP+44gj89KXwizpErqwsicgbyQVRIh67rwZD+V5 uHBab1165ahecA8TnhAPt3xBWuWUHLzle1cs9TSdhu1UQDkBIDhYy9iS/HtZVeC0Ua1ISYYZP3vZ ALM1nx8T5Szm/XqS0K9VPxgiyEABt4RsLGw7W17/d6Vc6fLuSqG7wCOA3vL34b1pLJIHQQJ+x2Du qqe2wYlb8AnrqMJXIshoTKgeEePvER9mkutQ3MUnUw+ZGgnYNdOBaxyoyQAlyCYHyjKEzbDJL8mP Wkk7Tfd7Y8iV1edRNkqKaDa+Rglyjls6zzmMKg1EDAUa+vf3F+XFnKMUIfqAVgo6xjiD6Yh8eMeC DHXgWJ0LsfFghnt8aQwDZqClXQMYlSm61ci47hTBxWrylT4gxZpY+/MOupyqfHCYoTJfTl92prQd HwjqVzgxq9yx5GnYF5eU6rGMe/Vm/iY4UFglZpUeU1ALRJ59nTubbmN10W7s+tivNdJdhjUZCfpl gqS9hSZ6nwYTlSJtagXs04wzrcUVs4l9HvuRRg27EmW4HH+YmUV1+Yq+RmSp3zkHgqfdPTU05LDL 9Uk6Zck12vlsbA8bP+2sIWrHgHOTeNIccR4W4Djg+KWTC2k2gard8cjehqWSfgB0e2GOw1gr7L94 gsabBn9GJ+AQPY2cJDpNDru6A3YZmZ7eEXHCj4O8cdhG982K9Y4On/spjc6RISJFh7x+dmSaZ/PC uDwWNTRV0d27K78Vs/4D7NJPaL7DH0kh63r7lMnwg40y1H8QoOBQMIXsdO5dpLk7pc6fJdt4Z/wu BFTywHPE3t9JQo/q+KfrHTRh++1SCkTqabr6tIUOpJft86IeZKRh8G2mUgGaTgSOGsm5CQArSmKC vi+k7QaE2PbSnzjvSZYtdFrCB3vdnyjpo5+gmvFBwClQcJ005Hx9+Bf6u0Ez3cKyBIIpGDdP651M rdid1PusYgLD3rKY+MfciThjwKwCQRvw5+rwGsOlIbtnWaERuqTafEeB09728+t2c2zEWaMaXwzu QCr+pl+7+MMVOgrrl7PO35wR2Qc90DvBf5tVdctVxx5YRaBHtLLnRC6pQUOUGCvywVQYeEvNr2TB ArWGxTKTZG1DlbITXi2uKg6e4z5cyhvh6UqdxPR/L0EWnBclKlzChy/UlTRYFu6GMuOsHrpd+ZUv vOj/gbBheWBi/PUtqZX2tH03nF+qLmu8m+B+TIauH+yfQYZz/n5FGrMnGqfvuA9HNCF7171kj9a+ EgqlbyUKLN4CXGl/Q8NRBl6nRpVs1VT9nXeFCunxuw4zErAAu53mdgqzkqlJC4lG3V+jtqJFrDsY QEs9pRdphf2X24qnLu4We2ApmmFVuPDdZA6tE/hiFEdGPhajwXVqCh+zienUFFA/vhYTg+U6uNZz pZzZj8EV49DuFlPPggkqT5poonxDkZq2DbncsUaC/qsehvObr+CJTxqBvetTwO6+2jvwROAeLKgG 6KQIgsRy1LRWGj6AiJJW2LtbkiqHYzjixzo8XJP1SRMpT6+zmsVblswtG9x8gmUnll1p42M9fD67 1lDL3M73q+7kUtfBVSglMzHEK+vCvEF1XJTxO7wveblT3swNFicuz0V0j/FAlOJSSEpqi/qxbc6k enr1WM0zg4K3IxWvg4hQW1lM/dE0oEbdDJL7HqezgprhkDISVKYTaD6pTPFK+++VxMW9ZXA2bXx8 0+H8Tzj04X36/4OWI+Lb8OQThAQNJVnVhvwQWxInyJdasJf8Mc5UuHCMXbjMqt0WaC01Zxiiwqeh VefiTnSdkOWuG3Mk3S75ZVCJZz4yJJAs3hdwe/uGfyvDRcBGgdxMSOm6INhDm7m0bYBc7yoiMi3M LsTTc4QJsK3aPQVatz0R6PG5VypCAgH5laUPFd9F3vLMonlSkRW3sqViWCh3T+pRxwAYj+ve94Ct LsTq0pwsOa9/IfjitEjKCL6a9B02VmsG9UUmtLUGP8MIT12vsmMul+ALG4WxjtYxCw9VL6DHHrfY ny8yvImyH9N8lKstSi/TrX4tmyKhzzfB58Iku/Kpr6tuQGTGxZaFFP2GQ/JDyQ9rxkb3udiNvr+K 6fjnYTJc0f9FoDZ035gkZS94tKiy8hv6Ei+h2THZipsOg6hfduUi/5UOX46tKi7wjHDvNVW6p7sP +UL9xO+jl9lnGQqnQRNI45jclayJgaFQXaG/2qOWwVKzVlwpOipqgWSdVGWSbriLFxa62OmsJTBo s0lwx+6K/unLo3Ck2LuOe/ZHhV/ZiZ3efOudz/dtaBErmVGTDm/L33r9erhveoBhpbh76mFTjzH0 hLNQe8mjgUlaN+lDc7Sa+LzOOTmc8g353vxQfHEwPsivuLZXqirR9NlqIRZSPM0g+jorNR3yX/rm o7AD2/qlXWmdhXrBgLBBQHNGNGKISZIBsVE9CYryCZIaY1DvnKT79SLmwzcIjlQO9B/Pd0+ExJcr ojYuFeFElWauPSU5G52wD1PjCbn+cueh7N8iWbgCKxtndhkoGXr7BbeNn7607K7t+0im0F6lUNrz ++WEbMfaYQnUYE4y2qQX3UkAOuS9ybnhHmoII3ELFVcniOrmiAk4PmpbZwaDKKghaGE36dmxWQx3 dCLCxJ2JH4fXhyaztvZXE1b6+TyRT1b1N7FEwVJokvuQXiWYNPYKWhhgJAuM69nKjIYeaOgZZqr/ Hb1oyRsY3o4oFrfwI7FmVJ2lbLf3kAut/BTBiE7FovkH2D00H8YuUtQod/qKgAGTXdlgId1b1bLG lz5rLC+enuxO6eZtNcEqVN4QRmsByj1CR43W8LP4unm2UtfTjwCtJiwvf2nEeuNx5UeLGE1gNaTS yBmWNR89TxHSLM7axGrRxPIARnsQZpBw2RGVtMkWhSuuGf0/ozEuMpRFfTHfjp09/0O5B2PkNBiS LUv26m3KKQxBU1NJG2flb+ltXjdYYth1LNsL06/kL4EGg3v+LiXiuUIzmmrsmrZoRYIuJgbQZJeX MtnUXBm2JRDSYpjNR0P5euqAbYFBpjlruF9/6CGUqHqY69cwUiyDn6KWJ10pD9+SBFi8+7zGk1A2 +LSlNJzFUFSLQ5J3/tkoinVOk/C+HDuGLCaEZVV+1GQ51AJkD8lToi9IDyiSF+6bo8tJyRpsQiDL R+96XsYjB4WNRa/Xd0B5lP/sBQKfCQXuUacjOoZXArDKahM6pAYzGbMjwvK33kQfw0kVXhmvOqYM FvY7RS7A4FwVDlkfsIU33m6gygo8Q1zBq7MVx0O2F4gCssm0hmV5FN9ekCU1jeCwb+R0bF03JI2L vt6UkyRO+m6Q+dlg3gdeLHZWBiIgBv8k44EQvQuIADKgTty2mUeq+24zz0Df+E8wo4b2cD/A3n7Q /4xhqSaLCTbmTeNnhVfTqFIyW2q6tJPU1dtJu6pNduIriyPcpWO3u9ATVE7rC0X+W8OxGhUIasBv Y9KLGq1sk3YsntrI2YoPnkxevqV/dOtny/eG9MDhnSybBex5q5LrF06XbGCDDJKxVZzmdRSL2ZuE jY35jRZ9fkXOrAUXEXn2vcXusD/OCfE2XQ+VadVe0/QvZyis3Lf5gffRwgzCJU+H/eZYqb5pRMJ9 QhHwJTpf7WnN+vW982Yv/1nrYaSyS802O8eQSvHaYPxizvXg2fzHI6fBCisuOnVD+A5T15i5qJAi qyF0bti5ydeH8pKLti8+Te32/WTOUmkJrFVzSM1adk/ZYOKOAZwzbc+vEp9IKtYQOVw3djVZaLD9 ktTGmU5HP06Z9OHcbmv5KQtX38LJtjPykB4lq7RsB2+TYU9DPRiqtd27jUvGpZw87gNJft/Nta4g LUCGKjExhqItSgbv08QJmqzNkEWDG/zBb/H6IFUS0xCg/hcuvNIfrW1XtRZwLBE0EU2BcHhxDE9V I6BIrPxUhRzZaszIM8+d+NngbwqHOOxg88eKvi2l8HJIzgsqO+1/qpgBht6v3Ex2SpgY69+1lYPf gFToGi6lpQyxXiDf8m/Ox0e4EqBnHkF3mG/be4qcCB0qwFmMVabp4E0maHKA0kBZ2p7vi++nBo+e zh0FRkGYDN3lXV/6nP1kWpQzYJRR7HN8LBXWI5JhRIBin+Kj5RDKs5RqfXVXtHfpsUaZ1Rg84WNM 10cUuOaIDFCbo3xm9UI+mv5NFLrXcjRLY6k9cxq7IJ53cCn+Eia81X2ntNuWT+jaWc3OjvPGrZ2v kYh+i7St8sTvTpS8HbM29Dc4kPSctKP3mn/KCe/LrYE+vX0LasM5rQ3YydxSl+z5Bb6xy9G8l9zD JqvFb6M2XWBgnSTbXDOHuhIYqsFqLYT7nnQ6bx8X3uff7ZPP05lsKkh0DVMrNxn5oH/34oVxI648 gSHabM3CW3rHo2z0csjQMIFIPxaGDJ5CWmLxuYQqumV9qxCLR2KMXbP3tJkbEKIA7RT678ikAxrr 2pEzJGEoq0U0ArKvT+ZEl3b/J/ZjujBEizyYq0MTYbIsOUgvStgaljsIgogSib7eOhcvtKX5vPsl fGeZhfWyKoAlQV1Igtqjw1NLI4dM1iKEzBQrdFC/YWT6GZ7F486L/oocaKj25WPUlh86qW+WBA6c awQrG95AWVjSIlzHJrV8J9hxR409jKhdmLtWnMaqS2PhtN58cnB7TpnhZyA19MFV4ruHQqszZ8OQ CHWFHX036uzNYCYYk/jP9RYjwMuSxGOi1pH3FJsyITKEa/fG6LuR3Ut4PK1aK8G/wYBWPK8YkLIk C4NXV1alv1mo9bRtC9mg/6kwarzDKAp6THrxAI1Jxx5xYtR7z2Qalo96ZdI8RdROG7fvPQdg+xWJ BvMNfOZt0SQ5GD3/0u608jp6wC17uYnTx0nhz4mwMsPi7cPcMrO11pFo+PnxurPcAtXIx3fPvDFN dtS38xGsH9Cf9r86QSANeGoz3Z1FWGMlYfCeyOeypJr0T3XTO5xoHewluKTkMWaBkbK67msteegt 5ypIDIxbd23PjFWh6RCeouYKz85RudiYIacKiJMu0xaSDQteK0Ij5SkFXfHJThRyezQekBBrFSwx 4cuFOMWf00ea3A0Rx1w3S8tQzGlodDfghSt/mWIzXgHrR8q4XvFjZ118dtEbaZc12bgrzgrheWWX Wxl+Gtrrr9Olpryt03PJRt3VCIzOyn0Eu5sXXiNj1CSxHqn+azTD8wSnPHwEpFnn3YkTVQGz7l+K aAew8KzgvVGicCCh8kj0yc8wcEPiG4L9M5K2utCWAGr6HCovFAFButBXnDoi/OIKCrJo6oZZ+klK rfUD+4crGjHUV5SJWwweQ39nowNvihdOxZwh9O/iLoq98i4w4N+xcoUwkedtD6Ap6nn2rmSwTPOu 7TvUg1rIO0lpzV45VtIW4F2dVut6L3Y9bSkA3lUc4OA6ryZq0RNef5aC9tbuB1ZxOtlLEpxm8oLm etJ9JIFdL+rHc7TSiugYqALwg1e3Vde3iM2SNz7NPnGNoyFClrPA7Y7zBHd1Xv3CX5pB3Y48gsbE eWHfdl10y7GGL5faemaHEc2Iv28rfq1yWZoBw8dY4vIXgk5N3kQOkFKiGS4d/Vt/cqZTke/pBlwx 092Kzr0mo3MRXpgYSVqoal7QWXW8NW+ZnNKFjSV692P+lB8TEFzZlUiPijaEsONM2hmbSjVP1maK FtA1wHG9z6KvvkFiHDSAhMtrOpfwUpvcV3XPZM2DHA+4vul4j3w6emvmbNa4AwtsjR05CYkrdnjV vAjtwLvYzn800yYLaAybJbetbBrrW4dZtB3tTpTN4NadEkvoeHRrA9Qyho2K6Y9rFJNlTEy9rDA3 25QDZVhHoiBdSM83TPqBygUJP2MyX+6Y5f46lj+HXLpnc1f+Xfw7c7H4kTO285QaIC+/o8Tm/YEk RePqfPzEG/GHvUSkShC+YeY7zwYO1Qw5xgfl/35rGsqz5BJx4oprcUJtSd2TaqmQAaXHzKS33fzj KvLlHIAHabU3pzgPzkH9YL0pfAsgz9Hq5FK3aa7QRHssEPhxfHJJpRjczlXCH+UfqhHRr989Df21 cE6cWeeY4C5wLzzd9HO1/C/R4sqbsnjSXs4glvrZsUQPPIuzXeSZfH7IYlwNrpjw2KOIXnxGLYA7 d0doA1s/KUTbj3itB4Q+lQwB0uegxf/jTsYdAAWoEk4n5VcNUVsyr8RMMSRYfgJBDsrofad4mjCd MGOVc3/azWMjy7jrsjiNsAcqEjdQRGLub813k+wcqxd+fSjnCIJbZsDNF2yvAq2bwHf0D/vqB/hf NETAwhLhRjvHf7dbtR8aLVviMq3wOw2PSilfIYRmTFCUsMe9yWl2NpUbXNkU2QjSEMaoOvcY4QX2 8oYbXUNuOoVvKDix9ZXvtthL5R2uFi6C3eCDt84oLKUJ7xZGMCBHmeccVs2pc+NED5yWlpx9QWCM oGeXpEM1pBBE3RNS+Z21P9E/ExIoONhCtZDrM8Koqtvyq7YIEvcICI0fSdvOn6Kdb9wJnPHPiVbT 1fTj0G8aS5I1pg31ZpDYLs4HiS/N/oOW/N1vfNgsWIzUY3jL8jL6A4Qrh5TLE9AYxcHQgBEgl9vH KE8FCTWEQa6NOzKuRiLPIuTzN0bhnzIFvU2++UItD5s7vtMmyUTL0VQH5z9bH699GCCJgjdE4+5A hDTp9H8ZFFvH+h0+qi3bZVnnW2ahU0DheHXb+/C/aPrz8C25GI4Y5vxD8Osbwx1xeaann54DN8r0 gY/3owTah8AnVCQMZd+0T6uaSl3DMuiyPYDQPsy45SLZRmFwWebVvRe37f0aYtbSsusom+iOB3R3 7FILJWX8XejouYXnZMyKuAqy0RAYpIt4Nbp2dR/Stj4oAPHc4FPyFcg1hQ0yc6ThKQDV26+7H4Ve hplB4D58sXIi4ZbqhAvA557Sl5ASxMPUN0TBhj29z0CtK3tmYYq1YSFkayEj8OiE3RIMqzuEyIEn 8bMAly8d8oB3DMUVaM+GLcrVDZcnObAMVqXQKuko8nbGIh3RNPY4pjiOwGWv0Oo36W+C/p9k33PR EW0RoMHyaH8Ovst3A9FnA70r2AgxPm195l+gekfbedNFBew+IJxl/qdOK79/Y3kyafHS4dkBHBqT SBYa+gTGCEsN4Vk6svFR0xXbdpwk16sbM7kPgmt3B2mq2YhnEg1vw0c5qOQryAreLnCoERSAIMAH A8lnro5NHJAwu076/n7Kjxwmu47qnyKng/OuwnteW8wLR/+WlV5dlizzJZaVEZF2GdP/N7YJa6fO R9LMSOLzL3OfiLC5kx57MbtfaqOCXpm/3mGpnh1BtPhiE15EnWJfiC0OUAq5dfdCq1QE3Rb4ZkKq pfF/p+15ScmPN71qYfOvxT/yP4+mB4PdOkxQ99qkwGBeu1g4RXOZ+RsogYaFUPtJzGf4hSL9cGzo bS11Sh4q/F7W4AnSFaDJ8dyxpiREt2I1H6ZixCLKIqghBnHxSSoQkQh2UGP22ardIzGx4KkkAFI4 qnWe9OLTf6RT7qRVj3O9CoiqXtiRkzOfC0Mw6+HybFpt2+dho42oXGeIyJwjig/qvOIGzzfFvzKd wwbVvemYxpq9sznSUpXpZUIt1y3cpZwb6mLuLjMKhux/9HNIOuhdahm2mxrKYWS9he2gWxPS/cQ6 zUbg0DdgEwJncz79Gh5X/2NC7AH1/fQAr3G/7wRRgS1K2b74OMIla94suM0UbMNEUbFLflYwnWDh KLvMV0Rvu933MjrU8cn1hbSBEIDpo6BG4T0qCsGKzZeWjziHQu4F94L60tTsxq/18u1/JKHOq3Sc P+V0YsYpiovG6bJBf6x+woAN3BZWd2dLaTOvHSoNdRXbRF2rxKGccVc607mkvMJicoUleuwWWDQI 00P12tO7I8DoXszLDVl1FvxvjnW32OIDLGC0gRqKhD8jWI9i72AQVlEQMQn0V3/5rX+YBNzRkqkt c7WtDspUO0uljbKYiEQzDAksn1sa9jXMmGOP1/A2bJu1xV4TBboOdh79U/MQ9/RT4+fvIZ92WIQO lFQQ9r3OzXsYTB7XCBKnMOFVNL7jNZHIRU1+xXDMpoa9Yaocxln4/xblQvuQpwrZH/Sa7pHwV2ot EzbILbZuuv++MyxUuCZ7oZszB6m74H1AmhmA7d5xmJtYCFVBsE7xvmXMAYQBnT5/N3y4qBOMCu2I 0WrRDzBHnFK2i+8TuZedaajfiMVl7u5lTYEw4jJDhD9rXgi7O8d9HBraLEcmh89fE1QIzyWiHS4t 9/oIWoiGbfr5vkrm/2mH5BhySBrioY1O74VydhkFb4yORY8T3i6irsJauPkBuvnC7e5KtwPVcdRB B7DhdvcLZlzOpXYKmI0/afjFtWVwImEzKiSGaF3kxMwUi7qE00KIJ/K78WtyCBI1CzJS6Bnz6576 MvNK+TcY33u2sQUdqPT3Fcy7VWOGLT9HoaYehy+jIxKQrnoYEDxA6u5i5dFqGFXghVO6bX6N36Zx E7x3SGMdXwR3EYyyIZ+QpH6ggJmcGaZ6zntdCd2h5JfqS0nrEbEOsp4w4Q0b7YE6Oo7xr9lVL05n NYpY/pLxP+vxu2yW44QKE6Ae9Xh+Gs0BKVVto5dXiPtws13nRvvdoJ6mQG5rymnca3HGMk9oAx9q g5ExLhom5VeJMEyOx7za1vk/6fX1Zh4N+kUvYkWL2QkkfxDDgNFMf6WLN0M16HlInlxBiBjychEd 65QMp4A5BgqsBudF1O5mTHPSM2yc6Aq552jqd+ImrKG2hPCkxI3C9kfqfXinqpwhiQgmhjEHFf+x GFskiRu6yRh8X6XUszndL3dVEpEUaIPdc/DfdqSW2aYvUJ7pofvgwu5mK3rku2lC3yPQtovud1Rb ltTXrxUrDx3r5bFxmyMIQ11A+Tr5mPuiH9hH4FdYVTBruOdLG5EKm2Y0Jq3NKWuhq+kSrwv61jRI 39ZFvpILWJK9FoPRRkzrJbWUkwPYiz3ycPacx+Rb+acxgJuBIqw2ePpruGH34H+Zzma+VoAps+6s 6pUYJ4qjXRwfkxGbce0XChEEtVxDcmYtvK01zI3qVLqDrnDntPp86Qh0wWrVOia01Qw+2ykiB5zE V24VuipPGeaSCnALfIZ71YFRx3N0OfT8IesjhdV6l2QkqT9DaSzTV05y2hL8E8uXDo4vtlcv9sUa IeJBbcEp5X+wT6aGnVKCHkxw3Ju8GCcFRuai0j0d3pgY0LYlzhMXtZhXp4a0LKEdwV0AngM/ENy1 SL0Ypj3yQVw5YDpRpWut9YZEPP1DWVh8Ml39uj8O/+sGPeee0b6Sr+LsqF6BHmDWJTIWWKCxXtFB vccNxpyv3gnOTMUNLqr1RCGyxJK1y+2j+LIZSDdIVz4R3c8m0+QFJXsAuQSYy+IGDvzJfX1r1Kx1 tbkSp9J7GKTF1dgyjvwXQp+uvWr3lNIzlLI5mz3k6lRkWGEiiI8VKanOnp9+4FyurUCWd13LbDjK 2jJs0QXUhxNg0rkqgbCtwp7kL5YU1NVQ8yLnSrFRBZBbG2hYcr9PZRrT5wf9C4JeTmS/r3PNB5Lr q+q1ym8kWMbc2oECm2uu+RExwx2BSy571o9EO21vclUi2YU39L+OfF1NL1BvxHK8ivaBWdExNgdN axdRMVOckHFKP6JRqdpIvtxI4F650W2s6rbzDVk55NAru7DwIyF/DowT/6jYwRZZLzF8l2y9aARi ySA19ICiI95f2kBy4wWwj+GgXR3gxaFlkqXFx+6ZpvfCEc2w6Q9D/SxvIU4fIjiC4BVMC4Clx4Mr d59wCRMHhPrcbTD5jkMpat7ZB8hKl5tfLjcHmlVwJIhRk4sMSRmc6+sAOhsR/qTaXqfJgqU/J0p/ nD7DNTT8bCu6Ucfkma2iL/HYZMwy9uJB3BpCSxKxqsvWdUqnHaxpUcl4QztrRcnw7W7mVbPq/A1Y b/onFG/4r0mqO1M3ZWd6JgPHpBHoW9ocFb8kfjZbgtaEQRjD5nrOkGYIOloNjLzfckuonArnVJPQ FPdLRIQA5P6Pz0JZjG5W9CfLeAOzz1kzpchDW0v6BCOFpAohfRw6ADExGcbza06+lFqh8QCMvjdL PdhMPbE2iATwoq0iPdL3YPzUP9pnwVjsJ9IpfKrIwHBUeK/144Xv+t3A7vw5J+Ipf10gI+1sSjdu 8Bef1GdRbe9LRKnqb3duwwQ3nTwJyOLJkEszefgC9ukPRUz4CEnWP9KoYv4nIV/0HH+XOSbjE8bc rVKMG0nFyGmmlQ1h7hVT4iiWNHIvzQHv9jWw9INkD8cH3U2K9HspAx3iyXNB6uovtL+ksYkoHJXg HKOA50ymARaxr/+iD1r7rX0eI2Y3Y2ip8f1+R5pqOLvzFSsaa6Y+N8ZUhpVvZmK50Evmzchzohic 4vKYVpm20J4vk3fdeYzGg1u4TJXSgGoI7T5vQqBFgkfVCfeI37hbJtHuKZx19rd/ve24ntPmBz2p imNvUXXCRcqfSTBvr7V3CSSAErowzm2J+XQQvzj53M0uEN17lj33Mdfe550s2q2dajC+7nrWSfzE 0bETYNMHnTfdvRCHtb5SOkfs9ghtcuTecpmpR7VosbtfdJFze+OCXWQdQsr9Ggj4qMB+/VhDk4Ld sdBE6Jf36CoUxauxCd/sZq0GfEDS5KPFvPO21zJSaHDWznHHsLRZL98jzk22sjFZyFxzmYW5j4ph u/UqWovWKxSYZFhFbTU40oDmm8jQHRAHYWws3ytJOjOZdkFv/i54j5nDicmbIwfYbedwCpAcPD/p vnOjc1CYMCghVmZLBeCJcspOXYB5mRUgltFXoqSqQyXZbYTChmKocxsmvM2vUqlf2BFByMCGFOEG iyRvcaOgd9QtMeKn8euFjQ7WGmEumAm94yba0CW1fcAJTXw6vi/0UYtNWB3wqmCcGJ7zARCBA4Bt GW/2UBFSoXLJl+nx3ZXID5dFeHi3Fvn/vVVARojVk7R2KQCyVGSFK0IegoxpBOv3DxOLBNgXkjBq aa3j/ydJc+Dyw7+w6yhab4YqI3erQsudcAqEBovc461HjEvNp/0fqEO263sPUeTB0rLpACWqTSPl UzGPH9Hs/3kXXphFx5JEiFQQr52Prmq7L/n7Z9IvCHNV0iAwSDgUsMJUEMzTKcqWPyXL5iCVKyXC Hp1QS2mRuFloRFQmdZetDPDPD9dGdnNHKF9cklEfhUjnloIwGEZDnIZhYB0Qb6bKxWgbKy6i3VWE lSiqOSntbsPQmylkEd6Rs43srJRDd359RTQpWg6jMkqHtCja2LkgSvhMiPE38YfdhyB/mQ/c3D2r qFiX+Eg3wtUQUjGlIUIZlYfgrTXn+sVfTCHmDb9GMI59qOE6xbGmZdjIwvwYJ9VDp7yeLHCrVjpz 6jhYNbYqcN9QvUMuPSy8k259i+dSfWHtv+WSqdUdzsgXOMQD8dE2/1su4sNwVTT97CH4aqJUIkDy KU2f9NGCPjiUjywdPXD4dOgzUiVj0FiHcoN/vBr8xfgz24wtrr/ibNfZgv8xclMKsjyuXghVRAX0 EnGToCfZyAdJR4FxjHNO1FHx+p834HH7KOyvzTVVDh+nu3MC2IxxXR4KyyU/W9jPraSe3UP1+1rJ uAOk0tD/QVCw8ufrEJKThM+TxR3PBIBttPeJ1Go2Ire0CoZve9k+gpRuRxRt8qEvMuBVrw4wn/Wo ARtJp5C6lBr/BHNZjEjdBohfBRuURcJm6FYgGr/lOMTDPVIYXnT3dQ1KRhTNOP1Rn9xjnZ9cYmlJ ynRGdO54LkxI931XItLuIwIYhM8M9scoKvpanTIZ+wUw83B7M6p3dKUnz/vOnTuZE+8H/3pGU9gZ GDBAWpblTuA5JTi71NRQspGYnl1HRbjABO1BxT6Pe5m2RuCKHpZy4LXc/f1TsXjDbxGbmxjtTCiv kNvzRttzvRon5lVWeg3XuoyL7wAVFNEiI+SdFgXg/6T46k80ifoTGMzPJjz83o7tacV2Y20maDrk L+1V3G3BnlJkxLmSNssd3SLLYfWVXVcjU2YdmD/qApMYuWmktLqGkL5sQyOj68DKgWyxxFTyDck0 MCpdwz7YvphURMOO4p7AT6BpUvIjGIszCpOTeQVHFT7DUcjHHWFcCNP0zlkwo0h5SJJOHZ8uLxQI IEsitXFe0SGT1kiukLXkAhQUBmvDmqNJLh7U4q1aPPrdZq8v+95pZRuZskLHlYiCbx5bYXm0ck5S uyUlQ4UEXGPj9nUgFdw7/w/oVHL/Jmc8uVKQSZSX693wjuAKQtrPPnl2Rl2omu7Hwefme3xG0hhm ny2sX/A48VJWhNRnU2S/0b/QyWhLNnkP2Vx3qn97IUCo0pgvPvTqz1OBElZLIHYF/ndGMgxh7j6o 5cGcvzi7v/yXFkUQL7ZTMKE36joYjp3k7ixu9uKv6fGHLgllHNdbDSyDWgqmzqQiqlrTKIsvPV9s /npV+G9BFPUhlYPzN4ioBmizfMVlk6g3BtIVc9NopKM6UOsZ05SCpAB8hAOl7O2CkMREEKugzLxb Rq7bCcizfzFYqlyiCaNyBAnOYmEYzTiM2/QO6XLPBLxEhTUO4qa0H6DfZmAVfzaiIVICnbz1Rser SH+wfOMWh6jke2CQ+4+vb5LKIWOemtKWaDDl8Mte0ZdFqhwPAB/n1F1UAOkP5R0mEsmSCXXTwNL/ Wfv1SftPPrvlUj5x82GDP9tQD0ZPjbZ5WrZAnUcW+FxiP678ikPvjlLJEjnQpTwTVi8OIgWCAynJ Mfx6yX9Vk3tONVDkd7CAWCRJzSFYXMFZL4mn9O8w6GrcZaQlUBJp57vLLGOXz3BUwZKqxEK0JaZ7 T5JS+jBKAnWKl7S3pYQUhYkik9kZkm9r86+cihBjc9kcv6m5Wv52vzNszrpKQL07vekRIp6H/3aF KM6l5GYiIITRF9+ISAWCuToFpZ6Zag2CiHdaj9hnyx11bDNpLFeLHeabBOGrT3joRQkNG9ryFwFV 0pKu88cAqi4PvfMB+9yuJN6fiGvvvRtKLM84srNRnbZTU+q1R0WwNa2usH4WZxzTEFB7HVuMKf5P b7dQvfl/sS4hF3MRsWrfU/++hkFJjBNX//K9qeugmVjnL8h67srjMQj0K6XP3YxGm8wqzpJC+/v2 SMEIaIJT6hvFe6kq6MByq7mOGINGc6ESXCHcbKIkKksa5VTZfg9P+wXOGwc2FkJrZSzpn2B682Aj 2hJWkU4h6IQsKhPHBsbfD7XAZCBzSG9pYKpEOck4jw9UvwyPvm3DWlOAlZ2EO+33tTQBOrD9Om2Z EBMGUGLkX0LjnErpbg6q2G8Dj0l4/gTt0vR5Sy4+8hpLc4uBnDeOKK+KyugZAths+pWtd9KpnMk6 WspEkajpq66J/Ap1z1Sl6LKILU1ggA5xa4XeY5YC3thxUs7dv+Z6xwoJJRiGfIHAC4Xa0f63BNZq EJIqwrJJxjVZDdF/1cgeF7RZLzz2xqLHIIA3aIORSNp2MfEDPD/S6JOJhnitRUfb5/XRTrZWhvME BZp0kzO3Ecml2ZfHaTNxee824deenaDr78FDYT7iYRmkNBIrtBKlCaO8qc+oPmxIhh+J+c1mp/ey e3GxHnBDJXNLieNIKKVPnUGmGG6a+Jfy+oUIjweHlvXrIZsq8iGTL8KPrQz93JM1YUz2JfbgFA+K /bIGVrUrcCGZCfJuuV6qJe47KFsuxNq2zjMR0vYCxI/WdlySwk0QIfFhxMUi4uxLs1GyGdLaSJDr mNExyNf9IOx669o9ddbBfDKHoAkXPUHrUimL5BiLRwDCQmuOrdNFrdxTPjINTjt4xp/Qcm9ukMkX 7+WHjF4IclvrOwvFPpSaYiHlCEbciAjAHyFRswDkAS5Nd8RowgrH4NpfW0ElamzQaJ0INUNLh/hO fcR3QG147KmL6zjpHoyArqerQWoafqmmSJmOHGVp61Yn7Din+O9xyDWWYUzQHlHxA4VeW0Oe6011 SH9WFNolgvRwKaIvrKgYyc1ztQC28Ep3x5z5QXDBzebpZMIVL4BelnUJCLqcOn6TEM9Xk+ZyLD4U XPnuL8ipighETqbYYNS1klzzelTUi/09C1+XJSQkZhBxI7yCnkhzXIj3MyjWG5wP6xYfI+Ag6jKc xlXwol3Fi7TlZgSXVcVQKSx7T8/WyGP4KOCnSBJDHdvuCpsYvOZSm6078b6YIrOyaSl8Vb0Jw5wV lo45eNN7LDhah+L/n44dS0ar4/95w/r3BcS0RBbk7DFBDUXYFgP7VkzSRkY2Hds16wHsz23YQkka 8D9RQlwR8qnpUGjgN2cQGdBZNsrXUuFKwXsKmarN2IKxIi361glNTcso0+f1a7QyfjhgH6CBL5Ii YlTTRAday+XkJK91UEX/rbqMr7+wDoijwRZOai5Gpvlnbf8gUG18kwThKLtOms3Kba5KfxonZSYg FshVrgoTdcBMQFJtjv576RBo5iD0MqfVMb8X53wiM4rOVPrXLIbSq16FWp+cjvn0e3YuNJKF2j9y 9g3fG0zPV17ePqbi3bTANztntK7kQ+Zu2zfdh1iAhUQw0qhGYcqFFSoD8vegeYkqXljp0i+Ejfgg o0mwHAhz8z/2QagWfqbf6NjKrnIH/WFlxPSV3L9F0dClPzTDKeq7YCuIVgA6XOVghJPEzJ/XWjs9 rLV12ITKtS+VUkNH2y4MZqTx/We7u+cOQCeJGSIOrIIWRmLmWnWYi26Y1PaZUCvfsDO4UiK4QQ12 nNjeCykHJHJLkRXTUKGyoMT0/SxTSqA6QkG/TATkN3mPHhWN1yc//btE3km50OBvtU/cwS7kT+wW YaWLhM6KM+7LIAPSRfdjgp1WX/pCEMmdKBbXAfWFVqoD4I2e61cNiERfMELzWSPGxGeQuROC0hqE tHK5h+eJaUYYZBXQpAOT5NDLbFriO+A3HORZlho+5MOzbwPRMAVAUgXWgXYQ1OvutEw2lTlzlrk9 LbjK/VJTWfFhVsllIYAQnTlDTQplRidViEGuv9d+HVII/wQWsvhmbbBP/KhX/EBsQ9dDlxnv4la+ e612qQ43cpEqyukpdrnUv8WpuTO0MD3aCm6VF92tro2kK9lAtTH/w+B0OBOnpfl/ShsZpKChrTJW kwd9sg/d4BbK8lhtt0bE9DWeZc6DBoXbTsIMnrpa2To7zDJ0hjEQcmpHzPAisxREZGqOXZswWaxG eVv/JbvtyjUTonVbpl/I4Q2bUk+KpYzbuqt6bF8NseLIyIBj8QmV0aud5MAKEae+Zqz4K0jDot06 VsxQpWmCceZmT4jybV/LapVh9s4OqENXu4LaL4UTfmfD2F9bgBRTURZ6aq5TDmaJqOX7lKpXUZHr bqHVidf5Gh4DbTkCgdmim9g8QtqvHXiYFyqF4N91UvqdLn3kMSu7QMQxhAZWB2DppE/2KWSI4//N Sro62z0mOd7jB27ZMTEi7yTuJpCioSXvBwa8kvcxD2HCqakKsxrLIIXRlUKvjf76+9pAlfrvGV/8 dR8KPkB+nSKxoBNXnfFOZwjZ+E12T7Wp2mBQ5XL9/DQ3u62YKxpeb35Tt/BUtKxqtK5rExnPGvP3 Dx3P/YwFKFxRNjx32vP5PspWPEyMNgiHsNfSKxrdCvrM5rz2m01zhyNAWOHE6dIhAuTx37rV8sSV cpn3UX3V9LYQpPBCZaO8x8tgz/j+2cBD0nDBex0Kn/aTGTz7Ov+7c4bl8TiMg1W2LI/9Inp4h+qX FWEB5Axu1FtDZ3sMR87K+0DvYzqKRAdysz6HUE9b+3DQzhbcBsqA206hg85+nFNr5Bp9lpElJkLw gRHm7EAAO6wHfVkTI13oXrRgyju6suGm4L32taJvW36ohClhLS8beBS4+xGCJeSD9i5LtjphmSbB mRxaUajPlvdj4FXAdTGaNgaKT0boFlGs8X6GRscbZcq9Q4WJ2TJW66HEZ/7QV8+9RESQJXWlLF+e z493mKqK2reNV8pD5/BaTFTF3yaV88AOml5LU1idLedSC+3058jP1DgZMe8KczKA9zaoy1Cr1I7a HqdD6eFioi4TWDkPQSDBwMgcott0kICKpnwOfWZ3XR/h3EGtWBE2GfNsoQqQdyH7lXK3ejQ7AdMK +9o0mk/4g1z4yO657omUz11OqD4jx+9xWZXTqpD+QbqvuabkQVL/leZRVkNcqVM+KRQbnNfQPoZV TrlJFrbUct3/b5fm4Ml5c0jQXzM4wnIX+CcMydbZ8wCE5ydRmZhZUEuytqq/ERrcgJZSW6WgZPfJ NxVdyLSK0NzaVAW0VFf0mAyDqbDm/NRwfp48yBdlETH7n+JFvHaiqKMrDpNTOX5limbLcnKa6RJ1 gycxFjByaa7RdrXvcwGKq2+aCQ2lXCmOLicKG7IPYSxUrHi5YJa/EZsZEpNcOg+3DmcwiN6IuUxn VlaLbT/JRPCrps/fRaTu2SkG4AcDlDHR+b1JMprXNGM4SFZjiH2tn92bkcuoA9DoTdz7dNCJ5lxU 8Yws3xnvSaNLPf9euARdXdPdZIGOm/ooSz0jObbPNUTuOnqQV/mRt+kXF/GILizy/qFoTKrV6W3x fzUzn5jteEKx5C4l4lW2FzhwrylYs7HOyhFKAHnOzU5YzFXKkv8RGWKUAhi5RXimSVa/9JC8b3x8 B0sDCgNaUuVkd4iaDNcgH/glSL44cLGkrBBSV4UC48qABgCVXFnL6QAqY0HB/WZRMgymxaFMqROk VV6jIVOtap2ASAX9MiJoFrnrH45W1h+63judCMUjCn2qq3U9XvfoSpTPpLgoSMlrCKo1T3OsnVdE 4l1rHOoLJsOrOX1t0IsyB7psRwfPp35lMXhYe2E/TP1EZHLlF3geWxFvqFNEvJkO3SPCePhNrt0x Tct0i2gpVZtBdro0jsfPFg5z371ZlR9kcM2tr9UmwemuUjoIYnmWBU1Ank7O9rvDlvJFfruQlbwk Dr7WP9pP/1n28bvdLwPHjxQKeVpRI2loHbQRYuxAQZ+WVIbMyAp/EmrGlNs8LZoultH2dm/Qv9Yv BtK1MqEsdP219UHIUdIdd1rZiM5Nj17F98cntAFq3TdWTjaMTh5BSGb1l1s2NQ53UH8LPGz1hfgE mPmCk7ziOAVfggl/fN1idkIqUI5tJckGpuUTs1sVEW3RrfwPkZ3Bpo8jxyuFq/ycmE/OXnTQhOM8 LQnfTECtbbCLvfIg8re1/dsjXnKcGX432O8O81hEyJ6YeTR2KnC78TTEI7lhNYqXuNPle3Ht+Adf 7fvuReMuuV4pBkbcKeLeIp/rYb/5XZrrESFybv4D6qGEkhswdujMjc59ufOsZEKikxP4zN7eIjnY yzI8AqugoHQ67ZFcnsDh/IcwHdY4OsGAM4bJN5nFERyoFpGOTREzNlmr5dzVawKTe/TPJoKgiPgB npxYSV2lnPupTGwar0SIpDDE0rDdHj+fOPvsSAh7SZzM3uLCX45LglGRm+hYlxjs+QC0/pY8aOil EkfPXEW1OWFVzPIQ/LbfylgbyMTYa8Rf5toq3WbZyGrJkt+TxhRQNdGGOdXZC0lM0KxbK3GqECjz TxzF22YDNlNkYdSfDZ56CBgxFi9T3dePmFUqbE6KLlaaAqLpgAPAVX+N3sMdQlA5FbpBd68sfwSm aoeZqB24BD5WBZV3+bRE2gmXMxX8PORloqnOqKveZoDUcDG0mYlvdf+2YeyRcRdQWJLKQI+Z7Zx6 /15kyUml5taCNg5s3qz+kPcFn9OyZTljA+bYkGC8bmdj7NmU3DYs7gTBDIahqkl91IANVSGIBcyj D4RzGg+drC2naXaS8va9czVeS/DEQ071svWGHJAl88xEd5fBVoezzzprbIdqXzrQg782kq/IFutV pw8zrhQjotFhxArYdbv1dKy7OARzsmxSNnNw3Cl5VIQbEiCfiLMk/reRuGVctC64c4RptimGCvov kzVbSzhmm2cDLF0pg0oVs16M1UHKuiiEAUP1cGj28V1wkXOCfuwRfn7ncHPr9B7OOZNhrVvZikXR 47vRqn1R33/mgghaL6H95eAiB1zpYkmFVT2tms9TF/gVmL2x6FsBwOJa93LxO+Ijw7IE0Qrrf6w2 3GvrviqdFZ3UfN6VWnaeev4wtmIyn42pRehI6rkJ+b85XmWFM3HLyJc0nhW+ef5zskNjoYvO/O23 lARKtJtuHbsL0YUJAbIlI4z5bZIYP1YEzSunQ+dnU/EdwOSbloPfFx3xgbkcEVKos/p/lesW3CAK kPqCy9uryAv+Ofn2uEDw6GfaM6VMNqE4Aw9CKmO6wFBysZ6qLZH8H2NCdAhrfRSVSU8IQus7efd5 py1l9z64mLo1H/VALxmXNyK57vBfUdWn5vSiojkxWQFEzLLOCy/ny3UfQqk+TAeIxg443Fdqrcjq xBzJ9+aazK/Xr5vqgsmlYVbBs3wraWNELXc5FJgSexHwu7IIT09l5NS9SZIwaWMFxcJ8gp97Rp8n pzI4CiBtn1IRs2sknnVZXSOqk3xPY9QU6gS/W2VEoEP+sVJHUiYY7hg2e3xFwWhZWTeFpIHrS3Hc RDhOv37P5FH3g/h2eFNlbElnrGxYGQWFynA8+px0HizooSmgTPJ3TLuTI+wsN3Km1VRsqVg2OcLu Xeahe6sQh7DqYak1MPq2cIPlSbOScJao4UX9v8qNhLzA/i6fEw+EjZWNa4TaiDkWOKpAwRh9Ua99 7ZAcftZw6ZTXvUbz3HZ/sZYVTY32dCQ89ji5gQOgCbm4E4Cd3j6HrWo4Hqf7+sGl7f8CSg/71xeB TaqROBu7w6mo5ANJpJ01jr6PKKh1G4YNzZutItQ+/ckGfwxEfa2OuEZPdr/wMBnZt8M6Dv5OxtR0 mBe6adEi9X7ra9x2XYpWUvIBfkgV8VUjQaF0ptt/pKaED4wIB6rBhhKnmNz1xzoc5ivRy+GB7LZm ICu75CQh6gO/nY0NFQMjOAmip00HoWa0Cz3c/8li5V0EW93EBJ2J9UDwqDPgVbVEmatWew7tkC5N S87gQRAToD862J21vycbhjqPZSthFaHjbWtKLogP0cnBz1kEe685CyCUlWKmVq0U5lvgr3gB38lD nwssEMZs7OruVBiSwg+xvKnSDuJLcQ91T2wClYXvNXmBMWSVP8Ey5+nprQoai3KOXs6dlASZZNUY //VEXQf+p7AKy4/tE4xbDismBWaSkB7i3+HVxA3ZEpLz4tDVdRQXAPynU2MnHEf6NwxXFmre+YDQ bQayapEBqgaH7No2GlMyux/a8Otu6ynIq+ATDzKxoFjSJ2waSQhORiQEahC6DRAUWrb+buSxvg1r 1ewmmfxEa7o6jf7jRbhjGvHAzwwQNzR2Khy66xb9hoeSrV1EP8nWnKkuVWoK7dpDX5+ouxSMNeSI SwpUqcEi3HRpWdQ0aNWPbE2q9LQzdQ+WXrVbfYsNe+relki4QTTudk2c8TxEohzKYQ/r/do/4ri5 RPkfO/HPMzg39z7BBMXfQtDDdghHhiC+BOV84IC2YN/aF/fTn5GiVoiTOIOCP7TUAnBmgMEUsT9e ov0v1quicWTCjP97S4cUiNrZyz4RM8hYqHPUPQyQjBnNzuPul4/8IwuJjvPMEZeby489Bix/SryJ uuQnN+U26VYrTlc+0dAOuKicU2ZECKc/Dks2gTVuljHhMfk6/5scF45U4EomBpePGl2GcUzue1OI mGfETuboDJ5G2lFolyjIxbPL2v7ylu9LOe6GRow52iDxm/iKLglsfuTk+2dDU5+tJsRNBrEQ+zs/ 0GHqiqbXviAo+gbHnQgFr+4KSI2NUu/2mY4M883n9qIIQYm7vpj+B6TCrXeHKLHMZpEmA/kkE1X1 XEWDto29A+hZ/FeocUjKIofK76M566EhieKCqR/Eog0p3g4VPCqqGg32PtgQ8FlMAfwbqhp2XGmF gshyTh3XVSNn4XRsQ/q4gTUVdFu2Z9zOn8K33wjP7h7QNL4m5v8j1Mkkdf3cf+jtASZZiDCQiQm7 h8BzCOMC3lPw9WD32HrkGHCPn6huhyJd3Xcz5PQU7ORzvLvfvKUsgBcY+RPN91nkmE0o5TTvNchd 4cBKST3ITeXSp7ImQjan10JvjnnAI1WJjfzvrWxrgkA/amVdeQT56fvV1pr9LGb4xas85q365Edr 70+urAAJpM9VBmIH781hXxcu/7MvW2dySOl6KJ35Imp85bUdzVCpiTwpQ8RKG2RxGn2FmfYVXV+L Oqz8R7TJL7Een9mIN4Z6Ch7ZhTExIzspKvNaIRw0WFa0GTCS7+Gkg4zNR+kYLDPK/XRXGdyBEJ+Q Os8u0T67/FuFXsbI8/RJH5Y2fIjV6YOULVB2glduCXerdMV82e9BpM2kAvgFyBB57CJpjFO2qTaf fxEaVQOIUgQctCz/twOx6z+HjZ01wRDf9KP1DmZMIeC//0yc5PHHAc2nyJgbE+cUojBeFptPQeNy mwehvZoyUfIwAkDbR5gg1R/Qt+LuVlOfUbkoAPyhLKKmTA5F1S2FN/80g63EhA+ZmZjI7JrB2t5Y WmBgCv8u0n1mKduxfcQbNPEh04XhMX5UI1cZo2jni+NIX9d+IvLfAB4qkBa/Lu1HKw0U0Ct3C0P3 oYINqmfGIg5zWKYcY2T4Z8nveA3GJ0VHXCehnBGuUPONFuNzppSrLk7WE61niwx1F0r94DTUg9Hn eDdZjWgnbrQX+iE/2PzIyCKY0Kwj4/9xp0norlTejRvoMRVA7KMOoBwJpMONOFAx0UhT/yr6tndR fAGw4iV2Z/t21juJEamh4Yc9biWeFhi4LIedtRtNeWCpDSdOTHbBsx+r7gLPLjBQtTkPASYNQohr b4s18x3sJ4tJVbeqvhvSmq5fUo0HyV3ed93u/iXMtls08KssR8xv8mfMa3UMwRMZ3bDUfb11ib2i yBBdmS4g0tzFF1MBWsCv96BCUCVtBrjf7CBsdzG/5HS7cGHZzXTHsPCqQOtntMySyfgbTm5y6x5m lFc2yhL6Pbu4Zq+ftNvleYiCFLllm3Zu817DEFDEdTdhwbJQv2jOTjKePRfuJsxpH7Ef37cZDLRk 93EXo8vBce2bqgy5iutPei6e6v2Rpc+QK0Tg52RaxrpyyvRI7u3Rm8ICrOjBe0AUP+pa5EvGSiAW fCV4AKCButam5+0yG18vsxlwYObQxJTgW0roDLcrnJn08BvPHpO+AMFfHlWjBcpQV1OXxB/Q0bYc zGOuNQM9x/b9/P14n17dqEpL9jeOEnq1qSBtV+D8PTsGd+cc46O8vILLYH3pIp/pR6++B0qgPhA2 H/CDKK0lphDRurVcPt/8j7q+kX6GkQiqppMO8Drwt6TTCte4Yc8n9H0a31e/1mYVeFZ8HCO+CDUS 8IgnYsSmh0xbgElKK8blIVntfaie75pUVn5qB9nNST7uPWL1bJXwd54gpMqNjTS8W67gOgrAXO/M lqzKH9jXsExSRg3SBgk3qGXlPOEw+2N2Pxw4Bbl99VZOT/l1yr/Od4I/AFAYIpLAZKSoD7sOXXVG /r7wE5jEsYddX3QjGMmzTY7rR0gpois/gAkOt18wzVmIjvr/2rXFT1DKYkfHXTmiCPHuJkF2EXR7 1N6tJQv6ocFK67fXJhiXx++fp1hZtT56soazJBzOxqpwTSpGRH4nB5xVR64pSgoX4804xOd6yieG UzAJfhy5cSi9/gjcXX5y0r2ywqZIzkmcMa3Aq4AZzTYJcx8l8LsiUnwmcnzgfBDhkL7BN1NHrQMz Kmt5yJktwF5Sus0NFBdytR5Ow2n7Di0zuln9rRGtzmQskD8zL5RxK88c3Ov7Wg0/HltLOEi/pKZE hks/xtImpXYkDiyXmQ3xQotmexng3+/2E6BfANqYLzqjr0ycXjaUk4QV5UzNMyl0LExnYkcS0r3H HTE3GhqsvHMZMkp1mvizKC6TGcybbrR6Zxb3akFRhpErLJ7Nngah9KanztvqNtKMc1q9N9BMO8iS ip+3GfaEE8FM8U/krAV2/ZzXJipB5+g3Inkdiu8mEtffGc8xDcTMQtut58b29B+ycsONQ+pFhS1f Gc5NZr98bFFqKv5v8bn/UjHNhgErxEwSwQtJqPpDQFL1Y+vTqim/9H+LUXyvRfJmGlm45AauIBFm 32BmQf9OWEQvsXB7KsXLtIINMEw+C/RagbRnGAjmrBUdCnG53CVuq+eyLrqK5nKjwjjmYeuWkjeS MeeGnoi87nwQ7OesZo9jte0s0AlBqErPF9LoUcIrGCw3FqiL0kpng8bIAqJG+QehTeu1EGu4PrIY Tl1il5txY1k+kBFz/Q2J38CfjJRuLtrhANoApuCE0+A87bMBL+vnK/YL3V3aLP+Y1lI0kE1U1JjM 3x21YXgPBZ49CAPrtRCjCMsYxS696k+1tyHAgQfEbHEDICeXxW2edXJYHwZgtlj25cntxO8A7Ry0 v0HFaLgO+q7x3s+mM8io11EGF9qZ05BRWTrZTi7R7wzGDaq4J12uhUtLk4XVkGgjaXZg3n1hgV0k aPcjpw3MZ7RH1b2WuKKhQUHwyaHHp4eKymNuCB/+Hualk7ZGgtBNX8qZCV6OHKWGkxMOaGULzkWK D+nKz97fpdOwUnGmXSLGAT6ffpgYhtiUXv5T5tB5kN+AZEGgboHcOoS228kqD7eU9q9tgDf0wDQc xUOfK9QAeYBYcYUrinO1OxUO/UsFB+5aC+Kcl9utdGOdrdemJaYCNWKKt0fdx6oT5qlC47kvfT23 /5//q1ct3nPozWypeEnRDpT8mzt19mYNFD1IbFP/psUCLGh6aBBHz7en611gYmOHncah2b7XBO1L Q/RIQTfU+3LboRigGUF56ZAr+fUd5Q0LU0FYjxxqymN0R3YHd4lmUR6/Ydm6cn+Krme5QdBqCPTU sH23C+/JEWwY/+UJZjMB1wJnw8B2DiCwHoNGQyOAX3H0sTI+J5EL5KSGI798TqjDe6ZqaDV9VNoC eDgk11q5OsoY50lpxQiM7woD6pAEVaCrD+p5Z9mgmeNQIBV50yJGsRm7mwrFjFqTOWKpMJyO9jqu Jx20cnW/RsTe1OvW7G5ca3Tb0rTlkxLkTeXl7VAyuRNGNYJke0TRXl/XzglAkZR+iZerzAVAdTPV 1Ckw0zXLM9y7Jj8IBlnpd2KEvgoq58sPPq/e6PjLPx4dhZGItuQXyK4zqu1T12G8EDJfTHkSFM0S DnIhR8PytECgmcB/o+wDyDHZQIYkWlM2L85ROc6wspV7bOiMZwkXj3NBauYjH4WrnV4mLzTzdZYw aZOovUVktxccYoT1hqMgg9fO5KuDJosa5OdFkgDk2rGm4S/ei08to3z7SRhMzZgn03AiPWRQTsGE DerYbbZkuhU/aRSmLbCysaoiHZ4IzlDCfbXZs/2fGOtXJb+B003nmYcb3qRRfXvj+XkBJRdM/DA3 QdaiAHFEbwfYWN0RWeZJnM35jE5Y9HXGfRcMzUe+QSdGrW1h3kApdaclSFRnR0f2aeG8cCLoKTTc y1Aw4j7+f27iVwMitM1B6IGd6AYgJn+Z09f1v2Py7lw4n8T/j4giFqHowD3YjNNWH5LCyf1MeKs+ 0bD99sFpNzppvtfCDrBc4Yyf9878vszxuRzpJDTDwXpIkWCeg92LSxZaK9dInnDfomjAf5VlPAQZ nwjTzb861s2NJEoZFeCqkdMxbr3ltgdT5kPpzM3tB/cXV8759dtUorYuG+qcvO0GUDHvVjzVePkL Cka/DWx7eX3XK6jWsZocXFmzomkEnJB/YydzhFeSUPpg9u49Do2A7JmTYqIVJS5NRYwn+QrkYqT3 AKY7do1JgkieWZE0/P7zO1NNkgL+Yks6T6H0Y1pquWZEh23QDZOWMyX5z4eDFvQLB20A5TCBhlt6 oRH6efrSE3Org2jhH6o9rGR073dxuE+UYYI0FlUmcnoFWzb7yZQ7euL/I74vTfG+/m7y+jg/oj4m ZmdglhRX/VfGfY4CH7o7xvvpGuzFsNVPmxK4294WKhIHG6aTDx/It4g7Do+sf5NPY6TbhwZqDwyp EmDHjQUJnDcQZahmyOZ1p2Od9riXJo+rsV6um6UuDj+NL1nxy524oYCqYjQ7fs2dT5SB+n6lKiKx 0EC76mZgfrQc5FTf5oUX79V5NGhvq0L2F7ESaCKGcFEsFlGs8Rd4XYC/Or4BIM8jNmWv+OMlA2dj QptP/cVgSIoLvWLuBn5F2xX5T+7ROxJSNu6TdCxJs05ysChl+kJIllm3rQL0pEZkK4BkpSLxDlg6 bPa6yUiSH6oXoMiLoG2YePCsXHD3qDIqw4/3lTC8+SA1Z7WXXk1Eicoc7mxpXKOtDAlGviqDs8DY AtkAiy22Hw4ZEf/LHEkkhZwfZ89t7RTkgNqyppdg9D5BmqMbXs5zv8wKMyhwLgqVz/LNe48valJG SWrO7tY15EG9WT8g0HpAzGfMtTqrQWPMVXagZ0lWxT/JNbNCPnTtksIpb1Ru3iARCYJ+Mqk6Qw8p YsGm6BsuHZKWJep+dJJOURE2XhH9FrUQmt8ONHdNgAX7u8xsII9sR+FodPQLS4whXKxU4d8xt9ar BzVcJEhOD1Z/gFJHP8hiif5Kz3hVyMRSfpiJ3WLNs9XU59zQTbH9M4Fa+pftHrO/OCm+rFAVRmMk yLC/KrvpAXlgk2aB1CQbluymH7GTSejNyGixLjYpjOui49e90IdWaiNTzdnMtnynu0SyPWVZXpAl DZP4uGixh06v87jlE+W+mBsxS546XOgEVJXX6qC9I8iovECRoprHAhRHSVwFrBhNtMHbpdSPGlBE 0f4jU7E5ZmOY0TQFOdNSwYnL4diGujtSE2rPt9dokxekcvhLateQ+9BtZyTPK9HRjlBI/jOx4BAn anQ3rGbtjq6s2vT3E4JzQ6AO05SpR/p/OBv7Xf1d2ay9JXXnT45pEe4JG5rYP+u6HCPatT6o4cf2 QF8CmOzN6vXJfN5BBzQytV+hGjIs429bVIU4prmmnXFu7jmq2zbWB3iykmC+NrV4L+nS51D83eq3 uZt2iXwKeK/e2K+lHUZ0BHqI6gE8XKT2iVufXuphq2PE5G3mKvaIxmNKB5kZxvL5z6OPwLYZmBli 0QzXhpfY+rMpyQx76SnyNubECRnEo4kc0FW98nGveW5swk7GL+kGKrjQoQQ16l72j2r45RTtfDkd JbCyxPFdwXJvrcQfyhN9uXnNqEka8fe0JXX63pzpge9RKQSwdQR5f1SbddN6Xd6KoRRULCIkwL+y BRp0B2lyN1+eHXMzKz3j4Xu1eROHd6e7RucYrX0fulxGFMBS2w2KKWYL4PpxmFzmfq+ctBpCcdbi C6RdXjJ1DUNr1wbfC0eVxcq3VZGmmsrajABdYvWZCNAVxs6pNyiYt1TZjlzQrbvxhJ3LKWgq6kB+ 6JdzaDPXuajVr0LB7hYasdEB64D2jUmYq9bkq9iaYvgMNk/JIOewTc2o6Gs+dwA7Ox7ObXAs8SpI y7XduGF1QlG36hrAb58k/VJdNVBchQNYBJWxh30VbpkptKhvyEEFm52tY5tHfcNWpQQYtESrFE/y E+lf+60ZVWo8K803IX5eP4QO46ghuHIxLMwXOt7/0rOg1AL8Lx8+d8INt6OtX9XOZ1RHmmteuvQM Z0DTNKqYQZeh/OckjZU3UZhFCim2NMhtVbN8aGbC8RqASWc6DDE2oTN1rzun9/X/mGzesYvADSR3 KmKicCgPg0t0++OQC8gheG7Pqd7cWXdlXl0QnoQTHd1jysR0UzukF4V/rXmEJkdDgjs/APkrDSmZ ELNMZJE2PtolrHUF6f+WGWoJdX7ZxBfKbSleU1JMlcAlO8EJscjBaPPxBO4llqt7kjbzws8/UfAd PLMgPCNc917XG+RPKd3hIAvEv3Pf/NdxeWfeVq1cGQz7dsa8HkJUd8AdiuRW+Lb12EN2K67cFkrx xoX94RqClW75RP6pc33GMHfp8b7jRcRfOuUTHmJSK3cMTUd0ao/S4mgPB/1P276rgWgTujsDA0pD fKuUYi4xmWgIgWKNvjRlMdpBaXWE8gRgfi0RIjAv/Q9regX0nBrycZEEBd/5zOtAnKLKJ0chg6Is /Veu91L3Oi766WZkdJHDZ8PvA60vPN17XpE2B3jPJyuXKDZ8m2+JzhcGQt/XRgab3y545QPPU9Nu Q1Kt7AVT+qUxc+Rp4seKmUc8WTQM+xr8ctkzgZ0D1m89j7yEr4LxcTh2ORMAaAzw+qFJfZPa+5Rw UUHahKs0BBsu06Xl/6IsfeGbifMi5095lrmtgHm9FHAfJNUN+tRaPb/3wH0iZj25Adpqz7EIa/hg /SUnIy77EmV5hGwhBEpSPRfpU4aH4AZ+bXU4XYPDXbGuvUS/Wu9xM6aE5a5iJmD4st0f7Qmx6s5H UUR4FtoSEuL05j7grnMuzedHyxLE5/rzjJiojfx+8g3FIRI7nRk92m64J7o38kdj0tlyvUexc3Io pdFZBwjUNV0QFyqZtabtgrGEQMVV2iwv3zdhwMv6weUmE7RyOa/SbalgeHCuK7ADoE6bR6CRGYBy bkY9HZIegwj+Cb8fSqJmsFr4inPL3vtXxVImltsFdPZZ7+YyNQ9zoMKIZFwVaGwEpff6Evx6yMv8 ykI3GFhH+4Cy+2tXeHeDq/CynzSy53atf8yMnhkFYJ0leIaoBLna/BgZ19MHyJkfyurGy9xR1Qdk +KJrKYtnBB+Hs84ev5ztP3aS5TZhudSo+FBF2Qb4j+C3khdirU6Y6Co1RCdDosi95R8ypxK8c7cA kEPePlSsucZqAHP08gSQkO5M8wv0RwDbwwF4bDifpSD58OKbQhcEQu7ymjgi2fl1BBYQlEMoVtIm IlJNkFCtGlKDeZ+ORHZBD/MR1zA4/dCQ4jvyWFWugMbwLI3R6RDR9x8DbhY42twtPJIuU/8v1R46 RxipKZ8zoWHuH2gr5mGWtMTcZgAZFvScCBsUlZQqbNKTcO223OnbUqLrWM+9ITY1zoN3zjhkbBzJ JgA2AfOBJwl5YwuJ7ijY4uFFVkPd1wtJ41bDdNB1+zw6F3/1OL2WIGSBCOTJCzac4XoRz6JGmj2f ZhQU2U8hXFbuHB/6VSz+mPqzmLQXs4GNomI2k+hl2LOVTYIIKBCSVERwdiKOfJfFUaqqNDZ1kCWX 1xzkX03XE0QOeisx+Y5gwm+ynAb/Ue+DECYeAtkjkbDQOJ3imdmNGBb5+xXq7268S6hIu02YmoWa Z3PJH4YpdlGK3LKl3JA2V+tZJRex9LjZ7c/vWskeWqWBSN2mM5KcuKpoaSuEKPkWm2FT/pqAoxt6 5JudA4j2beRovce4+qbsipDs5GBVMgn8lqSdU8QqHx7qvtszBLgr0MdtGuV5kjyQa5C/t6ce3w4e jt6RuWTN1xtrhXBiykOH8dPZpLu80qBlvzcRYVsdMGm2ZkE1Vt656jopqXGNoDJ9nC9Vg5YDSOW0 giEEaswiOwZHe0qkMtpYt/+akKPd2fk913XZh273faNRTu9NYa03KGRJu0SyL7Fz1KQDT3v0N6tL jICvLndO5ALWNcjwlJk8hDn3xfKGS8AGHSojTbMe5WnBuKlCfvJl0KNtTpnzIHBdKU5peYJoS3Jg p8ntHWfa1QsTuR70w/YvMt7FSPyBOUVHdGIAGhi8BxGutXwt7RAAdAWoGSyGc5S8Soh08d2ewVW8 GePE295m5dZoj4qGcVhKJFdUy0Sv1hzzfIr+s7pQwAO66kj+moYLKWKaNCdRNkKzeBaFaGOQ0zgO 7QfB6n9TMcCQiMZUP3gtWF/3uQTOMW8upwCc7IDxj4IvylZELmuEi9CdBHn4p7n5YndjRVaAkjGk SY48d+6aM5NCVRg8fscAJAU8SmvJFhjSAFN2E9fuhOC/anD7k6rVw6SoZMX2c5LpjsM30A2O8vDy Ap48PU8EaEcOlk6QACWJmyt06pjwdCngufvRbgMBobeClHoiFZ8NquYWHkqTw14y0ZCOZVFMKdjD 3UMXudTfXNHT9oCjQZf9EnKSbbxB0yC2ZzTXSXmFjlVO/qkkh5JzAv5/nmfr1AwFtHt0Uymfg6JN c8dImUx22GlhGeRpSank5MWIAA6089BoxERAFr8a2f6x2QYwqAdzSATF5pTe9y7gbEisSp2lMemJ UgjeGxhtuOJNFkogi7CbwyIpzfTVELwpGEe1XeqsEC2LkTHPBnIU5OkirXwhD+QIMNf++LlxaGjz GZA0G7WOPRT1D5RGsYKGNgPoIubirjc6XcRmYvH731JAwK/Ki+spHU3rI1A2+tc4zazwxfLvGoX+ MBWrDpU54FziNIlsVa8KizaTH58HdRa/fKzOlJ3Mh1i4aIQobbeH30GGuvvvFBEIyhI5jVDLAhGX TFvsrMgLW73IYQ39psz5iaFWxkVAuNKBsVDlY5/sRe86ehBts7ZDEFgxuBt0hx0g3HRUJ++RRzWB OkLfcAqUibgdUvf1e4Rn7upFh6LgxCXVX99StwNBDq5r50VrmwppSu4X2rA7g0IU+6TJ05/BuQEG +5sRmNRSKVEtUAFCSyRiiWoCKWGIbOqWpXDQpXQ3kUrXDpflRJrP6VoyOy6EYoUz4mnx9WrehTUR lPjEcDXL4/Pc32gJFkaMCfXdoDR3lArlQ4GWC9w5NJNTF86EpxPTcaQ7/QYvpdBHYQMXjqsKghND /AVw5visVyVYe3M1n/764xNxevdPEV6PZOhEUs+Y4GXWvkPkeRFZD5CM0qzRefG8vXOogYtsVYw6 /P3tMUEmCriqUwDOzGKX/qYioyR3IqC+WmGPmYPXwQHOOwpXelgCUPXfPWHUt7zkrli44x1jX0ce DTFNedzfyoH2xmlFat+J4kM3ICPMppro/ecX737zxEAoYL0quZW1a/aJW8Cqe1cuxyFXjW77Wktv TedRLPQj26iuKKAZVVFqAEh6Niuq6fyN8Z5mjQAz3YCs+DohHl1nzOPdDxU7/fEncfI0IxIipUnA cER8HpyK8UxzxoNYfPl8GGtyof9YWnswLWuDN8g3eq5xjQwTp3eSqrdU3cqJC887nsNQX0EDJL8e DlpzQ0KBe/VsvdbrdgaMQM1OgH52K/M/1QgSS0A+hMrcM0uS1BL2lQzZKwLGLWrCUoTg+Pr78Byr aIeacqiwMhOSWDWLdWAlBRHsQNtAaIxkRCiSzvYsPNlD9XRHbVS9ryY6uYRDF6J+G/0+r6fbDXvG jG1dh6gF6lhC6V5gsunf+9zfOmxgHlSb2Ld5OZkATC7rCnUqs6Kr5LG/7t6FO4HNAXWG5f1GF4T9 VLSLEeh+XS3XIZhNrf7R5BG9iVcZVEk5sYpO4YH+tfaKqNd3z0C7awxOsSLY9hxdfB3TXQSE57FH xwHgu3Usjl0dowupvplrfw78Ad5pXqg+KZTYQymIvnuSA8390AH+O8Qd2wnfxZ/7+M1xcxUlqUUC A2NKryFK+w+2G6b1DK9rfNNT54264INZ5uB5ECT9A+Gwpz34PUyPIdpI8PoVD2ufJwIxn6oes1C2 OI7+qsXdwRIwZNUZMHIwP2AMBkCnb+AN9g7XpRc0FXy0ZlAK3JjMCaXoL67S64+ImGy6wI5drlaS 3MdYitHpkhf/GR06uD/+Or/maBOERLrKqrD4Mm6qO31jBqpA/B6vZvqGeDxY7iyPUq23PPv7jkGB mMlUT1Y7tipYdp6f92/sCYoyOELTggC0AYhVscxdkFUkbiyIbHorJa0STruxmkqhbnuiQdOThsZj ULBqEEefOuzQLSCkO4Pr4MYqyatv4Y0l39BGN1ICkzefqFBmL4dyvVAeTBf61UJ+hThEFRgvWhrs UOUC50XLjfY47W3aI27leiviw+JXmMD2WXU+UsMvSKp2Tb3D7jt2Z1tZDnqJiAllGUF6WxwV0+7J 3bp1jkW6FI2HDF19f1kPxNTf8goWS/jdAyRRW3RUy+OHJsJFgYuqGeBVZJAJun0oDfvmQdsPxO/I Cd+kIfRzRYtVTueuZAkEc18+1D/ZfRw63m7T1iYxKm5/KBiqLgdQCNEeyOiaeLaj0KGgnS+EOsJx o4uHGzJdBOd6UEUAxUGD5rBLe7Kp6RhSvPhh2UxzdJYtUKyTyP4tkOOBGElRqzrxZRC5U6lqrA8r w67K8FoBomRP64+wynbciWCWADxftUud2vKTZEDMKVCt90rFzTcpepRI87DkKA7Lwf3T6ck4l3mE RnepC+l5kjKVB//+Ws/50an+E5GbnTSwhPmrumkL1OunPaRQewHY0lsdbebGbHRs6KeAIXqiLLWQ ema1oFjQtWXovW8RhLsQ0lABfhpcAlRDFwnuXmeqj0mrY/KAI/b0WwsgveCN6PbWE9iYya0Uim7g V0xUU4DAAfZuVu95gkKsdF5tEFCYuHtCte1sqZnHEj3VVX9cLJUsZl3EgSTXtvUv2rzQ+VOOtGpz MQICIfrTnM66NMFnICWYgrqTAcyugUrWxPmnC3k7lYx7xuJwPB97L9jWy3Oo6Gs36vs5VGMJK/n+ LA0RBfmtfQxOmuxMjuc2KrECx6M7kXZ4pEe27zSanaJJ/T7eNkyM5G3rHUqp6BaStFyn6cffp1SD V5xfmeN3p+qYAoi2noT9FUTNU7zeqpGgN9EWZ8vl0x96gzuadbUACTjbwqr7Pl1wLY3U1+E1YVAr k/mu6pHoeqN1FrxbntNEQwKATwPI8bhaBHEEEI1Rkt5j+PaFngM6vZX9fm9eUsugtyCAGEijs8cV uXKl+PqYJFnSMg2qZAxu04A9WtvQs+oHeADy+lMZzjuLNqrKFxzgXC9atjHp0gZsiA0XU6A66k76 FVamdgMGZuds0cpzP5H3RgeL52vY7UFpODgfkEDZH9SG2mhZrAz+MtR1ZoaHQmt4vXSeP/yUtfzS YdbiTI7rb7XOHMyZ9nuurlaFKNioHdvxYs2xqi4R/p3ZX4JcMdrYPcgeo6T3NNQEF9d1NXn9wS00 mqlO3evwHWBNzYm0Lf76z3ddy1/FVjCBf+/oSZWGnT+X477B23dRgzsYDss86IriVJHBld+zRMBw LRPCel7P7Y4ur18+H+Vs6Uw1rfuInwrW3LwYmjmYIxjj8vptrMFOoDPlOTEtGYHMtLFJGIpyqLuz mEMgxSgVf524bluVJrVPp+r08yuyFZQ3XGpXCaIW3InC5IgyNB4PPOV1Zcy7HCUXIP7LwsliPnEz U0mW29tlR3O16ehYKxmVQJ+AdVex3KjDvdlIVrf79L39A1WRmyoIWUzCADauq/b7h2FtfP/MMJm/ gkyvPP6Cxm1QTOOHwR6wDTlFDMYJoOGzrNBMubcr+cMLFqHudOC9S4bXNdYIDk+0nG5lvNfIwQKz JCd2IQnwzupH30Vg7PkHZ5Qych8BrlyBJ3wY8Z7Z2mRMBihswQbRFA86s3f67CptRFhp0eoU7BpF pQ0tOWf8ULHy8280PDv5uNCH+PC9xo3x8EkC1S8xOD57Eae60G/KZZ1FzBxc8Jz41EiU8cxG6E8X 7kWNjkHao/Jak2rTuR2w7d3daJEenA5mBcwi/fsMu7UPcrob/tVzs6f1qBAERJPJLKbrAoBxyIRl 2KsZdSOQB3wLiccZkJcsF94QN+x5IwtGqpDU9spP0FkboLyyQqYFhImO7jkgoBg7ABW/MkY3T7gH U24KZrzXqE5dkbQ+L4rT4Kqm26bKrUZBwEGF9IBqfTATdaoNvS4X2GNr0hoP1IF1W7WYMwRWb6JV eu3RNaKnu7nU7CmXDbyUdQmPhwo1bYKj78+nFOVaCRj3pDLynrKaHGsX3+TL7LRZDzBjVC9l1qk1 XZ+/Gwyb/pPX8DabwURZ/B9r9m9lJr7wFiGmSEK58cSfbxjpMEMrvuyqYf4nfbumBv8hd5B4zoWT VRHAFkVNHmPTq+KhVFZ37iKTr6M+tzW6m0cE9ycWI9Znq70NerlEv7IMxs41YwdldiCY6/3uDKTB /nVfXyqkaZv/Ikogpu+oH0/Y31by+aHB0oUKRHuiycHtaE5VtGCpXl6nSy6pz3oc1TuoQdnAdzxn kZ+DVzHQYqSbasC+0MHnGsNZe9TOWP2Nbn9+HJImRSljhHy3kTzsOkCkIqnxw++fwlCpMgwrCQQy iZRhT+dTE9YmqcTdxBAQgFCWvcejL0OQDta7Q/5IVApDCKAnyBZBh0QIyuw4YNGB6fDL3+u+SPJy VX70dJh4SSzixgKB8tth+EpRkpFig5gQMnItSikt1Olct/SoQnTUrtT/lshpyOMTK0QiwGmc8lYG WFbnofG3AgU53rphhWQixH5/o/VLzlUd6AAyU0WQMH0pvhqSHIJZVTPPlcBkBpV4+Kt9z/B5hyx1 Ru+3dE/YNkZihv0hfzRk6RqkF5EAdG37zpXUtQ44PIISjBhsUeo96qQz1HW1xJtLNcue0HNtvndI QLFVwlLQXdxsxoTjvgUfXsP+ITMTCWcxJNx8umP7Qp6MZ7o5xYHt0gnKJmFieSxvOclRKAzZGIHK f6YoodWIgzdCl+xXBXbM6yZOfyHcyo8KMKdgFsoND/PjaBoAm1LA20+17BiC3ONF66zgqdUDxvyj 88C56Z+ZiAX8lr8uGNZRMRph9r5e9AU0NhvFZNJIdfamS4H5jKeVeX/slwTnCnavX/dW7/B9lcdg tmr1vSHU7bhapEaRvL7/K0RjUsxW3YEae9OWNM+5KvgIYGYfiEWOkO3PIRCVTl9C4orAQhqKuxTO 3/oGBX9MHUSNH+081AYlvpGdYVOwR3qQjD6MXszhBq8SkZpA4mMWqMGw5WResXGUShPkguxkBcwa 2ave1WRU9CpqxNiOARPqAzwZyJCgJrSneN47O2vYCK3+2YqaftFnCtqAOyI9GP+IFDHrrkD45kVy VhrzlMmYpd6CfiZpBhUnrFqt6ipVMtvRqA7tXMB5U069Rfp5OJmXgcD+4bhPH91sefiMUAn9lqn4 dIiFRb8+fmMSWSKmLsy4g5B9g8kBkfymAFxCmHP/Qg3GKLmW+CLeWc0HSnbWLfNHZZ0SjSyx4lOM boDSRFdDeHfwlCgpd3b2Fmp8aP+wbhC5x1j+iwNVHlQH369LgyY9tx0FKeSYjJ9IZzbNuRUTBHBJ JoSDCi6S7UItLdjiZOz7md6EMzEV+6pUdHSLxZn2npwn379+yAkRwGt/Hnrf7ou+7+8ZsqTaSjxJ cdJVvHswl3LAFkLCmdlROxj0pPoGgh/ukbaoV1TY9jM9Vip06AEMSuKYT6JxePKpgDR8aCZgJF1x +YzuSPX3tJbgUQVwIdtOcL3N+qywEEPwYzVtR4iDTP7OQMF/1lXrKIoEI6MhI8eW2TWI8HJvhxBq +Oqy/lpDPYLf8gu8c8xYdAcqNOpJPeiIWrxMcFG3/HsjlSM7KqB3WSFnaqD44K+RsUfJH0J3Ar2W n1OQ4+/G7znNaN0zZdjnmXey6nQk6YCpGH9FtQT47YJwayS6P2G79XI09sLWk5GBUuHpk05frR3z 5jJav1vHOda+Ea+yd6dXBblXuoGiPbnpuCBkios1e9K/Bq+R2/3BKNr8ZlwpnuPX4jOJw8rpg7w1 sztjCqJb3yycE2SH9HkW0DltlfnqLtwhMfFmoZ+ZtQOyy4xRwN1E/MEmz1Z+WNNeZNuv70V1y7+o Zhvcv5de/zCKobfVuVvmi2vt9fdOV89eH9YgWHaok7NBPSFyPv9Ft6aYTE/hZb8FkeVeuDcyp9cA zAOLGAKeO7fESZc7/HWq7R8kkyli7EXyPfH8ZqYwPosOq6NHzo9VTtjPlBMBIb0zrnr5t1l0cVEy hZ5qVstLfN6lK/RvP/xE1b6gtilkNJ/jYdyIysQSKr/49i0z/ypr5Pj2t12ghS+VSVCKYvV9f20G f/YE2NIH3L9Kz3SwFI6WyY9EgksQGIUoeLOROmFl5ustCQcjXt41KrrnuyHWeV3TvczdOH2n1jci /n4AR6ejQvYlzr7+4kljZeY4FbZrUmlkmWYVpWf3dInjvcgqttADT2VIGUeuUIHY3wQ7D+56wALY /ut/oNDEsT2obUsIfxEX9hLU0lLXAJi53Q26V4sGjotDMk+wPwnWIlgls0SDYUpJT6s+n+XqqgyA UtkFK8JCzHmZUtLSeaXl4g3axQ+Z6GKH89HmXBHWHkTZMiQyaZx5EOLYJZ4kkM8q76GHkV8uqIkz P3DHEdCKJrUAlFWxFoQPbBv4/IYjSEe779YuRv/Xgd68/s59PPJLcQFbYQPqb9ynLt2J6Yn+Je1K rdCHwJT/cOqvzieUMZ0stKZSl/4LFFAX7Y14oiLHqreGttY4RffTuKrIs5Judy1BnKoV9cwU/0OL Gg+vdxhwc6fM+dk1CwFLCaeFgHdnUYSvgU9Bcg+jTA9uRGUKYVSJBKRQYTcZdQFM9PrkPwT4dlA0 ChKI+pEyzelf5C+cUtUWPf81Ve6CzYJLkej83IIRKN6+oGmBOWkKO+Evu2tyG9kMRvYv7QXav6K+ Wsm1CAcHzFkCL3qeaZIxQ5SjrNh/W6JqSavPAywdI5riqo5N3+nSuYWHNO4o+1O/erKId+M1mdNo uSmCr5CvS8xp6wwAW1tsf3O/9YP7TWu8IFUqPTQ2KgqKelIvC0gvIIJwGeXNPrCWAmffW5S855dX co7X1t/DQird/NNb9EWXivxiH0FZcV1WaFV4xHJtf/8NBx3fs3GM4wCg3KtGWM2ll6P6n8xvxwic jC3O4D4w0igD22PS7BfV889a+WLar2IrfQMhJgHBrHbRc6D21Dc8LWC90ikhFeaNwtMwFPPZ2rII 4m06wVzGvAyovaEvPys5GzGLtJanKatfBpNm/G2kP5u1r5fMPnd9A3Ppah/osEXiO+zC3PO13H0n dVt0vGa/AayNe4F7ZJOueBMm7lYQ3jOp2x3zCa/VazgD5ViDkgAsfiiUCDCI0bdaMkf3Y054dvhC rDbRa/p31R8f2c78qu1ZIm48TysJLQkzkJYy1rnh/2rkD315k5t4n+q7WdWd73Jk02/NEej9Gl88 9g8I4LEuIJsdZrs4xMzR5OGliI3LH/uEqk1HV1APYA7/GIT58cXL5cDHXJ47Lf1ARzFhYyDfkISD 0P4lvyUIpnQLN0SLuYzaOs/3JI6cATYuXd0RF01CMpuggsqJ44Ddw259UbPfgJSgThiR49yyFYih xqcVGo+Fu8/8+hY4i0J9q4PxrkWvbI9h00dqmZc2UlZjNIw99NYsrrqdrppHGMKmi5/dqEUxMNKw t/0OemdY9pOl1mTFXn1zEW7UV+kPerT/vNlax+2CkpWxx/lIwaEGEwYKZ4Oaa+H6avCEcGrhtCva AqNg7JQW45K31D1bRDM9bt/ViFr6jOnppy5qkSnClNXjNuAqbEKEyzKov2+viqOLe9rb0YqohhBt zEB3xKD68iTg60XtZ5KlcrFK516VhveJOOTchaVz1I+4fwip209/QHJ9fjD3YZu1BfCUYGlNmk3h 4iMhVRzQrAXcTdJyd2najCJDwEXmdR4KytSi7+kw3XdqCvy8idBnLjJQLBPg+WwDxJmW0mvD0ocL hXNLFCuBfo63PZg48NYq92ygpbm0jnsV7sE81cxaL+ijeGxvX665J39c4NACQB4cgqTlWtB9dUqJ YCaEegrPpRuoTSSEa9GPtzE4DDxz3QTHnhT1bGe1x+8dKHpo2ue08hx652c/r/GNgKtso60nA5nn f4WqkMOD3dHiMTZyL740IuX1gAnqK7/K4oom8GqL1vsUfjIC/OLFB4XeAfwL+9PRTYlXbdpmxOKZ 2qvbWv35SifBjLgjtEbPz0ogzb3+Dhe5bcjpZwsExWD88iRji0jBilYd8CJSXZBM6xqUMJDr0UV/ QE/pMUW+iAYpw84vShmiD6Lx+EXPQRbVhcfz9VIkURegV7BMZLD1Rqs+6rsBFNfzB+pZ+BJRBgvQ 9d4MacHC9aOumNIrWxPY5NWmtuatqChYtwxr7DxsZLapGpz818bhL9rq56ByEA6LvP6kgLsTPh2w VnMvs/ByEpvEnxNhbn6dcZN7BdB0ElmZDnWe651wHLmU+e31HYtEX8JDKkfp/xeOm3c+SpSlWQv2 2BDc+8N2b80ejbeitbe3l8IWyE+rgqG069O8Z6Y2d5dllc0rhmgDUQRExuwbxNmHf+QdeOKDzHJg 6LrmJw0np1F5jQ4s/XRSP/6yLlxXueWN7EXwT1pZllGa4dpgHqoxWQt1nj0X8JomB49vAus/QXyW qjdABvSoWCih24C2aiKbnIX55N3YdkIA2vqJOs6PBYw5RWQ0IwqvCtuJoVeKurDU1gO6ep42gmvy ILiilLJ534cluyviBmPtLUrbouHLPg7ctfeJl6xNhVJS4faCtE2PQDXPopZRi5ySVb9STf8J+iG9 BH9I7u753jbw7tffNe+MbB+Apv2InKbtQazG8ukOO6tz5q9pdJs2e1OfZFfVgblmowj1rb9I+iOY SSylNk7IX9oYX5OSkQyHs/3WxCLU5TRCKE/eUPmKbf8WxueJRC7tM2WxFPcW2VjWHZBD6la9mM0u ziofEWja9MYellIIDdNNIlUT2POMiQ/Oii+4M7cHr8SKhW2+H7xSHE8IWDMMuWz+/3WQj/ToD1Xt BlBjWyx4UG3lz2LJwfg+BpV3MecQANBJ55ep4ElZbL+4nOF1teYvv47lbOwByE1Ab983+ILRshVA ny4Mig+4BARLCvXVQZNoKeej14z7VLG5NYI7O+EZnXJFDq3g/Eagyw3oaNK/cur/CgrwU/+L56y9 JS4bFDlM3qV8e7Ci7lRgpjPHV7jCVWFSgMccvjLgDiVtB2BQuD/0ddQ+AZf7GSZepUCAeHV3bTRO yUA2pNiBy2bjry0rAQ68jMQXBRNkBFejoUlH+MyMHOs8PbBJopZt/by6ObQkeEu23QJRiYPUcZ6/ F1oKiG+Z8bEkGYsBM3ZI7RD65ZpDWrbySAq6krQrhjT+0jwNUg4kuwoSbjhtgLqDW53vvmZqzpln +2r7vUV/0bWrnlc9ltb76LxNMSK30Cbr6mcxDUtHMGyWl62RUUtYxyG0KNXMnr9sNG7Tsqe/3RuE JJZnTgC1fhx5UZgP1PNfICkyvD4ds7U3AR6HOGU2kD4ZB4+3aog1frnYtkl7OQWybPAbysPAjhBK RDEVIRF6LSzcHJRMGwP2NM6JO4iNEIvas29cfbtFYwUDqz8eL/qgbM73KvNoJn1vetb8d4HNdGDV pYKLd6RAgJ3A435WXNAvD9SXSMB3nif4V6WhYOVOsmRDHTeeb85o4Rxyw8maA8GbG/MoJru6Wlf8 RN8Q9T1M2UVxW7gqXr0VeQe6hZ+2ktBxRlIE52pRDaeG6QaZDWYKOdA2oS5ztOktqjnmdX6um2FG fp3Po1gN7dwhk5A2bmWTJELqnZhMAujivp126uvm7+KXjR51OMn/VXZW4SsaKvSCZ+Wvskc0cZHl LlICld/Pit5dw3SAy17fdMjf1AtNhudcZ/LEWGfdkMcj/eRZq47DFJ3+j9d9tUKNqSQazivwZZO1 srMs3mAX8/NY1w9lSXHjXX4j70lhobq70uDCf8tSeiSx4emxbJQJ8wsRBr6SHGFXJz/sSKGiylOt O7+mdP4p1GefR3F0ybs7yMmk749idUarLOwuRmtKLBYzfcDy5wSJ4FYOOstPvOhdenGm7b/E2Vty Eou6vHfp4IbMT6OI/91tNcgdshS0/n1F7hT+KtaqZMmh6v4Y0Zh/++Py1D+gA1KQP5vi379J7LmV Fb1cBHxuQU+kpvGP3dqajjWvBuaPfwabXGPnNmj//EQBA10PCHolHD7GFTMNcUevkIzHsFUJAHyG 0nF1fDDxfNceb2DtwSbXpWx6YVJRbe9uWUapjkG6MlUdzAcwf7k4LvgtBPwCGGxD9FYHVVvUElNX E0f64ocV8vImzD6gTrn9VDS3uYTWnWBMCZzHJMVepOqEU7XWB43ftQwn4ltb6IPTvklCFPR7d8IE R8+KFOdS/AZAF8HYSh6dMtvLD8dE0ZQdX20pKmo2zgIs81mMUxvfj/LYtQFnGMimV5fTu5lIxXmO eb30oHtqnuBQ/9lkYhOSsEmpIiOd8s7Dlk/u8EfN2YJQXAYq/bdLEJB29DedJdzx+/zX6DHJyvbz UoOHHc2wW3+AZDpb2/xWxRFLhq8+t2WN7D7X4W047HLxPR3+1mhmNfFkmi3WPlSYZ2rwvYgfeA4T FOeIagotNwxCrsxHqrDBjuQITmSrnZmbBkkl0F3WZuQsChQZPLTwTzdsbh/oYa44AWX51kwWLmJk Fh2i0gI4hKh/3Y6O0fo48Z13O+gtoNHRRuuHtNIxTO1NoBgW2rjdpgEEoSRBNsWR2GoiT1VlA3gp g5j0mMF5RxsW9obQeaK+4BtBdJYZIOiH9na6yqkSS50I7fQw/alor9nIfWI0kt7IRww5zf6JPYfd X9FtUS/BkbcwVs0W593u6tQQph43O2mojMjKJAwo02vjj1894pCvYtsyFElLvjXfG6uDaynqxGiq UXbca7IJdH1Yxh46CWEpkuGg9ceQJphFjZsneTInGjZyPGILV9CIft5nDR2QvRrX/GyoJ2TeFUn+ LoJY0J/GEDIN5zoapiTVcF6LM+7LLEjjl1GATg9wohWngQrqtRcBsv+6r9nQX2nHrL9cZzyQDyKp oR0tK0DmtEZylUSzlT9MTcdXyL0oh2V3WV9oAOmX9O2XhtIlTYw3kDg9lVwqye1Dq4sMawgn/B82 8BTGS2TZUOuc1EhNW3etfEojjfVuInHKDd88KfvoK59kkToZCn9DBshkd1RTHswv/YerrEHm2ycj CZUtZf5rBUfChMVGC7ooqV3FpDoJMqsC/PuBWQYTAZoXIUTU4JL6pQet7DJAEK3ayI7dcl2sw3fI RsBns1usYmWcuXZvdh8gJ5lbTF1p/3saj3NLkImIAu6/F6vYOH7+mzgMK/5ON0S4gUzSWARmbXYf hjUr1xxtwz4CKyBwdH5kiai2FMwK/CQN2j7Ikx38/ujBAOaroymX2DoxYAIG/8oCU0I4p9zKu8or ET9+MLiy39BiPudzzoO0dAFsgym0hov+QBmFuIezaz4+lG4C1VleEEbQPDBge8wIbfNn/ICUVcCN eTv8Emz+8mCLx8WFGMoV0WHCeJ225zBntC8/HjQlnq97nN1OOfoAnsi7/KChCp7aYHOt64jQsSui 9BjtJhbCfEknw4/oYzox9uWMBuqWhkJQFVttq7Xk9d+dujGtojzJnJeva9k2jI/Pl338UV01E6+b jeh7AXdsKamWNwyMb1s7ApCFrDLNGKNXywjahM+5eXaiTdavWV8B2PQ6zVVSvQIT2ZyBBV0YL2ss l6qEJPPMV2LSEaxSm08TxEBnTLuZiKWfszmGIEdHoDWjlyB4sqCPkjzAECyrZrIb4n+n9e/UekKe 5eGHVwgkaM48If0Wzd1jKT2E4jaZda+FoXXS3ZE72mbwV4Xw7t4UDC3825m+nmisdzw8N5+cKVdx wuAVA7VPkKvyrXZce8Bd3c+pl6hHHkXkizBmfdgB1ZBXqocDYJv2IQE2KN9GCZW/zB8uQJVOHK7g IhYDky9I4z+GNFheEnDmkRlrlJfyqv9VbB6Op4FchdDvGv/p5KzaHesnmQDG1AlI/EawlIF53Rk5 Y2CZJp6JUxwv+qLBOv7E+AXMytn/apVLKV3jwNqXwVq77CfkyowEQudXr3cPXfg/NwzOX/HYcYyV 29nACqSRO23LuXeBGYWgCZbyThimI8hW++3QyYk1LPpVXUALCxR3ikGhQUwbLhzEOBqhgonlpJET EGBlY0J7r34yNPuLlQPQKNYeWP5zM2WAgMRQ8ygS1aZfOtZdmO6uuqdPvPywLxLDUIPBx8h/vCIJ f7bklEvJS3w4/lwTFZwwW6sAY3/FeKHnPkf+H0Lv5c5V7vciPz6yfnTj2frVkDJ8QfGM40LOVUpz K198GIdhHVM3svFEtdlJP1Lu0kaf7N7FGfrgGrOs2VOIVRl+TtAh1df0Pi/vyjIttZMh+mvZsyve KKCeqCFvneDaHLLMnaXpebK/qenqF/f+4wm4Prj9566XLxBSjlDl0NpbKt09QU6CKFB2Qqt87gB+ SUyCDV4JE2YdXDDUUr0JrZkg7rL0fxCSf1DfB0i7WlbXdfz7QmBaXzdQ8OuAHFqXgT3I/cNY2+/0 T9o6rg5RDGD239kuPNtNPcJFc8WaZvtgGu+fTokWSRDlKXRII+dL12S4idVPVwdTM90M89OXX8Av Vg3bCSxXiR9ZyFq+ZGIC9hExJuCWaWkrVONdBXKv3nlqGgkYZP+wBOrieIXCsYMqAWPkx/kso7R5 wfcb6prMComIS3tnm1EjCTkXWQPALNmt1WSC0bGORYZhvfncGlcYdTLOZbnZbdwj3qgeRJo/4BrZ KLn75X3Y7XxveHM+MGrReTFxrFrimr9YmQ5O55/7p6fjpHZDWhnoeHwbw/hyFbH/66Es/n/aJa/q 6HVX2kyhfLGaNO/bUbe/Tm+0RRlEIz0VLJZ+wEZgtD4drIBtYa9J3Hka95dkidr3OZ6LBaKaxfsu U5zMDKzdfIqCgs+QTdRsUdwu4et15ZD92HEDimgZMp7McK40SSSC+nwDNiNSttfVT+hyf288vqS7 /xyGpKckIEJVV35UaQCKnztEYx07uZypBk/wnM5q3sAf/UfuQWD2ZqyQeNhr/iF8lekeGb2g9m+g 4BUeloe3aNVsK7AcspwdSUCrpFJFka0H6ND3jlehTzOj5TkzvL8VyjzOuwbVIAZM4akt9LODuqOI dvhxg6MtZHWytjB8OoI7X5piPMXNPSLQG5xpmA7xGDJSwoeXBEkFGAYPOSa9+tQ7Q7oloej9e/e7 IiBU7kzT45FxhRtq5oOPQGxG10QtL7dusYy72WvcyW5DpHnfokmU8ry9r61jY40SsdxzNvdXcIv6 hFe+4E4nCEIcx6VHmnlpKEeWf5iTulLr+t1zvRGyuuJ7Ze29s0b9nqS/EKcPFEg8PzP3QKeQi1oY rOQSgKo87eL8wPpC10wLAapsAnQChsIOCToYyPjxk0QE7V4c21gtgvBc9yfbhRxFxS0I/pZAwa3C OOSvyKwN7pg7hTKxhAd8we/2EgPGl8UwAJ1praUGqVxPJbWLC4dyMWbN1FZ4HMxCD61yXvyqv9TN JdYLf9/ny4mVQtCOm7yzYG8zgDRd8mPihR6/XtBW+adLRwXU9LtttI/uhHvRQrQ9B0d94KZPogNx eEidrdNdNs3t6hHSpuRhkGBCQB12sm727bsw8ri2oJpttE5YXNzIyxARZDVo/F0G4+WUFTD9mVlL hxsi4CRYXn7rPk18l9jAjn8rKK03oMUqhaRloMsm8KbihGed56jSFPF6heIM1HrkCZyxLO7JKI8c 3F0WnOW2pUqLxSlxNUWGhCJLuG0RIg1x/cucl/LucnySAkOgjZsowtzXE0C8198LxXR4onibVTqx ullNPqZIP0cuFKkfdnlMTKPt8erBjehH+BZUzw5F6EPM367Rtr4XZXBshuvsceDgJOVnmB4oIPSO Mb2xYI2BfOgfiMqrVkUXfkoR1yT+OnKRmm/Zg1nhqvCK6GvL2oUhyOpP7L3DRm8AJt6C9Ymxk/2X 9Pc6bIgJ+pwx9uAi1u0iCzetf/G6PiHkIl51tTD0jmk+JZyVOqeD4QVfe88YDlH03WqiB8FL73rX QKzYYjROWhL0l5H95CtLZY0OuCrPf8HjbNegzwl4lc3zRmmtN4+3PsHM9F8HpLCLBt+QtJgOHRe7 MX+DdFG+N23BZ2kRGMi2/1qBgXM5/8wURr94z0uuHjxDxFB7B7EcoUg4b6bDKrKvrPKd7xX8zeWX QnnU+yr4E4FboTfTfgd2fpeZllcyHRPYd5kbXr+aZWC5UjY11ruePIs4yBB/T8qQH9RjSl9T0q5E nthuj0U1LAL+E8gHIgxKCQ7lNJaCveBIR7SgcGMwJ8q86osM+rctk6TQHmmgTYFA+hBiZJE6ArLi +ya8D4OSQhKHvz7gAgR7DKcsxyR4E65rCL5qXYl909qzehPmcF58Ys8+GfwnTvpX2OVgzi3pJhU5 JN2nV9ha1dBIynoQDAvDm5JZknxk8L6pmjrY7sqq6Nnu2JmvfkXYzZm4TUFM1wMBzzY2F01DEQBP PMth36wDYAbRy0eoCAILks6qXa1V6zGZIHv3kTps5itro4+zNnLBhKaygQOGdsUnZy+yqFP6+bEq gYsS5ZhNdifMZRuLFJaMHs+fa/9jcU6cBu0qroMiLEJGikseHLrFP7jW7yBWMYWuBBRDynokVc21 2VX1Twa4Px98F7E0kv3ShYnZf8/GmwN6ofb/oGOoy7nrSuwVSc8T9g1O6qGfPJECSIbKhtwA8LGP IjhRy/y//bal58YZmCLGLABsXnr79c9DH7kRT+vQJz/qgHlwPjNlE5qSQVQWmunxChjVYVi2BNR+ yhZ5Dwl06n8dzMRfdGhBcGyoSQDBxEK3m9h4C9defjhOH2j7sIX+PRPxDA75ZuM5hkaG9M901gDB zhUBVjfhi6r6oQtTd8d61yX1d1bnN1O0pzOWebqTQjFGVsHe2VdW/sRJpnFwmXFg3GshUveviUSh VrI7j3ve83T0TEQLKaV9mdrWEJ+8MsaWNvXljqfBagOgKHpzJfKhhJM27l6W7O8KrR9HQuJSolv/ T2+oSrZf0h4ZSyDq4mdZ2onpLiuSLIDVymBps3UKjJPZGotxmLXbGD4FwroVfER7Uoc43W5z6ryE fiXfAb88eP8h/MceHsgvQ8OjWNbUygUZ+3mEcNQQQQyoLw0j3KJCe4A9+JfDr7lkoEkbGYor1mKi Y7URvQCcSi5trt9DH5OqRBvNkTcaW3YPoyMgI0aVUs+RE1sYvEvPtKKGSHknN5/nc1iYE2n224ZP xPyANaekBDQ0NrdOgeVkcz1/GqAx4nfEgPXj01bG5SuOPUOdtRs761RC2YNQfVGcNOQxWDsbHUNi cynPC4cpptgsS1cbEa9eJq9sqcR0xevjq5l2SZEcCx6GXO1vNc01EJbmhDVwwPHyF+a4qGD/qyti 4mWQYlbHaPTaUmnph3I7RFDLXn9TBY0qTlDkliCp1ImG6qJkJwsg2h7LlF6NHGAVmScD+yVNG/Gx W6b0whtLwUtLrlrqi1BxvQcKWwgp9At8yUztq3NXhOpamtIF/CEafVlY/WlyFN9VZSn0uw4i5DP1 v+4qg9sTCokO68oDymTXytYClUJ52QJOwOfXPL0TvseUIEyxsCSCvlTrAHFQEjRFI6s2o55z0DfT H3I3KoeR8MHbXjQDy1e5bKA0gEsUoVymnf9nk3BERO/FSE0JLu1dF+l3N1ctOEQoKYWZEl/cKeJO e4JMFUM/0n8Qe/4lXB5wHb+cUDBD7pTJdKJPwU20oqTf9JrsNmL7WQDE7uYX+mW7J5EgwX4Cl17N jRzy/yJXRz4NXEA2lIDS5Cas9s+CJl3lNo+cR1Ys/Kb61I51wHy3boU21KE+3WWfUZBAhHJP3J0N tRcXoHC7TM9KKo1xppPAhGaJpEjk7B8YUHJNn684SuQxvHPo5dRD7AZvF/GNsCq4CGWxOyedm9uj K62jvttXuxQEW9Q29V0zoD/xEhgArRq7VPB0XgsJLU8Jwr8+AZ2XdA7cHPMr6KVm7HKJY9jONMvP 9TRVEQz3RHXjHMNGCIZbXyP4w/GbN2xzZiYzTuqeDDfIVxKnvINHFZMc6ajPpWOE4dtr2xbLxTA+ v0lku//8O7G/nGaaHuDVmYd2IKKglYJXCdqwjjcufonCyZogBrwhI8yPGRQkgmYTQfOVpCN0ntcd /8e9UoLJBpPMOU/hzk1xXLSBWNL9IpIorA3ErYlpB7c6mzfwJ08KZxzeJBDR9NdSawLL20p5ItYt PeDzMrWWs5Q6u/xgCqEZ+2NyH8oybalOx58N3U5qu9MT+lLn8NPiQGIqcAAA/grpvIcwYMY5tfpc fua+2CuCBOI6M+hvldh0tWVgv1KLrpVSPIb2PH8QFaosmFrvvHOIr9lojnf6fRWBFiqDW/i5Tx7q 2ibsXMHjzc8d44WQ/wb/mcE4FUrR7WJOzzfA3hPysCr2Vt6kSahUAsQ6fv2f3iPWthSvgnO40/0b lyhB+1W9TTVm+1oaYapZx1F47naJzp09Xf5YPhDOg2o7zVWzCV84xEAMSf/gTYvecbXPmBq4CosS 9BVfJu4stro/lEkDmLncLXLAcjeC+DrFZvEHjQ4Y4hKfKvRip+hKsXppEKC960L3LdXABZ4g3T9y AeqAI8ZDGgOubNGn+HKeRipJAZl8Is5tZHK+Fhz43dxwW1jx7LABuD4O79+Xaq7UQSmVDXhr1cPS YVyZpC5JIfK4j4Wvct0CkVsldrNLyUHCRptIpIQ2aw84aGh8YgDJBAt2hoOym6jL8XAHjIK9bcwo sgwt85264hYPuIWjjrqu75y2rlVWo6FkQTW0obSXgV5CHhLY3nJCp7qi6bSF2cIkw8TcSCN/5gcG YQJZI1QxfZMhlPY/u5GH5CHOQulwKuDjjUAjweKQdaeRmqE0OQEZXNBJ6bWzvL7HYRYGHkhJTwWK m7Fmc21zMhmOJDv1W1zERAOHlu+zMxH6GKNYWhtBLIXCLziqZDBU46/DuUL0RxyrR0AI2KuPI+WE ALDv91JW8j/74hQx9JpUiTILwFqEn3PBzNOi+kKxKyqVa3Q3z5WjPMw6FWXwFLXpVxI54jCrK9Mm YZ9BwalUqMovZftFPRtmQusQc3Ok6bJ3hF5qbFydDSiz52ykKupoYQp8dLp1H0R5nd5QpvAcVzAG QVamA05ZMjR3Infqz2qWIrIHsZN/GKL65vS8sNx6o2pcjhMrHqrwp4SgKVOIvg2Cw7zZrEfPC+1S C/WwXFCy9EHCZ8ChUaXzccO7aFoCrT5JqtOHaTFrNW3K41f/GdFvY5c0QkLHwiY2vuVB2h3Eo7Ae xvKsgKMgT1tZcCRHFp+Eaj8x1aJ8j6Tm2Qfl+HQPC1JhKM66ojdDKtSjPO8jxDJpRMT0u72TedWW m3LF98Zmdx6Ej8/t6EGEzRYX3rKIZI72RhLp9lO9hSQ5CrCVmlkZLxEitbXhJDv1MGk/Mn6bt6D9 YUlIIhPUK8bOzRHsQx2DsChIjC3oYyoCfuwp0HUFNporqVQBEd4zQQFjVL4CTMHuN38rH7jkmFvM ikoAXq1y3pM3C1lqFkZQ70upYwpWguKYXWpq+SnaIiYoy7DHMC5YcZyn4bTgmYssg9EK2oy248+1 4Rd2yIBPYhVF0s7pftIubZJhiZ+MRVUPD/g8QBwGT2q5d2P983T8Pvdrm2dTrWo2gTvI4b8SPFV9 QwCEIijdPPzyPknrOloM8+dP+xv0DB7Kde1uRrsp+xhD23i2HBkjP4Km6kTJwwNDMfJez0AijYRJ H+8ah+IV7CUHGwMnqnlqLkodq8gSnI7ARmEY7Oko+6zsGBU3DYPHYYFJtpuBdpSrhgh6M+rzcB0H ccGGUy92YzN2zVsAEOowJFNyT2gpvnYFcX0O4sL0AB7F+XWI4Y6HWyDPaVSioONgwW3cfAPt/Ggi HqL6HeNuFKTh0oNw9pX9wIi8BggCKJEe2CJ5mYyr6I2vqy/3XhVuSQMkW9ae+WZDhWiQk3BKga7M T7A/M+JV0KPsMhh3Nzie7vVDcCIubHVF0/lKKRjLzz8d8wgf+Rc+1hIF60f8jmZHtoZHPBsiLnf5 YZHFeYXt8NLbvo3OeKtHBgdLH9RrJLMAjJ6bL2Sli8XGQsd2C3FJM0QPiiWlO4YpUvfLu5RbCMyF +fMe7xRCCcusoFQVnnejLF3Oo8eWnD8z5QflZtdQOy24ggP9bt6a3VxLVCJcAQyN9qhMXJ8jWE+p b6g4GXs7Dm9uFiTh8NTNAKkuDQTHpr109KHkaJfI8YGc/JWTUCXsV9IlFrmIKXB+Mh2CFlRFHyvN z9tt94YWgmRK7KVwADrcZwzn9lndNPd5Apj5nMJ6VuyyVdz7kpH3W+gDGLm8fu4BYMtWWwo80eoA AMQHGKt7laDY3I9jU5+ZscqZKQJ3O8JhTnIl2Y9h7EiFixvcw1/JjQumnY3/nENMe/lGKS8K9u8R 5UMzVVDJFRQpWwy0s2FoIUsS2dYYVWj3v03SBBmXZRYHU83rqoehJkorqov9qEvro/Qy1Ep0yF1k Y4n6cqKzC4Oqe9eTBd9peUEz/av0Jq1l72n+mf3dU/Dr4XGwwrrR5oCh9NYectjDJF6Y55wDeO5z 3GgHT29uR12wV7/j/38h/eL/1qAb4gM0GbBQBH9AhAIfi+g6tPK3w7rTSP7yefeSQ3FiJDbEae9b zIec+ICF/ZTgLgD9jmg88LkoiuOQu3TFoDZ5ekZ4W4B32zWtwdLxIEWQ+NU4YdkPdD8+fKOtH2Mp c57WLTfW8zfN4YGJN9+L+fZdHvsDeGxl/AuJI3dXQ+4GUreQle7o9c6wljKRgeHPI/vcbewtZ8/F 9oQ3Eam4f1f21Gw1lGL/6V25uHTviUd9uyU1IwtZCjYSTL3G98hQNManl7ymmfbEvwkFAr/x1Sl+ syb0Ydgc30+wdWmIGdR4JV6tEIO2ypi2uavLDbVl1sbyFZY5kudoh5YKOhCYaSFksSz7820eqZyS xPCEEN/3NbGZRdmV3q42b1f46HhDn8p7MmXUESRQc0P6JqFYSwmIi2dwHX3HygnZN2L6L5I+kxQR +C+i6Tv68zqvTtxHa02qU56Uy8TDgYhczT+aNqU1Dols8ZNac8rZUYiRrDoBe7zrV60qpQmZF8Ck 25brAMhjpsJBomQ5lKBOTKDEWLGUyeaMqiZ3if9kTmuYpE+vS/4N5kfHjfdX2iwCcFEa4dmdHG4L cbkl3E67dL0yvmvCSlk0T2aZXuVj0JzqYBp7no3hzai9kDX5PKl9wj378m1odo/Re1Cf5mJj73P6 gOSvZlPri+ArQSNDNKY/LBem21u+9rZwbjYc3tcm7p04IledB6kZHm4F51VnSZBXelQh1smExk/y lW3Pz5DmzWdqkhlamOGWewcukELYj3HoA6i7k7z35kZ91WV6nYh0cyCQdo3fhqTSKTldt5XhnUog ZKS/yzyxjcFagzi55YOOJME7GzoTu3RqpzGz9RYe67UmbigAMRYN8KdXBHH0EOEdVu2zHn5XaACZ K7OXX4HfvyKiQvdEOYdmo1QN3n9i/0RgbS7AOekXLb6PK0Lva3RH188xgyz1AiEhYye4NPaIz9Sg qC1Nu5yTbc4GmoLrLS/nV85EsUaD2JWPocKwF+SWYRcd9pUDPaxb97MSPDjl0RXAshyOiIR1YBu1 YS878KUkAMsen+Mm8n2Fl3CoJ2lir8Y1r99jy5nCrX3cSibie6Jbot+i67v3Ww+lE6tOTkYnWLXN klKRgmGrGGso702/t4CR/c9JAH/6nF7Uv+WzXUO1fRqg+B+usbHtUY2mrl+MoEnRSKwSB5PcobY4 uM+CEMcGpaZ2SqhKchmHS1yIvn8FqdXiWKDo8wi1ZxK/pnGcMkM9dnwL/iEasgDPNOD73ZIQHbYp Iv4aMkC5aGqyY3uiS3R8/aT9ZITecdh4I5++csCf4gg7DxYfqanVhnFbmxTBTXNV2g2E802QlFwm XlPFZU7dcz6utbWU2uRf2tDMBhkNvm3zAlT127cGAARDn/e4UpQo4Ntm7NWRT27cEUW4pEFHI/eV 2lCeES7UnRofEIVK3i7T02zWeBSB6xqAB6RWUpMm0X+nKApaDztfiXuYRuo6HjxTyjGxl0yYxRvm xIwllhWs7s41j1cdvEPUEUa83ZN55ZHxwmAn3yKUpR/sFW+zGPCh4yfe+592MbSLwEwzualmZJvN QqtuPUlL4ZPjoMYJvY5LQ0UsVYCJSYoOw739ayd4rLEyv9rPrWKFJeBdll/601t33WdAQGWldOtt lCWopzlncJg9dUj7BdqHsHo+A1kbMGQhBsK9qWMnCSU06kBKP5kgrX7ZB1xGOtRX0QsC5sy6ihe/ nMQ9xcL4uiRwLTg+LGMZSBc3LV6QrULb8Dn2oyZc6ICbnYCzaEtLcJG6PPvT8/XE1pAfIhzQXqEc w00bZnI1gIlJkL4JcKXoYWS5/pwUls+7UEVB9qALqhyQpTYtpB7ad8ksGotk84+d/iVwR7MHvcLS g16XTBqwVxjFwfEVRWPUdryzToJvKNsG0UO0W9F3YNHJQ2ZTaXxtmDdR7G1p8qjNZaeAvMWlHGI2 z03ZyoIHjEve5eOq4M+pdsMAPN7ofCY12U+TPyKwE6+B8yNgogfSY1q1h0jUTtW4Yjtg4DdKzloR g/D15kHw2gY1Mds7K+ga5/lvrahRsp3C2oZGIq5tgwMvsP6obeP1ZiOyvpNUr/Q61BMbWOC9gFg7 ti2/5XXuYIghHxjbSSyzd8IBEtAW3TtCKR//RFGEthybbiLWZP+migDPxKZu8hB8vrv3s0K2IywT BDQiAluzVM3ZHik9hjoHoLcVvPhZc43jVOqLWyGaWIIhLhtmovu4wjlUXRbSPO5ltg58dy4416No fwMiN76DdIL6GJNF/7DpSbEFxAwzwQ1EgVbBc6S/1gh+T2B8VgA5m/8vyIlooEgc2gVVpfkK25z5 Fuu3f/VHHxwnkYkHAWpI+lG2KTMyXxmjJW2D1URltYkJ20Km+KI0YfB6XdPJ3z2MgOnAuf9PHlBQ KRIGcDjjSugoJcGGoTB7vvo78NNxJ2D6W0BaG7OjoA9QMsRnj7fHMXdDVmbPhzFXJCghSxVcshsj Q+X/hbY26OYt7t1B4KmY9PI0pqwJ7bWwbxAnkAmJyhHscDEmSaG7jPflw+A7Mn0XC/odgKOrkA7P FqUfs58sIP4/xGMJ8kRJ8YLgI7MSQdYx8fXFUmqNQhIaKC5eraA7B5RnNCoSitLCXej0ii6a7LQ8 lLOzf+Q5KwHGJBBM88PuwYHSlEPCdvWGt24GfE9SkrgJFj/j+1sL/s7XdQj+wEwWdtYGgDsYZm3I 2xOzjgeQaR5dRzQzCkmDG4IdrzXsD1qfqOYPMFUXk8DoeWtJ+k3sTAmo6l4xJLNVHT/aZOKMrVzD SCiwZpk+C/XO4pcVtXpn1sM1QT4MoKqwYUW7qzof3QNLiw5TUP9YS0w++mjJeHZLjan9NZo3ziL6 e+t2LrM6HpYVu9usae+LDRmDNWfS5OHgfGZQ2Yu2gmDeFTbRc4ZhHoO2v/z5nhGXuH5kKLiOoNaa xFL/7ZK/mWLgt+schQbYB2LIja6X5I9syOVwVPdXKiTgHrCWkblfqCI5cXMQBTyjR/TDeHq05kpm zHWJdJQofJYyEldo92YvLhFFZEUZTO6fA6xUG9ouWuk3HOjAFRojYOtIo/u41V2kQszDWM1xrFH5 NdxTbuaZdfbtUlMqxzPgY9m1NRYBaaGajUr4pCgOmLKONTdIkOu20SkRsJrNtvwl3MtcEy4dKrXH k/S44xgXZzvzPeQGjtowfFt8eMPkzO9k1J/ulw6zIWx7U2LfopCFa1znCxH8s3BcZhAsvRRF2G+4 C6/hwAFdgpxf5yj6q6HsrrTi3fV1LkXbCqVYntA66aZvIqykEBAWuFN96Nl5c5Jm/MkfG3xgn20N H0+Wbzgr2BKpRP2rMxKqx13M451Zbwwe458NS4c2Wtpft1/DtfskuiUUT7KBBpDRwQLFixVNACEl byz5vqD81mU4D9msebom8aC0DRfUiO/l+mG6+sFfcvCD/U0gq3mSMCIv1QAfB/LKdCjTJWDNNTUl 9WQIqtSx6DOAtIS9NNPqg+07MGZamJishyUEeei5rT4b6kASrA9aHj6avUbCNCYFWHCiJyNhye6A cOkHJJDIzkLlwP5DslDOFzwIw42ZWHENQGf8shYzeXYR/zKX8RErmeVZtvAJlMgTxHO2BztO7Id1 Omdu/0DUJhf2jyl4LAa6hZ9cSfmZ5W8yL4FwA3BYKhHU7pl7609FKlH+JgYsjUsuGBr1Ibfz2RNM zoXVnqg3Pm6RzGUdm7U6kIzepWXwcE6mFtS1qTT+D2XuoXFjmUbjxXloeDR3LsZR94AydgSVBoyF CU6ZLwBHj0EXRG0xLDsnaYzKYv2lMKfj8PVETcJTi3hzKuOjsp1rvagyu5PyqCpfgJPXefhBK9o7 NLICXZgKv1HTLor7TBja8T8T0Y2h0sJ13Paax+1XN9EWjlK0gPgZ7CqbSVk1IcEET2UCWc0EPS4G O/cprb13+WhTvRBnZDQln50NLqiT90/o3d4syotVlxK9e1ds5nC/6/woKLf0haJx9DJpVznIBbjz zlc3o/07W6+4OTeUJAZ7+uilB5+UR9RoQjg/YfwZSNXJagh5LewXlbAA1emXZjQHz/HRKDJezADv Zuf5K3qNCru9covqAmIHv/eCiGJ8c580MBeC02Q1tXeWmOJwntVSXk0sDqFP0NNdAEWUVJwgJlY8 zewowjC5Qi1zJuNmuthnytnXmOb+IACWpVuIKups0EV12Il2Y+RG/Hf40nL9TIaTmvQRgnqfVPX5 mmE2W70GUHERJj3zGS1qfNf3QInjk0H7aywCtRkywDaTnGMrex/qOd7AfzJxBLV5axTAu8zL3SOn 0jK0gzu0X48J0aQ/nvpVXWOfGAgr5Jt/r4a6Kh8aTPXS/w9WYYpXn01GFgfPdHcq+e71UL5Osir1 Cp8HgoIdkwBLnRVxM1Y0LJlZxm6v7tSE7t/RLxJtmU2g3HunpVjvjjCrWVx02GT35A2aeC57hmZn ucN27za1IcECV7kznmRWzJwf0AUozamxGOuIQ3G9VKysQ1XCJvlGmIqI9SjFVz660k7mhIo4u3Hh OKsT+0m9gWDGO/Bwet7EeobQwwpcmltluuVRysop0Q0NMk/1jRDhw1m/l93Zpj0tq9kJHH8MF0X7 aIlq0WKj7gG2o8Y5Jr5ApjTyjBfGOv14G0EW2HK3cRGTEswrTZkuLFtaD5sHHDPSudgMXpGvZXXP M/QVSzJ7VjtMaZQi7sUaiZu8ThfiWFXN9hdS8IVeskZ6ky/j81RSpaChxLlwiaENdRoM0lq9gmt+ 6UV26OPpZT4cp0sIrXI1YQgMsGr3OZ1BkkM3G2aP6SxbnpIaFhhoeBG5xbrUAAAh5pSCD81bF0zl t0f93L5PzIyTmLfuxbodBRIKqEOpAJQ8d6KBgrb6PZBcpEcTYsNNOBzhoIa1lYjBTnU8YvO/gn4R 0mYs641JxyQQdvUdeTUryUCpS8i0y3ByOgfQ2qixF4ETWB3Ahg6+MkSRLBN8ODAw/PItMEr83hoX W60Qc2Cmoy1KozCHl/oEqXn0WYFySyFqZbCHKT1RKcItdofl25LZNXA9LR1SG/JvVGczjvN1nXj9 ll09bfufp9Bn/CZhLMyiNL+uXRHyyhgXyooR52rnJWfqpgz0/yfwOZmjqBq2jWDzekN/uUOulf9g UvZEolbMPEGVadhhU9oM+qsM8tkL0959G3QlN2d1D9X7UN0O4D7RY0y5AxK9O8IKswZZlXFsKlv9 ZDAdlUs582nV+wqc7ZrJMhv1OenDlVrknATW/re3XHbiGD0v424lvHsojQ4/Ud+Q0DlYldOBGNGl r2YcYzn2QFqVFoYxHaA7NqIfEiN65KWX444gK9COsHf9p7uBswq/SK6/kMveQroGQK/OXYNNl3Sn FbrB//FlOnuPToxmgjtgo11fTVYzg3Jgi3HBT14u2hEwuvZCKMzHb984bix+inXED9xsHtE1fYJW kX0BHhyBSDpBLirOnt3dzSZ7W/MFeywXij+nr7M6uhFS8yffjrtpqVx6rSp0XX+FG7zXtFMoDH65 OStqVsR/emuREvBJ29gS2MCWWGWEThVz2dym1jRVWh4nm+8aEumUMlB6BUAMH4wRw8Qy1Czfx+No USBhZnYTBMdjkbZIPxeu+M7Xc0Xr+8EgxS32ihdXM28qXlSYaxADn7Op89/vhXYMkcVr2FJPY2Tr J7QN8E5ld6VyZEZHKgM2y7dCp11vOX6ikVWvwZltY80ZK3BN3s3e/x+yiPKTdt3NS69gIxjPwA+M q9rpzpBIAFrGSlMwPDNNmy9TiKlNkDhfN1XCt/9FxkhcvwzLdS7/7TUmJFiD9KY6dUZcEk2z2pth 0tFufW9KNFElMLPnOarHaqfLQmaZM0OvIpIIRKnQysQx0N2FsNkD/w0vG5JYcR2bmvi2L+ONf4L+ 5AwXnNHsHgk++bc/3pLwQ386cyunuW40jWo7ewXVHmZqTEqhOaIMAivQ2Hvw8HnrK56CfBasB27t oqqoRhklFf8JE3+ynmeH+u+4x8NQd5prZxcHobkYCP5mlGBSxrqeTr/ugwiY+Gz9QSoDYGoWak/T 0sp0l69nq4Dv+Kblac4j5n434QzzsseFaI17N5L93E38fV6bEzL7ZXPIK9+BYD9RnMXuxKeL/Ptp WgkRR/YKubKegygNUH8EHjXEu9PEmB7dpNkAk4QmXAyVtEOoYi8304M9mWBO9cqH2nXWAFXR53Hn ISypWwPevJ95ojhSiHYJPBGzNfbDas91KbmKz3PcDVvtsZvBNCqhpGGLuBIRltdkG+U+n/4L3ELf qbrmfOL7eVZsXHB49M46dgk34CrWfAxTUbu8NSDhjNCYCQtBfFPbtVYSqO82HQEiDjtYsxighNRU HcE9wT3o534/BqYKRhfQEQACJtmMbK15JeNn+KJrpuOTy0VHhIdvrKq5aBg7TfQvZdK/sLo7SCSQ y8qqDxn1Ug7lAz5RNwgPyB8zGe4y4ls7y/x2NF0LmsFRxZIqU519n6P9Iifm2p4LIFksEojYfLlT d9bD58NIgTd3UOHCEqziZ8pWbPRoQhnZ7+yKS3TGkkQkMNJpir7dxCJ6DP8O5G5QaMDV3TcYZwTo z/1HJtMpxcqOdVfQCWgT58x8VZdgB01WQvd4gjonycgwoJXzse7jHdXXawUD8GSoklP6EXkdv49I a3pvNFlTC+5IUKOdSHOpfNBNtxmIuSF3cpTzw9Wq6rBpSbf/wlvCF2no4ce1BkYLf1fzhNsHuOPT rnQzFDDbJiMXbdXpkRcOtmBoBiNtPPMh9e0liyGa6w/db6QMuCmvQrjRggngZO7mRqO62kgndnx/ VVEKSuiSts2vvP4VYixRLRMtaHa/70014my1C58KOpRW/V/eYSGXGvNDTvqfCs62d9DPms5HB1wJ wT7C/WVvLCfCq7eybH+mQ5l/iWmxUdYjDCRRD1ZYE5AHkczHtfa5Fye+NEC8QBguFEjvtcnb8569 QmIA+Q+dy5RDzJ4Vy2eWEOmjl/yGKEDzCRUl38ixaoVYG054nU6H2TlA6gl8D1p+u17mPZOUwZy9 sZlbX8u0gEqv5uQwcJ2jp+fDIfAFYGsUyz5/m6dYs/AcpgCy2/lsibafYdjMqmcYy/O1Fh//Uz2a S1dR3+fhEwJM229eRB2QEpnaLBj5yzKPnQk6FwCETCFac/zLegiXm9RTd8bMldb9XeiIAwM25BKz GGprooxcVwxhy3JvvQWuAfgulmaAKic8tY+Q1H+dDbc78FLEP9I1e1kYx5FYrt7mQifjATdnHTNK 9/3xVZelqBKcsyQM7521G3tpzwReeFoIpRQNsq4U5ik9G2gFeVVP7UFgeQ99p7DzXdI6VDyoQ9aY 85jLXPonGYkwwz50VOb/AIcL2q/oflcFwJHtn4k+ilpVNSEGUgI0MAF14egFVxslYGVWKR+O4Qxt CbKYu3H5Ap18Zb5syvmfuhntIK/y2uv/F5WwL6keW6C1LXRFEjn0/1ZISUbTEkliTlo5Pdrj2tdx 3zdT72+SQ8d8tzG0B5I0HHA41hY+ax68epzvR7peWgP9/hsPH7CO3S1oJqwQSu+F67lmc57VPxuz C+iZCXceD+gwkeGCSjVrs7SW8V9OK3VX4OvrJXVihQgS7/qO0fYeM9GHS9oM/3p9u/YgZS+/tGJq kh7DZnjSOko631xJSL/Fz9HFFG7k5EOJQpDRWHf4LKXt49u9/7q9UhZ5x5+8DfMlyZXq9POomauE krGnT51mZ2Ouj96Iiy1DUHOKbGZ0UNWsw+0uE+FrJJk0AqyU+nwUmouxAtBqkPfrsZ1gfxJwkZcj D9jhA8cG6+Nx5Iee9vGsKgpMzz3OR3xFV+Q/9XbzVl6rZSefvz4v6a9nWjbaKkCUUTkANFo8m1BU cR0wRvAQ76mKIshUQu2MM6y17TEc/bZO766ZLBcTFYCE3Rf/4DwXkMB/ikIE5AR7Kc0SzGAJQaWL 0o+avQpUyTTCQvU8RA7DzRCjoGF6KgfWT40UVmJ5nuKVd+xvN0w/CB83z2bN9btONxyKKl7eSW49 xKjqKoj1vvmbDOmKt9nJIfuFT7K+LsxJlKv/Vw9Jxjna+MzYAk0t0uP4Eb+jfxIwIWK3uhusqiph Vsi+Fwg0iL1xGFoalaMMrJBr38EilFdfIv3XdFKO5PebTLFSOGL8x2WNxesga/5WrAVfqa1Edf78 a2BMxzT8cfUfDd3bG7RdWBuMtkc3AnWb6dNHslG8UUXXJ4rFKeXL5CXEK9EkfCZ0YQ1eILJTf77P dOtMiwz1BExyfztRyQ8V87Xeh+/rxl2EbpjJH7WwcfQIzJPvwGo2ygPb6bo8TAQc3UnyYR/GJ2/h 6ugiy5w6RzRtjcUnKJ2o5hcZnnGejsT5/Eo6FMewTmvjGuvvv7eJ4BlPzQ+EebDpxwg05OuF4RbG HDQIbrZvsN0d7jL+UEYlxlDptlL4JGYyDhfDahaale0tjtoKGzysO6HCMbcf3MzcYhsiGm3pbGtE IjXjzA+BwG2G9g+ijVTlBZDGu5z27OlSBcSHctHUwbPceidDAfAXiULYHwBepLz+9flOZa5tXL+G JfpDwiCLUHKavZqRf8/2icwmEa4s3yYhAFeLcFAYCCLt8r1FRbwn5tDN7cn+zWyJgwCu5W/SelD2 aXIXlOEMkGO/9qaKUOi1ccXp5FsKbePzzki7hsTPaKAVQO6FA+XSCm/P9BUNN9Xm5QO/7l/wbkfP CFnASDZUkZpsBpaDxm2YDjnbAAgRykl7B+5f0HeHZmgBdsdR1k+1UFMsV5GN/Vy7Vcj5vnawlCLj lFv9yN8tCnD0CpiOhJp131HsdVeFPAvJBxXv9xEH9TpGussuko8ft+SqhKvi0Gi67hc/mUVPbOP9 jncIYI8eNePyo6DKu/VOytWmLm27g/bIYljYTEC58Ubniy1QaklCmoJ+ZC0BHUuZpNmu+/NaOaqv LzzQoZXo/8CcZMRxV7nO2U8RUflBOurGj/YI2YXEg7oXWwSVqNRvCvm9hddMJHd2E90v6p2Or3sE aa6J2Rm4lyt56qRBmpfalDSoW2D0ndKmC36+kjWAwZOVQShAAuRmVmsw4y3dkFs9FQfBXmZZ2dW/ lGcbam7Dl7AquXchgIQcjpoRG5k8CP5Qw9Evwuh3yiZGz2nCmvaPx4ZyOOsKL1tRKO5FB7P98vfZ jc6ZXCkuj4WcZdZN8IKy1+bE7Iuc/FD01SQcCNV2ocnxFr9oC/J9A9hZTDYs2bUZYpC+wYRUrO1C 4nKEwvfqdEWc8Ms9MO6fybVTWZBUCtgPvNTtM7FKuADapdXtTSGyxvxFoMhrD0LgRwFWaLS5mcPb z+1Gj8Q4cO2av0coKWq+Rx8V1a9ScjXHH0TMYd8CZODH24n3J/nYRwxDDA/GSOWiRjHu6kfoQEnU 04+AGtSn/aedbeKq3Qj2l1UoyItL0jZO86Ujwu+ihyHWuQ2Cs/LYo1DBRB+fnZHM4i0Lh+k95EVe xEJorR1YNKuwhe71XrPpnDmZOUMpYD2PDYnJ+RZb3YmUe3Mx9dy4htQ5iSM3e9q9KqxCuRuptoz7 Tvt049JO73mzHBYnBMejTtxYQS17ogwflIzELSLT72icTbeXvfU1HN2iCCXah/jQQgwHFguyY44i 4PK9SjcK4Qj0LbFhdMQMXoPb9JWnFYhxJMYYasrYqs+XoQoSJYtGe+iSErQPEdKC8ltH4lv8Dpbl jRAt98pIGgCdCDoUGus/8+/NVNm6FOT3exGjKnN47bgLinrBO0Uk52Jahz2n2ySgUfdsJ2HbIdNs AA2LKQgI2xEqEJ5t9F7crXllDdQfyGxWkm1z8sPVW/r4TXt4mdkumdwupILT8P0cSfNLDd/bb8Yq 7I1W93sVLLeNzAFo1T7bTdKqD4RvHa19ae6cAb+2vYZyJdFtVQMp1Xn2U19pSjS/TqvEAgDM6Crw BzyyKGEpGONgqpiQL2tS0avC9oh9ojfDqe2zvDbJ64+uQQ0hKwDaItPcAeyxtf42U0ZylCbiWRNV hJZn6GT2VY24oFl6wYBsr3ksppGJD1EtMIu0hS6VGMgaLoc4Br9UE+qeNqjGdY9RnhAFiO8AKhOb 84ZsTP8vHWr71B//D9wbkRpyfE4Nmyil+SuKKsgfnY+zzf6Rg/TxGthpPwdeEyu8OMXj7X9LC8d5 jdxgWfetpHSsGaEiGuR+yhG7vIKhe5Bb2oz9VIk8tRpiug2fhtxPb9PQ3+XHShZ7aYBLINEjoAo6 OwGMBI+jcqHywN2lEhV/d5ZLHcFJO45chlhAXHLtv6IrLt9XAndJuiyDotFAoffUwf8J5F3kFcnA AFCT+UWxQH2x5U7603XklFwgKGUZFFLsHQM8RZIWzQHkBps7uADSzs1ovxGjRlUQepxkMvpv9svn o4beIU60guXKMTPUf9D84Y5cDP6apIh9s6jFNby9resrqPkhA8hpXHmNAmaoS3XHNwpvoSY2B7gj RaJSrqcKS1Cagy4hkn0jcMu+TXU4Pv6ho+Wk60NW+8SF/qENOvDuplmf3evqin06N5Betswqv980 WqyDKFSFUaCbRxkl3By3VSXz1cBPzZN1K3L5sjc/9xTvNkPC8LZZWQWYT3G702qGCcIQO0kT//tj 4bRopwV+899vXM3wI8vwvk7sqKAIZfVb74l+akSJkJoxOg8lkNbF8DYNjKFpwSrV7fxMP2+gwqhU N8QK72JJYC2fG696VbWO95mX/mtXv0j7MeuiIorIfNdUWBYkm9NfOenbtx73cQ6Ls/NK3ORXBqTe K6yljb2n3VN+24PZjDCw6bgdjcDkqKlRrQwxsmtegTS/eY7lJE/Y3JMtk5IIbTHgHidCPpbpajXR Vkh3o8tvr5ZsaQuJoAFlmP85+K12UxMegTNkUlezKAiQdEhui7bIyJ8QiG0O11nGAzkXhSpN0GoM guFfgAlItVhVxavZx1bunmjWXvP4L7weZdEomvH53Vg0Elmcag0BbCs3z4kM9egbCPNgp2hmWOnh 5lau0gDe3KmdBSbaJ+ov9RvxnzfsmGTgPMkr3vHj/AZoZIwMREGwDOkOxmhqUks28vj5yFIeIgMs BV2RL3CSpF0gB5PUc333TNT0BxS5bioWHxpV8sy/WjJbob8cTbQniN2EfVbuIDFSX8hxLxqN1z4h c0T8X7KPD+BcatI4gU8q367CO9Bv9YcLEFkRQ83nlKGBaVRsxQhsDLQQqYiyuoxA/Diy+JCRXWaI Nz8y2PD5dKkvVZNVKFr/XDxDVmk6C46u2DxZ0ezUr7jZGiZqB1jvlVVWv0pLInMh0OqSxuG2e6bI m96Rbw+1mMmav3tOJWthxZcsmJjeYEcIRyfCydO8XoVS6K23qFVCU71j9f9VSHmi3+zqIfXaTG8a NLVc07FZRE4wDVCsHKuWGRXHscgO/+yTA32R4K333H9q8DcH2zdZTBSfq6WTmY3jmwZvd1NfzFRI /CAEPthv0Q7kQEPUj79ODMKswNSsz09io/+t0cTIrjVZE++vhi+7yXyNiwO9B7dJakHSRDFGo9IA xmeJtCP10piMuxq3OT8S3doHcSLGHVibfxuMdTOZZcu50Hp2mjB93hzUh8teVRww3lIySBOQlYKV KLqaGOE7D4z1U7y0RW4hW+POfBb9cE7ryzEtdWrrXm55b7OnET1wk74/cnwZQ3wzn5EpHLcMYARv 92F5+nNXJoqDA0w5JtRISnnlXX50A/OKcigYqyA2CmaIAsFmbYyZY/drdK9uMn8pSFXm0suFat2b hfPZMRg46YmYgaz2uzhWbITiZ6EP/Q+30TuvzcS4QiEFGnZNSaZ4+QvbOxC24TkQgEZRZhNKRKcX qEy/bHa9YkPdMqmo7u3kkLKnM6cD0CGezPbodQ3rodSE6W7K/b2/TgyR3CV8LlEQ2kThlmXRH62w ItpOtOZpZlMWGIuM4QOCAVkBwUZ4fEiAW3U5WZh4W8MOhVe9UNAjN86yScBjEU5rYrZ2twNUVMpV XKtKgRkWMVY4c6CTDRCfGyzl7n4MPkpKWtKsIaYCsU8evh910fZOFWr7Zl7fG3ZO/3vir5K4kI3J OOfed+xB5chZG8teVGcfCfauiYjpgetxidqPdEkHWt8hvKWT6lcm5wuoApn01LmC0HRMnietkmd6 2o4OJHyDk7VEU1gVLlksMaj+aNPJItOfsa5SqB15zFrmL7UQIbGxEkocnLqh57bZEKraC+r6wG89 DIpmrsBBBymMN4g6Nf6NFGYn8QNv38eIrEA8IvQhAKx9CxELshODkPt5YQNWlQKwz81ARriJa8Xe DDXJOZ6tRATjT7n3s9HrUVU3kPiPAwEikwm1kEroiEHVVUnPqgqswYwxVes0N5oJnKRT/BoQAQbN 2hSJfyHoBOT/9NGmZCcgElx/zevfWJ9UeBfA+y6cxrZUh6NYX/k3vdUc5XAh+2xEPzfRTHgdfLfG /1ndaZhx1YNXRhQ32SROO+kSYgw00nOvMBTs9SJluEQHSgogMaBjVfi7ee0A1DNhfEVorVqhp0ny LbibL2jaTX1EIXBUP+z6Qw3Ns41orl+urpdMBlKOLm8iLtol8IDlgY3FSaPvY92I/q6lSlUDcsGf qL3IBT+AUSytjMT02eGMECS5gMlsRnMVQqhkaFXSg7257mIwIjVOc9gpJtVBvLNMzP8RSu1NSgeH 7RhyvSWmr4HG7akCjMVhGjKq+AaRrWoUXMdNdUNdaU3R4/i/vL73nB1XlFRLxo6YUXeas/9UqMHX nRh5h7azUzU3S98dyFeGcSNAk3AvIbxqxkmKQrTMU415sUkEc9eXjBLiBZFiPjhLkewWHbWNpsuw 0O8k63SRx6VK8IwYddBKZG7ES+aY4mxWegXo/P7cZMi6ajA0+YZSUFPXde2l2UG3m+pTXuInLC8J 1t8RrAIdjTo+JW4WDIORAbs3+OehvXXcKdfNWeQ80cze9wug7Yphs/oLx4XFmUwqWLwDP3W/xsUM pLSE0a/2p1FVsCjzRXm+ylzv2WJ2WMmD8fdF/cLOS2q4TsoDK7z0/LVC+mVujz902AqUsO760g5P C2fydtnSs2wQ4qliWWUdPqQYdyl8/pXjyKxB7OK8TxYtxosBUdPJkuZqbO3hYuICcRUS38eiEIng 9WPy84YQRSgTJvXsQSQpE2dPjc8aMFFPh9v0CQEhAy5wqaQyXQu2rPqpTacepM2l/uEe497Ub4CN 311dH0zanvyHpsi3jXFH09IH60cmVtHhPqJ/uM9rvgqNmd5ZvpoYJD8cAffPv7j0t9XILDWwoLOI Q46BVLXF37OiGWzJLLwwzyhlTqVxSS6DqYqBOppwb9RRpgSsFBSZhqfwWOw//xmJ1XeLBOdYMUiF gp9+w6sQbHSnjd+Xh9Ned8e2T8MoKGik5fTSAaGnEEfmNFTJaA654q+t8vhk5MtcRNAoHpIXAEXA mH0ZDp2cAxiUNznABxd7oM/OY0Rw8km6348LmE77MVzBv72BELQNIcg+58OpylUujEBSmz1CtOd/ ydjTQCWhCNYnfWCr2X4gvcIfdr7gJOOuiOw4eGsik8ftJWCpA2w8eIaeSvMdcsNI8RgRkV+MBAu4 pcqEweaELbbBn6XcrWcQec+9lbQwbmTb1Ixnn5jE8nMOtSzUrY9r5pC6+pAO7464uV+S0xonc5oK eDulb80FprDoQitAKDlVi1dUuEXZicIDbsh2IWMuiqOYbru42Kh1WERm7s2qgVzc6NrhVWIqO9ST c2TBS8oWsNk+kxZ/oi8MGM0SdRWmRY0f9+Tzd+ea6zlzHdeQ6Pi72Qegelxw6fn6dm2q99WVTxG6 OxxJcMBPx+8zAQk5PlOFT7WUPIl2cd0xwGqkQQ9dV5gh3cK89ja3WROWqpZ4U4NsEfmkQJ0Xhw1K 9pblo36b6UTu7V4l3XaSctjeozupxfQulpEtNHl78zeFWU0QDyJBzZUMAwzCUIHEjSxa4ZftD8fM /hFlNWRfbZA24Q3qamYTS4H0LEbYlOu6Uic1ZXJEbA9c1qPG8QdaKaRZCAU2g1YmWt3JKuGGtjhH zjeYFR/iYS9su3i79YagFI4TSihPHNgQJONNeWaBapHKhfb3d83pP6RpVE1k9gzu5wkxZfIqi0sy H4TWRFTCOXz9QFPi1TrrZws7A/FKhR5b6aczS2E5rbKd4uhorGhlhb0SkfgQXmUr61P1AblqfLp7 xK5ih/hZG72LTy45W4e8v6L4RaxKg7ykVAIAZ6d5cIrvJThhjyiM0QmA2bB2ONgM/GOnqlGVSpO0 JEOQIVP3m3w+N6avBDr7yvQ6Mrz1ZaZm8yy1VvnyOwOKftk+3OwlaW8ORhxvsO3ciwUAMT3bspgt Dk7/IBH3PrnC3MdHWLFScEMfG/XLEip3B0Jg4PQJvSAOXRQdiK3bogbRaL2b22rBhHNcdY14k1wo n7MyD3PL0b7pIddkAzYTUGkyXOIclFFtLasYyxcx4DX6rp3lsbOhO7gQ+fwFTnhNRncSIP/VOzqC uorwU6rmOfEs4iGOdpNS1wLAZgIgcROvmEjeMPc2CqzVviVDcrIjMUf44iegNNj+nVlDRxmInOU1 aR1K22UKz3DSr+BngJRlXfyR+BHTcOI4EEhfuOEKt+e1/RKg7heKxnamOmcRT5Jy3t4O5vzmug2h IqHjjiC1L+gPRgWguCMk7/A4EXv8i0uvP3xkLDgqYfhY5N2bYBsSgVSwK4eeqswkTLRR7L78Z2nH G/UPumcSy5HjbPESHq0w4bEP+wVDPuMNpbG7DtU9SSQlkLK8IDvpdevSkM6IkknCZmfra1uHiGI7 26ssk0I+Fdc4LGWCCzc0zGLQHaR/1V5PfYPmsrmx8M2jV6l7gZ01eYC0vMTNo3aJiG8GMjJgydwp YSCpm9XwI5rYBvIi0K6tLZjhiBdoOK99Hus2BwdnCWW1rUJHI7D8yyKbSIvZukRUr9PStvebUa/u emoeZkk2sqQK+kGR5jR5LZH7jLnlVrXRipfmrL7x9R36ErrfJNpDSTEpM/0/vJx9cxkh3VBMY+TN VvliwigDB90PkKL8Foh+28XGKnu3PcoCzdWcsHpZe3Id4uW5ahYFX1rOJ6pCfMLaUvGm4tv4BROr iBzMu/EvAMsPsSakyI5iTIfooe9bmFkGVDofYpJGyO36Xmug1DJD2dMLLcDzMCkdGMHQfr5kL7qC QBaYWTJ8X6IcQ1Dsg/pjSmgX7tsGKewQcHHJ8d7GhfO0pJ3bOyIuWdM12XSD+YXeV0cHR00hnxbk YSUJcy0GITErDvTztiHt1MXDoMDWL1x8AWrGq09BufDEuPJXTzPw9RJ8UEwrs87SRuS8oWfVm/2i wWihTVLiEIt4FF3smx4lJe131Phk3F56KL0liZgG2mxQoOLI41LWXg0ndWhzrhJDVY/n9k/yjsM+ UDxpa2+n4fA524lbFoUmvDgoTXb9fLeKyAW+4y9jARfDp6/095kVZpEn2qiem4h1bxf4d3P0JQNj BnQLxoOWet1OL+3b+nF2fHEesscu0GLOTixP3d3rdvRytqOtexAoS5zgV+7mOswHgpm4mPAntbV8 O1hrKAfRJX09uUvnUvNsv19syBuZ2AAzDf5g6BXGC+5fGf6EjOhx2gXILbj0g/xrGlxOP5U//nmq 41DEjSaAO6N6NZmv6AA0Ql8KLwuC2dH32Zf/cKIk4sRopu+i+7BEbU1xTYnZhDDFfFH6miqKkb2O y/DM2hoAwWCzIp+6I4JIbXc4hyw216IJdJsERS84ggGEF00FFDKNtylgk29Nyo9hQ0u4gjCcCnSf 0Ukc0HMAieGDM0F55RLwGX3k/JqtD3RHulYPLPE0vCLHaeNKb4YhofgrArLBER7siysStrizY9lW E7EGUq5X95aFan/2w1nOgEUPZJV8oW15/zhvHuXisn7B6YxJAfFfWTGP+avSO1MuJ0OdWYs1G8vs oizxz++VIL+tt58L/QeYuE/30MWJMMTYT7pwaIrILN5FOhjXJDF5CdsGxFjJXI3WrKNQKXwxdRqu JXygbieM4E52llab/dF8XIS/Hl3NUGZa2FsjU35GZmN2MsM1F/yEkvDW/c62/j8ZVX5Xh2ptpfjf 1xfBq6f99LXbspKp+zEU1tNLS7HKF1F7+5T8HoTuReFLtrRRzELu88XfJo6p7dBiN+aju7DwbCW9 9VlJQls0mVC2DK+Un2MTmKs7fKnuDbw6Cf4M/3ZUXpScOrKJ199IhLOxgrajoUJdCbLicAXQ4FGt xeHmrVNtuvFZaJLiATz0YbXiBUw0i70DyIEVKMVS8LQ3TBZ3+UA3BO6vsqSF9Q0sWjD4vHDggwok 1JQi4ksSvvatrUjASfz067uRP1sS6LynDDZpwOUIpxqzpAvy/asGAMzXiM0aTHNWlPucRGOwULDq cgojMIbYONEXKhmYyW3/gFAjevv7EkTm1nNSzMAH22BQcbWO3zpX5T9KOJuBPQwwO0soamh6D63v 0ATlUUZHpRmD8cf+XDC/HjQcMMsU6PqgWSKYjiE4opWdBXf5fUfUkdK4L/pDd3m6Js7CpyM6eRws zrnk0DPpAwVbLCq3gCBSPtme0YfEmo6MMRWjm8ohMiFJt2QcQYLZ6c08xWGeMf7MT4WO7Y4LzWSx xzipo1EnrVcNb54NNLuUQSGnEHm5hS0++RfkltcJhuyhF9MAyy2ojfnKcV24t2biq3rB+ZKzLz4c Hy5GK/ApA4Rn8lkEfRMRod08L7Sk2szngRHRnEL9GECtehKjxtaVHj++XuGGze2ScHTbcANNZRT6 WAlx8LvzEUozj3xPgledfb9a7/IlUX+L+KMf/gKuAeGQ7md12lUTtdAKAqgG6JIHytuqKm/ug6RZ sPtyA6JSZXCzLNVQON8mzkfncqSltwrXrkNWSicirH+eRfZdLPWi34TFqQzgAqg3ZT/eLazy3dz5 YPF6VNJN7Qn28Ha0datjeyuWfFwtWLLaeb5tyqfRuiAkOZApI6jTZdx6g00CvSz6+PqbmZhRErQu PCqT+ZhLvuNPVQB1b/7SBcZrERNum4+FPHsw3f4LzzIa9eZzIakIx6PcyxPORMTJht4Gf4SOqjZF +ejoCGPzoDtWQOamrYKVTUxuFkL78i9z1dcCjMIxOgHDvrIVXyjprMzxtEBoDbYyY7E3WjOsGv02 l80GGHaXbeggfO7JMj0lv2yFXuLV6noLXhMMkZjwFAtprD38Nlp3Eun/+IpCq2ljDdzBjxjASaSc Cq8kZJfpqdtIm4gh8Scpsg/I/ObnZ5EZzla/05UPj9OVKmhPtVWU2l2ccAm/dALXMeMhONaZ1uxm 80lMRG1w9jelo09Or1bz9RhH1w9JvNRu+LYYI7WeyPB6hwkgv0cmxNuatUR40ATyknDOPOFKlvCx 6yLl58Pem2Pk40ygiAr5Y3WhNypp0Xxwob9/B+ONYhW765rzqgVtH/TaL/CeRMNldr8zrkamfPR3 0/z95hHt0yVguMfoSitMhqsDI454xeBgYauJWi9LIVdPtCE3e16bcEZfWSUk54ObWoqMHT/O5326 GbiLKjMGxSX0POBCSOy8Qu4YTQXdG7FOiHxPjVMXq4m5EmW/Xtugs0vku3EwdgvIZ7ZOzS5ZvNQ5 EJ5ClsAYNpEujgABqL9DjmTEuOM8mRAdlDlks1uqNauK2PyKjlqSmg2vLXgSAVFJG5AwR42osJDs kAmdHm5JW9MRQUhSIMl7nx8ixcSBVy8PdKSI6ZyZMOcPKJw49cFUvFO+60/dXhgKi6e+5iGC398s pZx8920F8Z++K1qNaVTHgDiyzWqYvIYl4N7JMS8UFlTHAtuQ3tIngjcKvS9OYWIn8LZqjyWClDCD cvgGd0KEK+J6+qguEDgFnqQmTnIpNC/ZMMS8l+XhXlg2ZTmBi3udDFLw8NWZWZw4L5x+uHOx3rT2 2MCcdFjsMedZXSl2ExmY0GGAkcZ5jONSeu6jz3v2uOo+G77fTcfhhr5ugYqE6lf5gc55QEBFsL1O JtO4VshZfCwuBNTiTv5COSwy08eP2l6FeBqsP5Y7xwZNuuCSnSZs0c+4CkeLMDTWpm5lQe3ZdWIn iIfcA3JdH/wogUuC+p4l802CtmbQDqJef0/i3gpnijdUMMCAsHdzI6YhqK9Bc1eWMsVYEjRjBF3A WqPSzfiWeLgxYAbS2/OxWuAaOcYD5pnWrjtR2YrMIF2RDrgub/sL/Y6PNGWMgfYEjm+IxdSnKozb qTG/Algl9pZ8MbRq2YN/+mcXMGmEAJkKS9TlNo6LJt6zbAtfwU9sjZ+pZuCmZQD33pM35NRXqePl U1CK6C6RjhinZ0lnWyj3nGguMIGEv8WbPNCRW5Zk4zDd7gq/Q3nhX8xvh2stS0x0BdKDSo80z/vL dE/GENAGfFHYS+wi8sRI1r4lhu+tP+5LQ76YSAsGvWdMZPWUWK3ZhkfvPN7Y/ETTT41Xjo0hBbNV wYTglTY6gy0M7oZnvlbRp10IRuan2TuOZ8tG6v7n1Rr/LPs8v9Ti8PqYgnPpmoY3KX+hU55hFre/ yqNV+TLDVz++U6npUc1JA5iVHinDbf6Dq+06B5uzR+cSSFGcMtGSl6E3C2QL7Soanvy2gJvQF9jq WwcPnBtvPnQlTQ5DW/0gWT8jJD0krrgFWVu9JDUqbVE41uCERXDo8BEaWfuEraMOenR0sK34glx+ OPelahSnclEGtChpXGPcf6ildJvz+87erC60pA+dzQ5vM77OhJ73M12t0/gvHNJ5mB/n7QPhHCND OaLKQSIGBQGWAUzImNsrh4gaSUCNnKjKoQSoY2CWyKN+kh0B+6NEn/hBDR00v6lDwgZgT4l+hpCi MdP6Krr9L2qlwxR9FR9eylXQjZ+DSF2ADAmXinG+s2TWJ/jyBtoh2nS/WaTxOMiyL6+m/KlNAK0g DzbZeZnMXJr8prrRnwXT4G0KKMY3AiKQ8v8GZ9EXRyLF43DCNMBVswAz/w7DQNLP5ZO/HvYS//zH KVimQiAHrqeygpTYVkjSfpXi2u9QIaYRvd6K2UcFjtjnl8iuRm5ggaC3JhAsHB/MLyir4IqIqy8u e7zA15YFN/uUGVde1AwPN4rKWtqYMnuKH72G6q8L6fu17xP/+IkG/bNImLsmBbAFPnDduDxtWOcx rQKEhMjxoiMUhc5vnD9c8lQM+j448uoil00CUVAGC97D/O9MjsXBJt8C9G6zW4HgZ6py57wPcQYO +l6wKC/2Eca+0cUaVdRH7EQKTstA7ieQ4j9B3W5ppilYaTvY4OqY2cPi0VIdT5yDnZJRMcUQSG74 g4yrnvyLTHV0U+J70zUVrXh0blrPHcy5D/1yl0gRzI8ut99Vlx2TPT1AgplXA1y5dODy7AzWy78J eVv7D2IAa2rg0Tu3Uh2JrKuOeTz7glxrGtrm3Z42dhcfXRgoIOWm+w+0JjypHtz0HOw3UEJUTKeJ TOesKehKx6YD+KLphbShgT6ZKPs12T5DD4++ann10StUEPKWHfJWU97f6JK9+G5iM9aiJoCMpud9 SBq/mLqkrGwKtSCMu3uix1IecRxbe5TP6dv80g6Kq+Ys9mJ247tcctKsrfNqRELmjzxynXWvrJyR QqYDXOjWpb9o+o0CmROKUGU5+as4Ptf1J34oYcvjfrbZtgMz9vJRI+EDNP/kFILNkBq9zRDONr2k xmRBWfIQhja29JRunzzHh2hUnTX45t4znvkDb/jHuoZKbnZCImXpb3qrEkWPEOUFlFaWR7wYMXoQ QA95+/9gYdi/Y5+pCm4tIiSxYkNJ5FisFRd33Ik6waKGZV5qtgT106iDEY68on9iLDrzESVGfGrS wadKTq1MxH0dOcQO1guj/eVC02s3/CSn54tfNQzhNI8Jqfw58EL1s0MhAcmkkE1R5spzxYUa0N+a rCwmA/SNa8ORFWCQZA827AfRxsoqkCtwS3bIgrQtB1C2L2iNlHOArF8EvSq+1nMj1doYzlVWmKOU pS8Z97kQRNuUEeLzVndKQibJ4ifQmWXWD90lTRi8WJBcog+Decs818A+EiaIeWB/FFoVjt1znmbM V7uNQhaitWlJJPs3MC3pj75gBeVQP8TyK3ieprzU8NQLkZbR4u+ZYiPcY3mNl6Oku2MotImOt5uA GbBi5OZazIGCk9xRhyAC5uLMi61urUIPQVkozvew7pBSKAnOjEWnnJcdmOJYLlOOKH1cU7OGyrOK rgLoNaoHwaq/E+6rn8H8JCaHX199QH+A/KQM4ROaj2XvU0Wc/Dlt7eejvkv1oDiGgu6yCegL09EL wVYjEnbqQITNODHAomwT3k0dUE44vfWXjkjV4GyROCtOExJVprYjVkHOVirxnJOytZXgcpv3U+43 VOWO8MxWUXRq910mCuvmS5AWLNX+3SbANIPrGJEjxQoPCVh0lJkv/dvKaCtdWotRjF8/Ye8Av5r8 zMKMFMRX+osN3Y2igN2dzevY4SjDm80yjhpQ5ZLhIvGyQSuU/KikrzTlsetfQi0kMROGxDJJ5imH 5DatVAXaOriiakREIixahS4KrC0vCdLBqgJZZouTmyQ8ouq1BMsEvRkSeM0gqq7iKapgvrz99U3U S87I+WZaEOkvtUAu4TIxMTpXmkzozJNZJy6z/Vc8UCKJQZ73y8ta+7pTs+AoiwlfDPUvYWm9/72+ 1tmcWDO8AF+O06BJtf/EBAsFjyvU/oG602snegVmAzaMpvGdU31glMqb73GbTjldqWgqZ+Pb+pg7 HA7lcA5XKydPE1+LOOdOKcbgZE5OGnbZRqHazctX2zZh0odiZnlluolns5qVT/R0AxKpZ2yc5eXo NK1DgAi2dj54kPjDGP83+V2K6lfvZrA+ppYiqv+w3g2hahDtKa7Ei3NN5XZh2+7UqEcFIK2o0qS8 8p8T76xM9wUV06qNCfTxoJlcha8zGmHbtJYVU5RUGsN/HK/yra9aq4xZjavod3BqTfF4g9qT+BNd BQPja9GfjP4dPJ1lcm5LKXo91xdY/iva5QSIeFX84kZ8u7q2C8pkM3cGrGHYRlkx1wlMFqysDw6S n18lsDdy2PvVjaGmGXI0RPjH5Cko6o5wFOJkCHTZdxsKTEFHVnRBXegs/zNeIf2Hh3SDbOXi0zmW AArzBdhzBb0YiA5XLVT8gx2RwPMbs2cvq6J5M6QKsOmxKLlHqlNQ8GXCwTqdsAAwWq+5baHvUI7q XkpWv3ihIQo28YM7n3jwxEUvZ6oMoPmyHIEc8pr9FuTV8iavnEhD7fWf6z/BVlwRCwFpOSulZcjD KEJu2TF3ukHNKl67AUzXIRdQ6gjcVGde36atnjvj3alGZRxQn+zPwVqlyPvBlqx9QWbVl7aKgLq8 iAs+kN64MCfkYMwWi9adL19E82dMiIE7UVjBu9M5pWnSM72/ZTDAnxDnWvae2JDWbMzwEXBszG4d IITUA1HdG+7sHIhf4ZUNc8I9bkQio+tofUkpldSAlU/CJ80flzRi7fxR+cI6rb/wFCSrRdNaPFZC gFQzBT09azqs4t5nwbvvWFbIg3eFQzwUM2ZFS2KppNtJDBZup8GRhGzXUfimwky0ZegTu04jQdxg oYwpJSoXyD/5oVD6ywm263i977xlBTgGXCvQxzpou1IdL2k9kSLbY+YFs2Z3TX3KOKEcTm9j9Pdv 2KpMxOd2y0IWXGi497glx2qIG1Crhx4xZSVoCzKgtrez3saL0ab+I8ZGKX6Q5t11mwwsGA0vAte1 ln09LWYrP0IeIKTPPSzyOwpVxZvo0LS9WDJ4tP35K4zq28xLgYzka6cQ41e5CRxfvF1J1cZr6LBf E/IRzmCslV7Zm04XCerorqfzflxOSCHZVziXnIhd+W/VQ36xQlFiteKqAke1NAMgioFaMpA+M0wJ Nh4CHZnMTQ/1U+Vpvhp6zjUXCTkbw7DI8I0jmx4/0HDC7/jIO0k+k6pN8Kvoag7ddkZ6L+rvOExM mHVSI/vHQfsdWFewityRHEC8hJvdp0Pa6aop3gWxceqPDK5JHfuEBqbJl0KL0hWPHfXOe0s4FZ1e Me5iTEkfHPNpdXgthaXYkcgiMpbqIsg1zMI/H2s7LHRDcaqmZMsUSa3rtxnvcenZxwBMdH0XzF/y RJLUgICJGO56TnV1wPArkLfBIlRPC/wNMD3qzMOFzK8MQUE0JC3icQo7bS+nywfMpRGyD5noZTNn X25bdOlX5VABlKK6+02gug+2gewcemM/G+q45Ns/zJbCxVGWAvjZ7jNXIFfeXtHawRkbofma1O5m X0gq5MZZ0GGbqMp0OPfbxZw2P22fg5VjDdmVNUMBhtGVxSLtL+GzerhmlgMuSsCBg/N4LXgvENEa NSU4K92XHCXZ5inCt5AQtpebnom+3S7+EvKl+V2XB1VemkB2ONbGShOpHjpfxz5v72qFJGm5Izs2 /+dSYKdSbyiGdTFmaiExOdkFBAuuG4O6AB9c9WYKL0dvjUr4g3v9BgdDWMt/3p51NlvZC1DwyQq4 M/Pcx1Qx9sWXOouu/0lCh5BVypV/dMNytDOzj4/ICoG1HpqW4rrODhUA22c6zdeG2s/CW8y+GKNR De4UdCihTafO8wpIpGfyqlHv9G8tmkLd+0kzjleVpdl89tEQnxt1V2H3WIlPwg89AUj6sU/AbZU4 +KyX8f0sEOf2QZszkxSCJIl8LJHjGvbolNEModAvAhpMloslIoTdWc9XHzlRdXND1UMbIarT/v7L lR27wiEPmJuzFrwIgdm2aEGNyt+GQdzoYBbbQEtbe5XCrd+MnUpGRScUNoTTrXayg1EKJ+szsB1a 5hpyd/zqnqy3HU/MIov91OY3ysbIIQtFBYOaW3ljZn3/3XXLASly0iO10HMQxnkRkshlckWYDKoo qEPZitNmCo43/Zgzl4XMkgfL5u+OZcjBRvbvR3AnqER8ltT5NJyMTlIR49xw0c0RM+2Rij0qBwpD 77Z+BeTqiaq4hKs5cDBapCISkeLvT1O3MQPMe1V1KODSzQHXPfuBUU0dyDU2U5Cgzba/v7+qNHm7 NAP6P8MUhWBw1fT8+9n+YBlbKqr04b+QqEuOnyOGcy6q1r+fKLRsJAr5QdeDLqdzrg3AcF/d76HZ wnRTUhOVVvSMjn2cGx7KIZ2ipPO3AvuDkWdXbitdq/BzQLR4jY3ClgbH07hB9AGUpO8wHb/tYm0Q Q/frC8O5XUBvDIjVRKVgZuenQG6o5OUGK8ICYnW8WWZ8zMy0tT1uK/A1nTpjpOX7QO2Q7BmBEpXl Bq4owTHunn/s4R4g0i8FznRkckYgEHO2aK8mJ9ZHobms1Js8XDcOjfLd4KoJFpbRnVRm0xDyJoXg +xVbLakkcIacBYda3S7LzSanz9xkry5sQU4wyFPDbYwdJlHEL0OqfM0Dfe4S7L4p+pKnkocnR6FU KR/vqnEZkA9koiE0/kqpBJqNbM98mjvnexhXeVvUkK8bJAtl/3xzwqoV4vtJwmRvs9hw2Do/rNVY b8l+FRgjAo4SUmhYH+QKFfZvVf1fJSphwqo7RVDBiYks7MA/TVKL0414jsSfDlhqtUBenWW+Opo8 VShe1ntJEHfb/PG0mWE/2MlLKpn43o7pItb1ZbCYy15HjVIFoKxX9/C3Ehmxrl/Vf/kc2LxMZzOK MPTJ1AfvWfXnWv5J5eOHsAZ/yP+XjSbRq17413ye2LbU7nYdXVzhqNNoaOROGMy4iGYNJSQXpckA fuuU6NdF1dthPcM7WP28JhltvUW1GS9aFRvZHmz0zZi8HO3uSarIpk4YYrYA/WMRrG1qGJhNxfSe sEDZ3eiczKYiJ+PCxAdhd9hbMTfWypd11PsHMHtMttUBD1buTcX59EFhMCBan27PtZA0lQLiwWac GXHH3SgCZZSPVtVTWouIzyDR2l5PYUHNWcsr9vAzDkh1PGWJhgEtVhyWlyeArYDwHOmE6evnBna4 X7wIfC1I7WWUmb2gE28KKsnDPQv9SN+L2+OhqVT4p3Ej9tlvrHT1BN2w7ujcVC+kJ9WSkVN5p5E/ MvTzg8uGQe0L0n6ul8k6OwzZnCRMXI9mNYc3DFMIR4fzyzVUJ0qxrEMoOW8iFT26J6L/Jx5WjFJf R5khRzz2gGtIJ3IlFPt3wNob4eEooyEUeEIvvNrUZYT6HTrERR9uSNWNcGgr3/nQyoSnGQEt14yl FmH1IJon7v7ebJMQeeYE6WgKiSFVOAkeyGHa9pKyf7P3Xqs1VoMSPm7nzCKG9Za+79Q0422FDlq7 +T9DtWeh7GtHufh7DQpqb54tCAwfnZQfETKy+QwqIWtRxEyobVArlNePh5EmKGKf7rhpqD7uKbNV UiOF4xd64Gerw7Qh7AG5mxzW51EfFX1HDaK7xFplGr7SZkgHWU8r2E0OuNr4Y8ptBZCZxBDzmkEG hMj1D07P4+MJa2JRa3KjsbcJdYMnssYGjO2JDvq06Oojy5TFwhf3GngX1BqZricbQeYopt9yvPLK UI0OAGGQj/zXwDWQIHGAqucsNq5d6IB5A2r0VN8XDF9K4j9TxyeSMmfLMzche5QBuuIo3xsT208L 8yMz4pBZnIJdgOIm8rotZ/U4kfbYFlgfRFCUmOYTHBelx21f7TQBFRyYuVGrlO40e6zTnVMqSVhK RkqumkWkVeaUfEMQJx7lhbxPciKehB15TJPQt5cZ7u3iozAij9NkjSI1WPrvXLZ350HRl0uXGk22 Q69zt0eel8gDsTF0XntbVJHO6KgbJlu5LWggbFDrciNmeUFhZF0+hs+DJeW03kPKdlHcEoPtd4x+ M2sSs4K2HRMJ0z4THOSTAXyojUts2YJjBBg9+iiffu7K05z8DGGMNO2KvOdFORWeJZwh5Fd/XQvg lTX6lwHEOnLfDdvn0LDth7mPu9qw1hvc61JTS3L4F8qcDKXxF0+kFSj1Xn2V5U+oFNPa1+vsTdIN zEpZUqaaPLcGlypNB1JMUj/6mEYRCRDbCYqBozeRTRTVuIcgUlme3eUR1zRwaLLNcnOeMUMEbglg 6IT8yL3ZcAP0mQMv6xjVoY53PHAXds5TGkynqR+hKV5OF7dUzdJJeFMsFpuR/THCWJMQ/gO9kwP4 Ox2EOIAlMl5lHlqm87nsYFp9MQYVYtMdsEeNrOocDUEnaVItLi3eMGcySVlwPXCB2jkSdF5i/u4h LAAiKCWxriFZZnt+Z0w0MLSchHj5zVLhg/SnKcWfWWHhqoEqWQEkBSDoZ8ZVTmSz/bV55Aaw4zVk 4Fu2FejfLbZNzNBge1ifSLFtZRFeANS5L7COgaPhYFL3hzu7zw6khnDhYJ9caTpxLkEmmBAieogU aXGWB7sbdqcewXRdYUr7pCkdpo32+JrxaAbykz4BlUpuREWecQKAMoEYK4poz1g/+RIBTaQff8B4 zATF6MWsYVtELAY/w1HoxAdM2y/mijLCJTjmh4l1ysINmypbZ4wDexKFpk4ytT5PjZSu7diGgz2C MTFUvS3YoR1+vcu/XzmRCfkAcN9l2mcDG1TEDaa+Zto7M7kV+6o0D923LjKlexf/ajki/DpEPzEc r1ynvYK7NgnZ1j35mudRI3BybmKQQ5W1S3dEYCOWalqezwx4XrmHhrPEILFUYvTdOvgHiG3pQyJm nJPDw3fx0MbDm8EaSQB0wOwci7iWSCQICwOU+969BVljdjFihkVgmcnX3+ZL7jF410hYcQZdfzu4 5hslmdRlfvwjH7ZU1UN0IK44QaY+3uzsG7oSjq5Fy9y7Duv88sxlNdNfle/7zk0L5AQEyqcqeZue RdnJZjmXWk3BGktks8Zx9fO3E7m3llbhXt3ZxxBzAWlagxGl+PROfCtzLID2V6R7U7bAHdT8b+o3 GsWMxbGh54u479tvTVlzew73TatWPbo7249wK2VLJFrHGXRk4Tha0PGfEhXQUDS3+vOps9GL8EtZ fjGIpxH4JNxSX56ApvgGU0X4OrSHzID2kMHVrUy9i96kvLc0tCvOQ0CyhA0cyM5/GLhLpz6kpDZr Egl5C4Sw9whVJcV1+4y2xGmBd2aweroab2AgX07ZUsw3hMRa6J/LmlkesLxEQLh2eo2j5gkcZTHX V+nIfyniPvn6SsdXNlgR1aDAyUrYBSoGEG+gt0jwQ9Dlj0qoCLNNVPOn+qHUc//AynUCdUGHdqch Xb5WNhZYjFWPaHHxQI7mrPr/sagNynQpIOfnmGthpWT8+Qq21OJQGiedFO3r1mXLGTk9O/atiiIc cYnQZXkHOmArw4GS30yI5yXtUH9pqUjeZ/tC4nc3rXa5NoRl5aZmfGklHZzV98POzUIeX/ZQEiIK WpMhD1PlFVAYRQ5ckG+NmstQwmWOJiF94i8J69yH9RlqdMsZl/2v7YgIoxk5h5EZgCwa5WeJdPRD E1CZP5G43n8I6D5cuZnDlRt19GnKUIkG4+5Yv3QmEa8AGDyscwTWJySreibA/CjoIyFaYmclwA6v Al6NsxzxM1eCWoDclrsbZDWlns3RYuoFu1feJTCrP+gD8cTJ0Cjt38x2Ba5zx94OLyqP7bhO5APx 0TttDVtlNuDGDbKhJcNqCdFv52qJtq+mJ4bvzCyhqIGE/iRrMXvO6uOimqCFXq36idFTzmxDq+9v Q0oZwqeEVQHcwTSWOCd5pXGF814XEJUH/BZaIgGdP6kBnHjOkkKN9kKlRVoY8u7PGCwPwAdT2DSE 7PrbfwJzCwquW4AXRSLvdmL7QUMBb9mUS0EU/mq78QFH3RX4/howgNvrF9/CUwdQJwzBcj5yXfrQ 5YKVeMCLKOVeG0CGdS1D8/R8GCG/vgarIGX/Jx/ZskytQ8HHrCJgakCk+SoAFXdLJv6sFsjYpJ25 qXCNaOaMm/Xv8z2hGdC9fnGhb+tMY25ZBbjeDr+rXute2lSLaGPLjN5mte/rxypa0nlGmFA8Mq5w A9O+k4aKfd6wzDRU/gsOUlIMVwlU1gCvLSzwHY8rTET/weozE9knwDu+W2oFJkwWT+oUj+9f7CF0 LsftvzT8z4rBCBiAX2yS9ulnskm7+jtiWTrukab1LEByS/hYadC1sOJsGeZhJ2hiyOq20aEfvsUg fnKgtdQAn1jsyCTf16HCthOhQDQGj36jiXRwp74m7VnIwHJbrEl+fVNA7ysKWnlmkyQlT+xpZAze Mem4CTLPMNPhOg71Bv/NPgmjxE5p2XEnDgEcNdsPdOCYinbXj5y9gI/8I/b9WVxqfV6Ec9nUVCet qOaFFCUccZfmgdWciEncy61pCJcrPtZdxFDUk8fFKoFKAsMk/D3wNiiuL7reiNwTasiLwoh+GHYp 6kAg6YSB5S4vkXhUKnYMcdRfOWWsvCu5PVk7dSFzq4B1BuQIXZV4esX9BwvDWKZkkxBUZeC4X7gd 3DKEMskr/qLPPKdQs0fyTg7unHdRxoprDrHZV6Seu0anZKfRaE4gW336NcML0VFF+NOICmQLt1Je 9H/B79uXnZF1m58fofOkGwfpO/CoAAzu56YNqQSqLIOi7/j492/AjRm1o2qITH7ZgAubpExoPX7e r6E6ZO0sX+eZW5SvsMIot5TjNmRfSdQmMJiQQ9WR1dPX1hMFUT8NVeBxpF+FYL4bJbo49aDixurv MP2hNwZG2w0lcWLWTFfwIsGJJyEE/6GpPeSFpxMZg/MknD/pnunrLd3oWukBzlp+nj6gZkAfcU7l 8G9gLq0r5N8TzT6SNK23FKLfEEGhhbzp5UsUOEI48qhBJvpwFx0e1bX4DxgObA0kYQFMFnDYG7yu Ks5KFGMqLe6QUPs6gGO2j77X8CV/KVs3RI9Zlv7f+ivyX4b5G86hirX/uAchsDW1qL90aWInOnwY vinEwxoE2MdKuZr/qK2cOvh2stI0N9jt4Tix6s0kT9ytsDg55QvhqQVlgpCKucBqTat0Zq0jCCiV +Z9AcuB5tPLVn6EiJ7NZHLuiCVALunzdzQPMLdxoBUQahHWGC4h7X/CqlLkcPRnNNqyg9VdFj/6z 1kdLzkHTleASIJy3vGK5doPFajd/+ltG+4aiZq/1Pn+QeDic+dm5PtgZPJ8ZqDrwi47R+Ry0Q8pN BGoxdW749nI0lCPCdDd8OEK7XqX5KaVR4EbaSUGB027M7HledgMxt5wEFehSQENKJMw6kFNPlDNK 6CLNg655Y0DE5gl0db7lquSLdk3idPHL97EZz8B3sbHgPwk2+XnZUG1WYlOnNADQiXFGXO9EJHQy sfMVu2M6qUkOCkTRR+yyv0rqrWN0uk0hL0L5+zJatAcv42zPUK8g6OXHwJRNvn5oAMMHsiLsdl1U gTHiq9Ir+gakPi4EBU5ubYbsy9oCgre2+MUaPFCW1s0zb0t6WIaK1No+hSbxjvzi/ZsStDFyGSI5 xsEbWA/e+HoxY3oi4C3b4PmzhmPvmmTLNgar8DLVQf2cbDUhy9yvpYn2dwCOHNZ6Pz3IPWddYVHu ykzGPEXEeFL0cnALgIj8jL+adZhNmX8zAnBIiyg2hvfY5Z7GHkOZYkf4vbCFtmUlaRB0O+xjr4Jc cUmdxONzGniYSWo3ID7M7GPEt8FgDhgqBC2EjHOIn2/j60obbxsdfdUFpGVCFreGWxGM9hDAaK3G Irw3uVY7kbmMDwnKSDWQyFtCPAnIDRXN4L2sQj/w11IA0jw4eaXyzVGkmp6JRu7AcQ0leE3+i0Xm 0tE35JjL0ciJTM1xiLRdpnlKKfVhn2wC/3JYenrxerRy3kk9xbQCNGg8XTYuvgEo56txbZiOMpAV v0aNIPhnUsIcjlEcIX4LnJFXu1UHdLh3uICUAG5Zb1ZI2RsHSw1ImpEVBa7tl6n8czUt6biGyKB2 MscGkvKnyY9m+AHMr7GR9vwGPe58zo/DcdjDBqTfz4BlatywQG5l9THJZyhHNBEnsz87aEmaGub3 bXFvNRQqigzPd4qNP9HFOD86VO0ml4Q+ES3UYYjzJFfEIEPzH7l356LL7YA7Xg4WnaihGIzLffrQ jDcjAFhr+Y/sAIO+Qg+VvZMqguQYr8xAciOFV5tn+v8K9Vy+p79TjlsZxlZAZJP0qrusLrjfWPjJ AGC3qQP+FvYjjRVR250No2Bm5LmBzAuxKdAQ1BTDqJJj/+UaodRnxdUd4OIFElbSY49ci2jDMPEp sFQYp65jbqhaxMlsBeSI9HWyk+wdPdW2ugGUWYm15mHPii+7496sZcjn/2N0clMRZNZWC/kk7QbS 3vhuLVbv9wwukzGUQjkvZVWVZIdlOu7KgA+LCkfFll9JnQs7GLhPZ14Vtr6dW3gokoiNy9pGQ6m4 haVv2aoj7qcwU6ZoSJjQ9PF2ydR6QCyaOqbRlQLPbhhqyN+5HMKkLzLNaskcs7sC/1qOE8ZekPSj ba1nVBjODtQXbhujTtfywLt6b1i5Ljm0Ib+qSQg5bEWJei2wBdka28U9FqtrmFFBNHMe/m1cpftK jArWV6FwRnGzQbYfWt3yFTS2mDl1r/aUkLSPtrL+9B8fCg5laQsUkmFPBh9Jp+i5XXl+lwfXZerl 0KNU0mwRNbE4Y4phGbQrHoO16M6219DOV83u678TRWoBBtlBOHVkQCaFtd0zfWGTomUpmJvX1ilZ ewCJ2CDj115ZaYiWgKDg/NLbTPYOI0ZbDTUuH8r/oL5pk1yH8dfDwj3Roq4wqW4tuxXBIdJQm2Te M45N3SzhufhryL6wvzXxTzCt+/EWVQON0Ih+F78bIDRI0S+4hMUfNIOoENU2Ls+SmZvXEmOCG6ei L7+dC8G9KWF9zUnmN1DBJ6DlLE7jV2clzxeIyXFinzoFcYAQn/+i6STgS183itAdKa8/Adwl8cBm 31uzzmoGw8RIhzU76yC8x6H82Yvts4l1u5c3BEXPc/iYvEX8oRj32XXIti5cvbEaCDR09ViH6PaO gVo9iZlDdgtlV9AWXvtx8A5+PDVMKcT/JQi0t6TzrsYlEdbS2CPUZErRT4vNSYxt6A6Jvyu9//ln CTL1E/f7Yex9e7aCUbmVhUH7WX5rKyW91CLAomAo1fenPw79omVlcA/xJmuyhzUDz9Y5wzQqDHBd v/ZlMSQ7fz6SsQkpJTaU/cLnyAi81F369a6l93/pEE9hdholUOKpEEK1rxEzOmDRKl4xR2mWldWx GaGLxPZkmLONN/9liFQGYMEMQIq51rUi379JGqmm5YlsnrSu21YrymkVoI/JE9gTF7Ah9HHKogrT YISaUuIZ430GcegjqovHsG4P/ciBjNzRLS8qPw5rri8hRaPZPNBwTr5z7z1wsU0X9FKpeZm8CJP/ b92y/2a80nfr6QcTQJQJNadGkE6t5XZa9QQ5X5K2UQbSaEQBeCWh53EVQByBa0OrCNdeiWIQN9vr aO1rRsy0FwPrCcNZXtuTjeJdxxyo6JJTzTum3SFvC0Ex2VFCCd8UaV/p2kOhsEErjjzcEfSG96zy O7r0G672CJh4kwbtUpjRiVCyfWtuwFX3Bq/xFqNkE77dD85acMucCKci+pkGz5xjIMuptePcFA+X 94bQ+xzphRDDa4ARCVeyXHz3+T3o/DE6oJ7TCFLv8YE8CxitcboBhqSPw5DiAchR3pdmUUPiGVtg KEnbLw6H4XIuQxr7pe7579DrMm058Nk9L+P7i6ajvl/uOKoQMxUL70FwH4GTqIZ79niR99XdVbXA TU1+FPpweQObuXgU+AU2PqyAmA1q6OR00PIEF+AfZshZGORDY7hYb/ZaKKVg5qPL1Hm+FA6AeBpl GKfM2K20sklAd/0+ymaO4+/t7m9spsoIqYXsaG9APLD8+qIvOK1wf5VVh1gX2WxiJeHn6KMEj0ya n2j/gRuvIQHXD0iU2iUXAoSqvRQJ6lo5GJ8ZeFe0olDJkHouMiQnbaAx86N13ZseheG+QjvyOrk/ iUDEdx46oUipIISKlLc2hb3T2uwagnGS9zFbO4dYtxnkFlrJsljc4Jojic8SNFs310xBr+ApoSvi yO0iI7gR1lUUuU10lbm/dV1EsEIhAm6Sg+yUoMhfsA+QihQCBda2Z9IFswAOqrjwkYXqVl9AjvOp ahkifHuZMGzdzAWheVWlURYxOCb7QWaKO7JSgMUSlQ4zGkYILyQVDNl+XCWB4ESo5fXOppljiUQo iCcGrKbI0kgWJRDjDCXKw1dOXVv2c2RbttVt/ze2tZryOyW9etCKtnyfvIeEW20GX/V8bAfRRsTW JKMJuj0+r9BXU5tLtU3TlBNMGjL/cgQwCNBoUicHOZ3XogtwhFzG4rQmFDwvYiRBG8PMV8avR4Dw U73Mzt+CjUhy3nid75IX/nTwYNaiZpI8+rdBwxXOi2UF6G8OQdt+XwwX+vqcuFLa+KL27fmzu8/G ij0cOtC79Wc5Th0GolN3XMEbzhTnamz/bzbLFN0I9OXNStmBNGjJr/S6Wqk1yUMT117v+ovfsZeR MFm4tbhwCDHczd9T9AG8YEmNfKjjg9f5zYDNlzBUGSlDfM+mNp3WYch1YcSvLLqxhmdNZXNnQO5K 1u1e06wljw6tvmBlGhIT7eirY9s4lGg/T8kKI/7wd8Gwq4w4qkhxNJS9MTrnm0+9nTFMj5hUgw7b 1sdfF294hllMdYkUm35LMp4B289ymWuJgjz3dOSnJ7hziDOiA2oKOUgTL86NJ18rhTSe5L+nHIqm ljwWYUsUJeJ8tCB7bNOv13Egeui/ZNLCATx53QFwBhWnI77jnc2FIFCOwuxvkd9hakNxxcwZ5PbS ALBDX/wOXvh3sl9EYbYtTFX94j6/83P6WQbEixktc56fSR97/k5hFuKNe7Cdp+GhK/VKykV48FOs nbzJWQUoF9qQqHbMuusDiwkKl1v+LfDTaVFW1fniC5kKHpO9myX83ikUyeO0PLOqYUrCxbvVER9b GF7WEHSfeiEXCvpn5HSxE4N5jJk0k4psSzVfaz9vX7OY3QiD5Nra0rZ2KrcvsVReMMNroew/IUZi 2kt88VHr+1DKCD+lrXGmWyGYjmyx2MIyHjhQfn2fSXPYkxmFQyNhzBTNBsAw/giy7zjb+9c1q278 5cXesv00B0uH7nVMbfIByM7Hzsn2mXFPc1En9gMe7E5pdzpb7usGPluYDHIEvnMFhj65uWQ9/kAA bbkilcpTSLu9alDet8gDofFz4SiV/mHJU4fG0q7qDK/yl1g1N9OG8SGRvT9G5Jtcsjf5UBwKLJip J5tEGcvN+nu1juCn43ZuMA5TmRKhCsYG4nLE96rLhb5BtuVOc1Xd7PIwxgq9AZWBfpnuA3Nmp1AP Qta+bOcslf4Vcb8U8+BT98Weahyi9YVTgk/LnyguQqSJH179kC3xmTdTWCbmmVpB/K73Th3DqWxY lXZrvRsvLF9N7rJqA/39b2H4B2CcWQgve2Zk0hFsxmyy3+543UJ7wRnkbC6bJhBwjRKQniHbYu8t 95Th3eG9BuVIK3CTe7f1vh48H+gHa1SW8w2R88OEe6aqrStuUkBEdy3LJVF27o6fACHNALljf9r1 MKhOjLRHyWA6sROo6PCRX/tcA8bx0wcLRGBcE5wHo52lTWqPGAzjrsEtAXg+ars5i7sS97Ni4zrp vIKdJwdtzc66XokTDCjeQTYGfPOKC/tvuk83gv5Sx450FzNeyRWY9Y07te/zXXeMMxbqqQz088FI 0dN+BY/y4r9n5AIaExkRhVekjijvEh4DRP8Lfyv+Fm11R/ZEUQihV7hCgLWc0n9a6DzTdl+Fs/Zd qDVct0NpRPITs8nbg66DiAp9GFH1/WUdHv2Okv2EImn6o76AjH0an6pvq4qvIW+kOkjHcgmVUyf2 C7QEYXs5DBjxOqZve4eL8E55WeubWPswdYDuWnBzJYb9YlGDxHtrLY+L4UwdfLSOJ/Q5URnQc3oO zAilqN6IN3qWXEdxD39b5aQHglE/hj4Y+o1N1ZyTO/W0OWlzzUbNlLBhytLt+a8i/GHfl65tJq8l Jg5FwerdI1sNg1AGmvXi98T+i6o9nLA/7gpCfs2+SzQDEldkpu1F6+cgZ7pq7ysBFjxx1cogPqAc jCr+3qej4YkIL+j8hG7Tqe2kVo8z/ISDxBkgOhwDfM1FMrk0qTQvX0oWmNXi7wPVg5E2YbzJPrHe 7Xbxl0gY/G9SMn+VgHQIgAR+QwbolyWZdH5fNLdqzSh2Q8045EMDFO39aCHLu9JVgpcR02d6Hrqh NhnBiYGulR8P+4T9UWwvcsRRWom26YfYrkzfPEaGhhg5HEwAVohGw4Il621GUPHXtsxmyyiXpeQE Q60Cy80//Nou2rSPAlEOTAy7lIBdSA6gjjEon9Nihp5O0MLiCRl0U5L6y8jFhfel7DYMU1JcL23S hLEnaZknccPO3q7XmHM0x+k3oYeFjfm+D4OaSWH0BUPtSLXbccAllRkRKTdSqa7C0Ju5t8JzMR0Y T5PEMNLQDUuLKSRAHc7AqS07vBmY6kXYa1P3C0miskhzg3TKmuCAR2JparmegBG8wia+ADWflKJh I1ifA+PFLK1aTmEHjDYq7E3Cz2JGU/bhzMpyTU7ohRtnjv6DmfepwbfegHy82wMqYQA0oC7jVGIk +ZU0JjDnPJBd4jRj7sEEEOCgvC/1OGxwLcyBdNSZfKxLBKYuJR7GyQ9IbHWKgzruUmmc9XCagSd+ /I52bHTybM/eUjWBu3yuas8gUi9ioJb4KRpvYKHCL3uBujwkRpcvFxcDwgzuNboaFct8qYsfqUTe fzsuvDgcCL2/1Z8Z75VilNtG8xq7AvVT7FDUj3oJ9dcE5dYgO263A0R0vDnHB0ylqBUBHRbNpzEm gi1Km9InL26FncaP0EK1JHWZtemGGTxt0Hg649GoSaIIfZGfJT8cZi9NV4FhDDtl8Np+MVHEMT0J Fz3gBnloc728ZKN4nyZFS2qrhVIq3/+aua3DHHI6ri7IEyLXwxbXZekxqadiaDpUsjTfa564dh6y FC8dTEOOx2EiYWAWocJAOMRI8mvfD0Vw/YykhYAYlarrid2g1773IdaiPvo8e8u750wPm6KCBql1 54EQ5pGAAAW8ggLEDlLNUO2SvU8A0VtFjlLxDE+g97Kb3HXXLp4WHFAU/WvkeuBFZRKceNR6miGl vyP1JyuKMsc+5OiBQGFqZg3JTNNKrMc6G8l7jqB/HglW7c44WK7jiO1IWAxCr7G73j5qiMn70JP/ qOCnSIUnrDL2+48s/y6LA/HvFkuz0Mkbe5rWlMLlyew87c0U5FX33LB2iAa14WES000ujGJb268u urvGx8j0J+qG8jDvZYqvg0mE78hTzGT3/oo8eX9veK2pgvBnPJoGhxAMxT2cHFl2ZwURnCApYzQp XPq4IdVcnUZiJxTSPFlCF9IuU/VofHGQsvd9AsjxlIkmUnWqqqOqG0zOLgNPus68c/VqP00OD1Se 4r8qalHlGrQcU5D1eTTAQm+bmrLs15pbWdqnP5952UOqhyVSzQcHNmDuC8oxxImrAxCUAz5Tt/Jf 7gIJ833jpHx/FZfaVHGcLRD+r37gHkS1pnWhsKx6ZhB9srkKp/qvJO2QKnwCaX0T5CC1HuwIg/sS adpe2p52ntZ1Ar2iKsJS/qdAeVXYqZ9dJXlbdREReKeqzi6ny02UDYYV9LT35z4P3YQesMSeKjAg pKc4BcIoUodhjr7/jr+/UEBhYuWpiR+Qzj+Gar9diV3Bql8pVU8uMkcTHZyyckyGEGanN3urbZv8 ZRRb28mZmvQHWVtFsiZqhDr47jLme9WYZ4KunXE4/k7jhiZGLa9udoUB5T47oRkFrCoPnZc5R/x2 /+14SGyiqpoJOxwKjc97s6Azuom6m+t4HkpTZx4bNBIZs0C3n09svA9bQx/mbjCyRtWePa493cll 13e1eicX4CIFXvkRXjE4zkdZARoYRP9HAfhaGRuO+vzFpVsfpMhqzl9Uv1rhErU0dtFgb/eKXhbB 4tTzemb1l2EKEoKGtDiw0Er2abZSVNG8X5v58C9HxcOS4k6hh0Nduip6wB7hs5iiKwA+BvfIn291 wgXDF549aZlTyKXCrU8dhu1xs6N1t1yfmhWmsA1gjbWoxFDEahFfNCBYwwS+w+/JLXAnyG4TnCiy ZeyFZSy0J7OvqNI3hZYQfq41GvCKDZGpPdvtlWtME8Y6bsebEFgtpTm5I8Us1Gy+XX1yx8hHNnfM 8kZjPTH6yWxFv3/w3iOGlHjMqLT2dco1zuIuLgwtfHL9fFRnuHC1AfiHYSG5ffjtG/pH+iLrwoy1 r9ua4wICc5jJHE5A3pCbFgDudGB7P0+VXl24kgnYZUhiR2hmlu7shz5tBDJXcliDQMIT/Z2a9gJ5 IFRic9WfxgunoGSd0Vwg18ZSDcEKNyk7KGE9393qX6fTv2Da+oxOFFkg0ZghM1gwvg0VJW0EOJAO tN5YruMlXv2MmO3KLOz/q5vyZxwOpRcIhTRC6ncArpim0QmMunbKEisc8qwOH1tmObcX4k2Zjzw0 O+7xea8ARiodu3Nn0Hx0KJZrgWIFDZwy87taV9sWEkwvHnBT3SxRYGmQ4BVquC1yU2AYUuW2sVU+ VpY1lK8qDM2R7C20vtfc/1r31HTOQsTqtoPvfeBaetB4bfMrlB4Qkq9vrYTa5EA3DT9ZqRCSueIV e5zXQaX+QhiYwgs1L46LFZO+SSTfojkYoRHBUNiReQvVodAxzgmsuMQXBXwlKKq6VuuukJIUaFim IuY9jtBHsP1QqgBLvy4cNuoB7DDLARF0JbreMOyJ8i0RJJLvZ6UhY83JSaFNxypzGU86F/XyJLH7 /thryqNEm401+YJQ5r9h+5FmEg2zwFMAyMfUC6OaNRuEmgkEGTHIYwkwL+F5MecWtqRWlBn4pmQ2 vp9fKDdF0RHTTU98PUDx4kHmR2TkkeVLx2NhTISNDs1/7NTf0ylB2dYQ7kYBhK9uW+DxxuiAkwK7 WozjT1L+KW7+8s6kzba024s0u15cbGrpIx8UQHdaZJKeR26w8aW5QgIfqPsmoqx/79ZSa8StCBv8 Fca1BHwVg+qwNjgPucqhaUSepFaZufLeksXDHYq8OUrSJ1oS4Iqxd+zciC56vx2oXXsxqFhFlE3z f3TBBrjfsINgODZ4z09KngQkrXLCYMuw5UF9EmQQsVLIhAZmjwwa/M6pWSAvYO5icd4hsbTRKwdA QR0qcpOff1YGlvMh2laygkfO/dGvlUfcPIDziPPbWOQcAWm3V3dbhSS2EbHfAkMTdZSSw9gtxp7d KpFOBJPx8SBLKIbin/OetW++GrYjLFKCkmEJDYYK4Lxa6p69HD8ja0mElyOLCOMDsGmUbD/IOTPi 7WTHqv2xjs0OiDbml++8FDChKIdWCCxhqq1PbQgGlMB8EDX52b4wOPAX5wJxhPmyk1amiLLRA191 Luyd0ezTuNDtFWoif7UG83m+QIHhC3RD02rXQNSOp4cxZqakt6hMwYGp69WjQBkd9z7LJUshmq/d EKYbG3FnsA3y+qRbrV2u+LkyugkXMeuRs/yXp7yXcU2L1tbckjX81/Dl1lP7rgsBCV9FrFCPakgl /m5YXvpxUZgIME4hMiHR3c+rkCdeRsEW/dVmPFu/HmqrHDLuhQfgLPxGdRDQANjNnksW1KnI1u1t 2gwgz7oTFogSuFPcjHg2nAhf91TLl/V1dd8UTRIzijJe1LZs1As00Mt1HGZ1HoRNw2lTFWahwzDT k03ygvkrKnNMeAmCoJAYkyUvuzIDBssYXnQ3+9pI5iq9wm0LSahY49JQidSiiV7mwWvMQUJnMubp MQWlc6mjCJLSXDoaTU/Iyxpxi9mimNclTH5iYBF900SoT8b3IfczBRGjrPDP2d8UXWNxYUW9YZHx ryDghadERxk82zuFZVYj7rZUu3Rr7Fb4gpivvPZQUq97w2C+ky/nwadjo5/liBRu2lBYX3DXjvlp CLahcNfsvyjYqWn1q6hRx4tHkYkULSpqhHLtIu+OTR/oJQH/oFE8FAqmKNmmRQNzrK8lny7q7+ec otbmRGWvbAS5XMBsdYaK3bDYyY4/N++rZ/IxTD5XcO8gElizKiXt1hfCEg/pth56YlkHOdhS4Lo7 UbzD0uG1guV4i5rALSNSXtfugWAO6tsHmF2UPNau5wLS9z0eHsW9AxbPoWXor7AbdZHH1/scxz/6 kG6SghWIj8mKW3U26TPfADzU2LxA77SABz71YjAXUxKWMLJLr99pQz/ccyKpJxoDNqLVP7Xf4L+X 9bxA1doRqX+DmRFJb38a01s0VGpBWR+x0Mobu6TrQzRybQfO6ZHVQn61k5bW2VflE2apoH/7Y1Y7 GTu2xvScIzan+K66OWWV0UJW/oZmH9Uvgv3DTMPGQkCgIbA/K1T1hQoLugUYlyVctk5+6OOGS29P vXaLSFaXZlMHPGtHVkCK4V28Gf8iLUnT6BK3PVhNVXB5y8uqeQ30gKTepZGc1Z97rLnFgc2ncxGs MgPx062CSo4DcZF9WbWGq8qL0HP3/iyDMzPnu0vcASRFjEs3xq7KcfJuQB3FBVM7Z7YDmqYVmyJp 39naBBD7Rxxt0zLPQTU26N2kPgPlFWodEXId6LL18HTA2fr4Gg+qblIjGFtrk5O/4gFtdbRGiRqQ zYKWI1pRmiQbuSJD+LRTz9ScnTsBtkIO4EXAC40A0PjFTDh5BpUCOk/i/RnUM55NrXcPCHBAzLDK zrTBbvbPP/V8yCk6iNwf9QvaReiIN2zUjhWi4+pSmJPy94bOxZoRxQO/gXfbf3CcLJ+I8AGUqO9M a15SJfd7AjyaxG9qaYWNUjFUWqUQ8X7Jqkon1ZPTYPem3AmAJkHbjwjN3GAIfXnIBvE5Y84IKa87 vK7VdNfPMpOq+MJc6sJV9eBhIc7eHfjWbr+Oucqds3ciUS6YSLFYw66RE9zQe31F0qnmJ/KehL6K 8tfsxaA1eKaL+RhYb5KLpQhSiyoSWwpWQjiDP7zG38aEZVsuqYWEVN/tyZXwL0RRHktx5EF4E3Ea QvLzoQfdWgJ4hEVogdmCfWQbUEkkC5sgJuZydEzzMHmBE4K34IbjfNdLntF/KbjgJ0+mLTf8cx2M xhEp8YUT1YjD08RykRI34dR83xmmxJ0WmEuNHBjohvgV6UIeHHnDe53gO5Rjf40W6nltpnFsBpF2 e7SfQ+rm9dI+H4779WzaV1VAd6bwWzVR+ta0S2M/ORYtATV+SdEBOT2t2/HLLX8/kbJjdaklER1h 1RH0FMebu+K1UlqKNkJ2Evcx18PiywbKxu7LTIpk/rf2JUWR//52wgzHwgItXqqNwaofP81+jYZ5 IADo6H16qFo/PuMx1U/4TSttMQAMzMni2m9m8bK3Bux9Nm8C0a8VoR82ZwFr/xvk5vVNsS01gQEL IcOMNL6++JtmsR02CSpDfbAd8Q60eQdkIV1Oedk4bqMQQVazH/IQBRj+wt6DceYuT7tMl/kBkQa8 BmfZyRUz4eHZMmkM6nP+OTRqiUB/jNnj8ma78xb5KYVsLzvnmM7SeZHfVyZ2TTE75jX+szadepUp jKlGqyBVr9f1aiA+Faq7uAY+qPfKzgUaJwKQW20XYenra8yf67ja0dqOQoB7si3upKq+BW6t5Udc se2Ub/rkQ/tGlSbAnLggXqPRva+VA4W1m2SMB7RwFdQ/tgCFlIM05uge27+jDmHjZ5VpjKs2ay4C vhn5UDxclNWJfvPW57u7dl3cfW2ZJPBhQmr3wkPHri2ZYSR974SAfjmUMHusPLC+5H/Migyfl44D PbdNjuyKPdobKwOsFRjG4+BlNdJ1Ai12jCf3BigOAHyrwn8RDDCrrQTZX1chi77Aeh6DqKED+NAk 8PtFP0Ch+8ZHiJ2cR/BrcM8z5QnYUy4/i2T/dnhQDjNeUkGdpdW3A9EQFqTKia80ap+PaIjyaivE 5WfY7l+2AccmZYN/+W7UhcL87M2+i0PTEtKrpsWpuFykqkf2n9RJ/HaQHYIKbIOSIRDictdQmPAX eQU9iMz5oC5f7hOEMmPC3U1RU72PVD+9n4bWIieIxT0XBbIN80mkVnqa0juOceyxbrGHyHOAeEUT 4b82D+YhKhH48caMF0nCF6egqcvFIaHXtYm08gEzBcjv2/cDlL8rUf30XtQNJ8jyyDyUSMGI4CQ8 gX7a8avkEdCpNOs0cuB6qiz8al+bv6IHFCtbgIUm3TWzU9DMNvYQQK6S5kQ9jD8e6X8p6RJdkYLc Ut/HW/x1gmm5wgFSMAk+keLlFwg9RmthY4VxQRllDTW5srBQNqnWz6JdA5HdmJ1bJTgPxFjOQMCs Yl1QiSfcSyOQXtru4FA82dR+Dl03GWVrXqJtXFp7m7xfQwIpnNNJ7X9rI4XlTS4cl73SQx3v2oI2 x9cfUtrL/WfkBm8k3NPPQqz4iyP5An+PqmFsMSHfUC744j1gga4yvVwB2HF7coFz+8hcqReX+zik +EjBWou3tW/3wM/x7bNRNiRKgUZunMddF7DpVthoyjepwE5tEFT1DAUWS4LUdJvsx/dN0v0uMSmz q2luVfAGbq1wsXsMJIZ4WJutDeJKaYmAEfAja6LVQrJojVZnOgwboNMyxLGpbslmLTOGHvuGFLX4 /kSsceN2h1WMJtsSerGaD0mQB8ZOOwLJEjRZOFxDlOPe1rRqjnce6KV92c6gKxR93PM+PcGpV4Df XOzE/ZiNSfwb5xDIL3jWzlO7rgnxZDzgopVSJJM9D0KJ0dX/KbHKVpRuqZjnOZVIZOypInKWlTfk 6kUv/L5XL726bpfBGzaXfnzVT9Oqnyg8yakcfeUcu1jBl7oWbCSgYzxshNmj93F39JuozD52EX1X JNbslnWIQCCybk4sTXh/rTjefMDsMxbnPKuhYxUQotr/cmjlMzC+ssDnJVgWQCPmRb9pCTtuhPPp WcwiwU0pPTrl9j6pugDnn6pZ4i0Br3pcn/sxVcmlilSAkP552kFLL0JApnr422hNj0aofztXRLRY 065YdP9RuvpQ4zkX99IxCwpw6mRXRMV1lC7eVISkPwh2JylbtP0UiT2VvAuAQXPioRL912qhcvdD rRMwwfHKE9vIj0SB5jrs2Fjr3BMKAfZl6/A8NJ5rd7UF62sRjCCiSPKxf1WmX9lf4JR5ris4bfyV PievcwAnjwo9TaiCUViMP0jAzFoBouluokqgxRBa/p78OKUQ4Za8kfAW1VzEldNbA8RCHeRBEtbv pmwW1g6F4ea4RJqRbElqg1cB79RF9HUyamo+UPfl0AFBBdW4XCdD5MVlRxfUlkHL/gBW6nY/jd0y aZtqzQxuJx+hht76EmyiSRnSk1+R6zPSc0kGQD+UFA2A0+jr3zbXqpv50jLoH+NsQXxa8labva1/ nQsPyuEDJOM4Q3+m6f0hoGpcbeHL1ZgU8Z99UC+v6NKryc3y8OTCQLCPl8FBDsA0Oo8TAq0YxWoO 3dMFqSo+MH+mUikN3N2C80VXMTc1xI25a+c47UGHsda0V++3mEd+K5LVnryuHRC37TPQkVeCgGI5 xQeXVh7B58PjdbnGl8lCuAuFaRPO9YBr5QA0mExdab7bDivXkGq192gcXmKmOotkI3VCk8g86IUs lWEkWK8euls7TXkvuAZDbno0xSnH6OWCjpewtZmmslQWvceSPhkzfkhk+50XX1l4PD/AwcZws4SI Npw9cJPrKDASoCd9iQ+0YS7lyR/SudN3ANsKdJvxb5TGKd8VXfxWTFTnDjAyckPVi3F/kCyjW2AW SRzsaEmm9ZjSzbUBklPWau+oR18dIsWvNMuUpIvmrE6AcKUD5p/ivzkTc//tHv+dHTE5lQhE/+pW xmqh+7uKn7sQCjvyunHyApDMgqE/DWUw9vV9MdkPF8VyVkBETNcP/VA3M6GcjqSYMgL29CjLRIKR 4veBd+yD+j6qclQv56WqWysee2o/ppidu0cqm4DWkYDKMIQFUUu0EneOWRTVgK1Fdr1ch1R0GK9X 5KI6bS/qGRJirFbtZUlsj+okWRfbVKOMiMkI1/tAdakxiub+uFPLJlnLC8TiKsrMqs76B+qt03tz HoL7k5t/O5VIxIg+BOv3aZIlDHi65ZXhTit3OUAUXrcUPRh6nqk/2uiJs4jXF0Y1WUmKqggiwaSj AAFcjXQf/ESeMtykgaVeN9bRDlh6F8mHEE9ebWAgbyMbmg/JkNSlGFhhU7lMUiPdWz8b9oaE/boM vfP2tP7k3iSZO4NLmbdEXlyUNCH13q8zwh6u3UnYOihajYhid3ShdeP6dVf7EBznVKrObjDlM2fm HA5iSI5k4b2ML/FI7AIFwb9i4oZLcggyo4WfCVesETaSPkNPw/c5qgLtBtYI2Lz9qy1IoMTftKA6 UJWqcPXgGw94e6YzF4+vCVyi4w84J+7jSO2lMv0AU3b1MMaPH6I3tX3Ckqpjt7Y8Ga/MbmR7ONc1 B8z8nPMJTn7vuGz9PyGMcFFdC639x0Hz/KPufw2jit0WKoCyyJblrPd+nuv4TyXJxFM3hUeboAz6 9olPp/GmR9TAj8BZUJhIAr6Jgf+ouB6Kc6m5yebKTOgbkVEFlhEetxA9DIevZIW3a9Iwkf8xaxxt ERNRVNvamGdaGe9FGEmwo0xT6S2WFIHFUWwJbBlp1yBB2NOaSrpuxteSp38wGbU50Bh9FowL5dya mWhyphomTlmjC5sV636OJOOCa7AGraH7LpR2Sy7zqV5FwNNPtM5eZQAuufzfcmAw276yXWrSQwGM uxauvsj3Srlye2Q0ZnC/mWGdXm5DcAogcnqE/w2QG7e5m0NPA57vZotNFWZsNvv06+pcpHSTwnrE zTGrff3J01VzJZNW4LBdq7ZJ1LRHaJsMrK5O7+7DUVPsNZuIuYYGpTYqVy6WYD/EXDMweBh3GbS2 94jROczHiIuEa/RPZ70Y+awjBVcnagC6WVBDPmH/zebaZxxNcPK3bVjiaR9uxBcNcVzLtUU5LY+9 TzEX2dA2gXXJzJ9wEa/OWe1pIwQht5cXrO5ehbXIh9GtY+IUUM512DaC2Q0QXHPzhEfDtyJ56As1 kL0HEWK9eYfZlD88u5oWqjPUmsswBO4k9LM+4WMmawymhLxmi/vXfMQ7usoRrMtmpUgDGlz53k3v T7AHmmIeHs3sM8a8kfLkh/E6t81nTzgUhLmKvK/VhJjUNtNkvHd2N9NmX/sl2T/nWptj4Eu4pOaa luP0mTC48mFnPR310kz/0HpShQ6QZNji/GiHDo4Ya9aSevJWwi87eCwZC6+Rz4boSUOeeYMy6n7u XO+NGFmahrzw1Vy9XBZHUPC6RjLxjtSoqirwYtvJx5c4GOQHqxNupyvyc2meeIpKu78uQmGUnXmH x+lFqigyPiyi2NF0xWFeHVMGXdgM286o2ofh7m+3fFaz54o7WbLpDkUfWwYj9UUZP7c7ldV8K1nq T3HnNXdV9w/LSw2BAh7gcoK57kmSFL1m/qRVLwkTEhbcpbM08YlDx0iQltYmroCUJ4yTJ1S4OwDV hGQA27bnj0ZG8XTtD4EyA7kLU9rcTMz2tStzJV89u+Rp0D3CdOBwrxwZOmHPX81PtbNxO2ABeHG1 t6ozzpMlNN9HhCRlIaMdltvRT0GjOXlccz3VSexsfzCivLcoQqtqqHTdZUhE7a9VzILf2+pl9b4/ fgbe+HyUL9VXRTUcYqd4VQej2IziXaOupCsrF/OPaWbTyLYTQyeDGhCA/FgCfR8Y9Ec6nO0ueKWZ OngLwjaFpGv8/ncdQk2XKDLflF5pBaa7qBuaXAI2NOvdMdtFeHGie861L6rA3q8XMw3iDICwR40o GE880Uv5mF90Jc24s4bEBcpRmaldHt6B3BjQ/dgrFnYMs98HNpGnQdnjtRjloyfvv0ipM/ukP9+1 GyvvgK7T6D0TAGdSsx5d7mkZod6+PH1qE8A+u7IUwRUDzB+ZZ+3RxBCco5WcP5S8N8EHlqQ+BCK9 Ne1FpcSGmZyUVc/VfsFKVDtRu2xVXVmXWaL25H4x/pMO3De4nVfkIMbxcsoBOG2Nf93ADoqIe2RW A/drFhL6d9fdVZg/2dQd7WQu6vFDkJPpHt0sSuG0uC4/859HohhVbWrc9a0oYWgQ17nZoituts6q hvcuMKSwBT1rbTCQrwGAfZ4xw4VgAvMg0debbw4K/XFeMeqrDxFWcFNo4hLWCtBVQHjl5Jo3mqjO h1abO4ASXfDoXh/0zdyco7JGm2SzvY+/fAcZzGCg/KnlUfRusf80APlKjCQ6/TKBETaluDjG3JW/ OSEgrs0LbHwERiqj1c7/a6T0Jy6yfDkMWcbF9PSzZjRADwxM/ov/f41jihYEmSRs/wegoKgB2s4i EAEcPc6XM7OuKFrUnYtR9ojHd5/YLB2yJe/Z2ozhmyMx4R0Ri5y1FLuk9GV0MXhA2z8RawGSnkIC 1J1Ei5PwVDb/s0KFz2+67y7+T2gnpGwSvJgcSfHyCApnFi89we8k10NW2hg9E2mE2kQHSNi+0350 15CT6SerG1JbNYrBs44+2JmbfyOMEoKRv3K7cgQr/oolp5SxpAwkItLig2C86hWERfa114sQrdi8 q19uR9OwIPElwhuHs88d5tR6zdSpko9j6g0kl4nYfdL8RkjrN9Dmd+cneOYP3RFUE8Yvcev8qZxM +toTCJPjstaIODyuUY+q787p8j1Q2LUwaBrpqJJ5kLAsKXZp/psVuFU7Hnr6DD947GPLtBfU+ivm qE2ONIKNM/+lv7S+asj7TN6WRA471pDoVIgRmc/VXO+V6A1vkboRQkv2O4FymdB8rh2RBSHWpAwH 0p+l80DxdJjZBSoZLMFD8bru/f89l03dhS8Eg8r0hUaDSXMOKi4WTzHoMghk71R+81688DCsXU4w AMBkQw0moS4jJx/1aMfmWq+OQEtjzdGqkjNrc/I7oklvPXJQcROBz5juSbBA0otU3EcmEhA5/nic VTa64/2O8GzyLLOQWSHPrRxnKP5zD6id1jXzi/UCxHbafUiz0zEpN8pLBOZOlLlPP0gp04MkrJJJ H0VC1AkOu9wKzSOXCDe/9/iD1z5mc3hRN8K2P924AENixOnJWGLukHc8XU6bjwOhR9KPu1PcoLHu jXUQcvO2rqbQK+GDz7Gy7EJd1PIu1O62onY6JccZ72/76k/e3216xQjMQACommXVLMM2BQYInZ3f v3Fkm8tlWO/kBLOivJDEP8cav5xCnriJAvAXlBJwmyCps0fkt2BQFu0L8CmDjwUhFqMwrcmdSPJb EKbZ5wjui1oS2ELK81lvn98D2KppZcWAUCXV9wllWJaj3xWXIO3VInh9jn8uwvwY9nl9GhoUkuv1 5XH5RnooFLmjoXVJzL9SzGkBOp/npxSHJYox2lI49mzwLxhfWIe5wHmp5GrzZY7RCVRnkSAT2j5b //q7p7BSl2y55UMoPV4SsN99cGa0AIbLR2EIgkWq9bOgVbZhU8EVeoR6XnBbfNWBVoqozPRij+/a +2mrqEYTdfNm+6YP0bIzwJ3ON4yxIpEFZ0ScNucV58RGslwbQu1cYc/woBTvxucmJ87ntMFezqys om+M6Z7hujyXhHSf91CcopEdILHSAXTwDQDgRwzPw+YwgNee102f1ztg/1P4kHkmXwYN2VFDP9vf cyR9FKaQ1q/wyXRaXwD00o7rriz0QSMZmtMUzw2p5icHu6rW3WY+VdFqR0MapYyD+wN5iwBEMyE1 mS40dVTBuBNQrHIrZc0QTK7lnXUAgri+x9jywngzVihAIAb1et1UKtWI13T/wOHX7Bxiw9fNa4/3 HGQDjSjS8uezfzIxhKIzIzQ9d2DrnRn2NtbgpjJc+twYjBe2J2z1zcE1TkGV/VYZAN3sU6ABH1qw gtY1JYtqF+yEpxFTtapbkUSjizYDPigwowLD1lwnFDJQO8QAEavjb1uGNTSQaU2qhGkOhjrRRnSM P1LPt4/QEcP1ACw9/CWwyn89vKDszCnLTb0oj9ay/ILsy1Q/BH2uReBqMy2mHFr27E+MUj6MhKYv WK4k0TU760dkLV/atQ3f0MMMWp4FvHZ0n+gW5jJDSFRpzW39xOUGloCNvdEU2xAe3Cq1iYCgcLEG Yf5rzzpkZ6qxAX6WjYSnKsmPWE6Eeub+Z8iwiDrREerQkLZQC/iaO+z6ze7zf7FMxOtub4o1KQ/g +olQkC4EfBeeUdxU6GI2dA2zghrSY5GE+vmtes0PPs7mgW+8PccxgJEmVeyODLNp9ce5cnhQSkIN TCLOYdrNosZLrU7Yjo74W93sTfsHIXToQJlGzTSqDEprj9BMa17UrYn4Dp6VIEMFS8m6/gL6osxs iISyAf4DooebiwsIH31JMbCiL4QDcVqpQr4eVgZ6wHbp+M+Sfdo9/PyfC9fD2W/mzUL0CN+O6hDF yeOpUuGqpstIfT+O0omdWlqHx9DsbVJfLnf22Xr3vcZTJ2L67+aZxVSB8uwskPi/UAAOF//CbfrB EhnpIJRpIiCHHa1fPvzG5Pz/AF5Y0jhn0Pbm0UrPY1dsZN5+WIvlPuSwt1JUxNoDdzsE7H8ncKYQ 6O7JBp0s0NHVc1KGCFIh91MGz+4ZOkEcyHwWP7hqdrRCC7PeW1c0AynXPON5KKQQg0rZezcJkiZE KGon6niLDN1xIZXhv+AqhRC5oNpAJYuOif5tzVhifdVKvS7CaZnOW/LWk+zg1xLqfc+p/WzeIAD0 lCsYSBNdFtqoD9YSjtudJihgP1tABvsUlyWlOAPcONUOonUeDbb1ClYAfuYeSksppumvQTzepjWv FpjH1tsGRcUUNM+NZqILSICdQ/ja83Hdjiqzlmjyvo8QDyKUu59BEjcikifpwXzIKcdjihToQLTi Xc5sAQGleSgxSDl8aGAJp6zvCYgfo9J09eJOYPYMN9b/WbAdhOklpJ75td48A22kyaoGYYhe1A1f KXK1lLlO7zyAoh/7y9lPFOrzLYoA5I8Nfj92lOUMf6LtJIfVlipoRFDLKeaV/HOW1t7vJl2R2k3M npzPtoZfRbz3IexhV1buxuGC60uHGtyAz9Paek4CVFI9YYN8AyGX5Zi+8OoC1GAkOIPn3F9iZYxq QZRzxtA6jbLdzHJpL8OlCwUKEjJd2q5LdZ0J/Fjjvl52eixVW9QnAW7moXW5wal+t7wH2GnQjT8K GKy7igc0YyMO1Tru8BYpvdyU80uNm+2Atcst8qoHGavvLzBdtGF1+jNWp4kn6mxsZNP0QTKSLRF1 6vbjcYeUS/ysOitAdPzeuP57gjZOfK+HVp4pm2Ewe/sClPnVOmj48vQpJf9F9rgid/GZVK78Oy6j 2KT8OM6cYn9jjMS6TF5LUs/rtxYDBy/3gip4t9IZKZ5eEMeczbM41SmyP+D2zIDofc1Kiyi64yvi +NhcGANa2uyMBXmLJ09eVIfVsydoqzoyFrPyfGZQlwqY22Czmkuvr9A0kMfC0v/SJFm+qUQEDc9j r28AppU8eXnnIHoPJ2KYpAsHb/fDcJUyaA4AIa7Epc0yEwE47pwL8Y/lL0mJmSZJN7wv4LiV5XqC MklUajuEpD+xwyJBdYHhn2qD98E7ZGvXd3NhpT7aH++SZwK3D4R6dmGs+oGDjyqTCAXF9v+bT47S 9cgvNNG8TVWLS+jy+VKdDdt92af0EOUfoRxqx1RSAQUd81Xm4vc5x+VoFFIG2XOy/twEuCN1xAUa eLo71X1tZ0dqGRGzJuJFP1qrdrPpRpPClbFIOK/2njqhc5VSWuFwyyTB+C+2Wp0GLuazqWK7aJDx IZwn6iCFTdavSq6wIAlBqTSQFD/tRm1khoHJxXH/eF4m74sCi+xp7p6pnAvdsEanmE40RV6l5CWE J7wukh5EJ9/gqjbQSflhXoSjPnpV5g+9HpTOJDOiOJ/UDJ3LNrPdq+aYFEf97rMHRlT//QDgvFrF 0Lx2sur9qSyJzQOysI0+IlJFg4fyRy8xVnFAewOZcUu/ioeLG7Hptw1pD4RH6afk5baATRhBDesR GreaAigDp1BNJzUKlKDPrdHw9y8Qui1yKkIfdejKPVkCWO7rBn+/LFyKBxUC8nYDySq0DPKpHOSG TATEuZTarOa6reUcOsQly1TxnMyYP/v7ZWrSy7GkXTjI+HDV63X2YucAiqO3k+Yn/a+yBlRZefqg nINj7aLUcJshgmgUg609TmfHZja/RdPAgIFYeyat3WxS/8B5jTSv9SOU1NYW2jZJzX1ItNJPWPT8 2Z01gCtdeC/alHPhDXX/k7p8j4ZcSbDZfMN0Zyh60Yi5XBIDChpHdzLpVTZRAq8DrHiur7h4WYsm 6yoFhDxaU+oTUDfAxkkIPfBBrzQ5PN5v7PkR680rwxRD35XTdu7rziI0jrJwQE+rshvDq+9u0c98 qhjD8QRicMSFhlgdIY8Ingou+Cjwl4XL8SfbdhWiQ8ySqKPL2cfqTWoF/ojUq/QILdoreKeRRxb0 U1N3F23wJ01vaVnTxn3LP+rWnuXVIkWYLXBBr47WFAD577AVI0/sk9pLpqgSnFpg5+W7du70PzOj WEplj62AMWcx+MSWZ7PpmmbCGuz7UHgvfMbwVy0Gb1lazYst+PM34WHefAOJwruSKKzCsKK8L9eM fAOXBaO5ZY+cDRHyUZNapjO33+VnTHXsxhMZ/9rAKnhqOpK34nBvnu/AZrzrV5zJOZVsCN8Nwjo9 NwLtnJrl0JhGinB0aGzm1XdlCrm7lqcspR926HvBm7C9Vc5BKXFT63rh8elyYbyGMhSNMbTAH7f7 uVyXqRu9rpgP7kuCCQir+L146kzCoig5zWvIMG5N1umFzFFVSyNnoo5ODBss6dbpDV/I0zY4oZXc eLSoonVmHhNI95eHgWcAjyk7HbucfbAUb6wvmIyL7GfXcRbL2+nx6zh7oxHS/uA1o2/PSNEpIRt/ OheB3f+TRjXmFp9u2s00VxgXW+iVSzLphVdZOhFv2hCnQT6/WqvHAmre8eSo+6p5/mEmeHPDm6jr CtiiyEhmEZiDWw97KKrWDGc4LQ0zwxVccg8L45sgsNTsqvmmH9Mj8fy6UeOjUaH+luOwboqzFeNl /+j0HotCrQGdxvyib2Ba4YKyiPbAFNpbZpguRrw8OC7GkWDUaET9O/23iWs2ZDLaV3Zh46rgxLFp zUeN8yv+JLlXPiPRwwjFNoWtSTYHvsoCT38Uku5XYZaII3LAi7YnD7a9QZJh0nWDAxDHtOio5/rV ywhPd/0MIGt1AtAW6jS/oOZi20cyAvxd1iUb60hUpzjhQst7PdpmaJFaMQarK3IM10EtrsIpTDpw ibInp1rjbBHjjwJP8JjeKtcfWvd0H3QecQBcTqfIzcKr9mz7Hxi3l+9F8/yJE1IlT5qMrVCJrI6m aRzd78x08EnowGlKefSHc+yyRMO3VAIgnRDl2y3Yoot5y3+ARiganx/w+j41EZ4L171GJ34JXk67 dl+ELTiKTqcfI6Q1jipHoMUpLn5PeTBb5URFeG4oCDoBFXLFe6HZbSaYrxsJZ+AVgbkg7CU+eSK/ RCiWuckIiKzJ+cB4u3WMu5Gw2/RpdUgyYyeZTS041LsZDPQKW39YLX/tm9/t2xOo1jR0EKKXwkY+ LSJngLx7muyDtetNmVQ108KXSopPFT6lSQqyB4G1WFz1qBCmnBCynmlxfz0eSmX5z/s3Ck+yPHVt BviXTpnoXSZxksTFd3ZZdAlknkbFbLDOdplMo/jiFGlSdI3pJH/Ej/xSdedby0IAF5k2roZB4+Fw 6laE2MMVoNGUGsx5StZO//jhbDVdWkciyQNPAAbn/GFVUp7KkOUBnmkNqlhLtowzWax7tN8VJzj6 z10ySbQl4ySTY/EaQQ437h4BtIhJ7jHrL5GxSBZAHAE09JHt+vMoAcojSRJfJQQaKgg5Z+xyWwCp P8k8AyzSjedOdKTZaO7FnC/ghisLbAhDeXWbE4e9dIhfvDORn/6myAnRTwkkGKqPYuhwyaRrNQBz nNeepe7LzAGgKIuVvFhzYdG5grX1L7FusPgLhQkDDnyos8CI9KkOF/gxNCO6KNgeqyPD4gZq0HIK HGBoAiEaFwd4AoRxuEn+CC61iPnC4U2fnb0boMqm5inaRmA2HcfaWS8W5n6Wo5cd+XoowT1zrfVE 1pLzMM5a3vUoTSEznlv8Lc1yefAxVD0ouzHdQ2goTfTuanxRjFvYUWwZhOeCnhpMIvD1MmMoNxnv +to9uiaDGjs0IvMVsWpjwKzlJa7e5k+YA7nkpyEypvnXTvZ3IFIwgVJFisI1c1FTfLRRzMAuxOh9 C2g8GpydH/FTYEcphdXcw9piYyuQRvnO7tSGXHXoCDavtndd01nF0bpMqAeXJCFAlViH94WzbS00 9G9zJ6GCS7Kz/1Xvs18y/Xpilwbgn5/pQcRyaqC7fkdno4gtQodXANlPPzgclXrZrBEcnSUTa50k 8wBii/ZvoTbmMjrHNu1KkxA7Bo0C5wzaD1PP+pP6dpgLg+Og2tAK+Qk5TtlT5ZZInzMSumZLHtMm jjXZxfUFNvgobKFN9MC9u7NmMqxNFLH5fwZ9RngEKClHl7ujHBPQcaD3zbazuzJAQVKDUAyV4PTE rgNNL1453KSowIfMywUXFHTLxeyvqO+NxU20CfkkWx0grgNHEw+T2HcYF9pRTAtI9nP0o0vxrNtK +QghfbCx4aVwWUmDtNdQmVvIolSvu16Cwiax5vbslsMjbstZuGfkAuvumoRw8lROgnL5zJ9qgBEd GB+Omp+p9muu7SAtGyG5LtSkT5WVgUPtvPvJ/OmkZid7Ww5sj+TJsl5omdpO7BZ26Jb5QOjt1Uk/ Da5Mkf0JSq4vLBvKM/8FBlw6JE3F3MI4+t6s+IInsZglF10BR0w5rOBn4Tr4KU4qtP8P5MTySDMD kYHnFWNgP+q6SFMNlZdRJC4yDtoxI/D5OAOxba+0pWNsw3VaG0Wy7RvA8gqVaxb4FlZ0CvcGAgCx pQLXKPCa9ZU6TxFHGZP4ArS/NzLyjrI6OjRtYk2mEkAjLdm41Rd5qlKw+UdtwjV9cJ0yM1S+Xk7J g3RJI82iA+WXErJ9gbYWO6MRBir1gHhJ1Vn4qG6hYQQNshdojh/LfLexl7ThShbgggdLs+05wcql mpkfr/Mlxxy50gLfxze5IcvuqLrYvU1Og/ezApUZg5nK+3h/bU6bp95iaHg5SmwNlnRk/03fD7JZ FJqnLFRJTdMfrOFhj1P84uo0w979hy4aim9YBW3GmID6V2ucbW4IkMimVpgQ1kjQnPG8wB/0ZaUy XRZsIChYbmzpjM5PJsVcSeLaODglyLgW7q17E3I/F94jjOpOyZWYgwRpLfKTOd2fLzU5b+qcHOaI xDJWv3tfvoTViDR8yiDWEE3aD0uvDl57dMpTBYVSNP8e9JRDor1mXVMhLTanQWgauZ4AWBuX9OZU wO7ev96Zy6Y8AlOpaRUZTPvtGq0d/MwD8nT/GwhzC1+Y4ZiASCGGCgqYDZCdv/IzuomXsiK16x2m 2USrmGFSvKgteRmhajWPez7h0olnTpN1C1sPL8QOYMTeTB9bPKO1bay27Am6rdL3tDFmLfgCsjfY PHZa7gW8Pphnq7G0EVAW/MLOkUsPlZz/qNQdK8KoSSAHZewYtyfHhVT65ghSxoSCsKx90ZL55gfQ /LLedfwdJKfyM2+h2Qe7jSP+c9DkuI0yrRFovir8S/25jcdrFD+RXcmN3moWnoURUwTJt76uwp/N IAVv8UKEnC42CCJzk0M27OwtXMpSIa/YlRT2Hng7vTELDWrrH9GzbQQmSADdrgXU/b8imVs/susk 0udxqAuOKq02eDoJZomQyd/ruDZNZ4bBGIPJKsMMg5JPjvYOAOCclRHnAmjjbssk1plWEwhXhVsE 1YqP1m1b6922BjQCAIOOaVcRhS2KD2k7owEy3VwHsBil14zo/N5CNhkzQz7HNj6VidJ8W1C4fFxH qlqyDDmcHFBeyIjHv0fEma7CRcaWuFFm21GVZ9P7lbzWRe3GNF/IW/8kU5/s4Oc+xibTxXCctgdg fTp5e42iD950yoG27y0pIyP42mPyTw3ncqnNLxJFwedGH+Jz64kLSLF8SL9B2Vuz4A/2I42j7Sw7 +gT72PWLS5qJgA17DVuhR1Ev5xkrfmLOqf/YYNG8OylGIH59LX+b18e000TdnNZKNfXIB3FjJFvw bYr2pWtGVUikML2DmTyoQfI11L6QsPppgdOYSsvmC+eeJ9M5YhA63ITRNwt7MpxinYkaS1Adzu2A dFgT/K3qgrYoTWVEtryOFXG2k4CLDdDTfmQo0T3BlM/I9s4K1XDjvDzsIlAMqxWionPz5l4GJ04t Bun4E0SqydQeCzgcrZRufOGDbBUb/1orb8AuUaRpISzxY51pFkrW215sCKC6XF5QuXsXzBq0a9Ur qkqV2dsi61Y5TwAetx3JFjQDo/CH2L58IcdCPVpRTeR8QqFK6DMNfs10BVSHGtUfv4n8z8hL1KFi dbPKdrXxyUdclNBOp7NqGp39RKGdstGj74GchFDxnuwH/l/9Aiy56Y2odDZHE6lXKCTSym28VSo+ 1UT0KmoVsAj/Lx+66uIiLIDINfC5HYXoao0BZxb2PO/DZ3MHOHrsui3ccOSOhX3ahIjhzFCADxtS 0dgOzmPQ/z+Gz9Zs8fcJ2Tg4LoFaCWG758d/WPuKRGRulM+3QYIHG45xeMMJeWuRZBiE6RZEaJfl 1srwpsSDoviJVF2x/H9qOS4oYor8T86xuWN3VX5n24ZVWdfKH9YMtyJZgsc9yJ+GnderAurhkkXi FxsDQ10P1N6lMPMN+xCXchWx361X4jl8wkA5y8NG2T5SJAQUKRgt+zd4hjk5+KydiysFJy7a2WJd WHPyq9KoW7v1xjIJeGcyR5cmy+4kLzOM6krHDLThS+qMKtGfB6NDXRmS5i8VuLm+S+nd2UmUuE39 ILEcuwmeo3stCkv848RUXYxiC+t544actCZ7szHGIqJJX1QhfOWJiC+RuWwBsclsKDtGPOZk4Pov 0f4Q4r1t4gFvGZuAS5E5iDcU40i9EoMUxyKXBg9ZY4PpYH3XDxOWCYx8fuhWGtBusSngdYoKlBJw CM1lZO/XYN9Ur/P0KqO+0MDlJHs+7ohAK2qOIkEa5c1PD7XZZ/TfYeyaOcayqvzbXoq1q6Mv7dvH y+e2jkoIG9i0ktdQFEAlVpi7gJVvWqFFv14V7v0LDHyP7DeE/fRq6qNgAKDraF0H5VL52PoCKPDi +V9YS8gvPkHzpMUnRMuLBzzOcieK+vWBSIc2WOImBvYzGlCP2NYdmMFXHiyrxLCYFAv5IueiBuAP KHUfmDbmQygahVyngGzfHLNUBpdo3rxy3eOlcZoMqZSebE/Q9P8Mzs4dkO/7PZ15hXVJggaq/ALN /sxsMPm5HYfimR7JvGOC0U/4Lpfi2/eb2dgmMxlZEai3yiOwO3co9yepU4h6RPYQO+hZfJLJjkl9 hEii2WWov4jwh9rfLeWw5BfnBVMbp4kR0B3g87QTX0f66FdpkBJA/XOZ7G3bOz/7fD8YIJlzO2QN lCEyeU75or4QjXnNGKaBlaDgKBMLs0L+qagj3U8cQiL2hx9ha95dNoVqFkxoOfgkeOwOzD3GMlMB 4f2HrLmLtKGow3+M+oS+oe0aPNPeTVKrfmPu4QFlNrBjXzmbAK2IoJ64ztVQ4A0gymCAfUdPgtcS eWvKEXg3nSTe24OFUtz5lX2SIkMO0YkRxxl6JcQuiDUlc/7m0H9vIxd3UR4AbnWu60I3SkqKYJ0u azyFyrK1v6X+DaJSs6SvPUL5Q2b3fFYKF9/fkVh8lQkp5aRXBrzhPGWeE2yhrbwm4DqWS5dHrq0/ rbq6ppuC5ON28VD1fbJag/C7JhPhe+KG982Ncx+BnE/cS5Uo3o6JDA+cAYQkN878o0DxaYKxmJwO PiXQkqkiHAz1TW8T4xDIlBZe77NtVd1x+t7H91IOfKbZbPJy2tKpuYKT8PtQk/LYI99wG5dtZfCH Mw5hnd0efgqzCVI4R9PsELMjdUlBQA9COV8W2gImiIXzFjt6qhbbqX4ux1eC1D4Ed35ojB2CjDIK dKYc1GFUkQ8TOr2jYD0+uqYoh7aLOP/1t5/dUXrfPDgPfb1PTnpLcYxbcI9J1TUyRTWf1Qtx67rq Hlq5lgiSO8SzKlO2T32KvHpr2zqfyft4QPfvkLZTNBpBmm8suaa27IQhsoj3EEC2Ch43Ur/VE2H5 Z98/JEcdRS+0404hXLKqUtLf8+AxnvuqpUuI/Te+X+xV9lxCy6sHjbmj7x1FYl/m+pdnPhy0doXi R2h7jgU4ADhvu5IhAE6TfETWbLOQCQQW15/5iN5rxExU0iWahNGvxaC7XrUK/LrBflsYroBiBFbr hCem7QSQNIC5/ytuJKVkJNWUr6qphOXSg6dvaGYR0ZzWn43h7WTDuZg30K/WZOpUa0a9PNknUd/6 vfkBurhrSxBScyWbCyblapEQuLf/vMzHBoWMpLwvpa+5Dq+1VsjaMyobLf2LSY0MMwYVj4AvEkCM RQFUsZksxJWRUu1Ownfc6spYOe3H7GBYdvJbuYsoRp/QZrCsvx0CEVYc1ZTUKgpbobzSmeohFSW9 39DX9QwVC113q3AMF1XGZSlqofbFQWE9CUv+eSKBUYTXBbQWSnlK0X46qhwamCdZ8cIGP0Y2Za7S eOZU0YK+1oePt/kjJ6tlDpACE6S8IMkQDVTEEY8YjAkif1aaIv8rcslGUvFkNjPgbKgkG0uLirXx Aj8SJTJfrvQpNNgKNMHbBG5luYEhgIKSRrtsomHbGd41YBFugMGxIzpkigs9qQNapJYOFS0AAve6 7LIv8G97WMd+JJZwPosFUO8PDgJzMtCBBSUEUjX6ECvZrL4Yo5+3CQo10oCNBlZ6jN6K1Ou7pVEs V2xbGGmUkqtm8HRotBQUZbtk3bZEtsWLdSPqkGJuvyK1tajuM7VPVxZ420t3vQOjpVxtg6iDDpQo 4GcGVD130BaQF8J8jpWc58nsGsLFOf5EncB1GHZfSyex9nNRgAxJTJUfqGSEfnmSbr70M/s2yeoM Bt9btqdjFKMo6sBF5uWnyWmD3h/72Mi0Ajxm2l/Dp2DOOEJM9UX0qBjZCHSU+jTVe+ZM6c9OgqoZ mQC/Q1mHHIadpylfJRnRsFCl8f3ifZxnJFPH5nxyTkyv1Juj84rf1kEmBMsYYSqWRi47/F2qWPy2 sS6mxihTkZiuhY3zTzHnITMwLAmiGx99efMqplWnykXgg4Vpx8zwj3yY6lAZafNweWKtGUr/ifoS J5HviybRaw8J2Ioj7kTPZ1Z/05ihbKEjKTT9/Or1el6h9oOMYfswkpO05VwmpbxWrBLDFgZeFEi5 tC3H55d+sFAQSsyEkmlXPTV7XT//QJ57+y4oGHy/8ujGZP9xvHcxja36dvCDL6DUzXC/tEpKwnLZ hNXHv25Q7YmTp93F9Ihwp7jYEGxSwh3Fey+fLkJcMFcDY6nW5N5zePksHzGTqDXypv2G5vi+WJ1a TRrDNkqOoI8PJZ7MkE31mHnxy2Ub6EKD/Hs8g030gML1lVBleLrm1RimM9DLBEsbGT08pzmK6ewT AFKKiWjU0sW5ifpXtpncliRkWS/g1E63eefAgQeUDaeZWcH6mlXspVBvEMdB3p+qzoVHW+JojN0i w36wHFDyYxvOKq+hwO6cJTQd3UqZ4lwEhdOlpHm3favG35fkU/DHDU7mI8N+oOl/uxqXSQtz1po0 R2q/Y4bSQ5JX0QHXOQIKsssxcccZM2m5HVdk5X939l6n+3l7Tfbe25RIjIETYdWpB0bBdJMAw9fc xtFtUCDcV6j6Kz0VGblplwq6oYF6fGPn4O0BYby0kA2d2LyVqV3TioTChXe9YmrpZu3TKbhwaUCj opiP2dXYd1NgRB1nThwAfTywC6ZSg0WtI2RT0Z4adRN0/z813gv3rolPk2OmdW7o72N94oOKZBJC P08TNNqERGLCSFvemT32FWW30NFFH8YqaoZO6Fn4Bg9IxO204BF48Oeq83pu3/Fyef5gOmFLd4ql QlcSWoFCQgBymhJBu1slyYcLGTZWwrgGFBz9A4McXakQCr1hTuovAFJVP7MyxZNxq35hFZ7J1hn0 ecMoQsaEiw8GBLclNKfVZHOxgJQeqQhQOibUfTyxTncB3lm8xXwy+uZWeFul1IJJ4QArsRV9UX7z K4dTIG2p5tbaAebiOtkPrOBRtFjyjkXnhmHFkO3h+Bm6JfIll7BGWKiq7NdG1aUg1hgR7GxvEt8W VxSOvH0cWoOHXFsDDAOCTRIFJJ5bf7CPLvlLUi7/obYXyXemyrKRF/rVpoAF/zUvO+SlM/wlwRtj VF3JjBqDr+B9oBxh2RHxUQrL9pgXBaKWqK374o+2Hyc55jsn2gFdSq65UPTJFDDkKQRXK0WUUtfk 2Btj/tzzyBFSYIC8hM25guwBO7UCWurirqbFajjWPGa+A522IJsatweRPni411th6Luv5DxTas44 Tf69cVztqttZ5IjXsxOKVhTwkC+onylcc5eCB1kfNi0jBIziJTevwMSRqKShGJe+ToADQS90A1bx F91hiqt4CF9fKIlD7cz4neuUdqrfadZqcm5sLhl1x2JgXmhG/4Aoj40WH78HhCRD+eGUeUYcPhXk kmqmvgug2ID9BnRnDUSmOS8GrU2CR8prx+1m6V4iOGY/uPCNkxYxHOj92WesMO21v2oWXoCNk2qt /q+18YYhiGWveiyNkMobYN7W28aQxbyWOGapvRa+fY6J/Dpq7FIMo/DzspbUIOLZWGujCX+dua6r O2Y3TGVB0CBZCGmwJRv9SYiS0VAOtWnTP61QowsICaQMkGjnN/9qlHHwPIhnUk2Njf76Ysb26WaM 6iAr+YS3OUxrFZIuBi4JkUG+sRU7skuJzFoSKncPFaAAA6ZMPP+tKIfPexbEKIT0bCUccHYwZ5cU uhCIeZ5PQs9SpiavBe9jyY0VTZgUSAkPkRZqk7GjHa2uLz+ZNowMBPRURYzeyWHpd9QcjO0jl1w6 b8clLsKg7bINi7nDZU4NgnTvkBtM9fpJGoFq7/Zc+l2/WbWxDEfOYU75+NOi8mMf6CI+bdGUmSHG 8rkzC16tq7m3suTFgFWUbgLpfABRJfnYMBKJFxtP9Zc0U6AP7PUarTceaVoIDcGbTKRPE60TbDP/ We6qrIYc7IapDhUnEUAu3namVKEvC8gLszoQzUUpyco6Tq4V60EPIBLpw3XgxBAVbqzcj3t+F3xk w5h/NKbzu8XcuSA3Aso6ZOGGSTLQznwqwLAmRX9MYlU+moyygPeZrRKs+46PYyg5aPWM7ZVZbSqS jG5d9UgNHVLV2CEo/rObR+ZdxcTlOIpVmRW05rFTM4rpXH1jzyVeu+rs5dOS9S5uK7QHAatkJFsm dvujYseOQEEJX8WUckyqhiynTsaOvj1/dQIqrvdOGHKP/xg9l37FLEL1TKWd9OifVAVTHrA3aouL Qr1bvH3o1fZZn2hvGagME7UP5VC5zYckglBpNtLF3H9CQzcuD/fbGv9x1mPZKUwZ7EO2cH7Ztvfy W94Yx5SArd5PvXPYQLBN6ZDHz7QIDPtgLf0IThJz8aNbQafcIiUJBonH6eOiCtyBwPoX7zh/EEGv x2iiomo0ZKUG1zhNJ8vZwVLrU3Ifu7E4f4B6SKCARkiXISUGL+1ItId576d4iTmg+ufHfFScvr0B tyQAt6GV6wrqj4DvyGYuIShUVX9EoRuLxldbcW9SeNpD3Gnvd5SbrNT1T9eCDUPgEFaeBVDoaehJ ny7mB+HQK+Kp1NB22Mh6jLyaQQNJJ7030cwHZNMkSojDQRQdZIQIiqZnwZf8nM4uRINRwtcy/T2w ygIBiUlESgHQatMlyEEWevlgWKoLgoLN3fDm4CQQvvcH5P7EiaKcD49u9aGdtK8ToP3FLl3wg34k 7mZCgMNHRTPQqUK+qh4WHkK6IoNhWPedWneXt0QnmdMaZZihiLIe6Sgm9VwiHUq25F8ycHQ35373 9kYKvK8XlZeLYdQ9O7joneNLw/VYP1r7oSyADLG1wdHNyOJADMjBAAxYaYIvpa9ZO+L6cOarQ/PN YQ3gHCki4zELqpwcCZ2uQJeFyPMt+lWws++Gr8YdBQTnYQgMp+SnOxAAoSVelM/hMEy8XFSdC3O7 UvOipLul6N2p/EEtbHs/riYO2bn2WG7QVoOc97Lk0Wo0jScgCjpYa8Zyma9cnb8kDTN0jhNSTYq2 P0sVOT4udscJZ1BgKa5eJKFAzrlMX3/j7kKmCdONbxfzReumFj4ws4txYqvA7pyMCE3RHbSIU1eX FX7vH2UBVvzOvwLnxjrEu3+FVspTaYXkVvqTdrb5ap+diTcxXpiKLKJTNlYmJRZVHdzwB+EUFpK1 EbhoZIqb2zFJRRgmCgHoOKba1pamE1vmKWTtgaqv4IPl+cgVddFwvrVEffpDGLSf9CyHOhYi1BQS AnGXNgMtn1P9eM2c7/eynwBdLqQr7eAz9JzzI5e7EXoUPxeU3Q/W0UZQzvMd6RTCfBzNhv/oQacm OBK88JVEy3tYAvBeOfHQTlBi3Yh6ISYFP+035m9LnwJ/ATaWcDaV3o6lrBF3GEKJ1GwMj4ozkBDS hqzT04W1jJGANLEdcbiIbgpBrb7tvrC0DLpsETDMmbdLlgLGm1xg2MGhf2cPgAqVtzaiuCUbMCW5 CcK8FSwfEjDln54f2dSfx+doi4UgMW7O+sgh8jOlIvGFGkavDcdoqEAb1z6JJZwa2Ay42vRtlMpF /wZMqoLiBZgUvQEn8RzOaI86ZV5SmDEKDzzeS9XbBhv5F7d/yH+udhCbnM/WUqES2Brho4aMCCYM C1Z7YKwuojKp1uybfVn059ifDZB9Q7aUFVTb5bKGOv2lKQuBOcyjqqVnLN+JGV3coaQ0WdiMTbbC b1zetNS9wO+8CnAHsxWB2FOeu3Ux7whz/4xN2DPjAXmoXcsPZgnO3w5RfDOY9IKEubhmEx2xOiRB WKEH+xf5010bukz0hqOe3AM9eMtVSijhC7out0qj3hHoMgNB/NczqhyKmqXS+heho08srGWO6dfT KKZMOquzg43m58lzhNzNdqEvOnAiAwnLJP4PQSkZZD1zw51XWYK4gpPVYrqK4FOpZ8/0oqSJxS+b F48Y5fBt2XzneGuyhJE06CzEfx4gDPz/LrJYTZbDubI4Eb6fqoyxKXZNNx4AdBUIeGJZ/C5WoVQW Fj60YKgrRc+Yg7LDdVB8CEW5ZvihxRbSh5TltrKw3Vl9tBxe20JSRoSHlFJnX6LWO1qYz01Q1ddm 4gR7S9w3/cE1Mfj03b4ge/reAXXEu++SZr3Yp6usDVbfm3vCZexuxWdaAPKQ+XHIU79866j5I2H2 g2k8YXaSxreYO1obhb7hpyQAmRKBIhhCIQq9GCgkNd8lwjbDUwvnoza4My64CMUiq/vP8+Zth/yb anuPYz6L1pEVsol+6o0J3mKmNvAYlM2Voo0ikKWjTx9mICgv84MqU50p7xeqgHd8ZENXI0vLhA2A fgh80/jsdZNBEHNnHp+54/G7VGrt4o6PmtRjrZRm02DSy9LGFx7/u6QDiax93/P4e6fqJv3iNL1A J51iFt+StU/liTfw7oXMvNi4sNA5MYCrk5GEVl0KCd7ugGUPo/QwAkJOw8tqyHCD/+9cr7jxThAA M+qXRPf7eBSUtEvT/lB9xzC8i4/zwg6adocqU/2x72Vo2/peuwUdczXftwjk6/2zGRlIHj8iluVB ioUak44W1hNNHIUjiSwOrNAT9FP83Ld+kER5KEHrJUb8bUeV56QtmRjCk+uipfh6l84SvHUbDxaa ujJucNFVjE7NDcZO0101LoQDlxS5jqElvxjQBBJd552VpMjzVo9dCn923gUd0E7TbOnFeLSqYq4n T2zUJDJKsTWkyViwhOLG0mU1C4d/L0JHl4acLt/Zi3Ioaw81mNfomydQnR95Fb3jNYJDKUAMvKR+ MuVIrZ1/qhlk274rxfrkJazMSIvnKCs01nAG2SKVPOZIEfG8quIRgnqIwH0iZw/Q5Ybp7T8jhxCU uZscR4Pf1NbRNQn6xfGHkKdpyLl3y6qvCQhhwV5E1rXvEAEqugzCTTQhOS2pVXqdiWlv0/dyyPg8 NBy9mNX2XUIKeR89iKYljfS9QMRlkeTV9/XL1vfnv0q1wCgdAI3hlgFDs4q7VFHOpcs1XqFivjMk zLoQ4hEYI4Uu5ZAGGagNa96w9kZKPTzdAh9F53UK6hH5A3nSDzerKJ5crCD/JaW7sh4jFpy9q7SJ uTTkLvtfQJUT7k9UJeP2FXWXJVcdoY6dcAZnyPVk+f/ZAx74JHfkxq2DXzdvaDtM2ehe7GWaN9ps FQnS/pD88PDewYGyAPwQGcxRJ6X5qRAXzz1wDd4kl718s4B2ytzvh5YG+tLzvS4YoDepHgPf+tHk KkifMemH3AqUmhJwfWNkc0qbEduXNwGE2pNQPw5DM0JyRqLuaskAybBKHneV1nTze1uTaY3MsFZ0 V/MKS6fP8fHx9LPc1jqvLkNZkK7oTPGkIbv3WdISoAimbcjZBdsyTET8uMpv8qmWPkto2EZKbHVd LDzblWUs0K3J+QVcOQyq2PKxpYeT99ic4fmzizKWCcY+3lPwY+RhHuEB6XqJJkwxvC7S1mmnOcSq T7/X26AQeXIpO6JsljBgTkrQFe/wa4Ar8Eq1+fVo6BWXAimTWHDPYN0BIYGsI98EnNU4xe32iRo9 otB6jXjPjiCrUj86G5ctls2L4cnroaD0KYc5xCaDF1fnUpADZuUV4d4ZwSS8TwmZ1W/LUAAq9x19 5ruTfXR+B5TcZOo3MR1CjqfJyUKG74HPzgHErSgU04Y2K3RYxIUdV6Jt7Hi2/OqiOuAg4j+R9rN2 VXwGJCznaqC6XGkOAYNL2RFQ1jwL862bxZQ63nsXErHmvnGiXhc0fNRfU+RfG5ffefZbrf4JZrXs u3J1brKc6VP29OhqKwTuWdFoZE8yLJ7GJWen5w3KrS9NXakzCbD6iJwa+NAuo3qdUJX2kX0uzi/m ixo2Ctc6C5mlWD9YX2SJD92r31t3voQ0taEDmNrDThvtCWaR58iVt4E8EtjKD0hegn2LNIjPh8U/ BK25WoMD7cwQ4aFjqQTFSe2JmGpcUSP6mYifMwZoPSdoWMkwRlUlGeQA244bIqpA3HSIhqTwirhA lzUN7l8GhUfBe+YOUa8O9IXF1xnyrO3gq66cmvbpEnAFhnEBaWLOOkhGtD1R4FYVXDUC9H4+fMPT gBpecG6pQNtk4UqeazdxmPtr/LPxPiRyC1ZVt16/zNpkSx7NYJLKZZyktS3SMjlB4RqF86GnHwL3 7fq+uwpTK+H3x1J9uuZOJ1ZRBXBdVF0gMvxKt9cyuRijcYLf5lkzJibP4UmX/YzpqxulO2SK2s2d dWZW0Ak1UtPT/VXnq4mEciA3jz6jZk1FHvNbQ01icZP9DeJGMENp/mpnZmcMDmKsq50UnCQmYYqO NlxIiqbjxd3q8TOXyK/PDs2RJPH7uE9l0GIxGbMpUmOZe2DGUPrL/+9OvFuVa1SQH36w8nOner+Y IGMZ4D8RQZ+CLzsr4AIFHkeV1jAfac9B2Uj/AHjiH+zx8qBLOB8HyQrZ+gBkMRrZnhSnTuUqN34N C1FYtfc+ylYE4iOHzBfyC69MnqIf4kArrgDOZqbyX9JUtQgsT4xZKmziTC7oTBjpSD4+lFXmbARc 5xQ3zz8d3HXz3zrJndPYMteaShmldL3OrEbdCBYwx3J9TbX4uEe3Yg8z8t6M0hjazZ/g5KDe3ZWp 1Y6RBuugjOY5InZLVuGRTNFK3MjK7MnFzmfqxYhcA0sQVYEND6jQGhfG7MQrXDNGOkBhuWYTIeKk +GC/6vwjxevPdxh0gDzh+hXi6DBRARisqz0pTgil2l6xhF6FVbRuLqYiiNGq/3QPg60E0m1/HLC3 zSYi00UVunJqEn1rGqH9vVWdmKlysIJj01eXqcVjQamYlzDk39NIhJwqGW/6o4n9P1AqQ8uoH9p0 Ztafm5QrcdPIrEQXtnKAQ4NcBsD4sJ+3Xu7ypJVheFSqK8BG4I71vYdrOdmGs7he5VIEEuqCzjlq 8eKCNC+dLPEVrpkFC9K/yp3Cw/ypVBMa5zf+UhsPjlilc56eh8BpWEpeQ8cNnl4HQhcijDVw8Lj6 ZbIKZVDLaZvN1vCDEBHNe7W+WY+rQ+bWrAnsMfeeYnCrRyemouUMjYFK9MJ4cdc8Tf3l0VS8HrgM KpcQYyTOBGR+Q7yOKjobzJoaRlj1nuGftUcHkQ3VbEuTi/4OPsUEINlo0PlwotgfNrW76fqe/l1h L6brn/3eqFpxdVmvjOsQrlNecmKhi9R+/FZ0H+F1IFUDT+aAYwgj/5gWxr6QpePcqRH/e2SEzQ3a p/ic8vCLruatlxRzsJ4uEVsjOMHW/DH3Rb7vWlPH2WPFRRqP5Ae+FWJAjY62UcRWO+14/t2rVwzm abIcKw+X5aNP2lB5YaiVeJICcHxuQhz8rv03FgDtm6kuNR4nj7t1lc3Ng6vtXS+L59imMuJrE9jt 5xkLvkXAtPO0ce8O6EE3+J65AgGGfyJQmWulh44BREVD8stRsxY3qnGf9Le18Nj+Kd6SvAE/S88X Yb1NnFA1SRptDBMDh3h3gDnmqpQgMqcbzaPY5lnamPbjXgSybTKy9GW5dltlCx5OjxvZEZPXAW8x ioWElaaH6uXoL43XoHAer3EesDIBXKpNRQeKBMIlfv5P9epGfY6twA0R/CT+Am9uP44l7+DXojyV C+TWo3KLNWJ5/QTZ8Hpdq3kOGUg+Nls/4PIqNmDFqb10g88PgVxePkkC7IoJMUWPwvU/CsX1erR3 MqBcqGKFNhjW7Sa5908lPY3Evjn/ffIP2sGlZ+RjnuIooR+pKe9ezo6Isp6msYppx3acizYNCSh1 OLemlRQ00Mxzi8vMILh8nXWIfltUFY+hcfAK/IbI/Ymt+4CWst1v/a1fCZGjEB/H481PT66uTSkY mnMk5UP0JzCGJQf7mSVnWIstB+6ORYhqWQclTOOGml6BZzJDIw9Y9Gp5QuPJd8DaASB//3i1Q92g +qQoNF4waacUcB+YCEA4NPtY/f1ZSU7xYs/6NUCO7cBwUBX9X0cKcQ2U5zYRqSz9paeT4J4KT43/ d0hfuiW5SCuYlwS/+0XAZaSpMAF4QBAHOtpPet7ANoFPaiS+jaJd8Oz+OKEykoUp0xaKGs4tyRr0 N2Rr75QAVQHWD1I4iUjQL31uG+3erPpDEm75DIvku9SXqsr+jNk7wV73eJ9JFoTQta4F4sljPYCm RmYBS0LlsA/WkseZeTI/Tzd9ytGcCzxW7ncDzSVwO47i++ZD56roK9QiOb+lgibmVTTrctzZGSWU 8IH0NngkOgnWW0b65wYbCQm9YPS8wLqN0RBeKB9RYYFgeSgnTSbMlPv01sADj5dOLid9Cl33YNj8 UOhVYe1V6WZbOXp5blJjUKsCofnHwF8djMGPIRK0t3A9ud5lmvRlK6rd8V3eSydiA3ebJ3fyRsrv mxVV/a2z7d/fosAP7bqKn+cdqTMxkv2RxjdSzOX3Tpd4kQrruNbf0KR1QT10FS30i4Edl0lDsF8g Z298TYUGdMTwC3CAk9BHzearUzQsyLLBh9pbQwD4LUDoZXb8wDXzWL2HE/5QGEWZgh165S30HDdN qEjukE/V1JZvo8yFjadJOgEGKZG58raWWGbZULAnXW1/CdNuWMmGkZj/aASqxQztuxuCj+1ANgeA MdsWR61umPdG2DMcVyGQW6IP7jTXRB155EbcrEXOAEdYnqKuLhcXmrRudkSE4m0Q/xBjz5m0w34a pvTdHG4Q+VxQ1qly3JyxcDx38eGei7eTIhIVsWNrs6CM/fQ02T1rKK5t61uFaTAxR6mqOHHoRUCP 1am0M7Yr6rppjVjmj8epBGE1cQyC82XXK/D+ruWAAlZo49AefNujk/vSgRMXxQSQ9+rfzdwdYYxe zBu+3FPcBoryde/SihVvJhjG3dCxHDHflJbH46fLq6aJ33tuicFthTQyDPj3tlp/OZk3C8N0FIuN 2q0WZphUQtH4lr2azYRXxsT1BZVqbFzOYHVt3whkEQ7qhHJudbexBM2cYpKW6uOquQ9mRRGMDMP7 Zpbslhh3iGBuad8uhktKOwcfrNDaISZ3wEHKAJmHd90lg/HaRTUoymecS4+q4MPQwdQtwj37DSXX cZVNxdRxeiuhygbRNaSfMqephMx83IiRPmYDAQeFCT9wjSaAK4XNdNonsq57AFDS/LCvPt+9r6x7 Qw+B/YCDH5s0qzSoSL71pSYVyz1m0NkLPubiUHaYSXTLop+76Hmc/Tv82EmkUZe9IWqNkz6YYXky 9i4pCK3/laPozAzadSj/6kEC5fLkTZ5Hy61CTwKoEa34t8FlLRH5R5BrgYZTc9YImUBBM1UxTFY1 oJqMBG7ZmaDXwZT1+TmRmgbWgl5nBvV/lVGtKHqP92fk5BiD9ZdHTi7RjtCQuhURkMeUPnXyFWcX iDvLQDt7qGqnplwYQIg0OnEh3DUsnlHl0xxzHPuMDl8xRZc4FXM51CPB48f5jy2NiJc35FBqmMbN rTTeJuxUulFdV/9/dH3mgtyZvGpufuLg7x/VzoyVXBteXfrsAx2gKWalV+EBfaHvxeFNrMqX2aAK QvFZmBix8bJHP97+YXZPgVZHu4rcVwkylDzjG6m2igh4jNT+uGnIg0OfkDUJ7ogSrWtaN6qo9671 RFLmx+Y1QVqLy1fjXGlDtdKhBUdENucKIkVG7KlZ44wBwD5u43FJrAFBIiY8A5q/VTGqIOaLIRVg RnRgn1GRuP5f6/pzTiKNgtsR2BT0L2zqQGRCHQ2dyyw2CxSg3zQAXg7dVhJ4p7xx9QCtO2sC4uHb tMzzJTzRlQcV+we09BqTtwKu3AxrnyMHkftc+G5mhaA4GQ6cPWs9V03zwWXBZEvVUtrP8WDauGFD KkmTysH6mZR5QCYFPcyZM/cMWC0CnLk1SUwMlZW9/GpFEwuieue8uF3J5mDYMMHmc3HcQPEdFKRS 0Y8T9ecfEkQWrTFSZ7enHpVUQuSVAAQx3QBpgGM14jpbQvJuytTKRnmbPoiqohCzZSEFh4DE1Ezz kZt6b3jA1R6uEXMlouvRSTHIP9CdaAwU61hixm1IXxmrDXnbRQ0KRFJM2LqDGxGPqTLHvzlpFv0E yOsq4JPmtpovmxWs0xjLLIswnwGNrDZtTf7nQwznOerScj7EMDDzp/lxf8SaSiSkwssbgGWHXvI8 WOXGI/JYJHHM/kHqp02TiImYWV9U3kRwDTAk8qf3+kv7aMpbCx3yP8gHpUa2pyMNbHDBo/jLyQVZ KHj7esUXURPfLwEP1GicrsOxKskjMKkysN80ZGgjL35sp9PUbBmL5Gn5v5vsnPb15r4Q76jBsA6+ ZTbzyO0yYsujuQVm967ocbH5j1r7LPtLEZREvarfmnxMxiUfQjeLAJg39FJqfOJLlCoH7Azvj5XN AtjltuSnOxoNSlEadQCx9dMU7axTfRJHpZqYAXG60sgm9HflLKPlt5JPqCZ27oeHlPL0gHyORpCw p4wxRfsrQYpWyb9TuE/E8sDoR9YWPGqxJ+pcXjWdTnpdwI9+Jfj9SOkeuIa6vbUDZhKQvBP8B3+3 jqFWlG4gSrMJgUteo36LcK+bK7nnODLU1+NK3m8WT8VLcHS7oMnUHzwKSKvR7NdA2XBzwEchmMc1 WJfECy3TlOIpXqAe/+R9RVAzYY7k/fuaVJsNxBdm8Df+YgpJ8t52IdlzNgdFqt8R1SG34QdJ2zak AzWazgwsgr2KbLYfjr+CPcQY4i93PeNv9IFGzpTd5WXvkIL55trKUeo8uQqb2nme38gHGCN7kiG5 HMpVwwamk7nNQgT0PDym9wI7JkeyeuO0BnsDMaZwYLaSzdj//EtQoRNUCX6VBMCKzjFnqVNKF7LE Ub455TyDKCTUMvrTY4BzI1e509cSa50+8YvcipKGDVocUliu6AiSepDDxOTJiNPG7nftxKPXD20Z uTzO291pjP4l+FGRfTBusQFxXoqgiFo115is/P+fU2/n96Wvun0YKYSsN/X0oA5tLLdK7Hl8VzQC aTyXWSqMjln9BhDGqhyTH9O1sEyPBq+zkwX7XKYbMjrBjdZAWNuskj1izUdRNoviclQAzV5w6a4J tp4tuxKTMvHJfp5sxxPjR77W0u+UJUawt02QesdYiXlcgiiTRvrjgT0Qpx9bVvqvY8rzBN14JOkO pgpazCLr9tmu9pQkIXon2S3CaVzX1bdEGx3D62Lk9z1YuOaU0BBRa6j5c1Bovtbp57pvBoW74hJ/ tVkdE5VFtQdpVIEbcyjMJRsUXAohcZV2RkVrUOUr6rUjxRsfQg5Mg0TvCX7SoNd9wMoSJgX7jZDw uoUdYiE/5xM/upxhSFCayZc7Tu4mHvHxU2TSwdatHGLYxa/akjW1/GiGA54k55uVZ/w0ovhZ9uJ2 GolyC9iJObs/ZJfbfMQIcJjXK9SeR+Z6ZSLNeTrNRdKx/yZ4xPo7uLPJTSkC6SsWEN38GzPuD2Ne UxwffJz+bY7ktIDdn6FrNB2uIVcSbIu13etWWCfjXh7sPTbZV1VyDxR/fN/6gXC41BbxQca5Z2E6 Aed/IhcVMX+KFaJGEprer0EDmZTtXPYvDm4xu2G+KQGCrCvjkmD65dlv/2m1AuUQ5CxMxUtFU2sG iZNN1hr465uqTZbuEePm6WZgs8S0OXH4GO5gmQrFxtGDM/H9podvRMlVuikPyDf3+2WnyUsMCxQr TCOGudgvFX4zzjFWMeLNbv1ax6AM0DDLEzL1uo0tW/9wiSt9ZdgysoGQHVSqqoLYnKoMVaIrHC3N 9bSN/YfPS6LaI876I5/AFPHZ+A+zSH3nZvTVIkDmgqXs3nWpRGx2o35Fx+NiWvn3tKRRzQMXSflR f2cxxpCGl4FDD+UxyZ+BvidCzXFWECEPw0tyrW61IvGx7j16/E8uGpHXDKckWPOVdpglfjzPxNKG VLiPd0vPynbZ83x7QFEFjwJ5Jl2m7MkJUrglUh4IAvYcUKifTLawidv1QRxjDCqbf6sSHITiDjgs Nfl0kjBjwKDUkGtmMcJDDoJuiZnRTzw4qLgyuiFz0cUANfgB7IhsdoGKu0dMXT3XzNwZXS5seqXP eOBnpqHV1PR1pLaOekaoLeD3jywHiIKaw9pG9SOe1muomXG68hA5aNTYZNtF9uQelNpdXjGH8joo xOztevHdYV//QvtFq/wZSmMTQ09qQ2NsSoMup3ZW87ASBoMrXPPzdceFcotMxzvZWkaXn4LBsxTi L4pAW/sDRTKQ5QIU2GNfgkne+8ZP0aEbgAE4+6gv/rPmPowpCGGlYXAPZAeYvs37vn05G9TYm75y P2RLPTNtCMIgw8ubIWQrwSP6Xks2wx1PDy/2ROaZ8TouTeBjj81Wz73CDUDOCiAMj7bTOK2g1SFf /dwJ0L0EoPoxNmgeSZr4OxMhlkfAWLD6MX84BNU6IjY4Ha4Wt+3/vua4s7f+weSiF9Qa7cN7Iu9x 6cIAzBJKQVQel3PWihl7WADkP8rpEZWwOiZbRTsa4SJpXSTcniQg1Fr6AKMGd71U91kD+nBQWxko N8xwoL6wZpSP+8BHsYoY4hLp+RQXsP+frnAuvVC24WRu2yLeUiStqboiCPwBsGe+TY7RyHnqUqBL rC13//38ejfgLLvYPmEO+nN07S2+PoFWqIJDV87/gLUUMbDI7Mu4x1+Jzjac9ZuabTkWYmrjVMUh wZyJ6EuoUf+srQzzeRMZYdqCo5ehGY1wDgz3OWM/2QMB+K6+KjCK0Xf+R9ygCX0uEzbr86q8kHys jjbGX8aEhgyHLTVE2nG7TB8svSH2SacFK5Dcbt/zDNn0U+clBSGB2kgGnt7QkHbyar8juoR3Pyt1 UX7gZN0ps42PbuxRJrq49TOLFPmK7OQRLGA10BnRb99beG/rZfSkyiZ0AeRhfvJlpssns34Eu/vD 9HzsuiIChuZnK2kiNzJPt6mvQ5Q7mtjg1PJe8F3T+2cUAjfy4sUPhJogd7aYeGR/1rpdk0hb/XEN ceyQm8wJ3HkQlL5qXQ1LSyKKCyZYoR5tCUQZ8QMwJP2+jZjQzvOdKCqyUo/BuxfMiFwX82sao133 OjGKMdxsZ9wvlaOaJ+yZeaFBM+EcaQOl44Tz7kkQsctGMx9EQgeMhvh07XyNiNk3f1JpysCdx5Oo cUJzbqKiCtf/fj+/L/rRxtKogqpDVYVn0hwpC77jY+EivXH0YfN3/9KhVnWiTxKwkVWL176bkven tt4jHDFVNYhRsD5CXSnQ0P+4qoXsUAm1Y+m30xDPnoavxY2Ba4+24AL5j8V0l8TcFKnrn5lc6PCf rp+LBOZ5CxbKLMwVQvRwohxsMjsCKhMWTpox7PmusTT8Grp3oWN4PmjhMtDR3TvXkaeud1pNeTJP BsSiNnGFTw+IwsI54EU2VbVzmOu+faCv7yt+VyhAvyuFLSTdq16Ym1LO1Ve63LECuMshSzrw02Ur 8nEplfKiBoJoUw9YrPgKPsrKfvnbCPMT+3aEwlbH2uNhNik/rd7nYwNQwvosHTWt7Z4yxihUIZv7 E4z2A0Dc19werCGcu99jYmwn1/eV1S94WTzfQ/lT31tCFNL6xzjDY9B7KuZvmo5Yi/SZWKlCfJfj 0ELq1ven1ji3WeFVvGYuezEQ/LkYSvTVHNWRsf7s4dMqWt5oypTAtIXNnB9qIvCqs3XPDPThsF+6 /seWW2B7ByrQLFjBWwWCr8VXjCPR7onI6E+uqCwMcuem61hYgW7F0G4OnIPcCkT1dO7sXZVn5YnK ASsM3Vv/287ggf+h/BIgBrzx2Hm3RbuKswTS+Yz7YCGPjIson+HnK0c3bRHZtRED7m3zDvxHhE1d Kze9RSKGMGzQ/Mry7VVwxsLsEZ3Bz9dBPB/RK/2M6D0gQ6pYZ3wz/RufwTlGAmp0yWGcc6zfMtsx /qs4mFFa2jsFWRJ9Rr7Q630ulm81SeWorWnUxSEhT1ypn8ltu0IsBNEwTBSVuHLmblh2xDbgtdFf XlpWo+tUI1CHKbhyr4jEF74JIYS4BCKLPQIdJxcGsznEmmoKmiy2Tvr0X0V0XuYMLkmk/stZCiv4 BW5JEjejPL05hRK2mHctEvUKB7vENuMx9T08DLlbkVTmzCgLiDDbkpCoX7V/Y79GAuQGXqYcl8Ch U2PpDfNA237D7qtFbwgXRxBXv8dRiaoaGcvqAnmbBOoH424ot7Jchvl+BJ3U41cVphCBaliaICDf 73CSosEs9x9cXsWExQZKWSrGh7rJxuCk8JCxSpRVlNO0g67x9kQLsGnObmxS9AZLnK81CUi+9puI /Ihd7KgW7ZSqEoE3PGS+F7alaBAnJ1CwVjwtmT6/Fac/zxOX6p3eJS/h1hHzBKD2AYgv3PP8L+29 wBHHDxtkr9CiRnofPaOEkxeeOlBNYykflOSCkIer36vUeexCvGjBqEgkcn/WS3E5BjWhaMqz10lS yaZnZH/cIJwEDYfWabt1lCHH7whEzkZ44rvEJybpvChaqqdcZVROchMWsJMp03mL5yh3YAHj87C8 mLjavXggGXSjtwUeoWuSA5kJwL2XUpCQd0wpANFbUqzI+XfCD+pJuilrGUFMpy9MBY3ZXGVZI/zA 28ynBOLgs6A7xMHQJSc6oN6sZ/N5G2AjmR4Uea6C2cKuPuDfZ2S46JdrqoUZ8Zeev1QB5rYf1Md7 CU++0Ku+bfZR39dGjNzyrQeY/R6fv5vSg2KkVOYZT+0JT8vv7ENV23kSHv79scP6Yjao1SVyWT8c jCVw/FtYmqvGXVEUij8zWK6EzJCj7JrNqdH+Xur0fLl3JZ7iCyS4YGbYzD9i3RI0VQMl89n4tdeo IxMr+eWZnNv1cIYe4/FgjlDixnYGDAuZOVURZZQ9x/15EKP9/qccjBYTvv8/L7l0vGLUptPF46fS yLvvD0NEWwdJlVXGC18rLzrWkyTzipGuUAVyp9khHdrEWnbyUx3uWNtn4/QX/dkcHoNKUf/anrLJ dE7Ro2rhBSxeqCTJjEHBnBQgupXo3PUPpEhVF3r8QdIcLb5XzJMHmgC5EfHD5EKtBeEu613u5WJ0 HCCuanPqTJqBzCR/CqCENLUWxnnMlLAfU607k27q0hj5K89x6QLmhw292+jyWo85d/2O+irNT4JN 6xxfIkYDdLvkBX5X6frjf6GVUPKXonIHEqU/BLstvkYXxWZCAU6d26f5aXzmQ/oLd2+lH4qLn3XV tYkDx//zAFyt1on6DnTmGD5tqGDLpX3eL/rN0zqD6WK2WqLTLk/YU63fGZzvTrodzh7CRuGaQUAs dm6p0iJmoQ+E9F1FEe+tBC0/9nwPJwQffnw7Q+60d1DzOaKt3V3+HZi9EyI83U3beSWCSHlxl4dj +9dXRKrRFRpFfgW5/I1JtnQRIfv0SlLWEeu3nhBY6XhNe8Fg+jEmmZoBLB+heNA8wIMZ+ZYWSiJV lF5kSPXZ9qJRc5LZ1VdS/df1pp3wtgk0q1y8enjOhrInJhYc11SSXUS9x0DvDS+z6Qsjtmb916WZ QC1B3+jgtnpKASQC2LL2T8dZHSif2O+7dkTCJN4eICJUlkAeTPcrM3cyzH0d6cRb66HPh5MLksbZ Pbt2FLeMuCU4Iv0i+QuVVn5WNK/w2dcdcIVBA71Wz57J6+ZNoAj8vhTuPv7jaE1K6mY3Tc8GQnGK EKVvHvHLFik2ds1pbbTJWSHbRxMx9ubjF1uULnIsCAANn4C3TvYwFHZS7pemHPStMyXFIni4dUNY D6TWQXREg3Fl7eAfxCCkjXQVrDhg7WPjl5Zkh2Hjk7oBAFxkwXKbozrgnxj26cetCBunc2mwHS2C L9ckTo7mYNCnjO/pGItS7IIIX5QuY/XmAFxFnE6onCgUq3+Gl8JXx8f4Uqk+oFyRo29JRid80p+1 npjXI3Mye59gqx9iIWXNUQrA29lV/M8tySI7dxmc+eD9hNzWgBvqiBx9IXfpm9pylW3pGFQmSq5E BlHDddr6Xg8f1KSBeSso1yb7KW2VQ2k18dzHLsWNYiCyMA/2EmcqROV9x/eDCSndmZ8qHGiakqoF SR+B3OOBWN9NNkmTeOPYy941A3oIZB+j3/5CKEI2up0bCx82YG6wKq1LEfB2ntOmKLLQZKL6pEjB +TfIvSVdWH3Mt3OkAt8vjEwZ9t91Ou7Z/zezyajbDuOpP/Pq7KpQT8+aJyX9ncHUwfl7CI75sWwi bpZbRIndK/AF+ZfFjL0fGXtqRw6saeZRondQ2eKRqfaTOxW7rTPfcbYfEYqBQzQOHZJ4msgwCOXq YT1oMqITvRlfWmTU3d20A+QYHl+HWi/5arIUfJm8lKD96+65AhbOsK4AU5SkdMtd8lhQ9NCaEy4w ASe7MLeS6JPTsU3ukTdKT48a0h9ifjGXd1SNKRW23SvuoYHCIBnEmSHHEPTSO6pdHbtYyNiu0Tvf 9aUbFsmBKx0sZJRccIMdqKmdZvOkZ3i51NqQuaknE3TMyF5LvxZBE5TBXrSKk9pGwdjBXbv2rn10 eBAlFh6XcSmfozk3cltGopzAOp/htoHZYEjfOPlwrGDN4lOJaiNdt3eT4VlRsTkvarSIEL1kSaW/ M9853bKbjj3f1a5WRBYBFNz/O1aWLWeOHFMV/8DDop6klRiLZ/Fw7vz0jxdrmU4Vak1MBmcNEjwP T2hKyDbJDxeq6Uw+5rPf+VKhMvgH8dhzBpzZYQlohQql5RBNNuQRyszpQKMzmXLL6Lvgi44A9pzr lfEHBWC0T9P45ESv3akedaBXD7d+j0za1Sjge9YpXRzs0krvNtZJW+zpBo4hFa2CHY9RMy+pLXxk vsBl1XzyVtQoGnQTxwy4CNxB+xe0tC4TfSuv29DvX/LiT/2tGgFxbm6/CYOWOtVUxGOUUwuLjlRM ZpfYi5n45szbCbKfYrDF2KqafBZ7ot5XPu5jWZjLfP983nFDTrKgjMF4U0Vg9vB4fnylTWyYeT95 RLOhJKAQPmQa+Go8I/TsXAjAalkN8P1ZnxbpcOuAdSiyFnrg5IUoG0DMvrc7lxjGv5hsISowJwHf ZSHSs7UeyKakRBaFUYNXqIV2ymkv6LrjCuRhgxVMe/TX30Nx/tKDEWr33ju5y9hxnp/DI31po2ci r5x8lyHhDLUivHnFKwRHtA7VDlBbA140zpoefKXaSBNsS7jBzR9sKXOZPljA2JjqREVmX43cZit6 sOOSw+1IDxKtZYutnug41HYq3rrJjrtuYZawTChBtitLtAcbv/8dtEIrIWPBDP799ZjmWLCEV17H hKEeAVvDi6ZmJAFtuhxZULVa9nMBKWruX0yAw5FMd59wBpReHlDrkxnVILFMdmXXlIE/cV1KoTNm KKvp6cefwFLCBR3B8seydfrlS4J77/+Jv1oQIzamJA6j1NXw1SylApXCAxJ8v8N465ebHzMkMYw6 z5bcp/qghGo301YF3E6ykGewn+JCXFubTyr06M++VN+iYyQPXFXeJFerdLBvQnFRu0pIwzuhftme jqPPv7R5ltq3q11gOEB4korPwqQcxaMyXFxiUDmBu9EmIqTkffscIK6vtqr+Wgy/bONxr63nFmCg 6+DjlCMcOoQU3IVdTL7TdCy9I3htN0+9jPV7YikwOozJv2AdRVpvo4kNSmPmZDX2+yBTC8GqW2YB wODSrCJWa4DabH3HN95EsFTHwpMbh/7YplcjGlZon60L/jlcmEkhoQkY+Tc2nFdvnDPzCKdIeFiM graDbztKGSx3hfNZdJZhDxTwz0ZNa55Y1cll62b1/PLQBXxYU3YR/Da2XmpjJ/Eo3rivN4b1D2Bk Mk2F/nPpfCRYYO/EbZEp85GqZJXOTnp5lHlEt/B8qD2PEzBNJPyRIJNW6+2Mz8+kH/ZQsE8hH3Mr ZhtaFauYQO1HFEv89rHILCSsMBsaAbPR+jFLm8v6TNU88QarNk9ZpeAlKwsC6fK44HR2IQkVArzT GdFkuIpKCRE50o4Efn5JH0TXPIlo6fd8Y2sg0G2ZbIYA0/yCqBp+Ut0euucaBleuGSiLPy6vkRLt SE0iw/UGXn21yzRcKqN6Da7ihjCyjNdZMxBmn4gNUGzJI8j0oMS5a9VAKGJ0cX0D8uG6lEJfk3fk Vf/kFCMSaCBNC6/g9BllRwR9Nim5cHrofX8s3LDt9XSp0xzL12KdmfjnohUNr+Fy9+bZmyOScbtH bOF2wkPlF7Z710Hi5FNozS17UO3ltCYOQPGTMuOcaKkHOdpOHJUeQPIuHK+HXmpF/0hmpv4Px+a9 dV2SnwCYrAjEnWYwSXgXWgMaYgM6rBwo3niy1MSmqOd8Jz6Z6V3SaKAKZKNGkMPa3KhxxIGpYsj0 jhMJfEwJ7hRvBeUXV6IuKgYDn8/QYHswXi5x7fpEJXE54iEYDVZ6qw7iOewvMg7vb9CObPhAiHqf RhpzKtIx/QphZ2AzKTplEh2k/I+Hvxdtd0wVzy6xXzLMrSgBOY+AcbLMYAWZvTRSlRpWBEl7mjSt D6aTUQpYm4XkKnVU/T5+hslotpq+W4e9l3QuiVaUBls2mK2HJfwCfN0FhGpOS7L7rYMBkeJpNgP/ tnOrLg/U7cu2ZQC0kQcHyrebMZ3/FW1VmpAf8l3zeLm/QRkxZEynNhofJjmke8yCtTrH6TN9LWuF Vz7M9oD8zEtecX7WBebZ4mRsfkvu+5IDpJ1mMxw9JM5Dx83A0qJqJg1zHRVvs4IGUngra2NwA5sn 1Pg2slenWcRDGMCYHr84bWkvaGiAJ4hUX/IaE+OW74PxzyOKZeEgQyWoentfJMGC2efAsmwRN2xp Yiy7aMLg1p3S3Ka+uQLRtSKQvifzVS+GeBiQSf3fSDr1gqsfZxH5Wge8ZuTDizBGX8lDifitYBpd v+kuyZKTATLs4zXTnk6bJr5vXsCK4dV3li8bjsNuBjvQW6yN9xmcYn6bZN4Rg5f+bcGej2FMFibH JH7EjFpDyLdgEN6Vvi1152MBncQ2pzqX8BQfZY1VUHxuxOPU1UEusV9qJpQTszEQHysVqxYp/Ha6 pRcQBJHdOkz/OQd1REJ3XxBCfIn5osCFguqTuhjMTAYcgcYWwTGOKsvtqttDns9RmuQXnFkI1LhA 0JtqLdB1MmocxtKoMwa/gi91+tz06o6SAs2YJhGMy3weNzn8xjF+OxtTLEYWZ0cCUH6lIjilI8p/ iHH0VvXwVrWB5Evj9K0Xh8rkMnhLEdLvJaT7H9YWOS/e1v+vVPyCjPLQfrFoHfvcWxH2NYUnoFPW 5Obtzh6ne73MtMYwsQHuTS/68dq3C/r9MLc5Trynvhos3gD7qn2REsH/GYlx0gps/swZNRirlf12 mcQNMCQVSMnwPl/vY9JMnoJgTIthRWHgRmQeAtlQ+gN1gn6I6jHdixCJLWOY4koL9DdR+ZvxN6Gn 6QdawxlOlDVybsSSoMez/GoRouH9UUlCdVl7IwA7JzXXi9bnFhI5TrblPcP4aGsl00Npnu7seSNd uOhdfwrD8dyyzIVHPmhftfLoLX2a+XdTtwzz3lQNac8bj2cb6w012PZlA5DosbTnARcKRe3C/c4y IbjghMRkZQIZO5CAkbQMogMkLHUkRDyqXq5W9vYi/BpSFZeQ9NxJaiNwm49gb4dfkTDAIZ8qDQfz 7ufv9cHuEkVcuUALtPBYzbkTlHw1UJ7l4ifHQzaPqrF9I0IA+q8Z0q1IYSDdSYNEe3MxZDYoaI62 DLu08mpzLPpxhzcRNyjRehjTbhvDuq+c+QBqLydeRDZoUd1Cs2eXAZWjmAbRPiz6ylXVVMDlHklf HkGbtiMTyEo5EUG7tJ5dOsV7DKmiRqNkuJcBJ5EYB/nWw9+XxdQLTNd2tJN7TgpgUCCvBSVaO1Bp Xk+ASlk5n/QaNgmjpJPXJc5It4iptabxsya3LoPzkfPmekoQ9jlJybCZFG84LzGMEAQTs3HLZ2UH pGd1Sl29ireYafLFRFp61IknocPGc96xaYpRnebKQhyD6Yy/R5nmdUBG8F7HPkRV+m/A1j7Szths ocD9g09R9nsNvxlNDdGKp4anOc0pfY7UCnPY53+ywXalbbQaDR5TRV5zhjY9QQQr13A/wDqtQUIe GlMptR9nVvANVjNm5AE4B19aKlIPHw5VvXy4om3nAAuXJNUMdAHQyi2yfZwFElWtRrdt9hrscQyp 2JBRNCY2dmxdLU8z60qC6Fk6DbcZy3F8XOWqu0tp/Xje4CyP5qYkLAKYygVfgKheSR2y8JivvKfh YR3LawM1i7wtdmNFMruXjQQEBwTlgNoGlph9/xR7g4NCPhHXepSlVuXF41UulvM5yHe68QpxDZLI 3xqWnlXPEyPjp9gKuGnguiTy+V2vFlHYK9H57ppJh/sJYnlB3VgTqR2qBIJwAobLCrxhj/fLG8fH EjJN1oTRfZafDYKaTjkNvdJMiSfeqa6/C4ERHZA3tv6+jGXNOldCTrg9pv/fSrLm2ZjitUhJC74a Gb0KkyMBWbQHfP/BeUCFO7xu4+E6tFjDgqZGyD8oWoQ3zyyOboPuFWsAoIupPFy/Gz2t/eeIV3Xr A73KCCsRcl35/Ugl9++yBU7bPJakBMmSJqe5ioHLM6hk1029kg0Y67cKwMLLtraXmLh5RWGX8B6H H5o7CZ7UZfvHc7shTSlLBpdv4l3xdJcUvPdvBYXxP6v6Zux5dVk+SVto0OWIxNU70w31D6TWne28 iyHZ3lNs21M1VW3OnsDg2KyePJXKscPus76ZKbCLDTZ5e4giJgKJX778ubKX8wzC4/pVOdNWEAb/ 2G97xD4/+3GAKVxPQKwCoF8Cx8RNLOFVe6jshk8SCRfa3KCG39aqgBScv8RocZBB1SrohFXtnJz6 hMsrVJhN58ht+00MEWzZuTQxhm1o2Sveo+ggM2T7WUUjMX3jUgpCAF8Um1jGP1X4FZjrd7gKOylg L6Pe6p7iiwaL8HyzFQZn+zv+dlE9tbzodKXrf8G+7buqDhyqxRzKMT52251rMczjo9SDwKzj28WJ p2O6gB2QlXhL4jWiLNL4ddpFH6RzXVHR7p9+UXBn1lIJu4AYbLp3QwyZPBsEnx1bm+DVwkF/R3HW j/FiRGmlZ41DghV0o7ZfUIHOfXFpTnrw13AZvrx44jl8TN6DYEe/xKFB92BWzyVSQFf0cMrg3m0Z fp7X6wjNIxa9iQIn1L5DOQ7/63Z8DEc4V2WvXNUU0B5y9l/oAuemmUXMZ21cc9fz19DiPtwJ4otD c5Ie7a5CrxRAB5rsSqKQY1t54CCS76ts+UesJYndhLmlrB5xLj8Nush0/XatKbexVa4HqomVxaDr P/FAwedkviGktUKxrMHu48rlf4WJXNz5ZLpQyQ/E4jFEIE28l7pzt8aV5NXiPrc337+qxfmPLU3I Wuf1zJ+BPtoVjbKN7AdzaNsq9KcpLY0Xhz+BybUswKarwuFpNqUwOrwPqz4kBjQSng7FAOT9+W7K czFhgmv0go6eXXXad6WoqX9WadQGrt+0Ggt6Ipp+FpEJZJ9CsgPr/iQyej5VaJ5szdkqIJHXI7uO RrZYGzvE45r4Zaqjg4wEsnF+E8Rioz+QY/xAl7TlcxfCW+roxLsb5k4NI/TX2tW9E842KHYdVXZM kKC6lRm7hyVh12A348Vgi2b1Tl0pD1dnN5vY1JPB8keAyl8qcYK6w+M57t1m1NrZAB1AmcTZS1j4 gwu/95Ox7XiH9eh9gCwc5AgsuDd0YVT8DcgDHpFYU0asp69f8Y9kBp/J66XwLWETo1aLIot5hHaD OUHYFWXlPyxSdoK9kyWadD3m9bQwvIv/ktyebmMQ/kb99rvQitQ+iBJT+DSR2Jwf9rWoJeRlC8Xw zc9FwJ+VbKKIus+og01t7PRsfXVbP4uIowQmoMCyhMR7rKNUkavQPNX+0/b2vQgG7DvXB5L/3qiF kkAgLZAzmgr5us/WHlupurf5aNPiH2Usi8pQ5V67NkWy4KJ2tOfXIhD2wB/Lzl1gbW2fvNecCwvh EdB8o311792ykH+UWm9GBKipTrJpZY/MKk8f84vGq5ye/9e/aBGJOtUJFj6xARM5YDx1t3Syq2sO oehrmsshs2NJlJbGOZ4zqveVKEncWAEemVzGc0/ac/lNW84Vr+wC1aDtU4BMm/r44LQn2KhHfAT7 IXMH/6Mq+VL2vCvaFVVDtySMVQSLzNoBW1k8WWr1h3MNdJ+QlidshFH3lngYccDm9qnQMepU/Yr7 K51f4f1nVFvA+4bO+DzZH7bvXzxAlpctn9Oa2McVZUhUNIx8YzzzCvaGT4kM/pYKCyxOKFVqVKhV nyo8QcgeM/c1waJIg1jYI1miv2XbaGcufk9Ayx9nNUPeOFoQLQQ7OlTWuNYymDYhOPl/q06QWFbZ E5oAhzEweeKhS+PDSd5+5Nm36qsxcdIz5SZaPOxtZGRILdWeSvV8X3d3jsq/DL4t5ul6d4GWV+n7 BrdtmkZxgzylb6wS4leUfpRkJz9OP8oyTMbGeqNI5Lg+qNmOzoFBCZDLcMx3gXa7Vz9CXPJfzM0r IoxiAonZ9rY2rOaXYuKYhz3S36KJ9nq5V0t663+HqLtqTm7C7t4CzFOneJWVziWKugwMLmbmqjG7 pKza7LenCCqQ+9rzQz5bB26rK7NuEx7sIqlgQo9Jy8k0zp9Db5uCAHmLQdzd+nmSHNa/h26Y/k1Q CmsB+OxzzmC+Zruh5t6AWYpU1sM0iczb8LPxVapJXeIzyODoGyDQCexn6eobtsO2+wf405ElSfkj h89q4UONz6RMUeAToqo+M7KM2DviOrG7gtUKsxJbkk4ZpmrJGmY/viXQDnge05L6G2/lHeaqQcFG QLtzrBmMAlal+GPIQMImutPOS/OPCYVplrSk15gQW2RH8HLrSMiOmQBlQYD0VGepWocwJsufPMZi 2jrkrBY8WC72rp1RjfyoHNKAZJjwqSrkyQmrxyZA5MmzdtQc4eIhRsahQUOMPaPe1aue7XoK3ru8 5ad5lwc56NXoIvLrUxlL1MYAq1xkAxkZohS8pjE0j94zokWe3s7SgrVrinAOzQbQy0kULBKaXP/9 xeSMSlKmDues3WMspy+8rGNnw1C95dnOrsNoK4RmKRu/Tkw3dxvkko6pggu5n554yOZPQZ2t2XB3 LAxouSaqoVE4UJRGZ3hxVSpxMpJLAIKhjgaY4riPFvF/U4s5l00NuvFPXGZmpvMp2vChWsY5sHZY /UseZrEnJNIBObKlbzK1BhhY52VVzPo7mtl4v3MTgUCSYHuOiGMGjNMmeXa8bWOH1ofDQv8AN+ub cQEBoARfN+PeAxxtQNxIZPI/sAlcNhtznbcHlYkTlDgpTKHGyeFywKzbAApJw+/IgHB+YwMG+LCN +k5DTw67lOj5vVaUoys7GekwBErqb/3xsC0mJ5pJ7JVF9swtX8KVLqJy/8wukDcmIGW3282CgCe3 QGI7ZuTOzPUksWrFdsjpA+vGIY97+2bSU0JZ8DjzzyBbTmZFsgjHEA1D9BqPL/urcyL8Xs4UsMw1 ARj9TTT9Mh84FuF8DS3RCWTxB/0YvzrlMek637HIOGbxKHJxDyxAx6eDYEmszPUBS/kxVGm8LObU G5ygD00JOLSerenz+TeX6p2rMJEK6qTRbH+oCPDLWBZXWM9ZTlFB+JZ0ccivHbz262XyOA54nNj5 UVKwdJ1g9OUOm55JarOIqS19rMChj9fVYNn48HvhnNO/jJ6cITRzm4MiEtt+69AXh7N0QwiwgAga Fnvwb0/eYvxIvVeDL2cWaquhdlj/dDuaCBG+gSqu5XJrpacetHq36P4N5GGrT3BrGn+zlBPQ6ZUc kiljw/p1sAHBpWpUOD5TjOTgNBT7hhji9cjqht82VeorVjKymdigWjvzNqRztRgzXulvMJRivtzf TeUPIInj+mjENQEBXvsol3mlXoFqxEjSo5kUeTkUCIqKIuAnF+KuekabzvPg6PfzxjTcuI5bUiFE 3QTddNSyfEDrVJ8+vk7/kz/StFg6RHKoxX4MBC/AmQIk2UuY8UovoidREUngrl5VgRdyTkZC/v5f pM07bT9WHFj45AD4irszbTMgK+u1Udmt2G021A3s7DZE9mjpkzNXRD+bb81Y7y/M//eat9O0sCDf CVPh7GzxWWVrokcjm73XquAzuw4h6N1wmpK4VCNdyJphnyJSd7REgoIdwR2bIgPhYZlQxrV+BR8q VIwRl7szoSMaKBWCnC74HH1BDQqbS0waHVFBLYcDSO55FEJBTxJy230nI1bG4NDCs3F8Hrpg5/X/ k4lbVWB2mXqU4xmBqxUUuMTPsIZQ7p2PFmNOaUdI2AqmG17PFi12N+MlpFEp6fPRok+Lie4EYLBo iLwQ7eSXtKbX3IDnYMH8QQD70YSJQEoGPbndC2WnmHWariGmHxbw25vyPoGWOh0y4MJP/f2rHXGj gEtvrYQgQRZV2eLp99nmhjy0OJqHwix80kD/Z1ZSLQMpvFOz+ivB58oTGMHQ5ihsGUA3CS3tYAon eqnxstIaUj1Th8i/k1qnBRFP4eNx3f3vFmSfYpGurx/GpffnTS3PnQB+hGOdk3r7oz4tgdLbfVI7 po8ObNGSaqeGhN1w3wt7+fOk69zNxJEyEfCOzobzMATBxjMcFHb66u7rvM3qKjXIKsoa7DsV16wM 8eU0FNm8SmlgVJfLojaOUV0cuOULDhqMsnTmWZTKGnNzmSoMQ46m8dI3wKKdrwm/+xk2+lwDVVZx W197oOwc8WvILIlAoZyGKakQJWIfUS+uNHAVsTseOrXDAshCJX97/fxrDKc4Kkilv3JU2700Q/J9 zYvILkdr7EIjaMvz7/mhV9gpMqY4mKx1SevLHzT9O2s0JRr6CM9tK56kYdpFsq3/viHIxR/A8rQX g3gBGgxdP/kBqA/vEAkyY0G6T3Q2VZuTtp/BK7KfaAfknUEFH5f7iO7pBdnhoAAN+DiOHqpw5IWq h/xqgdtxrba4ZbbThCSa0c0yzuXCVAkoq3TwELIMW1lRGMY/B/u4nCtvo5661Ge7ippmKVIWfKxp XDK2GaKvEk/S6VkiSnmxhftoSYokRErwtIVS5uCjJm6RssJcgRdT92r1O1gZ8L1GSjJCgTz4kDvD fkPq4/9BaL9l2kQOr7WovBrmxQzn/9MVuqvXBaDER9fy8bRbY3ICxKaF2K+etfTxC8Sc56GwO18b W1AAY9aoN6JUqSFkS7y8kgdV0y4AvFFKXLF6WlpmfXP8Vw5i4hS39PghgEryRJWOVXPN1EuHfXrE Nbye0Iu5EpFnPIL4jva9Wgmq6JnFvNXuufOOvkjaqVaWALU4QOtpRvxPb7L113ZW+6X1+gJ0oySW LII/Tm1+UbTI3zCCMXt7LPP9i7KcM/VCnBgFB4KXyXnhHIyKmwDppgL3HbhHtnyS5b2fnJ+qbakj Xhmn/avH1RN43WVrWFXVxXyOFi1D82jIEPPC3qQ45elVsshRTk/NICpRJP/BeVinxUTfcK7Qkyk1 irDKm09ztYuOillLHDZ5VH0WSZOp3nScHE9RmKtr0uvL/KuIFdtUnBrgJ+a+8CF1YTTlM/tcURTR cxBVd7+fFEJIhHT/t1MOfAY4ax55o39m1a0jKiSQH8W+cMD6l/OB2K/gb5mb5hV4PR1hiEywU1hB F2ayBeqgNp04G61lUsEL7uubGxNail7SnJugynhsbfKsY0Qjn34ChgAjqG0ZXVYo81IcI70pp3kE MUGd1NY2h/c9aYWVvmQbPgdERC2A6c88a9n0BAnZ+S4k9jrBeq1R7vpvLnYgu7BokSV4uEUj8MaS H0djsiEDmAZsKzXKIxGm8T7oWjKpHJw1EHNEEZL+pL0rR8a99tO/Rw1B6HAkMZtA6TgL9KN2nWEe mJNrdiRfKWfxeAL493tMped2+DCKLOPWQHS0YgDzvegbLO20Zu6gXBDfFr3U9fa7MOkCZJ8IknkK 0x/bPManybGizb5+//D4c1gf0yR4+5eU1cqciW5ePgzu+e1xIEiujVDetXJqGQCbgsR/iNwfK/Zb +hP5uEadErfrNjc1+jwSKLiWBCC06NAOjxcZ1i7gZbhuM/r1vGEMSxbCWgYxjgNob5cqqpADctKd RpNV5o1YR8v2wJdXfS89UqJUOxwKbqDAu2coNvmUfvIazZrr8k4tZhJtgKJSHberyG4SymK/L1fd OF71XjdS4x5scVZWJIayhZ/8cGd4c/aAonT8URjjSBtNk7ZfQsVDfby/DlEJD4S5gd4mVGsjP/66 URBXOWgZG/EtY3Gy7f+eWfI4403zJB3SHiaZP7feJeRXAtagzjSBrBJi8SGsrhhlxayRkpHVSm1A QRyazo0ybXJJLWW5A9qJXe4C8BaoqxQLCXZyIx8PGBjCBddLe6f7C9PywH2iu2Jy/vtECo/6sGLv b+1Ehi7rxwWf5aSK9JxPMxuOkxNTp39EqD9KOKrw7oR94M0kR4MnJW/ovZsThICuh8ge+0HX3kME NZu936B0REovlP4cchIqM9M5NnGidpJcR7+SbJI/iadhkJTDz9424/g3vHBMZO18tpKl2XGQvg/+ nJC3rhAg2+lAkyzzK6QtP4uH+dfqfKIPY0S2SGqoUfxu99l+sGPRubE3dlh0m3jgXeb4pI+JPOov BksdOImmK49jolYM6VwONqWTgnwhkzZshIR8MyVia8hC1udKCgdcq4Ql+66xAtQ+PLBULUZehY9q tNIkonEoiLV/6wD8cjBLYTnTMs6mCbCZdTf5KOAKoSex4Y1A3ppnMEZ8cONFwTgMW+8HXB9IME02 nIh2aXP6iOqWKt3gw8Tz0b4h4/Lup4DJqdhPz/HXJiAJg5TjdxktWDplX8mnA681MyoSj5TAo9Ha RufFjjgB2me/aMoSBkyLm/JWy1CZAkbtg0ja+Uj59iaAhyhfRwQMKDEem6EgVUkhNIPzd3R4jdml bptgOjroMwJy7Mt6PyAvbbztrmBXmoWueWNTkF/aNiugxalM1FuGu+/g3Yf4rmgMCEBAKGWjGT+u ptyy62jZUoRzRA8Ofc4e6Z7U8coXiedS/u5vmibtQgb4/A1Nb88GU6OseYuFnE+LW2cszcCW2251 XYzmfIxKak255n919+lbMXBu7kQSwGquxcLfr5woJpsHGr279MNvNKG1NCFAVnprTG/Kc44Cg1iQ DY2h2D2GwTP+kWz7ipyE1vWadc1/lSSlQmaGQxGyVbQwuhnf5Ix2FU0KYzokCI/Qk1VYzaofZfFk Y5TaUbmbO7+vK/vvBxFvQIwMUaI4KcRnG2w7Ofb+RltFR5m2IapiRtaw8NyKuixnfCAfnsj8X1eX YnQ9TWnpT4VJvXq+Y6kI9F5GeSzW34pDvgIIoBxXLQ2CD4PJ5OtojXLSx8XgMg8FbK17ZZRhNHg4 LW3U2vor+SRVEg6Y40a692XRCoKfvExmuhQDKSxake7bgasAaLZPR76D5dBPthS8hWJqhvOmfo45 y8xALMm5/+zQtdpesq3y+n+hlESaNl1+fXdzRLBGfjCxIzzoNL4/tYeFMWJNry9GeoIN7V4ylNCK 6wiEGe93QOQ7WyRIjF6lPV+LuHwV6/v5Ktl48EU/YGV1ajppexUhzIGG1ESynbN4kAmUux16797x LgV5QouFMogskKmvo3iX3Cl1CUwG/nqTmG17Ymgjg7BzhrJvzIiEZx6scUsXHAcxhARs3Se51MtV U6XjRS3e/rVRX8dQFkOzq5e4eofg1ppx4sgXdSS6y3/CS1dMQk8NdC55I175tZEx4vqWVrJaFvas HwWlGO4iNsJJVU90iv0u5hA8MKkyOIdWIBxvgIJoayzXyJLXQWtdLuDVcRIurJ2Fv32KDN4qqnnU yrpLTgk5L0yrWv0vU2wJxog6OcuzbhUCGi1iP1sG0bwhFRW4aWoD8zzaIjevoYAUwEu1oyL6QG4D MkKHgEd87aK7QF0MmEc3OcLStBnBuYuY0hPZvagVR3WPpN2G307WSXnmohQjO3MPj3/mWOOYx/Pl G7bsYYoNan27ON7+WIvbcCSdP3VN3gRcWZqahN0N4he01pd6Dn4G5Pvvk3ZZKHGp/+I6sWeIkmcy z6F9L9PnQ7YVq9seIRMZZ9XCl8qCMGNbL1xfPn+4OrQonq0VyftB0j5Ufg0oNDncC2G7LpiC2BAJ zKhZJsM6Jgyf/H55LmD5qFNEOXhBRL3K1mCFO6KNmDec9xIAfZH98MuQFeIuW2ratqlYWJIjtFwc 8utYQ3xoqGXSd3BKzppQsY4/9J++19xSqRcEx1m6L4kn7UA7/pnGC/Y6pCN52XOT7SB1PihL3l9y fc/IKwKxxfNiq4MDUDwclFk80kg1XO1Ux6QwreD5Qoez1KTRnREOrtg5jF/BACRVE0Ed3ER7NQxN e+iZx9X0qWS1RLD+uxiK8ISHqnX9aHq6DUL5Lzpqd3AwvbISkinzoBUUDutihUL8WmDbrrJmX7aT No/XjGoOgWSkJXJ0IodfDD1NunUe/kz6kzPs89mErPdAJ4Q+wQVoX52GUvJD8Dvh48jJQTKGTMFB ziD3O7k2vtVxnjHH2jd3JzJI27G/Vt//VzHRcwPezQNwNet9z+g3aVB3PXKURlfO8Lve+p9r/Jka R8+h680vdkWkC5KGWXQ67wulfJzzb3hZIIr15v7AHGnbREHuwrmb0O1H+YRTBnyv/HLOjWwYU29a 78+KV7VCoaYFdLdXhmUfZ3kMraSlSXQE09KoQoFBNs+VTJg+r8rx21bPVNnjmQOibW0Tls4yE5ZH VoYLRtu60apq4e4EFtFxbygov5lTRkO8cmhlxwu7dlDeDr+fdm7lhFbMjcJn0Ya6qX/j0KZoo9Jr 40YOytQ32Ke4x1oVMXwb2GtgT64a5pGOVtKSyPOPS7vA+RgJ9Q+Nij/m/QLw09ime6YdXEivqqvA 8RxZfadK3HVZ4aS5Q0m4d7JCxo9cUtmZz+OqdUERkUXTyKCL5muv8a/IKZ5SRMgXIvDAVh5ijvSe SnCnLBP4DhRe/m6AHPCdZDiczGNopzjmqss9DrEVJ7Tw5MqXpTjUUSt0gnrOiTk5SMiuCPjtb6EA Ot9ZqlmHXt3k4NUrWWwH6zGuBtJ8a7gX+f80Xbx71gjHfQpKyJ+ymNEt1UgYwSGV+LrLN5eHvqAP LezXPIpXuYRsbEot5XM/hFVOQ9iZIZTcdV5UEufmdOZTocRUVNDnsQsILTn9NKMQ2sVtltxRLKgS mVT1ontsONy5oqTBnYa1h74JGoJi3QfO/zXYjKGLx21lP6n1I4dJvR0dWMTl26UM72gUn6FTjpcY m5+/ytpPo7DPZhTud5s2YEDS7g/HT/JJ02YBESyMtvoEzPHQeiNyJ8fPuT6QkCLljjwaAf6rdLeX 1rG5O1J6/P/Br3oMFWW+IvIns4/fxYKwDCn9/Cmzeh50dqdXhdZL8qyQE73sm4r3xB73eWjHrPT1 gVIc2r0Cd4uIu4ZyXiDSx9Yyt1ZkkhpgFdaSlFNZmRJt8WZcP51Hn8o0RgqyNhtr9zYjluI/funN 1wes7Z1JUKAkSxq8xznOlIpmYWw9W+0qyhBEOXsGWImfy9Qb2Mn7+1uPz2TH35ncnZUiViwMTzOM 3g4xM9zk8WLEEAOdobSMIf/nffuV+kdeWSEOC448x20ZAA4QGFOsZyOXiwteFjdp7Zjl7B4XwYbl C2CeOagWURBSAxE+S1P7I/P0fwmG/AHfsMMIYdIuhBJZ42Z1ptNd8eBxCB/8H2l0TkW7NONcaLpA 36nbxEpEE1nXxCj/5urJU/7C1QamUQLyB9EX2qkohMyqHck9dRtWDNvUAIL8hfqRpzkcgwqjxvBn FUfwRYFPLNhAAwrfT/J64gtE3ImfUbOtnLogwL9K3bkqfTykSpib5pgLZlFVObzlMMqHmchcScuv My85O/f/YTCD+s73ZytuTGPi7jyYrpOHKXesnP1OO4eiAuOogWH3WPTCnHe2Htybhec1ZFM9RvV9 N6E8pGlXkKCGq3JAECdKHEaa+6fakd9E6miOxdd2z06n4iro0glxYtzel4cHNOh3JlVpm6xlf06Y 60pKEgrjUIMRTu8+obIrqP0eA3yzutE7lr8ogqyFavcoFd2sSZSSeoJiyYdOS9f3laUBMWbirplw 4rz104HibWxH2MnNsfRHQcFBr7afFGpIFpi0fasjRVSAZETS6nLx/rzGXqtE+ovQNISjb2L3Qj3J /xTTMrw3E86fI70QHaAfeqeSaoDiUM+blauK5LHGrOX8mu7i2ZKicJVuz5Rg9gKoZxgh24EDa/uI gvU9NBoDRsu9vCq/CBiVhJPgWstIJUKWsAHAmcmLKCyenDKZrRBjV7fct+cIdVW3e3i0IkKTF4hr LlgA2TXpKOaCdtNnGOlJh33OoSHwqGnd4XowhYbVXioYutmzYPQk+FAUS+GT2IuxcJIC3DsKX92+ CyrjXd2+z2Gafm8MKEaPo3weW4e0Hu7SO8kmYWWEdjErJ8x1LQg9OwkhQAp1A//ZCHAkaKqYc8Ok zzRG7hBqSYYRc9Jz8eAKWNvsK4Qd6QFShphoUT9H+MhceDn+6jBopqkbzuC9eh/pXgYhQUzDExA9 tvkk2A7chC1mzDLEkTo5RI3Oxn9csVoXZGay1lhskPIq9rqP9uR41T8TNA7z2QB2x588Whd/a8Li 95cX4J3tAmL7OlkQik1S3Rqf3r6FoLpPpPEcFenryrzdtSsIfj751uwuZXDU2LDUvei69t6tfw5S CVBpuMkKpu3zShsresSMQJqYV7uzxqkD//HnOqx3durQo7NXftmbX7/K/oEK8WnPu1vJH3uOazqK a+bB+b4fhKXZOuFwNV3nu2UCmKWUvUonvdboTDMpb7nVOmJkOQOEsB2QkMG8GcXykvCIfgESSt62 5Kp2lKD7EcQpGjqym2eB+kM9Nz2vwJTqGiNlKkPH0VdKiKoWvSu0o9wwQNKhBEsoLxQeeEM04ozb R8bWJB5Gj1xPJMIs+oMjt1I5d7BxcaOWLc6/a3P2UjJepEWTqXEqnTCB5sfOHJ44x9Stcl3wQrbV Ep/qVcIQZd5IBvLFJSnNO6AnFJGckxG9/pao4IlWXkf1xyw7TZD5ismMMVceP2O/p7ALJh9bO3Zn 2e2R2mTKvzclHdOtNgit/zFCkH9T/4SShUuFVHPELTlJYaGiuwKfqDZnMdLcvQEfvlbl3vQ+0jqi nayOp2i3DTx0mALW160u3ku/w603u8vL6/KMXJK2Iu9QIAsvIcj5OjY7asYnXBpsNFDh2OJj2teV +NiMb6qBnZqy6bjOdPfukhHYQ4DTz909parqFIicrRz2gZlbRW8+ymyS+gt9w0IN+ropzI/ZcQAY bSNzs7EU8eg4mbrtyQXJ3IPEpxJlMKAjB4/y5PAtMWvpWQdtGr6tLSIYuCAJ9gKIXwsmZdVI+8wN htSqaQO2Lr0wvggtD7Vw+x2hs6OX/A52iEdzTlAbKvFWyJreZk/vTMfPDYHusROiMW9XLtRi8xAF yZDeJy5jlPlGtsdU7mQeN0q2VzYwHWVX1I5Q6Dnb7O3gB3e6aFVEdhB5j9TarXDDXKcpKmkFflUD KYjaPW8S1UF6ID8P/mdtmtCN7hP6zvDKtrxNHlP6dfTPHRgOd9yEMhR26otZocnelJ1h1hCOFLKh ea9zL1v4PNru6IMKH/WVaeTZa3nRr866HI+BDq6ah4/IDxh8pasPAPnIL8SAVcfK980gwvV3hnaC Ex9fNvm1HGUWA+tkzSTH5DPmhp8SE5JwzZCIUv4wbMpjti+WUP38jWOyhScleSkjc3yPCpsOaTV5 uDBMRDaSxHr/OL1187k9ewqn2FZ7wxfE9pFXCUSjZPyCpsgB7PaQnIjsGwLFv8ha5BTUG0/H0cCE 48cXbWLAnISexRzFawvWzfRNApU4Z6p3y4IwoV+gitO/J0Ls14gxz+7z/ynTi+ABS7dlDLMxRwzK azk5HRRCecY/sCfkW7giLZlt/n33RdVfdD4TZNughqlvYxxOIrfU97bNjwS+po6tYCaI7z0ncodn clNAhIlLIvxZL9maYbVvRL7PEMBxeJCmzBJRmpG3xdJ8ym3CUyYIg8LhBZku9PDTY32qrISyaX1C KkWqgYADE5P0/D51AiOFPWvfUAHQqASFzAJLPJPf9svdhjJMiQS9rvPNBk9WqH2zS3Qu7adhvvnT 4dOk6FzC6/u462EU0S3r+RMkXj+EviEMe3LYGALTty1xjlmN5de1P43XEqx7orO5o852PaBlnXk4 7EHeXa7nYrh7m90PYNffNkynnmbyogu7IsS/kQDr5y3jPThP9sqVCiY8Y+ADsAo7UMACh34qGe8M bM3ptTJLUGbISEGvS205ql10oZaC7ER8v89hOtlKw4I3D1tSQinZvzxoTEPbioQxSG9y/Rnihxn1 8ipsSkxStIuifTQV3IJKll7+WNinH0ojrsy2jJq6I6OdTTMGY6r4iphGJ0Fd0h9vHa/rqtnCNDdV w1uqN1Dezd4u/LZagBlkTY9YBdyNmu52ASbdmHD/6Ramv39/MM8MI4nLv+YUIw6hqj9gns51eJYe GIzfv6cUR7ndOVoqNIqHV9mI6cAgPwBmV6tWqnmth+6YASLP6QmxZr8rSh69Px40uAjuU7UQZsrY kxbA3vdAXrKEuNDWlcVjvCTv/jaVZ1GA+3zergYv169esvnU4QiGk87KnFTmB3SJf2F6YudcMml+ yjYW38IZEV/g4gUmesA+7tAmbI3Czec+ofZ6K3cksjt5uzNTJPdM8i0DRlbk8TWefml5BHcf29zx w+1739+jqx6sSB+j4Z9mG4sywvbVgVBNqRFwJdaSo1o7Itm8o4NIZzKcyWS3DQ8z/X3KWHI1GuWH 0viFYpr2MnaG65lzNeUxnu6i7x3Zk/XznwrC0JBOn22Pl5OfWh/pV0QafjT3okZ1+j9IO3eXnEED ATIVzqLZgeelxS93zIstDmudz8zAXMuAOe29KFAFmnVd1YubmoYl/X9XYP6EQcVRJRYp6ua/Q8Fa 2RU5KiG0dZjm9b6QfP7E9D9D81o0Lv7tTYFkGArWh3teEFO+mFpwlN4KUXGsX+dqWZkzSXX11BT9 ixSJMN8R5zwLraTcQq2joUe1RZ8sU8ywap9mjkJjuh+up0Ua4jjOw2naWpWp5GPurvpS5WlGdfEc wdqKQOgIkPc2DVme7VATS1aDDkeoE7MTH7hC6KSZsfyy43dABr9asHiZZ3Uf0KkGaBS1TBr8j0Xa GRmhSkb8uZlxkpgq/kI4b4WsewZI/0ONPWWMHUZRppfE1qQHGQfUEPUylbGosXYLBTlTW6NR1bG4 Osf0tKhFOIoTeP4/E1X4GXkro8vAhGMDqj1XFpCnnaRxDtbhFC74Ioi2bQTtr5Wk/JIhMAGAaB1m BCZ5o7DCDdv8egVnciP7pxZ+Wpg3rThN8PgChtPFJ/BxIFEWhmNjanesHSe+4BmUM3mWNmQv5cOL zU+bdcM0PREzu9HKakwK8FOxsOqKx7orwpn3iYdsYJqc2l74UX8rRZWNxlYWC+cSwFMN3+pjAOsl UZQFxkVotcPIr0tIXjY9XX5b5KJ1g54OmSLIpaO247ggruCh0Nd4NKkwwd+AOBquF2oVWNPVh8HQ eNaL8AKfHlkSiPamG0it9yHKNEr1QRjXGR7Rnhdds1RllJruGFhFIujOksTGbDknm54QxVMfg2ea mjZhflgWy/U4Yjddmqk7lHkxG7ZhapDAT0RB6Q93ABpjq/8iKdpdlHQ8E3IQ31zBWX5Cv07j/kPa jc81J9Z1AnGmZuQN9naShpdEtAMlKcARC7jjsOoy2P/TxSrooD74/we5q/BNgZo/jYV7cmxLjwEk b1I2BqO1s2COcMbrUiq/AxlABUFIARDwTqU1RxDzWPutAy+LmV6W5rAwQ41m1obTK+Wg95UlRvB4 KguuGX7fHkWPY5DjbYAdccEi+VEsy/IgLTfq0E0nLlPpPShdPTqcFcVsNhLf09thrcBbAe7U4qT1 +SUumrRvf+T5opg7z4Yqqs2NtCWbJDHMKj8VU55lAHNaMn5HPXfUVCIPtSMN1sHfk4P7kWzdoiG0 XhfRnUaK3hihVxhfsn9vl0j024a39NW7OkFeC0A6MkbsczgDVYCvESObi29+0mjpoW2i2E0Oncnb eSUIRNShezw6cIpdQNgtJohDrAactPXWWYBMkJuVgRyHOpG5UzapIr9CkEJxd5zrsT2B2JSQGBYn wP6HcZ8OQ8slRPjrRBfUeJtGExAfcVrK76cE6rrmwgaCn2japsinnI/vv+upc8MOcqsT57LcCQa4 NxZN5+jDTlTDj2TU+yI1+4BTimvMgttub3STygnBB3nhWrPeZJQlN4rNIsPp5nX7xIZR/tcjGfM4 xsY3AzbJn4cpM2dltYNs9mWMQv6cnjstERzJRkdEuwkdnpY/3vok17PGSa15s/0M0m2nfMv1a03R n52yoc91aeF5HCe+yaAigLX92t5lh2kfgtZAaq60TBJL8sgAPBQF9QR++JQoZqqwsoL98JC6yOTz sR4wMoA1FQ3XzFPI8Q+cg6kfXk7/kA7bjLjRU7pdInQQki27gf9xbpBrlMM6/2B1gDH6Ls2dCTJm 6LwjZsd79ezWgfBb9nomMMlZtYtKV/tuRB7e9z6UkB+OtKbYWHMmE7XCa0Vg9LfdOOjdVRx/18BN Jhu8/RFctwIEgwtHZMAY4AaY2BawrXtju9POEAZfNNY31ukTDJ+z/1YTYn+Vm+PCxyTZkRSlBEpv Xv8jkBIXZVFCETtp6wZG7RbHMhQ8Qa/52iakXe6UJJGYDXRanq3wDg4Ap8Nw8rRmMMJNt7JPQMF0 +BnRT/iQJzyC86gVoZokGMZPGe0Y8MRJKTD2mCybOArKRUVZPrflMtfEYQ33IxlqhPbRbJp9FRb4 Ft4vB1ARSN62e73XKdi9St/wiH41PEQlMkwJ3TNfjfv9IjDfHlZuc/hr9JvxleGDd6Dtrm0mShPJ Q6LWQ6rkFohDr2kX4/mg+b8+9EAa/zmY10ZYzZvtpCC3ROrGCTg8WVlZakYkJqPSJLAwIHJ/jPYA 4Uj7NX1tXuv9FvxzEg8c9wnGHdhVmVVrhxnE+viaZzZJfPxWggMGlfGg+8S8IAIlGiAyTGIDw+M1 B01Loxanu9o5n95zLEMeY/isjueel1+qQ4zwYdoYFomhK3zTFmwcy9pDxOzrm7tEjoeV9/lGpnPv GWQOTiiBN5JGoB12pCOt/TZO+Vi4ZngykO3V2zdYnQBHdAhAlXYLFPNy+5Eu2Vd76Vma3LTvZ91S qgT49fIjdk8vxan+mIHLtb9RYwc2z2YS2mNerZ/W6f4h9apfJ5ZBFtzbrdGrNJulqGZwGJaQLhJb hTBWZKA9OEhQrQtcmDFyeel6GfrZbMji/q0Wu7mDg9aEXEUB8U2r/neAAkmWAw+5R5djlZ6g+mLs mpD1gz4bouqCGoSV8PcR+BdIF22KrRmxfLvN3fLt6CTeceMNs7eDEWtfGnehPHmDXYgO1Vd+YsQe R3quojnBG8BmwRyOgPqeRyT/RyoLnEHhgrzV4eQgch1eAHAq4HQYHGJDAy71Q9oSLogemdUQ2d2c VrdtsxpMTr26f3Rqtu2ImQk6PQiXX/QKyH+GTA9zCQhvd17XiOhfluVTjTvEnrUtuYbCYY4r06jk s7No33Sgzoea5/ePAIpXkbSPGC6OeHiw+ZYmDRbzCBT3Aty12D4JSFPzenCzQbSBvxfvQbm8R9cA gBFceaijz3qeQrkqVZ/ahoOgDvgHVua9idbYTt+bxdw8y7di75EO31GLKuGogRQ1Hi2PUsOFkUFZ hpsL09t2N4ehRjrsymxA1vqMAnOWT/2W319mAA9VwbfyC2d7l9oRYZMFGi5yNzF5GKy9fzz4X8+w k9wTih4ggsGLdxGAdfWN6duEexcxY9A/ddbgg3FPu8Qk6gUIApTiM3SRz9Hl9q1H8NDffHt3mAXl UF8UB0STAg1XtSyVUif/QDmJ6l2ygkuQcVXJ6XBP62AeABBZYGjt/t83HHM+Np0pW0+SobPMS0UZ qJvRhDQFbW8c5afNmHJNCyPjOGj3TjQzTKmHsDy3qTTKqIUj/uhASHKzttEwaDZPcGu7olHSOoN/ cFRspF5tO6LMgZEvvBDlXLJAHE8nceYIteAISnMXLlbJKO0yoXCPBKFTPuwEw9zOacctInn4I4RE oQRJ8/5WMyxEsZhiFlO6TK/m567O43f7jP70RE37XBukyriEgtNl53/jYOmTxH09TBkA4Gk+2wu+ 1MdnJoRTKpaZfm0wMralCfSqhaS6VSxvxCiZk2GdzAPcHb4iKAbi2bepwmlVI4/BKPjIxm+fhXKJ OWn5VAhH02Ia5ZMrqikCDA465yQZ08CV9DgSvEQyI3Cjthq+mAvA/ck7TamFvhLqjqggSzQOe7ir y6443Da0B99p8fsX1nbNiPY8f65JAFauVL3ivUXnZsWky9lUF30+nVNntGYqlEGs2XXNZsXxCrvw 5zSep3p7qwFf0q0dDgbOOGdlvgxMS6ES3aecfNtZnF6oIWdkgAm271eRy2ZvxaXraMyzgLu5IR7r pERyaIWtt7iGze8ZsDlTzwS3GRAJ9tlrI9/xOWWt5Bp4yNpjw4g3p8udVlp1M3AoxckbiK2Dk4Tt DINXgGGC6CjxnMTnwdTCtMlyYb5E3Zk+8hpjgGVcRJcBqzvMe/R+2VX+J44JRIcM1bhpTQ3B2Ef+ v3mbNmCOSX6yQaYWUP1xp+LB/ov2Zn60K7Tpmi1H1WfuK1p9PpfhN88Fv44gOizfq557ejH62xv2 Rzj7HShZDRB2EWO85NHCpz9wCUk1Tx9RyB1NBC/5QADWYGuMryOcyAwFPK6SFri3A2/L3zW1iFPr 4UAtLc99lJzusy5a2VQ6Jjsw6yIDBDZoGl02whmWwl4qfRac7WBO2jtliLAqnSawJiRECtrFF3cf l25dcd90GvMEkzhjl+XLSdsNlnQue97gNa0WZUSET4wfL9IjFN40YPK9jAzr9Nsk8WCHvsrwr/Y0 dggdkRir5t/Ipxjj77jxxdmI9Ghy8sSXalWmM1/FeRq4ec9lYkuT2lBJwlXW12/BwH8YS98rz7No VE03GscJt91+HMC63QzuQ1+kT+nt5HVaywxOjmrfVV7lBbwcZB+VIb5mNIeTRBDo2fRoU1ing8+l 65NB0NBv+uq1OIpSwA9QhB8GvxSzDYKz1sh7QLLfQZoBBqlWhRBZsV9fVW1iXNm1kg5Dg00s1FOp r+Jp7cMB0gHw0bwo/ZMeBGbRE14W94lIBaCRrVPh3/pg7bVhScsXhW5BEUqDUdrfuzmt+wK7RZsX foXE+f57lLRT9FAU7ih7995uVTHuTezy3iMv02z7t0xSN3JLCclVyUZO2kt6eG0XqrAGp1kXHltK zcGr0xCIsNroVXJGpa70skkaUFnFxcPHES+UOPNJ/kPpVHdXomPvqChV+SSKQ7QxSNiXw0oG7etg ZztrQd5nx5vNlDfEFopHeSgwwrQEjUqLyUaKWBDi5b7F2Rfk09nQwfunqB6Ev1q6hE9lMDcW14PQ N2mUOGJ4FT/gAMcqQjy0rYf/jSuxXNfqjjoKGNiN0gwcAyDaIxJD46hgB3+dLmA2d5vl5Ei0PI8Q rBrlpT3bm/CgkvwtSMwTu6jBuzqeLn6841j5ekEFJOhWEnt6WlZRpbtbzpd7hsxqAqc9yxC0ilmP 72kMdiC8b2E4N6fLxLDmemcfLaD6szRROOl9ugiyJzQ/pEDPoyplzatnhkkvTvWWi7Wsw0mdD5+n Pb4i74LA/rvkjWgoDPRS6/Ycf5WMuLRRtBqtklGDQCsEUV4RPPj628Rd8Dqof7imsPHREqLx4kHm 6gPvW5P/sVldJLBziB0709LxEKxV3NZ+DfNkUl1qSy/yyqjp+x5xSHXLCCg6ZnYyrJRC4M8z84yw 7SkLF2Oe4SCs0sTk5cBuoQCWQZ4xpTnI/qKsuqclaUnxzgIhwn4c2oCaFaRjF5idV0TBDnH7L3Xj b+Xivpu2kkAyndl0elUOxMTNOHZjQcFFyTRxbkY/WUDVlzgqMBjMC1cUOrwqo/EJgl2OefNpITzg oEw5B8P+hkSc3mW5FOTcRh2C/gV+1Oy326RUmEsdBwUXAYx63gw/NCVKRbZpZWeJ9BGdPyy3gUFf ixDojC7F0JP3BzBsmcLf/N/om58K1zq26fWsUzSVaHgyU84izZoLJHzWwnleNZOHKEF61JLsinIM npSIjIn4AReqC8pD+ahLXW7pzWuGV2qar5W8Ski0C6QNSw+MRISZgQA6PjWIPemjf0a/1SVIhTMM Aux9sip24VQlyuVLh5jjhXGdTNqSEUUy/PiNA2xQmIKtNZIpjPBWlgUIoi8SiA0sKjzncIKsnYFo b+8+Eh+WI2k/qYppMCPP8cBKVzBKP6yf6kxFCUqv+NCGhJaNv2DTkYO303u8qRsuq83dcJT0aVH/ Wc6VtnHY3gbKgodvIZ/YsbnmitiffL3Tqex11bAiC+pBK2dbwTo2Nayxdi0K6JE7+D1lyMK5YBZw HA3o5uCaNDY4Hbk3nUesfuzt5+iPASH2VIuqSax61hRSPGYYYPjyVjVLnIa9q2v/4u0dXQN56I1J uEzfDGFw2JIWgnwEh93WqobECMX8BHWLmjY185rX8clornIFZUMW2SOPMef0uYN0LrlhU6Ekeikw s4CZrHPXvGanPCeEnQ3XRv9e+whMlr2dqZbx+bT5wiO/X0Y6B7Gf51Gm7tty8r91hCZx1KAhaRqV ZAXkXhyDhfu9z9+wGFijD1HoZx1ZROnvQpOTi2D9ZfG0RbwntAnoSc2Gj4LTU/qH7dDpRQRND6yf Ll8sz6DScEzf7TKANeHSY+zfeDJyCqxTUmLvIL9DdAOI9eTSJR3D3GyXxEpDY9uCMmxOUA4Ulwgp ecPM5y833esanDL4urF3RBO6XRo6FGlzhCHXGP/3vEGpXEaPiboPQXFADBOXkkw7fyufQ1b1Wxsr iEJh0YfV1SjRvisNZLV0TtaFQt/o7VCaZF+GW63z2ZxNEu+5IqMzlwswJ33KSlOFjB/VFkJvmwI9 TLUqZBoGknuQDEErByQLykYiHIxnA3G9Fu5pEZregq7LPKzvR6Q3+it/6mQ8udoYX7C5EQTa6TPj ESouGihAP1cmdISSfJS7uTVZ3a8acF7m40iqy2mwYcIHbu19fzJDG4n5daIHhh4/IGSVB+qiVpwl OHsJx4JuFy3dZXHTCoHPEIhSyI4JYOuJXpCEpjVO4++sQTUmvXEL+uCUXqQHUxfTwotcDh2Zzwjv UmXvgMk8XYQHAfKmaZQJCxAKiMLIENZq1GcH+tm/iCEpPRHKKHZf2I2lTtL+50nybQjG/OtqPJ2R HGiyDZC1hcnlREFyLIhdOyUPm2L6QEvTg0nvMtb2Gj4BQ1movwnNEDJKEqhNrTTVR07d5qxG9bBB 5ydrIR0nGdE/i7QvfHAcusluSv/Pszi37Bmt+9Xn7PmCoaYA7E+RkeXIYyA/7i+882+7FObC5ZFo /7tXShEa6oIzmyYPtsycIBEnuvSqy8GzA1inzcOK1gHGNPZly7v9+Uv6KMFurxvntdoh/pyD6hC0 0NvmQGlGS+/ATL4bkINoIqP7eK5ocgxY8CbVhi39Zuol1w/i4ygxFJRT+Y4u+SknLMmiegbkJUar E6dQ4l/6wI+MDvp5VQfCh6HZL4OU44ZrKaZEbmpGeP4wz4ZF/lBvGhMp0gSgiotmmUW64HrpJisz OkADuaDR7LD90Ey9bnLBSBnkFnSSjuYLnYM3pi6AyRn41oijaLN8CQi/Fi4CDWzcdaT2hNGH+RII L6WRibdRG4wIr9jViPkyTmdQQ5F01mEtThBJui4TzVpu50ReXzGzVj460/Ik0ZxgTohVY+5lM8gy JRJHOATYiH90tHyvUBL+b/iqOIRyBoDfNxhaXSS9Br5MWEQYfsduglIAAEB7dRZVbyJtxBsMRD6e fI/jH1Dffz3Fn3b12pa4xOa81Pah8pSwYPpWtTcV93kmRpeprw35cY8tV8D3gxvmQ2vIonfJe0m1 7gdqWhth5iTFEDEBtnJy+8RkSCrOgozYF2RbU4KcRAs7ru66B9bsQ7OYGNGX2o8LkL5LkdCdlTq9 FiN39SP5wl1QDuZDxuF4v6VdBNX+tTBYPQ1KqNCod6OUvwdUuheMC0vYhXFGkOuJYEh3L1rWSv0G X0PVfBPsoD/z04t0810KrCNrvjpxiwEGGVLOm6RUNSWdGd5wdgulg/Dc3T0cptlcWpIV9+G08y08 LI9TGsBQaFBx2XoJYmZtya/MrlhhyjiSzA3pChzUvBBZmmOQAh0Lq1VfN7r4DTHMkSAS1r3Wa2RL T/MX50GKuD1gcSaikgFZdMdebHvpoQWDeXsuXinlQkE6MIQjJEkFPQmcuBnYpmcrzHGiXtaB4VMa kGQwLRWTkG/m4mKvCr+vy/pbnjmkqULNR8fJfVMKxGIiYgtN6gW/JMI13EeiL3K1+P+4YAsX7BqT DV9M5oQmeUkQx++H5EE3qxn0P+PxvokqL89OjB+Tf6Slf7IVowFntsibGJ8dWdzPBin1oTKOk4jh G4Nk84R8FDXTxOPKsgXABlCvNMWKPmgUh0p66Tp+QeU2XvSWQOm91hxvLJwFXJuMKtpyiHtdaUzd zMDNsw0HgzreugGk01fT/VakVswOXkkhcBX7O+yBnfClC29qowhp+RGe2Yld2APsalfJqI61dfy6 fO5Ui1R7qk0WucjtVV8+7D6XWF0pCfxUH8FdGIkzKcbg8kr5tHMRNBJi008GqY+6wsCMecgkm7Aq s0IKBL+14cZ7p/1wGF5d8SRSKewjKyDwp2m1EusVGQ7MqJ0QEtnft1a30hlx658hBozkiQELZl6I ABiN9/1McV1opcnvIoBK2fHlbRHfrQYCyAYGJgqHnuPxn73fnVD0v+BFlCmDR8WEe/cbXqVSHxxK 0X5ubt8vuDyoxeCnNrZr3bHB2NzSkKucA+ALKq/6Cjza/vpFqJtt6iBCb65o1K6/6M3NC7PD8yoT gbY+ed2hCZz1HY9hc90V07bHq+rp4uEdkEx55qGVtN/P367YIiOFE7OrA3TXsNFEqq3GEbF0qhfe 5laiWTaXzwbkYmtVV0G0i25LtkdyKZdxvLr/OI4P1v47nXlxC+AgxwmYezeFRZFaAIp+LhKqBHlf lnMx01wUYCAGwrG1tbqEcrbtVBc2sI2hSkBLMQ/qM06XJbMvuAyDT3Wpx3WfiEeWD99l4UAjtANH Hqk5bwj2t9HRcBb/J4J2eSjwFfapXK7GVzJ6dN0DQc+c8XArAL20231VeX1GogtLnD4qlhkS1J/R raLdW7t8v9NPE1N/rugLqJ9iSJecsoR/qupzsfi3Nb+sQws2h/B9pAHj38+nbCCiGbCEwNkLGzlG uJnfwJdDFNSs7Ausne4LOUCbQLRz/skF92dY+VRYniRTeW21DIAc3I/v6KTMM2UqLoqjy7EJAiIy UJXQQsIQwR81crn2GBMuzQpOkTLda7O8b7rdpdiSZRgUBz9RwHtPW2/NPoWmLYUxFSQ7l9bQz22H n+ax/GTfZ2NN65S2BuO/6vwEmIlL706ZHq4zqcfZjWsuEEyPTWLg9h2nkswJ8T1uTlnllYlr+9XN lzIlPdJyeMWVlapFvVUuIHj48+Jt5GucSQNauHUDbXFUvGmHDF1oFF3ssu02d1hXFvXL7RXtc16o qsagyAZyHwrnur8tSrJHLrtQYB6HX1jHU8CiHCqInWRTTsKl6rrUIu+9E/anfqx7fMHAO1+R2CkM 75A3L9m8sCBdmqb+b4hHpIaD0KPjPTxzEc0+2JxTfxIJetg4rp+aTbsamc1HTch1NK3XB6zYOzRs pwURqXklyAOc5uRv5g7/r3Pd/a2MZvo5BDGzG6JTb/dcpaDR/p31FeInFQoYDRC5T9J3oafNRB7S j0Rm7th6GlSQf1V7hrbv0i22SpJ9eK+L3Y0yeJero+oTCJFyBEYzCREfoC77hr+aH5ohsIAJtr1S +P3ZAb9Aubq+2n4+EuxUDX9cnvsLVLreKyS9n6FkI+RgZ8r7yJdP7oTHtQy8mnbVre9whAIfALlT 3hA+CHYQHJQi63Tu2YyB+d6eB70ySYtDFms4NrY+pIHKHnEcmh7Gvf4SLP+gJOLE5rbDA2mFqJ3A YwmeDBJe3Ja1G45bDbr2OguiC/3lUaLcBrR2ZDXWRCIv6/bPXxzjuTL8PNmdF5up+yT/CW43Zb2L 4dJiBmkeQYLtnG8VrTga6O2ImwXUf+T/p6fyapG6TYGMYPAU12cv1RNkxdOot4KdkkLmIYP22QKG kmAqc1HB8DRfN4pSVhbWAyo2eU2XGbjixt1Y9h/CKz5p0su8oq9j4X/3jhmvpVHcBAUsMF0mDieV tYCbZQeTFq/9l9aYBhMQ7MEiHAuCR6Dm0Y+NxqJrl4yLsU/ma9pPGjVQr2Ahu0AH3UwCw0y6Onsi MvUd1sWRd63qp2X8c/gRrn0aiBzMvNCCv3+uU1wS5woBQOEdDXrDT4IQBrwb5TrcGJbyZLzQXFPd FT5+QJ8GuVF6QMe5auWQNJk080fGsZlWNRfX2Bza8FrNjSMSEoKIviRjHgQkZVKFLFjiVhOGiucX gwu/e0hSsUt4GWMjX9b6U0gsT7kGP8B3xAA8ybE9f4OJxq2Gh1Yhpz8a998mQUBKAIExkC9C4vxh CwcJXq0C2FmV0p/Fhqug+irmuIodYok+s8G+a17XyFqNFih14aHOPSE2g3hFiJnJ8+kFWXYr5ciF +iqFJfMrrsZiK60tkR1qKC6GGZYJyjO4IqU+mYPX32c0Q/BrdeGofzA7DnzIpL/Ii3a4OGR3v7DE FpKZJSX+XFyZObc3pSBs4/XqA/UyZf6KpIBNCFE24G/Q4Xeit/g9Fsoh/lcWdnEjDbGQAYClb1gQ 6Ve+OyoKgnWg0MoCfVJk478KGzznzlWuRMNHEvYewlSfpNS4DMRqhCA1VDwX9Pn5vBxEHwJjnxX6 yf3wkcf2Kj7eci7UXYZSdhpH/iPgmcgmpOIG9ELP5O6xMJ20jT/h9yPp37m+I0up9ozUVdrpHcfm laJvu/SLGfpu2zT5INOW/pDm6CC86gNC/cwtoN1aQoHt0KX/WWpUdIhv5ni46BpafkqJ1x9eRWYL 9B1DAYQUvljTFdenHhoOhcmjZHdkYBC8SHQnI+X+Jj+yRlRH6F18p2bi1kqZjqREbtZrqaa5Yx2P nIJAzM2W8leYZNfnB7wDrN7w3q5rUKKw3mzyO86TWbVCbqjdIIe08pvce/iQZUyUzbKHtexRjLkQ GU5KD0VUhodFx2+kngUnrah/AHU0r3O05BGA0edg/fXXAthfYi/17Sbl49oPe3pM9aApyxopkqkW RtSVAwPF514bmnKL6Rs2OQnu3KJ8Segno7UXhaZBoqxeu1dm53K4TsJTJW7N+L3sgpA2IJbRbCih 1AE9s0gG1bZoNbFXC9D7no7AUWAofa+K2DR0gObCHp4WMK0nXQck/syny2ZNErLkJsZ0bZ7aggU/ jsb+VyRyErV2DIatNl9+Gb9oDg5Qp9qSAQ6H/5ugueJCsi72FNrdXDkJ7daWL0p4ZbjcOXis4/Bi OHFBTEX3SgiclPhBVakGLF9yBuuNg3UxCO7iKDW07Y+BzvV+intjNLTi38M1xjju6fjgNJs5tg7s mjAL1eHDtoMl0ek5ebAQWp/lwgdfDwBGotqXuLTM4d7qi1iSNx4xG5xHczDZGaYeZIYx6RRYZBS8 kynD+TSYW6Q/hh+oofb05IX7Kau4qOJn9OPu50As2iCPXJGuCmpCyqmPeJDmtP8WA3VRSC/q8BSt qNP/MzlXPlkY/ZIexl3iYc+HQ94ievtpCMfRIEASgTYh4sDVAGp5QOV3oqUBwjgZHcwUAqIhbVsQ vJZE5GHrK37T5tLwxhwkS+aPkSSp0/Ef4qhVxYlLjqqwRvZqC3MonYYZvFgmpQe5Y4ifMnoni/ZW /leZOWzfHLyP62vKVTJUX8z96+rV9etUHYuT2w6uHlSzSrVmS4pN5uLb7zK1Ky8IYAk6NPlj+RgU xQLWNxi3iO0zVX/os9JCYV+FxpCo4RgBqwBZnPu24Y0T2vyTDiAy4HhVFn/X+Mmcz1tLoiAvVKQf P1iFza2Z1+nA5pzFIKpFLIhAK42aFCDWSzg031W5Cod6KiIXagufIMWtDOV4evUTHGzecYAAhRsY l3jIlX6YUeevZ6gldFgz7UCvJI9mo8xO4ekBRxh7qUBeByDQviLWebxGysd02ievFq8Qk4HTOkQp 0JBEjFxaaBg51DshCYWvvRaykAMrJRSEyJ0b2N3wESdsHYKbaEdhAzAFbMZdRG9U1egRjGBdzcPx OD6gYtzdVXRgaPP6M8aiPLCiKVWbfn8CE0TDRtGMZ7G2smpMbO0piGWYu/in+HH3LpPZ/3xQh9L/ UNKJiPjhBeh0ZdbA2XcC/cCxVO+SwzE18Uye2Sg3wRZoZfx4M8Urv26yhv140IknNCLESO9mmNU0 Us+CBiiOyZSPA5EpHacPdHLGZ9R6XNXoIIVPEsArMPtJH/OFkp+Ya/kvPn1MKiQoK79tERoWkhDR 4BG8WPTFxHPcW0XoPEf/OgX5Qmw2CgT0JCCz5ZTDBy3cLjBj8l8Tzt/VZskPuBtgMxPJk7NP9M7N R/n1jOF7QSZhlGzUvhCnCSbzbJseYrmNgduAgP3KBEe/3YB5CKPi45piRQ786fxDDWgHQ+xGg73U TY4il0r2PHifcD65ZRy/+bD2asTjm5YVcXWhR0D03G8hDqEPtSK161NEgqv/rMzCNwSTmB8zbXqX NX9R+9rn66KTEHBUJBT+3ZUyQqGbryr+0omBR8Kn2hbne9wO6KoE6oSl8i+vMC23rnjwGWcZsYMK JX7mEDJh9tUfVr6KqAKzaLXWEeoNaDAUqmKbsHDYLi0l1ADYQjguDQJ1eBq7qVi19srOpq1NRy9P pMkdDymOeOaAaIqOoesoymZOwo9/P7txX3Usp04r6i3UVCMOmuQ+oSDseTKxM26yJRHTy73R9N2v hkDDnk7GSHSiNshi4N+YomlIqcecKa2X2pTo9n1XeUD6GrUuV6NUT3M9Z9t82ylOfFX0w4O8aFHD FMecj2GTnvhcIgDAiNHJgt3la58VXTLvcoJu+2zEz195ZhfB17fUa+UYdC5cnuhwG7DSVhD735S3 bvTsFEycKf/K2IMtcN9HjhWOw33mGYOEuvFRMTGY3H9K0hLJqnl1k+GjzsWRBzLOS7NL2UL7l8xB ysHRVkc3IRTc5mnfu5JWEE4vo2ebgXLwTF5TcIEgTZUqbx9Tb5+gmR9tHENgEwyGcVgM4+e+xxZR CzScnGyMRceoI0fOf4J16x4WnSfjKjQhzKptV0v0zgXDOvRqOFH/LrjxQK4/qwVo3kFxQJcgB/xq jYyN3QJhGK9EQbYITVXeP/3iCD8tFB+jz4oXTyL1/nUWPSdxi0SFRdxGSBRsPieq9c3TsEl3gfCW J2p1KvEB8UBR6/fNtlvvhunTI1QM5MiKJdw/MpVkzJtcaxR0LNviW90ks7eAmc8SELH+SN2Cbkt1 zmFXOafD85Ojl5bxV5cocB0B+1ZPyPMtt1QS2+inU5q5GhiyHICg4irTbci7pMfFmIxTWpz9sBZJ GRvs99f438yoSiC4eVaEUNwfW5pNo77jK/dpdt7MIhRWkKn5bPvpuDOh5ye3kwM+HWliP2Ux3mgf v2K1jhveaLg5E+ur1yCRFNF/dw6G7cSeS22/P481FplY11WqpD5mnssFRtAVjeFszOGur8cmuS7F DPW1RraeEs6YGwmBVOrNzWCKcF7e4LaDiQPvEkUcXaEAyjucKMGK9uXFa5yljGHAFPY1By+u1vzB 3tSo3Gzg8uYCKkEt/tsg8OILzgpb96U66FUZMFYkLvbwmU2wo8q+q/q7YY7jah95bPvIdjfIgEJK s6vqHN9elIVA7pVnikp3qL4NvjoAKJtAd6W/xTcX5mObEoXly/2qibEsvCZ5OhLNsQCmeSQvycBw WAbBKLVgjZRYU6gUOdXySOeBYRT3+faRf3brKDX+u3d6sJTULEORy7TPu+V9O45OyqQybFIR9MJk W0F0Rc8dXkKJ2OHu/og0+tO1DMomN++i2tU7Bk5vg+dPXZCeo09KPE5d4gNVpqRZQNNeyXLnvCiY Al2pMTY/+LMnU7DY+25wlpwW4WWDZLpTXmnvTA7g7Jt7uFbuRv0CuGUW4r3ar+J1nHJZ5SIX5pwP oXaiGtfh5nWAqoBRrG9aZGTdQr/QiifD0HWjpVNqRnPEaa5c9Hr1FB0Zdp/6ty2vgRdim0IOqHDh TIUi0bgY309dy4KofwGYh4cm5uxelcrVDaXCN5+7YN8psR6eb6zpaVP8iGaduRbFQo9Qgo9OgcwN V1UnEL8TSSP11Zip5zwi6voTbYJPfJkqevHdsR1swUO882QHiDYAYiuwG7ZxOau3jMVqHTIu6Es7 h/kLqs9T9Bu+7Xe4STXDlL+Zq0AbztBp4J3CtdUy4n4/3c1AHLCxJN6AiAx+PDpTKQqw3XQC4K1k 8/gVW0YXEuORl5ZwH+VeW27GtX7XiJHlLSzavU2U2iwKRk076FXim+64prRQu9nNgIEqT/jkZI3S dwxZ4luhqBJs5s028fFXXnxAst0aRrmP3sJqVLivESL5LBIQRIXV7jLhjjwimH8ALq9CwFD79PFk uoa1AMp5Dwu2ih8F9pu7JJPhCOplrAE8YiAVg01cDklsX+wQrqWuQ+MzVHkNUHVBDF6r1Xt0Nbbp AbmMbX5CnVkwRFSaGznZZKaXQmA2OdeJ37DpPoNfEog5kV2yAzdx3DxHLUBmE4y6ilMHCl5VtBes ebnzrhpNgefXcTUoxhpSZINraABtSB8DNVGwA3skyQ3AQGHRq6kSBuZrwBYRx3ViwXsspySs6NEP rzYSsR44JhuIi8TAf5vI/5scKh+gY5ouunfI6dwpiE4XiSEp2Efu7VEGOxkmNoqpbPEsOYVNwj7e X87bu6iXLrjwaq/9KkV8O9ErOtxirBvJwCUhHokiUl1emlgFpjZWWrFOQj0i5/wvtyLzTfWcooxu 0D5QSFd679oc9akDOyK61HC+V6mJRG7NBcVzrf+xHgyNAcTPlXaIqPTmsbHDl/8V6KXCS344tRd8 8Z5nGAc2dHHkAgaxHZ0DVL9UV7ho7fbThJbKYI2D34LSDPdc+xUyLLlOT+KRRb9Rkwp5p5ubdH5e iMJga0Dai4SHOwSjFstzkhqMJBoD464pRQ/3eyP/uwYB+mp5FYzNCXl19EIjywZZk+aGKub1+J74 8GDYDdIMaPN10sWna6LxWaeI6fKUANcE7zv0t6glSMUc+Znrqu3eUhGVFAqQUol4vqD26BAVoZhv XLkMn5uhRr302SknIrL2FZJeIhpIssa0VCbaZ+ChANcyJKilGMsGdNzHe1ZbI5MujSz5wwXnrjMT e4/mAnYcGaJBSDUBoweJ54VprFK7mLwAJvYAVOXi/iqE+tI22LcHEBwz/l/yL1d5452VlMvNkr8f RQC4h1dXioEVFF9RG44/Jcily1VGhu7rb20+u0PdhR0y2QR+7HXKg8psugynvEy3HUPIgy3UgpHg dMLAMlUI8y0WwRjSSBuClXQ+i9PiD/9GCoRiI72p/giWFF0f7JcbPynPG+yRb0bo8tz4lbXA8Gnm xAcqQ3v32f1SZR2jthZ7LQSpWvq4TmEKRnLY8aYCSOsSN8CDCzJpVt0/9IOvLkvc7A55GYcMOnSq FocNJJ2ybqpKrHBUCEDmReifk8XNR4QN0e53YzYhKkQixwJZlKpWNOUMvpSTNmY6DVQvQ4eR7oqR 3mq0DP/s79ldgloYg+8qYhTOq+MqP45QQbof+CApJ9CUQqVL+sDVv4wt2FspWtY6g+1mzsbNMZ7S l+uvf0awIPmXyn36cr5yMAr0Awnwudw9oV5pwWJLHIHW2XHcTLrLNg3wGiIxn8TkjEwi89Q+Cj99 HF4XVFRY2spZvCp7XZbEC8CwITDjmmSrwMfDAQ7p6yQeIZ1UISGjyuUdOlheUZQFsIHO0+heZsf4 7D2S6Dl+Rtrz/Z8a7kUnwarPBfNsGGIpLy64FiHHiMP5mJym1Lq3ggvutbctBRRQgRh7mr7qAcO1 ZjMNGzd56jRu6N4BSkaOK/3E/AuRBk1E4SdjEge5dli/ZXbq0NQaRwtOQPoJH/Fbv5PE1Zz0I7WE CDSwzsT44YmYR0I3d7B9uP6mkLe3KMiEuuyGOprJBMCLxbT+GxGw+LPT/2RuEWfXHSi+/ml91TCK 6j8S243olEx3wRYOxVrPzBUSXP7fcXlw+8W7jOCvMw1ZhwuA0f3WGeGgsm9VyzKFgrweqt2bWWQ4 jEkCz650oM5dGteBXzPXzGoMp+aEdAT6qJjXt+vQ+e2k8j0+PL+Skghjqx5M5MnrWmD+KqLn+GVV /wO1uw7P88dEc2l+rggcApjMgOvoX2ZteR0aNdW5BsUBsNvhQBzC1kq6yPIGpFTgs+VyX+RMUfVA OZK5qpDMpyYUD0uZBWmOj+Whjd8P0k71g4XnMPW3Px0pqOrec+kWOLVBMbxs62K/mMyxs+5WL2pA wE6jPM1CM4PERb9UDs9juDCDVaAnlgnzS0zj6/bsACM8+wdk7r3FT/+F8ZyG70abR2SI8ojH0Avi x1NqJWwjUjPHJYVgnosWyn4G+HUKYBneKd4LM2DLex3q323T/BxbOo9/OYTU7UpcY/nb08m5MzBo p3U9bOWLdpWaNI4fX36Yue4uMFUdE7MAMySM8ahuPRemi40mTNKZTpVzDHNdsqdyN5vwgR0lpWIT 2DqVzLiKGlnjmPt45rM6b/Mn85wALKGjKMRt6MarJZ13eQvZwNd6UJalme4Jtv1BN+RvxTr4q8fB +v91Dej4KVSRVs4qXFdD00fw4+y8dbuYs2D84nEFjygqK38fCE3ZCyY8VbofLZKDpOsL2wPu5HlW y3ZEcRuEsqWhlzjH9dJx3hS87xvws9srZGCWINrLH67F477mgdeHyLFGd2A38bkvbNL5cvdwPY2m 8uX33fWDhqsFNBZzcNF3BXyvgbfoohkx5OK0xO8ZDy/dlKpYM6pC77kkWx01ovLp76kEXfr9PJ9q JruE5myog00l4hGGKnivRGMP4VTsWo6VDiz2okzlcsSE1WhtV5OsbSvh+paN4pdbF9b+sDPLMeLv H3ysnnxUS8PnANY3M2ONnPU4FDg0xqc/mnLLtqUrqg67wfhL7P6M4G2w4lbeqQGNccoiL8NR+sVM YGt5FWOMODFEokbICD22lW3VPGsZE9sLYw05JYWU9QB7lVKn76526tIyUvOW0/hLZWRmyZRARkhg Z6306dZ4mMyI+RKRH+5hiRPIDg0LA2rm+tiPFFfle9jwsV5VhHoVp7sbYeBc1DtCc7cFcNFzx2oJ /kf2mZK0WRPRs09XUUPkXlCzkCBx0JF/ghjTgextcd1N+07OYOXkv1Dae9Zowfxs2E7+20/juZYn /aa1d6jUbN7boV5JnzlfJrDhZscOqIv5OdeGy9AxWNsFDWo+BTe8pICcAy3z4I4Xs0S0PqCdIem4 +LVA6N1kTOSPV5xis5QRSgLJs+2GGtxqTD1QfVXa/be6PWH67uxpX1nIqXBIWQzTYdFkeAcIk0tu whbY+kQ7n1Cv09fqDnHpTUH9IrJdS94tlkNszYWDYsNH6aEgCRQHQW9dFKeYOa6oJcdrFG3Xvlcq GvbYpuW6oS6JhjOR5/mLon9Ol6qORabd6D3+Fj80bq3KcSqVO0axxeeIC0j8aQB9Ct5IgzpzS9Va YwqVomdBbK3D5bdZCjpfrFGXmIB4djabYGG3ny5zZ8oTvG9I9IPYm2CppT5vMrKG/4ZMe4V807P3 FLQiJe1jWOxvCYpwYn8WqkN2PhvyU+yu40rDH8Xdm4aEKR6830/zxE002wC08LHDQJ/u1sw0vpm8 lITLpdAtj/uq7y2p6G95YQV/CA6k3zQJeishnzsXVOAsFA7OdUiSNolWTQRvDHubd140XyI1gnCt mX/NvtKFVeDPYdecyGapqiQnwo9I9FEDlruf4VTrNkrVxhWS8ZZy0MExOsz88MsMPPeY+KRs/41+ PB+VUAMEaXS68iieZhJsIhCnt6wMH/y6XUCzTlexb+edae85CviK2LwfzVzentFZni3IDkdrOTCU 4orsR6yo1rIT+5+SVDZacLHvKwbkWL/kbRhUe5XnpblpCEgcIdFl9GF6WL9DnvFnrRNLkoc9zs/l uDLDnXqvE9G3MjtXrnTMY0qnHth1Ctw/wSwJqy55i6U8MhehfbPFaZiX9jpUgda6i1uHBZ5K/FK/ FfSMueSz2SHfcQncXv7VhTC52JGjggw/3Uraecn4+v+D+cylVbu0D2JikN6Q81ckSIng9wQ/BZCc YUeX4O0JieO6JUO8+7eDT40eM2N6kK+p9iOv+regGrX8Vd51x43rpNDRB4PRsmMQFaw4nfUl38/o R3RR8QH1OCZfIpiIpclsKwaLFQWIdld6gutUUXtDsMD83NSJaFdJ4tcLLvhiXtu+es86/VEdy5Lv QY3Gtz3OoTFaMC3qDKt6rIletDakhgcRQ4kWCWKiKbmseCzyzZYjVJuYjs4A/XDkQcn7irYGBXnj d189CYbLX6ToGYhcK+hW5FWiTX0WNLTxdUJZLB9tF3XM7nA1gOniXXodKrL+fr4KI89tbyzi46pN oMx4vIy+LSVr/fXZ4NmweGKQGeF4qKlvCXEzAtFY18Lcg3Ne/GiJvtAG1CVht5a4JSDa8y1Q/j61 lUwBLaOUOS+BsX/QOnFKa1VuVcdP3vejfi74a8nhkpBUb+omDJzgBb+ZOz44RosE+qHXUNdeInSM l38HC9Fnn1fowXWljoSTyAlKbDvOk95jLGyzx5iVcvFOa8c9wQdh9hyCIUq4Jg6zPVCdYk9gyEBd /Y6RhNVKAuGn+NQZgJ7ugcbM3sM6/9qPm21qKEytW6VfhoySV17rjwToFB3dKD7F0IwEVms3u2Wr qvdokiFYyUEBxOYBhJjh8mOkt8hEv2/amATCEisgOwXFZwyJkgPxydVDUpdu7MzXKAoQweZfOaeA JzE8PXp7GUSV3d1ozq9V8mSOjJsX1QzBxm1zpUffR246+hOjqrbnvE+a+Yf5U/XoTZQKXyn9LuxF xt0gLXi4bLdnGCfKuu1zC0jFqVswtYhmWz5Y7imZIESOouxQVi6HwgFSN+2n1v+lhddt/1OLa/jD hbnmf4DZ1ZyIwqIksqkZB2VdXXvLZgTsLuISbknUj9okSs+xCx4mMgL7u5WvHWD18NgfqmmWKa24 EPes26AEiP8m3l/LxY70IFMf+OWseZv30t8blhutD1PDDfGquZkSAS0mr6zhAJ/AHVe7IEhXHL/J Uxq03tgST5DAsWLP3lW6TFoHMZOPb6ow/wmOYB+f4ra1ybPl8xeyUiUo5YCop40puP+PQfZPX7hE kDObQHEQ6Ep326mIlOaht1Pgju6t585nuUQQMo4gYgg5k2FnNyENKTCTYEaACwsyqYbWHBCO5WVl 9a6GIQgK1lddvKi7phcyYhxJJ/H7CjLishBwrn0vRqQm3D1wXa0kwQyK5YnLpbCjO+vn55ZCAu3M 4Rnh2sDBvrdNwC5gUnES958EcuKobwvD9kCJp7UoCgLOQ0QehlrjrLuuKVGk6Q6G9W5u1pr74z7h 2Nto7jPylodo6ai42oUuWF6dh9ion53NtooAihppLB8jigIuBXr9wvaN8bkhA79cJysnhorGeoxs Psmyav2bTNL+OA+agSuB2WnurnEwQzHdMFLhj8TxZlb7qAj6HYcAihi6wiLmRcuOTpiZCtoxbjB/ A5NBtSWpVJ0Fgm8fb9oZ+byd08+C+icHTRhYTkxPazpxdYvCI6aLfIHsLVdkgkiR5nv22A0sy2bM hTDcdirnHb2BYJfclxINJzkQvcvuDKSbKXutGjq6yAmP9Hnj5VtrjfJNYpMjvrXGUHszKHV/ylNu Lb3iDn+5ISEiaYa8GTqYbAA/c6meZlT+8wzCvqbGz1Q27o6Km6VthOZ4kP9/26zgpFtg2an2yL5q GVt1swZjx7ZGfmZSJFazpWHIv3x0+pHaKXpslU08/Y5tUQvmy+/IjgG28dQF+8V9t9Qiqc+vFCT1 n7oQfaZyEQWd9a6/Jw8haSzzVlwmkl47jMDYeESXZeQu6IUCmfBfMK52ImzoidetfNnmxLnFYMs3 BMdDoKXOtDJnlm0Nakn3JNhRAenZmhXnY8dsuh3fx0FHa5pQB6Zyj1i8d+LFRxTTAK6UQzO8U6q9 L0lBAkynm8VdPPcqgnopL1v2rYGX7ZQlclw9YaarJWC9jRaIrO8BaMdEoCy+WySBxHGBCwuanZ75 kL3MGJ4d2Idv1/MYDp72Mfm5pvPkoy3uI4FxWUmjs3ors7YF+lLkwipTjjVBurPtePwkoUDM/JYN 2ySH7qS0z/IjQRU3iWdKgsjmDSFfpTGeybMGfpbBPtdES1PIZ376nc3j+BYkfWILZpdP0mV43jb7 RAGASsqrpjm+5B9Q+vKYfRzavnLzkBnVmYGdkRdnMR23T/5H4SPAG8xalL3BRfUP7Se0uECq/IFy 7mOeRKThmEENriAnTgN6ZiCG6W1tXQNzzD0BWEAArlGTev34YflEMY0rOhfZAp6W+bhkJwWmIUic XgjG8HeWVV7+iM/x5uvVJX7mBQ6r6tKJiJi5N4NIERKP7nLZJr1sJ7Q+qqtP3qIDJ4DxBVkNvOmW OdkRhzIYnnEcRfFgI5LzdDTXh6MMUEBV/kgxREsTWUVA4ebVv5qlM9DAvIRORICyuK04IywYWqyQ mthOhdyW4L9/rxQkVjCyWijBpQTIiUEw7x4rSYSJbW9MyKu5wHurqbKKgZSuYrWsiZ8xfBlZq/Nj pLEnQo++SpwOjiB34okqI3PqnmZY1OyfW6f6QM1eWMVBOafNn7q2wVKbuHvuWnyXA6bBkwVYu9bB EtU6X51JMB2TcUlJCbxvGPXAV04doBdeaFnC44q1I41mx11opxkl4V5Jvl8qb8EALnRAKHlYrJCT Ene2MXBPKbJWxu7zP1mESnXTnvV+ErltHaLN8X0J82JejPOlKk7jYXtCUEX0r3saveZBu5z2aGtM OSel5OV6rmZAI7J43Mws2lkWFyZRelcGnKxay9VmFxLelzq6VkdWTuWKOVJ6uyq8uj6YKvGRL7tY odOe7e4yJqcF7A2H/cTeFd2Wj6WKsDf5NQn27DLc1UmjhKdynVLpQeq7xbrbplDIO7Jj1J/emPhk Ztk4Ncj18xAAuaR9NkY04AEd/pB9Jpx4+JsIe0aRMUTjMXd4Jf143mbmzH58//W1K3T2O32OUcYk dzLY0BXc94voJ5PrnYZuBgO2b6kX6Jba1yKeMZqrjIUbOMGU3ZTI6Kw444nAXiqxgY8Pp7NgD1OL /DwFEesCAlKPVjjn+XxMXZVN1j0JOHI5KY3Akk+zXjbhy4P5iakd5UNZ3fVxrSgTF6HrIDdH9dmO Nt0CncfxiUx8mT6gM2G1oqk46DFUYlwnPJxoEPv4wh2XiQ+NACO1S0AvKHCAlAIrEa0Cf3gDGxYO rs/3CDEYwwfGEFl2c8bKdS/2bEolwp2K `protect end_protected

gpl-2.0

c164cc8c32966adeecf3e662bdcc3211

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_viv.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block UhVeas6K+zJkxzAJ/XH1tiqQR+XspsoQJ3dEE8+NZ2li/evybvRR2CFFWlkn8VHqMN9rvRtldUOC AgZ6PTRk7A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Rz7+zXWBctYQ/50cGVEG3Toj4CInTVWZ0c4T7rfFyHGo1fa/YgddoAqsvH7qyYwDZcrYpT5hpEmn cFc1YeIlYloc1EaeTJDtWuPiIlcMz2kYk3MBHTzU5MIkyzIkATn2/OxceutmubtSsvRoimZqpVhu 4rHEfrUXr4U61RD2nsM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block X3azlMHeEDySdNGo+NHRLVhUQeoDEhghKhi+IvY2MUX5S5C0HbXWISGVnlCl1zEfsB50hXL1G4OR kOAPftYogI9OPmHAVfLAUKfW3/AebOq0Oykvg4+sU0VD1VoueDHkcct4AijoaqFAjdFhbDGl4pQW DdiL7zN1Q9uXwVQ6Aarj8w0xF1fxyiYw/e32FnfCVuw5GVRfdO2e4Mabu84yq8avdSobdF0oBfoj /oaBxlsYxSoVPNb4cRBubTrF90rAt7/lJgIHxnoLP+3hN36gpW9tkiytunSogmKo44iOBbKcrhIg h2SQQ87sKJeTDGxyazeT+8OJho6YuMPNaQHE6Q== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mbIlGrXZMmPot30Jibhwb5d34uJ2kRrtfyMuP9COPO8/wvMqVlHAjEAFm9kAbyNt+P8a8ltkrgIe noTjfdkgT/jV4xOK8Loi32GdoUncVm/i8mHnDk1HwVDVW4H6PgVoSZZnrIGUYTvd4KkcOFQX/TET wouLW2mJLw5aX4PYJF8= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block TIXqnUNEqWbewR1mPB8N19YGlayBdy6oisZqLFfYkhOvNm8MeNH+aT/Z/okD6Sp1ZlLyCqNZtPj3 uWjaaMopcBv3dk8ixDHEmCttVJVrP2ApTlw2GLb1ZMtfCxABRbJPoBtZH1/84uFe6qY/4MD8eKuL Fa3ZdP8KVYSDqILI+DH8OjyzIboN7OOExrlN08BcCsADH9MiFKnBH/FdCd7IEKuMiGEb3nNqHxCE 6yuvfo2DzFmniZXdPqWuHhYF4mhlrdggna5jpJMAryPY/Z/TAVz/dbVQjoZ6bsFSUDgLnTFwG3cJ osaBYwPy+y+wR3KCwSlWSJGiq8VTTAnzFVzYng== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6464) `protect data_block ZhRasI8C9Aatts4vEtPsrsyLUa65LhrvsNnJxXzv+cC/ClwkHaz6KteqaoVTDdmzNWnynBv2GFKl ZL7uGjJJ0Cj4WDEgwjH3ndlQdc32cdFChvNNel3BiUm0azZK+NeQLtA0kYGoeLdp1rVodH1hJCBp x3Q4hlGIb05r67uPU7Pby/WVtMG9evyOhp7oaSl43CdzrZ9/VwpJ1RqFXF/1jvRk9O/fC8x9fL0j ZeDAGxx0+F10N5Yu/WA/PlO404ib7T8PyvqIlgaxzKNlHtjIZVpFLRM1N42wC/kuBeu+n7IL8rD3 7a7qcF58q7r3WG8vm/ol4KL6QPx1C90vMq5UAprQBxaSPInyYv3BVv7OEgqYkqxcWFu4spXmYpJh yijUUCkDFr4/+8k2xxuKtsRXXIX3ZpSikSpao8nQwXuUYQfy2rUiylY9W+rguzNBYrZgmvUGIpLl PjRLpa0QNSnUXIN0Cwsuuajw0EmYBwHjaER0LDhvHkhkl2FnhNWtacsjQ5iQdjW5w1nrZawuPk+2 nPsmt301/RRy/CaPAaM4xwpvjEWPsf/tMktnVQtAOB00iDcU1TzkwJOsGk9hrpREKXlN6Ks28pqS iO9+VKElpO9IUodHjZd29gShcXvuPBmaPpJwzVh7gjJyxR7tHPx1ctRaeNJCJEnrpFbzTZ9iYNb4 XhwauyWWG21Orjlb432hwyxoD4vGsXQJaGICfaSoN0rDvw1NU/7L8LAIju4zKRy0AYZjpac0NyQh /K3FcyCYX4SLCeh/27eHm/yNm/gVjnRCZeInNiwiMg8sk/7154MgOklmFpdTIf/djEwHTpnVbOI5 BBhcUWdfFcK8Adrd7AJvc3R9uvJawym7ZfMU9R2yvekA47DhT/BX06zduTtpNlG/XLyqDeTd1D5U 9AbkcIk3cJht6dtKYPx0rEHW/f7I7wONOgs9QPcwHDvJuAvYXP3ESPDCCHkoV6RDj7V53QlTyOFB QK2Motz88UH/r0a+Z2SFqaTFP1SbsXf36yY7q6gSDM1WR0uP77dnIC03Bp5hAHn2ZtNkIYZZT/X1 q7aD90F9qNlsWQ17bZ3A8WG7XwMfJv/axZnYFrAvLXHgU1b2fTrNsBT/xqwztN5anjVIgQ/YE6qm XOQfLAV+UjySjvedt+ziSmxECBqyDuy/ahp2KflS8n+cLxlUBoVFmVD/eSQq/u5W9qTAu3wwpvwk JzlI+9zUPShAM3+ssg/G1ZWedq0ZDAKyWHBTUa24Ue+UGIBD4+i1yPLqz77/j+RE5jB4ZLh3gY7P /Ctxjl90kbLd1AEQ5MiRGcQqYeK5IWaXqsVTEAGitUUP8mfxIEtXy/fygtovVtdb+FwSYVeZrOET 61lTHKVW3v0pEcAZVi1qKPioiGkUMdEjga/s8U8E2ShUjBbbH9flb4GHEn0xlpC9zXVgeqgskbF3 jOKagtBcFuXzKAkJsUsN70blg6T9d9E6lnFqzRlEdox6KNIFtRFV0ENsxmSVBdfQXtszUUpPi/fQ 3538EWBNCI1GQMbpViF0JfW/yEKiAaHWZfL/0ugetZ8yBpGpXx2w7Xw4eaX5ePif29VJMbwD1esU 2SHwtANr3Io9Wwaoq2F+qiGe77DU4qMkEgt5oL6tGSq0wtjuPM30a5C5ALrAdo6IkuTn7V4K9tSS UyT4xkfLZZ1BdGidGssrw7iKRuV4c7k5o5rmliHIkHeU3fq0JQFbDWwtPUQ31GdkJJEJmKrLlZDm rcYOt2mYJIKBDEjGTootD8s1MydrGlHtmCS5JqINhVYjUEboHPljWV7QRMkg+RzKHZPAWNgxNCQe TkT02JiGFlfvXs3PCwaplCK4GemRB3jpCOBZNmco9RP9CnuqGKjRGcyd86UjUmcVGNA3pY/ZGUmm 7+olVs74pNYHjkaeOiioHd+EeZpoYjy01Il/Z6j0H6fnz0C9wsc0iLjMpazRZvVbql4G1SA1y4We UZcugkyHXq0RDAqbwwyJ9pDK3ue7Mx3hjY/oaCbS4kmdxRpZS4dV4Ws/b+zEs5bIY95N6fRj6vaM K9J/a1xqUrTiu6cj9cR9khHbSslwtH18xH5Okcpfxx0ZIvJjYzjWpTA9VwE6QNKjjMt2c2l0Hjvk xE/Q3++yz/f6S/VLqe8GVTSfXnrWi3x8kfs9ZVjaP2PgLGs2RNe6Mk9jGFYnPGCYEhXqVOuP9ruH pCraDuZTX4d7o6RIjTYlfsaVWJF3jNxHxTEw+7Gre588p2+Vlmzh0tDa948YkmdoEGAgxTQtCvcd 7FueL671b0717pgQYBhHk62DP1Z5c8rDPzj9Q0qVaHeiwG9a/8wJgw90OoBejYQsuJX1V9AlnzrX fcdLUgd+p03TjA7iyqbdZfMEkjKO5gFiQxolx4oELP2cXfwArxOimRuRd4D959GNArJH3rQXLbVJ Iwq+C0Wo3hit985fwtvXPNm5nVs6ULrPVp0jgozw0sL9evq/EIrOy8Xpw1B6wgbH5k4PWozErNio Uc6a8WEzFqrd6x3feju7eOewEJeUYoY6+SXKV7l1518h/8juH/SlD4RA72Xi/VWAfx7WTSgACcnE lU+F+PMXvCDB0FNMBzjMW6BosbaWL9CHEm5RiFVjA0KUjfK4awPQu2h2YKWqECfpFJiRfr3ItHvV /JWhurYDyeLXIhuDgBP+mtZgtsyGiLmQ64/zNa4Wk/1+Abh6wcekKCYzy0B3+79/LXXwH+X7nXv0 VGljkhyMqvZnAKXeR5y2+OF3h5w7mWeg37fNVKdvh1jUOV+1XC21g1lSScJFHblY+YFrEH8ySPJj BdfBwd1V/4CEOG0oJN4GyRF8NwLtkjfo6OK210adqeAKtuicXPKqMWszSojw7eltNh63We8Ld/zh Mnv6PMa0MHIGUrw1LIJDLzlug6IySF0oucOmcQ7Vc/rhX9BGlNF+4q2VONJQ1hXMr506k9tTW/JZ 9GTbTACbE+8gwWbUcw6Mjqu5r/KOh/XEgtK7RQ2+w1xGiNzaC7O1ecyiAANqUP87kvzZ+lcythwW plfvotcB19cgpPrlnIBZPBkTk9x5Y+oooE8usVmfhj2CUiZmGUQdnO4U+lOEXYjjsjw2Y5RfAsiN O//zUcvTzj9Q/+2oBJ/iroqGJtM49lomPpadchHRQLH8ndPlTUZ9ij7Nevl5o3sQwmzWpS03mhC8 p9UIlMC9rPB2LjVCLChAKI+kx9XuMV7xg7QL7Qh02g+vqkJAKq+VzXWt0koaWRM8iqDA9tJr/ygQ dUUMpLt23KZ7g7klTezttdzhxQcibbO422Nfemrp4E0nDmBz7uk7h731KwLnviMVFOLhsVd72t2B jTh5YxaoJ8r4nXXYFBX14MXD4vcjo79UVSPIPzZa9gavmhfU3pfeuIapv33BVKTmcb5KukPHk377 cHg1UgvqpkyodWEPGsy8fxo858Ipv4xOvQjyU6gdxhE4T5OynQ72NfFzZRjNOMfjzSZQFlKkVwCu J2MtxBcMxwLEEu9PFKV9I0iRndVXmCf1+bjhti6184KihF8o1C1LRvj0QY6UTm3Y5MkxPN3O+Mt1 iVl0YWXA9jrtz5cEG95VP54MwoLCcy8K44yiWzi+T/RPbyYLZQEDsrWeBYUUQS9W9DN9jWJYXuod 6SmX/jLsNt7FKC6J/VosMqK/Rm9Pt95PHhDYlyQFkw7dO2oy+02s5jnjNqPCPHCvxXZ03MJ3o1r/ +WevUmMP12qk3ubIDSe4g6UK6MhoDBM/Ecvkr08o8lQ1KIc7tWafPQCgl1vkX+VBM/guubk/9gep HB+0NkQ2AxhgcgjtyS+NF0H51w06MQzMJ8X1Df/cXDMt/sxt7+G+P5VRRf5T6oAQzac1PN/yS6sS 5ZTHIaEiIsN2a+kofN8VNzNvw3g0IkQOZOvnLizUDD8cvwOFwFP+bqNfuYt4yVoBnHRP3syf1LSq ka3F6XKxiVGuHo/StRzuBoSvQwMjqSMFPW43BTSurCRgdQ5UH8FIwOuOe4RSFlLl6l0wDIlPEwRR 8KyzkDC5hlLsiKdbOlW1TKQdudi+HKEVnEk/G7L6BpBZBtSlkr99WX4hSuYKI5ypRC/4aNU6Pa++ VV9dUngYhBMo8yQEABsuJc8OJdRJpQneffURdr6FvApw/dJU3bYGeFljZ2jUr//867brI8yAvkiL 4ciEwxy7qO4DbMe1f6a1+DoXV/+rYZdfV7LluD2fMi8AcI+Z4SYuCSoG5c8dYaSmc12o4JTcnOBV ZmwPeObPsjc4vQqHAgK0qtySDrUT/gmjs+n47zT/sBNGzOgzu14m4QidF2Kyp1YLzveq/Qi62d9T srgooq6AOBqIkfwfQivW8uXKNTte0bbLbExcx3DzVfOKTlzLxIDVuvvJ59scIeCZ8p1ewA3RUt9w u9wKOzXbhDJqoiiS1Q7HVP9nVuwwtEoZxQX5pIWM1XisBLg+uoB3SgDlI6mEprhwvfAyC066FwQy i1wqoarsqlniZqPEp6e6Q4rnQueaPaZZ3trBDPR/q4gqH1YptgVdrGKNRhIk6fp3XpdW5SWEnghJ 3TEJmEmxAYYd6Hjv4mcIhZtADPxlNYl3EAzXaZVLl5gIkAi3/4Ehx6vCTrF2NldoY3HFb+RS9RPR 4gMLoW6jbbJf65N4/1RxWGGY8EII0J67ojaQ4f1BcYIiaoQPy8PboL6kYrZb4y1fmIoMrJBFK1lF ClDpwjqwuF0eLMc3WsbvgUxZ9OmAgLTEL5JSQVnCFXLoAw0ZOlstIYfCBe3O3sTf1TdfjRhFkIg8 kkAqS8lMeoC4oagyW0jkQ5za3+3wPmKaq5ui2KUUOZjKhE/2b6qgcqQePaj0Uhd9VZpmI7L9CTm1 aCryx+zXcMHyI6sqcbCCsSftrRn1yTuuTLxninT3RLg7X2b34LXzxRi5mtj4kbKIoeFhDIRP0rV9 8d6+c1WN3KQxZruLM08ZasjmpvTLCqpHnjSChuk6MRR5TVDjEpRQeQ43pGfaA60sPCDQbDYx2/nU ZIdfKRs/KO1XcFPPoonEeGSe4+9BfYsAqkLNX8ah5OfHsrV9fwxq7D0mn6lcCykFbN7uCWsG5arY klfDRsO9IZ7+rRkxSTaCM7cyiFgkbXhGtSrMvhATZ0hE2VD61b++zBKiTwf6oHSPBXYHx3AYwOOQ NuxPjKzDN8HnuM/SXi87TFcA286hJDWV93V9AUicwL6oASQ/oOlqy694HXwj3W68XsGNnj1Maaiu 1V2H1ydsr1SizRNt6JlFxe0ogJjcqAEQhPiYzzc4s5HUo2Wyg/Ycx4aBNhGWrTbWyQ71J7eZGMuK KkbBseA2nN5iZ8O0sOLHenx0+JvW1gBUYHdB3fs5N8CWSC6+Rgzr98HS7Py6x0MfLbpd5H+8etKw 8h2BXt96t10BFub8GUeNQX2D20zyTFov41D8hywFsdH46w/UzMgnqrXL8f6ymuUAjtGdfBKE3iRr ztR1f0lbTfOogwWePOs/yYQPeLWGmAkGISlzo55tfinaQ9XBRttz/XggUmljulIApN2sdQRm1nZJ NQmbXO5MouHe/ZrHuYm8GqeDa/fV4s/SWLszVm0xNiOQuHyZ/UTWHCYgv9QSr89bWpLPX2S3xTY2 623QeOG71o4Mk9sMNv5XH5xHoDFCT/XKZSeOXgnHf2G2IIrws+uaKWGCvacHsnNZR4ScgZgX8iuG LijfRcJ0iHC6vC23nEAolYBKWcs4jx6kI4CQIGvhl3OAJyEHSQ5jGD6RtpQN2GiqfTd8Zu0dwIC5 7ROkNuILqFvCRT8zOQ1kWWQVxx1zSSlYzq6DIZLRCXEIkZ/+lV7Z/grWmC1PzZer+RUhHxleeFA3 l59bfmg7oDTFficpF/LKmobQfjYFxUuOq5m1Q1AoMh4fhkJlAS2dIgtTKcm19dsaDY/8v/hIjSqZ 9kHtqOCfAxhNCdUVZ9uHRMNsVicc/Va7yIz/GxGx8ACGO20M3OL3fYLg7uF7xF/mFLlJ/8W1Ghxk kRVkyi3xMBqkpVxz8RamtW36raI+1tPKSN/+ivt9IYH+xCrcdAD2lUMp3HpS0Sj/nTBdg8Y7mbgC Z5HvEaU8mwTgiro/3lactUy2/NzT78GRPQuTHljSoosGBsTnuNa40JgvwC8fE3fbd+AwCVDPhdcB ZEcHyUGkVTg/WWVRVQQuzleOfhmrjEkEu7ejCNiEQf40Bd+Z6nGssl/AHQjbLOfSNX/gkrUtHrQ5 NVZ1VOugs8/PTar864+egdUaMqVwuCY70RpZ2NkzXqoqzmWJu28sqQSZ4iceq/w2+QdA5AgOPlUa i2QrUR2jyFwshUMdU32qu8TWJQgBQh4uyqdAEHrSU1Kg2ukJXSzSfPFP3oenQ+XPdJrFg1NriqzC ZmNM5lMtH8zkgbmIbzmFI0QRzqdbkRxJ1cy+MD2Mtd9Dg27yrlmKdqfKiew4Oz0S66B8vAr0BOIT rS4djKVXBc19CPHfX1X9Ej2KW/dyRzca8mDSI+aeLQI1P9EudHB0z08km3/51wcpVBtRLJbxG4Jq ULb/NPLxt6xFGlgLmVEbJylPBk0qWb0ddT3yRGAEi72YhtlcYh6yqat+tYYfS+oyd8qkxKkQVALg 5ZHYVQqQCq47QpuO+CfkW0Cjp2cGhpMI01qNc8ErzMXSDsh1WaJkmf0WusK0EDyvWKIMsaGdbWqj 2JfDlcQk6fIT+aRXWiVPiiREeo9VyRfTdJ+LBcpAwi6e7QGdUj5c7om+5zRD3NsckaVeInAnUsBp mVtFk7w62Mh8raUb8GlMZ1T/fhL49PrAKS4+tYcw7I3eYnNauCpyxN39yMPmEolcnC8I0OnBRfjm wE/3X4PIddMQV2x8l0UaD4KXIMb+QpSNs4+5Kwxpa+R1ZLUW/2YEkNF2DtxgD6NClNIlewPmacpQ vmQkD432wlWSJ40Da0cPfCvKzx73BMFPOu8WND2D9xyeQbBPowPhEXwTghAm5gKKGO/5xDH1APgw tH5yZpst4ym/TomWoP3YDNvPzMhXLWXAEBK2UMda9wI4Et0bYuREh+Q3u5zd0ikwDmMj62qgGT/e cqS9ZKXDbAblJhak9FglHgyZt5qsn2cQsxR8KodXNEo5TzjkUlKTwNvbeMN9MypqR2aa8XDxghGc 9HPIp3CuBUH/QFul4d/qdflT2qC/gP1LBQ4PoP1y6vurAN0WDSaIeZT4+yPodU0alz7HBgX1nS9Q BEFlbGcLVDOlpevUPB/H8gM7/cdTzqFah3/6NcImE8YwD7SN0OBkbo/JHrgzwMdKMyD9OD1oZYcs uc6saS5IY7yqOeqwuKh3LUfOrN8BmEWMhVr9Is/0ixBYyHRxx9FQJDCu9m4Rz8yQPbPiXM0xSdZ8 vNc9OrKrmlNuRZP+rWdtoZOdAbwSft24JrpFnfMV7DSlT/bdrNlNGeiriKeW7fTCa78BNoRVZcQR 6nvVBQy4cYJz3HkBgojrqBZyduVGd++MIoj1en5zzMBCbfGiQYhmuGn6ZPX/MXUhe7FbUg9O39IJ X//1Pfi0U49hDM71GHq4ucD362hjeQf83qvXanhTBLKoGdnX8hGQlh4Mja6IBTV5ocgk7hvENZ3D mCg9wzM1uTbhC6/ZvbscpPUsyIM/y1U1iN6+FK6pFeXIL6jGQIR0VrN90ASemS73qS6CDrroOaur 7dFNd3+x/kP5W1Uao20nVOfq4OGMd/w+a2vecFpEINh2XNLZJC/yWJOHb+zSsQs9+dJup6RTRwYY ZCkXTFyl1tXTpql2VnsDCzYr69gM/GqBx74Ryn+4WuVxtfIKfeHyNr4xve+Q90VVsB0FY0OchD4I l5Yc6zq1goixX3kEXgI//su9DTGixv6LtXu3fDkavdqyebjsNna4tZxSZY3LxEXrz5KZiMFV6jWg lWlgLe79Uiq2gQXjIbaDeOhwJfP0SVkvbt8oXeAuxuHCV7KZsYs9EubsNzdb8ABfa+aUiT0bD/JD 1QlOguxdu/9aGyBherYleAWEsE2YOD3RDZSA57s/J0cscsgszAUUQ8w0I0f+lPO725sNdoPoEjHq dsmtmspq3An5XSnV2H8UEAyApgI1gAl/CnHBmHdj4HshXQEwV2+NKfvjgzrTqIrBCUKIXsDJzDp7 LMypfG54wdGEfvTqzTgvmT327GT09BKWxWVTOW0y4sBfuXBLA1SKXRsdOYrVdFe67IlBWO0DXs08 hJMY/wpLFCRiO+5k0UUao+b+E5ekolXvGE03c/5WBRgan+8ZKcPtr07AtUHqcUTti35GaqW7HUbo xZwOCaLSHDFe2PuVl8iVq3cGheyRE1KxWXwZBFDLCmXbdf/j2hx/lpzrmVTqIQLyT0seIm7PNHOz zYCWPEwpXs2Aw8BlpaDlFdCPKqNWnN1f64KVaEpGSAJBmpAulxWBp8ULvt/+yfedUxvV7Fsuux/Y nNpHMfnDmLZxAPDIp4VZGJljxSrgW2eqgyeooQyuxXTX7DOx3utt2A9uqemaNGoYFZM3kmoRsBTs yeKu0jXPxSv4bRh9h2VOc09822cTbjPUfoPgHa29OSc7Es4WUMaeYM/5BuIVjZUNd2lt/Xr+8Mq9 aXSCRmMgj7+Yg2LmsbbuGVso51y/VNo= `protect end_protected

gpl-2.0

ea244940b7a41eb250915cc26f781201

keith-epidev/VHDL-lib

top/stereo_radio/ip/xfft/xfft_v9_0/hdl/pipe_blank.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ksoqXXpoADBgea3cNs3hm32MbN+7E2PpkazvHBg3S/blvhmlKCaLNgapz5Djadl75Erlr3L8Vfwz r/53tldjtA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bKOWDQXB8ZisYiNIuBSmYAwm8wBzuGI5IC8dzIC60efyAuxINp7PCEFxp7SVjscYSnzYB/iWKRgE +G+zzVnt6D4x9Lk74L/nvxh1CRWPamV+ib8tTadY2EHS76JKePj22ECQ3D+J3xG0ej5SiYr1BxWt Sh5p5Bmfw6TMgF8iGAg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block se1b2M2l3PTGyoGYwOHkp4+30VlK6wvF3he5myg+jNNSigzzBuSL7vYp5w5XU9kdc5vajWiveG1t xr6KiAicG8qRfq6mcVlQ7v210KdfemcHZICkTdlYqBwsaoqfuGcC+PWSchbA2ZMxR0wrg8Y5why/ ArRqxgKKZa+pwh01f7dtW1XYu4uhTtkVM03+4BWBha7+Q+XZeLhTSe2CgJTAK4UiQvj28AtlWAFE PxLLErra3cijoRv7fbFtSMVP9vVgsL+nZ2v2kGdK37+U+7NUBq+WK1G1iQ6Ww8CHt3sw+132ao1L eF1XcL1aHmVuEKGLbmQ8QvH5x55hm0B1vTe9rw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ttFT8VaaSnEJKmSQc1OJtn/6hEgkLaxHGu4pFMG6Ub8onkAX2BQDKOapyIg1PIfKNCgMbsg5+JIZ sDz4SQuSghT2rjcq1DZ+HaXE6ND4ot8mf5bFr7CFmz+NIAnreytHCP85HJLz5lKbbCtuQM5GtsBC SgEBzP9LXw7ntpCWH8M= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block gHfjyY42hoFMZMpw82ShHP6oHal5ONRMLsGnn3sgkc81uZeonB9Kz8LmLtwE5mA3cBCXH559LdjO +utJEmAYsNpAD8OFSM6SALAarwJRLeKUMStLTnB5/Gg2EQ2X/AxRQttkLnc2xC+aLLnZXBysMHfW RHzLgrbwMAaYecSMqXquPQfa1ktsxLhW1oNFWTsTBPqfAfQ6CkFYjscHl8j2qjbEMvr7tOeCM/oJ +ZYTRPrgo3SR+Tau+lKR5pJDxfD6Dmzd/y2FMgrrB0raaw3a6nyhQC1wIKiKTBQ/dHKV1uBZaz98 3qxatj0xtjJ9A97bg2df2JBKxyqXiCe9r/c/Nw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6592) `protect data_block QI4hYb6uFza+PyrPoSPHQzIDVuwtabXUw1pCxti/SBWDJFHKhT6WYDzPuur6S2qLwBKsSaf3iTlP N/pQ7ijglQwWTfZHoG+YhV2mH1IpwQPPkhOPERj+JlNELhxN0JxjsIvV2PiT0znF5/IOWQ9Wc8gj 7JuGX2VAVEOQiOoybj5APDxLgW7qMYXCGhq0M5KtWxgt5iCfaiejFxxPA0X9/iHGqb5vJls3WMDm DdhSwzdfkFFHCSn8/Fms13Pb0If6UbOHo1jymx7NJ8lVYWT2FQg/bU/HtXUddIoD+BxCs94arTsj 6EhFFm4uoHUCLoN8GTnKmEGVyVYU79ncgg+sv1klJY/4rvXwSj9eGjx3TvI6tHAyuSkCVW9hm/lH XjTUeH3kQldftbAu3umeHAPPHlihIKmh2qV/kg40NFyJdKm6ZBwq5GTR/fZTBgnd66sQt1irkU8/ F2x7BCTaa3sICVdRaWQmEKO0Fae0EzVFSV8p/NxNcjns0AdYN5buhEbsDiq3qNYssYjynwf2Qqy4 jrBHXkyqnk5P9W5w0tHLfF4Zy2cj1j8txIXt6M2IFs8glTcMUkI77gh9/BupLKlgzv42P388A4Rq 90t0uXTKZY+EOmcWMmDNvZ+eV7Twwvbo7RiJgxBUYg507Mb1Gzya0JSF8oIF/n+g6D9jPkmuELPA 1n0hhvigrA+3kwsm/49BmW6ApjP6PM3DInt/UfkyGsPm3XonjqOooj9tN4Qyy47PRbYTS0M9kSPP xuBfNhG0hdmyftCgLHy8LOaW1V56E5gVQrutZDi+C0Q10j9sa29wcD1veJs0Zdr5EobeesheK6jY WMLXBCJy5FVWSJ/ylIVd3lK/JJGmDE4ByQeMmmPIAqBRzqhtmSwZdxlx9FwLdZHZlUHwB0nQgH2C bU3UutzLemG4ZD726kTGjpQgN/5ynP/FAR/xdFNLe7rQohfZC1fZvscPPzwow0E1MYmE67c2v5AJ qvUBWdzPCxk51Ole8bRQNTkCbtSJZfjas2kQqo437rVlHQ3ZA7geLN7vxfk25wA2U4r/CsL9qo/8 0PTb5DLCzA6sQ+jgV1zvF0cRoQlDus4DkGpKsOSOsC+rbacJ9tgjgeb+ufcwRKW3d0eSl5S0+2WM iHUtl2t3h/oIxTnVf/kKKmUPhuMy8gJBDGYNpuhH40IW8KOCCxiYCc4ns0k7ByRWnXZUVCKiCqGs zs3/75gQkk6rWRo/tx3kVWD37Z6eSP2AMe801IIN4T7BMkAb80O2L/snCBO1LIqvHbOg3oGXKqJG adWRDXninm/WBY2MfwW/xiTStM5QA1NPwA5tn5vUYqU4+WRDMPI+R7bKS/LZd3SjiJQdI5kp+hu9 LszAc1Po/Mt1c13WV4JVZuodh9QsLRhumElSbnLuWYlKtbu41uKFzw8qz6GRRPFxq6h1nJn7BDmS cIp5D9Wm6GiU5AqYqEV/ckoza5g8z948lDX9dZDX18ZcJW5KgJTkF6jHO1BsU/gugq9oPkoz0h9P VpmSEuxsRahGl01mPpy9/eEDs0gg6Tr4072nLxMpY95cKmHsw4aowW2B/6RNLk/WvXgTa82/PliQ h6eOj0w3wFbEje1YiENNJptycI3FRLIDinlMlmiRE35D1QPOf05mYSqbH/YHqJGvoY6kBkEmCywe I41ab5k8itES+c8HddamcHp22mAWS2QNsFs48q8Ay/4sfJT0cvXGGYsEgLaENt6Dr6TwGjFscZeM zCtKvscr/7xIZyAA/Dkcy63gYrxKKtNCkX/C3m5crwZEbo98lTBOQI7qavpy+Q+ZtpS8mDur2vTV efoif2ZCIYx44ek3XrC+/4lGpGv369LvmCUN8g7DGwhueRnZtyhMyKqv9Z52a3n5p/d01Wpa1p5T ojgZ7ubJyp8afOJv2PC2f9RE9gyYhBYx/Mo1NDf9d3HioUmSrdqkH5IYwFcy/OWsylI2DJi90fP/ n4TZ3c+8BxNNImbh4r3IIfkcQBDFhnnOXTqs2RCEhLvp9IUWmu+AYRHdmfWiUW58JQwLhDc3wmO1 QvxlOxeitduC5JlKJhvR7Vny0ckXWmMAOUiF4BDpZ4cg/TVrP/0429FhMXyyhucYwIl15VhpYWcR rOcULJ0a38Iauh45w5hwhOtB0co3qZMohMMEx9YWseDTtLtYyAS/27LLb9gaGvmZ7Qm6bcQiTx1F 4h6eOcTQ86l4Ns6lTf38F7xZwatlHm/G/a6Ghh9K/Dez/87wOuk8VrIQw92SGHweOgy8JMLKO/g1 Wu6aYcuvGZHGqG9tvn19Y28joY9P7FbsRH8WtnMQPIaEodgqyByDLZl+JrbG1+6Eni0OIv8sCgJb NRgjbHfClfBs3bTtXRJcwysh5xeQgOBeJx0Htg2qN9VSO48h6EekzbCX5wP9cB/reDQR/ZhZqv4o Z6fOPrxjV2n3Q98wfk18osQhkC4xGURCAyVDBnL3FK3XoDspJd1hnERgdkPNezyKqCooTnNEYhkW IQkq+WV2EWgqN0MBSeOQhcDDfJta3dpr84p+N8uZHpEvMgzg2NgUDoZnLn/wI6DsysEe4gbUhP7q CH1/zdD2K9CsB8v2MvMEzg7TvES1f4vKoIcevdSu+dHUmN7sC+tddeiT0Ms4rmfHBYZk5qq4lMdp vXKZmVzTEF/PSbRhR60YOX0s5WVxilzF8Kb10jxIB1QWsbuPAa2tuED1tTrGlSFvHHiEW8PhS+Ra pCDFXehcWdrpzjJ7cMMkQi4ji53D+XmrqitbdVaGad8y+ay0cc2BQlYE9dae7oij0oZ/i0OIsJZJ wXcDFE+2Xy0a9K7oDPgn0w+VtUNr1JZMB/WVX1DW9YOFcX85HXuus9Tyt8M3DpPac4GS8Rwyc/s+ xc+ofHVY38YqDwTpmiGpSstFEOx3juYsW/HRMmr/LhDWrNKmfSiCjOUlwmXtPPiRhfgXsI5FRSgC zo18pd9KBPCVJasl/bx2fMeQfDd7Fd7XOy6m9B9YVOqpLaIvtOCD6kG9CXxlU7JQsY5iHTI/7b8G +vSw46BWwMDZ7S0nWquhKlK0rk1g2VaicgdPYeP73xZC51iHzuOOVl1T2k3uJjJWF3hgr3z4Toyr wReGJm0B6zZgkuxn9vQjfOguWbUQFE+ql30CXuE4V2vSe2gpcvHeyYB3xL+G5j4WnHdtAhcm/8MP IMs7gZ7P3uBJOUWJCOpzXUXJqbhPOgVVa1Ou40E5l1YpKlZY5fUUGCh89sPtqiGRsC2R3mbrWxgn COYyFUQu8Uigs7HO1wsGi/1TWScje/noMrFJLZID+ecWpAVbFjoV8IaeyH0l6w8QntfOVmdqrkU9 19nP1bJsmsDzmJqo51rRFbw18q737WjgXX99vrit6PS/pp3OqODO+bPgLtCwHt/q6tA39KLw75vR RMSqwTqREJM/K0UKymzuuC/a4kwTDozvKDqXamC7tKTjksixVgfphsTIkB+3YGrxzzfXBqa+/pzt DlWMePCZXwaVcgW9jkzQEEHO+d6R+EXx5WlJul3iltPRl9rq1p200t/+IEUK8P/5/oYrfA+hvGv6 tu4YT8+C6yKIDkbcqMZOooMVjtZPSO2Ik0f1QQPHSM5TUBzP8gUWEfNbde+EktdKtjGy7+/RjBPG C3+eHkv/UzieQJcudDjpRF82a/xLUJkpFSIdUNdZjozosA57J6SGpFLxqAhKNHZhyznuneuDZELo pZ8krg7prSIyUWoyYb7q1WVW52V5mw423d0FJ2WWBoIF7aX1g5p2OxiInrX/zETG4jBcBH5c6YOg qAiC4QSRUpfhrqne788sG1PZL+3BtqmqHN1s6hcXlNM/NqYZ3BDfn7QcayFOMbbx3vdXUF86owe+ k/YYUG4kXRX8NBxJGpVvDSTYwYwaAAe6t/LJQlm1sxewlOKtZhsVSm7HG6QkcSxfNhkDaCXWVi4g D3+EVAu0zRrb3wdjxT1+a8BdW+tHP+rKdS41HFXBwRb5EyPKj2maB4zEUa74IjNCOSH1oMOL0R7B IEtMpAxmw18s5MZnD72ubtvs6m/38WnS0w/L2RwdO8n/uosUEoI7Kw56Binc81iXCHaNtsNFJGEx JkWPiOnnB7NsPGcAu5fYs8Wu6zPEqCgdlU6WqKcFmqCwe/ODJXBuSOeRXWmKGx2vt8VL0nkNai0n mbIBSblRmcnoY9TkpHBC/z5JTO/gJihJoKfyFd1bm0X5guvm8VOn4WSBUtcAn5iTHm1SzC6grt6W dRsa4kO02Ds1FDe1JJr+6+JLhlgARG9WX+V7kWuAVT+NsO6GCX+alpmLaLR1Lwl72RZCcHF3C/Om woBHVz3t0j/NERH74B+xn7ZwZ9r5xa8I50Yw8FkQRaRxCVfM1lvX42+V7zhwe37y2zND0/1KLth7 ZrhLzAZ+cKHLse/HBD5v+kO7IV78pvMbkSkbw+Y42wSgVqhT1Msn3SuUhI7vII7walSiA90+fBVT xItw9ym7BC6r+ZfSb1N+1iv8+lYUyMZzssMpmKpBG0jhlmNxpv/nxPzegSeJ7nc7SmAoJwp7RhKU xJnTEX6fqrPaaAmuQu4k67F9kSOZEMCGNMZLHjWLfgCYHx3dNO/PEi10SlcvcTgc7P9m8IQ9H+qO tY6PfRQIS61rEvptZBH1VRjmGipcSVGhWF3Rjs46ArjPcNxoCevpAa3aCUvk0JUbdt2y930pMZTq 7v1Rrt8Q/6Zz05fmZKsP54wx9yQZMBED0kNbuuSA5GMJ45LA/nKQ3XSUUYUr1PVqEw2U6+/Lilva H3Pg3j2C3b3E+tQLE3pHQl46kozFxkx9NTYOuQxOVszJJjtLqPRQv6R0P4WoLnrrrSSzwDddpEL4 FI5QB6UkodUZYDSXwIfyhRPE1gC/X4u6XV+5L5LApLuXoXe89zvHhxenM5wSbuq5luQGj3c2vTO5 22B8gVrWEenAMy/7I7uJE8Mv0vvtEPIN1z8Vr65hBMa4uC0f6TXCM2ejZIL94ojTiwI455gQHejo QpNOuFDhPaa3La/ibEDQ2JfomL2Tr258oRJKeNXa1lLERP2Gfvn/5punaQNf2mhdVrR+NboiYWE+ XISNNe8OFilv8ewamRwH8FV2Wa0Lq4dw/QQh0IqKNctZNo2nOcnyh5MZtIZRQtABW3jrqAXRmgo5 +ecDwwqfjJtN7zfkoXgO7DQ9QPgVsV/aOJTCpFmnPGZduZ2i/aWrWA95MtaDpGFPryHZq6c/TLq5 U/lMnhby2hZjb/9NqG0iSl2kGOQMSQVQtmatmssto6RCLvka8EoWWSXlPOgdijtZU/kHV9+FkJWr pCDd3UeZ/Yo5aRE2PnLKCwiUUdonRtGRTlAA3CASYouFF7zO8BMMorMti8GROQqtfczRyEt8+2xh YgLS0fDCTa+iBndT3PxDegifp185+MxWOl/ux7FhdW/DpTcSRxtkI4Ba1oemax4MYphB+lPifq7b 6g/Nyi1oN10kRuv/umB9Ym0R7Hb24OYgD/39UlU4y/a2TEB/lpMSd0La49xCUwLvs8UgwBoEO12N O6LCR298XXPpZ6BogRgbj+8x4XVIWDNJGLeWDanJWhfb56drgBM3N6wtUx/OBF7sY038MIMZ/yZ0 SgH6OwL3TjSQh2RNUahwcx7GjjIOulOR1fA/FmcVBF/sBgWtUWztoyyJbd9txmB1CGZTvqxo/Yfy ZkJTnvCHrF6FcOcRpWg/cLCH5TyiWzxm0c57zVUoy5H/sDrmePqjGgh/NxBZxN4AFZ4ZQR25q6Bs gXHV9OMVnXHOg6k3txy6iZhJdFCyVoWeg8BNDryYGy8WjhMNpVmpH4d0pniBl/EZAW1nuNyHtb4p Tk9vWGyFeCvvIgEdpQrfdRxgUuuwCtS/0R+7RTQfTTAZ+S6lftIEDGJrjWsBY06JtObx9GR/+C3t DZLH1DOM+35L5DGMyeVbVGjnfwm/7h/+G4CBlEYB301iv1o1PfD03L1xWTfujgNtuUEEdkMHmViH TdeUK7+rXBssEw2cbeTJiE46EsNsKluEBnG0UDOGtEF7u3G7Nwfuf1qP9xMarRoAX6nW0atKjhxC VzbCgHyjZz76AVVxJsBQ+qQd9RTlWKpEhz8Dg1najApsFeb7LjSAevRupJHuPd0qz9gEUL6N3djy UCVrxVN9Pv8sl3ep6GbyQYc+dBKcK8bSwy0NlNJeVpmqlha0i3wR0JHHaKDWr4FeYaC0GCdD6ufG tGzxCIUvXK0kJe5TKIslYB/U7Ft27WcOrr6lf6vMUEAO7XlqFqchLCwvbfHD1rGOYvvIMf0A9TWx 2EO6R/3xVuIruuT0wg7RxVNqfpftmxwqu+Cuq7qtT8BuKL6pv8eKjKn1hDXuzg/kejd5XBxB8nNO oNhDEmR4//7kSrXd88yh++y3/aIMCSbKcD+DnTktRZwoCPIOFXkPudZXfq7jWlVq2tr0MqWr81e1 k4Mr82QmiZiBcZK9KL6VX1mnPbHMlb7muK4sYvKF2YwYJuY41M5JMbPjdFoHbg29KtM8DsPcc+cb 2vQ55Cn/Le8tLc3F47LzbkUq/boivimjpzpHNT2Ix07k4SwuNregwSeInOUlkimCGBIV5p94IF0a E3bzhY5z9/KYOQB6uF580HAG/9yuJvpiaa1bZU3mYHTNy85pCCptJS0inOupSuIc7vC1/4awveGE S2nVjjOQrHWNaXJduYhqEfCKKCEv9n1NqPPLs6znHWU6iSqSXEo74snJchSzP1NKsZhAck7A045Y pukdkqZrzbLQdRx+j+fytYBqE+3d8UOd2btpBjtcZlLUyzcYOlaMwwZlC4QcQmxqXLmFQZPKDKrB 1WRi+jliPDvnh83x9/CqTKNxGCO8gdpGSZDAHbCMmcRpT+/LAgCxHTY9k4jHR3wI993MRfV9DDW6 S2uc3OCdHdalcJBI/RFHDRutBh+oWijWDoO/+yeCMYJlUuxvklBPBFkwQfiIKkla3j0zXU5BLlb7 ORkvuf6lMZEzfZTWMvdOfzCZNMdNp3PSzbnQzmQlWvXr94MVOO9QR6amwlvHBlAzU1AKn+3oLYvj 6BU/ocD2pk8qIRqIrtXs0yr6iWG+/n0y5A/jnRzLjKPSX5Zt/X6HaTCA/vX8nEoRgTkMGm3821v0 apuLDBX+PbyOIqzv+j4EaPlXIi47svwFXYSHL6Jr+1QcWzfc0EVr0rPjGfTie6TjUrHuFFvp9gKK 0th839AKO2qqXzkUL4DNWn8uR++Ep+Ae5Nzi6WGIDnR1qZ75rYiffugjXV4a3qg7LxwHD37TF6DO 3mEmCdvnSawYXJvkR78t566sXfEesBQ+/MGT1BCSYarRG6uI4UyT1gdTi/WiacmXprUjzF2M/kIs Texb2R1np3w2wicv3cCwmP21vY/tHvs8vRP+Xg7t25GaA+LevCeOccvW9RbY2kEBsNlDQ9sCOkks jiGBvnb3dPEurzc7ORTNe0EAjGD/Oh/ICWRjRE/7TEEPAQo8aa7o+WT4yQwkBM6ifKRANbCkxIzF XP+ij/TPSg6zWlC9ZRsc4B58xHswVaocmYkazSo7TxOr+LuUarzMmHr6xoeNE+NXzdqUl0m2et8w FN6uH3cLJHE36zJ8HowPr2RHLSEqyd7vVDlA9I6LCGPb10q794abOMlXboAvQ8C3H1z6iC7Q9IkY EzF0go3hkIbkBBPI3ZKveEvGPaUOt+q7c3BveCsRjqG/KM99pWDrL4tVhiWqa4obu+WwfevIqymA qxFS0yh3A1+xbzRqPilyByBLK/JeOlm0Z38gUx/TdfYrjQ9cL8Fbi15oSKM7kikTfQDjrH44vlnz 2FZRXIKiQcNabUb+XV3JbTnDuA2wttZFj0yDFIIBRP02qUw2UPi60AAHmxFv5S5IiNGyZ5Zs3Olu bM++puPxF7S5fkZtJFwaHCalaWeT4n1bN1sgLDdGDp1p+PwE1dJb5AbGd2Z/pC0/mNPDulTVZ/zt nBlzl/CF4YKAG6Sz741hEKJLQKT6mLRhSqAtNaKcQSwXktbs5Xx1MmAJ8cqC0DPjFRe1pgAEmcA4 +9ACp06MHmSooOLWCK+AORFResmWqSK0HIhzE2pLmJlGgv6gYh75sjLl7Ih4exIoWvasBMObEO/4 +DByudCpkmupMT8myYB4/PMTuckUU7uBB5hvnEQG81wat0TcYXYwm4f25Gz1Yho+W46iSVXqHczY WRyY9T2QSpi1qaiXH8b77+Jypcuo8SGhyKI0wEa9d6PfmQriyrEs9w++/60kjkzdTVsycUPHveTr XmxTpN1kQ57l7t9qwTD5eKq6vHdil4PYlXUioWldi2P2Kfp3EmBs9NXZkleBdQH1WpAgPAgaZzIT Koe2WVEj6TyNobpWMtftIY55kbhv//f80fmeKkGBBQeLb7EoDhuEJEzwq9VOA9fCnHcDgDZZPvhm eCNmrnXUD0b87d5Kr6ShDb5dSaF69Hw6b2B4fXhelg77ywWKXQTJGy3s3YIfGVLIkY1ETsH30JF4 CrijEbJU7d2oMf26BCz+E5lvZz2kOUUG6eBqrIs1rLISDBEVn/TnW/KGVM01wcNc+ObaoBvqo4To qK+9D3dfBNFq1K5dGWZlQnHvYyYl+B7AlvULy4T4/qmITEcPrHZB/KjikKow3LogPZIE0XtfRGzv 1f8d0OyxaM1zBwj47bV2kku6PuX/DKCunIeGp9BgJPnjvYX6ZDrsYGL3npbqYZbi80EVexH9/Od9 pSwBzwfTNhv6UH5AW2kxkxJXOLMBAY3mXY16feheZPwF2kLWpw== `protect end_protected

gpl-2.0

97f2268214a5b67cae5a68ba9a61b458

r2t2sdr/r2t2

fpga/modules/r2t2/dac/dac.vhdl

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.NUMERIC_STD.all; LIBRARY unisim; USE unisim.vcomponents.all; ENTITY radio_dac_if IS PORT( DCLKIO : IN std_logic; S_AXIS_DAC_A_tdata : IN std_logic_vector (15 DOWNTO 0); S_AXIS_DAC_A_tvalid : IN std_logic; S_AXIS_DAC_B_tdata : IN std_logic_vector (15 DOWNTO 0); S_AXIS_DAC_B_tvalid : IN std_logic; clk : IN std_logic; resetn : IN std_logic; clk_ioctrl_200MHz : IN std_logic; DB : OUT std_logic_vector (13 DOWNTO 0) ); END ENTITY radio_dac_if; ARCHITECTURE struct OF radio_dac_if IS SIGNAL dac_clk : std_logic; SIGNAL data_I : std_logic_vector(13 DOWNTO 0); SIGNAL data_Q : std_logic_vector(13 DOWNTO 0); -- Component Declarations COMPONENT IDELAYCTRL PORT ( REFCLK : IN std_ulogic; RST : IN std_ulogic; RDY : OUT std_ulogic ); END COMPONENT IDELAYCTRL; COMPONENT IDELAYE2 GENERIC ( CINVCTRL_SEL : string := "FALSE"; DELAY_SRC : string := "IDATAIN"; HIGH_PERFORMANCE_MODE : string := "FALSE"; IDELAY_TYPE : string := "FIXED"; IDELAY_VALUE : integer := 0; PIPE_SEL : string := "FALSE"; REFCLK_FREQUENCY : real := 200.0; SIGNAL_PATTERN : string := "DATA" ); PORT ( C : IN std_ulogic; CE : IN std_ulogic; CINVCTRL : IN std_ulogic; CNTVALUEIN : IN std_logic_vector (4 DOWNTO 0); DATAIN : IN std_ulogic; IDATAIN : IN std_ulogic; INC : IN std_ulogic; LD : IN std_ulogic; LDPIPEEN : IN std_ulogic; REGRST : IN std_ulogic; CNTVALUEOUT : OUT std_logic_vector (4 DOWNTO 0); DATAOUT : OUT std_ulogic ); END COMPONENT IDELAYE2; COMPONENT BUFR GENERIC ( BUFR_DIVIDE : string := "BYPASS"; SIM_DEVICE : string := "VIRTEX4" ); PORT ( CE : IN std_ulogic; CLR : IN std_ulogic; I : IN std_ulogic; O : OUT std_ulogic ); END COMPONENT BUFR; COMPONENT ODDR GENERIC ( DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; INIT : bit := '0'; SRTYPE : string := "SYNC" ); PORT ( C : IN std_ulogic; CE : IN std_ulogic; D1 : IN std_ulogic; D2 : IN std_ulogic; R : IN std_ulogic := 'L'; S : IN std_ulogic := 'L'; Q : OUT std_ulogic ); END COMPONENT ODDR; BEGIN dac_clk_delay : IDELAYE2 GENERIC MAP ( CINVCTRL_SEL => "FALSE", DELAY_SRC => "IDATAIN", HIGH_PERFORMANCE_MODE => "FALSE", IDELAY_TYPE => "FIXED", IDELAY_VALUE => 10, -- 25: 125MHz -> 8ns/4/78ps PIPE_SEL => "FALSE", REFCLK_FREQUENCY => 200.0, SIGNAL_PATTERN => "CLOCK" ) PORT MAP ( CNTVALUEOUT => OPEN, DATAOUT => dac_clk, C => '0', CE => '0', CINVCTRL => '0', CNTVALUEIN => (others => '0'), DATAIN => '0', IDATAIN => DCLKIO, INC => '0', LD => '0', LDPIPEEN => '0', REGRST => '0' ); DAC_DDRs1: FOR i IN 0 TO 13 GENERATE BEGIN DAC_d : ODDR GENERIC MAP ( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC" ) PORT MAP ( Q => DB(i), C => dac_clk, CE => '1', D1 => data_Q(i), D2 => data_I(i), R => not resetn, S => '0' ); END GENERATE DAC_DDRs1; read_data : PROCESS(clk) BEGIN IF clk'EVENT AND clk = '1' THEN if S_AXIS_DAC_A_tvalid = '1' then data_I <= S_AXIS_DAC_A_tdata(15 downto 2); else data_I <= (others => '0'); end if; if S_AXIS_DAC_B_tvalid = '1' then data_Q <= S_AXIS_DAC_B_tdata(15 downto 2); else data_Q <= (others => '0'); end if; end if; END PROCESS; END ARCHITECTURE struct;

gpl-3.0

b5936e19f17f28b63406ef3549666e0d