Datasets:

davide221

/

hdl-raw-35k

like 0

malkadi/FGPU

RTL/floating_point/fmul.vhd

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY fmul IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END fmul; ARCHITECTURE fmul_arch OF fmul IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF fmul_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_2 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_2; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_2 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 1, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 8, C_OPTIMIZATION => 1, C_MULT_USAGE => 2, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 0 ) PORT MAP ( aclk => aclk, aclken => '1', aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END fmul_arch;

gpl-3.0

51eadc17385f1b2f8c673bdac989a84e

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_float_8ALUs_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

4bf42eec09d2799d79016980c8054233

Kinxil/VHDL_Projects

Mandelbrot/cpt_iter.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.CONSTANTS.all; use work.CONFIG_MANDELBROT.all; entity cpt_iter is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; inib : in std_logic; endcalcul : in STD_LOGIC; maxiter : in STD_LOGIC; iter : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0)); end cpt_iter; architecture Behavioral of cpt_iter is Signal iterS : unsigned(ITER_RANGE-1 downto 0); begin process(reset,clock) begin if reset='1' then iterS<=to_unsigned(5,ITER_RANGE); elsif rising_edge(clock) then if maxiter = '1' then iterS <= to_unsigned(ITER_MAX,ITER_RANGE); elsif inib = '1' then if endcalcul ='1' then if iterS < (ITER_MAX-10) then iterS<=iterS+1; else iterS<=to_unsigned(10,ITER_RANGE); end if; end if; end if; end if; end process; iter<=std_logic_vector(iterS); end Behavioral;

gpl-3.0

47e1e04b1d0e8c2f67d10dec8ff46bed

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fsqrt_uitofp.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 3; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

20fde2ec2a04026663c15c3fa01642d6

malkadi/FGPU

RTL/CU_instruction_dispatcher.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity CU_instruction_dispatcher is --{{{ port( clk, nrst : in std_logic; cram_rqst : out std_logic := '0'; cram_rdAddr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdAddr_conf : in unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdData : in std_logic_vector(DATA_W-1 downto 0); -- cram_rdData is delayed by 1 clock cycle to cram_rdAddr_conf PC_indx : in integer range 0 to N_WF_CU-1; --response in two clk cycles wf_active : in std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); pc_updated : in std_logic_vector(N_WF_CU-1 downto 0); PCs : in CRAM_ADDR_ARRAY(N_WF_CU-1 downto 0); pc_rdy : out std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); instr : out std_logic_vector(DATA_W-1 downto 0) := (others => '0'); -- 1 clock cycle delayed after pc_rdy instr_gmem_op : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_scratchpad_ld : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_gmem_read : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_branch : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_jump : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_fpu : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); branch_distance : out branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); wf_retired : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0') ); end CU_instruction_dispatcher; -- }}} architecture Behavioral of CU_instruction_dispatcher is -- internal signals definitions {{{ signal cram_rdAddr_i : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal pc_rdy_i : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_retired_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_gmem_op_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_scratchpad_ld_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_branch_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_jump_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_fpu_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_gmem_read_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal branch_distance_i : branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); -- }}} -- signals definitions {{{ type st_cram_type is (request, wait_resp, check); type instr_vec_type is array (N_WF_CU-1 downto 0) of std_logic_vector(DATA_W-1 downto 0); -- global FSM signals signal instr_vec, instr_vec_n : instr_vec_type := (others=>(others=>'0')); signal st_cram, st_cram_n : st_cram_type := check; signal cram_ack : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- next signals signal cram_rdAddr_n : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal pc_rdy_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal cram_rdData_gmem_op : std_logic := '0'; signal instr_gmem_op_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_scratchpad_ld_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_branch_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_jump_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_fpu_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_gmem_read_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_retired_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal branch_distance_n : branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); -- }}} begin -- internal signals -------------------------------------------------------------------------------------{{{ cram_rdAddr <= cram_rdAddr_i; pc_rdy <= pc_rdy_i; wf_retired <= wf_retired_i; instr_gmem_op <= instr_gmem_op_i; instr_scratchpad_ld <= instr_scratchpad_ld_i; instr_gmem_read <= instr_gmem_read_i; instr_branch <= instr_branch_i; instr_jump <= instr_jump_i; instr_fpu <= instr_fpu_i; branch_distance <= branch_distance_i; ---------------------------------------------------------------------------------------------------------}}} -- cram FSM ----------------------------------------------------------------------------------- {{{ process(clk) begin if rising_edge(clk) then if nrst = '0' then st_cram <= check; instr_gmem_op_i <= (others=>'0'); instr_scratchpad_ld_i <= (others=>'0'); instr_branch_i <= (others=>'0'); instr_jump_i <= (others=>'0'); instr_fpu_i <= (others=>'0'); branch_distance_i <= (others=>(others=>'0')); instr_gmem_read_i <= (others=>'0'); wf_retired_i <= (others=>'0'); pc_rdy_i <= (others=>'0'); cram_rdAddr_i <= (others=>'0'); instr_vec <= (others=>(others=>'0')); instr <= (others=>'0'); else st_cram <= st_cram_n; pc_rdy_i <= pc_rdy_n; cram_rdAddr_i <= cram_rdAddr_n; instr_vec <= instr_vec_n; instr <= instr_vec(PC_indx); instr_gmem_op_i <= instr_gmem_op_n; instr_scratchpad_ld_i <= instr_scratchpad_ld_n; branch_distance_i <= branch_distance_n; instr_branch_i <= instr_branch_n; instr_jump_i <= instr_jump_n; instr_fpu_i <= instr_fpu_n; instr_gmem_read_i <= instr_gmem_read_n; wf_retired_i <= wf_retired_n; cram_ack <= (others=>'0'); for i in 0 to N_WF_CU-1 loop if pc_rdy_i(i) = '0' and pc_updated(i) = '0' and PCs(i) = cram_rdAddr_conf and wf_active(i) = '1' then cram_ack(i) <= '1'; end if; end loop; -- for i in 0 to N_WF_CU-1 loop -- if wf_activate(i) = '1' then -- wf_active(i) <= '1'; -- elsif wf_retired_i(i) = '1' then -- wf_active(i) <= '0'; -- end if; -- end loop; end if; end if; end process; WFs_bufs: for i in 0 to N_WF_CU-1 generate begin WF_buf: process(pc_updated(i), pc_rdy_i(i), cram_rdData, instr_vec(i), wf_retired_i(i), instr_gmem_op_i(i), instr_branch_i(i), instr_gmem_read_i(i), branch_distance_i(i), cram_ack(i), instr_jump_i(i), instr_fpu_i(i), instr_scratchpad_ld_i(i)) begin pc_rdy_n(i) <= pc_rdy_i(i); instr_vec_n(i) <= instr_vec(i); wf_retired_n(i) <= wf_retired_i(i); instr_gmem_op_n(i) <= instr_gmem_op_i(i); instr_scratchpad_ld_n(i) <= instr_scratchpad_ld_i(i); branch_distance_n(i) <= branch_distance_i(i); instr_branch_n(i) <= instr_branch_i(i); instr_jump_n(i) <= instr_jump_i(i); instr_fpu_n(i) <= instr_fpu_i(i); instr_gmem_read_n(i) <= instr_gmem_read_i(i); -- if wf_active(i) = '0' then -- wf_retired_n(i) <= '0'; -- end if; if pc_updated(i) = '1' then pc_rdy_n(i) <= '0'; elsif cram_ack(i) = '1' then instr_vec_n(i) <= cram_rdData; instr_gmem_op_n(i) <= '0'; instr_gmem_read_n(i) <= '0'; instr_branch_n(i) <= '0'; instr_jump_n(i) <= '0'; instr_fpu_n(i) <= '0'; pc_rdy_n(i) <= '1'; wf_retired_n(i) <= '0'; instr_scratchpad_ld_n(i) <= '0'; case cram_rdData(FAMILY_POS+FAMILY_W-1 downto FAMILY_POS) is when GLS_FAMILY => instr_gmem_op_n(i) <= '1'; instr_gmem_read_n(i) <= not cram_rdData(CODE_POS+CODE_W-1); when ATO_FAMILY => instr_gmem_op_n(i) <= '1'; instr_gmem_read_n(i) <= '1'; when BRA_FAMILY => if cram_rdData(CODE_POS+CODE_W-1 downto CODE_POS) = JSUB then instr_jump_n(i) <= '1'; else instr_branch_n(i) <= '1'; end if; branch_distance_n(i) <= unsigned(cram_rdData(BRANCH_ADDR_POS+BRANCH_ADDR_W-1 downto BRANCH_ADDR_POS)); when CTL_FAMILY => if cram_rdData(CODE_POS+CODE_W-1 downto CODE_POS) = RET then wf_retired_n(i) <= '1'; end if; when LSI_FAMILY => instr_scratchpad_ld_n(i) <= not cram_rdData(CODE_POS+CODE_W-1); when FLT_FAMILY => instr_fpu_n(i) <= '1'; when others => end case; end if; end process; end generate; process(st_cram, cram_rdAddr_i, cram_rdAddr_conf, pc_rdy_i, wf_active, PCs) begin cram_rdAddr_n <= cram_rdAddr_i; cram_rqst <= '0'; st_cram_n <= st_cram; case st_cram is when check => for i in 0 to N_WF_CU-1 loop if wf_active(i)='1' and pc_rdy_i(i)='0' then st_cram_n <= request; cram_rdAddr_n <= PCs(i); end if; end loop; when request => cram_rqst <= '1'; st_cram_n <= wait_resp; when wait_resp => cram_rqst <= '1'; if cram_rdAddr_conf = cram_rdAddr_i then st_cram_n <= check; cram_rqst <= '0'; end if; end case; end process; ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

a9a2f45df88b09bf35c95c9cee5bb24b

preusser/q27

src/vhdl/PoC/xilinx/xil_SystemMonitor_Virtex6.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: System Monitor wrapper for temperature supervision applications -- -- Description: -- ------------------------------------ -- This module wraps a Virtex-6 System Monitor primitive to report if preconfigured -- temperature values are overrun. -- -- Temperature curve: -- ------------------ -- -- | /-----\ -- Temp_ov on=80 | - - - - - - /-------/ \ -- | / | \ -- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ -- | / | \ -- | / | | \ -- Temp_us on=35 | - /---/ | | \ -- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\ -- | / | | | \ -- ----------------|--------|------------|--------------|----------|--------- -- pwm = | min | medium | max | medium | min -- -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.NUMERIC_STD.all; LIBRARY UniSim; USE UniSim.vComponents.ALL; entity xil_SystemMonitor_Virtex6 is port ( Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output Alarm : out STD_LOGIC; -- OR'ed output of all the Alarms VP : in STD_LOGIC; -- Dedicated Analog Input Pair VN : in STD_LOGIC ); end; architecture xilinx of xil_SystemMonitor_Virtex6 is signal FLOAT_VCCAUX_ALARM : STD_LOGIC; signal FLOAT_VCCINT_ALARM : STD_LOGIC; signal aux_channel_p : STD_LOGIC_VECTOR(15 downto 0); signal aux_channel_n : STD_LOGIC_VECTOR(15 downto 0); signal SysMonitor_Alarm : STD_LOGIC_VECTOR(2 downto 0); signal SysMonitor_OverTemp : STD_LOGIC; begin genAUXChannel : for i in 0 to 15 generate aux_channel_p(i) <= '0'; aux_channel_n(i) <= '0'; end generate; SysMonitor : SYSMON generic map ( INIT_40 => x"0000", -- config reg 0 INIT_41 => x"300c", -- config reg 1 INIT_42 => x"0a00", -- config reg 2 INIT_48 => x"0100", -- Sequencer channel selection INIT_49 => x"0000", -- Sequencer channel selection INIT_4A => x"0000", -- Sequencer Average selection INIT_4B => x"0000", -- Sequencer Average selection INIT_4C => x"0000", -- Sequencer Bipolar selection INIT_4D => x"0000", -- Sequencer Bipolar selection INIT_4E => x"0000", -- Sequencer Acq time selection INIT_4F => x"0000", -- Sequencer Acq time selection INIT_50 => x"a418", -- Temp alarm trigger INIT_51 => x"5999", -- Vccint upper alarm limit INIT_52 => x"e000", -- Vccaux upper alarm limit INIT_53 => x"b363", -- Temp alarm OT upper INIT_54 => x"9c87", -- Temp alarm reset INIT_55 => x"5111", -- Vccint lower alarm limit INIT_56 => x"caaa", -- Vccaux lower alarm limit INIT_57 => x"a425", -- Temp alarm OT reset SIM_DEVICE => "VIRTEX6", SIM_MONITOR_FILE => "SystemMonitor_sim.txt" ) port map ( -- Control and Clock RESET => Reset, CONVSTCLK => '0', CONVST => '0', -- DRP port DCLK => '0', DEN => '0', DADDR => "0000000", DWE => '0', DI => x"0000", DO => open, DRDY => open, -- External analog inputs VAUXN => aux_channel_n(15 downto 0), VAUXP => aux_channel_p(15 downto 0), VN => VN, VP => VP, -- Alarms OT => SysMonitor_OverTemp, ALM => SysMonitor_Alarm, -- Status CHANNEL => open, BUSY => open, EOC => open, EOS => open, JTAGBUSY => open, JTAGLOCKED => open, JTAGMODIFIED => open ); Alarm_UserTemp <= SysMonitor_Alarm(0); Alarm_OverTemp <= SysMonitor_OverTemp; Alarm <= SysMonitor_Alarm(0) or SysMonitor_OverTemp; end;

agpl-3.0

d1eef6130d2fe5c57ac20109d57f6d82

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_2CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

1426be4e6fdf5b9c0d6fe9b113384af1

jpidancet/mips

rtl/mips_defs.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; package mips_defs is subtype mips_opcode_type is std_logic_vector(5 downto 0); subtype mips_func_type is std_logic_vector(5 downto 0); constant OP_SPECIAL : std_logic_vector(5 downto 0) := "000000"; constant OP_J : std_logic_vector(5 downto 0) := "000010"; constant OP_JAL : std_logic_vector(5 downto 0) := "000011"; constant OP_BEQ : std_logic_vector(5 downto 0) := "000100"; constant OP_BNE : std_logic_vector(5 downto 0) := "000101"; constant OP_ADDI : std_logic_vector(5 downto 0) := "001000"; constant OP_ADDIU : std_logic_vector(5 downto 0) := "001001"; constant OP_SLTI : std_logic_vector(5 downto 0) := "001010"; -- Not implemented constant OP_SLTIU : std_logic_vector(5 downto 0) := "001011"; -- Not implemented constant OP_ANDI : std_logic_vector(5 downto 0) := "001100"; constant OP_ORI : std_logic_vector(5 downto 0) := "001101"; constant OP_LUI : std_logic_vector(5 downto 0) := "001111"; constant OP_LB : std_logic_vector(5 downto 0) := "100000"; -- Not implemented constant OP_LW : std_logic_vector(5 downto 0) := "100011"; constant OP_LBU : std_logic_vector(5 downto 0) := "100100"; -- Not implemented constant OP_LHU : std_logic_vector(5 downto 0) := "100101"; -- Not implemented constant OP_SB : std_logic_vector(5 downto 0) := "101000"; -- Not implemented constant OP_SH : std_logic_vector(5 downto 0) := "101001"; -- Not implemented constant OP_SW : std_logic_vector(5 downto 0) := "101011"; constant OP_LL : std_logic_vector(5 downto 0) := "110000"; -- Not implemented constant OP_SC : std_logic_vector(5 downto 0) := "111000"; -- Not implemented constant FUNC_SLL : std_logic_vector(5 downto 0) := "000000"; constant FUNC_SRL : std_logic_vector(5 downto 0) := "000010"; constant FUNC_JR : std_logic_vector(5 downto 0) := "001000"; constant FUNC_JALR : std_logic_vector(5 downto 0) := "001001"; constant FUNC_ADD : std_logic_vector(5 downto 0) := "100000"; constant FUNC_ADDU : std_logic_vector(5 downto 0) := "100001"; constant FUNC_SUB : std_logic_vector(5 downto 0) := "100010"; constant FUNC_SUBU : std_logic_vector(5 downto 0) := "100011"; constant FUNC_AND : std_logic_vector(5 downto 0) := "100100"; constant FUNC_OR : std_logic_vector(5 downto 0) := "100101"; constant FUNC_XOR : std_logic_vector(5 downto 0) := "100110"; constant FUNC_NOR : std_logic_vector(5 downto 0) := "100111"; constant FUNC_SLT : std_logic_vector(5 downto 0) := "101010"; constant FUNC_SLTU : std_logic_vector(5 downto 0) := "101011"; type branch_type is (NO_BRANCH, BRANCH_COND, JUMP_IMM, JUMP_REG); type extend_type is (ZERO_EXTEND, SIGN_EXTEND, SHIFT16_EXTEND); type compare_type is (CMP_EQUAL, CMP_NOT_EQUAL, CMP_GREATER, CMP_GREATER_OR_EQUAL, CMP_LESS, CMP_LESS_OR_EQUAL); type alucontrol_type is (ALU_SLL, ALU_SRL, ALU_AND, ALU_XOR, ALU_NOR, ALU_OR, ALU_ADD, ALU_SUB, ALU_SLT, ALU_SLTU, ALU_BPLUS4); end package mips_defs; package body mips_defs is end package body;

isc

aa8023f06d541d6a8209ed69329f0d49

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd

"`protect begin_protected\n`protect version = 1\n`protect encrypt_agent = \"XILINX\"\n`protect encry(...TRUNCATED)

mit

6c7a32c885f78d562f59ef0102b884af

wltr/cern-fgclite

critical_fpga/src/rtl/cf/nf/nf_transmitter.vhd

"-------------------------------------------------------------------------------\n--! @file nf_(...TRUNCATED)

mit

0496a48fdbd4ed236824656e758d6b3b