Datasets:

davide221

/

hdl-raw-35k

like 0

jpidancet/mips

rtl/hazard.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity hazard is port (branch_d : in std_logic; rs_d : in std_logic_vector(4 downto 0); rt_d : in std_logic_vector(4 downto 0); rs_e : in std_logic_vector(4 downto 0); rt_e : in std_logic_vector(4 downto 0); writereg_e : in std_logic_vector(4 downto 0); memtoreg_e : in std_logic; regwrite_e : in std_logic; writereg_m : in std_logic_vector(4 downto 0); memtoreg_m : in std_logic; regwrite_m : in std_logic; writereg_w : in std_logic_vector(4 downto 0); regwrite_w : in std_logic; forward_ad : out std_logic; forward_bd : out std_logic; forward_ae : out std_logic_vector(1 downto 0); forward_be : out std_logic_vector(1 downto 0); stall : out std_logic); end entity hazard; architecture rtl of hazard is signal branchstall : std_logic; signal loadstall : std_logic; begin forward_ae <= "10" when (rs_e /= 0) and regwrite_m = '1' and (writereg_m = rs_e) else "01" when (rs_e /= 0) and regwrite_w = '1' and (writereg_w = rs_e) else "00"; forward_be <= "10" when (rt_e /= 0) and regwrite_m = '1' and (writereg_m = rt_e) else "01" when (rt_e /= 0) and regwrite_w = '1' and (writereg_w = rt_e) else "00"; forward_ad <= '1' when (rs_d /= 0) and regwrite_m = '1' and (writereg_m = rs_d) else '0'; forward_bd <= '1' when (rt_d /= 0) and regwrite_m = '1' and (writereg_m = rt_d) else '0'; branchstall <= '1' when branch_d = '1' and regwrite_e = '1' and ((writereg_e = rs_d) or (writereg_e = rt_d)) else '1' when branch_d = '1' and memtoreg_m = '1' and ((writereg_m = rs_d) or (writereg_m = rt_d)) else '0'; loadstall <= '1' when (memtoreg_e = '1') and ((rs_d = rt_e) or (rt_d = rt_e)) else '0'; stall <= branchstall or loadstall; end architecture rtl;

isc

5504bd1422ae6594e67f79a9f348251e

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_hdl_node_user_params.vhd

-- File: dyplo_hdl_node_user_params.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package hdl_node_user_params is constant c_vendor_id : integer range 0 to 255 := 1; constant c_product_id : integer range 0 to 255 := 4; constant c_version_id : integer range 0 to 255 := 1; constant c_revision_id : integer range 0 to 255 := 1; constant c_input_streams : integer range 0 to 4 := 4; constant c_hdl_in_fifo_depth : integer range 7 to 12 := 8; -- specify power of 2. FIFO size = 2^x. 7 = 128, 12 = 4096 constant c_hdl_in_fifo_type : string := "DISTRIBUTED"; constant c_output_streams : integer range 0 to 4 := 4; end hdl_node_user_params;

gpl-2.0

2761ae9e0e9ce208d103e3d05c5430c4

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_2AXI_4CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a2b523e4f4fe0bf9e574e95236935830

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_fsm.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IHxkGpWEInM/BoGXBAEZYpVnkSCZxZAesmVubZbyazFANRNV77NX7ZWE14tZ8Vps711wDoFE4h9i YKyRsHC08g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block esWGwXLncnFGIJNJq1TkZqEtlK/5WAzC5YCdzQO/sEMt7GtUn3Aafmhyi7Gg9EDyD1YlcDejtAAb A9W3URRYM3i7BJEEdGsKsxgPAmCZQZg6aAg2c6Yt2qUQcQpvHnIEMVcHTLpZFSjghhfM32BJO74Q JJ2dv3HBI3rrE79B9Gk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

c3bfafd09468012eed81ca01e0e48093

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

77e4ea1acbfd7794a2e6714011d6ec53

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_hdl_node_logic.vhd

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gpl-2.0

8c8260ccc600dcb0c8ff1ba07af389cc

preusser/q27

src/vhdl/PoC/uart/uart_tx.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- =========================================================================== -- Module: -- -- Authors: Thomas B. Preusser -- -- Description: UART (RS232) Transmitter: 1 Start + 8 Data + 1 Stop -- ------------ -- -- License: -- =========================================================================== -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- =========================================================================== library IEEE; use IEEE.std_logic_1164.all; entity uart_tx is port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Bit Clock and TX Line bclk : in std_logic; -- bit clock, one strobe each bit length tx : out std_logic; -- Byte Stream Input di : in std_logic_vector(7 downto 0); put : in std_logic; ful : out std_logic ); end entity; library IEEE; use IEEE.numeric_std.all; architecture rtl of uart_tx is -- Buf Cnt -- Idle "---------1" "0----" -- Start "hgfedcba01" -10 -- Send "1111hgfedc" -10 -> -1 -- Done "1111111111" 0 signal Buf : std_logic_vector(9 downto 0) := (0 => '1', others => '-'); signal Cnt : signed(4 downto 0) := "0----"; begin process(clk) begin if rising_edge(clk) then if rst = '1' then Buf <= (0 => '1', others => '-'); Cnt <= "0----"; else if Cnt(Cnt'left) = '0' then -- Idle if put = '1' then -- Start Transmission Buf <= di & "01"; Cnt <= to_signed(-10, Cnt'length); else Buf <= (0 => '1', others => '-'); Cnt <= "0----"; end if; else -- Transmitting if bclk = '1' then Buf <= '1' & Buf(Buf'left downto 1); Cnt <= Cnt + 1; end if; end if; end if; end if; end process; tx <= Buf(0); ful <= Cnt(Cnt'left); end;

agpl-3.0

d2a233b602d02800fb8d68d34facc42a

wltr/cern-fgclite

critical_fpga/src/rtl/cf/sram.vhd

------------------------------------------------------------------------------- --! @file sram.vhd --! @author Johannes Walter <[email protected]> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief External SRAM communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.sram_pkg.all; --! @brief Entity declaration of sram --! @details --! This component handles the interface with the external SRAM. entity sram is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Command and status --! @{ --! ADC log index adc_log_idx_o : out std_ulogic_vector(15 downto 0); --! DIM log index dim_log_idx_o : out std_ulogic_vector(15 downto 0); --! ADC log freeze adc_freeze_i : in std_ulogic; --! DIM log freeze dim_freeze_i : in std_ulogic; --! Millisecond strobe indicating start of cycle ms_0_strobe_i : in std_ulogic; --! @} --! @name ADC and DIM data --! @{ --! ADC VS data adc_vs_i : in std_ulogic_vector(23 downto 0); --! ADC VS data enable adc_vs_en_i : in std_ulogic; --! ADC IA data adc_ia_i : in std_ulogic_vector(23 downto 0); --! ADC IA data enable adc_ia_en_i : in std_ulogic; --! ADC IB data adc_ib_i : in std_ulogic_vector(23 downto 0); --! ADC IB data enable adc_ib_en_i : in std_ulogic; --! DIM data dim_i : in std_ulogic_vector(19 downto 0); --! DIM data enable dim_en_i : in std_ulogic; --! @} --! @name Read interface --! @{ --! Memory index idx_i : in std_ulogic_vector(14 downto 0); --! Memory index type idx_type_i : in std_ulogic_vector(2 downto 0); --! ADC Address adc_addr_i : in std_ulogic_vector(4 downto 0); --! ADC Read enable adc_rd_en_i : in std_ulogic; --! ADC Data output adc_data_o : out std_ulogic_vector(23 downto 0); --! ADC Data output enable adc_data_en_o : out std_ulogic; --! ADC Done flag adc_done_i : in std_ulogic; --! DIM Address dim_addr_i : in std_ulogic_vector(4 downto 0); --! DIM Read enable dim_rd_en_i : in std_ulogic; --! DIM Data output dim_data_o : out std_ulogic_vector(15 downto 0); --! DIM Data output enable dim_data_en_o : out std_ulogic; --! DIM Done flag dim_done_i : in std_ulogic; --! @} --! @name External SRAM interface --! @{ --! Inputs sram_i : in sram_in_t; --! Outputs sram_o : out sram_out_t); --! @} end entity sram; --! RTL implementation of sram architecture rtl of sram is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ constant adc_vs_base_addr_c : unsigned(2 downto 0) := "000"; constant adc_ia_base_addr_c : unsigned(2 downto 0) := "001"; constant adc_ib_base_addr_c : unsigned(2 downto 0) := "010"; constant dim_base_addr_c : unsigned(18 downto 0) := "0110000000000000000"; type state_t is (RD_CHECK, RD_ADC_IA, WR_ADC_IA_0, WR_ADC_IA_1, RD_ADC_IB, WR_ADC_IB_0, WR_ADC_IB_1, RD_ADC_VS, WR_ADC_VS_0, WR_ADC_VS_1, RD_DIM, WR_DIM, FETCH_REQ, FETCH_ADC_0, STORE_ADC_0, FETCH_ADC_1, STORE_ADC_1, FETCH_DIM, STORE_DIM); type reg_t is record state : state_t; adc_idx : unsigned(14 downto 0); dim_idx : unsigned(10 downto 0); adc_rd_req : std_ulogic; dim_rd_req : std_ulogic; adc_data : std_ulogic_vector(23 downto 0); adc_data_en : std_ulogic; dim_data : std_ulogic_vector(15 downto 0); dim_data_en : std_ulogic; end record; constant init_c : reg_t := ( state => RD_CHECK, adc_idx => (others => '0'), dim_idx => (others => '0'), adc_rd_req => '0', dim_rd_req => '0', adc_data => (others => '0'), adc_data_en => '0', dim_data => (others => '0'), dim_data_en => '0'); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg: reg_t; signal tmr_addr : std_ulogic_vector(18 downto 0); signal tmr_rd_en : std_ulogic; signal tmr_wr_en : std_ulogic; signal tmr_data_in : std_ulogic_vector(15 downto 0); signal tmr_data_out : std_ulogic_vector(15 downto 0); signal tmr_data_en : std_ulogic; signal tmr_done : std_ulogic; signal tmr_busy : std_ulogic; signal sram_addr : std_ulogic_vector(19 downto 0); signal sram_rd_en : std_ulogic; signal sram_wr_en : std_ulogic; signal sram_data_in : std_ulogic_vector(15 downto 0); signal sram_data_out : std_ulogic_vector(15 downto 0); signal sram_data_en : std_ulogic; signal sram_busy : std_ulogic; signal sram_done : std_ulogic; signal dim_fifo_rd_en : std_ulogic; signal dim_fifo_data : std_ulogic_vector(19 downto 0); signal dim_fifo_data_en : std_ulogic; signal dim_fifo_empty : std_ulogic; signal dim_fifo_wr_busy : std_ulogic; signal adc_vs_fifo_rd_en : std_ulogic; signal adc_vs_fifo_data : std_ulogic_vector(23 downto 0); signal adc_vs_fifo_data_en : std_ulogic; signal adc_vs_fifo_empty : std_ulogic; signal adc_vs_fifo_wr_busy : std_ulogic; signal adc_ia_fifo_rd_en : std_ulogic; signal adc_ia_fifo_data : std_ulogic_vector(23 downto 0); signal adc_ia_fifo_data_en : std_ulogic; signal adc_ia_fifo_empty : std_ulogic; signal adc_ia_fifo_wr_busy : std_ulogic; signal adc_ib_fifo_rd_en : std_ulogic; signal adc_ib_fifo_data : std_ulogic_vector(23 downto 0); signal adc_ib_fifo_data_en : std_ulogic; signal adc_ib_fifo_empty : std_ulogic; signal adc_ib_fifo_wr_busy : std_ulogic; signal adc_req_base_addr : unsigned(2 downto 0); --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- adc_log_idx_o <= '0' & std_ulogic_vector(reg.adc_idx); dim_log_idx_o <= "00000" & std_ulogic_vector(reg.dim_idx); adc_data_o <= reg.adc_data; adc_data_en_o <= reg.adc_data_en; dim_data_o <= reg.dim_data; dim_data_en_o <= reg.dim_data_en; --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- with idx_type_i select adc_req_base_addr <= adc_vs_base_addr_c when "010", adc_ia_base_addr_c when "011", adc_ib_base_addr_c when "100", (others => '0') when others; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! DIM FIFO dim_fifo_inst : entity work.fifo_tmr generic map ( depth_g => 32, width_g => 20) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => dim_en_i, data_i => dim_i, done_o => open, full_o => open, wr_busy_o => dim_fifo_wr_busy, rd_en_i => dim_fifo_rd_en, data_o => dim_fifo_data, data_en_o => dim_fifo_data_en, empty_o => dim_fifo_empty, rd_busy_o => open); --! ADC VS FIFO adc_vs_fifo_inst : entity work.fifo_tmr generic map ( depth_g => 20, width_g => 24) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => adc_vs_en_i, data_i => adc_vs_i, done_o => open, full_o => open, wr_busy_o => adc_vs_fifo_wr_busy, rd_en_i => adc_vs_fifo_rd_en, data_o => adc_vs_fifo_data, data_en_o => adc_vs_fifo_data_en, empty_o => adc_vs_fifo_empty, rd_busy_o => open); --! ADC IA FIFO adc_ia_fifo_inst : entity work.fifo_tmr generic map ( depth_g => 20, width_g => 24) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => adc_ia_en_i, data_i => adc_ia_i, done_o => open, full_o => open, wr_busy_o => adc_ia_fifo_wr_busy, rd_en_i => adc_ia_fifo_rd_en, data_o => adc_ia_fifo_data, data_en_o => adc_ia_fifo_data_en, empty_o => adc_ia_fifo_empty, rd_busy_o => open); --! ADC IB FIFO adc_ib_fifo_inst : entity work.fifo_tmr generic map ( depth_g => 20, width_g => 24) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => adc_ib_en_i, data_i => adc_ib_i, done_o => open, full_o => open, wr_busy_o => adc_ib_fifo_wr_busy, rd_en_i => adc_ib_fifo_rd_en, data_o => adc_ib_fifo_data, data_en_o => adc_ib_fifo_data_en, empty_o => adc_ib_fifo_empty, rd_busy_o => open); --! External SRAM data triplicator tmr_inst : entity work.mem_data_triplicator generic map ( depth_g => 2**sram_addr'length, width_g => 16) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, addr_i => tmr_addr, rd_en_i => tmr_rd_en, wr_en_i => tmr_wr_en, data_i => tmr_data_in, data_o => tmr_data_out, data_en_o => tmr_data_en, busy_o => tmr_busy, done_o => tmr_done, voted_o => open, mem_addr_o => sram_addr, mem_rd_en_o => sram_rd_en, mem_wr_en_o => sram_wr_en, mem_data_o => sram_data_in, mem_data_i => sram_data_out, mem_data_en_i => sram_data_en, mem_busy_i => sram_busy, mem_done_i => sram_done); --! External SRAM interface sram_if_inst : entity work.sram_interface generic map ( addr_width_g => 20, data_width_g => 16, read_delay_g => 8, write_delay_g => 4) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, addr_i => sram_addr, rd_en_i => sram_rd_en, wr_en_i => sram_wr_en, data_i => sram_data_in, data_o => sram_data_out, data_en_o => sram_data_en, busy_o => sram_busy, done_o => sram_done, sram_addr_o => sram_o.addr, sram_data_i => sram_i.data, sram_data_o => sram_o.data, sram_cs1_n_o => sram_o.cs1_n, sram_cs2_o => sram_o.cs2, sram_we_n_o => sram_o.we_n, sram_oe_n_o => sram_o.oe_n, sram_le_n_o => sram_o.le_n, sram_ue_n_o => sram_o.ue_n, sram_byte_n_o => sram_o.byte_n); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, idx_i, tmr_busy, tmr_done, tmr_data_out, tmr_data_en, adc_ia_fifo_empty, adc_ia_fifo_data_en, adc_ia_fifo_data, adc_ib_fifo_empty, adc_ib_fifo_data_en, adc_ib_fifo_data, adc_vs_fifo_empty, adc_vs_fifo_data_en, adc_vs_fifo_data, dim_fifo_empty, dim_fifo_data_en, dim_fifo_data, adc_rd_en_i, dim_rd_en_i, adc_addr_i, dim_addr_i, adc_req_base_addr, adc_done_i, dim_done_i, adc_freeze_i, dim_freeze_i, dim_fifo_wr_busy, adc_vs_fifo_wr_busy, adc_ia_fifo_wr_busy, adc_ib_fifo_wr_busy, ms_0_strobe_i) is begin -- comb -- Defaults next_reg <= reg; next_reg.adc_data_en <= '0'; next_reg.dim_data_en <= '0'; adc_vs_fifo_rd_en <= '0'; adc_ia_fifo_rd_en <= '0'; adc_ib_fifo_rd_en <= '0'; dim_fifo_rd_en <= '0'; tmr_rd_en <= '0'; tmr_wr_en <= '0'; tmr_data_in <= (others => '0'); tmr_addr <= (others => '0'); if adc_rd_en_i = '1' then next_reg.adc_rd_req <= '1'; end if; if dim_rd_en_i = '1' then next_reg.dim_rd_req <= '1'; end if; if ms_0_strobe_i = '1' and dim_freeze_i = '0' then next_reg.dim_idx <= reg.dim_idx + 1; end if; case reg.state is when RD_CHECK => if adc_freeze_i = '0' and adc_ia_fifo_empty = '0' and adc_ib_fifo_empty = '0' and adc_vs_fifo_empty = '0' then next_reg.adc_idx <= reg.adc_idx + 1; next_reg.state <= RD_ADC_IA; else next_reg.state <= RD_DIM; end if; when RD_ADC_IA => if tmr_busy = '0' and adc_ia_fifo_wr_busy = '0' then adc_ia_fifo_rd_en <= '1'; next_reg.state <= WR_ADC_IA_0; end if; when WR_ADC_IA_0 => if adc_ia_fifo_data_en = '1' then tmr_wr_en <= '1'; tmr_data_in <= adc_ia_fifo_data(15 downto 0); tmr_addr <= std_ulogic_vector(adc_ia_base_addr_c & reg.adc_idx & '0'); next_reg.state <= WR_ADC_IA_1; end if; when WR_ADC_IA_1 => if tmr_busy = '0' then tmr_wr_en <= '1'; tmr_data_in <= (31 downto 24 => adc_ia_fifo_data(adc_ia_fifo_data'high)) & adc_ia_fifo_data(23 downto 16); tmr_addr <= std_ulogic_vector(adc_ia_base_addr_c & reg.adc_idx & '1'); next_reg.state <= RD_ADC_IB; end if; when RD_ADC_IB => if tmr_busy = '0' and adc_ib_fifo_wr_busy = '0' then adc_ib_fifo_rd_en <= '1'; next_reg.state <= WR_ADC_IB_0; end if; when WR_ADC_IB_0 => if adc_ib_fifo_data_en = '1' then tmr_wr_en <= '1'; tmr_data_in <= adc_ib_fifo_data(15 downto 0); tmr_addr <= std_ulogic_vector(adc_ib_base_addr_c & reg.adc_idx & '0'); next_reg.state <= WR_ADC_IB_1; end if; when WR_ADC_IB_1 => if tmr_busy = '0' then tmr_wr_en <= '1'; tmr_data_in <= (31 downto 24 => adc_ib_fifo_data(adc_ib_fifo_data'high)) & adc_ib_fifo_data(23 downto 16); tmr_addr <= std_ulogic_vector(adc_ib_base_addr_c & reg.adc_idx & '1'); next_reg.state <= RD_ADC_VS; end if; when RD_ADC_VS => if tmr_busy = '0' and adc_vs_fifo_wr_busy = '0' then adc_vs_fifo_rd_en <= '1'; next_reg.state <= WR_ADC_VS_0; end if; when WR_ADC_VS_0 => if adc_vs_fifo_data_en = '1' then tmr_wr_en <= '1'; tmr_data_in <= adc_vs_fifo_data(15 downto 0); tmr_addr <= std_ulogic_vector(adc_vs_base_addr_c & reg.adc_idx & '0'); next_reg.state <= WR_ADC_VS_1; end if; when WR_ADC_VS_1 => if tmr_busy = '0' then tmr_wr_en <= '1'; tmr_data_in <= (31 downto 24 => adc_vs_fifo_data(adc_vs_fifo_data'high)) & adc_vs_fifo_data(23 downto 16); tmr_addr <= std_ulogic_vector(adc_vs_base_addr_c & reg.adc_idx & '1'); next_reg.state <= RD_DIM; end if; when RD_DIM => if tmr_busy = '0' and dim_fifo_wr_busy = '0' then if dim_fifo_empty = '0' and dim_freeze_i = '0' then dim_fifo_rd_en <= '1'; next_reg.state <= WR_DIM; else next_reg.state <= FETCH_REQ; end if; end if; when WR_DIM => if dim_fifo_data_en = '1' then tmr_wr_en <= '1'; tmr_data_in <= dim_fifo_data(15 downto 0); tmr_addr <= std_ulogic_vector(dim_base_addr_c + (unsigned(dim_fifo_data(19 downto 16)) & reg.dim_idx & unsigned(dim_fifo_data(13 downto 12)))); next_reg.state <= FETCH_REQ; end if; when FETCH_REQ => if reg.adc_rd_req = '1' then next_reg.state <= FETCH_ADC_0; elsif reg.dim_rd_req = '1' then next_reg.state <= FETCH_DIM; else next_reg.state <= RD_CHECK; end if; when FETCH_ADC_0 => if tmr_busy = '0' then tmr_rd_en <= '1'; tmr_addr <= std_ulogic_vector(adc_req_base_addr & (unsigned(idx_i) + unsigned(adc_addr_i)) & '0'); next_reg.state <= STORE_ADC_0; end if; when STORE_ADC_0 => if tmr_data_en = '1' then next_reg.adc_data(15 downto 0) <= tmr_data_out; next_reg.state <= FETCH_ADC_1; end if; when FETCH_ADC_1 => if tmr_busy = '0' then tmr_rd_en <= '1'; tmr_addr <= std_ulogic_vector(adc_req_base_addr & (unsigned(idx_i) + unsigned(adc_addr_i)) & '1'); next_reg.state <= STORE_ADC_1; end if; when STORE_ADC_1 => if tmr_data_en = '1' then next_reg.adc_data(23 downto 16) <= tmr_data_out(7 downto 0); next_reg.adc_data_en <= '1'; end if; if adc_rd_en_i = '1' then next_reg.state <= FETCH_ADC_0; elsif adc_done_i = '1' then next_reg.state <= RD_CHECK; next_reg.adc_rd_req <= '0'; end if; when FETCH_DIM => if tmr_busy = '0' then tmr_rd_en <= '1'; tmr_addr <= std_ulogic_vector((dim_base_addr_c(18 downto 2) + unsigned(idx_i) + unsigned(dim_addr_i(4 downto 2)))) & dim_addr_i(1 downto 0); next_reg.state <= STORE_DIM; end if; when STORE_DIM => if tmr_data_en = '1' then next_reg.dim_data <= tmr_data_out; next_reg.dim_data_en <= '1'; end if; if dim_rd_en_i = '1' then next_reg.state <= FETCH_DIM; elsif dim_done_i = '1' then next_reg.state <= RD_CHECK; next_reg.dim_rd_req <= '0'; end if; end case; end process comb; end architecture rtl;

mit

87c66b48a37a7cf786c4a6f3236bb55e

malkadi/FGPU

RTL/floating_point/uitofp.vhd

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY uitofp IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END uitofp; ARCHITECTURE uitofp_arch OF uitofp IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF uitofp_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_2 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_2; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_2 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 1, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 0, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 0, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 0, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 5, C_OPTIMIZATION => 1, C_MULT_USAGE => 0, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 0, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 1 ) PORT MAP ( aclk => aclk, aclken => '1', aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => '0', s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END uitofp_arch;

gpl-3.0

0544ef946024f027aed5e25cfe6a8d04

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_priority_decoder.vhd

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gpl-2.0

3846a774fb524106e9a9f484ca7fbef0

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_prod_bytes_retriever.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_prod_bytes_retriever | -- | --------------------------------------------------------------------------------------------------- -- File wf_prod_bytes_retriever.vhd | -- | -- Description After an ID_DAT frame requesting for a variable to be produced, the unit provides | -- to the wf_tx_serializer unit one by one, all the bytes of data needed for the | -- RP_DAT frame (apart from the FSS, FCS and FES bytes). The coordination of the | -- retrieval is done through the wf_engine_control and the signal byte_index_i. | -- | -- General structure of a produced RP_DAT frame: | -- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|_LGTH_|_...User-Data..._|_nstat_|__MPS__||____FCS____|__FES__| | -- | -- Data provided by the this unit: | -- ______ _______ ______ _________________ _______ _______ | -- |_CTRL_||__PDU__|_LGTH_|_...User-Data..._|_nstat_|__MPS__|| | -- | -- If the variable to be produced is the | -- o presence : The unit retreives the bytes from the WF_PACKAGE. | -- No MPS & no nanoFIP status are associated with this variable. | -- ______ _______ ______ ______ ______ ______ ______ ______ | -- |_CTRL_||__PDU__|__05__|__80__|__03__|__00__|__F0__|__00__|| | -- | -- | -- o identification: The unit retreives the Constructor & Model bytes from the | -- wf_model_constr_decoder, & all the rest from the WF_PACKAGE. | -- No MPS & no nanoFIP status are associated with this variable. | -- ______ _______ ______ ______ ______ ______ ______ _______ ______ ______ ______ | -- |_CTRL_||__PDU__|__08__|__01__|__00__|__00__|_cons_|__mod__|__00__|__00__|__00__|| | -- | -- | -- o var_3 : If the operation is in stand-alone mode, the unit retreives | -- the user-data bytes from the "nanoFIP User Interface, NON- | -- WISHBONE" bus DAT_I. | -- If it is in memory mode,it retreives them from the Produced RAM -- The MPS and the nanoFIP status bytes are retrieved from the | -- wf_status_bytes_gen. | -- The LGTH byte is retrieved from the wf_prod_data_lgth_calc. | -- The rest of the bytes (CTRL & PDU) come from the WF_PACKAGE. | -- ______ _______ ______ ________________________________________ _______ _______ | -- |_CTRL_||__PDU__|_LGTH_|_____________..User-Data..______________|_nstat_|__MPS__|| | -- | -- | -- o var_5 : Regardless of the operational mode or the P3_LGTH, the unit | -- sends 1 user-data byte coming from the wf_jtag_controller. | -- The nanoFIP status is always sent regardless of the NOSTAT | -- input. The MPS, LGTH, CTRL, PDU_TYPE bytes are retrived in | -- the same way as for a var_3. | -- | -- ______ _______ ______ ________ _______ _______ | -- |_CTRL_||__PDU__|_LGTH_|_jc_tdo_|_nstat_|__MPS__|| | -- | -- | -- Authors Pablo Alvarez Sanchez ([email protected]) | -- Evangelia Gousiou ([email protected]) | -- Date 04/01/2011 | -- Version v0.05 | -- Depends on wf_reset_unit | -- wf_wb_controller | -- wf_engine_control | -- wf_prod_permit | -- wf_status_bytes_gen | -- wf_model_constr_dec | -- wf_jtag_controller | ---------------- | -- Last changes | -- 06/2010 v0.02 EG subs_i is not sent in the RP_DAT frames | -- signal s_wb_we includes the wb_stb_r_edge_p_i | -- cleaner structure | -- 06/2010 v0.03 EG signal s_mem_byte was not in sensitivity list in v0.01! by adding it | -- changes were essential in the timing of the tx (wf_osc, wf_tx, | -- wf_engine_control and the configuration of the memory needed changes) | -- 11/2010 v0.04 EG for simplification, new unit Slone_Data_Sampler created | -- 4/1/2011 v0.05 EG unit renamed from wf_prod_bytes_to_tx to wf_prod_bytes_retriever; | -- input byte_being_sent_p_i added, so that the reseting of status bytes | -- does not pass from the engine; clening-up+commenting | -- 2/2011 v0.051 EG wf_prod_bytes_from_dati unit removed. | -- 6/2011 v0.051 EG added jc var treatment. | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_prod_bytes_retriever --================================================================================================= entity wf_prod_bytes_retriever is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock nostat_i : in std_logic; -- if negated, nFIP status is sent slone_i : in std_logic; -- stand-alone mode -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP User Interface, WISHBONE Slave wb_clk_i : in std_logic; -- WISHBONE clock wb_adr_i : in std_logic_vector (8 downto 0); -- WISHBONE address to memory wb_data_i : in std_logic_vector (7 downto 0); -- WISHBONE data bus -- Signal from the wf_wb_controller wb_ack_prod_p_i : in std_logic; -- WISHBONE acknowledge -- latching moment of wb_data_i -- nanoFIP User Interface, NON WISHBONE slone_data_i : in std_logic_vector (15 downto 0); -- input data bus for slone mode -- Signals from the wf_engine_control unit byte_index_i : in std_logic_vector (7 downto 0); --index of the byte to be retrieved byte_being_sent_p_i : in std_logic; -- pulse on the beginning of the -- delivery of a new byte data_lgth_i : in std_logic_vector (7 downto 0); -- # bytes of the Conrol&Data fields -- of the RP_DAT frame; includes: -- 1 byte RP_DAT.CTRL, -- 1 byte RP_DAT.Data.PDU_type, -- 1 byte RP_DAT.Data.LGTH -- several bytes of RP_DAT.Data, and -- if applicable 1 byte RP_DAT.Data.MPS_status & -- 1 byte RP_DAT.Data.nanoFIP_status var_i : in t_var; --variable type that is being treated -- Signals from the wf_prod_permit var3_rdy_i : in std_logic; -- nanoFIP output VAR3_RDY -- Signals from the wf_status_bytes_gen mps_status_byte_i : in std_logic_vector (7 downto 0); -- MPS status byte nFIP_status_byte_i : in std_logic_vector (7 downto 0); -- nanoFIP status byte -- Signals from the wf_model_constr_dec unit constr_id_dec_i : in std_logic_vector (7 downto 0); -- decoded constructor id settings model_id_dec_i : in std_logic_vector (7 downto 0); -- decoded model id settings -- Signals from the wf_jtag_controller unit jc_tdo_byte_i : in std_logic_vector (7 downto 0); -- sampled JC_TDO -- OUTPUTS -- Signal to the wf_status_bytes_gen rst_status_bytes_p_o : out std_logic; -- reset for the nanoFIP&MPS status -- status bytes.It is activated after -- the delivery of the last one (MPS) -- Signal to the wf_tx_serializer byte_o : out std_logic_vector (7 downto 0));-- output byte to be serialized end entity wf_prod_bytes_retriever; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_prod_bytes_retriever is -- addressing the memory signal s_base_addr, s_mem_addr_offset : unsigned (8 downto 0); signal s_mem_addr_A : std_logic_vector (8 downto 0); -- index of byte to be sent signal s_byte_index_d1 : std_logic_vector (7 downto 0); signal s_byte_index_d_aux : integer range 0 to 15; -- data bytes signal s_mem_byte, s_slone_byte : std_logic_vector (7 downto 0); signal s_slone_bytes : std_logic_vector (15 downto 0); -- Length byte signal s_lgth_byte : std_logic_vector (7 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Memory mode Produced RAM -- -- Storage (by the user) & retrieval (by the unit) of produced bytes -- --------------------------------------------------------------------------------------------------- -- Instantiation of a 512 x 8 Produced Dual Port RAM. -- Port A is used by the nanoFIP for the readings from the Produced RAM; -- Port B is connected to the WISHBONE interface for the writings from the user. -- Note: only 124 bytes are used. Produced_Bytes_From_RAM: wf_dualram_512x8_clka_rd_clkb_wr port map( clk_porta_i => uclk_i, -- 40 MHz clock addr_porta_i => s_mem_addr_A, -- address of byte to be read from memory clk_portb_i => wb_clk_i, -- WISHBONE clock addr_portb_i => wb_adr_i, -- address of byte to be written data_portb_i => wb_data_i, -- byte to be written write_en_portb_i => wb_ack_prod_p_i, -- WISHBONE write enable ----------------------------------------- data_porta_o => s_mem_byte); -- output byte read ----------------------------------------- --------------------------------------------------------------------------------------------------- -- Slone mode DAT_I bus Sampling -- -- retrieval of the two bytes to be produced -- --------------------------------------------------------------------------------------------------- -- Sampling of the input data bus DAT_I(15:0) for the operation in stand-alone mode. -- The sampling takes place on the 1st clock cycle after the VAR3_RDY has been de-asserted. Sample_DAT_I_bus: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_slone_bytes <= (others=>'0'); else if var3_rdy_i = '1' then -- data latching s_slone_bytes <= slone_data_i; end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s_slone_byte <= s_slone_bytes(7 downto 0) when byte_index_i = c_1st_DATA_BYTE_INDEX else s_slone_bytes(15 downto 8); --------------------------------------------------------------------------------------------------- -- Bytes Generation -- --------------------------------------------------------------------------------------------------- -- Combinatorial process Bytes_Generation: Generation of bytes for the CTRL and Data fields of an -- RP_DAT frame: If the variable requested in the ID_DAT is of "produced" type (identification/ -- presence/ var3/ var5) the process prepares accordingly, one by one, bytes of data to be sent. -- The pointer "s_byte_index_d1" (or "s_byte_index_d_aux") indicates which byte of the frame is to be sent. -- Some of the bytes are defined in the WF_PACKAGE, -- the rest come either from the memory (if slone = 0) or from the the input bus DAT_I (if slone = 1), -- or from the wf_status_bytes_gen or the wf_model_constr_decoder units. -- The output byte "byte_o" is sent to the wf_tx_serializer unit for manchester encoding and serialization. Bytes_Generation: process (var_i, s_byte_index_d1, data_lgth_i, constr_id_dec_i, model_id_dec_i, nFIP_status_byte_i, mps_status_byte_i, s_slone_byte, s_byte_index_d_aux, s_mem_byte, nostat_i, byte_being_sent_p_i, s_lgth_byte, slone_i, jc_tdo_byte_i) begin -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- generation of bytes according to the type of produced var: case var_i is -- case: presence variable -- all the bytes for the RP_DAT.CTRL and RP_DAT.Data fields are predefined -- in the c_VARS_ARRAY matrix. when var_presence => byte_o <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).byte_array(s_byte_index_d_aux); s_base_addr <= (others => '0'); rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- case: identification variable -- The Constructor and Model bytes of the identification variable arrive from the -- wf_model_constr_decoder, wereas all the rest are predefined in the c_VARS_ARRAY matrix. when var_identif => if s_byte_index_d1 = c_CONSTR_BYTE_INDEX then byte_o <= constr_id_dec_i; elsif s_byte_index_d1 = c_MODEL_BYTE_INDEX then byte_o <= model_id_dec_i; else byte_o <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).byte_array(s_byte_index_d_aux); end if; s_base_addr <= (others => '0'); rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- case: variable 3 -- For a var_3 there is a separation according to the operational mode (stand-alone or memory) -- In general, few of the bytes are predefined in the c_VARS_ARRAY matrix, whereas the rest come -- either from the memory/ DAT_I bus or from wf_status_bytes_generator unit. when var_3 => --------------------------------------------------------------------------------------------- -- In memory mode: if slone_i = '0' then -- retrieval of base address info for the memory from the WF_PACKAGE s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_addr; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The first (CTRL) and second (PDU_TYPE) bytes to be sent -- are predefined in the c_VARS_ARRAY matrix of the WF_PACKAGE if unsigned(s_byte_index_d1) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_d_aux); rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The &c_LGTH_BYTE_INDEX byte is the Length elsif s_byte_index_d1 = c_LGTH_BYTE_INDEX then byte_o <= s_lgth_byte; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- If the nostat_i is negated, the one but last byte is the nanoFIP status byte elsif (unsigned(s_byte_index_d1) = (unsigned(data_lgth_i)-1 )) and nostat_i = '0' then byte_o <= nFIP_status_byte_i; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The last byte is the MPS status elsif s_byte_index_d1 = (data_lgth_i) then byte_o <= mps_status_byte_i; rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes; -- the reset arrives after the delivery -- of the MPS byte to the wf_tx_serializer -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rest of the bytes come from the memory else byte_o <= s_mem_byte; rst_status_bytes_p_o <= '0'; end if; --------------------------------------------------------------------------------------------- -- In stand-alone mode: else s_base_addr <= (others => '0'); -- no memory access needed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The first (CTRL) and second (PDU_TYPE) bytes to be sent -- are predefined in the c_VARS_ARRAY matrix of the WF_PACKAGE if unsigned(s_byte_index_d1) <= c_VARS_ARRAY(c_VAR_3_INDEX).array_lgth then -- less or eq byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_d_aux); rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The &c_LGTH_BYTE_INDEX byte is the Length elsif s_byte_index_d1 = c_LGTH_BYTE_INDEX then byte_o <= s_lgth_byte; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- If the nostat_i is negated, the one but last byte is the nanoFIP status byte elsif unsigned(s_byte_index_d1) = (unsigned(data_lgth_i)-1 ) and nostat_i = '0' then byte_o <= nFIP_status_byte_i; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The last byte is the MPS status elsif s_byte_index_d1 = data_lgth_i then byte_o <= mps_status_byte_i; rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes. -- The reset arrives after having sent the -- MPS byte to the wf_tx_serializer. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rest of the bytes come from the input bus DAT_I(15:0) else byte_o <= s_slone_byte; rst_status_bytes_p_o <= '0'; end if; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- case: jtag produced variable var_5 -- For a var_5 the 1 user-data byte comes from the wf_jtag_controller unit. -- The nanoFIP status byte comes from the wf_status_bytes_gen and it is always sent, regardless -- of the NOSTAT input. The MPS byte is also coming from the wf_status_bytes_gen. -- The rest of the bytes come from the WF_PACKAGE. when var_5 => s_base_addr <= (others => '0'); -- no memory access needed -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The &c_LGTH_BYTE_INDEX byte is the Length if s_byte_index_d1 = c_LGTH_BYTE_INDEX then byte_o <= s_lgth_byte; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The first and only data byte comes from the JATG_controller elsif s_byte_index_d1 = c_1st_DATA_BYTE_INDEX then byte_o <= jc_tdo_byte_i; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The one but last byte is the nanoFIP status byte elsif unsigned(s_byte_index_d1) = (unsigned(data_lgth_i)-1 ) then byte_o <= nFIP_status_byte_i; rst_status_bytes_p_o <= '0'; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The last byte is the MPS status elsif s_byte_index_d1 = data_lgth_i then byte_o <= mps_status_byte_i; rst_status_bytes_p_o <= byte_being_sent_p_i; -- reset signal for both status bytes. -- The reset arrives after having sent the -- MPS byte to the wf_tx_serializer. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The rest of the bytes (the very first one, CTRL, and the second one, PDU_TYPE) are -- predefined in the c_VARS_ARRAY matrix of the WF_PACKAGE else byte_o <= c_VARS_ARRAY(c_VAR_5_INDEX).byte_array(s_byte_index_d_aux); rst_status_bytes_p_o <= '0'; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when others => rst_status_bytes_p_o <= '0'; byte_o <= (others => '0'); s_base_addr <= (others => '0'); end case; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Synchronous process Delay_byte_index_i: in the combinatorial process Bytes_Generation, -- according to the value of the signal s_byte_index_d1, a byte is retrieved either from the memory, -- or from the WF_PACKAGE or from the wf_status_bytes_gen or wf_model_constr_decoder units. -- Since the memory needs one clock cycle to output its data (as opposed to the other units that -- have them ready) the signal s_byte_index_d1 has to be a delayed version of the byte_index_i -- (byte_index_i is the signal used as address for the mem; s_byte_index_d1 is the delayed one -- used for the other units). Delay_byte_index_i: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_byte_index_d1 <= (others => '0'); else s_byte_index_d1 <= byte_index_i; -- index of byte to be sent end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Auxiliary signals -- --------------------------------------------------------------------------------------------------- s_mem_addr_A <= std_logic_vector (s_base_addr + s_mem_addr_offset - 1); -- address of the byte to be read from memory: base_address(from WF_PACKAGE) + byte_index_i - 1 -- (the -1 is because the byte_index_i counts also the CTRL byte, that is not part of the -- memory; for example when byte_index_i is 3 which means that the CTRL, PDU_TYPE and LGTH -- bytes have preceded and a byte from the memory is now requested, the byte from the memory cell -- 2 (00000010) has to be retrieved). s_mem_addr_offset <= (resize((unsigned(byte_index_i)), s_mem_addr_offset'length)); s_byte_index_d_aux <= (to_integer(unsigned(s_byte_index_d1(3 downto 0)))); -- index of byte to be sent(range restricted) -- used to retreive bytes from the matrix -- c_VARS_ARRAY.byte_array, with a predefined -- width of 15 bytes s_lgth_byte <= std_logic_vector (resize((unsigned(data_lgth_i)-2),byte_o'length)); -- represents the RP_DAT.Data.LGTH byte -- it includes the # bytes of user-data -- (P3_LGTH) plus 1 byte of MPS_status -- plus 1 byte of nanoFIP_status, if -- applicable. It does not include the -- CTRL byte and itself. end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

b0c8e6135dc9132f43f75d89e0e51f64

Kinxil/VHDL_Projects

Mandelbrot/increment.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.CONSTANTS.all; use work.CONFIG_MANDELBROT.all; use WORK.FUNCTIONS.ALL; use IEEE.NUMERIC_STD.ALL; entity increment is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; start : in STD_LOGIC; x_start : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); y_start : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); step : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); y : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x2 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x3 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x4 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x5 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x6 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x7 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); x8 : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0); stop : out std_logic); end increment; architecture Behavioral of increment is signal xs, ys : signed(XY_RANGE-1 downto 0); signal xcount : integer range 0 to XRES-1:=0; signal ycount : integer range 0 to YRES-1:=0; begin process(clock, reset,start,x_start,y_start,step) begin if reset='1' then xcount<=0; ycount<=0; xs<= signed(x_start); ys<= signed(y_start); stop<='0'; elsif rising_edge(clock) then if(start='1') then if xcount >= XRES-8 then if ycount >= YRES-1 then xcount <= 0; ycount <= 0; xs<=signed(x_start); ys<=signed(y_start); stop<='1'; else xcount <= 0; ycount <= ycount+1; ys<=ys+signed(step); xs<=signed(x_start); stop<='0'; end if; else stop<='0'; xs<=xs+(signed(step) sll 3); xcount<=xcount+8; end if; end if; end if; end process; x<=std_logic_vector(xs); y<=std_logic_vector(ys); x2 <= std_logic_vector(xs + signed(step)); x3 <= std_logic_vector(xs + mult(signed(step),X"20000000",FIXED)); x4 <= std_logic_vector(xs + mult(signed(step),X"30000000",FIXED)); x5 <= std_logic_vector(xs + mult(signed(step),X"40000000",FIXED)); x6 <= std_logic_vector(xs + mult(signed(step),X"50000000",FIXED)); x7 <= std_logic_vector(xs + mult(signed(step),X"60000000",FIXED)); x8 <= std_logic_vector(xs + mult(signed(step),X"70000000",FIXED)); end Behavioral;

gpl-3.0

68b614bce376683209dcf4cf755249c7

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_cons_bytes_processor.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_cons_bytes_processor | -- | --------------------------------------------------------------------------------------------------- -- File wf_cons_bytes_processor.vhd | -- | -- Description The unit is consuming the RP_DAT data bytes that are arriving from the | -- wf_fd_receiver, according to the following: | -- | -- o If the variable identifier of the preceded ID_DAT was: | -- | -- var_1 or var_2 | -- - If the operation is in memory mode : the unit is registering the | -- application-data bytes along with the PDU_TYPE, LGTH and MPS bytes in the | -- Consumed or Broadcast Consumed memories | -- - If the operation is in stand-alone mode: the unit is transferring the 2 appli-| -- cation-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O| -- | -- o var_rst | -- the two application-data bytes are identified and sent to the wf_reset_unit. | -- | -- o var_5 | -- regardless of the operational mode (memory or slone) the unit is registering | -- the application-data bytes along with the PDU_TYPE, LGTH and MPS bytes in the | -- JC_consumed memory. | -- | -- Note: The validity of the consumed bytes (stored in the memories or transfered | -- to DATO or transfered to the wf_reset_unit) is indicated by the "nanoFIP User | -- Interface, NON_WISHBONE" signals VAR1_RDY/ VAR2_RDY or the nanoFIP internal | -- signals rst_nFIP_and_FD_p/ assert_RSTON_p/ start_jc_i, which are treated in | -- the wf_cons_outcome unit and are assessed after the end of the reception of a | -- complete frame. | -- | -- Reminder: | -- | -- Consumed RP_DAT frame structure : | -- ___________ ______ _______ ________ __________________ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|__LGTH__|__..ApplicData..__|__MPS__||____FCS____|__FES__| | -- | -- |--------&LGTH bytes-------| | -- |--------write to Consumed memories---------| | -- |-----to DAT_O-----| | -- |---to Reset Unit--| | -- | -- Authors Pablo Alvarez Sanchez ([email protected]) | -- Evangelia Gousiou ([email protected]) | -- Date 15/12/2010 | -- Version v0.03 | -- Depends on wf_reset_unit | -- wf_fd_receiver | -- wf_engine_control | ---------------- | -- Last changes | -- 11/09/2009 v0.01 EB First version | -- 09/2010 v0.02 EG Treatment of reset variable added; Bytes_Transfer_To_DATO unit | -- creation for simplification; Signals renamed; | -- CTRL, PDU_TYPE, LGTH bytes registered; | -- Code cleaned-up & commented. | -- 15/12/2010 v0.03 EG Unit renamed from wf_cons_bytes_from_rx to wf_cons_bytes_processor | -- byte_ready_p comes from the rx_deserializer (no need to pass from | -- the engine) Code cleaned-up & commented (more!) | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------- | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_cons_bytes_processor --================================================================================================= entity wf_cons_bytes_processor is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock slone_i : in std_logic; -- stand-alone mode (active high) -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP User Interface, WISHBONE Slave wb_clk_i : in std_logic; -- WISHBONE clock wb_adr_i : in std_logic_vector (8 downto 0); -- WISHBONE address to memory -- Signals from the wf_fd_receiver unit byte_i : in std_logic_vector (7 downto 0); -- input byte byte_ready_p_i : in std_logic; -- indication of a new input byte -- Signals from the wf_engine_control unit byte_index_i : in std_logic_vector (7 downto 0); -- index of a byte inside the frame; -- starting from 0, it counts all the -- bytes after the FSS&before the FES var_i : in t_var; -- variable type that is being treated -- Signals from the wf_jtag_controller unit jc_mem_adr_rd_i : in std_logic_vector (8 downto 0); -- address of byte to be read and -- transferred to the wf_jtag _controller -- OUTPUTS -- nanoFIP User Interface, WISHBONE Slave output -- MODIFIED was (15 downto 0) data_o : out std_logic_vector (7 downto 0); -- data out bus -- Signals to the wf_jtag_controller unit jc_mem_data_o : out std_logic_vector (7 downto 0); -- byte to be transferred to the wf_jtag _controller -- Signals to the wf_cons_outcome unit cons_ctrl_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT CTRL byte cons_lgth_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT LGTH byte cons_pdu_byte_o : out std_logic_vector (7 downto 0); -- received RP_DAT PDY_TYPE byte cons_var_rst_byte_1_o : out std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 1st data byte cons_var_rst_byte_2_o : out std_logic_vector (7 downto 0)); -- received var_rst RP_DAT, 2nd data byte end entity wf_cons_bytes_processor; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_cons_bytes_processor is -- addressing the memory signal s_base_adr : unsigned (8 downto 0); signal s_adr : std_logic_vector (8 downto 0); -- bus/ memories write enable signal s_slone_wr_en_p : std_logic_vector (1 downto 0); signal s_mem_wr_en_p : std_logic; signal s_jc_mem_wr_en_p : std_logic; -- data bytes signal s_slone_data_out : std_logic_vector (15 downto 0); signal s_mem_data_out : std_logic_vector (7 downto 0); -- Length byte signal s_cons_lgth_byte : std_logic_vector (7 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Memory mode Consumed & Consumed Broadcast RAM -- -- Storage (by the unit) & retrieval (by the user) of consumed bytes -- --------------------------------------------------------------------------------------------------- -- Instantiation of a 512 x 8 Dual Port RAM, for both the consumed and consumed broadcast vars -- Port A is connected to the WISHBONE interface for the readings from the user -- Port B is used by the nanoFIP for the writings into the memory Consumption_RAM : wf_dualram_512x8_clka_rd_clkb_wr port map( clk_porta_i => wb_clk_i, -- WISHBONE clock addr_porta_i => wb_adr_i, -- address of byte to be read clk_portb_i => uclk_i, -- 40 MHz clock addr_portb_i => s_adr, -- address of byte to be written data_portb_i => byte_i, -- byte to be written write_en_portb_i => s_mem_wr_en_p, -- write enable -------------------------------------------- data_porta_o => s_mem_data_out); -- output byte read -------------------------------------------- --------------------------------------------------------------------------------------------------- -- JTAG Consumed RAM -- -- Storage (by this unit) & retrieval (by the JTAG_controller unit) of consumed bytes -- --------------------------------------------------------------------------------------------------- -- Instantiation of a 512 x 8 Dual Port RAM for the storage of var_4 variables. -- nanoFIP's user clock uclk is connected to both ports of the memory; the writing of the -- consumed data and the reading of them (by the wf_jtag_controller) take place internally. -- Note: only 127 bytes are used. Consumption_JTAG_RAM : wf_dualram_512x8_clka_rd_clkb_wr port map( clk_porta_i => uclk_i, -- user clock addr_porta_i => jc_mem_adr_rd_i, -- address of byte to be read clk_portb_i => uclk_i, -- 40 MHz clock addr_portb_i => s_adr, -- address of byte to be written data_portb_i => byte_i, -- byte to be written write_en_portb_i => s_jc_mem_wr_en_p, -- write enable -------------------------------------------- data_porta_o => jc_mem_data_o); -- output byte read -------------------------------------------- --------------------------------------------------------------------------------------------------- -- Slone mode Storage of consumed bytes to DATO -- --------------------------------------------------------------------------------------------------- -- Synchronous process Data_Transfer_To_Dat_o: In stand-alone mode, according to the signal -- s_slone_wr_en_p, the first or second byte of the "User Interface, NON WISHBONE" bus DAT_O -- takes the byte byte_i. Data_Transfer_To_Dat_o: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then -- bus initialization s_slone_data_out <= (others => '0'); else if s_slone_wr_en_p(0) = '1' then -- the 1st byte is transfered in the lsb of the bus s_slone_data_out(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives -- (or until a reset!) end if; if s_slone_wr_en_p(1) = '1' then -- the 2nd byte is transfered in the msb of the bus s_slone_data_out(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives -- (or until a reset!) end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- In stand-alone mode the 16 bits DAT_O fills up with the s_slone_data_out. -- In memory mode,the lsb of DAT_O contains the output of the reading of the consumed memory -- MODIFIED -- data_o <= s_slone_data_out when slone_i = '1' else "00000000" & s_mem_data_out; data_o <= s_mem_data_out; --------------------------------------------------------------------------------------------------- -- Bytes Processing -- --------------------------------------------------------------------------------------------------- -- Combinatorial process Bytes_Processing: Data bytes are consumed according to the -- variable type (var_1, var_2, var_rst, var_4) they belong to. -- In memory and in stand-alone mode, bytes are consumed even if any of the CTRL, PDU_TYPE, -- LGTH, CRC or FES bytes of the consumed RP_DAT frame are incorrect. -- It is the VAR_RDY signal that signals the user for the validity of the consumed data. -- The treatment of a var_1 or a var_2 in memory mode is identical to the treatment of a var_5; -- it is only the addresses of the memories that differ. The incoming bytes (byte_i) after the CTRL -- byte and before the CRC bytes, are written in the memory one by one as they arrive, on the -- moments indicated by the byte_ready_p_i pulses. -- To distinguish the CTRL and the CRC bytes from the rest, the signals byte_index_i and LGTH -- (s_cons_lgth_byte) are used: -- o the CTRL byte arrives when byte_index_i = 0 -- o the CRC bytes arrive &LGTH bytes after the LGTH byte. -- Note: the byte_index_i signal coming from the wf_engine_control is counting each byte after the -- FSS and before the FES. -- the LGTH byte (s_cons_lgth_byte) is received when byte_index_i is equal to 3 and -- indicates the amount of bytes in the frame after the CTRL, PDU_TYPE and itself and -- before the CRC. -- In stand-alone mode, in total two bytes of data have to be transferred to the DAT_O bus. The -- process manages the signal slone_write_byte_p which indicates on which one of the bytes of the -- bus (msb: 15 downto 8 or lsb: 7 downto 0) the new incoming byte has to be written. -- In memory and in stand-alone mode, if the consumed variable is the var_rst the process latches -- the first and second data bytes. s_adr <= std_logic_vector (unsigned(byte_index_i)+s_base_adr - 1); -- memory address of -- the byte to be written -- (-1 bc the CTRL -- byte is not written) Bytes_Processing: process (var_i,byte_index_i,slone_i, byte_i, byte_ready_p_i,s_cons_lgth_byte) begin case var_i is -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when var_1 => cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); s_jc_mem_wr_en_p <= '0'; s_base_adr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_addr;-- base address -- from WF_PACKAGE -- -- -- -- -- -- -- -- -- -- -- -- -- in memory mode if slone_i = '0' then s_slone_wr_en_p <= (others => '0'); if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits if byte_index_i > c_LGTH_BYTE_INDEX then -- after the reception -- of the LGTH byte if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then -- less or eq s_mem_wr_en_p <= byte_ready_p_i; -- &LGTH amount of -- bytes are written --(to avoid writing CRC!) else s_mem_wr_en_p <= '0'; end if; else -- before the reception s_mem_wr_en_p <= byte_ready_p_i; -- of the LGTH byte end if; -- all the bytes (after -- CTRL) are written else s_mem_wr_en_p <= '0'; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- in stand-alone mode else -- slone_i = '1' then s_mem_wr_en_p <= '0'; if byte_index_i = c_1st_DATA_BYTE_INDEX then -- 1st byte to be transferred s_slone_wr_en_p <= '0'& byte_ready_p_i; elsif byte_index_i = c_2nd_DATA_BYTE_INDEX then -- 2nd byte to be transferred s_slone_wr_en_p <= byte_ready_p_i & '0'; else s_slone_wr_en_p <= (others=>'0'); end if; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when var_2 => -- same treatment as var 1 on a different memory location (base_addr) cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); s_jc_mem_wr_en_p <= '0'; s_base_adr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_addr; -- -- -- -- -- -- -- -- -- -- -- -- -- in memory mode if slone_i = '0' then s_slone_wr_en_p <= (others => '0'); if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then if byte_index_i > c_LGTH_BYTE_INDEX then if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then s_mem_wr_en_p <= byte_ready_p_i; else s_mem_wr_en_p <= '0'; end if; else s_mem_wr_en_p <= byte_ready_p_i; end if; else s_mem_wr_en_p <= '0'; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- stand-alone mode does not treat consumed broadcast vars else s_mem_wr_en_p <= '0'; s_slone_wr_en_p <= (others => '0'); end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when var_rst => s_mem_wr_en_p <= '0'; -- no writing in memory or DAT_O for the var_rst s_jc_mem_wr_en_p <= '0'; s_slone_wr_en_p <= (others => '0'); s_base_adr <= (others => '0'); if (byte_ready_p_i = '1') and (byte_index_i = c_1st_DATA_BYTE_INDEX) then -- 1st byte cons_var_rst_byte_1_o <= byte_i; cons_var_rst_byte_2_o <= (others => '0'); elsif (byte_ready_p_i='1') and (byte_index_i = c_2nd_DATA_BYTE_INDEX) then -- 2nd byte cons_var_rst_byte_2_o <= byte_i; cons_var_rst_byte_1_o <= (others => '0'); else cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when var_4 => cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); s_slone_wr_en_p <= (others => '0'); s_mem_wr_en_p <= '0'; s_base_adr <= c_VARS_ARRAY(c_VAR_4_INDEX).base_addr;-- base address -- from WF_PACKAGE -- -- -- -- -- -- -- -- -- -- -- -- if (unsigned(byte_index_i)> 0 and unsigned(byte_index_i)< 127) then -- memory limits if byte_index_i > c_LGTH_BYTE_INDEX then -- after the reception -- of the LGTH byte if unsigned(byte_index_i) <= unsigned(s_cons_lgth_byte) + 2 then -- less or eq s_jc_mem_wr_en_p <= byte_ready_p_i; -- &LGTH amount of -- bytes are written --(to avoid writing CRC!) else s_jc_mem_wr_en_p <= '0'; end if; else -- before the reception s_jc_mem_wr_en_p <= byte_ready_p_i; -- of the LGTH byte end if; -- all the bytes (after -- CTRL) are written else s_jc_mem_wr_en_p <= '0'; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- when others => s_base_adr <= (others => '0'); s_mem_wr_en_p <= '0'; s_jc_mem_wr_en_p <= '0'; s_slone_wr_en_p <= (others => '0'); cons_var_rst_byte_1_o <= (others => '0'); cons_var_rst_byte_2_o <= (others => '0'); end case; end process; --------------------------------------------------------------------------------------------------- -- CTRL, PDU_TYPE, LGTH bytes -- --------------------------------------------------------------------------------------------------- -- Synchronous process Register_CTRL_PDU_LGTH_bytes: Storage of the CTRL, PDU_TYPE -- and LGTH bytes of an incoming RP_DAT frame. The bytes are sent to the wf_cons_outcome -- unit that validates them and accordingly activates the: -- VAR1_RDY, for a var_1, -- VAR2_RDY, for a var_2, -- assert_rston_p & rst_nfip_and_fd_p, for a var_rst, -- jc_start_p, for a var_4. Register_CTRL_PDU_LGTH_bytes: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then cons_ctrl_byte_o <= (others => '0'); cons_pdu_byte_o <= (others => '0'); s_cons_lgth_byte <= (others => '0'); else if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_4)then -- only for consumed vars if (byte_index_i = c_CTRL_BYTE_INDEX) and (byte_ready_p_i='1') then cons_ctrl_byte_o <= byte_i; elsif (byte_index_i = c_PDU_BYTE_INDEX) and (byte_ready_p_i ='1') then cons_pdu_byte_o <= byte_i; elsif (byte_index_i = c_LGTH_BYTE_INDEX) and (byte_ready_p_i ='1') then s_cons_lgth_byte <= byte_i; end if; else cons_ctrl_byte_o <= (others => '0'); cons_pdu_byte_o <= (others => '0'); s_cons_lgth_byte <= (others => '0'); end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- cons_lgth_byte_o <= s_cons_lgth_byte; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

104b5b6f84715b4488b2605f04c83f54

mohamed/fsl_perf_counter

hw/perf_counter_v1_00_a/hdl/vhdl/perf_counter.vhd

-- Performance Counter for MicroBlaze -- Author: Mohamed A. Bamakhrama <[email protected]> -- Copyrights (c) 2010 by Universiteit Leiden library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity perf_counter is generic ( C_NUM_OF_COUNTERS : integer := 4; C_LOG2_NUM_OF_COUNTERS : integer := 2; C_EXT_RESET_HIGH : integer := 1 ); port ( FSL_Clk : in std_logic; FSL_Rst : in std_logic; FSL_S_Clk : out std_logic; FSL_S_Read : out std_logic; FSL_S_Data : in std_logic_vector(0 to 31); FSL_S_Control : in std_logic; FSL_S_Exists : in std_logic; FSL_M_Clk : out std_logic; FSL_M_Write : out std_logic; FSL_M_Data : out std_logic_vector(0 to 31); FSL_M_Control : out std_logic; FSL_M_Full : in std_logic ); end perf_counter; architecture rtl of perf_counter is constant MSB_OP : integer := 31; constant LSB_OP : integer := 29; constant MSB_ID : integer := 28; constant LSB_ID : integer := 28-C_LOG2_NUM_OF_COUNTERS+1; constant RST_ALL : std_logic_vector(0 to 2) := "000"; constant RST_ID : std_logic_vector(0 to 2) := "001"; constant START_ID : std_logic_vector(0 to 2) := "010"; constant STOP_ID : std_logic_vector(0 to 2) := "011"; constant READ_ID : std_logic_vector(0 to 2) := "100"; -- 64-bit counter @ 100MHz = > 5800 years -- This eliminates the need for handling overflows type counter_t is array(1 to C_NUM_OF_COUNTERS) of std_logic_vector(0 to 63); signal counter : counter_t; type op_t is (idle, running, reset, rd); type op_array_t is array(1 to C_NUM_OF_COUNTERS) of op_t; signal op_r : op_array_t; signal op_i : op_array_t; subtype id_int_t is integer range 0 to C_NUM_OF_COUNTERS; signal rd_id_r : id_int_t; signal rd_id_i : id_int_t; signal rst : std_logic; begin rst <= FSL_Rst when (C_EXT_RESET_HIGH = 1) else not FSL_Rst; FSL_M_Control <= '0'; FSL_M_Clk <= FSL_Clk; FSL_S_Clk <= FSL_Clk; registers: process(FSL_Clk) begin if rising_edge(FSL_Clk) then if (rst = '1') then counter <= (others => (others => '0')); op_r <= (others => idle); rd_id_r <= 0; else op_r <= op_i; rd_id_r <= rd_id_i; for i in 1 to C_NUM_OF_COUNTERS loop case (op_i(i)) is when idle => counter(i) <= counter(i); when running => counter(i) <= std_logic_vector(unsigned(counter(i))+1); when reset => counter(i) <= (others => '0'); when rd => counter(i) <= counter(i); when others => null; end case; end loop; end if; end if; end process; fsm: process(FSL_S_Exists, FSL_S_Data, op_r, counter, rd_id_r) variable id : integer; begin -- Default assignments id := 0; op_i <= op_r; FSL_M_Data <= (others => '0'); FSL_M_Write <= '0'; FSL_S_Read <= '0'; rd_id_i <= 0; if (FSL_S_Exists = '1' and rd_id_r = 0) then id := to_integer(unsigned(FSL_S_Data(LSB_ID to MSB_ID))) + 1; case(FSL_S_Data(LSB_OP to MSB_OP)) is when RST_ALL => op_i <= (others => reset); FSL_S_Read <= '1'; when RST_ID => op_i(id) <= reset; FSL_S_Read <= '1'; when STOP_ID => op_i(id) <= idle; FSL_S_Read <= '1'; when START_ID => op_i(id) <= running; FSL_S_Read <= '1'; when READ_ID => op_i(id) <= rd; rd_id_i <= id; FSL_S_Read <= '1'; FSL_M_Data <= counter(id)(32 to 63); FSL_M_Write <= '1'; when others => null; end case; end if; if (rd_id_r /= 0) then op_i(rd_id_r) <= running; FSL_S_Read <= '0'; FSL_M_Data <= counter(rd_id_r)(0 to 31); FSL_M_Write <= '1'; rd_id_i <= 0; end if; end process; end architecture rtl;

bsd-3-clause

78d91e86c78a873fbc4cb59fbb0be137

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_synth_comp.vhd

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mit

e88561b78a58f204ef9a592fccfa4cdb

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_cons_outcome.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_cons_outcome | -- | --------------------------------------------------------------------------------------------------- -- File wf_cons_outcome.vhd | -- | -- Description The unit starts by validating a consumed RP_DAT frame with respect to the | -- correctness of: | -- o the CTRL, PDU_TYPE and LGTH bytes; these bytes are received from the | -- wf_consumption unit | -- o the CRC, FSS & FES bytes; the rx_fss_crc_fes_ok_p_i pulse, received from the | -- wf_fd_receiver unit, groups these checks | -- | -- Then, according to the consumed variable that has been received (var_1, var_2, | -- var_rst, var_4) it generates the signals: | -- o "nanoFIP User Interface, NON_WISHBONE" output signals VAR1_RDY and VAR2_RDY | -- o "nanoFIP User Interface, NON_WISHBONE" output signal r_tler_o, also used by | -- the wf_status_bytes_generator unit (nanoFIP status byte, bit 4) | -- o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the wf_reset_unit | -- o jc_start_p that triggers the start-up of thr wf_jtag_controller unit | -- | -- | -- Reminder: | -- | -- Consumed RP_DAT frame structure : | -- ___________ ______ _______ ______ _________________________ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__| | -- | -- |-----------&LGTH bytes-----------| | -- |---------- >0 and <128 ----------| | -- |--------------------------&byte_index_i bytes--------------------------------| | -- | -- The LGTH byte is considered correct if it is coherent with the actual number of | -- bytes received in the frame and also respects the frame limits. | -- | -- | -- Authors Pablo Alvarez Sanchez ([email protected]) | -- Evangelia Gousiou ([email protected]) | -- Date 06/2011 | -- Version v0.06 | -- Depends on wf_reset_unit | -- wf_engine_control | -- wf_fd_receiver | -- wf_consumption | ---------------- | -- Last changes | -- 10/2010 v0.01 EG First version | -- 11/2010 v0.02 EG Treatment of reset vars added to the unit | -- Correction on var1_rdy, var2_rdy for slone | -- 12/2010 v0.03 EG Finally no broadcast in slone, cleanning-up+commenting | -- 01/2011 v0.04 EG Unit wf_var_rdy_generator separated in wf_cons_outcome | -- (for var1_rdy,var2_rdy+var_rst outcome) & wf_prod_permit (for var3) | -- 02/2011 v0.05 EG Added here functionality of wf_cons_frame_validator | -- Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received | -- was always set to 1!) | -- Added check of CTRL byte for rtler | -- Added cons_bytes_excess_i for tracking of too long RP_DATs | -- 06/2011 v0.06 EG added var_4 treatment | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_cons_outcome --================================================================================================= entity wf_cons_outcome is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock slone_i : in std_logic; -- stand-alone mode -- nanoFIP WorldFIP Settings subs_i : in std_logic_vector (7 downto 0); -- subscriber number coding -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signal from the wf_fd_receiver unit rx_fss_crc_fes_ok_p_i : in std_logic; -- indication of a frame with correct FSS, FES & CRC; -- pulse upon FES detection rx_crc_wrong_p_i : in std_logic; -- indication of a frame with a wrong CRC; -- pulse upon FES detection -- Signals from the wf_consumption unit cons_ctrl_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT CTRL byte cons_lgth_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT LGTH byte cons_pdu_byte_i : in std_logic_vector (7 downto 0); -- received RP_DAT PDU_TYPE byte cons_var_rst_byte_1_i : in std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 1st data-byte cons_var_rst_byte_2_i : in std_logic_vector (7 downto 0); -- received var_rst RP_DAT, 2nd data-byte -- Signals from the wf_engine_control unit cons_bytes_excess_i : in std_logic; -- RP_DAT frame with > 133 bytes byte_index_i : in std_logic_vector (7 downto 0); -- index of byte being received var_i : in t_var; -- variable type that is being treated -- OUTPUTS -- nanoFIP User Interface, NON-WISHBONE outputs var1_rdy_o : out std_logic; -- signals new data is received and can safely be read var2_rdy_o : out std_logic; -- signals new data is received and can safely be read -- Signal to the wf_jtag_controller unit jc_start_p_o : out std_logic; -- pulse upon the end of a new valid var_4 -- Signal to the wf_status_bytes_gen unit nfip_status_r_tler_p_o : out std_logic; -- received PDU_TYPE or LGTH error -- nanoFIP status byte bit 4 -- Signals to the wf_reset_unit assert_rston_p_o : out std_logic; -- indicates that a var_rst with its 2nd data-byte -- containing the station's address has been -- correctly received rst_nfip_and_fd_p_o : out std_logic);-- indicates that a var_rst with its 1st data-byte -- containing the station's address has been -- correctly received end entity wf_cons_outcome; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_cons_outcome is signal s_cons_frame_ok_p : std_logic; signal s_rst_nfip_and_fd, s_assert_rston : std_logic; --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Consumed RP_DAT frame Validation -- --------------------------------------------------------------------------------------------------- -- Sequential process Frame_Validation: validation of a consumed RP_DAT frame, with -- respect to the CTRL, PDU_TYPE and LGTH bytes as well as to the CRC, FSS & FES. -- The bytes cons_ctrl_byte_i, cons_pdu_byte_i, cons_lgth_byte_i that -- arrive at the beginning of a frame, have been registered and keep their values until the end -- of it. The signal rx_fss_crc_fes_ok_p_i, is a pulse at the end of the FES that combines -- the checks of the FSS, CRC & FES. -- To check the correctness of the the RP_DAT.Data.LGTH byte, we compare it to the value of the -- bytes counter byte_index_i, when the FES is detected (pulse rx_fss_crc_fes_ok_p_i). -- Note: Upon FES detection the counter byte_index_i should be equal to &cons_lgth_byte_i + 5. -- This is because the byte_index_i also counts the: CTRL, PDU_TYPE, LGTH, the 2 CRC and -- the FES bytes (and counting starts from 0!). Frame_Validation: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_cons_frame_ok_p <= '0'; else -- only consumed RP_DATs if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_4) then if (rx_fss_crc_fes_ok_p_i = '1') and -- FSS CRC FES check ((cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_CTRL_BYTE) or -- CTRL byte check (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_MSG_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ1_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ2_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ1_MSG_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ2_MSG_CTRL_BYTE)) and (cons_pdu_byte_i = c_PDU_TYPE_BYTE) and -- PDU_TYPE byte check (unsigned(byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5)) then -- LGTH byte check s_cons_frame_ok_p <= '1'; else s_cons_frame_ok_p <= '0'; end if; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- r_tler generation -- --------------------------------------------------------------------------------------------------- -- Gneration of the of the "nanoFIP User Interface, NON_WISHBONE" output signal r_tler_o which -- indicates a received CTRL or PDU_TYPE byte error or a LGTH byte incoherency. -- Note: The end of a frame is marked by either the signal rx_fss_crc_fes_ok_p_i or by the -- rx_crc_wrong_p_i. nFIP_statusbyte_bit4: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then nfip_status_r_tler_p_o <= '0'; else -- only consumed RP_DATs if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) or (var_i = var_4) then if (cons_bytes_excess_i = '1') or -- excess of bytes (without FES detection) (((rx_fss_crc_fes_ok_p_i = '1') or (rx_crc_wrong_p_i = '1')) and -- upon FES detection checking of CTRL, PDU_TUPE, LGTH ((not ((cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_CTRL_BYTE) or -- CTRL byte check (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_MSG_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ1_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ2_CTRL_BYTE) or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ1_MSG_CTRL_BYTE)or (cons_ctrl_byte_i(5 downto 0) = c_RP_DAT_RQ2_MSG_CTRL_BYTE)))or (cons_pdu_byte_i /= c_PDU_TYPE_BYTE) or -- PDU_TYPE byte check (unsigned(byte_index_i ) /= (unsigned(cons_lgth_byte_i) + 5)))) then -- LGTH byte check nfip_status_r_tler_p_o <= '1'; else nfip_status_r_tler_p_o <= '0'; end if; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- VAR_RDY_Generation -- --------------------------------------------------------------------------------------------------- -- Synchronous process VAR_RDY_Generation: -- Memory Mode: -- Since the three memories (consumed, consumed broadcast, produced) are independent, when a -- produced var is being sent, the user can read form the consumed memories; similarly, when a -- consumed var is being received the user can read from the consumed broadcast memory. -- VAR1_RDY (for consumed vars) : signals that the user can safely read from the -- consumed memory. The signal is asserted only after the reception of a correct var_1 RP_DAT -- frame. It is de-asserted after the reception of a correct var_1 ID_DAT frame. -- VAR2_RDY (for broadcast consumed vars): signals that the user can safely read from the -- consumed broadcast memory. The signal is asserted only after the reception of a correct -- consumed broadcast var_2 RP_DAT frame. It is de-asserted after the reception of a correct -- var_2 ID_DAT frame. -- Stand-alone Mode: -- Similarly, in stand-alone mode, the DAT_I and DAT_O buses for the produced and the consumed -- bytes are independent. Stand-alone mode though does not treat the consumed broadcast variable. -- VAR1_RDY (for consumed vars) : signals that the user can safely retrieve data from -- the DAT_O bus. The signal is asserted only after the reception of a correct var_1 RP_DAT frame. -- It is de-asserted after the reception of a correct var_1 ID_DAT frame (same as in memory mode). -- VAR2_RDY (for broadcast consumed vars): stays always deasserted. -- Note: A correct consumed RP_DAT frame is signaled by the s_cons_frame_ok_p, which arrives upon -- FES detection. A correct ID_DAT frame along with the variable it contained is signaled by the -- var_i. The signal var_i gets its value (var_1, var_2, var_rst) after the reception of a correct -- ID_DAT and of a correct RP_DAT FSS; var_i retains its value until the FES detection (or the -- detection of an excess of bytes) of the RP_DAT frame. An example follows: -- frames : ___[ID_DAT,var_1]__[......RP_DAT......]______________[ID_DAT,var_1]___[.....RP_DAT.. -- cons_frame_ok_p : ______________________________________|-|___________________________________________ -- var_i : var_whatever > < var_1 > < var_whatever > < var_1 -- VAR1_RDY : ______________________________________|--------------------------------|____________ VAR_RDY_Generation: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then var1_rdy_o <= '0'; var2_rdy_o <= '0'; else -- VAR1_RDY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- if (var_i = var_1) and (s_cons_frame_ok_p = '1') then -- only if the received var_1 RP_DAT frame is correct var1_rdy_o <= '1'; -- the nanoFIP signals the user to retreive data -- note: the signal var1_rdy_o remains asserted -- until the beginning of a new var_1 elsif (var_i = var_1) then var1_rdy_o <= '0'; -- while consuming a var_1, VAR1_RDY is '0' end if; -- VAR2_RDY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- if (var_i = var_2) and (s_cons_frame_ok_p = '1') and (slone_i = '0') then -- only in memory mode and if the received var_2 var2_rdy_o <= '1'; -- RP_DAT is correct the nanoFIP signals the user -- to retreive data -- note: the signal var2_rdy_o remains asserted -- until the beginning of a new var_2 elsif (var_i = var_2) then var2_rdy_o <= '0'; -- while consuming a var_2, VAR2_RDY is '0' end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- var_rst: Reset Signals Generation -- --------------------------------------------------------------------------------------------------- -- Generation of the signals rst_nfip_and_fd : signals that the 1st byte of a consumed -- var_rst contains the station address -- and assert_rston : signals that the 2nd byte of a consumed -- var_rst contains the station address Cons_Reset_Signals: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_rst_nfip_and_fd <= '0'; s_assert_rston <= '0'; else if var_i = var_rst then if (byte_index_i = c_1st_DATA_BYTE_INDEX) and (cons_var_rst_byte_1_i = subs_i) then s_rst_nfip_and_fd <= '1'; -- rst_nFIP_and_FD_o stays asserted until end if; -- the end of the var_rst RP_DAT frame if (byte_index_i = c_2nd_DATA_BYTE_INDEX) and (cons_var_rst_byte_2_i = subs_i) then s_assert_rston <= '1'; -- assert_RSTON_o stays asserted until end if; -- the end of the var_rst RP_DAT frame else s_rst_nfip_and_fd <= '0'; s_assert_rston <= '0'; end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- rst_nfip_and_fd_p_o <= '1' when s_rst_nfip_and_fd = '1' and s_cons_frame_ok_p = '1' else '0'; assert_rston_p_o <= '1' when s_assert_rston = '1' and s_cons_frame_ok_p = '1' else '0'; --------------------------------------------------------------------------------------------------- -- var_4: JTAG_contoller startup signal -- --------------------------------------------------------------------------------------------------- -- Generation of the signal jc_start_p_o that is a 1 uclk-long pulse after the reception of a -- valid JTAG consumed RP_DAT frame (var_4). The pulse triggers the startup of the wf_jtag_controller -- state machine. jc_start_p_generation: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then jc_start_p_o <= '0'; else if (var_i = var_4) and (s_cons_frame_ok_p = '1') then jc_start_p_o <= '1'; else jc_start_p_o <= '0'; end if; end if; end if; end process; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

4ed6b51e0ed781dc73b3a101a9eb2b3b

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sim_1/tb_env_pkg.m.vhd

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end_protected

gpl-2.0

c3eb5e6b0de6789748fd3cd54c5da3a9

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

264cc81566214296c5884c525f152652

preusser/q27

src/vhdl/PoC/sync/sync.pkg.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Package: VHDL package for component declarations, types and -- functions associated to the PoC.misc.sync namespace -- -- Description: -- ------------------------------------ -- For detailed documentation see below. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.utils.all; use PoC.physical.all; package sync is component sync_Bits is generic ( BITS : POSITIVE := 1; -- number of bit to be synchronized INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits ); port ( Clock : in STD_LOGIC; -- <Clock> output clock domain Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @async: input bits Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock: output bits ); end component; component sync_Bits_Altera is generic ( BITS : POSITIVE := 1; -- number of bit to be synchronized INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits ); port ( Clock : in STD_LOGIC; -- Clock to be synchronized to Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data ); end component; component sync_Bits_Xilinx is generic ( BITS : POSITIVE := 1; -- number of bit to be synchronized INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits ); port ( Clock : in STD_LOGIC; -- Clock to be synchronized to Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- Data to be synchronized Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- synchronised data ); end component; component sync_Reset is port ( Clock : in STD_LOGIC; -- <Clock> output clock domain Input : in STD_LOGIC; -- @async: reset input Output : out STD_LOGIC -- @Clock: reset output ); end component; component sync_Reset_Altera is port ( Clock : in STD_LOGIC; -- Clock to be synchronized to Input : in STD_LOGIC; -- Data to be synchronized Output : out STD_LOGIC -- synchronised data ); end component; component sync_Reset_Xilinx is port ( Clock : in STD_LOGIC; -- Clock to be synchronized to Input : in STD_LOGIC; -- high active asynchronous reset Output : out STD_LOGIC -- "Synchronised" reset signal ); end component; end package;

agpl-3.0

f2bfc7d6a1a5c1ffd832869f5fed53f6

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- nanoFIP | -- | --------------------------------------------------------------------------------------------------- -- File : nanofip.vhd | -- | -- Description: nanoFIP is an FPGA component acting as a client node/ agent in the communication | -- over WorldFIP fieldbus. nanoFIP is designed to be radiation tolerant by using different | -- Single Event Upset mitigation techniques such as Triple Module Redundancy, fail-safe state | -- machines and several reset possibilities. The nanoFIP design is to be implemented in an Actel | -- ProASIC3 Flash family FPGA (130nm CMOS technology) that offers an inherent resistance to | -- radiation: it is immune to Single Event Latchups for the LHC environment, it has high tolerance| -- to Total Ionizing Dose effects (>300 Gy) and its configuration memory is not disturbed by SEUs.| -- nanoFIP is used in conjunction with a FIELDRIVE chip and FIELDTR insulating transformer, | -- both available from the company ALSTOM. | -- | -- __________________________________________________________________ | -- | | | -- | Field devices, Radioactive environment | Radiation free zone | -- | _____________ _____________ _____________ | _______________ | -- | | | | | | | | | | | -- | | user logic | | user logic | | user logic | | | | | -- | |_____________| |_____________| |_____________| | | | | -- | ______|______ ______|______ ______|______ | | | | -- | | | | | | | | | BUS ARBITRER | | -- | | nanoFIP | | nanoFIP | . . . | nanoFIP | | | | | -- | |_____________| |_____________| |_____________| | | | | -- | _____|_____ _____|_____ _____|_____ | | | | -- | |_FIELDRIVE_| |_FIELDRIVE_| |_FIELDRIVE_| | | | | -- | _____|_____ _____|_____ _____|_____ | | | | -- | |__FIELDTR__| |__FIELDTR__| |__FIELDTR__| | |_______________| | -- | | | | | | | -- |________|_____________________|________________________|__________| | | -- | | | | | -- _______^_____________________^________________________^________________________^____________ | -- 0____________________________________WorldFIP FIELDBUS______________________________________O | -- | -- Figure 1: Fieldbus layout | -- | -- In the WorldFIP protocol, the access to the bus is controlled by a central Bus Arbitrer (BA) | -- that grants bus access to the different agents following the sequence in a pre-configured | -- table. The BA is broadcasting ID_DAT frames to all the agents connected to the same network | -- segment requesting for a particular variable. Figure 2 shows the structure of an ID_DAT frame: | -- ___________ ______ _______ ______ ___________ _______ | -- |____FSS____|_CTRL_||__Var__|_SUBS_||____FCS____|__FES__| | -- | -- Figure 2: ID_DAT frame structure | -- | -- nanoFIP agents can handle the following set of variables: | -- o ID_DAT Var_Subs = 14_xy: for the presence variable | -- o ID_DAT Var_Subs = 10_xy: for the identification variable | -- o ID_DAT Var_Subs = 05_xy: for the consumed variable of any length up to 124 bytes | -- o ID_DAT Var_Subs = aa_xy: for the JTAG consumed variable of any length up to 124 bytes | -- o ID_DAT Var_Subs = 91_..: for the broadcast consumed variable of any length up to 124 bytes | -- o ID_DAT Var_Subs = 06_xy: for the produced variable of a user-settable length (P3_LGTH) | -- o ID_DAT Var_Subs = ab_xy: for the JTAG produced variable of a predefined length of 1 byte | -- o ID_DAT Var_Subs = E0_..: for the broadcast consumed reset variable | -- | -- After a 14_xy, a 10_xy, a 06_xy or a ab_xy ID_DAT, if nanoFIP's address (SUBS) is xy, nanoFIP | -- will respond with an RP_DAT frame, containing the variable requested. Figure 3 shows the | -- structure of a RP_DAT frame: | -- ___________ ______ ____________________ ___________ _______ | -- |____FSS____|_CTRL_||_____...Data..._____||____FCS____|__FES__| | -- | -- Figure 3: RP_DAT frame structure | -- | -- After a 05_xy or an aa_xy ID_DAT, if nanoFIP's address (SUBS) is xy, | -- or after a broadcast ID_DAT 91..h or E0..h, nanoFIP will receive/ "consume" the next incoming | -- RP_DAT frame. | -- | -- Regarding the interface with the user logic, nanoFIP provides: | -- o data transfer over an integrated memory accessible with an 8-bit WISHBONE System-On-Chip | -- interconnection | -- o possibility of stand-alone mode with a 16 bits input bus and 16 bits output bus, without | -- the need to transfer data to or from the memory | -- o separate data valid outputs for the consumed (05_xy), broadcast consumed (91_..) and | -- produced (06_xy) variables | -- o JTAG master controller interfacing with the Test Access Port of the user logic FPGA | -- | -- nanoFIP provides several reset possibilities: | -- o External reset input pin, RSTIN, activated by the user logic | -- o External reset input pin, RST_I, activated by the user, that resets only the WISHBONE logic | -- o Addressed reset by the reset broadcast consumed variable (E0..h), | -- validated by station address as data | -- o External Power On Reset input pin, RSTPON | -- | -- nanoFIP also provides resets to the user and to the FIELDRIVE: | -- o Reset output available to external logic (RSTON) by the reset broadcast consumed variable | -- (E0..h), validated by station address as data | -- o FIELDRIVE reset output (FD_RSTN) by the reset broadcast consumed variable (E0..h), | -- validated by station address as data | -- | -- nanoFIP's main building blocks are (Figure 4): | -- o wf_reset_unit : for the treatment of the reset input signals & the generation | -- of the reset outputs | -- | -- o wf_fd_receiver : for the deserialization of the FIELDRIVE input and the formation | -- of ID_DAT or consumed RP_DAT bytes of data | -- | -- o wf_consumption : for the processing, storage & validation of consumed RP_DAT frames | -- | -- o wf_fd_transmitter : for the serialization of produced RP_DAT frames | -- | -- o wf_production : for the retrieval of bytes for produced RP_DAT frames | -- | -- o wf_engine_control : for the processing of the ID_DAT frames and the coordination of the | -- wf_consumption, wf_fd_receiver, wf_production & wf_fd_transmitter units| -- | -- o wf_model_constr_dec: for the decoding of the WorldFIP settings M_ID and C_ID and the | -- generation of the S_ID | -- | -- o wf_wb_controller : for the handling of the "User Interface WISHBONE Slave" control | -- signals | -- | -- o wf_jtag_controller : for driving and monitoring the user logic TAP upon reception of JTAG | -- variables (aa_xy and ab_xy). | -- | -- _____________ ____________________________________________________ | -- | | | wf_WB_controller | | -- | wf_reset | |____________________________________________________| | -- | _unit | _____________ _____________ | -- | | | | ______________ | | | -- |_____________| | | | | | | | -- | wf_ | | | | wf_ | | -- _____________ | consumption | | | | production | | -- | | | | | | | | | -- | wf_JTAG | | | | | | | | -- | _controller | |_____________| | wf_ | |_____________| | -- | | _____________ |engine_control| _____________ | -- |_____________| | | | | | | | -- | | | | | | | -- _____________ | | | | | | | -- | | | wf_FD_ | | | | wf_FD_ | | -- | wf_model_ | | receiver | | | | transmitter | | -- | constr_dec | | | | | | | | -- | | | | | | | | | -- |_____________| |_____________| |______________| |_____________| | -- | -- Figure 4: nanoFIP block diagram | -- | -- The design is based on the nanoFIP functional specification document, available at: | -- http://www.ohwr.org/projects/cern-fip/documents | -- Complete information about this project at: http://www.ohwr.org/projects/cern-fip | -- | -- | -- Authors Erik Van der Bij ([email protected]) | -- Pablo Alvarez Sanchez ([email protected]) | -- Evangelia Gousiou ([email protected]) | -- Date 10/2011 | -- Version v0.06 | -- Depends on wf_reset_unit | -- wf_model_constr_dec | -- wf_fd_receiver | -- wf_fd_transmitter | -- wf_consumption | -- wf_production | -- wf_engine_control | -- wf_wb_controller | -- wf_jtag_controller | ---------------- | -- Last changes | -- 30/06/2009 v0.010 EB First version | -- 06/07/2009 v0.011 EB Dummy blocks | -- 07/07/2009 v0.011 EB Comments | -- 15/09/2009 v0.v2 PA | -- 09/12/2010 v0.v3 EG Logic removed (new unit inputs_synchronizer added) | -- 7/01/2011 v0.04 EG major restructuring; only 7 units on top level | -- 20/01/2011 v0.05 EG new unit wf_wb_controller(removes the or gate from top level) | -- 06/2011 v0.06 EG jtag_controller unit added | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for nanoFIP --================================================================================================= entity nanofip is port( -- MODIFIED nanofip_rst_o : out std_logic; --INPUTS -- WorldFIP settings c_id_i : in std_logic_vector (3 downto 0); -- Constructor identification settings m_id_i : in std_logic_vector (3 downto 0); -- Model identification settings p3_lgth_i : in std_logic_vector (2 downto 0); -- Produced variable data length rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate subs_i : in std_logic_vector (7 downto 0); -- Subscriber number coding (station address) -- FIELDRIVE fd_rxcdn_i : in std_logic; -- Reception activity detection, active low fd_rxd_i : in std_logic; -- Receiver data fd_txer_i : in std_logic; -- Transmitter error fd_wdgn_i : in std_logic; -- Watchdog on transmitter -- User Interface, General signals nostat_i : in std_logic; -- No nanoFIP status with produced data rstin_i : in std_logic; -- Initialization control, active low -- Resets nanoFIP & the FIELDRIVE rstpon_i : in std_logic; -- Power On Reset, active low slone_i : in std_logic; -- Stand-alone mode uclk_i : in std_logic; -- 40 MHz clock -- User Interface, NON-WISHBONE var1_acc_i : in std_logic; -- Signals that the user logic is accessing var 1 var2_acc_i : in std_logic; -- Signals that the user logic is accessing var 2 var3_acc_i : in std_logic; -- Signals that the user logic is accessing var 3 -- User Interface, WISHBONE Slave wclk_i : in std_logic; -- WISHBONE clock; may be independent of uclk adr_i : in std_logic_vector (9 downto 0); -- WISHBONE address cyc_i : in std_logic; -- WISHBONE cycle dat_i : in std_logic_vector (15 downto 0);-- DAT_I(7 downto 0) : WISHBONE data in, memory mode -- DAT_I(15 downto 0): data in, stand-alone mode rst_i : in std_logic; -- WISHBONE reset -- Does not reset other internal logic stb_i : in std_logic; -- WISHBONE strobe we_i : in std_logic; -- WISHBONE write enable -- User Interface, JTAG Controller jc_tdo_i : in std_logic; -- JTAG Test Data Out; input from the target TAP -- OUTPUTS -- WorldFIP settings -- MODIFIED --s_id_o : out std_logic_vector (1 downto 0);-- Identification selection -- FIELDRIVE fd_rstn_o : out std_logic; -- Initialization control, active low fd_txck_o : out std_logic; -- Line driver half bit clock fd_txd_o : out std_logic; -- Transmitter data fd_txena_o : out std_logic; -- Transmitter enable -- User Interface, General signals rston_o : out std_logic; -- Reset output, active low -- User Interface, NON-WISHBONE r_fcser_o : out std_logic; -- nanoFIP status byte, bit 5 r_tler_o : out std_logic; -- nanoFIP status byte, bit 4 u_cacer_o : out std_logic; -- nanoFIP status byte, bit 2 u_pacer_o : out std_logic; -- nanoFIP status byte, bit 3 var1_rdy_o : out std_logic; -- Signals new data received & can safely be read var2_rdy_o : out std_logic; -- Signals new data received & can safely be read var3_rdy_o : out std_logic; -- Signals that the var 3 can safely be written -- User Interface, WISHBONE Slave -- MODIFIED was (15 downto 0) dat_o : out std_logic_vector (7 downto 0);-- DAT_O(7 downto 0) : WISHBONE data out, memory mode -- DAT_O(15 downto 0): data out, stand-alone mode ack_o : out std_logic; -- WISHBONE acknowledge -- User Interface, JTAG Controller jc_tms_o : out std_logic; -- Drives the JTAG Test Mode Select of the target TAP jc_tdi_o : out std_logic; -- Drives the JTAG Test Data In of the target TAP jc_tck_o : out std_logic); -- Drives the JTAG Test Clock of the target TAP end entity nanofip; --================================================================================================= -- architecture declaration --================================================================================================= architecture struc of nanofip is -- wf_reset_unit outputs signal s_nfip_intern_rst, s_wb_rst : std_logic; -- wf_consumption outputs signal s_var1_rdy, s_var2_rdy, s_var3_rdy : std_logic; signal s_assert_RSTON_p, s_reset_nFIP_and_FD_p : std_logic; signal s_nfip_status_r_tler : std_logic; signal s_jc_start_p : std_logic; signal s_jc_mem_data : std_logic_vector (7 downto 0); -- wf_fd_receiver outputs signal s_rx_fss_received_p, s_rx_fss_crc_fes_ok_p : std_logic; signal s_rx_crc_wrong_p, s_rx_byte_ready_p : std_logic; signal s_rx_byte : std_logic_vector (7 downto 0); -- wf_production outputs signal s_byte_to_tx : std_logic_vector (7 downto 0); -- wf_fd_transmitter outputs signal s_tx_last_byte_p, s_tx_completed_p : std_logic; -- wf_engine_control outputs signal s_tx_start_p, s_tx_request_byte_p : std_logic; signal s_byte_request_accepted_p, s_cons_bytes_excess, s_rx_rst : std_logic; signal s_var : t_var; signal s_prod_data_lgth, s_prod_byte_index, s_cons_byte_index : std_logic_vector (7 downto 0); -- wf_model_constr_dec outputs signal s_model_id_dec, s_constr_id_dec : std_logic_vector (7 downto 0); -- wf_wb_controller outputs signal s_wb_ack_prod : std_logic; -- wf_model_constr_dec outputs signal s_jc_mem_adr_rd : std_logic_vector (8 downto 0); signal s_jc_tdo_byte : std_logic_vector (7 downto 0); --================================================================================================= -- architecture declaration --================================================================================================= begin -- MODIFIED nanofip_rst_o <= s_nfip_intern_rst; --------------------------------------------------------------------------------------------------- -- wf_reset_unit -- --------------------------------------------------------------------------------------------------- reset_unit : wf_reset_unit port map( uclk_i => uclk_i, wb_clk_i => wclk_i, rstin_a_i => rstin_i, rstpon_a_i => rstpon_i, rate_i => rate_i, rst_i => rst_i, rst_nFIP_and_FD_p_i => s_reset_nFIP_and_FD_p, assert_RSTON_p_i => s_assert_RSTON_p, ------------------------------------------------------------- nFIP_rst_o => s_nfip_intern_rst, wb_rst_o => s_wb_rst, rston_o => rston_o, fd_rstn_o => fd_rstn_o); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_consumption -- --------------------------------------------------------------------------------------------------- Consumption: wf_consumption port map( uclk_i => uclk_i, slone_i => slone_i, nfip_rst_i => s_nfip_intern_rst, subs_i => subs_i, rx_byte_i => s_rx_byte, rx_byte_ready_p_i => s_rx_byte_ready_p, rx_fss_crc_fes_ok_p_i => s_rx_fss_crc_fes_ok_p, rx_crc_wrong_p_i => s_rx_crc_wrong_p, wb_clk_i => wclk_i, wb_adr_i => adr_i (8 downto 0), cons_bytes_excess_i => s_cons_bytes_excess, var_i => s_var, byte_index_i => s_cons_byte_index, jc_mem_adr_rd_i => s_jc_mem_adr_rd, ------------------------------------------------------------- var1_rdy_o => s_var1_rdy, var2_rdy_o => s_var2_rdy, jc_start_p_o => s_jc_start_p, data_o => dat_o, nfip_status_r_tler_p_o => s_nfip_status_r_tler, assert_rston_p_o => s_assert_RSTON_p, rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p, jc_mem_data_o => s_jc_mem_data); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_fd_receiver -- --------------------------------------------------------------------------------------------------- FIELDRIVE_Receiver: wf_fd_receiver port map( uclk_i => uclk_i, rate_i => rate_i, fd_rxd_a_i => fd_rxd_i, nfip_rst_i => s_nfip_intern_rst, rx_rst_i => s_rx_rst, ------------------------------------------------------------- rx_byte_o => s_rx_byte, rx_byte_ready_p_o => s_rx_byte_ready_p, rx_fss_crc_fes_ok_p_o => s_rx_fss_crc_fes_ok_p, rx_fss_received_p_o => s_rx_fss_received_p, rx_crc_wrong_p_o => s_rx_crc_wrong_p); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_production -- --------------------------------------------------------------------------------------------------- Production: wf_production port map( uclk_i => uclk_i, slone_i => slone_i, nostat_i => nostat_i, nfip_rst_i => s_nfip_intern_rst, wb_clk_i => wclk_i, wb_data_i => dat_i(7 downto 0), wb_adr_i => adr_i(8 downto 0), wb_ack_prod_p_i => s_wb_ack_prod, slone_data_i => dat_i, var1_acc_a_i => var1_acc_i, var2_acc_a_i => var2_acc_i, var3_acc_a_i => var3_acc_i, fd_txer_a_i => fd_txer_i, fd_wdgn_a_i => fd_wdgn_i, var_i => s_var, data_lgth_i => s_prod_data_lgth, byte_index_i => s_prod_byte_index, byte_request_accept_p_i => s_byte_request_accepted_p, nfip_status_r_tler_p_i => s_nfip_status_r_tler, nfip_status_r_fcser_p_i => s_rx_crc_wrong_p, var1_rdy_i => s_var1_rdy, var2_rdy_i => s_var2_rdy, model_id_dec_i => s_model_id_dec, constr_id_dec_i => s_constr_id_dec, jc_tdo_byte_i => s_jc_tdo_byte, ------------------------------------------------------------- byte_o => s_byte_to_tx, u_cacer_o => u_cacer_o, u_pacer_o => u_pacer_o, r_tler_o => r_tler_o, r_fcser_o => r_fcser_o, var3_rdy_o => s_var3_rdy); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_fd_transmitter -- --------------------------------------------------------------------------------------------------- FIELDRIVE_Transmitter: wf_fd_transmitter port map( uclk_i => uclk_i, rate_i => rate_i, nfip_rst_i => s_nfip_intern_rst, tx_byte_i => s_byte_to_tx, tx_byte_request_accept_p_i => s_byte_request_accepted_p, tx_last_data_byte_p_i => s_tx_last_byte_p, tx_start_p_i => s_tx_start_p, ------------------------------------------------------------- tx_byte_request_p_o => s_tx_request_byte_p, tx_completed_p_o => s_tx_completed_p, tx_data_o => fd_txd_o, tx_enable_o => fd_txena_o, tx_clk_o => fd_txck_o); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_jtag_controller -- --------------------------------------------------------------------------------------------------- JTAG_controller: wf_jtag_controller port map( uclk_i => uclk_i, nfip_rst_i => s_nfip_intern_rst, jc_mem_data_i => s_jc_mem_data, jc_start_p_i => s_jc_start_p, jc_tdo_i => jc_tdo_i, ----------------------------------------------------------------- jc_tms_o => jc_tms_o, jc_tdi_o => jc_tdi_o, jc_tck_o => jc_tck_o, jc_tdo_byte_o => s_jc_tdo_byte, jc_mem_adr_rd_o => s_jc_mem_adr_rd); ----------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_engine_control -- --------------------------------------------------------------------------------------------------- engine_control : wf_engine_control port map( uclk_i => uclk_i, nfip_rst_i => s_nfip_intern_rst, tx_byte_request_p_i => s_tx_request_byte_p, tx_completed_p_i => s_tx_completed_p, rx_fss_received_p_i => s_rx_fss_received_p, rx_byte_i => s_rx_byte, rx_byte_ready_p_i => s_rx_byte_ready_p, rx_fss_crc_fes_ok_p_i => s_rx_fss_crc_fes_ok_p, rx_crc_wrong_p_i => s_rx_crc_wrong_p, rate_i => rate_i, subs_i => subs_i, p3_lgth_i => p3_lgth_i, slone_i => slone_i, nostat_i => nostat_i, ------------------------------------------------------------- var_o => s_var, tx_start_p_o => s_tx_start_p, tx_byte_request_accept_p_o => s_byte_request_accepted_p, tx_last_data_byte_p_o => s_tx_last_byte_p, prod_byte_index_o => s_prod_byte_index, cons_byte_index_o => s_cons_byte_index, prod_data_lgth_o => s_prod_data_lgth, cons_bytes_excess_o => s_cons_bytes_excess, rx_rst_o => s_rx_rst); ------------------------------------------------------------- var1_rdy_o <= s_var1_rdy; var2_rdy_o <= s_var2_rdy; var3_rdy_o <= s_var3_rdy; --------------------------------------------------------------------------------------------------- -- wf_model_constr_decoder -- --------------------------------------------------------------------------------------------------- model_constr_decoder : wf_model_constr_decoder port map( uclk_i => uclk_i, nfip_rst_i => s_nfip_intern_rst, model_id_i => m_id_i, constr_id_i => c_id_i, ------------------------------------------------------------- -- MODIFIED -- s_id_o => s_id_o, model_id_dec_o => s_model_id_dec, constr_id_dec_o => s_constr_id_dec); ------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- wf_wb_controller -- --------------------------------------------------------------------------------------------------- WISHBONE_controller: wf_wb_controller port map( wb_clk_i => wclk_i, wb_rst_i => s_wb_rst, wb_stb_i => stb_i, wb_cyc_i => cyc_i, wb_we_i => we_i, wb_adr_id_i => adr_i (9 downto 7), ------------------------------------------------------------- wb_ack_prod_p_o => s_wb_ack_prod, wb_ack_p_o => ack_o); ------------------------------------------------------------- end architecture struc; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

f78aa49b1a702ae1a65e807ed14c50f3

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_Atomic_SubInteger_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant ATOMIC_IMPLEMENT : natural := 1; constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

f18ebb962378d48230bb5b050002cbf2

preusser/q27

src/vhdl/PoC/common/my_project.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- This is a template file. -- -- TODO -- -- USAGE: -- 1) Copy this file into your project's source directory and rename it to -- "my_project.vhdl". -- 2) Add file to library "poc" in your synthesis tool. -- 3) Change setup appropriately. -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library PoC; package my_project is constant MY_PROJECT_DIR : string := "/non/existent"; constant MY_OPERATING_SYSTEM : string := "LINUX"; end; package body my_project is end;

agpl-3.0

20f5ec1f300a07bdc3aaf961bba27534

preusser/q27

src/vhdl/PoC/uart/uart.pkg.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- =========================================================================== -- Package: UART (RS232) Components -- -- Authors: Martin Zabel -- Thomas B. Preusser -- -- License: -- =========================================================================== -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- =========================================================================== library IEEE; use IEEE.std_logic_1164.all; package uart is component uart_bclk generic ( CLK_FREQ : positive; BAUDRATE : positive ); port ( clk : in std_logic; rst : in std_logic; bclk : out std_logic; bclk_x8 : out std_logic ); end component; component uart_rx is generic ( SYNC_DEPTH : natural := 2 -- use zero for already clock-synchronous rx ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Bit Clock and RX Line bclk_x8 : in std_logic; -- bit clock, eight strobes per bit length rx : in std_logic; -- Byte Stream Output do : out std_logic_vector(7 downto 0); stb : out std_logic ); end component; component uart_tx is port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Bit Clock and TX Line bclk : in std_logic; -- bit clock, one strobe each bit length tx : out std_logic; -- Byte Stream Input di : in std_logic_vector(7 downto 0); put : in std_logic; ful : out std_logic ); end component; end uart; package body uart is end uart;

agpl-3.0

57816f5421cc2deeb63dcd9a023a4f7e

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sim_1/tb_stim_reader.vhd

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gpl-2.0

f53f43da34b40bbc7de17c9716638a81

preusser/q27

src/vhdl/top/xilinx/kc705_queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <[email protected]> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity kc705_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 250; COUNT_CYCLES : boolean := false; CLK_FREQ : FREQ := 200 MHz; CLK_DIVA : positive := 9; CLK_MULA : positive := 64; CLK_DIVB : positive := 5; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( clk_p : in std_logic; clk_n : in std_logic; rx : in std_logic; tx : out std_logic; rts : in std_logic; cts : out std_logic; -- Fan Control FanControl_PWM : out std_logic ); end kc705_queens_uart; library IEEE; use IEEE.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; library PoC; architecture rtl of kc705_queens_uart is -- Global Control constant CLK_COMP_FREQ : FREQ := CLK_FREQ / CLK_DIVA * CLK_MULA / CLK_DIVB; constant CLK_SLOW_FREQ : FREQ := CLK_FREQ / CLK_DIVA * CLK_MULA / 100; signal clk200 : std_logic; -- 200 MHz Input Clock signal clk_comp : std_logic; -- Computation Clock signal clk_slow : std_logic; -- Slow Interface Clock signal rst : std_logic; begin ----------------------------------------------------------------------------- -- Generate Global Controls blkGlobal: block is signal clkfb : std_logic; -- Feedback Clock signal clk_compu : std_logic; -- Unbuffered Synthesized Clock signal clk_slowu : std_logic; -- Unbuffered Synthesized Clock begin clk_in : IBUFGDS port map( O => clk200, I => clk_p, IB => clk_n ); pll : PLLE2_BASE generic map ( CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns), DIVCLK_DIVIDE => CLK_DIVA, CLKFBOUT_MULT => CLK_MULA, CLKOUT0_DIVIDE => CLK_DIVB, CLKOUT1_DIVIDE => 100, STARTUP_WAIT => "true" ) port map ( CLKIN1 => clk200, CLKFBIN => clkfb, RST => '0', CLKOUT0 => clk_compu, CLKOUT1 => clk_slowu, CLKOUT2 => open, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, CLKFBOUT => clkfb, LOCKED => open, PWRDWN => '0' ); comp_buf : BUFG port map ( I => clk_compu, O => clk_comp ); slow_buf : BUFH port map ( I => clk_slowu, O => clk_slow ); -- No Reset rst <= '0'; end block blkGlobal; ----------------------------------------------------------------------------- -- Fan Control fan : entity PoC.io_FanControl generic map ( CLOCK_FREQ => CLK_SLOW_FREQ ) port map ( Clock => clk_slow, Reset => '0', Fan_PWM => FanControl_PWM, TachoFrequency => open ); ---------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_uart generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES, CLK_FREQ => integer(to_real(CLK_COMP_FREQ, 1 Hz)), BAUDRATE => BAUDRATE, SENTINEL => SENTINEL ) port map ( clk => clk_comp, rst => rst, rx => rx, tx => tx, avail => open ); cts <= rts; end rtl;

agpl-3.0

52cedee3da5d12d74f387ffd321e0930

malkadi/FGPU

RTL/FGPU_tb.vhd

-- libraries --------------------------------------------------------------------------------- {{{ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.math_real.all; library work; use work.all; use work.FGPU_definitions.all; use work.FGPU_simulation_pkg.all; ------------------------------------------------------------------------------------------------- }}} ENTITY FGPU_tb IS END FGPU_tb; ARCHITECTURE behavior OF FGPU_tb IS signal target_offset_addr : natural := 0; --2**(N+L+M-1+2); constant MAX_NDRANGE_SIZE : natural := 64*1024; -- constants and functions {{{ CONSTANT clk_period : time := 5000 ps; CONSTANT C_MAXI_ID_WIDTH : natural := 6; CONSTANT S_DATA_W : integer := 32; CONSTANT N_WF_WG_ADDR : natural := 0; CONSTANT WG_SIZE_DX_ADDR : integer := 7; CONSTANT N_WG_D0_ADDR : integer := 8; CONSTANT N_WG_D1_ADDR : integer := 9; CONSTANT SIZE_D0_ADDR : natural := 1; CONSTANT SIZE_D1_ADDR : natural := 2; CONSTANT SIZE_D2_ADDR : natural := 3; CONSTANT WG_SIZE_ADDR : natural := 11; CONSTANT PARAM_ADDR : natural := 16; CONSTANT N_WF_WG_POS : natural := 28; CONSTANT WG_SIZE_D0_POS : natural := 0; CONSTANT WG_SIZE_D1_POS : natural := 10; CONSTANT WG_SIZE_D2_POS : natural := 20; CONSTANT N_DIM_POS : natural := 30; CONSTANT N_WF_WG_W : natural := 4; CONSTANT WG_SIZE_POS : natural := 0; --}}} -- general signals {{{ signal start_debug : std_logic := '0'; signal clk : std_logic := '0'; signal nrst : std_logic := '0'; signal gmem_addr : unsigned(GMEM_ADDR_W-1 downto 0) := (others => '0'); signal gmem_wrData : std_logic_vector(GMEM_DATA_W-1 downto 0) := (others => '0'); signal gmem_we : std_logic := '0'; signal gmem_re : std_logic := '0'; signal new_kernel, finished_kernel : std_logic := '0'; signal written_count : integer := 0; signal gmem_rdData : std_logic_vector(GMEM_DATA_W-1 downto 0); signal gmem_wr_ack, gmem_rd_ack : std_logic := '0'; signal size : natural := 1024; signal size_0, size_1, size_2 : integer := MAX_NDRANGE_SIZE; signal problemSize_sig : natural := 16; -- }}} -- axi slave signals {{{ signal s0_awaddr : std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0'); signal s0_awprot : std_logic_vector(2 downto 0) := (others=>'0'); signal s0_awvalid : std_logic := '0'; signal s0_awready : std_logic := '0'; signal s0_wdata : std_logic_vector(S_DATA_W-1 downto 0) := (others=>'0'); signal s0_wstrb : std_logic_vector((S_DATA_W/8)-1 downto 0) := (others=>'0'); signal s0_wvalid : std_logic := '0'; signal s0_wready : std_logic := '0'; signal s0_bresp : std_logic_vector(1 downto 0) := (others=>'0'); signal s0_bvalid : std_logic := '0'; signal s0_bready : std_logic := '0'; signal s0_araddr : std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0'); signal s0_arprot : std_logic_vector(2 downto 0) := (others=>'0'); signal s0_arvalid : std_logic := '0'; signal s0_arready : std_logic := '0'; signal s0_rdata : std_logic_vector(S_DATA_W-1 downto 0) := (others=>'0'); signal s0_rresp : std_logic_vector(1 downto 0) := (others=>'0'); signal s0_rvalid : std_logic := '0'; signal s0_rready : std_logic := '0'; -- }}} -- axi master signals {{{ -- interface 0 {{{ -- ar channel signal m0_araddr : std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); signal m0_arlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m0_arsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m0_arburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m0_arvalid : std_logic := '0'; signal m0_arready : std_logic := '0'; signal m0_arid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel signal m0_rdata : std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); signal m0_rresp : std_logic_vector(1 downto 0):= (others=>'0'); signal m0_rlast : std_logic := '0'; signal m0_rvalid : std_logic := '0'; signal m0_rready : std_logic := '0'; signal m0_rid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- aw channel signal m0_awaddr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal m0_awvalid : std_logic := '0'; signal m0_awready : std_logic := '0'; signal m0_awlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m0_awsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m0_awburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m0_awid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel signal m0_wdata : std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); signal m0_wstrb : std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); signal m0_wlast : std_logic := '0'; signal m0_wvalid : std_logic := '0'; signal m0_wready : std_logic := '0'; -- b channel signal m0_bvalid : std_logic := '0'; signal m0_bready : std_logic := '0'; signal m0_bid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); --}}} -- interface 1 {{{ -- ar channel signal m1_araddr : std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); signal m1_arlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m1_arsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m1_arburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m1_arvalid : std_logic := '0'; signal m1_arready : std_logic := '0'; signal m1_arid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel signal m1_rdata : std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); signal m1_rresp : std_logic_vector(1 downto 0):= (others=>'0'); signal m1_rlast : std_logic := '0'; signal m1_rvalid : std_logic := '0'; signal m1_rready : std_logic := '0'; signal m1_rid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- aw channel signal m1_awaddr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal m1_awvalid : std_logic := '0'; signal m1_awready : std_logic := '0'; signal m1_awlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m1_awsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m1_awburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m1_awid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel signal m1_wdata : std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); signal m1_wstrb : std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); signal m1_wlast : std_logic := '0'; signal m1_wvalid : std_logic := '0'; signal m1_wready : std_logic := '0'; -- b channel signal m1_bvalid : std_logic := '0'; signal m1_bready : std_logic := '0'; signal m1_bid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); --}}} -- interface 2 {{{ -- ar channel signal m2_araddr : std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); signal m2_arlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m2_arsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m2_arburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m2_arvalid : std_logic := '0'; signal m2_arready : std_logic := '0'; signal m2_arid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel signal m2_rdata : std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); signal m2_rresp : std_logic_vector(1 downto 0):= (others=>'0'); signal m2_rlast : std_logic := '0'; signal m2_rvalid : std_logic := '0'; signal m2_rready : std_logic := '0'; signal m2_rid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- aw channel signal m2_awaddr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal m2_awvalid : std_logic := '0'; signal m2_awready : std_logic := '0'; signal m2_awlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m2_awsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m2_awburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m2_awid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel signal m2_wdata : std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); signal m2_wstrb : std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); signal m2_wlast : std_logic := '0'; signal m2_wvalid : std_logic := '0'; signal m2_wready : std_logic := '0'; -- b channel signal m2_bvalid : std_logic := '0'; signal m2_bready : std_logic := '0'; signal m2_bid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); --}}} -- interface 3 {{{ -- ar channel signal m3_araddr : std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); signal m3_arlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m3_arsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m3_arburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m3_arvalid : std_logic := '0'; signal m3_arready : std_logic := '0'; signal m3_arid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel signal m3_rdata : std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); signal m3_rresp : std_logic_vector(1 downto 0):= (others=>'0'); signal m3_rlast : std_logic := '0'; signal m3_rvalid : std_logic := '0'; signal m3_rready : std_logic := '0'; signal m3_rid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- aw channel signal m3_awaddr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal m3_awvalid : std_logic := '0'; signal m3_awready : std_logic := '0'; signal m3_awlen : std_logic_vector(7 downto 0):= (others=>'0'); signal m3_awsize : std_logic_vector(2 downto 0):= (others=>'0'); signal m3_awburst : std_logic_vector(1 downto 0):= (others=>'0'); signal m3_awid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel signal m3_wdata : std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); signal m3_wstrb : std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); signal m3_wlast : std_logic := '0'; signal m3_wvalid : std_logic := '0'; signal m3_wready : std_logic := '0'; -- b channel signal m3_bvalid : std_logic := '0'; signal m3_bready : std_logic := '0'; signal m3_bid : std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); --}}} --}}} -- observation signals ----------------------------------------------------------------------------------{{{ signal cycles_total : nat_array(N_CU-1 downto 0) := (others=>0); signal cycles_busy : nat_array(N_CU-1 downto 0) := (others=>0); signal executing : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); ---------------------------------------------------------------------------------------------------------}}} BEGIN -- instantiate the Unit Under Test (UUT) {{{ uut: entity FGPU port map ( clk => clk, -- slave axi {{{ s0_awaddr => s0_awaddr, s0_awprot => s0_awprot, s0_awvalid => s0_awvalid, s0_awready => s0_awready, s0_wdata => s0_wdata, s0_wstrb => s0_wstrb, s0_wvalid => s0_wvalid, s0_wready => s0_wready, s0_bresp => s0_bresp, s0_bvalid => s0_bvalid, s0_bready => s0_bready, s0_araddr => s0_araddr, s0_arprot => s0_arprot, s0_arvalid => s0_arvalid, s0_arready => s0_arready, s0_rdata => s0_rdata, s0_rresp => s0_rresp, s0_rvalid => s0_rvalid, s0_rready => s0_rready, -- }}} -- axi master 0 {{{ -- ar channel m0_araddr => m0_araddr, m0_arlen => m0_arlen, m0_arsize => m0_arsize, m0_arburst => m0_arburst, m0_arvalid => m0_arvalid, m0_arready => m0_arready, m0_arid => m0_arid, -- r channel m0_rdata => m0_rdata, m0_rresp => m0_rresp, m0_rlast => m0_rlast, m0_rvalid => m0_rvalid, m0_rready => m0_rready, m0_rid => m0_rid, -- aw channel m0_awvalid => m0_awvalid, m0_awaddr => m0_awaddr, m0_awready => m0_awready, m0_awlen => m0_awlen, m0_awsize => m0_awsize, m0_awburst => m0_awburst, m0_awid => m0_awid, -- w channel m0_wdata => m0_wdata, m0_wstrb => m0_wstrb, m0_wlast => m0_wlast, m0_wvalid => m0_wvalid, m0_wready => m0_wready, -- bchannel m0_bvalid => m0_bvalid, m0_bready => m0_bready, m0_bid => m0_bid, -- }}} -- axi master 1 {{{ -- ar channel m1_araddr => m1_araddr, m1_arlen => m1_arlen, m1_arsize => m1_arsize, m1_arburst => m1_arburst, m1_arvalid => m1_arvalid, m1_arready => m1_arready, m1_arid => m1_arid, -- r channel m1_rdata => m1_rdata, m1_rresp => m1_rresp, m1_rlast => m1_rlast, m1_rvalid => m1_rvalid, m1_rready => m1_rready, m1_rid => m1_rid, -- aw channel m1_awvalid => m1_awvalid, m1_awaddr => m1_awaddr, m1_awready => m1_awready, m1_awlen => m1_awlen, m1_awsize => m1_awsize, m1_awburst => m1_awburst, m1_awid => m1_awid, -- w channel m1_wdata => m1_wdata, m1_wstrb => m1_wstrb, m1_wlast => m1_wlast, m1_wvalid => m1_wvalid, m1_wready => m1_wready, -- bchannel m1_bvalid => m1_bvalid, m1_bready => m1_bready, m1_bid => m1_bid, -- }}} -- axi master 2 {{{ -- ar channel m2_araddr => m2_araddr, m2_arlen => m2_arlen, m2_arsize => m2_arsize, m2_arburst => m2_arburst, m2_arvalid => m2_arvalid, m2_arready => m2_arready, m2_arid => m2_arid, -- r channel m2_rdata => m2_rdata, m2_rresp => m2_rresp, m2_rlast => m2_rlast, m2_rvalid => m2_rvalid, m2_rready => m2_rready, m2_rid => m2_rid, -- aw channel m2_awvalid => m2_awvalid, m2_awaddr => m2_awaddr, m2_awready => m2_awready, m2_awlen => m2_awlen, m2_awsize => m2_awsize, m2_awburst => m2_awburst, m2_awid => m2_awid, -- w channel m2_wdata => m2_wdata, m2_wstrb => m2_wstrb, m2_wlast => m2_wlast, m2_wvalid => m2_wvalid, m2_wready => m2_wready, -- bchannel m2_bvalid => m2_bvalid, m2_bready => m2_bready, m2_bid => m2_bid, -- }}} -- axi master 3 {{{ -- ar channel m3_araddr => m3_araddr, m3_arlen => m3_arlen, m3_arsize => m3_arsize, m3_arburst => m3_arburst, m3_arvalid => m3_arvalid, m3_arready => m3_arready, m3_arid => m3_arid, -- r channel m3_rdata => m3_rdata, m3_rresp => m3_rresp, m3_rlast => m3_rlast, m3_rvalid => m3_rvalid, m3_rready => m3_rready, m3_rid => m3_rid, -- aw channel m3_awvalid => m3_awvalid, m3_awaddr => m3_awaddr, m3_awready => m3_awready, m3_awlen => m3_awlen, m3_awsize => m3_awsize, m3_awburst => m3_awburst, m3_awid => m3_awid, -- w channel m3_wdata => m3_wdata, m3_wstrb => m3_wstrb, m3_wlast => m3_wlast, m3_wvalid => m3_wvalid, m3_wready => m3_wready, -- bchannel m3_bvalid => m3_bvalid, m3_bready => m3_bready, m3_bid => m3_bid, -- }}} nrst => nrst -- loc_mem_rdAddr_dummy => loc_mem_rdAddr_dummy ); --}}} -- instantiate globel memory & cram{{{ gmem_inst: entity global_mem generic map( MAX_NDRANGE_SIZE => MAX_NDRANGE_SIZE ) port map ( new_kernel => new_kernel, finished_kernel => finished_kernel, size_0 => size_0, size_1 => size_1, problemSize => problemSize_sig, target_offset_addr => target_offset_addr, -- AXI Slave Interface mx_arlen_awlen => m0_arlen, -- interface 0{{{ -- ar channel m0_araddr => m0_araddr, m0_arvalid => m0_arvalid, m0_arready => m0_arready, m0_arid => m0_arid, -- r channel m0_rdata => m0_rdata, m0_rlast => m0_rlast, m0_rvalid => m0_rvalid, m0_rready => m0_rready, m0_rid => m0_rid, -- aw channel m0_awvalid => m0_awvalid, m0_awaddr => m0_awaddr, m0_awready => m0_awready, m0_awid => m0_awid, -- w channel m0_wdata => m0_wdata, m0_wstrb => m0_wstrb, m0_wlast => m0_wlast, m0_wvalid => m0_wvalid, m0_wready => m0_wready, -- b channel m0_bready => m0_bready, m0_bvalid => m0_bvalid, m0_bid => m0_bid, --}}} -- interface 1 {{{ -- ar channel m1_araddr => m1_araddr, m1_arvalid => m1_arvalid, m1_arready => m1_arready, m1_arid => m1_arid, -- r channel m1_rdata => m1_rdata, m1_rlast => m1_rlast, m1_rvalid => m1_rvalid, m1_rready => m1_rready, m1_rid => m1_rid, -- aw channel m1_awvalid => m1_awvalid, m1_awaddr => m1_awaddr, m1_awready => m1_awready, m1_awid => m1_awid, -- w channel m1_wdata => m1_wdata, m1_wstrb => m1_wstrb, m1_wlast => m1_wlast, m1_wvalid => m1_wvalid, m1_wready => m1_wready, -- b channel m1_bready => m1_bready, m1_bvalid => m1_bvalid, m1_bid => m1_bid, --}}} -- interface 2 {{{ -- ar channel m2_araddr => m2_araddr, m2_arvalid => m2_arvalid, m2_arready => m2_arready, m2_arid => m2_arid, -- r channel m2_rdata => m2_rdata, m2_rlast => m2_rlast, m2_rvalid => m2_rvalid, m2_rready => m2_rready, m2_rid => m2_rid, -- aw channel m2_awvalid => m2_awvalid, m2_awaddr => m2_awaddr, m2_awready => m2_awready, m2_awid => m2_awid, -- w channel m2_wdata => m2_wdata, m2_wstrb => m2_wstrb, m2_wlast => m2_wlast, m2_wvalid => m2_wvalid, m2_wready => m2_wready, -- b channel m2_bready => m2_bready, m2_bvalid => m2_bvalid, m2_bid => m2_bid, --}}} -- interface 3 {{{ -- ar channel m3_araddr => m3_araddr, m3_arvalid => m3_arvalid, m3_arready => m3_arready, m3_arid => m3_arid, -- r channel m3_rdata => m3_rdata, m3_rlast => m3_rlast, m3_rvalid => m3_rvalid, m3_rready => m3_rready, m3_rid => m3_rid, -- aw channel m3_awvalid => m3_awvalid, m3_awaddr => m3_awaddr, m3_awready => m3_awready, m3_awid => m3_awid, -- w channel m3_wdata => m3_wdata, m3_wstrb => m3_wstrb, m3_wlast => m3_wlast, m3_wvalid => m3_wvalid, m3_wready => m3_wready, -- b channel m3_bready => m3_bready, m3_bvalid => m3_bvalid, m3_bid => m3_bid, --}}} clk => clk, nrst => nrst ); --}}} -- clock process definitions {{{ clk_process :process begin clk <= '0'; wait for clk_period; clk <= not clk; wait for clk_period; end process; --}}} -- stimuls process {{{ process -- variables {{{ variable tmp_integer : integer := 0; variable nStages, stageIndx, passIndx : integer := 0; variable wg_size : integer := 100; variable size_d0, size_d1, size_d2 : integer := MAX_NDRANGE_SIZE; variable wg_size_d0, wg_size_d1, wg_size_d2 : natural := 1; variable nDim : natural := 1; variable reduce_factor_sum : natural := 4; variable minReduceSize : natural := 8; variable problemSize : natural := 16; variable swap_base_target : boolean := false; --}}} -- procedures {{{ procedure swap_base_target_params is --{{{ variable tmp1, tmp2 : std_logic_vector(DATA_W-1 downto 0); begin s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+0,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; tmp1 := s0_rdata; s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+1,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; tmp2 := s0_rdata; s0_wdata <= tmp2; wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+0,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; s0_awvalid <= '0'; s0_wvalid <= '0'; wait until rising_edge(clk); s0_wdata <= tmp1; s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+1,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure write_param(factor: in integer; paramIndx: in integer) is --{{{ begin s0_wdata <= std_logic_vector(to_unsigned(factor, DATA_W)); wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+paramIndx,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure replace_target_addr is --{{{ variable target_param : natural := 0; begin case kernel_name is when floydwarshall => target_param := 0; when copy | bitonic | add_float | parallelSelection | sum_atomic | fft_hard | sobel | median | max_half_atomic => target_param := 1; when fadd | mat_mul | fir | xcorr | mul_float | fir_char4 => target_param := 2; when others => report "undefined kernel index" severity failure; end case; s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+target_param,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; s0_wdata <= std_logic_vector(unsigned(s0_rdata) + to_unsigned(target_offset_addr, DATA_W)); wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(PARAM_ADDR+target_param,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure write_WG_size_dx_sch_ram(nDim, wg_size_d0, wg_size_d1, wg_size_d2: in natural) is --{{{ begin s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 5) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(WG_SIZE_DX_ADDR,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_wdata(WG_SIZE_D0_POS+WG_SIZE_W downto WG_SIZE_D0_POS) <= std_logic_vector(to_unsigned(wg_size_d0, WG_SIZE_W+1)); s0_wdata(WG_SIZE_D1_POS+WG_SIZE_W downto WG_SIZE_D1_POS) <= std_logic_vector(to_unsigned(wg_size_d1, WG_SIZE_W+1)); s0_wdata(WG_SIZE_D2_POS+WG_SIZE_W downto WG_SIZE_D2_POS) <= std_logic_vector(to_unsigned(wg_size_d2, WG_SIZE_W+1)); s0_wdata(N_DIM_POS+1 downto N_DIM_POS) <= std_logic_vector(to_unsigned(nDim-1, 2)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure update_WG_size_sch_ram (val: in integer) is --{{{ begin s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(WG_SIZE_ADDR,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; s0_wdata <= s0_rdata; wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(WG_SIZE_ADDR,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_wdata(WG_SIZE_POS+WG_SIZE_W downto WG_SIZE_POS) <= std_logic_vector(to_unsigned(val, WG_SIZE_W+1)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure update_nWF_WG_sch_ram (val: in integer) is --{{{ begin s0_araddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_araddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_araddr(4 downto 0) <= std_logic_vector(to_unsigned(N_WF_WG_ADDR,5)); s0_araddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; s0_wdata <= s0_rdata; wait until rising_edge(clk); s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 9) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(N_WF_WG_ADDR,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_wdata(N_WF_WG_POS+N_WF_WG_W-1 downto N_WF_WG_POS) <= std_logic_vector(to_unsigned(val, N_WF_WG_W)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure write_cram ( addr: in integer; val: in integer) is -- {{{ begin s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "01"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 0) <= std_logic_vector(to_unsigned(addr,INTERFCE_W_ADDR_W-2)); s0_wdata <= std_logic_vector(to_unsigned(val, DATA_W)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure write_sch_ram ( addr: in integer; val: in integer) is -- {{{ begin s0_awaddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) <= "00"; s0_awaddr(INTERFCE_W_ADDR_W-3 downto 5) <= (others=>'0'); s0_awaddr(4 downto 0) <= std_logic_vector(to_unsigned(addr,5)); s0_awaddr(8 downto 5) <= std_logic_vector(to_unsigned(get_kernel_index(kernel_name),4)); s0_wdata <= std_logic_vector(to_unsigned(val, DATA_W)); s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure clear_write_cache is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(RcleanCache_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure set_write_cache is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(RcleanCache_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_wdata(get_kernel_index(kernel_name)) <= '1'; s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure set_initialize is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(RInitiate_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_wdata(get_kernel_index(kernel_name)) <= '1'; s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure clear_initialize is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(RInitiate_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_awvalid <= '1'; s0_wvalid <= '1'; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; end procedure; --}}} procedure start_kernel(initialize_gmem : in integer) is --{{{ begin s0_awaddr <= std_logic_vector(to_unsigned(Rstart_addr, INTERFCE_W_ADDR_W)); s0_wdata <= X"0000_0000"; s0_wdata(get_kernel_index(kernel_name)) <= '1'; s0_awvalid <= '1'; s0_wvalid <= '1'; if initialize_gmem /= 0 then new_kernel <= '1'; end if; size <= size_d0*size_d1*size_d2; wait until s0_awready = '1' and s0_wready = '1'; wait until rising_edge(clk); s0_awvalid <= '0'; s0_wvalid <= '0'; new_kernel <= '0'; end procedure; --}}} procedure read_status0_reg( res: out std_logic_vector(DATA_W-1 downto 0)) is --{{{ begin s0_araddr <= std_logic_vector(to_unsigned(Rstat_addr, INTERFCE_W_ADDR_W)); s0_arvalid <= '1'; wait until s0_arready = '1'; wait until rising_edge(clk); s0_arvalid <= '0'; wait until s0_rvalid = '1'; res := s0_rdata; wait until rising_edge(clk); end procedure; --}}} procedure wait_to_finish is --{{{ variable tmp : std_logic_vector(DATA_W-1 downto 0); begin read_status0_reg(tmp); while to_integer(unsigned(tmp)) = 0 loop read_status0_reg(tmp); end loop; finished_kernel <= '1'; wait until rising_edge(clk); finished_kernel <= '0'; -- wait for 20*clk_period; -- the finish flag is set when the last axi_write is issued. Some extra cycles are still needed end procedure; --}}} procedure download_code is --{{{ begin case kernel_name is when copy => --copy case COMP_TYPE is when 0 => -- byte write_cram(9, 16#71000462#); write_cram(10, 16#21000C64#); write_cram(11, 16#28001042#); write_cram(13, 16#79001062#); when 1 => --half write_cram(9, 16#72000462#); write_cram(10, 16#21001064#); write_cram(11, 16#28001042#); write_cram(13, 16#7A001062#); when others => -- word write_cram(9, 16#74000462#); write_cram(10, 16#00000000#); write_cram(11, 16#00000000#); write_cram(13, 16#7C001062#); end case; when others => end case; end procedure; --}}} -- }}} begin report "Kernel Nr. "& integer'image(get_kernel_index(kernel_name)); wait for clk_period; nrst <= '1'; wait for 2*clk_period; s0_rready <= '1'; case kernel_name is when mat_mul | median | floydwarshall | sobel => nDim := 2; when others => nDim := 1; end case; replace_target_addr; download_code; set_initialize; size_d2 := 1; for i in 1 to 64 loop -- wait for 2*clk_period; case kernel_name is when mat_mul | floydwarshall | median=> wg_size_d0 := 8; wg_size_d1 := 8; wg_size := wg_size_d0 * wg_size_d1; size_d0 := wg_size_d0*i; size_d1 := wg_size_d1*i; when sobel => wg_size_d0 := 4; wg_size_d1 := 4; problemSize := 16; size_d0 := 4; size_d1 := 4; wg_size := wg_size_d0 * wg_size_d1; when bitonic | fft_hard => wg_size_d0 := 64; size_d0 := 1024*i; -- size_d0 := wg_size_d0*2**(i-1); problemSize := size_d0*2; wg_size := wg_size_d0; when others => wg_size_d0 := 64; -- size_d0 := (i+8)*1024; size_d0 := 64*i; -- size_d0 := 128*2**(i-1); -- size_d0 := wg_size_d0*i; size_d1 := 1; wg_size_d1 := 1; wg_size := wg_size_d0; problemSize := REDUCE_FACTOR*size_d0; end case; problemSize_sig <= problemSize; assert wg_size <= WF_SIZE*8 severity failure; case kernel_name is when fft_hard => -- {{{ -- clear_write_cache; set_write_cache; set_initialize; nStages := 0; tmp_integer := 1; while tmp_integer < problemSize loop tmp_integer := tmp_integer * 2; nStages := nStages + 1; end loop; stageIndx := 0; report "problemSize = " & integer'image(problemSize) & ", nStages = " & integer'image(nStages); while stageIndx /= nStages loop report "stageIndx = " & integer'image(stageIndx); if (wg_size mod WF_SIZE ) = 0 then update_nWF_WG_sch_ram(wg_size/WF_SIZE-1); else update_nWF_WG_sch_ram(wg_size/WF_SIZE); end if; write_sch_ram(SIZE_D0_ADDR, size_d0); write_WG_size_dx_sch_ram(nDim, wg_size_d0, wg_size_d1, wg_size_d2); update_WG_size_sch_ram(wg_size); write_sch_ram(N_WG_D0_ADDR, max(size_d0/wg_size_d0-1, 0)); write_param(stageIndx, 1); size_0 <= size_d0; if stageIndx = 0 then start_kernel(1); else start_kernel(0); end if; stageIndx := stageIndx + 1; if stageIndx = nStages then set_write_cache; -- report "cache write set"; end if; wait_to_finish; clear_initialize; -- if stageIndx = 1 then -- start_debug <= '1'; -- end if; end loop; -- }}} when bitonic => -- {{{ -- clear_write_cache; set_write_cache; set_initialize; nStages := 0; tmp_integer := 1; while tmp_integer < problemSize loop tmp_integer := tmp_integer * 2; nStages := nStages + 1; end loop; stageIndx := 0; passIndx := 0; report "problemSize = " & integer'image(problemSize) & ", nStages = " & integer'image(nStages); write_param(0, 3); -- direction is decreasing while stageIndx /= nStages loop -- report "stageIndx = " & integer'image(stageIndx) & ", passIndx = " & integer'image(passIndx); if (wg_size mod WF_SIZE ) = 0 then update_nWF_WG_sch_ram(wg_size/WF_SIZE-1); else update_nWF_WG_sch_ram(wg_size/WF_SIZE); end if; write_sch_ram(SIZE_D0_ADDR, size_d0); write_WG_size_dx_sch_ram(nDim, wg_size_d0, wg_size_d1, wg_size_d2); update_WG_size_sch_ram(wg_size); write_sch_ram(N_WG_D0_ADDR, max(size_d0/wg_size_d0-1, 0)); write_param(stageIndx, 1); write_param(passIndx, 2); size_0 <= size_d0; if passIndx = 0 and stageIndx = 0 then start_kernel(1); else start_kernel(0); end if; if passIndx < stageIndx then passIndx := passIndx + 1; else passIndx := 0; stageIndx := stageIndx + 1; if stageIndx = nStages then set_write_cache; -- report "cache write set"; end if; end if; wait_to_finish; clear_initialize; if stageIndx = 1 and passIndx = 1 then start_debug <= '1'; end if; wait for 50*clk_period; end loop; -- wait for 100*clk_period; -- assert false severity failure; if kernel_name = bitonic then report "bitonic_kernel finished"; else report "bitonic_kernel_float finished"; end if; -- }}} when others => -- {{{ if (wg_size mod WF_SIZE ) = 0 then update_nWF_WG_sch_ram(wg_size/WF_SIZE-1); else update_nWF_WG_sch_ram(wg_size/WF_SIZE); end if; -- write_sch_ram(WG_SIZE_DX_ADDR, wg_size); write_sch_ram(SIZE_D0_ADDR, size_d0); write_sch_ram(SIZE_D1_ADDR, size_d1); write_sch_ram(SIZE_D2_ADDR, size_d2); write_WG_size_dx_sch_ram(nDim, wg_size_d0, wg_size_d1, wg_size_d2); update_WG_size_sch_ram(wg_size); write_sch_ram(N_WG_D0_ADDR, max(size_d0/wg_size_d0-1, 0)); write_sch_ram(N_WG_D1_ADDR, max(size_d1/wg_size_d1-1, 0)); if kernel_name = max_half_atomic or kernel_name = sum_atomic then write_param(REDUCE_FACTOR, 3); end if; size_0 <= size_d0; size_1 <= size_d1; set_write_cache; start_kernel(1); -- clear_initialize; wait_to_finish; -- }}} end case; end loop; report "END of simulation" severity failure; wait; end process; -- }}} -- observing the CVs load ------------------------------------------------------------------------------{{{ CV_load: if STAT_LOAD = 1 generate begin busy_calculation: for i in 0 to N_CU-1 generate begin process(clk) alias start_CUs is <<signal .FGPU_tb.uut.start_CUs : std_logic >>; alias wf_active is <<signal .FGPU_tb.uut.wf_active : wf_active_array >>; begin if rising_edge(clk) then if <<signal .FGPU_tb.uut.compute_units_i(i).compute_unit_inst.instr: std_logic_vector >> /= (0 to DATA_W-1 => '0') then cycles_busy(i) <= cycles_busy(i) + 1; end if; if start_CUs = '1' then cycles_busy(i) <= 0; end if; if wf_active(i) /= (0 to N_WF_CU-1=>'0') then executing(i) <= '1'; end if; if wf_active(i) = (0 to N_WF_CU-1=>'0') then executing(i) <= '0'; end if; if start_CUs = '1' then cycles_total(i) <= 0; end if; if executing(i) = '1' then cycles_total(i) <= cycles_total(i) + 1; end if; end if; end process; end generate; process(clk) alias start_CUs is <<signal .FGPU_tb.uut.start_CUs : std_logic >>; alias finish_exec is << signal .FGPU_tb.uut.finish_exec : std_logic >>; variable load_ratio : real_array(N_CU-1 downto 0); variable statistics_printed : std_logic := '0'; variable load_average : real; variable std : real; variable n_active_CUs: natural; begin if rising_edge(clk) then if start_CUs = '1' then statistics_printed := '0'; end if; if finish_exec = '1' and statistics_printed = '0' then statistics_printed := '1'; load_average := 0.0; std := 0.0; n_active_CUs := 0; for i in 0 to N_CU-1 loop if cycles_total(i) /= 0 then n_active_CUs := n_active_CUs + 1; load_ratio(i) := real((cycles_busy(i) * 100)) / real(cycles_total(i)); load_average := load_average + load_ratio(i); std := std + real(load_ratio(i)*load_ratio(i)); -- report "Average load on CU " & integer'image(i) & " is " & integer'image(integer(round(load_ratio(i)))) & "%"; end if; end loop; load_average := load_average / real(n_active_CUs); std := sqrt(std/real(n_active_CUs) - load_average*load_average); report "Average CU load is " & integer'image(integer(round(load_average))) & "% width stnadard deviation of " & integer'image(integer(round(std))) & "%"; end if; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- }}} END;

gpl-3.0

47b49f676b165af269e6e7064c11677b

malkadi/FGPU

RTL/rd_cache_fifo.vhd

-- libraries --------------------------------------------------------------------------------------------{{{ library ieee; use ieee.std_logic_1164.all; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity rd_cache_fifo is -- {{{ -- cu_mem_cntrl <- port A (myram) port B -> cache generic( SIZEA : integer := 1024; ADDRWIDTHA : integer := 10; SIZEB : integer := 256; ADDRWIDTHB : integer := 8 ); port( clk : in std_logic; push : in std_logic; cache_rdData : in std_logic_vector(DATA_W*CACHE_N_BANKS - 1 downto 0); cache_rdAddr : in unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); rdData : out std_logic_vector(DATA_W*RD_CACHE_N_WORDS - 1 downto 0); rdAddr : out unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0) := (others=>'0'); nempty : out std_logic := '0'; nrst : in std_logic ); end entity; -- }}} architecture behavioral of rd_cache_fifo is function log2(val : INTEGER) return natural is -- {{{ variable res : natural; begin for i in 0 to 31 loop if (val <= (2 ** i)) then res := i; exit; end if; end loop; return res; end function Log2; -- }}} -- signals {{{ constant minWIDTH : integer := DATA_W*RD_CACHE_N_WORDS; constant maxSIZE : integer := SIZEA; constant RATIO : integer := CACHE_N_BANKS*DATA_W/minWIDTH; -- An asymmetric RAM is modeled in a similar way as a symmetric RAM, with an -- array of array object. Its aspect ratio corresponds to the port with the -- lower data width (larger depth) type ramType is array (natural range <>) of std_logic_vector(minWIDTH - 1 downto 0); -- cu_mem_cntrl <- port A (myram) port B -> cache signal data_fifo : ramType(0 to maxSIZE-1) := (others=>(others=>'0')); type addr_fifo_type is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0); signal addr_fifo : addr_fifo_type(0 to maxSIZE-1) := (others=>(others=>'0')); signal data_fifo_rdData_n : std_logic_vector(DATA_W*RD_CACHE_N_WORDS-1 downto 0) := (others => '0'); signal data_fifo_rdData : std_logic_vector(DATA_W*RD_CACHE_N_WORDS-1 downto 0) := (others => '0'); signal addr_fifo_rdData_n : unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0) := (others=>'0'); signal addr_fifo_rdData : unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0) := (others=>'0'); signal addrA : unsigned(ADDRWIDTHA - 1 downto 0) := (others=>'0'); signal addrB : unsigned(ADDRWIDTHB - 1 downto 0) := (others=>'0'); signal enB, enA : std_logic := '0'; signal nempty_p0 : std_logic := '0'; -- }}} begin enB <= '1'; enA <= '1'; -- addr fifo -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then if enA = '1' then addr_fifo_rdData_n <= addr_fifo(to_integer(addrA)); end if; addr_fifo_rdData <= addr_fifo_rdData_n; end if; end process; rdAddr <= addr_fifo_rdData; process(clk) begin if rising_edge(clk) then for i in 0 to RATIO - 1 loop if enB = '1' then if push = '1' then addr_fifo(to_integer(addrB & to_unsigned(i, log2(RATIO)))) <= cache_rdAddr & to_unsigned(i, log2(RATIO)); end if; end if; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- data fifo -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then if enA = '1' then data_fifo_rdData_n <= data_fifo(to_integer(addrA)); end if; data_fifo_rdData <= data_fifo_rdData_n; end if; end process; rdData <= data_fifo_rdData; process(clk) begin if rising_edge(clk) then for i in 0 to RATIO - 1 loop if enB = '1' then if push = '1' then data_fifo(to_integer(addrB & to_unsigned(i, log2(RATIO)))) <= cache_rdData((i + 1) * minWIDTH - 1 downto i * minWIDTH); end if; end if; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} process(clk) begin if rising_edge(clk) then if addrA(addrA'high downto addrA'high-ADDRWIDTHB+1) /= addrB then nempty_p0 <= '1'; else nempty_p0 <= '0'; end if; nempty <= nempty_p0; if nrst = '0' then addrB <= (others=>'0'); addrA <= (others=>'0'); else if enB = '1' and push = '1' then addrB <= addrB + 1; end if; if addrA(addrA'high downto addrA'high-ADDRWIDTHB+1) /= addrB then addrA <= addrA + 1; end if; end if; end if; end process; end architecture;

gpl-3.0

5f674a0ef96d20cb5b4eb13c9a586ff1

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_4AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 2; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a3968fbf9ed5a1eb58ed6c06ef906c37

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_tx_serializer.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_tx_serializer | -- | --------------------------------------------------------------------------------------------------- -- File wf_tx_serializer.vhd | -- | -- Description The unit is generating the nanoFIP FIELDRIVE outputs FD_TXD and FD_TXENA. | -- It is retreiving bytes of data from: | -- o the wf_production (from the CTRL byte until the MPS) | -- o WF_PACKAGE (FSS and FES bytes) | -- o and the wf_crc (FCS bytes). | -- | -- It encodes the bytes to the Manchester 2 (manch.)scheme and outputs one by one the| -- encoded bits on the moments indicated by the wf_tx_osc unit. | -- | -- Reminder of the Produced RP_DAT frame structure : | -- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| | -- | -- |------------- Bytes from the wf_production -------------| | -- | -- | -- Authors Pablo Alvarez Sanchez ([email protected]) | -- Evangelia Gousiou ([email protected]) | -- Date 07/2011 | -- Version v0.05 | -- Depends on wf_engine_control | -- wf_production | -- wf_tx_osc | -- wf_reset_unit | ---------------- | -- Last changes | -- v0.02 2009 PAS Entity Ports added, start of architecture content | -- v0.03 07/2010 EG timing changes; tx_sched_p_buff_i got 1 more bit | -- briefly byte_index_i needed to arrive 1 clock tick earlier | -- renamed from tx to tx_serializer; | -- STOP_TRANSMISSION state added for the synch of txena | -- v0.04 01/2011 EG SYNC_TO_TXCK state added to start always with the bits 1,2,3 of the | -- clock buffer available(tx_start_p_i may arrive at any time) | -- tx_completed_p_o signal added | -- v0.05 07/2011 EG bits_to_txd unit removed | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_tx_serializer --================================================================================================= entity wf_tx_serializer is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signals from the wf_production byte_i : in std_logic_vector (7 downto 0); -- byte to be delivered -- Signals from the wf_engine_control unit tx_start_p_i : in std_logic; -- indication for the start of the production byte_request_accept_p_i : in std_logic; -- indication that a byte is ready to be delivered last_byte_p_i : in std_logic; -- indication of the last data byte -- (CRC, FES not included) -- Signal from the wf_tx_osc tx_sched_p_buff_i : in std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0); -- pulses for the transmission synchronization -- OUTPUTS -- Signal to the wf_engine_control unit tx_byte_request_p_o : out std_logic; -- request for a new byte tx_completed_p_o : out std_logic; -- pulse upon the end of transmission -- Signal to the wf_tx_osc unit tx_osc_rst_p_o : out std_logic; -- oscillator reset after a transmission error -- nanoFIP FIELDRIVE outputs tx_data_o : out std_logic; -- transmitter serial data tx_enable_o : out std_logic);-- transmitter enable end entity wf_tx_serializer; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_tx_serializer is -- FSM type tx_st_t is (IDLE, SYNC_TO_TXCK, SEND_FSS, SEND_DATA_BYTE, SEND_CRC_BYTES, SEND_FES, STOP_TRANSMISSION); signal tx_st, nx_tx_st : tx_st_t; signal s_prepare_to_produce, s_sending_fss, s_sending_data : std_logic; signal s_sending_crc, s_sending_fes, s_stop_transmission : std_logic; -- bits counter signal s_bit_index_decr_p,s_bit_index_load, s_bit_index_is_zero : std_logic; signal s_bit_index, s_bit_index_top : unsigned (4 downto 0); -- transmitter output signal s_txd : std_logic; -- byte to be transmitted signal s_data_byte : std_logic_vector (7 downto 0); signal s_data_byte_manch : std_logic_vector (15 downto 0); -- CRC calculations signal s_start_crc_p, s_data_bit_to_crc_p : std_logic; signal s_crc_bytes : std_logic_vector (15 downto 0); signal s_crc_bytes_manch : std_logic_vector (31 downto 0); -- independent timeout counter signal s_session_timedout : std_logic; --================================================================================================= -- architecture begin --================================================================================================= begin -- The signal tx_sched_p_buff_i is used for the scheduling of the state transitions of the machine -- as well as of the actions on the output signals. -- The following drawing shows the transitions of the signal tx_sched_p_buff_i with respect to -- the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit clock). -- FD_TXCK : _________|-------...---------|________...________|-------...---------|____ -- tx_sched_p_buff(3): |0|0|0|1 |0|0|0|1 -- tx_sched_p_buff(2): |0|0|1|0 |0|0|1|0 -- tx_sched_p_buff(1): |0|1|0|0 |0|1|0|0 -- tx_sched_p_buff(0): |1|0|0|0 |1|0|0|0 ---------------------- -- new byte request : ^ -- new byte ready : . . ^ -- 1st bit of new . . . . . . . . . . . . . . . . . .^ -- byte delivery : -- bit counter : [ 15 . . .][ 14 -- A new bit is delivered after the assertion of tx_sched_p_buff (1). -- The counter Outgoing_Bits_Index that keeps the index of a bit being delivered is updated after -- the delivery of the bit, after the tx_sched_p_buff (3) assertion. The counter is ahead of the -- bit being sent. -- In the sending_bytes state, where the unit is expecting data bytes from the wf_production, -- the unit delivers a request for a new byte after the tx_sched_p_buff (0) assertion, -- and when the Outgoing_Bits_Index counter is empty (which means that the last bit of a previous -- byte is now being delivered). -- The wf_engine_control responds to the request by sending a new address to the wf_production -- for the retrieval of a byte from the memory or the stand-alone bus. -- The byte becomes available at the byte_request_accept_p_i pulse, 2 cycles after the request, -- and starts being transmitted at the tx_sched_p_buff (1) of the next FD_TXCK cycle. -- The wf_engine_control is the one keeping track of the amount of bytes delivered and asserts -- the last_byte_p_i signal accordingly; after the arrival of this signal the serializer's FSM -- proceeds with the transmission of the CRC and the FES bytes and then goes back to IDLE. -- To add a robust layer of protection to the FSM, we have implemented a counter, dependent only -- on the system clock, that from any state can bring the FSM back to IDLE. At any bit rate the -- transmission of the longest RP_DAT should not last more than 35ms. Hence, we have generated a -- 21 bits (c_SESSION_TIMEOUT_C_LGTH) counter that will reset the machine if more than 52ms -- (complete 21 bit counter) have passed since it has left this IDLE state. --------------------------------------------------------------------------------------------------- -- Serializer's FSM -- --------------------------------------------------------------------------------------------------- -- Serializer's state machine: the state machine is divided in three parts (a clocked -- process to store the current state, a combinatorial process to manage state transitions and -- finally a combinatorial process to manage the output signals), which are the 3 processes that -- follow. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Synchronous process Serializer_FSM_Sync: Serializer_FSM_Sync: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' or s_session_timedout = '1' then tx_st <= IDLE; else tx_st <= nx_tx_st; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Combinatorial process Serializer_FSM_Comb_State_Transitions Serializer_FSM_Comb_State_Transitions: process (tx_st, tx_start_p_i, last_byte_p_i, s_bit_index_is_zero, tx_sched_p_buff_i) begin case tx_st is when IDLE => if tx_start_p_i = '1' then -- trigger from wf_engine_control nx_tx_st <= SYNC_TO_TXCK; else nx_tx_st <= IDLE; end if; when SYNC_TO_TXCK => -- synch to the free running FD_TXTCK if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-4) = '1' then nx_tx_st <= SEND_FSS; else nx_tx_st <= SYNC_TO_TXCK; end if; when SEND_FSS => -- delivery of 2 FSS bytes if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1) = '1') then nx_tx_st <= SEND_DATA_BYTE; else nx_tx_st <= SEND_FSS; end if; when SEND_DATA_BYTE => -- delivery of several data bytes -- until the last_byte_p_i notification if last_byte_p_i = '1' then nx_tx_st <= SEND_CRC_BYTES; else nx_tx_st <= SEND_DATA_BYTE; end if; when SEND_CRC_BYTES => -- delivery of 2 CRC bytes if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then nx_tx_st <= SEND_FES; -- state change early enough (tx_sched_p_buff_i(2)) -- for the Outgoing_Bits_Index, that is loaded on -- tx_sched_p_buff_i(3), to get the 31 as top value else nx_tx_st <= SEND_CRC_BYTES; end if; when SEND_FES => -- delivery of 1 FES byte if (s_bit_index_is_zero = '1') and (tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1') then nx_tx_st <= STOP_TRANSMISSION; -- state change early enough (tx_sched_p_buff_i(2)) -- for the Outgoing_Bits_Index that is loaded on -- tx_sched_p_buff_i(3) to get the 15 as top value else nx_tx_st <= SEND_FES; end if; when STOP_TRANSMISSION => -- end of transmission synchronous to the FD_TXCK if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2) = '1' then nx_tx_st <= IDLE; else nx_tx_st <= STOP_TRANSMISSION; end if; when OTHERS => nx_tx_st <= IDLE; end case; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Combinatorial process Serializer_FSM_Comb_Output_Signals Serializer_FSM_Comb_Output_Signals: process ( tx_st ) begin case tx_st is when IDLE | SYNC_TO_TXCK => --------------------------------- s_prepare_to_produce <= '1'; --------------------------------- s_sending_fss <= '0'; s_sending_data <= '0'; s_sending_crc <= '0'; s_sending_fes <= '0'; s_stop_transmission <= '0'; when SEND_FSS => s_prepare_to_produce <= '0'; --------------------------------- s_sending_fss <= '1'; --------------------------------- s_sending_data <= '0'; s_sending_crc <= '0'; s_sending_fes <= '0'; s_stop_transmission <= '0'; when SEND_DATA_BYTE => s_prepare_to_produce <= '0'; s_sending_fss <= '0'; --------------------------------- s_sending_data <= '1'; --------------------------------- s_sending_crc <= '0'; s_sending_fes <= '0'; s_stop_transmission <= '0'; when SEND_CRC_BYTES => s_prepare_to_produce <= '0'; s_sending_fss <= '0'; s_sending_data <= '0'; --------------------------------- s_sending_crc <= '1'; --------------------------------- s_sending_fes <= '0'; s_stop_transmission <= '0'; when SEND_FES => s_prepare_to_produce <= '0'; s_sending_fss <= '0'; s_sending_data <= '0'; s_sending_crc <= '0'; --------------------------------- s_sending_fes <= '1'; --------------------------------- s_stop_transmission <= '0'; when STOP_TRANSMISSION => s_prepare_to_produce <= '0'; s_sending_fss <= '0'; s_sending_data <= '0'; s_sending_crc <= '0'; s_sending_fes <= '0'; --------------------------------- s_stop_transmission <= '1'; --------------------------------- when OTHERS => --------------------------------- s_prepare_to_produce <= '1'; --------------------------------- s_sending_fss <= '0'; s_sending_data <= '0'; s_sending_crc <= '0'; s_sending_fes <= '0'; s_stop_transmission <= '0'; end case; end process; --------------------------------------------------------------------------------------------------- -- Input Byte Retrieval -- --------------------------------------------------------------------------------------------------- Input_Byte_Retrieval: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_data_byte <= (others => '0'); else if byte_request_accept_p_i = '1' then s_data_byte <= byte_i; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Manchester Encoding -- --------------------------------------------------------------------------------------------------- s_data_byte_manch <= f_manch_encoder (s_data_byte); s_crc_bytes_manch <= f_manch_encoder (s_crc_bytes); --------------------------------------------------------------------------------------------------- -- CRC calculation -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instantiation of the CRC unit crc_generation: wf_crc port map( uclk_i => uclk_i, nfip_rst_i => nfip_rst_i, start_crc_p_i => s_start_crc_p, data_bit_ready_p_i => s_data_bit_to_crc_p, data_bit_i => s_txd, crc_ok_p_o => open, ------------------------------------------------- crc_o => s_crc_bytes); ------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- concurrent signals assignement for the crc_generator inputs s_start_crc_p <= s_sending_fss and s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1); -- the CRC calculation starts when at the end of th e FSS (beginning of data bytes delivery) s_data_bit_to_crc_p <= s_sending_data and s_bit_index(0) and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1); -- only the 1st part of a manchester encoded bit goes to the CRC calculator --------------------------------------------------------------------------------------------------- -- Bits counter -- --------------------------------------------------------------------------------------------------- -- Managment of the pointer that indicates which bit of a manchester encoded byte is to be -- delivered. According to the state of the FSM, a byte may be a FSS one, or a data byte or a -- CRC or a FES byte. Outgoing_Bits_Index: wf_decr_counter generic map(g_counter_lgth => 5) port map( uclk_i => uclk_i, counter_rst_i => nfip_rst_i, counter_top_i => s_bit_index_top, counter_load_i => s_bit_index_load, counter_decr_i => s_bit_index_decr_p, ----------------------------------------------- counter_o => s_bit_index, counter_is_zero_o => s_bit_index_is_zero); ----------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s_bit_index_top <= to_unsigned (15, s_bit_index'length) when s_sending_fss = '1' or s_sending_data = '1' else to_unsigned (s_crc_bytes_manch'length-1, s_bit_index'length) when s_sending_crc = '1' else to_unsigned (c_FES'length - 1, s_bit_index'length) when s_sending_fes = '1' else to_unsigned (c_FSS'length - 1, s_bit_index'length); s_bit_index_load <= (s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1)) when (s_sending_fss = '1' or s_sending_data = '1' or s_sending_crc = '1' or s_sending_fes = '1') else '1' when s_prepare_to_produce ='1' else '0'; s_bit_index_decr_p <= tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-1) when (s_sending_fss = '1' or s_sending_data = '1' or s_sending_crc = '1' or s_sending_fes = '1') else '0'; --------------------------------------------------------------------------------------------------- -- Bits delivery -- --------------------------------------------------------------------------------------------------- -- Synchronous process Bits_Delivery: handling of nanoFIP output signal FD_TXD by -- placing bits of data according to the state of wf_tx_serializer's state machine and to the -- counter s_bit_index. The delivery takes place upon a tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) -- pulse. Bits_Delivery: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_txd <= '0'; else if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) = '1' then if s_sending_fss = '1' then s_txd <= c_FSS (to_integer (s_bit_index)); -- FSS: 2 bytes long (no need to resize) elsif s_sending_data = '1' then s_txd <= s_data_byte_manch (to_integer (resize(s_bit_index, 4))); -- 1 data-byte at a time elsif s_sending_crc = '1' then s_txd <= s_crc_bytes_manch (to_integer (s_bit_index)); -- CRC: 2 bytes long elsif s_sending_fes = '1' then s_txd <= c_FES(to_integer (resize(s_bit_index,4))); -- FES: 1 byte else s_txd <= '0'; end if; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- TXENA generation -- --------------------------------------------------------------------------------------------------- -- Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the -- same moment as the first bit of the FSS starts being delivered and stays asserted until the -- end of the delivery of the last FES bit. FD_TXENA_Generator: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then tx_enable_o <= '0'; else if ((s_sending_fss = '1') or (s_sending_data = '1') or (s_sending_crc = '1') or (s_sending_fes = '1') or (s_stop_transmission = '1')) then -- tx sending bits if tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-3) = '1' then -- in order to synchronise the tx_enable_o <= '1'; -- activation of tx_enable with the -- the delivery of the 1st FSS bit end if; -- FD_TXD (FSS) :________|-----|___________|-------- -- tx_sched_p_buff(1):______|-|___|-|___|-|___|-|___|-|__ -- sending_FSS :___|------------------------------- -- FD_TXENA :________|-------------------------- else tx_enable_o <= '0'; end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Independent Timeout Counter -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instantiation of a wf_decr_counter relying only on the system clock as an additional -- way to go back to IDLE state, in case any other logic is being stuck. Session_Timeout_Counter: wf_decr_counter generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH) port map( uclk_i => uclk_i, counter_rst_i => nfip_rst_i, counter_top_i => (others => '1'), counter_load_i => s_prepare_to_produce, counter_decr_i => '1', -- on each uclk tick counter_o => open, --------------------------------------------------- counter_is_zero_o => s_session_timedout); --------------------------------------------------- --------------------------------------------------------------------------------------------------- -- Outputs -- --------------------------------------------------------------------------------------------------- tx_data_o <= s_txd; tx_osc_rst_p_o <= s_session_timedout; tx_completed_p_o <= s_stop_transmission and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-2); tx_byte_request_p_o <= s_sending_data and s_bit_index_is_zero and tx_sched_p_buff_i(c_TX_SCHED_BUFF_LGTH-4); -- request for a new byte from the wf_prod_bytes_retriever unit (passing from wf_engine_control) end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

314e98af7d6ad5b29661ea69d7e9ca8b

alvieboy/iotpanel

cpld/tb.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:05:08 03/28/2015 -- Design Name: -- Module Name: /home/alvieboy/otpanel/cpld/tb.vhd -- Project Name: cpld -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: top -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; library work; use work.all; ENTITY tb IS END tb; ARCHITECTURE behavior OF tb IS -- Component Declaration for the Unit Under Test (UUT) --Inputs signal clk : std_logic := '0'; signal cs : std_logic := '0'; signal di : std_logic := '0'; --signal idtr : std_logic := '0'; signal gpio13 : std_logic := '0'; signal gpio14 : std_logic := '0'; signal esptx : std_logic := '0'; --BiDirs signal gpio2 : std_logic; signal gpio0 : std_logic; signal gpio5 : std_logic; signal gpio4 : std_logic; signal gpio16 : std_logic; signal gpio12 : std_logic; signal usr : std_logic_vector(6 downto 3); --Outputs signal rgb : std_logic_vector(5 downto 0); signal col : std_logic_vector(3 downto 0); signal stb : std_logic; signal clko : std_logic; signal espreset : std_logic; signal espen : std_logic; signal esprx : std_logic; --signal espchpd : std_logic; signal oe : std_logic; signal panelen : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; -- constant clko_period : time := 10 ns; alias idtr:std_logic is usr(4); BEGIN usr(4) <= '1'; gpio16 <= '0'; -- Instantiate the Unit Under Test (UUT) uut: entity work.iotpanel PORT MAP ( clk => clk, cs => cs, --di => di, rgb => rgb, col => col, stb => stb, clko => clko, --idtr => idtr, gpio13 => gpio13, gpio14 => gpio14, espreset => espreset, espen => espen, esptx => esptx, esprx => esprx, gpio2 => gpio2, gpio0 => gpio0, gpio5 => gpio5, gpio4 => gpio4, --espchpd => espchpd, gpio16 => gpio16, gpio12 => di,--gpio12, oe => oe, panelen => panelen, usr => usr, iusr => 'X' ); -- Stimulus process stim_proc: process procedure transfer(data: in std_logic_vector; deassert: in boolean) is variable w,i: natural; variable d: std_logic_vector(data'high downto data'low); begin w := data'length; d := data; wait for clk_period/2; cs <= '0'; wait for clk_period/2; l1: for i in 0 to w-1 loop -- Setup data. di <= d(data'high); wait for clk_period/2; clk <= '1'; wait for clk_period/2; clk <= '0'; d := d(data'high-1 downto 0) & 'X'; end loop; wait for clk_period/2; if (deassert) then cs<='1'; end if; end procedure; begin -- hold reset state for 100 ns. cs <= '1'; wait for 100 ns; transfer("11" & "010"&"010"&'X', false); transfer("11" & "111"&"111"&'X', false); transfer("11" & "000"&"000"&'X', false); transfer("10" & "XXX"&"XXX"&'X', true); transfer("00" & "0001111", true); wait for 100 ns; wait; end process; END;

lgpl-3.0

def52c9beeba57b6de6a552f123e81de

malkadi/FGPU

RTL/regFile.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity regFile is port( rs_addr, rt_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 2. rd_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 2. re : in std_logic; -- level 2. rs : out std_logic_vector(DATA_W-1 downto 0):= (others=>'0'); -- level 7. rt : out std_logic_vector(DATA_W-1 downto 0):= (others=>'0'); -- level 6. rd : out std_logic_vector(DATA_W-1 downto 0):= (others=>'0'); -- level 8. we : in std_logic; -- level 18. wrAddr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 18. wrData : in std_logic_vector(DATA_W-1 downto 0); -- level 18. clk : in std_logic ); end entity; architecture Behavioral of regFile is -- signals definitions {{{ signal regFile_rdAddr : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); signal regFile_rdAddr_n : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); signal regFile_outData : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal regFile_outData_n : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal clk_stable_int : std_logic; signal regFile512: SLV32_ARRAY(0 to REG_FILE_BLOCK_SIZE-1) := (others => (others => '0')); type read_state_type is (prepare_rt_addr, read_rs, read_rt, read_rd); signal state, state_n : read_state_type := prepare_rt_addr; type read_state_vec_type is array (natural range<>) of read_state_type; signal state_vec : read_state_vec_type(5 downto 0) := (others=>prepare_rt_addr); signal rs_n, rt_n, rd_n : std_logic_vector(DATA_W-1 downto 0):= (others=>'0'); signal we_d0 : std_logic := '0'; signal wrAddr_clk2x : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); signal wrData_d0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal wrAddr_d0 : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); -- }}} begin process(state, re, rs_addr, rt_addr, rd_addr) begin state_n <= state; case state is when prepare_rt_addr => if re = '1' then -- level 2. state_n <= read_rt; end if; regFile_rdAddr_n <= rt_addr; when read_rt => -- level 3. regFile_rdAddr_n <= rs_addr; state_n <= read_rs; when read_rs => -- level 4. regFile_rdAddr_n <= rd_addr; state_n <= read_rd; when read_rd => -- level 5 regFile_rdAddr_n <= rd_addr; state_n <= prepare_rt_addr; end case; end process; process(clk) begin if rising_edge(clk) then state <= state_n; -- @ 3. reset not necesary since the FSM will go always to the first state and waits until re = '1' state_vec(state_vec'high-1 downto 0) <= state_vec(state_vec'high downto 1); -- @ 5.->8. state_vec(state_vec'high) <= state; -- @ 4. we_d0 <= we; -- @ 19. wrData_d0 <= wrData; -- @ 19. wrAddr_d0 <= wrAddr; -- @ 19. case state_vec(state_vec'high-1) is -- level 5. when prepare_rt_addr => when read_rt => rt <= regFile_outData; -- @ 6. when read_rs => rs <= regFile_outData; -- @ 7. when read_rd => rd <= regFile_outData; -- @ 8. end case; end if; end process; regFile_Instance: process (clk) begin if (clk'event and clk = '1') then regFile_rdAddr <= regFile_rdAddr_n; -- rt @ 3., rs @ 4., rd @ 5. if we_d0 = '1' then -- level 19. regFile512(to_integer(wrAddr_d0)) <= wrData_d0; -- @ 20. end if; regFile_outData_n <= regFile512(to_integer(regFile_rdAddr)); -- rt @ 4., rs @ 5., rd @ 6. regFile_outData <= regFile_outData_n; -- rt @ 5., rs @ 6., rd @ 7. end if; end process; end Behavioral;

gpl-3.0

a9abb0d367aa8a57baee23c71960a10f

preusser/q27

src/vhdl/PoC/common/utils.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Common functions and types -- -- Description: -- ------------------------------------- -- For detailed documentation see below. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; library PoC; use PoC.my_config.all; package utils is -- PoC settings -- ========================================================================== constant POC_VERBOSE : boolean := MY_VERBOSE; -- Environment -- ========================================================================== -- Distinguishes simulation from synthesis constant SIMULATION : boolean; -- deferred constant declaration -- Type declarations -- ========================================================================== --+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++ type T_BOOLVEC is array(natural range <>) of boolean; type T_INTVEC is array(natural range <>) of integer; type T_NATVEC is array(natural range <>) of natural; type T_POSVEC is array(natural range <>) of positive; type T_REALVEC is array(natural range <>) of REAL; --+ Integer subranges sometimes useful for speeding up simulation ++++++++++ subtype T_INT_8 is integer range -128 to 127; subtype T_INT_16 is integer range -32768 to 32767; subtype T_UINT_8 is integer range 0 to 255; subtype T_UINT_16 is integer range 0 to 65535; --+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Intellectual Property (IP) type type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT); -- Bit Order type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST); -- Byte Order (Endian) type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN); -- rounding style type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN); -- define a new unrelated type T_BCD for arithmetic -- QUESTION: extract to an own BCD package? -- => overloaded operators for +/-/=/... and conversion functions type T_BCD is array(3 downto 0) of std_logic; type T_BCD_VECTOR is array(natural range <>) of T_BCD; constant C_BCD_MINUS : T_BCD := "1010"; constant C_BCD_OFF : T_BCD := "1011"; subtype byte is std_logic_vector(7 downto 0); type byte_vector is array(natural range<>) of byte; -- Function declarations -- ========================================================================== --+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(a / b) function div_ceil(a : natural; b : positive) return natural; --+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- is input a power of 2? function is_pow2(int : natural) return boolean; -- round to next power of 2 function ceil_pow2(int : natural) return positive; -- round to previous power of 2 function floor_pow2(int : natural) return natural; --+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Calculates: ceil(ld(arg)) function log2ceil(arg : positive) return natural; -- Calculates: max(1, ceil(ld(arg))) function log2ceilnz(arg : positive) return positive; -- Calculates: ceil(lg(arg)) function log10ceil(arg : positive) return natural; -- Calculates: max(1, ceil(lg(arg))) function log10ceilnz(arg : positive) return positive; --+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++ function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean; function ite(cond : boolean; value1 : integer; value2 : integer) return integer; function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL; function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic; function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector; function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector; function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned; function ite(cond : boolean; value1 : character; value2 : character) return character; function ite(cond : boolean; value1 : string; value2 : string) return string; -- conditional increment / decrement function inc_if(cond : boolean; value : integer; increment : integer := 1) return integer; function dec_if(cond : boolean; value : integer; decrement : integer := 1) return integer; --+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers alias rmin is IEEE.math_real.realmin[real, real return real]; -- function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals function imin(vec : T_INTVEC) return integer; -- Calculates: min(vec) for a integer vector function imin(vec : T_NATVEC) return natural; -- Calculates: min(vec) for a natural vector function imin(vec : T_POSVEC) return positive; -- Calculates: min(vec) for a positive vector function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers alias rmax is IEEE.math_real.realmax[real, real return real]; -- function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals function imax(vec : T_INTVEC) return integer; -- Calculates: max(vec) for a integer vector function imax(vec : T_NATVEC) return natural; -- Calculates: max(vec) for a natural vector function imax(vec : T_POSVEC) return positive; -- Calculates: max(vec) for a positive vector function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector function isum(vec : T_NATVEC) return natural; -- Calculates: sum(vec) for a natural vector function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector --+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- to integer: to_int function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer; function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer; -- to std_logic: to_sl function to_sl(Value : boolean) return std_logic; function to_sl(Value : character) return std_logic; -- to std_logic_vector: to_slv function to_slv(Value : natural; Size : positive) return std_logic_vector; -- short for std_logic_vector(to_unsigned(Value, Size)) function to_BCD(Digit : integer) return T_BCD; function to_BCD(Digit : character) return T_BCD; function to_BCD(Digit : unsigned) return T_BCD; function to_BCD(Digit : std_logic_vector) return T_BCD; function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR; function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR; -- TODO: comment function to_index(slv : unsigned; max : natural := 0) return integer; function to_index(slv : std_logic_vector; max : natural := 0) return integer; -- is_* function is_sl(c : character) return boolean; --+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++ -- Aggregate functions function slv_or (vec : std_logic_vector) return std_logic; function slv_nor (vec : std_logic_vector) return std_logic; function slv_and (vec : std_logic_vector) return std_logic; function slv_nand(vec : std_logic_vector) return std_logic; function slv_xor (vec : std_logic_vector) return std_logic; -- NO slv_xnor! This operation would not be well-defined as -- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd. -- Reverses the elements of the passed Vector. -- -- @synthesis supported -- function reverse(vec : std_logic_vector) return std_logic_vector; function reverse(vec : bit_vector) return bit_vector; function reverse(vec : unsigned) return unsigned; -- scale a value into a range [Minimum, Maximum] function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL; -- Resizes the vector to the specified length. The adjustment is make on -- on the 'high end of the vector. The 'low index remains as in the argument. -- If the result vector is larger, the extension uses the provided fill value -- (default: '0'). -- Use the resize functions of the numeric_std package for value-preserving -- resizes of the signed and unsigned data types. -- -- @synthesis supported -- function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector; function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector; -- Shift the index range of a vector by the specified offset. function move(vec : std_logic_vector; ofs : integer) return std_logic_vector; -- Shift the index range of a vector making vec'low = 0. function movez(vec : std_logic_vector) return std_logic_vector; function ascend(vec : std_logic_vector) return std_logic_vector; function descend(vec : std_logic_vector) return std_logic_vector; -- Least-Significant Set Bit (lssb): -- Computes a vector of the same length as the argument with -- at most one bit set at the rightmost '1' found in arg. -- -- @synthesis supported -- function lssb(arg : std_logic_vector) return std_logic_vector; function lssb(arg : bit_vector) return bit_vector; -- Returns the index of the least-significant set bit. -- -- @synthesis supported -- function lssb_idx(arg : std_logic_vector) return integer; function lssb_idx(arg : bit_vector) return integer; -- Most-Significant Set Bit (mssb): computes a vector of the same length -- with at most one bit set at the leftmost '1' found in arg. function mssb(arg : std_logic_vector) return std_logic_vector; function mssb(arg : bit_vector) return bit_vector; function mssb_idx(arg : std_logic_vector) return integer; function mssb_idx(arg : bit_vector) return integer; -- Swap sub vectors in vector (endian reversal) function swap(slv : std_logic_vector; Size : positive) return std_logic_vector; -- generate bit masks function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector; function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector; function genmask_alternate(len : positive; lsb : std_logic := '0') return std_logic_vector; --+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- One-Hot-Code to Binary-Code. -- If a non-negative value empty_val is specified, its unsigned -- representation will be returned upon an all-zero input. As a consequence -- of specifying this value, no simulation warnings will be issued upon empty -- inputs. Alleged 1-hot-encoded inputs with more than one bit asserted -- will always raise a simulation warning. function onehot2bin(onehot : std_logic_vector; empty_val : integer := -1) return unsigned; -- Converts Gray-Code into Binary-Code. -- -- @synthesis supported -- function gray2bin (gray_val : std_logic_vector) return std_logic_vector; -- Binary-Code to One-Hot-Code function bin2onehot(value : std_logic_vector) return std_logic_vector; -- Binary-Code to Gray-Code function bin2gray(value : std_logic_vector) return std_logic_vector; end package; package body utils is -- Environment -- ========================================================================== function is_simulation return boolean is variable ret : boolean; begin ret := false; -- WORKAROUND: for Xilinx ISE -- Version: all versions with enabled 'use_new_parser' option -- Issue: Is_X('X') does not evaluate to FALSE in synthesis -- Solution: Use '--synthesis translate_on/off' pragmas --synthesis translate_off if Is_X('X') then ret := true; end if; --synthesis translate_on return ret; end function; -- deferred constant assignment constant SIMULATION : boolean := is_simulation; -- Divisions: div_* -- =========================================================================== -- integer division; always round-up function div_ceil(a : natural; b : positive) return natural is -- calculates: ceil(a / b) begin return (a + (b - 1)) / b; end function; -- Power functions: *_pow2 -- ========================================================================== -- return TRUE, if input is a power of 2 function is_pow2(int : natural) return boolean is begin return ceil_pow2(int) = int; end function; -- round to next power of 2 function ceil_pow2(int : natural) return positive is begin return 2 ** log2ceil(int); end function; -- round to previous power of 2 function floor_pow2(int : natural) return natural is variable temp : unsigned(30 downto 0); begin temp := to_unsigned(int, 31); for i in temp'range loop if (temp(i) = '1') then return 2 ** i; end if; end loop; return 0; end function; -- Logarithms: log*ceil* -- ========================================================================== -- return log2; always rounded up function log2ceil(arg : positive) return natural is variable tmp : positive; variable log : natural; begin if arg = 1 then return 0; end if; tmp := 1; log := 0; while arg > tmp loop tmp := tmp * 2; log := log + 1; end loop; return log; end function; -- return log2; always rounded up; the return value is >= 1 function log2ceilnz(arg : positive) return positive is begin return imax(1, log2ceil(arg)); end function; -- return log10; always rounded up function log10ceil(arg : positive) return natural is variable tmp : positive; variable log : natural; begin if arg = 1 then return 0; end if; tmp := 1; log := 0; while arg > tmp loop tmp := tmp * 10; log := log + 1; end loop; return log; end function; -- return log2; always rounded up; the return value is >= 1 function log10ceilnz(arg : positive) return positive is begin return imax(1, log10ceil(arg)); end function; -- if-then-else (ite) -- ========================================================================== function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : integer; value2 : integer) return integer is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : character; value2 : character) return character is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : string; value2 : string) return string is begin if cond then return value1; else return value2; end if; end function; -- conditional increment / decrement -- =========================================================================== -- return the by increment incremented Value if cond is true else passthrough Value function inc_if(cond : boolean; Value : integer; increment : integer := 1) return integer is begin if cond then return Value + increment; else return Value; end if; end function; -- return the by decrement decremented Value if cond is true else passthrough Value function dec_if(cond : boolean; Value : integer; decrement : integer := 1) return integer is begin if cond then return Value - decrement; else return Value; end if; end function; -- *min / *max / *sum -- =========================================================================== function imin(arg1 : integer; arg2 : integer) return integer is begin if arg1 < arg2 then return arg1; end if; return arg2; end function; -- function rmin(arg1 : real; arg2 : real) return real is -- begin -- if arg1 < arg2 then return arg1; end if; -- return arg2; -- end function; function imin(vec : T_INTVEC) return integer is variable Result : integer; begin Result := integer'high; for i in vec'range loop if (vec(i) < Result) then Result := vec(i); end if; end loop; return Result; end function; function imin(vec : T_NATVEC) return natural is variable Result : natural; begin Result := natural'high; for i in vec'range loop if (vec(i) < Result) then Result := vec(i); end if; end loop; return Result; end function; function imin(vec : T_POSVEC) return positive is variable Result : positive; begin Result := positive'high; for i in vec'range loop if (vec(i) < Result) then Result := vec(i); end if; end loop; return Result; end function; function rmin(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := REAL'high; for i in vec'range loop if vec(i) < Result then Result := vec(i); end if; end loop; return Result; end function; function imax(arg1 : integer; arg2 : integer) return integer is begin if arg1 > arg2 then return arg1; end if; return arg2; end function; -- function rmax(arg1 : real; arg2 : real) return real is -- begin -- if arg1 > arg2 then return arg1; end if; -- return arg2; -- end function; function imax(vec : T_INTVEC) return integer is variable Result : integer; begin Result := integer'low; for i in vec'range loop if (vec(i) > Result) then Result := vec(i); end if; end loop; return Result; end function; function imax(vec : T_NATVEC) return natural is variable Result : natural; begin Result := natural'low; for i in vec'range loop if (vec(i) > Result) then Result := vec(i); end if; end loop; return Result; end function; function imax(vec : T_POSVEC) return positive is variable Result : positive; begin Result := positive'low; for i in vec'range loop if (vec(i) > Result) then Result := vec(i); end if; end loop; return Result; end function; function rmax(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := REAL'low; for i in vec'range loop if vec(i) > Result then Result := vec(i); end if; end loop; return Result; end function; function isum(vec : T_INTVEC) return integer is variable Result : integer; begin Result := 0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; function isum(vec : T_NATVEC) return natural is variable Result : natural; begin Result := 0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; function isum(vec : T_POSVEC) return natural is variable Result : natural; begin Result := 0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; function rsum(vec : T_REALVEC) return REAL is variable Result : REAL; begin Result := 0.0; for i in vec'range loop Result := Result + vec(i); end loop; return Result; end function; -- Vector aggregate functions: slv_* -- ========================================================================== function slv_or(vec : std_logic_vector) return std_logic is variable Result : std_logic; begin Result := '0'; for i in vec'range loop Result := Result or vec(i); end loop; return Result; end function; function slv_nor(vec : std_logic_vector) return std_logic is begin return not slv_or(vec); end function; function slv_and(vec : std_logic_vector) return std_logic is variable Result : std_logic; begin Result := '1'; for i in vec'range loop Result := Result and vec(i); end loop; return Result; end function; function slv_nand(vec : std_logic_vector) return std_logic is begin return not slv_and(vec); end function; function slv_xor(vec : std_logic_vector) return std_logic is variable res : std_logic; begin res := '0'; for i in vec'range loop res := res xor vec(i); end loop; return res; end function; -- =========================================================================== -- Type conversion -- =========================================================================== -- Convert to integer: to_int function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer is begin return ite(bool, one, zero); end function; function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer is begin if (sl = '1') then return one; end if; return zero; end function; -- Convert to bit: to_sl -- =========================================================================== function to_sl(Value : boolean) return std_logic is begin return ite(Value, '1', '0'); end function; function to_sl(Value : character) return std_logic is begin case Value is when 'U' => return 'U'; when '0' => return '0'; when '1' => return '1'; when 'Z' => return 'Z'; when 'W' => return 'W'; when 'L' => return 'L'; when 'H' => return 'H'; when '-' => return '-'; when others => return 'X'; end case; end function; -- Convert to vector: to_slv -- =========================================================================== -- short for std_logic_vector(to_unsigned(Value, Size)) -- the return value is guaranteed to have the range (Size-1 downto 0) function to_slv(Value : natural; Size : positive) return std_logic_vector is constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size)); begin return res; end function; -- Convert to T_BCD or T_BCD_VECTOR: to_BCD* -- =========================================================================== function to_BCD(Digit : integer) return T_BCD is begin return T_BCD(to_unsigned(Digit, T_BCD'length)); end function; function to_BCD(Digit : character) return T_BCD is begin return T_BCD(to_unsigned((character'pos(Digit) - CHARACTER'pos('0')), T_BCD'length)); end function; function to_BCD(Digit : unsigned) return T_BCD is begin return T_BCD(Digit); end function; function to_BCD(Digit : std_logic_vector) return T_BCD is begin return T_BCD(Digit); end function; function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is begin return to_BCD_Vector(integer'image(Value), Size, Fill); end function; function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is variable Result : T_BCD_VECTOR(Size - 1 downto 0); begin Result := (others => Fill); for i in Value'range loop Result(Value'length - (i - Value'low) - 1) := to_BCD(Value(i)); end loop; return Result; end function; -- bound array indices for simulation, to prevent out of range errors function to_index(slv : unsigned; max : natural := 0) return integer is variable res : integer; begin if (slv'length = 0) then return 0; end if; res := to_integer(slv); if SIMULATION and max > 0 then res := imin(res, max); end if; return res; end function; -- bound array indices for simulation, to prevent out of range errors function to_index(slv : std_logic_vector; max : natural := 0) return integer is begin return to_index(unsigned(slv), max); end function; -- is_* -- =========================================================================== function is_sl(c : character) return boolean is begin case c is when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true; when others => return false; end case; end function; -- Reverse vector elements function reverse(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'range); begin for i in vec'low to vec'high loop res(vec'low + (vec'high-i)) := vec(i); end loop; return res; end function; function reverse(vec : bit_vector) return bit_vector is variable res : bit_vector(vec'range); begin res := to_bitvector(reverse(to_stdlogicvector(vec))); return res; end function; function reverse(vec : unsigned) return unsigned is begin return unsigned(reverse(std_logic_vector(vec))); end function; -- Swap sub vectors in vector -- ========================================================================== function swap(slv : std_logic_vector; Size : positive) return std_logic_vector is constant SegmentCount : natural := slv'length / Size; variable FromH : natural; variable FromL : natural; variable ToH : natural; variable ToL : natural; variable Result : std_logic_vector(slv'length - 1 downto 0); begin for i in 0 to SegmentCount - 1 loop FromH := ((i + 1) * Size) - 1; FromL := i * Size; ToH := ((SegmentCount - i) * Size) - 1; ToL := (SegmentCount - i - 1) * Size; Result(ToH downto ToL) := slv(FromH downto FromL); end loop; return Result; end function; -- generate bit masks -- ========================================================================== function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector is begin if (Bits = 0) then return (MaskLength - 1 downto 0 => '0'); else return (MaskLength - 1 downto MaskLength - Bits + 1 => '1') & (MaskLength - Bits downto 0 => '0'); end if; end function; function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector is begin if (Bits = 0) then return (MaskLength - 1 downto 0 => '0'); else return (MaskLength - 1 downto Bits => '0') & (Bits - 1 downto 0 => '1'); end if; end function; function genmask_alternate(len : positive; lsb : std_logic := '0') return std_logic_vector is variable curr : std_logic; variable res : std_logic_vector(len-1 downto 0); begin curr := lsb; for i in res'reverse_range loop res(i) := curr; curr := not curr; end loop; return res; end function; -- binary encoding conversion functions -- ========================================================================== -- One-Hot-Code to Binary-Code function onehot2bin(onehot : std_logic_vector; empty_val : integer := -1) return unsigned is variable res : unsigned(log2ceilnz(imax(onehot'high, empty_val)+1)-1 downto 0); variable chk : natural; begin -- Note: empty_val = 0 takes the regular path to reduce on synthesized hardware if empty_val > 0 and onehot = (onehot'range => '0') then res := to_unsigned(empty_val, res'length); else res := (others => '0'); chk := 0; for i in onehot'range loop if onehot(i) = '1' then res := res or to_unsigned(i, res'length); chk := chk + 1; end if; end loop; if SIMULATION and chk /= 1 and (chk > 1 or empty_val < 0) then report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set." severity warning; res := (others => 'X'); -- computed result is implementation-dependant end if; end if; return res; end function; -- Gray-Code to Binary-Code function gray2bin(gray_val : std_logic_vector) return std_logic_vector is variable tmp : std_logic_vector(gray_val'length downto 0); variable res : std_logic_vector(gray_val'range); begin tmp := '0' & gray_val; for i in tmp'left-1 downto 0 loop tmp(i) := tmp(i+1) xor tmp(i); end loop; res := tmp(tmp'left-1 downto 0); return res; end function; -- Binary-Code to One-Hot-Code function bin2onehot(Value : std_logic_vector) return std_logic_vector is variable result : std_logic_vector(2**Value'length - 1 downto 0); begin result := (others => '0'); result(to_index(Value, 0)) := '1'; return result; end function; -- Binary-Code to Gray-Code function bin2gray(Value : std_logic_vector) return std_logic_vector is variable tmp : std_logic_vector(Value'length downto 0); variable res : std_logic_vector(Value'range); begin tmp := ('0' & Value) xor (Value & '0'); res := tmp(Value'length downto 1); return res; end function; -- bit searching / bit indices -- ========================================================================== -- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg. function lssb(arg : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(arg'range); begin res := arg and std_logic_vector(unsigned(not arg)+1); return res; end function; function lssb(arg : bit_vector) return bit_vector is variable res : bit_vector(arg'range); begin res := to_bitvector(lssb(to_stdlogicvector(arg))); return res; end function; -- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg. function mssb(arg : std_logic_vector) return std_logic_vector is begin return reverse(lssb(reverse(arg))); end function; function mssb(arg : bit_vector) return bit_vector is begin return reverse(lssb(reverse(arg))); end function; -- Index of lssb function lssb_idx(arg : std_logic_vector) return integer is begin return to_integer(onehot2bin(lssb(arg))); end function; function lssb_idx(arg : bit_vector) return integer is variable slv : std_logic_vector(arg'range); begin slv := to_stdlogicvector(arg); return lssb_idx(slv); end function; -- Index of mssb function mssb_idx(arg : std_logic_vector) return integer is begin return to_integer(onehot2bin(mssb(arg))); end function; function mssb_idx(arg : bit_vector) return integer is variable slv : std_logic_vector(arg'range); begin slv := to_stdlogicvector(arg); return mssb_idx(slv); end function; -- scale a value into a given range function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin return scale(real(Value), Minimum, Maximum, RoundingStyle); end function; function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is variable Result : REAL; begin if (Maximum < Minimum) then return integer'low; else Result := real(Value) * ((real(Maximum) + 0.5) - (real(Minimum) - 0.5)) + (real(Minimum) - 0.5); case RoundingStyle is when ROUND_TO_NEAREST => return integer(round(Result)); when ROUND_TO_ZERO => report "scale: unsupported RoundingStyle." severity FAILURE; when ROUND_TO_INF => report "scale: unsupported RoundingStyle." severity FAILURE; when ROUND_UP => return integer(ceil(Result)); when ROUND_DOWN => return integer(floor(Result)); when others => report "scale: unsupported RoundingStyle." severity FAILURE; end case; end if; end function; function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL is begin if (Maximum < Minimum) then return REAL'low; else return Value * (Maximum - Minimum) + Minimum; end if; end function; function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is constant high2b : natural := vec'low+length-1; constant highcp : natural := imin(vec'high, high2b); variable res_up : bit_vector(vec'low to high2b); variable res_dn : bit_vector(high2b downto vec'low); begin if vec'ascending then res_up := (others => fill); res_up(vec'low to highcp) := vec(vec'low to highcp); return res_up; else res_dn := (others => fill); res_dn(highcp downto vec'low) := vec(highcp downto vec'low); return res_dn; end if; end function; function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is constant high2b : natural := vec'low+length-1; constant highcp : natural := imin(vec'high, high2b); variable res_up : std_logic_vector(vec'low to high2b); variable res_dn : std_logic_vector(high2b downto vec'low); begin if vec'ascending then res_up := (others => fill); res_up(vec'low to highcp) := vec(vec'low to highcp); return res_up; else res_dn := (others => fill); res_dn(highcp downto vec'low) := vec(highcp downto vec'low); return res_dn; end if; end function; -- Move vector boundaries -- ========================================================================== function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs); variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs); begin if vec'ascending then res_up := vec; return res_up; else res_dn := vec; return res_dn; end if; end function; function movez(vec : std_logic_vector) return std_logic_vector is begin return move(vec, -vec'low); end function; function ascend(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'low to vec'high); begin res := vec; return res; end function; function descend(vec : std_logic_vector) return std_logic_vector is variable res : std_logic_vector(vec'high downto vec'low); begin res := vec; return res; end function; end package body;

agpl-3.0

d6343845153176d97c82783bbc1968ad

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_rx_osc.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_rx_osc | -- | --------------------------------------------------------------------------------------------------- -- File wf_rx_osc.vhd | -- | -- Description Generation of the clock signals needed for the FIELDRIVE reception | -- | -- Even if the bit rate of the communication is known, jitter is expected to affect | -- the arriving time of the incoming signal. The main idea of the unit is to | -- recalculate the expected arrival time of the next incoming bit, based on the | -- arrival of the previous one, so that drifts are not accumulated. The clock | -- recovery is based on the Manchester 2 coding which ensures that there is one edge | -- (transition) for each bit. | -- | -- In this unit, we refer to | -- o a significant edge: for the edge of a manch. encoded bit (bit 0:_|-, bit 1: -|_)| -- o a transition : for the moment in between two adjacent bits, that may or | -- may not result in an edge (eg. a 0 followed by a 0 will give an edge _|-|_|-, | -- but a 0 followed by a 1 will not _|--|_ ). | -- | -- Authors Pablo Alvarez Sanchez ([email protected]) | -- Evangelia Gousiou ([email protected]) | -- Date 14/02/2011 | -- Version v0.04 | -- Depends on wf_reset_unit | -- wf_deglitcher | -- wf_rx_deserializer | ------------------ | -- Last changes | -- 08/2009 v0.01 PS Entity Ports added, start of architecture content | -- 07/2010 v0.02 EG rx counter changed from 20 bits signed, to 11 bits unsigned; | -- rx clk generation depends on edge detection;code cleanedup+commented | -- rst_rx_osc signal clearified | -- 12/2010 v0.03 EG code cleaned-up | -- 01/2011 v0.031 EG rxd_edge_i became fd_rxd_edge_p_i; small correctiond on comments | -- 02/2011 v0.04 EG 2 units wf_rx_osc and wf_tx_osc; process replaced by wf_incr_counter | -- check for code violations removed completely | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_rx_osc --================================================================================================= entity wf_rx_osc is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signal from the wf_deglitcher unit fd_rxd_edge_p_i : in std_logic; -- indication of an edge on fd_rxd -- Signal from wf_rx_deserializer unit rx_osc_rst_i : in std_logic; -- resets the clock recovery procedure -- OUTPUTS -- Signals to the wf_rx_deserializer rx_manch_clk_p_o : out std_logic; -- signal with uclk-wide pulses -- o on a significant edge -- o between adjacent bits -- ____|-|___|-|___|-|___ rx_bit_clk_p_o : out std_logic; -- signal with uclk-wide pulses -- o between adjacent bits -- __________|-|_________ rx_signif_edge_window_o : out std_logic; -- time window where a significant edge is expected rx_adjac_bits_window_o : out std_logic); -- time window where a transition between adjacent -- bits is expected end entity wf_rx_osc; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_rx_osc is -- reception period counter signal s_period_c, s_period, s_margin : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0); signal s_half_period : unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0); signal s_period_c_reinit, s_period_c_is_full : std_logic; -- windows formed, based on the counter signal s_adjac_bits_window, s_signif_edge_window : std_logic; -- fd_rxd signal combined with the windows signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic; -- clocks signal s_bit_clk, s_bit_clk_d1, s_manch_clk, s_manch_clk_d1 : std_logic; --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Generation of windows where edges/ transitions are expected -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- # uclk ticks for a bit period, defined by the WorldFIP bit rate s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i))); s_half_period <= s_period srl 1; -- 1/2 s_period s_margin <= s_period srl 3; -- margin for jitter defined as 1/8 of the period -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instantiation of a wf_incr_counter unit : the rx_counter starts counting after the -- release of the reset signal rx_osc_rst_i. This takes place after a falling edge on the -- filtered FD_RXD; this edge should be representing the 1st Manchester 2 (manch.) encoded bit '1' -- of the PREamble. Starting from this edge, other falling or rising significant edges, are -- expected around one period (s_period) later. A time window around the expected arrival time is -- set and its length is defined as 1/4th of the period (1/8th before and 1/8th after the expected -- time). When the actual edge arrives, the counter is reset. -- If that first falling edge of FD_RXD is finally proven not to belong to a valid PRE the counter -- is reinitialialized through the rx_osc_rst_i signal from the wf_rx_deserializer. rx_periods_count: wf_incr_counter generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH) port map( uclk_i => uclk_i, counter_reinit_i => s_period_c_reinit, counter_incr_i => '1', counter_is_full_o => open, ------------------------------------------ counter_o => s_period_c); ------------------------------------------ s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- counter reinitialized: if nfip_rst_i is active or -- if rx_osc_rst_i is active or -- if an edge is detected in the expected window or -- if it fills up s_period_c_reinit <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i) or s_period_c_is_full; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Concurrent signal assignments: creation of the windows where -- "significant edges" and "adjacent bits transitions" are expected on the input signal. -- o s_signif_edge_window: extends s_margin uclk ticks before and s_margin uclk ticks after -- the completion of a period, where significant edges are expected. -- o s_adjac_bits_window : extends s_margin uclk ticks before and s_margin uclk ticks after -- the middle of a period, where transitions between adjacent bits are expected. s_signif_edge_window <= '1' when ((s_period_c < s_margin) or (s_period_c > s_period-1 - s_margin-1)) else '0'; s_adjac_bits_window <= '1' when ((s_period_c >= s_half_period-s_margin-1) and (s_period_c < s_half_period+s_margin)) else '0'; --------------------------------------------------------------------------------------------------- -- Clocks Generation -- --------------------------------------------------------------------------------------------------- -- Synchronous process rx_clks: the process rx_clk is following the edges that appear on the fd_rxd -- and constructs two clock signals: rx_manch_clk & rx_bit_clk. -- The signal rx_manch_clk: is inverted on each significant edge, as well as between adjacent bits -- The signal rx_bit_clk : is inverted only between adjacent bits -- The significant edges are normally expected inside the signif_edge_window. In the cases of a -- code violation (V+ or V-) no edge will arrive in this window. In this situation rx_manch_clk -- is inverted right after the end of the signif_edge_window. -- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive -- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window. rx_clks: process (uclk_i) begin if rising_edge (uclk_i) then if (nfip_rst_i = '1') then s_manch_clk <= '0'; s_bit_clk <= '0'; s_bit_clk_d1 <= '0'; s_manch_clk_d1 <= '0'; s_signif_edge_found <= '0'; s_adjac_bits_edge_found <= '0'; else -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- regarding significant edges: -- looking for a significant edge inside the corresponding window if (s_signif_edge_window='1') and (fd_rxd_edge_p_i='1') and (s_signif_edge_found='0') then s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk s_signif_edge_found <= '1'; -- indication that the edge was found s_adjac_bits_edge_found <= '0'; -- if a significant edge is not found where expected (code violation), the rx_manch_clk -- is inverted right after the end of the signif_edge_window. elsif (s_signif_edge_found = '0') and (s_period_c = s_margin) then s_manch_clk <= not s_manch_clk; s_adjac_bits_edge_found <= '0'; -- re-initialization before the -- next cycle -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- regarding edges between adjacent bits: -- looking for an edge inside the corresponding window elsif (s_adjac_bits_window = '1') and (fd_rxd_edge_p_i = '1') then s_manch_clk <= not s_manch_clk; -- inversion of rx_manch_clk s_bit_clk <= not s_bit_clk; -- inversion of rx_bit_clk s_adjac_bits_edge_found <= '1'; -- indication that an edge was found s_signif_edge_found <= '0'; -- re-initialization before next cycle -- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right -- after the end of it elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_margin) then s_manch_clk <= not s_manch_clk; s_bit_clk <= not s_bit_clk; s_signif_edge_found <= '0'; -- re-initialization before next cycle end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s_manch_clk_d1 <= s_manch_clk; -- s_manch_clk : ____|-----|_____|-----|____ -- s_manch_clk_d1 : ______|-----|_____|-----|__ -- rx_manch_clk_p_o : ____|-|___|-|___|-|___|-|__ s_bit_clk_d1 <= s_bit_clk; -- s_bit_clk : ____|-----------|__________ -- s_bit_clk_d1 : ______|-----------|________ -- rx_bit_clk_p_o : ____|-|_________|-|________ end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Concurrent signal assignments -- --------------------------------------------------------------------------------------------------- rx_manch_clk_p_o <= s_manch_clk_d1 xor s_manch_clk; -- a 1 uclk-wide pulse, after -- o a significant edge and -- o a new bit -- ___|-|___|-|___|-|___ rx_bit_clk_p_o <= s_bit_clk xor s_bit_clk_d1; -- a 1 uclk-wide pulse, after -- o a new bit -- _________|-|_________ rx_signif_edge_window_o <= s_signif_edge_window; rx_adjac_bits_window_o <= s_adjac_bits_window; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

da53ba137eb1edc68950129e732e1514

wltr/cern-fgclite

critical_fpga/src/rtl/cf/field_bus_timing.vhd

------------------------------------------------------------------------------- --! @file field_bus_timing.vhd --! @author Johannes Walter <[email protected]> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-09 --! @brief Field-bus timing synchronization. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.cf_pkg.all; --! @brief Entity declaration of field_bus_timing --! @details --! Synchronize internal timing to COMMAND 0 of field-bus transmission. entity field_bus_timing is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Timing signals --! @{ --! Cycle synchronization marker cmd_0_i : in std_ulogic; --! Millisecond strobe ms_strobe_o : out std_ulogic; --! Millisecond period (nominally 40000 * 25 ns clock cycles) ms_period_i : in std_ulogic_vector(15 downto 0); --! Millisecond number (0-19) ms_number_o : out std_ulogic_vector(0 to 19); --! Field-bus cycle period in 25 ns clock cycles (nominally 800000) cycle_period_o : out std_ulogic_vector(19 downto 0)); --! @} end entity field_bus_timing; --! RTL implementation of field_bus_timing architecture rtl of field_bus_timing is --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal ms_period : std_ulogic_vector(15 downto 0); signal ms_number : unsigned(15 downto 0); signal ms_strobe_dlyd : std_ulogic; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal ms_strobe : std_ulogic; signal cmd_0 : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- ms_number_o(00) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 00) else '0'; ms_number_o(01) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 01) else '0'; ms_number_o(02) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 02) else '0'; ms_number_o(03) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 03) else '0'; ms_number_o(04) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 04) else '0'; ms_number_o(05) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 05) else '0'; ms_number_o(06) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 06) else '0'; ms_number_o(07) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 07) else '0'; ms_number_o(08) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 08) else '0'; ms_number_o(09) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 09) else '0'; ms_number_o(10) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 10) else '0'; ms_number_o(11) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 11) else '0'; ms_number_o(12) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 12) else '0'; ms_number_o(13) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 13) else '0'; ms_number_o(14) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 14) else '0'; ms_number_o(15) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 15) else '0'; ms_number_o(16) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 16) else '0'; ms_number_o(17) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 17) else '0'; ms_number_o(18) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 18) else '0'; ms_number_o(19) <= '1' when (ms_strobe_dlyd = '1' and to_integer(ms_number) = 19) else '0'; ms_strobe_o <= ms_strobe_dlyd; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! Detect rising edges on COMMAND 0 input signal edge_detector_inst : entity work.edge_detector port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => '1', ack_i => '0', sig_i => cmd_0_i, edge_o => cmd_0); --! Millisecond strobe generator strobe_gen_inst : entity work.strobe_generator generic map ( init_value_g => 0, bit_width_g => 16) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => '1', period_i => ms_period, pre_i => cmd_0, pre_value_i => cmd_0_pre_value_c, strobe_o => ms_strobe); --! Field-bus cycle period counter stop_watch_inst : entity work.stop_watch generic map ( bit_width_g => 20) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => '1', sample_i => cmd_0, value_o => cycle_period_o); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin ms_period <= ms_period_c; ms_number <= to_unsigned(0, ms_number'length); ms_strobe_dlyd <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else ms_strobe_dlyd <= ms_strobe; if cmd_0 = '1' then ms_number <= to_unsigned(0, ms_number'length); elsif ms_strobe = '1' then if to_integer(ms_number) < 19 then ms_number <= ms_number + 1; else ms_number <= to_unsigned(0, ms_number'length); end if; end if; if ms_strobe = '1' and to_integer(ms_number) = 2 then ms_period <= ms_period_i; end if; end if; end if; end process regs; end architecture rtl;

mit

2e57f1b959100bcbf7baccd0fa7b1490

touilleMan/scrips

instmemory.vhd

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:21:35 05/08/2012 -- Design Name: -- Module Name: instmemory - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity instmemory is Port ( Address : in STD_LOGIC_VECTOR (31 downto 0); Instruction : out STD_LOGIC_VECTOR (31 downto 0)); end instmemory; architecture Behavioral of instmemory is begin process (Address) begin case Address is -- Main program when "00000000000000000000000000000000"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000000000100"=>Instruction<="00000000000000000011100000100101"; when "00000000000000000000000000001000"=>Instruction<="00000000000000000011000000100101"; when "00000000000000000000000000001100"=>Instruction<="00000000000000000010100000100101"; when "00000000000000000000000000010000"=>Instruction<="00000000000000000010000000100101"; when "00000000000000000000000000010100"=>Instruction<="00000000000000000001100000100101"; when "00000000000000000000000000011000"=>Instruction<="00000000000000000001000000100101"; when "00000000000000000000000000011100"=>Instruction<="00000000000000000000100000100101"; when "00000000000000000000000000100000"=>Instruction<="10101100000000000000000000010000"; when "00000000000000000000000000100100"=>Instruction<="10101100000000000000000000110001"; when "00000000000000000000000000101000"=>Instruction<="10101100000000000000000000110010"; when "00000000000000000000000000101100"=>Instruction<="10101100000000000000000000110011"; when "00000000000000000000000000110000"=>Instruction<="00110100000001000000000000000011"; when "00000000000000000000000000110100"=>Instruction<="00001000000000000000000000101111"; when "00000000000000000000000000111000"=>Instruction<="00110100000000010000000000011001"; when "00000000000000000000000000111100"=>Instruction<="00010000000000010000000000001001"; when "00000000000000000000000001000000"=>Instruction<="00100000001000011111111111111111"; when "00000000000000000000000001000100"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001001000"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001001100"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001010000"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001010100"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001011000"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001011100"=>Instruction<="00000000000000000000000000100101"; when "00000000000000000000000001100000"=>Instruction<="00001000000000000000000000001111"; when "00000000000000000000000001100100"=>Instruction<="00010000000000110000000000000100"; when "00000000000000000000000001101000"=>Instruction<="00100000011000111111111111111111"; when "00000000000000000000000001101100"=>Instruction<="00110100000000010000000000000001"; when "00000000000000000000000001110000"=>Instruction<="10101100000000010000000000110001"; when "00000000000000000000000001110100"=>Instruction<="00001000000000000000000000001110"; when "00000000000000000000000001111000"=>Instruction<="10101100000000000000000000110001"; when "00000000000000000000000001111100"=>Instruction<="00010000100000001111111111111111"; when "00000000000000000000000010000000"=>Instruction<="10001100000000010000000000110100"; when "00000000000000000000000010000100"=>Instruction<="00110000001000010000000000111111"; when "00000000000000000000000010001000"=>Instruction<="00010000001000000000000000011000"; when "00000000000000000000000010001100"=>Instruction<="00100000100001001111111111111111"; when "00000000000000000000000010010000"=>Instruction<="00110100000000010000000000000011"; when "00000000000000000000000010010100"=>Instruction<="00010000001001000000000000001001"; when "00000000000000000000000010011000"=>Instruction<="00110100000000010000000000000010"; when "00000000000000000000000010011100"=>Instruction<="00010000001001000000000000001010"; when "00000000000000000000000010100000"=>Instruction<="00110100000000010000000000000001"; when "00000000000000000000000010100100"=>Instruction<="00010000001001000000000000001011"; when "00000000000000000000000010101000"=>Instruction<="00001000000000000000000000111000"; when "00000000000000000000000010101100"=>Instruction<="00110100000000010000000000000001"; when "00000000000000000000000010110000"=>Instruction<="10101100000000010000000000110001"; when "00000000000000000000000010110100"=>Instruction<="00110100000000110110000110101000"; when "00000000000000000000000010111000"=>Instruction<="00001000000000000000000000001110"; when "00000000000000000000000010111100"=>Instruction<="00110100000000010000000001001111"; when "00000000000000000000000011000000"=>Instruction<="10101100000000010000000000110010"; when "00000000000000000000000011000100"=>Instruction<="00001000000000000000000000101011"; when "00000000000000000000000011001000"=>Instruction<="00110100000000010000000001011011"; when "00000000000000000000000011001100"=>Instruction<="10101100000000010000000000110010"; when "00000000000000000000000011010000"=>Instruction<="00001000000000000000000000101011"; when "00000000000000000000000011010100"=>Instruction<="00110100000000010000000000000110"; when "00000000000000000000000011011000"=>Instruction<="10101100000000010000000000110010"; when "00000000000000000000000011011100"=>Instruction<="00001000000000000000000000101011"; when "00000000000000000000000011100000"=>Instruction<="00110100000000010000000000111111"; when "00000000000000000000000011100100"=>Instruction<="10101100000000010000000000110010"; when "00000000000000000000000011101000"=>Instruction<="00001000000000000000000000101011"; when "00000000000000000000000011101100"=>Instruction<="10001100000001010000000000110000"; when "00000000000000000000000011110000"=>Instruction<="00110000101000010000000000000001"; when "00000000000000000000000011110100"=>Instruction<="00010000001000000000000000000011"; when "00000000000000000000000011111000"=>Instruction<="00110100000000010000000000000111"; when "00000000000000000000000011111100"=>Instruction<="10101100000000010000000000110011"; when "00000000000000000000000100000000"=>Instruction<="00001000000000000000000001000010"; when "00000000000000000000000100000100"=>Instruction<="10101100000000000000000000110011"; when "00000000000000000000000100001000"=>Instruction<="00010000110000000000000000000010"; when "00000000000000000000000100001100"=>Instruction<="00100000110001101111111111111111"; when "00000000000000000000000100010000"=>Instruction<="00001000000000000000000000001110"; when "00000000000000000000000100010100"=>Instruction<="00110000101000010000000000000010"; when "00000000000000000000000100011000"=>Instruction<="00010000001000000000000000000001"; when "00000000000000000000000100011100"=>Instruction<="00001000000000000000000001100000"; when "00000000000000000000000100100000"=>Instruction<="00110000101000010000000000000100"; when "00000000000000000000000100100100"=>Instruction<="00010000001000000000000000000001"; when "00000000000000000000000100101000"=>Instruction<="00001000000000000000000001001110"; when "00000000000000000000000100101100"=>Instruction<="00110100000001100000000010100111"; when "00000000000000000000000100110000"=>Instruction<="10101100000001110000000000010000"; when "00000000000000000000000100110100"=>Instruction<="00001000000000000000000000001110"; when "00000000000000000000000100111000"=>Instruction<="00110000111000010000000000001111"; when "00000000000000000000000100111100"=>Instruction<="00110100000000100000000000000001"; when "00000000000000000000000101000000"=>Instruction<="00010000001000100000000000000110"; when "00000000000000000000000101000100"=>Instruction<="00110100000000100000000000000010"; when "00000000000000000000000101001000"=>Instruction<="00010000001000100000000000000110"; when "00000000000000000000000101001100"=>Instruction<="00110100000000100000000000000100"; when "00000000000000000000000101010000"=>Instruction<="00010000001000100000000000000110"; when "00000000000000000000000101010100"=>Instruction<="00110100000000010000000000000001"; when "00000000000000000000000101011000"=>Instruction<="00010000000000000000000000000110"; when "00000000000000000000000101011100"=>Instruction<="00110100000000010000000000000010"; when "00000000000000000000000101100000"=>Instruction<="00010000000000000000000000000100"; when "00000000000000000000000101100100"=>Instruction<="00110100000000010000000000000100"; when "00000000000000000000000101101000"=>Instruction<="00010000000000000000000000000010"; when "00000000000000000000000101101100"=>Instruction<="00110100000000010000000000001000"; when "00000000000000000000000101110000"=>Instruction<="00010000000000000000000000000000"; when "00000000000000000000000101110100"=>Instruction<="00110000111001111111111111110000"; when "00000000000000000000000101111000"=>Instruction<="00000000111000010011100000100101"; when "00000000000000000000000101111100"=>Instruction<="00010000000000001111111111101011"; when "00000000000000000000000110000000"=>Instruction<="00110000111000010000000011110000"; when "00000000000000000000000110000100"=>Instruction<="00110100000000100000000000010000"; when "00000000000000000000000110001000"=>Instruction<="00010000001000100000000000001100"; when "00000000000000000000000110001100"=>Instruction<="00110100000000100000000000100000"; when "00000000000000000000000110010000"=>Instruction<="00010000001000100000000000000100"; when "00000000000000000000000110010100"=>Instruction<="00110100000000100000000001000000"; when "00000000000000000000000110011000"=>Instruction<="00010000001000100000000000000100"; when "00000000000000000000000110011100"=>Instruction<="00110100000000100000000010000000"; when "00000000000000000000000110100000"=>Instruction<="00010000001000100000000000000100"; when "00000000000000000000000110100100"=>Instruction<="00110100000000010000000000010000"; when "00000000000000000000000110101000"=>Instruction<="00010000000000000000000000000110"; when "00000000000000000000000110101100"=>Instruction<="00110100000000010000000000100000"; when "00000000000000000000000110110000"=>Instruction<="00010000000000000000000000000100"; when "00000000000000000000000110110100"=>Instruction<="00110100000000010000000001000000"; when "00000000000000000000000110111000"=>Instruction<="00010000000000000000000000000010"; when "00000000000000000000000110111100"=>Instruction<="00110100000000010000000010000000"; when "00000000000000000000000111000000"=>Instruction<="00010000000000000000000000000000"; when "00000000000000000000000111000100"=>Instruction<="00110000111001111111111100001111"; when "00000000000000000000000111001000"=>Instruction<="00000000111000010011100000100101"; when "00000000000000000000000111001100"=>Instruction<="00010000000000001111111111010100"; when others => Instruction <= "00000000000000000000000000000000"; End case; end process; end Behavioral;

mit

5548f7e21e4b841379d1d51520335d4f

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_mux.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block O+CNhRO2jpNpLYirT91PosAB0GPlv1fr/fRbZpGSAEpjuuZ2iwl3NN/1tsB2X5Ealflo+PrKhmBU Oor0p+/BTQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block aiZwqO5NkeR+mb9Httn86aLRz4MWEyJzTbe0FkOj6GK19Bz/s5xpJv4wBKYU7utf5uZuqMMFrb6E eLJAKrGr3w3WJeUG6sP0GBICaQjhBwcV7z+710jDBzD0CPhX+eXctHa8nj6rw2MzNdZEes3iUcjl XuHsaZ8Xz5ziVqOOZQE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

de326321f5036fb3e527118e09beb935

joalcava/sparcv8-monocicle

psr.vhd

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:25:06 10/20/2016 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity psr is Port( clk : in std_logic; reset : in std_logic; nzvc : in std_logic_vector(3 downto 0); ncwp : in std_logic; carry : out std_logic; cwp : out std_logic ); end psr; architecture psrArq of psr is signal PSRDATA : std_logic_vector (3 downto 0) := "0000"; begin process(clk,nzvc,ncwp,reset) begin if (reset='1') then PSRDATA<= "0000"; carry<= '0'; cwp <= '0'; else if (rising_edge(clk))then PSRDATA<= nzvc; carry<=PSRDATA(0); cwp <= ncwp; end if; end if; end process; end psrArq;

gpl-3.0

6573b5ff5afe0f63e3412da78475ecb4

joalcava/sparcv8-monocicle

MuxPC.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MuxPC is Port ( PCdisp30 : in STD_LOGIC_VECTOR(31 downto 0); PCdisp22 : in STD_LOGIC_VECTOR(31 downto 0); PC : in STD_LOGIC_VECTOR(31 downto 0); PCplus1 : in STD_LOGIC_VECTOR(31 downto 0); PCSource: in STD_LOGIC_VECTOR(1 downto 0); nPC : out STD_LOGIC_VECTOR(31 downto 0) ); end MuxPC; architecture Behavioral of MuxPC is begin process(PCdisp30,PCdisp22,PC,PCSource) begin if (PCSource="10") then nPC <= PCdisp22; elsif (PCsource="01") then nPC <= PCdisp30; elsif (PCSource="00") then nPC <= PC; else nPC <= PCplus1; end if; end process; end Behavioral;

gpl-3.0

614b946e8fe80bfaa8c517532e433bc4

preusser/q27

src/vhdl/PoC/common/physical.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Martin Zabel -- Thomas B. Preusser -- -- Package: This VHDL package declares new physical types and their -- conversion functions. -- -- Description: -- ------------------------------------- -- For detailed documentation see below. -- -- NAMING CONVENTION: -- t - time -- p - period -- d - delay -- f - frequency -- br - baud rate -- vec - vector -- -- ATTENTION: -- This package is not supported by Xilinx Synthese Tools prior to 14.7! -- -- It was successfully tested with: -- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7 -- - Quartus II 13.1 -- - QuestaSim 10.0d -- - GHDL 0.31 -- -- Tool chains with known issues: -- - Xilinx Vivado Synthesis 2014.4 -- -- Untested tool chains -- - Xilinx Vivado Simulator (xSim) 2014.4 -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.math_real.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.strings.all; package physical is type FREQ is range 0 to integer'high units Hz; kHz = 1000 Hz; MHz = 1000 kHz; GHz = 1000 MHz; end units; type BAUD is range 0 to integer'high units Bd; kBd = 1000 Bd; MBd = 1000 kBd; GBd = 1000 MBd; end units; type MEMORY is range 0 to integer'high units Byte; KiB = 1024 Byte; MiB = 1024 KiB; GiB = 1024 MiB; end units; -- vector data types type T_TIMEVEC is array(natural range <>) of time; type T_FREQVEC is array(natural range <>) of FREQ; type T_BAUDVEC is array(natural range <>) of BAUD; type T_MEMVEC is array(natural range <>) of MEMORY; -- if true: TimingToCycles reports difference between expected and actual result constant C_PHYSICAL_REPORT_TIMING_DEVIATION : boolean := TRUE; -- conversion functions function to_time(f : FREQ) return time; function to_freq(p : time) return FREQ; function to_freq(br : BAUD) return FREQ; function to_baud(str : string) return BAUD; -- inter-type arithmetic function "/"(x : real; t : time) return FREQ; function "/"(x : real; f : FREQ) return time; function "*"(t : time; f : FREQ) return real; function "*"(f : FREQ; t : time) return real; -- if-then-else function ite(cond : boolean; value1 : time; value2 : time) return time; function ite(cond : boolean; value1 : FREQ; value2 : FREQ) return FREQ; function ite(cond : boolean; value1 : BAUD; value2 : BAUD) return BAUD; function ite(cond : boolean; value1 : MEMORY; value2 : MEMORY) return MEMORY; -- min/ max for 2 arguments function tmin(arg1 : time; arg2 : time) return time; -- Calculates: min(arg1, arg2) for times function fmin(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies function bmin(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second function mmin(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory function tmax(arg1 : time; arg2 : time) return time; -- Calculates: max(arg1, arg2) for times function fmax(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies function bmax(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second function mmax(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory -- min/max/sum as vector aggregation function tmin(vec : T_TIMEVEC) return time; -- Calculates: min(vec) for a time vector function fmin(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector function bmin(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector function mmin(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector function tmax(vec : T_TIMEVEC) return time; -- Calculates: max(vec) for a time vector function fmax(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector function bmax(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector function mmax(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector function tsum(vec : T_TIMEVEC) return time; -- Calculates: sum(vec) for a time vector function fsum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector function bsum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector function msum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector -- convert standard types (NATURAL, REAL) to time (TIME) function fs2Time(t_fs : integer) return time; function ps2Time(t_ps : integer) return time; function ns2Time(t_ns : integer) return time; function us2Time(t_us : integer) return time; function ms2Time(t_ms : integer) return time; function sec2Time(t_sec : integer) return time; function fs2Time(t_fs : REAL) return time; function ps2Time(t_ps : REAL) return time; function ns2Time(t_ns : REAL) return time; function us2Time(t_us : REAL) return time; function ms2Time(t_ms : REAL) return time; function sec2Time(t_sec : REAL) return time; -- convert standard types (NATURAL, REAL) to period (TIME) function Hz2Time(f_Hz : natural) return time; function kHz2Time(f_kHz : natural) return time; function MHz2Time(f_MHz : natural) return time; function GHz2Time(f_GHz : natural) return time; function Hz2Time(f_Hz : REAL) return time; function kHz2Time(f_kHz : REAL) return time; function MHz2Time(f_MHz : REAL) return time; function GHz2Time(f_GHz : REAL) return time; -- convert standard types (NATURAL, REAL) to frequency (FREQ) function Hz2Freq(f_Hz : natural) return FREQ; function kHz2Freq(f_kHz : natural) return FREQ; function MHz2Freq(f_MHz : natural) return FREQ; function GHz2Freq(f_GHz : natural) return FREQ; function Hz2Freq(f_Hz : REAL) return FREQ; function kHz2Freq(f_kHz : REAL) return FREQ; function MHz2Freq(f_MHz : REAL) return FREQ; function GHz2Freq(f_GHz : REAL) return FREQ; -- convert physical types to standard type (REAL) function to_real(t : time; scale : time) return REAL; function to_real(f : FREQ; scale : FREQ) return REAL; function to_real(br : BAUD; scale : BAUD) return REAL; function to_real(mem : MEMORY; scale : MEMORY) return REAL; -- convert physical types to standard type (INTEGER) function to_int(t : time; scale : time; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer; function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return integer; -- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period function TimingToCycles(Timing : time; Clock_Period : time; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural; function TimingToCycles(Timing : time; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural; function CyclesToDelay(Cycles : natural; Clock_Period : time) return time; function CyclesToDelay(Cycles : natural; Clock_Frequency : FREQ) return time; -- convert and format physical types to STRING function to_string(t : time; precision : natural) return string; function to_string(f : FREQ; precision : natural) return string; function to_string(br : BAUD; precision : natural) return string; function to_string(mem : MEMORY; precision : natural) return string; end package; package body physical is -- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps) function MinimalTimeResolutionInSimulation return time is begin if (1 fs > 0 sec) then return 1 fs; elsif (1 ps > 0 sec) then return 1 ps; elsif (1 ns > 0 sec) then return 1 ns; elsif (1 us > 0 sec) then return 1 us; elsif (1 ms > 0 sec) then return 1 ms; else return 1 sec; end if; end function; -- real division for physical types -- =========================================================================== function div(a : time; b : time) return REAL is constant MTRIS : time := MinimalTimeResolutionInSimulation; variable a_real : real; variable b_real : real; begin -- Quartus-II work-around if a < 1 us then a_real := real(a / MTRIS); elsif a < 1 ms then a_real := real(a / (1000 * MTRIS)) * 1000.0; elsif a < 1 sec then a_real := real(a / (1000000 * MTRIS)) * 1000000.0; else a_real := real(a / (1000000000 * MTRIS)) * 1000000000.0; end if; if b < 1 us then b_real := real(b / MTRIS); elsif b < 1 ms then b_real := real(b / (1000 * MTRIS)) * 1000.0; elsif b < 1 sec then b_real := real(b / (1000000 * MTRIS)) * 1000000.0; else b_real := real(b / (1000000000 * MTRIS)) * 1000000000.0; end if; return a_real / b_real; end function; function div(a : FREQ; b : FREQ) return REAL is begin return real(a / 1 Hz) / real(b / 1 Hz); end function; function div(a : BAUD; b : BAUD) return REAL is begin return real(a / 1 Bd) / real(b / 1 Bd); end function; function div(a : MEMORY; b : MEMORY) return REAL is begin return real(a / 1 Byte) / real(b / 1 Byte); end function; -- conversion functions -- =========================================================================== function to_time(f : FREQ) return time is variable res : time; begin res := div(1000 MHz, f) * 1 ns; if (POC_VERBOSE = TRUE) then report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note; end if; return res; end function; function to_freq(p : time) return FREQ is variable res : FREQ; begin if (p <= 1 sec) then res := div(1 sec, p) * 1 Hz; else report "to_freq: input period exceeds output frequency scale." severity failure; end if; if (POC_VERBOSE = TRUE) then report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note; end if; return res; end function; function to_freq(br : BAUD) return FREQ is variable res : FREQ; begin res := (br / 1 Bd) * 1 Hz; if (POC_VERBOSE = TRUE) then report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note; end if; return res; end function; function to_baud(str : string) return BAUD is variable pos : integer; variable int : natural; variable base : positive; variable frac : natural; variable digits : natural; begin pos := str'low; int := 0; frac := 0; digits := 0; -- read integer part for i in pos to str'high loop if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i)); elsif (str(i) = '.') then pos := -i; exit; elsif (str(i) = ' ') then pos := i; exit; else pos := 0; exit; end if; end loop; -- read fractional part if ((pos < 0) and (-pos < str'high)) then for i in -pos+1 to str'high loop if ((frac = 0) and (str(i) = '0')) then next; elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i)); elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit; else pos := 0; exit; end if; end loop; end if; -- abort if format is unknown if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if; -- parse unit pos := pos + 1; if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then return int * 1 Bd; elsif (pos + 2 = str'high) then if (str(pos to pos + 2) = "kBd") then if (frac = 0) then return (int * 1 kBd); elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd); else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd); end if; elsif (str(pos to pos + 2) = "MBd") then if (frac = 0) then return (int * 1 kBd); elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd); elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd); else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd); end if; elsif (str(pos to pos + 2) = "GBd") then if (frac = 0) then return (int * 1 kBd); elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd); elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd); elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd); else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd); end if; else report "to_baud: Unknown unit." severity FAILURE; end if; else report "to_baud: Unknown format" severity FAILURE; end if; end function; -- inter-type arithmetic -- =========================================================================== function "/"(x : real; t : time) return FREQ is begin return x*div(1 ms, t) * 1 kHz; end function; function "/"(x : real; f : FREQ) return time is begin return x*div(1 kHz, f) * 1 ms; end function; function "*"(t : time; f : FREQ) return real is begin return div(t, 1.0/f); end function; function "*"(f : FREQ; t : time) return real is begin return div(f, 1.0/t); end function; -- if-then-else -- =========================================================================== function ite(cond : boolean; value1 : time; value2 : time) return time is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : FREQ; value2 : FREQ) return FREQ is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : BAUD; value2 : BAUD) return BAUD is begin if cond then return value1; else return value2; end if; end function; function ite(cond : boolean; value1 : MEMORY; value2 : MEMORY) return MEMORY is begin if cond then return value1; else return value2; end if; end function; -- min/ max for 2 arguments -- =========================================================================== -- Calculates: min(arg1, arg2) for times function tmin(arg1 : time; arg2 : time) return time is begin if (arg1 < arg2) then return arg1; end if; return arg2; end function; -- Calculates: min(arg1, arg2) for frequencies function fmin(arg1 : FREQ; arg2 : FREQ) return FREQ is begin if (arg1 < arg2) then return arg1; end if; return arg2; end function; -- Calculates: min(arg1, arg2) for symbols per second function bmin(arg1 : BAUD; arg2 : BAUD) return BAUD is begin if (arg1 < arg2) then return arg1; end if; return arg2; end function; -- Calculates: min(arg1, arg2) for memory function mmin(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is begin if (arg1 < arg2) then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for times function tmax(arg1 : time; arg2 : time) return time is begin if (arg1 > arg2) then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for frequencies function fmax(arg1 : FREQ; arg2 : FREQ) return FREQ is begin if (arg1 > arg2) then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for symbols per second function bmax(arg1 : BAUD; arg2 : BAUD) return BAUD is begin if (arg1 > arg2) then return arg1; end if; return arg2; end function; -- Calculates: max(arg1, arg2) for memory function mmax(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is begin if (arg1 > arg2) then return arg1; end if; return arg2; end function; -- min/max/sum as vector aggregation -- =========================================================================== -- Calculates: min(vec) for a time vector function tmin(vec : T_TIMEVEC) return time is variable res : time := time'high; begin for i in vec'range loop if (vec(i) < res) then res := vec(i); end if; end loop; return res; end; -- Calculates: min(vec) for a frequency vector function fmin(vec : T_FREQVEC) return FREQ is variable res : FREQ := FREQ'high; begin for i in vec'range loop if (integer(FREQ'pos(vec(i))) < integer(FREQ'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: min(vec) for a baud vector function bmin(vec : T_BAUDVEC) return BAUD is variable res : BAUD := BAUD'high; begin for i in vec'range loop if (integer(BAUD'pos(vec(i))) < integer(BAUD'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: min(vec) for a memory vector function mmin(vec : T_MEMVEC) return MEMORY is variable res : MEMORY := MEMORY'high; begin for i in vec'range loop if (integer(MEMORY'pos(vec(i))) < integer(MEMORY'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: max(vec) for a time vector function tmax(vec : T_TIMEVEC) return time is variable res : time := time'low; begin for i in vec'range loop if (vec(i) > res) then res := vec(i); end if; end loop; return res; end; -- Calculates: max(vec) for a frequency vector function fmax(vec : T_FREQVEC) return FREQ is variable res : FREQ := FREQ'low; begin for i in vec'range loop if (integer(FREQ'pos(vec(i))) > integer(FREQ'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: max(vec) for a baud vector function bmax(vec : T_BAUDVEC) return BAUD is variable res : BAUD := BAUD'low; begin for i in vec'range loop if (integer(BAUD'pos(vec(i))) > integer(BAUD'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: max(vec) for a memory vector function mmax(vec : T_MEMVEC) return MEMORY is variable res : MEMORY := MEMORY'low; begin for i in vec'range loop if (integer(MEMORY'pos(vec(i))) > integer(MEMORY'pos(res))) then -- Quartus workaround res := vec(i); end if; end loop; return res; end; -- Calculates: sum(vec) for a time vector function tsum(vec : T_TIMEVEC) return time is variable res : time := 0 fs; begin for i in vec'range loop res := res + vec(i); end loop; return res; end; -- Calculates: sum(vec) for a frequency vector function fsum(vec : T_FREQVEC) return FREQ is variable res : FREQ := 0 Hz; begin for i in vec'range loop res := res + vec(i); end loop; return res; end; -- Calculates: sum(vec) for a baud vector function bsum(vec : T_BAUDVEC) return BAUD is variable res : BAUD := 0 Bd; begin for i in vec'range loop res := res + vec(i); end loop; return res; end; -- Calculates: sum(vec) for a memory vector function msum(vec : T_MEMVEC) return MEMORY is variable res : MEMORY := 0 Byte; begin for i in vec'range loop res := res + vec(i); end loop; return res; end; -- convert standard types (NATURAL, REAL) to time (TIME) -- =========================================================================== function fs2Time(t_fs : integer) return time is begin return t_fs * 1 fs; end function; function ps2Time(t_ps : integer) return time is begin return t_ps * 1 ps; end function; function ns2Time(t_ns : integer) return time is begin return t_ns * 1 ns; end function; function us2Time(t_us : integer) return time is begin return t_us * 1 us; end function; function ms2Time(t_ms : integer) return time is begin return t_ms * 1 ms; end function; function sec2Time(t_sec : integer) return time is begin return t_sec * 1 sec; end function; function fs2Time(t_fs : REAL) return time is begin return t_fs * 1 fs; end function; function ps2Time(t_ps : REAL) return time is begin return t_ps * 1 ps; end function; function ns2Time(t_ns : REAL) return time is begin return t_ns * 1 ns; end function; function us2Time(t_us : REAL) return time is begin return t_us * 1 us; end function; function ms2Time(t_ms : REAL) return time is begin return t_ms * 1 ms; end function; function sec2Time(t_sec : REAL) return time is begin return t_sec * 1 sec; end function; -- convert standard types (NATURAL, REAL) to period (TIME) -- =========================================================================== function Hz2Time(f_Hz : natural) return time is begin return 1 sec / f_Hz; end function; function kHz2Time(f_kHz : natural) return time is begin return 1 ms / f_kHz; end function; function MHz2Time(f_MHz : natural) return time is begin return 1 us / f_MHz; end function; function GHz2Time(f_GHz : natural) return time is begin return 1 ns / f_GHz; end function; function Hz2Time(f_Hz : REAL) return time is begin return 1 sec / f_Hz; end function; function kHz2Time(f_kHz : REAL) return time is begin return 1 ms / f_kHz; end function; function MHz2Time(f_MHz : REAL) return time is begin return 1 us / f_MHz; end function; function GHz2Time(f_GHz : REAL) return time is begin return 1 ns / f_GHz; end function; -- convert standard types (NATURAL, REAL) to frequency (FREQ) -- =========================================================================== function Hz2Freq(f_Hz : natural) return FREQ is begin return f_Hz * 1 Hz; end function; function kHz2Freq(f_kHz : natural) return FREQ is begin return f_kHz * 1 kHz; end function; function MHz2Freq(f_MHz : natural) return FREQ is begin return f_MHz * 1 MHz; end function; function GHz2Freq(f_GHz : natural) return FREQ is begin return f_GHz * 1 GHz; end function; function Hz2Freq(f_Hz : REAL) return FREQ is begin return f_Hz * 1 Hz; end function; function kHz2Freq(f_kHz : REAL )return FREQ is begin return f_kHz * 1 kHz; end function; function MHz2Freq(f_MHz : REAL )return FREQ is begin return f_MHz * 1 MHz; end function; function GHz2Freq(f_GHz : REAL )return FREQ is begin return f_GHz * 1 GHz; end function; -- convert physical types to standard type (REAL) -- =========================================================================== function to_real(t : time; scale : time) return REAL is begin if (scale = 1 fs) then return div(t, 1 fs); elsif (scale = 1 ps) then return div(t, 1 ps); elsif (scale = 1 ns) then return div(t, 1 ns); elsif (scale = 1 us) then return div(t, 1 us); elsif (scale = 1 ms) then return div(t, 1 ms); elsif (scale = 1 sec) then return div(t, 1 sec); else report "to_real: scale must have a value of '1 <unit>'" severity failure; end if; end; function to_real(f : FREQ; scale : FREQ) return REAL is begin if (scale = 1 Hz) then return div(f, 1 Hz); elsif (scale = 1 kHz) then return div(f, 1 kHz); elsif (scale = 1 MHz) then return div(f, 1 MHz); elsif (scale = 1 GHz) then return div(f, 1 GHz); -- elsif (scale = 1 THz) then return div(f, 1 THz); else report "to_real: scale must have a value of '1 <unit>'" severity failure; end if; end; function to_real(br : BAUD; scale : BAUD) return REAL is begin if (scale = 1 Bd) then return div(br, 1 Bd); elsif (scale = 1 kBd) then return div(br, 1 kBd); elsif (scale = 1 MBd) then return div(br, 1 MBd); elsif (scale = 1 GBd) then return div(br, 1 GBd); else report "to_real: scale must have a value of '1 <unit>'" severity failure; end if; end; function to_real(mem : MEMORY; scale : MEMORY) return REAL is begin if (scale = 1 Byte) then return div(mem, 1 Byte); elsif (scale = 1 KiB) then return div(mem, 1 KiB); elsif (scale = 1 MiB) then return div(mem, 1 MiB); elsif (scale = 1 GiB) then return div(mem, 1 GiB); else report "to_real: scale must have a value of '1 <unit>'" severity failure; end if; end; -- convert physical types to standard type (INTEGER) -- =========================================================================== function to_int(t : time; scale : time; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(t, scale))); when ROUND_DOWN => return integer(floor(to_real(t, scale))); when ROUND_TO_NEAREST => return integer(round(to_real(t, scale))); when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(f, scale))); when ROUND_DOWN => return integer(floor(to_real(f, scale))); when ROUND_TO_NEAREST => return integer(round(to_real(f, scale))); when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(br, scale))); when ROUND_DOWN => return integer(floor(to_real(br, scale))); when ROUND_TO_NEAREST => return integer(round(to_real(br, scale))); when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return integer is begin case RoundingStyle is when ROUND_UP => return integer(ceil(to_real(mem, scale))); when ROUND_DOWN => return integer(floor(to_real(mem, scale))); when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale))); when others => null; end case; report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure; end; -- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period -- =========================================================================== -- @param Timing A given timing or delay, which should be archived -- @param Clock_Period The period of the circuits clock -- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN function TimingToCycles(Timing : time; Clock_Period : time; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural is variable res_real : REAL; variable res_nat : natural; variable res_time : time; variable res_dev : REAL; begin res_real := div(Timing, Clock_Period); case RoundingStyle is when ROUND_TO_NEAREST => res_nat := natural(round(res_real)); when ROUND_UP => res_nat := natural(ceil(res_real)); when ROUND_DOWN => res_nat := natural(floor(res_real)); when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure; end case; res_time := CyclesToDelay(res_nat, Clock_Period); res_dev := (div(res_time, Timing) - 1.0) * 100.0; if (POC_VERBOSE = TRUE) then report "TimingToCycles: " & CR & " Timing: " & to_string(Timing, 3) & CR & " Clock_Period: " & to_string(Clock_Period, 3) & CR & " RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR & " res_real = " & str_format(res_real, 3) & CR & " => " & integer'image(res_nat) severity note; end if; if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then report "TimingToCycles (timing deviation report): " & CR & " timing to achieve: " & to_string(Timing, 3) & CR & " calculated cycles: " & integer'image(res_nat) & " cy" & CR & " resulting timing: " & to_string(res_time, 3) & CR & " deviation: " & to_string(res_time - Timing, 3) & " (" & str_format(res_dev, 2) & "%)" severity note; end if; return res_nat; end; function TimingToCycles(Timing : time; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return natural is begin return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle); end function; function CyclesToDelay(Cycles : natural; Clock_Period : time) return time is begin return Clock_Period * Cycles; end function; function CyclesToDelay(Cycles : natural; Clock_Frequency : FREQ) return time is begin return CyclesToDelay(Cycles, to_time(Clock_Frequency)); end function; -- convert and format physical types to STRING function to_string(t : time; precision : natural) return string is variable tt : time; variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin tt := abs t; if (tt < 1 ps) then unit(1 to 2) := "fs"; value := to_real(tt, 1 fs); elsif (tt < 1 ns) then unit(1 to 2) := "ps"; value := to_real(tt, 1 ps); elsif (tt < 1 us) then unit(1 to 2) := "ns"; value := to_real(tt, 1 ns); elsif (tt < 1 ms) then unit(1 to 2) := "us"; value := to_real(tt, 1 us); elsif (tt < 1 sec) then unit(1 to 2) := "ms"; value := to_real(tt, 1 ms); else unit := "sec"; value := to_real(tt, 1 sec); end if; return ite(t >= 0 fs, str_format(value, precision) & " " & str_trim(unit), '-' & str_format(value, precision) & " " & str_trim(unit)); end function; function to_string(f : FREQ; precision : natural) return string is variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin if (f < 1 kHz) then unit(1 to 2) := "Hz"; value := to_real(f, 1 Hz); elsif (f < 1 MHz) then unit := "kHz"; value := to_real(f, 1 kHz); elsif (f < 1 GHz) then unit := "MHz"; value := to_real(f, 1 MHz); else unit := "GHz"; value := to_real(f, 1 GHz); end if; return str_format(value, precision) & " " & str_trim(unit); end function; function to_string(br : BAUD; precision : natural) return string is variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin if (br < 1 kBd) then unit(1 to 2) := "Bd"; value := to_real(br, 1 Bd); elsif (br < 1 MBd) then unit := "kBd"; value := to_real(br, 1 kBd); elsif (br < 1 GBd) then unit := "MBd"; value := to_real(br, 1 MBd); else unit := "GBd"; value := to_real(br, 1 GBd); end if; return str_format(value, precision) & " " & str_trim(unit); end function; function to_string(mem : MEMORY; precision : natural) return string is variable unit : string(1 to 3) := (others => C_POC_NUL); variable value : REAL; begin if (mem < 1 KiB) then unit(1) := 'B'; value := to_real(mem, 1 Byte); elsif (mem < 1 MiB) then unit := "KiB"; value := to_real(mem, 1 KiB); elsif (mem < 1 GiB) then unit := "MiB"; value := to_real(mem, 1 MiB); else unit := "GiB"; value := to_real(mem, 1 GiB); end if; return str_format(value, precision) & " " & str_trim(unit); end function; end package body;

agpl-3.0

eaa7433ac8ceef262a021cf9db4b2324

preusser/q27

src/vhdl/PoC/fifo/fifo_ic_got.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- =========================================================================== -- Module: FIFO, independent clocks (ic), first-word-fall-through mode -- -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- -- Description: -- ------------------------------------ -- Independent clocks meens that read and write clock are unrelated. -- -- This implementation uses dedicated block RAM for storing data. -- -- First-word-fall-through (FWFT) mode is implemented, so data can be read out -- as soon as 'valid' goes high. After the data has been captured, then the -- signal 'got' must be asserted. -- -- Synchronous reset is used. Both resets may overlap. -- -- DATA_REG (=true) is a hint, that distributed memory or registers should be -- used as data storage. The actual memory type depends on the device -- architecture. See implementation for details. -- -- *STATE_*_BITS defines the granularity of the fill state indicator -- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs -- the guaranteed number of words available in the FIFO. 'estate_wr' is -- associated with the write clock domain and outputs the number of words that -- is guaranteed to be accepted by the FIFO without a capacity overflow. Note -- that both these indicators cannot replace the 'full' or 'valid' outputs as -- they may be implemented as giving pessimistic bounds that are minimally off -- the true fill state. -- -- If a fill state is not of interest, set *STATE_*_BITS = 0. -- -- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- -- Examples: -- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full -- fstate_rd == 1 => 1/2 full (half full) -- -- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full -- fstate_rd == 1 => 1/4 full -- fstate_rd == 2 => 2/4 full -- fstate_rd == 3 => 3/4 full -- -- License: -- =========================================================================== -- Copyright 2007-2014 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================================================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library poc; USE PoC.utils.ALL; use poc.ocram.all; -- "all" required by Quartus RTL simulation entity fifo_ic_got is generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Write Interface clk_wr : in std_logic; rst_wr : in std_logic; put : in std_logic; din : in std_logic_vector(D_BITS-1 downto 0); full : out std_logic; estate_wr : out std_logic_vector(imax(ESTATE_WR_BITS-1, 0) downto 0); -- Read Interface clk_rd : in std_logic; rst_rd : in std_logic; got : in std_logic; valid : out std_logic; dout : out std_logic_vector(D_BITS-1 downto 0); fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS-1, 0) downto 0) ); end fifo_ic_got; architecture rtl of fifo_ic_got is -- Constants constant A_BITS : positive := log2ceilnz(MIN_DEPTH); constant AN : positive := A_BITS + 1; -- Registers, clk_wr domain signal IP1 : std_logic_vector(AN-1 downto 0); -- IP + 1 signal IP0 : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Write Pointer IP signal IPz : std_logic_vector(AN-1 downto 0) := (others => '0'); -- IP delayed by one clock signal OPs : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Sync stage: OP0 -> OPc signal OPc : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Copy of OP signal Ful : std_logic := '0'; -- RAM full -- Registers, clk_rd domain signal OP1 : std_logic_vector(AN-1 downto 0); -- OP + 1 signal OP0 : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Read Pointer OP signal IPs : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Sync stage: IPz -> IPc signal IPc : std_logic_vector(AN-1 downto 0) := (others => '0'); -- Copy of IP signal Avl : std_logic := '0'; -- RAM Data available signal Vld : std_logic := '0'; -- Output Valid -- Memory Connectivity signal wa : unsigned(A_BITS-1 downto 0); signal di : std_logic_vector(D_BITS-1 downto 0); signal puti : std_logic; signal ra : unsigned(A_BITS-1 downto 0); signal do : std_logic_vector(D_BITS-1 downto 0); signal geti : std_logic; signal goti : std_logic; -- Internal Read ACK begin ----------------------------------------------------------------------------- -- Write clock domain ----------------------------------------------------------------------------- blkIP: block signal Cnt : unsigned(AN-1 downto 0) := to_unsigned(1, AN); begin process(clk_wr) begin if rising_edge(clk_wr) then if rst_wr = '1' then Cnt <= to_unsigned(1, AN); elsif puti = '1' then Cnt <= Cnt + 1; end if; end if; end process; IP1 <= std_logic_vector(Cnt(A_BITS) & (Cnt(A_BITS-1 downto 0) xor ('0' & Cnt(A_BITS-1 downto 1)))); end block blkIP; -- Update Write Pointer upon puti process(clk_wr) begin if rising_edge(clk_wr) then if rst_wr = '1' then IP0 <= (others => '0'); IPz <= (others => '0'); OPs <= (others => '0'); OPc <= (others => '0'); Ful <= '0'; else IPz <= IP0; OPs <= OP0; OPc <= OPs; if puti = '1' then IP0 <= IP1; if IP1(A_BITS-1 downto 0) = OPc(A_BITS-1 downto 0) then Ful <= '1'; else Ful <= '0'; end if; end if; if Ful = '1' then if IP0 = (not OPc(A_BITS) & OPc(A_BITS-1 downto 0)) then Ful <= '1'; else Ful <= '0'; end if; end if; end if; end if; end process; puti <= put and not Ful; full <= Ful; di <= din; wa <= unsigned(IP0(A_BITS-1 downto 0)); ----------------------------------------------------------------------------- -- Read clock domain ----------------------------------------------------------------------------- blkOP: block signal Cnt : unsigned(AN-1 downto 0) := to_unsigned(1, AN); begin process(clk_rd) begin if rising_edge(clk_rd) then if rst_rd = '1' then Cnt <= to_unsigned(1, AN); elsif geti = '1' then Cnt <= Cnt + 1; end if; end if; end process; OP1 <= std_logic_vector(Cnt(A_BITS) & (Cnt(A_BITS-1 downto 0) xor ('0' & Cnt(A_BITS-1 downto 1)))); end block blkOP; process(clk_rd) begin if rising_edge(clk_rd) then if rst_rd = '1' then OP0 <= (others => '0'); IPs <= (others => '0'); IPc <= (others => '0'); Avl <= '0'; Vld <= '0'; else IPs <= IPz; IPc <= IPs; if geti = '1' then OP0 <= OP1; if OP1(A_BITS-1 downto 0) = IPc(A_BITS-1 downto 0) then Avl <= '0'; else Avl <= '1'; end if; Vld <= '1'; elsif goti = '1' then Vld <= '0'; end if; if Avl = '0' then if OP0 = IPc then Avl <= '0'; else Avl <= '1'; end if; end if; end if; end if; end process; geti <= (not Vld or goti) and Avl; ra <= unsigned(OP0(A_BITS-1 downto 0)); ----------------------------------------------------------------------------- -- Add register to data output -- -- Not needed if DATA_REG = true, because "dout" is already feed from a -- register in that case. ----------------------------------------------------------------------------- genRegN: if DATA_REG or not OUTPUT_REG generate goti <= got; dout <= do; valid <= Vld; end generate genRegN; genRegY: if (not DATA_REG) and OUTPUT_REG generate signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); signal VldB : std_logic := '0'; begin process(clk_rd) begin if rising_edge(clk_rd) then if rst_rd = '1' then Buf <= (others => '-'); VldB <= '0'; elsif goti = '1' then Buf <= do; VldB <= Vld; end if; end if; end process; goti <= not VldB or got; dout <= Buf; valid <= VldB; end generate genRegY; ----------------------------------------------------------------------------- -- Fill State ----------------------------------------------------------------------------- -- Write Clock Domain gEstateWr: if ESTATE_WR_BITS >= 1 generate signal d : unsigned(A_BITS-1 downto 0); begin d <= unsigned(gray2bin(OPc(A_BITS-1 downto 0))) + not unsigned(gray2bin(IP0(A_BITS-1 downto 0))); estate_wr <= (others => '0') when Ful = '1' else std_logic_vector(d(d'left downto d'left-ESTATE_WR_BITS+1)); end generate gEstateWr; gNoEstateWr: if ESTATE_WR_BITS = 0 generate estate_wr <= "X"; end generate gNoEstateWr; -- Read Clock Domain gFstateRd: if FSTATE_RD_BITS >= 1 generate signal d : unsigned(A_BITS-1 downto 0); begin d <= unsigned(gray2bin(IPc(A_BITS-1 downto 0))) + not unsigned(gray2bin(OP0(A_BITS-1 downto 0))); fstate_rd <= (others => '0') when Avl = '0' else std_logic_vector(d(d'left downto d'left-FSTATE_RD_BITS+1)); end generate gFstateRd; gNoFstateRd: if FSTATE_RD_BITS = 0 generate fstate_rd <= "X"; end generate gNoFstateRd; ----------------------------------------------------------------------------- -- Memory Instantiation ----------------------------------------------------------------------------- gLarge: if not DATA_REG generate ram : ocram_sdp generic map ( A_BITS => A_BITS, D_BITS => D_BITS ) port map ( wclk => clk_wr, rclk => clk_rd, wce => '1', rce => geti, we => puti, ra => ra, wa => wa, d => di, q => do ); end generate gLarge; gSmall: if DATA_REG generate -- Memory modelled as Array type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0); signal regfile : regfile_t; attribute ram_style : string; -- XST specific attribute ram_style of regfile : signal is "distributed"; -- Altera Quartus II: Allow automatic RAM type selection. -- For small RAMs, registers are used on Cyclone devices and the M512 type -- is used on Stratix devices. Pass-through logic is not required as -- reads do not occur on write addresses. -- Warning about undefined read-during-write behaviour can be ignored. attribute ramstyle : string; attribute ramstyle of regfile : signal is "no_rw_check"; begin -- Memory State process(clk_wr) begin if rising_edge(clk_wr) then --synthesis translate_off if SIMULATION AND (rst_wr = '1') then regfile <= (others => (others => '-')); else --synthesis translate_on if puti = '1' then regfile(to_integer(wa)) <= di; end if; --synthesis translate_off end if; --synthesis translate_on end if; end process; -- Memory Output process (clk_rd) begin -- process if rising_edge(clk_rd) then if SIMULATION and (rst_rd = '1') then do <= (others => 'U'); elsif geti = '1' then if Is_X(std_logic_vector(ra)) then do <= (others => 'X'); else do <= regfile(to_integer(ra)); end if; end if; end if; end process; end generate gSmall; end rtl;

agpl-3.0

759f4bb0d0f783d9dbb77939f797dd2d

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_max.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

cc60bc6fd7d36b1f70a787aa465677dd

berickson1/DE2-Adafruit-ZFM-20

Quartus/FingerprintSensorExample.vhd

-- ZFM-20 Fingerprint Sensor Example -- Top level system file library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.vital_primitives.all; use work.DE2_CONSTANTS.all; entity FingerprintSensorExample is port ( -- Reset and Clock KEY : in std_logic_vector (0 downto 0); CLOCK_50 : in std_logic; CLOCK_27 : in std_logic; -- Off Chip GPIO_1 : inout std_logic_vector(35 downto 0); -- SDRAM On Board DRAM_ADDR : out DE2_SDRAM_ADDR_BUS; DRAM_BA_0 : out std_logic; DRAM_BA_1 : out std_logic; DRAM_CAS_N : out std_logic; DRAM_CKE : out std_logic; DRAM_CLK : out std_logic; DRAM_CS_N : out std_logic; DRAM_DQ : inout DE2_SDRAM_DATA_BUS; DRAM_LDQM : out std_logic; DRAM_UDQM : out std_logic; DRAM_RAS_N : out std_logic; DRAM_WE_N : out std_logic; -- SRAM On Board SRAM_ADDR : out DE2_SRAM_ADDR_BUS; SRAM_DQ : inout DE2_SRAM_DATA_BUS; SRAM_WE_N : out std_logic; SRAM_OE_N : out std_logic; SRAM_UB_N : out std_logic; SRAM_LB_N : out std_logic; SRAM_CE_N : out std_logic; -- Flash memory FL_ADDR : out std_logic_vector (21 downto 0); FL_CE_N : out std_logic_vector (0 downto 0); FL_OE_N : out std_logic_vector (0 downto 0); FL_DQ : inout std_logic_vector (7 downto 0); FL_RST_N : out std_logic_vector (0 downto 0); FL_WE_N : out std_logic_vector (0 downto 0) ); end FingerprintSensorExample; architecture structure of FingerprintSensorExample is component nios_system is port ( clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n -- export altpll_0_c0_clk : out std_logic; -- clk serial_external_connection_rxd : in std_logic := 'X'; -- rxd serial_external_connection_txd : out std_logic; -- txd sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- addr sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba sdram_0_wire_cas_n : out std_logic; -- cas_n sdram_0_wire_cke : out std_logic; -- cke sdram_0_wire_cs_n : out std_logic; -- cs_n sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm sdram_0_wire_ras_n : out std_logic; -- ras_n sdram_0_wire_we_n : out std_logic; -- we_n tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- generic_tristate_controller_0_tcm_address_out ); end component nios_system; -- signals to match provided IP core to specific SDRAM chip of our system signal BA : std_logic_vector (1 downto 0); signal DQM : std_logic_vector (1 downto 0); begin DRAM_BA_1 <= BA(1); DRAM_BA_0 <= BA(0); DRAM_UDQM <= DQM(1); DRAM_LDQM <= DQM(0); FL_RST_N <= "1"; u0 : component nios_system port map ( reset_reset_n => KEY(0), -- reset.reset_n altpll_0_c0_clk => DRAM_CLK, -- altpll_0_c0.clk serial_external_connection_rxd => GPIO_1(26), -- GREEN serial_external_connection.rxd serial_external_connection_txd => GPIO_1(28), -- WHITE .txd sdram_0_wire_addr => DRAM_ADDR, -- sdram_0_wire.addr sdram_0_wire_ba => BA, -- .ba sdram_0_wire_cas_n => DRAM_CAS_N, -- .cas_n sdram_0_wire_cke => DRAM_CKE, -- .cke sdram_0_wire_cs_n => DRAM_CS_N, -- .cs_n sdram_0_wire_dq => DRAM_DQ, -- .dq sdram_0_wire_dqm => DQM, -- .dqm sdram_0_wire_ras_n => DRAM_RAS_N, -- .ras_n sdram_0_wire_we_n => DRAM_WE_N, -- .we_n clk_clk => CLOCK_50, -- clk.clk tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out => FL_OE_N, -- tristate_conduit_bridge_0_out.generic_tristate_controller_0_tcm_read_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out => FL_DQ, -- .generic_tristate_controller_0_tcm_data_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out => FL_CE_N, -- .generic_tristate_controller_0_tcm_chipselect_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out => FL_WE_N, -- .generic_tristate_controller_0_tcm_write_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out => FL_ADDR -- .generic_tristate_controller_0_tcm_address_out ); end structure; library ieee; --DE2 Constants use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.vital_primitives.all; package DE2_CONSTANTS is subtype DE2_LCD_DATA_BUS is std_logic_vector(7 downto 0); subtype DE2_LED_GREEN is std_logic_vector(7 downto 0); subtype DE2_SRAM_ADDR_BUS is std_logic_vector(17 downto 0); subtype DE2_SRAM_DATA_BUS is std_logic_vector(15 downto 0); subtype DE2_SDRAM_ADDR_BUS is std_logic_vector(11 downto 0); subtype DE2_SDRAM_DATA_BUS is std_logic_vector(15 downto 0); end DE2_CONSTANTS;

gpl-2.0

ae6082d7cb2be1e7469caacfbd3c5070

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_max.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 1; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

b24c8695fe201313b2233ccfe679a25f

malkadi/FGPU

RTL/CV.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity CV is -- {{{ port( -- CU Scheduler signals instr : in std_logic_vector(DATA_W-1 downto 0); -- level 0. wf_indx, wf_indx_in_wg : in natural range 0 to N_WF_CU-1; -- level 0. phase : in unsigned(PHASE_W-1 downto 0); -- level 0. alu_en_divStack : in std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 2. -- RTM signals rdAddr_alu_en : out unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0'); -- level 2. rdData_alu_en : in std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 4. rtm_rdAddr : out unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); -- level 13. rtm_rdData : in unsigned(RTM_DATA_W-1 downto 0); -- level 15. -- gmem signals gmem_re, gmem_we : out std_logic := '0'; -- level 17. mem_op_type : out std_logic_vector(2 downto 0) := (others=>'0'); --level 17. mem_addr : out GMEM_ADDR_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- level 17. mem_rd_addr : out unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); -- level 17. mem_wrData : out SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); --level 17. alu_en : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 17. alu_en_pri_enc : out integer range 0 to CV_SIZE-1 := 0; -- level 17. lmem_rqst, lmem_we : out std_logic := '0'; -- level 17. gmem_atomic : out std_logic := '0'; -- level 17. --branch wf_is_branching : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- level 18. alu_branch : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 18. mem_regFile_wrAddr : in unsigned(REG_FILE_W-1 downto 0); -- stage -1 (stable for 3 clock cycles) mem_regFile_we : in std_logic_vector(CV_SIZE-1 downto 0); -- stage 0 (stable for 2 clock cycles) (level 20. for loads from lmem) mem_regFile_wrData : in SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- stage 0 (stabel for 2 clock cycles) lmem_regFile_we_p0 : in std_logic := '0'; -- level 19. clk : in std_logic ); attribute max_fanout of wf_indx : signal is 10; end CV; -- }}} architecture Behavioral of CV is -- signals definitions -------------------------------------------------------------------------------------- {{{ ----------------- RTM & Initial ALU enable type rtm_rdAddr_vec_type is array (natural range <>) of unsigned(RTM_ADDR_W-1 downto 0); signal rtm_rdAddr_vec : rtm_rdAddr_vec_type(9 downto 0) := (others=>(others=>'0')); signal rdData_alu_en_vec : alu_en_vec_type(MAX_FPU_DELAY+6 downto 0) := (others=>(others=>'0')); signal rtm_rdData_d0 : unsigned(RTM_DATA_W-1 downto 0); signal alu_en_divStack_vec : alu_en_vec_type(2 downto 0) := (others=>(others=>'0')); signal rdAddr_alu_en_p0 : unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0'); ----------------- global use signal phase_d0, phase_d1 : unsigned( PHASE_W-1 downto 0) := (others=>'0'); signal op_arith_shift, op_arith_shift_n : op_arith_shift_type := op_add; ------------------ decoding signal family : std_logic_vector(FAMILY_W-1 downto 0) := (others=>'0'); signal code : std_logic_vector(CODE_W-1 downto 0) := (others=>'0'); signal inst_rd_addr, inst_rs_addr : std_logic_vector(WI_REG_ADDR_W-1 downto 0) := (others=>'0'); signal inst_rt_addr : std_logic_vector(WI_REG_ADDR_W-1 downto 0) := (others=>'0'); type dim_vec_type is array (natural range <>) of std_logic_vector(1 downto 0); signal dim_vec : dim_vec_type(1 downto 0) := (others=>(others=>'0')); signal dim : std_logic_vector(1 downto 0) := (others=>'0'); type params_vec_type is array (natural range <>) of std_logic_vector(N_PARAMS_W-1 downto 0); signal params_vec : params_vec_type(1 downto 0) := (others=>(others=>'0')); signal params : std_logic_vector(N_PARAMS_W-1 downto 0) := (others=>'0'); type family_vec_type is array(natural range <>) of std_logic_vector(FAMILY_W-1 downto 0); signal family_vec : family_vec_type(MAX_FPU_DELAY+10 downto 0) := (others=>(others=>'0')); signal family_vec_at_16 : std_logic_vector(FAMILY_W-1 downto 0) := (others=>'0'); -- this signal is extracted out of family_vec to dcrease the fanout @family_vec(..@16) attribute max_fanout of family_vec_at_16: signal is 40; signal branch_on_zero : std_logic := '0'; signal branch_on_not_zero : std_logic := '0'; signal wf_is_branching_p0 : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal code_vec : code_vec_type(15 downto 0) := (others=>(others=>'0')); type immediate_vec_type is array(natural range <>) of std_logic_vector(IMM_W-1 downto 0); signal immediate_vec : immediate_vec_type(5 downto 0) := (others=>(others=>'0')); type wf_indx_array is array (natural range <>) of natural range 0 to N_WF_CU-1; signal wf_indx_vec : wf_indx_array(15 downto 0) := (others=>0); signal wf_indx_in_wg_vec : wf_indx_array(1 downto 0) := (others=>0); ------------------ register file signal rs_addr, rt_addr, rd_addr : unsigned(REG_FILE_BLOCK_W-1 downto 0) := (others=>'0'); type op_arith_shift_vec_type is array(natural range <>) of op_arith_shift_type; signal op_arith_shift_vec : op_arith_shift_vec_type(4 downto 0) := (others => op_add); signal op_logical_v : std_logic := '0'; signal regBlock_re : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); -- attribute max_fanout of regBlock_re : signal is 10; signal regBlocK_re_n : std_logic := '0'; signal reg_we_alu, reg_we_alu_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal reg_we_float : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal res_alu : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); type rd_out_vec_type is array (natural range <>) of slv32_array(CV_SIZE-1 downto 0); signal rd_out_vec : rd_out_vec_type(6 downto 0) := (others=>(others=>(others=>'0'))); ------------------ global memory signal gmem_re_p0, gmem_we_p0 : std_logic := '0'; signal gmem_ato_p0 : std_logic := '0'; -------------------------------------------------------------------------------------}}} -- write back into regFiles {{{ type regBlock_we_vec_type is array(natural range <>) of std_logic_vector(N_REG_BLOCKS-1 downto 0); signal regBlock_we : regBlock_we_vec_type(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal regBlock_we_alu : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); attribute max_fanout of regBlock_we_alu : signal is 50; signal regBlock_we_mem : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); signal wrAddr_regFile_vec : reg_addr_array(MAX_FPU_DELAY+12 downto 0) := (others=>(others=>'0')); signal regBlock_wrAddr : reg_file_block_array(N_REG_BLOCKS-1 downto 0) := (others=>(others=>'0')); signal wrData_alu : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); type regBlock_wrData_type is array(natural range <>) of slv32_array(N_REG_BLOCKS-1 downto 0); signal regBlock_wrData : regBlock_wrData_type(CV_SIZE-1 downto 0) := (others=>(others=>(others=>'0'))); signal rtm_rdData_nlid_vec : std_logic_vector(3 downto 0) := (others=>'0'); signal res_low : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_alu_clk2x_d0 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_high : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal reg_we_mov_vec : alu_en_vec_type(6 downto 0) := (others=>(others=>'0')); signal mem_regFile_wrAddr_d0 : unsigned(REG_FILE_W-1 downto 0); signal lmem_regFile_we : std_logic := '0'; -- }}} -- floating point {{{ signal float_a, float_b : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_float : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_float_d0 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal res_float_d1 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal regBlock_we_float_vec : regBlock_we_vec_type(MAX_FPU_DELAY-7 downto 0) := (others=>(others=>'0')); signal regBlock_we_float : std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); attribute max_fanout of regBlock_we_float : signal is 50; -- }}} begin -- internal signals and asserts -------------------------------------------------------------------------{{{ ---------------------------------------------------------------------------------------------------------}}} -- RTM contorl & ALU enable -------------------------------------------------------------------- {{{ process(clk) begin if rising_edge(clk) then -- rtm {{{ rtm_rdData_d0 <= rtm_rdData; -- @ 16. if family_vec(family_vec'high-1) = RTM_FAMILY then -- level 2. case code_vec(code_vec'high-1) is -- level 2. when LID => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '0'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= unsigned(dim_vec(dim_vec'high-1)); --dimension rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= to_unsigned(wf_indx_in_wg_vec(wf_indx_in_wg_vec'high-1), N_WF_CU_W); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1 downto 0) <= phase_d1; when WGOFF => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= unsigned(dim_vec(dim_vec'high-1)); --dimension rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= to_unsigned(wf_indx_vec(wf_indx_vec'high-1), N_WF_CU_W); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1 downto 0) <= (others=>'0'); when SIZE => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= (others=>'1'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1) <= '0'; rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-2 downto 0) <= unsigned(dim_vec(dim_vec'high-1)); when WGID => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= (others=>'1'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1) <= '0'; rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-2 downto 0) <= unsigned(dim_vec(dim_vec'high-1)); when WGSIZE => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= (others=>'1'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-1) <= '0'; rtm_rdAddr_vec(rtm_rdAddr_vec'high)(PHASE_W-2 downto 0) <= unsigned(dim_vec(dim_vec'high-1)); when LP => rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-1) <= '1'; -- @ 3. rtm_rdAddr_vec(rtm_rdAddr_vec'high)(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; --dimension rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_WF_CU_W+PHASE_W-1 downto N_PARAMS_W) <= (others=>'0'); -- wf_indx is zero, except its LSB, rtm_rdAddr_vec(rtm_rdAddr_vec'high)(N_PARAMS_W-1 downto 0) <= unsigned(params_vec(params_vec'high-1)); -- @ 2. when others => end case; end if; rtm_rdAddr_vec(rtm_rdAddr_vec'high-1 downto 0) <= rtm_rdAddr_vec(rtm_rdAddr_vec'high downto 1); -- @ 4.->12. rtm_rdAddr <= rtm_rdAddr_vec(0); -- @ 13. rtm_rdData_nlid_vec(rtm_rdData_nlid_vec'high-1 downto 0) <= rtm_rdData_nlid_vec(rtm_rdData_nlid_vec'high downto 1); -- @ 14.->16. rtm_rdData_nlid_vec(rtm_rdData_nlid_vec'high) <= rtm_rdAddr_vec(0)(RTM_ADDR_W-1); -- @ 13. -- }}} -- ALU enable {{{ rdAddr_alu_en_p0(PHASE_W-1 downto 0) <= phase; --@ 1. rdAddr_alu_en_p0(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= to_unsigned(wf_indx_in_wg, N_WF_CU_W); --@ 1. rdAddr_alu_en <= rdAddr_alu_en_p0; -- @ 2. alu_en_divStack_vec(alu_en_divStack_vec'high) <= alu_en_divStack; -- @ 3. alu_en_divStack_vec(alu_en_divStack_vec'high-1 downto 0) <= alu_en_divStack_vec(alu_en_divStack_vec'high downto 1); -- @ 4.->5. rdData_alu_en_vec(rdData_alu_en_vec'high) <= rdData_alu_en; -- @ 5. rdData_alu_en_vec(rdData_alu_en_vec'high-1) <= rdData_alu_en_vec(rdData_alu_en_vec'high) and not alu_en_divStack_vec(0); -- @ 6. rdData_alu_en_vec(rdData_alu_en_vec'high-2 downto 0) <= rdData_alu_en_vec(rdData_alu_en_vec'high-1 downto 1); -- @ 7.->7+MAX_FPU_DELAY+4. -- for gmem operations alu_en <= rdData_alu_en_vec(rdData_alu_en_vec'high-11); -- @ 17. alu_en_pri_enc <= 0; -- @ 17. for i in CV_SIZE-1 downto 0 loop if rdData_alu_en_vec(rdData_alu_en_vec'high-11)(i) = '1' then -- level 16. alu_en_pri_enc <= i; -- @ 17. end if; end loop; -- }}} end if; end process; ----------------------------------------------------------------------------------------------}}} -- decoding logic --------------------------------------------------------------------{{{ family <= instr(FAMILY_POS+FAMILY_W-1 downto FAMILY_POS); -- alias code <= instr(CODE_POS+CODE_W-1 downto CODE_POS); -- alias inst_rd_addr <= instr(RD_POS+WI_REG_ADDR_W-1 downto RD_POS); -- alias inst_rs_addr <= instr(RS_POS+WI_REG_ADDR_W-1 downto RS_POS); -- alias inst_rt_addr <= instr(RT_POS+WI_REG_ADDR_W-1 downto RT_POS); -- alias dim <= instr(DIM_POS+1 downto DIM_POS); params <= instr(PARAM_POS+N_PARAMS_W-1 downto PARAM_POS); process(clk) begin if rising_edge(clk) then -- pipes {{{ family_vec(family_vec'high-1 downto 0) <= family_vec(family_vec'high downto 1); -- @ 2.->2+MAX_FPU_DELAY+9. family_vec(family_vec'high) <= family; -- @ 1. family_vec_at_16 <= family_vec(family_vec'high-14); -- @ 16. dim_vec(dim_vec'high-1 downto 0) <= dim_vec(dim_vec'high downto 1); -- @ 2 dim_vec(dim_vec'high) <= dim; -- @ 1. code_vec(code_vec'high-1 downto 0) <= code_vec(code_vec'high downto 1); -- @ 2.->16. code_vec(code_vec'high) <= code; -- @ 1. params_vec(params_vec'high-1 downto 0) <= params_vec(params_vec'high downto 1); -- @ 2.->2. params_vec(params_vec'high) <= params; -- @ 1. immediate_vec(immediate_vec'high-1 downto 0) <= immediate_vec(immediate_vec'high downto 1); -- @ 2.->6. immediate_vec(immediate_vec'high)(IMM_ARITH_W-1 downto 0) <= instr(IMM_POS+IMM_ARITH_W-1 downto IMM_POS); -- @ 1. immediate_vec(immediate_vec'high)(IMM_W-1 downto IMM_ARITH_W) <= instr(RS_POS+IMM_W-IMM_ARITH_W-1 downto RS_POS); -- @ 1. wf_indx_vec(wf_indx_vec'high-1 downto 0) <= wf_indx_vec(wf_indx_vec'high downto 1); -- @ 2.->16. wf_indx_vec(wf_indx_vec'high) <= wf_indx; -- @ 1. wf_indx_in_wg_vec(wf_indx_in_wg_vec'high-1 downto 0) <= wf_indx_in_wg_vec(wf_indx_in_wg_vec'high downto 1); -- @ 2.->2. wf_indx_in_wg_vec(wf_indx_in_wg_vec'high) <= wf_indx_in_wg; -- @ 1. regBlock_re(0) <= regBlock_re_n; -- @ 1. regBlock_re(regBlock_re'high downto 1) <= regBlock_re(regBlock_re'high-1 downto 0); -- @ 2.->4. op_arith_shift <= op_arith_shift_n; -- @ 1. op_arith_shift_vec(op_arith_shift_vec'high-1 downto 0) <= op_arith_shift_vec(op_arith_shift_vec'high downto 1); -- @ 3.->6. op_arith_shift_vec(op_arith_shift_vec'high) <= op_arith_shift; -- @ 2. phase_d0 <= phase; -- @ 1. phase_d1 <= phase_d0; -- @ 2. -- }}} -- Rs, Rt & Rd addresses {{{ rs_addr(REG_FILE_BLOCK_W-1) <= phase(PHASE_W-1); -- @1. rs_addr(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W) <= to_unsigned(wf_indx, N_WF_CU_W); -- @1. if family = ADD_FAMILY and code(3) = '1'then -- level 0. rs_addr(WI_REG_ADDR_W-1 downto 0) <= (others=>'0'); -- @1. -- for li & lui else rs_addr(WI_REG_ADDR_W-1 downto 0) <= unsigned(inst_rs_addr); -- @1. end if; rt_addr(REG_FILE_BLOCK_W-1) <= phase(PHASE_W-1); -- @1. rt_addr(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W) <= to_unsigned(wf_indx, N_WF_CU_W); -- @1. rt_addr(WI_REG_ADDR_W-1 downto 0) <= unsigned(inst_rt_addr); -- @1. rd_addr <= wrAddr_regFile_vec(wrAddr_regFile_vec'high)(REG_FILE_BLOCK_W-1 downto 0); -- @1. -- }}} -- set operation type {{{ op_logical_v <= '0'; -- @ 14. if family_vec(family_vec'high-12) = LGK_FAMILY then -- level 13. op_logical_v <= '1'; -- @ 14. end if; -- }}} end if; end process; -- memory accesses {{{ process(clk) begin if rising_edge(clk) then -- pipes {{{ rd_out_vec(rd_out_vec'high-1 downto 0) <= rd_out_vec(rd_out_vec'high downto 1); -- @ 11.->16. -- }}} -- @ 16 {{{ gmem_re_p0 <= '0'; -- @ 16. gmem_we_p0 <= '0'; -- @ 16. if family_vec(family_vec'high-14) = GLS_FAMILY then -- level 15. if code_vec(1)(3) = '1' then -- level 15. gmem_re_p0 <= '0'; -- store @ 16. gmem_we_p0 <= '1'; else gmem_re_p0 <= '1'; -- load @ 16. gmem_we_p0 <= '0'; end if; end if; if ATOMIC_IMPLEMENT /= 0 then gmem_ato_p0 <= '0'; if family_vec(family_vec'high-14) = ATO_FAMILY then -- level 15. gmem_ato_p0 <= '1'; -- @ 16. end if; end if; -- }}} -- @ 17 {{{ gmem_we <= gmem_we_p0; -- @ 17. gmem_re <= gmem_re_p0; -- @ 17. if ATOMIC_IMPLEMENT /= 0 then gmem_atomic <= gmem_ato_p0; -- @ 17. end if; if LMEM_IMPLEMENT /= 0 then lmem_rqst <= '0'; -- @ 17. lmem_we <= '0'; -- @ 17. if family_vec(family_vec'high-15) = LSI_FAMILY then -- level 16. lmem_rqst <= '1'; -- @ 17. if code_vec(0)(3) = '1' then -- level 16. lmem_we <= '1'; -- @ 17. else lmem_we <= '0'; -- @ 17. end if; end if; end if; mem_wrData <= rd_out_vec(0); -- @ 17. mem_rd_addr <= wrAddr_regFile_vec(wrAddr_regFile_vec'high-16); -- @ 17. for i in 0 to CV_SIZE-1 loop mem_addr(i) <= unsigned(res_low(i)(GMEM_ADDR_W-1 downto 0)); -- @ 17. end loop; mem_op_type <= code_vec(0)(2 downto 0); -- @ 17. -- }}} end if; end process; -- }}} ------------------------------------------------------------------------------------------------}}} -- ALUs ----------------------------------------------------------------------------------------- {{{ ALUs: for i in 0 to CV_SIZE-1 generate begin -- the calculation begins @ level 3 in the pipeline alu_inst: entity ALU port map( rs_addr => rs_addr, --level 1. rt_addr => rt_addr, -- level 1. rd_addr => rd_addr, -- level 1. family => family_vec(family_vec'high), -- level 1. regBlock_re => regBlock_re, -- level 1. op_arith_shift => op_arith_shift_vec(0), -- level 6. code => code_vec(code_vec'high-5), -- level 6. immediate => immediate_vec(0), -- level 6. rd_out => rd_out_vec(rd_out_vec'high)(i), -- level 10. reg_we_mov => reg_we_mov_vec(reg_we_mov_vec'high)(i), -- level 10. float_a => float_a(i), -- level 9. float_b => float_b(i), -- level 9. op_logical_v => op_logical_v, -- level 14. res_low => res_low(i), -- level 16. res_high => res_high(i), -- level 16. reg_wrData => regBlock_wrData(i), -- level 18. (level 21. for loads from lmem) (level 24. for float results) reg_wrAddr => regBlock_wrAddr, -- level 18. (level 21. for loads from lmem) (level 24. for float results) reg_we => regBlock_we(i), -- level 18. (level 21. for loads from lmem) (level 24. for float results) clk => clk ); end generate; -- set register files read enables {{{ set_register_re:process(phase(0), family) -- this process executes in level 0. begin regBlock_re_n <= '0'; -- level 0. case family is -- level 0. when ADD_FAMILY | MUL_FAMILY | BRA_FAMILY | SHF_FAMILY | LGK_FAMILY | CND_FAMILY | MOV_FAMILY | LSI_FAMILY | FLT_FAMILY | GLS_FAMILY | ATO_FAMILY=> if phase(PHASE_W-2 downto 0) = (0 to PHASE_W-2=>'0') then -- phase = 0 or 4 regBlock_re_n <= '1'; end if; when others => end case; -- }}} -- set opertion type {{{ op_arith_shift_n <= op_add; -- level 0. case family is -- level 0. when ADD_FAMILY => op_arith_shift_n <= op_add; when MUL_FAMILY => op_arith_shift_n <= op_mult; when GLS_FAMILY => op_arith_shift_n <= op_lw; when LSI_FAMILY => op_arith_shift_n <= op_lmem; when ATO_FAMILY => op_arith_shift_n <= op_ato; when BRA_FAMILY => op_arith_shift_n <= op_bra; when SHF_FAMILY => op_arith_shift_n <= op_shift; when CND_FAMILY => op_arith_shift_n <= op_slt; when MOV_FAMILY => op_arith_shift_n <= op_mov; when others => end case; end process; -- }}} ---------------------------------------------------------------------------------------}}} -- floating point ---------------------------------------------------------------------------------------{{{ float_units_inst: if FLOAT_IMPLEMENT /= 0 generate float_inst: entity float_units port map( float_a => float_a, -- level 9. float_b => float_b, -- level 9. fsub => code_vec(7)(CODE_W-1), -- level 9. code => code_vec(0), -- level 16. res_float => res_float, -- level MAX_FPU_DELAY+10. (38 if fdiv, 21 if fadd) clk => clk ); process(clk) begin if rising_edge(clk) then res_float_d0 <= res_float; -- @ MAX_FPU_DELAY+11 (39 if fdiv, 22 if fadd) res_float_d1 <= res_float_d0; -- @ MAX_FPU_DELAY+12 (40 if fdiv, 23 if fadd) -- float_ce <= '0'; -- for i in 0 to N_REG_BLOCKS-1 loop -- if regBlock_re_vec(1)(i) = '1' then -- float_ce <= '1'; -- end if; -- end loop; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- branch control ---------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then -- @ 17 {{{ res_alu <= res_low; -- @ 17. branch_on_zero <= '0'; -- @ 17. branch_on_not_zero <= '0'; -- @ 17. wf_is_branching_p0 <= (others=>'0'); if family_vec(family_vec'high-15) = BRA_FAMILY then -- level 16. wf_is_branching_p0(wf_indx_vec(0)) <= '1'; -- @ 17. case code_vec(0) is -- level 16. when BEQ => branch_on_zero <= '1'; -- @ 17. when BNE => branch_on_not_zero <= '1'; -- @ 17. when others=> end case; end if; -- }}} -- @ 18 {{{ wf_is_branching <= wf_is_branching_p0; -- @ 18. alu_branch <= (others=>'0'); -- @ 18. for i in 0 to CV_SIZE-1 loop if res_alu(i) = (res_alu(i)'reverse_range=>'0') then -- level 17. if branch_on_zero = '1' then -- level 17. alu_branch(i) <= '1'; -- @ 18. end if; else if branch_on_not_zero = '1' then -- level 17. alu_branch(i) <= '1'; -- @ 18. end if; end if; end loop; -- }}} end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- write back into regFiles ----------------------------------------------------------------------------------{{{ -- register file ----------------------------------------------------------------------- -- bits 10:9 8 7:5 4:0 -- phase(1:0) phase(2) wf_indx instr_rd_addr wrAddr_regFile_vec(wrAddr_regFile_vec'high)(REG_FILE_W-1 downto REG_FILE_W-2) <= phase(1 downto 0); -- level 0. wrAddr_regFile_vec(wrAddr_regFile_vec'high)(REG_FILE_W-3) <= phase(PHASE_W-1); -- level 0. wrAddr_regFile_vec(wrAddr_regFile_vec'high)(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W) <= to_unsigned(wf_indx, N_WF_CU_W); -- level 0. wrAddr_regFile_vec(wrAddr_regFile_vec'high)(WI_REG_ADDR_W-1 downto 0) <= unsigned(inst_rd_addr); -- level 0. write_alu_res_back: process(family_vec(family_vec'high-15), rdData_alu_en_vec(rdData_alu_en_vec'high-11), reg_we_mov_vec(0)) begin reg_we_alu_n <= (others=>'0'); -- level 16. case family_vec(family_vec'high-15) is -- level 16. when RTM_FAMILY | ADD_FAMILY | MUL_FAMILY | SHF_FAMILY | LGK_FAMILY | CND_FAMILY => reg_we_alu_n <= rdData_alu_en_vec(rdData_alu_en_vec'high-11); -- level 16. when MOV_FAMILY => reg_we_alu_n <= rdData_alu_en_vec(rdData_alu_en_vec'high-11) and reg_we_mov_vec(0); -- level 16. when others=> end case; end process; process(clk) begin if rising_edge(clk) then wrAddr_regFile_vec(wrAddr_regFile_vec'high-1 downto 0) <= wrAddr_regFile_vec(wrAddr_regFile_vec'high downto 1); -- @ 1.->MAX_FPU_DELAY+12. reg_we_mov_vec(reg_we_mov_vec'high-1 downto 0) <= reg_we_mov_vec(reg_we_mov_vec'high downto 1); -- @ 11.->16. lmem_regFile_we <= lmem_regFile_we_p0; reg_we_alu <= reg_we_alu_n; -- @ 17. reg_we_float <= (others=>'0'); -- @ 23. case MAX_FPU_DELAY is when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay if family_vec(1) = FLT_FAMILY then -- level 38. if fdiv reg_we_float <= rdData_alu_en_vec(1); -- @ 39. if fdiv end if; when others => -- fadd has the maximum delay if family_vec(0) = FLT_FAMILY then -- level 22. if fadd reg_we_float <= rdData_alu_en_vec(0); -- @ 23. if fadd end if; end case; wrData_alu <= (others=>(others=>'0')); -- @ 17. case family_vec_at_16 is -- level 16. when RTM_FAMILY => if rtm_rdData_nlid_vec(0) = '0' then -- level 16. for i in 0 to CV_SIZE-1 loop wrData_alu(i)(WG_SIZE_W-1 downto 0) <= std_logic_vector(rtm_rdData_d0((i+1)*WG_SIZE_W-1 downto i*WG_SIZE_W)); -- @ 17. end loop; else for i in 0 to CV_SIZE-1 loop wrData_alu(i) <= std_logic_vector(rtm_rdData_d0(DATA_W-1 downto 0)); -- @ 17. end loop; end if; when ADD_FAMILY | MUL_FAMILY | CND_FAMILY | MOV_FAMILY => wrData_alu <= res_low; -- @ 17. when SHF_FAMILY => if code_vec(0)(CODE_W-1) = '0' then -- level 16. wrData_alu <= res_low; -- @ 17. else wrData_alu <= res_high; end if; when LGK_FAMILY => wrData_alu <= res_low; -- @ 17. when GLS_FAMILY => when others => end case; regBlock_we_alu <= (others=>'0'); -- @ 17. regBlock_we_alu(to_integer(wrAddr_regFile_vec(wrAddr_regFile_vec'high-16)(REG_FILE_W-1 downto REG_FILE_BLOCK_W))) <= '1'; -- @ 17.+N_REG_BLOCKS*i -- regBlock_we_float {{{ regBlock_we_float_vec(regBlock_we_float_vec'high) <= regBlock_we_alu; -- @ 18.+N_REG_BLOCKS*i regBlock_we_float_vec(regBlock_we_float_vec'high-1 downto 0) <= regBlock_we_float_vec(regBlock_we_float_vec'high downto 1); -- @ 19.->19+MAX_FPU_DELAY-7-1 (39. if fdiv, 22. if fadd) case MAX_FPU_DELAY is when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay regBlock_we_float <= regBlock_we_float_vec(1); -- @ MAX_FPU_DELAY+11 (39. if fadd) when others => -- fadd has the maximum delay regBlock_we_float <= regBlock_we_float_vec(0); -- @ MAX_FPU_DELAY+12 (23. if fadd) end case; -- }}} -- the register block that will be written from global and local memory reads will be selected {{{ if LMEM_IMPLEMENT = 0 or lmem_regFile_we_p0 = '0' then -- if no read of lmem content is comming, prepare the we of the register block according to the current address sent from CU_mem_cntrl regBlock_we_mem <= (others=>'0'); -- stage 0 regBlock_we_mem(to_integer(mem_regFile_wrAddr(REG_FILE_W-1 downto REG_FILE_BLOCK_W))) <= '1'; -- (@ 22. for lmem reads) elsif lmem_regFile_we = '0' or regBlock_we_mem(N_REG_BLOCKS-1) = '1' then -- there will be a read from lmem or a half of the read data burst is over. Set the we of the first register block! regBlock_we_mem(N_REG_BLOCKS-1 downto 1) <= (others=>'0'); -- stage 0 regBlock_we_mem(0) <= '1'; else -- lmem is being read. Shift left for regBlock_we_mem! regBlock_we_mem(N_REG_BLOCKS-1 downto 1) <= regBlock_we_mem(N_REG_BLOCKS-2 downto 0); regBlock_we_mem(0) <= '0'; end if; mem_regFile_wrAddr_d0 <= mem_regFile_wrAddr; -- stage 1 -- }}} -- regBlock_wrAddr {{{ for j in 0 to N_REG_BLOCKS-1 loop if regBlock_we_alu(j) = '1' then -- level 17.+j regBlock_wrAddr(j) <= wrAddr_regFile_vec(wrAddr_regFile_vec'high-17)(REG_FILE_BLOCK_W-1 downto 0); -- @ 18.+j elsif FLOAT_IMPLEMENT /= 0 and regBlock_we_float(j) = '1' then -- level 23.+j if add, 39.+j if fdiv case MAX_FPU_DELAY is when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay regBlock_wrAddr(j) <= wrAddr_regFile_vec(1)(REG_FILE_BLOCK_W-1 downto 0); -- @ 40.+j if fdiv when others => -- fadd has the maximum delay regBlock_wrAddr(j) <= wrAddr_regFile_vec(0)(REG_FILE_BLOCK_W-1 downto 0); -- @ 24.+j if fadd end case; else regBlock_wrAddr(j) <= mem_regFile_wrAddr(REG_FILE_BLOCK_W-1 downto 0); -- stage 1. or 2. end if; end loop; -- }}} for i in 0 to CV_SIZE-1 loop for j in 0 to N_REG_BLOCKS-1 loop -- regBlock_wrData {{{ if regBlock_we_alu(j) = '1' then -- level 17. -- write by alu operations regBlock_wrData(i)(j) <= wrData_alu(i); -- @ 18. elsif FLOAT_IMPLEMENT /= 0 and regBlock_we_float(j) = '1' then -- level 23. if fadd, 39. if fdiv -- write by floating point units case MAX_FPU_DELAY is when FDIV_DELAY => -- fsqrt of fdiv has the maximum delay regBlock_wrData(i)(j) <= res_float_d0(i); -- @ 40.+j when others => -- fadd has the maximum delay regBlock_wrData(i)(j) <= res_float_d1(i); -- @ 24.+j end case; else -- write by memory reads regBlock_wrData(i)(j) <= mem_regFile_wrData(i); -- @ 1. or 2. end if; -- }}} -- regBlock_we {{{ if regBlock_we_alu(j) = '1' then -- level 17.+j regBlock_we(i)(j) <= reg_we_alu(i); -- @ 18.+j elsif FLOAT_IMPLEMENT /= 0 and regBlock_we_float(j) = '1' then -- level 23.+j if fadd, 39.+j uf fdiv regBlock_we(i)(j) <= reg_we_float(i); -- @ 24.+j if fadd, 40.+j if fdiv elsif regBlock_we_mem(j) = '1' then -- (level 22 for lmem reads; no conflict with 17+N_REG_BLOCKS*i) regBlock_we(i)(j) <= mem_regFile_we(i); -- @ 1. or 2. (@23. for loads from lmem) else regBlock_we(i)(j) <= '0'; end if; -- }}} end loop; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

149a9f52f207b9b109053da08d7ca52b

malkadi/FGPU

HW/sources/IPs/FGPU_3.0/hdl/FGPU_v3_0.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; library xil_defaultlib; use xil_defaultlib.all; ------------------------------------------------------------------------------------------------- }}} entity FGPU_v3_0 is -- generics {{{ generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Slave Bus Interface S0 C_S0_DATA_WIDTH : integer := 32; C_S0_ADDR_WIDTH : integer := 16; -- Parameters of Axi Master Bus Interface M0 C_M0_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M0_BURST_LEN : integer := 8; C_M0_ID_WIDTH : integer := 6; C_M0_ADDR_WIDTH : integer := 32; C_M0_DATA_WIDTH : integer := 64; C_M0_AWUSER_WIDTH : integer := 0; C_M0_ARUSER_WIDTH : integer := 0; C_M0_WUSER_WIDTH : integer := 0; C_M0_RUSER_WIDTH : integer := 0; C_M0_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M1 C_M1_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M1_BURST_LEN : integer := 8; C_M1_ID_WIDTH : integer := 6; C_M1_ADDR_WIDTH : integer := 32; C_M1_DATA_WIDTH : integer := 64; C_M1_AWUSER_WIDTH : integer := 0; C_M1_ARUSER_WIDTH : integer := 0; C_M1_WUSER_WIDTH : integer := 0; C_M1_RUSER_WIDTH : integer := 0; C_M1_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M2 C_M2_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M2_BURST_LEN : integer := 8; C_M2_ID_WIDTH : integer := 6; C_M2_ADDR_WIDTH : integer := 32; C_M2_DATA_WIDTH : integer := 64; C_M2_AWUSER_WIDTH : integer := 0; C_M2_ARUSER_WIDTH : integer := 0; C_M2_WUSER_WIDTH : integer := 0; C_M2_RUSER_WIDTH : integer := 0; C_M2_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M3 C_M3_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M3_BURST_LEN : integer := 8; C_M3_ID_WIDTH : integer := 6; C_M3_ADDR_WIDTH : integer := 32; C_M3_DATA_WIDTH : integer := 64; C_M3_AWUSER_WIDTH : integer := 0; C_M3_ARUSER_WIDTH : integer := 0; C_M3_WUSER_WIDTH : integer := 0; C_M3_RUSER_WIDTH : integer := 0; C_M3_BUSER_WIDTH : integer := 0 ); --}}} -- ports {{{ port ( -- Users to add ports here -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Slave Bus Interface S0 {{{ s0_aclk : in std_logic; s0_aresetn : in std_logic; s0_awaddr : in std_logic_vector(C_S0_ADDR_WIDTH-1 downto 0); s0_awprot : in std_logic_vector(2 downto 0); s0_awvalid : in std_logic; s0_awready : out std_logic; s0_wdata : in std_logic_vector(C_S0_DATA_WIDTH-1 downto 0); s0_wstrb : in std_logic_vector((C_S0_DATA_WIDTH/8)-1 downto 0); s0_wvalid : in std_logic; s0_wready : out std_logic; s0_bresp : out std_logic_vector(1 downto 0); s0_bvalid : out std_logic; s0_bready : in std_logic; s0_araddr : in std_logic_vector(C_S0_ADDR_WIDTH-1 downto 0); s0_arprot : in std_logic_vector(2 downto 0); s0_arvalid : in std_logic; s0_arready : out std_logic; s0_rdata : out std_logic_vector(C_S0_DATA_WIDTH-1 downto 0); s0_rresp : out std_logic_vector(1 downto 0); s0_rvalid : out std_logic; s0_rready : in std_logic; -- }}} -- Ports of Axi Master Bus Interface M0 {{{ m0_aclk : in std_logic; m0_aresetn : in std_logic; m0_awid : out std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_awaddr : out std_logic_vector(C_M0_ADDR_WIDTH-1 downto 0); m0_awlen : out std_logic_vector(7 downto 0); m0_awsize : out std_logic_vector(2 downto 0); m0_awburst : out std_logic_vector(1 downto 0); m0_awlock : out std_logic; m0_awcache : out std_logic_vector(3 downto 0); m0_awprot : out std_logic_vector(2 downto 0); m0_awqos : out std_logic_vector(3 downto 0); m0_awuser : out std_logic_vector(C_M0_AWUSER_WIDTH-1 downto 0); m0_awvalid : out std_logic; m0_awready : in std_logic; m0_wdata : out std_logic_vector(C_M0_DATA_WIDTH-1 downto 0); m0_wstrb : out std_logic_vector(C_M0_DATA_WIDTH/8-1 downto 0); m0_wlast : out std_logic; m0_wuser : out std_logic_vector(C_M0_WUSER_WIDTH-1 downto 0); m0_wvalid : out std_logic; m0_wready : in std_logic; m0_bid : in std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_bresp : in std_logic_vector(1 downto 0); m0_buser : in std_logic_vector(C_M0_BUSER_WIDTH-1 downto 0); m0_bvalid : in std_logic; m0_bready : out std_logic; m0_arid : out std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_araddr : out std_logic_vector(C_M0_ADDR_WIDTH-1 downto 0); m0_arlen : out std_logic_vector(7 downto 0); m0_arsize : out std_logic_vector(2 downto 0); m0_arburst : out std_logic_vector(1 downto 0); m0_arlock : out std_logic; m0_arcache : out std_logic_vector(3 downto 0); m0_arprot : out std_logic_vector(2 downto 0); m0_arqos : out std_logic_vector(3 downto 0); m0_aruser : out std_logic_vector(C_M0_ARUSER_WIDTH-1 downto 0); m0_arvalid : out std_logic; m0_arready : in std_logic; m0_rid : in std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_rdata : in std_logic_vector(C_M0_DATA_WIDTH-1 downto 0); m0_rresp : in std_logic_vector(1 downto 0); m0_rlast : in std_logic; m0_ruser : in std_logic_vector(C_M0_RUSER_WIDTH-1 downto 0); m0_rvalid : in std_logic; m0_rready : out std_logic; --}}} -- Ports of Axi Master Bus Interface M1 {{{ m1_aclk : in std_logic; m1_aresetn : in std_logic; m1_awid : out std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_awaddr : out std_logic_vector(C_M1_ADDR_WIDTH-1 downto 0); m1_awlen : out std_logic_vector(7 downto 0); m1_awsize : out std_logic_vector(2 downto 0); m1_awburst : out std_logic_vector(1 downto 0); m1_awlock : out std_logic; m1_awcache : out std_logic_vector(3 downto 0); m1_awprot : out std_logic_vector(2 downto 0); m1_awqos : out std_logic_vector(3 downto 0); m1_awuser : out std_logic_vector(C_M1_AWUSER_WIDTH-1 downto 0); m1_awvalid : out std_logic; m1_awready : in std_logic; m1_wdata : out std_logic_vector(C_M1_DATA_WIDTH-1 downto 0); m1_wstrb : out std_logic_vector(C_M1_DATA_WIDTH/8-1 downto 0); m1_wlast : out std_logic; m1_wuser : out std_logic_vector(C_M1_WUSER_WIDTH-1 downto 0); m1_wvalid : out std_logic; m1_wready : in std_logic; m1_bid : in std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_bresp : in std_logic_vector(1 downto 0); m1_buser : in std_logic_vector(C_M1_BUSER_WIDTH-1 downto 0); m1_bvalid : in std_logic; m1_bready : out std_logic; m1_arid : out std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_araddr : out std_logic_vector(C_M1_ADDR_WIDTH-1 downto 0); m1_arlen : out std_logic_vector(7 downto 0); m1_arsize : out std_logic_vector(2 downto 0); m1_arburst : out std_logic_vector(1 downto 0); m1_arlock : out std_logic; m1_arcache : out std_logic_vector(3 downto 0); m1_arprot : out std_logic_vector(2 downto 0); m1_arqos : out std_logic_vector(3 downto 0); m1_aruser : out std_logic_vector(C_M1_ARUSER_WIDTH-1 downto 0); m1_arvalid : out std_logic; m1_arready : in std_logic; m1_rid : in std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_rdata : in std_logic_vector(C_M1_DATA_WIDTH-1 downto 0); m1_rresp : in std_logic_vector(1 downto 0); m1_rlast : in std_logic; m1_ruser : in std_logic_vector(C_M1_RUSER_WIDTH-1 downto 0); m1_rvalid : in std_logic; m1_rready : out std_logic; -- }}} -- Ports of Axi Master Bus Interface M2 {{{ m2_aclk : in std_logic; m2_aresetn : in std_logic; m2_awid : out std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_awaddr : out std_logic_vector(C_M2_ADDR_WIDTH-1 downto 0); m2_awlen : out std_logic_vector(7 downto 0); m2_awsize : out std_logic_vector(2 downto 0); m2_awburst : out std_logic_vector(1 downto 0); m2_awlock : out std_logic; m2_awcache : out std_logic_vector(3 downto 0); m2_awprot : out std_logic_vector(2 downto 0); m2_awqos : out std_logic_vector(3 downto 0); m2_awuser : out std_logic_vector(C_M2_AWUSER_WIDTH-1 downto 0); m2_awvalid : out std_logic; m2_awready : in std_logic; m2_wdata : out std_logic_vector(C_M2_DATA_WIDTH-1 downto 0); m2_wstrb : out std_logic_vector(C_M2_DATA_WIDTH/8-1 downto 0); m2_wlast : out std_logic; m2_wuser : out std_logic_vector(C_M2_WUSER_WIDTH-1 downto 0); m2_wvalid : out std_logic; m2_wready : in std_logic; m2_bid : in std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_bresp : in std_logic_vector(1 downto 0); m2_buser : in std_logic_vector(C_M2_BUSER_WIDTH-1 downto 0); m2_bvalid : in std_logic; m2_bready : out std_logic; m2_arid : out std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_araddr : out std_logic_vector(C_M2_ADDR_WIDTH-1 downto 0); m2_arlen : out std_logic_vector(7 downto 0); m2_arsize : out std_logic_vector(2 downto 0); m2_arburst : out std_logic_vector(1 downto 0); m2_arlock : out std_logic; m2_arcache : out std_logic_vector(3 downto 0); m2_arprot : out std_logic_vector(2 downto 0); m2_arqos : out std_logic_vector(3 downto 0); m2_aruser : out std_logic_vector(C_M2_ARUSER_WIDTH-1 downto 0); m2_arvalid : out std_logic; m2_arready : in std_logic; m2_rid : in std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_rdata : in std_logic_vector(C_M2_DATA_WIDTH-1 downto 0); m2_rresp : in std_logic_vector(1 downto 0); m2_rlast : in std_logic; m2_ruser : in std_logic_vector(C_M2_RUSER_WIDTH-1 downto 0); m2_rvalid : in std_logic; m2_rready : out std_logic; -- }}} -- Ports of Axi Master Bus Interface M3 {{{ m3_aclk : in std_logic; m3_aresetn : in std_logic; m3_awid : out std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_awaddr : out std_logic_vector(C_M3_ADDR_WIDTH-1 downto 0); m3_awlen : out std_logic_vector(7 downto 0); m3_awsize : out std_logic_vector(2 downto 0); m3_awburst : out std_logic_vector(1 downto 0); m3_awlock : out std_logic; m3_awcache : out std_logic_vector(3 downto 0); m3_awprot : out std_logic_vector(2 downto 0); m3_awqos : out std_logic_vector(3 downto 0); m3_awuser : out std_logic_vector(C_M3_AWUSER_WIDTH-1 downto 0); m3_awvalid : out std_logic; m3_awready : in std_logic; m3_wdata : out std_logic_vector(C_M3_DATA_WIDTH-1 downto 0); m3_wstrb : out std_logic_vector(C_M3_DATA_WIDTH/8-1 downto 0); m3_wlast : out std_logic; m3_wuser : out std_logic_vector(C_M3_WUSER_WIDTH-1 downto 0); m3_wvalid : out std_logic; m3_wready : in std_logic; m3_bid : in std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_bresp : in std_logic_vector(1 downto 0); m3_buser : in std_logic_vector(C_M3_BUSER_WIDTH-1 downto 0); m3_bvalid : in std_logic; m3_bready : out std_logic; m3_arid : out std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_araddr : out std_logic_vector(C_M3_ADDR_WIDTH-1 downto 0); m3_arlen : out std_logic_vector(7 downto 0); m3_arsize : out std_logic_vector(2 downto 0); m3_arburst : out std_logic_vector(1 downto 0); m3_arlock : out std_logic; m3_arcache : out std_logic_vector(3 downto 0); m3_arprot : out std_logic_vector(2 downto 0); m3_arqos : out std_logic_vector(3 downto 0); m3_aruser : out std_logic_vector(C_M3_ARUSER_WIDTH-1 downto 0); m3_arvalid : out std_logic; m3_arready : in std_logic; m3_rid : in std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_rdata : in std_logic_vector(C_M3_DATA_WIDTH-1 downto 0); m3_rresp : in std_logic_vector(1 downto 0); m3_rlast : in std_logic; m3_ruser : in std_logic_vector(C_M3_RUSER_WIDTH-1 downto 0); m3_rvalid : in std_logic; m3_rready : out std_logic -- }}} ); --}}} end entity; architecture arch_imp of FGPU_v3_0 is signal nrst : std_logic := '0'; begin -- fixed signals ------------------------------------------------------------------------------------{{{ -- m0 {{{ m0_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m0_awcache <= "0010"; m0_awprot <= "000"; m0_awqos <= X"0"; m0_arlock <= '0'; m0_arcache <= "0010"; m0_arprot <= "000"; m0_arqos <= X"0"; -- }}} -- m1 {{{ m1_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m1_awcache <= "0010"; m1_awprot <= "000"; m1_awqos <= X"0"; m1_arlock <= '0'; m1_arcache <= "0010"; m1_arprot <= "000"; m1_arqos <= X"0"; --}}} -- m2 {{{ m2_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m2_awcache <= "0010"; m2_awprot <= "000"; m2_awqos <= X"0"; m2_arlock <= '0'; m2_arcache <= "0010"; m2_arprot <= "000"; m2_arqos <= X"0"; -- }}} -- m3 {{{ m3_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m3_awcache <= "0010"; m3_awprot <= "000"; m3_awqos <= X"0"; m3_arlock <= '0'; m3_arcache <= "0010"; m3_arprot <= "000"; m3_arqos <= X"0"; -- }}} ---------------------------------------------------------------------------------------------------------}}} process(s0_aclk) begin if rising_edge(s0_aclk) then nrst <= s0_aresetn and m0_aresetn and m1_aresetn and m2_aresetn and m3_aresetn; end if; end process; uut: entity FGPU PORT MAP ( clk => s0_aclk, -- slave axi {{{ s0_awaddr => s0_awaddr(C_S0_ADDR_WIDTH-1 downto 2), s0_awprot => s0_awprot, s0_awvalid => s0_awvalid, s0_awready => s0_awready, s0_wdata => s0_wdata, s0_wstrb => s0_wstrb, s0_wvalid => s0_wvalid, s0_wready => s0_wready, s0_bresp => s0_bresp, s0_bvalid => s0_bvalid, s0_bready => s0_bready, s0_araddr => s0_araddr(C_S0_ADDR_WIDTH-1 downto 2), s0_arprot => s0_arprot, s0_arvalid => s0_arvalid, s0_arready => s0_arready, s0_rdata => s0_rdata, s0_rresp => s0_rresp, s0_rvalid => s0_rvalid, s0_rready => s0_rready, -- }}} -- axi master 0 connections {{{ -- ar channel m0_araddr => m0_araddr, m0_arlen => m0_arlen, m0_arsize => m0_arsize, m0_arburst => m0_arburst, m0_arvalid => m0_arvalid, m0_arready => m0_arready, m0_arid => m0_arid, -- r channel m0_rdata => m0_rdata, m0_rresp => m0_rresp, m0_rlast => m0_rlast, m0_rvalid => m0_rvalid, m0_rready => m0_rready, m0_rid => m0_rid, -- aw channel m0_awvalid => m0_awvalid, m0_awaddr => m0_awaddr, m0_awready => m0_awready, m0_awlen => m0_awlen, m0_awsize => m0_awsize, m0_awburst => m0_awburst, m0_awid => m0_awid, -- w channel m0_wdata => m0_wdata, m0_wstrb => m0_wstrb, m0_wlast => m0_wlast, m0_wvalid => m0_wvalid, m0_wready => m0_wready, -- b channel m0_bvalid => m0_bvalid, m0_bready => m0_bready, m0_bid => m0_bid, -- }}} -- axi master 1 connections {{{ -- ar channel m1_araddr => m2_araddr, m1_arlen => m2_arlen, m1_arsize => m2_arsize, m1_arburst => m2_arburst, m1_arvalid => m2_arvalid, m1_arready => m2_arready, m1_arid => m2_arid, -- r channel m1_rdata => m2_rdata, m1_rresp => m2_rresp, m1_rlast => m2_rlast, m1_rvalid => m2_rvalid, m1_rready => m2_rready, m1_rid => m2_rid, -- aw channel m1_awvalid => m2_awvalid, m1_awaddr => m2_awaddr, m1_awready => m2_awready, m1_awlen => m2_awlen, m1_awsize => m2_awsize, m1_awburst => m2_awburst, m1_awid => m2_awid, -- w channel m1_wdata => m2_wdata, m1_wstrb => m2_wstrb, m1_wlast => m2_wlast, m1_wvalid => m2_wvalid, m1_wready => m2_wready, -- b channel m1_bvalid => m2_bvalid, m1_bready => m2_bready, m1_bid => m2_bid, -- }}} -- axi master 2 connections {{{ -- ar channel m2_araddr => m1_araddr, m2_arlen => m1_arlen, m2_arsize => m1_arsize, m2_arburst => m1_arburst, m2_arvalid => m1_arvalid, m2_arready => m1_arready, m2_arid => m1_arid, -- r channel m2_rdata => m1_rdata, m2_rresp => m1_rresp, m2_rlast => m1_rlast, m2_rvalid => m1_rvalid, m2_rready => m1_rready, m2_rid => m1_rid, -- aw channel m2_awvalid => m1_awvalid, m2_awaddr => m1_awaddr, m2_awready => m1_awready, m2_awlen => m1_awlen, m2_awsize => m1_awsize, m2_awburst => m1_awburst, m2_awid => m1_awid, -- w channel m2_wdata => m1_wdata, m2_wstrb => m1_wstrb, m2_wlast => m1_wlast, m2_wvalid => m1_wvalid, m2_wready => m1_wready, -- b channel m2_bvalid => m1_bvalid, m2_bready => m1_bready, m2_bid => m1_bid, -- }}} -- axi master 3 connections {{{ -- ar channel m3_araddr => m3_araddr, m3_arlen => m3_arlen, m3_arsize => m3_arsize, m3_arburst => m3_arburst, m3_arvalid => m3_arvalid, m3_arready => m3_arready, m3_arid => m3_arid, -- r channel m3_rdata => m3_rdata, m3_rresp => m3_rresp, m3_rlast => m3_rlast, m3_rvalid => m3_rvalid, m3_rready => m3_rready, m3_rid => m3_rid, -- aw channel m3_awvalid => m3_awvalid, m3_awaddr => m3_awaddr, m3_awready => m3_awready, m3_awlen => m3_awlen, m3_awsize => m3_awsize, m3_awburst => m3_awburst, m3_awid => m3_awid, -- w channel m3_wdata => m3_wdata, m3_wstrb => m3_wstrb, m3_wlast => m3_wlast, m3_wvalid => m3_wvalid, m3_wready => m3_wready, -- b channel m3_bvalid => m3_bvalid, m3_bready => m3_bready, m3_bid => m3_bid, -- }}} nrst => nrst ); end arch_imp;

gpl-3.0

12011149724dabcbd521e691716af0fe

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

d1de789a7ff07a9f15c7434e52b04e83

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_user_logic_subtractor.vhd

-- File: dyplo_user_logic_stub.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_signed.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; entity dyplo_user_logic_subtractor is generic( INPUT_STREAMS : integer := 4; OUTPUT_STREAMS : integer := 4 ); port( -- Processor bus interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(15 DOWNTO 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Streaming input interfaces cin_tdata : in cin_tdata_ul_type; cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tlevel : in cin_tlevel_ul_type; -- Streaming output interfaces cout_tdata : out cout_tdata_ul_type; cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0); cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); end dyplo_user_logic_subtractor; architecture rtl of dyplo_user_logic_subtractor is type signed_matrix_4x32 is array (0 to INPUT_STREAMS - 1) of signed(31 downto 0); signal value_to_subtract : signed_matrix_4x32; signal cin_tdata_i : signed_matrix_4x32; signal cout_tdata_i : signed_matrix_4x32; begin config_reg : process (dab_clk) variable index : integer; begin if rising_edge(dab_clk) then if (dab_rst = '1') then value_to_subtract <= (others => (others => '0')); else index := to_integer(unsigned(dab_addr(3 downto 2))); if (dab_sel = '1') and (dab_wvalid = '1') then value_to_subtract(index) <= signed(dab_wdata); end if; dab_rdata <= std_logic_vector(value_to_subtract(index)); end if; end if; end process config_reg; subtractors : for i in 0 to 3 generate type sm_calc_states is (S_FETCH, S_CALC, S_SEND, S_FINISH); signal sm_calc : sm_calc_states; signal tdata : signed(31 downto 0); begin calc_data : process (dab_clk) begin if rising_edge(dab_clk) then if (dab_rst = '1') then cout_tdata_i(i) <= (others => '0'); cout_tvalid(i) <= '0'; cin_tready(i) <= '0'; sm_calc <= S_FETCH; tdata <= (others => '0'); else case sm_calc is when S_FETCH => if (cin_tvalid(i) = '1') and (conv_integer(cin_tlevel(i)) /= 0) then cin_tready(i) <= '1'; tdata <= to_signed(conv_integer(cin_tdata(i)),32); sm_calc <= S_CALC; end if; when S_CALC => cin_tready(i) <= '0'; cout_tdata_i(i) <= tdata - value_to_subtract(i); cout_tvalid(i) <= '1'; sm_calc <= S_SEND; when S_SEND => if (cout_tready(i) = '1') then cout_tvalid(i) <= '0'; sm_calc <= S_FINISH; end if; when S_FINISH => sm_calc <= S_FETCH; end case; end if; end if; end process calc_data; end generate subtractors; cout_tdata(0) <= std_logic_vector(cout_tdata_i(0)); cout_tdata(1) <= std_logic_vector(cout_tdata_i(1)); cout_tdata(2) <= std_logic_vector(cout_tdata_i(2)); cout_tdata(3) <= std_logic_vector(cout_tdata_i(3)); end rtl;

gpl-2.0

da5d5018bcb1b096876f16026fd5adf5

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fdiv_fsqrt_8_2_2_2.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

b8122fbdc6d8aa7067a187ce6ea09c9d

kennethlyn/fpga-image-example

hdl_nodes/adder_2_to_1/adder_2_to_1.srcs/sources_1/dyplo_hdl_node_user_params.vhd

-- File: dyplo_hdl_node_user_params.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package hdl_node_user_params is constant c_vendor_id : integer range 0 to 255 := 1; constant c_product_id : integer range 0 to 255 := 4; constant c_version_id : integer range 0 to 255 := 1; constant c_revision_id : integer range 0 to 255 := 1; constant c_input_streams : integer range 0 to 4 := 2; constant c_hdl_in_fifo_depth : integer range 7 to 12 := 8; -- specify power of 2. FIFO size = 2^x. 7 = 128, 12 = 4096 constant c_hdl_in_fifo_type : string := "DISTRIBUTED"; constant c_output_streams : integer range 0 to 4 := 1; end hdl_node_user_params;

gpl-2.0

7c5846f03cee67c83993e271c339d561

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_fadd_fslt_max.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

bb5dee530315fea9c16824c204ee177c

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_SubInteger_6ALUs.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a213b4286eae0df5cd0131bbf343d847

joalcava/sparcv8-monocicle

Test_Instructionmemory.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Test_instructionMemory IS END Test_instructionMemory; ARCHITECTURE behavior OF Test_instructionMemory IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT instructionMemory PORT( address : IN std_logic_vector(3 downto 0); reset : IN std_logic; clkFPGA : IN std_logic; outInstruction : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal address : std_logic_vector(3 downto 0) := (others => '0'); signal reset : std_logic := '0'; signal clkFPGA : std_logic := '0'; --Outputs signal outInstruction : std_logic_vector(31 downto 0); -- Clock period definitions constant clkFPGA_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: instructionMemory PORT MAP ( address => address, reset => reset, clkFPGA => clkFPGA, outInstruction => outInstruction ); -- Clock process definitions clkFPGA_process :process begin clkFPGA <= '0'; wait for clkFPGA_period/2; clkFPGA <= '1'; wait for clkFPGA_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. reset<='1'; address <= "0000"; wait for 100 ns; reset<='0'; address <= "1110"; wait; end process; END;

gpl-3.0

f5a70dde47e3dc4583011188a4233d48

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_min.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

06161b0c3fa62827ca1649af44fcd31e

preusser/q27

src/vhdl/queens/xilinx/arbit_forward.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <[email protected]> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity arbit_forward is generic ( N : positive -- Length of Token Chain ); port ( tin : in std_logic; -- Fed Token have : in std_logic_vector(0 to N-1); -- Token Owner pass : in std_logic_vector(0 to N-1); -- Token Passers grnt : out std_logic_vector(0 to N-1); -- Token Output tout : out std_logic -- Unused Token ); end arbit_forward; library UNISIM; use UNISIM.vcomponents.all; architecture rtl_xilinx of arbit_forward is -- Intermediate Token Signals signal q : std_logic_vector(0 to N); begin -- First MUXCY only with switching LUT q(0) <= have(0) or (tin and pass(0)); MUXCY_inst : MUXCY port map ( O => q(1), CI => '1', DI => '0', S => q(0) ); grnt(0) <= tin and not q(1); genChain : for i in 1 to N-1 generate MUXCY_inst : MUXCY port map ( O => q(i+1), CI => q(i), DI => have(i), S => pass(i) ); grnt(i) <= q(i) and not q(i+1); end generate; tout <= q(N); end rtl_xilinx;

agpl-3.0

673ee4085a197963589cb4ef20dc87bd

wltr/cern-fgclite

critical_fpga/src/rtl/cf/pf.vhd

------------------------------------------------------------------------------- --! @file pf.vhd --! @author Johannes Walter <[email protected]> --! @copyright CERN TE-EPC-CCE --! @date 2015-01-19 --! @brief Power FPGA communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --! @brief Entity declaration of pf --! @details --! This component handles the Power FPGA communication and takes action in --! case field-bus communication is broken. entity pf is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name PF interface --! @{ --! Send power cycle request to PF pf_req_n_o : out std_ulogic; --! Enable power down on PF pf_pwr_dwn_en_o : out std_ulogic; --! Power down signal from PF pf_pwr_dwn_i : in std_ulogic; --! @} --! @name Internal interface --! @{ --! Start of cycle ms_0_strobe_i : in std_ulogic; --! Millisecond strobe ms_9_strobe_i : in std_ulogic; --! Millisecond strobe ms_11_strobe_i : in std_ulogic; --! Voltage reference input v_ref_i : in std_ulogic_vector(15 downto 0); --! Voltage reference output v_ref_o : out std_ulogic_vector(15 downto 0); --! Voltage reference output enable v_ref_en_o : out std_ulogic; --! Flag indicating voltage reference override v_ref_override_o : out std_ulogic; --! Backplane type backplane_i : in std_ulogic_vector(7 downto 0); --! Flags indicating which commands have been received command_received_i : in std_ulogic_vector(3 downto 0)); --! @} end entity pf; --! RTL implementation of pf architecture rtl of pf is --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal pf_req_n : std_ulogic; signal pf_pwr_dwn_en : std_ulogic; signal pwr_cyc_chk : std_ulogic_vector(1 downto 0); signal v_ref : unsigned(15 downto 0); signal v_ref_en : std_ulogic; signal v_ref_ovr : std_ulogic; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal rmp_dwn_strb_rst : std_ulogic; signal rmp_dwn_strb_en : std_ulogic; signal rmp_dwn_strb : std_ulogic; signal pf_pwr_dwn_redge : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- pf_req_n_o <= pf_req_n; pf_pwr_dwn_en_o <= pf_pwr_dwn_en; v_ref_o <= std_ulogic_vector(v_ref); v_ref_en_o <= v_ref_en; v_ref_override_o <= v_ref_ovr; --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- rmp_dwn_strb_rst <= not rmp_dwn_strb_en; rmp_dwn_strb_en <= v_ref_ovr; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- strobe_inst : entity work.lfsr_strobe_generator generic map ( period_g => 3051, -- 3051 * 25 ns = 76.275 us preset_value_g => 0) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => rmp_dwn_strb_en, pre_i => rmp_dwn_strb_rst, strobe_o => rmp_dwn_strb); pwr_dwn_edge_inst : entity work.edge_detector port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, en_i => '1', ack_i => '1', sig_i => pf_pwr_dwn_i, edge_o => pf_pwr_dwn_redge); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin pf_req_n <= '1'; pf_pwr_dwn_en <= '0'; pwr_cyc_chk <= "00"; v_ref <= to_unsigned(0, v_ref'length); v_ref_en <= '0'; v_ref_ovr <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else if ms_0_strobe_i = '1' then if command_received_i = "0000" then pwr_cyc_chk <= pwr_cyc_chk(0) & '1'; else pwr_cyc_chk <= "00"; pf_pwr_dwn_en <= '1'; end if; end if; if ms_9_strobe_i = '1' and pwr_cyc_chk(1) = '1' then pf_req_n <= '0'; elsif ms_11_strobe_i = '1' then if pf_req_n = '0' then pf_pwr_dwn_en <= '0'; end if; pf_req_n <= '1'; end if; if pf_pwr_dwn_redge = '1' and pwr_cyc_chk(1) = '1' then v_ref <= unsigned(v_ref_i); v_ref_ovr <= '1'; end if; v_ref_en <= '0'; if v_ref_ovr = '1' and rmp_dwn_strb = '1' then if to_integer(v_ref) > 0 then v_ref <= v_ref - 1; v_ref_en <= '1'; end if; end if; -- Don't do anything when backplane type is x00 if backplane_i = x"00" then reset; end if; end if; end if; end process regs; end architecture rtl;

mit

3eb20a1952d3c950c8a4974770184b44

wltr/cern-fgclite

nanofip_fpga/src/rtl/var2_rx.vhd

------------------------------------------------------------------------------- --! @file var2_rx.vhd --! @author Johannes Walter <[email protected]> --! @copyright CERN TE-EPC-CCE --! @date 2013-10-24 --! @brief NanoFIP VAR2 data receiver. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; --! @brief Entity declaration of var2_rx --! @details --! Whenever VAR2 data is received from the NanoFIP field-bus, this component --! ensures correct handling of the address space within the NanoFIP core. --! Each FGClite receives 4 bytes of data according to its station ID. entity var2_rx is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name FGClite interface --! @{ --! The FGClite station ID station_id_i : in std_ulogic_vector(4 downto 0); --! Signal reception of FGClite command 0 cmd_0_o : out std_ulogic; --! @} --! @name Receiver interface --! @{ --! Data is ready to be received rx_rdy_i : in std_ulogic; --! Read address rx_addr_o : out std_ulogic_vector(6 downto 0); --! Read enable rx_en_o : out std_ulogic; --! Read data input rx_data_i : in std_ulogic_vector(7 downto 0); --! Read data input enable rx_data_en_i : in std_ulogic; --! @} --! @name VAR2 interface --! @{ --! Received data for serial transmission tx_data_o : out std_ulogic_vector(39 downto 0); --! Received data enable tx_data_en_o : out std_ulogic; --! Transmitter busy tx_bsy_i : in std_ulogic; --! @} --! @name Error flags --! @{ --! Read-write collision err_rw_coll_i : in std_ulogic; --! Interface busy err_bsy_i : in std_ulogic; --! VAR not ready err_not_rdy_i : in std_ulogic; --! Wishbone bus acknowledge timeout err_timeout_i : in std_ulogic); --! @} end entity var2_rx; --! RTL implementation of var2_rx architecture rtl of var2_rx is --------------------------------------------------------------------------- -- Types and Constants --------------------------------------------------------------------------- --! Base address for data payload constant base_addr_c : natural := 2; --! Number of payload bytes for VAR2 constant num_data_c : positive := 4; --! Data array type data_t is array (0 to num_data_c - 1) of std_ulogic_vector(7 downto 0); --! FSM states type state_t is (IDLE, REQ_CMD, STORE_CMD, REQ_DATA, STORE_DATA, SEND, INIT); --! FSM registers type reg_t is record state : state_t; wb_addr : unsigned(6 downto 0); wb_en : std_ulogic; num : unsigned(integer(ceil(log2(real(num_data_c)))) - 1 downto 0); cmd : std_ulogic_vector(7 downto 0); data : data_t; data_en : std_ulogic; cmd_0 : std_ulogic; end record reg_t; --! FSM initial state constant init_c : reg_t := ( state => IDLE, wb_addr => to_unsigned(base_addr_c, 7), wb_en => '0', num => (others => '0'), cmd => (others => '0'), data => (others => (others => '0')), data_en => '0', cmd_0 => '0'); --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg : reg_t; signal wb_if_err : std_ulogic; signal data_addr : unsigned(6 downto 0); --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- rx_addr_o <= std_ulogic_vector(reg.wb_addr); rx_en_o <= reg.wb_en; tx_data_o <= reg.cmd & reg.data(3) & reg.data(2) & reg.data(1) & reg.data(0); tx_data_en_o <= reg.data_en; cmd_0_o <= reg.cmd_0; --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- -- Combine errors into one signal wb_if_err <= err_rw_coll_i or err_not_rdy_i or err_timeout_i or err_bsy_i; -- Calculate memory address based on station ID data_addr <= resize(base_addr_c + (unsigned(station_id_i) * num_data_c), data_addr'length); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, rx_rdy_i, rx_data_i, rx_data_en_i, wb_if_err, data_addr, tx_bsy_i) is begin -- process comb -- Defaults next_reg <= reg; next_reg.wb_en <= '0'; next_reg.data_en <= '0'; case reg.state is when IDLE => if rx_rdy_i = '1' then next_reg.state <= REQ_CMD; end if; when REQ_CMD => next_reg.wb_addr <= to_unsigned(base_addr_c, reg.wb_addr'length); next_reg.wb_en <= '1'; next_reg.state <= STORE_CMD; when STORE_CMD => if rx_data_en_i = '1' then next_reg.cmd <= rx_data_i; if rx_data_i = x"00" then next_reg.cmd_0 <= '1'; end if; next_reg.state <= REQ_DATA; end if; when REQ_DATA => next_reg.wb_addr <= data_addr + reg.num; next_reg.wb_en <= '1'; next_reg.state <= STORE_DATA; when STORE_DATA => if rx_data_en_i = '1' then next_reg.data(to_integer(reg.num)) <= rx_data_i; if to_integer(reg.num) < num_data_c - 1 then next_reg.num <= reg.num + 1; next_reg.state <= REQ_DATA; else next_reg.state <= SEND; end if; end if; when SEND => if tx_bsy_i = '0' then next_reg.data_en <= '1'; next_reg.state <= INIT; end if; when INIT => next_reg <= init_c; end case; -- Reset on error if wb_if_err = '1' then next_reg <= init_c; end if; end process comb; end architecture rtl;

mit

329f43ef331bfff61c668d1d823eaad9

preusser/q27

src/vhdl/queens/enframe.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <[email protected]> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity enframe is generic ( SENTINEL : std_logic_vector(7 downto 0) -- Start Byte ); port ( clk : in std_logic; rst : in std_logic; idat : in std_logic_vector(7 downto 0); ieof : in std_logic; ivld : in std_logic; igot : out std_logic; tx_ful : in std_logic; tx_put : out std_logic; tx_dat : out std_logic_vector(7 downto 0) ); end enframe; library IEEE; use IEEE.numeric_std.all; architecture rtl of enframe is -- CRC Table for 0x1D5 (CRC-8) type tFCS is array(0 to 255) of std_logic_vector(7 downto 0); constant FCS : tFCS := ( x"00", x"D5", x"7F", x"AA", x"FE", x"2B", x"81", x"54", x"29", x"FC", x"56", x"83", x"D7", x"02", x"A8", x"7D", x"52", x"87", x"2D", x"F8", x"AC", x"79", x"D3", x"06", x"7B", x"AE", x"04", x"D1", x"85", x"50", x"FA", x"2F", x"A4", x"71", x"DB", x"0E", x"5A", x"8F", x"25", x"F0", x"8D", x"58", x"F2", x"27", x"73", x"A6", x"0C", x"D9", x"F6", x"23", x"89", x"5C", x"08", x"DD", x"77", x"A2", x"DF", x"0A", x"A0", x"75", x"21", x"F4", x"5E", x"8B", x"9D", x"48", x"E2", x"37", x"63", x"B6", x"1C", x"C9", x"B4", x"61", x"CB", x"1E", x"4A", x"9F", x"35", x"E0", x"CF", x"1A", x"B0", x"65", x"31", x"E4", x"4E", x"9B", x"E6", x"33", x"99", x"4C", x"18", x"CD", x"67", x"B2", x"39", x"EC", x"46", x"93", x"C7", x"12", x"B8", x"6D", x"10", x"C5", x"6F", x"BA", x"EE", x"3B", x"91", x"44", x"6B", x"BE", x"14", x"C1", x"95", x"40", x"EA", x"3F", x"42", x"97", x"3D", x"E8", x"BC", x"69", x"C3", x"16", x"EF", x"3A", x"90", x"45", x"11", x"C4", x"6E", x"BB", x"C6", x"13", x"B9", x"6C", x"38", x"ED", x"47", x"92", x"BD", x"68", x"C2", x"17", x"43", x"96", x"3C", x"E9", x"94", x"41", x"EB", x"3E", x"6A", x"BF", x"15", x"C0", x"4B", x"9E", x"34", x"E1", x"B5", x"60", x"CA", x"1F", x"62", x"B7", x"1D", x"C8", x"9C", x"49", x"E3", x"36", x"19", x"CC", x"66", x"B3", x"E7", x"32", x"98", x"4D", x"30", x"E5", x"4F", x"9A", x"CE", x"1B", x"B1", x"64", x"72", x"A7", x"0D", x"D8", x"8C", x"59", x"F3", x"26", x"5B", x"8E", x"24", x"F1", x"A5", x"70", x"DA", x"0F", x"20", x"F5", x"5F", x"8A", x"DE", x"0B", x"A1", x"74", x"09", x"DC", x"76", x"A3", x"F7", x"22", x"88", x"5D", x"D6", x"03", x"A9", x"7C", x"28", x"FD", x"57", x"82", x"FF", x"2A", x"80", x"55", x"01", x"D4", x"7E", x"AB", x"84", x"51", x"FB", x"2E", x"7A", x"AF", x"05", x"D0", x"AD", x"78", x"D2", x"07", x"53", x"86", x"2C", x"F9" ); -- State Machine type tState is (Idle, Transmit, WriteCRC); signal State : tState := Idle; signal NextState : tState; signal CRC : std_logic_vector(7 downto 0) := (others => '-'); signal InitCRC : std_logic; signal UpdateCRC : std_logic; begin -- State process(clk) begin if rising_edge(clk) then if rst = '1' then State <= Idle; CRC <= (others => '-'); else State <= NextState; if InitCRC = '1' then CRC <= FCS(255); elsif UpdateCRC = '1' then CRC <= FCS(to_integer(unsigned(CRC xor idat))); end if; end if; end if; end process; process(State, tx_ful, ivld, ieof, idat, CRC) begin NextState <= State; InitCRC <= '0'; UpdateCRC <= '0'; tx_dat <= (others => '-'); tx_put <= '0'; igot <= '0'; if tx_ful = '0' then case State is when Idle => if ivld = '1' then InitCRC <= '1'; tx_dat <= SENTINEL; tx_put <= '1'; NextState <= Transmit; end if; when Transmit => if ivld = '1' then UpdateCRC <= '1'; tx_dat <= idat; tx_put <= '1'; igot <= '1'; if ieof = '1' then NextState <= WriteCRC; end if; end if; when WriteCRC => tx_dat <= CRC; tx_put <= '1'; NextState <= Idle; end case; end if; end process; end rtl;

agpl-3.0

67d3ce827b42b83fbc672cfa30bb22e8

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fsqrt_uitofp_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 3; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

8c3129e1083bf6af66588a8383503204

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_2Banks.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 1; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 1; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

dd77b113e04153da1854d10cc990b66b

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd

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4bNb1gO/SKIQj2hS `protect end_protected

mit

cb4b3e159a7400c2dd5ca33d7a1c0994

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM_2_CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

e62a978e767ad8d7a521a9fa3ae71371

malkadi/FGPU

RTL/RTM.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity RTM is -- ports {{{ port( clk : in std_logic; rtm_rdAddr : in unsigned(RTM_ADDR_W-1 downto 0); -- level 13. rtm_rdData : out unsigned(RTM_DATA_W-1 downto 0) := (others=> '0'); -- level 15. rtm_wrData_cv : in unsigned(DATA_W-1 downto 0) := (others => '0'); rtm_wrAddr_cv : in unsigned(N_WF_CU_W+2-1 downto 0) := (others => '0'); rtm_we_cv : in std_logic := '0'; rtm_wrAddr_wg : in unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); rtm_wrData_wg : in unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); -- from _wg_dispatcher rtm_we_wg : in std_logic; WGsDispatched : in std_logic; start_CUs : in std_logic; nrst : in std_logic ); -- }}} end RTM; architecture Behavioral of RTM is -- signals definitions {{{ signal rtm : rtm_ram_type(0 to RTM_SIZE-1) := (others => (others => '0')); signal rtm_wrData, rtm_wrData_n : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); signal rtm_rdData_n : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); signal rtm_wrAddr, rtm_wrAddr_n : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); signal rtm_we, rtm_we_n : std_logic := '0'; type st_rtm_write_type is (wg_dispatcher, cv_Dispatcher); signal st_rtm_write : st_rtm_write_type := wg_dispatcher; signal st_rtm_write_n : st_rtm_write_type := wg_dispatcher; -- }}} begin -- Local Memory -------------------------------------------------------------------------------------------{{{ ---------------------------------------------------------------------------------------------------------}}} -- RTM ram ------------------------------------------------------------------------------------ {{{ process(clk) begin if rising_edge(clk) then if rtm_we = '1' then rtm(to_integer(rtm_wrAddr)) <= rtm_wrData; end if; rtm_rdData_n <= rtm(to_integer(rtm_rdAddr)); -- @ 14. rtm_rdData <= rtm_rdData_n; -- @ 15. end if; end process; process(clk) begin if rising_edge(clk) then rtm_wrData <= rtm_wrData_n; rtm_wrAddr <= rtm_wrAddr_n; if nrst = '0' then st_rtm_write <= wg_dispatcher; rtm_we <= '0'; else st_rtm_write <= st_rtm_write_n; rtm_we <= rtm_we_n; end if; end if; end process; process(st_rtm_write, start_CUs, WGsDispatched, rtm_wrAddr_cv, rtm_wrAddr_wg, rtm_wrData_cv, rtm_wrData_wg, rtm_we_cv, rtm_we_wg, rtm_wrData, rtm_wrAddr, rtm_we) begin st_rtm_write_n <= st_rtm_write; rtm_wrAddr_n <= rtm_wrAddr; rtm_wrData_n <= rtm_wrData; rtm_we_n <= rtm_we; case st_rtm_write is when wg_dispatcher => if start_CUs = '1' then st_rtm_write_n <= cv_Dispatcher; end if; rtm_wrAddr_n <= rtm_wrAddr_wg; rtm_wrData_n <= rtm_wrData_wg; rtm_we_n <= rtm_we_wg; when cv_Dispatcher => if WGsDispatched = '1' then st_rtm_write_n <= wg_dispatcher; end if; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto PHASE_W) <= rtm_wrAddr_cv; rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= rtm_wrData_cv; rtm_we_n <= rtm_we_cv; end case; end process; ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

f2c9550fe2bae5d2270ff44660f3ff33

malkadi/FGPU

RTL/FGPU.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ------------------------------------------------------------------------------------------------- }}} entity FGPU is -- Generics & ports {{{ port( clk : in std_logic; -- Contorl Interface - AXI LITE SLAVE {{{ s0_awaddr : in std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0); s0_awprot : in std_logic_vector(2 downto 0); s0_awvalid : in std_logic; s0_awready : out std_logic := '0'; s0_wdata : in std_logic_vector(DATA_W-1 downto 0); s0_wstrb : in std_logic_vector((DATA_W/8)-1 downto 0); s0_wvalid : in std_logic; s0_wready : out std_logic := '0'; s0_bresp : out std_logic_vector(1 downto 0) := (others=>'0'); s0_bvalid : out std_logic := '0'; s0_bready : in std_logic; s0_araddr : in std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0); s0_arprot : in std_logic_vector(2 downto 0); s0_arvalid : in std_logic; s0_arready : out std_logic := '0'; s0_rdata : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); s0_rresp : out std_logic_vector(1 downto 0) := (others=>'0'); s0_rvalid : out std_logic := '0'; s0_rready : in std_logic; -- }}} -- AXI MASTER 0 {{{ -- ar channel m0_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); m0_arlen : out std_logic_vector(7 downto 0):= (others=>'0'); m0_arsize : out std_logic_vector(2 downto 0):= (others=>'0'); m0_arburst : out std_logic_vector(1 downto 0):= (others=>'0'); m0_arvalid : out std_logic := '0'; m0_arready : in std_logic; m0_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel m0_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); m0_rresp : in std_logic_vector(1 downto 0):= (others=>'0'); m0_rlast : in std_logic; m0_rvalid : in std_logic; m0_rready : out std_logic := '0'; m0_rid : in std_logic_vector(ID_WIDTH-1 downto 0); -- aw channel m0_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); m0_awvalid : out std_logic := '0'; m0_awready : in std_logic; m0_awlen : out std_logic_vector(7 downto 0):= (others=>'0'); m0_awsize : out std_logic_vector(2 downto 0):= (others=>'0'); m0_awburst : out std_logic_vector(1 downto 0):= (others=>'0'); m0_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel m0_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); m0_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); m0_wlast : out std_logic := '0'; m0_wvalid : out std_logic := '0'; m0_wready : in std_logic; -- b channel m0_bvalid : in std_logic; m0_bready : out std_logic := '0'; m0_bid : in std_logic_vector(ID_WIDTH-1 downto 0); -- }}}} -- AXI MASTER 1 {{{ -- ar channel m1_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); m1_arlen : out std_logic_vector(7 downto 0):= (others=>'0'); m1_arsize : out std_logic_vector(2 downto 0):= (others=>'0'); m1_arburst : out std_logic_vector(1 downto 0):= (others=>'0'); m1_arvalid : out std_logic := '0'; m1_arready : in std_logic; m1_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel m1_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); m1_rresp : in std_logic_vector(1 downto 0):= (others=>'0'); m1_rlast : in std_logic; m1_rvalid : in std_logic; m1_rready : out std_logic := '0'; m1_rid : in std_logic_vector(ID_WIDTH-1 downto 0); -- -- aw channel m1_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); m1_awvalid : out std_logic := '0'; m1_awready : in std_logic; m1_awlen : out std_logic_vector(7 downto 0):= (others=>'0'); m1_awsize : out std_logic_vector(2 downto 0):= (others=>'0'); m1_awburst : out std_logic_vector(1 downto 0):= (others=>'0'); m1_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel m1_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); m1_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); m1_wlast : out std_logic := '0'; m1_wvalid : out std_logic := '0'; m1_wready : in std_logic; -- b channel m1_bvalid : in std_logic; m1_bready : out std_logic := '0'; m1_bid : in std_logic_vector(ID_WIDTH-1 downto 0); -- }}}} -- AXI MASTER 2 {{{ -- ar channel m2_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); m2_arlen : out std_logic_vector(7 downto 0):= (others=>'0'); m2_arsize : out std_logic_vector(2 downto 0):= (others=>'0'); m2_arburst : out std_logic_vector(1 downto 0):= (others=>'0'); m2_arvalid : out std_logic := '0'; m2_arready : in std_logic; m2_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel m2_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); m2_rresp : in std_logic_vector(1 downto 0):= (others=>'0'); m2_rlast : in std_logic; m2_rvalid : in std_logic; m2_rready : out std_logic := '0'; m2_rid : in std_logic_vector(ID_WIDTH-1 downto 0); -- -- aw channel m2_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); m2_awvalid : out std_logic := '0'; m2_awready : in std_logic; m2_awlen : out std_logic_vector(7 downto 0):= (others=>'0'); m2_awsize : out std_logic_vector(2 downto 0):= (others=>'0'); m2_awburst : out std_logic_vector(1 downto 0):= (others=>'0'); m2_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel m2_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); m2_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); m2_wlast : out std_logic := '0'; m2_wvalid : out std_logic := '0'; m2_wready : in std_logic; -- b channel m2_bvalid : in std_logic; m2_bready : out std_logic := '0'; m2_bid : in std_logic_vector(ID_WIDTH-1 downto 0); -- }}}} -- AXI MASTER 3 {{{ -- ar channel m3_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0'); m3_arlen : out std_logic_vector(7 downto 0):= (others=>'0'); m3_arsize : out std_logic_vector(2 downto 0):= (others=>'0'); m3_arburst : out std_logic_vector(1 downto 0):= (others=>'0'); m3_arvalid : out std_logic := '0'; m3_arready : in std_logic; m3_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- r channel m3_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0'); m3_rresp : in std_logic_vector(1 downto 0):= (others=>'0'); m3_rlast : in std_logic; m3_rvalid : in std_logic; m3_rready : out std_logic := '0'; m3_rid : in std_logic_vector(ID_WIDTH-1 downto 0); -- -- aw channel m3_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); m3_awvalid : out std_logic := '0'; m3_awready : in std_logic; m3_awlen : out std_logic_vector(7 downto 0):= (others=>'0'); m3_awsize : out std_logic_vector(2 downto 0):= (others=>'0'); m3_awburst : out std_logic_vector(1 downto 0):= (others=>'0'); m3_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0'); -- w channel m3_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0'); m3_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0'); m3_wlast : out std_logic := '0'; m3_wvalid : out std_logic := '0'; m3_wready : in std_logic; -- b channel m3_bvalid : in std_logic; m3_bready : out std_logic := '0'; m3_bid : in std_logic_vector(ID_WIDTH-1 downto 0); -- }}}} nrst : in std_logic ); -- ports }}} end FGPU; architecture Behavioral of FGPU is -- internal signals definitions {{{ signal s0_awready_i, s0_bvalid_i : std_logic := '0'; signal s0_wready_i, s0_arready_i : std_logic := '0'; signal nrst_CUs : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal nrst_gmem_cntrl : std_logic := '0'; signal nrst_wgDispatcher : std_logic := '0'; -- }}} -- slave axi interface {{{ signal mainProc_we : std_logic := '0'; signal mainProc_wrAddr : std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0'); signal mainProc_rdAddr : unsigned(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0'); signal s0_rvalid_vec : std_logic_vector(3 downto 0) := (others=>'0'); signal s0_wdata_d0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- }}} -- general signals definitions {{{ signal KRNL_SCHEDULER_RAM : KRNL_SCHEDULER_RAM_type := init_krnl_ram("krnl_ram.mif"); -- signal cram_b1 : CRAM_type := init_CRAM("cram_LUdecomposition.mif", 930); signal cram_b1 : CRAM_type := init_CRAM("cram.mif", 3000); signal KRNL_SCH_we : std_logic := '0'; signal krnl_sch_rdData : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal krnl_sch_rdData_n : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal krnl_sch_rdAddr : unsigned(KRNL_SCH_ADDR_W-1 downto 0) := (others => '0'); signal krnl_sch_rdAddr_WGD : std_logic_vector(KRNL_SCH_ADDR_W-1 downto 0) := (others => '0'); signal CRAM_we : std_logic := '0'; -- signal cram_rdData, cram_rdData_n : SLV32_ARRAY(CRAM_BLOCKS-1 downto 0) := (others=>(others=>'0')); -- signal cram_rdAddr, cram_rdAddr_d0 : CRAM_ADDR_ARRAY(CRAM_BLOCKS-1 downto 0) := (others=>(others=>'0')); signal cram_rdData, cram_rdData_n : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal cram_rdData_vec : slv32_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal cram_rdAddr, cram_rdAddr_d0 : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal cram_rdAddr_d0_vec : cram_addr_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal status_reg : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal regFile_we, regFile_we_d0 : std_logic := '0'; signal Rstat : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others => '0'); signal Rstart : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others => '0'); signal RcleanCache : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others=>'0'); signal RInitiate : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others=>'0'); type WG_dispatcher_state_type is (idle, st1_dispatch); signal st_wg_disp, st_wg_disp_n : WG_dispatcher_state_type := idle; signal new_krnl_indx : integer range 0 to NEW_KRNL_MAX_INDX-1 := 0; signal new_krnl_field : std_logic_vector(NEW_KRNL_DESC_W-1 downto 0) := (others =>'0'); signal start_kernel, clean_cache : std_logic := '0'; signal start_CUs, initialize_d0 : std_logic := '0'; -- informs all CUs to start working after initialization phase of the WG_dispatcher is finished signal start_CUs_vec : std_logic_vector(max(N_CU-1, 0) downto 0) := (others=>'0'); -- to improve timing signal finish_exec : std_logic := '0'; -- high when execution of a kernel is done signal WGsDispatched : std_logic := '0'; -- high when WG_Dispatcher has schedules all WGs signal finish_exec_d0 : std_logic := '0'; signal finish_krnl_indx : integer range 0 to NEW_KRNL_MAX_INDX-1 := 0; signal wg_req : std_logic_vector(N_CU-1 downto 0) := (others => '0'); signal wg_ack : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); type wg_req_vec_type is array(natural range <>) of std_logic_vector(N_CU-1 downto 0); signal wg_req_vec : wg_req_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal wg_ack_vec : wg_req_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal CU_cram_rqst : std_logic_vector(N_CU-1 downto 0) := (others => '0'); signal sch_rqst_n_WFs_m1 : unsigned(N_WF_CU_W-1 downto 0) := (others=>'0'); type sch_rqst_n_WFs_m1_vec_type is array (natural range <>) of unsigned(N_WF_CU_W-1 downto 0); signal sch_rqst_n_WFs_m1_vec : sch_rqst_n_WFs_m1_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal cram_served_CUs : std_logic := '0'; -- one-bit-toggle to serve different CUs when fetching instructions signal CU_cram_rdAddr : CRAM_ADDR_ARRay(N_CU-1 downto 0) := (others =>(others=>'0')); signal start_addr : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); -- the address of the first instruction to be fetched signal start_addr_vec : cram_addr_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); -- just to improve timing signal rdData_alu_en : alu_en_vec_type(N_CU-1 downto 0) := (others=>(others=>'0')); signal rdAddr_alu_en : alu_en_rdAddr_type(N_CU-1 downto 0) := (others=>(others=>'0')); signal rtm_wrAddr_wg : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); type rtm_addr_vec_type is array (natural range<>) of unsigned(RTM_ADDR_W-1 downto 0); signal rtm_wrAddr_wg_vec : rtm_addr_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal rtm_wrData_wg : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); signal rtm_wrData_wg_vec : rtm_ram_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); signal rtm_we_wg : std_logic := '0'; signal rtm_we_wg_vec : std_logic_vector(max(N_CU-1, 0) downto 0) := (others=>'0'); signal wg_info : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal wg_info_vec : slv32_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); -- }}} -- global memory ---------------------------------------------------- {{{ -- cache signals function distribute_cache_rd_ports_on_CUs (n_cus: integer) return nat_array is -- {{{ variable res: nat_array(n_cus-1 downto 0) := (others=>0); -- res(0) will have the maximum distance to the global memory controller begin for i in 0 to n_cus-1 loop res(i) := n_cus/2*(i mod 2) + (i/2); end loop; return res; end; -- }}} constant cache_rd_port_to_CU : nat_array(N_CU-1 downto 0) := distribute_cache_rd_ports_on_CUs(N_CU); type cache_rdData_vec_type is array(natural range <>) of std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0); signal cache_rdData_vec : cache_rdData_vec_type(N_CU downto 0) := (others=>(others=>'0')); signal atomic_rdData_vec : slv32_array(N_CU downto 0) := (others=>(others=>'0')); type rdData_v_vec_type is array(natural range <>) of std_logic_vector(N_CU-1 downto 0); signal atomic_rdData_v_vec : rdData_v_vec_type(N_CU downto 0) := (others=>(others=>'0')); type atomic_sgntr_vec_type is array(natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); signal atomic_sgntr_vec : atomic_sgntr_vec_type(N_CU downto 0) := (others=>(others=>'0')); signal cache_rdAddr_vec : GMEM_ADDR_ARRAY_NO_BANK(N_CU downto 0) := (others=>(others=>'0')); signal cache_rdAck_vec : rdData_v_vec_type(N_CU downto 0) := (others=>(others=>'0')); signal cache_rdData_out : std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0) := (others=>'0'); signal cache_rdAddr_out : unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0) := (others=>'0'); signal cache_rdAck_out : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal atomic_rdData : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal atomic_rdData_v : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal atomic_sgntr : std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); signal cu_gmem_valid, cu_gmem_ready : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal cu_gmem_we : be_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_gmem_rnw, cu_gmem_atomic : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal cu_gmem_atomic_sgntr : atomic_sgntr_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_rqst_addr : GMEM_WORD_ADDR_ARRAY(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_gmem_wrData : SLV32_ARRAY(N_CU-1 downto 0) := (others=>(others=>'0')); signal wf_active : wf_active_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal CU_gmem_idle : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal CUs_gmem_idle : std_logic := '0'; signal axi_araddr : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_arvalid, axi_arready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_rdata : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_rlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_rvalid, axi_rready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_awaddr : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_awvalid, axi_awready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_wdata : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wstrb : gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_wvalid, axi_wready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_bvalid, axi_bready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_arid, axi_rid : id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_awid, axi_bid : id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); --}}} begin -- asserts -------------------------------------------------------------------------------------------{{{ assert KRNL_SCH_ADDR_W <= CRAM_ADDR_W severity failure; --Code RAM is the biggest block assert CRAM_ADDR_W <= INTERFCE_W_ADDR_W-2 severity failure; --there should be two bits to choose among: HW_sch_RAM, CRAM and the register file assert DATA_W >= GMEM_ADDR_W report "the width bus between a gmem_ctrl_CV and gmem_ctrl is GMEM_DATA_W" severity failure; assert CV_SIZE = 8 or CV_SIZE = 4 severity failure; assert 2**N_CU_STATIONS_W >= N_STATIONS_ALU*CV_SIZE report "increase N_STATIONS_W" severity failure; assert N_TAG_MANAGERS_W > 0 report "There should be at least two tag managers" severity failure; assert DATA_W = 32; -- assert CRAM_BLOCKS = 1 or CRAM_BLOCKS = 2; -- assert N_AXI = 1 or N_AXI = 2; -- assert N_AXI = 1 or N_AXI = 2; ---------------------------------------------------------------------------------------------------------}}} -- interal signals assignments --------------------------------------------------------------------------{{{ s0_awready <= s0_awready_i; s0_bvalid <= s0_bvalid_i; s0_wready <= s0_wready_i; s0_arready <= s0_arready_i; ---------------------------------------------------------------------------------------------------------}}} -- slave axi interface ----------------------------------------------------------------------------------{{{ -- aw & w channels process(clk) begin if rising_edge(clk) then if nrst = '0' then s0_awready_i <= '0'; s0_wready_i <= '0'; mainProc_we <= '0'; mainProc_wrAddr <= (others=>'0'); else if s0_awready_i = '0' and s0_awvalid = '1' and s0_wvalid = '1' then s0_awready_i <= '1'; mainProc_wrAddr <= s0_awaddr; s0_wready_i <= '1'; mainProc_we <= '1'; else s0_awready_i <= '0'; s0_wready_i <= '0'; mainProc_we <= '0'; end if; end if; end if; end process; -- b channel process(clk) begin if rising_edge(clk) then if nrst = '0' then s0_bvalid_i <= '0'; else if s0_awready_i = '1' and s0_awvalid = '1' and s0_wready_i = '1' and s0_wvalid = '1' and s0_bvalid_i = '0' then s0_bvalid_i <= '1'; elsif s0_bready = '1' and s0_bvalid_i = '1' then s0_bvalid_i <= '0'; end if; end if; end if; end process; -- ar channel process(clk) begin if rising_edge(clk) then -- if nrst = '0' then -- s_arready_i <= '0'; -- mainProc_rdAddr <= (others=>'0'); -- else if s0_arready_i = '0' and s0_arvalid = '1' then s0_arready_i <= '1'; mainProc_rdAddr <= unsigned(s0_araddr); else s0_arready_i <= '0'; end if; -- end if; end if; end process; -- r channel process(clk) begin if rising_edge(clk) then if nrst = '0' then s0_rvalid_vec <= (others=>'0'); s0_rvalid <= '0'; else s0_rvalid_vec(s0_rvalid_vec'high-1 downto 0) <= s0_rvalid_vec(s0_rvalid_vec'high downto 1); if s0_arready_i = '1' and s0_arvalid = '1' and s0_rvalid_vec(s0_rvalid_vec'high) = '0' then s0_rvalid_vec(s0_rvalid_vec'high) <= '1'; else s0_rvalid_vec(s0_rvalid_vec'high) <= '0'; end if; if s0_rvalid_vec(1) = '1' then s0_rvalid <= '1'; end if; if s0_rvalid_vec(0) = '1' then if s0_rready = '1' then s0_rvalid <= '0'; else s0_rvalid_vec(0) <= '1'; end if; end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if mainProc_rdAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "00" then -- HW_scheduler_ram s0_rdata <= krnl_sch_rdData; elsif mainProc_rdAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "01" then -- Code_ram s0_rdata <= cram_rdData; -- s0_rdata <= cram_rdData(0); else -- "10", register file case mainProc_rdAddr(1 downto 0) is when "00" => s0_rdata(NEW_KRNL_MAX_INDX-1 downto 0) <= Rstat(NEW_KRNL_MAX_INDX-1 downto 0); when "10" => s0_rdata(NEW_KRNL_MAX_INDX-1 downto 0) <= RcleanCache(NEW_KRNL_MAX_INDX-1 downto 0); when others => s0_rdata(NEW_KRNL_MAX_INDX-1 downto 0) <= RInitiate(NEW_KRNL_MAX_INDX-1 downto 0); end case; s0_rdata(DATA_W-1 downto NEW_KRNL_MAX_INDX) <= (others=>'0'); end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- fixed signals --------------------------------------------------------------------------------- {{{ s0_bresp <= "00"; s0_rresp <= "00"; ------------------------------------------------------------------------------------------------- }}} -- HW Scheduler RAM ----------------------------------------------------------------------------- {{{ Krnl_Scheduler: process (clk) begin if rising_edge(clk) then krnl_sch_rdData_n <= KRNL_SCHEDULER_RAM(to_integer(krnl_sch_rdAddr)); krnl_sch_rdData <= krnl_sch_rdData_n; if KRNL_SCH_we = '1' then KRNL_SCHEDULER_RAM(to_integer(unsigned(mainProc_wrAddr(KRNL_SCH_ADDR_W-1 downto 0)))) <= s0_wdata_d0; end if; end if; end process; krnl_sch_rdAddr <= mainProc_rdAddr(KRNL_SCH_ADDR_W-1 downto 0) when st_wg_disp = idle else unsigned(krnl_sch_rdAddr_WGD); KRNL_SCH_we <= '1' when mainProc_wrAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "00" and mainProc_we = '1' else '0'; ------------------------------------------------------------------------------------------------- }}} -- Code RAM -------------------------------------------------------------------------------------- {{{ CRAM_inst: process (clk) begin if rising_edge(clk) then nrst_wgDispatcher <= nrst; cram_rdData_n <= cram_b1(to_integer(cram_rdAddr)); -- cram_rdData_n <= cram_b1(to_integer(cram_rdAddr(0))); -- cram_rdData_n(0) <= cram_b1(to_integer(cram_rdAddr(0))); if CRAM_we = '1' then cram_b1(to_integer(unsigned(mainProc_wrAddr(CRAM_ADDR_W-1 downto 0)))) <= s0_wdata_d0; end if; -- if CRAM_BLOCKS > 1 then -- cram_rdData_n(CRAM_BLOCKS-1) <= cram_b2(to_integer(cram_rdAddr(CRAM_BLOCKS-1))); -- if CRAM_we = '1' then -- cram_b2(to_integer(unsigned(mainProc_wrAddr(CRAM_ADDR_W-1 downto 0)))) <= s0_wdata_d0; -- end if; -- end if; cram_rdData <= cram_rdData_n; end if; end process; CRAM_we <= '1' when mainProc_wrAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "01" and mainProc_we = '1' else '0'; process(clk) begin if rising_edge(clk) then cram_rdAddr_d0 <= cram_rdAddr; cram_rdAddr <= mainProc_rdAddr(CRAM_ADDR_W-1 downto 0); -- cram_rdAddr(0) <= mainProc_rdAddr(CRAM_ADDR_W-1 downto 0); cram_served_CUs <= not cram_served_CUs; if cram_served_CUs = '0' then for i in 0 to max(N_CU/2-1,0) loop if CU_cram_rqst(i) = '1' then cram_rdAddr <= CU_cram_rdAddr(i); -- cram_rdAddr(i mod CRAM_BLOCKS) <= CU_cram_rdAddr(i); end if; end loop; else for i in N_CU/2 to N_CU-1 loop if CU_cram_rqst(i) = '1' then cram_rdAddr <= CU_cram_rdAddr(i); -- cram_rdAddr(i mod CRAM_BLOCKS) <= CU_cram_rdAddr(i); end if; end loop; end if; end if; end process; ------------------------------------------------------------------------------------------------- }}} -- WG dispatcher -------------------------------------------------------------------------------------- {{{ WG_dispatcher_inst: entity WG_dispatcher port map( krnl_indx => new_krnl_indx, start => start_kernel, initialize_d0 => initialize_d0, krnl_sch_rdAddr => krnl_sch_rdAddr_WGD, krnl_sch_rdData => krnl_sch_rdData, finish_krnl_indx => finish_krnl_indx, -- to CUs start_exec => start_CUs, req => wg_req, ack => wg_ack, rtm_wrAddr => rtm_wrAddr_wg, rtm_wrData => rtm_wrData_wg, rtm_we => rtm_we_wg, sch_rqst_n_WFs_m1 => sch_rqst_n_WFs_m1, finish => WGsDispatched, start_addr => start_addr, rdData_alu_en => rdData_alu_en, wg_info => wg_info, -- from CUs wf_active => wf_active, rdAddr_alu_en => rdAddr_alu_en, clk => clk, nrst => nrst_wgDispatcher ); ------------------------------------------------------------------------------------------------- }}} -- compute units -------------------------------------------------------------------------------------- {{{ compute_units_i: for i in 0 to N_CU-1 generate begin compute_unit_inst: entity compute_unit port map( clk => clk, wf_active => wf_active(i), WGsDispatched => WGsDispatched, nrst => nrst_CUs(i), cram_rdAddr => CU_cram_rdAddr(i), cram_rdData => cram_rdData_vec(i), -- cram_rdData => cram_rdData(i mod CRAM_BLOCKS), cram_rqst => CU_cram_rqst(i), cram_rdAddr_conf => cram_rdAddr_d0_vec(i), -- cram_rdAddr_conf => cram_rdAddr_d0(i mod CRAM_BLOCKS), start_addr => start_addr_vec(i), start_CUs => start_CUs_vec(i), sch_rqst_n_wfs_m1 => sch_rqst_n_WFs_m1_vec(i), sch_rqst => wg_req_vec(i)(i), sch_ack => wg_ack(i), wg_info => unsigned(wg_info_vec(i)), rtm_wrAddr_wg => rtm_wrAddr_wg_vec(i), rtm_wrData_wg => rtm_wrData_wg_vec(i), rtm_we_wg => rtm_we_wg_vec(i), rdData_alu_en => rdData_alu_en(i), rdAddr_alu_en => rdAddr_alu_en(i), gmem_valid => cu_gmem_valid(i), gmem_we => cu_gmem_we(i), gmem_rnw => cu_gmem_rnw(i), gmem_atomic => cu_gmem_atomic(i), gmem_atomic_sgntr => cu_gmem_atomic_sgntr(i), gmem_rqst_addr => cu_rqst_addr(i), gmem_ready => cu_gmem_ready(i), gmem_wrData => cu_gmem_wrData(i), --cache read data cache_rdAddr => cache_rdAddr_vec(cache_rd_port_to_CU(i)), cache_rdAck => cache_rdAck_vec(cache_rd_port_to_CU(i))(i), cache_rdData => cache_rdData_vec(cache_rd_port_to_CU(i)), atomic_rdData => atomic_rdData_vec(cache_rd_port_to_CU(i)), atomic_rdData_v => atomic_rdData_v_vec(cache_rd_port_to_CU(i))(i), atomic_sgntr => atomic_sgntr_vec(cache_rd_port_to_CU(i)), gmem_cntrl_idle => CU_gmem_idle(i) -- loc_mem_rdAddr_dummy => loc_mem_rdAddr_dummy(DATA_W*(i+1)-1 downto i*DATA_W) ); end generate; process(clk) begin if rising_edge(clk) then cache_rdAck_vec(cache_rdAck_vec'high) <= cache_rdAck_out; cache_rdAck_vec(cache_rdAck_vec'high-1 downto 0) <= cache_rdAck_vec(cache_rdAck_vec'high downto 1); cache_rdAddr_vec(cache_rdAddr_vec'high) <= cache_rdAddr_out; cache_rdAddr_vec(cache_rdAddr_vec'high-1 downto 0) <= cache_rdAddr_vec(cache_rdAddr_vec'high downto 1); cache_rdData_vec(cache_rdData_vec'high) <= cache_rdData_out; cache_rdData_vec(cache_rdData_vec'high-1 downto 0) <= cache_rdData_vec(cache_rdData_vec'high downto 1); atomic_rdData_vec(atomic_rdData_vec'high) <= atomic_rdData; atomic_rdData_vec(atomic_rdData_vec'high-1 downto 0) <= atomic_rdData_vec(atomic_rdData_vec'high downto 1); atomic_rdData_v_vec(atomic_rdData_v_vec'high) <= atomic_rdData_v; atomic_rdData_v_vec(atomic_rdData_vec'high -1 downto 0) <= atomic_rdData_v_vec(atomic_rdData_v_vec'high downto 1); atomic_sgntr_vec(atomic_sgntr_vec'high) <= atomic_sgntr; atomic_sgntr_vec(atomic_sgntr_vec'high-1 downto 0) <= atomic_sgntr_vec(atomic_sgntr_vec'high downto 1); start_addr_vec(start_addr_vec'high) <= start_addr; start_addr_vec(start_addr_vec'high-1 downto 0) <= start_addr_vec(start_addr_vec'high downto 1); start_CUs_vec(start_CUs_vec'high) <= start_CUs; wg_req_vec(wg_req_vec'high) <= wg_req; wg_info_vec(wg_info_vec'high) <= std_logic_vector(wg_info); rtm_we_wg_vec(rtm_we_wg_vec'high) <= rtm_we_wg; sch_rqst_n_WFs_m1_vec(sch_rqst_n_WFs_m1_vec'high) <= sch_rqst_n_WFs_m1; rtm_wrData_wg_vec(rtm_wrData_wg_vec'high) <= rtm_wrData_wg; rtm_wrAddr_wg_vec(rtm_wrAddr_wg_vec'high) <= rtm_wrAddr_wg; cram_rdData_vec(cram_rdData_vec'high) <= cram_rdData; cram_rdAddr_d0_vec(cram_rdAddr_d0_vec'high) <= cram_rdAddr_d0; if N_CU > 1 then start_CUs_vec(start_CUs_vec'high-1 downto 0) <= start_CUs_vec(start_CUs_vec'high downto 1); wg_req_vec(wg_req_vec'high-1 downto 0) <= wg_req_vec(wg_req_vec'high downto 1); -- wg_ack_vec(wg_ack_vec'high-1 downto 0) <= wg_ack_vec(wg_ack_vec'high downto 1); wg_info_vec(wg_info_vec'high-1 downto 0) <= wg_info_vec(wg_info_vec'high downto 1); rtm_wrAddr_wg_vec(rtm_wrAddr_wg_vec'high-1 downto 0) <= rtm_wrAddr_wg_vec(rtm_wrAddr_wg_vec'high downto 1); rtm_wrData_wg_vec(rtm_wrData_wg_vec'high-1 downto 0) <= rtm_wrData_wg_vec(rtm_wrData_wg_vec'high downto 1); rtm_we_wg_vec(rtm_we_wg_vec'high-1 downto 0) <= rtm_we_wg_vec(rtm_we_wg_vec'high downto 1); sch_rqst_n_WFs_m1_vec(sch_rqst_n_WFs_m1_vec'high-1 downto 0) <= sch_rqst_n_WFs_m1_vec(sch_rqst_n_WFs_m1_vec'high downto 1); cram_rdData_vec(cram_rdData_vec'high-1 downto 0) <= cram_rdData_vec(cram_rdData_vec'high downto 1); cram_rdAddr_d0_vec(cram_rdAddr_d0_vec'high-1 downto 0) <= cram_rdAddr_d0_vec(cram_rdAddr_d0_vec'high downto 1); end if; for i in 0 to N_CU-1 loop nrst_CUs(i) <= nrst; end loop; end if; end process; process(clk) begin if rising_edge(clk) then if to_integer(unsigned(CU_gmem_idle)) = 2**N_CU-1 then CUs_gmem_idle <= '1'; else CUs_gmem_idle <= '0'; end if; end if; end process; ------------------------------------------------------------------------------------------------- }}} -- global memory controller----------------------------------------------------------------------------------- {{{ gmem_controller_inst: entity gmem_cntrl port map( clk => clk, cu_valid => cu_gmem_valid, cu_ready => cu_gmem_ready, cu_we => cu_gmem_we, cu_rnw => cu_gmem_rnw, cu_atomic => cu_gmem_atomic, cu_atomic_sgntr => cu_gmem_atomic_sgntr, cu_rqst_addr => cu_rqst_addr, cu_wrData => cu_gmem_wrData, WGsDispatched => WGsDispatched, finish_exec => finish_exec, start_kernel => start_kernel, clean_cache => clean_cache, CUs_gmem_idle => CUs_gmem_idle, -- read data from cache rdAck => cache_rdAck_out, rdAddr => cache_rdAddr_out, rdData => cache_rdData_out, atomic_rdData => atomic_rdData, atomic_rdData_v => atomic_rdData_v, atomic_sgntr => atomic_sgntr, -- read axi bus {{{ -- ar channel axi_araddr => axi_araddr, axi_arvalid => axi_arvalid, axi_arready => axi_arready, axi_arid => axi_arid, -- r channel axi_rdata => axi_rdata, axi_rlast => axi_rlast, axi_rvalid => axi_rvalid, axi_rready => axi_rready, axi_rid => axi_rid, -- aw channel axi_awaddr => axi_awaddr, axi_awvalid => axi_awvalid, axi_awready => axi_awready, axi_awid => axi_awid, -- w channel axi_wdata => axi_wdata, axi_wstrb => axi_wstrb, axi_wlast => axi_wlast, axi_wvalid => axi_wvalid, axi_wready => axi_wready, -- b channel axi_bvalid => axi_bvalid, axi_bready => axi_bready, axi_bid => axi_bid, --}}} nrst => nrst_gmem_cntrl ); -- fixed signals assignments {{{ m0_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m0_arlen'length)); m1_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m1_arlen'length)); m2_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m2_arlen'length)); m3_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m3_arlen'length)); m0_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m1_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m2_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m3_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m0_arburst <= "01"; --INCR burst type m1_arburst <= "01"; --INCR burst type m2_arburst <= "01"; --INCR burst type m3_arburst <= "01"; --INCR burst type m0_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m0_awlen'length)); m1_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m1_awlen'length)); m2_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m2_awlen'length)); m3_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m3_awlen'length)); m0_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m1_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m2_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m3_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes, m0_awburst <= "01"; --INCR burst type m1_awburst <= "01"; --INCR burst type m2_awburst <= "01"; --INCR burst type m3_awburst <= "01"; --INCR burst type --}}} -- ar & r assignments {{{ m0_araddr <= std_logic_vector(axi_araddr(0)); m0_arvalid <= axi_arvalid(0); axi_arready(0) <= m0_arready; axi_rdata(0) <= m0_rdata; axi_rlast(0) <= m0_rlast; axi_rvalid(0) <= m0_rvalid; axi_rid(0) <= m0_rid; axi_bid(0) <= m0_bid; m0_awid <= axi_awid(0); m0_rready <= axi_rready(0); m0_arid <= axi_arid(0); AXI_READ_1: if N_AXI > 1 generate m1_araddr <= std_logic_vector(axi_araddr(1)); m1_arvalid <= axi_arvalid(1); axi_arready(1) <= m1_arready; axi_rdata(1) <= m1_rdata; axi_rlast(1) <= m1_rlast; axi_rvalid(1) <= m1_rvalid; axi_rid(1) <= m1_rid; axi_bid(1) <= m1_bid; m1_awid <= axi_awid(1); m1_rready <= axi_rready(1); m1_arid <= axi_arid(1); end generate; AXI_READ_2: if N_AXI > 2 generate m2_araddr <= std_logic_vector(axi_araddr(2)); m2_arvalid <= axi_arvalid(2); axi_arready(2) <= m2_arready; axi_rdata(2) <= m2_rdata; axi_rlast(2) <= m2_rlast; axi_rvalid(2) <= m2_rvalid; axi_rid(2) <= m2_rid; axi_bid(2) <= m2_bid; m2_awid <= axi_awid(2); m2_rready <= axi_rready(2); m2_arid <= axi_arid(2); end generate; AXI_READ_3: if N_AXI > 3 generate m3_araddr <= std_logic_vector(axi_araddr(3)); m3_arvalid <= axi_arvalid(3); axi_arready(3) <= m3_arready; axi_rdata(3) <= m3_rdata; axi_rlast(3) <= m3_rlast; axi_rvalid(3) <= m3_rvalid; axi_rid(3) <= m3_rid; axi_bid(3) <= m3_bid; m3_awid <= axi_awid(3); m3_rready <= axi_rready(3); m3_arid <= axi_arid(3); end generate; -- }}} -- aw, w & b assignments {{{ m0_awaddr <= std_logic_vector(axi_awaddr(0)); m0_awvalid <= axi_awvalid(0); axi_awready(0) <= m0_awready; m0_wdata <= axi_wdata(0); m0_wstrb <= axi_wstrb(0); m0_wlast <= axi_wlast(0); m0_wvalid <= axi_wvalid(0); axi_wready(0) <= m0_wready; axi_bvalid(0) <= m0_bvalid; m0_bready <= axi_bready(0); AXI_WRITE_1: if N_AXI > 1 generate m1_awaddr <= std_logic_vector(axi_awaddr(1)); m1_awvalid <= axi_awvalid(1); axi_awready(1) <= m1_awready; m1_wdata <= axi_wdata(1); m1_wstrb <= axi_wstrb(1); m1_wlast <= axi_wlast(1); m1_wvalid <= axi_wvalid(1); axi_wready(1) <= m1_wready; axi_bvalid(1) <= m1_bvalid; m1_bready <= axi_bready(1); end generate; AXI_WRITE_2: if N_AXI > 2 generate m2_awaddr <= std_logic_vector(axi_awaddr(2)); m2_awvalid <= axi_awvalid(2); axi_awready(2) <= m2_awready; m2_wdata <= axi_wdata(2); m2_wstrb <= axi_wstrb(2); m2_wlast <= axi_wlast(2); m2_wvalid <= axi_wvalid(2); axi_wready(2) <= m2_wready; axi_bvalid(2) <= m2_bvalid; m2_bready <= axi_bready(2); end generate; AXI_WRITE_3: if N_AXI > 3 generate m3_awaddr <= std_logic_vector(axi_awaddr(3)); m3_awvalid <= axi_awvalid(3); axi_awready(3) <= m3_awready; m3_wdata <= axi_wdata(3); m3_wstrb <= axi_wstrb(3); m3_wlast <= axi_wlast(3); m3_wvalid <= axi_wvalid(3); axi_wready(3) <= m3_wready; axi_bvalid(3) <= m3_bvalid; m3_bready <= axi_bready(3); end generate; -- }}} ------------------------------------------------------------------------------------------------- }}} -- WG dispatcher FSM -------------------------------------------------------------------------------------- {{{ regFile_we <= '1' when mainProc_wrAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "10" and mainProc_we = '1' else '0'; regs_trans: process(clk) begin if rising_edge(clk) then nrst_gmem_cntrl <= nrst; if start_kernel = '1' then clean_cache <= RcleanCache(new_krnl_indx); initialize_d0 <= RInitiate(new_krnl_indx); end if; s0_wdata_d0 <= s0_wdata; finish_exec_d0 <= finish_exec; if nrst = '0' then st_wg_disp <= idle; Rstat <= (others =>'0'); RcleanCache <= (others=>'0'); Rstart <= (others =>'0'); RInitiate <= (others=>'0'); else st_wg_disp <= st_wg_disp_n; -- regFile_we_d0 <= regFile_we; if start_kernel = '1' then Rstart(new_krnl_indx) <= '0'; elsif regFile_we = '1' and to_integer(unsigned(mainProc_wrAddr(N_REG_W-1 downto 0))) = Rstart_regFile_addr then Rstart <= s0_wdata_d0(NEW_KRNL_MAX_INDX-1 downto 0); end if; if regFile_we = '1' and to_integer(unsigned(mainProc_wrAddr(N_REG_W-1 downto 0))) = RcleanCache_regFile_addr then RcleanCache <= s0_wdata_d0(NEW_KRNL_MAX_INDX-1 downto 0); end if; if regFile_we = '1' and to_integer(unsigned(mainProc_wrAddr(N_REG_W-1 downto 0))) = RInitiate_regFile_addr then RInitiate <= s0_wdata_d0(NEW_KRNL_MAX_INDX-1 downto 0); end if; if start_kernel = '1' then Rstat(new_krnl_indx) <= '0'; elsif finish_exec = '1' and finish_exec_d0 = '0' then Rstat(finish_krnl_indx) <= '1'; end if; end if; end if; end process; process(Rstart) begin new_krnl_indx <= 0; for i in NEW_KRNL_MAX_INDX-1 downto 0 loop if Rstart(i) = '1' then new_krnl_indx <= i; end if; end loop; end process; start_kernel <= '1' when st_wg_disp_n = st1_dispatch and st_wg_disp = idle else '0'; process(st_wg_disp, finish_exec, Rstart) begin st_wg_disp_n <= st_wg_disp; case(st_wg_disp) is when idle => if to_integer(unsigned(Rstart)) /= 0 then --new kernel to start st_wg_disp_n <= st1_dispatch; end if; when st1_dispatch => if finish_exec = '1' then -- kernel is dispatched st_wg_disp_n <= idle; end if; end case; end process; ------------------------------------------------------------------------------------------------- }}} end Behavioral;

gpl-3.0

ef7e609a8088bf1fb519b87a94320587

wltr/cern-fgclite

nanofip_fpga/src/rtl/rx_var_select.vhd

------------------------------------------------------------------------------- --! @file rx_var_select.vhd --! @author Johannes Walter <[email protected]> --! @copyright CERN TE-EPC-CCE --! @date 2014-04-03 --! @brief Toggle between VAR1 and VAR2 when receiving data. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; --! @brief Entity declaration of rx_var_select --! @details --! Multiplexer control for data reception. When VAR1 or VAR2 are received, --! the Wishbone interface will be connected to the corresponding receiver. entity rx_var_select is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Ready signals --! @{ --! VAR1 is ready var1_rdy_i : in std_ulogic; --! VAR2 is ready var2_rdy_i : in std_ulogic; --! @} --! @name Multiplexer control --! @{ --! Select receiver, 0 = VAR1, 1 = VAR2, VAR2 is default var_select_o : out std_ulogic); --! @} end entity rx_var_select; --! RTL implementation of rx_var_select architecture rtl of rx_var_select is --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal var_select : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- var_select_o <= var_select; --------------------------------------------------------------------------- -- Registering --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin var_select <= '1'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; elsif var1_rdy_i = '1' then var_select <= '0'; elsif var2_rdy_i = '1' then var_select <= '1'; end if; end if; end process regs; end architecture rtl;

mit

c919e7cd2801be8a9107dc999b420b00

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_decr_counter.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_decr_counter | -- | --------------------------------------------------------------------------------------------------- -- File wf_decr_counter.vhd | -- Description Decreasing counter with synchronous reset, load enable and decrease enable | -- Authors Pablo Alvarez Sanchez ([email protected]) | -- Evangelia Gousiou ([email protected]) | -- Date 10/2010 | -- Version v0.01 | -- Depends on - | ---------------- | -- Last changes | -- 10/2010 EG v0.01 first version | -- 10/2011 EG v0.01b nfip_rst_i renamed to counter_rst_i; counter_top renamed to | -- counter_top_i; initial value after reset is all '1'; | -- counter_decr_p_i renamed to counter_decr_i | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_decr_counter --================================================================================================= entity wf_decr_counter is generic(g_counter_lgth : natural := 4); -- default length port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit counter_rst_i : in std_logic; -- resets counter to all '1' -- Signals from any unit counter_decr_i : in std_logic; -- decrement enable counter_load_i : in std_logic; -- load enable; loads counter to counter_top_i counter_top_i : in unsigned (g_counter_lgth-1 downto 0); -- load value -- OUTPUTS -- Signal to any unit counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter counter_is_zero_o : out std_logic); -- empty counter indication end entity wf_decr_counter; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_decr_counter is signal s_counter : unsigned (g_counter_lgth-1 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Synchronous process Decr_Counter Decr_Counter: process (uclk_i) begin if rising_edge (uclk_i) then if counter_rst_i = '1' then s_counter <= (others => '1'); else if counter_load_i = '1' then s_counter <= counter_top_i; elsif counter_decr_i = '1' then s_counter <= s_counter - 1; end if; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- counter_o <= s_counter; counter_is_zero_o <= '1' when s_counter = to_unsigned(0, s_counter'length) else '0'; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

b4a4873134df7108f8f0c602de50448a

Ttl/fsm_uart

examples/echo.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity echo is Port ( rx : in STD_LOGIC; tx : out STD_LOGIC; clk : in STD_LOGIC); end echo; architecture Behavioral of echo is -- Implementation parameters constant CLK_FREQ : integer := 32; constant SER_FREQ : integer := 115200; constant PARITY : boolean := true; -- UART signals signal uart_tx_req, uart_tx_end, uart_rx_ready : std_logic; signal uart_rx_tx_data : std_logic_vector(7 downto 0); -- FSM states type statetype is (s_rx, s_tx); signal state, next_state : statetype := s_rx; -- Transmission delay, wait for 2^10=1024 clock cycles before responding -- to make sure that receiver catches the beginning signal tx_delay, tx_delay_next : std_logic_vector(10 downto 0); component uart is generic ( CLK_FREQ : integer := CLK_FREQ; -- Main frequency (MHz) SER_FREQ : integer := SER_FREQ; -- Baud rate (bps) PARITY_BIT : boolean := PARITY -- RS232 parity bit ); port ( -- Control clk : in std_logic; -- Main clock rst : in std_logic; -- Main reset -- External Interface rx : in std_logic; -- RS232 received serial data tx : out std_logic; -- RS232 transmitted serial data -- uPC Interface tx_req : in std_logic; -- Request SEND of data tx_end : out std_logic; -- Data SENDED tx_data : in std_logic_vector(7 downto 0); -- Data to transmit rx_ready : out std_logic; -- Received data ready to uPC read rx_data : out std_logic_vector(7 downto 0) -- Received data ); end component; begin u1 : uart generic map( CLK_FREQ => CLK_FREQ, -- Main frequency (MHz) SER_FREQ => SER_FREQ, -- Baud rate (bps) PARITY_BIT => PARITY -- RS232 parity bit ) port map( -- Control clk => clk, rst => '0', -- External Interface rx => rx, tx => tx, -- uPC Interface tx_req => uart_tx_req, tx_end => uart_tx_end, tx_data => uart_rx_tx_data, rx_ready => uart_rx_ready, rx_data => uart_rx_tx_data ); process(clk) begin if rising_edge(clk) then state <= next_state; tx_delay <= tx_delay_next; end if; end process; process(state, uart_rx_ready, uart_tx_end, tx_delay) begin uart_tx_req <= '0'; tx_delay_next <= (others => '0'); case state is when s_rx => next_state <= s_rx; -- Received data if uart_rx_ready = '1' then -- Echo it back next_state <= s_tx; end if; when s_tx => next_state <= s_tx; if tx_delay(10) = '1' then -- Start TX uart_tx_req <= '1'; -- Hold tx_req --tx_delay_next <= tx_delay; else tx_delay_next <= std_logic_vector(unsigned(tx_delay) + 1); end if; -- Transmission done if uart_tx_end = '1' then next_state <= s_rx; end if; end case; end process; end Behavioral;

lgpl-3.0

196fa2685f245abdcc8d848eafbb05ab

wltr/cern-fgclite

critical_fpga/src/rtl/cf/fetch_page/fetch_page_dim.vhd

------------------------------------------------------------------------------- --! @file fetch_page_dim.vhd --! @author Johannes Walter <[email protected]> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief Prepare DIM page for NanoFIP communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --! @brief Entity declaration of fetch_page_dim --! @details --! This component prepares the DIM page for the NanoFIP response. entity fetch_page_dim is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Commands --! @{ --! Start flag start_i : in std_ulogic; --! Done flag done_o : out std_ulogic; --! Memory index idx_i : in std_ulogic_vector(14 downto 0); --! @} --! @name Memory page interface --! @{ --! Address page_addr_o : out std_ulogic_vector(5 downto 0); --! Write enable page_wr_en_o : out std_ulogic; --! Data output page_data_o : out std_ulogic_vector(7 downto 0); --! Done flag page_done_i : in std_ulogic; --! @} --! @name DIM data --! @{ --! Address dim_addr_o : out std_ulogic_vector(6 downto 0); --! Read enable dim_rd_en_o : out std_ulogic; --! Data input dim_data_i : in std_ulogic_vector(15 downto 0); --! Data input enable dim_data_en_i : in std_ulogic); --! @} end entity fetch_page_dim; --! RTL implementation of fetch_page_dim architecture rtl of fetch_page_dim is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type state_t is (IDLE, WRITE_LOW, WRITE_HIGH, DONE); type reg_t is record state : state_t; addr : unsigned(5 downto 0); data : std_ulogic_vector(7 downto 0); wr_en : std_ulogic; rd_en : std_ulogic; done : std_ulogic; end record; constant init_c : reg_t := ( state => IDLE, addr => (others => '0'), data => (others => '0'), wr_en => '0', rd_en => '0', done => '0'); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg : reg_t; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- page_addr_o <= std_ulogic_vector(reg.addr); page_wr_en_o <= reg.wr_en; page_data_o <= reg.data; dim_addr_o <= idx_i(1 downto 0) & std_ulogic_vector(reg.addr(5 downto 1)); dim_rd_en_o <= reg.rd_en; done_o <= reg.done; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, start_i, page_done_i, dim_data_i, dim_data_en_i) is begin -- comb -- Defaults next_reg <= reg; next_reg.rd_en <= '0'; next_reg.wr_en <= '0'; next_reg.done <= '0'; case reg.state is when IDLE => if start_i = '1' then next_reg.rd_en <= '1'; next_reg.state <= WRITE_LOW; end if; when WRITE_LOW => if dim_data_en_i = '1' then next_reg.data <= dim_data_i(7 downto 0); next_reg.wr_en <= '1'; end if; if page_done_i = '1' then next_reg.addr <= reg.addr + 1; next_reg.state <= WRITE_HIGH; end if; when WRITE_HIGH => next_reg.data <= dim_data_i(15 downto 8); next_reg.wr_en <= '1'; next_reg.state <= DONE; when DONE => if page_done_i = '1' then if to_integer(reg.addr) < 63 then next_reg.addr <= reg.addr + 1; next_reg.rd_en <= '1'; next_reg.state <= WRITE_LOW; else next_reg <= init_c; next_reg.done <= '1'; end if; end if; end case; end process comb; end architecture rtl;

mit

c1d4169b153eb1365b1098a0828f3bfa

malkadi/FGPU

RTL/WG_dispatcher.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity WG_dispatcher is -- ports {{{ port( clk, nrst : in std_logic; start : in std_logic; initialize_d0 : in std_logic; start_exec : out std_logic := '0'; krnl_indx : in integer range 0 to NEW_KRNL_MAX_INDX-1; krnl_sch_rdAddr : out std_logic_vector(KRNL_SCH_ADDR_W-1 downto 0) := (others => '0'); krnl_sch_rdData : in std_logic_vector(DATA_W-1 downto 0) := (others => '0'); finish : out std_logic := '0'; finish_krnl_indx : out integer range 0 to NEW_KRNL_MAX_INDX-1 := 0; -- index of kernel whose execution just finished start_addr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); -- cds interface req : out std_logic_vector(N_CU-1 downto 0) := (others => '0'); ack : in std_logic_vector(N_CU-1 downto 0) := (others => '0'); sch_rqst_n_WFs_m1 : out unsigned(N_WF_CU_W-1 downto 0) := (others=>'0'); wf_active : in wf_active_array(N_CU-1 downto 0) := (others=>(others=>'0')); wg_info : out unsigned(DATA_W-1 downto 0) := (others=>'0'); rdData_alu_en : out alu_en_vec_type(N_CU-1 downto 0) := (others=>(others=>'0')); rdAddr_alu_en : in alu_en_rdAddr_type(N_CU-1 downto 0) := (others=>(others=>'0')); rtm_wrAddr : out unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); rtm_wrData : out unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); rtm_we : out std_logic := '0' ); -- }}} end WG_dispatcher; architecture Behavioral of WG_dispatcher is -- internal signals {{{ signal start_exec_i : std_logic := '0'; signal finish_i : std_logic := '0'; signal sch_rqst_n_WFs_m1_i : unsigned(N_WF_CU_W-1 downto 0) := (others=>'0'); -- }}} -- signals definitions {{{ signal schedulingInProgress : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal schedulingInProgress_n : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal nDim : integer range 0 to 2 := 0; type WG_st_sch_type is (idle, read_delay, prepare, seekCV, allocateWFs, checkAgain, wait_wf_active, wait_finish); signal st_sch, st_sch_n : WG_st_sch_type := idle; signal st_prepare, st_prepare_d0 : unsigned(NEW_KRNL_DESC_W-1 downto 0) := (others => '0'); signal st_prepare_n : unsigned(NEW_KRNL_DESC_W-1 downto 0) := (others => '0'); signal params : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal params_wrAddr : unsigned(N_PARAMS_W-1 downto 0) := (others=>'0'); signal params_written, params_written_n : std_logic := '0'; signal krnl_infos_we : std_logic := '0'; signal id0_offset : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id1_offset : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id2_offset : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id0_size : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id1_size : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id2_size : unsigned(DATA_W-1 downto 0) := (others => '0'); signal wg_size : unsigned(WG_SIZE_W downto 0) := (others=>'0'); signal wg_size_d0 : integer range 0 to WG_MAX_SIZE := 0; signal wg_size_d1 : integer range 0 to WG_MAX_SIZE := 0; signal wg_size_d2 : integer range 0 to WG_MAX_SIZE := 0; signal start_prepare : std_logic := '0'; signal prepare_params_n, prepare_params : std_logic := '0'; signal krnl_indx_ltchd : integer range 0 to NEW_KRNL_MAX_INDX-1 := 0; signal addr_first_inst : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal n_wg_d0_m1 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal n_wg_d1_m1 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal n_wg_d2_m1 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal prepare_fin : std_logic := '0'; signal nDisp_wg_d0 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d1 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d2 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d1_ov : std_logic := '0'; signal nDisp_wg_d0_ov : std_logic := '0'; signal id0,id1,id2 : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nParams : integer range 0 to N_PARAMS := 0; -- next signals signal prepare_fin_n, prepare_fin_d0 : std_logic := '0'; signal start_loc_indcs : std_logic := '0'; signal start_prepare_n : std_logic := '0'; signal nDisp_wg_d0_n : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d1_n : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d2_n : unsigned(DATA_W-1 downto 0) := (others => '0'); signal id0_n,id1_n,id2_n : unsigned(DATA_W-1 downto 0) := (others => '0'); signal nDisp_wg_d0_ov_n : std_logic := '0'; signal nDisp_wg_d1_ov_n : std_logic := '0'; signal req_n : std_logic_vector(N_CU-1 downto 0) := (others => '0'); signal wg_info_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal alu_en_rdy : std_logic := '0'; signal start_d0 : std_logic := '0'; -- }}} -- RTM signals{{{ signal rtm_we_n : std_logic := '0'; signal rtm_wrAddr_n : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0'); signal rtm_wrData_n : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); --}}} -- scheduling signals {{{ signal alloc_CV_indx : integer range 0 to N_CU := 0; signal cd_indx, cd_indx_d0, cd_indx_d1 : unsigned(max(N_CU_W, 1)-1 downto 0) := (others=>'0'); signal wf_active_slctd : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal n_inactive_wfs : integer range 0 to N_WF_CU := 0; --}}} -- loc indices signals {{{ signal loc_indcs_fin : std_logic := '0'; signal loc_indcs_wrAddr : unsigned(RTM_ADDR_W-2 downto 0) := (others => '0'); signal loc_indcs_wrData : unsigned(RTM_DATA_W-1 downto 0) := (others => '0'); signal loc_indcs_we : std_logic := '0'; type loc_indcs_wr_state_type is ( write_size0, write_size1, write_size2, write_wg_size_d0, write_wg_size_d1, write_wg_size_d2, write_n_wgs_d0, write_n_wgs_d1, write_n_wgs_d2, write_params, write_loc_indcs, write_d0, write_d1, write_d2); signal loc_indcs_wr_state : loc_indcs_wr_state_type := write_size0; signal loc_indcs_wr_state_n : loc_indcs_wr_state_type := write_size0; -- }}} begin -- internal signals assignments --------------------------------------------------------------------{{{ assert(RTM_DATA_W >= DATA_W) severity failure; start_exec <= start_exec_i; sch_rqst_n_WFs_m1 <= sch_rqst_n_WFs_m1_i; ---------------------------------------------------------------------------------------------------------}}} -- others {{{ finish_krnl_indx <= krnl_indx_ltchd; start_addr <= addr_first_inst; --}}} -- local indices generator ------------------------------------------------------------------------------------ {{{ loc_indcs_gen: entity loc_indcs_generator port map( clk => clk, start => start_loc_indcs, finish => loc_indcs_fin, clear_finish => start_exec_i, n_wf_wg_m1 => sch_rqst_n_WFs_m1_i, wg_size_d0 => wg_size_d0, wg_size_d1 => wg_size_d1, wg_size_d2 => wg_size_d2, wrAddr => loc_indcs_wrAddr, we => loc_indcs_we, wrData => loc_indcs_wrData, nrst => nrst ); start_exec_i <= (loc_indcs_fin and alu_en_rdy) or params_written; process(clk) begin if rising_edge(clk) then finish <= finish_i; rtm_we <= rtm_we_n; rtm_wrAddr <= rtm_wrAddr_n; rtm_wrData <= rtm_wrData_n; wg_info <= wg_info_n; start_d0 <= start; params_written <= params_written_n; if nrst = '0' then loc_indcs_wr_state <= write_size0; else loc_indcs_wr_state <= loc_indcs_wr_state_n; end if; end if; end process; process(loc_indcs_wr_state, req_n, id0, id1, id2, start_exec_i, loc_indcs_we, loc_indcs_wrAddr, loc_indcs_wrData, krnl_infos_we, params_wrAddr, params, prepare_fin_d0, finish_i, wg_size_d0, wg_size_d1, wg_size_d2, id0_size, id1_size, id2_size, n_wg_d0_m1, n_wg_d1_m1, n_wg_d2_m1, initialize_d0, start_d0) begin loc_indcs_wr_state_n <= loc_indcs_wr_state; rtm_we_n <= loc_indcs_we; rtm_wrAddr_n(RTM_ADDR_W-2 downto 0) <= loc_indcs_wrAddr; rtm_wrAddr_n(RTM_ADDR_W-1) <= '0'; rtm_wrData_n <= loc_indcs_wrData; wg_info_n <= id0; params_written_n <= '0'; case loc_indcs_wr_state is when write_size0 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= id0_size; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_size1; end if; if start_d0 = '1' and initialize_d0 = '0' then loc_indcs_wr_state_n <= write_params; end if; when write_size1 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (0=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= id1_size; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_size2; end if; when write_size2 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'0', others=>'1'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (1=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= id2_size; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_wg_size_d0; end if; when write_wg_size_d0 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0'); rtm_wrData_n(DATA_W-1 downto WG_SIZE_W+1) <= (others=>'0'); rtm_wrData_n(WG_SIZE_W downto 0) <= to_unsigned(wg_size_d0, WG_SIZE_W+1); if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_n_wgs_d0; end if; when write_n_wgs_d0 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= n_wg_d0_m1; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_n_wgs_d1; end if; when write_n_wgs_d1 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (0=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= n_wg_d1_m1; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_n_wgs_d2; end if; when write_n_wgs_d2 => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+2=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (1=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto 0) <= n_wg_d2_m1; if krnl_infos_we = '1' then loc_indcs_wr_state_n <= write_wg_size_d1; end if; when write_wg_size_d1 => rtm_we_n <= '1'; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (0=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto WG_SIZE_W+1) <= (others=>'0'); rtm_wrData_n(WG_SIZE_W downto 0) <= to_unsigned(wg_size_d1, WG_SIZE_W+1); loc_indcs_wr_state_n <= write_wg_size_d2; when write_wg_size_d2 => rtm_we_n <= '1'; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(N_WF_CU_W+PHASE_W-1 downto PHASE_W) <= (PHASE_W+1=>'1', others=>'0'); rtm_wrAddr_n(PHASE_W-1 downto 0) <= (1=>'1', others=>'0'); rtm_wrData_n(DATA_W-1 downto WG_SIZE_W+1) <= (others=>'0'); rtm_wrData_n(WG_SIZE_W downto 0) <= to_unsigned(wg_size_d2, WG_SIZE_W+1); loc_indcs_wr_state_n <= write_params; when write_params => rtm_we_n <= krnl_infos_we; rtm_wrAddr_n(RTM_ADDR_W-1) <= '1'; rtm_wrAddr_n(RTM_ADDR_W-2 downto RTM_ADDR_W-3) <= "11"; rtm_wrAddr_n(RTM_ADDR_W-4 downto N_PARAMS_W) <= (others=>'0'); rtm_wrAddr_n(N_PARAMS_W-1 downto 0) <= params_wrAddr; rtm_wrData_n(DATA_W-1 downto 0) <= params; if prepare_fin_d0 = '1' then if initialize_d0 = '0' then loc_indcs_wr_state_n <= write_d0; params_written_n <= '1'; else loc_indcs_wr_state_n <= write_loc_indcs; end if; end if; when write_loc_indcs => if start_exec_i = '1' then loc_indcs_wr_state_n <= write_d0; end if; rtm_wrData_n <= loc_indcs_wrData; when write_d0 => -- rtm_we has not to be set during write_dx because it is done in the CU_schceduler. -- in case that a WG consists of multiple WFs, the WG's offsets need to written multiple times. wg_info_n <= id0; if to_integer(unsigned(req_n)) /= 0 then loc_indcs_wr_state_n <= write_d1; end if; if finish_i = '1' then loc_indcs_wr_state_n <= write_size0; end if; when write_d1 => wg_info_n <= id1; loc_indcs_wr_state_n <= write_d2; when write_d2 => wg_info_n <= id2; loc_indcs_wr_state_n <= write_d0; end case; end process; ---------------------------------------------------------------------------------------------------------------}}} -- WG scheduler FSM ------------------------------------------------------------------------------------{{{ process(st_sch, start, alloc_CV_indx, start_exec_i, nDisp_wg_d0_ov, nDisp_wg_d1_ov, nDisp_wg_d0, nDisp_wg_d1, nDisp_wg_d2, id0, id1, id2, id0_offset, id1_offset, id2_offset, n_wg_d0_m1, n_wg_d1_m1, n_wg_d2_m1, wg_size_d0, wg_size_d1, wg_size_d2, wf_active, schedulingInProgress, initialize_d0) --, alloc_CV_indx_ltchd) begin st_sch_n <= st_sch; start_prepare_n <= '0'; id0_n <= id0; id1_n <= id1; id2_n <= id2; nDisp_wg_d0_n <= nDisp_wg_d0; nDisp_wg_d1_n <= nDisp_wg_d1; nDisp_wg_d2_n <= nDisp_wg_d2; nDisp_wg_d0_ov_n <= nDisp_wg_d0_ov; nDisp_wg_d1_ov_n <= nDisp_wg_d1_ov; req_n <= (others=>'0'); finish_i <= '0'; prepare_params_n <= '0'; schedulingInProgress_n <= schedulingInProgress; -- rtm_we_dx <= (others=>'0'); case st_sch is when idle => if start = '1' then st_sch_n <= read_delay; end if; when read_delay => st_sch_n <= prepare; start_prepare_n <= '1'; if initialize_d0 = '0' then prepare_params_n <= '1'; end if; when prepare => if start_exec_i = '1' then st_sch_n <= seekCV; id0_n <= id0_offset; id1_n <= id1_offset; id2_n <= id2_offset; end if; when seekCV => if alloc_CV_indx /= N_CU then st_sch_n <= allocateWFs; req_n(alloc_CV_indx) <= '1'; schedulingInProgress_n(alloc_CV_indx) <= '1'; -- rtm_we_dx(alloc_CV_indx) <= '1'; if nDisp_wg_d0 = n_wg_d0_m1 then nDisp_wg_d0_ov_n <= '1'; else nDisp_wg_d0_ov_n <= '0'; end if; end if; when allocateWFs => st_sch_n <= checkAgain; -- rtm_we_dx(alloc_CV_indx_ltchd) <= '1'; nDisp_wg_d1_ov_n <= '0'; if nDisp_wg_d0_ov = '1' and nDisp_wg_d1 = n_wg_d1_m1 then nDisp_wg_d1_ov_n <= '1'; end if; when checkAgain => st_sch_n <= seekCV; -- rtm_we_dx(alloc_CV_indx_ltchd) <= '1'; if nDisp_wg_d0_ov = '1' then nDisp_wg_d0_n <= (others => '0'); id0_n <= id0_offset; nDisp_wg_d1_n <= nDisp_wg_d1 + 1; id1_n <= id1 + WG_size_d1; else nDisp_wg_d0_n <= nDisp_wg_d0 + 1; id0_n <= id0 + wg_size_d0; end if; if nDisp_wg_d1_ov = '1' then nDisp_wg_d1_n <= (others => '0'); id1_n <= id1_offset; nDisp_wg_d2_n <= nDisp_wg_d2 + 1; id2_n <= id2 + WG_size_d2; if nDisp_wg_d2 = n_wg_d2_m1 then st_sch_n <= wait_wf_active; end if; end if; when wait_wf_active => if schedulingInProgress = (schedulingInProgress'reverse_range=>'0') then st_sch_n <= wait_finish; end if; when wait_finish => finish_i <= '1'; st_sch_n <= idle; for i in 0 to N_CU-1 loop if to_integer(unsigned(wf_active(i))) /= 0 then st_sch_n <= wait_finish; finish_i <= '0'; end if; end loop; end case; end process; process(clk) variable tmp : integer range 0 to N_WF_CU := 0; begin if rising_edge(clk) then if nrst = '0' or finish_i = '1' then nDisp_wg_d0 <= (others => '0'); nDisp_wg_d1 <= (others => '0'); nDisp_wg_d2 <= (others => '0'); nDisp_wg_d0_ov <= '0'; nDisp_wg_d1_ov <= '0'; req <= (others=>'0'); cd_indx <= (others=>'0'); wf_active_slctd <= (others=>'0'); cd_indx_d0 <= (others=>'0'); n_inactive_wfs <= 0; cd_indx_d1 <= (others=>'0'); alloc_CV_indx <= 0; schedulingInProgress <= (others=>'0'); else nDisp_wg_d0 <= nDisp_wg_d0_n; nDisp_wg_d1 <= nDisp_wg_d1_n; nDisp_wg_d2 <= nDisp_wg_d2_n; nDisp_wg_d0_ov <= nDisp_wg_d0_ov_n; nDisp_wg_d1_ov <= nDisp_wg_d1_ov_n; req <= req_n; schedulingInProgress <= schedulingInProgress_n; for i in 0 to N_CU-1 loop if ack(i) = '1' then schedulingInProgress(i) <= '0'; end if; end loop; -- stage 0 if N_CU_W > 0 then cd_indx <= cd_indx+1; end if; -- stage 1 wf_active_slctd <= wf_active(to_integer(cd_indx)); cd_indx_d0 <= cd_indx; -- stage 2 tmp := 0; for i in 0 to N_WF_CU-1 loop if wf_active_slctd(i) = '0' then tmp := tmp + 1; end if; end loop; n_inactive_wfs <= tmp; cd_indx_d1 <= cd_indx_d0; -- stage 3 alloc_CV_indx <= N_CU; if n_inactive_wfs > to_integer(sch_rqst_n_WFs_m1_i) and schedulingInProgress(to_integer(cd_indx_d1)) = '0' then alloc_CV_indx <= to_integer(cd_indx_d1); end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then id0 <= id0_n; id1 <= id1_n; id2 <= id2_n; prepare_params <= prepare_params_n; if start = '1' and st_sch = idle then krnl_indx_ltchd <= krnl_indx; end if; if nrst = '0' then st_sch <= idle; start_prepare <= '0'; else st_sch <= st_sch_n; start_prepare <= start_prepare_n; end if; end if; end process; ------------------------------------------------------------------------------------------------}}} -- prepare FSM -------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then prepare_fin <= prepare_fin_n; prepare_fin_d0 <= prepare_fin; start_loc_indcs <= prepare_fin and initialize_d0; krnl_infos_we <= '0'; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WF then addr_first_inst <= unsigned(krnl_sch_rdData(ADDR_FIRST_INST_OFFSET+CRAM_ADDR_W-1 downto ADDR_FIRST_INST_OFFSET)); -- addr_last_inst <= to_integer(unsigned(krnl_sch_rdData(ADDR_LAST_INST_OFFSET+CRAM_ADDR_W-1 downto ADDR_LAST_INST_OFFSET))); sch_rqst_n_WFs_m1_i <= unsigned(krnl_sch_rdData(N_WF_OFFSET+N_WF_CU_W-1 downto N_WF_OFFSET)); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID0_SIZE then id0_size <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID1_SIZE then id1_size <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID2_SIZE then id2_size <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID0_OFFSET then id0_offset <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID1_OFFSET then id1_offset <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_ID2_OFFSET then id2_offset <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_WG_SIZE then krnl_infos_we <= '1'; wg_size_d0 <= to_integer(unsigned(krnl_sch_rdData(WG_SIZE_0_OFFSET+WG_SIZE_W downto WG_SIZE_0_OFFSET))); --WG_SIZE_W+1 bits are assigned if to_integer(unsigned(krnl_sch_rdData(N_DIM_OFFSET+1 downto N_DIM_OFFSET))) /=0 then -- compare with nDim wg_size_d1 <= to_integer(unsigned(krnl_sch_rdData(WG_SIZE_1_OFFSET+WG_SIZE_W downto WG_SIZE_1_OFFSET))); else wg_size_d1 <= 1; end if; if to_integer(unsigned(krnl_sch_rdData(N_DIM_OFFSET+1 downto N_DIM_OFFSET))) = 2 then -- compare with nDim wg_size_d2 <= to_integer(unsigned(krnl_sch_rdData(WG_SIZE_2_OFFSET+WG_SIZE_W downto WG_SIZE_2_OFFSET))); else wg_size_d2 <= 1; end if; nDim <= to_integer(unsigned(krnl_sch_rdData(N_DIM_OFFSET+1 downto N_DIM_OFFSET))); end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WG_0 then n_wg_d0_m1 <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WG_1 then krnl_infos_we <= '1'; if nDim /= 0 then n_wg_d1_m1 <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); else n_wg_d1_m1 <= (others => '0'); end if; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_WG_2 then krnl_infos_we <= '1'; if nDim = 2 then n_wg_d2_m1 <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); else n_wg_d2_m1 <= (others => '0'); end if; end if; if to_integer(st_prepare_d0) = NEW_KRNL_DESC_N_PARAMS then nParams <= to_integer(unsigned(krnl_sch_rdData(N_PARAMS_OFFSET+N_PARAMS_W-1 downto N_PARAMS_OFFSET))); wg_size <= unsigned(krnl_sch_rdData(WG_SIZE_OFFSET+WG_SIZE_W downto WG_SIZE_OFFSET)); end if; if to_integer(st_prepare_d0) >= PARAMS_OFFSET then params <= unsigned(krnl_sch_rdData(DATA_W-1 downto 0)); krnl_infos_we <= '1'; params_wrAddr <= st_prepare_d0(N_PARAMS_W-1 downto 0); end if; if nrst = '0' then st_prepare <= (others=>'0'); st_prepare_d0 <= (others=>'0'); else st_prepare <= st_prepare_n; st_prepare_d0 <= st_prepare; end if; end if; end process; process(st_prepare, start_prepare, nParams, prepare_params) begin st_prepare_n <= st_prepare; prepare_fin_n <= '0'; case to_integer(st_prepare) is when 0 => if start_prepare = '1' then if prepare_params = '0' then st_prepare_n <= st_prepare + 1; else st_prepare_n <= (st_prepare_n'high => '1', others=>'0'); end if; end if; when others => st_prepare_n <= st_prepare + 1; if st_prepare = (2**(NEW_KRNL_DESC_W-1))+nParams-1 then prepare_fin_n <= '1'; st_prepare_n <= (others=>'0'); else end if; end case; end process; krnl_sch_rdAddr(KRNL_SCH_ADDR_W-1 downto NEW_KRNL_DESC_W) <= std_logic_vector(to_unsigned(krnl_indx_ltchd, NEW_KRNL_INDX_W)); krnl_sch_rdAddr(NEW_KRNL_DESC_W-1 downto 0) <= std_logic_vector(st_prepare_n); --------------------------------------------------------------------------------------------------}}} -- init alu enable -------------------------------------------------------------------------------------------{{{ init_alu_enable: entity init_alu_en_ram generic map( N_RD_PORTS => N_CU )port map( start => start_loc_indcs, finish => alu_en_rdy, clear_finish => start_exec_i, wg_size => wg_size, sch_rqst_n_WFs_m1 => sch_rqst_n_WFs_m1_i, rdData_alu_en => rdData_alu_en, rdAddr_alu_en => rdAddr_alu_en, clk => clk, nrst => nrst ); ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

8858900db7eafa4961077cb21ff0d974

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_6Stations_8Banks_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

4ab1f143beae153f51c54734d96fec51

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_all.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 1; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

aa6adf91dd558d6bdf0af8fd71850cd6

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_float_8ALUs.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data por0s constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

619fe0c8d0adb2f77b0b38bfa3c0ea4e

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_area_estimation.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

366dac64cc17c8bf3e3149d6c1f02107

preusser/q27

src/vhdl/PoC/common/vectors.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Common functions and types -- -- Description: -- ------------------------------------- -- For detailed documentation see below. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.strings.all; package vectors is -- ========================================================================== -- Type declarations -- ========================================================================== -- STD_LOGIC_VECTORs subtype T_SLV_2 is std_logic_vector(1 downto 0); subtype T_SLV_3 is std_logic_vector(2 downto 0); subtype T_SLV_4 is std_logic_vector(3 downto 0); subtype T_SLV_8 is std_logic_vector(7 downto 0); subtype T_SLV_12 is std_logic_vector(11 downto 0); subtype T_SLV_16 is std_logic_vector(15 downto 0); subtype T_SLV_24 is std_logic_vector(23 downto 0); subtype T_SLV_32 is std_logic_vector(31 downto 0); subtype T_SLV_48 is std_logic_vector(47 downto 0); subtype T_SLV_64 is std_logic_vector(63 downto 0); subtype T_SLV_96 is std_logic_vector(95 downto 0); subtype T_SLV_128 is std_logic_vector(127 downto 0); subtype T_SLV_256 is std_logic_vector(255 downto 0); subtype T_SLV_512 is std_logic_vector(511 downto 0); -- STD_LOGIC_VECTOR_VECTORs -- type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR; -- VHDL 2008 syntax - not yet supported by Xilinx type T_SLVV_2 is array(natural range <>) of T_SLV_2; type T_SLVV_3 is array(natural range <>) of T_SLV_3; type T_SLVV_4 is array(natural range <>) of T_SLV_4; type T_SLVV_8 is array(natural range <>) of T_SLV_8; type T_SLVV_12 is array(natural range <>) of T_SLV_12; type T_SLVV_16 is array(natural range <>) of T_SLV_16; type T_SLVV_24 is array(natural range <>) of T_SLV_24; type T_SLVV_32 is array(natural range <>) of T_SLV_32; type T_SLVV_48 is array(natural range <>) of T_SLV_48; type T_SLVV_64 is array(natural range <>) of T_SLV_64; type T_SLVV_128 is array(natural range <>) of T_SLV_128; type T_SLVV_256 is array(natural range <>) of T_SLV_256; type T_SLVV_512 is array(natural range <>) of T_SLV_512; -- STD_LOGIC_MATRIXs type T_SLM is array(natural range <>, natural range <>) of std_logic; -- ATTENTION: -- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave) -- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z')); -- 2. Xilinx iSIM bug: DON'T use myMatrix'range(n) for n >= 2 -- myMatrix'range(2) returns always myMatrix'range(1); see work-around notes below -- -- USAGE NOTES: -- dimension 1 => rows - e.g. Words -- dimension 2 => columns - e.g. Bits/Bytes in a word -- -- WORKAROUND: for Xilinx ISE/iSim -- Version: 14.2 -- Issue: myMatrix'range(n) for n >= 2 returns always myMatrix'range(1) -- ========================================================================== -- Function declarations -- ========================================================================== -- slicing boundary calulations function low (lenvec : T_POSVEC; index : natural) return natural; function high(lenvec : T_POSVEC; index : natural) return natural; -- Assign procedures: assign_* procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural); -- assign vector to complete row procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural); -- assign short vector to row starting at position procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural); -- assign short vector to row in range high:low procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural); -- assign vector to complete column -- ATTENTION: see T_SLM definition for further details and work-arounds -- Matrix to matrix conversion: slm_slice* function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all rows in RowIndex range high:low function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all columns in ColIndex range high:low -- Boolean Operators function "not" (a : t_slm) return t_slm; function "and" (a, b : t_slm) return t_slm; function "or" (a, b : t_slm) return t_slm; function "xor" (a, b : t_slm) return t_slm; function "nand"(a, b : t_slm) return t_slm; function "nor" (a, b : t_slm) return t_slm; function "xnor"(a, b : t_slm) return t_slm; -- Matrix concatenation: slm_merge_* function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM; function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM; -- Matrix to vector conversion: get_* function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector; -- get a matrix column function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector; -- get a matrix row function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector; -- get a matrix row of defined length [length - 1 downto 0] function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector; -- get a sub vector of a matrix row at high:low -- Convert to vector: to_slv function to_slv(slvv : T_SLVV_2) return std_logic_vector; -- convert vector-vector to flatten vector function to_slv(slvv : T_SLVV_4) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_8) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_12) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_16) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_24) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_32) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_64) return std_logic_vector; -- ... function to_slv(slvv : T_SLVV_128) return std_logic_vector; -- ... function to_slv(slm : T_SLM) return std_logic_vector; -- convert matrix to flatten vector -- Convert flat vector to avector-vector: to_slvv_* function to_slvv_4(slv : std_logic_vector) return T_SLVV_4; -- function to_slvv_8(slv : std_logic_vector) return T_SLVV_8; -- function to_slvv_12(slv : std_logic_vector) return T_SLVV_12; -- function to_slvv_16(slv : std_logic_vector) return T_SLVV_16; -- function to_slvv_32(slv : std_logic_vector) return T_SLVV_32; -- function to_slvv_64(slv : std_logic_vector) return T_SLVV_64; -- function to_slvv_128(slv : std_logic_vector) return T_SLVV_128; -- function to_slvv_256(slv : std_logic_vector) return T_SLVV_256; -- function to_slvv_512(slv : std_logic_vector) return T_SLVV_512; -- -- Convert matrix to avector-vector: to_slvv_* function to_slvv_4(slm : T_SLM) return T_SLVV_4; -- function to_slvv_8(slm : T_SLM) return T_SLVV_8; -- function to_slvv_12(slm : T_SLM) return T_SLVV_12; -- function to_slvv_16(slm : T_SLM) return T_SLVV_16; -- function to_slvv_32(slm : T_SLM) return T_SLVV_32; -- function to_slvv_64(slm : T_SLM) return T_SLVV_64; -- function to_slvv_128(slm : T_SLM) return T_SLVV_128; -- function to_slvv_256(slm : T_SLM) return T_SLVV_256; -- function to_slvv_512(slm : T_SLM) return T_SLVV_512; -- -- Convert vector-vector to matrix: to_slm function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM; -- create matrix from vector function to_slm(slvv : T_SLVV_4) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_8) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_12) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_16) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_32) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_48) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_64) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_128) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_256) return T_SLM; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_512) return T_SLM; -- create matrix from vector-vector -- Change vector direction function dir(slvv : T_SLVV_8) return T_SLVV_8; -- Reverse vector elements function rev(slvv : T_SLVV_4) return T_SLVV_4; function rev(slvv : T_SLVV_8) return T_SLVV_8; function rev(slvv : T_SLVV_12) return T_SLVV_12; function rev(slvv : T_SLVV_16) return T_SLVV_16; function rev(slvv : T_SLVV_32) return T_SLVV_32; function rev(slvv : T_SLVV_64) return T_SLVV_64; function rev(slvv : T_SLVV_128) return T_SLVV_128; function rev(slvv : T_SLVV_256) return T_SLVV_256; function rev(slvv : T_SLVV_512) return T_SLVV_512; -- TODO: function resize(slm : T_SLM; size : positive) return T_SLM; -- to_string function to_string(slvv : T_SLVV_8; sep : character := ':') return string; function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string; end package vectors; package body vectors is -- slicing boundary calulations -- ========================================================================== function low(lenvec : T_POSVEC; index : natural) return natural is variable pos : natural := 0; begin for i in lenvec'low to index - 1 loop pos := pos + lenvec(i); end loop; return pos; end function; function high(lenvec : T_POSVEC; index : natural) return natural is variable pos : natural := 0; begin for i in lenvec'low to index loop pos := pos + lenvec(i); end loop; return pos - 1; end function; -- Assign procedures: assign_* -- ========================================================================== procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural) is variable temp : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration begin temp := slv; for i in temp'range loop slm(RowIndex, i) <= temp(i); end loop; end procedure; procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural) is variable temp : std_logic_vector(Position + slv'length - 1 downto Position); begin temp := slv; for i in temp'range loop slm(RowIndex, i) <= temp(i); end loop; end procedure; procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural) is variable temp : std_logic_vector(High downto Low); begin temp := slv; for i in temp'range loop slm(RowIndex, i) <= temp(i); end loop; end procedure; procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural) is variable temp : std_logic_vector(slm'range(1)); begin temp := slv; for i in temp'range loop slm(i, ColIndex) <= temp(i); end loop; end procedure; -- Matrix to matrix conversion: slm_slice* -- ========================================================================== function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM is variable Result : T_SLM(Height - 1 downto 0, Width - 1 downto 0) := (others => (others => '0')); begin for i in 0 to Height - 1 loop for j in 0 to Width - 1 loop Result(i, j) := slm(RowIndex + i, ColIndex + j); end loop; end loop; return Result; end function; function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM is variable Result : T_SLM(High - Low downto 0, slm'length(2) - 1 downto 0) := (others => (others => '0')); begin for i in 0 to High - Low loop for j in 0 to slm'length(2) - 1 loop Result(i, j) := slm(Low + i, slm'low(2) + j); end loop; end loop; return Result; end function; function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM is variable Result : T_SLM(slm'length(1) - 1 downto 0, High - Low downto 0) := (others => (others => '0')); begin for i in 0 to slm'length(1) - 1 loop for j in 0 to High - Low loop Result(i, j) := slm(slm'low(1) + i, Low + j); end loop; end loop; return Result; end function; -- Boolean Operators function "not"(a : t_slm) return t_slm is variable res : t_slm(a'range(1), a'range(2)); begin for i in res'range(1) loop for j in res'range(2) loop res(i, j) := not a(i, j); end loop; end loop; return res; end function; function "and"(a, b : t_slm) return t_slm is variable bb, res : t_slm(a'range(1), a'range(2)); begin bb := b; for i in res'range(1) loop for j in res'range(2) loop res(i, j) := a(i, j) and bb(i, j); end loop; end loop; return res; end function; function "or"(a, b : t_slm) return t_slm is variable bb, res : t_slm(a'range(1), a'range(2)); begin bb := b; for i in res'range(1) loop for j in res'range(2) loop res(i, j) := a(i, j) or bb(i, j); end loop; end loop; return res; end function; function "xor"(a, b : t_slm) return t_slm is variable bb, res : t_slm(a'range(1), a'range(2)); begin bb := b; for i in res'range(1) loop for j in res'range(2) loop res(i, j) := a(i, j) xor bb(i, j); end loop; end loop; return res; end function; function "nand"(a, b : t_slm) return t_slm is begin return not(a and b); end function; function "nor"(a, b : t_slm) return t_slm is begin return not(a or b); end function; function "xnor"(a, b : t_slm) return t_slm is begin return not(a xor b); end function; -- Matrix concatenation: slm_merge_* function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is constant ROWS : positive := slm1'length(1) + slm2'length(1); constant COLUMNS : positive := slm1'length(2); variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0); begin for i in slm1'range(1) loop for j in slm1'low(2) to slm1'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slm(i, j) := slm1(i, j); end loop; end loop; for i in slm2'range(1) loop for j in slm2'low(2) to slm2'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slm(slm1'length(1) + i, j) := slm2(i, j); end loop; end loop; return slm; end function; function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is constant ROWS : positive := slm1'length(1); constant COLUMNS : positive := slm1'length(2) + slm2'length(2); variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0); begin for i in slm1'range(1) loop for j in slm1'low(2) to slm1'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slm(i, j) := slm1(i, j); end loop; for j in slm2'low(2) to slm2'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slm(i, slm1'length(2) + j) := slm2(i, j); end loop; end loop; return slm; end function; -- Matrix to vector conversion: get_* -- ========================================================================== -- get a matrix column function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector is variable slv : std_logic_vector(slm'range(1)); begin for i in slm'range(1) loop slv(i) := slm(i, ColIndex); end loop; return slv; end function; -- get a matrix row function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector is variable slv : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration begin for i in slv'range loop slv(i) := slm(RowIndex, i); end loop; return slv; end function; -- get a matrix row of defined length [length - 1 downto 0] function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector is begin return get_row(slm, RowIndex, (Length - 1), 0); end function; -- get a sub vector of a matrix row at high:low function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector is variable slv : std_logic_vector(High downto Low); begin for i in slv'range loop slv(i) := slm(RowIndex, i); end loop; return slv; end function; -- Convert to vector: to_slv -- ========================================================================== -- convert vector-vector to flatten vector function to_slv(slvv : T_SLVV_2) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 2) - 1 downto 0); begin for i in slvv'range loop slv((i * 2) + 1 downto (i * 2)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_4) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 4) - 1 downto 0); begin for i in slvv'range loop slv((i * 4) + 3 downto (i * 4)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_8) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 8) - 1 downto 0); begin for i in slvv'range loop slv((i * 8) + 7 downto (i * 8)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_12) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 12) - 1 downto 0); begin for i in slvv'range loop slv((i * 12) + 11 downto (i * 12)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_16) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 16) - 1 downto 0); begin for i in slvv'range loop slv((i * 16) + 15 downto (i * 16)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_24) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 24) - 1 downto 0); begin for i in slvv'range loop slv((i * 24) + 23 downto (i * 24)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_32) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 32) - 1 downto 0); begin for i in slvv'range loop slv((i * 32) + 31 downto (i * 32)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_64) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 64) - 1 downto 0); begin for i in slvv'range loop slv((i * 64) + 63 downto (i * 64)) := slvv(i); end loop; return slv; end function; function to_slv(slvv : T_SLVV_128) return std_logic_vector is variable slv : std_logic_vector((slvv'length * 128) - 1 downto 0); begin for i in slvv'range loop slv((i * 128) + 127 downto (i * 128)) := slvv(i); end loop; return slv; end function; -- convert matrix to flatten vector function to_slv(slm : T_SLM) return std_logic_vector is variable slv : std_logic_vector((slm'length(1) * slm'length(2)) - 1 downto 0); begin for i in slm'range(1) loop for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration slv((i * slm'length(2)) + j) := slm(i, j); end loop; end loop; return slv; end function; -- Convert flat vector to a vector-vector: to_slvv_* -- ========================================================================== -- create vector-vector from vector (4 bit) function to_slvv_4(slv : std_logic_vector) return T_SLVV_4 is variable Result : T_SLVV_4((slv'length / 4) - 1 downto 0); begin if ((slv'length mod 4) /= 0) then report "to_slvv_4: width mismatch - slv'length is no multiple of 4 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 4) + 3 downto (i * 4)); end loop; return Result; end function; -- create vector-vector from vector (8 bit) function to_slvv_8(slv : std_logic_vector) return T_SLVV_8 is variable Result : T_SLVV_8((slv'length / 8) - 1 downto 0); begin if ((slv'length mod 8) /= 0) then report "to_slvv_8: width mismatch - slv'length is no multiple of 8 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 8) + 7 downto (i * 8)); end loop; return Result; end function; -- create vector-vector from vector (12 bit) function to_slvv_12(slv : std_logic_vector) return T_SLVV_12 is variable Result : T_SLVV_12((slv'length / 12) - 1 downto 0); begin if ((slv'length mod 12) /= 0) then report "to_slvv_12: width mismatch - slv'length is no multiple of 12 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 12) + 11 downto (i * 12)); end loop; return Result; end function; -- create vector-vector from vector (16 bit) function to_slvv_16(slv : std_logic_vector) return T_SLVV_16 is variable Result : T_SLVV_16((slv'length / 16) - 1 downto 0); begin if ((slv'length mod 16) /= 0) then report "to_slvv_16: width mismatch - slv'length is no multiple of 16 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 16) + 15 downto (i * 16)); end loop; return Result; end function; -- create vector-vector from vector (32 bit) function to_slvv_32(slv : std_logic_vector) return T_SLVV_32 is variable Result : T_SLVV_32((slv'length / 32) - 1 downto 0); begin if ((slv'length mod 32) /= 0) then report "to_slvv_32: width mismatch - slv'length is no multiple of 32 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 32) + 31 downto (i * 32)); end loop; return Result; end function; -- create vector-vector from vector (64 bit) function to_slvv_64(slv : std_logic_vector) return T_SLVV_64 is variable Result : T_SLVV_64((slv'length / 64) - 1 downto 0); begin if ((slv'length mod 64) /= 0) then report "to_slvv_64: width mismatch - slv'length is no multiple of 64 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 64) + 63 downto (i * 64)); end loop; return Result; end function; -- create vector-vector from vector (128 bit) function to_slvv_128(slv : std_logic_vector) return T_SLVV_128 is variable Result : T_SLVV_128((slv'length / 128) - 1 downto 0); begin if ((slv'length mod 128) /= 0) then report "to_slvv_128: width mismatch - slv'length is no multiple of 128 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 128) + 127 downto (i * 128)); end loop; return Result; end function; -- create vector-vector from vector (256 bit) function to_slvv_256(slv : std_logic_vector) return T_SLVV_256 is variable Result : T_SLVV_256((slv'length / 256) - 1 downto 0); begin if ((slv'length mod 256) /= 0) then report "to_slvv_256: width mismatch - slv'length is no multiple of 256 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 256) + 255 downto (i * 256)); end loop; return Result; end function; -- create vector-vector from vector (512 bit) function to_slvv_512(slv : std_logic_vector) return T_SLVV_512 is variable Result : T_SLVV_512((slv'length / 512) - 1 downto 0); begin if ((slv'length mod 512) /= 0) then report "to_slvv_512: width mismatch - slv'length is no multiple of 512 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if; for i in Result'range loop Result(i) := slv((i * 512) + 511 downto (i * 512)); end loop; return Result; end function; -- Convert matrix to avector-vector: to_slvv_* -- ========================================================================== -- create vector-vector from matrix (4 bit) function to_slvv_4(slm : T_SLM) return T_SLVV_4 is variable Result : T_SLVV_4(slm'range(1)); begin if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (8 bit) function to_slvv_8(slm : T_SLM) return T_SLVV_8 is variable Result : T_SLVV_8(slm'range(1)); begin if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (12 bit) function to_slvv_12(slm : T_SLM) return T_SLVV_12 is variable Result : T_SLVV_12(slm'range(1)); begin if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (16 bit) function to_slvv_16(slm : T_SLM) return T_SLVV_16 is variable Result : T_SLVV_16(slm'range(1)); begin if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (32 bit) function to_slvv_32(slm : T_SLM) return T_SLVV_32 is variable Result : T_SLVV_32(slm'range(1)); begin if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (64 bit) function to_slvv_64(slm : T_SLM) return T_SLVV_64 is variable Result : T_SLVV_64(slm'range(1)); begin if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (128 bit) function to_slvv_128(slm : T_SLM) return T_SLVV_128 is variable Result : T_SLVV_128(slm'range(1)); begin if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (256 bit) function to_slvv_256(slm : T_SLM) return T_SLVV_256 is variable Result : T_SLVV_256(slm'range); begin if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- create vector-vector from matrix (512 bit) function to_slvv_512(slm : T_SLM) return T_SLVV_512 is variable Result : T_SLVV_512(slm'range(1)); begin if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if; for i in slm'range(1) loop Result(i) := get_row(slm, i); end loop; return Result; end function; -- Convert vector-vector to matrix: to_slm -- ========================================================================== -- create matrix from vector function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM is variable slm : T_SLM(ROWS - 1 downto 0, COLS - 1 downto 0); begin for i in 0 to ROWS - 1 loop for j in 0 to COLS - 1 loop slm(i, j) := slv((i * COLS) + j); end loop; end loop; return slm; end function; -- create matrix from vector-vector function to_slm(slvv : T_SLVV_4) return T_SLM is variable slm : T_SLM(slvv'range, 3 downto 0); begin for i in slvv'range loop for j in T_SLV_4'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_8) return T_SLM is -- variable test : STD_LOGIC_VECTOR(T_SLV_8'range); -- variable slm : T_SLM(slvv'range, test'range); -- BUG: iSIM 14.5 cascaded 'range accesses let iSIM break down -- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimension 2 variable slm : T_SLM(slvv'range, 7 downto 0); -- WORKAROUND: use constant range begin -- report "slvv: slvv.length=" & INTEGER'image(slvv'length) & " slm.dim0.length=" & INTEGER'image(slm'length(1)) & " slm.dim1.length=" & INTEGER'image(slm'length(2)) severity NOTE; -- report "T_SLV_8: .length=" & INTEGER'image(T_SLV_8'length) & " .high=" & INTEGER'image(T_SLV_8'high) & " .low=" & INTEGER'image(T_SLV_8'low) severity NOTE; -- report "test: test.length=" & INTEGER'image(test'length) & " .high=" & INTEGER'image(test'high) & " .low=" & INTEGER'image(test'low) severity NOTE; for i in slvv'range loop for j in T_SLV_8'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_12) return T_SLM is variable slm : T_SLM(slvv'range, 11 downto 0); begin for i in slvv'range loop for j in T_SLV_12'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_16) return T_SLM is variable slm : T_SLM(slvv'range, 15 downto 0); begin for i in slvv'range loop for j in T_SLV_16'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_32) return T_SLM is variable slm : T_SLM(slvv'range, 31 downto 0); begin for i in slvv'range loop for j in T_SLV_32'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_48) return T_SLM is variable slm : T_SLM(slvv'range, 47 downto 0); begin for i in slvv'range loop for j in T_SLV_48'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_64) return T_SLM is variable slm : T_SLM(slvv'range, 63 downto 0); begin for i in slvv'range loop for j in T_SLV_64'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_128) return T_SLM is variable slm : T_SLM(slvv'range, 127 downto 0); begin for i in slvv'range loop for j in T_SLV_128'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_256) return T_SLM is variable slm : T_SLM(slvv'range, 255 downto 0); begin for i in slvv'range loop for j in T_SLV_256'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; function to_slm(slvv : T_SLVV_512) return T_SLM is variable slm : T_SLM(slvv'range, 511 downto 0); begin for i in slvv'range loop for j in T_SLV_512'range loop slm(i, j) := slvv(i)(j); end loop; end loop; return slm; end function; -- Change vector direction -- ========================================================================== function dir(slvv : T_SLVV_8) return T_SLVV_8 is variable Result : T_SLVV_8(slvv'reverse_range); begin Result := slvv; return Result; end function; -- Reverse vector elements function rev(slvv : T_SLVV_4) return T_SLVV_4 is variable Result : T_SLVV_4(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_8) return T_SLVV_8 is variable Result : T_SLVV_8(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_12) return T_SLVV_12 is variable Result : T_SLVV_12(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_16) return T_SLVV_16 is variable Result : T_SLVV_16(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_32) return T_SLVV_32 is variable Result : T_SLVV_32(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_64) return T_SLVV_64 is variable Result : T_SLVV_64(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_128) return T_SLVV_128 is variable Result : T_SLVV_128(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_256) return T_SLVV_256 is variable Result : T_SLVV_256(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; function rev(slvv : T_SLVV_512) return T_SLVV_512 is variable Result : T_SLVV_512(slvv'range); begin for i in slvv'low to slvv'high loop Result(slvv'high - i) := slvv(i); end loop; return Result; end function; -- Resize functions -- ========================================================================== -- Resizes the vector to the specified length. Input vectors larger than the specified size are truncated from the left side. Smaller input -- vectors are extended on the left by the provided fill value (default: '0'). Use the resize functions of the numeric_std package for -- value-preserving resizes of the signed and unsigned data types. function resize(slm : T_SLM; size : positive) return T_SLM is variable Result : T_SLM(size - 1 downto 0, slm'high(2) downto slm'low(2)) := (others => (others => '0')); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration begin for i in slm'range(1) loop for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration Result(i, j) := slm(i, j); end loop; end loop; return Result; end function; function to_string(slvv : T_SLVV_8; sep : character := ':') return string is constant hex_len : positive := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1); variable Result : string(1 to hex_len) := (others => sep); variable pos : positive := 1; begin for i in slvv'range loop Result(pos to pos + 1) := to_string(slvv(i), 'h'); pos := pos + ite((sep = C_POC_NUL), 2, 3); end loop; return Result; end function; function to_string_bin(slm : T_SLM; groups : positive := 4; format : character := 'h') return string is variable PerLineOverheader : positive := div_ceil(slm'length(2), groups); variable Result : string(1 to (slm'length(1) * (slm'length(2) + PerLineOverheader)) + 10); variable Writer : positive; variable GroupCounter : natural; begin Result := (others => C_POC_NUL); Result(1) := LF; Writer := 2; GroupCounter := 0; for i in slm'low(1) to slm'high(1) loop for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration Result(Writer) := to_char(slm(i, j)); Writer := Writer + 1; GroupCounter := GroupCounter + 1; if (GroupCounter = groups) then Result(Writer) := ' '; Writer := Writer + 1; GroupCounter := 0; end if; end loop; Result(Writer - 1) := LF; GroupCounter := 0; end loop; return str_trim(Result); end function; function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string is begin if (format = 'b') then return to_string_bin(slm, groups); else return "Format not supported."; end if; end function; end package body;

agpl-3.0

4ca7955c9b7ef61bdc167fb4f2439ad3

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ab1de88cfdb6373168238a28fc11e4bf

preusser/q27

src/vhdl/PoC/sync/sync_Bits.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Patrick Lehmann -- -- Module: Synchronizes a flag signal across clock-domain boundaries -- -- Description: -- ------------------------------------ -- This module synchronizes multiple flag bits from clock-domain 'Clock1' to -- clock-domain 'Clock'. The clock-domain boundary crossing is done by two -- synchronizer D-FFs. All bits are independent from each other. If a known -- vendor like Altera or Xilinx are recognized, a vendor specific -- implementation is chosen. -- -- ATTENTION: -- Use this synchronizer only for long time stable signals (flags). -- -- CONSTRAINTS: -- General: -- Please add constraints for meta stability to all '_meta' signals and -- timing ignore constraints to all '_async' signals. -- -- Xilinx: -- In case of a Xilinx device, this module will instantiate the optimized -- module PoC.xil.SyncBits. Please attend to the notes of xil_SyncBits.vhdl. -- -- Altera sdc file: -- TODO -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.STD_LOGIC_1164.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.sync.all; entity sync_Bits is generic ( BITS : POSITIVE := 1; -- number of bit to be synchronized INIT : STD_LOGIC_VECTOR := x"00000000" -- initialitation bits ); port ( Clock : in STD_LOGIC; -- <Clock> output clock domain Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @async: input bits Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock: output bits ); end entity; architecture rtl of sync_Bits is constant INIT_I : STD_LOGIC_VECTOR := resize(descend(INIT), BITS); begin genGeneric : if ((VENDOR /= VENDOR_ALTERA) and (VENDOR /= VENDOR_XILINX)) generate attribute ASYNC_REG : STRING; attribute SHREG_EXTRACT : STRING; begin gen : for i in 0 to BITS - 1 generate signal Data_async : STD_LOGIC; signal Data_meta : STD_LOGIC := INIT_I(i); signal Data_sync : STD_LOGIC := INIT_I(i); -- Mark register DataSync_async's input as asynchronous and ignore timings (TIG) attribute ASYNC_REG of Data_meta : signal is "TRUE"; -- Prevent XST from translating two FFs into SRL plus FF attribute SHREG_EXTRACT of Data_meta : signal is "NO"; attribute SHREG_EXTRACT of Data_sync : signal is "NO"; begin Data_async <= Input(i); process(Clock) begin if rising_edge(Clock) then Data_meta <= Data_async; Data_sync <= Data_meta; end if; end process; Output(i) <= Data_sync; end generate; end generate; -- use dedicated and optimized 2 D-FF synchronizer for Altera FPGAs genAltera : if (VENDOR = VENDOR_ALTERA) generate sync : sync_Bits_Altera generic map ( BITS => BITS, INIT => INIT_I ) port map ( Clock => Clock, Input => Input, Output => Output ); end generate; -- use dedicated and optimized 2 D-FF synchronizer for Xilinx FPGAs genXilinx : if (VENDOR = VENDOR_XILINX) generate sync : sync_Bits_Xilinx generic map ( BITS => BITS, INIT => INIT_I ) port map ( Clock => Clock, Input => Input, Output => Output ); end generate; end architecture;

agpl-3.0

2d365783d680ac209a6590014cb4f072

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_6Stations_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

33c740904e4551277df08a5557debe9e

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fslt.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

d00b1d3c4b3182b8db9315be37840808

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

d3ce749ccb0c9e7343442d10cb4eca40

malkadi/FGPU

RTL/lmem.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity lmem is --{{{ port ( clk : in std_logic; rqst, we : in std_logic; -- stage 0 alu_en : in std_logic_vector(CV_SIZE-1 downto 0); wrData : in SLV32_ARRAY(CV_SIZE-1 downto 0); rdData : out SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- stage 2 rdData_v : out std_logic := '0'; -- stage 2 rdData_rd_addr : out unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); rdData_alu_en : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); sp : in unsigned(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0); rd_addr : in unsigned(REG_FILE_W-1 downto 0); nrst : in std_logic ); end lmem; --}}} architecture basic of lmem is type lmemory_type is array (0 to 2**LMEM_ADDR_W-1) of std_logic_vector(CV_SIZE*DATA_W-1 downto 0); signal lmemory : lmemory_type := (others=>(others=>'0')); signal lmemory_addr : unsigned(LMEM_ADDR_W-1 downto 0) := (others=>'0'); signal phase : unsigned(PHASE_W-1 downto 0) := (others=>'0'); signal rdData_n : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal alu_en_vec : alu_en_vec_type(1 downto 0) := (others=>(others=>'0')); signal rd_addr_vec : reg_addr_array(1 downto 0) := (others=>(others=>'0')); signal rdData_v_p0 : std_logic := '0'; begin -- lmemory ----------------------------------------------------------------------------------------------{{{ lmemory_addr(LMEM_ADDR_W-1 downto LMEM_ADDR_W-PHASE_W) <= phase; lmemory_addr(LMEM_ADDR_W-PHASE_W-1 downto LMEM_ADDR_W-PHASE_W-N_WF_CU_W) <= rd_addr(WI_REG_ADDR_W+N_WF_CU_W-1 downto WI_REG_ADDR_W); lmemory_addr(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0) <= sp; process(clk) begin if rising_edge(clk) then for i in 0 to CV_SIZE-1 loop rdData_n(i) <= lmemory(to_integer(lmemory_addr))((i+1)*DATA_W-1 downto i*DATA_W); -- @ 1 end loop; rdData <= rdData_n; -- @ 2 if we = '1' then for i in 0 to CV_SIZE-1 loop if alu_en(i) = '1' then lmemory(to_integer(lmemory_addr))((i+1)*DATA_W-1 downto i*DATA_W) <= wrData(i); end if; end loop; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- control ----------------------------------------------------------------------------------------------{{{ rdData_alu_en <= alu_en_vec(0); rdData_rd_addr <= rd_addr_vec(0); process(clk) begin if rising_edge(clk) then alu_en_vec(alu_en_vec'high) <= alu_en; alu_en_vec(alu_en_vec'high-1 downto 0) <= alu_en_vec(alu_en_vec'high downto 1); rd_addr_vec(rd_addr_vec'high) <= rd_addr; rd_addr_vec(rd_addr_vec'high-1 downto 0) <= rd_addr_vec(rd_addr_vec'high downto 1); rdData_v <= rdData_v_p0; if nrst = '0' then phase <= (others=>'0'); rdData_v_p0 <= '0'; else if rqst = '1' then phase <= phase + 1; end if; if phase = (phase'reverse_range=>'0') then rdData_v_p0 <= '0'; end if; if rqst = '1' and we = '0' then if phase = (phase'reverse_range=>'0') then rdData_v_p0 <= '1'; end if; end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

c004bd8e9f0943b1588e5681d125109a

Kinxil/VHDL_Projects

Mandelbrot/Zoom.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library WORK; use WORK.CONSTANTS.ALL; use WORK.FUNCTIONS.ALL; entity Zoom is Port ( bleft : in STD_LOGIC; bright : in STD_LOGIC; bup : in STD_LOGIC; bdwn : in STD_LOGIC; bctr : in STD_LOGIC; clock : in STD_LOGIC; reset : in STD_LOGIC; ce_param : in std_logic; x_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0); y_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0); step : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0)); end Zoom; architecture Behavioral of Zoom is signal s_xstart, s_ystart, s_step : signed(XY_RANGE-1 downto 0); begin process(clock, ce_param, reset, bup, bdwn, bleft, bright, bctr) begin if reset = '1' then s_xstart <= x"E0000000"; s_ystart <= x"F0000000"; s_step <= x"00111111"; --Mandelbrot -2 1 x -1 1 sur 640x480 elsif ((rising_edge(clock)) and (ce_param='1')) then -- TODO : Centrer le zoom if bctr = '1' then if bup = '1' then s_xstart <= s_xstart + (mult(s_step srl 2,x"28000000",FIXED) sll 8); s_ystart <= s_ystart + (mult(s_step srl 2,x"1E000000",FIXED) sll 8); s_step <= s_step srl 1; --Zoom x2> réduction du step elsif bdwn = '1' then s_xstart <= s_xstart + not (mult(s_step srl 1,x"28000000",FIXED) sll 8) + 1; s_ystart <= s_ystart + not (mult(s_step srl 1,x"1E000000",FIXED) sll 8) +1; s_step <= s_step sll 1; --Dezoom x0.5> augmentation du step end if; elsif bup = '1' then s_ystart <= s_ystart + (s_step sll 7); elsif bdwn = '1' then s_ystart <= s_ystart - (s_step sll 7); end if; if bleft = '1' then s_xstart <= s_xstart + (s_step sll 7); elsif bright = '1' then s_xstart <= s_xstart - (s_step sll 7); end if; end if; end process; x_start <= STD_LOGIC_VECTOR(s_xstart); y_start <= STD_LOGIC_VECTOR(s_ystart); step <= STD_LOGIC_VECTOR(s_step); end Behavioral;

gpl-3.0

dc0c9a87dd2fc2d236f92db6dd961ac1

preusser/q27

src/vhdl/queens/queens_slice.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <[email protected]> -- Benedikt Reuter <[email protected]> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity queens_slice is generic ( N : positive; -- size of field L : natural -- number of preplaced outer rings ); port ( -- Global Clock clk : in std_logic; rst : in std_logic; -- Inputs (strobed) start : in std_logic; -- Strobe for Start BH_l : in std_logic_vector(0 to N-2*L-1); -- Blocking for leftmost Column BU_l : in std_logic_vector(0 to 2*N-4*L-2); BD_l : in std_logic_vector(0 to 2*N-4*L-2); BV_l : in std_logic_vector(0 to N-2*L-1); -- Output Strobes sol : out std_logic; done : out std_logic ); end queens_slice; library IEEE; use IEEE.numeric_std.all; architecture rtl of queens_slice is --------------------------------------------------------------------------- -- Matrix to iterate through -- These types are plain ugly but the multidiemsional tMatrix(<>, <>) -- is not slicable. Thus, these types are still better than lots of -- generate loops working through the columns. subtype tColumn is std_logic_vector(L to N-L-1); type tField is array(L to N-L-1) of tColumn; -- Placed Queen Matrix signal QN : tField := (others => (others => '-')); component arbit_forward generic ( N : positive -- Length of Token Chain ); port ( tin : in std_logic; -- Fed Token have : in std_logic_vector(0 to N-1); -- Token Owner pass : in std_logic_vector(0 to N-1); -- Token Passers grnt : out std_logic_vector(0 to N-1); -- Token Output tout : out std_logic -- Unused Token ); end component; -- Blocking Signals signal BH : std_logic_vector(L to N-L-1) := (others => '-'); -- Window: L to N-L-1 signal BV : std_logic_vector(L to N-L-1) := (others => '-'); -- Window: L -- put rotates left signal BU : std_logic_vector(2*L to 2*N-2*L-2) := (others => '-'); -- Window: N-1 to 2*N-2*L-2 -- put rotates right signal BD : std_logic_vector(2*L to 2*N-2*L-2) := (others => '-'); -- Window: 2*L to N-1 -- put rotates left signal s : std_logic_vector(L to N-L-1); signal put : std_logic; begin assert false report LF& "Queens@TUD Solver Slice [N="&integer'image(N)&", L="&integer'image(L)&']' &LF& "Copyright (C) 2015-2016 Thomas B. Preusser <[email protected]> " &LF& " Benedikt Reuter <[email protected]>" &LF& "This design is free software, and you are welcome to redistribute it " &LF& "under the conditions of the GPL version 3. " &LF& "It comes with ABSOLUTELY NO WARRANTY. " &LF& "For details see the notice in the file COPYING."&LF severity note; ---------------------------------------------------------------------------- -- Queen Matrix process(clk) begin if rising_edge(clk) then if put = '1' then QN(L to N-L-2) <= QN(L+1 to N-L-1); else QN(L to N-L-2) <= tColumn'(tColumn'range => '-') & QN(L to N-L-3); end if; end if; end process; ---------------------------------------------------------------------------- -- Blocking Signals process(clk) variable b : std_logic_vector(2*L to 2*N-2*L-2); begin if rising_edge(clk) then -- Initialization if start = '1' then BH <= BH_l; BV <= BV_l; BU <= BU_l; BD <= BD_l; else -- In Progress if put = '1' then -- Add placed Queen BH <= BH or s; BV <= BV(BV'left+1 to BV'right) & BV(BV'left); b := BU(BU'left to N-2) & (BU(N-1 to BU'right) or s); BU <= b(b'right) & b(b'left to b'right-1); b := (BD(BD'left to N-1) or s) & BD(N to BD'right); BD <= b(b'left+1 to b'right) & b(b'left); else -- Clear Queen BH <= BH and not QN(N-L-2); BV <= BV(BV'right) & BV(BV'left to BV'right-1); b := BU(BU'left+1 to BU'right) & BU(BU'left); BU <= b(b'left to N-2) & (b(N-1 to b'right) and not QN(N-L-2)); b := BD(BD'right) & BD(BD'left to BD'right-1); BD <= (b(b'left to N-1) and not QN(N-L-2)) & b(N to b'right); end if; end if; end if; end process; ---------------------------------------------------------------------------- -- Placement Calculation blkPlace : block -- State signal CS : std_logic_vector(L to N-L-1) := (others => '0'); -- Column Front Selector signal Ins : std_logic := '-'; -- Direction signal H : std_logic_vector(L to N-L-1) := (others => '-'); -- Last Placement in active Col -- Combined Blocking signal pass : std_logic_vector(L to N-L-1); signal tout : std_logic; begin -- Combine Blocking Signals pass <= BH or BD(2*L to N-1) or BU(N-1 to 2*N-2*L-2) when BV(L) = '0' else (others => '1'); col : arbit_forward generic map ( N => N-2*L ) port map ( tin => Ins, have => H, pass => pass, grnt => s, tout => tout ); QN(N-L-1) <= s; -- Column Front Selector, a shift-based counter with: process(clk) begin if rising_edge(clk) then if rst = '1' then CS <= (others => '0'); elsif start = '1' then CS <= (others => '0'); CS(CS'left) <= '1'; else if put = '1' then CS <= '0' & CS(CS'left to CS'right-1); else CS <= CS(CS'left+1 to CS'right) & '0'; end if; end if; end if; end process; -- Direction Control process(clk) begin if rising_edge(clk) then if start = '1' then H <= (others => '0'); Ins <= not BV_l(BV_l'left); elsif put = '1' then H <= (others => '0'); Ins <= not BV(L+1); else H <= QN(N-L-2); Ins <= BV(BV'right); end if; end if; end process; -- Control put <= (not tout) and not CS(CS'right); -- Outputs process(clk) begin if rising_edge(clk) then if rst = '1' or start = '1' then sol <= '0'; done <= '0'; else sol <= (not tout) and CS(CS'right); done <= tout and CS(CS'left); end if; end if; end process; end block blkPlace; end rtl;

agpl-3.0

e35d2161ae65d392f842e670c457abb7

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_synth.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block KWVujtFtbw2d3/xo1vIOEwFbjfeUp9+LiAOLaVI0YOyvz7SGsiVFnnecIKH6LMaBGbmqJwypQ3ho hUJUXG7oeg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QlSlzBPpn2RO2nmaEL2fz9rmzwO0yDVwrWv7lQUEYRWypJ9MhVr2icMJgfDllwNeh752IVAvHfu5 1DqlBXy4RN268XSRRvWwZVkyCibbFrBD5gLLVrX5/LhrGH+VbBo3ca57Td+b4JmoTIHzjewhBFK0 07J2/uAi3nDn9hQG7m8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block N7Vl1+JEpjWDLeSFRqDioddAogxF8TeXLnQrr3ffCBlkfrbnKyHo7n3nYMT2CgAK8qjLViq2bi2J p2Ij/AJ6t8JZNKepVq2fhxo2eyzU4tE8SKNtPqOv3j1aWUpmq73uRDewpv1Kj9/r4yP3csQXBgGY Kys/i9LiLIRFFKop/08nhTTOlpmBAZb/BtKhq/5vSxOfdoPrBlwwgIKJwDkwPcbqqAbXWTMY6ehf FN0S7KEWvq2TDeG32O5bZ0YTZLnPzHfhxUE0wowVvXdiseZJ8+IClAJDnB3owq4wSI578oyeVM5l KvRfHaQ6BXgMwvxtSljoo5nAn0WWi6EQ9ltr0Q== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block MW2/vR6BjDsekINPI5JlK8VQ7uMy/SHABv/a7DoboW9d+p0rjHCd3jqdFCM5SxCubk6+yTiKguoa Uq1nTIoCk/woIauS11brot4t4RHEbRy9y9YHezmtfj4zNhhgG06oD1Aorh9hd6WPLO6Zjv78l4J8 xdOFfGo1BX+v8lRHR/4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Veh9j/fHCHllxA/7Gidu4fcWHIjPSuh9FU1gLxrdqbqnlm+XRejKfn/4II23RCKOsSIS1d+0WSYj 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end_protected

mit

b7e3262438dd4d5fe57171dd1b318d5e

malkadi/FGPU

RTL/axi_controllers.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; use ieee.std_logic_textio.all; use std.textio.all; ---------------------------------------------------------------------------------------------------------}}} entity axi_controllers is port( -- {{{ -- to tag controller ---- axi read control axi_rdAddr : in gmem_addr_array_no_bank(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); wr_fifo_go : in std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); wr_fifo_free : out std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); --free ports have to respond to go ports immediately (in one clock cycle) ---- axi write controls axi_wrAddr : in gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_writer_go : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_writer_free : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_writer_id : in std_logic_vector(N_TAG_MANAGERS_W-1 downto 0) := (others=>'0'); axi_writer_ack : out std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- high for just one clock cycle -- to cache controller wr_fifo_cache_rqst : out std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); rd_fifo_cache_rqst : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); wr_fifo_cache_ack : in std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); rd_fifo_cache_ack : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); wr_fifo_rqst_addr : out cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); rd_fifo_rqst_addr : out cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); wr_fifo_dout : out cache_word_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); cache_dob : in std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); rd_fifo_din_v : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); ---- be signals fifo_be_din : in std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); -- axi signals {{{ --Read address channel axi_araddr : out GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_arvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_arready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_arid : out id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- Read data channel axi_rdata : in gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_rlast : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rvalid : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rready : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rid : in id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- write address channel axi_awaddr : out GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_awvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_awready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_awid : out id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- write data channel axi_wdata : out gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_wstrb : out gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_wlast : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); -- write response channel axi_bvalid : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_bready : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_bid : in id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); --}}} clk, nrst : std_logic ); -- }}} end entity; architecture basic of axi_controllers is -- internal signals {{{ signal axi_arvalid_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_rready_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_awvalid_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_free_i : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_araddr_i : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_arid_i : id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_cache_rqst_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_rqst_addr_i : cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_rqst_addr_i : cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wvalid_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); -- }}} -- functions & constants {{{ function distribute_fifos_on_axis (n_fifos: integer; n_axis: integer) return nat_array is variable res: nat_array(n_fifos-1 downto 0) := (others=>0); variable axi_indx: integer range 0 to n_axis-1 := 0; begin for i in 0 to n_fifos-1 loop res(i) := axi_indx; if axi_indx /= n_axis-1 then axi_indx := axi_indx + 1; else axi_indx := 0; end if; end loop; return res; end; function axi_wr_fifos_indcs(n_axis: natural; n_fifos_axi: natural) return nat_2d_array is variable res: nat_2d_array(n_axis-1 downto 0, n_fifos_axi-1 downto 0) := (others=>(others=>0)); begin for i in 0 to n_axis-1 loop for j in 0 to n_fifos_axi-1 loop res(i,j) := i+j*n_axis; end loop; end loop; return res; end function; function find_fifo_indx (n_fifos: integer; n_axis: integer) return nat_array is variable res: nat_array(n_fifos-1 downto 0) := (others=>0); begin for i in 0 to n_fifos-1 loop res(i) := i / n_axis ; end loop; return res; end; constant c_wr_fifo_axi_indx : nat_array(N_WR_FIFOS-1 downto 0) := distribute_fifos_on_axis(N_WR_FIFOS, N_AXI); -- fifo -> axi constant c_axi_wr_fifos : nat_2d_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := axi_wr_fifos_indcs(N_AXI, N_WR_FIFOS_AXI); -- axi -> fifo constant c_wr_fifo_indx : nat_array(N_WR_FIFOS-1 downto 0) := find_fifo_indx(N_WR_FIFOS, N_AXI); -- 0 <= fifo indx < N_WR_FIFOS_AXI-1 -- }}} -- axi interfaces {{{ type st_addr_channel is (idle, active); type st_addr_channel_array is array(natural range <>) of st_addr_channel; signal st_ar, st_ar_n : st_addr_channel_array(N_AXI-1 downto 0) := (others=>idle); signal axi_arvalid_n, axi_rready_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_free_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_araddr_n : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_set_araddr_ack : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_set_araddr_ack_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_arid_n : id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_writer_free_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); -- }}} -- a fifo can write (wr_fifo) the cache or can read (rd_fifo) from the cache -- write fifos (read axi channels) {{{ type st_wr_fifo_type is (idle, send_address, get_data, wait_empty, wait_for_writing_cache, wait2); type st_wr_fifo_array is array (natural range <>) of st_wr_fifo_type; signal st_wr_fifo, st_wr_fifo_n : st_wr_fifo_array(N_WR_FIFOS-1 downto 0) := (others=>idle); signal wr_fifo_rqst_addr_n : cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_push, wr_fifo_push_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal wr_fifo_set_araddr : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal wr_fifo_set_araddr_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); type wr_fifo_narrow_port_addr_vec is array (natural range <>) of unsigned(BURST_W-1 downto 0); type fifo_wide_port_addr_vec is array (natural range <>) of unsigned(BURST_WORDS_W-CACHE_N_BANKS_W-1 downto 0); signal wr_fifo_wrAddr : wr_fifo_narrow_port_addr_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_wrAddr_n : wr_fifo_narrow_port_addr_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_rdAddr : fifo_wide_port_addr_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_rdAddr_n : fifo_wide_port_addr_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_full, wr_fifo_full_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); type wr_fifo_vec is array(natural range <>) of gmem_word_array(2**BURST_W-1 downto 0); signal wr_fifo : wr_fifo_vec(N_WR_FIFOS-1 downto 0) := (others=>(others=>(others=>'0'))); signal axi_rdata_d0 : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_rdata_wr_fifo : gmem_word_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); attribute max_fanout of wr_fifo_rdAddr : signal is 60; -- }}} -- read fifos (write axi channels) {{{ type rd_fifo_vec is array(natural range <>) of gmem_word_array(2**RD_FIFO_W-1 downto 0); signal rd_fifo : rd_fifo_vec(N_AXI-1 downto 0) := (others=>(others=>(others=>'0'))); signal rd_fifo_cache_rqst_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal rd_fifo_rqst_addr_n : cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal fifo_cache_rqst_rd_data : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_pop, rd_fifo_slice_filled: std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_written : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); type st_rd_fifo_fill_type is (idle, fill_fifo, wait_w_channel); type st_rd_fifo_fill_array is array (natural range <>) of st_rd_fifo_fill_type; signal st_rd_fifo_data : st_rd_fifo_fill_array(N_AXI-1 downto 0) := (others=>idle); signal st_rd_fifo_data_n : st_rd_fifo_fill_array(N_AXI-1 downto 0) := (others=>idle); type rd_fifo_wrAddr_array is array (natural range <>) of unsigned(RD_FIFO_N_BURSTS_W+BURST_WORDS_W-CACHE_N_BANKS_W-1 downto 0); signal rd_fifo_wrAddr : rd_fifo_wrAddr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_wrAddr_n : rd_fifo_wrAddr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); attribute max_fanout of rd_fifo_wrAddr : signal is 60; type rd_fifo_rdAddr_array is array (natural range <>) of unsigned(RD_FIFO_N_BURSTS_W+BURST_WORDS_W-GMEM_N_BANK_W-1 downto 0); signal rd_fifo_rdAddr, rd_fifo_rdAddr_n : rd_fifo_rdAddr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_nempty, rd_fifo_nempty_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); type rd_fifo_n_filled_array is array (natural range <>) of unsigned(RD_FIFO_W-1 downto 0); signal rd_fifo_n_filled : rd_fifo_n_filled_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_n_filled_n : rd_fifo_n_filled_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_n_filled_on_ack : rd_fifo_n_filled_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_n_filled_on_ack_n : rd_fifo_n_filled_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal cache_dob_latched : std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); signal axi_wlast_p0 : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal rd_fifo_din_v_d0 : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal cache_dob_d0 : std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); signal fifo_be_din_d0 : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); -- be fifos type fifo_be_vec is array(natural range <>) of gmem_be_array(2**RD_FIFO_W-1 downto 0); signal fifo_be : fifo_be_vec(N_AXI-1 downto 0) := (others=>(others=>(others=>'0'))); type awaddr_fifo_type is array(natural range <>) of gmem_addr_array(2**RD_FIFO_N_BURSTS_W-1 downto 0); signal awaddr_fifo : awaddr_fifo_type(N_AXI-1 downto 0) := (others=>(others=>(others=>'0'))); type tmanager_indx_array is array(natural range <>) of std_logic_vector(N_TAG_MANAGERS_W-1 downto 0); type awid_fifo_type is array(natural range <>) of tmanager_indx_array(2**RD_FIFO_N_BURSTS_W-1 downto 0); signal awid_fifo : awid_fifo_type(N_AXI-1 downto 0) := (others=>(others=>(others=>'0'))); type awaddr_fifo_addr_vec is array(natural range <>) of unsigned(RD_FIFO_N_BURSTS_W-1 downto 0); signal awaddr_fifo_wrAddr : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0')); signal awaddr_fifo_wrAddr_n : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0')); signal awaddr_fifo_rdAddr : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0')); signal awaddr_fifo_rdAddr_n : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0')); signal awaddr_fifo_pop_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_pop : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_full_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_full : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_nempty_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal awaddr_fifo_nempty : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_wdata_n : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wstrb_n : gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0')); --}}} begin -- internal & fixed signals assignments -------------------------------------------------------------------------{{{ axi_arvalid <= axi_arvalid_i; axi_wvalid <= axi_wvalid_i; axi_rready <= axi_rready_i; axi_awvalid <= axi_awvalid_i; axi_bready <= (others=>'1'); wr_fifo_free <= wr_fifo_free_i; rd_fifo_cache_rqst <= rd_fifo_cache_rqst_i; wr_fifo_rqst_addr <= wr_fifo_rqst_addr_i; rd_fifo_rqst_addr <= rd_fifo_rqst_addr_i; axi_araddr <= axi_araddr_i; axi_arid <= axi_arid_i; assert N_TAG_MANAGERS_W <= ID_WIDTH report "Width of AWID channel is not enough for sending the tag manager id" severity failure; ---------------------------------------------------------------------------------------------------------}}} -- axi fifos wr (to cache) ----------------------------------------------------------------------------------------{{{ wr_fifo_cache_rqst <= wr_fifo_full; wr_fifos: for i in 0 to N_WR_FIFOS-1 generate begin process(clk) begin if rising_edge(clk) then if wr_fifo_push(i) = '1' then wr_fifo(i)(to_integer(wr_fifo_wrAddr(i))) <= axi_rdata_wr_fifo(i); -- wr_fifo(i)(to_integer(wr_fifo_wrAddr(i))) <= axi_rdata_d0(c_wr_fifo_axi_indx(i)); end if; wr_fifo_push(i) <= wr_fifo_push_n(i); wr_fifo_free_i(i) <= wr_fifo_free_n(i); if nrst = '0' then st_wr_fifo(i) <= idle; wr_fifo_set_araddr(i) <= '0'; wr_fifo_rqst_addr_i(i) <= (others=>'0'); else st_wr_fifo(i) <= st_wr_fifo_n(i); wr_fifo_set_araddr(i) <= wr_fifo_set_araddr_n(i); wr_fifo_rqst_addr_i(i) <= wr_fifo_rqst_addr_n(i); end if; end if; end process; process(st_wr_fifo(i), wr_fifo_set_araddr(i), wr_fifo_free_i(i), wr_fifo_go(i), axi_rdAddr(i), axi_set_araddr_ack(i), wr_fifo_rqst_addr_i(i), axi_rvalid(c_wr_fifo_axi_indx(i)), wr_fifo_cache_ack(i), axi_rlast(c_wr_fifo_axi_indx(i)), axi_rid(c_wr_fifo_axi_indx(i)), wr_fifo_rdAddr(i)) begin st_wr_fifo_n(i) <= st_wr_fifo(i); wr_fifo_set_araddr_n(i) <= wr_fifo_set_araddr(i); wr_fifo_free_n(i) <= wr_fifo_free_i(i); wr_fifo_rqst_addr_n(i) <= wr_fifo_rqst_addr_i(i); if wr_fifo_cache_ack(i) = '1' or wr_fifo_rdAddr(i) /= (wr_fifo_rdAddr(i)'reverse_range => '0') then wr_fifo_rqst_addr_n(i) <= wr_fifo_rqst_addr_i(i) + 1; end if; wr_fifo_push_n(i) <= '0'; case st_wr_fifo(i) is when idle => wr_fifo_free_n(i) <= '1'; if wr_fifo_go(i) = '1' then wr_fifo_free_n(i) <= '0'; wr_fifo_set_araddr_n(i) <= '1'; st_wr_fifo_n(i) <= send_address; wr_fifo_rqst_addr_n(i) <= axi_rdAddr(i)(M+L-1 downto 0); -- this signal has priority on wr_fifo_cache_ack when setting wr_fifo_rqst_addr_n end if; when send_address => if axi_set_araddr_ack(i) = '1' then st_wr_fifo_n(i) <= get_data; wr_fifo_set_araddr_n(i) <= '0'; end if; when get_data => if axi_rvalid(c_wr_fifo_axi_indx(i)) = '1' and to_integer(unsigned(axi_rid(c_wr_fifo_axi_indx(i)))) = c_wr_fifo_indx(i) then wr_fifo_push_n(i) <= '1'; if axi_rlast(c_wr_fifo_axi_indx(i)) = '1' then st_wr_fifo_n(i) <= wait_empty; end if; end if; when wait_empty => -- if wr_fifo_cache_ack(i) = '1' then if wr_fifo_rdAddr(i) = (wr_fifo_rdAddr(i)'reverse_range => '1') then -- st_wr_fifo_n(i) <= wait_for_writing_cache; st_wr_fifo_n(i) <= idle; wr_fifo_free_n(i) <= '1'; end if; when wait_for_writing_cache => -- st_wr_fifo_n(i) <= wait2; st_wr_fifo_n(i) <= idle; wr_fifo_free_n(i) <= '1'; when wait2 => wr_fifo_free_n(i) <= '1'; st_wr_fifo_n(i) <= idle; end case; end process; wr_fifo_out: process(wr_fifo(i), wr_fifo_rdAddr(i)) variable indx: unsigned(BURST_W-1 downto 0) := (others=>'0'); begin for j in 0 to CACHE_N_BANKS/GMEM_N_BANK-1 loop if CACHE_N_BANKS_W > GMEM_N_BANK_W then indx(max(CACHE_N_BANKS_W-GMEM_N_BANK_W-1, 0) downto 0) := to_unsigned(j, CACHE_N_BANKS_W-GMEM_N_BANK_W); end if; indx(indx'high downto CACHE_N_BANKS_W-GMEM_N_BANK_W) := wr_fifo_rdAddr(i); wr_fifo_dout(i)((j+1)*GMEM_DATA_W-1 downto j*GMEM_DATA_W) <= wr_fifo(i)(to_integer(indx)); end loop; end process; process(wr_fifo_rdAddr(i), wr_fifo_cache_ack(i), wr_fifo_push(i), wr_fifo_wrAddr(i), wr_fifo_full(i)) begin wr_fifo_rdAddr_n(i) <= wr_fifo_rdAddr(i); wr_fifo_wrAddr_n(i) <= wr_fifo_wrAddr(i); wr_fifo_full_n(i) <= wr_fifo_full(i); if wr_fifo_cache_ack(i) = '1' or wr_fifo_rdAddr(i) /= (wr_fifo_rdAddr(i)'reverse_range => '0') then wr_fifo_rdAddr_n(i) <= wr_fifo_rdAddr(i) + 1; end if; if wr_fifo_push(i) = '1' then wr_fifo_wrAddr_n(i) <= wr_fifo_wrAddr(i) + 1; end if; if wr_fifo_push(i) = '1' and wr_fifo_wrAddr(i) = (wr_fifo_wrAddr(i)'reverse_range => '1') then wr_fifo_full_n(i) <= '1'; elsif wr_fifo_cache_ack(i) = '1' then wr_fifo_full_n(i) <= '0'; end if; end process; process(clk) begin if rising_edge(clk) then if nrst = '0' then wr_fifo_wrAddr(i) <= (others=>'0'); wr_fifo_rdAddr(i) <= (others=>'0'); wr_fifo_full(i) <= '0'; else wr_fifo_rdAddr(i) <= wr_fifo_rdAddr_n(i); wr_fifo_wrAddr(i) <= wr_fifo_wrAddr_n(i); wr_fifo_full(i) <= wr_fifo_full_n(i); end if; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- axi read channels ------------------------------------------------------------------------------------------- {{{ axi_trans_read: process(clk) begin if rising_edge(clk) then axi_set_araddr_ack <= axi_set_araddr_ack_n; cache_dob_d0 <= cache_dob; axi_arid_i <= axi_arid_n; rd_fifo_din_v_d0 <= rd_fifo_din_v; fifo_be_din_d0 <= fifo_be_din; if nrst = '0' then axi_arvalid_i <= (others=>'0'); axi_rready_i <= (others=>'0'); axi_araddr_i <= (others=>(others=>'0')); st_ar <= (others=>idle); else -- read signals axi_arvalid_i <= axi_arvalid_n; axi_rready_i <= axi_rready_n; axi_araddr_i <= axi_araddr_n; st_ar <= st_ar_n; end if; end if; end process; process(st_ar, wr_fifo_set_araddr, axi_arvalid_i, axi_arready, axi_araddr_i, axi_arid_i, axi_rdAddr) begin for i in 0 to N_AXI-1 loop st_ar_n(i) <= st_ar(i); axi_arvalid_n(i) <= axi_arvalid_i(i); axi_araddr_n(i) <= axi_araddr_i(i); axi_araddr_n(i)(2+N-1 downto 0) <= (others=>'0'); axi_arid_n(i) <= axi_arid_i(i); for j in 0 to N_WR_FIFOS_AXI-1 loop axi_set_araddr_ack_n(c_axi_wr_fifos(i, j)) <= '0'; end loop; case st_ar(i) is when idle => for j in 0 to N_WR_FIFOS_AXI-1 loop if wr_fifo_set_araddr(c_axi_wr_fifos(i, j)) = '1' then st_ar_n(i) <= active; axi_arvalid_n(i) <= '1'; axi_araddr_n(i)(GMEM_ADDR_W-1 downto 2+N) <= axi_rdAddr(c_axi_wr_fifos(i, j)); axi_set_araddr_ack_n(c_axi_wr_fifos(i, j)) <= '1'; axi_arid_n(i) <= std_logic_vector(to_unsigned(j, ID_WIDTH)); exit; end if; end loop; when active => if axi_arready(i) = '1' then axi_arvalid_n(i) <= '0'; st_ar_n(i) <= idle; end if; end case; axi_rready_n(i) <= '1'; end loop; end process; ---------------------------------------------------------------------------------------------------------}}} -- axi fifos rd (from cache) ------------------------------------------------------------------------------------{{{ fifos_rd: for i in 0 to N_AXI-1 generate begin fifor_rd_fill: process(clk) variable indx: unsigned(BURST_W+RD_FIFO_N_BURSTS_W-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then if axi_written(i) = '1' or rd_fifo_slice_filled(i) = '0' then axi_wdata(i) <= rd_fifo(i)(to_integer(rd_fifo_rdAddr(i))); axi_wstrb(i) <= fifo_be(i)(to_integer(rd_fifo_rdAddr(i))); axi_wvalid_i(i) <= rd_fifo_nempty(i); axi_wlast(i) <= axi_wlast_p0(i); end if; if rd_fifo_din_v_d0(i) = '1' then for j in 0 to CACHE_N_BANKS/GMEM_N_BANK-1 loop if CACHE_N_BANKS_W > GMEM_N_BANK_W then indx(max(CACHE_N_BANKS_W-GMEM_N_BANK_W-1,0) downto 0) := to_unsigned(j, CACHE_N_BANKS_W-GMEM_N_BANK_W); end if; indx(indx'high downto CACHE_N_BANKS_W-GMEM_N_BANK_W) := rd_fifo_wrAddr(i); rd_fifo(i)(to_integer(indx)) <= cache_dob_d0((j+1)*GMEM_DATA_W-1 downto j*GMEM_DATA_W); fifo_be(i)(to_integer(indx)) <= fifo_be_din_d0((j+1)*GMEM_DATA_W/8-1 downto j*GMEM_DATA_W/8); end loop; end if; end if; end process; rd_fifo_trans: process(clk) variable tmp: std_logic_vector(BURST_W-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then rd_fifo_rqst_addr_i(i) <= rd_fifo_rqst_addr_n(i); axi_writer_free(i) <= axi_writer_free_n(i); rd_fifo_nempty(i) <= rd_fifo_nempty_n(i); axi_writer_ack <= (others=>'0'); for i in 0 to N_TAG_MANAGERS-1 loop if axi_bvalid(c_wr_fifo_axi_indx(i)) = '1' then axi_writer_ack(to_integer(unsigned(axi_bid(c_wr_fifo_axi_indx(i))))) <= '1'; end if; end loop; -- for i in 0 to N_AXI-1 loop -- if axi_bvalid(i) = '1' then -- axi_writer_ack(to_integer(unsigned(axi_bid(i)))) <= '1'; -- end if; -- end loop; if nrst = '0' then st_rd_fifo_data(i) <= idle; rd_fifo_cache_rqst_i(i) <= '0'; rd_fifo_rdAddr(i) <= (others=>'0'); rd_fifo_wrAddr(i) <= (others=>'0'); rd_fifo_n_filled(i) <= (others=>'0'); rd_fifo_n_filled_on_ack(i) <= (others=>'0'); axi_wlast_p0(i) <= '0'; rd_fifo_slice_filled(i) <= '0'; else st_rd_fifo_data(i) <= st_rd_fifo_data_n(i); rd_fifo_cache_rqst_i(i) <= rd_fifo_cache_rqst_n(i); rd_fifo_rdAddr(i) <= rd_fifo_rdAddr_n(i); rd_fifo_wrAddr(i) <= rd_fifo_wrAddr_n(i); rd_fifo_n_filled(i) <= rd_fifo_n_filled_n(i); rd_fifo_n_filled_on_ack(i) <= rd_fifo_n_filled_on_ack_n(i); if axi_written(i) = '1' or rd_fifo_slice_filled(i) = '0' then axi_wlast_p0(i) <= '0'; if rd_fifo_rdAddr(i)(BURST_W-1 downto 1) = (1 to BURST_W-1 =>'1') and rd_fifo_rdAddr(i)(0) = '0' and rd_fifo_pop(i) = '1' then axi_wlast_p0(i) <= '1'; end if; end if; -- if axi_wready(i) = '1' and rd_fifo_nempty(i) = '1' then -- axi_wlast_p0(i) <= '0'; -- end if; if axi_written(i) = '1' and rd_fifo_nempty(i) = '0' then rd_fifo_slice_filled(i) <= '0'; end if; if rd_fifo_slice_filled(i) = '0' and rd_fifo_nempty(i) = '1' then rd_fifo_slice_filled(i) <= '1'; end if; end if; end if; end process; rd_fifo_proc: process(rd_fifo_wrAddr(i), rd_fifo_rdAddr(i), rd_fifo_pop(i), rd_fifo_din_v_d0(i), rd_fifo_n_filled(i), rd_fifo_n_filled_on_ack(i), rd_fifo_cache_ack(i)) begin rd_fifo_rdAddr_n(i) <= rd_fifo_rdAddr(i); rd_fifo_wrAddr_n(i) <= rd_fifo_wrAddr(i); if rd_fifo_pop(i) = '1' then rd_fifo_rdAddr_n(i) <= rd_fifo_rdAddr(i) + 1; end if; if rd_fifo_din_v_d0(i) = '1' then rd_fifo_wrAddr_n(i) <= rd_fifo_wrAddr(i) + 1; end if; if rd_fifo_pop(i) = '0' and rd_fifo_din_v_d0(i) = '0' then rd_fifo_n_filled_n(i) <= rd_fifo_n_filled(i); elsif rd_fifo_pop(i) = '1' and rd_fifo_din_v_d0(i) = '0' then rd_fifo_n_filled_n(i) <= rd_fifo_n_filled(i) - 1; elsif rd_fifo_pop(i) = '1' and rd_fifo_din_v_d0(i) = '1' then rd_fifo_n_filled_n(i) <= rd_fifo_n_filled(i) - 1 + CACHE_N_BANKS/GMEM_N_BANK; else rd_fifo_n_filled_n(i) <= rd_fifo_n_filled(i) + CACHE_N_BANKS/GMEM_N_BANK; end if; -- consider the rd_fifo_cache_ack as the push signal for not overfilling the fifo if rd_fifo_pop(i) = '0' and rd_fifo_cache_ack(i) = '0' then rd_fifo_n_filled_on_ack_n(i) <= rd_fifo_n_filled_on_ack(i); elsif rd_fifo_pop(i) = '1' and rd_fifo_cache_ack(i) = '0' then rd_fifo_n_filled_on_ack_n(i) <= rd_fifo_n_filled_on_ack(i) - 1; elsif rd_fifo_pop(i) = '1' and rd_fifo_cache_ack(i) = '1' then rd_fifo_n_filled_on_ack_n(i) <= rd_fifo_n_filled_on_ack(i) - 1 + (2**BURST_WORDS_W)/GMEM_N_BANK; else rd_fifo_n_filled_on_ack_n(i) <= rd_fifo_n_filled_on_ack(i) + 2**(BURST_WORDS_W)/GMEM_N_BANK; end if; end process; rd_fifo_nempty_n(i) <= '0' when rd_fifo_n_filled_n(i) = (rd_fifo_n_filled_n(i)'reverse_range=>'0') else '1'; axi_written(i) <= axi_wready(i) and axi_wvalid_i(i); rd_fifo_pop(i) <= rd_fifo_nempty(i) and (axi_written(i) or (not rd_fifo_slice_filled(i))); process(st_rd_fifo_data(i), axi_writer_go(i), rd_fifo_rqst_addr_i(i), rd_fifo_cache_ack(i), axi_wrAddr(i)(M+L-1 downto 0), rd_fifo_cache_rqst_i(i), awaddr_fifo_full(i), rd_fifo_n_filled_on_ack_n(i)) --, axi_awvalid_i(i), axi_awready(i)) begin st_rd_fifo_data_n(i) <= st_rd_fifo_data(i); rd_fifo_rqst_addr_n(i) <= rd_fifo_rqst_addr_i(i); rd_fifo_cache_rqst_n(i) <= rd_fifo_cache_rqst_i(i); axi_writer_free_n(i) <= not awaddr_fifo_full(i); case st_rd_fifo_data(i) is when idle => if axi_writer_go(i) = '1' then st_rd_fifo_data_n(i) <= fill_fifo; rd_fifo_rqst_addr_n(i) <= axi_wrAddr(i)(M+L-1 downto 0); rd_fifo_cache_rqst_n(i) <= '1'; axi_writer_free_n(i) <= '0'; end if; when fill_fifo => axi_writer_free_n(i) <= '0'; if rd_fifo_cache_ack(i) = '1' then rd_fifo_cache_rqst_n(i) <= '0'; if rd_fifo_n_filled_on_ack_n(i)(rd_fifo_n_filled_on_ack_n(i)'high downto BURST_W) /= (0 to rd_fifo_n_filled_on_ack_n(i)'high-BURST_W =>'1') then axi_writer_free_n(i) <= not awaddr_fifo_full(i); st_rd_fifo_data_n(i) <= idle; else st_rd_fifo_data_n(i) <= wait_w_channel; end if; end if; when wait_w_channel => axi_writer_free_n(i) <= '0'; if rd_fifo_n_filled_on_ack_n(i)(rd_fifo_n_filled_on_ack_n(i)'high downto BURST_W) /= (0 to rd_fifo_n_filled_on_ack_n(i)'high-BURST_W =>'1') then axi_writer_free_n(i) <= not awaddr_fifo_full(i); st_rd_fifo_data_n(i) <= idle; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- awaddr fifo -------------------------------------------------------------------------------------------{{{ awaddr_fifos: for i in 0 to N_AXI-1 generate begin awaddr_fifo_trans: process(clk) begin if rising_edge(clk) then if axi_writer_go(i) = '1' then awaddr_fifo(i)(to_integer(awaddr_fifo_wrAddr(i)))(GMEM_ADDR_W-1 downto 2+N) <= axi_wrAddr(i); awaddr_fifo(i)(to_integer(awaddr_fifo_wrAddr(i)))(2+N-1 downto 0) <= (others=>'0'); awid_fifo(i)(to_integer(awaddr_fifo_wrAddr(i))) <= axi_writer_id; end if; for i in 0 to N_WR_FIFOS-1 loop axi_rdata_wr_fifo(i) <= axi_rdata(c_wr_fifo_axi_indx(i)); end loop; -- axi_rdata_d0(i) <= axi_rdata(i); if nrst = '0' then awaddr_fifo_wrAddr(i) <= (others=>'0'); awaddr_fifo_rdAddr(i) <= (others=>'0'); awaddr_fifo_full(i) <= '0'; awaddr_fifo_nempty(i) <= '0'; else awaddr_fifo_nempty(i) <= awaddr_fifo_nempty_n(i); awaddr_fifo_full(i) <= awaddr_fifo_full_n(i); awaddr_fifo_wrAddr(i) <= awaddr_fifo_wrAddr_n(i); awaddr_fifo_rdAddr(i) <= awaddr_fifo_rdAddr_n(i); end if; end if; end process; axi_awaddr(i) <= awaddr_fifo(i)(to_integer(awaddr_fifo_rdAddr(i))); axi_awid(i)(N_TAG_MANAGERS_W-1 downto 0) <= awid_fifo(i)(to_integer(awaddr_fifo_rdAddr(i))); axi_awid(i)(ID_WIDTH-1 downto N_TAG_MANAGERS_W) <= (others=>'0'); awaddr_fifo_proc: process(awaddr_fifo_wrAddr(i), axi_writer_go(i), awaddr_fifo_rdAddr(i), axi_awready(i), axi_awvalid_i(i)) begin awaddr_fifo_wrAddr_n(i) <= awaddr_fifo_wrAddr(i); awaddr_fifo_rdAddr_n(i) <= awaddr_fifo_rdAddr(i); if axi_writer_go(i) = '1' then awaddr_fifo_wrAddr_n(i) <= awaddr_fifo_wrAddr(i) + 1; end if; if axi_awvalid_i(i) = '1' and axi_awready(i) = '1' then awaddr_fifo_rdAddr_n(i) <= awaddr_fifo_rdAddr(i) + 1; end if; end process; axi_awvalid_i(i) <= awaddr_fifo_nempty(i); awaddr_fifo_proc1: process(axi_writer_go(i), awaddr_fifo_full(i), awaddr_fifo_nempty(i), awaddr_fifo_wrAddr(i), awaddr_fifo_wrAddr_n(i), awaddr_fifo_rdAddr(i), awaddr_fifo_rdAddr_n(i), axi_awvalid_i(i), axi_awready(i)) begin awaddr_fifo_full_n(i) <= awaddr_fifo_full(i); awaddr_fifo_nempty_n(i) <= awaddr_fifo_nempty(i); if axi_writer_go(i) = '1' and (axi_awvalid_i(i) = '0' or axi_awready(i) = '0') and awaddr_fifo_wrAddr_n(i) = awaddr_fifo_rdAddr(i) then awaddr_fifo_full_n(i) <= '1'; elsif axi_writer_go(i) = '0' and axi_awvalid_i(i) = '1' and axi_awready(i) = '1' then awaddr_fifo_full_n(i) <= '0'; end if; if axi_writer_go(i) = '1' and (axi_awvalid_i(i) = '0' or axi_awready(i) = '0') then awaddr_fifo_nempty_n(i) <= '1'; elsif axi_writer_go(i) = '0' and axi_awvalid_i(i) = '1' and axi_awready(i) = '1' and awaddr_fifo_wrAddr(i) = awaddr_fifo_rdAddr_n(i) then awaddr_fifo_nempty_n(i) <= '0'; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

87178071a3abe437755af29f3d192830

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/VOICE_ROM_INIT_funcsim.vhdl

-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014 -- Date : Wed Sep 10 03:37:56 2014 -- Host : Dtysky running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- d:/spira_heaven/0-myworks/ld3320_axi/ld3320_axi_1.0/src/VOICE_ROM_INIT/VOICE_ROM_INIT_funcsim.vhdl -- Design : VOICE_ROM_INIT -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_prim_wrapper is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper"; end VOICE_ROM_INIT_blk_mem_gen_prim_wrapper; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_prim_wrapper is signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; signal \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "SDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 36, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 0, WRITE_WIDTH_B => 36 ) port map ( ADDRARDADDR(13) => '0', ADDRARDADDR(12) => '0', ADDRARDADDR(11) => '0', ADDRARDADDR(10 downto 5) => addrb(5 downto 0), ADDRARDADDR(4) => '0', ADDRARDADDR(3) => '0', ADDRARDADDR(2) => '0', ADDRARDADDR(1) => '0', ADDRARDADDR(0) => '0', ADDRBWRADDR(13) => '0', ADDRBWRADDR(12) => '0', ADDRBWRADDR(11) => '0', ADDRBWRADDR(10 downto 5) => addra(5 downto 0), ADDRBWRADDR(4) => '0', ADDRBWRADDR(3) => '0', ADDRBWRADDR(2) => '0', ADDRBWRADDR(1) => '0', ADDRBWRADDR(0) => '0', CLKARDCLK => clkb, CLKBWRCLK => clka, DIADI(15) => '0', DIADI(14) => '0', DIADI(13) => '0', DIADI(12) => '0', DIADI(11 downto 8) => dina(7 downto 4), DIADI(7) => '0', DIADI(6) => '0', DIADI(5) => '0', DIADI(4) => '0', DIADI(3 downto 0) => dina(3 downto 0), DIBDI(15) => '0', DIBDI(14) => '0', DIBDI(13) => '0', DIBDI(12) => '0', DIBDI(11 downto 8) => dina(15 downto 12), DIBDI(7) => '0', DIBDI(6) => '0', DIBDI(5) => '0', DIBDI(4) => '0', DIBDI(3 downto 0) => dina(11 downto 8), DIPADIP(1) => '0', DIPADIP(0) => '0', DIPBDIP(1) => '0', DIPBDIP(0) => '0', DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(14) => \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(13) => \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(12) => \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(11 downto 8) => doutb(7 downto 4), DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(6) => \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(5) => \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(4) => \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOADO(3 downto 0) => doutb(3 downto 0), DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(14) => \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(13) => \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(12) => \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(11 downto 8) => doutb(15 downto 12), DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(6) => \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(5) => \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(4) => \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOBDO(3 downto 0) => doutb(11 downto 8), DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\, ENARDEN => '1', ENBWREN => wea(0), REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => '0', WEA(0) => '0', WEBWE(3) => '1', WEBWE(2) => '1', WEBWE(1) => '1', WEBWE(0) => '1' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_prim_width is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end VOICE_ROM_INIT_blk_mem_gen_prim_width; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_prim_width is begin \prim_noinit.ram\: entity work.VOICE_ROM_INIT_blk_mem_gen_prim_wrapper port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_generic_cstr is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end VOICE_ROM_INIT_blk_mem_gen_generic_cstr; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.VOICE_ROM_INIT_blk_mem_gen_prim_width port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_top is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_top : entity is "blk_mem_gen_top"; end VOICE_ROM_INIT_blk_mem_gen_top; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_top is begin \valid.cstr\: entity work.VOICE_ROM_INIT_blk_mem_gen_generic_cstr port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT_blk_mem_gen_v8_2_synth is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth"; end VOICE_ROM_INIT_blk_mem_gen_v8_2_synth; architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_v8_2_synth is begin \gnativebmg.native_blk_mem_gen\: entity work.VOICE_ROM_INIT_blk_mem_gen_top port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); douta : out STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 15 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 ); sleep : in STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2"; attribute C_FAMILY : string; attribute C_FAMILY of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq"; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq"; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "./"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 4; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 9; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "VOICE_ROM_INIT.mem"; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "CE"; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64; attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 6; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "CE"; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_INITB_VAL : string; attribute C_INITB_VAL of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 6; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL"; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0"; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "1"; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 3.01735 mW"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "yes"; end \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\; architecture STRUCTURE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; douta(15) <= \<const0>\; douta(14) <= \<const0>\; douta(13) <= \<const0>\; douta(12) <= \<const0>\; douta(11) <= \<const0>\; douta(10) <= \<const0>\; douta(9) <= \<const0>\; douta(8) <= \<const0>\; douta(7) <= \<const0>\; douta(6) <= \<const0>\; douta(5) <= \<const0>\; douta(4) <= \<const0>\; douta(3) <= \<const0>\; douta(2) <= \<const0>\; douta(1) <= \<const0>\; douta(0) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.VOICE_ROM_INIT_blk_mem_gen_v8_2_synth port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity VOICE_ROM_INIT is port ( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 5 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; addrb : in STD_LOGIC_VECTOR ( 5 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of VOICE_ROM_INIT : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of VOICE_ROM_INIT : entity is "yes"; attribute x_core_info : string; attribute x_core_info of VOICE_ROM_INIT : entity is "blk_mem_gen_v8_2,Vivado 2014.2"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of VOICE_ROM_INIT : entity is "VOICE_ROM_INIT,blk_mem_gen_v8_2,{}"; attribute core_generation_info : string; attribute core_generation_info of VOICE_ROM_INIT : entity is "VOICE_ROM_INIT,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=VOICE_ROM_INIT.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=64,C_READ_DEPTH_A=64,C_ADDRA_WIDTH=6,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=64,C_READ_DEPTH_B=64,C_ADDRB_WIDTH=6,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.01735 mW}"; end VOICE_ROM_INIT; architecture STRUCTURE of VOICE_ROM_INIT is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 6; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 6; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 9; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "0"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.01735 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 0; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "VOICE_ROM_INIT.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 0; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 1; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 64; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 64; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 16; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 16; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 0; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 0; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 64; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 64; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 16; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 16; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.\VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ port map ( addra(5 downto 0) => addra(5 downto 0), addrb(5 downto 0) => addrb(5 downto 0), clka => clka, clkb => clkb, dbiterr => NLW_U0_dbiterr_UNCONNECTED, dina(15 downto 0) => dina(15 downto 0), dinb(15) => '0', dinb(14) => '0', dinb(13) => '0', dinb(12) => '0', dinb(11) => '0', dinb(10) => '0', dinb(9) => '0', dinb(8) => '0', dinb(7) => '0', dinb(6) => '0', dinb(5) => '0', dinb(4) => '0', dinb(3) => '0', dinb(2) => '0', dinb(1) => '0', dinb(0) => '0', douta(15 downto 0) => NLW_U0_douta_UNCONNECTED(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), eccpipece => '0', ena => '0', enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(5 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(5 downto 0), regcea => '0', regceb => '0', rsta => '0', rstb => '0', s_aclk => '0', s_aresetn => '0', s_axi_araddr(31) => '0', s_axi_araddr(30) => '0', s_axi_araddr(29) => '0', s_axi_araddr(28) => '0', s_axi_araddr(27) => '0', s_axi_araddr(26) => '0', s_axi_araddr(25) => '0', s_axi_araddr(24) => '0', s_axi_araddr(23) => '0', s_axi_araddr(22) => '0', s_axi_araddr(21) => '0', s_axi_araddr(20) => '0', s_axi_araddr(19) => '0', s_axi_araddr(18) => '0', s_axi_araddr(17) => '0', s_axi_araddr(16) => '0', s_axi_araddr(15) => '0', s_axi_araddr(14) => '0', s_axi_araddr(13) => '0', s_axi_araddr(12) => '0', s_axi_araddr(11) => '0', s_axi_araddr(10) => '0', s_axi_araddr(9) => '0', s_axi_araddr(8) => '0', s_axi_araddr(7) => '0', s_axi_araddr(6) => '0', s_axi_araddr(5) => '0', s_axi_araddr(4) => '0', s_axi_araddr(3) => '0', s_axi_araddr(2) => '0', s_axi_araddr(1) => '0', s_axi_araddr(0) => '0', s_axi_arburst(1) => '0', s_axi_arburst(0) => '0', s_axi_arid(3) => '0', s_axi_arid(2) => '0', s_axi_arid(1) => '0', s_axi_arid(0) => '0', s_axi_arlen(7) => '0', s_axi_arlen(6) => '0', s_axi_arlen(5) => '0', s_axi_arlen(4) => '0', s_axi_arlen(3) => '0', s_axi_arlen(2) => '0', s_axi_arlen(1) => '0', s_axi_arlen(0) => '0', s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2) => '0', s_axi_arsize(1) => '0', s_axi_arsize(0) => '0', s_axi_arvalid => '0', s_axi_awaddr(31) => '0', s_axi_awaddr(30) => '0', s_axi_awaddr(29) => '0', s_axi_awaddr(28) => '0', s_axi_awaddr(27) => '0', s_axi_awaddr(26) => '0', s_axi_awaddr(25) => '0', s_axi_awaddr(24) => '0', s_axi_awaddr(23) => '0', s_axi_awaddr(22) => '0', s_axi_awaddr(21) => '0', s_axi_awaddr(20) => '0', s_axi_awaddr(19) => '0', s_axi_awaddr(18) => '0', s_axi_awaddr(17) => '0', s_axi_awaddr(16) => '0', s_axi_awaddr(15) => '0', s_axi_awaddr(14) => '0', s_axi_awaddr(13) => '0', s_axi_awaddr(12) => '0', s_axi_awaddr(11) => '0', s_axi_awaddr(10) => '0', s_axi_awaddr(9) => '0', s_axi_awaddr(8) => '0', s_axi_awaddr(7) => '0', s_axi_awaddr(6) => '0', s_axi_awaddr(5) => '0', s_axi_awaddr(4) => '0', s_axi_awaddr(3) => '0', s_axi_awaddr(2) => '0', s_axi_awaddr(1) => '0', s_axi_awaddr(0) => '0', s_axi_awburst(1) => '0', s_axi_awburst(0) => '0', s_axi_awid(3) => '0', s_axi_awid(2) => '0', s_axi_awid(1) => '0', s_axi_awid(0) => '0', s_axi_awlen(7) => '0', s_axi_awlen(6) => '0', s_axi_awlen(5) => '0', s_axi_awlen(4) => '0', s_axi_awlen(3) => '0', s_axi_awlen(2) => '0', s_axi_awlen(1) => '0', s_axi_awlen(0) => '0', s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2) => '0', s_axi_awsize(1) => '0', s_axi_awsize(0) => '0', s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(5 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(5 downto 0), s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(15) => '0', s_axi_wdata(14) => '0', s_axi_wdata(13) => '0', s_axi_wdata(12) => '0', s_axi_wdata(11) => '0', s_axi_wdata(10) => '0', s_axi_wdata(9) => '0', s_axi_wdata(8) => '0', s_axi_wdata(7) => '0', s_axi_wdata(6) => '0', s_axi_wdata(5) => '0', s_axi_wdata(4) => '0', s_axi_wdata(3) => '0', s_axi_wdata(2) => '0', s_axi_wdata(1) => '0', s_axi_wdata(0) => '0', s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, sleep => '0', wea(0) => wea(0), web(0) => '0' ); end STRUCTURE;

mit

19781ae9dd3483a4f1d470bc0e8cdbb1

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

038e33b4409c1faf505e6e9437baf45a

preusser/q27

src/vhdl/queens/queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <[email protected]> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity queens_uart is generic ( -- Problem Size N : positive; L : positive; -- Design Spec SOLVERS : positive; COUNT_CYCLES : boolean; -- Communication Parameters CLK_FREQ : positive; BAUDRATE : positive; SENTINEL : std_logic_vector(7 downto 0) ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- UART Interface rx : in std_logic; tx : out std_logic; -- Activity avail : out std_logic ); end queens_uart; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; use PoC.uart.all; architecture rtl of queens_uart is -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- UART-to-Unframe Interface signal rx_dat : std_logic_vector(7 downto 0); signal rx_stb : std_logic; -- Unframe-to-Chain Interface signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; -- Chain-to-Enframe Interface signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; -- Enframe-to-UART Interface signal tx_dat : std_logic_vector(7 downto 0); signal tx_ful : std_logic; signal tx_put : std_logic; begin ----------------------------------------------------------------------------- -- UART -> Byte Interface blkUART: block signal bclk_x8 : std_logic; signal bclk_x1 : std_logic; begin -- Bit Clock Generation bclk_gen_x8: entity PoC.arith_counter_free generic map ( DIVIDER => CLK_FREQ/(8*BAUDRATE) ) port map ( clk => clk, rst => '0', inc => '1', stb => bclk_x8 ); bclk_gen_x1: entity PoC.arith_counter_free generic map ( DIVIDER => 8 ) port map ( clk => clk, rst => '0', inc => bclk_x8, stb => bclk_x1 ); -- Receive Bytes uart_rx_2 : uart_rx port map ( clk => clk, rst => rst, bclk_x8 => bclk_x8, rx => rx, stb => rx_stb, do => rx_dat ); -- Transmit Byte uart_tx_1 : uart_tx port map ( clk => clk, rst => rst, bclk => bclk_x1, put => tx_put, di => tx_dat, ful => tx_ful, tx => tx ); end block blkUART; blkUnframe: block -- Input Glue FIFO -> Unframe signal glue_vld : std_logic; signal glue_dat : std_logic_vector(7 downto 0); signal glue_got : std_logic; -- Unframe -> Input Buffer signal odat : std_logic_vector(7 downto 0); signal oeof : std_logic; signal oful : std_logic; signal oput : std_logic; signal ocommit : std_logic; signal orollback : std_logic; signal pvld : std_logic; begin glue: fifo_glue generic map ( D_BITS => 8 ) port map ( clk => clk, rst => rst, put => rx_stb, di => rx_dat, ful => open, vld => glue_vld, do => glue_dat, got => glue_got ); unframe_i: entity work.unframe generic map ( SENTINEL => SENTINEL, PAY_LEN => PRE_BYTES ) port map ( clk => clk, rst => rst, rx_dat => glue_dat, rx_vld => glue_vld, rx_got => glue_got, odat => odat, oeof => oeof, oful => oful, oput => oput, ocommit => ocommit, orollback => orollback ); buf: fifo_cc_got_tempput generic map ( MIN_DEPTH => 5*(SOLVERS+5), D_BITS => 9 ) port map ( clk => clk, rst => rst, put => oput, din(8) => oeof, din(7 downto 0) => odat, full => oful, commit => ocommit, rollback => orollback, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pvld ); piput <= pvld and not piful; avail <= pvld; end block blkUnframe; chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk, rst => rst, piful => piful, pidat => pidat, pieof => pieof, piput => piput, poful => '1', podat => open, poeof => open, poput => open, sivld => '0', sidat => (others => '-'), sieof => '-', sigot => open, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); blkEnframe: block signal sful : std_logic; signal ogot : std_logic; signal oeof : std_logic; signal odat : byte; signal ovld : std_logic; begin sogot <= sovld and not sful; buf: fifo_cc_got generic map ( MIN_DEPTH => 5*(SOLVERS+5), D_BITS => 9, STATE_REG => true ) port map ( clk => clk, rst => rst, put => sogot, din(8) => soeof, din(7 downto 0) => sodat, full => sful, got => ogot, dout(8) => oeof, dout(7 downto 0) => odat, valid => ovld ); enframe_i: entity work.enframe generic map ( SENTINEL => SENTINEL ) port map ( clk => clk, rst => rst, ivld => ovld, idat => odat, ieof => oeof, igot => ogot, tx_ful => tx_ful, tx_put => tx_put, tx_dat => tx_dat ); end block blkEnframe; end rtl;

agpl-3.0

72e5d8e2d553987d631dc72cd036b5e1

malkadi/FGPU

RTL/gmem_cntrl.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; use ieee.std_logic_textio.all; use std.textio.all; ---------------------------------------------------------------------------------------------------------}}} entity gmem_cntrl is -- {{{ port( clk : in std_logic; start_kernel : in std_logic; clean_cache : in std_logic; WGsDispatched : in std_logic; CUs_gmem_idle : in std_logic; finish_exec : out std_logic := '0'; cu_valid : in std_logic_vector(N_CU-1 downto 0); cu_ready : out std_logic_vector(N_CU-1 downto 0) := (others=>'0'); cu_we : in be_array(N_CU-1 downto 0); cu_rnw, cu_atomic : in std_logic_vector(N_CU-1 downto 0); cu_atomic_sgntr : in atomic_sgntr_array(N_CU-1 downto 0); cu_rqst_addr : in GMEM_WORD_ADDR_ARRAY(N_CU-1 downto 0); cu_wrData : in SLV32_ARRAY(N_CU-1 downto 0); rdAck : out std_logic_vector(N_CU-1 downto 0) := (others=>'0'); rdAddr : out unsigned(GMEM_WORD_ADDR_W-1-CACHE_N_BANKS_W downto 0) := (others=>'0'); rdData : out std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0) := (others => '0'); atomic_rdData : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); atomic_rdData_v : out std_logic_vector(N_CU-1 downto 0) := (others=>'0'); atomic_sgntr : out std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); -- AXI Interface signals {{{ --Read address channel axi_araddr : out GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_arvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_arready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_arid : out id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- Read data channel axi_rdata : in gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_rlast : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rvalid : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rready : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rid : in id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- write address channel axi_awaddr : out GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_awvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_awready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_awid : out id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- write data channel axi_wdata : out gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_wstrb : out gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_wlast : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wvalid : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wready : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); -- write response channel axi_bvalid : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_bready : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_bid : in id_array(N_AXI-1 downto 0) := (others=>(others=>'0')); -- }}} nrst : in std_logic ); end gmem_cntrl; --}}} architecture Behavioral of gmem_cntrl is -- internal signals {{{ signal cu_ready_i : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal axi_wvalid_i : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal rdData_i : std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0) := (others => '0'); signal finish_exec_i : std_logic := '0'; -- }}} -- axi signals {{{ signal axi_rdAddr : gmem_addr_array_no_bank(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_go : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); -- attribute mark_debug of wr_fifo_go : signal is "true"; signal axi_writer_go : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_free : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_writer_free : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_wrAddr : gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_writer_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal axi_writer_id : std_logic_vector(N_TAG_MANAGERS_W-1 downto 0) := (others=>'0'); -- attribute mark_debug of axi_writer_id : signal is "true"; --}}} -- doc part (obselete) -------------------------------------------------------------------------------{{{ -- rmem = request mem -- rmem_blk = request memory block. There are GMEM_N_BANKS of rmem_block -- mir_blk = request memory mirror of a block. -- -- byte count : |7 6 5 |4 |3 2 1 0 | -- |_____|______________________|____|____|________________________________| | -- | cnt | TAG | we | re | Data to write | | -- _ _ |_____|______________________|____|____|________________________________| _ | -- | | | | TAG |____|____|________________________________| | | -- | rqst | | |¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|____|____|________________________________| rqst line | 2^L | -- | entry | | | XXX |____|____|________________________________| | | -- | |_ |_____|______________________|____|____|________________________________| _| | * 2^N rmem_block -- 2^M | | | | | | | | -- | | | | | | | | -- : : : : : : : : -- : : : : : : : : -- | | | | | | | | -- |_ |_____|______________________|____|____|________________________________| | -- -- 2^N = GMEM_N_BANKS (default=2^1) -- 2^M = number of rqst entries (default=2^5) -- 2^N = number of rqst lines/entry = burst length (default=2^4) -- TAG should be identical in all instances of request memory blocks -- cnt is the number of set bits either in re or we. It's limited in bit width and needs to sturated while incrementing. ------------------------------------------------------------------------------------------------}}} -- functions ------------------------------------------------------------------ {{{ function distribute_rcvs_on_CUs (n_rcvs: integer; n_cus: integer) return nat_array is variable res: nat_array(n_rcvs-1 downto 0) := (others=>0); begin for i in 0 to n_rcvs-1 loop for k in 0 to n_cus-1 loop if i < (k+1)*(n_rcvs/n_cus) and i >= k*(n_rcvs/n_cus) then res(i) := k; exit; end if; end loop; end loop; return res; end; function distribute_rcvs_on_gmem_banks (n_rcvs: natural; n_banks: natural) return nat_array is variable res: nat_array(n_rcvs-1 downto 0) := (others=>0); begin for i in 0 to n_rcvs-1 loop for k in 0 to n_banks-1 loop for j in 0 to (n_rcvs/n_banks)-1 loop if i = k + j*n_banks then res(i) := k; exit; end if; end loop; end loop; end loop; return res; end function distribute_rcvs_on_gmem_banks; -------------------------------------------------------------------------------------}}} -- Constants & types -------------------------------------------------------------------------------{{{ CONSTANT c_rcv_cu_indx : nat_array(N_RECEIVERS-1 downto 0) := distribute_rcvs_on_CUs(N_RECEIVERS, N_CU); CONSTANT c_rcv_bank_indx : nat_array(N_RECEIVERS-1 downto 0) := distribute_rcvs_on_gmem_banks(N_RECEIVERS, N_RD_PORTS); type cache_bank is array(natural range <>) of unsigned(DATA_W-1 downto 0); type cache_type is array(natural range <>) of cache_bank(2**(L+M)-1 downto 0); ------------------------------------------------------------------------------------------------}}} -- CUs' interface{{{ signal cu_ready_n : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal cuIndx_msb : std_logic := '0'; signal cu_atomic_ack_p0 : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); -- }}} -- receivers signals {{{ type st_rcv_type is ( get_addr, get_read_tag_ticket, wait_read_tag, check_tag_rd, check_tag_wr, alloc_tag, clean, request_write_addr, request_write_data, write_cache, read_cache, requesting_atomic); type st_rcv_array is array (N_RECEIVERS-1 downto 0) of st_rcv_type; signal st_rcv, st_rcv_n : st_rcv_array := (others=>get_addr); signal rcv_idle, rcv_idle_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_all_idle : std_logic := '0'; signal rcv_gmem_addr, rcv_gmem_addr_n : gmem_word_addr_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_gmem_data, rcv_gmem_data_n : SLV32_ARRAY(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_rnw, rcv_rnw_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic, rcv_atomic_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_be, rcv_be_n : be_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_atomic_sgntr : atomic_sgntr_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_atomic_sgntr_n : atomic_sgntr_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); signal rcv_go, rcv_go_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_must_read : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_read_tag, rcv_read_tag_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic_rqst : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic_rqst_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic_ack : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_atomic_performed : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal atomic_sgntr_p0 : std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); alias rcv_atomic_type : be_array(N_RECEIVERS-1 downto 0) is rcv_be; signal rcv_read_tag_ack : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_alloc_tag, rcv_alloc_tag_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal cu_rqst_addr_d0 : gmem_word_addr_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_wrData_d0 : SLV32_ARRAY(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_rnw_d0, cu_atomic_d0 : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); signal cu_we_d0 : be_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal cu_atomic_sgntr_d0 : atomic_sgntr_array(N_CU-1 downto 0) := (others=>(others=>'0')); signal rcv_tag_written, rcv_tag_updated : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_page_validated : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_perform_read : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_perform_read_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_request_write_addr : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_request_write_addr_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); attribute max_fanout of rcv_request_write_addr : signal is 50; signal rcv_request_write_data : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_request_write_data_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_tag_compared : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_wait_1st_cycle : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_wait_1st_cycle_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- }}} -- tag signals {{{ signal rdData_tag : tag_array(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); signal rdData_tag_v : std_logic_vector(N_RD_PORTS-1 downto 0) := (others=>'0'); signal rdData_page_v, rdData_page_v_d0 : std_logic_vector(N_RD_PORTS-1 downto 0) := (others=>'0'); -- }}} -- cache signals {{{ signal cache_mem : cache_type(2**N-1 downto 0) := (others=>(others=>(others=>'0'))); signal cache_wea, cache_wea_n : std_logic_vector((2**N)*DATA_W/8-1 downto 0) := (others=>'0'); signal cache_we, cache_we_n : std_logic := '0'; signal cache_addra, cache_addra_n : unsigned(M+L-1 downto 0) := (others=>'0'); signal cache_read_v, cache_read_v_p0 : std_logic := '0'; signal rcv_rd_done, rcv_rd_done_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); attribute max_fanout of cache_read_v : signal is 100; signal cache_read_v_p0_n : std_logic := '0'; signal cache_read_v_d0 : std_logic := '0'; signal cache_last_rdAddr : unsigned(M+L-1 downto 0) := (others=>'0'); -- }}} -- responder signals {{{ signal rcv_to_read, rcv_to_read_n : integer range 0 to N_RECEIVERS-1 := 0; signal rdAddr_p0, rdAddr_p1 : unsigned(GMEM_WORD_ADDR_W-N-1 downto 0) := (others=>'0'); signal cache_wrData : std_logic_vector((2**N)*DATA_W-1 downto 0) := (others=>'0'); constant c_n_priority_classes_w : natural := 2; type rcv_priority_vec is array (natural range <>) of unsigned(RCV_PRIORITY_W-1 downto 0); signal rcv_priority, rcv_priority_n : rcv_priority_vec(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); constant c_served_vec_len : natural := 2; -- max(CACHE_N_BANKS-1, 2); type served_vec is array (natural range <>) of std_logic_vector(c_served_vec_len-1 downto 0); signal cu_served : served_vec(N_CU-1 downto 0) := (others=>(others=>'0')); signal write_phase : unsigned(WRITE_PHASE_W-1 downto 0) := (others=>'0'); attribute max_fanout of write_phase : signal is 8; signal cu_served_n : std_logic_vector(N_CU-1 downto 0) := (others=>'0'); type rcv_to_read_priority_vec is array (natural range <>) of integer range 0 to N_RECEIVERS-1; signal rcv_to_read_pri : rcv_to_read_priority_vec(2**c_n_priority_classes_w-1 downto 0) := (others=>0); signal rcv_to_read_pri_n : rcv_to_read_priority_vec(2**c_n_priority_classes_w-1 downto 0) := (others=>0); signal rcv_to_write_pri : rcv_to_read_priority_vec(2**c_n_priority_classes_w-1 downto 0) := (others=>0); signal rcv_to_write_pri_n : rcv_to_read_priority_vec(2**c_n_priority_classes_w-1 downto 0) := (others=>0); signal rcv_to_read_pri_v_n : std_logic_vector(2**c_n_priority_classes_w-1 downto 0) := (others=>'0'); signal rcv_to_read_pri_v : std_logic_vector(2**c_n_priority_classes_w-1 downto 0) := (others=>'0'); signal rcv_to_write_pri_v_n : std_logic_vector(2**c_n_priority_classes_w-1 downto 0) := (others=>'0'); signal rcv_to_write_pri_v : std_logic_vector(2**c_n_priority_classes_w-1 downto 0) := (others=>'0'); --}}} -- write pipeline {{{ signal rcv_to_write, rcv_to_write_n : natural range 0 to N_RECEIVERS-1 := 0; attribute max_fanout of rcv_to_write : signal is 60; signal rcv_write_in_pipeline : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_write_in_pipeline_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal write_addr : cache_addr_array(3 downto 0) := (others=>(others=>'0')); signal rcv_will_write, rcv_will_write_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_will_write_d0 : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal write_word : std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); type write_word_rcv_indx_type is array (natural range <>) of integer range 0 to N_RECEIVERS-1; signal write_word_rcv_indx : write_word_rcv_indx_type(DATA_W/8*2**N-1 downto 0) := (others=>0); signal write_word_rcv_indx_n : write_word_rcv_indx_type(DATA_W/8*2**N-1 downto 0) := (others=>0); signal write_be_p0 : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); signal write_be_p0_n : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); signal stall_write_pipe : std_logic := '0'; signal write_v : std_logic_vector(3 downto 0) := (others=>'0'); signal write_v_n : std_logic := '0'; signal write_be : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); signal write_pipe_wrTag : tag_addr_array(4 downto 0) := (others=>(others=>'0')); signal write_pipe_wrTag_valid : std_logic_vector(4 downto 0) := (others=>'0'); signal write_addr_match : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal write_addr_match_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); --}}} -- fifos {{{ signal wr_fifo_cache_rqst : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal rd_fifo_cache_rqst : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_cache_ack : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal rd_fifo_cache_ack : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal wr_fifo_rqst_addr : cache_addr_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal rd_fifo_rqst_addr : cache_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0')); signal wr_fifo_dout : cache_word_array(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); signal cache_dob : std_logic_vector(DATA_W*2**N-1 downto 0) := (others=>'0'); signal rd_fifo_din_v : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal fifo_be_din : std_logic_vector(DATA_W/8*2**N-1 downto 0) := (others=>'0'); --}}} -- atomics -------------------------------------------------------------------------------------------{{{ signal flush_ack, flush_ack_n : std_logic := '0'; signal flush_done : std_logic := '0'; signal flush_rcv_index : integer range 0 to N_RECEIVERS-1 := 0; signal flush_rcv_index_n : integer range 0 to N_RECEIVERS-1 := 0; signal flush_v : std_logic := '0'; signal flush_gmem_addr : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); signal flush_data : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal atomic_can_finish : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} begin -- internal & fixed signals assignments -------------------------------------------------------------------------{{{ cu_ready <= cu_ready_i; axi_wvalid <= axi_wvalid_i; rdData <= rdData_i; finish_exec <= finish_exec_i; ---------------------------------------------------------------------------------------------------------}}} -- error handling ------------------------------------------------------------------------------------------- {{{ assert GMEM_WORD_ADDR_W-BRMEM_ADDR_W-CACHE_N_BANKS_W <= 24; assert CACHE_N_BANKS_W > 0 and CACHE_N_BANKS_W <= 3; assert (N_RECEIVERS/2**N)*2**N = N_RECEIVERS; assert N_AXI = 1 or N_AXI = 2 or N_AXI = 4; assert BURST_WORDS_W >= CACHE_N_BANKS_W; ---------------------------------------------------------------------------------------------------------------}}} -- cache -------------------------------------------------------------------------------------------{{{ cache_inst: entity cache port map( clk => clk, nrst => nrst, ena => '1', wea => cache_wea, addra => cache_addra, dia => cache_wrData, doa => rdData_i, enb => '1', enb_be => '1', wr_fifo_rqst_addr => wr_fifo_rqst_addr, rd_fifo_rqst_addr => rd_fifo_rqst_addr, wr_fifo_dout => wr_fifo_dout, dob => cache_dob, rd_fifo_din_v => rd_fifo_din_v, be_rdData => fifo_be_din, ticket_rqst_wr => wr_fifo_cache_rqst, ticket_rqst_rd => rd_fifo_cache_rqst, ticket_ack_wr_fifo=> wr_fifo_cache_ack, ticket_ack_rd_fifo=> rd_fifo_cache_ack ); ---------------------------------------------------------------------------------------------------------}}} -- write pipeline -------------------------------------------------------------------------------------- {{{ process(clk) begin if rising_edge(clk) then write_phase <= write_phase + 1; rcv_to_write_pri <= rcv_to_write_pri_n; rcv_to_write_pri_v <= rcv_to_write_pri_v_n; if stall_write_pipe = '0' or write_v(2) = '0' or write_v(1) = '0' or write_v(0) = '0'then --stage 0 rcv_to_write <= rcv_to_write_n; write_v(0) <= write_v_n; rcv_write_in_pipeline <= rcv_write_in_pipeline_n; end if; if stall_write_pipe = '0' or write_v(2) = '0' or write_v(1) = '0' then --stage 1 write_addr(1) <= write_addr(0); write_v(1) <= write_v(0); write_addr_match <= write_addr_match_n; end if; if stall_write_pipe = '0' or write_v(2) = '0' then -- stage 2 rcv_will_write <= rcv_will_write_n; write_word_rcv_indx <= write_word_rcv_indx_n; write_be_p0 <= write_be_p0_n; write_addr(2) <= write_addr(1); write_v(2) <= write_v(1); end if; -- write_be <= (others=>'0'); if stall_write_pipe = '0' then -- stage 3 rcv_will_write_d0 <= rcv_will_write; write_addr(3) <= write_addr(2); write_be <= (others=>'0'); write_v(3) <= write_v(2); write_be <= write_be_p0; if SUB_INTEGER_IMPLEMENT /= 0 then for k in 0 to DATA_W/8-1 loop for j in 0 to 2**N-1 loop write_word(j*DATA_W+(k+1)*8-1 downto j*DATA_W+k*8) <= rcv_gmem_data(write_word_rcv_indx(j*DATA_W/8+k))(8*(k+1)-1 downto 8*k); end loop; end loop; else for j in 0 to 2**N-1 loop write_word((j+1)*DATA_W-1 downto j*DATA_W) <= rcv_gmem_data(write_word_rcv_indx(j)); end loop; end if; end if; end if; end process; process(rcv_priority, rcv_request_write_addr, write_phase) variable indx : unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin indx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-WRITE_PHASE_W) := write_phase; for j in 0 to 2**c_n_priority_classes_w-1 loop rcv_to_write_pri_n(j) <= 0; rcv_to_write_pri_v_n(j) <= '0'; for i in 0 to N_RECEIVERS/2**WRITE_PHASE_W-1 loop indx(N_RECEIVERS_W-WRITE_PHASE_W-1 downto 0) := to_unsigned(i, N_RECEIVERS_W-WRITE_PHASE_W); if rcv_request_write_addr(to_integer(indx)) = '1' and to_integer(rcv_priority(to_integer(indx))(RCV_PRIORITY_W-1 downto RCV_PRIORITY_W-c_n_priority_classes_w)) = j then rcv_to_write_pri_n(j) <= to_integer(indx); rcv_to_write_pri_v_n(j) <= '1'; end if; end loop; end loop; end process; process(rcv_gmem_addr, rcv_to_write, write_v, rcv_request_write_data, rcv_to_write_pri_v, rcv_to_write_pri, rcv_be, write_addr_match, rcv_request_write_addr) variable rcv_indx : unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin rcv_to_write_n <= rcv_to_write; write_v_n <= '0'; rcv_write_in_pipeline_n <= (others=>'0'); -- stage 0: define the rcv indx to write for j in 2**c_n_priority_classes_w-1 downto 0 loop if rcv_to_write_pri_v(j) = '1' and rcv_request_write_addr(rcv_to_write_pri(j)) = '1' then rcv_to_write_n <= rcv_to_write_pri(j); write_v_n <= '1'; rcv_write_in_pipeline_n(rcv_to_write_pri(j)) <= '1'; exit; end if; end loop; -- stage 1: define the address to be written write_addr(0) <= rcv_gmem_addr(rcv_to_write)(M+L+N-1 downto N); write_addr_match_n <= (others=>'0'); for i in 0 to N_RECEIVERS-1 loop if rcv_gmem_addr(i)(M+L+N-1 downto N) = rcv_gmem_addr(rcv_to_write)(M+L+N-1 downto N) and rcv_request_write_data(i) = '1' then write_addr_match_n(i) <= '1'; end if; end loop; -- stage 2: define which receivers will write rcv_will_write_n <= (others=>'0'); write_word_rcv_indx_n <= (others=>0); write_be_p0_n <= (others=>'0'); if write_v(1) = '1' then if SUB_INTEGER_IMPLEMENT /= 0 then for k in 0 to DATA_W/8-1 loop for j in 0 to 2**N-1 loop for i in 0 to N_RECEIVERS-1 loop if write_addr_match(i) = '1' and to_integer(rcv_gmem_addr(i)(N-1 downto 0)) = j and rcv_be(i)(k) = '1' and rcv_request_write_data(i) = '1' then -- if rcv_gmem_addr(i)(M+L+N-1 downto N) = write_addr(1) and rcv_request_write_data(i) = '1' and -- to_integer(rcv_gmem_addr(i)(N-1 downto 0)) = j and rcv_be(i)(k) = '1' then rcv_will_write_n(i) <= '1'; write_word_rcv_indx_n(j*DATA_W/8+k) <= i; write_be_p0_n(j*DATA_W/8+k) <= '1'; -- exit; end if; end loop; end loop; end loop; else for j in 0 to 2**N-1 loop for i in 0 to N_RECEIVERS-1 loop if write_addr_match(i) = '1' and to_integer(rcv_gmem_addr(i)(N-1 downto 0)) = j and rcv_be(i)(0) = '1' and rcv_request_write_data(i) = '1' then rcv_will_write_n(i) <= '1'; write_word_rcv_indx_n(j) <= i; write_be_p0_n((j+1)*DATA_W/8-1 downto j*DATA_W/8) <= (others=>'1'); end if; end loop; end loop; end if; end if; -- stage 3: form the data word to be written end process; --------------------------------------------------------------------------------------------------------- }}} -- responder -------------------------------------------------------------------------------------------{{{ -- TODO: the effeciency of this should be studied on the real hardware read_priority_pipe_true: if ENABLE_READ_PRIORIRY_PIPE generate process(rcv_priority, rcv_perform_read, rcv_to_read_pri, cu_served) begin for j in 0 to 2**c_n_priority_classes_w-1 loop rcv_to_read_pri_n(j) <= rcv_to_read_pri(j); rcv_to_read_pri_v_n(j) <= '0'; for i in N_RECEIVERS-1 downto 0 loop if rcv_perform_read(i) = '1' and to_integer(rcv_priority(i)(RCV_PRIORITY_W-1 downto RCV_PRIORITY_W-c_n_priority_classes_w)) = j and cu_served(c_rcv_cu_indx(i)) = (c_served_vec_len-1 downto 0 => '0') then rcv_to_read_pri_n(j) <= i; rcv_to_read_pri_v_n(j) <= '1'; end if; end loop; end loop; end process; process(rcv_to_read_pri_v, rcv_to_read_pri, rcv_to_read, rcv_perform_read) begin rcv_to_read_n <= rcv_to_read; cache_read_v_p0_n <= '0'; cu_served_n <= (others=>'0'); for j in 2**c_n_priority_classes_w-1 downto 0 loop if rcv_to_read_pri_v(j) = '1' and rcv_perform_read(rcv_to_read_pri(j)) = '1' then rcv_to_read_n <= rcv_to_read_pri(j); cache_read_v_p0_n <= '1'; cu_served_n(c_rcv_cu_indx(rcv_to_read_pri(j))) <= '1'; exit; end if; end loop; end process; end generate; read_priority_pipe_false: if not ENABLE_READ_PRIORIRY_PIPE generate process(rcv_priority, rcv_perform_read, rcv_to_read_pri, cu_served) begin for j in 0 to 2**c_n_priority_classes_w-1 loop rcv_to_read_pri_n(j) <= rcv_to_read_pri(j); rcv_to_read_pri_v_n(j) <= '0'; for i in N_RECEIVERS-1 downto 0 loop if rcv_perform_read(i) = '1' and to_integer(rcv_priority(i)(RCV_PRIORITY_W-1 downto RCV_PRIORITY_W-c_n_priority_classes_w)) = j and cu_served(c_rcv_cu_indx(i)) = (0 to c_served_vec_len-1 => '0') then rcv_to_read_pri_n(j) <= i; rcv_to_read_pri_v_n(j) <= '1'; end if; end loop; end loop; end process; process(rcv_to_read_pri_v_n, rcv_to_read_pri_n, rcv_to_read) begin rcv_to_read_n <= rcv_to_read; cache_read_v_p0_n <= '0'; cu_served_n <= (others=>'0'); for j in 2**c_n_priority_classes_w-1 downto 0 loop if rcv_to_read_pri_v_n(j) = '1' then rcv_to_read_n <= rcv_to_read_pri_n(j); cache_read_v_p0_n <= '1'; cu_served_n(c_rcv_cu_indx(rcv_to_read_pri_n(j))) <= '1'; exit; end if; end loop; end process; end generate; process(clk) variable rcv_indx : unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then for i in 0 to N_CU-1 loop cu_served(i)(c_served_vec_len-2 downto 0) <= cu_served(i)(c_served_vec_len-1 downto 1); cu_served(i)(c_served_vec_len-1) <= cu_served_n(i); -- cu_served(i)(c_served_vec_len-1) <= '0'; end loop; rcv_to_read_pri_v <= rcv_to_read_pri_v_n; cache_read_v_p0 <= '0'; cache_wea <= cache_wea_n; cache_we <= cache_we_n; -- assert cache_we = '0' or cache_addra /= X"23" severity failure; --stage 0 (read) --stage 1 (read) cache_addra <= cache_addra_n; rdAddr_p1 <= rcv_gmem_addr(rcv_to_read)(GMEM_WORD_ADDR_W-1 downto N); -- stage 1(write) cache_wrData <= write_word; --stage 2 rdAddr_p0 <= rdAddr_p1; rcv_rd_done <= rcv_rd_done_n; --stage 3 rdAddr <= rdAddr_p0; rdAck <= (others=>'0'); for i in 0 to N_RECEIVERS-1 loop if rcv_rd_done(i) = '1' then rdAck(c_rcv_cu_indx(i)) <= '1'; end if; end loop; if nrst = '0' then cache_read_v <= '0'; cache_read_v_d0 <= '0'; rcv_to_read <= 0; rcv_to_read_pri <= (others=>0); else --stage 0 (read) rcv_to_read_pri <= rcv_to_read_pri_n; rcv_to_read <= rcv_to_read_n; cache_read_v_p0 <= cache_read_v_p0_n; --stage 1 (read) cache_read_v <= cache_read_v_p0; -- stage 1(write) --stage 2 cache_read_v_d0 <= cache_read_v; end if; end if; end process; -- process(rcv_gmem_addr, rcv_to_read, cache_read_v_p0, write_addr(3), write_v(3), cache_addra) -- begin -- cache_addra_n <= cache_addra; -- if cache_read_v_p0 = '1' then -- cache_addra_n <= rcv_gmem_addr(rcv_to_read)(L+M+N-1 downto N); -- elsif write_v(3) = '1' then -- cache_addra_n <= write_addr(3); -- end if; -- end process; process(rcv_gmem_addr, rcv_to_read, cache_read_v_p0, write_addr(3)) begin if cache_read_v_p0 = '1' then cache_addra_n <= rcv_gmem_addr(rcv_to_read)(L+M+N-1 downto N); else cache_addra_n <= write_addr(3); end if; end process; process(write_v(3), cache_read_v_p0, write_be) begin if write_v(3) = '0' or cache_read_v_p0 = '0' then stall_write_pipe <= '0'; else stall_write_pipe <= '1'; end if; cache_wea_n <= (others=>'0'); cache_we_n <= '0'; if write_v(3) = '1' and cache_read_v_p0 = '0' then cache_wea_n <= write_be; cache_we_n <= '1'; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- axi controllers --------------------------------------------------------------------------------------{{{ axi_cntrl: entity axi_controllers port map( clk => clk, axi_rdAddr => axi_rdAddr, axi_wrAddr => axi_wrAddr, wr_fifo_go => wr_fifo_go, axi_writer_go => axi_writer_go, axi_writer_ack => axi_writer_ack, axi_writer_id => axi_writer_id, wr_fifo_free => wr_fifo_free, axi_writer_free => axi_writer_free, wr_fifo_cache_rqst=> wr_fifo_cache_rqst, rd_fifo_cache_rqst=> rd_fifo_cache_rqst, wr_fifo_cache_ack => wr_fifo_cache_ack, rd_fifo_cache_ack => rd_fifo_cache_ack, wr_fifo_rqst_addr => wr_fifo_rqst_addr, rd_fifo_rqst_addr => rd_fifo_rqst_addr, wr_fifo_dout => wr_fifo_dout, cache_dob => cache_dob, rd_fifo_din_v => rd_fifo_din_v, fifo_be_din => fifo_be_din, axi_araddr => axi_araddr, axi_arvalid => axi_arvalid, axi_arready => axi_arready, axi_arid => axi_arid, axi_rdata => axi_rdata, axi_rlast => axi_rlast, axi_rvalid => axi_rvalid, axi_rready => axi_rready, axi_rid => axi_rid, axi_awaddr => axi_awaddr, axi_awvalid => axi_awvalid, axi_awready => axi_awready, axi_awid => axi_awid, axi_wdata => axi_wdata, axi_wstrb => axi_wstrb, axi_wlast => axi_wlast, axi_wvalid => axi_wvalid_i, axi_wready => axi_wready, axi_bvalid => axi_bvalid, axi_bready => axi_bready, axi_bid => axi_bid, nrst => nrst ); ---------------------------------------------------------------------------------------------------------}}} -- tags mem ------------------------------------------------------------------------------------------- {{{ process(write_addr, write_v, cache_addra, cache_we) begin for i in 0 to 3 loop write_pipe_wrTag(i) <= write_addr(i)(M+L-1 downto L); write_pipe_wrTag_valid(i) <= write_v(i); end loop; write_pipe_wrTag(4) <= cache_addra(M+L-1 downto L); write_pipe_wrTag_valid(4) <= cache_we; end process; tags_controller: entity gmem_cntrl_tag port map( clk => clk, wr_fifo_go => wr_fifo_go, axi_writer_go => axi_writer_go, axi_writer_ack => axi_writer_ack, axi_writer_id => axi_writer_id, wr_fifo_free => wr_fifo_free, axi_writer_free => axi_writer_free, axi_rd_fifo_filled=> rd_fifo_cache_ack, axi_rdAddr => axi_rdAddr, axi_wrAddr => axi_wrAddr, wr_fifo_cache_ack => wr_fifo_cache_ack, axi_wvalid => axi_wvalid_i, --receivers signals rcv_alloc_tag => rcv_alloc_tag, rcv_rnw => rcv_rnw, rcv_gmem_addr => rcv_gmem_addr, rcv_read_tag => rcv_read_tag, rcv_read_tag_ack => rcv_read_tag_ack, rdData_page_v => rdData_page_v, rdData_tag_v => rdData_tag_v, rdData_tag => rdData_tag, rcv_tag_written => rcv_tag_written, rcv_tag_updated => rcv_tag_updated, rcv_page_validated=> rcv_page_validated, -- it is a one-cycle message cache_we => cache_we, cache_addra => cache_addra, cache_wea => cache_wea, --finish WGsDispatched => WGsDispatched, CUs_gmem_idle => CUs_gmem_idle, rcv_all_idle => rcv_all_idle, rcv_idle => rcv_idle, finish_exec => finish_exec_i, start_kernel => start_kernel, clean_cache => clean_cache, atomic_can_finish => atomic_can_finish, -- write pipeline write_pipe_active => write_pipe_wrTag_valid, write_pipe_wrTag => write_pipe_wrTag, nrst => nrst ); ---------------------------------------------------------------------------------------------------------}}} -- atomics ----------------------------------------------------------------------------------------------{{{ atomics_if: if ATOMIC_IMPLEMENT /=0 generate atomics_inst: entity gmem_atomics port map( clk => clk, rcv_atomic_rqst => rcv_atomic_rqst, rcv_atomic_ack => rcv_atomic_ack, rcv_atomic_type => rcv_atomic_type, rcv_gmem_addr => rcv_gmem_addr, rcv_must_read => rcv_must_read, rcv_gmem_data => rcv_gmem_data, gmem_rdAddr_p0 => rdAddr_p0, gmem_rdData => rdData_i, gmem_rdData_v_p0 => cache_read_v_d0, rcv_retire => rcv_atomic_performed, atomic_rdData => atomic_rdData, flush_ack => flush_ack, flush_done => flush_done, flush_v => flush_v, flush_gmem_addr => flush_gmem_addr, flush_data => flush_data, finish => finish_exec_i, atomic_can_finish => atomic_can_finish, WGsDispatched => WGsDispatched, nrst => nrst ); end generate; ---------------------------------------------------------------------------------------------------------}}} -- receivers -------------------------------------------------------------------------------------------{{{ receivers_trans: process(clk) -- {{{ begin if rising_edge(clk) then rcv_gmem_addr <= rcv_gmem_addr_n; rcv_gmem_data <= rcv_gmem_data_n; rcv_be <= rcv_be_n; rcv_rnw <= rcv_rnw_n; cu_rnw_d0 <= cu_rnw; cu_we_d0 <= cu_we; cu_rqst_addr_d0 <= cu_rqst_addr; cu_wrData_d0 <= cu_wrData; if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_sgntr <= rcv_atomic_sgntr_n; rcv_atomic <= rcv_atomic_n; cu_atomic_d0 <= cu_atomic; cu_atomic_sgntr_d0 <= cu_atomic_sgntr; cu_atomic_ack_p0 <= (others=>'0'); if flush_ack = '1' then cu_atomic_d0(0) <= '0'; cu_rqst_addr_d0(0) <= flush_gmem_addr; cu_wrData_d0(0) <= flush_data; cu_we_d0(0) <= (others=>'1'); cu_rnw_d0(0) <= '0'; end if; for i in 0 to N_RECEIVERS-1 loop if rcv_atomic_performed(i) = '1' then cu_atomic_ack_p0(c_rcv_cu_indx(i)) <= '1'; end if; end loop; atomic_rdData_v <= cu_atomic_ack_p0; for i in 0 to N_RECEIVERS-1 loop if rcv_atomic_performed(i) = '1' then atomic_sgntr_p0 <= rcv_atomic_sgntr(i); end if; end loop; atomic_sgntr <= atomic_sgntr_p0; end if; if rcv_idle = (rcv_idle'reverse_range => '1') then rcv_all_idle <= '1'; else rcv_all_idle <= '0'; end if; rcv_priority <= rcv_priority_n; rcv_go <= rcv_go_n; for i in 0 to N_RECEIVERS-1 loop if rdData_tag(c_rcv_bank_indx(i)) = rcv_gmem_addr(i)(GMEM_WORD_ADDR_W-1 downto L+M+N) and rdData_tag_v(c_rcv_bank_indx(i)) = '1' then rcv_tag_compared(i) <= '1'; else rcv_tag_compared(i) <= '0'; end if; end loop; rdData_page_v_d0 <= rdData_page_v; rcv_wait_1st_cycle <= rcv_wait_1st_cycle_n; rcv_request_write_data <= rcv_request_write_data_n; if nrst = '0' then st_rcv <= (others=>get_addr); rcv_idle <= (others=>'0'); rcv_read_tag <= (others=>'0'); if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_rqst <= (others=>'0'); end if; rcv_alloc_tag <= (others=>'0'); rcv_perform_read <= (others=>'0'); rcv_request_write_addr <= (others=>'0'); else st_rcv <= st_rcv_n; rcv_idle <= rcv_idle_n; rcv_read_tag <= rcv_read_tag_n; if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_rqst <= rcv_atomic_rqst_n; end if; rcv_alloc_tag <= rcv_alloc_tag_n; rcv_perform_read <= rcv_perform_read_n; rcv_request_write_addr <= rcv_request_write_addr_n; end if; end if; end process; -- }}} rcv_comb: for i in 0 to N_RECEIVERS-1 generate begin rcv_com: process (st_rcv(i), rcv_gmem_addr(i), cu_rqst_addr_d0(c_rcv_cu_indx(i)), rcv_read_tag(i), rcv_be(i), rcv_rnw(i), rcv_idle(i), -- {{{ rcv_write_in_pipeline(i), cu_we_d0(c_rcv_cu_indx(i)), rcv_tag_compared(i), rcv_go(i), rcv_read_tag_ack(i), rcv_atomic_sgntr(i), rcv_alloc_tag(i), rdData_page_v_d0(c_rcv_bank_indx(i)), rcv_atomic_rqst(i), cu_rnw_d0(c_rcv_cu_indx(i)), cu_wrData_d0(c_rcv_cu_indx(i)), rcv_tag_written(i), rcv_tag_updated(i), rcv_request_write_addr(i), rcv_request_write_data(i), rcv_perform_read(i), cache_addra, cache_read_v, rcv_page_validated(i), cache_we, rcv_will_write(i), rcv_gmem_data(i), rcv_priority(i), rcv_atomic_ack(i), rcv_will_write_d0(i), rcv_wait_1st_cycle(i), cu_atomic_d0(c_rcv_cu_indx(i)), rcv_atomic(i), rcv_must_read(i), rcv_atomic_performed(i), cu_atomic_sgntr_d0(c_rcv_cu_indx(i))) variable li : line; -- }}} begin -- assignments {{{ st_rcv_n(i) <= st_rcv(i); rcv_gmem_addr_n(i) <= rcv_gmem_addr(i); rcv_gmem_data_n(i) <= rcv_gmem_data(i); rcv_read_tag_n(i) <= rcv_read_tag(i); if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_rqst_n(i) <= rcv_atomic_rqst(i); end if; rcv_rnw_n(i) <= rcv_rnw(i); rcv_atomic_n(i) <= rcv_atomic(i); rcv_perform_read_n(i) <= rcv_perform_read(i); rcv_request_write_addr_n(i) <= rcv_request_write_addr(i); rcv_request_write_data_n(i) <= rcv_request_write_data(i); rcv_wait_1st_cycle_n(i) <= rcv_wait_1st_cycle(i); rcv_alloc_tag_n(i) <= rcv_alloc_tag(i); rcv_be_n(i) <= rcv_be(i); rcv_atomic_sgntr_n(i) <= rcv_atomic_sgntr(i); rcv_idle_n(i) <= rcv_idle(i); rcv_priority_n(i) <= rcv_priority(i); rcv_rd_done_n(i) <= '0'; --}}} case st_rcv(i) is when get_addr => -- {{{ -- rcv_be_n(i) <= (others=>'0'); rcv_idle_n(i) <= '1'; rcv_wait_1st_cycle_n(i) <= '0'; rcv_request_write_data_n(i) <= '0'; rcv_priority_n(i) <= (others=>'0'); rcv_rnw_n(i) <= cu_rnw_d0(c_rcv_cu_indx(i)); if rcv_go(i) = '1' then rcv_gmem_addr_n(i) <= unsigned(cu_rqst_addr_d0(c_rcv_cu_indx(i))); rcv_be_n(i) <= cu_we_d0(c_rcv_cu_indx(i)); rcv_atomic_sgntr_n(i) <= cu_atomic_sgntr_d0(c_rcv_cu_indx(i)); rcv_gmem_data_n(i) <= cu_wrData_d0(c_rcv_cu_indx(i)); rcv_atomic_n(i) <= cu_atomic_d0(c_rcv_cu_indx(i)); -- assert to_integer(unsigned(cu_rqst_addr_d0(c_rcv_cu_indx(i)))) = 792 or cu_rnw_d0(c_rcv_cu_indx(i)) = '1' severity failure; if cu_atomic_d0(c_rcv_cu_indx(i)) = '0' then st_rcv_n(i) <= get_read_tag_ticket; rcv_read_tag_n(i) <= '1'; else st_rcv_n(i) <= requesting_atomic; if ATOMIC_IMPLEMENT /= 0 then rcv_atomic_rqst_n(i) <= '1'; end if; end if; rcv_idle_n(i) <= '0'; end if; -- }}} when requesting_atomic => -- {{{ if ATOMIC_IMPLEMENT /= 0 then rcv_priority_n(i) <= rcv_priority(i) + 1; if rcv_priority(i) = (rcv_priority(i)'reverse_range=>'1') then rcv_atomic_rqst_n(i) <= '1'; end if; if rcv_atomic_ack(i) = '1' then rcv_atomic_rqst_n(i) <= '0'; end if; if rcv_must_read(i) = '1' then -- rcv_must_read & rcv_atomic_performed cann't be at 1 simultaneously rcv_atomic_rqst_n(i) <= '0'; rcv_rnw_n(i) <= '1'; st_rcv_n(i) <= get_read_tag_ticket; rcv_read_tag_n(i) <= '1'; end if; if rcv_atomic_performed(i) = '1' then rcv_atomic_rqst_n(i) <= '0'; st_rcv_n(i) <= get_addr; end if; end if; -- }}} when get_read_tag_ticket => -- rdAddr of tag mem is being selected {{{ if rcv_read_tag_ack(i) = '1' then st_rcv_n(i) <= wait_read_tag; rcv_read_tag_n(i) <= '0'; end if; -- }}} when wait_read_tag => --address is fixed and tag mem is being read {{{ rcv_wait_1st_cycle_n(i) <= '1'; if rcv_tag_written(i) = '1' then if rcv_rnw(i) = '1' then st_rcv_n(i) <= clean; rcv_alloc_tag_n(i) <= '1'; else if rcv_rnw(i) = '1' then st_rcv_n(i) <= read_cache; rcv_perform_read_n(i) <= '1'; else st_rcv_n(i) <= request_write_addr; rcv_request_write_addr_n(i) <= '1'; rcv_request_write_data_n(i) <= '1'; end if; end if; elsif rcv_tag_updated(i) = '1' then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; else if rcv_wait_1st_cycle(i) = '1' then if rcv_rnw(i) = '1' then st_rcv_n(i) <= check_tag_rd; else st_rcv_n(i) <= check_tag_wr; end if; end if; end if; --}}} when check_tag_rd => -- rdData of tag mem are ready {{{ if rcv_tag_updated(i) = '1' or (rcv_tag_written(i) = '0' and rcv_tag_compared(i) = '0') then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; elsif rcv_tag_compared(i) = '1' and rdData_page_v_d0(c_rcv_bank_indx(i)) = '1' then st_rcv_n(i) <= read_cache; rcv_perform_read_n(i) <= '1'; elsif rcv_page_validated(i) = '0' then --if rcv_rnw(i) = '1' and ( rcv_tag_written(i) = '1' or (rcv_tag_compared(i) = '1' and rdData_page_v_d0(c_rcv_bank_indx(i)) = '0' ) ) the st_rcv_n(i) <= clean; rcv_alloc_tag_n(i) <= '1'; else st_rcv_n(i) <= read_cache; rcv_perform_read_n(i) <= '1'; end if; -- }}} when check_tag_wr => -- rdData of tag mem are ready {{{ if rcv_tag_updated(i) = '1' or (rcv_tag_written(i) = '0' and rcv_tag_compared(i) = '0') then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; elsif rcv_tag_written(i) = '1' or rcv_tag_compared(i) = '1' then st_rcv_n(i) <= request_write_addr; rcv_request_write_addr_n(i) <= '1'; rcv_request_write_data_n(i) <= '1'; else st_rcv_n(i) <= clean; rcv_alloc_tag_n(i) <= '1'; end if; --}}} when alloc_tag => -- {{{ if rcv_tag_written(i) = '1' then if rcv_rnw(i) = '1' then st_rcv_n(i) <= clean; else st_rcv_n(i) <= request_write_addr; rcv_request_write_addr_n(i) <= '1'; rcv_request_write_data_n(i) <= '1'; rcv_alloc_tag_n(i) <= '0'; end if; end if; --}}} when clean => --{{{ if rcv_tag_updated(i) = '1' then st_rcv_n(i) <= alloc_tag; elsif rcv_page_validated(i) = '1' then rcv_alloc_tag_n(i) <= '0'; if rcv_rnw(i) = '1' then st_rcv_n(i) <= read_cache; rcv_perform_read_n(i) <= '1'; else st_rcv_n(i) <= request_write_addr; rcv_request_write_addr_n(i) <= '1'; rcv_request_write_data_n(i) <= '1'; end if; end if; -- }}} when read_cache => -- {{{ if rcv_tag_updated(i) = '1' then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; rcv_perform_read_n(i) <= '0'; elsif (cache_addra = rcv_gmem_addr(i)(L+M+N-1 downto N)) and cache_read_v = '1' then rcv_perform_read_n(i) <= '0'; if ATOMIC_IMPLEMENT /= 0 and rcv_atomic(i) = '1' then rcv_atomic_rqst_n(i) <= '1'; st_rcv_n(i) <= requesting_atomic; else st_rcv_n(i) <= get_addr; rcv_idle_n(i) <= '1'; rcv_rd_done_n(i) <= '1'; end if; end if; if rcv_priority(i) /= (rcv_priority(i)'reverse_range=>'1') then rcv_priority_n(i) <= rcv_priority(i) + 1; end if; -- }}} when request_write_addr => -- {{{ if rcv_tag_updated(i) = '1' then st_rcv_n(i) <= alloc_tag; rcv_alloc_tag_n(i) <= '1'; rcv_request_write_addr_n(i) <= '0'; rcv_request_write_data_n(i) <= '0'; elsif rcv_will_write(i) = '1' then rcv_request_write_addr_n(i) <= '0'; rcv_request_write_data_n(i) <= '0'; st_rcv_n(i) <= write_cache; elsif rcv_write_in_pipeline(i) = '1' then rcv_request_write_addr_n(i) <= '0'; st_rcv_n(i) <= request_write_data; end if; if rcv_priority(i) /= (rcv_priority(i)'reverse_range=>'1') then rcv_priority_n(i) <= rcv_priority(i) + 1; end if; -- }}} when request_write_data => -- {{{ if rcv_will_write(i) = '1' then st_rcv_n(i) <= write_cache; rcv_request_write_data_n(i) <= '0'; end if; -- }}} when write_cache=> -- {{{ -- assert std_logic_vector(rcv_gmem_addr(i)(15 downto 0)) = rcv_gmem_data(i)(15 downto 0); if cache_we = '1' and rcv_will_write_d0(i) = '0' then st_rcv_n(i) <= get_addr; rcv_idle_n(i) <= '1'; end if; -- }}} end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- interface to CUs ----------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then cu_ready_i <= cu_ready_n; cuIndx_msb <= not cuIndx_msb; if ATOMIC_IMPLEMENT /= 0 then flush_ack <= flush_ack_n; flush_rcv_index <= flush_rcv_index_n; flush_done <= rcv_idle(flush_rcv_index); end if; end if; end process; process(cu_valid, cu_ready_i, rcv_idle, cuIndx_msb, rcv_idle_n, flush_v, flush_ack, flush_rcv_index) variable rcvIndx: unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin rcv_go_n <= (others=>'0'); -- setting ready signal for CU0 cu_ready_n(0) <= '0'; flush_ack_n <= '0'; if ATOMIC_IMPLEMENT /= 0 then flush_rcv_index_n <= flush_rcv_index; end if; for j in N_RECEIVERS_CU/2-1 downto 0 loop rcvIndx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-max(N_CU_W, 1)) := to_unsigned(0, max(1, N_CU_W)); rcvIndx(N_RECEIVERS_CU_W-1) := not cuIndx_msb; rcvIndx(N_RECEIVERS_CU_W-2 downto 0) := to_unsigned(j, N_RECEIVERS_CU_W-1); if rcv_idle_n(to_integer(rcvIndx)) = '1' then if ATOMIC_IMPLEMENT /= 0 and flush_v = '1' and flush_ack = '0' then flush_ack_n <= '1'; cu_ready_n(0) <= '0'; else flush_ack_n <= '0'; cu_ready_n(0) <= '1'; end if; end if; end loop; -- starting receviers for CU0 if (cu_valid(0) = '1' and cu_ready_i(0) = '1') or (ATOMIC_IMPLEMENT /= 0 and flush_v = '1' and flush_ack = '1' ) then for j in N_RECEIVERS_CU/2-1 downto 0 loop rcvIndx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-max(1,N_CU_W)) := to_unsigned(0, max(1, N_CU_W)); rcvIndx(N_RECEIVERS_CU_W-1) := cuIndx_msb; rcvIndx(N_RECEIVERS_CU_W-2 downto 0) := to_unsigned(j, N_RECEIVERS_CU_W-1); if rcv_idle(to_integer(rcvIndx)) = '1' then rcv_go_n(to_integer(rcvIndx)) <= '1'; flush_rcv_index_n <= to_integer(rcvIndx); exit; end if; end loop; end if; -- other receivers if N_CU > 1 then for i in 1 to max(N_CU-1,1) loop -- starting receviers if cu_valid(i) = '1' and cu_ready_i(i) = '1' then for j in N_RECEIVERS_CU/2-1 downto 0 loop rcvIndx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-max(1,N_CU_W)) := to_unsigned(i, max(1, N_CU_W)); rcvIndx(N_RECEIVERS_CU_W-1) := cuIndx_msb; rcvIndx(N_RECEIVERS_CU_W-2 downto 0) := to_unsigned(j, N_RECEIVERS_CU_W-1); if rcv_idle(to_integer(rcvIndx)) = '1' then rcv_go_n(to_integer(rcvIndx)) <= '1'; exit; end if; end loop; end if; -- setting ready signal cu_ready_n(i) <= '0'; for j in N_RECEIVERS_CU/2-1 downto 0 loop rcvIndx(N_RECEIVERS_W-1 downto N_RECEIVERS_W-max(N_CU_W, 1)) := to_unsigned(i, max(1, N_CU_W)); rcvIndx(N_RECEIVERS_CU_W-1) := not cuIndx_msb; rcvIndx(N_RECEIVERS_CU_W-2 downto 0) := to_unsigned(j, N_RECEIVERS_CU_W-1); if rcv_idle_n(to_integer(rcvIndx)) = '1' then cu_ready_n(c_rcv_cu_indx(to_integer(rcvIndx))) <= '1'; end if; end loop; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

c73c7819336b346f5269cc9c0c1e7f25

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_4_CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

4583efed39b90b089d2a0fed0ed4e53b

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ed68248997189b34ae774a791a7d9c95

viccuad/fpga-thingies

tron/ps2KeyboardInterface.vhd

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY ps2KeyboardInterface IS PORT ( clk: IN std_logic; rst: IN std_logic; ps2Clk: IN std_logic; ps2Data: IN std_logic; data: OUT std_logic_vector (7 DOWNTO 0); newData: OUT std_logic; newDataAck: IN std_logic ); END ps2KeyboardInterface; ARCHITECTURE ps2KeyboardInterfaceArch OF ps2KeyboardInterface IS SIGNAL ldData, validData, lastBitRcv, ps2ClkSync, ps2ClkFallingEdge: std_logic; SIGNAL ps2DataRegOut: std_logic_vector(10 DOWNTO 0); SIGNAL goodParity: std_logic; BEGIN synchronizer: PROCESS (rst, clk) VARIABLE aux1: std_logic; BEGIN IF (rst='0') THEN aux1 := '1'; ps2ClkSync <= '1'; ELSIF (clk'EVENT AND clk='1') THEN ps2ClkSync <= aux1; aux1 := ps2Clk; END IF; END PROCESS synchronizer; edgeDetector: PROCESS (rst, clk) VARIABLE aux1, aux2: std_logic; BEGIN ps2ClkFallingEdge <= (NOT aux1) AND aux2; IF (rst='0') THEN aux1 := '1'; aux2 := '1'; ELSIF (clk'EVENT AND clk='1') THEN aux2 := aux1; aux1 := ps2ClkSync; END IF; END PROCESS edgeDetector; ps2DataReg: PROCESS (rst, clk) BEGIN IF (rst='0') THEN ps2DataRegOut <= (OTHERS =>'1'); ELSIF (clk'EVENT AND clk='1') THEN IF (lastBitRcv='1') THEN ps2DataRegOut <= (OTHERS=>'1'); ELSIF (ps2ClkFallingEdge='1') THEN ps2DataRegOut <= ps2Data & ps2DataRegOut(10 downto 1); END IF; END IF; END PROCESS ps2DataReg; oddParityCheker: goodParity <= ((ps2DataRegOut(9) XOR ps2DataRegOut(8)) XOR (ps2DataRegOut(7) XOR ps2DataRegOut(6))) XOR ((ps2DataRegOut(5) XOR ps2DataRegOut(4)) XOR (ps2DataRegOut(3) XOR ps2DataRegOut(2))) XOR ps2DataRegOut(1); lastBitRcv <= NOT ps2DataRegOut(0); validData <= lastBitRcv AND goodParity; dataReg: PROCESS (rst, clk) BEGIN IF (rst='0') THEN data <= (OTHERS=>'0'); ELSIF (clk'EVENT AND clk='1') THEN IF (ldData='1') THEN data <= ps2DataRegOut(8 downto 1); END IF; END IF; END PROCESS dataReg; controller: PROCESS (validData, rst, clk) TYPE states IS (waitingData, waitingNewDataAck); VARIABLE state: states; BEGIN ldData <= '0'; newData <= '0'; CASE state IS WHEN waitingData => IF (validData='1') THEN ldData <= '1'; END IF; WHEN waitingNewDataAck => newData <= '1'; WHEN OTHERS => NULL; END CASE; IF (rst='0') THEN state := waitingData; ELSIF (clk'EVENT AND clk='1') THEN CASE state IS WHEN waitingData => IF (validData='1') THEN state := waitingNewDataAck; END IF; WHEN waitingNewDataAck => IF (newDataAck='1') THEN state := waitingData; END IF; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS controller; END ps2KeyboardInterfaceArch;

gpl-3.0

78f8e9af873e7cfed535c7ee26d5b447

viccuad/fpga-thingies

monophonic_keyb/keyboard.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity keyboard is port( clk: IN std_logic; rst: IN std_logic; ps2Clk: IN std_logic; ps2Data: IN std_logic; segs : out STD_LOGIC_VECTOR (6 downto 0); altavoz: OUT std_logic ); end keyboard; architecture Behavioral of keyboard is component ps2KeyboardInterface port ( clk: IN std_logic; rst: IN std_logic; ps2Clk: IN std_logic; ps2Data: IN std_logic; data: OUT std_logic_vector (7 DOWNTO 0); newData: OUT std_logic; newDataAck: IN std_logic ); end component; type fsm_estados is (esperando, pulsada, despulsarPosible); signal estado: fsm_estados; signal scancode: std_logic_vector (7 downto 0); signal newData: std_logic; signal newDataAck: std_logic; signal letra: std_logic_vector (7 downto 0); signal in_semiperiodo: std_logic_vector (17 downto 0); signal out_semiperiodo: std_logic_vector (17 downto 0); signal cuentacont: std_logic_vector (17 downto 0); signal onda: std_logic; signal silencio: std_logic; signal clSemiper: std_logic; signal clLetra: std_logic; signal ldLetra: std_logic; signal ldNewNote: std_logic; signal st : std_logic_vector (2 downto 0); begin interfaz_ps2: ps2KeyboardInterface port map ( rst => rst, clk => clk, ps2Clk => ps2Clk, ps2Data => ps2Data, data => scancode, newData => newData, newDataAck => newDataAck ); --tabla memoria para convertir codigo de teclas al semiperiodo de la nota memoria_notas: process(letra) begin case letra is when "00011100" => in_semiperiodo <= "010111010101001101"; --A(1C): do when "00011101" => in_semiperiodo <= "010110000001001011"; --W(1D): do# when "00011011" => in_semiperiodo <= "010100110010000000"; --S(1B): re when "00100100" => in_semiperiodo <= "010011100111101000"; --E(24): re# when "00100011" => in_semiperiodo <= "010010100001001001"; --D(23): mi when "00101011" => in_semiperiodo <= "010001011110101000"; --F(2B): fa when "00101100" => in_semiperiodo <= "010000011111101111"; --T(2C): fa# when "00110100" => in_semiperiodo <= "001111100100011111"; --G(34): sol when "00110101" => in_semiperiodo <= "001110101100001000"; --Y(35): sol# when "00110011" => in_semiperiodo <= "001101110111110010"; --H(33): la when "00111100" => in_semiperiodo <= "001101000101111001"; --U(3C): la# when "00111011" => in_semiperiodo <= "001100010110111001"; --J(3b): si when "01000010" => in_semiperiodo <= "001011101010011101"; --K(42): do when "00000000" => in_semiperiodo <= "000000000000000000"; -- silencio when others => in_semiperiodo <= "000000000000000000"; -- silencio end case; end process memoria_notas; --maquina de estados----------------------------------------------------- controladorEstados: process (clk, rst, newData, scancode) begin if(rst = '0') then estado <= esperando; elsif (clk'event and clk = '1') then estado <= esperando; -- estado por defecto, puede ser sobreescrito luego case estado is when esperando => if (newData = '1') then estado <= pulsada; else estado <= esperando; end if; when pulsada => if (newData = '1' and scancode /= "11110000") then --11110000: F0 estado <= pulsada; elsif (newData = '1' and scancode = "11110000") then --11110000: F0 estado <= despulsarPosible; else estado <= pulsada; end if; when despulsarPosible => if (newData = '1' and scancode = letra) then estado <= esperando; elsif (newData = '1' and scancode /= letra) then estado <= pulsada; else estado <= despulsarPosible; end if; end case; end if; end process; generadorSalidaMealy: process (newDataAck, scancode, estado, newData, letra) begin --inicializamos: newDataAck <= '0'; clLetra <= '0'; ldletra <= '0'; case estado is when esperando => if (newData = '1') then ldletra <= '1'; ldNewNote <= '1'; newDataAck <= '1'; end if; when pulsada => if (newData = '1') then --esto contiene las 2 posibles transiciones newDataAck <= '1'; ldletra <= '0'; end if; when despulsarPosible => if (newData = '1') then if (scancode = letra) then clLetra <= '1'; newDataAck <= '1'; ldNewNote <= '1'; else newDataAck <= '1'; end if; end if; when others => newDataAck <= '0'; end case; end process; generadorSalidaMoore: process (estado) --genera st begin case estado is when esperando => st <= "000"; when pulsada => st <= "001"; when despulsarPosible => st <= "010"; end case; end process; conversor7seg: process(st) begin case st is -- gfedcba when "000" => segs <= "0111111"; -- cerrado: Locked when "001" => segs <= "0000110"; when "010" => segs <= "1011011"; when "011" => segs <= "1001111"; when others => segs <= "1111001"; -- error end case; end process; ----------------------------------------------------------------------------- oscilador18bits: process(clk,rst,clSemiper) begin if(rst = '0')then cuentacont <= (others => '0'); onda <= '0'; --reset biestable T elsif(clk'event and clk = '1') then if (clSemiper = '1') then cuentacont <= (others => '0'); onda <= not onda; else cuentacont <= cuentacont + 1; end if; end if; end process oscilador18bits; generadorSonido: process(clk,rst,out_semiperiodo,cuentacont,letra,onda,silencio) begin if(rst = '0')then -- registro SemiPer out_semiperiodo <= (others => '0'); elsif(clk'event and clk = '1' and ldNewNote = '1') then out_semiperiodo <= in_semiperiodo; end if; if (out_semiperiodo = cuentaCont) then -- comparador del oscilador clSemiper <= '1'; else clSemiper <= '0'; end if; if (letra = "00000000") then -- puerta NOR para generar silencio silencio <= '1'; else silencio <= '0'; end if; altavoz <= onda or silencio; -- puerta OR para generar onda del sonido end process generadorSonido; registroLetra: process(rst,clk,ldLetra,clLetra) begin if(rst = '0')then letra <= (others => '0'); elsif(clk'event and clk = '1' ) then if (clLetra = '1') then letra <= (others => '0'); elsif (ldLetra = '1') then letra <= scancode; end if; end if; end process registroLetra; end Behavioral;

gpl-3.0

3633647b11a440478f2fc2cd4612c004

preusser/q27

src/vhdl/PoC/fifo/fifo.pkg.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- Patrick Lehmann -- -- Package: VHDL package for component declarations, types and functions -- associated to the PoC.fifo namespace -- -- Description: -- ------------------------------------ -- For detailed documentation see below. -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library poc; use PoC.utils.all; package fifo is -- Minimal FIFO with single clock to decouple enable domains. component fifo_glue generic ( D_BITS : positive -- Data Width ); port ( -- Control clk : in std_logic; -- Clock rst : in std_logic; -- Synchronous Reset -- Input put : in std_logic; -- Put Value di : in std_logic_vector(D_BITS - 1 downto 0); -- Data Input ful : out std_logic; -- Full -- Output vld : out std_logic; -- Data Available do : out std_logic_vector(D_BITS - 1 downto 0); -- Data Output got : in std_logic -- Data Consumed ); end component; -- Minimal Local-Link-FIFO with single clock and first-word-fall-through mode. component fifo_ll_glue generic ( D_BITS : positive; FRAME_USER_BITS : natural; REGISTER_PATH : boolean ); port ( clk : in std_logic; reset : in std_logic; -- in port sof_in : in std_logic; data_in : in std_logic_vector(D_BITS downto 1); frame_data_in : in std_logic_vector(imax(1, FRAME_USER_BITS) downto 1); eof_in : in std_logic; src_rdy_in : in std_logic; dst_rdy_in : out std_logic; -- out port sof_out : out std_logic; data_out : out std_logic_vector(D_BITS downto 1); frame_data_out : out std_logic_vector(imax(1, FRAME_USER_BITS) downto 1); eof_out : out std_logic; src_rdy_out : out std_logic; dst_rdy_out : in std_logic ); end component; -- Simple FIFO backed by a shift register. component fifo_shift generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive -- Minimum FIFO Size in Words ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data ful : out std_logic; -- Capacity Exhausted -- Reading Interface got : in std_logic; -- Read Done Strobe dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data vld : out std_logic -- Data Valid ); end component; -- Full-fledged FIFO with single clock domain using on-chip RAM. component fifo_cc_got generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers STATE_REG : boolean := false; -- Registered Full/Empty Indicators OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Global Reset and Clock rst, clk : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data full : out std_logic; estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0); -- Reading Interface got : in std_logic; -- Read Completed dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0) ); end component; component fifo_dc_got_sm generic ( D_BITS : positive; MIN_DEPTH : positive); port ( clk_wr : in std_logic; rst_wr : in std_logic; put : in std_logic; din : in std_logic_vector(D_BITS - 1 downto 0); full : out std_logic; clk_rd : in std_logic; rst_rd : in std_logic; got : in std_logic; valid : out std_logic; dout : out std_logic_vector(D_BITS - 1 downto 0)); end component; component fifo_ic_got generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Write Interface clk_wr : in std_logic; rst_wr : in std_logic; put : in std_logic; din : in std_logic_vector(D_BITS - 1 downto 0); full : out std_logic; estate_wr : out std_logic_vector(imax(ESTATE_WR_BITS - 1, 0) downto 0); -- Read Interface clk_rd : in std_logic; rst_rd : in std_logic; got : in std_logic; valid : out std_logic; dout : out std_logic_vector(D_BITS - 1 downto 0); fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS - 1, 0) downto 0) ); end component; component fifo_cc_got_tempput generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers STATE_REG : boolean := false; -- Registered Full/Empty Indicators OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Global Reset and Clock rst, clk : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data full : out std_logic; estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0); commit : in std_logic; rollback : in std_logic; -- Reading Interface got : in std_logic; -- Read Completed dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0) ); end component; component fifo_cc_got_tempgot is generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers STATE_REG : boolean := false; -- Registered Full/Empty Indicators OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Global Reset and Clock rst, clk : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data full : out std_logic; estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0); -- Reading Interface got : in std_logic; -- Read Completed dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0); commit : in std_logic; rollback : in std_logic ); end component; end fifo; package body fifo is end fifo;

agpl-3.0

071b4b9fde2537657c6babb8da0bb25c

jcowgill/cs-dacs-robot

Common/AsyncRxTest.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY AsyncRxTest IS END AsyncRxTest; ARCHITECTURE behavioral OF AsyncRxTest IS COMPONENT AsyncRx PORT ( Q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); UPDATE : OUT STD_LOGIC; RX : IN STD_LOGIC; CLK : IN STD_LOGIC; CLR : IN STD_LOGIC); END COMPONENT; SIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL UPDATE : STD_LOGIC; SIGNAL RX : STD_LOGIC; SIGNAL CLK : STD_LOGIC; SIGNAL CLR : STD_LOGIC; BEGIN UUT: AsyncRx PORT MAP( Q => Q, UPDATE => UPDATE, RX => RX, CLK => CLK, CLR => CLR ); clk_process : PROCESS BEGIN -- Clock signal (4 MHz) CLK <= '0'; WAIT FOR 125ns; CLK <= '1'; WAIT FOR 125ns; END PROCESS; tb_process : PROCESS BEGIN -- Reset CLR <= '1'; WAIT FOR 1000ns; CLR <= '0'; -- Send some crap over WAIT FOR 2000ns; RX <= '1'; WAIT FOR 1us; RX <= '0'; WAIT FOR 4us; RX <= '1'; WAIT FOR 4us; RX <= '0'; WAIT FOR 4us; RX <= '0'; WAIT FOR 4us; RX <= '0'; WAIT FOR 4us; RX <= '1'; WAIT FOR 4us; RX <= '1'; WAIT; END PROCESS; END;

apache-2.0

fdf560b394e966f402265b1010dc3ea2

wltr/cern-fgclite

critical_fpga/src/rtl/cf/xf.vhd

------------------------------------------------------------------------------- --! @file xf.vhd --! @author Johannes Walter <[email protected]> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-08 --! @brief Auxiliary FPGA communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.xf_pkg.all; use work.nf_pkg.all; --! @brief Entity declaration of xf --! @details --! This component handles the NanoFIP communication and provides a --! synchronization mechanism with the field-bus cycle. entity xf is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Auxiliary FPGA interface --! @{ --! Inputs xf_i : in xf_in_t; --! Outputs xf_o : out xf_out_t; --! @} --! @name Internal interface --! @{ --! Millisecond strobe indicating start of cycle ms_0_strobe_i : in std_ulogic; --! Millisecond strobe indicating start of second millisecond ms_1_strobe_i : in std_ulogic; --! Commands command_i : in nf_command_t; --! @} --! @name Auxiliary FPGA data --! @{ --! DIM analogue data dim_o : out std_ulogic_vector(19 downto 0); --! DIM analogue data enable dim_en_o : out std_ulogic; --! DIM trigger number dim_trig_num_o : out std_ulogic_vector(3 downto 0); --! DIM latched trigger dim_trig_lat_o : out std_ulogic; --! DIM unlatched trigger dim_trig_unl_o : out std_ulogic; --! Backplane type backplane_type_o : out std_ulogic_vector(7 downto 0); --! Backplane type enable backplane_type_en_o : out std_ulogic; --! XF and PF versions version_xfpf_o : out std_ulogic_vector(7 downto 0); --! XF and PF versions enable version_xfpf_en_o : out std_ulogic; --! Single-event upset (SEU) count seu_count_o : out std_ulogic_vector(7 downto 0); --! Single-event upset (SEU) count enable seu_count_en_o : out std_ulogic; --! 1-wire scan busy ow_scan_busy_o : out std_ulogic; --! @} --! @name DIM data --! @{ --! Address dim_addr_i : in std_ulogic_vector(6 downto 0); --! Read enable dim_rd_en_i : in std_ulogic; --! Data output dim_data_o : out std_ulogic_vector(15 downto 0); --! Data output enable dim_data_en_o : out std_ulogic; --! @} --! @name One-wire data --! @{ --! Address ow_addr_i : in std_ulogic_vector(5 downto 0); --! Read enable ow_rd_en_i : in std_ulogic; --! Data output ow_data_o : out std_ulogic_vector(79 downto 0); --! Data output enable ow_data_en_o : out std_ulogic); --! @} end entity xf; --! RTL implementation of xf architecture rtl of xf is --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal ow_scan_busy : std_ulogic; signal dim_trigger : std_ulogic; signal dim_reset : std_ulogic; signal ow_scan : std_ulogic; signal ow_bus_select : std_ulogic_vector(2 downto 0); --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal xf_rx_data_0 : std_ulogic_vector(41 downto 0); signal xf_rx_data_en_0 : std_ulogic; signal xf_rx_error_0 : std_ulogic; signal xf_rx_data_1 : std_ulogic_vector(83 downto 0); signal xf_rx_data_en_1 : std_ulogic; signal xf_rx_error_1 : std_ulogic; signal dim_addr : std_ulogic_vector(6 downto 0); signal ow_addr : std_ulogic_vector(5 downto 0); --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- xf_o.dim_trig <= dim_trigger; xf_o.dim_rst <= dim_reset; xf_o.ow_trig <= ow_scan; xf_o.ow_bus_select <= ow_bus_select; backplane_type_o <= "00" & xf_rx_data_0(13 downto 8); backplane_type_en_o <= xf_rx_data_en_0; version_xfpf_o <= xf_rx_data_0(7 downto 0); version_xfpf_en_o <= xf_rx_data_en_0; seu_count_o <= xf_rx_data_0(21 downto 14); seu_count_en_o <= xf_rx_data_en_0 when dim_addr = "0000000" else '0'; ow_scan_busy_o <= ow_scan_busy; dim_o <= xf_rx_data_0(41 downto 22); dim_en_o <= xf_rx_data_en_0 and xf_rx_data_0(36); -- only save analogue values dim_trig_num_o <= xf_rx_data_0(41 downto 38); dim_trig_lat_o <= xf_rx_data_en_0 when (xf_rx_data_0(37) = '1' and xf_rx_data_0(36 downto 34) = "010") else '0'; dim_trig_unl_o <= xf_rx_data_en_0 when (xf_rx_data_0(37) = '1' and xf_rx_data_0(36) = '1') else '0'; --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- dim_addr <= xf_rx_data_0(41 downto 38) & xf_rx_data_0(36 downto 34); ow_addr <= "00" & xf_rx_data_1(83 downto 80); --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! 1st 3-wire serial receiver from XF xf_rx_inst_0 : entity work.serial_3wire_rx generic map ( data_width_g => 42) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, rx_frame_i => xf_i.rx_frame(0), rx_bit_en_i => xf_i.rx_bit_en(0), rx_i => xf_i.rx(0), data_o => xf_rx_data_0, data_en_o => xf_rx_data_en_0, error_o => xf_rx_error_0); --! 2nd 3-wire serial receiver from XF xf_rx_inst_1 : entity work.serial_3wire_rx generic map ( data_width_g => 84) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, rx_frame_i => xf_i.rx_frame(1), rx_bit_en_i => xf_i.rx_bit_en(1), rx_i => xf_i.rx(1), data_o => xf_rx_data_1, data_en_o => xf_rx_data_en_1, error_o => xf_rx_error_1); --! DIM pages dim_page_inst : entity work.two_port_ram_tmr generic map ( depth_g => 128, width_g => 16) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_addr_i => dim_addr, wr_en_i => xf_rx_data_en_0, wr_data_i => xf_rx_data_0(37 downto 22), wr_done_o => open, wr_busy_o => open, rd_addr_i => dim_addr_i, rd_en_i => dim_rd_en_i, rd_data_o => dim_data_o, rd_data_en_o => dim_data_en_o, rd_busy_o => open); --! One-wire pages ow_page_inst : entity work.two_port_ram_tmr generic map ( depth_g => 64, width_g => 80) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_addr_i => ow_addr, wr_en_i => xf_rx_data_en_1, wr_data_i => xf_rx_data_1(79 downto 0), wr_done_o => open, wr_busy_o => open, rd_addr_i => ow_addr_i, rd_en_i => ow_rd_en_i, rd_data_o => ow_data_o, rd_data_en_o => ow_data_en_o, rd_busy_o => open); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin dim_trigger <= '0'; ow_scan_busy <= '0'; dim_reset <= '0'; ow_scan <= '0'; ow_bus_select <= (others => '0'); end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else if ms_0_strobe_i = '1' then dim_reset <= command_i.dim_reset; ow_scan <= command_i.ow_scan; ow_bus_select <= command_i.ow_bus_select; end if; if ms_0_strobe_i = '1' then dim_trigger <= '1'; elsif ms_1_strobe_i = '1' then dim_trigger <= '0'; end if; if command_i.ow_scan = '1' then ow_scan_busy <= '1'; elsif xf_rx_data_en_1 = '1' then ow_scan_busy <= '0'; end if; end if; end if; end process regs; end architecture rtl;

mit

ed4dac5ab55122f4d30ba064ffdb0c9b

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_regs_fwd.vhd

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mit

5628c9748a9da4787e3742e4396f7da9

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_SubInteger_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ed8c1617dc984620f833ba689baadd3b

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2_CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ab8ce06cae016799d6e4c0ae204ff97f

joalcava/sparcv8-monocicle

Test_PC.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Test_PC IS END Test_PC; ARCHITECTURE behavior OF Test_PC IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT pc PORT( clk : IN std_logic; rst : IN std_logic; address : IN std_logic_vector(31 downto 0); sig : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal address : std_logic_vector(31 downto 0) := (others => '0'); --Outputs signal sig : std_logic_vector(31 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: pc PORT MAP ( clk => clk, rst => rst, address => address, sig => sig ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. address <= x"FFFFFFFF"; wait for 200 ns; rst <= '1'; wait for 100 ns; rst <= '0'; wait for 50 ns; address <= x"11111111"; -- insert stimulus here wait; end process; END;

gpl-3.0

b5db93745d1cf7d9eef425a3489fd2b2

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_Atomic.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant ATOMIC_IMPLEMENT : natural := 1; constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

f34c83881c698be50b33d8048d3d1d53

malkadi/FGPU

RTL/FGPU_definitions.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is -- Begin of Configurable FGPU Parameters ----------------------------------------------------------------{{{ constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; -- Bitwidth of # of words the global read bus cache -> CUs constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; -- Bitwidth of the fifo buffer for the data read out of the cache. A fifo is implemented in each CU. constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst (only 5 is tested intensively, 4 & 6 should work but needs testing) constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; -- Implements a priority pipeline for the stations of the global memory controller which prioritizes waiting stations when more time is elapsed constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV (only 3 was tested, i.e. 8 PEs/CU) -- Floating-point hardware support: constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; -- End of Configurable FGPU Parameters ------------------------------------------------------------------}}} constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; -- one fifo to store data read out of global memory for each tag manager (now, only 0 makes sense) constant GMEM_N_BANK_W : natural := 1; -- Bitwidth of the number of words of a single AXI data interface, i.e. the global memory bus constant ID_WIDTH : natural := 6; -- Bitwidth of the read & write id channels of AXI4 constant PHASE_W : natural := 3; -- # of clock cycles when executing the same instruction on the a CV (only 3 is tested) constant CV_SIZE : natural := 2**CV_W; -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

7bf93125aeb39845261492008274a30d