foilfoilfoil/FireCheese · Datasets at Hugging Face

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Victor Aranda#0096:next time for sure
♡ FuzzPawsOokami! ♡#6719:heck yeah
Gifted Gummy Bee::kek:
Gifted Gummy Bee:https://twitter.com/LGAchippy/status/1569313159353335809?s=20&t=jIJNt3r-g59z2Ln4xIeAfA
Happsquid#7838:Certified leek^tm intel ded
Gifted Gummy Bee:alright
Nexus#8203:That's 96MB of L3 stacked on each die
Nexus#8203:50% increase over last gen
Gifted Gummy Bee:We need something to get AMD fans hard
Gifted Gummy Bee::kek:
AC_666__#4965:It's called fake
Gifted Gummy Bee:"Remember, its a thick ass IHS"
Gifted Gummy Bee::kek:
Gifted Gummy Bee:Huh
AC_666__#4965:"that has to be fake, no?"
Nexus#8203:It's possible
uzzi38#2586:Yeah
uzzi38#2586:It's fake
Nexus#8203:But it's not just a plain screenshot at least this time
TitanicFreak#4722:tbh even a video of cpu-z wouldn't do it justice.
uzzi38#2586:V-Cache dies are still 64MB for Zen 4
AC_666__#4965:"ugh yeah,, but N5 SRAM would be $++, so don't see why that'd be sensible"
uzzi38#2586:They're not N5
Nexus#8203:V-Cache is N6 IIRC for Zen 4
TitanicFreak#4722:makes sense to stack higher than it does to make those cache dies bigger imo
AC_666__#4965:Yeah. 64MB N7 dies make way more sense
TitanicFreak#4722:uh is zen4's l3 the same size still?
Slafs#1234:5.8GHz at 1.3xV tho :booba:
AC_666__#4965:can't bc 🔥 🥵
Slafs#1234:Ye
Nexus#8203:Yes
Nexus#8203:32MB
TitanicFreak#4722:I should of said physically the same size
TitanicFreak#4722:my phrasing do be bad right now
AC_666__#4965:prob not
Nexus#8203:"No, it's smaller I think"
Nexus#8203:So they might have to shrink the V-Cache dies
Nexus#8203:So in theory it could be 2hi 48MB if it is real? But I doubt that
Gifted Gummy Bee:I mean technically speaking AMD could just make the IHS thinner
AC_666__#4965:N6 doesn't provide a shrink for your SRAM
Gifted Gummy Bee::kek:
TitanicFreak#4722:this is not the most scientific measurement given the very shitty image amd provided. https://www.titanicfreak.com/imgs/c548219f4bc01d99b12516a50f380c83.png
TitanicFreak#4722:but yeah probably not gonna reuse the same die.
Gifted Gummy Bee:Z4 IHS is really thick
AC_666__#4965:"Remember, Genoa-X is >1GB of V-cache.
So whatever they do, they'll at least have that"
Nexus#8203:IHS thickness is irrelevant right now
Nexus#8203:It's also 12 CCDs though
VallahExperteלונה#7557:Homemade memes 😎
Gifted Gummy Bee:Anyways
Nexus#8203:96 x 12 = 1152MB
AC_666__#4965:"well, yes"
AC_666__#4965:1.125GB
Nexus#8203:1.125GiB
AC_666__#4965:ugh. Same thing 🤣
Nexus#8203:Don't say that to a storage engineer
TitanicFreak#4722:I won't spend an entire afternoon trying to figure this out.
Stranger#6171:so amd confirmed it now huh?
AC_666__#4965:I'll say it to the windows team :Trollface:
Nexus#8203:It would make sense to migrate from N7 to N6 given it has slightly better density and better yields
Nexus#8203:But no official confirmation
Nexus#8203:We just know that we're getting V-Cache of some variety with Zen 4 parts
Stranger#6171:yeah
TitanicFreak#4722:yeah definitely a different cache die for sure
AC_666__#4965:TSMC have said there is no benefit in density for SRAM. which is what V-cache is entirely
TitanicFreak#4722:"same size most likely, but uh."
AC_666__#4965:Yeah maybe a lil Contol logic on each SRAM bank. But not a whole lot
Slafs#1234:Maybe they just made a bigger SRAM slab. There is ample space after all
TitanicFreak#4722:"what if we just overhang the die, make it a cache spoiler"
Nexus#8203:Well the other option is that they put the cache under the die
Nexus#8203:But that would need Wafer-on-Wafer bonding
Nexus#8203:From what I understand
AC_666__#4965:You can do WoW on top as well
AC_666__#4965:Keep in mind TSMC WoW only supports DTC wafers rn
Nexus#8203:Right now they're using CoW though
Nexus#8203:For V-Cache
Nexus#8203:I believe
AC_666__#4965:yup.
Nexus#8203:WoW on top sounds like a thermal nightmare
TitanicFreak#4722:5.7+ghz? sounds fine to me!
TitanicFreak#4722:only a couple of weeks to thermal cycle ourselves to death
TitanicFreak#4722:"I should go to bed, been up all night playing cod zombies like an idiot"
Agni#6311:What about saucy tomatos
AC_666__#4965:deeeeeeep fried tomatoes
Cheesecake16#5950:This is now the Trashcan channel...... it's for...... well....... y'all know
Stranger#6171:@TechnicallyLogic :Smirking:
TechnicallyLogic#2455:A place to put all my NSFW C&C material?
Cheesecake16#5950:NO
Cheesecake16#5950:NO
Cheesecake16#5950:NO
Cheesecake16#5950:NO
Cheesecake16#5950:NO
Cheesecake16#5950:NO
Cheesecake16#5950:NO
Cheesecake16#5950:NO
Stranger#6171::kek:
Cheesecake16#5950:NO
Cheesecake16#5950:NO
Cheesecake16#5950:NO
Cheesecake16#5950:NO

Victor Aranda#0096:next time for sure

♡ FuzzPawsOokami! ♡#6719:heck yeah

Gifted Gummy Bee::kek:

Gifted Gummy Bee:https://twitter.com/LGAchippy/status/1569313159353335809?s=20&t=jIJNt3r-g59z2Ln4xIeAfA

Happsquid#7838:Certified leek^tm intel ded

Gifted Gummy Bee:alright

Nexus#8203:That's 96MB of L3 stacked on each die

Nexus#8203:50% increase over last gen

Gifted Gummy Bee:We need *something* to get AMD fans hard

Gifted Gummy Bee::kek:

AC_666__#4965:It's called fake

Gifted Gummy Bee:"Remember, its a thick ass IHS"

Gifted Gummy Bee::kek:

Gifted Gummy Bee:Huh

AC_666__#4965:"that has to be fake, no?"

Nexus#8203:It's possible

uzzi38#2586:Yeah

uzzi38#2586:It's fake

Nexus#8203:But it's not just a plain screenshot at least this time

TitanicFreak#4722:tbh even a video of cpu-z wouldn't do it justice.

uzzi38#2586:V-Cache dies are still 64MB for Zen 4

AC_666__#4965:"ugh yeah,, but N5 SRAM would be $++, so don't see why that'd be sensible"

uzzi38#2586:They're not N5

Nexus#8203:V-Cache is N6 IIRC for Zen 4

TitanicFreak#4722:makes sense to stack higher than it does to make those cache dies bigger imo

AC_666__#4965:Yeah. 64MB N7 dies make way more sense

TitanicFreak#4722:uh is zen4's l3 the same size still?

Slafs#1234:5.8GHz at 1.3xV tho :booba:

AC_666__#4965:can't bc 🔥 🥵

Slafs#1234:Ye

Nexus#8203:Yes

Nexus#8203:32MB

TitanicFreak#4722:I should of said physically the same size

TitanicFreak#4722:my phrasing do be bad right now

AC_666__#4965:prob not

Nexus#8203:"No, it's smaller I think"

Nexus#8203:So they might have to shrink the V-Cache dies

Nexus#8203:So in theory it could be 2hi 48MB if it *is* real? But I doubt that

Gifted Gummy Bee:I mean technically speaking AMD could just make the IHS thinner

AC_666__#4965:N6 doesn't provide a shrink for your SRAM

Gifted Gummy Bee::kek:

TitanicFreak#4722:this is not the most scientific measurement given the very shitty image amd provided. https://www.titanicfreak.com/imgs/c548219f4bc01d99b12516a50f380c83.png

TitanicFreak#4722:but yeah probably not gonna reuse the same die.

Gifted Gummy Bee:Z4 IHS is really thick

AC_666__#4965:"Remember, Genoa-X is >1GB of V-cache.

So whatever they do, they'll at least have that"

Nexus#8203:IHS thickness is irrelevant right now

Nexus#8203:It's also 12 CCDs though

VallahExperteלונה#7557:Homemade memes 😎

Gifted Gummy Bee:Anyways

Nexus#8203:96 x 12 = 1152MB

AC_666__#4965:"well, yes"

AC_666__#4965:1.125GB

Nexus#8203:1.125GiB

AC_666__#4965:ugh. Same thing 🤣

Nexus#8203:Don't say that to a storage engineer

TitanicFreak#4722:I won't spend an entire afternoon trying to figure this out.

Stranger#6171:so amd confirmed it now huh?

AC_666__#4965:I'll say it to the windows team :Trollface:

Nexus#8203:It would make sense to migrate from N7 to N6 given it has slightly better density and better yields

Nexus#8203:But no official confirmation

Nexus#8203:We just know that we're getting V-Cache of some variety with Zen 4 parts

Stranger#6171:yeah

TitanicFreak#4722:yeah definitely a different cache die for sure

AC_666__#4965:TSMC have said there is no benefit in density for SRAM. which is what V-cache is entirely

TitanicFreak#4722:"same size most likely, but uh."

AC_666__#4965:Yeah maybe a lil Contol logic on each SRAM bank. But not a whole lot

Slafs#1234:Maybe they just made a bigger SRAM slab. There is ample space after all

TitanicFreak#4722:"what if we just overhang the die, make it a cache spoiler"

Nexus#8203:Well the other option is that they put the cache under the die

Nexus#8203:But that would need Wafer-on-Wafer bonding

Nexus#8203:From what I understand

AC_666__#4965:You can do WoW on top as well

AC_666__#4965:Keep in mind TSMC WoW only supports DTC wafers rn

Nexus#8203:Right now they're using CoW though

Nexus#8203:For V-Cache

Nexus#8203:I believe

AC_666__#4965:yup.

Nexus#8203:WoW on top sounds like a thermal nightmare

TitanicFreak#4722:5.7+ghz? sounds fine to me!

TitanicFreak#4722:only a couple of weeks to thermal cycle ourselves to death

TitanicFreak#4722:"I should go to bed, been up all night playing cod zombies like an idiot"

Agni#6311:What about saucy tomatos

AC_666__#4965:deeeeeeep fried tomatoes

Cheesecake16#5950:This is now the Trashcan channel...... it's for...... well....... y'all know

Stranger#6171:@TechnicallyLogic :Smirking:

TechnicallyLogic#2455:A place to put all my NSFW C&C material?

Cheesecake16#5950:NO

Stranger#6171::kek:

Cheesecake16#5950:NO