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Victor Aranda#0096:Close TDP prolly too |
Olrak#9007:I’m seeing a 128 EU MTL-P iGPU on sisoft |
🌺 ¿butterflies? 🌸#4118:https://images.anandtech.com/doci/18844/AMD%20Ryzen%207040U%20Slide%20Deck%205.PNG |
Olrak#9007:With various scores with different PLs |
JamesCJ#2023:Probably the Core Ultra 5 1003H’s |
Olrak#9007:28W and 45W |
🌺 ¿butterflies? 🌸#4118:8.6TFlops is **FP16** |
🌺 ¿butterflies? 🌸#4118:1.8TFlops higher YoY |
JamesCJ#2023:And FP32 via dual issue :kek: |
Jiray#3048:This thing can also reach up to 8.6 TFLOPs with FP32 |
🌺 ¿butterflies? 🌸#4118:we'll see |
🌺 ¿butterflies? 🌸#4118:probably not 😛 |
🌺 ¿butterflies? 🌸#4118:FP16 is also doubled |
Jiray#3048:"No, it is not." |
🌺 ¿butterflies? 🌸#4118:hm? |
Jiray#3048:Unless you use the WMMA instructions |
JamesCJ#2023:U have 12CUs running at 2.7GHz with dual issue :kek: |
🌺 ¿butterflies? 🌸#4118:it's not NVIDIA with a 1:1 FP16:FP32 ratio |
🌺 ¿butterflies? 🌸#4118:AMD will have picked the numbers most favorable to them |
🌺 ¿butterflies? 🌸#4118:so this is 8.6Tflops FP16 |
🌺 ¿butterflies? 🌸#4118:and so 4.3Tflops FP32 tops |
JamesCJ#2023:Nope :kek: |
Jiray#3048:That would be a significantly smaller GPU |
🌺 ¿butterflies? 🌸#4118:the other option is their marketing dept being utterly inconsistent |
Victor Aranda#0096:FP16 not doubled then on PHX RDNA3? |
TitanicFreak#4722:I put money on marketing being idiots as usual. |
🌺 ¿butterflies? 🌸#4118:and sharing numbers that do not belong together at all |
JamesCJ#2023:12CUs with dual issue running at 2.7GHz is over 8TFlops in FP32 |
Mohamexiety#7230:note that the marketed FP16 number for N31 _was_ doubled (i.e. assuming WMMA instructions) |
Jiray#3048:"Yes, regular packed FP16 is 1:1 with dual-issued FP32." |
🌺 ¿butterflies? 🌸#4118:reminder that compute shaders in Vk are wave64 |
🌺 ¿butterflies? 🌸#4118:AMD will always pick the highest numbers they can except if their marketing dept went nuts |
🌺 ¿butterflies? 🌸#4118:but available for benchmarking soon |
Mohamexiety#7230:"I wonder if it uses packed FP16 now actually. when N31 launched, nemes and I did some poking around and we found that it doesn't use packed FP16 lol" |
🌺 ¿butterflies? 🌸#4118:so you'll see |
bnieuwenhuizen#2820:so the weird thing with AMD is that FP16 isn't dual issue (except for some dot2) |
Mohamexiety#7230:yep |
bnieuwenhuizen#2820:so you have fp16 vec2 (which you had on rdna2 already) or dual issue on fp32 |
bnieuwenhuizen#2820:so ironically in practice getting good speeds is easier with fp32 than fp16 on RDNA3 (at least with wave64) |
Mohamexiety#7230:(^ dual issue on FP32 was what we saw from RGA at launch) |
🌺 ¿butterflies? 🌸#4118:why do they advertise a 2:1 FP16 ratio |
🌺 ¿butterflies? 🌸#4118:then |
Mohamexiety#7230:because teeechnically if you use dot2 you can reach that ratio |
🌺 ¿butterflies? 🌸#4118:"and if FP16 and FP32 are the same, why say FP16?" |
bnieuwenhuizen#2820:but 8.7 is the fp32 value |
🌺 ¿butterflies? 🌸#4118:something doesn't compute |
🌺 ¿butterflies? 🌸#4118:their slides explicitly say 8.7 _FP16_ |
bnieuwenhuizen#2820:12 CU * 64 lanes * 2 (dual issue) * 2 (FMA) * 2.7 GHZ = 8.3 TFlops of fp32 |
Mohamexiety#7230:"no, in the compiler disassembly. |
throughput between FP32 dual issue and packed FP16 should be the same" |
🌺 ¿butterflies? 🌸#4118:and _1.8 TFLOPS_ higher YoY |
🌺 ¿butterflies? 🌸#4118:something doesn't make sense |
BigChungus#1843:The replies to this tweet is fucking funny |
🌺 ¿butterflies? 🌸#4118:this marketing copy makes no sense |
Mohamexiety#7230:I wanted to verify this with the newer RGA but it doesn't want to run on my end 😐 |
Jiray#3048:"Yes, which is what we see here" |
bnieuwenhuizen#2820:"so either they use 1:1 for ""normal fp16"", or 2:1 for AI fp16" |
nepnep#8359:https://tenor.com/view/metal-gear-rising-metal-gear-rising-revengeance-senator-armstrong-revengeance-i-made-it-the-fuck-up-gif-25029602 |
bnieuwenhuizen#2820:also kind weird the 8.7 vs. 8.3 |
Mohamexiety#7230:"yeah. what I was talking about is that previously, the compiler would prefer packed FP16, but on RDNA 3 what we saw was that it used FP32 with dual issue for FP16" |
Jiray#3048:Huh. |
bnieuwenhuizen#2820:"if I calculate back the clockspeed for this thing should be ~2.83 GHz, not 2.7 GHz" |
Mohamexiety#7230:I am curious if this is still how it works but I can't get the newer RGA to compile any kernel offline |
TitanicFreak#4722:glad to know aida64 still is broken https://twitter.com/TechEpiphany/status/1651602877335445507 |
TitanicFreak#4722:had to unbury that |
TitanicFreak#4722:eugh |
bnieuwenhuizen#2820:I mean kinda broken but also very realistic wrt real uplift :kek: |
TitanicFreak#4722:realistically I think someone in their marketing wanted to make the teraflop increase more.... honest with what it actually was going to be. |
TitanicFreak#4722:but instead is causing confusion |
TitanicFreak#4722:because if you compare FP16 to FP16 across those two gens. you get a more reasonable number. going off of FP32 leads to console wars. |
TitanicFreak#4722:idk just a theory. |
bnieuwenhuizen#2820:you already see people comparing the thing to ps5 based on tflops :kek: |
🌺 ¿butterflies? 🌸#4118:AMD themselves said that the increase in wave32 was surprisingly small |
🌺 ¿butterflies? 🌸#4118:for RTRT |
🌺 ¿butterflies? 🌸#4118:"well, meant the increase from dual-issue" |
bnieuwenhuizen#2820:that is just poor utilization because most stuff in the RT loop is int |
cha0s#0085:What’s broken about that? |
TitanicFreak#4722:opencl dual issue is hard |
bnieuwenhuizen#2820:+ VOPD restrictions in wave32 are pretty terrible |
cha0s#0085:Oh well |
TitanicFreak#4722:wave64 it and it'll magically do better. |
cha0s#0085:If you just go by shaders |
cha0s#0085:It’s 4.15TFlops |
Mohamexiety#7230:"also iirc you can't actually dual issue int, right? you can only do int + fp" |
TitanicFreak#4722:makes no sense for amd to remove fp32 dual issue on phoenix. literally a core part of rdna3 lol. |
bnieuwenhuizen#2820:you can do fp+fp too |
Mohamexiety#7230:yeah I meant specifically for integer stuff |
bnieuwenhuizen#2820:there are some int options for int+fp |
bnieuwenhuizen#2820:in wave32 (not wave64) |
cha0s#0085:Since dual issue can only be used in specific scenarios |
bnieuwenhuizen#2820:"but a lot of the core RT loop ends up just being a lot of masking and shifts and indexing, which are decidedly not float" |
cha0s#0085:Why are we talking about it again? |
bnieuwenhuizen#2820:confusion about tflops of Phoenix |
Jiray#3048:LH thinks that Penix might not have dual-issue |
cha0s#0085:8.3 FP16 sounds right on the money for me |
cha0s#0085:Just like N31 is around 30Tflops |
bnieuwenhuizen#2820:the confusion is about also having 8.3 fp32 |