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618 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
); |
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
619 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
X,
A
);
output X;
input A;
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__lpflow_clkbufkapwr_2 (
X,
A
); |
output X;
input A;
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A)
);
endmodule | 0 |
620 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
); |
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
621 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
X,
A
);
output X;
input A;
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__lpflow_clkbufkapwr_4 (
X,
A
); |
output X;
input A;
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A)
);
endmodule | 0 |
622 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nand2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
623 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__nand2_4 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | 0 |
624 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nand2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
625 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__nand2_8 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | 0 |
626 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nand2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
627 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__nand2_1 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | 0 |
628 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
630 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
wire nand0_out_Y;
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule | module sky130_fd_sc_hd__nand2 (
Y,
A,
B
); |
output Y;
input A;
input B;
wire nand0_out_Y;
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule | 0 |
631 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nand0_out_Y;
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule | module sky130_fd_sc_hd__nand2 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nand0_out_Y;
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule | 0 |
632 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
633 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__nand2_2 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | 0 |
634 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
636 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
wire mux_4to20_out_X;
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule | module sky130_fd_sc_hd__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
); |
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
wire mux_4to20_out_X;
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule | 0 |
637 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire mux_4to20_out_X;
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule | module sky130_fd_sc_hd__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
); |
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire mux_4to20_out_X;
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule | 0 |
638 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux4_1 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__mux4_1 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
639 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux4_1 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule | module sky130_fd_sc_hd__mux4_1 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
); |
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule | 0 |
640 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux4_4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__mux4_4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
641 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux4_4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule | module sky130_fd_sc_hd__mux4_4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
); |
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule | 0 |
642 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux4_2 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__mux4_2 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
643 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux4_2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule | module sky130_fd_sc_hd__mux4_2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
); |
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule | 0 |
644 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | 0 |
646 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlymetal6s4s (
X,
A
);
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__dlymetal6s4s (
X,
A
); |
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
647 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlymetal6s4s (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__dlymetal6s4s (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
648 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlymetal6s4s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlymetal6s4s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlymetal6s4s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlymetal6s4s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
649 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlymetal6s4s_1 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlymetal6s4s base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__dlymetal6s4s_1 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlymetal6s4s base (
.X(X),
.A(A)
);
endmodule | 0 |
650 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
651 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | module sky130_fd_sc_hd__and3_4 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | 0 |
652 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
653 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | module sky130_fd_sc_hd__and3_1 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | 0 |
654 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
655 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | module sky130_fd_sc_hd__and3_2 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | 0 |
656 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
658 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
wire and0_out_X;
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and3 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
wire and0_out_X;
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule | 0 |
659 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out_X;
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and3 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out_X;
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule | 0 |
660 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__ha_1 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__ha_1 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
661 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__ha_1 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__ha_1 (
COUT,
SUM ,
A ,
B
); |
output COUT;
output SUM ;
input A ;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule | 0 |
662 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__ha_4 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__ha_4 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
663 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__ha_4 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__ha_4 (
COUT,
SUM ,
A ,
B
); |
output COUT;
output SUM ;
input A ;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule | 0 |
664 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule | module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule | 0 |
666 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
wire and0_out_COUT;
wire xor0_out_SUM ;
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule | module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B
); |
output COUT;
output SUM ;
input A ;
input B ;
wire and0_out_COUT;
wire xor0_out_SUM ;
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule | 0 |
667 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out_COUT;
wire xor0_out_SUM ;
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule | module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B
); |
output COUT;
output SUM ;
input A ;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out_COUT;
wire xor0_out_SUM ;
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule | 0 |
668 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__ha_2 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__ha_2 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
669 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__ha_2 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__ha_2 (
COUT,
SUM ,
A ,
B
); |
output COUT;
output SUM ;
input A ;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule | 0 |
670 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule | module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule | 0 |
672 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule | module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
); |
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule | 0 |
673 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule | module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
); |
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule | 0 |
674 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
675 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule | module sky130_fd_sc_hd__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI
); |
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule | 0 |
676 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
677 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
678 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
679 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
680 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
682 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
wire b ;
wire and0_out ;
wire nor0_out_Y;
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
wire b ;
wire and0_out ;
wire nor0_out_Y;
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
683 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire b ;
wire and0_out ;
wire nor0_out_Y;
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire b ;
wire and0_out ;
wire nor0_out_Y;
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
684 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
685 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
686 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
687 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__a21boi_1 (
Y ,
A1 ,
A2 ,
B1_N
); |
output Y ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
688 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
689 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule | module sky130_fd_sc_hd__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule | 0 |
690 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET ;
wire intgate;
wire buf_Q ;
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET ;
wire intgate;
wire buf_Q ;
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | 0 |
691 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | 0 |
692 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
wire RESET ;
wire intgate;
wire buf_Q ;
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
wire RESET ;
wire intgate;
wire buf_Q ;
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
endmodule | 0 |
693 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | 0 |
694 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
695 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule | module sky130_fd_sc_hd__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule | 0 |
696 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
697 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule | module sky130_fd_sc_hd__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N
); |
output Q ;
input RESET_B;
input D ;
input GATE_N ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule | 0 |
698 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a211oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a211oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
699 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a211oi_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__a211oi_4 (
Y ,
A1,
A2,
B1,
C1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
700 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a211oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a211oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
701 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a211oi_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__a211oi_1 (
Y ,
A1,
A2,
B1,
C1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
702 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
703 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
704 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
706 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a211oi (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__a211oi (
Y ,
A1,
A2,
B1,
C1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
707 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a211oi (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__a211oi (
Y ,
A1,
A2,
B1,
C1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
708 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fah_1 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__fah_1 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
709 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fah_1 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule | module sky130_fd_sc_hd__fah_1 (
COUT,
SUM ,
A ,
B ,
CI
); |
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule | 0 |
710 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule | module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule | 0 |
712 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule | module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI
); |
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule | 0 |
713 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule | module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI
); |
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule | 0 |
714 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
715 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule | module sky130_fd_sc_hd__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule | 0 |
716 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
717 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule | module sky130_fd_sc_hd__sdlclkp_4 (
GCLK,
SCE ,
GATE,
CLK
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule | 0 |
718 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
and and0 (GCLK , m0n, CLK );
endmodule | module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
and and0 (GCLK , m0n, CLK );
endmodule | 0 |
719 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule | module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule | 0 |
720 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule | module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule | 0 |
721 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule | module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule | 0 |
722 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp_2 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__sdlclkp_2 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
723 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdlclkp_2 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule | module sky130_fd_sc_hd__sdlclkp_2 (
GCLK,
SCE ,
GATE,
CLK
); |
output GCLK;
input SCE ;
input GATE;
input CLK ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule | 0 |
724 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q;
wire RESET;
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q;
wire RESET;
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule | 0 |
725 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule | 0 |
726 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
wire buf_Q;
wire RESET;
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
); |
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
wire buf_Q;
wire RESET;
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule | 0 |
Subsets and Splits