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// $Id: c_fifo_ctrl.v 1922 2010-04-15 03:47:49Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// simple FIFO controller
module c_fifo_ctrl
(clk, reset, push, pop, write_addr, read_addr, almost_empty, empty,
almost_full, full, errors);
`include "c_constants.v"
// address width
parameter addr_width = 3;
// starting address (i.e., address of leftmost entry)
parameter offset = 0;
// number of entries in FIFO
parameter depth = 8;
// minimum (leftmost) address
localparam [0:addr_width-1] min_value = offset;
// maximum (rightmost) address
localparam [0:addr_width-1] max_value = offset + depth - 1;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// write (add) an element
input push;
// read (remove) an element
input pop;
// address to write current input element to
output [0:addr_width-1] write_addr;
wire [0:addr_width-1] write_addr;
// address to read next output element from
output [0:addr_width-1] read_addr;
wire [0:addr_width-1] read_addr;
// buffer nearly empty (1 used slot remaining) indication
output almost_empty;
wire almost_empty;
// buffer empty indication
output empty;
wire empty;
// buffer almost full (1 unused slot remaining) indication
output almost_full;
wire almost_full;
// buffer full indication
output full;
wire full;
// internal error condition detected
output [0:1] errors;
wire [0:1] errors;
wire [0:addr_width-1] read_ptr_next, read_ptr_q;
c_incr
#(.width(addr_width),
.min_value(min_value),
.max_value(max_value))
read_ptr_incr
(.data_in(read_ptr_q),
.data_out(read_ptr_next));
wire [0:addr_width-1] read_ptr_s;
assign read_ptr_s = pop ? read_ptr_next : read_ptr_q;
c_dff
#(.width(addr_width),
.reset_value(min_value),
.reset_type(reset_type))
read_ptrq
(.clk(clk),
.reset(reset),
.d(read_ptr_s),
.q(read_ptr_q));
assign read_addr[0:addr_width-1] = read_ptr_q;
wire [0:addr_width-1] write_ptr_next, write_ptr_q;
c_incr
#(.width(addr_width),
.min_value(min_value),
.max_value(max_value))
write_ptr_incr
(.data_in(write_ptr_q),
.data_out(write_ptr_next));
wire [0:addr_width-1] write_ptr_s;
assign write_ptr_s = push ? write_ptr_next : write_ptr_q;
c_dff
#(.width(addr_width),
.reset_value(min_value),
.reset_type(reset_type))
write_ptrq
(.clk(clk),
.reset(reset),
.d(write_ptr_s),
.q(write_ptr_q));
assign write_addr[0:addr_width-1] = write_ptr_q;
assign almost_empty = (read_ptr_next == write_ptr_q);
wire empty_s, empty_q;
assign empty_s = (empty_q | (almost_empty & pop & ~push)) & ~(push & ~pop);
c_dff
#(.width(1),
.reset_type(reset_type),
.reset_value(1'b1))
emptyq
(.clk(clk),
.reset(reset),
.d(empty_s),
.q(empty_q));
assign empty = empty_q;
assign almost_full = (write_ptr_next == read_ptr_q);
wire full_s, full_q;
assign full_s = (full_q | (almost_full & push & ~pop)) & ~(pop & ~push);
c_dff
#(.width(1),
.reset_type(reset_type))
fullq
(.clk(clk),
.reset(reset),
.d(full_s),
.q(full_q));
assign full = full_q;
wire error_underflow;
assign error_underflow = empty & pop & ~push;
wire error_overflow;
assign error_overflow = full & push & ~pop;
assign errors = {error_underflow, error_overflow};
// synopsys translate_off
generate
if(depth > (1 << addr_width))
begin
initial
begin
$display({"ERROR: FIFO controller %m requires that addr_width ",
"be at least wide enough to cover the entire depth."});
$stop;
end
end
endgenerate
// synopsys translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DIODE_PP_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DIODE_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_SYMBOL_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_SYMBOL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd1 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_SYMBOL_V
|
module data_path_testbench;
reg[1:0] input_register_selector_1;
reg[1:0] input_register_selector_2;
reg[1:0] output_register_selector;
reg[1:0] output_source_selector;
reg output_enable;
reg[1:0] alu_opcode;
reg[31:0] immediate_1;
reg[31:0] immediate_2;
data_path data_path_0(input_register_selector_1, input_register_selector_2,
output_register_selector, output_source_selector,
output_enable, alu_opcode, immediate_1, immediate_2);
initial
begin
$display("a\tb\tout\tout enabled\talu_opcode\tout data 1\tout data 2");
$monitor("%d,\t%d,\t%d,\t%b,\t\t%b\t%d\t%d",
input_register_selector_1, input_register_selector_2,
output_register_selector, output_enable, alu_opcode,
data_path_0.input_data_1, data_path_0.input_data_2);
#0 assign output_enable = 1;
#0 assign output_source_selector = 1;
#0 assign immediate_1 = 0;
#0 assign output_register_selector = 0;
#0 assign immediate_1 = 21;
#1 assign output_register_selector = 1;
#1 assign immediate_1 = 42;
#2 assign output_register_selector = 2;
#2 assign immediate_1 = 84;
#3 assign output_register_selector = 3;
#3 assign immediate_1 = 168;
#4 assign output_enable = 0;
#4 assign input_register_selector_1 = 0;
#4 assign input_register_selector_2 = 1;
#5 assign input_register_selector_1 = 2;
#5 assign input_register_selector_2 = 3;
#6 assign input_register_selector_1 = 2;
#6 assign input_register_selector_2 = 3;
#6 assign output_register_selector = 0;
#6 assign output_source_selector = 0;
#6 assign output_enable = 1;
#6 assign alu_opcode = 'b10;
#7 assign output_enable = 0;
#7 assign input_register_selector_1 = 0;
#7 assign input_register_selector_2 = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR2B_PP_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2B_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [32:0] in = crc[32:0];
logic bank_rd_vec_m3;
always_ff @(posedge clk) bank_rd_vec_m3 <= crc[33];
logic [3:0][31:0] data_i;
wire [3:0] out;
for (genvar i = 0; i < 4; ++i) begin
always_ff @(posedge clk) data_i[i] <= crc[63:32];
ecc_check_pipe u_bank_data_ecc_check(
.clk (clk),
.bank_rd_m3 (bank_rd_vec_m3),
.data_i ({1'b0, data_i[i]}),
.ecc_err_o (out[i])
);
end
// Aggregate outputs into a single result vector
wire [63:0] result = {60'b0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha2601675a6ae4972
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module ecc_check_pipe (
input logic clk,
input logic bank_rd_m3,
input logic [32:0] data_i,
output logic ecc_err_o
);
logic [3:0] check_group_6_0;
logic check_group_6_0_q;
always_comb check_group_6_0 = {data_i[0], data_i[2], data_i[4], data_i[7] };
always_ff @(posedge clk) if (bank_rd_m3) check_group_6_0_q <=^check_group_6_0;
assign ecc_err_o = check_group_6_0_q;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module mig_7series_v2_3_round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import ZAxioms ZMulOrder ZSgnAbs NZDiv.
(** * Euclidean Division for integers (Floor convention)
We use here the convention known as Floor, or Round-Toward-Bottom,
where [a/b] is the closest integer below the exact fraction.
It can be summarized by:
[a = bq+r /\ 0 <= |r| < |b| /\ Sign(r) = Sign(b)]
This is the convention followed historically by [Z.div] in Coq, and
corresponds to convention "F" in the following paper:
R. Boute, "The Euclidean definition of the functions div and mod",
ACM Transactions on Programming Languages and Systems,
Vol. 14, No.2, pp. 127-144, April 1992.
See files [ZDivTrunc] and [ZDivEucl] for others conventions.
*)
Module Type ZDivProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZSgnAbsProp A B).
(** We benefit from what already exists for NZ *)
Module Import Private_NZDiv := Nop <+ NZDivProp A A B.
(** Another formulation of the main equation *)
Lemma mod_eq :
forall a b, b~=0 -> a mod b == a - b*(a/b).
Proof.
intros.
rewrite <- add_move_l.
symmetry. now apply div_mod.
Qed.
(** We have a general bound for absolute values *)
Lemma mod_bound_abs :
forall a b, b~=0 -> abs (a mod b) < abs b.
Proof.
intros.
destruct (abs_spec b) as [(LE,EQ)|(LE,EQ)]; rewrite EQ.
destruct (mod_pos_bound a b). order. now rewrite abs_eq.
destruct (mod_neg_bound a b). order. rewrite abs_neq; trivial.
now rewrite <- opp_lt_mono.
Qed.
(** Uniqueness theorems *)
Theorem div_mod_unique : forall b q1 q2 r1 r2 : t,
(0<=r1<b \/ b<r1<=0) -> (0<=r2<b \/ b<r2<=0) ->
b*q1+r1 == b*q2+r2 -> q1 == q2 /\ r1 == r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 EQ.
destruct Hr1; destruct Hr2; try (intuition; order).
apply div_mod_unique with b; trivial.
rewrite <- (opp_inj_wd r1 r2).
apply div_mod_unique with (-b); trivial.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
now rewrite 2 mul_opp_l, <- 2 opp_add_distr, opp_inj_wd.
Qed.
Theorem div_unique:
forall a b q r, (0<=r<b \/ b<r<=0) -> a == b*q + r -> q == a/b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0) by (destruct Hr; intuition; order).
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
destruct Hr; [left; apply mod_pos_bound|right; apply mod_neg_bound];
intuition order.
now rewrite <- div_mod.
Qed.
Theorem div_unique_pos:
forall a b q r, 0<=r<b -> a == b*q + r -> q == a/b.
Proof. intros; apply div_unique with r; auto. Qed.
Theorem div_unique_neg:
forall a b q r, b<r<=0 -> a == b*q + r -> q == a/b.
Proof. intros; apply div_unique with r; auto. Qed.
Theorem mod_unique:
forall a b q r, (0<=r<b \/ b<r<=0) -> a == b*q + r -> r == a mod b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0) by (destruct Hr; intuition; order).
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
destruct Hr; [left; apply mod_pos_bound|right; apply mod_neg_bound];
intuition order.
now rewrite <- div_mod.
Qed.
Theorem mod_unique_pos:
forall a b q r, 0<=r<b -> a == b*q + r -> r == a mod b.
Proof. intros; apply mod_unique with q; auto. Qed.
Theorem mod_unique_neg:
forall a b q r, b<r<=0 -> a == b*q + r -> r == a mod b.
Proof. intros; apply mod_unique with q; auto. Qed.
(** Sign rules *)
Ltac pos_or_neg a :=
let LT := fresh "LT" in
let LE := fresh "LE" in
destruct (le_gt_cases 0 a) as [LE|LT]; [|rewrite <- opp_pos_neg in LT].
Fact mod_bound_or : forall a b, b~=0 -> 0<=a mod b<b \/ b<a mod b<=0.
Proof.
intros.
destruct (lt_ge_cases 0 b); [left|right].
apply mod_pos_bound; trivial. apply mod_neg_bound; order.
Qed.
Fact opp_mod_bound_or : forall a b, b~=0 ->
0 <= -(a mod b) < -b \/ -b < -(a mod b) <= 0.
Proof.
intros.
destruct (lt_ge_cases 0 b); [right|left].
rewrite <- opp_lt_mono, opp_nonpos_nonneg.
destruct (mod_pos_bound a b); intuition; order.
rewrite <- opp_lt_mono, opp_nonneg_nonpos.
destruct (mod_neg_bound a b); intuition; order.
Qed.
Lemma div_opp_opp : forall a b, b~=0 -> -a/-b == a/b.
Proof.
intros. symmetry. apply div_unique with (- (a mod b)).
now apply opp_mod_bound_or.
rewrite mul_opp_l, <- opp_add_distr, <- div_mod; order.
Qed.
Lemma mod_opp_opp : forall a b, b~=0 -> (-a) mod (-b) == - (a mod b).
Proof.
intros. symmetry. apply mod_unique with (a/b).
now apply opp_mod_bound_or.
rewrite mul_opp_l, <- opp_add_distr, <- div_mod; order.
Qed.
(** With the current conventions, the other sign rules are rather complex. *)
Lemma div_opp_l_z :
forall a b, b~=0 -> a mod b == 0 -> (-a)/b == -(a/b).
Proof.
intros a b Hb H. symmetry. apply div_unique with 0.
destruct (lt_ge_cases 0 b); [left|right]; intuition; order.
rewrite <- opp_0, <- H.
rewrite mul_opp_r, <- opp_add_distr, <- div_mod; order.
Qed.
Lemma div_opp_l_nz :
forall a b, b~=0 -> a mod b ~= 0 -> (-a)/b == -(a/b)-1.
Proof.
intros a b Hb H. symmetry. apply div_unique with (b - a mod b).
destruct (lt_ge_cases 0 b); [left|right].
rewrite le_0_sub. rewrite <- (sub_0_r b) at 5. rewrite <- sub_lt_mono_l.
destruct (mod_pos_bound a b); intuition; order.
rewrite le_sub_0. rewrite <- (sub_0_r b) at 1. rewrite <- sub_lt_mono_l.
destruct (mod_neg_bound a b); intuition; order.
rewrite <- (add_opp_r b), mul_sub_distr_l, mul_1_r, sub_add_simpl_r_l.
rewrite mul_opp_r, <-opp_add_distr, <-div_mod; order.
Qed.
Lemma mod_opp_l_z :
forall a b, b~=0 -> a mod b == 0 -> (-a) mod b == 0.
Proof.
intros a b Hb H. symmetry. apply mod_unique with (-(a/b)).
destruct (lt_ge_cases 0 b); [left|right]; intuition; order.
rewrite <- opp_0, <- H.
rewrite mul_opp_r, <- opp_add_distr, <- div_mod; order.
Qed.
Lemma mod_opp_l_nz :
forall a b, b~=0 -> a mod b ~= 0 -> (-a) mod b == b - a mod b.
Proof.
intros a b Hb H. symmetry. apply mod_unique with (-(a/b)-1).
destruct (lt_ge_cases 0 b); [left|right].
rewrite le_0_sub. rewrite <- (sub_0_r b) at 5. rewrite <- sub_lt_mono_l.
destruct (mod_pos_bound a b); intuition; order.
rewrite le_sub_0. rewrite <- (sub_0_r b) at 1. rewrite <- sub_lt_mono_l.
destruct (mod_neg_bound a b); intuition; order.
rewrite <- (add_opp_r b), mul_sub_distr_l, mul_1_r, sub_add_simpl_r_l.
rewrite mul_opp_r, <-opp_add_distr, <-div_mod; order.
Qed.
Lemma div_opp_r_z :
forall a b, b~=0 -> a mod b == 0 -> a/(-b) == -(a/b).
Proof.
intros. rewrite <- (opp_involutive a) at 1.
rewrite div_opp_opp; auto using div_opp_l_z.
Qed.
Lemma div_opp_r_nz :
forall a b, b~=0 -> a mod b ~= 0 -> a/(-b) == -(a/b)-1.
Proof.
intros. rewrite <- (opp_involutive a) at 1.
rewrite div_opp_opp; auto using div_opp_l_nz.
Qed.
Lemma mod_opp_r_z :
forall a b, b~=0 -> a mod b == 0 -> a mod (-b) == 0.
Proof.
intros. rewrite <- (opp_involutive a) at 1.
now rewrite mod_opp_opp, mod_opp_l_z, opp_0.
Qed.
Lemma mod_opp_r_nz :
forall a b, b~=0 -> a mod b ~= 0 -> a mod (-b) == (a mod b) - b.
Proof.
intros. rewrite <- (opp_involutive a) at 1.
rewrite mod_opp_opp, mod_opp_l_nz by trivial.
now rewrite opp_sub_distr, add_comm, add_opp_r.
Qed.
(** The sign of [a mod b] is the one of [b] (when it isn't null) *)
Lemma mod_sign_nz : forall a b, b~=0 -> a mod b ~= 0 ->
sgn (a mod b) == sgn b.
Proof.
intros a b Hb H. destruct (lt_ge_cases 0 b) as [Hb'|Hb'].
destruct (mod_pos_bound a b Hb'). rewrite 2 sgn_pos; order.
destruct (mod_neg_bound a b). order. rewrite 2 sgn_neg; order.
Qed.
Lemma mod_sign : forall a b, b~=0 -> sgn (a mod b) ~= -sgn b.
Proof.
intros a b Hb H.
destruct (eq_decidable (a mod b) 0) as [EQ|NEQ].
apply Hb, sgn_null_iff, opp_inj. now rewrite <- H, opp_0, EQ, sgn_0.
apply Hb, sgn_null_iff. apply eq_mul_0_l with 2; try order'. nzsimpl'.
apply add_move_0_l. rewrite <- H. symmetry. now apply mod_sign_nz.
Qed.
Lemma mod_sign_mul : forall a b, b~=0 -> 0 <= (a mod b) * b.
Proof.
intros. destruct (lt_ge_cases 0 b).
apply mul_nonneg_nonneg; destruct (mod_pos_bound a b); order.
apply mul_nonpos_nonpos; destruct (mod_neg_bound a b); order.
Qed.
(** A division by itself returns 1 *)
Lemma div_same : forall a, a~=0 -> a/a == 1.
Proof.
intros. pos_or_neg a. apply div_same; order.
rewrite <- div_opp_opp by trivial. now apply div_same.
Qed.
Lemma mod_same : forall a, a~=0 -> a mod a == 0.
Proof.
intros. rewrite mod_eq, div_same by trivial. nzsimpl. apply sub_diag.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem div_small: forall a b, 0<=a<b -> a/b == 0.
Proof. exact div_small. Qed.
(** Same situation, in term of modulo: *)
Theorem mod_small: forall a b, 0<=a<b -> a mod b == a.
Proof. exact mod_small. Qed.
(** * Basic values of divisions and modulo. *)
Lemma div_0_l: forall a, a~=0 -> 0/a == 0.
Proof.
intros. pos_or_neg a. apply div_0_l; order.
rewrite <- div_opp_opp, opp_0 by trivial. now apply div_0_l.
Qed.
Lemma mod_0_l: forall a, a~=0 -> 0 mod a == 0.
Proof.
intros; rewrite mod_eq, div_0_l; now nzsimpl.
Qed.
Lemma div_1_r: forall a, a/1 == a.
Proof.
intros. symmetry. apply div_unique with 0. left. split; order || apply lt_0_1.
now nzsimpl.
Qed.
Lemma mod_1_r: forall a, a mod 1 == 0.
Proof.
intros. rewrite mod_eq, div_1_r; nzsimpl; auto using sub_diag.
intro EQ; symmetry in EQ; revert EQ; apply lt_neq; apply lt_0_1.
Qed.
Lemma div_1_l: forall a, 1<a -> 1/a == 0.
Proof. exact div_1_l. Qed.
Lemma mod_1_l: forall a, 1<a -> 1 mod a == 1.
Proof. exact mod_1_l. Qed.
Lemma div_mul : forall a b, b~=0 -> (a*b)/b == a.
Proof.
intros. symmetry. apply div_unique with 0.
destruct (lt_ge_cases 0 b); [left|right]; split; order.
nzsimpl; apply mul_comm.
Qed.
Lemma mod_mul : forall a b, b~=0 -> (a*b) mod b == 0.
Proof.
intros. rewrite mod_eq, div_mul by trivial. rewrite mul_comm; apply sub_diag.
Qed.
Theorem div_unique_exact a b q: b~=0 -> a == b*q -> q == a/b.
Proof.
intros Hb H. rewrite H, mul_comm. symmetry. now apply div_mul.
Qed.
(** * Order results about mod and div *)
(** A modulo cannot grow beyond its starting point. *)
Theorem mod_le: forall a b, 0<=a -> 0<b -> a mod b <= a.
Proof. exact mod_le. Qed.
Theorem div_pos : forall a b, 0<=a -> 0<b -> 0<= a/b.
Proof. exact div_pos. Qed.
Lemma div_str_pos : forall a b, 0<b<=a -> 0 < a/b.
Proof. exact div_str_pos. Qed.
Lemma div_small_iff : forall a b, b~=0 -> (a/b==0 <-> 0<=a<b \/ b<a<=0).
Proof.
intros a b Hb.
split.
intros EQ.
rewrite (div_mod a b Hb), EQ; nzsimpl.
now apply mod_bound_or.
destruct 1. now apply div_small.
rewrite <- div_opp_opp by trivial. apply div_small; trivial.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
Qed.
Lemma mod_small_iff : forall a b, b~=0 -> (a mod b == a <-> 0<=a<b \/ b<a<=0).
Proof.
intros.
rewrite <- div_small_iff, mod_eq by trivial.
rewrite sub_move_r, <- (add_0_r a) at 1. rewrite add_cancel_l.
rewrite eq_sym_iff, eq_mul_0. tauto.
Qed.
(** As soon as the divisor is strictly greater than 1,
the division is strictly decreasing. *)
Lemma div_lt : forall a b, 0<a -> 1<b -> a/b < a.
Proof. exact div_lt. Qed.
(** [le] is compatible with a positive division. *)
Lemma div_le_mono : forall a b c, 0<c -> a<=b -> a/c <= b/c.
Proof.
intros a b c Hc Hab.
rewrite lt_eq_cases in Hab. destruct Hab as [LT|EQ];
[|rewrite EQ; order].
rewrite <- lt_succ_r.
rewrite (mul_lt_mono_pos_l c) by order.
nzsimpl.
rewrite (add_lt_mono_r _ _ (a mod c)).
rewrite <- div_mod by order.
apply lt_le_trans with b; trivial.
rewrite (div_mod b c) at 1 by order.
rewrite <- add_assoc, <- add_le_mono_l.
apply le_trans with (c+0).
nzsimpl; destruct (mod_pos_bound b c); order.
rewrite <- add_le_mono_l. destruct (mod_pos_bound a c); order.
Qed.
(** In this convention, [div] performs Rounding-Toward-Bottom.
Since we cannot speak of rational values here, we express this
fact by multiplying back by [b], and this leads to separates
statements according to the sign of [b].
First, [a/b] is below the exact fraction ...
*)
Lemma mul_div_le : forall a b, 0<b -> b*(a/b) <= a.
Proof.
intros.
rewrite (div_mod a b) at 2; try order.
rewrite <- (add_0_r (b*(a/b))) at 1.
rewrite <- add_le_mono_l.
now destruct (mod_pos_bound a b).
Qed.
Lemma mul_div_ge : forall a b, b<0 -> a <= b*(a/b).
Proof.
intros. rewrite <- div_opp_opp, opp_le_mono, <-mul_opp_l by order.
apply mul_div_le. now rewrite opp_pos_neg.
Qed.
(** ... and moreover it is the larger such integer, since [S(a/b)]
is strictly above the exact fraction.
*)
Lemma mul_succ_div_gt: forall a b, 0<b -> a < b*(S (a/b)).
Proof.
intros.
nzsimpl.
rewrite (div_mod a b) at 1; try order.
rewrite <- add_lt_mono_l.
destruct (mod_pos_bound a b); order.
Qed.
Lemma mul_succ_div_lt: forall a b, b<0 -> b*(S (a/b)) < a.
Proof.
intros. rewrite <- div_opp_opp, opp_lt_mono, <-mul_opp_l by order.
apply mul_succ_div_gt. now rewrite opp_pos_neg.
Qed.
(** NB: The four previous properties could be used as
specifications for [div]. *)
(** Inequality [mul_div_le] is exact iff the modulo is zero. *)
Lemma div_exact : forall a b, b~=0 -> (a == b*(a/b) <-> a mod b == 0).
Proof.
intros.
rewrite (div_mod a b) at 1; try order.
rewrite <- (add_0_r (b*(a/b))) at 2.
apply add_cancel_l.
Qed.
(** Some additional inequalities about div. *)
Theorem div_lt_upper_bound:
forall a b q, 0<b -> a < b*q -> a/b < q.
Proof.
intros.
rewrite (mul_lt_mono_pos_l b) by trivial.
apply le_lt_trans with a; trivial.
now apply mul_div_le.
Qed.
Theorem div_le_upper_bound:
forall a b q, 0<b -> a <= b*q -> a/b <= q.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
Theorem div_le_lower_bound:
forall a b q, 0<b -> b*q <= a -> q <= a/b.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
(** A division respects opposite monotonicity for the divisor *)
Lemma div_le_compat_l: forall p q r, 0<=p -> 0<q<=r -> p/r <= p/q.
Proof. exact div_le_compat_l. Qed.
(** * Relations between usual operations and mod and div *)
Lemma mod_add : forall a b c, c~=0 ->
(a + b * c) mod c == a mod c.
Proof.
intros.
symmetry.
apply mod_unique with (a/c+b); trivial.
now apply mod_bound_or.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add : forall a b c, c~=0 ->
(a + b * c) / c == a / c + b.
Proof.
intros.
apply (mul_cancel_l _ _ c); try order.
apply (add_cancel_r _ _ ((a+b*c) mod c)).
rewrite <- div_mod, mod_add by order.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add_l: forall a b c, b~=0 ->
(a * b + c) / b == a + c / b.
Proof.
intros a b c. rewrite (add_comm _ c), (add_comm a).
now apply div_add.
Qed.
(** Cancellations. *)
Lemma div_mul_cancel_r : forall a b c, b~=0 -> c~=0 ->
(a*c)/(b*c) == a/b.
Proof.
intros.
symmetry.
apply div_unique with ((a mod b)*c).
(* ineqs *)
destruct (lt_ge_cases 0 c).
rewrite <-(mul_0_l c), <-2mul_lt_mono_pos_r, <-2mul_le_mono_pos_r by trivial.
now apply mod_bound_or.
rewrite <-(mul_0_l c), <-2mul_lt_mono_neg_r, <-2mul_le_mono_neg_r by order.
destruct (mod_bound_or a b); tauto.
(* equation *)
rewrite (div_mod a b) at 1 by order.
rewrite mul_add_distr_r.
rewrite add_cancel_r.
rewrite <- 2 mul_assoc. now rewrite (mul_comm c).
Qed.
Lemma div_mul_cancel_l : forall a b c, b~=0 -> c~=0 ->
(c*a)/(c*b) == a/b.
Proof.
intros. rewrite !(mul_comm c); now apply div_mul_cancel_r.
Qed.
Lemma mul_mod_distr_l: forall a b c, b~=0 -> c~=0 ->
(c*a) mod (c*b) == c * (a mod b).
Proof.
intros.
rewrite <- (add_cancel_l _ _ ((c*b)* ((c*a)/(c*b)))).
rewrite <- div_mod.
rewrite div_mul_cancel_l by trivial.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
rewrite <- neq_mul_0; auto.
Qed.
Lemma mul_mod_distr_r: forall a b c, b~=0 -> c~=0 ->
(a*c) mod (b*c) == (a mod b) * c.
Proof.
intros. rewrite !(mul_comm _ c); now rewrite mul_mod_distr_l.
Qed.
(** Operations modulo. *)
Theorem mod_mod: forall a n, n~=0 ->
(a mod n) mod n == a mod n.
Proof.
intros. rewrite mod_small_iff by trivial.
now apply mod_bound_or.
Qed.
Lemma mul_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)*b) mod n == (a*b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite add_comm, (mul_comm n), (mul_comm _ b).
rewrite mul_add_distr_l, mul_assoc.
intros. rewrite mod_add by trivial.
now rewrite mul_comm.
Qed.
Lemma mul_mod_idemp_r : forall a b n, n~=0 ->
(a*(b mod n)) mod n == (a*b) mod n.
Proof.
intros. rewrite !(mul_comm a). now apply mul_mod_idemp_l.
Qed.
Theorem mul_mod: forall a b n, n~=0 ->
(a * b) mod n == ((a mod n) * (b mod n)) mod n.
Proof.
intros. now rewrite mul_mod_idemp_l, mul_mod_idemp_r.
Qed.
Lemma add_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)+b) mod n == (a+b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite <- add_assoc, add_comm, mul_comm.
intros. now rewrite mod_add.
Qed.
Lemma add_mod_idemp_r : forall a b n, n~=0 ->
(a+(b mod n)) mod n == (a+b) mod n.
Proof.
intros. rewrite !(add_comm a). now apply add_mod_idemp_l.
Qed.
Theorem add_mod: forall a b n, n~=0 ->
(a+b) mod n == (a mod n + b mod n) mod n.
Proof.
intros. now rewrite add_mod_idemp_l, add_mod_idemp_r.
Qed.
(** With the current convention, the following result isn't always
true with a negative last divisor. For instance
[ 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) ], or
[ 5/2/(-2) = -1 <> -2 = 5 / (2*-2) ]. *)
Lemma div_div : forall a b c, b~=0 -> 0<c ->
(a/b)/c == a/(b*c).
Proof.
intros a b c Hb Hc.
apply div_unique with (b*((a/b) mod c) + a mod b).
(* begin 0<= ... <b*c \/ ... *)
apply neg_pos_cases in Hb. destruct Hb as [Hb|Hb].
right.
destruct (mod_pos_bound (a/b) c), (mod_neg_bound a b); trivial.
split.
apply le_lt_trans with (b*((a/b) mod c) + b).
now rewrite <- mul_succ_r, <- mul_le_mono_neg_l, le_succ_l.
now rewrite <- add_lt_mono_l.
apply add_nonpos_nonpos; trivial.
apply mul_nonpos_nonneg; order.
left.
destruct (mod_pos_bound (a/b) c), (mod_pos_bound a b); trivial.
split.
apply add_nonneg_nonneg; trivial.
apply mul_nonneg_nonneg; order.
apply lt_le_trans with (b*((a/b) mod c) + b).
now rewrite <- add_lt_mono_l.
now rewrite <- mul_succ_r, <- mul_le_mono_pos_l, le_succ_l.
(* end 0<= ... < b*c \/ ... *)
rewrite (div_mod a b) at 1 by order.
rewrite add_assoc, add_cancel_r.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
Qed.
(** Similarly, the following result doesn't always hold when [c<0].
For instance [3 mod (-2*-2)) = 3] while
[3 mod (-2) + (-2)*((3/-2) mod -2) = -1].
*)
Lemma rem_mul_r : forall a b c, b~=0 -> 0<c ->
a mod (b*c) == a mod b + b*((a/b) mod c).
Proof.
intros a b c Hb Hc.
apply add_cancel_l with (b*c*(a/(b*c))).
rewrite <- div_mod by (apply neq_mul_0; split; order).
rewrite <- div_div by trivial.
rewrite add_assoc, add_shuffle0, <- mul_assoc, <- mul_add_distr_l.
rewrite <- div_mod by order.
apply div_mod; order.
Qed.
Lemma mod_div: forall a b, b~=0 ->
a mod b / b == 0.
Proof.
intros a b Hb.
rewrite div_small_iff by assumption.
auto using mod_bound_or.
Qed.
(** A last inequality: *)
Theorem div_mul_le:
forall a b c, 0<=a -> 0<b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof. exact div_mul_le. Qed.
End ZDivProp.
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_mem_staging_reg #(
parameter WIDTH = 32,
parameter LOW_LATENCY = 0 //used by mem1x when the latency through the memory is only 1 cycle
)
(
input wire clk,
input wire resetn,
input wire enable,
input wire [WIDTH-1:0] rdata_in,
output logic [WIDTH-1:0] rdata_out
);
generate
if (LOW_LATENCY) begin
reg [WIDTH-1:0] rdata_r;
reg enable_r;
always @(posedge clk or negedge resetn) begin
if (!resetn) begin
enable_r <= 1'b1;
end else begin
enable_r <= enable;
if (enable_r) begin
rdata_r <= rdata_in;
end
end
end
assign rdata_out = enable_r ? rdata_in : rdata_r;
end else begin
reg [WIDTH-1:0] rdata_r[0:1];
reg [1:0] rdata_vld_r;
reg enable_r;
always @(posedge clk or negedge resetn) begin
if (!resetn) begin
rdata_vld_r <= 2'b00;
enable_r <= 1'b0;
end else begin
if (~rdata_vld_r[1] | enable) begin
enable_r <= enable;
rdata_vld_r[0] <= ~enable | (~rdata_vld_r[1] & ~enable_r & enable); //use the first staging register if disabled, or re-enabled after only one cycle
rdata_vld_r[1] <= rdata_vld_r[0] & (rdata_vld_r[1] | ~enable);
rdata_r[1] <= rdata_r[0];
rdata_r[0] <= rdata_in;
end
end
end
always @(*) begin
case (rdata_vld_r)
2'b00: rdata_out = rdata_in;
2'b01: rdata_out = rdata_r[0];
2'b10: rdata_out = rdata_r[1];
2'b11: rdata_out = rdata_r[1];
default: rdata_out = {WIDTH{1'bx}};
endcase
end
end
endgenerate
endmodule
// vim:set filetype=verilog:
|
(** * PE: Partial Evaluation *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if eq_id_dec V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V' SCase
means to reason by cases over [eq_id_dec V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (eq_id_dec i j);
[ Case_aux c "equal"; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** *** Aside on [In].
We will make heavy use of the [In] predicate from the standard library.
[In] is equivalent to the [appears_in] predicate introduced in Logic.v, but
defined using a [Fixpoint] rather than an [Inductive]. *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** [In] comes with various useful lemmas. *)
Check in_or_app.
(* ===> in_or_app: forall (A : Type) (l m : list A) (a : A),
In a l \/ In a m -> In a (l ++ m) *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
Check in_dec.
(* ===> in_dec : forall A : Type,
(forall x y : A, {x = y} + {x <> y}) ->
forall (a : A) (l : list A), {In a l} + {~ In a l}] *)
(** Note that we can compute with [in_dec], just as with [eq_id_dec]. *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3);(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update.
compare V0 V Case; auto. rewrite eq_id; auto. rewrite neq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st || c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if eq_id_dec V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if eq_id_dec V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (eq_id_dec V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
destruct (eq_id_dec V V0). reflexivity. rewrite neq_id; auto.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite neq_id; auto.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if eq_id_dec V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0 Case.
Case "equal". rewrite eq_id; auto.
Case "not equal". rewrite pe_remove_correct. repeat rewrite neq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_or_app.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => if eq_id_dec x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
Case "->".
intros. inversion H; clear H.
left. assumption.
destruct (eq_id_dec h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite neq_id; auto.
Case "<-".
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
Case "->".
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
apply ex_falso_quodlibet. apply Heq. split. assumption. reflexivity.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if in_dec eq_id_dec V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V Case.
reflexivity.
destruct (in_dec eq_id_dec V ids);
reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (in_dec eq_id_dec V (pe_compare pe_st1 pe_st2)).
reflexivity.
apply pe_compare_correct. auto. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if in_dec eq_id_dec V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (in_dec eq_id_dec V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); auto.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (in_dec eq_id_dec V ids); reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
|| (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
|| (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ;; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
`include "timescale.v"
// UART Protocol Layer
module uart_if (/*AUTOARG*/
// Outputs
uart_dout, uart_addr, uart_mem_we, uart_mem_re, reg_we, uart_tx,
// Inputs
uart_mem_i, uart_reg_i, clk, arst_n, uart_rx
);
output [23:0] uart_dout;
output [13:0] uart_addr;
output uart_mem_we;
output uart_mem_re;
output reg_we;
output uart_tx;
input [23:0] uart_mem_i;
input [23:0] uart_reg_i;
input clk;
input arst_n;
input uart_rx;
reg [15:0] cmd;
reg [23:0] uart_dout;
parameter stIdle = 0;
parameter stCmd1 = 1;
parameter stCmd2 = 2;
parameter stData1 = 3;
parameter stData2 = 4;
parameter stData3 = 5;
parameter stWr = 6;
parameter stRd = 7;
reg [2:0] state;
reg [7:0] din_i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] dout_o; // From uart_ of sasc_top.v
wire empty_o; // From uart_ of sasc_top.v
wire full_o; // From uart_ of sasc_top.v
wire sio_ce; // From baud_ of sasc_brg.v
wire sio_ce_x4; // From baud_ of sasc_brg.v
// End of automatics
wire cmdRd;
wire cmdMem;
reg re_i;
reg we_i;
sasc_top uart_ (// Outputs
.txd_o (uart_tx),
.rts_o (),
// Inputs
.rxd_i (uart_rx),
.cts_i (1'b0),
.rst_n (arst_n),
/*AUTOINST*/
// Outputs
.dout_o (dout_o[7:0]),
.full_o (full_o),
.empty_o (empty_o),
// Inputs
.clk (clk),
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
.din_i (din_i[7:0]),
.re_i (re_i),
.we_i (we_i));
sasc_brg baud_ (/*AUTOINST*/
// Outputs
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
// Inputs
.clk (clk),
.arst_n (arst_n));
always @ (posedge clk or negedge arst_n)
if (~arst_n)
state <= stIdle;
else
case (state)
stIdle : if (~empty_o) state <= stCmd1;
stCmd1 : if (~empty_o) state <= stCmd2;
stCmd2 : if (cmdRd) state <= stRd; // read
else if (~empty_o) state <= stData1; // write
stData1: if (cmdRd) state <= stData2; // read
else if (~empty_o) state <= stData2; // write
stData2: if (cmdRd) state <= stData3; // read
else if (~empty_o) state <= stData3; // write
stData3: if (cmdRd) state <= stIdle; // read done
else state <= stWr; // write commit
stWr: state <= stIdle;
stRd: state <= stData1;
endcase // case(state)
// --------------- Command Word Capture ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n) cmd <= 0;
else
begin
if (state==stIdle) cmd[15:8] <= dout_o[7:0];
if (state==stCmd1) cmd[7:0] <= dout_o[7:0];
end
assign cmdRd = ~cmd[15];
assign cmdMem = cmd[14];
assign uart_addr = cmd[13:0];
// --------------- Write Command ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n)
uart_dout <= 0;
else
begin
if (state==stCmd2 & ~cmdRd) uart_dout[23:16] <= dout_o[7:0];
if (state==stData1 & ~cmdRd) uart_dout[15:8] <= dout_o[7:0];
if (state==stData2 & ~cmdRd) uart_dout[7:0] <= dout_o[7:0];
end
always @ (/*AS*/cmdRd or empty_o or state)
case (state)
stIdle : re_i = ~empty_o;
stCmd1 : re_i = ~empty_o;
stCmd2 : re_i = ~empty_o & ~cmdRd;
stData1: re_i = ~empty_o & ~cmdRd;
stData2: re_i = ~empty_o & ~cmdRd;
default: re_i = 0;
endcase // case(state)
assign uart_mem_we = (state==stWr) & cmdMem;
assign reg_we = (state==stWr) & ~cmdMem;
// --------------- Read Command ----------------- //
always @ (/*AS*/cmdMem or state or uart_mem_i or uart_reg_i)
case (state)
stData2: din_i[7:0] = cmdMem ? uart_mem_i[15:8] : uart_reg_i[15:8];
stData3: din_i[7:0] = cmdMem ? uart_mem_i[7:0] : uart_reg_i[7:0];
default: din_i[7:0] = cmdMem ? uart_mem_i[23:16] : uart_reg_i[23:16];
endcase // case(state)
always @ (/*AS*/cmdRd or state)
case (state)
stData1: we_i = cmdRd;
stData2: we_i = cmdRd;
stData3: we_i = cmdRd;
default: we_i = 0;
endcase // case(state)
assign uart_mem_re = (state==stRd);
endmodule // uart_if
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_prp_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [5:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [5:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_jtag_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module: altor32_ram_dp - Dual port RAM (used in cache)
//-----------------------------------------------------------------
module altor32_ram_dp
#(
parameter WIDTH = 8,
parameter SIZE = 14
)
(
input aclk_i /*verilator public*/,
output [(WIDTH - 1):0] adat_o /*verilator public*/,
input [(WIDTH - 1):0] adat_i /*verilator public*/,
input [(SIZE - 1):0] aadr_i /*verilator public*/,
input awr_i /*verilator public*/,
input bclk_i /*verilator public*/,
output [(WIDTH - 1):0] bdat_o /*verilator public*/,
input [(WIDTH - 1):0] bdat_i /*verilator public*/,
input [(SIZE - 1):0] badr_i /*verilator public*/,
input bwr_i /*verilator public*/
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [(SIZE - 1):0] rd_addr_a_q;
reg [(SIZE - 1):0] rd_addr_b_q;
//-----------------------------------------------------------------
// Processes
//-----------------------------------------------------------------
always @ (posedge aclk_i)
begin
if (awr_i == 1'b1)
ram[aadr_i] <= adat_i;
rd_addr_a_q <= aadr_i;
end
always @ (posedge bclk_i)
begin
if (bwr_i == 1'b1)
ram[badr_i] <= bdat_i;
rd_addr_b_q <= badr_i;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign adat_o = ram[rd_addr_a_q];
assign bdat_o = ram[rd_addr_b_q];
//-----------------------------------------------------------------
// Init Memory
//-----------------------------------------------------------------
`ifdef ALTOR32_CLEAR_RAM
integer i;
initial
begin
for (i=0;i<((2<< (SIZE-1)) - 1);i=i+1)
begin
ram[i] = 0;
end
end
`endif
endmodule
|
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
//`define ENABLE_HPS
module DE0_NANO_SOC_Default(
//////////// ADC //////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
//////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
`ifdef ENABLE_HPS
//////////// HPS //////////
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CKE,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout HPS_GSENSOR_INT,
inout HPS_I2C0_SCLK,
inout HPS_I2C0_SDAT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif /*ENABLE_HPS*/
//////////// KEY //////////
input [1:0] KEY,
//////////// LED //////////
output [7:0] LED,
//////////// SW //////////
input [3:0] SW,
//////////// GPIO_0, GPIO connect to GPIO Default //////////
inout [35:0] GPIO_0,
//////////// GPIO_1, GPIO connect to GPIO Default //////////
inout [35:0] GPIO_1
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
assign GPIO_0 = 36'hzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzz;
//mainPLL PLL( FPGA_CLK1_50, SW[2], clk );
wire [31:0] cpuDataOut;
wire [31:0] cpuDataIn;
wire [31:0] cpuDataInAddr;
wire [31:0] cpuDataOutAddr;
wire cpuWrEn;
wire [31:0] instrBus;
wire [31:0] pcBus;
wire [31:0] CPU_StatusBus;
wire forceRoot;
wire flushing;
wire [31:0] instrCacheAddr;
wire [31:0] instrCacheData;
wire [31:0] dataOutFlowCtrl;
wire [31:0] dataOutUART;
wire [31:0] dataOutDataCache;
wire clk;
wire rst;
wire TxD;
assign GPIO_0[0] = TxD;
assign rst = SW[0];
assign clk = FPGA_CLK1_50;
wolfcore CPU(
.dataOutput(cpuDataOut),
.dataInput(cpuDataIn),
.dataInAddr(cpuDataInAddr),
.dataOutAddr(cpuDataOutAddr),
.dataWrEn(cpuWrEn),
.instrInput(instrBus),
.pc(pcBus),
.CPU_Status(CPU_StatusBus),
.rst(rst),
.clk(clk),
.forceRoot(forceRoot),
.flushing(flushing)
);
flowController instrCtrl(
.rst(rst),
.clk(clk),
.pc(pcBus),
.CPU_Status(CPU_StatusBus),
.flushing(flushing),
.instrOut(instrBus),
.forceRoot(forceRoot),
.memAddr(instrCacheAddr),
.instrIn(instrCacheData),
.IRQ(32'h00000000),
.inputAddr(cpuDataOutAddr),
.outputAddr(cpuDataInAddr),
.inputData(cpuDataOut),
.outputData(dataOutFlowCtrl),
.wrEn(cpuWrEn)
);
progMem instrCache(
.instrOutput(instrCacheData),
.instrAddress(instrCacheAddr),
.clk(clk)
);
dataController dataCache(
.dataIn(cpuDataOut),
.dataInAddr(cpuDataOutAddr),
.dataOut(dataOutDataCache),
.dataOutAddr(cpuDataInAddr),
.wren(cpuWrEn),
.clk(clk)
);
UART testUART(
.clk(clk),
.rst(rst),
.RxD(1'b0),
.TxD(TxD),
.inputData(cpuDataOut),
.inputAddr(cpuDataOutAddr),
.outputData(dataOutUART),
.outputAddr(cpuDataInAddr),
.wren(cpuWrEn)
);
outputDataMux dataMux(
.outputAddr(cpuDataInAddr),
.outputDataUART(dataOutUART),
.outputDataFlowCtrl(dataOutFlowCtrl),
.outputDataDataCache(dataOutDataCache),
.outputData(cpuDataIn)
);
endmodule
|
module REG(clk, rw, addr, data_in, data_out);
parameter data_witdh = 32;
parameter addr_witdh = 5;
parameter reg_witdh = 28;
input clk;
wire clk;
input rw;
wire rw;
input req;
wire req;
output ack;
reg ack;
input [addr_witdh-1: 0] addr;
wire addr;
input [data_witdh-1: 0] data_in;
wire data_in;
output [data_witdh-1: 0] data_out;
reg data_out;
//0
output [15: 0] SDMA_System_Address_Low;
wire [15: 0] SDMA_System_Address_Low;
output [15: 0] SDMA_System_Address_High;
wire [15: 0] SDMA_System_Address_High;
//1
output [15: 0] Block_Size;
wire [15: 0] Block_Size;
output [15: 0] Block_Count;
wire [15: 0] Block_Count;
//2
output [15: 0] Argument0;
wire [15: 0] Argument0;
output [15: 0] Argument1;
wire [15: 0] Argument1;
output [31:0] Argument;
wire [31:0] Argument;
assign Argument[15:0] = Argument0;
assign Argument[31:16] = Argument1;
//3
output [15: 0] Transfer_Mode;
wire [15: 0] Transfer_Mode;
output [15: 0] Command;
wire [15: 0] Command;
wire [5:0] cmd_index; //CMD
assign cmd_index[5:0] = Command[13:8];
//4-5-6-7
output [15: 0] Response0; //read only
output [15: 0] Response1;
output [15: 0] Response2;
output [15: 0] Response3;
output [15: 0] Response4;
output [15: 0] Response5;
output [15: 0] Response6;
output [15: 0] Response7;
wire [15: 0] Response0;
wire [15: 0] Response1;
wire [15: 0] Response2;
wire [15: 0] Response3;
wire [15: 0] Response4;
wire [15: 0] Response5;
wire [15: 0] Response6;
wire [15: 0] Response7;
//8
output [15: 0] Buffer_Data_Port0;
wire [15: 0] Buffer_Data_Port0;
output [15: 0] Buffer_Data_Port1;
wire [15: 0] Buffer_Data_Port1;
//9
output [15: 0] Present_State1; // read only
wire [15: 0] Present_State1;
output [15: 0] Present_State2;
wire [15: 0] Present_State2;
//10
output [7: 0] Host_Control;
output [7: 0] Power_Control;
wire [7: 0] Host_Control;
wire [7: 0] Power_Control;
output [7: 0] Block_Gap_Control;
output [7: 0] Wakeup_Control;
wire [7: 0] Block_Gap_Control;
wire [7: 0] Wakeup_Control;
//11
output [15: 0] Clock_Control;
wire [15: 0] Clock_Control;
output [7: 0] Timeout_Control;
output [7: 0] Software_Reset;
wire [7: 0] Timeout_Control;
wire [7: 0] Software_Reset;
//12
output [15: 0] Normal_Interrupt_Status;
wire [15: 0] Normal_Interrupt_Status;
output [15: 0] Error_Interrupt_Status;
wire [15: 0] Error_Interrupt_Status;
//13
output [15: 0] Normal_Interrupt_Status_Enable;
wire [15: 0] Normal_Interrupt_Status_Enable;
output [15: 0] Error_Interrupt_Status_Enable;
wire [15: 0] Error_Interrupt_Status_Enable;
//14
output [15: 0] Normal_Interrupt_Signal_Enable;
wire [15: 0] Normal_Interrupt_Signal_Enable;
output [15: 0] Error_Interrupt_Signal_Enable;
wire [15: 0] Error_Interrupt_Signal_Enable;
//15
output [15: 0] Auto_CMD12_Error_Status;
wire [15: 0] Auto_CMD12_Error_Status;
//--
//16
output [15: 0] Capabilities1; //*
wire [15: 0] Capabilities1; //*
output [15: 0] Capabilities2; //*
wire [15: 0] Capabilities2; //*
//17
output [15: 0] Capabilities_Reserved_1; //*
wire [15: 0] Capabilities_Reserved_1; //*
output [15: 0] Capabilities_Reserved_2; //*
wire [15: 0] Capabilities_Reserved_2; //*
//18
output [15: 0] Maximum_Current_Capabilities1; //*
wire [15: 0] Maximum_Current_Capabilities1; //*
output [15: 0] Maximum_Current_Capabilities2; //*
wire [15: 0] Maximum_Current_Capabilities2; //*
//19
output [15: 0] Maximum_Current_Capabilities_Reserved_1; //*
output [15: 0] Maximum_Current_Capabilities_Reserved_2; //*
wire [15: 0] Maximum_Current_Capabilities_Reserved_1; //*
wire [15: 0] Maximum_Current_Capabilities_Reserved_2; //*
//20
output [15: 0] Force_Event_for_Auto_CMD12_Error_Status;
output [15: 0] Force_Event_for_Error_Interrupt_Status;
wire [15: 0] Force_Event_for_Auto_CMD12_Error_Status;
wire [15: 0] Force_Event_for_Error_Interrupt_Status;
//21
output [7: 0] ADMA_Error_Status;//*
wire [7: 0] ADMA_Error_Status;//*
//22-23
output [15: 0] ADMA_System_Address_15;
output [15: 0] ADMA_System_Address_31;
output [15: 0] ADMA_System_Address_47;
output [15: 0] ADMA_System_Address_63;
wire [15: 0] ADMA_System_Address_15;
wire [15: 0] ADMA_System_Address_31;
wire [15: 0] ADMA_System_Address_47;
wire [15: 0] ADMA_System_Address_63;
//27
output [15: 0] Host_Controller_Version;
output [15: 0] Slot_Interrupt_Status;
wire [15: 0] Host_Controller_Version;
wire [15: 0] Slot_Interrupt_Status;
//24
output [15:0] Timeout_Reg;
wire [15:0] Timeout_Reg;
output [15:0] data;
wire writeRead;
wire multipleData;
wire timeout_enable;
wire [3:0] block_count;
//25
input cmd_complete;
wire cmd_complete;
input cmd_index_error;
wire cmd_index_error;
always @(cmd_complete)
regs[5'b11001][0] <= cmd_complete;
always @(cmd_index_error)
regs[5'b11001][1] <= cmd_index_error;
reg [data_witdh-1: 0] regs [0: reg_witdh-1];
assign SDMA_System_Address_Low[15:0] = regs[5'b00000][15:0];
assign SDMA_System_Address_High[15:0] = regs[5'b00000][31:16];
assign Block_Size[15:0] = regs[5'b00001][15:0];
assign Block_Count[15:0] = regs[5'b00001][31:16];
wire [3:0] blockCount; //DATA
assign blockCount = Block_Count[3:0];
assign Argument0[15:0] = regs[ 5'b00010][15: 0];
assign Argument1[15:0] = regs[ 5'b00010][31: 16];
assign Transfer_Mode[15:0] = regs[5'b00011];
assign Command[15:0] = regs[5'b00011][31: 16];
assign Response0[15:0] = regs[5'b00100][15:0];
assign Response1[15:0] = regs[5'b00100][31: 16];
assign Response2[15:0] = regs[5'b00101][15:0];
assign Response3[15:0] = regs[5'b00101][31: 16];
assign Response4[15:0] = regs[5'b00110][15:0];
assign Response5[15:0] = regs[5'b00110][31: 16];
assign Response6[15:0] = regs[5'b00111][15:0];
assign Response7[15:0] = regs[5'b00111][31: 16];
assign Buffer_Data_Port0[15:0] = regs[5'b01000][15:0];
assign Buffer_Data_Port1[15:0] = regs[5'b01000][31: 16];
assign Present_State1[15:0] = regs[5'b01001][15:0];
assign Present_State2[15:0] = regs[5'b01001][31: 16];
assign Host_Control[7:0] = regs[5'b01010][7:0];
assign Power_Control[7:0] = regs[5'b01010][15:8];
assign Block_Gap_Control[7:0] = regs[5'b01010][23:16];
assign Wakeup_Control[7:0] = regs[5'b01010][31:24];
assign Clock_Control[15:0] = regs[5'b01011][15:0];
assign Timeout_Control[7:0] = regs[5'b01011][23:16];
assign Software_Reset[7:0] = regs[5'b01011][31:24];
assign Normal_Interrupt_Status[15:0] = regs[5'b01100][15:0];
assign Error_Interrupt_Status[15:0] = regs[5'b01100][31: 16];
assign Normal_Interrupt_Status_Enable[15:0] = regs[5'b01101][15:0];
assign Error_Interrupt_Status_Enable[15:0] = regs[5'b01101][31: 16];
assign Normal_Interrupt_Signal_Enable[15:0] = regs[5'b01110][15:0];
assign Error_Interrupt_Signal_Enable[15:0] = regs[5'b01110][31: 16];
assign Auto_CMD12_Error_Status[15:0] = regs[5'b01111][15:0];
//assign 0 = [31: 16] regs[addr];
assign Capabilities1[15:0] = regs[5'b10000][15:0];
assign Capabilities2[15:0] = regs[5'b10000][31: 16];
assign Capabilities_Reserved_1[15:0] = regs[5'b10001][15:0];
assign Capabilities_Reserved_2[15:0] = regs[5'b10001][31: 16];
assign Maximum_Current_Capabilities1[15:0] = regs[5'b10010][15:0];
assign Maximum_Current_Capabilities2[15:0] = regs[5'b10010][31: 16];
assign Maximum_Current_Capabilities_Reserved_1[15:0] = regs[5'b10011][15:0];
assign Maximum_Current_Capabilities_Reserved_2[15:0] = regs[5'b10011][31: 16];
assign Force_Event_for_Auto_CMD12_Error_Status[15:0] = regs[5'b10100][15:0];
assign Force_Event_for_Error_Interrupt_Status[15:0] = regs[5'b10100][31: 16];
assign ADMA_Error_Status[7:0] = regs[5'b10101][7:0];
assign ADMA_System_Address_15[15:0] = regs[5'b10110][15:0];
assign ADMA_System_Address_31[15:0] = regs[5'b10110][31: 16];
assign ADMA_System_Address_47[15:0] = regs[5'b10111][15:0];
assign ADMA_System_Address_63[15:0] = regs[5'b10111][31: 16];
assign Slot_Interrupt_Status[15: 0] = regs[5'b10011][15: 0];
assign Host_Controller_Version[15: 0] = regs[5'b10011][31: 16];
assign Timeout_Reg[15: 0] = regs[5'b11000][15: 0];
assign data[15: 0] = regs[5'b11000][31: 16];
// assign timeout_Reg[14:0] = Timeout[14:0]; //DATA
assign timeout_enable = data[0];
assign writeRead = data[1];
assign multipleData = data[2];
assign block_count = data[6:3];
assign cmd_complete = regs[5'b11001][0];
assign cmd_complete = regs[5'b11001][0];
// Lectura y escritura desde CPU (se estan leyendo y escribiendo 32)
always @(posedge clk) begin
if(req == 1) begin
if (rw == 1) begin //lectura
data_out <= regs[addr];
ack <= 1;
end
else begin
regs[addr] <= data_in;
ack <= 1;
end
end
else begin
data_out <= data_out;
ack <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:04:14 06/30/2012
// Design Name:
// Module Name: MIO_BUS
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MIO_BUS(input clk,
input rst,
input[3:0]BTN,
input[15:0]SW,
input mem_w,
input[31:0]Cpu_data2bus, //data from CPU
input[31:0]addr_bus,
input[31:0]ram_data_out,
input[15:0]led_out,
input[31:0]counter_out,
input counter0_out,
input counter1_out,
input counter2_out,
output reg[31:0]Cpu_data4bus, //write to CPU
output reg[31:0]ram_data_in, //from CPU write to Memory
output reg[9:0]ram_addr, //Memory Address signals
output reg data_ram_we,
output reg GPIOf0000000_we,
output reg GPIOe0000000_we,
output reg counter_we,
output reg[31:0]Peripheral_in
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Peter Monsson.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
wire [31:0] in = cyc;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
package lpcm_pkg;
class lpcm_tr;
int latency;
int sample;
function new();
latency = 0;
sample = 0;
endfunction
function string convert2string();
return $sformatf("sample=0x%0h latency=%0d", sample, latency);
endfunction
endclass
endpackage
//internal error happens when lpcm_pkg is not imported
//import lpcm_pkg::*;
module Test (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input [31:0] in;
initial begin
string s;
lpcm_pkg::lpcm_tr tr; // internal error happens when lpcm_pkg is not imported
tr = new();
tr.sample = 1;
tr.latency = 2;
s = tr.convert2string();
$display("hello %s", tr.convert2string());
if (s != "sample=0x1 latency=2") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//
// 8192 bytes, 32bit interface
`timescale 1ns/1ps
module bb_ram(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [12:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
wire [3:0] dip;
RAMB16_S9_altera ram0 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[7:0] ),
.rden ( en ),
.wren ( we[0] ),
.q ( data_out[7:0] )
);
defparam ram0.init_file = "bb_ram00.mif";
RAMB16_S9_altera ram1 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[15:8] ),
.rden ( en ),
.wren ( we[1] ),
.q ( data_out[15:8] )
);
defparam ram1.init_file = "bb_ram01.mif";
RAMB16_S9_altera ram2 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[23:16] ),
.rden ( en ),
.wren ( we[2] ),
.q ( data_out[23:16] )
);
defparam ram2.init_file = "bb_ram02.mif";
RAMB16_S9_altera ram3 (
.address ( addr[12:2] ),
.clock ( clk ),
.data ( data_in[31:24] ),
.rden ( en ),
.wren ( we[3] ),
.q ( data_out[31:24] )
);
defparam ram3.init_file = "bb_ram03.mif";
endmodule
|
`include "defines.v"
module ex_mem(
input wire clk,
input wire rst,
//input
//MEM-WB
input wire[31:0] writeData_i,
//MEM
input wire[31:0] insAddr_i,
input wire[31:0] storeData_i,
input wire[2:0] memOp_i,
//WB
input wire writeReg_i,
input wire[4:0] writeRegAddr_i,
input wire[31:0] writeDataHi_i,
input wire[31:0] writeDataLo_i,
input wire writeRegHiLo_i,
input wire writeCP0_i,
input wire[4:0] writeCP0Addr_i,
//Exception
input wire insValid_i,
input wire inDelaySlot_i,
input wire[3:0] exception_i,
input wire[31:0] badVAddr_i,
//Control
input wire pauseControl_i,
input wire flush_i,
//output
//MEM-WB
output reg[31:0] writeData_o,
//MEM
output reg[31:0] insAddr_o,
output reg[31:0] storeData_o,
output reg[2:0] memOp_o,
//WB
output reg writeReg_o,
output reg[4:0] writeRegAddr_o,
output reg[31:0] writeDataHi_o,
output reg[31:0] writeDataLo_o,
output reg writeRegHiLo_o,
output reg writeCP0_o,
output reg[4:0] writeCP0Addr_o,
//Exception
output reg insValid_o,
output reg inDelaySlot_o,
output reg[3:0] exception_o,
output reg[31:0] badVAddr_o
);
//MEM-WB
wire[31:0] writeData = writeData_o;
//MEM
wire[31:0] insAddr = insAddr_o;
wire[31:0] storeData = storeData_o;
wire[2:0] ramOp = memOp_o;
//WB
wire writeReg = writeReg_o;
wire[4:0] writeRegAddr = writeRegAddr_o;
wire[31:0] writeDataHi = writeDataHi_o;
wire[31:0] writeDataLo = writeDataLo_o;
wire writeRegHiLo = writeRegHiLo_o;
wire writeCP0 = writeCP0_o;
wire[4:0] writeCP0Addr = writeCP0Addr_o;
//Exception
wire insValid = insValid_o;
wire inDelaySlot = inDelaySlot_o;
wire[3:0] exception = exception_o;
wire[31:0] badVAddr = badVAddr_o;
always @(posedge clk) begin
if (rst == `Enable) begin
//MEM-WB
writeData_o <= `ZeroWord;
//MEM
insAddr_o <= `ZeroWord;
storeData_o <= `ZeroWord;
memOp_o <= `MEM_NOP_OP;
//WB
writeReg_o <= `Disable;
writeRegAddr_o <= `ZeroWord;
writeDataHi_o <= `ZeroWord;
writeDataLo_o <= `ZeroWord;
writeRegHiLo_o <= `Disable;
writeCP0_o <= `Disable;
writeCP0Addr_o <= `CP0_NoAddr;
//Exception
insValid_o <= `Disable;
inDelaySlot_o <= `Disable;
exception_o <= `EXC_NONE;
badVAddr_o <= `ZeroWord;
end else if (pauseControl_i == `PAUSE_CONTROLED) begin
//MEM-WB
writeData_o <= writeData;
//MEM
insAddr_o <= insAddr;
storeData_o <= storeData;
memOp_o <= ramOp;
//WB
writeReg_o <= writeReg;
writeRegAddr_o <= writeRegAddr;
writeDataHi_o <= writeDataHi;
writeDataLo_o <= writeDataLo;
writeRegHiLo_o <= writeRegHiLo;
writeCP0_o <= writeCP0;
writeCP0Addr_o <= writeCP0Addr;
//Exception
insValid_o <= insValid;
inDelaySlot_o <= inDelaySlot;
exception_o <= exception;
badVAddr_o <= badVAddr;
end else if (flush_i == `Enable) begin
//MEM-WB
writeData_o <= `ZeroWord;
//MEM
insAddr_o <= `ZeroWord;
storeData_o <= `ZeroWord;
memOp_o <= `MEM_NOP_OP;
//WB
writeReg_o <= `Disable;
writeRegAddr_o <= `ZeroWord;
writeDataHi_o <= `ZeroWord;
writeDataLo_o <= `ZeroWord;
writeRegHiLo_o <= `Disable;
writeCP0_o <= `Disable;
writeCP0Addr_o <= `CP0_NoAddr;
//Exception
insValid_o <= `Disable;
inDelaySlot_o <= `Disable;
exception_o <= `EXC_NONE;
badVAddr_o <= `ZeroWord;
end else begin
//MEM-WB
writeData_o <= writeData_i;
//MEM
insAddr_o <= insAddr_i;
storeData_o <= storeData_i;
memOp_o <= memOp_i;
//WB
writeReg_o <= writeReg_i;
writeRegAddr_o <= writeRegAddr_i;
writeDataHi_o <= writeDataHi_i;
writeDataLo_o <= writeDataLo_i;
writeRegHiLo_o <= writeRegHiLo_i;
writeCP0_o <= writeCP0_i;
writeCP0Addr_o <= writeCP0Addr_i;
//Exception
insValid_o <= insValid_i;
inDelaySlot_o <= inDelaySlot_i;
exception_o <= exception_i;
badVAddr_o <= badVAddr_i;
end
end
endmodule
|
//
// 8192 bytes, 32bit interface
`timescale 1ns/1ps
module bb_ram(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [12:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
wire [3:0] dip;
RAMB16_S9 ram0(
.DO (data_out[7:0]),
.DOP (),
.ADDR (addr[12:2]),
.CLK (clk),
.DI (data_in[7:0]),
.DIP (dip[0]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam ram0.INIT_00 = 256'h0505050505050505050505040303030303030303020202020202020201010101;
defparam ram0.INIT_01 = 256'h0505050505050505050505050505050505050505050505050505050505050505;
defparam ram0.INIT_02 = 256'h0707070707070707070707070706060605050505050505050505050505050505;
defparam ram0.INIT_03 = 256'h0909090909080807070707070707070707070707070707070707070707070707;
defparam ram0.INIT_04 = 256'h0D0D0D0C0C0C0C0C0C0C0C0C0C0C0B0B0A0A0A0A0A0A0A0A0A0A0A0A0A0A0A09;
defparam ram0.INIT_05 = 256'h00000000101010101010100F0F0E0E0E0E0E0E0E0E0E0D0D0D0D0D0D0D0D0D0D;
defparam ram0.INIT_06 = 256'h0000000000000000000000000000;
defparam ram0.INIT_07 = 256'h0000000000000000000000000000;
defparam ram0.INIT_08 = 256'h0000000000000000000000000000;
defparam ram0.INIT_09 = 256'h0000000000000000000000000000;
defparam ram0.INIT_0A = 256'h0000000000000000000000000000;
defparam ram0.INIT_0B = 256'h0000000000000000000000000000;
defparam ram0.INIT_0C = 256'h0000000000000000000000000000;
defparam ram0.INIT_0D = 256'h0000000000000000000000000000;
defparam ram0.INIT_0E = 256'h0000000000000000000000000000;
defparam ram0.INIT_0F = 256'h0000000000000000000000000000;
defparam ram0.INIT_10 = 256'h0000000000000000000000000000;
defparam ram0.INIT_11 = 256'h0000000000000000000000000000;
defparam ram0.INIT_12 = 256'h0000000000000000000000000000;
defparam ram0.INIT_13 = 256'h0000000000000000000000000000;
defparam ram0.INIT_14 = 256'h0000000000000000000000000000;
defparam ram0.INIT_15 = 256'h0000000000000000000000000000;
defparam ram0.INIT_16 = 256'h0000000000000000000000000000;
defparam ram0.INIT_17 = 256'h0000000000000000000000000000;
defparam ram0.INIT_18 = 256'h0000000000000000000000000000;
defparam ram0.INIT_19 = 256'h0000000000000000000000000000;
defparam ram0.INIT_1A = 256'h0000000000000000000000000000;
defparam ram0.INIT_1B = 256'h0000000000000000000000000000;
defparam ram0.INIT_1C = 256'h0000000000000000000000000000;
defparam ram0.INIT_1D = 256'h0000000000000000000000000000;
defparam ram0.INIT_1E = 256'h0000000000000000000000000000;
defparam ram0.INIT_1F = 256'h0000000000000000000000000000;
defparam ram0.INIT_20 = 256'h0000000000000000000000000000;
defparam ram0.INIT_21 = 256'h0000000000000000000000000000;
defparam ram0.INIT_22 = 256'h0000000000000000000000000000;
defparam ram0.INIT_23 = 256'h0000000000000000000000000000;
defparam ram0.INIT_24 = 256'h0000000000000000000000000000;
defparam ram0.INIT_25 = 256'h0000000000000000000000000000;
defparam ram0.INIT_26 = 256'h0000000000000000000000000000;
defparam ram0.INIT_27 = 256'h0000000000000000000000000000;
defparam ram0.INIT_28 = 256'h0000000000000000000000000000;
defparam ram0.INIT_29 = 256'h0000000000000000000000000000;
defparam ram0.INIT_2A = 256'h0000000000000000000000000000;
defparam ram0.INIT_2B = 256'h0000000000000000000000000000;
defparam ram0.INIT_2C = 256'h0000000000000000000000000000;
defparam ram0.INIT_2D = 256'h0000000000000000000000000000;
defparam ram0.INIT_2E = 256'h0000000000000000000000000000;
defparam ram0.INIT_2F = 256'h0000000000000000000000000000;
defparam ram0.INIT_30 = 256'h0000000000000000000000000000;
defparam ram0.INIT_31 = 256'h0000000000000000000000000000;
defparam ram0.INIT_32 = 256'h0000000000000000000000000000;
defparam ram0.INIT_33 = 256'h0000000000000000000000000000;
defparam ram0.INIT_34 = 256'h0000000000000000000000000000;
defparam ram0.INIT_35 = 256'h0000000000000000000000000000;
defparam ram0.INIT_36 = 256'h0000000000000000000000000000;
defparam ram0.INIT_37 = 256'h0000000000000000000000000000;
defparam ram0.INIT_38 = 256'h0000000000000000000000000000;
defparam ram0.INIT_39 = 256'h0000000000000000000000000000;
defparam ram0.INIT_3A = 256'h0000000000000000000000000000;
defparam ram0.INIT_3B = 256'h0000000000000000000000000000;
defparam ram0.INIT_3C = 256'h0000000000000000000000000000;
defparam ram0.INIT_3D = 256'h0000000000000000000000000000;
defparam ram0.INIT_3E = 256'h0000000000000000000000000000;
defparam ram0.INIT_3F = 256'h0000000000000000000000000000;
RAMB16_S9 ram1(
.DO (data_out[15:8]),
.DOP (),
.ADDR (addr[12:2]),
.CLK (clk),
.DI (data_in[15:8]),
.DIP (dip[1]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam ram1.INIT_00 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_01 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_02 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_03 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_04 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_05 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_06 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_07 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_08 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_09 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_0A = 256'h00000000000000000000000000000000;
defparam ram1.INIT_0B = 256'h00000000000000000000000000000000;
defparam ram1.INIT_0C = 256'h00000000000000000000000000000000;
defparam ram1.INIT_0D = 256'h00000000000000000000000000000000;
defparam ram1.INIT_0E = 256'h00000000000000000000000000000000;
defparam ram1.INIT_0F = 256'h00000000000000000000000000000000;
defparam ram1.INIT_10 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_11 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_12 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_13 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_14 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_15 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_16 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_17 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_18 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_19 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_1A = 256'h00000000000000000000000000000000;
defparam ram1.INIT_1B = 256'h00000000000000000000000000000000;
defparam ram1.INIT_1C = 256'h00000000000000000000000000000000;
defparam ram1.INIT_1D = 256'h00000000000000000000000000000000;
defparam ram1.INIT_1E = 256'h00000000000000000000000000000000;
defparam ram1.INIT_1F = 256'h00000000000000000000000000000000;
defparam ram1.INIT_20 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_21 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_22 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_23 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_24 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_25 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_26 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_27 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_28 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_29 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_2A = 256'h00000000000000000000000000000000;
defparam ram1.INIT_2B = 256'h00000000000000000000000000000000;
defparam ram1.INIT_2C = 256'h00000000000000000000000000000000;
defparam ram1.INIT_2D = 256'h00000000000000000000000000000000;
defparam ram1.INIT_2E = 256'h00000000000000000000000000000000;
defparam ram1.INIT_2F = 256'h00000000000000000000000000000000;
defparam ram1.INIT_30 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_31 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_32 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_33 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_34 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_35 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_36 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_37 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_38 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_39 = 256'h00000000000000000000000000000000;
defparam ram1.INIT_3A = 256'h00000000000000000000000000000000;
defparam ram1.INIT_3B = 256'h00000000000000000000000000000000;
defparam ram1.INIT_3C = 256'h00000000000000000000000000000000;
defparam ram1.INIT_3D = 256'h00000000000000000000000000000000;
defparam ram1.INIT_3E = 256'h00000000000000000000000000000000;
defparam ram1.INIT_3F = 256'h00000000000000000000000000000000;
RAMB16_S9 ram2(
.DO (data_out[23:16]),
.DOP (),
.ADDR (addr[12:2]),
.CLK (clk),
.DI (data_in[23:16]),
.DIP (dip[2]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam ram2.INIT_00 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_01 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_02 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_03 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_04 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_05 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_06 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_07 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_08 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_09 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_0A = 256'h00000000000000000000000000000000;
defparam ram2.INIT_0B = 256'h00000000000000000000000000000000;
defparam ram2.INIT_0C = 256'h00000000000000000000000000000000;
defparam ram2.INIT_0D = 256'h00000000000000000000000000000000;
defparam ram2.INIT_0E = 256'h00000000000000000000000000000000;
defparam ram2.INIT_0F = 256'h00000000000000000000000000000000;
defparam ram2.INIT_10 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_11 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_12 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_13 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_14 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_15 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_16 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_17 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_18 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_19 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_1A = 256'h00000000000000000000000000000000;
defparam ram2.INIT_1B = 256'h00000000000000000000000000000000;
defparam ram2.INIT_1C = 256'h00000000000000000000000000000000;
defparam ram2.INIT_1D = 256'h00000000000000000000000000000000;
defparam ram2.INIT_1E = 256'h00000000000000000000000000000000;
defparam ram2.INIT_1F = 256'h00000000000000000000000000000000;
defparam ram2.INIT_20 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_21 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_22 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_23 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_24 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_25 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_26 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_27 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_28 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_29 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_2A = 256'h00000000000000000000000000000000;
defparam ram2.INIT_2B = 256'h00000000000000000000000000000000;
defparam ram2.INIT_2C = 256'h00000000000000000000000000000000;
defparam ram2.INIT_2D = 256'h00000000000000000000000000000000;
defparam ram2.INIT_2E = 256'h00000000000000000000000000000000;
defparam ram2.INIT_2F = 256'h00000000000000000000000000000000;
defparam ram2.INIT_30 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_31 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_32 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_33 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_34 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_35 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_36 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_37 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_38 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_39 = 256'h00000000000000000000000000000000;
defparam ram2.INIT_3A = 256'h00000000000000000000000000000000;
defparam ram2.INIT_3B = 256'h00000000000000000000000000000000;
defparam ram2.INIT_3C = 256'h00000000000000000000000000000000;
defparam ram2.INIT_3D = 256'h00000000000000000000000000000000;
defparam ram2.INIT_3E = 256'h00000000000000000000000000000000;
defparam ram2.INIT_3F = 256'h00000000000000000000000000000000;
RAMB16_S9 ram3(
.DO (data_out[31:24]),
.DOP (),
.ADDR (addr[12:2]),
.CLK (clk),
.DI (data_in[31:24]),
.DIP (dip[3]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam ram3.INIT_00 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_01 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_02 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_03 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_04 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_05 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_06 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_07 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_08 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_09 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_0A = 256'h00000000000000000000000000000000;
defparam ram3.INIT_0B = 256'h00000000000000000000000000000000;
defparam ram3.INIT_0C = 256'h00000000000000000000000000000000;
defparam ram3.INIT_0D = 256'h00000000000000000000000000000000;
defparam ram3.INIT_0E = 256'h00000000000000000000000000000000;
defparam ram3.INIT_0F = 256'h00000000000000000000000000000000;
defparam ram3.INIT_10 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_11 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_12 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_13 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_14 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_15 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_16 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_17 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_18 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_19 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_1A = 256'h00000000000000000000000000000000;
defparam ram3.INIT_1B = 256'h00000000000000000000000000000000;
defparam ram3.INIT_1C = 256'h00000000000000000000000000000000;
defparam ram3.INIT_1D = 256'h00000000000000000000000000000000;
defparam ram3.INIT_1E = 256'h00000000000000000000000000000000;
defparam ram3.INIT_1F = 256'h00000000000000000000000000000000;
defparam ram3.INIT_20 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_21 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_22 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_23 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_24 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_25 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_26 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_27 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_28 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_29 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_2A = 256'h00000000000000000000000000000000;
defparam ram3.INIT_2B = 256'h00000000000000000000000000000000;
defparam ram3.INIT_2C = 256'h00000000000000000000000000000000;
defparam ram3.INIT_2D = 256'h00000000000000000000000000000000;
defparam ram3.INIT_2E = 256'h00000000000000000000000000000000;
defparam ram3.INIT_2F = 256'h00000000000000000000000000000000;
defparam ram3.INIT_30 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_31 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_32 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_33 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_34 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_35 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_36 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_37 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_38 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_39 = 256'h00000000000000000000000000000000;
defparam ram3.INIT_3A = 256'h00000000000000000000000000000000;
defparam ram3.INIT_3B = 256'h00000000000000000000000000000000;
defparam ram3.INIT_3C = 256'h00000000000000000000000000000000;
defparam ram3.INIT_3D = 256'h00000000000000000000000000000000;
defparam ram3.INIT_3E = 256'h00000000000000000000000000000000;
defparam ram3.INIT_3F = 256'h00000000000000000000000000000000;
endmodule
|
module etx(/*AUTOARG*/
// Outputs
tx_active, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
txo_data_p, txo_data_n, cclk_p, cclk_n, chip_resetb, txrd_wait,
txwr_wait, txrr_wait, etx_cfg_access, etx_cfg_packet, etx_reset,
tx_lclk_div4,
// Inputs
sys_reset, soft_reset, sys_clk, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, txrd_access, txrd_packet,
txwr_access, txwr_packet, txrr_access, txrr_packet, etx_cfg_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1;
//Reset and clocks
input sys_reset; // reset for fifos
input soft_reset; // software controlled reset
//Clocks
input sys_clk; // clock for fifos
//TX boot done
output tx_active; // tx ready to transmit
//Transmit signals for IO
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx async write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx async read pushback
//Epiphany Chip Signals
output cclk_p,cclk_n;
output chip_resetb;
//Read Request Channel Input
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Write Channel Input
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Response Channel Input
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Configuration Interface (for ERX)
output etx_cfg_access;
output [PW-1:0] etx_cfg_packet;
output etx_reset;
output tx_lclk_div4;
input etx_cfg_wait;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire tx_lclk; // From etx_clocks of etx_clocks.v
wire tx_lclk90; // From etx_clocks of etx_clocks.v
// End of automatics
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire tx_access; // From etx_core of etx_core.v
wire tx_burst; // From etx_core of etx_core.v
wire tx_io_wait; // From etx_io of etx_io.v
wire [PW-1:0] tx_packet; // From etx_core of etx_core.v
wire tx_rd_wait; // From etx_io of etx_io.v
wire tx_wr_wait; // From etx_io of etx_io.v
wire txrd_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txrd_fifo_packet; // From etx_fifo of etx_fifo.v
wire txrd_fifo_wait; // From etx_core of etx_core.v
wire txrr_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txrr_fifo_packet; // From etx_fifo of etx_fifo.v
wire txrr_fifo_wait; // From etx_core of etx_core.v
wire txwr_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txwr_fifo_packet; // From etx_fifo of etx_fifo.v
wire txwr_fifo_wait; // From etx_core of etx_core.v
/************************************************************/
/*Clocks */
/************************************************************/
etx_clocks etx_clocks (
.etx_io_reset (etx_io_reset),
/*AUTOINST*/
// Outputs
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.etx_reset (etx_reset),
.chip_resetb (chip_resetb),
.tx_active (tx_active),
// Inputs
.sys_reset (sys_reset),
.soft_reset (soft_reset),
.sys_clk (sys_clk));
/************************************************************/
/*FIFOs */
/************************************************************/
etx_fifo etx_fifo (/*AUTOINST*/
// Outputs
.txrd_wait (txrd_wait),
.txwr_wait (txwr_wait),
.txrr_wait (txrr_wait),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.txrd_fifo_access (txrd_fifo_access),
.txrd_fifo_packet (txrd_fifo_packet[PW-1:0]),
.txrr_fifo_access (txrr_fifo_access),
.txrr_fifo_packet (txrr_fifo_packet[PW-1:0]),
.txwr_fifo_access (txwr_fifo_access),
.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
// Inputs
.etx_reset (etx_reset),
.sys_reset (sys_reset),
.sys_clk (sys_clk),
.tx_lclk_div4 (tx_lclk_div4),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.etx_cfg_wait (etx_cfg_wait),
.txrd_fifo_wait (txrd_fifo_wait),
.txrr_fifo_wait (txrr_fifo_wait),
.txwr_fifo_wait (txwr_fifo_wait));
/***********************************************************/
/*ELINK CORE LOGIC */
/***********************************************************/
/*etx_core AUTO_TEMPLATE ( .tx_access (tx_access),
.tx_burst (tx_burst),
.tx_io_wait (tx_io_wait),
.tx_rd_wait (tx_rd_wait),
.tx_wr_wait (tx_wr_wait),
.tx_packet (tx_packet[PW-1:0]),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.etx_cfg_wait (etx_cfg_wait),
.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
.\(.*\)_access (\1_fifo_access),
.\(.*\)_wait (\1_fifo_wait),
);
*/
defparam etx_core.ID=ID;
etx_core etx_core (.clk (tx_lclk_div4),
.reset (etx_reset),
/*AUTOINST*/
// Outputs
.tx_access (tx_access), // Templated
.tx_burst (tx_burst), // Templated
.tx_packet (tx_packet[PW-1:0]), // Templated
.txrd_wait (txrd_fifo_wait), // Templated
.txrr_wait (txrr_fifo_wait), // Templated
.txwr_wait (txwr_fifo_wait), // Templated
.etx_cfg_access (etx_cfg_access), // Templated
.etx_cfg_packet (etx_cfg_packet[PW-1:0]), // Templated
// Inputs
.tx_io_wait (tx_io_wait), // Templated
.tx_rd_wait (tx_rd_wait), // Templated
.tx_wr_wait (tx_wr_wait), // Templated
.txrd_access (txrd_fifo_access), // Templated
.txrd_packet (txrd_fifo_packet[PW-1:0]), // Templated
.txrr_access (txrr_fifo_access), // Templated
.txrr_packet (txrr_fifo_packet[PW-1:0]), // Templated
.txwr_access (txwr_fifo_access), // Templated
.txwr_packet (txwr_fifo_packet[PW-1:0]), // Templated
.etx_cfg_wait (etx_cfg_wait)); // Templated
/***********************************************************/
/*TRANSMIT I/O LOGIC */
/***********************************************************/
defparam etx_io.IOSTD_ELINK=IOSTD_ELINK;
etx_io etx_io (.reset (etx_io_reset),
/*AUTOINST*/
// Outputs
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.tx_io_wait (tx_io_wait),
.tx_wr_wait (tx_wr_wait),
.tx_rd_wait (tx_rd_wait),
// Inputs
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.tx_packet (tx_packet[PW-1:0]),
.tx_access (tx_access),
.tx_burst (tx_burst));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] in;
wire a,y,y_fixed;
wire b = in[0];
wire en = in[1];
pullup(a);
ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) );
initial in=0;
// Test loop
always @ (posedge clk) begin
in <= in + 1;
$display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed);
if (en) begin
// driving b
// a should be b
// y and yfix should also be b
if (a!=b || y != b || y_fixed != b) begin
$display ( "Expected a %d y %b yfix %b" , a, y, y_fixed);
$stop;
end
end else begin
// not driving b
// a should be 1 (pullup)
// y and yfix shold be 1
if (a!=1 || y != 1 || y_fixed != 1) begin
$display( "Expected a,y,yfix == 1");
$stop;
end
end
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module ChildA(inout A, input B, input en, output Y, output Yfix);
// workaround
wire a_in = A;
ChildB childB(.A(A), .Y(Y));
assign A = en ? B : 1'bz;
ChildB childBfix(.A(a_in),.Y(Yfix));
endmodule
module ChildB(input A, output Y);
assign Y = A;
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Wishbone master interface port buffer //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// This is a sub-module of the Amber wishbone master //
// interface. The wishbone master interface connects a number //
// of internal amber ports to the wishbone bus. The ports //
// are; //
// instruction cache read accesses //
// data cache read and write accesses (cached) //
// data cache read and write accesses (uncached) //
// //
// The buffer module buffers a single port. For write //
// requests, this allows the processor core to continue //
// executing withont having to wait for the wishbone write //
// operation to complete. //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2011 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a25_wishbone_buf (
input i_clk,
// Core side
input i_req,
input i_write,
input [127:0] i_wdata,
input [15:0] i_be,
input [31:0] i_addr,
output [127:0] o_rdata,
output o_ack,
// Wishbone side
output o_valid,
input i_accepted,
output o_write,
output [127:0] o_wdata,
output [15:0] o_be,
output [31:0] o_addr,
input [127:0] i_rdata,
input i_rdata_valid
);
// ----------------------------------------------------
// Signals
// ----------------------------------------------------
reg [1:0] wbuf_used_r = 'd0;
reg [127:0] wbuf_wdata_r [1:0];
reg [31:0] wbuf_addr_r [1:0];
reg [15:0] wbuf_be_r [1:0];
reg [1:0] wbuf_write_r = 'd0;
reg wbuf_wp_r = 'd0; // write buf write pointer
reg wbuf_rp_r = 'd0; // write buf read pointer
reg busy_reading_r = 'd0;
reg wait_rdata_valid_r = 'd0;
wire in_wreq;
reg ack_owed_r = 'd0;
// ----------------------------------------------------
// Access Buffer
// ----------------------------------------------------
assign in_wreq = i_req && i_write;
assign push = i_req && !busy_reading_r && (wbuf_used_r == 2'd1 || (wbuf_used_r == 2'd0 && !i_accepted));
assign pop = o_valid && i_accepted && wbuf_used_r != 2'd0;
always @(posedge i_clk)
if (push && pop)
wbuf_used_r <= wbuf_used_r;
else if (push)
wbuf_used_r <= wbuf_used_r + 1'd1;
else if (pop)
wbuf_used_r <= wbuf_used_r - 1'd1;
always @(posedge i_clk)
if (push && in_wreq && !o_ack)
ack_owed_r = 1'd1;
else if (!i_req && o_ack)
ack_owed_r = 1'd0;
always @(posedge i_clk)
if (push)
begin
wbuf_wdata_r [wbuf_wp_r] <= i_wdata;
wbuf_addr_r [wbuf_wp_r] <= i_addr;
wbuf_be_r [wbuf_wp_r] <= i_write ? i_be : 16'hffff;
wbuf_write_r [wbuf_wp_r] <= i_write;
wbuf_wp_r <= !wbuf_wp_r;
end
always @(posedge i_clk)
if (pop)
wbuf_rp_r <= !wbuf_rp_r;
// ----------------------------------------------------
// Output logic
// ----------------------------------------------------
assign o_wdata = wbuf_used_r != 2'd0 ? wbuf_wdata_r[wbuf_rp_r] : i_wdata;
assign o_write = wbuf_used_r != 2'd0 ? wbuf_write_r[wbuf_rp_r] : i_write;
assign o_addr = wbuf_used_r != 2'd0 ? wbuf_addr_r [wbuf_rp_r] : i_addr;
assign o_be = wbuf_used_r != 2'd0 ? wbuf_be_r [wbuf_rp_r] : i_write ? i_be : 16'hffff;
assign o_ack = (in_wreq ? (wbuf_used_r == 2'd0) : i_rdata_valid) || (ack_owed_r && pop);
assign o_valid = (wbuf_used_r != 2'd0 || i_req) && !wait_rdata_valid_r;
assign o_rdata = i_rdata;
always@(posedge i_clk)
if (o_valid && !o_write)
busy_reading_r <= 1'd1;
else if (i_rdata_valid)
busy_reading_r <= 1'd0;
always@(posedge i_clk)
if (o_valid && !o_write && i_accepted)
wait_rdata_valid_r <= 1'd1;
else if (i_rdata_valid)
wait_rdata_valid_r <= 1'd0;
endmodule
|
//-----------------------------------------------------------------------------
//-- Divisor de frecuencia generico
//-- (c) BQ. August 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "divider.vh"
//-- Entrada: clk_in. Señal original
//-- Salida: clk_out. Señal de frecuencia 1/M de la original
module divider(input wire clk_in, output wire clk_out);
//-- Valor por defecto del divisor
//-- Lo ponemos a 1 Hz
parameter M = `F_2KHz;
//-- Numero de bits para almacenar el divisor
//-- Se calculan con la funcion de verilog $clog2, que nos devuelve el
//-- numero de bits necesarios para representar el numero M
//-- Es un parametro local, que no se puede modificar al instanciar
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk_in)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
//-- Sacar el bit mas significativo por clk_out
assign clk_out = divcounter[N-1];
endmodule
//-- Contador módulo M: Otra manera de implementarlo
/*
always @(posedge clk_in)
if (divcounter == M - 1)
divcounter <= 0;
else
divcounter <= divcounter + 1;
*/
|
// CONFIG:
// NUM_COEFF = 11
// PIPLINED = 1
// WARNING: more than enough COEFFICIENTS in array (there are 26, and we only need 6)
module fir (
clk,
reset,
clk_ena,
i_valid,
i_in,
o_valid,
o_out
);
// Data Width
parameter dw = 18; //Data input/output bits
// Number of filter coefficients
parameter N = 11;
parameter N_UNIQ = 6; // ciel(N/2) assuming symmetric filter coefficients
//Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers
localparam N_VALID_REGS = 16;
input clk;
input reset;
input clk_ena;
input i_valid;
input [dw-1:0] i_in; // signed
output o_valid;
output [dw-1:0] o_out; // signed
// Data Width dervied parameters
localparam dw_add_int = 18; //Internal adder precision bits
localparam dw_mult_int = 36; //Internal multiplier precision bits
localparam scale_factor = 17; //Multiplier normalization shift amount
// Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders
localparam N_INPUT_REGS = 11;
// Debug
// initial begin
// $display ("Data Width: %d", dw);
// $display ("Data Width Add Internal: %d", dw_add_int);
// $display ("Data Width Mult Internal: %d", dw_mult_int);
// $display ("Scale Factor: %d", scale_factor);
// end
reg [dw-1:0] COEFFICIENT_0;
reg [dw-1:0] COEFFICIENT_1;
reg [dw-1:0] COEFFICIENT_2;
reg [dw-1:0] COEFFICIENT_3;
reg [dw-1:0] COEFFICIENT_4;
reg [dw-1:0] COEFFICIENT_5;
always@(posedge clk) begin
COEFFICIENT_0 <= 18'd88;
COEFFICIENT_1 <= 18'd0;
COEFFICIENT_2 <= -18'd97;
COEFFICIENT_3 <= -18'd197;
COEFFICIENT_4 <= -18'd294;
COEFFICIENT_5 <= -18'd380;
end
////******************************************************
// *
// * Valid Delay Pipeline
// *
// *****************************************************
//Input valid signal is pipelined to become output valid signal
//Valid registers
reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS;
always@(posedge clk or posedge reset) begin
if(reset) begin
VALID_PIPELINE_REGS <= 0;
end else begin
if(clk_ena) begin
VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid};
end else begin
VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS;
end
end
end
////******************************************************
// *
// * Input Register Pipeline
// *
// *****************************************************
//Pipelined input values
//Input value registers
wire [dw-1:0] INPUT_PIPELINE_REG_0;
wire [dw-1:0] INPUT_PIPELINE_REG_1;
wire [dw-1:0] INPUT_PIPELINE_REG_2;
wire [dw-1:0] INPUT_PIPELINE_REG_3;
wire [dw-1:0] INPUT_PIPELINE_REG_4;
wire [dw-1:0] INPUT_PIPELINE_REG_5;
wire [dw-1:0] INPUT_PIPELINE_REG_6;
wire [dw-1:0] INPUT_PIPELINE_REG_7;
wire [dw-1:0] INPUT_PIPELINE_REG_8;
wire [dw-1:0] INPUT_PIPELINE_REG_9;
wire [dw-1:0] INPUT_PIPELINE_REG_10;
input_pipeline in_pipe(
.clk(clk), .clk_ena(clk_ena),
.in_stream(i_in),
.pipeline_reg_0(INPUT_PIPELINE_REG_0),
.pipeline_reg_1(INPUT_PIPELINE_REG_1),
.pipeline_reg_2(INPUT_PIPELINE_REG_2),
.pipeline_reg_3(INPUT_PIPELINE_REG_3),
.pipeline_reg_4(INPUT_PIPELINE_REG_4),
.pipeline_reg_5(INPUT_PIPELINE_REG_5),
.pipeline_reg_6(INPUT_PIPELINE_REG_6),
.pipeline_reg_7(INPUT_PIPELINE_REG_7),
.pipeline_reg_8(INPUT_PIPELINE_REG_8),
.pipeline_reg_9(INPUT_PIPELINE_REG_9),
.pipeline_reg_10(INPUT_PIPELINE_REG_10),
.reset(reset) );
defparam in_pipe.WIDTH = 18; // = dw
////******************************************************
// *
// * Computation Pipeline
// *
// *****************************************************
// ************************* LEVEL 0 ************************* \\
wire [dw-1:0] L0_output_wires_0;
wire [dw-1:0] L0_output_wires_1;
wire [dw-1:0] L0_output_wires_2;
wire [dw-1:0] L0_output_wires_3;
wire [dw-1:0] L0_output_wires_4;
wire [dw-1:0] L0_output_wires_5;
adder_with_1_reg L0_adder_0and10(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_0),
.datab (INPUT_PIPELINE_REG_10),
.result(L0_output_wires_0)
);
adder_with_1_reg L0_adder_1and9(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_1),
.datab (INPUT_PIPELINE_REG_9),
.result(L0_output_wires_1)
);
adder_with_1_reg L0_adder_2and8(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_2),
.datab (INPUT_PIPELINE_REG_8),
.result(L0_output_wires_2)
);
adder_with_1_reg L0_adder_3and7(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_3),
.datab (INPUT_PIPELINE_REG_7),
.result(L0_output_wires_3)
);
adder_with_1_reg L0_adder_4and6(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_4),
.datab (INPUT_PIPELINE_REG_6),
.result(L0_output_wires_4)
);
// (5 main tree Adders)
// ********* Byes ******** \\
one_register L0_byereg_for_5(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_5),
.result(L0_output_wires_5)
);
// (1 byes)
// ************************* LEVEL 1 ************************* \\
// **************** Multipliers **************** \\
wire [dw-1:0] L1_mult_wires_0;
wire [dw-1:0] L1_mult_wires_1;
wire [dw-1:0] L1_mult_wires_2;
wire [dw-1:0] L1_mult_wires_3;
wire [dw-1:0] L1_mult_wires_4;
wire [dw-1:0] L1_mult_wires_5;
multiplier_with_reg L1_mul_0(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_0),
.datab (COEFFICIENT_0),
.result(L1_mult_wires_0)
);
multiplier_with_reg L1_mul_1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_1),
.datab (COEFFICIENT_1),
.result(L1_mult_wires_1)
);
multiplier_with_reg L1_mul_2(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_2),
.datab (COEFFICIENT_2),
.result(L1_mult_wires_2)
);
multiplier_with_reg L1_mul_3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_3),
.datab (COEFFICIENT_3),
.result(L1_mult_wires_3)
);
multiplier_with_reg L1_mul_4(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_4),
.datab (COEFFICIENT_4),
.result(L1_mult_wires_4)
);
multiplier_with_reg L1_mul_5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_5),
.datab (COEFFICIENT_5),
.result(L1_mult_wires_5)
);
// (6 Multipliers)
// **************** Adders **************** \\
wire [dw-1:0] L1_output_wires_0;
wire [dw-1:0] L1_output_wires_1;
wire [dw-1:0] L1_output_wires_2;
adder_with_1_reg L1_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_0),
.datab (L1_mult_wires_1),
.result(L1_output_wires_0)
);
adder_with_1_reg L1_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_2),
.datab (L1_mult_wires_3),
.result(L1_output_wires_1)
);
adder_with_1_reg L1_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_4),
.datab (L1_mult_wires_5),
.result(L1_output_wires_2)
);
// (3 main tree Adders)
// ************************* LEVEL 2 ************************* \\
wire [dw-1:0] L2_output_wires_0;
wire [dw-1:0] L2_output_wires_1;
adder_with_1_reg L2_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_0),
.datab (L1_output_wires_1),
.result(L2_output_wires_0)
);
// (1 main tree Adders)
// ********* Byes ******** \\
one_register L2_byereg_for_2(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_2),
.result(L2_output_wires_1)
);
// (1 byes)
// ************************* LEVEL 3 ************************* \\
wire [dw-1:0] L3_output_wires_0;
adder_with_1_reg L3_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_0),
.datab (L2_output_wires_1),
.result(L3_output_wires_0)
);
// (1 main tree Adders)
////******************************************************
// *
// * Output Logic
// *
// *****************************************************
//Actual outputs
assign o_out = L3_output_wires_0;
assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1];
endmodule
module input_pipeline (
clk,
clk_ena,
in_stream,
pipeline_reg_0,
pipeline_reg_1,
pipeline_reg_2,
pipeline_reg_3,
pipeline_reg_4,
pipeline_reg_5,
pipeline_reg_6,
pipeline_reg_7,
pipeline_reg_8,
pipeline_reg_9,
pipeline_reg_10,
reset);
parameter WIDTH = 1;
//Input value registers
input clk;
input clk_ena;
input [WIDTH-1:0] in_stream;
output [WIDTH-1:0] pipeline_reg_0;
output [WIDTH-1:0] pipeline_reg_1;
output [WIDTH-1:0] pipeline_reg_2;
output [WIDTH-1:0] pipeline_reg_3;
output [WIDTH-1:0] pipeline_reg_4;
output [WIDTH-1:0] pipeline_reg_5;
output [WIDTH-1:0] pipeline_reg_6;
output [WIDTH-1:0] pipeline_reg_7;
output [WIDTH-1:0] pipeline_reg_8;
output [WIDTH-1:0] pipeline_reg_9;
output [WIDTH-1:0] pipeline_reg_10;
reg [WIDTH-1:0] pipeline_reg_0;
reg [WIDTH-1:0] pipeline_reg_1;
reg [WIDTH-1:0] pipeline_reg_2;
reg [WIDTH-1:0] pipeline_reg_3;
reg [WIDTH-1:0] pipeline_reg_4;
reg [WIDTH-1:0] pipeline_reg_5;
reg [WIDTH-1:0] pipeline_reg_6;
reg [WIDTH-1:0] pipeline_reg_7;
reg [WIDTH-1:0] pipeline_reg_8;
reg [WIDTH-1:0] pipeline_reg_9;
reg [WIDTH-1:0] pipeline_reg_10;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
pipeline_reg_0 <= 0;
pipeline_reg_1 <= 0;
pipeline_reg_2 <= 0;
pipeline_reg_3 <= 0;
pipeline_reg_4 <= 0;
pipeline_reg_5 <= 0;
pipeline_reg_6 <= 0;
pipeline_reg_7 <= 0;
pipeline_reg_8 <= 0;
pipeline_reg_9 <= 0;
pipeline_reg_10 <= 0;
end else begin
if(clk_ena) begin
pipeline_reg_0 <= in_stream;
pipeline_reg_1 <= pipeline_reg_0;
pipeline_reg_2 <= pipeline_reg_1;
pipeline_reg_3 <= pipeline_reg_2;
pipeline_reg_4 <= pipeline_reg_3;
pipeline_reg_5 <= pipeline_reg_4;
pipeline_reg_6 <= pipeline_reg_5;
pipeline_reg_7 <= pipeline_reg_6;
pipeline_reg_8 <= pipeline_reg_7;
pipeline_reg_9 <= pipeline_reg_8;
pipeline_reg_10 <= pipeline_reg_9;
end //else begin
//pipeline_reg_0 <= pipeline_reg_0;
//pipeline_reg_1 <= pipeline_reg_1;
//pipeline_reg_2 <= pipeline_reg_2;
//pipeline_reg_3 <= pipeline_reg_3;
//pipeline_reg_4 <= pipeline_reg_4;
//pipeline_reg_5 <= pipeline_reg_5;
//pipeline_reg_6 <= pipeline_reg_6;
//pipeline_reg_7 <= pipeline_reg_7;
//pipeline_reg_8 <= pipeline_reg_8;
//pipeline_reg_9 <= pipeline_reg_9;
//pipeline_reg_10 <= pipeline_reg_10;
//end
end
end
endmodule
module adder_with_1_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa + datab;
end
end
endmodule
module multiplier_with_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa * datab;
end
end
endmodule
module one_register (
clk,
clk_ena,
dataa,
result);
input clk;
input clk_ena;
input [17:0] dataa;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa;
end
end
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT2____25.000______0.000______50.0______175.402_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (40),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));
endmodule
|
// niosii_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "alu.syn.v"
`include "control.h"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/alu.sdf",a_l_u,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
r_A=128'h0102030405060708f00a0b0cff0eff00;
r_B=128'h01010202030303031004f505ff09fe10;
e_r=128'h00010006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module FIFO_image_filter_src1_data_stream_2_V
#(parameter
MEM_STYLE = "block",
DATA_WIDTH = 8,
ADDR_WIDTH = 15,
DEPTH = 20000
)
(
// system signal
input wire clk,
input wire reset,
// write
output wire if_full_n,
input wire if_write_ce,
input wire if_write,
input wire [DATA_WIDTH-1:0] if_din,
// read
output wire if_empty_n,
input wire if_read_ce,
input wire if_read,
output wire [DATA_WIDTH-1:0] if_dout
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
(* ram_style = MEM_STYLE *)
reg [DATA_WIDTH-1:0] mem[0:DEPTH-1];
reg [DATA_WIDTH-1:0] q_buf = 1'b0;
reg [ADDR_WIDTH-1:0] waddr = 1'b0;
reg [ADDR_WIDTH-1:0] raddr = 1'b0;
wire [ADDR_WIDTH-1:0] wnext;
wire [ADDR_WIDTH-1:0] rnext;
wire push;
wire pop;
reg [ADDR_WIDTH-1:0] usedw = 1'b0;
reg full_n = 1'b1;
reg empty_n = 1'b0;
reg [DATA_WIDTH-1:0] q_tmp = 1'b0;
reg show_ahead = 1'b0;
reg [DATA_WIDTH-1:0] dout_buf = 1'b0;
reg dout_valid = 1'b0;
//------------------------Instantiation------------------
//------------------------Task and function--------------
//------------------------Body---------------------------
assign if_full_n = full_n;
assign if_empty_n = dout_valid;
assign if_dout = dout_buf;
assign push = full_n & if_write_ce & if_write;
assign pop = empty_n & if_read_ce & (~dout_valid | if_read);
assign wnext = !push ? waddr :
(waddr == DEPTH - 1) ? 1'b0 :
waddr + 1'b1;
assign rnext = !pop ? raddr :
(raddr == DEPTH - 1) ? 1'b0 :
raddr + 1'b1;
// waddr
always @(posedge clk) begin
if (reset == 1'b1)
waddr <= 1'b0;
else
waddr <= wnext;
end
// raddr
always @(posedge clk) begin
if (reset == 1'b1)
raddr <= 1'b0;
else
raddr <= rnext;
end
// usedw
always @(posedge clk) begin
if (reset == 1'b1)
usedw <= 1'b0;
else if (push & ~pop)
usedw <= usedw + 1'b1;
else if (~push & pop)
usedw <= usedw - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1)
full_n <= 1'b1;
else if (push & ~pop)
full_n <= (usedw != DEPTH - 1);
else if (~push & pop)
full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1)
empty_n <= 1'b0;
else if (push & ~pop)
empty_n <= 1'b1;
else if (~push & pop)
empty_n <= (usedw != 1'b1);
end
// mem
always @(posedge clk) begin
if (push)
mem[waddr] <= if_din;
end
// q_buf
always @(posedge clk) begin
q_buf <= mem[rnext];
end
// q_tmp
always @(posedge clk) begin
if (reset == 1'b1)
q_tmp <= 1'b0;
else if (push)
q_tmp <= if_din;
end
// show_ahead
always @(posedge clk) begin
if (reset == 1'b1)
show_ahead <= 1'b0;
else if (push && usedw == pop)
show_ahead <= 1'b1;
else
show_ahead <= 1'b0;
end
// dout_buf
always @(posedge clk) begin
if (reset == 1'b1)
dout_buf <= 1'b0;
else if (pop)
dout_buf <= show_ahead? q_tmp : q_buf;
end
// dout_valid
always @(posedge clk) begin
if (reset == 1'b1)
dout_valid <= 1'b0;
else if (pop)
dout_valid <= 1'b1;
else if (if_read_ce & if_read)
dout_valid <= 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A31OI_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31oi (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_TB_V
`define SKY130_FD_SC_LP__O32A_TB_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o32a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_TB_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:43:33 09/07/2013
// Design Name: synchronizer
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab2/laboratorio2/test_synchronizer.v
// Project Name: laboratorio2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: synchronizer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_synchronizer;
// Inputs
reg clk;
reg rst;
reg sensor;
reg reprogram;
reg walk_btn;
// Outputs
wire rst_out;
wire sensor_out;
wire walk_register;
wire reprogram_out;
// Instantiate the Unit Under Test (UUT)
synchronizer uut (
.clk(clk),
.rst(rst),
.sensor(sensor),
.reprogram(reprogram),
.walk_btn(walk_btn),
.rst_out(rst_out),
.sensor_out(sensor_out),
.walk_register(walk_register),
.reprogram_out(reprogram_out)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
sensor = 0;
reprogram = 0;
walk_btn = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
//--------------------------------------------------------------------------
// --
// OneWireMaster --
// A synthesizable 1-wire master peripheral --
// Copyright 1999-2005 Dallas Semiconductor Corporation --
// --
//--------------------------------------------------------------------------
// --
// Purpose: Provides timing and control of Dallas 1-wire bus --
// through a memory-mapped peripheral --
// File: OWM.v --
// Date: February 1, 2005 --
// Version: v2.100 --
// Authors: Rick Downs and Charles Hill, --
// Dallas Semiconductor Corporation --
// --
// Note: This source code is available for use without license. --
// Dallas Semiconductor is not responsible for the --
// functionality or utility of this product. --
// --
// Rev: Added Overdrive, Bit control, and strong pullup control --
// along with many other features described in the new spec --
// released version 2.0 9/5/01 - Greg Glennon --
// Significant changes to improve synthesis - English --
// Ported to Verilog - Sandelin --
//--------------------------------------------------------------------------
module OWM (
ADDRESS, ADS_bar, CLK, EN_bar, MR, RD_bar, WR_bar, /*DDIR, DOUT,*/ INTR,
STPZ, DATA_IN, DATA_OUT,
DQ0_T, DQ1_T, DQ2_T, DQ3_T, DQ4_T, DQ5_T, DQ6_T, DQ7_T,
DQ0_O, DQ1_O, DQ2_O, DQ3_O, DQ4_O, DQ5_O, DQ6_O, DQ7_O,
DQ0_I, DQ1_I, DQ2_I, DQ3_I, DQ4_I, DQ5_I, DQ6_I, DQ7_I);
input [2:0] ADDRESS; // SFR address
input ADS_bar; // address latch control (active low)
input CLK; // system clock
input EN_bar; // SFR access enable (active low)
input MR; // master reset
input RD_bar; // SFR read (active low)
input WR_bar; // SFR write (active low)
//output DDIR;
//output [7:0] DOUT;
output INTR; // one wire master interrupt
output STPZ; // strong pullup (active low)
input [7:0] DATA_IN; // input DATA bus
output [7:0] DATA_OUT; // output DATA bus
output DQ0_T;
output DQ1_T;
output DQ2_T;
output DQ3_T;
output DQ4_T;
output DQ5_T;
output DQ6_T;
output DQ7_T;
output DQ0_O;
output DQ1_O;
output DQ2_O;
output DQ3_O;
output DQ4_O;
output DQ5_O;
output DQ6_O;
output DQ7_O;
input DQ0_I;
input DQ1_I;
input DQ2_I;
input DQ3_I;
input DQ4_I;
input DQ5_I;
input DQ6_I;
input DQ7_I;
wire [2:0] dq_sel;
wire [7:0] DIN;
wire [7:0] DOUT;
wire [7:0] rcvr_buffer;
wire [7:0] xmit_buffer;
wire [2:0] ADDRESS;
wire clk_1us;
one_wire_io xone_wire_io
(
.CLK(CLK),
.DDIR(DDIR),
.DOUT(DOUT),
.DQ_CONTROL(DQ_CONTROL),
.MR(MR),
.DIN(DIN),
.DQ_IN(DQ_IN),
.DATA_IN(DATA_IN),
.DATA_OUT(DATA_OUT),
.DQ0_T(DQ0_T),
.DQ0_O(DQ0_O),
.DQ0_I(DQ0_I),
.DQ1_T(DQ1_T),
.DQ1_O(DQ1_O),
.DQ1_I(DQ1_I),
.DQ2_T(DQ2_T),
.DQ2_O(DQ2_O),
.DQ2_I(DQ2_I),
.DQ3_T(DQ3_T),
.DQ3_O(DQ3_O),
.DQ3_I(DQ3_I),
.DQ4_T(DQ4_T),
.DQ4_O(DQ4_O),
.DQ4_I(DQ4_I),
.DQ5_T(DQ5_T),
.DQ5_O(DQ5_O),
.DQ5_I(DQ5_I),
.DQ6_T(DQ6_T),
.DQ6_O(DQ6_O),
.DQ6_I(DQ6_I),
.DQ7_T(DQ7_T),
.DQ7_O(DQ7_O),
.DQ7_I(DQ7_I),
.DQ_SEL(dq_sel)
);
clk_prescaler xclk_prescaler
(
.CLK(CLK),
.CLK_EN(CLK_EN),
.div_1(div_1),
.div_2(div_2),
.div_3(div_3),
.MR(MR),
.pre_0(pre_0),
.pre_1(pre_1),
.clk_1us(clk_1us)
);
one_wire_interface xone_wire_interface
(
.ADDRESS(ADDRESS),
.ADS_bar(ADS_bar),
.clear_interrupts(clear_interrupts),
.DIN(DIN),
.DQ_IN(DQ_IN),
.EN_bar(EN_bar),
.FSM_CLK(FSM_CLK),
.MR(MR),
.OneWireIO_eq_Load(OneWireIO_eq_Load),
.pdr(pdr),
.OW_LOW(OW_LOW),
.OW_SHORT(OW_SHORT),
.rbf(rbf),
.rcvr_buffer(rcvr_buffer),
.RD_bar(RD_bar),
.reset_owr(reset_owr),
.rsrf(rsrf),
.temt(temt),
.WR_bar(WR_bar),
.BIT_CTL(BIT_CTL),
.CLK_EN(CLK_EN),
.clr_activate_intr(clr_activate_intr),
.DDIR(DDIR),
.div_1(div_1),
.div_2(div_2),
.div_3(div_3),
.DOUT(DOUT),
.EN_FOW(EN_FOW),
.EOWL(EOWL),
.EOWSH(EOWSH),
.epd(epd),
.erbf(erbf),
.ersf(ersf),
.etbe(etbe),
.etmt(etmt),
.FOW(FOW),
.ias(ias),
.LLM(LLM),
.OD(OD),
.owr(owr),
.pd(pd),
.PPM(PPM),
.pre_0(pre_0),
.pre_1(pre_1),
.rbf_reset(rbf_reset),
.sr_a(sr_a),
.STP_SPLY(STP_SPLY),
.STPEN(STPEN),
.tbe(tbe),
.xmit_buffer(xmit_buffer),
.dq_sel(dq_sel)
);
onewiremaster xonewiremaster(
.BIT_CTL(BIT_CTL),
.clk(CLK),
.clk_1us_en(clk_1us),
.clr_activate_intr(clr_activate_intr),
.DQ_IN(DQ_IN),
.EN_FOW(EN_FOW),
.EOWL(EOWL),
.EOWSH(EOWSH),
.epd(epd),
.erbf(erbf),
.ersf(ersf),
.etbe(etbe),
.etmt(etmt),
.FOW(FOW),
.ias(ias),
.LLM(LLM),
.MR(MR),
.OD(OD),
.owr(owr),
.pd(pd),
.PPM(PPM),
.rbf_reset(rbf_reset),
.sr_a(sr_a),
.STP_SPLY(STP_SPLY),
.STPEN(STPEN),
.tbe(tbe),
.xmit_buffer(xmit_buffer),
.clear_interrupts(clear_interrupts),
.DQ_CONTROL(DQ_CONTROL),
.FSM_CLK(FSM_CLK),
.INTR(INTR),
.OneWireIO_eq_Load(OneWireIO_eq_Load),
.OW_LOW(OW_LOW),
.OW_SHORT(OW_SHORT),
.pdr(pdr),
.rbf(rbf),
.rcvr_buffer(rcvr_buffer),
.reset_owr(reset_owr),
.rsrf(rsrf),
.STPZ(STPZ),
.temt(temt)
);
//synthesis attribute clock_signal of clk_1us IS no
//synthesis attribute buffer_type of clk_1us IS none
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's generate PC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PC, interface to IC. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_genpc(
// Clock and reset
clk, rst,
// External i/f to IC
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
icpu_rty_i, icpu_adr_i,
// Internal i/f
branch_op, except_type, except_prefix,
branch_addrofs, lr_restor, flag, taken, except_start,
binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
genpc_freeze, genpc_stop_prefetch, no_more_dslot
);
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External i/f to IC
//
output [31:0] icpu_adr_o;
output icpu_cycstb_o;
output [3:0] icpu_sel_o;
output [3:0] icpu_tag_o;
input icpu_rty_i;
input [31:0] icpu_adr_i;
//
// Internal i/f
//
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
input except_prefix;
input [31:2] branch_addrofs;
input [31:0] lr_restor;
input flag;
output taken;
input except_start;
input [31:2] binsn_addr;
input [31:0] epcr;
input [31:0] spr_dat_i;
input spr_pc_we;
input genpc_refetch;
input genpc_stop_prefetch;
input genpc_freeze;
input no_more_dslot;
//
// Internal wires and regs
//
reg [31:2] pcreg;
reg [31:0] pc;
reg taken; /* Set to in case of jump or taken branch */
reg genpc_refetch_r;
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
//
// Control access to IC subsystem
//
// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
//
// genpc_freeze_r
//
always @(posedge clk or posedge rst)
if (rst)
genpc_refetch_r <= #1 1'b0;
else if (genpc_refetch)
genpc_refetch_r <= #1 1'b1;
else
genpc_refetch_r <= #1 1'b0;
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
{2'b00, `OR1200_BRANCHOP_NOP}: begin
pc = {pcreg + 30'd1, 2'b0};
taken = 1'b0;
end
{2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
pc = {branch_addrofs, 2'b0};
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
pc = lr_restor;
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
pc = {binsn_addr + branch_addrofs, 2'b0};
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_BF}:
if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
pc = {binsn_addr + branch_addrofs, 2'b0};
taken = 1'b1;
end
else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
pc = {pcreg + 30'd1, 2'b0};
taken = 1'b0;
end
{2'b00, `OR1200_BRANCHOP_BNF}:
if (flag) begin
pc = {pcreg + 30'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
taken = 1'b0;
end
else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
pc = {binsn_addr + branch_addrofs, 2'b0};
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
pc = epcr;
taken = 1'b1;
end
{2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
taken = 1'b1;
end
default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
pc = spr_dat_i;
taken = 1'b0;
end
endcase
end
//
// PC register
//
always @(posedge clk or posedge rst)
if (rst)
// pcreg <= #1 30'd63;
pcreg <= #1 ({`OR1200_EXCEPT_EPH0_P, `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
else if (spr_pc_we)
pcreg <= #1 spr_dat_i[31:2];
else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
pcreg <= #1 pc[31:2];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
wire [63:0] result;
Test test(/*AUTOINST*/
// Outputs
.result (result[63:0]),
// Inputs
.clk (clk),
.cyc (cyc));
reg [63:0] sum;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d result=%x\n", $time, cyc, result);
`endif
cyc <= cyc + 1;
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc == 0) begin
// Setup
sum <= '0;
end
else if (cyc < 10) begin
sum <= '0;
end
else if (cyc < 90) begin
end
else if (cyc == 99) begin
$write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum);
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hfefad16f06ba6b1f
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test(/*AUTOARG*/
// Outputs
result,
// Inputs
clk, cyc
);
input clk;
input int cyc;
output reg [63:0] result;
logic [63:0] adder;
always @(posedge clk) begin
adder = 0;
for (int i = 0; i < 1000; ++i)
adder += {32'h0, (cyc+i)} ** 3;
result <= adder;
end
endmodule
|
/*
reset...init...save.start_write.stop_write.restore.start_read(compare).stop_read.loop
error...
*/
module mem_tester(
clk,
rst_n,
led, // LED flashing or not
// SRAM signals
SRAM_DQ, // sram inout databus
SRAM_ADDR, // sram address bus
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N, //
SRAM_CE_N, //
SRAM_OE_N //
);
parameter SRAM_DATA_SIZE = 8;
parameter SRAM_ADDR_SIZE = 19;
inout [SRAM_DATA_SIZE-1:0] SRAM_DQ;
wire [SRAM_DATA_SIZE-1:0] SRAM_DQ;
output [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
wire [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
output SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
wire SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
input clk;
input rst_n;
output led; reg led;
reg inc_pass_ctr; // increment passes counter (0000-9999 BCD)
reg inc_err_ctr; // increment errors counter (10 red binary LEDs)
reg check_in_progress; // when 1 - enables errors checking
reg [19:0] ledflash;
reg was_error;
initial ledflash='d0;
always @(posedge clk)
begin
if( inc_pass_ctr )
ledflash <= 20'd0;
else if( !ledflash[19] )
ledflash <= ledflash + 20'd1;
end
always @(posedge clk)
begin
led <= ledflash[19] ^ was_error;
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
was_error <= 1'b0;
else if( inc_err_ctr )
was_error <= 1'b1;
end
reg rnd_init,rnd_save,rnd_restore; // rnd_vec_gen control
wire [SRAM_DATA_SIZE-1:0] rnd_out; // rnd_vec_gen output
reg sram_start,sram_rnw;
wire sram_stop,sram_ready;
rnd_vec_gen my_rnd( .clk(clk), .init(rnd_init), .next(sram_ready), .save(rnd_save), .restore(rnd_restore), .out(rnd_out) );
defparam my_rnd.OUT_SIZE = SRAM_DATA_SIZE;
defparam my_rnd.LFSR_LENGTH = 41;
defparam my_rnd.LFSR_FEEDBACK = 3;
wire [SRAM_DATA_SIZE-1:0] sram_rdat;
sram_control my_sram( .clk(clk), .clk2(clk), .start(sram_start), .rnw(sram_rnw), .stop(sram_stop), .ready(sram_ready),
.rdat(sram_rdat), .wdat(rnd_out),
.SRAM_DQ(SRAM_DQ), .SRAM_ADDR(SRAM_ADDR),
.SRAM_CE_N(SRAM_CE_N), .SRAM_OE_N(SRAM_OE_N), .SRAM_WE_N(SRAM_WE_N) );
defparam my_sram.SRAM_DATA_SIZE = SRAM_DATA_SIZE;
defparam my_sram.SRAM_ADDR_SIZE = SRAM_ADDR_SIZE;
// FSM states and registers
reg [3:0] curr_state,next_state;
parameter RESET = 4'h0;
parameter INIT1 = 4'h1;
parameter INIT2 = 4'h2;
parameter BEGIN_WRITE1 = 4'h3;
parameter BEGIN_WRITE2 = 4'h4;
parameter BEGIN_WRITE3 = 4'h5;
parameter BEGIN_WRITE4 = 4'h6;
parameter WRITE = 4'h7;
parameter BEGIN_READ1 = 4'h8;
parameter BEGIN_READ2 = 4'h9;
parameter BEGIN_READ3 = 4'hA;
parameter BEGIN_READ4 = 4'hB;
parameter READ = 4'hC;
parameter END_READ = 4'hD;
parameter INC_PASSES1 = 4'hE;
parameter INC_PASSES2 = 4'hF;
// FSM dispatcher
always @*
begin
case( curr_state )
RESET:
next_state <= INIT1;
INIT1:
if( sram_stop )
next_state <= INIT2;
else
next_state <= INIT1;
INIT2:
next_state <= BEGIN_WRITE1;
BEGIN_WRITE1:
next_state <= BEGIN_WRITE2;
BEGIN_WRITE2:
next_state <= BEGIN_WRITE3;
BEGIN_WRITE3:
next_state <= BEGIN_WRITE4;
BEGIN_WRITE4:
next_state <= WRITE;
WRITE:
if( sram_stop )
next_state <= BEGIN_READ1;
else
next_state <= WRITE;
BEGIN_READ1:
next_state <= BEGIN_READ2;
BEGIN_READ2:
next_state <= BEGIN_READ3;
BEGIN_READ3:
next_state <= BEGIN_READ4;
BEGIN_READ4:
next_state <= READ;
READ:
if( sram_stop )
next_state <= END_READ;
else
next_state <= READ;
END_READ:
next_state <= INC_PASSES1;
INC_PASSES1:
next_state <= INC_PASSES2;
INC_PASSES2:
next_state <= BEGIN_WRITE1;
default:
next_state <= RESET;
endcase
end
// FSM sequencer
always @(posedge clk,negedge rst_n)
begin
if( !rst_n )
curr_state <= RESET;
else
curr_state <= next_state;
end
// FSM controller
always @(posedge clk)
begin
case( curr_state )
//////////////////////////////////////////////////
RESET:
begin
// various initializings begin
inc_pass_ctr <= 1'b0;
check_in_progress <= 1'b0;
rnd_init <= 1'b1; //begin RND init
rnd_save <= 1'b0;
rnd_restore <= 1'b0;
sram_start <= 1'b1;
sram_rnw <= 1'b1; // start condition for sram controller, in read mode
end
INIT1:
begin
sram_start <= 1'b0; // end sram start
end
INIT2:
begin
rnd_init <= 1'b0; // end rnd init
end
//////////////////////////////////////////////////
BEGIN_WRITE1:
begin
rnd_save <= 1'b1;
sram_rnw <= 1'b0;
end
BEGIN_WRITE2:
begin
rnd_save <= 1'b0;
sram_start <= 1'b1;
end
BEGIN_WRITE3:
begin
sram_start <= 1'b0;
end
/* BEGIN_WRITE4:
begin
rnd_save <= 1'b0;
sram_start <= 1'b1;
end
WRITE:
begin
sram_start <= 1'b0;
end
*/
//////////////////////////////////////////////////
BEGIN_READ1:
begin
rnd_restore <= 1'b1;
sram_rnw <= 1'b1;
end
BEGIN_READ2:
begin
rnd_restore <= 1'b0;
sram_start <= 1'b1;
end
BEGIN_READ3:
begin
sram_start <= 1'b0;
check_in_progress <= 1'b1;
end
/* BEGIN_READ4:
begin
rnd_restore <= 1'b0;
sram_start <= 1'b1;
end
READ:
begin
sram_start <= 1'b0;
check_in_progress <= 1'b1;
end
*/
END_READ:
begin
check_in_progress <= 1'b0;
end
INC_PASSES1:
begin
inc_pass_ctr <= 1'b1;
end
INC_PASSES2:
begin
inc_pass_ctr <= 1'b0;
end
endcase
end
// errors counter
always @(posedge clk)
inc_err_ctr <= check_in_progress & sram_ready & ((sram_rdat==rnd_out)?0:1);
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max interp rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_int_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 21;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases
8'd4 : bitgain = 6;
8'd8 : bitgain = 9;
8'd16 : bitgain = 12;
8'd32 : bitgain = 15;
8'd64 : bitgain = 18;
8'd128 : bitgain = 21;
// Nearest without overflow
8'd5 : bitgain = 7;
8'd6 : bitgain = 8;
8'd7 : bitgain = 9;
8'd9,8'd10 : bitgain = 10;
8'd11,8'd12 : bitgain = 11;
8'd13,8'd14,8'd15 : bitgain = 12;
8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
default : bitgain = 19;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd6 : signal_out = signal_in[6+bw-1:6];
5'd9 : signal_out = signal_in[9+bw-1:9];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd7 : signal_out = signal_in[7+bw-1:7];
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
default : signal_out = signal_in[21+bw-1:21];
endcase // case(shift)
endmodule // cic_int_shifter
|
//////////////////////////////////////////////////////////////////////
//// ////
//// adbg_or1k_biu.v ////
//// ////
//// ////
//// This file is part of the SoC Advanced Debug Interface. ////
//// ////
//// Author(s): ////
//// Nathan Yawn ([email protected]) ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 - 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_or1k_biu.v,v $
// Revision 1.3 2010-01-10 22:54:10 Nathan
// Update copyright dates
//
// Revision 1.2 2009/05/17 20:54:56 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/22 20:28:30 Nathan
// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.5 2008/07/08 19:04:03 Nathan
// Many small changes to eliminate compiler warnings, no functional
// changes. System will now pass SRAM and CPU self-tests on Altera
// FPGA using altera_virtual_jtag TAP.
//
module adbg_or1k_biu
(
// Debug interface signals
tck_i,
rst_i,
data_i,
data_o,
addr_i,
strobe_i,
rd_wrn_i, // If 0, then write op
rdy_o,
// OR1K SPR bus signals
cpu_clk_i,
cpu_addr_o,
cpu_data_i,
cpu_data_o,
cpu_stb_o,
cpu_we_o,
cpu_ack_i
);
// Debug interface signals
input tck_i;
input rst_i;
input [31:0] data_i; // Assume short words are in UPPER order bits!
output [31:0] data_o;
input [31:0] addr_i;
input strobe_i;
input rd_wrn_i;
output rdy_o;
// OR1K SPR bus signals
input cpu_clk_i;
output [31:0] cpu_addr_o;
input [31:0] cpu_data_i;
output [31:0] cpu_data_o;
output cpu_stb_o;
output cpu_we_o;
input cpu_ack_i;
reg rdy_o;
reg cpu_stb_o;
// Registers
reg [31:0] addr_reg;
reg [31:0] data_in_reg; // dbg->WB
reg [31:0] data_out_reg; // WB->dbg
reg wr_reg;
reg str_sync; // This is 'active-toggle' rather than -high or -low.
reg rdy_sync; // ditto, active-toggle
// Sync registers. TFF indicates TCK domain, WBFF indicates cpu_clk domain
reg rdy_sync_tff1;
reg rdy_sync_tff2;
reg rdy_sync_tff2q; // used to detect toggles
reg str_sync_wbff1;
reg str_sync_wbff2;
reg str_sync_wbff2q; // used to detect toggles
// Control Signals
reg data_o_en; // latch wb_data_i
reg rdy_sync_en; // toggle the rdy_sync signal, indicate ready to TCK domain
// Internal signals
wire start_toggle; // CPU domain, indicates a toggle on the start strobe
//////////////////////////////////////////////////////
// TCK clock domain
// There is no FSM here, just signal latching and clock
// domain synchronization
// Latch input data on 'start' strobe, if ready.
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) begin
addr_reg <= 32'h0;
data_in_reg <= 32'h0;
wr_reg <= 1'b0;
end
else
if(strobe_i && rdy_o) begin
addr_reg <= addr_i;
if(!rd_wrn_i) data_in_reg <= data_i;
wr_reg <= ~rd_wrn_i;
end
end
// Create toggle-active strobe signal for clock sync. This will start a transaction
// to the CPU once the toggle propagates to the FSM in the cpu_clk domain.
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) str_sync <= 1'b0;
else if(strobe_i && rdy_o) str_sync <= ~str_sync;
end
// Create rdy_o output. Set on reset, clear on strobe (if set), set on input toggle
always @ (posedge tck_i or posedge rst_i)
begin
if(rst_i) begin
rdy_sync_tff1 <= 1'b0;
rdy_sync_tff2 <= 1'b0;
rdy_sync_tff2q <= 1'b0;
rdy_o <= 1'b1;
end
else begin
rdy_sync_tff1 <= rdy_sync; // Synchronize the ready signal across clock domains
rdy_sync_tff2 <= rdy_sync_tff1;
rdy_sync_tff2q <= rdy_sync_tff2; // used to detect toggles
if(strobe_i && rdy_o) rdy_o <= 1'b0;
else if(rdy_sync_tff2 != rdy_sync_tff2q) rdy_o <= 1'b1;
end
end
//////////////////////////////////////////////////////////
// Direct assignments, unsynchronized
assign cpu_data_o = data_in_reg;
assign cpu_we_o = wr_reg;
assign cpu_addr_o = addr_reg;
assign data_o = data_out_reg;
///////////////////////////////////////////////////////
// Wishbone clock domain
// synchronize the start strobe
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if(rst_i) begin
str_sync_wbff1 <= 1'b0;
str_sync_wbff2 <= 1'b0;
str_sync_wbff2q <= 1'b0;
end
else begin
str_sync_wbff1 <= str_sync;
str_sync_wbff2 <= str_sync_wbff1;
str_sync_wbff2q <= str_sync_wbff2; // used to detect toggles
end
end
assign start_toggle = (str_sync_wbff2 != str_sync_wbff2q);
// CPU->dbg data register
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if(rst_i) data_out_reg <= 32'h0;
else if(data_o_en) data_out_reg <= cpu_data_i;
end
// Create a toggle-active ready signal to send to the TCK domain
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if(rst_i) rdy_sync <= 1'b0;
else if(rdy_sync_en) rdy_sync <= ~rdy_sync;
end
/////////////////////////////////////////////////////
// Small state machine to create OR1K SPR bus accesses
// Not much more that an 'in_progress' bit, but easier
// to read. Deals with single-cycle and multi-cycle
// accesses.
reg cpu_fsm_state;
reg next_fsm_state;
`define STATE_IDLE 1'h0
`define STATE_TRANSFER 1'h1
// Sequential bit
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if(rst_i) cpu_fsm_state <= `STATE_IDLE;
else cpu_fsm_state <= next_fsm_state;
end
// Determination of next state (combinatorial)
always @ (cpu_fsm_state or start_toggle or cpu_ack_i)
begin
case (cpu_fsm_state)
`STATE_IDLE:
begin
if(start_toggle && !cpu_ack_i) next_fsm_state <= `STATE_TRANSFER; // Don't go to next state for 1-cycle transfer
else next_fsm_state <= `STATE_IDLE;
end
`STATE_TRANSFER:
begin
if(cpu_ack_i) next_fsm_state <= `STATE_IDLE;
else next_fsm_state <= `STATE_TRANSFER;
end
endcase
end
// Outputs of state machine (combinatorial)
always @ (cpu_fsm_state or start_toggle or cpu_ack_i or wr_reg)
begin
rdy_sync_en <= 1'b0;
data_o_en <= 1'b0;
cpu_stb_o <= 1'b0;
case (cpu_fsm_state)
`STATE_IDLE:
begin
if(start_toggle) begin
cpu_stb_o <= 1'b1;
if(cpu_ack_i) begin
rdy_sync_en <= 1'b1;
end
if (cpu_ack_i && !wr_reg) begin // latch read data
data_o_en <= 1'b1;
end
end
end
`STATE_TRANSFER:
begin
cpu_stb_o <= 1'b1; // OR1K behavioral model needs this. OR1200 should be indifferent.
if(cpu_ack_i) begin
data_o_en <= 1'b1;
rdy_sync_en <= 1'b1;
end
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
module DE0_NANO_SOC_Default();
wire [31:0] cpuDataOut;
wire [31:0] cpuDataIn;
wire [31:0] cpuDataInAddr;
wire [31:0] cpuDataOutAddr;
wire cpuWrEn;
wire [31:0] instrBus;
wire [31:0] pcBus;
wire [31:0] CPU_StatusBus;
wire forceRoot;
wire flushing;
wire [31:0] instrCacheAddr;
wire [31:0] instrCacheData;
wire [31:0] dataOutFlowCtrl;
wire [31:0] dataOutUART;
wire [31:0] dataOutDataCache;
wire [31:0] IRQBus;
wire [31:0] uartStatus;
reg clk;
reg rst;
wire TxD;
assign IRQBus = 0;
assign IRQBus[0] = uartStatus[2]; // RX buffer ready
assign IRQBus[1] = uartStatus[1]; // TX complete
wolfcore CPU(
.dataOutput(cpuDataOut),
.dataInput(cpuDataIn),
.dataInAddr(cpuDataInAddr),
.dataOutAddr(cpuDataOutAddr),
.dataWrEn(cpuWrEn),
.instrInput(instrBus),
.pc(pcBus),
.CPU_Status(CPU_StatusBus),
.rst(rst),
.clk(clk),
.forceRoot(forceRoot),
.flushing(flushing)
);
flowController instrCtrl(
.rst(rst),
.clk(clk),
.pc(pcBus),
.CPU_Status(CPU_StatusBus),
.flushing(flushing),
.instrOut(instrBus),
.forceRoot(forceRoot),
.memAddr(instrCacheAddr),
.instrIn(instrCacheData),
.IRQ(IRQBus),
.inputAddr(cpuDataOutAddr),
.outputAddr(cpuDataInAddr),
.inputData(cpuDataOut),
.outputData(dataOutFlowCtrl),
.wrEn(cpuWrEn)
);
progMem instrCache(
.instrOutput(instrCacheData),
.instrAddress(instrCacheAddr),
.clk(clk)
);
dataController dataCache(
.dataIn(cpuDataOut),
.dataInAddr(cpuDataOutAddr),
.dataOut(dataOutDataCache),
.dataOutAddr(cpuDataInAddr),
.wren(cpuWrEn),
.clk(clk)
);
UART testUART(
.clk(clk),
.rst(rst),
.RxD(1'b0),
.TxD(TxD),
.inputData(cpuDataOut),
.inputAddr(cpuDataOutAddr),
.outputData(dataOutUART),
.outputAddr(cpuDataInAddr),
.wren(cpuWrEn),
.uartStatus(uartStatus)
);
outputDataMux dataMux(
.outputAddr(cpuDataInAddr),
.outputDataUART(dataOutUART),
.outputDataFlowCtrl(dataOutFlowCtrl),
.outputDataDataCache(dataOutDataCache),
.outputData(cpuDataIn)
);
initial begin
clk = 1'b0;
forever begin
#1
clk = ~clk;
end
end
initial begin
rst = 1'b1;
#10
rst = 1'b0;
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_sync_clock_converter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_clock_converter_v2_1_axic_sync_clock_converter # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex6",
parameter integer C_PAYLOAD_WIDTH = 32,
parameter integer C_S_ACLK_RATIO = 1,
parameter integer C_M_ACLK_RATIO = 1 ,
parameter integer C_MODE = 0 // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SAMPLE_CYCLE_EARLY,
input wire SAMPLE_CYCLE,
// Slave side
input wire S_ACLK,
input wire S_ARESETN,
input wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,
input wire S_VALID,
output wire S_READY,
// Master side
input wire M_ACLK,
input wire M_ARESETN,
output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,
output wire M_VALID,
input wire M_READY
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam [1:0] ZERO = 2'b10;
localparam [1:0] ONE = 2'b11;
localparam [1:0] TWO = 2'b01;
localparam [1:0] INIT = 2'b00;
localparam integer P_LIGHT_WT = 0;
localparam integer P_FULLY_REG = 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru
assign M_PAYLOAD = S_PAYLOAD;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end else begin : gen_sync_clock_converter
wire s_sample_cycle;
wire s_sample_cycle_early;
wire m_sample_cycle;
wire m_sample_cycle_early;
wire slow_aclk;
wire slow_areset;
wire s_areset_r;
wire m_areset_r;
reg s_tready_r;
wire s_tready_ns;
reg m_tvalid_r;
wire m_tvalid_ns;
reg [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;
reg [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;
wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns;
wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns;
reg m_tready_hold;
wire m_tready_sample;
wire load_tpayload;
wire load_tstorage;
wire load_tpayload_from_tstorage;
reg [1:0] state;
reg [1:0] next_state;
reg s_aresetn_r = 1'b0; // Reset delay register
always @(posedge S_ACLK) begin
if (~S_ARESETN | ~M_ARESETN) begin
s_aresetn_r <= 1'b0;
end else begin
s_aresetn_r <= S_ARESETN & M_ARESETN;
end
end
assign s_areset_r = ~s_aresetn_r;
reg m_aresetn_r = 1'b0; // Reset delay register
always @(posedge M_ACLK) begin
if (~S_ARESETN | ~M_ARESETN) begin
m_aresetn_r <= 1'b0;
end else begin
m_aresetn_r <= S_ARESETN & M_ARESETN;
end
end
assign m_areset_r = ~m_aresetn_r;
if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi
assign slow_aclk = M_ACLK;
end else begin : gen_slowclk_si
assign slow_aclk = S_ACLK;
end
assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;
assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;
assign s_sample_cycle = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;
assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;
assign m_sample_cycle = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;
// Output flop for S_READY, value is encoded into state machine.
assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];
always @(posedge S_ACLK) begin
if (s_areset_r) begin
s_tready_r <= 1'b0;
end
else begin
s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;
end
end
assign S_READY = s_tready_r;
// Output flop for M_VALID
assign m_tvalid_ns = next_state[0];
always @(posedge M_ACLK) begin
if (m_areset_r) begin
m_tvalid_r <= 1'b0;
end
else begin
m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;
end
end
assign M_VALID = m_tvalid_r;
// Hold register for M_READY when M_ACLK is fast.
always @(posedge M_ACLK) begin
if (m_areset_r) begin
m_tready_hold <= 1'b0;
end
else begin
m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;
end
end
assign m_tready_sample = (M_READY ) | m_tready_hold;
// Output/storage flops for PAYLOAD
assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :
load_tpayload_from_tstorage ? m_tstorage_r :
S_PAYLOAD;
assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;
always @(posedge slow_aclk) begin
m_tpayload_r <= m_tpayload_ns;
m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;
end
assign M_PAYLOAD = m_tpayload_r;
// load logic
assign load_tstorage = C_MODE && (state != TWO);
assign load_tpayload = m_tready_sample || (state == ZERO);
assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;
// State machine
always @(posedge slow_aclk) begin
state <= next_state;
end
always @* begin
if (slow_areset) begin
next_state = INIT;
end else begin
case (state)
INIT: begin
next_state = ZERO;
end
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
next_state = C_MODE ? ONE : TWO; // Push from empty
end
else begin
next_state = ZERO;
end
end
// One transaction stored locally
ONE: begin
if (C_MODE == 0) begin
next_state = TWO; // State ONE is inaccessible when C_MODE=0
end
else if (m_tready_sample & ~S_VALID) begin
next_state = ZERO; // Read out one so move to ZERO
end
else if (~m_tready_sample & S_VALID) begin
next_state = TWO; // Got another one so move to TWO
end
else begin
next_state = ONE;
end
end
// Storage registers full
TWO: begin
if (m_tready_sample) begin
next_state = C_MODE ? ONE : ZERO; // Pop from full
end
else begin
next_state = TWO;
end
end
endcase // case (state)
end
end
end // gen_sync_clock_converter
endgenerate
endmodule
`default_nettype wire
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
////
//// /* Modifications to spi_top.v */
//// /* Copyright (c) 2006 Rice University */
//// /* All Rights Reserved */
//// /* This code is covered by the Rice-WARP license */
//// /* See http://warp.rice.edu/license/ for details */
module spi_top
(
// OPB signals
opb_clk_i, opb_rst_i,
// SPI registers
reg_ctrl, reg_ss, reg_divider, reg_tx, ctrlwrite, busval, go,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o
);
parameter Tp = 1;
// OPB signals
input opb_clk_i; // master clock input
input opb_rst_i; // synchronous active high reset
// SPI registers
input [13:0] reg_ctrl;
input [7:0] reg_ss;
input [3:0] reg_divider;
input [17:0] reg_tx;
input ctrlwrite;
input busval;
output go;
// SPI signals
output [8-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
// Internal signals
wire [17:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [4:0] char_len; // char len
//wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
reg ctrlbitgo;
assign rx_negedge = reg_ctrl[9];
assign tx_negedge = reg_ctrl[10];
assign go = ctrlbitgo;
assign char_len = reg_ctrl[6:0];
assign lsb = reg_ctrl[11];
assign ie = reg_ctrl[12];
assign ass = reg_ctrl[13];
always @(posedge opb_clk_i or posedge opb_rst_i)
begin
if (opb_rst_i)
ctrlbitgo <= #Tp 1'b0;
else if(ctrlwrite && !tip)
ctrlbitgo <= #Tp busval;
else if(tip && last_bit && pos_edge)
ctrlbitgo <= #Tp 1'b0;
end
assign ss_pad_o = ~((reg_ss & {8{tip & ass}}) | (reg_ss & {8{!ass}}));
spi_clgen clgen (.clk_in(opb_clk_i), .rst(opb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
.divider(reg_divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
spi_shift shift (.clk(opb_clk_i), .rst(opb_rst_i), .len(char_len[5-1:0]),
.lsb(lsb), .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in(reg_tx), .p_out(rx),
.s_clk(sclk_pad_o), .s_out(mosi_pad_o));
endmodule
|
module mio_dp (/*AUTOARG*/
// Outputs
tx_full, tx_prog_full, tx_empty, rx_full, rx_prog_full, rx_empty,
tx_access, tx_packet, rx_wait, wait_out, access_out, packet_out,
// Inputs
clk, io_clk, nreset, datasize, ddr_mode, lsbfirst, framepol, tx_en,
rx_en, tx_wait, rx_clk, rx_access, rx_packet, access_in, packet_in,
wait_in
);
//#####################################################################
//# INTERFACE
//#####################################################################
//parameters
parameter PW = 104; // data width (core)
parameter NMIO = 8; // Mini IO width
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
// reset, clk, config
input clk; // main core clock
input io_clk; // clock for TX
input nreset; // async active low reset
input [7:0] datasize; // size of data transmitted
input ddr_mode; // dual data rate mode
input lsbfirst; // send data lsbfirst
input framepol; // polarity of frame signal
input tx_en; // enable transmit
input rx_en; // enable receive
// status
output tx_full;
output tx_prog_full;
output tx_empty;
output rx_full;
output rx_prog_full;
output rx_empty;
// tx interface
output tx_access; // access signal for IO
output [NMIO-1:0] tx_packet; // packet for IO
input tx_wait; // pushback from IO
// rx interface
input rx_clk; // rx clock
input rx_access; // rx access
input [NMIO-1:0] rx_packet; // rx packet
output rx_wait; // pushback from IO
// core interface
input access_in; // fifo data valid
input [PW-1:0] packet_in; // fifo packet
output wait_out; // wait pushback for fifo
output access_out; // fifo data valid
output [PW-1:0] packet_out; // fifo packet
input wait_in; // wait pushback for fifo
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
mtx #(.NMIO(NMIO),
.PW(PW),
.TARGET(TARGET))
mtx (/*AUTOINST*/
// Outputs
.tx_empty (tx_empty),
.tx_full (tx_full),
.tx_prog_full (tx_prog_full),
.wait_out (wait_out),
.tx_access (tx_access),
.tx_packet (tx_packet[NMIO-1:0]),
// Inputs
.clk (clk),
.io_clk (io_clk),
.nreset (nreset),
.tx_en (tx_en),
.datasize (datasize[7:0]),
.ddr_mode (ddr_mode),
.lsbfirst (lsbfirst),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.tx_wait (tx_wait));
mrx #(.NMIO(NMIO),
.PW(PW),
.TARGET(TARGET))
mrx (/*AUTOINST*/
// Outputs
.rx_empty (rx_empty),
.rx_full (rx_full),
.rx_prog_full (rx_prog_full),
.rx_wait (rx_wait),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.datasize (datasize[7:0]),
.ddr_mode (ddr_mode),
.lsbfirst (lsbfirst),
.framepol (framepol),
.rx_clk (rx_clk),
.rx_access (rx_access),
.rx_packet (rx_packet[NMIO-1:0]),
.wait_in (wait_in));
endmodule // mio_dp
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_divide
// ============================================================
// File Name: DIV27_19.v
// Megafunction Name(s):
// lpm_divide
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DIV27_19 (
clock,
denom,
numer,
quotient,
remain);
input clock;
input [34:0] denom;
input [42:0] numer;
output [42:0] quotient;
output [34:0] remain;
wire [42:0] sub_wire0;
wire [34:0] sub_wire1;
wire [42:0] quotient = sub_wire0[42:0];
wire [34:0] remain = sub_wire1[34:0];
lpm_divide lpm_divide_component (
.denom (denom),
.clock (clock),
.numer (numer),
.quotient (sub_wire0),
.remain (sub_wire1),
.aclr (1'b0),
.clken (1'b1));
defparam
lpm_divide_component.lpm_drepresentation = "UNSIGNED",
lpm_divide_component.lpm_hint = "MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE",
lpm_divide_component.lpm_nrepresentation = "UNSIGNED",
lpm_divide_component.lpm_pipeline = 6,
lpm_divide_component.lpm_type = "LPM_DIVIDE",
lpm_divide_component.lpm_widthd = 35,
lpm_divide_component.lpm_widthn = 43;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "5"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "6"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "35"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "43"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: denom 0 0 35 0 INPUT NODEFVAL denom[34..0]
// Retrieval info: USED_PORT: numer 0 0 43 0 INPUT NODEFVAL numer[42..0]
// Retrieval info: USED_PORT: quotient 0 0 43 0 OUTPUT NODEFVAL quotient[42..0]
// Retrieval info: USED_PORT: remain 0 0 35 0 OUTPUT NODEFVAL remain[34..0]
// Retrieval info: CONNECT: @numer 0 0 43 0 numer 0 0 43 0
// Retrieval info: CONNECT: @denom 0 0 35 0 denom 0 0 35 0
// Retrieval info: CONNECT: quotient 0 0 43 0 @quotient 0 0 43 0
// Retrieval info: CONNECT: remain 0 0 35 0 @remain 0 0 35 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV27_19.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV27_19.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV27_19.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV27_19.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV27_19_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DIV27_19_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
//
// Copyright (c) 1999 Thomas Coonan ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// **** Here's a simple, sequential multiplier. Very simple, unsigned..
// Not very well tested, play with testbench, use at your own risk, blah blah blah..
//
//
// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit output)
//
// Present data and assert start synchronous with clk.
// Assert start for ONLY one cycle.
// Wait N cycles for answer (at most). Answer will remain stable until next start.
// You may use DONE signal as handshake.
//
// Written by tom coonan
//
module mult16 (clk, resetb, start, done, ain, bin, yout);
parameter N = 16;
input clk;
input resetb;
input start; // Register the ain and bin inputs (they can change afterwards)
//input [N-1:0] ain;
//input [N-1:0] bin;
//output [2*N-1:0] yout;
input [15:0] ain;
input [15:0] bin;
output [31:0] yout;
output done;
//reg [2*N-1:0] a;
//reg [N-1:0] b;
//reg [2*N-1:0] yout;
reg [31:0] a;
reg [15:0] b;
reg [31:0] yout;
reg done;
always @(posedge clk or negedge resetb) begin
if (~resetb) begin
a <= 0;
b <= 0;
yout <= 0;
done <= 1'b1;
end
else begin
// Load will register the input and clear the counter.
if (start) begin
a <= ain;
b <= bin;
yout <= 0;
done <= 0;
end
else begin
// Go until b is zero
if (~done) begin
if (b != 0) begin
// If '1' then add a to sum
if (b[0]) begin
yout <= yout + a;
end
b <= b >> 1;
a <= a << 1;
$display ("a = %h, b = %h, yout = %h", a,b,yout);
end
else begin
done <= 1'b1;
end
end
end
end
end
endmodule
module mul16;
reg clk, resetb, start;
reg [15:0] a;
reg [15:0] b;
wire [31:0] y;
wire done;
mult16 mult16inst (clk, resetb, start, done, a, b, y);
initial begin
clk = 0;
forever begin
#10 clk = ~clk;
end
end
initial begin
resetb = 0;
#30 resetb = 1;
end
integer num_errors;
parameter MAX_TRIALS = 10;
initial begin
// $dumpfile ("multdiv.vcd");
// $dumpvars (0,a);
// $dumpvars (0,b);
// $dumpvars (0,y);
// $dumpvars (0,resetb);
// $dumpvars (0,done);
num_errors = 0;
#100;
// Do a bunch of random multiplies
repeat (MAX_TRIALS) begin
test_multiply ($random, $random);
end
// Special cases
test_multiply ($random, 1);
test_multiply (1, $random);
test_multiply ($random, 0);
test_multiply (0, $random);
$display ("Done. %0d Errors", num_errors);
#800;
$finish;
end
task test_multiply;
input [15:0] aarg;
input [15:0] barg;
integer expected_answer;
begin
if (~done) begin
$display ("Multiplier is Busy!!");
end
else begin
@(negedge clk);
start = 1;
a = aarg;
b = barg;
@(negedge clk) start = 0;
@(posedge done);
expected_answer = a*b;
$display ("%0d * %0d = %0h, Reality = %0h", a, b, y, expected_answer);
if (y !== expected_answer) begin
$display (" FAILURE!");
num_errors = num_errors + 1;
end
end
end
endtask
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_Onchip_Memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../video_sys_Onchip_Memory.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "video_sys_Onchip_Memory.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 4096,
// the_altsyncram.numwords_a = 4096,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 12;
//
//synthesis read_comments_as_HDL off
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level bank machine block. A structural block instantiating the configured
// individual bank machines, and a common block that computes various items shared
// by all bank machines.
`timescale 1ps/1ps
module mig_7series_v1_9_bank_mach #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter nOP_WAIT = 0,
parameter nRAS = 20,
parameter nRCD = 5,
parameter nRFC = 44,
parameter nRTP = 4,
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter nRP = 10,
parameter nSLOTS = 2,
parameter nWR = 6,
parameter nXSDLL = 512,
parameter ORDERING = "NORM",
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
output accept, // From bank_common0 of bank_common.v
output accept_ns, // From bank_common0 of bank_common.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v
output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v
output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v
output col_periodic_rd, // From arb_mux0 of arb_mux.v
output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v
output col_rmw, // From arb_mux0 of arb_mux.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v
output col_size, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [5:0] mc_data_offset_1,
output [5:0] mc_data_offset_2,
output [1:0] mc_cas_slot,
output insert_maint_r1, // From arb_mux0 of arb_mux.v
output maint_wip_r, // From bank_common0 of bank_common.v
output wire [nBANK_MACHS-1:0] sending_row,
output wire [nBANK_MACHS-1:0] sending_col,
output wire sent_col,
output wire sent_col_r,
output periodic_rd_ack_r,
output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
output idle,
// Inputs
input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input clk, // To bank0 of bank_cntrl.v, ...
input [2:0] cmd, // To bank0 of bank_cntrl.v, ...
input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v
input init_calib_complete, // To bank_common0 of bank_common.v
input phy_rddata_valid, // To bank0 of bank_cntrl.v
input dq_busy_data, // To bank0 of bank_cntrl.v
input hi_priority, // To bank0 of bank_cntrl.v, ...
input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v
input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ...
input maint_req_r, // To bank0 of bank_cntrl.v, ...
input maint_zq_r, // To bank0 of bank_cntrl.v, ...
input maint_sre_r, // To bank0 of bank_cntrl.v, ...
input maint_srx_r, // To bank0 of bank_cntrl.v, ...
input periodic_rd_r, // To bank_common0 of bank_common.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v
input rd_rmw, // To bank0 of bank_cntrl.v
input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v
input rst, // To bank0 of bank_cntrl.v, ...
input size, // To bank0 of bank_cntrl.v
input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ...
input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ...
input use_addr
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1;
localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1;
localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1;
localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1;
localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0));
localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR;
// Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nWTP_CLKS = (nCK_PER_CLK == 1)
? nWTP :
(nCK_PER_CLK == 2)
? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) :
(nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2);
localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS)
? nRAS_CLKS
: nWTP_CLKS) - 1);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire accept_internal_r; // From bank_common0 of bank_common.v
wire accept_req; // From bank_common0 of bank_common.v
wire adv_order_q; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v
wire insert_maint_r; // From bank_common0 of bank_common.v
wire low_idle_cnt_r; // From bank_common0 of bank_common.v
wire maint_idle; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v
wire periodic_rd_insert; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v
wire sent_row; // From arb_mux0 of arb_mux.v
wire was_priority; // From bank_common0 of bank_common.v
wire was_wr; // From bank_common0 of bank_common.v
// End of automatics
wire [RANK_WIDTH-1:0] rnk_config;
wire rnk_config_strobe;
wire rnk_config_kill_rts_col;
wire rnk_config_valid_r;
wire [nBANK_MACHS-1:0] rts_row;
wire [nBANK_MACHS-1:0] rts_col;
wire [nBANK_MACHS-1:0] rts_pre;
wire [nBANK_MACHS-1:0] col_rdy_wr;
wire [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] sending_pre;
wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;
wire [nBANK_MACHS-1:0] req_size_r;
wire [RANK_VECT_INDX:0] req_rank_r;
wire [BANK_VECT_INDX:0] req_bank_r;
wire [ROW_VECT_INDX:0] req_row_r;
wire [ROW_VECT_INDX:0] col_addr;
wire [nBANK_MACHS-1:0] req_periodic_rd_r;
wire [nBANK_MACHS-1:0] req_wr_r;
wire [nBANK_MACHS-1:0] rd_wr_r;
wire [nBANK_MACHS-1:0] req_ras;
wire [nBANK_MACHS-1:0] req_cas;
wire [ROW_VECT_INDX:0] row_addr;
wire [nBANK_MACHS-1:0] row_cmd_wr;
wire [nBANK_MACHS-1:0] demand_priority;
wire [nBANK_MACHS-1:0] demand_act_priority;
wire [nBANK_MACHS-1:0] idle_ns;
wire [nBANK_MACHS-1:0] rb_hit_busy_r;
wire [nBANK_MACHS-1:0] bm_end;
wire [nBANK_MACHS-1:0] passing_open_bank;
wire [nBANK_MACHS-1:0] ordered_r;
wire [nBANK_MACHS-1:0] ordered_issued;
wire [nBANK_MACHS-1:0] rb_hit_busy_ns;
wire [nBANK_MACHS-1:0] maint_hit;
wire [nBANK_MACHS-1:0] idle_r;
wire [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] start_rcd;
wire [nBANK_MACHS-1:0] end_rtp;
wire [nBANK_MACHS-1:0] op_exit_req;
wire [nBANK_MACHS-1:0] op_exit_grant;
wire [nBANK_MACHS-1:0] start_pre_wait;
wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns;
genvar ID;
generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl
mig_7series_v1_9_bank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRCD (nRCD),
.nRTP (nRTP),
.nRP (nRP),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank0
(.demand_priority (demand_priority[ID]),
.demand_priority_in ({2{demand_priority}}),
.demand_act_priority (demand_act_priority[ID]),
.demand_act_priority_in ({2{demand_act_priority}}),
.rts_row (rts_row[ID]),
.rts_col (rts_col[ID]),
.rts_pre (rts_pre[ID]),
.col_rdy_wr (col_rdy_wr[ID]),
.rtc (rtc[ID]),
.sending_row (sending_row[ID]),
.sending_pre (sending_pre[ID]),
.sending_col (sending_col[ID]),
.req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]),
.req_size_r (req_size_r[ID]),
.req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]),
.req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]),
.req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.req_wr_r (req_wr_r[ID]),
.rd_wr_r (rd_wr_r[ID]),
.req_periodic_rd_r (req_periodic_rd_r[ID]),
.req_ras (req_ras[ID]),
.req_cas (req_cas[ID]),
.row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.row_cmd_wr (row_cmd_wr[ID]),
.act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]),
.wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]),
.rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]),
.idle_ns (idle_ns[ID]),
.rb_hit_busy_r (rb_hit_busy_r[ID]),
.bm_end (bm_end[ID]),
.bm_end_in ({2{bm_end}}),
.passing_open_bank (passing_open_bank[ID]),
.passing_open_bank_in ({2{passing_open_bank}}),
.ordered_r (ordered_r[ID]),
.ordered_issued (ordered_issued[ID]),
.rb_hit_busy_ns (rb_hit_busy_ns[ID]),
.rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}),
.maint_hit (maint_hit[ID]),
.req_rank_r_in ({2{req_rank_r}}),
.idle_r (idle_r[ID]),
.head_r (head_r[ID]),
.start_rcd (start_rcd[ID]),
.start_rcd_in ({2{start_rcd}}),
.end_rtp (end_rtp[ID]),
.op_exit_req (op_exit_req[ID]),
.op_exit_grant (op_exit_grant[ID]),
.start_pre_wait (start_pre_wait[ID]),
.ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]),
.ras_timer_ns_in ({2{ras_timer_ns}}),
.rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]),
/*AUTOINST*/
// Inputs
.accept_internal_r (accept_internal_r),
.accept_req (accept_req),
.adv_order_q (adv_order_q),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.low_idle_cnt_r (low_idle_cnt_r),
.maint_idle (maint_idle),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rank (rank[RANK_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.sent_col (sent_col),
.sent_row (sent_row),
.size (size),
.use_addr (use_addr),
.was_priority (was_priority),
.was_wr (was_wr));
end
endgenerate
mig_7series_v1_9_bank_common #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRFC (nRFC),
.nXSDLL (nXSDLL),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.CWL (CWL),
.tZQCS (tZQCS))
bank_common0
(.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]),
/*AUTOINST*/
// Outputs
.accept_internal_r (accept_internal_r),
.accept_ns (accept_ns),
.accept (accept),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_ack_r (periodic_rd_ack_r),
.accept_req (accept_req),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.idle (idle),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.adv_order_q (adv_order_q),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.low_idle_cnt_r (low_idle_cnt_r),
.was_wr (was_wr),
.was_priority (was_priority),
.maint_wip_r (maint_wip_r),
.maint_idle (maint_idle),
.insert_maint_r (insert_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.idle_ns (idle_ns[nBANK_MACHS-1:0]),
.init_calib_complete (init_calib_complete),
.periodic_rd_r (periodic_rd_r),
.use_addr (use_addr),
.rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]),
.idle_r (idle_r[nBANK_MACHS-1:0]),
.ordered_r (ordered_r[nBANK_MACHS-1:0]),
.ordered_issued (ordered_issued[nBANK_MACHS-1:0]),
.head_r (head_r[nBANK_MACHS-1:0]),
.end_rtp (end_rtp[nBANK_MACHS-1:0]),
.passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]),
.op_exit_req (op_exit_req[nBANK_MACHS-1:0]),
.start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_hit (maint_hit[nBANK_MACHS-1:0]),
.bm_end (bm_end[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
mig_7series_v1_9_arb_mux #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nRAS (nRAS),
.nRCD (nRCD),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nSLOTS (nSLOTS),
.nWR (nWR),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_mux0
(.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input.
/*AUTOINST*/
// Outputs
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_valid_r (rnk_config_valid_r),
.mc_cas_slot (mc_cas_slot),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.sent_col_r (sent_col_r),
.sent_row (sent_row),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.clk (clk),
.rst (rst));
endmodule // bank_mach
|
// Must be run with -gspecify
module top;
reg passed;
reg a, b;
wire y;
initial begin
passed = 1'b1;
a = 0;
b = 1;
#2 if (y !== 1'bx && y !== 1'bz) begin
$display("Failed: Initial value, expected 1'bx, got %b", y);
passed = 1'b0;
end
#2 if (y !== 1'b0) begin
$display("Failed: Initial value propagation, expected 1'b0, got %b", y);
passed = 1'b0;
end
a = 1;
#2 if (y !== 1'b0) begin
$display("Failed: to hold initial value, expected 1'b0, got %b", y);
passed = 1'b0;
end
#2 if (y !== 1'b1) begin
$display("Failed: Final value propagation, expected 1'b1, got %b", y);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
my_and dut(y, a, b);
endmodule
module my_and(output wire y, input wire a, b);
specify
specparam ta = 1;
specparam tb = 2;
endspecify
// A specparam is just like a parameter in this context. In reality
// they can be overridden at run-time so the following should really
// be an expression instead of just a constant 3, but for now 3 would
// be acceptable. Specparams and the specify block need a major rework.
assign #(ta+tb) y = a & b;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [4:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 12,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 25,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 4800,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20833,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.010000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.01000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4800"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O221AI_PP_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test #(16,2) test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hf9b3a5000165ed38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
parameter N = 0;
parameter PASSDOWN = 1;
add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]),
.out (out));
endmodule
module add (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter PASSDOWN = 9999;
input [31:0] in;
output [31:0] out;
wire out = in + PASSDOWN;
endmodule
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:21:38 02/02/2015
// Design Name:
// Module Name: crypto_sha256_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module crypto_sha256_top (
input wb_clk_i,
input wb_rst_i,
input core_clk,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o,
output wb_rty_o,
output [31:0] wb_dat_o
);
wire [255:0] wb2core_state, core2wb_state;
wire [511:0] wb2core_data;
wire load_clk1, busy_clk2;
reg [1:0] busy_clk1_buf;
reg [1:0] load_clk2_buf;
wire busy_clk1 = busy_clk1_buf[1];
wire load_clk2 = load_clk2_buf[1];
wb_sha256_ctrl wb_ctrl_inst (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_adr_i[6:0]),
.wb_dat_i(wb_dat_i),
.wb_sel_i(wb_sel_i),
.wb_we_i(wb_we_i),
.wb_bte_i(wb_bte_i),
.wb_cti_i(wb_cti_i),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_ack_o(wb_ack_o),
.wb_err_o(wb_err_o),
.wb_rty_o(wb_rty_o),
.wb_dat_o(wb_dat_o),
.load_o(load_clk1),
.state_o(wb2core_state),
.data_o(wb2core_data),
.busy_i(busy_clk1),
.state_i(core2wb_state)
);
always @(posedge wb_clk_i) busy_clk1_buf <= { busy_clk1_buf[0], busy_clk2 };
always @(posedge core_clk) load_clk2_buf <= { load_clk2_buf[0], load_clk1 };
// Adding (* use_dsp48 = "yes" *) allows DSP48's for addition
// However this is slower and only saves 400 LUTs
sha256_core sha256_inst (
.clk(core_clk),
.load_i(load_clk2),
.data_i(wb2core_data),
.state_i(wb2core_state),
.state_o(core2wb_state),
.busy_o(busy_clk2)
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_c3fe_slot_0_w_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_cols_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_cols_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_cols_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_cols_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// This is just a test module.
module comm (
input hash_clk,
input rx_new_nonce,
input [31:0] rx_golden_nonce,
output [255:0] tx_midstate,
output [95:0] tx_data
);
reg [351:0] jtag_data_shift = 352'd0;
reg [255:0] midstate = 256'd0;
reg [95:0] data = 96'd0;
assign tx_midstate = midstate;
assign tx_data = data;
reg [31:0] golden_out = 32'd0;
reg [3:0] golden_count = 3'd0;
reg read = 1'b0;
wire [8:0] jtag_data;
wire full, empty;
reg [5:0] jtag_data_count = 6'd0;
wire golden_writing = golden_count[0];
jtag_fifo jtag_fifo_blk (
.rx_clk (hash_clk),
.rx_data ({golden_count, golden_out[7:0]}),
.wr_en (golden_writing & ~full),
.rd_en (read),
.tx_data (jtag_data),
.tx_full (full),
.tx_empty (empty)
);
always @ (posedge hash_clk)
begin
// Writing to JTAG
if (!golden_writing & rx_new_nonce)
begin
golden_out <= rx_golden_nonce;
golden_count <= 4'b1111;
end
else if (golden_writing & !full)
begin
golden_out <= golden_out >> 8;
golden_count <= {1'b0, golden_count[3:1]};
end
// Reading from JTAG
if (!empty & !read)
read <= 1'b1;
if (read)
begin
read <= 1'b0;
jtag_data_shift <= {jtag_data_shift[343:0], jtag_data[7:0]};
if (jtag_data[8] == 1'b0)
jtag_data_count <= 6'd1;
else if (jtag_data_count == 6'd43)
begin
jtag_data_count <= 6'd0;
{midstate, data} <= {jtag_data_shift[343:0], jtag_data[7:0]};
end
else
jtag_data_count <= jtag_data_count + 6'd1;
end
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_dipsw_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTGATE128_IDLE 2'b00
`define S_TXPORTGATE128_OPENING 2'b01
`define S_TXPORTGATE128_OPEN 2'b10
`define S_TXPORTGATE128_CLOSED 2'b11
`timescale 1ns/1ns
module tx_port_channel_gate_128 #(
parameter C_DATA_WIDTH = 9'd128,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
)
(
input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE128_IDLE, _rState=`S_TXPORTGATE128_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE128_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY)
);
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE128_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
case (rState)
`S_TXPORTGATE128_IDLE: begin // Write the len, off, last
_rPause = 0;
_rClosed = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, 64'd0, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE128_OPENING;
end
end
`S_TXPORTGATE128_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
else
_rState = `S_TXPORTGATE128_OPEN;
end
end
`S_TXPORTGATE128_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
end
`S_TXPORTGATE128_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE128_IDLE;
end
end
endcase
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CHNL_CLK),
.CONTROL(wControl0),
.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
.DATA({313'd0,
rChnlOff, // 31
rChnlLen, // 32
rChnlLast, // 1
rChnlTx, // 1
CHNL_TX_OFF, // 31
CHNL_TX_LEN, // 32
CHNL_TX_LAST, // 1
CHNL_TX, // 1
wFifoFull, // 1
rFifoData, // 65
rFifoWen, // 1
rState}) // 2
);
*/
endmodule
|
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [8:0] addr;
wire [35:0] ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(9),
.PHASE_SHIFT(3)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(| ram_out),
.ram_in(ram_in)
);
RAMB36E1 #(
.RAM_MODE("TDP"), // True dual-port mode (2x2 in/out ports)
.READ_WIDTH_A(36),
.WRITE_WIDTH_B(36),
.WRITE_MODE_B("WRITE_FIRST") // transparent write
) ram (
// read from A
.CLKARDCLK(clk), // shared clock
.ENARDEN(1'b1), // enable read
.REGCEAREGCE(1'b0), // disable clock to the output register (not using it)
.RSTRAMARSTRAM(1'b0), // don't reset output latch
.RSTREGARSTREG(1'b0), // don't reset output register
.ADDRARDADDR({~sw[0], addr, 5'b0}), // use upper 10 bits, lower 5 are zero
.WEA(4'h0), // disable writing from this half
.DIADI(32'h0000_0000), // no input
.DIPADIP(4'h0), // no input
.DOADO(ram_out[31:0]), // 32 bit output
.DOPADOP(ram_out[35:32]), // 4 more output bits
// write to B
.CLKBWRCLK(clk), // shared clock
.ENBWREN(1'b1), // enable write
.REGCEB(1'b0), // disable clock to the output register (no output)
.RSTRAMB(1'b0), // don't reset the output latch
.RSTREGB(1'b0), // don't reset the output register
.ADDRBWRADDR({sw[0], addr, 5'b0}), // use upper 10 bits, lower 5 are zero
.DIBDI({32{ram_in}}), // 32 bit input
.DIPBDIP({4{ram_in}}), // 4 more input bits
.WEBWE(8'h0f) // enable writing all 4 bytes-wide (32 bits)
);
endmodule
|
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
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// -- international copyright and other intellectual property
// -- laws.
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// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI data fifo module:
// 5-channel memory-mapped AXI4 interfaces.
// SRL or BRAM based FIFO on AXI W and/or R channels.
// FIFO to accommodate various data flow rates through the AXI interconnect
//
// Verilog-standard: Verilog 2001
//-----------------------------------------------------------------------------
//
// Structure:
// axi_data_fifo
// fifo_generator
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axi_data_fifo #
(
parameter C_FAMILY = "virtex7",
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_WRITE_FIFO_DEPTH = 0, // Range: (0, 32, 512)
parameter C_AXI_WRITE_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based,
// "bram" = BRAM based
parameter integer C_AXI_WRITE_FIFO_DELAY = 0, // 0 = No, 1 = Yes
// Indicates whether AWVALID and WVALID assertion is delayed until:
// a. the corresponding WLAST is stored in the FIFO, or
// b. no WLAST is stored and the FIFO is full.
// 0 means AW channel is pass-through and
// WVALID is asserted whenever FIFO is not empty.
parameter integer C_AXI_READ_FIFO_DEPTH = 0, // Range: (0, 32, 512)
parameter C_AXI_READ_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based,
// "bram" = BRAM based
parameter integer C_AXI_READ_FIFO_DELAY = 0) // 0 = No, 1 = Yes
// Indicates whether ARVALID assertion is delayed until the
// the remaining vacancy of the FIFO is at least the burst length
// as indicated by ARLEN.
// 0 means AR channel is pass-through.
// System Signals
(input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready);
localparam integer P_WIDTH_RACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_ARUSER_WIDTH;
localparam integer P_WIDTH_WACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_AWUSER_WIDTH;
localparam integer P_WIDTH_RDCH = 1 + 2 + C_AXI_DATA_WIDTH + C_AXI_ID_WIDTH + C_AXI_RUSER_WIDTH;
localparam integer P_WIDTH_WDCH = 1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+((C_AXI_PROTOCOL==1)?C_AXI_ID_WIDTH:0)+C_AXI_WUSER_WIDTH;
localparam integer P_WIDTH_WRCH = 2 + C_AXI_ID_WIDTH + C_AXI_BUSER_WIDTH;
localparam P_PRIM_FIFO_TYPE = "512x72" ;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_WRITE_FIFO_DEPTH_LOG = (C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1;
localparam integer P_READ_FIFO_DEPTH_LOG = (C_AXI_READ_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1;
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
generate
if (((C_AXI_WRITE_FIFO_DEPTH == 0) && (C_AXI_READ_FIFO_DEPTH == 0)) || (C_AXI_PROTOCOL == P_AXILITE)) begin : gen_bypass
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_axi_awvalid;
assign s_axi_awready = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_wready = m_axi_wready;
assign s_axi_bid = m_axi_bid;
assign s_axi_bresp = m_axi_bresp;
assign s_axi_buser = m_axi_buser;
assign s_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = s_axi_bready;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_axi_arvalid;
assign s_axi_arready = m_axi_arready;
assign s_axi_rid = m_axi_rid;
assign s_axi_rdata = m_axi_rdata;
assign s_axi_rresp = m_axi_rresp;
assign s_axi_rlast = m_axi_rlast;
assign s_axi_ruser = m_axi_ruser;
assign s_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = s_axi_rready;
end else begin : gen_fifo
wire [4-1:0] s_axi_awregion_i;
wire [4-1:0] s_axi_arregion_i;
wire [4-1:0] m_axi_awregion_i;
wire [4-1:0] m_axi_arregion_i;
wire [C_AXI_ID_WIDTH-1:0] s_axi_wid_i;
wire [C_AXI_ID_WIDTH-1:0] m_axi_wid_i;
assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_awregion;
assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_arregion;
assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_awregion_i;
assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_arregion_i;
assign s_axi_wid_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_wid : {C_AXI_ID_WIDTH{1'b0}};
assign m_axi_wid = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_wid_i : {C_AXI_ID_WIDTH{1'b0}};
fifo_generator_v12_0 #(
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : 3),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4),
.C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2),
.C_HAS_AXI_ARUSER(1),
.C_HAS_AXI_AWUSER(1),
.C_HAS_AXI_BUSER(1),
.C_HAS_AXI_RUSER(1),
.C_HAS_AXI_WUSER(1),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),
.C_DIN_WIDTH_RACH(P_WIDTH_RACH),
.C_DIN_WIDTH_RDCH(P_WIDTH_RDCH),
.C_DIN_WIDTH_WACH(P_WIDTH_WACH),
.C_DIN_WIDTH_WDCH(P_WIDTH_WDCH),
.C_DIN_WIDTH_WRCH(P_WIDTH_WDCH),
.C_RACH_TYPE(((C_AXI_READ_FIFO_DEPTH != 0) && C_AXI_READ_FIFO_DELAY) ? 0 : 2),
.C_WACH_TYPE(((C_AXI_WRITE_FIFO_DEPTH != 0) && C_AXI_WRITE_FIFO_DELAY) ? 0 : 2),
.C_WDCH_TYPE((C_AXI_WRITE_FIFO_DEPTH != 0) ? 0 : 2),
.C_RDCH_TYPE((C_AXI_READ_FIFO_DEPTH != 0) ? 0 : 2),
.C_WRCH_TYPE(2),
.C_COMMON_CLOCK(1),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(C_AXI_READ_FIFO_DELAY ? 1 : 0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(C_AXI_WRITE_FIFO_DELAY ? 1 : 0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DIN_WIDTH_AXIS(1),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(2),
.C_IMPLEMENTATION_TYPE_RDCH((C_AXI_READ_FIFO_TYPE == "bram") ? 1 : 2),
.C_IMPLEMENTATION_TYPE_WACH(2),
.C_IMPLEMENTATION_TYPE_WDCH((C_AXI_WRITE_FIFO_TYPE == "bram") ? 1 : 2),
.C_IMPLEMENTATION_TYPE_WRCH(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE(P_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(510),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(510),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(32),
.C_WR_DEPTH_RDCH(C_AXI_READ_FIFO_DEPTH),
.C_WR_DEPTH_WACH(32),
.C_WR_DEPTH_WDCH(C_AXI_WRITE_FIFO_DEPTH),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(5),
.C_WR_PNTR_WIDTH_RDCH((C_AXI_READ_FIFO_DEPTH> 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1),
.C_WR_PNTR_WIDTH_WACH(5),
.C_WR_PNTR_WIDTH_WDCH((C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.s_aclk(aclk),
.s_aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awregion(s_axi_awregion_i),
.s_axi_awuser(s_axi_awuser),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid_i),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awregion(m_axi_awregion_i),
.m_axi_awuser(m_axi_awuser),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid_i),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arregion(s_axi_arregion_i),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arregion(m_axi_arregion_i),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
.m_aclk(aclk),
.m_aclk_en(1'b1),
.s_aclk_en(1'b1),
.s_axi_wuser(s_axi_wuser),
.s_axi_buser(s_axi_buser),
.m_axi_wuser(m_axi_wuser),
.m_axi_buser(m_axi_buser),
.s_axi_aruser(s_axi_aruser),
.s_axi_ruser(s_axi_ruser),
.m_axi_aruser(m_axi_aruser),
.m_axi_ruser(m_axi_ruser),
.almost_empty(),
.almost_full(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(5'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(5'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(5'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(5'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),
.axi_r_prog_full(),
.axi_r_prog_full_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),
.axi_w_prog_full(),
.axi_w_prog_full_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(),
.dbiterr(),
.din(18'b0),
.dout(),
.empty(),
.full(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full(),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.rd_clk(1'b0),
.rd_data_count(),
.rd_en(1'b0),
.rd_rst(1'b0),
.rst(1'b0),
.sbiterr(),
.srst(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_clk(1'b0),
.wr_data_count(),
.wr_en(1'b0),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end
endgenerate
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_channel_1 (
// rst and clocks
rst,
ref_clk,
cpll_pd,
cpll_rst,
qpll_clk,
qpll_ref_clk,
cpll_locked,
// receive
rx_p,
rx_n,
rx_sys_clk_sel,
rx_out_clk_sel,
rx_out_clk,
rx_rst_done,
rx_clk,
rx_charisk,
rx_disperr,
rx_notintable,
rx_data,
rx_rate,
rx_comma_align_enb,
// transmit
tx_p,
tx_n,
tx_sys_clk_sel,
tx_out_clk_sel,
tx_out_clk,
tx_rst_done,
tx_clk,
tx_charisk,
tx_data,
// drp interface
drp_clk,
drp_en,
drp_addr,
drp_wr,
drp_wdata,
drp_rdata,
drp_ready,
// monitor signals
mon_trigger,
mon_data);
// parameters
parameter CPLL_FBDIV = 2;
parameter RX_OUT_DIV = 1;
parameter TX_OUT_DIV = 1;
parameter RX_CLK25_DIV = 10;
parameter TX_CLK25_DIV = 10;
parameter PMA_RSV = 32'h00018480;
parameter RX_CDR_CFG = 72'h03000023ff20400020;
localparam RX_RATE_P = 0;
// rst and clocks
input rst;
input ref_clk;
input cpll_pd;
input cpll_rst;
input qpll_clk;
input qpll_ref_clk;
output cpll_locked;
// receive
input rx_p;
input rx_n;
input [ 1:0] rx_sys_clk_sel;
input [ 2:0] rx_out_clk_sel;
output rx_out_clk;
output rx_rst_done;
input rx_clk;
output [ 3:0] rx_charisk;
output [ 3:0] rx_disperr;
output [ 3:0] rx_notintable;
output [31:0] rx_data;
output [ 7:0] rx_rate;
input rx_comma_align_enb;
// transmit
output tx_p;
output tx_n;
input [ 1:0] tx_sys_clk_sel;
input [ 2:0] tx_out_clk_sel;
output tx_out_clk;
output tx_rst_done;
input tx_clk;
input [ 3:0] tx_charisk;
input [31:0] tx_data;
// drp interface
input drp_clk;
input drp_en;
input [11:0] drp_addr;
input drp_wr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
// monitor signals
output mon_trigger;
output [49:0] mon_data;
// internal signals
wire rx_ilas_f_s;
wire rx_ilas_q_s;
wire rx_ilas_a_s;
wire rx_ilas_r_s;
wire rx_cgs_k_s;
wire [ 3:0] rx_valid_k_s;
wire rx_valid_k_1_s;
wire [ 3:0] rx_charisk_open_s;
wire [ 3:0] rx_disperr_open_s;
wire [ 3:0] rx_notintable_open_s;
wire [31:0] rx_data_open_s;
// monitor interface
assign mon_data[31: 0] = rx_data;
assign mon_data[35:32] = rx_notintable;
assign mon_data[39:36] = rx_disperr;
assign mon_data[43:40] = rx_charisk;
assign mon_data[44:44] = rx_valid_k_1_s;
assign mon_data[45:45] = rx_cgs_k_s;
assign mon_data[46:46] = rx_ilas_r_s;
assign mon_data[47:47] = rx_ilas_a_s;
assign mon_data[48:48] = rx_ilas_q_s;
assign mon_data[49:49] = rx_ilas_f_s;
assign mon_trigger = rx_valid_k_1_s;
// ilas frame characters
assign rx_ilas_f_s =
(((rx_data[31:24] == 8'hfc) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'hfc) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'hfc) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'hfc) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_q_s =
(((rx_data[31:24] == 8'h9c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h9c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h9c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h9c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_a_s =
(((rx_data[31:24] == 8'h7c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h7c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h7c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h7c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_ilas_r_s =
(((rx_data[31:24] == 8'h1c) && (rx_valid_k_s[ 3] == 1'b1)) ||
((rx_data[23:16] == 8'h1c) && (rx_valid_k_s[ 2] == 1'b1)) ||
((rx_data[15: 8] == 8'h1c) && (rx_valid_k_s[ 1] == 1'b1)) ||
((rx_data[ 7: 0] == 8'h1c) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
assign rx_cgs_k_s =
(((rx_data[31:24] == 8'hbc) && (rx_valid_k_s[ 3] == 1'b1)) &&
((rx_data[23:16] == 8'hbc) && (rx_valid_k_s[ 2] == 1'b1)) &&
((rx_data[15: 8] == 8'hbc) && (rx_valid_k_s[ 1] == 1'b1)) &&
((rx_data[ 7: 0] == 8'hbc) && (rx_valid_k_s[ 0] == 1'b1))) ? 1'b1 : 1'b0;
// validate all characters
assign rx_valid_k_s = rx_charisk & (~rx_disperr) & (~rx_notintable);
assign rx_valid_k_1_s = (rx_valid_k_s == 4'd0) ? 1'b0 : 1'b1;
// rate
assign rx_rate = (RX_RATE_P == 0) ? RX_OUT_DIV :
(RX_RATE_P == 1) ? 8'h01 :
(RX_RATE_P == 2) ? 8'h02 :
(RX_RATE_P == 3) ? 8'h04 :
(RX_RATE_P == 4) ? 8'h08 :
(RX_RATE_P == 5) ? 8'h10 : 8'h00;
// instantiations
GTXE2_CHANNEL #(
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_CPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("3.0"),
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
.ALIGN_COMMA_WORD (1),
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.SHOW_REALIGN_COMMA ("TRUE"),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RX_SIG_VALID_DLY (10),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (35),
.CLK_COR_MIN_LAT (31),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_LEN (1),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_1_1 (10'b0000000000),
.CLK_COR_SEQ_1_2 (10'b0000000000),
.CLK_COR_SEQ_1_3 (10'b0000000000),
.CLK_COR_SEQ_1_4 (10'b0000000000),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0000000000),
.CLK_COR_SEQ_2_2 (10'b0000000000),
.CLK_COR_SEQ_2_3 (10'b0000000000),
.CLK_COR_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (7),
.CHAN_BOND_SEQ_LEN (1),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
.ES_HORZ_OFFSET (12'h000),
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER (80'h00000000000000000000),
.ES_QUAL_MASK (80'h00000000000000000000),
.ES_SDATA_MASK (80'h00000000000000000000),
.ES_VERT_OFFSET (9'b000000000),
.RX_DATA_WIDTH (40),
.OUTREFCLK_SEL_INV (2'b11),
.PMA_RSV (PMA_RSV),
.PMA_RSV2 (16'h2070),
.PMA_RSV3 (2'b00),
.PMA_RSV4 (32'h00000000),
.RX_BIAS_CFG (12'b000000000100),
.DMONITOR_CFG (24'h000A00),
.RX_CM_SEL (2'b11),
.RX_CM_TRIM (3'b010),
.RX_DEBUG_CFG (12'b000000000000),
.RX_OS_CFG (13'b0000010000000),
.TERM_RCAL_CFG (5'b10000),
.TERM_RCAL_OVRD (1'b0),
.TST_RSV (32'h00000000),
.RX_CLK25_DIV (RX_CLK25_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.UCODEER_CLR (1'b0),
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD_ATTR (48'h000000000000),
.RXBUF_ADDR_MODE ("FULL"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RX_BUFFER_CFG (6'b000000),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.RXBUFRESET_TIME (5'b00001),
.RXBUF_THRESH_OVFLW (61),
.RXBUF_THRESH_OVRD ("FALSE"),
.RXBUF_THRESH_UNDFLW (4),
.RXDLY_CFG (16'h001F),
.RXDLY_LCFG (9'h030),
.RXDLY_TAP_CFG (16'h0000),
.RXPH_CFG (24'h000000),
.RXPHDLY_CFG (24'h084020),
.RXPH_MONITOR_SEL (5'b00000),
.RX_XCLK_SEL ("RXREC"),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RXCDR_CFG (RX_CDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCDR_LOCK_CFG (6'b010101),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXISCANRESET_TIME (5'b00001),
.RXPCSRESET_TIME (5'b00001),
.RXPMARESET_TIME (5'b00011),
.RXOOB_CFG (7'b0000110),
.RXGEARBOX_EN ("FALSE"),
.GEARBOX_MODE (3'b000),
.RXPRBS_ERR_LOOPBACK (1'b0),
.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h3c),
.PD_TRANS_TIME_TO_P2 (8'h64),
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
.SATA_BURST_SEQ_LEN (4'b1111),
.SATA_BURST_VAL (3'b100),
.SATA_EIDLE_VAL (3'b100),
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
.TRANS_TIME_RATE (8'h0E),
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'h001F),
.TXDLY_LCFG (9'h030),
.TXDLY_TAP_CFG (16'h0000),
.TXPH_CFG (16'h0780),
.TXPHDLY_CFG (24'h084020),
.TXPH_MONITOR_SEL (5'b00000),
.TX_XCLK_SEL ("TXOUT"),
.TX_DATA_WIDTH (40),
.TX_DEEMPH0 (5'b00000),
.TX_DEEMPH1 (5'b00000),
.TX_EIDLE_ASSERT_DELAY (3'b110),
.TX_EIDLE_DEASSERT_DELAY (3'b100),
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_DRIVE_MODE ("DIRECT"),
.TX_MARGIN_FULL_0 (7'b1001110),
.TX_MARGIN_FULL_1 (7'b1001001),
.TX_MARGIN_FULL_2 (7'b1000101),
.TX_MARGIN_FULL_3 (7'b1000010),
.TX_MARGIN_FULL_4 (7'b1000000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000100),
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),
.TXGEARBOX_EN ("FALSE"),
.TXPCSRESET_TIME (5'b00001),
.TXPMARESET_TIME (5'b00001),
.TX_RXDETECT_CFG (14'h1832),
.TX_RXDETECT_REF (3'b100),
.CPLL_CFG (24'hBC07DC),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (5),
.CPLL_INIT_CFG (24'h00001E),
.CPLL_LOCK_CFG (16'h01E8),
.CPLL_REFCLK_DIV (1),
.RXOUT_DIV (RX_OUT_DIV),
.TXOUT_DIV (TX_OUT_DIV),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.RXDFELPMRESET_TIME (7'b0001111),
.RXLPM_HF_CFG (14'b00000011110000),
.RXLPM_LF_CFG (14'b00000011110000),
.RX_DFE_GAIN_CFG (23'h020FEA),
.RX_DFE_H2_CFG (12'b000000000000),
.RX_DFE_H3_CFG (12'b000001000000),
.RX_DFE_H4_CFG (11'b00011110000),
.RX_DFE_H5_CFG (11'b00011100000),
.RX_DFE_KL_CFG (13'b0000011111110),
.RX_DFE_LPM_CFG (16'h0954),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DFE_UT_CFG (17'b10001111000000000),
.RX_DFE_VP_CFG (17'b00011111100000011),
.RX_CLKMUX_PD (1'b1),
.TX_CLKMUX_PD (1'b1),
.RX_INT_DATAWIDTH (1),
.TX_INT_DATAWIDTH (1),
.TX_QPI_STATUS_EN (1'b0),
.RX_DFE_KL_CFG2 (32'h3010D90C),
.RX_DFE_XYD_CFG (13'b0001100010000),
.TX_PREDRIVER_MODE (1'b0))
i_gtxe2_channel (
.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked),
.CPLLLOCKDETCLK (drp_clk),
.CPLLLOCKEN (1'd1),
.CPLLPD (cpll_pd),
.CPLLREFCLKLOST (),
.CPLLREFCLKSEL (3'b001),
.CPLLRESET (cpll_rst),
.GTRSVD (16'b0000000000000000),
.PCSRSVDIN (16'b0000000000000000),
.PCSRSVDIN2 (5'b00000),
.PMARSVDIN (5'b00000),
.PMARSVDIN2 (5'b00000),
.TSTIN (20'b11111111111111111111),
.TSTOUT (),
.CLKRSVD (4'b0000),
.GTGREFCLK (1'd0),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTREFCLK0 (ref_clk),
.GTREFCLK1 (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.DRPADDR (drp_addr[8:0]),
.DRPCLK (drp_clk),
.DRPDI (drp_wdata),
.DRPDO (drp_rdata),
.DRPEN (drp_en),
.DRPRDY (drp_ready),
.DRPWE (drp_wr),
.GTREFCLKMONITOR (),
.QPLLCLK (qpll_clk),
.QPLLREFCLK (qpll_ref_clk),
.RXSYSCLKSEL (rx_sys_clk_sel),
.TXSYSCLKSEL (tx_sys_clk_sel),
.DMONITOROUT (),
.TX8B10BEN (1'd1),
.LOOPBACK (3'd0),
.PHYSTATUS (),
.RXRATE (RX_RATE_P),
.RXVALID (),
.RXPD (2'b00),
.TXPD (2'b00),
.SETERRSTATUS (1'd0),
.EYESCANRESET (1'd0),
.RXUSERRDY (1'd1),
.EYESCANDATAERROR (),
.EYESCANMODE (1'd0),
.EYESCANTRIGGER (1'd0),
.RXCDRFREQRESET (1'd0),
.RXCDRHOLD (1'd0),
.RXCDRLOCK (),
.RXCDROVRDEN (1'd0),
.RXCDRRESET (1'd0),
.RXCDRRESETRSV (1'd0),
.RXCLKCORCNT (),
.RX8B10BEN (1'd1),
.RXUSRCLK (rx_clk),
.RXUSRCLK2 (rx_clk),
.RXDATA ({rx_data_open_s, rx_data}),
.RXPRBSERR (),
.RXPRBSSEL (3'd0),
.RXPRBSCNTRESET (1'd0),
.RXDFEXYDEN (1'd0),
.RXDFEXYDHOLD (1'd0),
.RXDFEXYDOVRDEN (1'd0),
.RXDISPERR ({rx_disperr_open_s, rx_disperr}),
.RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}),
.GTXRXP (rx_p),
.GTXRXN (rx_n),
.RXBUFRESET (1'd0),
.RXBUFSTATUS (),
.RXDDIEN (1'd0),
.RXDLYBYPASS (1'd1),
.RXDLYEN (1'd0),
.RXDLYOVRDEN (1'd0),
.RXDLYSRESET (1'd0),
.RXDLYSRESETDONE (),
.RXPHALIGN (1'd0),
.RXPHALIGNDONE (),
.RXPHALIGNEN (1'd0),
.RXPHDLYPD (1'd0),
.RXPHDLYRESET (1'd0),
.RXPHMONITOR (),
.RXPHOVRDEN (1'd0),
.RXPHSLIPMONITOR (),
.RXSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
.RXCOMMADET (),
.RXCOMMADETEN (1'd1),
.RXMCOMMAALIGNEN (rx_comma_align_enb),
.RXPCOMMAALIGNEN (rx_comma_align_enb),
.RXCHANBONDSEQ (),
.RXCHBONDEN (1'd0),
.RXCHBONDLEVEL (3'd0),
.RXCHBONDMASTER (1'd1),
.RXCHBONDO (),
.RXCHBONDSLAVE (1'd0),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXDFEAGCHOLD (1'd0),
.RXDFEAGCOVRDEN (1'd0),
.RXDFECM1EN (1'd0),
.RXDFELFHOLD (1'd0),
.RXDFELFOVRDEN (1'd1),
.RXDFELPMRESET (1'd0),
.RXDFETAP2HOLD (1'd0),
.RXDFETAP2OVRDEN (1'd0),
.RXDFETAP3HOLD (1'd0),
.RXDFETAP3OVRDEN (1'd0),
.RXDFETAP4HOLD (1'd0),
.RXDFETAP4OVRDEN (1'd0),
.RXDFETAP5HOLD (1'd0),
.RXDFETAP5OVRDEN (1'd0),
.RXDFEUTHOLD (1'd0),
.RXDFEUTOVRDEN (1'd0),
.RXDFEVPHOLD (1'd0),
.RXDFEVPOVRDEN (1'd0),
.RXDFEVSEN (1'd0),
.RXLPMLFKLOVRDEN (1'd0),
.RXMONITOROUT (),
.RXMONITORSEL (2'd0),
.RXOSHOLD (1'd0),
.RXOSOVRDEN (1'd0),
.RXLPMHFHOLD (1'd0),
.RXLPMHFOVRDEN (1'd0),
.RXLPMLFHOLD (1'd0),
.RXRATEDONE (),
.RXOUTCLK (rx_out_clk),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXOUTCLKSEL (rx_out_clk_sel),
.RXDATAVALID (),
.RXHEADER (),
.RXHEADERVALID (),
.RXSTARTOFSEQ (),
.RXGEARBOXSLIP (1'd0),
.GTRXRESET (rst),
.RXOOBRESET (1'd0),
.RXPCSRESET (1'd0),
.RXPMARESET (1'd0),
.RXLPMEN (1'd0),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXCOMINITDET (),
.RXELECIDLE (),
.RXELECIDLEMODE (2'b10),
.RXPOLARITY (1'd0),
.RXSLIDE (1'd0),
.RXCHARISCOMMA (),
.RXCHARISK ({rx_charisk_open_s, rx_charisk}),
.RXCHBONDI (5'd0),
.RXRESETDONE (rx_rst_done),
.RXQPIEN (1'd0),
.RXQPISENN (),
.RXQPISENP (),
.TXPHDLYTSTCLK (1'd0),
.TXPOSTCURSOR (5'd0),
.TXPOSTCURSORINV (1'd0),
.TXPRECURSOR (5'd0),
.TXPRECURSORINV (1'd0),
.TXQPIBIASEN (1'd0),
.TXQPISTRONGPDOWN (1'd0),
.TXQPIWEAKPUP (1'd0),
.CFGRESET (1'd0),
.GTTXRESET (rst),
.PCSRSVDOUT (),
.TXUSERRDY (1'b1),
.GTRESETSEL (1'd0),
.RESETOVRD (1'd0),
.TXCHARDISPMODE (8'd0),
.TXCHARDISPVAL (8'd0),
.TXUSRCLK (tx_clk),
.TXUSRCLK2 (tx_clk),
.TXELECIDLE (1'd0),
.TXMARGIN (3'd0),
.TXRATE (3'd0),
.TXSWING (1'd0),
.TXPRBSFORCEERR (1'd0),
.TXDLYBYPASS (1'd1),
.TXDLYEN (1'd0),
.TXDLYHOLD (1'd0),
.TXDLYOVRDEN (1'd0),
.TXDLYSRESET (1'd0),
.TXDLYSRESETDONE (),
.TXDLYUPDOWN (1'd0),
.TXPHALIGN (1'd0),
.TXPHALIGNDONE (),
.TXPHALIGNEN (1'd0),
.TXPHDLYPD (1'd0),
.TXPHDLYRESET (1'd0),
.TXPHINIT (1'd0),
.TXPHINITDONE (),
.TXPHOVRDEN (1'd0),
.TXBUFSTATUS (),
.TXBUFDIFFCTRL (3'b100),
.TXDEEMPH (1'd0),
.TXDIFFCTRL (4'b1000),
.TXDIFFPD (1'd0),
.TXINHIBIT (1'd0),
.TXMAINCURSOR (7'b0000000),
.TXPISOPD (1'd0),
.TXDATA ({32'd0, tx_data}),
.GTXTXP (tx_p),
.GTXTXN (tx_n),
.TXOUTCLK (tx_out_clk),
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
.TXOUTCLKSEL (tx_out_clk_sel),
.TXRATEDONE (),
.TXCHARISK ({4'd0, tx_charisk}),
.TXGEARBOXREADY (),
.TXHEADER (3'd0),
.TXSEQUENCE (7'd0),
.TXSTARTSEQ (1'd0),
.TXPCSRESET (1'd0),
.TXPMARESET (1'd0),
.TXRESETDONE (tx_rst_done),
.TXCOMFINISH (),
.TXCOMINIT (1'd0),
.TXCOMSAS (1'd0),
.TXCOMWAKE (1'd0),
.TXPDELECIDLEMODE (1'd0),
.TXPOLARITY (1'd0),
.TXDETECTRX (1'd0),
.TX8B10BBYPASS (8'd0),
.TXPRBSSEL (3'd0),
.TXQPISENP (),
.TXQPISENN ());
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dac vdma read
module ad_axis_dma_tx (
// vdma interface
dma_clk,
dma_rst,
dma_fs,
dma_valid,
dma_data,
dma_ready,
dma_ovf,
dma_unf,
// dac interface
dac_clk,
dac_rst,
dac_rd,
dac_valid,
dac_data,
// processor interface
dma_frmcnt);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
localparam RDY_THRESHOLD_LO = 6'd40;
localparam RDY_THRESHOLD_HI = 6'd50;
// vdma interface
input dma_clk;
input dma_rst;
output dma_fs;
input dma_valid;
input [DW:0] dma_data;
output dma_ready;
output dma_ovf;
output dma_unf;
// dac interface
input dac_clk;
input dac_rst;
input dac_rd;
output dac_valid;
output [DW:0] dac_data;
// processor interface
input [31:0] dma_frmcnt;
// internal registers
reg dac_start_m1 = 'd0;
reg dac_start = 'd0;
reg dac_resync_m1 = 'd0;
reg dac_resync = 'd0;
reg [ 5:0] dac_raddr = 'd0;
reg [ 5:0] dac_raddr_g = 'd0;
reg dac_rd_d = 'd0;
reg dac_rd_2d = 'd0;
reg dac_valid = 'd0;
reg [DW:0] dac_data = 'd0;
reg [31:0] dma_clkcnt = 'd0;
reg dma_fs = 'd0;
reg [ 5:0] dma_raddr_g_m1 = 'd0;
reg [ 5:0] dma_raddr_g_m2 = 'd0;
reg [ 5:0] dma_raddr = 'd0;
reg [ 5:0] dma_addr_diff = 'd0;
reg dma_ready = 'd0;
reg dma_almost_full = 'd0;
reg dma_almost_empty = 'd0;
reg dma_ovf = 'd0;
reg dma_unf = 'd0;
reg dma_resync = 'd0;
reg dma_start = 'd0;
reg dma_wr = 'd0;
reg [ 5:0] dma_waddr = 'd0;
reg [DW:0] dma_wdata = 'd0;
// internal signals
wire dma_wr_s;
wire [ 6:0] dma_addr_diff_s;
wire dma_ovf_s;
wire dma_unf_s;
wire [DW:0] dac_rdata_s;
// binary to grey coversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// dac read interface
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_start_m1 <= 'd0;
dac_start <= 'd0;
dac_resync_m1 <= 'd0;
dac_resync <= 'd0;
end else begin
dac_start_m1 <= dma_start;
dac_start <= dac_start_m1;
dac_resync_m1 <= dma_resync;
dac_resync <= dac_resync_m1;
end
if ((dac_start == 1'b0) || (dac_resync == 1'b1) || (dac_rst == 1'b1)) begin
dac_raddr <= 6'd0;
end else if (dac_rd == 1'b1) begin
dac_raddr <= dac_raddr + 1'b1;
end
dac_raddr_g <= b2g(dac_raddr);
dac_rd_d <= dac_rd;
dac_rd_2d <= dac_rd_d;
dac_valid <= dac_rd_2d;
dac_data <= dac_rdata_s;
end
// generate fsync
always @(posedge dma_clk) begin
if ((dma_resync == 1'b1) || (dma_rst == 1'b1) || (dma_clkcnt >= dma_frmcnt)) begin
dma_clkcnt <= 16'd0;
end else begin
dma_clkcnt <= dma_clkcnt + 1'b1;
end
if (dma_clkcnt == 32'd1) begin
dma_fs <= 1'b1;
end else begin
dma_fs <= 1'b0;
end
end
// overflow or underflow status
assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0;
assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_raddr_g_m1 <= 'd0;
dma_raddr_g_m2 <= 'd0;
end else begin
dma_raddr_g_m1 <= dac_raddr_g;
dma_raddr_g_m2 <= dma_raddr_g_m1;
end
dma_raddr <= g2b(dma_raddr_g_m2);
dma_addr_diff <= dma_addr_diff_s[5:0];
if (dma_addr_diff >= RDY_THRESHOLD_HI) begin
dma_ready <= 1'b0;
end else if (dma_addr_diff <= RDY_THRESHOLD_LO) begin
dma_ready <= 1'b1;
end
if (dma_addr_diff > BUF_THRESHOLD_HI) begin
dma_almost_full <= 1'b1;
end else begin
dma_almost_full <= 1'b0;
end
if (dma_addr_diff < BUF_THRESHOLD_LO) begin
dma_almost_empty <= 1'b1;
end else begin
dma_almost_empty <= 1'b0;
end
dma_ovf <= dma_ovf_s;
dma_unf <= dma_unf_s;
dma_resync <= dma_ovf | dma_unf;
end
// vdma write
assign dma_wr_s = dma_valid & dma_ready;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_start <= 1'b0;
end else if (dma_wr_s == 1'b1) begin
dma_start <= 1'b1;
end
dma_wr <= dma_wr_s;
if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin
dma_waddr <= 6'd0;
end else if (dma_wr == 1'b1) begin
dma_waddr <= dma_waddr + 1'b1;
end
dma_wdata <= dma_data;
end
// memory
ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem (
.clka (dma_clk),
.wea (dma_wr),
.addra (dma_waddr),
.dina (dma_wdata),
.clkb (dac_clk),
.addrb (dac_raddr),
.doutb (dac_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [31:0] r32;
wire [3:0] w4;
wire [4:0] w5;
assign w4 = NUMONES_8 ( r32[7:0] );
assign w5 = NUMONES_16( r32[15:0] );
function [3:0] NUMONES_8;
input [7:0] i8;
reg [7:0] i8;
begin
NUMONES_8 = 4'b1;
end
endfunction // NUMONES_8
function [4:0] NUMONES_16;
input [15:0] i16;
reg [15:0] i16;
begin
NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] ));
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
r32 <= 32'h12345678;
end
if (cyc==2) begin
if (w4 !== 1) $stop;
if (w5 !== 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//
// Copyright (c) 2003 Launchbird Design Systems, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
// Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// Overview:
//
// Cordics (COordinate Rotation DIgital Computers) are used to calculate
// trigonometric functions and complex plane phase rotations.
// This vector mode cordic rotates any complex vector to the positive real axis.
// The resulting angle is the initial angle plus the angle of rotation.
//
// Interface:
//
// Synchronization:
// clock_c : Clock input.
// enable_i : Synchronous enable.
// reset_i : Synchronous reset.
//
// Inputs:
// real_i : Initial real component (signed).
// imag_i : Initial imaginary component (signed).
// angle_i : Initial angle (modulo 2PI).
//
// Outputs:
// real_o : Resulting real component (signed).
// imag_o : Resulting imaginary component (signed).
// angle_o : Resulting angle (modulo 2PI).
//
// Built In Parameters:
//
// Cordic Mode = Vector
// Vector Width = 18
// Angle Width = 18
// Cordic Stages = 18
//
// Resulting Pipeline Latency is 20 clock cycles.
//
//
//
// Generated by Confluence 0.3.0 -- Launchbird Design Systems, Inc. -- www.launchbird.com
//
// Interface
//
// Build Name : cf_cordic_v_18_18_18
// Clock Domains : clock_c
// Input : enable_i(1)
// Input : reset_i(1)
// Input : real_i(18)
// Input : imag_i(18)
// Input : ang_i(18)
// Output : real_o(18)
// Output : imag_o(18)
// Output : ang_o(18)
//
//
//
module cf_cordic_v_18_18_18 (clock_c, enable_i, reset_i, real_i, imag_i, ang_i, real_o, imag_o, ang_o);
input clock_c;
input enable_i;
input reset_i;
input [17:0] real_i;
input [17:0] imag_i;
input [17:0] ang_i;
output [17:0] real_o;
output [17:0] imag_o;
output [17:0] ang_o;
wire [17:0] n6;
wire n8;
wire n21;
wire [1:0] n22;
wire [2:0] n23;
wire [3:0] n24;
wire [4:0] n25;
wire [5:0] n26;
wire [6:0] n27;
wire [7:0] n28;
wire [8:0] n29;
wire [9:0] n30;
wire [10:0] n31;
wire [11:0] n32;
wire [12:0] n33;
wire [13:0] n34;
wire [14:0] n35;
wire [15:0] n36;
wire [16:0] n37;
wire [17:0] n38;
wire n39;
wire n40;
wire [16:0] n41;
wire [17:0] n42;
wire n43;
wire n44;
wire [16:0] n45;
wire [17:0] n46;
wire n47;
wire [17:0] n48;
wire [17:0] n49;
wire n50;
wire n51;
wire [1:0] n52;
wire [2:0] n53;
wire [3:0] n54;
wire [4:0] n55;
wire [5:0] n56;
wire [6:0] n57;
wire [7:0] n58;
wire [8:0] n59;
wire [9:0] n60;
wire [10:0] n61;
wire [11:0] n62;
wire [12:0] n63;
wire [13:0] n64;
wire [14:0] n65;
wire [15:0] n66;
wire [16:0] n67;
wire [17:0] n68;
wire [17:0] n69;
wire [17:0] n70;
wire [17:0] n75;
wire [17:0] n80;
wire n97;
wire [1:0] n98;
wire [2:0] n99;
wire [3:0] n100;
wire [4:0] n101;
wire [5:0] n102;
wire [6:0] n103;
wire [7:0] n104;
wire [8:0] n105;
wire [9:0] n106;
wire [10:0] n107;
wire [11:0] n108;
wire [12:0] n109;
wire [13:0] n110;
wire [14:0] n111;
wire [15:0] n112;
wire [16:0] n113;
wire [17:0] n114;
wire n115;
wire n116;
wire [16:0] n117;
wire [17:0] n118;
wire n119;
wire n120;
wire [16:0] n121;
wire [17:0] n122;
wire n123;
wire n124;
wire [17:0] n126;
wire [17:0] n127;
wire [17:0] n128;
wire [17:0] n129;
wire [17:0] n130;
wire n135;
wire [17:0] n137;
wire [17:0] n138;
wire [17:0] n139;
wire [17:0] n140;
wire [17:0] n141;
wire [17:0] n146;
wire [17:0] n147;
wire [17:0] n148;
wire [17:0] n149;
wire n166;
wire [1:0] n167;
wire [2:0] n168;
wire [3:0] n169;
wire [4:0] n170;
wire [5:0] n171;
wire [6:0] n172;
wire [7:0] n173;
wire [8:0] n174;
wire [9:0] n175;
wire [10:0] n176;
wire [11:0] n177;
wire [12:0] n178;
wire [13:0] n179;
wire [14:0] n180;
wire [15:0] n181;
wire [16:0] n182;
wire [17:0] n183;
wire n184;
wire n185;
wire [16:0] n186;
wire [17:0] n187;
wire n188;
wire n189;
wire [16:0] n190;
wire [17:0] n191;
wire n192;
wire n193;
wire n194;
wire n195;
wire [16:0] n196;
wire [17:0] n197;
wire [17:0] n198;
wire [17:0] n199;
wire [17:0] n200;
wire n205;
wire n206;
wire n207;
wire [16:0] n208;
wire [17:0] n209;
wire [17:0] n210;
wire [17:0] n211;
wire [17:0] n212;
wire [17:0] n217;
wire [17:0] n218;
wire [17:0] n219;
wire [17:0] n220;
wire n237;
wire [1:0] n238;
wire [2:0] n239;
wire [3:0] n240;
wire [4:0] n241;
wire [5:0] n242;
wire [6:0] n243;
wire [7:0] n244;
wire [8:0] n245;
wire [9:0] n246;
wire [10:0] n247;
wire [11:0] n248;
wire [12:0] n249;
wire [13:0] n250;
wire [14:0] n251;
wire [15:0] n252;
wire [16:0] n253;
wire [17:0] n254;
wire n255;
wire n256;
wire [16:0] n257;
wire [17:0] n258;
wire n259;
wire n260;
wire [16:0] n261;
wire [17:0] n262;
wire n263;
wire n264;
wire n265;
wire n266;
wire [1:0] n267;
wire [15:0] n268;
wire [17:0] n269;
wire [17:0] n270;
wire [17:0] n271;
wire [17:0] n272;
wire n277;
wire n278;
wire n279;
wire [1:0] n280;
wire [15:0] n281;
wire [17:0] n282;
wire [17:0] n283;
wire [17:0] n284;
wire [17:0] n285;
wire [17:0] n290;
wire [17:0] n291;
wire [17:0] n292;
wire [17:0] n293;
wire n310;
wire [1:0] n311;
wire [2:0] n312;
wire [3:0] n313;
wire [4:0] n314;
wire [5:0] n315;
wire [6:0] n316;
wire [7:0] n317;
wire [8:0] n318;
wire [9:0] n319;
wire [10:0] n320;
wire [11:0] n321;
wire [12:0] n322;
wire [13:0] n323;
wire [14:0] n324;
wire [15:0] n325;
wire [16:0] n326;
wire [17:0] n327;
wire n328;
wire n329;
wire [16:0] n330;
wire [17:0] n331;
wire n332;
wire n333;
wire [16:0] n334;
wire [17:0] n335;
wire n336;
wire n337;
wire n338;
wire n339;
wire [1:0] n340;
wire [2:0] n341;
wire [14:0] n342;
wire [17:0] n343;
wire [17:0] n344;
wire [17:0] n345;
wire [17:0] n346;
wire n351;
wire n352;
wire n353;
wire [1:0] n354;
wire [2:0] n355;
wire [14:0] n356;
wire [17:0] n357;
wire [17:0] n358;
wire [17:0] n359;
wire [17:0] n360;
wire [17:0] n365;
wire [17:0] n366;
wire [17:0] n367;
wire [17:0] n368;
wire n385;
wire [1:0] n386;
wire [2:0] n387;
wire [3:0] n388;
wire [4:0] n389;
wire [5:0] n390;
wire [6:0] n391;
wire [7:0] n392;
wire [8:0] n393;
wire [9:0] n394;
wire [10:0] n395;
wire [11:0] n396;
wire [12:0] n397;
wire [13:0] n398;
wire [14:0] n399;
wire [15:0] n400;
wire [16:0] n401;
wire [17:0] n402;
wire n403;
wire n404;
wire [16:0] n405;
wire [17:0] n406;
wire n407;
wire n408;
wire [16:0] n409;
wire [17:0] n410;
wire n411;
wire n412;
wire n413;
wire n414;
wire [1:0] n415;
wire [2:0] n416;
wire [3:0] n417;
wire [13:0] n418;
wire [17:0] n419;
wire [17:0] n420;
wire [17:0] n421;
wire [17:0] n422;
wire n427;
wire n428;
wire n429;
wire [1:0] n430;
wire [2:0] n431;
wire [3:0] n432;
wire [13:0] n433;
wire [17:0] n434;
wire [17:0] n435;
wire [17:0] n436;
wire [17:0] n437;
wire [17:0] n442;
wire [17:0] n443;
wire [17:0] n444;
wire [17:0] n445;
wire n462;
wire [1:0] n463;
wire [2:0] n464;
wire [3:0] n465;
wire [4:0] n466;
wire [5:0] n467;
wire [6:0] n468;
wire [7:0] n469;
wire [8:0] n470;
wire [9:0] n471;
wire [10:0] n472;
wire [11:0] n473;
wire [12:0] n474;
wire [13:0] n475;
wire [14:0] n476;
wire [15:0] n477;
wire [16:0] n478;
wire [17:0] n479;
wire n480;
wire n481;
wire [16:0] n482;
wire [17:0] n483;
wire n484;
wire n485;
wire [16:0] n486;
wire [17:0] n487;
wire n488;
wire n489;
wire n490;
wire n491;
wire [1:0] n492;
wire [2:0] n493;
wire [3:0] n494;
wire [4:0] n495;
wire [12:0] n496;
wire [17:0] n497;
wire [17:0] n498;
wire [17:0] n499;
wire [17:0] n500;
wire n505;
wire n506;
wire n507;
wire [1:0] n508;
wire [2:0] n509;
wire [3:0] n510;
wire [4:0] n511;
wire [12:0] n512;
wire [17:0] n513;
wire [17:0] n514;
wire [17:0] n515;
wire [17:0] n516;
wire [17:0] n521;
wire [17:0] n522;
wire [17:0] n523;
wire [17:0] n524;
wire n541;
wire [1:0] n542;
wire [2:0] n543;
wire [3:0] n544;
wire [4:0] n545;
wire [5:0] n546;
wire [6:0] n547;
wire [7:0] n548;
wire [8:0] n549;
wire [9:0] n550;
wire [10:0] n551;
wire [11:0] n552;
wire [12:0] n553;
wire [13:0] n554;
wire [14:0] n555;
wire [15:0] n556;
wire [16:0] n557;
wire [17:0] n558;
wire n559;
wire n560;
wire [16:0] n561;
wire [17:0] n562;
wire n563;
wire n564;
wire [16:0] n565;
wire [17:0] n566;
wire n567;
wire n568;
wire n569;
wire n570;
wire [1:0] n571;
wire [2:0] n572;
wire [3:0] n573;
wire [4:0] n574;
wire [5:0] n575;
wire [11:0] n576;
wire [17:0] n577;
wire [17:0] n578;
wire [17:0] n579;
wire [17:0] n580;
wire n585;
wire n586;
wire n587;
wire [1:0] n588;
wire [2:0] n589;
wire [3:0] n590;
wire [4:0] n591;
wire [5:0] n592;
wire [11:0] n593;
wire [17:0] n594;
wire [17:0] n595;
wire [17:0] n596;
wire [17:0] n597;
wire [17:0] n602;
wire [17:0] n603;
wire [17:0] n604;
wire [17:0] n605;
wire n622;
wire [1:0] n623;
wire [2:0] n624;
wire [3:0] n625;
wire [4:0] n626;
wire [5:0] n627;
wire [6:0] n628;
wire [7:0] n629;
wire [8:0] n630;
wire [9:0] n631;
wire [10:0] n632;
wire [11:0] n633;
wire [12:0] n634;
wire [13:0] n635;
wire [14:0] n636;
wire [15:0] n637;
wire [16:0] n638;
wire [17:0] n639;
wire n640;
wire n641;
wire [16:0] n642;
wire [17:0] n643;
wire n644;
wire n645;
wire [16:0] n646;
wire [17:0] n647;
wire n648;
wire n649;
wire n650;
wire n651;
wire [1:0] n652;
wire [2:0] n653;
wire [3:0] n654;
wire [4:0] n655;
wire [5:0] n656;
wire [6:0] n657;
wire [10:0] n658;
wire [17:0] n659;
wire [17:0] n660;
wire [17:0] n661;
wire [17:0] n662;
wire n667;
wire n668;
wire n669;
wire [1:0] n670;
wire [2:0] n671;
wire [3:0] n672;
wire [4:0] n673;
wire [5:0] n674;
wire [6:0] n675;
wire [10:0] n676;
wire [17:0] n677;
wire [17:0] n678;
wire [17:0] n679;
wire [17:0] n680;
wire [17:0] n685;
wire [17:0] n686;
wire [17:0] n687;
wire [17:0] n688;
wire n705;
wire [1:0] n706;
wire [2:0] n707;
wire [3:0] n708;
wire [4:0] n709;
wire [5:0] n710;
wire [6:0] n711;
wire [7:0] n712;
wire [8:0] n713;
wire [9:0] n714;
wire [10:0] n715;
wire [11:0] n716;
wire [12:0] n717;
wire [13:0] n718;
wire [14:0] n719;
wire [15:0] n720;
wire [16:0] n721;
wire [17:0] n722;
wire n723;
wire n724;
wire [16:0] n725;
wire [17:0] n726;
wire n727;
wire n728;
wire [16:0] n729;
wire [17:0] n730;
wire n731;
wire n732;
wire n733;
wire n734;
wire [1:0] n735;
wire [2:0] n736;
wire [3:0] n737;
wire [4:0] n738;
wire [5:0] n739;
wire [6:0] n740;
wire [7:0] n741;
wire [9:0] n742;
wire [17:0] n743;
wire [17:0] n744;
wire [17:0] n745;
wire [17:0] n746;
wire n751;
wire n752;
wire n753;
wire [1:0] n754;
wire [2:0] n755;
wire [3:0] n756;
wire [4:0] n757;
wire [5:0] n758;
wire [6:0] n759;
wire [7:0] n760;
wire [9:0] n761;
wire [17:0] n762;
wire [17:0] n763;
wire [17:0] n764;
wire [17:0] n765;
wire [17:0] n770;
wire [17:0] n771;
wire [17:0] n772;
wire [17:0] n773;
wire n790;
wire [1:0] n791;
wire [2:0] n792;
wire [3:0] n793;
wire [4:0] n794;
wire [5:0] n795;
wire [6:0] n796;
wire [7:0] n797;
wire [8:0] n798;
wire [9:0] n799;
wire [10:0] n800;
wire [11:0] n801;
wire [12:0] n802;
wire [13:0] n803;
wire [14:0] n804;
wire [15:0] n805;
wire [16:0] n806;
wire [17:0] n807;
wire n808;
wire n809;
wire [16:0] n810;
wire [17:0] n811;
wire n812;
wire n813;
wire [16:0] n814;
wire [17:0] n815;
wire n816;
wire n817;
wire n818;
wire n819;
wire [1:0] n820;
wire [2:0] n821;
wire [3:0] n822;
wire [4:0] n823;
wire [5:0] n824;
wire [6:0] n825;
wire [7:0] n826;
wire [8:0] n827;
wire [8:0] n828;
wire [17:0] n829;
wire [17:0] n830;
wire [17:0] n831;
wire [17:0] n832;
wire n837;
wire n838;
wire n839;
wire [1:0] n840;
wire [2:0] n841;
wire [3:0] n842;
wire [4:0] n843;
wire [5:0] n844;
wire [6:0] n845;
wire [7:0] n846;
wire [8:0] n847;
wire [8:0] n848;
wire [17:0] n849;
wire [17:0] n850;
wire [17:0] n851;
wire [17:0] n852;
wire [17:0] n857;
wire [17:0] n858;
wire [17:0] n859;
wire [17:0] n860;
wire n877;
wire [1:0] n878;
wire [2:0] n879;
wire [3:0] n880;
wire [4:0] n881;
wire [5:0] n882;
wire [6:0] n883;
wire [7:0] n884;
wire [8:0] n885;
wire [9:0] n886;
wire [10:0] n887;
wire [11:0] n888;
wire [12:0] n889;
wire [13:0] n890;
wire [14:0] n891;
wire [15:0] n892;
wire [16:0] n893;
wire [17:0] n894;
wire n895;
wire n896;
wire [16:0] n897;
wire [17:0] n898;
wire n899;
wire n900;
wire [16:0] n901;
wire [17:0] n902;
wire n903;
wire n904;
wire n905;
wire n906;
wire [1:0] n907;
wire [2:0] n908;
wire [3:0] n909;
wire [4:0] n910;
wire [5:0] n911;
wire [6:0] n912;
wire [7:0] n913;
wire [8:0] n914;
wire [9:0] n915;
wire [7:0] n916;
wire [17:0] n917;
wire [17:0] n918;
wire [17:0] n919;
wire [17:0] n920;
wire n925;
wire n926;
wire n927;
wire [1:0] n928;
wire [2:0] n929;
wire [3:0] n930;
wire [4:0] n931;
wire [5:0] n932;
wire [6:0] n933;
wire [7:0] n934;
wire [8:0] n935;
wire [9:0] n936;
wire [7:0] n937;
wire [17:0] n938;
wire [17:0] n939;
wire [17:0] n940;
wire [17:0] n941;
wire [17:0] n946;
wire [17:0] n947;
wire [17:0] n948;
wire [17:0] n949;
wire n966;
wire [1:0] n967;
wire [2:0] n968;
wire [3:0] n969;
wire [4:0] n970;
wire [5:0] n971;
wire [6:0] n972;
wire [7:0] n973;
wire [8:0] n974;
wire [9:0] n975;
wire [10:0] n976;
wire [11:0] n977;
wire [12:0] n978;
wire [13:0] n979;
wire [14:0] n980;
wire [15:0] n981;
wire [16:0] n982;
wire [17:0] n983;
wire n984;
wire n985;
wire [16:0] n986;
wire [17:0] n987;
wire n988;
wire n989;
wire [16:0] n990;
wire [17:0] n991;
wire n992;
wire n993;
wire n994;
wire n995;
wire [1:0] n996;
wire [2:0] n997;
wire [3:0] n998;
wire [4:0] n999;
wire [5:0] n1000;
wire [6:0] n1001;
wire [7:0] n1002;
wire [8:0] n1003;
wire [9:0] n1004;
wire [10:0] n1005;
wire [6:0] n1006;
wire [17:0] n1007;
wire [17:0] n1008;
wire [17:0] n1009;
wire [17:0] n1010;
wire n1015;
wire n1016;
wire n1017;
wire [1:0] n1018;
wire [2:0] n1019;
wire [3:0] n1020;
wire [4:0] n1021;
wire [5:0] n1022;
wire [6:0] n1023;
wire [7:0] n1024;
wire [8:0] n1025;
wire [9:0] n1026;
wire [10:0] n1027;
wire [6:0] n1028;
wire [17:0] n1029;
wire [17:0] n1030;
wire [17:0] n1031;
wire [17:0] n1032;
wire [17:0] n1037;
wire [17:0] n1038;
wire [17:0] n1039;
wire [17:0] n1040;
wire n1057;
wire [1:0] n1058;
wire [2:0] n1059;
wire [3:0] n1060;
wire [4:0] n1061;
wire [5:0] n1062;
wire [6:0] n1063;
wire [7:0] n1064;
wire [8:0] n1065;
wire [9:0] n1066;
wire [10:0] n1067;
wire [11:0] n1068;
wire [12:0] n1069;
wire [13:0] n1070;
wire [14:0] n1071;
wire [15:0] n1072;
wire [16:0] n1073;
wire [17:0] n1074;
wire n1075;
wire n1076;
wire [16:0] n1077;
wire [17:0] n1078;
wire n1079;
wire n1080;
wire [16:0] n1081;
wire [17:0] n1082;
wire n1083;
wire n1084;
wire n1085;
wire n1086;
wire [1:0] n1087;
wire [2:0] n1088;
wire [3:0] n1089;
wire [4:0] n1090;
wire [5:0] n1091;
wire [6:0] n1092;
wire [7:0] n1093;
wire [8:0] n1094;
wire [9:0] n1095;
wire [10:0] n1096;
wire [11:0] n1097;
wire [5:0] n1098;
wire [17:0] n1099;
wire [17:0] n1100;
wire [17:0] n1101;
wire [17:0] n1102;
wire n1107;
wire n1108;
wire n1109;
wire [1:0] n1110;
wire [2:0] n1111;
wire [3:0] n1112;
wire [4:0] n1113;
wire [5:0] n1114;
wire [6:0] n1115;
wire [7:0] n1116;
wire [8:0] n1117;
wire [9:0] n1118;
wire [10:0] n1119;
wire [11:0] n1120;
wire [5:0] n1121;
wire [17:0] n1122;
wire [17:0] n1123;
wire [17:0] n1124;
wire [17:0] n1125;
wire [17:0] n1130;
wire [17:0] n1131;
wire [17:0] n1132;
wire [17:0] n1133;
wire n1150;
wire [1:0] n1151;
wire [2:0] n1152;
wire [3:0] n1153;
wire [4:0] n1154;
wire [5:0] n1155;
wire [6:0] n1156;
wire [7:0] n1157;
wire [8:0] n1158;
wire [9:0] n1159;
wire [10:0] n1160;
wire [11:0] n1161;
wire [12:0] n1162;
wire [13:0] n1163;
wire [14:0] n1164;
wire [15:0] n1165;
wire [16:0] n1166;
wire [17:0] n1167;
wire n1168;
wire n1169;
wire [16:0] n1170;
wire [17:0] n1171;
wire n1172;
wire n1173;
wire [16:0] n1174;
wire [17:0] n1175;
wire n1176;
wire n1177;
wire n1178;
wire n1179;
wire [1:0] n1180;
wire [2:0] n1181;
wire [3:0] n1182;
wire [4:0] n1183;
wire [5:0] n1184;
wire [6:0] n1185;
wire [7:0] n1186;
wire [8:0] n1187;
wire [9:0] n1188;
wire [10:0] n1189;
wire [11:0] n1190;
wire [12:0] n1191;
wire [4:0] n1192;
wire [17:0] n1193;
wire [17:0] n1194;
wire [17:0] n1195;
wire [17:0] n1196;
wire n1201;
wire n1202;
wire n1203;
wire [1:0] n1204;
wire [2:0] n1205;
wire [3:0] n1206;
wire [4:0] n1207;
wire [5:0] n1208;
wire [6:0] n1209;
wire [7:0] n1210;
wire [8:0] n1211;
wire [9:0] n1212;
wire [10:0] n1213;
wire [11:0] n1214;
wire [12:0] n1215;
wire [4:0] n1216;
wire [17:0] n1217;
wire [17:0] n1218;
wire [17:0] n1219;
wire [17:0] n1220;
wire [17:0] n1225;
wire [17:0] n1226;
wire [17:0] n1227;
wire [17:0] n1228;
wire n1245;
wire [1:0] n1246;
wire [2:0] n1247;
wire [3:0] n1248;
wire [4:0] n1249;
wire [5:0] n1250;
wire [6:0] n1251;
wire [7:0] n1252;
wire [8:0] n1253;
wire [9:0] n1254;
wire [10:0] n1255;
wire [11:0] n1256;
wire [12:0] n1257;
wire [13:0] n1258;
wire [14:0] n1259;
wire [15:0] n1260;
wire [16:0] n1261;
wire [17:0] n1262;
wire n1263;
wire n1264;
wire [16:0] n1265;
wire [17:0] n1266;
wire n1267;
wire n1268;
wire [16:0] n1269;
wire [17:0] n1270;
wire n1271;
wire n1272;
wire n1273;
wire n1274;
wire [1:0] n1275;
wire [2:0] n1276;
wire [3:0] n1277;
wire [4:0] n1278;
wire [5:0] n1279;
wire [6:0] n1280;
wire [7:0] n1281;
wire [8:0] n1282;
wire [9:0] n1283;
wire [10:0] n1284;
wire [11:0] n1285;
wire [12:0] n1286;
wire [13:0] n1287;
wire [3:0] n1288;
wire [17:0] n1289;
wire [17:0] n1290;
wire [17:0] n1291;
wire [17:0] n1292;
wire n1297;
wire n1298;
wire n1299;
wire [1:0] n1300;
wire [2:0] n1301;
wire [3:0] n1302;
wire [4:0] n1303;
wire [5:0] n1304;
wire [6:0] n1305;
wire [7:0] n1306;
wire [8:0] n1307;
wire [9:0] n1308;
wire [10:0] n1309;
wire [11:0] n1310;
wire [12:0] n1311;
wire [13:0] n1312;
wire [3:0] n1313;
wire [17:0] n1314;
wire [17:0] n1315;
wire [17:0] n1316;
wire [17:0] n1317;
wire [17:0] n1322;
wire [17:0] n1323;
wire [17:0] n1324;
wire [17:0] n1325;
wire n1342;
wire [1:0] n1343;
wire [2:0] n1344;
wire [3:0] n1345;
wire [4:0] n1346;
wire [5:0] n1347;
wire [6:0] n1348;
wire [7:0] n1349;
wire [8:0] n1350;
wire [9:0] n1351;
wire [10:0] n1352;
wire [11:0] n1353;
wire [12:0] n1354;
wire [13:0] n1355;
wire [14:0] n1356;
wire [15:0] n1357;
wire [16:0] n1358;
wire [17:0] n1359;
wire n1360;
wire n1361;
wire [16:0] n1362;
wire [17:0] n1363;
wire n1364;
wire n1365;
wire [16:0] n1366;
wire [17:0] n1367;
wire n1368;
wire n1369;
wire n1370;
wire n1371;
wire [1:0] n1372;
wire [2:0] n1373;
wire [3:0] n1374;
wire [4:0] n1375;
wire [5:0] n1376;
wire [6:0] n1377;
wire [7:0] n1378;
wire [8:0] n1379;
wire [9:0] n1380;
wire [10:0] n1381;
wire [11:0] n1382;
wire [12:0] n1383;
wire [13:0] n1384;
wire [14:0] n1385;
wire [2:0] n1386;
wire [17:0] n1387;
wire [17:0] n1388;
wire [17:0] n1389;
wire [17:0] n1390;
wire n1395;
wire n1396;
wire n1397;
wire [1:0] n1398;
wire [2:0] n1399;
wire [3:0] n1400;
wire [4:0] n1401;
wire [5:0] n1402;
wire [6:0] n1403;
wire [7:0] n1404;
wire [8:0] n1405;
wire [9:0] n1406;
wire [10:0] n1407;
wire [11:0] n1408;
wire [12:0] n1409;
wire [13:0] n1410;
wire [14:0] n1411;
wire [2:0] n1412;
wire [17:0] n1413;
wire [17:0] n1414;
wire [17:0] n1415;
wire [17:0] n1416;
wire [17:0] n1421;
wire [17:0] n1422;
wire [17:0] n1423;
wire [17:0] n1424;
wire n1441;
wire [1:0] n1442;
wire [2:0] n1443;
wire [3:0] n1444;
wire [4:0] n1445;
wire [5:0] n1446;
wire [6:0] n1447;
wire [7:0] n1448;
wire [8:0] n1449;
wire [9:0] n1450;
wire [10:0] n1451;
wire [11:0] n1452;
wire [12:0] n1453;
wire [13:0] n1454;
wire [14:0] n1455;
wire [15:0] n1456;
wire [16:0] n1457;
wire [17:0] n1458;
wire n1459;
wire n1460;
wire [16:0] n1461;
wire [17:0] n1462;
wire n1463;
wire n1464;
wire [16:0] n1465;
wire [17:0] n1466;
wire n1467;
wire n1468;
wire n1469;
wire n1470;
wire [1:0] n1471;
wire [2:0] n1472;
wire [3:0] n1473;
wire [4:0] n1474;
wire [5:0] n1475;
wire [6:0] n1476;
wire [7:0] n1477;
wire [8:0] n1478;
wire [9:0] n1479;
wire [10:0] n1480;
wire [11:0] n1481;
wire [12:0] n1482;
wire [13:0] n1483;
wire [14:0] n1484;
wire [15:0] n1485;
wire [1:0] n1486;
wire [17:0] n1487;
wire [17:0] n1488;
wire [17:0] n1489;
wire [17:0] n1490;
wire n1495;
wire n1496;
wire n1497;
wire [1:0] n1498;
wire [2:0] n1499;
wire [3:0] n1500;
wire [4:0] n1501;
wire [5:0] n1502;
wire [6:0] n1503;
wire [7:0] n1504;
wire [8:0] n1505;
wire [9:0] n1506;
wire [10:0] n1507;
wire [11:0] n1508;
wire [12:0] n1509;
wire [13:0] n1510;
wire [14:0] n1511;
wire [15:0] n1512;
wire [1:0] n1513;
wire [17:0] n1514;
wire [17:0] n1515;
wire [17:0] n1516;
wire [17:0] n1517;
wire [17:0] n1522;
wire [17:0] n1523;
wire [17:0] n1524;
wire [17:0] n1525;
wire n1542;
wire [1:0] n1543;
wire [2:0] n1544;
wire [3:0] n1545;
wire [4:0] n1546;
wire [5:0] n1547;
wire [6:0] n1548;
wire [7:0] n1549;
wire [8:0] n1550;
wire [9:0] n1551;
wire [10:0] n1552;
wire [11:0] n1553;
wire [12:0] n1554;
wire [13:0] n1555;
wire [14:0] n1556;
wire [15:0] n1557;
wire [16:0] n1558;
wire [17:0] n1559;
wire n1560;
wire n1561;
wire [16:0] n1562;
wire [17:0] n1563;
wire n1564;
wire n1565;
wire [16:0] n1566;
wire [17:0] n1567;
wire n1568;
wire n1569;
wire n1570;
wire n1571;
wire [1:0] n1572;
wire [2:0] n1573;
wire [3:0] n1574;
wire [4:0] n1575;
wire [5:0] n1576;
wire [6:0] n1577;
wire [7:0] n1578;
wire [8:0] n1579;
wire [9:0] n1580;
wire [10:0] n1581;
wire [11:0] n1582;
wire [12:0] n1583;
wire [13:0] n1584;
wire [14:0] n1585;
wire [15:0] n1586;
wire [16:0] n1587;
wire n1588;
wire [17:0] n1589;
wire [17:0] n1590;
wire [17:0] n1591;
wire [17:0] n1592;
wire n1597;
wire n1598;
wire n1599;
wire [1:0] n1600;
wire [2:0] n1601;
wire [3:0] n1602;
wire [4:0] n1603;
wire [5:0] n1604;
wire [6:0] n1605;
wire [7:0] n1606;
wire [8:0] n1607;
wire [9:0] n1608;
wire [10:0] n1609;
wire [11:0] n1610;
wire [12:0] n1611;
wire [13:0] n1612;
wire [14:0] n1613;
wire [15:0] n1614;
wire [16:0] n1615;
wire n1616;
wire [17:0] n1617;
wire [17:0] n1618;
wire [17:0] n1619;
wire [17:0] n1620;
wire [17:0] n1625;
wire [17:0] n1626;
wire [17:0] n1627;
wire n1635;
wire n1636;
wire n1637;
wire n1638;
reg [17:0] n11;
reg [17:0] n15;
reg [17:0] n19;
reg [17:0] n74;
reg [17:0] n79;
reg [17:0] n84;
reg [17:0] n88;
reg [17:0] n92;
reg [17:0] n96;
reg [17:0] n134;
reg [17:0] n145;
reg [17:0] n153;
reg [17:0] n157;
reg [17:0] n161;
reg [17:0] n165;
reg [17:0] n204;
reg [17:0] n216;
reg [17:0] n224;
reg [17:0] n228;
reg [17:0] n232;
reg [17:0] n236;
reg [17:0] n276;
reg [17:0] n289;
reg [17:0] n297;
reg [17:0] n301;
reg [17:0] n305;
reg [17:0] n309;
reg [17:0] n350;
reg [17:0] n364;
reg [17:0] n372;
reg [17:0] n376;
reg [17:0] n380;
reg [17:0] n384;
reg [17:0] n426;
reg [17:0] n441;
reg [17:0] n449;
reg [17:0] n453;
reg [17:0] n457;
reg [17:0] n461;
reg [17:0] n504;
reg [17:0] n520;
reg [17:0] n528;
reg [17:0] n532;
reg [17:0] n536;
reg [17:0] n540;
reg [17:0] n584;
reg [17:0] n601;
reg [17:0] n609;
reg [17:0] n613;
reg [17:0] n617;
reg [17:0] n621;
reg [17:0] n666;
reg [17:0] n684;
reg [17:0] n692;
reg [17:0] n696;
reg [17:0] n700;
reg [17:0] n704;
reg [17:0] n750;
reg [17:0] n769;
reg [17:0] n777;
reg [17:0] n781;
reg [17:0] n785;
reg [17:0] n789;
reg [17:0] n836;
reg [17:0] n856;
reg [17:0] n864;
reg [17:0] n868;
reg [17:0] n872;
reg [17:0] n876;
reg [17:0] n924;
reg [17:0] n945;
reg [17:0] n953;
reg [17:0] n957;
reg [17:0] n961;
reg [17:0] n965;
reg [17:0] n1014;
reg [17:0] n1036;
reg [17:0] n1044;
reg [17:0] n1048;
reg [17:0] n1052;
reg [17:0] n1056;
reg [17:0] n1106;
reg [17:0] n1129;
reg [17:0] n1137;
reg [17:0] n1141;
reg [17:0] n1145;
reg [17:0] n1149;
reg [17:0] n1200;
reg [17:0] n1224;
reg [17:0] n1232;
reg [17:0] n1236;
reg [17:0] n1240;
reg [17:0] n1244;
reg [17:0] n1296;
reg [17:0] n1321;
reg [17:0] n1329;
reg [17:0] n1333;
reg [17:0] n1337;
reg [17:0] n1341;
reg [17:0] n1394;
reg [17:0] n1420;
reg [17:0] n1428;
reg [17:0] n1432;
reg [17:0] n1436;
reg [17:0] n1440;
reg [17:0] n1494;
reg [17:0] n1521;
reg [17:0] n1529;
reg [17:0] n1533;
reg [17:0] n1537;
reg [17:0] n1541;
reg [17:0] n1596;
reg [17:0] n1624;
reg [17:0] n1631;
assign n6 = 18'b000000000000000000;
assign n8 = 1'b0;
assign n21 = n8;
assign n22 = {n8, n21};
assign n23 = {n8, n22};
assign n24 = {n8, n23};
assign n25 = {n8, n24};
assign n26 = {n8, n25};
assign n27 = {n8, n26};
assign n28 = {n8, n27};
assign n29 = {n8, n28};
assign n30 = {n8, n29};
assign n31 = {n8, n30};
assign n32 = {n8, n31};
assign n33 = {n8, n32};
assign n34 = {n8, n33};
assign n35 = {n8, n34};
assign n36 = {n8, n35};
assign n37 = {n8, n36};
assign n38 = {n8, n37};
assign n39 = n11[17];
assign n40 = ~n39;
assign n41 = {n11[16],
n11[15],
n11[14],
n11[13],
n11[12],
n11[11],
n11[10],
n11[9],
n11[8],
n11[7],
n11[6],
n11[5],
n11[4],
n11[3],
n11[2],
n11[1],
n11[0]};
assign n42 = {n40, n41};
assign n43 = n38[17];
assign n44 = ~n43;
assign n45 = {n38[16],
n38[15],
n38[14],
n38[13],
n38[12],
n38[11],
n38[10],
n38[9],
n38[8],
n38[7],
n38[6],
n38[5],
n38[4],
n38[3],
n38[2],
n38[1],
n38[0]};
assign n46 = {n44, n45};
assign n47 = n42 < n46;
assign n48 = 18'b000000000000000000 - n11;
assign n49 = 18'b000000000000000000 - n15;
assign n50 = 1'b1;
assign n51 = n8;
assign n52 = {n8, n51};
assign n53 = {n8, n52};
assign n54 = {n8, n53};
assign n55 = {n8, n54};
assign n56 = {n8, n55};
assign n57 = {n8, n56};
assign n58 = {n8, n57};
assign n59 = {n8, n58};
assign n60 = {n8, n59};
assign n61 = {n8, n60};
assign n62 = {n8, n61};
assign n63 = {n8, n62};
assign n64 = {n8, n63};
assign n65 = {n8, n64};
assign n66 = {n8, n65};
assign n67 = {n8, n66};
assign n68 = {n50, n67};
assign n69 = n19 - n68;
assign n70 =
n47 == 1'b0 ? n11 :
n48;
assign n75 =
n47 == 1'b0 ? n15 :
n49;
assign n80 =
n47 == 1'b0 ? n19 :
n69;
assign n97 = n8;
assign n98 = {n8, n97};
assign n99 = {n8, n98};
assign n100 = {n8, n99};
assign n101 = {n8, n100};
assign n102 = {n8, n101};
assign n103 = {n8, n102};
assign n104 = {n8, n103};
assign n105 = {n8, n104};
assign n106 = {n8, n105};
assign n107 = {n8, n106};
assign n108 = {n8, n107};
assign n109 = {n8, n108};
assign n110 = {n8, n109};
assign n111 = {n8, n110};
assign n112 = {n8, n111};
assign n113 = {n8, n112};
assign n114 = {n8, n113};
assign n115 = n92[17];
assign n116 = ~n115;
assign n117 = {n92[16],
n92[15],
n92[14],
n92[13],
n92[12],
n92[11],
n92[10],
n92[9],
n92[8],
n92[7],
n92[6],
n92[5],
n92[4],
n92[3],
n92[2],
n92[1],
n92[0]};
assign n118 = {n116, n117};
assign n119 = n114[17];
assign n120 = ~n119;
assign n121 = {n114[16],
n114[15],
n114[14],
n114[13],
n114[12],
n114[11],
n114[10],
n114[9],
n114[8],
n114[7],
n114[6],
n114[5],
n114[4],
n114[3],
n114[2],
n114[1],
n114[0]};
assign n122 = {n120, n121};
assign n123 = n118 <= n122;
assign n124 = ~n123;
assign n126 = {n92[17],
n92[16],
n92[15],
n92[14],
n92[13],
n92[12],
n92[11],
n92[10],
n92[9],
n92[8],
n92[7],
n92[6],
n92[5],
n92[4],
n92[3],
n92[2],
n92[1],
n92[0]};
assign n127 = n126;
assign n128 = n88 - n127;
assign n129 = n88 + n127;
assign n130 =
n124 == 1'b0 ? n128 :
n129;
assign n135 = ~n124;
assign n137 = {n88[17],
n88[16],
n88[15],
n88[14],
n88[13],
n88[12],
n88[11],
n88[10],
n88[9],
n88[8],
n88[7],
n88[6],
n88[5],
n88[4],
n88[3],
n88[2],
n88[1],
n88[0]};
assign n138 = n137;
assign n139 = n92 - n138;
assign n140 = n92 + n138;
assign n141 =
n135 == 1'b0 ? n139 :
n140;
assign n146 = 18'b011001001000011111;
assign n147 = n96 - n146;
assign n148 = n96 + n146;
assign n149 =
n124 == 1'b0 ? n147 :
n148;
assign n166 = n8;
assign n167 = {n8, n166};
assign n168 = {n8, n167};
assign n169 = {n8, n168};
assign n170 = {n8, n169};
assign n171 = {n8, n170};
assign n172 = {n8, n171};
assign n173 = {n8, n172};
assign n174 = {n8, n173};
assign n175 = {n8, n174};
assign n176 = {n8, n175};
assign n177 = {n8, n176};
assign n178 = {n8, n177};
assign n179 = {n8, n178};
assign n180 = {n8, n179};
assign n181 = {n8, n180};
assign n182 = {n8, n181};
assign n183 = {n8, n182};
assign n184 = n161[17];
assign n185 = ~n184;
assign n186 = {n161[16],
n161[15],
n161[14],
n161[13],
n161[12],
n161[11],
n161[10],
n161[9],
n161[8],
n161[7],
n161[6],
n161[5],
n161[4],
n161[3],
n161[2],
n161[1],
n161[0]};
assign n187 = {n185, n186};
assign n188 = n183[17];
assign n189 = ~n188;
assign n190 = {n183[16],
n183[15],
n183[14],
n183[13],
n183[12],
n183[11],
n183[10],
n183[9],
n183[8],
n183[7],
n183[6],
n183[5],
n183[4],
n183[3],
n183[2],
n183[1],
n183[0]};
assign n191 = {n189, n190};
assign n192 = n187 <= n191;
assign n193 = ~n192;
assign n194 = n161[17];
assign n195 = n194;
assign n196 = {n161[17],
n161[16],
n161[15],
n161[14],
n161[13],
n161[12],
n161[11],
n161[10],
n161[9],
n161[8],
n161[7],
n161[6],
n161[5],
n161[4],
n161[3],
n161[2],
n161[1]};
assign n197 = {n195, n196};
assign n198 = n157 - n197;
assign n199 = n157 + n197;
assign n200 =
n193 == 1'b0 ? n198 :
n199;
assign n205 = ~n193;
assign n206 = n157[17];
assign n207 = n206;
assign n208 = {n157[17],
n157[16],
n157[15],
n157[14],
n157[13],
n157[12],
n157[11],
n157[10],
n157[9],
n157[8],
n157[7],
n157[6],
n157[5],
n157[4],
n157[3],
n157[2],
n157[1]};
assign n209 = {n207, n208};
assign n210 = n161 - n209;
assign n211 = n161 + n209;
assign n212 =
n205 == 1'b0 ? n210 :
n211;
assign n217 = 18'b001110110101100011;
assign n218 = n165 - n217;
assign n219 = n165 + n217;
assign n220 =
n193 == 1'b0 ? n218 :
n219;
assign n237 = n8;
assign n238 = {n8, n237};
assign n239 = {n8, n238};
assign n240 = {n8, n239};
assign n241 = {n8, n240};
assign n242 = {n8, n241};
assign n243 = {n8, n242};
assign n244 = {n8, n243};
assign n245 = {n8, n244};
assign n246 = {n8, n245};
assign n247 = {n8, n246};
assign n248 = {n8, n247};
assign n249 = {n8, n248};
assign n250 = {n8, n249};
assign n251 = {n8, n250};
assign n252 = {n8, n251};
assign n253 = {n8, n252};
assign n254 = {n8, n253};
assign n255 = n232[17];
assign n256 = ~n255;
assign n257 = {n232[16],
n232[15],
n232[14],
n232[13],
n232[12],
n232[11],
n232[10],
n232[9],
n232[8],
n232[7],
n232[6],
n232[5],
n232[4],
n232[3],
n232[2],
n232[1],
n232[0]};
assign n258 = {n256, n257};
assign n259 = n254[17];
assign n260 = ~n259;
assign n261 = {n254[16],
n254[15],
n254[14],
n254[13],
n254[12],
n254[11],
n254[10],
n254[9],
n254[8],
n254[7],
n254[6],
n254[5],
n254[4],
n254[3],
n254[2],
n254[1],
n254[0]};
assign n262 = {n260, n261};
assign n263 = n258 <= n262;
assign n264 = ~n263;
assign n265 = n232[17];
assign n266 = n265;
assign n267 = {n265, n266};
assign n268 = {n232[17],
n232[16],
n232[15],
n232[14],
n232[13],
n232[12],
n232[11],
n232[10],
n232[9],
n232[8],
n232[7],
n232[6],
n232[5],
n232[4],
n232[3],
n232[2]};
assign n269 = {n267, n268};
assign n270 = n228 - n269;
assign n271 = n228 + n269;
assign n272 =
n264 == 1'b0 ? n270 :
n271;
assign n277 = ~n264;
assign n278 = n228[17];
assign n279 = n278;
assign n280 = {n278, n279};
assign n281 = {n228[17],
n228[16],
n228[15],
n228[14],
n228[13],
n228[12],
n228[11],
n228[10],
n228[9],
n228[8],
n228[7],
n228[6],
n228[5],
n228[4],
n228[3],
n228[2]};
assign n282 = {n280, n281};
assign n283 = n232 - n282;
assign n284 = n232 + n282;
assign n285 =
n277 == 1'b0 ? n283 :
n284;
assign n290 = 18'b000111110101101101;
assign n291 = n236 - n290;
assign n292 = n236 + n290;
assign n293 =
n264 == 1'b0 ? n291 :
n292;
assign n310 = n8;
assign n311 = {n8, n310};
assign n312 = {n8, n311};
assign n313 = {n8, n312};
assign n314 = {n8, n313};
assign n315 = {n8, n314};
assign n316 = {n8, n315};
assign n317 = {n8, n316};
assign n318 = {n8, n317};
assign n319 = {n8, n318};
assign n320 = {n8, n319};
assign n321 = {n8, n320};
assign n322 = {n8, n321};
assign n323 = {n8, n322};
assign n324 = {n8, n323};
assign n325 = {n8, n324};
assign n326 = {n8, n325};
assign n327 = {n8, n326};
assign n328 = n305[17];
assign n329 = ~n328;
assign n330 = {n305[16],
n305[15],
n305[14],
n305[13],
n305[12],
n305[11],
n305[10],
n305[9],
n305[8],
n305[7],
n305[6],
n305[5],
n305[4],
n305[3],
n305[2],
n305[1],
n305[0]};
assign n331 = {n329, n330};
assign n332 = n327[17];
assign n333 = ~n332;
assign n334 = {n327[16],
n327[15],
n327[14],
n327[13],
n327[12],
n327[11],
n327[10],
n327[9],
n327[8],
n327[7],
n327[6],
n327[5],
n327[4],
n327[3],
n327[2],
n327[1],
n327[0]};
assign n335 = {n333, n334};
assign n336 = n331 <= n335;
assign n337 = ~n336;
assign n338 = n305[17];
assign n339 = n338;
assign n340 = {n338, n339};
assign n341 = {n338, n340};
assign n342 = {n305[17],
n305[16],
n305[15],
n305[14],
n305[13],
n305[12],
n305[11],
n305[10],
n305[9],
n305[8],
n305[7],
n305[6],
n305[5],
n305[4],
n305[3]};
assign n343 = {n341, n342};
assign n344 = n301 - n343;
assign n345 = n301 + n343;
assign n346 =
n337 == 1'b0 ? n344 :
n345;
assign n351 = ~n337;
assign n352 = n301[17];
assign n353 = n352;
assign n354 = {n352, n353};
assign n355 = {n352, n354};
assign n356 = {n301[17],
n301[16],
n301[15],
n301[14],
n301[13],
n301[12],
n301[11],
n301[10],
n301[9],
n301[8],
n301[7],
n301[6],
n301[5],
n301[4],
n301[3]};
assign n357 = {n355, n356};
assign n358 = n305 - n357;
assign n359 = n305 + n357;
assign n360 =
n351 == 1'b0 ? n358 :
n359;
assign n365 = 18'b000011111110101011;
assign n366 = n309 - n365;
assign n367 = n309 + n365;
assign n368 =
n337 == 1'b0 ? n366 :
n367;
assign n385 = n8;
assign n386 = {n8, n385};
assign n387 = {n8, n386};
assign n388 = {n8, n387};
assign n389 = {n8, n388};
assign n390 = {n8, n389};
assign n391 = {n8, n390};
assign n392 = {n8, n391};
assign n393 = {n8, n392};
assign n394 = {n8, n393};
assign n395 = {n8, n394};
assign n396 = {n8, n395};
assign n397 = {n8, n396};
assign n398 = {n8, n397};
assign n399 = {n8, n398};
assign n400 = {n8, n399};
assign n401 = {n8, n400};
assign n402 = {n8, n401};
assign n403 = n380[17];
assign n404 = ~n403;
assign n405 = {n380[16],
n380[15],
n380[14],
n380[13],
n380[12],
n380[11],
n380[10],
n380[9],
n380[8],
n380[7],
n380[6],
n380[5],
n380[4],
n380[3],
n380[2],
n380[1],
n380[0]};
assign n406 = {n404, n405};
assign n407 = n402[17];
assign n408 = ~n407;
assign n409 = {n402[16],
n402[15],
n402[14],
n402[13],
n402[12],
n402[11],
n402[10],
n402[9],
n402[8],
n402[7],
n402[6],
n402[5],
n402[4],
n402[3],
n402[2],
n402[1],
n402[0]};
assign n410 = {n408, n409};
assign n411 = n406 <= n410;
assign n412 = ~n411;
assign n413 = n380[17];
assign n414 = n413;
assign n415 = {n413, n414};
assign n416 = {n413, n415};
assign n417 = {n413, n416};
assign n418 = {n380[17],
n380[16],
n380[15],
n380[14],
n380[13],
n380[12],
n380[11],
n380[10],
n380[9],
n380[8],
n380[7],
n380[6],
n380[5],
n380[4]};
assign n419 = {n417, n418};
assign n420 = n376 - n419;
assign n421 = n376 + n419;
assign n422 =
n412 == 1'b0 ? n420 :
n421;
assign n427 = ~n412;
assign n428 = n376[17];
assign n429 = n428;
assign n430 = {n428, n429};
assign n431 = {n428, n430};
assign n432 = {n428, n431};
assign n433 = {n376[17],
n376[16],
n376[15],
n376[14],
n376[13],
n376[12],
n376[11],
n376[10],
n376[9],
n376[8],
n376[7],
n376[6],
n376[5],
n376[4]};
assign n434 = {n432, n433};
assign n435 = n380 - n434;
assign n436 = n380 + n434;
assign n437 =
n427 == 1'b0 ? n435 :
n436;
assign n442 = 18'b000001111111110101;
assign n443 = n384 - n442;
assign n444 = n384 + n442;
assign n445 =
n412 == 1'b0 ? n443 :
n444;
assign n462 = n8;
assign n463 = {n8, n462};
assign n464 = {n8, n463};
assign n465 = {n8, n464};
assign n466 = {n8, n465};
assign n467 = {n8, n466};
assign n468 = {n8, n467};
assign n469 = {n8, n468};
assign n470 = {n8, n469};
assign n471 = {n8, n470};
assign n472 = {n8, n471};
assign n473 = {n8, n472};
assign n474 = {n8, n473};
assign n475 = {n8, n474};
assign n476 = {n8, n475};
assign n477 = {n8, n476};
assign n478 = {n8, n477};
assign n479 = {n8, n478};
assign n480 = n457[17];
assign n481 = ~n480;
assign n482 = {n457[16],
n457[15],
n457[14],
n457[13],
n457[12],
n457[11],
n457[10],
n457[9],
n457[8],
n457[7],
n457[6],
n457[5],
n457[4],
n457[3],
n457[2],
n457[1],
n457[0]};
assign n483 = {n481, n482};
assign n484 = n479[17];
assign n485 = ~n484;
assign n486 = {n479[16],
n479[15],
n479[14],
n479[13],
n479[12],
n479[11],
n479[10],
n479[9],
n479[8],
n479[7],
n479[6],
n479[5],
n479[4],
n479[3],
n479[2],
n479[1],
n479[0]};
assign n487 = {n485, n486};
assign n488 = n483 <= n487;
assign n489 = ~n488;
assign n490 = n457[17];
assign n491 = n490;
assign n492 = {n490, n491};
assign n493 = {n490, n492};
assign n494 = {n490, n493};
assign n495 = {n490, n494};
assign n496 = {n457[17],
n457[16],
n457[15],
n457[14],
n457[13],
n457[12],
n457[11],
n457[10],
n457[9],
n457[8],
n457[7],
n457[6],
n457[5]};
assign n497 = {n495, n496};
assign n498 = n453 - n497;
assign n499 = n453 + n497;
assign n500 =
n489 == 1'b0 ? n498 :
n499;
assign n505 = ~n489;
assign n506 = n453[17];
assign n507 = n506;
assign n508 = {n506, n507};
assign n509 = {n506, n508};
assign n510 = {n506, n509};
assign n511 = {n506, n510};
assign n512 = {n453[17],
n453[16],
n453[15],
n453[14],
n453[13],
n453[12],
n453[11],
n453[10],
n453[9],
n453[8],
n453[7],
n453[6],
n453[5]};
assign n513 = {n511, n512};
assign n514 = n457 - n513;
assign n515 = n457 + n513;
assign n516 =
n505 == 1'b0 ? n514 :
n515;
assign n521 = 18'b000000111111111110;
assign n522 = n461 - n521;
assign n523 = n461 + n521;
assign n524 =
n489 == 1'b0 ? n522 :
n523;
assign n541 = n8;
assign n542 = {n8, n541};
assign n543 = {n8, n542};
assign n544 = {n8, n543};
assign n545 = {n8, n544};
assign n546 = {n8, n545};
assign n547 = {n8, n546};
assign n548 = {n8, n547};
assign n549 = {n8, n548};
assign n550 = {n8, n549};
assign n551 = {n8, n550};
assign n552 = {n8, n551};
assign n553 = {n8, n552};
assign n554 = {n8, n553};
assign n555 = {n8, n554};
assign n556 = {n8, n555};
assign n557 = {n8, n556};
assign n558 = {n8, n557};
assign n559 = n536[17];
assign n560 = ~n559;
assign n561 = {n536[16],
n536[15],
n536[14],
n536[13],
n536[12],
n536[11],
n536[10],
n536[9],
n536[8],
n536[7],
n536[6],
n536[5],
n536[4],
n536[3],
n536[2],
n536[1],
n536[0]};
assign n562 = {n560, n561};
assign n563 = n558[17];
assign n564 = ~n563;
assign n565 = {n558[16],
n558[15],
n558[14],
n558[13],
n558[12],
n558[11],
n558[10],
n558[9],
n558[8],
n558[7],
n558[6],
n558[5],
n558[4],
n558[3],
n558[2],
n558[1],
n558[0]};
assign n566 = {n564, n565};
assign n567 = n562 <= n566;
assign n568 = ~n567;
assign n569 = n536[17];
assign n570 = n569;
assign n571 = {n569, n570};
assign n572 = {n569, n571};
assign n573 = {n569, n572};
assign n574 = {n569, n573};
assign n575 = {n569, n574};
assign n576 = {n536[17],
n536[16],
n536[15],
n536[14],
n536[13],
n536[12],
n536[11],
n536[10],
n536[9],
n536[8],
n536[7],
n536[6]};
assign n577 = {n575, n576};
assign n578 = n532 - n577;
assign n579 = n532 + n577;
assign n580 =
n568 == 1'b0 ? n578 :
n579;
assign n585 = ~n568;
assign n586 = n532[17];
assign n587 = n586;
assign n588 = {n586, n587};
assign n589 = {n586, n588};
assign n590 = {n586, n589};
assign n591 = {n586, n590};
assign n592 = {n586, n591};
assign n593 = {n532[17],
n532[16],
n532[15],
n532[14],
n532[13],
n532[12],
n532[11],
n532[10],
n532[9],
n532[8],
n532[7],
n532[6]};
assign n594 = {n592, n593};
assign n595 = n536 - n594;
assign n596 = n536 + n594;
assign n597 =
n585 == 1'b0 ? n595 :
n596;
assign n602 = 18'b000000011111111111;
assign n603 = n540 - n602;
assign n604 = n540 + n602;
assign n605 =
n568 == 1'b0 ? n603 :
n604;
assign n622 = n8;
assign n623 = {n8, n622};
assign n624 = {n8, n623};
assign n625 = {n8, n624};
assign n626 = {n8, n625};
assign n627 = {n8, n626};
assign n628 = {n8, n627};
assign n629 = {n8, n628};
assign n630 = {n8, n629};
assign n631 = {n8, n630};
assign n632 = {n8, n631};
assign n633 = {n8, n632};
assign n634 = {n8, n633};
assign n635 = {n8, n634};
assign n636 = {n8, n635};
assign n637 = {n8, n636};
assign n638 = {n8, n637};
assign n639 = {n8, n638};
assign n640 = n617[17];
assign n641 = ~n640;
assign n642 = {n617[16],
n617[15],
n617[14],
n617[13],
n617[12],
n617[11],
n617[10],
n617[9],
n617[8],
n617[7],
n617[6],
n617[5],
n617[4],
n617[3],
n617[2],
n617[1],
n617[0]};
assign n643 = {n641, n642};
assign n644 = n639[17];
assign n645 = ~n644;
assign n646 = {n639[16],
n639[15],
n639[14],
n639[13],
n639[12],
n639[11],
n639[10],
n639[9],
n639[8],
n639[7],
n639[6],
n639[5],
n639[4],
n639[3],
n639[2],
n639[1],
n639[0]};
assign n647 = {n645, n646};
assign n648 = n643 <= n647;
assign n649 = ~n648;
assign n650 = n617[17];
assign n651 = n650;
assign n652 = {n650, n651};
assign n653 = {n650, n652};
assign n654 = {n650, n653};
assign n655 = {n650, n654};
assign n656 = {n650, n655};
assign n657 = {n650, n656};
assign n658 = {n617[17],
n617[16],
n617[15],
n617[14],
n617[13],
n617[12],
n617[11],
n617[10],
n617[9],
n617[8],
n617[7]};
assign n659 = {n657, n658};
assign n660 = n613 - n659;
assign n661 = n613 + n659;
assign n662 =
n649 == 1'b0 ? n660 :
n661;
assign n667 = ~n649;
assign n668 = n613[17];
assign n669 = n668;
assign n670 = {n668, n669};
assign n671 = {n668, n670};
assign n672 = {n668, n671};
assign n673 = {n668, n672};
assign n674 = {n668, n673};
assign n675 = {n668, n674};
assign n676 = {n613[17],
n613[16],
n613[15],
n613[14],
n613[13],
n613[12],
n613[11],
n613[10],
n613[9],
n613[8],
n613[7]};
assign n677 = {n675, n676};
assign n678 = n617 - n677;
assign n679 = n617 + n677;
assign n680 =
n667 == 1'b0 ? n678 :
n679;
assign n685 = 18'b000000001111111111;
assign n686 = n621 - n685;
assign n687 = n621 + n685;
assign n688 =
n649 == 1'b0 ? n686 :
n687;
assign n705 = n8;
assign n706 = {n8, n705};
assign n707 = {n8, n706};
assign n708 = {n8, n707};
assign n709 = {n8, n708};
assign n710 = {n8, n709};
assign n711 = {n8, n710};
assign n712 = {n8, n711};
assign n713 = {n8, n712};
assign n714 = {n8, n713};
assign n715 = {n8, n714};
assign n716 = {n8, n715};
assign n717 = {n8, n716};
assign n718 = {n8, n717};
assign n719 = {n8, n718};
assign n720 = {n8, n719};
assign n721 = {n8, n720};
assign n722 = {n8, n721};
assign n723 = n700[17];
assign n724 = ~n723;
assign n725 = {n700[16],
n700[15],
n700[14],
n700[13],
n700[12],
n700[11],
n700[10],
n700[9],
n700[8],
n700[7],
n700[6],
n700[5],
n700[4],
n700[3],
n700[2],
n700[1],
n700[0]};
assign n726 = {n724, n725};
assign n727 = n722[17];
assign n728 = ~n727;
assign n729 = {n722[16],
n722[15],
n722[14],
n722[13],
n722[12],
n722[11],
n722[10],
n722[9],
n722[8],
n722[7],
n722[6],
n722[5],
n722[4],
n722[3],
n722[2],
n722[1],
n722[0]};
assign n730 = {n728, n729};
assign n731 = n726 <= n730;
assign n732 = ~n731;
assign n733 = n700[17];
assign n734 = n733;
assign n735 = {n733, n734};
assign n736 = {n733, n735};
assign n737 = {n733, n736};
assign n738 = {n733, n737};
assign n739 = {n733, n738};
assign n740 = {n733, n739};
assign n741 = {n733, n740};
assign n742 = {n700[17],
n700[16],
n700[15],
n700[14],
n700[13],
n700[12],
n700[11],
n700[10],
n700[9],
n700[8]};
assign n743 = {n741, n742};
assign n744 = n696 - n743;
assign n745 = n696 + n743;
assign n746 =
n732 == 1'b0 ? n744 :
n745;
assign n751 = ~n732;
assign n752 = n696[17];
assign n753 = n752;
assign n754 = {n752, n753};
assign n755 = {n752, n754};
assign n756 = {n752, n755};
assign n757 = {n752, n756};
assign n758 = {n752, n757};
assign n759 = {n752, n758};
assign n760 = {n752, n759};
assign n761 = {n696[17],
n696[16],
n696[15],
n696[14],
n696[13],
n696[12],
n696[11],
n696[10],
n696[9],
n696[8]};
assign n762 = {n760, n761};
assign n763 = n700 - n762;
assign n764 = n700 + n762;
assign n765 =
n751 == 1'b0 ? n763 :
n764;
assign n770 = 18'b000000000111111111;
assign n771 = n704 - n770;
assign n772 = n704 + n770;
assign n773 =
n732 == 1'b0 ? n771 :
n772;
assign n790 = n8;
assign n791 = {n8, n790};
assign n792 = {n8, n791};
assign n793 = {n8, n792};
assign n794 = {n8, n793};
assign n795 = {n8, n794};
assign n796 = {n8, n795};
assign n797 = {n8, n796};
assign n798 = {n8, n797};
assign n799 = {n8, n798};
assign n800 = {n8, n799};
assign n801 = {n8, n800};
assign n802 = {n8, n801};
assign n803 = {n8, n802};
assign n804 = {n8, n803};
assign n805 = {n8, n804};
assign n806 = {n8, n805};
assign n807 = {n8, n806};
assign n808 = n785[17];
assign n809 = ~n808;
assign n810 = {n785[16],
n785[15],
n785[14],
n785[13],
n785[12],
n785[11],
n785[10],
n785[9],
n785[8],
n785[7],
n785[6],
n785[5],
n785[4],
n785[3],
n785[2],
n785[1],
n785[0]};
assign n811 = {n809, n810};
assign n812 = n807[17];
assign n813 = ~n812;
assign n814 = {n807[16],
n807[15],
n807[14],
n807[13],
n807[12],
n807[11],
n807[10],
n807[9],
n807[8],
n807[7],
n807[6],
n807[5],
n807[4],
n807[3],
n807[2],
n807[1],
n807[0]};
assign n815 = {n813, n814};
assign n816 = n811 <= n815;
assign n817 = ~n816;
assign n818 = n785[17];
assign n819 = n818;
assign n820 = {n818, n819};
assign n821 = {n818, n820};
assign n822 = {n818, n821};
assign n823 = {n818, n822};
assign n824 = {n818, n823};
assign n825 = {n818, n824};
assign n826 = {n818, n825};
assign n827 = {n818, n826};
assign n828 = {n785[17],
n785[16],
n785[15],
n785[14],
n785[13],
n785[12],
n785[11],
n785[10],
n785[9]};
assign n829 = {n827, n828};
assign n830 = n781 - n829;
assign n831 = n781 + n829;
assign n832 =
n817 == 1'b0 ? n830 :
n831;
assign n837 = ~n817;
assign n838 = n781[17];
assign n839 = n838;
assign n840 = {n838, n839};
assign n841 = {n838, n840};
assign n842 = {n838, n841};
assign n843 = {n838, n842};
assign n844 = {n838, n843};
assign n845 = {n838, n844};
assign n846 = {n838, n845};
assign n847 = {n838, n846};
assign n848 = {n781[17],
n781[16],
n781[15],
n781[14],
n781[13],
n781[12],
n781[11],
n781[10],
n781[9]};
assign n849 = {n847, n848};
assign n850 = n785 - n849;
assign n851 = n785 + n849;
assign n852 =
n837 == 1'b0 ? n850 :
n851;
assign n857 = 18'b000000000011111111;
assign n858 = n789 - n857;
assign n859 = n789 + n857;
assign n860 =
n817 == 1'b0 ? n858 :
n859;
assign n877 = n8;
assign n878 = {n8, n877};
assign n879 = {n8, n878};
assign n880 = {n8, n879};
assign n881 = {n8, n880};
assign n882 = {n8, n881};
assign n883 = {n8, n882};
assign n884 = {n8, n883};
assign n885 = {n8, n884};
assign n886 = {n8, n885};
assign n887 = {n8, n886};
assign n888 = {n8, n887};
assign n889 = {n8, n888};
assign n890 = {n8, n889};
assign n891 = {n8, n890};
assign n892 = {n8, n891};
assign n893 = {n8, n892};
assign n894 = {n8, n893};
assign n895 = n872[17];
assign n896 = ~n895;
assign n897 = {n872[16],
n872[15],
n872[14],
n872[13],
n872[12],
n872[11],
n872[10],
n872[9],
n872[8],
n872[7],
n872[6],
n872[5],
n872[4],
n872[3],
n872[2],
n872[1],
n872[0]};
assign n898 = {n896, n897};
assign n899 = n894[17];
assign n900 = ~n899;
assign n901 = {n894[16],
n894[15],
n894[14],
n894[13],
n894[12],
n894[11],
n894[10],
n894[9],
n894[8],
n894[7],
n894[6],
n894[5],
n894[4],
n894[3],
n894[2],
n894[1],
n894[0]};
assign n902 = {n900, n901};
assign n903 = n898 <= n902;
assign n904 = ~n903;
assign n905 = n872[17];
assign n906 = n905;
assign n907 = {n905, n906};
assign n908 = {n905, n907};
assign n909 = {n905, n908};
assign n910 = {n905, n909};
assign n911 = {n905, n910};
assign n912 = {n905, n911};
assign n913 = {n905, n912};
assign n914 = {n905, n913};
assign n915 = {n905, n914};
assign n916 = {n872[17],
n872[16],
n872[15],
n872[14],
n872[13],
n872[12],
n872[11],
n872[10]};
assign n917 = {n915, n916};
assign n918 = n868 - n917;
assign n919 = n868 + n917;
assign n920 =
n904 == 1'b0 ? n918 :
n919;
assign n925 = ~n904;
assign n926 = n868[17];
assign n927 = n926;
assign n928 = {n926, n927};
assign n929 = {n926, n928};
assign n930 = {n926, n929};
assign n931 = {n926, n930};
assign n932 = {n926, n931};
assign n933 = {n926, n932};
assign n934 = {n926, n933};
assign n935 = {n926, n934};
assign n936 = {n926, n935};
assign n937 = {n868[17],
n868[16],
n868[15],
n868[14],
n868[13],
n868[12],
n868[11],
n868[10]};
assign n938 = {n936, n937};
assign n939 = n872 - n938;
assign n940 = n872 + n938;
assign n941 =
n925 == 1'b0 ? n939 :
n940;
assign n946 = 18'b000000000001111111;
assign n947 = n876 - n946;
assign n948 = n876 + n946;
assign n949 =
n904 == 1'b0 ? n947 :
n948;
assign n966 = n8;
assign n967 = {n8, n966};
assign n968 = {n8, n967};
assign n969 = {n8, n968};
assign n970 = {n8, n969};
assign n971 = {n8, n970};
assign n972 = {n8, n971};
assign n973 = {n8, n972};
assign n974 = {n8, n973};
assign n975 = {n8, n974};
assign n976 = {n8, n975};
assign n977 = {n8, n976};
assign n978 = {n8, n977};
assign n979 = {n8, n978};
assign n980 = {n8, n979};
assign n981 = {n8, n980};
assign n982 = {n8, n981};
assign n983 = {n8, n982};
assign n984 = n961[17];
assign n985 = ~n984;
assign n986 = {n961[16],
n961[15],
n961[14],
n961[13],
n961[12],
n961[11],
n961[10],
n961[9],
n961[8],
n961[7],
n961[6],
n961[5],
n961[4],
n961[3],
n961[2],
n961[1],
n961[0]};
assign n987 = {n985, n986};
assign n988 = n983[17];
assign n989 = ~n988;
assign n990 = {n983[16],
n983[15],
n983[14],
n983[13],
n983[12],
n983[11],
n983[10],
n983[9],
n983[8],
n983[7],
n983[6],
n983[5],
n983[4],
n983[3],
n983[2],
n983[1],
n983[0]};
assign n991 = {n989, n990};
assign n992 = n987 <= n991;
assign n993 = ~n992;
assign n994 = n961[17];
assign n995 = n994;
assign n996 = {n994, n995};
assign n997 = {n994, n996};
assign n998 = {n994, n997};
assign n999 = {n994, n998};
assign n1000 = {n994, n999};
assign n1001 = {n994, n1000};
assign n1002 = {n994, n1001};
assign n1003 = {n994, n1002};
assign n1004 = {n994, n1003};
assign n1005 = {n994, n1004};
assign n1006 = {n961[17],
n961[16],
n961[15],
n961[14],
n961[13],
n961[12],
n961[11]};
assign n1007 = {n1005, n1006};
assign n1008 = n957 - n1007;
assign n1009 = n957 + n1007;
assign n1010 =
n993 == 1'b0 ? n1008 :
n1009;
assign n1015 = ~n993;
assign n1016 = n957[17];
assign n1017 = n1016;
assign n1018 = {n1016, n1017};
assign n1019 = {n1016, n1018};
assign n1020 = {n1016, n1019};
assign n1021 = {n1016, n1020};
assign n1022 = {n1016, n1021};
assign n1023 = {n1016, n1022};
assign n1024 = {n1016, n1023};
assign n1025 = {n1016, n1024};
assign n1026 = {n1016, n1025};
assign n1027 = {n1016, n1026};
assign n1028 = {n957[17],
n957[16],
n957[15],
n957[14],
n957[13],
n957[12],
n957[11]};
assign n1029 = {n1027, n1028};
assign n1030 = n961 - n1029;
assign n1031 = n961 + n1029;
assign n1032 =
n1015 == 1'b0 ? n1030 :
n1031;
assign n1037 = 18'b000000000000111111;
assign n1038 = n965 - n1037;
assign n1039 = n965 + n1037;
assign n1040 =
n993 == 1'b0 ? n1038 :
n1039;
assign n1057 = n8;
assign n1058 = {n8, n1057};
assign n1059 = {n8, n1058};
assign n1060 = {n8, n1059};
assign n1061 = {n8, n1060};
assign n1062 = {n8, n1061};
assign n1063 = {n8, n1062};
assign n1064 = {n8, n1063};
assign n1065 = {n8, n1064};
assign n1066 = {n8, n1065};
assign n1067 = {n8, n1066};
assign n1068 = {n8, n1067};
assign n1069 = {n8, n1068};
assign n1070 = {n8, n1069};
assign n1071 = {n8, n1070};
assign n1072 = {n8, n1071};
assign n1073 = {n8, n1072};
assign n1074 = {n8, n1073};
assign n1075 = n1052[17];
assign n1076 = ~n1075;
assign n1077 = {n1052[16],
n1052[15],
n1052[14],
n1052[13],
n1052[12],
n1052[11],
n1052[10],
n1052[9],
n1052[8],
n1052[7],
n1052[6],
n1052[5],
n1052[4],
n1052[3],
n1052[2],
n1052[1],
n1052[0]};
assign n1078 = {n1076, n1077};
assign n1079 = n1074[17];
assign n1080 = ~n1079;
assign n1081 = {n1074[16],
n1074[15],
n1074[14],
n1074[13],
n1074[12],
n1074[11],
n1074[10],
n1074[9],
n1074[8],
n1074[7],
n1074[6],
n1074[5],
n1074[4],
n1074[3],
n1074[2],
n1074[1],
n1074[0]};
assign n1082 = {n1080, n1081};
assign n1083 = n1078 <= n1082;
assign n1084 = ~n1083;
assign n1085 = n1052[17];
assign n1086 = n1085;
assign n1087 = {n1085, n1086};
assign n1088 = {n1085, n1087};
assign n1089 = {n1085, n1088};
assign n1090 = {n1085, n1089};
assign n1091 = {n1085, n1090};
assign n1092 = {n1085, n1091};
assign n1093 = {n1085, n1092};
assign n1094 = {n1085, n1093};
assign n1095 = {n1085, n1094};
assign n1096 = {n1085, n1095};
assign n1097 = {n1085, n1096};
assign n1098 = {n1052[17],
n1052[16],
n1052[15],
n1052[14],
n1052[13],
n1052[12]};
assign n1099 = {n1097, n1098};
assign n1100 = n1048 - n1099;
assign n1101 = n1048 + n1099;
assign n1102 =
n1084 == 1'b0 ? n1100 :
n1101;
assign n1107 = ~n1084;
assign n1108 = n1048[17];
assign n1109 = n1108;
assign n1110 = {n1108, n1109};
assign n1111 = {n1108, n1110};
assign n1112 = {n1108, n1111};
assign n1113 = {n1108, n1112};
assign n1114 = {n1108, n1113};
assign n1115 = {n1108, n1114};
assign n1116 = {n1108, n1115};
assign n1117 = {n1108, n1116};
assign n1118 = {n1108, n1117};
assign n1119 = {n1108, n1118};
assign n1120 = {n1108, n1119};
assign n1121 = {n1048[17],
n1048[16],
n1048[15],
n1048[14],
n1048[13],
n1048[12]};
assign n1122 = {n1120, n1121};
assign n1123 = n1052 - n1122;
assign n1124 = n1052 + n1122;
assign n1125 =
n1107 == 1'b0 ? n1123 :
n1124;
assign n1130 = 18'b000000000000011111;
assign n1131 = n1056 - n1130;
assign n1132 = n1056 + n1130;
assign n1133 =
n1084 == 1'b0 ? n1131 :
n1132;
assign n1150 = n8;
assign n1151 = {n8, n1150};
assign n1152 = {n8, n1151};
assign n1153 = {n8, n1152};
assign n1154 = {n8, n1153};
assign n1155 = {n8, n1154};
assign n1156 = {n8, n1155};
assign n1157 = {n8, n1156};
assign n1158 = {n8, n1157};
assign n1159 = {n8, n1158};
assign n1160 = {n8, n1159};
assign n1161 = {n8, n1160};
assign n1162 = {n8, n1161};
assign n1163 = {n8, n1162};
assign n1164 = {n8, n1163};
assign n1165 = {n8, n1164};
assign n1166 = {n8, n1165};
assign n1167 = {n8, n1166};
assign n1168 = n1145[17];
assign n1169 = ~n1168;
assign n1170 = {n1145[16],
n1145[15],
n1145[14],
n1145[13],
n1145[12],
n1145[11],
n1145[10],
n1145[9],
n1145[8],
n1145[7],
n1145[6],
n1145[5],
n1145[4],
n1145[3],
n1145[2],
n1145[1],
n1145[0]};
assign n1171 = {n1169, n1170};
assign n1172 = n1167[17];
assign n1173 = ~n1172;
assign n1174 = {n1167[16],
n1167[15],
n1167[14],
n1167[13],
n1167[12],
n1167[11],
n1167[10],
n1167[9],
n1167[8],
n1167[7],
n1167[6],
n1167[5],
n1167[4],
n1167[3],
n1167[2],
n1167[1],
n1167[0]};
assign n1175 = {n1173, n1174};
assign n1176 = n1171 <= n1175;
assign n1177 = ~n1176;
assign n1178 = n1145[17];
assign n1179 = n1178;
assign n1180 = {n1178, n1179};
assign n1181 = {n1178, n1180};
assign n1182 = {n1178, n1181};
assign n1183 = {n1178, n1182};
assign n1184 = {n1178, n1183};
assign n1185 = {n1178, n1184};
assign n1186 = {n1178, n1185};
assign n1187 = {n1178, n1186};
assign n1188 = {n1178, n1187};
assign n1189 = {n1178, n1188};
assign n1190 = {n1178, n1189};
assign n1191 = {n1178, n1190};
assign n1192 = {n1145[17],
n1145[16],
n1145[15],
n1145[14],
n1145[13]};
assign n1193 = {n1191, n1192};
assign n1194 = n1141 - n1193;
assign n1195 = n1141 + n1193;
assign n1196 =
n1177 == 1'b0 ? n1194 :
n1195;
assign n1201 = ~n1177;
assign n1202 = n1141[17];
assign n1203 = n1202;
assign n1204 = {n1202, n1203};
assign n1205 = {n1202, n1204};
assign n1206 = {n1202, n1205};
assign n1207 = {n1202, n1206};
assign n1208 = {n1202, n1207};
assign n1209 = {n1202, n1208};
assign n1210 = {n1202, n1209};
assign n1211 = {n1202, n1210};
assign n1212 = {n1202, n1211};
assign n1213 = {n1202, n1212};
assign n1214 = {n1202, n1213};
assign n1215 = {n1202, n1214};
assign n1216 = {n1141[17],
n1141[16],
n1141[15],
n1141[14],
n1141[13]};
assign n1217 = {n1215, n1216};
assign n1218 = n1145 - n1217;
assign n1219 = n1145 + n1217;
assign n1220 =
n1201 == 1'b0 ? n1218 :
n1219;
assign n1225 = 18'b000000000000001111;
assign n1226 = n1149 - n1225;
assign n1227 = n1149 + n1225;
assign n1228 =
n1177 == 1'b0 ? n1226 :
n1227;
assign n1245 = n8;
assign n1246 = {n8, n1245};
assign n1247 = {n8, n1246};
assign n1248 = {n8, n1247};
assign n1249 = {n8, n1248};
assign n1250 = {n8, n1249};
assign n1251 = {n8, n1250};
assign n1252 = {n8, n1251};
assign n1253 = {n8, n1252};
assign n1254 = {n8, n1253};
assign n1255 = {n8, n1254};
assign n1256 = {n8, n1255};
assign n1257 = {n8, n1256};
assign n1258 = {n8, n1257};
assign n1259 = {n8, n1258};
assign n1260 = {n8, n1259};
assign n1261 = {n8, n1260};
assign n1262 = {n8, n1261};
assign n1263 = n1240[17];
assign n1264 = ~n1263;
assign n1265 = {n1240[16],
n1240[15],
n1240[14],
n1240[13],
n1240[12],
n1240[11],
n1240[10],
n1240[9],
n1240[8],
n1240[7],
n1240[6],
n1240[5],
n1240[4],
n1240[3],
n1240[2],
n1240[1],
n1240[0]};
assign n1266 = {n1264, n1265};
assign n1267 = n1262[17];
assign n1268 = ~n1267;
assign n1269 = {n1262[16],
n1262[15],
n1262[14],
n1262[13],
n1262[12],
n1262[11],
n1262[10],
n1262[9],
n1262[8],
n1262[7],
n1262[6],
n1262[5],
n1262[4],
n1262[3],
n1262[2],
n1262[1],
n1262[0]};
assign n1270 = {n1268, n1269};
assign n1271 = n1266 <= n1270;
assign n1272 = ~n1271;
assign n1273 = n1240[17];
assign n1274 = n1273;
assign n1275 = {n1273, n1274};
assign n1276 = {n1273, n1275};
assign n1277 = {n1273, n1276};
assign n1278 = {n1273, n1277};
assign n1279 = {n1273, n1278};
assign n1280 = {n1273, n1279};
assign n1281 = {n1273, n1280};
assign n1282 = {n1273, n1281};
assign n1283 = {n1273, n1282};
assign n1284 = {n1273, n1283};
assign n1285 = {n1273, n1284};
assign n1286 = {n1273, n1285};
assign n1287 = {n1273, n1286};
assign n1288 = {n1240[17],
n1240[16],
n1240[15],
n1240[14]};
assign n1289 = {n1287, n1288};
assign n1290 = n1236 - n1289;
assign n1291 = n1236 + n1289;
assign n1292 =
n1272 == 1'b0 ? n1290 :
n1291;
assign n1297 = ~n1272;
assign n1298 = n1236[17];
assign n1299 = n1298;
assign n1300 = {n1298, n1299};
assign n1301 = {n1298, n1300};
assign n1302 = {n1298, n1301};
assign n1303 = {n1298, n1302};
assign n1304 = {n1298, n1303};
assign n1305 = {n1298, n1304};
assign n1306 = {n1298, n1305};
assign n1307 = {n1298, n1306};
assign n1308 = {n1298, n1307};
assign n1309 = {n1298, n1308};
assign n1310 = {n1298, n1309};
assign n1311 = {n1298, n1310};
assign n1312 = {n1298, n1311};
assign n1313 = {n1236[17],
n1236[16],
n1236[15],
n1236[14]};
assign n1314 = {n1312, n1313};
assign n1315 = n1240 - n1314;
assign n1316 = n1240 + n1314;
assign n1317 =
n1297 == 1'b0 ? n1315 :
n1316;
assign n1322 = 18'b000000000000000111;
assign n1323 = n1244 - n1322;
assign n1324 = n1244 + n1322;
assign n1325 =
n1272 == 1'b0 ? n1323 :
n1324;
assign n1342 = n8;
assign n1343 = {n8, n1342};
assign n1344 = {n8, n1343};
assign n1345 = {n8, n1344};
assign n1346 = {n8, n1345};
assign n1347 = {n8, n1346};
assign n1348 = {n8, n1347};
assign n1349 = {n8, n1348};
assign n1350 = {n8, n1349};
assign n1351 = {n8, n1350};
assign n1352 = {n8, n1351};
assign n1353 = {n8, n1352};
assign n1354 = {n8, n1353};
assign n1355 = {n8, n1354};
assign n1356 = {n8, n1355};
assign n1357 = {n8, n1356};
assign n1358 = {n8, n1357};
assign n1359 = {n8, n1358};
assign n1360 = n1337[17];
assign n1361 = ~n1360;
assign n1362 = {n1337[16],
n1337[15],
n1337[14],
n1337[13],
n1337[12],
n1337[11],
n1337[10],
n1337[9],
n1337[8],
n1337[7],
n1337[6],
n1337[5],
n1337[4],
n1337[3],
n1337[2],
n1337[1],
n1337[0]};
assign n1363 = {n1361, n1362};
assign n1364 = n1359[17];
assign n1365 = ~n1364;
assign n1366 = {n1359[16],
n1359[15],
n1359[14],
n1359[13],
n1359[12],
n1359[11],
n1359[10],
n1359[9],
n1359[8],
n1359[7],
n1359[6],
n1359[5],
n1359[4],
n1359[3],
n1359[2],
n1359[1],
n1359[0]};
assign n1367 = {n1365, n1366};
assign n1368 = n1363 <= n1367;
assign n1369 = ~n1368;
assign n1370 = n1337[17];
assign n1371 = n1370;
assign n1372 = {n1370, n1371};
assign n1373 = {n1370, n1372};
assign n1374 = {n1370, n1373};
assign n1375 = {n1370, n1374};
assign n1376 = {n1370, n1375};
assign n1377 = {n1370, n1376};
assign n1378 = {n1370, n1377};
assign n1379 = {n1370, n1378};
assign n1380 = {n1370, n1379};
assign n1381 = {n1370, n1380};
assign n1382 = {n1370, n1381};
assign n1383 = {n1370, n1382};
assign n1384 = {n1370, n1383};
assign n1385 = {n1370, n1384};
assign n1386 = {n1337[17],
n1337[16],
n1337[15]};
assign n1387 = {n1385, n1386};
assign n1388 = n1333 - n1387;
assign n1389 = n1333 + n1387;
assign n1390 =
n1369 == 1'b0 ? n1388 :
n1389;
assign n1395 = ~n1369;
assign n1396 = n1333[17];
assign n1397 = n1396;
assign n1398 = {n1396, n1397};
assign n1399 = {n1396, n1398};
assign n1400 = {n1396, n1399};
assign n1401 = {n1396, n1400};
assign n1402 = {n1396, n1401};
assign n1403 = {n1396, n1402};
assign n1404 = {n1396, n1403};
assign n1405 = {n1396, n1404};
assign n1406 = {n1396, n1405};
assign n1407 = {n1396, n1406};
assign n1408 = {n1396, n1407};
assign n1409 = {n1396, n1408};
assign n1410 = {n1396, n1409};
assign n1411 = {n1396, n1410};
assign n1412 = {n1333[17],
n1333[16],
n1333[15]};
assign n1413 = {n1411, n1412};
assign n1414 = n1337 - n1413;
assign n1415 = n1337 + n1413;
assign n1416 =
n1395 == 1'b0 ? n1414 :
n1415;
assign n1421 = 18'b000000000000000011;
assign n1422 = n1341 - n1421;
assign n1423 = n1341 + n1421;
assign n1424 =
n1369 == 1'b0 ? n1422 :
n1423;
assign n1441 = n8;
assign n1442 = {n8, n1441};
assign n1443 = {n8, n1442};
assign n1444 = {n8, n1443};
assign n1445 = {n8, n1444};
assign n1446 = {n8, n1445};
assign n1447 = {n8, n1446};
assign n1448 = {n8, n1447};
assign n1449 = {n8, n1448};
assign n1450 = {n8, n1449};
assign n1451 = {n8, n1450};
assign n1452 = {n8, n1451};
assign n1453 = {n8, n1452};
assign n1454 = {n8, n1453};
assign n1455 = {n8, n1454};
assign n1456 = {n8, n1455};
assign n1457 = {n8, n1456};
assign n1458 = {n8, n1457};
assign n1459 = n1436[17];
assign n1460 = ~n1459;
assign n1461 = {n1436[16],
n1436[15],
n1436[14],
n1436[13],
n1436[12],
n1436[11],
n1436[10],
n1436[9],
n1436[8],
n1436[7],
n1436[6],
n1436[5],
n1436[4],
n1436[3],
n1436[2],
n1436[1],
n1436[0]};
assign n1462 = {n1460, n1461};
assign n1463 = n1458[17];
assign n1464 = ~n1463;
assign n1465 = {n1458[16],
n1458[15],
n1458[14],
n1458[13],
n1458[12],
n1458[11],
n1458[10],
n1458[9],
n1458[8],
n1458[7],
n1458[6],
n1458[5],
n1458[4],
n1458[3],
n1458[2],
n1458[1],
n1458[0]};
assign n1466 = {n1464, n1465};
assign n1467 = n1462 <= n1466;
assign n1468 = ~n1467;
assign n1469 = n1436[17];
assign n1470 = n1469;
assign n1471 = {n1469, n1470};
assign n1472 = {n1469, n1471};
assign n1473 = {n1469, n1472};
assign n1474 = {n1469, n1473};
assign n1475 = {n1469, n1474};
assign n1476 = {n1469, n1475};
assign n1477 = {n1469, n1476};
assign n1478 = {n1469, n1477};
assign n1479 = {n1469, n1478};
assign n1480 = {n1469, n1479};
assign n1481 = {n1469, n1480};
assign n1482 = {n1469, n1481};
assign n1483 = {n1469, n1482};
assign n1484 = {n1469, n1483};
assign n1485 = {n1469, n1484};
assign n1486 = {n1436[17],
n1436[16]};
assign n1487 = {n1485, n1486};
assign n1488 = n1432 - n1487;
assign n1489 = n1432 + n1487;
assign n1490 =
n1468 == 1'b0 ? n1488 :
n1489;
assign n1495 = ~n1468;
assign n1496 = n1432[17];
assign n1497 = n1496;
assign n1498 = {n1496, n1497};
assign n1499 = {n1496, n1498};
assign n1500 = {n1496, n1499};
assign n1501 = {n1496, n1500};
assign n1502 = {n1496, n1501};
assign n1503 = {n1496, n1502};
assign n1504 = {n1496, n1503};
assign n1505 = {n1496, n1504};
assign n1506 = {n1496, n1505};
assign n1507 = {n1496, n1506};
assign n1508 = {n1496, n1507};
assign n1509 = {n1496, n1508};
assign n1510 = {n1496, n1509};
assign n1511 = {n1496, n1510};
assign n1512 = {n1496, n1511};
assign n1513 = {n1432[17],
n1432[16]};
assign n1514 = {n1512, n1513};
assign n1515 = n1436 - n1514;
assign n1516 = n1436 + n1514;
assign n1517 =
n1495 == 1'b0 ? n1515 :
n1516;
assign n1522 = 18'b000000000000000001;
assign n1523 = n1440 - n1522;
assign n1524 = n1440 + n1522;
assign n1525 =
n1468 == 1'b0 ? n1523 :
n1524;
assign n1542 = n8;
assign n1543 = {n8, n1542};
assign n1544 = {n8, n1543};
assign n1545 = {n8, n1544};
assign n1546 = {n8, n1545};
assign n1547 = {n8, n1546};
assign n1548 = {n8, n1547};
assign n1549 = {n8, n1548};
assign n1550 = {n8, n1549};
assign n1551 = {n8, n1550};
assign n1552 = {n8, n1551};
assign n1553 = {n8, n1552};
assign n1554 = {n8, n1553};
assign n1555 = {n8, n1554};
assign n1556 = {n8, n1555};
assign n1557 = {n8, n1556};
assign n1558 = {n8, n1557};
assign n1559 = {n8, n1558};
assign n1560 = n1537[17];
assign n1561 = ~n1560;
assign n1562 = {n1537[16],
n1537[15],
n1537[14],
n1537[13],
n1537[12],
n1537[11],
n1537[10],
n1537[9],
n1537[8],
n1537[7],
n1537[6],
n1537[5],
n1537[4],
n1537[3],
n1537[2],
n1537[1],
n1537[0]};
assign n1563 = {n1561, n1562};
assign n1564 = n1559[17];
assign n1565 = ~n1564;
assign n1566 = {n1559[16],
n1559[15],
n1559[14],
n1559[13],
n1559[12],
n1559[11],
n1559[10],
n1559[9],
n1559[8],
n1559[7],
n1559[6],
n1559[5],
n1559[4],
n1559[3],
n1559[2],
n1559[1],
n1559[0]};
assign n1567 = {n1565, n1566};
assign n1568 = n1563 <= n1567;
assign n1569 = ~n1568;
assign n1570 = n1537[17];
assign n1571 = n1570;
assign n1572 = {n1570, n1571};
assign n1573 = {n1570, n1572};
assign n1574 = {n1570, n1573};
assign n1575 = {n1570, n1574};
assign n1576 = {n1570, n1575};
assign n1577 = {n1570, n1576};
assign n1578 = {n1570, n1577};
assign n1579 = {n1570, n1578};
assign n1580 = {n1570, n1579};
assign n1581 = {n1570, n1580};
assign n1582 = {n1570, n1581};
assign n1583 = {n1570, n1582};
assign n1584 = {n1570, n1583};
assign n1585 = {n1570, n1584};
assign n1586 = {n1570, n1585};
assign n1587 = {n1570, n1586};
assign n1588 = n1537[17];
assign n1589 = {n1587, n1588};
assign n1590 = n1533 - n1589;
assign n1591 = n1533 + n1589;
assign n1592 =
n1569 == 1'b0 ? n1590 :
n1591;
assign n1597 = ~n1569;
assign n1598 = n1533[17];
assign n1599 = n1598;
assign n1600 = {n1598, n1599};
assign n1601 = {n1598, n1600};
assign n1602 = {n1598, n1601};
assign n1603 = {n1598, n1602};
assign n1604 = {n1598, n1603};
assign n1605 = {n1598, n1604};
assign n1606 = {n1598, n1605};
assign n1607 = {n1598, n1606};
assign n1608 = {n1598, n1607};
assign n1609 = {n1598, n1608};
assign n1610 = {n1598, n1609};
assign n1611 = {n1598, n1610};
assign n1612 = {n1598, n1611};
assign n1613 = {n1598, n1612};
assign n1614 = {n1598, n1613};
assign n1615 = {n1598, n1614};
assign n1616 = n1533[17];
assign n1617 = {n1615, n1616};
assign n1618 = n1537 - n1617;
assign n1619 = n1537 + n1617;
assign n1620 =
n1597 == 1'b0 ? n1618 :
n1619;
assign n1625 = n1541 - n6;
assign n1626 = n1541 + n6;
assign n1627 =
n1569 == 1'b0 ? n1625 :
n1626;
assign real_o = n1596;
assign imag_o = n1624;
assign ang_o = n1631;
assign n1635 = enable_i & n50;
assign n1636 = n8 | n1635;
assign n1637 = n50 & n1636;
assign n1638 = reset_i | n8;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n11 <= 18'b000000000000000000;
else
n11 <= real_i;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n15 <= 18'b000000000000000000;
else
n15 <= imag_i;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n19 <= 18'b000000000000000000;
else
n19 <= ang_i;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n74 <= 18'b000000000000000000;
else
n74 <= n70;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n79 <= 18'b000000000000000000;
else
n79 <= n75;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n84 <= 18'b000000000000000000;
else
n84 <= n80;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n88 <= 18'b000000000000000000;
else
n88 <= n74;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n92 <= 18'b000000000000000000;
else
n92 <= n79;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n96 <= 18'b000000000000000000;
else
n96 <= n84;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n134 <= 18'b000000000000000000;
else
n134 <= n130;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n145 <= 18'b000000000000000000;
else
n145 <= n141;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n153 <= 18'b000000000000000000;
else
n153 <= n149;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n157 <= 18'b000000000000000000;
else
n157 <= n134;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n161 <= 18'b000000000000000000;
else
n161 <= n145;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n165 <= 18'b000000000000000000;
else
n165 <= n153;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n204 <= 18'b000000000000000000;
else
n204 <= n200;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n216 <= 18'b000000000000000000;
else
n216 <= n212;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n224 <= 18'b000000000000000000;
else
n224 <= n220;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n228 <= 18'b000000000000000000;
else
n228 <= n204;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n232 <= 18'b000000000000000000;
else
n232 <= n216;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n236 <= 18'b000000000000000000;
else
n236 <= n224;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n276 <= 18'b000000000000000000;
else
n276 <= n272;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n289 <= 18'b000000000000000000;
else
n289 <= n285;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n297 <= 18'b000000000000000000;
else
n297 <= n293;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n301 <= 18'b000000000000000000;
else
n301 <= n276;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n305 <= 18'b000000000000000000;
else
n305 <= n289;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n309 <= 18'b000000000000000000;
else
n309 <= n297;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n350 <= 18'b000000000000000000;
else
n350 <= n346;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n364 <= 18'b000000000000000000;
else
n364 <= n360;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n372 <= 18'b000000000000000000;
else
n372 <= n368;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n376 <= 18'b000000000000000000;
else
n376 <= n350;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n380 <= 18'b000000000000000000;
else
n380 <= n364;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n384 <= 18'b000000000000000000;
else
n384 <= n372;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n426 <= 18'b000000000000000000;
else
n426 <= n422;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n441 <= 18'b000000000000000000;
else
n441 <= n437;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n449 <= 18'b000000000000000000;
else
n449 <= n445;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n453 <= 18'b000000000000000000;
else
n453 <= n426;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n457 <= 18'b000000000000000000;
else
n457 <= n441;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n461 <= 18'b000000000000000000;
else
n461 <= n449;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n504 <= 18'b000000000000000000;
else
n504 <= n500;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n520 <= 18'b000000000000000000;
else
n520 <= n516;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n528 <= 18'b000000000000000000;
else
n528 <= n524;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n532 <= 18'b000000000000000000;
else
n532 <= n504;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n536 <= 18'b000000000000000000;
else
n536 <= n520;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n540 <= 18'b000000000000000000;
else
n540 <= n528;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n584 <= 18'b000000000000000000;
else
n584 <= n580;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n601 <= 18'b000000000000000000;
else
n601 <= n597;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n609 <= 18'b000000000000000000;
else
n609 <= n605;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n613 <= 18'b000000000000000000;
else
n613 <= n584;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n617 <= 18'b000000000000000000;
else
n617 <= n601;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n621 <= 18'b000000000000000000;
else
n621 <= n609;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n666 <= 18'b000000000000000000;
else
n666 <= n662;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n684 <= 18'b000000000000000000;
else
n684 <= n680;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n692 <= 18'b000000000000000000;
else
n692 <= n688;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n696 <= 18'b000000000000000000;
else
n696 <= n666;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n700 <= 18'b000000000000000000;
else
n700 <= n684;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n704 <= 18'b000000000000000000;
else
n704 <= n692;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n750 <= 18'b000000000000000000;
else
n750 <= n746;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n769 <= 18'b000000000000000000;
else
n769 <= n765;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n777 <= 18'b000000000000000000;
else
n777 <= n773;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n781 <= 18'b000000000000000000;
else
n781 <= n750;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n785 <= 18'b000000000000000000;
else
n785 <= n769;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n789 <= 18'b000000000000000000;
else
n789 <= n777;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n836 <= 18'b000000000000000000;
else
n836 <= n832;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n856 <= 18'b000000000000000000;
else
n856 <= n852;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n864 <= 18'b000000000000000000;
else
n864 <= n860;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n868 <= 18'b000000000000000000;
else
n868 <= n836;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n872 <= 18'b000000000000000000;
else
n872 <= n856;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n876 <= 18'b000000000000000000;
else
n876 <= n864;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n924 <= 18'b000000000000000000;
else
n924 <= n920;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n945 <= 18'b000000000000000000;
else
n945 <= n941;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n953 <= 18'b000000000000000000;
else
n953 <= n949;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n957 <= 18'b000000000000000000;
else
n957 <= n924;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n961 <= 18'b000000000000000000;
else
n961 <= n945;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n965 <= 18'b000000000000000000;
else
n965 <= n953;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1014 <= 18'b000000000000000000;
else
n1014 <= n1010;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1036 <= 18'b000000000000000000;
else
n1036 <= n1032;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1044 <= 18'b000000000000000000;
else
n1044 <= n1040;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1048 <= 18'b000000000000000000;
else
n1048 <= n1014;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1052 <= 18'b000000000000000000;
else
n1052 <= n1036;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1056 <= 18'b000000000000000000;
else
n1056 <= n1044;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1106 <= 18'b000000000000000000;
else
n1106 <= n1102;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1129 <= 18'b000000000000000000;
else
n1129 <= n1125;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1137 <= 18'b000000000000000000;
else
n1137 <= n1133;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1141 <= 18'b000000000000000000;
else
n1141 <= n1106;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1145 <= 18'b000000000000000000;
else
n1145 <= n1129;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1149 <= 18'b000000000000000000;
else
n1149 <= n1137;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1200 <= 18'b000000000000000000;
else
n1200 <= n1196;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1224 <= 18'b000000000000000000;
else
n1224 <= n1220;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1232 <= 18'b000000000000000000;
else
n1232 <= n1228;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1236 <= 18'b000000000000000000;
else
n1236 <= n1200;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1240 <= 18'b000000000000000000;
else
n1240 <= n1224;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1244 <= 18'b000000000000000000;
else
n1244 <= n1232;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1296 <= 18'b000000000000000000;
else
n1296 <= n1292;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1321 <= 18'b000000000000000000;
else
n1321 <= n1317;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1329 <= 18'b000000000000000000;
else
n1329 <= n1325;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1333 <= 18'b000000000000000000;
else
n1333 <= n1296;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1337 <= 18'b000000000000000000;
else
n1337 <= n1321;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1341 <= 18'b000000000000000000;
else
n1341 <= n1329;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1394 <= 18'b000000000000000000;
else
n1394 <= n1390;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1420 <= 18'b000000000000000000;
else
n1420 <= n1416;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1428 <= 18'b000000000000000000;
else
n1428 <= n1424;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1432 <= 18'b000000000000000000;
else
n1432 <= n1394;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1436 <= 18'b000000000000000000;
else
n1436 <= n1420;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1440 <= 18'b000000000000000000;
else
n1440 <= n1428;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1494 <= 18'b000000000000000000;
else
n1494 <= n1490;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1521 <= 18'b000000000000000000;
else
n1521 <= n1517;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1529 <= 18'b000000000000000000;
else
n1529 <= n1525;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1533 <= 18'b000000000000000000;
else
n1533 <= n1494;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1537 <= 18'b000000000000000000;
else
n1537 <= n1521;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1541 <= 18'b000000000000000000;
else
n1541 <= n1529;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1596 <= 18'b000000000000000000;
else
n1596 <= n1592;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1624 <= 18'b000000000000000000;
else
n1624 <= n1620;
always @ (posedge clock_c)
if (n1637 == 1'b1)
if (n1638 == 1'b1)
n1631 <= 18'b000000000000000000;
else
n1631 <= n1627;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pixel_clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pixel_clock (
inclk0,
c0);
input inclk0;
output c0;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 125,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 81,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pixel_clock",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.400002"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.40000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pixel_clock.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "81"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pixel_clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pixel_clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pixel_clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pixel_clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pixel_clock.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pixel_clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pixel_clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_pipe_user.v
// Version : 3.0
//------------------------------------------------------------------------------
// Filename : pipe_user.v
// Description : PIPE User Module for 7 Series Transceiver
// Version : 15.3.3
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE User Module --------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_pipe_user #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_USE_MODE = "3.0", // PCIe sim version
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter RXCDRLOCK_MAX = 4'd15, // RXCDRLOCK max count
parameter RXVALID_MAX = 4'd15, // RXVALID max count
parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
)
(
//---------- Input -------------------------------------
input USER_TXUSRCLK,
input USER_RXUSRCLK,
input USER_OOBCLK_IN,
input USER_RST_N,
input USER_RXUSRCLK_RST_N,
input USER_PCLK_SEL,
input USER_RESETOVRD_START,
input USER_TXRESETDONE,
input USER_RXRESETDONE,
input USER_TXELECIDLE,
input USER_TXCOMPLIANCE,
input USER_RXCDRLOCK_IN,
input USER_RXVALID_IN,
input USER_RXSTATUS_IN,
input USER_PHYSTATUS_IN,
input USER_RATE_DONE,
input USER_RST_IDLE,
input USER_RATE_RXSYNC,
input USER_RATE_IDLE,
input USER_RATE_GEN3,
input USER_RXEQ_ADAPT_DONE,
//---------- Output ------------------------------------
output USER_OOBCLK,
output USER_RESETOVRD,
output USER_TXPMARESET,
output USER_RXPMARESET,
output USER_RXCDRRESET,
output USER_RXCDRFREQRESET,
output USER_RXDFELPMRESET,
output USER_EYESCANRESET,
output USER_TXPCSRESET,
output USER_RXPCSRESET,
output USER_RXBUFRESET,
output USER_RESETOVRD_DONE,
output USER_RESETDONE,
output USER_ACTIVE_LANE,
output USER_RXCDRLOCK_OUT,
output USER_RXVALID_OUT,
output USER_PHYSTATUS_OUT,
output USER_PHYSTATUS_RST,
output USER_GEN3_RDY,
output USER_RX_CONVERGE
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 1:0] oobclk_cnt = 2'd0;
reg [ 7:0] reset_cnt = 8'd127;
reg [ 3:0] rxcdrlock_cnt = 4'd0;
reg [ 3:0] rxvalid_cnt = 4'd0;
reg [21:0] converge_cnt = 22'd0;
reg converge_gen3 = 1'd0;
//---------- Output Registers --------------------------
reg oobclk = 1'd0;
reg [ 7:0] reset = 8'h00;
reg gen3_rdy = 1'd0;
reg [ 1:0] fsm = 2'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 2'd0;
localparam FSM_RESETOVRD = 2'd1;
localparam FSM_RESET_INIT = 2'd2;
localparam FSM_RESET = 2'd3;
//---------- Simulation Speedup ------------------------
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= 1'd0;
resetovrd_start_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txelecidle_reg1 <= 1'd0;
txcompliance_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
rxeq_adapt_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= 1'd0;
resetovrd_start_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txelecidle_reg2 <= 1'd0;
txcompliance_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
rxeq_adapt_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= USER_PCLK_SEL;
resetovrd_start_reg1 <= USER_RESETOVRD_START;
txresetdone_reg1 <= USER_TXRESETDONE;
rxresetdone_reg1 <= USER_RXRESETDONE;
txelecidle_reg1 <= USER_TXELECIDLE;
txcompliance_reg1 <= USER_TXCOMPLIANCE;
rxcdrlock_reg1 <= USER_RXCDRLOCK_IN;
rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
resetovrd_start_reg2 <= resetovrd_start_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txelecidle_reg2 <= txelecidle_reg1;
txcompliance_reg2 <= txcompliance_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1;
end
end
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= 1'd0;
rxstatus_reg1 <= 1'd0;
rst_idle_reg1 <= 1'd0;
rate_done_reg1 <= 1'd0;
rate_rxsync_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
rate_gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= 1'd0;
rxstatus_reg2 <= 1'd0;
rst_idle_reg2 <= 1'd0;
rate_done_reg2 <= 1'd0;
rate_rxsync_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
rate_gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= USER_RXVALID_IN;
rxstatus_reg1 <= USER_RXSTATUS_IN;
rst_idle_reg1 <= USER_RST_IDLE;
rate_done_reg1 <= USER_RATE_DONE;
rate_rxsync_reg1 <= USER_RATE_RXSYNC;
rate_idle_reg1 <= USER_RATE_IDLE;
rate_gen3_reg1 <= USER_RATE_GEN3;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= rxvalid_reg1;
rxstatus_reg2 <= rxstatus_reg1;
rst_idle_reg2 <= rst_idle_reg1;
rate_done_reg2 <= rate_done_reg1;
rate_rxsync_reg2 <= rate_rxsync_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rate_gen3_reg2 <= rate_gen3_reg1;
end
end
//---------- Generate Reset Override -------------------------------------------
generate if (PCIE_USE_MODE == "1.0")
begin : resetovrd
//---------- Reset Counter -------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset_cnt <= 8'd127;
else
//---------- Decrement Counter ---------------------
if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0))
reset_cnt <= reset_cnt - 8'd1;
//---------- Reset Counter -------------------------
else
case (reset)
8'b00000000 : reset_cnt <= 8'd127; // Programmable PMARESET time
8'b11111111 : reset_cnt <= 8'd127; // Programmable RXCDRRESET time
8'b11111110 : reset_cnt <= 8'd127; // Programmable RXCDRFREQRESET time
8'b11111100 : reset_cnt <= 8'd127; // Programmable RXDFELPMRESET time
8'b11111000 : reset_cnt <= 8'd127; // Programmable EYESCANRESET time
8'b11110000 : reset_cnt <= 8'd127; // Programmable PCSRESET time
8'b11100000 : reset_cnt <= 8'd127; // Programmable RXBUFRESET time
8'b11000000 : reset_cnt <= 8'd127; // Programmable RESETOVRD deassertion time
8'b10000000 : reset_cnt <= 8'd127;
default : reset_cnt <= 8'd127;
endcase
end
//---------- Reset Shift Register ------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset <= 8'h00;
else
//---------- Initialize Reset Register ---------
if (fsm == FSM_RESET_INIT)
reset <= 8'hFF;
//---------- Shift Reset Register --------------
else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0))
reset <= {reset[6:0], 1'd0};
//---------- Hold Reset Register ---------------
else
reset <= reset;
end
//---------- Reset Override FSM --------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
fsm <= FSM_IDLE;
else
begin
case (fsm)
//---------- Idle State ------------------------
FSM_IDLE : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE;
//---------- Assert RESETOVRD ------------------
FSM_RESETOVRD : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD;
//---------- Initialize Reset ------------------
FSM_RESET_INIT : fsm <= FSM_RESET;
//---------- Shift Reset -----------------------
FSM_RESET : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET;
//---------- Default State ---------------------
default : fsm <= FSM_IDLE;
endcase
end
end
end
//---------- Disable Reset Override --------------------------------------------
else
begin : resetovrd_disble
//---------- Generate Default Signals --------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
else
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
end
end
endgenerate
//---------- Generate OOB Clock Divider ------------------------
generate if (PCIE_OOBCLK_MODE == 1)
begin : oobclk_div
//---------- OOB Clock Divider -----------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= oobclk_cnt + 2'd1;
oobclk <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0];
end
end
end
else
begin : oobclk_div_disable
//---------- OOB Clock Default -------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
end
end
endgenerate
//---------- RXCDRLOCK Filter --------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
rxcdrlock_cnt <= 4'd0;
else
//---------- Increment RXCDRLOCK Counter -----------
if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1;
//---------- Hold RXCDRLOCK Counter ----------------
else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt;
//---------- Reset RXCDRLOCK Counter ---------------
else
rxcdrlock_cnt <= 4'd0;
end
//---------- RXVALID Filter ----------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
rxvalid_cnt <= 4'd0;
else
//---------- Increment RXVALID Counter -------------
if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2))
rxvalid_cnt <= rxvalid_cnt + 4'd1;
//---------- Hold RXVALID Counter ------------------
else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX))
rxvalid_cnt <= rxvalid_cnt;
//---------- Reset RXVALID Counter -----------------
else
rxvalid_cnt <= 4'd0;
end
//---------- Converge Counter --------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
converge_cnt <= 22'd0;
else
//---------- Enter Gen1/Gen2 -----------------------
if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2)
begin
//---------- Increment Converge Counter --------
if (converge_cnt < converge_max_cnt)
converge_cnt <= converge_cnt + 22'd1;
//---------- Hold Converge Counter -------------
else
converge_cnt <= converge_cnt;
end
//---------- Reset Converge Counter ----------------
else
converge_cnt <= 22'd0;
end
//---------- Converge ----------------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
converge_gen3 <= 1'd0;
else
//---------- Enter Gen3 ----------------------------
if (rate_gen3_reg2)
//---------- Wait for RX equalization adapt done
if (rxeq_adapt_done_reg2)
converge_gen3 <= 1'd1;
else
converge_gen3 <= converge_gen3;
//-------- Exit Gen3 -------------------------------
else
converge_gen3 <= 1'd0;
end
//---------- GEN3_RDY Generator ------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
gen3_rdy <= 1'd0;
else
gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2;
end
//---------- PIPE User Override Reset Output -----------------------------------
assign USER_RESETOVRD = (fsm != FSM_IDLE);
assign USER_TXPMARESET = 1'd0;
assign USER_RXPMARESET = reset[0];
assign USER_RXCDRRESET = reset[1];
assign USER_RXCDRFREQRESET = reset[2];
assign USER_RXDFELPMRESET = reset[3];
assign USER_EYESCANRESET = reset[4];
assign USER_TXPCSRESET = 1'd0;
assign USER_RXPCSRESET = reset[5];
assign USER_RXBUFRESET = reset[6];
assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE);
//---------- PIPE User Output --------------------------------------------------
assign USER_OOBCLK = oobclk;
assign USER_RESETDONE = (txresetdone_reg2 && rxresetdone_reg2);
assign USER_ACTIVE_LANE = !(txelecidle_reg2 && txcompliance_reg2);
//----------------------------------------------------------
assign USER_RXCDRLOCK_OUT = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX)); // Filtered RXCDRLOCK
//----------------------------------------------------------
assign USER_RXVALID_OUT = ((USER_RXVALID_IN && (rxvalid_cnt == RXVALID_MAX)) && // Filtered RXVALID
rst_idle_reg2 && // Force RXVALID = 0 during reset
rate_idle_reg2); // Force RXVALID = 0 during rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_OUT = (!rst_idle_reg2 || // Force PHYSTATUS = 1 during reset
((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS
rate_done_reg2); // Gated PHYSTATUS for rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_RST = !rst_idle_reg2; // Filtered PHYSTATUS for reset
//----------------------------------------------------------
assign USER_GEN3_RDY = 0;//gen3_rdy;
//----------------------------------------------------------
assign USER_RX_CONVERGE = (converge_cnt == converge_max_cnt) || converge_gen3;
endmodule
|
module bfm (/*AUTOARG*/
// Inputs
name
);
input [8*5:1] name ;
endmodule
module tb;
// -------------------------------------------------------------------------
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
// -------------------------------------------------------------------------
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
// -------------------------------------------------------------------------
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
// -------------------------------------------------------------------------
/* AUTO_CONSTANT ( "name0" "name1" "name2" ) */
// -------------------------------------------------------------------------
/* bfm AUTO_TEMPLATE (
// Inputs
.name ("name@"));
*/
// -------------------------------------------------------------------------
bfm bmf0 (/*AUTOINST*/
// Inputs
.name ("name0")); // Templated
// -------------------------------------------------------------------------
bfm bmf1 (/*AUTOINST*/
// Inputs
.name ("name1")); // Templated
// -------------------------------------------------------------------------
bfm bmf2 (/*AUTOINST*/
// Inputs
.name ("name2")); // Templated
// -------------------------------------------------------------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_16_V
`define SKY130_FD_SC_HS__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_16 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_16_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
// verilator lint_off WIDTH
`define INT_RANGE 31:0
`define INT_RANGE_MAX 31
`define VECTOR_RANGE 63:0
reg [`INT_RANGE] stashb, stasha, stashn, stashm;
function [`VECTOR_RANGE] copy_range;
input [`VECTOR_RANGE] y;
input [`INT_RANGE] b;
input [`INT_RANGE] a;
input [`VECTOR_RANGE] x;
input [`INT_RANGE] n;
input [`INT_RANGE] m;
begin
copy_range = y;
stashb = b;
stasha = a;
stashn = n;
stashm = m;
end
endfunction
parameter DATA_SIZE = 16;
parameter NUM_OF_REGS = 32;
reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf;
reg [DATA_SIZE-1:0] memread_rf_reg;
always @(memread_rf) begin : memread_convert
memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf,
DATA_SIZE-'d1, DATA_SIZE-'d1);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
memread_rf = 512'haa;
end
if (cyc==3) begin
if (stashb != 'd15) $stop;
if (stasha != 'd15) $stop;
if (stashn != 'd15) $stop;
if (stashm != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:40 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_1/zynq_design_1_axi_gpio_0_1_sim_netlist.v
// Design : zynq_design_1_axi_gpio_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zynq_design_1_axi_gpio_0_1,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zynq_design_1_axi_gpio_0_1
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_o);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [7:0]gpio_io_o;
wire [7:0]gpio_io_o;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [7:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "1" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
zynq_design_1_axi_gpio_0_1_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio_io_o(gpio_io_o),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[7:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "GPIO_Core" *)
module zynq_design_1_axi_gpio_0_1_GPIO_Core
(D,
gpio_io_o,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_t,
bus2ip_rnw_i_reg,
s_axi_aclk,
SS,
bus2ip_rnw,
bus2ip_cs,
E,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
rst_reg);
output [7:0]D;
output [7:0]gpio_io_o;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [7:0]gpio_io_t;
input bus2ip_rnw_i_reg;
input s_axi_aclk;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [0:0]E;
input [7:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
input [0:0]rst_reg;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [7:0]\MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire bus2ip_rnw_i_reg;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire [0:0]rst_reg;
wire s_axi_aclk;
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[7]),
.Q(D[7]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[6]),
.Q(D[6]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[5]),
.Q(D[5]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[4]),
.Q(D[4]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[3]),
.Q(D[3]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[2]),
.Q(D[2]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[1]),
.Q(D[1]),
.R(bus2ip_rnw_i_reg));
FDRE \Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_o[0]),
.Q(D[0]),
.R(bus2ip_rnw_i_reg));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]),
.Q(gpio_io_o[7]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]),
.Q(gpio_io_o[6]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]),
.Q(gpio_io_o[5]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [7]),
.Q(gpio_io_t[7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [6]),
.Q(gpio_io_t[6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [5]),
.Q(gpio_io_t[5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [4]),
.Q(gpio_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[5]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[6]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[7]
(.C(s_axi_aclk),
.CE(rst_reg),
.D(\MEM_DECODE_GEN[0].cs_out_i_reg[0] [0]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
iGPIO_xferAck_i_1
(.I0(bus2ip_cs),
.I1(gpio_xferAck_Reg),
.I2(GPIO_xferAck_i),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module zynq_design_1_axi_gpio_0_1_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_aclk,
rst_reg,
Q,
bus2ip_rnw_i_reg,
ip2bus_rdack_i_D1,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
ip2bus_wrack_i_D1,
is_write_reg,
s_axi_wdata,
start2_reg,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_arready;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
input s_axi_aclk;
input rst_reg;
input [2:0]Q;
input bus2ip_rnw_i_reg;
input ip2bus_rdack_i_D1;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input ip2bus_wrack_i_D1;
input is_write_reg;
input [15:0]s_axi_wdata;
input start2_reg;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [2:0]Q;
wire bus2ip_rnw_i_reg;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire start2_reg;
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(start2_reg),
.I2(s_axi_aresetn),
.I3(s_axi_arready),
.I4(s_axi_wready),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
LUT4 #(
.INIT(16'hFFF7))
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(gpio_xferAck_Reg),
.I3(GPIO_xferAck_i),
.O(\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAABAAAA))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(rst_reg),
.I1(Q[1]),
.I2(bus2ip_rnw_i_reg),
.I3(Q[0]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(Q[2]),
.O(E));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[7]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[15]),
.O(D[7]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[6]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[14]),
.O(D[6]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[5]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[13]),
.O(D[5]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[4]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[12]),
.O(D[4]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[3]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[11]),
.O(D[3]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[5]_i_1
(.I0(s_axi_wdata[2]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[10]),
.O(D[2]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[6]_i_1
(.I0(s_axi_wdata[1]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[9]),
.O(D[1]));
LUT4 #(
.INIT(16'hFB08))
\Not_Dual.gpio_Data_Out[7]_i_1
(.I0(s_axi_wdata[0]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(Q[1]),
.I3(s_axi_wdata[8]),
.O(D[0]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
\Not_Dual.gpio_OE[0]_i_1
(.I0(rst_reg),
.I1(Q[0]),
.I2(Q[1]),
.I3(bus2ip_rnw_i_reg),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(Q[2]),
.O(\Not_Dual.gpio_OE_reg[0] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(is_read),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(is_write_reg),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "1" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module zynq_design_1_axi_gpio_0_1_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_6;
wire AXI_LITE_IPIF_I_n_7;
wire [0:7]DBus_Reg;
wire GPIO_xferAck_i;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_core_1_n_19;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [24:31]ip2bus_data;
wire [24:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [7:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
zynq_design_1_axi_gpio_0_1_axi_lite_ipif AXI_LITE_IPIF_I
(.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_17),
.\Not_Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_7),
.Q({ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[31:24],s_axi_wdata[7:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
zynq_design_1_axi_gpio_0_1_GPIO_Core gpio_core_1
(.D({ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.E(AXI_LITE_IPIF_I_n_6),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] ({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7]}),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_17),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_19),
.rst_reg(AXI_LITE_IPIF_I_n_7),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_19),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module zynq_design_1_axi_gpio_0_1_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
bus2ip_cs,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
Q);
output bus2ip_reset;
output bus2ip_rnw;
output bus2ip_cs;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
output [7:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [15:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]Q;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [7:0]Q;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [7:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
zynq_design_1_axi_gpio_0_1_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ),
.\Not_Dual.gpio_Data_Out_reg[0] (bus2ip_rnw),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q(Q),
.SR(bus2ip_reset),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module zynq_design_1_axi_gpio_0_1_slave_attachment
(SR,
\Not_Dual.gpio_Data_Out_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
E,
\Not_Dual.gpio_OE_reg[0] ,
s_axi_wready,
D,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_aresetn,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
gpio_xferAck_Reg,
GPIO_xferAck_i,
Q);
output SR;
output \Not_Dual.gpio_Data_Out_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output [0:0]E;
output [0:0]\Not_Dual.gpio_OE_reg[0] ;
output s_axi_wready;
output [7:0]D;
output \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
output [7:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_aresetn;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [15:0]s_axi_wdata;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]Q;
wire [7:0]D;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Not_Dual.gpio_OE_reg[0] ;
wire [7:0]Q;
wire SR;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire bus2ip_rnw_i06_out;
wire clear;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [1:0]p_0_out;
wire p_1_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [7:0]s_axi_rdata;
wire \s_axi_rdata_i[7]_i_1_n_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [15:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
zynq_design_1_axi_gpio_0_1_address_decoder I_DECODER
(.D(D),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] (\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24] ),
.\Not_Dual.gpio_OE_reg[0] (\Not_Dual.gpio_OE_reg[0] ),
.Q({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Not_Dual.gpio_Data_Out_reg[0] ),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.rst_reg(SR),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2_reg(start2));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hCCCACCCC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(state[0]),
.I3(state[1]),
.I4(s_axi_arvalid),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[0]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h10))
bus2ip_rnw_i_i_1
(.I0(state[0]),
.I1(state[1]),
.I2(s_axi_arvalid),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(\Not_Dual.gpio_Data_Out_reg[0] ),
.R(SR));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(SR));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_1_in));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(SR));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[7]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\s_axi_rdata_i[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[4]),
.Q(s_axi_rdata[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[5]),
.Q(s_axi_rdata[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[6]),
.Q(s_axi_rdata[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[7]_i_1_n_0 ),
.D(Q[7]),
.Q(s_axi_rdata[7]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(state[0]),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(s_axi_wready),
.O(p_0_out[0]));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(\state[1]_i_3_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arready),
.O(p_0_out[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[0]),
.Q(state[0]),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[1]),
.Q(state[1]),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////////////
// File name : s29al032d_00.v
//////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2005 Spansion, LLC.
//
// MODIFICATION HISTORY :
//
//
// version: | author: | mod date: | changes made:
// V1.0 D.Lukovic 05 May 17 Initial release
//
//////////////////////////////////////////////////////////////////////////////
//
// PART DESCRIPTION:
//
// Library: FLASH
// Technology: Flash memory
// Part: s29al032d_00
//
// Description: 32Mbit (4M x 8-Bit) Flash Memory
//
//
//
///////////////////////////////////////////////////////////////////////////////
// Known Bugs:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ns
module s29al032d_00
(
A21 ,
A20 ,
A19 ,
A18 ,
A17 ,
A16 ,
A15 ,
A14 ,
A13 ,
A12 ,
A11 ,
A10 ,
A9 ,
A8 ,
A7 ,
A6 ,
A5 ,
A4 ,
A3 ,
A2 ,
A1 ,
A0 ,
DQ7 ,
DQ6 ,
DQ5 ,
DQ4 ,
DQ3 ,
DQ2 ,
DQ1 ,
DQ0 ,
CENeg ,
OENeg ,
WENeg ,
RESETNeg ,
ACC ,
RY
);
////////////////////////////////////////////////////////////////////////
// Port / Part Pin Declarations
////////////////////////////////////////////////////////////////////////
input A21 ;
input A20 ;
input A19 ;
input A18 ;
input A17 ;
input A16 ;
input A15 ;
input A14 ;
input A13 ;
input A12 ;
input A11 ;
input A10 ;
input A9 ;
input A8 ;
input A7 ;
input A6 ;
input A5 ;
input A4 ;
input A3 ;
input A2 ;
input A1 ;
input A0 ;
inout DQ7 ;
inout DQ6 ;
inout DQ5 ;
inout DQ4 ;
inout DQ3 ;
inout DQ2 ;
inout DQ1 ;
inout DQ0 ;
input CENeg ;
input OENeg ;
input WENeg ;
input RESETNeg ;
input ACC ;
output RY ;
// interconnect path delay signals
wire A21_ipd ;
wire A20_ipd ;
wire A19_ipd ;
wire A18_ipd ;
wire A17_ipd ;
wire A16_ipd ;
wire A15_ipd ;
wire A14_ipd ;
wire A13_ipd ;
wire A12_ipd ;
wire A11_ipd ;
wire A10_ipd ;
wire A9_ipd ;
wire A8_ipd ;
wire A7_ipd ;
wire A6_ipd ;
wire A5_ipd ;
wire A4_ipd ;
wire A3_ipd ;
wire A2_ipd ;
wire A1_ipd ;
wire A0_ipd ;
wire [21 : 0] A;
assign A = {
A21_ipd,
A20_ipd,
A19_ipd,
A18_ipd,
A17_ipd,
A16_ipd,
A15_ipd,
A14_ipd,
A13_ipd,
A12_ipd,
A11_ipd,
A10_ipd,
A9_ipd,
A8_ipd,
A7_ipd,
A6_ipd,
A5_ipd,
A4_ipd,
A3_ipd,
A2_ipd,
A1_ipd,
A0_ipd };
wire DQ7_ipd ;
wire DQ6_ipd ;
wire DQ5_ipd ;
wire DQ4_ipd ;
wire DQ3_ipd ;
wire DQ2_ipd ;
wire DQ1_ipd ;
wire DQ0_ipd ;
wire [7 : 0 ] DIn;
assign DIn = {DQ7_ipd,
DQ6_ipd,
DQ5_ipd,
DQ4_ipd,
DQ3_ipd,
DQ2_ipd,
DQ1_ipd,
DQ0_ipd };
wire [7 : 0 ] DOut;
assign DOut = {DQ7,
DQ6,
DQ5,
DQ4,
DQ3,
DQ2,
DQ1,
DQ0 };
wire CENeg_ipd ;
wire OENeg_ipd ;
wire WENeg_ipd ;
wire RESETNeg_ipd ;
wire ACC_ipd ;
wire VIO_ipd ;
// internal delays
reg HANG_out ; // Program/Erase Timing Limit
reg HANG_in ;
reg START_T1 ; // Start TimeOut
reg START_T1_in ;
reg CTMOUT ; // Sector Erase TimeOut
reg CTMOUT_in ;
reg READY_in ;
reg READY ; // Device ready after reset
reg [7 : 0] DOut_zd;
wire DQ7_Pass ;
wire DQ6_Pass ;
wire DQ5_Pass ;
wire DQ4_Pass ;
wire DQ3_Pass ;
wire DQ2_Pass ;
wire DQ1_Pass ;
wire DQ0_Pass ;
reg [7 : 0] DOut_Pass;
assign {DQ7_Pass,
DQ6_Pass,
DQ5_Pass,
DQ4_Pass,
DQ3_Pass,
DQ2_Pass,
DQ1_Pass,
DQ0_Pass } = DOut_Pass;
reg RY_zd;
parameter UserPreload = 1'b0;
parameter mem_file_name = "none";
parameter prot_file_name = "none";
parameter secsi_file_name = "none";
parameter TimingModel = "DefaultTimingModel";
parameter DelayValues = "FROM_PLI";
parameter PartID = "s29al032d";
parameter MaxData = 255;
parameter SecSize = 65535;
parameter SecNum = 63;
parameter HiAddrBit = 21;
parameter SecSiSize = 255;
// powerup
reg PoweredUp;
//FSM control signals
reg ULBYPASS ; ////Unlock Bypass Active
reg ESP_ACT ; ////Erase Suspend
reg OTP_ACT ; ////SecSi Access
reg PDONE ; ////Prog. Done
reg PSTART ; ////Start Programming
//Program location is in protected sector
reg PERR ;
reg EDONE ; ////Ers. Done
reg ESTART ; ////Start Erase
reg ESUSP ; ////Suspend Erase
reg ERES ; ////Resume Erase
//All sectors selected for erasure are protected
reg EERR ;
//Sectors selected for erasure
reg [SecNum:0] Ers_queue; // = SecNum'b0;
//Command Register
reg write ;
reg read ;
//Sector Address
integer SecAddr = 0;
integer SA = 0;
//Address within sector
integer Address = 0;
integer MemAddress = 0;
integer SecSiAddr = 0;
integer AS_ID = 0;
integer AS_SecSi_FP = 0;
integer AS_ID2 = 0;
//A19:A11 Don't Care
integer Addr ;
//glitch protection
wire gWE_n ;
wire gCE_n ;
wire gOE_n ;
reg RST ;
reg reseted ;
integer Mem[0:(SecNum+1)*(SecSize+1)-1];
//Sector Protection Status
reg [SecNum:0] Sec_Prot;
// timing check violation
reg Viol = 1'b0;
// CFI query address
integer SecSi[0:SecSiSize];
integer CFI_array[16:79];
reg FactoryProt = 0;
integer WBData;
integer WBAddr;
reg oe = 1'b0;
event oe_event;
event initOK;
event MergeE;
//Status reg.
reg[15:0] Status = 8'b0;
reg[7:0] old_bit, new_bit;
integer old_int, new_int;
integer wr_cnt;
reg[7:0] temp;
integer S_ind = 0;
integer ind = 0;
integer i,j,k;
integer Debug;
//TPD_XX_DATA
time OEDQ_t;
time CEDQ_t;
time ADDRDQ_t;
time OENeg_event;
time CENeg_event;
time OENeg_posEvent;
time CENeg_posEvent;
time ADDR_event;
reg FROMOE;
reg FROMCE;
reg FROMADDR;
integer OEDQ_01;
integer CEDQ_01;
integer ADDRDQ_01;
reg[7:0] TempData;
///////////////////////////////////////////////////////////////////////////////
//Interconnect Path Delay Section
///////////////////////////////////////////////////////////////////////////////
buf (A21_ipd, A21);
buf (A20_ipd, A20);
buf (A19_ipd, A19);
buf (A18_ipd, A18);
buf (A17_ipd, A17);
buf (A16_ipd, A16);
buf (A15_ipd, A15);
buf (A14_ipd, A14);
buf (A13_ipd, A13);
buf (A12_ipd, A12);
buf (A11_ipd, A11);
buf (A10_ipd, A10);
buf (A9_ipd , A9 );
buf (A8_ipd , A8 );
buf (A7_ipd , A7 );
buf (A6_ipd , A6 );
buf (A5_ipd , A5 );
buf (A4_ipd , A4 );
buf (A3_ipd , A3 );
buf (A2_ipd , A2 );
buf (A1_ipd , A1 );
buf (A0_ipd , A0 );
buf (DQ7_ipd , DQ7 );
buf (DQ6_ipd , DQ6 );
buf (DQ5_ipd , DQ5 );
buf (DQ4_ipd , DQ4 );
buf (DQ3_ipd , DQ3 );
buf (DQ2_ipd , DQ2 );
buf (DQ1_ipd , DQ1 );
buf (DQ0_ipd , DQ0 );
buf (CENeg_ipd , CENeg );
buf (OENeg_ipd , OENeg );
buf (WENeg_ipd , WENeg );
buf (RESETNeg_ipd , RESETNeg );
buf (ACC_ipd , ACC );
///////////////////////////////////////////////////////////////////////////////
// Propagation delay Section
///////////////////////////////////////////////////////////////////////////////
nmos (DQ7 , DQ7_Pass , 1);
nmos (DQ6 , DQ6_Pass , 1);
nmos (DQ5 , DQ5_Pass , 1);
nmos (DQ4 , DQ4_Pass , 1);
nmos (DQ3 , DQ3_Pass , 1);
nmos (DQ2 , DQ2_Pass , 1);
nmos (DQ1 , DQ1_Pass , 1);
nmos (DQ0 , DQ0_Pass , 1);
nmos (RY , 1'b0 , ~RY_zd);
wire deg;
//VHDL VITAL CheckEnable equivalents
// Address setup/hold near WE# falling edge
wire CheckEnable_A0_WE;
assign CheckEnable_A0_WE = ~CENeg && OENeg;
// Data setup/hold near WE# rising edge
wire CheckEnable_DQ0_WE;
assign CheckEnable_DQ0_WE = ~CENeg && OENeg && deg;
// Address setup/hold near CE# falling edge
wire CheckEnable_A0_CE;
assign CheckEnable_A0_CE = ~WENeg && OENeg;
// Data setup/hold near CE# rising edge
wire CheckEnable_DQ0_CE;
assign CheckEnable_DQ0_CE = ~WENeg && OENeg && deg;
specify
// tipd delays: interconnect path delays , mapped to input port delays.
// In Verilog is not necessary to declare any tipd_ delay variables,
// they can be taken from SDF file
// With all the other delays real delays would be taken from SDF file
// tpd delays
specparam tpd_RESETNeg_DQ0 =1;
specparam tpd_A0_DQ0 =1;//tacc ok
specparam tpd_CENeg_DQ0 =1;//ok
//(tCE,tCE,tDF,-,tDF,-)
specparam tpd_OENeg_DQ0 =1;//ok
//(tOE,tOE,tDF,-,tDF,-)
specparam tpd_WENeg_RY =1; //tBUSY
specparam tpd_CENeg_RY =1; //tBUSY
// tsetup values: setup time
specparam tsetup_A0_WENeg =1; //tAS edge \
specparam tsetup_DQ0_WENeg =1; //tDS edge /
// thold values: hold times
specparam thold_A0_WENeg =1; //tAH edge \
specparam thold_DQ0_CENeg =1; //tDH edge /
specparam thold_OENeg_WENeg =1; //tOEH edge /
specparam thold_CENeg_RESETNeg =1; //tRH edge /
specparam thold_WENeg_OENeg =1; //tGHVL edge /
// tpw values: pulse width
specparam tpw_RESETNeg_negedge =1; //tRP
specparam tpw_WENeg_negedge =1; //tWP
specparam tpw_WENeg_posedge =1; //tWPH
specparam tpw_CENeg_negedge =1; //tCP
specparam tpw_CENeg_posedge =1; //tCEPH
specparam tpw_A0_negedge =1; //tWC tRC ok
specparam tpw_A0_posedge =1; //tWC tRC ok
// tdevice values: values for internal delays
//Program Operation
specparam tdevice_POB = 9000; //9 us;
//Sector Erase Operation
specparam tdevice_SEO = 700000000; //700 ms;
//Timing Limit Exceeded
specparam tdevice_HANG = 400000000; //400 ms;
//Erase suspend time
specparam tdevice_START_T1 = 20000; //20 us;
//sector erase command sequence timeout
specparam tdevice_CTMOUT = 50000; //50 us;
//device ready after Hardware reset(during embeded algorithm)
specparam tdevice_READY = 20000; //20 us; //tReady
// If tpd values are fetched from specify block, these parameters
// must change along with SDF values, SDF values change will NOT
// imlicitly apply here !
// If you want tpd values to be fetched by the model itself, please
// use the PLI routine approach but be shure to set parameter
// DelayValues to "FROM_PLI" as default
///////////////////////////////////////////////////////////////////////////////
// Input Port Delays don't require Verilog description
///////////////////////////////////////////////////////////////////////////////
// Path delays //
///////////////////////////////////////////////////////////////////////////////
//for DQ signals
if (FROMCE)
( CENeg => DQ0 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ1 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ2 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ3 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ4 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ5 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ6 ) = tpd_CENeg_DQ0;
if (FROMCE)
( CENeg => DQ7 ) = tpd_CENeg_DQ0;
if (FROMOE)
( OENeg => DQ0 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ1 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ2 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ3 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ4 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ5 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ6 ) = tpd_OENeg_DQ0;
if (FROMOE)
( OENeg => DQ7 ) = tpd_OENeg_DQ0;
if (FROMADDR)
( A0 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A0 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A1 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A2 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A3 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A4 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A5 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A6 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A7 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A8 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A9 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A10 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A11 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A12 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A13 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A14 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A15 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A16 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A17 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A18 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A19 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A20 => DQ7 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ0 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ1 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ2 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ3 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ4 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ5 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ6 ) = tpd_A0_DQ0;
if (FROMADDR)
( A21 => DQ7 ) = tpd_A0_DQ0;
if (~RESETNeg)
( RESETNeg => DQ0 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ1 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ2 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ3 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ4 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ5 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ6 ) = tpd_RESETNeg_DQ0;
if (~RESETNeg)
( RESETNeg => DQ7 ) = tpd_RESETNeg_DQ0;
//for RY signal
(WENeg => RY) = tpd_WENeg_RY;
(CENeg => RY) = tpd_CENeg_RY;
////////////////////////////////////////////////////////////////////////////////
// Timing Violation //
////////////////////////////////////////////////////////////////////////////////
$setup ( A0 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A1 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A2 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A3 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A4 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A5 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A6 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A7 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A8 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A9 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A10, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A11, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A12, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A13, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A14, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A15, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A16, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A17, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A18, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A19, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A20, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A21, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol);
$setup ( A0 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A1 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A2 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A3 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A4 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A5 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A6 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A7 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A8 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A9 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A10, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A11, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A12, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A13, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A14, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A15, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A16, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A17, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A18, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A19, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A20, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( A21, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol);
$setup ( DQ0, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ1, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ2, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ3, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ4, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ5, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ6, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ7, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ0, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ1, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ2, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ3, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ4, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ5, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ6, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$setup ( DQ7, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol);
$hold ( posedge RESETNeg&&&(CENeg===1), CENeg, thold_CENeg_RESETNeg, Viol);
$hold ( posedge RESETNeg&&&(OENeg===1), OENeg, thold_CENeg_RESETNeg, Viol);
$hold ( posedge RESETNeg&&&(WENeg===1), WENeg, thold_CENeg_RESETNeg, Viol);
$hold ( posedge OENeg, WENeg, thold_WENeg_OENeg, Viol);
$hold ( posedge WENeg, OENeg, thold_OENeg_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A0 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A1 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A2 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A3 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A4 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A5 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A6 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A7 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A9 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A10 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A11 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A12 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A13 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A14 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A15 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A16 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A17 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A18 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A19 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A20 , thold_A0_WENeg, Viol);
$hold ( negedge CENeg &&& CheckEnable_A0_CE, A21 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A0 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A1 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A2 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A3 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A4 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A5 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A6 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A7 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A8 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A9 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A10 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A11 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A12 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A13 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A14 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A15 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A16 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A17 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A18 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A19 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A20 , thold_A0_WENeg, Viol);
$hold ( negedge WENeg &&& CheckEnable_A0_WE, A21 , thold_A0_WENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ0, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ1, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ2, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ3, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ4, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ5, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ6, thold_DQ0_CENeg, Viol);
$hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ7, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ0, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ1, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ2, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ3, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ4, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ5, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ6, thold_DQ0_CENeg, Viol);
$hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ7, thold_DQ0_CENeg, Viol);
$width (negedge RESETNeg, tpw_RESETNeg_negedge);
$width (posedge WENeg, tpw_WENeg_posedge);
$width (negedge WENeg, tpw_WENeg_negedge);
$width (posedge CENeg, tpw_CENeg_posedge);
$width (negedge CENeg, tpw_CENeg_negedge);
$width (negedge A0, tpw_A0_negedge);//ok
$width (negedge A1, tpw_A0_negedge);//ok
$width (negedge A2, tpw_A0_negedge);//ok
$width (negedge A3, tpw_A0_negedge);//ok
$width (negedge A4, tpw_A0_negedge);//ok
$width (negedge A5, tpw_A0_negedge);//ok
$width (negedge A6, tpw_A0_negedge);//ok
$width (negedge A7, tpw_A0_negedge);//ok
$width (negedge A8, tpw_A0_negedge);//ok
$width (negedge A9, tpw_A0_negedge);//ok
$width (negedge A10, tpw_A0_negedge);//ok
$width (negedge A11, tpw_A0_negedge);//ok
$width (negedge A12, tpw_A0_negedge);//ok
$width (negedge A13, tpw_A0_negedge);//ok
$width (negedge A14, tpw_A0_negedge);//ok
$width (negedge A15, tpw_A0_negedge);//ok
$width (negedge A16, tpw_A0_negedge);//ok
$width (negedge A17, tpw_A0_negedge);//ok
$width (negedge A18, tpw_A0_negedge);//ok
$width (negedge A19, tpw_A0_negedge);//ok
$width (negedge A20, tpw_A0_negedge);//ok
$width (negedge A21, tpw_A0_negedge);//ok
$width (posedge A0, tpw_A0_posedge);//ok
$width (posedge A1, tpw_A0_posedge);//ok
$width (posedge A2, tpw_A0_posedge);//ok
$width (posedge A3, tpw_A0_posedge);//ok
$width (posedge A4, tpw_A0_posedge);//ok
$width (posedge A5, tpw_A0_posedge);//ok
$width (posedge A6, tpw_A0_posedge);//ok
$width (posedge A7, tpw_A0_posedge);//ok
$width (posedge A8, tpw_A0_posedge);//ok
$width (posedge A9, tpw_A0_posedge);//ok
$width (posedge A10, tpw_A0_posedge);//ok
$width (posedge A11, tpw_A0_posedge);//ok
$width (posedge A12, tpw_A0_posedge);//ok
$width (posedge A13, tpw_A0_posedge);//ok
$width (posedge A14, tpw_A0_posedge);//ok
$width (posedge A15, tpw_A0_posedge);//ok
$width (posedge A16, tpw_A0_posedge);//ok
$width (posedge A17, tpw_A0_posedge);//ok
$width (posedge A18, tpw_A0_posedge);//ok
$width (posedge A19, tpw_A0_posedge);//ok
$width (posedge A20, tpw_A0_posedge);//ok
$width (posedge A21, tpw_A0_posedge);//ok
endspecify
////////////////////////////////////////////////////////////////////////////////
// Main Behavior Block //
////////////////////////////////////////////////////////////////////////////////
// FSM states
parameter RESET =6'd0;
parameter Z001 =6'd1;
parameter PREL_SETBWB =6'd2;
parameter PREL_ULBYPASS =6'd3;
parameter PREL_ULBYPASS_RESET =6'd4;
parameter AS =6'd5;
parameter A0SEEN =6'd6;
parameter OTP =6'd7;
parameter OTP_Z001 =6'd8;
parameter OTP_PREL =6'd9;
parameter OTP_AS =6'd10;
parameter OTP_AS_CFI =6'd11;
parameter OTP_A0SEEN =6'd12;
parameter C8 =6'd13;
parameter C8_Z001 =6'd14;
parameter C8_PREL =6'd15;
parameter ERS =6'd16;
parameter SERS =6'd17;
parameter ESPS =6'd18;
parameter SERS_EXEC =6'd19;
parameter ESP =6'd20;
parameter ESP_Z001 =6'd21;
parameter ESP_PREL =6'd22;
parameter ESP_A0SEEN =6'd23;
parameter ESP_AS =6'd24;
parameter PGMS =6'd25;
parameter CFI =6'd26;
parameter AS_CFI =6'd27;
parameter ESP_CFI =6'd28;
parameter ESP_AS_CFI =6'd29;
reg [5:0] current_state;
reg [5:0] next_state;
reg deq;
always @(DIn, DOut)
begin
if (DIn==DOut)
deq=1'b1;
else
deq=1'b0;
end
// check when data is generated from model to avoid setuphold check in
// those occasion
assign deg =deq;
// initialize memory and load preoload files if any
initial
begin : NBlck
integer i,j;
integer tmp1,tmp2,tmp3;
integer secure_silicon[0:SecSiSize];
reg sector_prot[0:SecNum];
for (i=0;i<=((SecNum+1)*(SecSize+1)-1);i=i+1)
begin
Mem[i]=MaxData;
end
for (i=0;i<=SecSiSize;i=i+1)
begin
secure_silicon[i]=MaxData;
end
for (i=0;i<=SecNum;i=i+1)
begin
sector_prot[i]=0;
end
if (UserPreload && !(prot_file_name == "none"))
begin
//s29al032d_00_prot sector protect file
// // - comment
// @aa - <aa> stands for sector address
// (aa is incremented at every load)
// b - <b> is 1 for protected sector <aa>, 0 for unprotect.
$readmemb(prot_file_name,sector_prot);
end
if (UserPreload && !(mem_file_name == "none"))
begin
//s29al032d_00_memory preload file
// @aaaaaa - <aaaaaa> stands for address within last defined sector
// dd - <dd> is byte to be written at Mem(nn)(aaaaaa++)
// (aaaaaa is incremented at every load)
$readmemh(mem_file_name,Mem);
end
if (UserPreload && !(secsi_file_name == "none"))
begin
//s29al032d_00_secsi memory preload file
// @aaaa - <aaaa> stands for address within last defined sector
// dd - <dd> is byte to be written at Mem(nn)(aaaa++)
// (aaaa is incremented at every load)
$readmemh(secsi_file_name,secure_silicon);
end
for (i=0;i<=SecSiSize;i=i+1)
begin
SecSi[i] = secure_silicon[i];
end
for (i=0;i<=SecNum;i=i+1)
Ers_queue[i] = 0;
// every 4-group sectors protect bit must equel
for (i=0;i<=SecNum;i=i+1)
Sec_Prot[i] = sector_prot[i];
if ((Sec_Prot[3:0] != 4'h0 && Sec_Prot[3:0] != 4'hF)
|| (Sec_Prot[7:4] != 4'h0 && Sec_Prot[7:4] != 4'hF)
|| (Sec_Prot[11:8] != 4'h0 && Sec_Prot[11:8] != 4'hF)
|| (Sec_Prot[15:12] != 4'h0 && Sec_Prot[15:12] != 4'hF)
|| (Sec_Prot[19:16] != 4'h0 && Sec_Prot[19:16] != 4'hF)
|| (Sec_Prot[23:20] != 4'h0 && Sec_Prot[23:20] != 4'hF)
|| (Sec_Prot[27:24] != 4'h0 && Sec_Prot[27:24] != 4'hF)
|| (Sec_Prot[31:28] != 4'h0 && Sec_Prot[31:28] != 4'hF)
|| (Sec_Prot[35:32] != 4'h0 && Sec_Prot[35:32] != 4'hF)
|| (Sec_Prot[39:36] != 4'h0 && Sec_Prot[39:36] != 4'hF)
|| (Sec_Prot[43:40] != 4'h0 && Sec_Prot[43:40] != 4'hF)
|| (Sec_Prot[47:44] != 4'h0 && Sec_Prot[47:44] != 4'hF)
|| (Sec_Prot[51:48] != 4'h0 && Sec_Prot[51:48] != 4'hF)
|| (Sec_Prot[55:52] != 4'h0 && Sec_Prot[55:52] != 4'hF)
|| (Sec_Prot[59:56] != 4'h0 && Sec_Prot[59:56] != 4'hF)
|| (Sec_Prot[63:60] != 4'h0 && Sec_Prot[63:60] != 4'hF))
$display("Bad sector protect group preload");
WBData = -1;
end
//Power Up time 100 ns;
initial
begin
PoweredUp = 1'b0;
#100 PoweredUp = 1'b1;
end
always @(RESETNeg)
begin
RST <= #499 RESETNeg;
end
initial
begin
write = 1'b0;
read = 1'b0;
Addr = 0;
ULBYPASS = 1'b0;
ESP_ACT = 1'b0;
OTP_ACT = 1'b0;
PDONE = 1'b1;
PSTART = 1'b0;
PERR = 1'b0;
EDONE = 1'b1;
ESTART = 1'b0;
ESUSP = 1'b0;
ERES = 1'b0;
EERR = 1'b0;
READY_in = 1'b0;
READY = 1'b0;
end
always @(posedge START_T1_in)
begin:TESTARTT1r
#tdevice_START_T1 START_T1 = START_T1_in;
end
always @(negedge START_T1_in)
begin:TESTARTT1f
#1 START_T1 = START_T1_in;
end
always @(posedge CTMOUT_in)
begin:TCTMOUTr
#tdevice_CTMOUT CTMOUT = CTMOUT_in;
end
always @(negedge CTMOUT_in)
begin:TCTMOUTf
#1 CTMOUT = CTMOUT_in;
end
always @(posedge READY_in)
begin:TREADYr
#tdevice_READY READY = READY_in;
end
always @(negedge READY_in)
begin:TREADYf
#1 READY = READY_in;
end
////////////////////////////////////////////////////////////////////////////
//// obtain 'LAST_EVENT information
////////////////////////////////////////////////////////////////////////////
always @(negedge OENeg)
begin
OENeg_event = $time;
end
always @(negedge CENeg)
begin
CENeg_event = $time;
end
always @(posedge OENeg)
begin
OENeg_posEvent = $time;
end
always @(posedge CENeg)
begin
CENeg_posEvent = $time;
end
always @(A)
begin
ADDR_event = $time;
end
////////////////////////////////////////////////////////////////////////////
//// sequential process for reset control and FSM state transition
////////////////////////////////////////////////////////////////////////////
always @(negedge RST)
begin
ESP_ACT = 1'b0;
ULBYPASS = 1'b0;
OTP_ACT = 1'b0;
end
reg R;
reg E;
always @(RESETNeg)
begin
if (PoweredUp)
begin
//Hardware reset timing control
if (~RESETNeg)
begin
E = 1'b0;
if (~PDONE || ~EDONE)
begin
//if program or erase in progress
READY_in = 1'b1;
R = 1'b1;
end
else
begin
READY_in = 1'b0;
R = 1'b0; //prog or erase not in progress
end
end
else if (RESETNeg && RST)
begin
//RESET# pulse < tRP
READY_in = 1'b0;
R = 1'b0;
E = 1'b1;
end
end
end
always @(next_state or RESETNeg or CENeg or RST or
READY or PoweredUp)
begin: StateTransition
if (PoweredUp)
begin
if (RESETNeg && (~R || (R && READY)))
begin
current_state = next_state;
READY_in = 1'b0;
E = 1'b0;
R = 1'b0;
reseted = 1'b1;
end
else if ((~R && ~RESETNeg && ~RST) ||
(R && ~RESETNeg && ~RST && ~READY) ||
(R && RESETNeg && ~RST && ~READY))
begin
//no state transition while RESET# low
current_state = RESET; //reset start
reseted = 1'b0;
end
end
else
begin
current_state = RESET; // reset
reseted = 1'b0;
E = 1'b0;
R = 1'b0;
end
end
// /////////////////////////////////////////////////////////////////////////
// //Glitch Protection: Inertial Delay does not propagate pulses <5ns
// /////////////////////////////////////////////////////////////////////////
assign #5 gWE_n = WENeg_ipd;
assign #5 gCE_n = CENeg_ipd;
assign #5 gOE_n = OENeg_ipd;
///////////////////////////////////////////////////////////////////////////
//Process that reports warning when changes on signals WE#, CE#, OE# are
//discarded
///////////////////////////////////////////////////////////////////////////
always @(WENeg)
begin: PulseWatch1
if (gWE_n == WENeg)
$display("Glitch on WE#");
end
always @(CENeg)
begin: PulseWatch2
if (gCE_n == CENeg)
$display("Glitch on CE#");
end
always @(OENeg)
begin: PulseWatch3
if (gOE_n == OENeg)
$display("Glitch on OE#");
end
//latch address on rising edge and data on falling edge of write
always @(gWE_n or gCE_n or gOE_n )
begin: write_dc
if (RESETNeg!=1'b0)
begin
if (~gWE_n && ~gCE_n && gOE_n)
write = 1'b1;
else
write = 1'b0;
end
if (gWE_n && ~gCE_n && ~gOE_n)
read = 1'b1;
else
read = 1'b0;
end
///////////////////////////////////////////////////////////////////////////
////Latch address on falling edge of WE# or CE# what ever comes later
////Latch data on rising edge of WE# or CE# what ever comes first
//// also Write cycle decode
////////////////////////////////////////////////////////////////////////////
integer A_tmp ;
integer SA_tmp ;
integer A_tmp1 ;
integer Mem_tmp;
integer AS_addr;
reg CE;
always @(WENeg_ipd)
begin
if (reseted)
begin
if (~WENeg_ipd && ~CENeg_ipd && OENeg_ipd )
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
AS_addr = A[21];
end
end
end
always @(CENeg_ipd)
begin
if (reseted)
begin
if (~CENeg_ipd && (WENeg_ipd != OENeg_ipd) )
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
AS_addr = A[21];
end
if (~CENeg_ipd && WENeg_ipd && ~OENeg_ipd)
begin
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
end
end
end
always @(negedge OENeg_ipd )
begin
if (reseted)
begin
if (~OENeg_ipd && WENeg_ipd && ~CENeg_ipd)
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
AS_addr = A[21];
end
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
CE = CENeg;
Addr = A_tmp;
end
end
always @(A)
begin
if (reseted)
if (WENeg_ipd && ~CENeg_ipd && ~OENeg_ipd)
begin
A_tmp = A[10:0];
SA_tmp = A[HiAddrBit:16];
A_tmp1 = A[15:0];
Mem_tmp = A;
AS_addr = A[21];
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
CE = CENeg;
end
end
always @(posedge write)
begin
SecAddr = SA_tmp;
Address = A_tmp1;
MemAddress = Mem_tmp;
Addr = A_tmp;
CE = CENeg;
end
///////////////////////////////////////////////////////////////////////////
// Timing control for the Program Operations
///////////////////////////////////////////////////////////////////////////
integer cnt_write = 0;
//time elapsed_write ;
time duration_write ;
//time start_write ;
event pdone_event;
always @(posedge reseted)
begin
PDONE = 1'b1;
end
always @(reseted or PSTART)
begin
if (reseted)
begin
if (PSTART && PDONE)
begin
if ((~FactoryProt && OTP_ACT)||
( ~Sec_Prot[SA] &&(~Ers_queue[SA] || ~ESP_ACT )&& ~OTP_ACT))
begin
duration_write = tdevice_POB + 5;
PDONE = 1'b0;
->pdone_event;
end
else
begin
PERR = 1'b1;
PERR <= #1005 1'b0;
end
end
end
end
always @(pdone_event)
begin:pdone_process
PDONE = 1'b0;
#duration_write PDONE = 1'b1;
end
/////////////////////////////////////////////////////////////////////////
// Timing control for the Erase Operations
/////////////////////////////////////////////////////////////////////////
integer cnt_erase = 0;
time elapsed_erase;
time duration_erase;
time start_erase;
always @(posedge reseted)
begin
disable edone_process;
EDONE = 1'b1;
end
event edone_event;
always @(reseted or ESTART)
begin: erase
integer i;
if (reseted)
begin
if (ESTART && EDONE)
begin
cnt_erase = 0;
for (i=0;i<=SecNum;i=i+1)
begin
if ((Ers_queue[i]==1'b1) && (Sec_Prot[i]!=1'b1))
cnt_erase = cnt_erase + 1;
end
if (cnt_erase>0)
begin
elapsed_erase = 0;
duration_erase = cnt_erase* tdevice_SEO + 4;
->edone_event;
start_erase = $time;
end
else
begin
EERR = 1'b1;
EERR <= #100005 1'b0;
end
end
end
end
always @(edone_event)
begin : edone_process
EDONE = 1'b0;
#duration_erase EDONE = 1'b1;
end
always @(reseted or ESUSP)
begin
if (reseted)
if (ESUSP && ~EDONE)
begin
disable edone_process;
elapsed_erase = $time - start_erase;
duration_erase = duration_erase - elapsed_erase;
EDONE = 1'b0;
end
end
always @(reseted or ERES)
begin
if (reseted)
if (ERES && ~EDONE)
begin
start_erase = $time;
EDONE = 1'b0;
->edone_event;
end
end
// /////////////////////////////////////////////////////////////////////////
// // Main Behavior Process
// // combinational process for next state generation
// /////////////////////////////////////////////////////////////////////////
reg PATTERN_1 = 1'b0;
reg PATTERN_2 = 1'b0;
reg A_PAT_1 = 1'b0;
reg A_PAT_2 = 1'b0;
reg A_PAT_3 = 1'b0;
integer DataByte ;
always @(negedge write)
begin
DataByte = DIn;
PATTERN_1 = DataByte==8'hAA ;
PATTERN_2 = DataByte==8'h55 ;
A_PAT_1 = 1'b1;
A_PAT_2 = Address==16'hAAA ;
A_PAT_3 = Address==16'h555 ;
end
always @(write or reseted)
begin: StateGen1
if (reseted!=1'b1)
next_state = current_state;
else
if (~write)
case (current_state)
RESET :
begin
if (PATTERN_1)
next_state = Z001;
else if ((Addr==8'h55) && (DataByte==8'h98))
next_state = CFI;
else
next_state = RESET;
end
CFI:
begin
if (DataByte==8'hF0)
next_state = RESET;
else
next_state = CFI;
end
Z001 :
begin
if (PATTERN_2)
next_state = PREL_SETBWB;
else
next_state = RESET;
end
PREL_SETBWB :
begin
if (A_PAT_1 && (DataByte==16'h20))
next_state = PREL_ULBYPASS;
else if (A_PAT_1 && (DataByte==16'h90))
next_state = AS;
else if (A_PAT_1 && (DataByte==16'hA0))
next_state = A0SEEN;
else if (A_PAT_1 && (DataByte==16'h80))
next_state = C8;
else if (A_PAT_1 && (DataByte==16'h88))
next_state = OTP;
else
next_state = RESET;
end
PREL_ULBYPASS :
begin
if (DataByte == 16'h90 )
next_state <= PREL_ULBYPASS_RESET;
if (A_PAT_1 && (DataByte == 16'hA0))
next_state = A0SEEN;
else
next_state = PREL_ULBYPASS;
end
PREL_ULBYPASS_RESET :
begin
if (DataByte == 16'h00 )
if (ESP_ACT)
next_state = ESP;
else
next_state = RESET;
else
next_state <= PREL_ULBYPASS;
end
AS :
begin
if (DataByte==16'hF0)
next_state = RESET;
else if ((Addr==8'h55) && (DataByte==8'h98))
next_state = AS_CFI;
else
next_state = AS;
end
AS_CFI:
begin
if (DataByte==8'hF0)
next_state = AS;
else
next_state = AS_CFI;
end
A0SEEN :
begin
next_state = PGMS;
end
OTP :
begin
if (PATTERN_1)
next_state = OTP_Z001;
else
next_state = OTP;
end
OTP_Z001 :
begin
if (PATTERN_2)
next_state = OTP_PREL;
else
next_state = OTP;
end
OTP_PREL :
begin
if (A_PAT_1 && (DataByte == 16'h90))
next_state = OTP_AS;
else if (A_PAT_1 && (DataByte == 16'hA0))
next_state = OTP_A0SEEN;
else
next_state = OTP;
end
OTP_AS:
begin
if (DataByte == 16'h00)
if (ESP_ACT)
next_state = ESP;
else
next_state = RESET;
else if (DataByte == 16'hF0)
next_state = OTP;
else if (DataByte == 16'h98)
next_state = OTP_AS_CFI;
else
next_state = OTP_AS;
end
OTP_AS_CFI:
begin
if (DataByte == 16'hF0)
next_state = OTP_AS;
else
next_state = OTP_AS_CFI;
end
OTP_A0SEEN :
begin
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
(Address >= 16'hFF00))
next_state = PGMS;
else
next_state = OTP;
end
C8 :
begin
if (PATTERN_1)
next_state = C8_Z001;
else
next_state = RESET;
end
C8_Z001 :
begin
if (PATTERN_2)
next_state = C8_PREL;
else
next_state = RESET;
end
C8_PREL :
begin
if (A_PAT_1 && (DataByte==16'h10))
next_state = ERS;
else if (DataByte==16'h30)
next_state = SERS;
else
next_state = RESET;
end
ERS :
begin
end
SERS :
begin
if (~CTMOUT && DataByte == 16'hB0)
next_state = ESP; // ESP according to datasheet
else if (DataByte==16'h30)
next_state = SERS;
else
next_state = RESET;
end
SERS_EXEC :
begin
end
ESP :
begin
if (DataByte == 16'h30)
next_state = SERS_EXEC;
else
begin
if (PATTERN_1)
next_state = ESP_Z001;
if (Addr == 8'h55 && DataByte == 8'h98)
next_state = ESP_CFI;
end
end
ESP_CFI:
begin
if (DataByte == 8'hF0)
next_state = ESP;
else
next_state = ESP_CFI;
end
ESP_Z001 :
begin
if (PATTERN_2)
next_state = ESP_PREL;
else
next_state = ESP;
end
ESP_PREL :
begin
if (A_PAT_1 && DataByte == 16'hA0)
next_state = ESP_A0SEEN;
else if (A_PAT_1 && DataByte == 16'h20)
next_state <= PREL_ULBYPASS;
else if (A_PAT_1 && DataByte == 16'h88)
next_state <= OTP;
else if (A_PAT_1 && DataByte == 16'h90)
next_state = ESP_AS;
else
next_state = ESP;
end
ESP_A0SEEN :
begin
next_state = PGMS; //set ESP
end
ESP_AS :
begin
if (DataByte == 16'hF0)
next_state = ESP;
else if ((Addr==8'h55) && (DataByte==8'h98))
next_state = ESP_AS_CFI;
end
ESP_AS_CFI:
begin
if (DataByte == 8'hF0)
next_state = ESP_AS;
else
next_state = ESP_AS_CFI;
end
endcase
end
always @(posedge PDONE or negedge PERR)
begin: StateGen6
if (reseted!=1'b1)
next_state = current_state;
else
begin
if (current_state==PGMS && ULBYPASS)
next_state = PREL_ULBYPASS;
else if (current_state==PGMS && OTP_ACT)
next_state = OTP;
else if (current_state==PGMS && ESP_ACT)
next_state = ESP;
else if (current_state==PGMS)
next_state = RESET;
end
end
always @(posedge EDONE or negedge EERR)
begin: StateGen2
if (reseted!=1'b1)
next_state = current_state;
else
begin
if ((current_state==ERS) || (current_state==SERS_EXEC))
next_state = RESET;
end
end
always @(negedge write or reseted)
begin: StateGen7 //ok
integer i,j;
if (reseted!=1'b1)
next_state = current_state;
else
begin
if (current_state==SERS_EXEC && (write==1'b0) && (EERR!=1'b1))
if (DataByte==16'hB0)
begin
next_state = ESPS;
ESUSP = 1'b1;
ESUSP <= #1 1'b0;
end
end
end
always @(CTMOUT or reseted)
begin: StateGen4
if (reseted!=1'b1)
next_state = current_state;
else
begin
if (current_state==SERS && CTMOUT) next_state = SERS_EXEC;
end
end
always @(posedge START_T1 or reseted)
begin: StateGen5
if (reseted!=1'b1)
next_state = current_state;
else
if (current_state==ESPS && START_T1) next_state = ESP;
end
///////////////////////////////////////////////////////////////////////////
//FSM Output generation and general funcionality
///////////////////////////////////////////////////////////////////////////
always @(posedge read)
begin
->oe_event;
end
always @(MemAddress)
begin
if (read)
->oe_event;
end
always @(oe_event)
begin
oe = 1'b1;
#1 oe = 1'b0;
end
always @(DOut_zd)
begin : OutputGen
if (DOut_zd[0] !== 1'bz)
begin
CEDQ_t = CENeg_event + CEDQ_01;
OEDQ_t = OENeg_event + OEDQ_01;
ADDRDQ_t = ADDR_event + ADDRDQ_01;
FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time));
FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time));
FROMADDR = 1'b1;
if ((ADDRDQ_t > $time )&&
(((ADDRDQ_t>OEDQ_t)&&FROMOE) ||
((ADDRDQ_t>CEDQ_t)&&FROMCE)))
begin
TempData = DOut_zd;
FROMADDR = 1'b0;
DOut_Pass = 8'bx;
#(ADDRDQ_t - $time) DOut_Pass = TempData;
end
else
begin
DOut_Pass = DOut_zd;
end
end
end
always @(DOut_zd)
begin
if (DOut_zd[0] === 1'bz)
begin
disable OutputGen;
FROMCE = 1'b1;
FROMOE = 1'b1;
if ((CENeg_posEvent <= OENeg_posEvent) &&
( CENeg_posEvent + 5 >= $time))
FROMOE = 1'b0;
if ((OENeg_posEvent < CENeg_posEvent) &&
( OENeg_posEvent + 5 >= $time))
FROMCE = 1'b0;
FROMADDR = 1'b0;
DOut_Pass = DOut_zd;
end
end
always @(oe or reseted or current_state)
begin
if (reseted)
begin
case (current_state)
RESET :
begin
if (oe)
MemRead(DOut_zd);
end
AS, ESP_AS, OTP_AS :
begin
if (oe)
begin
if (AS_addr == 1'b0)
begin
end
else
AS_ID = 1'b0;
if ((Address[7:0] == 0) && (AS_ID == 1'b1))
DOut_zd = 1;
else if ((Address[7:0] == 1) && (AS_ID == 1'b1))
DOut_zd = 8'hA3;
else if ((Address[7:0] == 2) &&
(((SecAddr < 32 ) && (AS_ID == 1'b1))
|| ((SecAddr > 31 ) && (AS_ID2 == 1'b1))))
begin
DOut_zd = 8'b00000000;
DOut_zd[0] = Sec_Prot[SecAddr];
end
else if ((Address[7:0] == 6) && (AS_SecSi_FP == 1'b1))
begin
DOut_zd = 8'b0;
if (FactoryProt)
DOut_zd = 16'h99;
else
DOut_zd = 16'h19;
end
else
DOut_zd = 8'bz;
end
end
OTP :
begin
if (oe)
begin
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
(Address >= 16'hFF00))
begin
SecSiAddr = Address%(SecSiSize +1);
if (SecSi[SecSiAddr]==-1)
DOut_zd = 8'bx;
else
DOut_zd = SecSi[SecSiAddr];
end
else
$display ("Invalid SecSi query address");
end
end
CFI, AS_CFI, ESP_CFI, ESP_AS_CFI, OTP_AS_CFI :
begin
if (oe)
begin
DOut_zd = 8'bZ;
if (((MemAddress>=16'h10) && (MemAddress <= 16'h3C)) ||
((MemAddress>=16'h40) && (MemAddress <= 16'h4F)))
begin
DOut_zd = CFI_array[MemAddress];
end
else
begin
$display ("Invalid CFI query address");
end
end
end
ERS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
// read status / embeded erase algorithm - Chip Erase
///////////////////////////////////////////////////////////
Status[7] = 1'b0;
Status[6] = ~Status[6]; //toggle
Status[5] = 1'b0;
Status[3] = 1'b1;
Status[2] = ~Status[2]; //toggle
DOut_zd = Status;
end
end
SERS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read status - sector erase timeout
///////////////////////////////////////////////////////////
Status[3] = 1'b0;
Status[7] = 1'b1;
DOut_zd = Status;
end
end
ESPS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read status / erase suspend timeout - stil erasing
///////////////////////////////////////////////////////////
if (Ers_queue[SecAddr]==1'b1)
begin
Status[7] = 1'b0;
Status[2] = ~Status[2]; //toggle
end
else
Status[7] = 1'b1;
Status[6] = ~Status[6]; //toggle
Status[5] = 1'b0;
Status[3] = 1'b1;
DOut_zd = Status;
end
end
SERS_EXEC:
begin
if (oe)
begin
///////////////////////////////////////////////////
//read status erase
///////////////////////////////////////////////////
if (Ers_queue[SecAddr]==1'b1)
begin
Status[7] = 1'b0;
Status[2] = ~Status[2]; //toggle
end
else
Status[7] = 1'b1;
Status[6] = ~Status[6]; //toggle
Status[5] = 1'b0;
Status[3] = 1'b1;
DOut_zd = Status;
end
end
ESP :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read
///////////////////////////////////////////////////////////
if (Ers_queue[SecAddr]!=1'b1)
begin
MemRead(DOut_zd);
end
else
begin
///////////////////////////////////////////////////////
//read status
///////////////////////////////////////////////////////
Status[7] = 1'b1;
// Status[6) No toggle
Status[5] = 1'b0;
Status[2] = ~Status[2]; //toggle
DOut_zd = Status;
end
end
end
PGMS :
begin
if (oe)
begin
///////////////////////////////////////////////////////////
//read status
///////////////////////////////////////////////////////////
Status[6] = ~Status[6]; //toggle
Status[5] = 1'b0;
//Status[2) no toggle
Status[1] = 1'b0;
DOut_zd = Status;
if (SecAddr == SA)
DOut_zd[7] = Status[7];
else
DOut_zd[7] = ~Status[7];
end
end
endcase
end
end
always @(write or reseted)
begin : Output_generation
if (reseted)
begin
case (current_state)
RESET :
begin
ESP_ACT = 1'b0;
ULBYPASS = 1'b0;
OTP_ACT = 1'b0;
if (~write)
if (A_PAT_2 && PATTERN_1)
AS_SecSi_FP = 1'b1;
else
AS_SecSi_FP = 1'b0;
end
Z001 :
begin
if (~write)
if (A_PAT_3 && PATTERN_2)
begin
end
else
AS_SecSi_FP = 1'b0;
end
PREL_SETBWB :
begin
if (~write)
begin
if (A_PAT_1 && (DataByte==16'h20))
ULBYPASS = 1'b1;
else if (A_PAT_1 && (DataByte==16'h90))
begin
ULBYPASS = 1'b0;
if (A_PAT_2)
begin
end
else
AS_SecSi_FP = 1'b0;
if (AS_addr == 1'b0)
begin
AS_ID = 1'b1;
AS_ID2= 1'b0;
end
else
begin
AS_ID = 1'b0;
AS_ID2= 1'b1;
end
end
else if (A_PAT_1 && (DataByte==16'h88))
begin
OTP_ACT = 1;
ULBYPASS = 1'b0;
end
end
end
PREL_ULBYPASS :
begin
if (~write)
begin
ULBYPASS = 1'b1;
if (A_PAT_1 && (DataByte==16'h90))
ULBYPASS = 1'b0;
end
end
PREL_ULBYPASS_RESET :
if ((~write) && (DataByte != 16'h00 ))
ULBYPASS = 1'b1;
OTP_A0SEEN :
begin
if (~write)
begin
if ((SecAddr == 16'h3F) && (Address <= 16'hFFFF) &&
(Address >= 16'hFF00))
begin
SecSiAddr = Address%(SecSiSize +1);
OTP_ACT = 1;
PSTART = 1'b1;
PSTART <= #1 1'b0;
WBAddr = SecSiAddr;
SA = SecAddr;
temp = DataByte;
Status[7] = ~temp[7];
WBData = DataByte;
end
else
$display ("Invalid program address in SecSi region:"
,Address);
end
end
OTP_PREL :
begin
if (~write)
if (A_PAT_1 && (DataByte==16'h90))
begin
ULBYPASS = 1'b0;
if (A_PAT_2)
begin
end
else
AS_SecSi_FP = 1'b0;
if (AS_addr == 1'b0)
begin
AS_ID = 1'b1;
AS_ID2= 1'b0;
end
else
begin
AS_ID = 1'b0;
AS_ID2= 1'b1;
end
end
end
OTP_Z001 :
begin
if (~write)
if (A_PAT_3 && PATTERN_2)
begin
end
else
AS_SecSi_FP = 1'b0;
end
OTP :
begin
if (~write)
if (A_PAT_2 && PATTERN_1)
AS_SecSi_FP = 1'b1;
else
AS_SecSi_FP = 1'b0;
RY_zd = 1;
end
AS :
begin
if (~write)
if (DataByte==16'hF0)
begin
AS_SecSi_FP = 1'b0;
AS_ID = 1'b0;
AS_ID2 = 1'b0;
end
end
A0SEEN :
begin
if (~write)
begin
PSTART = 1'b1;
PSTART <= #1 1'b0;
WBData = DataByte;
WBAddr = Address;
SA = SecAddr;
Status[7] = ~DataByte[7];
end
end
C8 :
begin
end
C8_Z001 :
begin
end
C8_PREL :
begin
if (~write)
if (A_PAT_1 && (DataByte==16'h10))
begin
//Start Chip Erase
ESTART = 1'b1;
ESTART <= #1 1'b0;
ESUSP = 1'b0;
ERES = 1'b0;
Ers_queue = ~(0);
Status = 8'b00001000;
end
else if (DataByte==16'h30)
begin
//put selected sector to sec. ers. queue
//start timeout
Ers_queue = 0;
Ers_queue[SecAddr] = 1'b1;
disable TCTMOUTr;
CTMOUT_in = 1'b0;
#1 CTMOUT_in <= 1'b1;
end
end
ERS :
begin
end
SERS :
begin
if (~write && ~CTMOUT)
begin
if (DataByte == 16'hB0)
begin
//need to start erase process prior to suspend
ESTART = 1'b1;
ESTART = #1 1'b0;
ESUSP = #1 1'b0;
ESUSP = #1 1'b1;
ESUSP <= #2 1'b0;
ERES = 1'b0;
end
else if (DataByte==16'h30)
begin
disable TCTMOUTr;
CTMOUT_in = 1'b0;
#1 CTMOUT_in <= 1'b1;
Ers_queue[SecAddr] = 1'b1;
end
end
end
SERS_EXEC :
begin
if (~write)
if (~EDONE && (EERR!=1'b1) && DataByte==16'hB0)
START_T1_in = 1'b1;
end
ESP :
begin
if (~write)
begin
if (A_PAT_2 && PATTERN_1)
AS_SecSi_FP = 1'b1;
else
AS_SecSi_FP = 1'b0;
if (DataByte == 16'h30)
begin
ERES = 1'b1;
ERES <= #1 1'b0;
end
end
end
ESP_Z001 :
begin
if (~write)
if (A_PAT_3 && PATTERN_2)
begin
end
else
AS_SecSi_FP = 1'b0;
end
ESP_PREL :
begin
if (~write)
if (A_PAT_1 && (DataByte==16'h90))
begin
ULBYPASS = 1'b0;
if (A_PAT_2)
begin
end
else
AS_SecSi_FP = 1'b0;
if (AS_addr == 1'b0)
begin
AS_ID = 1'b1;
AS_ID2= 1'b0;
end
else
begin
AS_ID = 1'b0;
AS_ID2= 1'b1;
end
end
end
ESP_A0SEEN :
begin
if (~write)
begin
ESP_ACT = 1'b1;
PSTART = 1'b1;
PSTART <= #1 1'b0;
WBData = DataByte;
WBAddr = Address;
SA = SecAddr;
Status[7] = ~DataByte[7];
end
end
ESP_AS :
begin
end
endcase
end
end
initial
begin
///////////////////////////////////////////////////////////////////////
//CFI array data
///////////////////////////////////////////////////////////////////////
//CFI query identification string
for (i=16;i<92;i=i+1)
CFI_array[i] = -1;
CFI_array[16'h10] = 16'h51;
CFI_array[16'h11] = 16'h52;
CFI_array[16'h12] = 16'h59;
CFI_array[16'h13] = 16'h02;
CFI_array[16'h14] = 16'h00;
CFI_array[16'h15] = 16'h40;
CFI_array[16'h16] = 16'h00;
CFI_array[16'h17] = 16'h00;
CFI_array[16'h18] = 16'h00;
CFI_array[16'h19] = 16'h00;
CFI_array[16'h1A] = 16'h00;
//system interface string
CFI_array[16'h1B] = 16'h27;
CFI_array[16'h1C] = 16'h36;
CFI_array[16'h1D] = 16'h00;
CFI_array[16'h1E] = 16'h00;
CFI_array[16'h1F] = 16'h04;
CFI_array[16'h20] = 16'h00;
CFI_array[16'h21] = 16'h0A;
CFI_array[16'h22] = 16'h00;
CFI_array[16'h23] = 16'h05;
CFI_array[16'h24] = 16'h00;
CFI_array[16'h25] = 16'h04;
CFI_array[16'h26] = 16'h00;
//device geometry definition
CFI_array[16'h27] = 16'h16;
CFI_array[16'h28] = 16'h00;
CFI_array[16'h29] = 16'h00;
CFI_array[16'h2A] = 16'h00;
CFI_array[16'h2B] = 16'h00;
CFI_array[16'h2C] = 16'h01;
CFI_array[16'h2D] = 16'h3F;
CFI_array[16'h2E] = 16'h00;
CFI_array[16'h2F] = 16'h00;
CFI_array[16'h30] = 16'h01;
CFI_array[16'h31] = 16'h00;
CFI_array[16'h32] = 16'h00;
CFI_array[16'h33] = 16'h00;
CFI_array[16'h34] = 16'h00;
CFI_array[16'h35] = 16'h00;
CFI_array[16'h36] = 16'h00;
CFI_array[16'h37] = 16'h00;
CFI_array[16'h38] = 16'h00;
CFI_array[16'h39] = 16'h00;
CFI_array[16'h3A] = 16'h00;
CFI_array[16'h3B] = 16'h00;
CFI_array[16'h3C] = 16'h00;
//primary vendor-specific extended query
CFI_array[16'h40] = 16'h50;
CFI_array[16'h41] = 16'h52;
CFI_array[16'h42] = 16'h49;
CFI_array[16'h43] = 16'h31;
CFI_array[16'h44] = 16'h31;
CFI_array[16'h45] = 16'h01;
CFI_array[16'h46] = 16'h02;
CFI_array[16'h47] = 16'h01;
CFI_array[16'h48] = 16'h01;
CFI_array[16'h49] = 16'h04;
CFI_array[16'h4A] = 16'h00;
CFI_array[16'h4B] = 16'h00;
CFI_array[16'h4C] = 16'h00;
CFI_array[16'h4D] = 16'hB5;
CFI_array[16'h4E] = 16'hC5;
CFI_array[16'h4F] = 16'h00;
end
always @(current_state or reseted)
begin
if (reseted)
if (current_state==RESET) RY_zd = 1'b1;
if (current_state==PREL_ULBYPASS) RY_zd = 1'b1;
if (current_state==A0SEEN) RY_zd = 1'b1;
if (current_state==ERS) RY_zd = 1'b0;
if (current_state==SERS) RY_zd = 1'b0;
if (current_state==ESPS) RY_zd = 1'b0;
if (current_state==SERS_EXEC) RY_zd = 1'b0;
if (current_state==ESP) RY_zd = 1'b1;
if (current_state==OTP) RY_zd = 1'b1;
if (current_state==ESP_A0SEEN) RY_zd = 1'b1;
if (current_state==PGMS) RY_zd = 1'b0;
end
always @(EERR or EDONE or current_state)
begin : ERS2
integer i;
integer j;
if (current_state==ERS && EERR!=1'b1)
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1'b1)
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = -1;
end
if (current_state==ERS && EDONE)
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1'b1)
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = MaxData;
end
end
always @(CTMOUT or current_state)
begin : SERS2
if (current_state==SERS && CTMOUT)
begin
CTMOUT_in = 1'b0;
START_T1_in = 1'b0;
ESTART = 1'b1;
ESTART <= #1 1'b0;
ESUSP = 1'b0;
ERES = 1'b0;
end
end
always @(START_T1 or current_state)
begin : ESPS2
if (current_state==ESPS && START_T1)
begin
ESP_ACT = 1'b1;
START_T1_in = 1'b0;
end
end
always @(EERR or EDONE or current_state)
begin: SERS_EXEC2
integer i,j;
if (current_state==SERS_EXEC)
begin
if (EERR!=1'b1)
begin
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = -1;
if (EDONE)
for (i=0;i<=SecNum;i=i+1)
begin
if (Sec_Prot[i]!=1'b1 && Ers_queue[i])
for (j=0;j<=SecSize;j=j+1)
Mem[sa(i)+j] = MaxData;
end
end
end
end
end
always @(current_state or posedge PDONE)
begin: PGMS2
integer i,j;
if (current_state==PGMS)
begin
if (PERR!=1'b1)
begin
new_int = WBData;
if (OTP_ACT!=1'b1) //mem write
old_int=Mem[sa(SA) + WBAddr];
else
old_int=SecSi[WBAddr];
new_bit = new_int;
if (old_int>-1)
begin
old_bit = old_int;
for(j=0;j<=7;j=j+1)
if (~old_bit[j])
new_bit[j]=1'b0;
new_int=new_bit;
end
WBData = new_int;
if (OTP_ACT!=1'b1) //mem write
Mem[sa(SA) + WBAddr] = -1;
else
SecSi[WBAddr] = -1;
if (PDONE && ~PSTART)
begin
if (OTP_ACT!=1'b1) //mem write
Mem[sa(SA) + WBAddr] = WBData;
else
SecSi[WBAddr] = WBData;
WBData= -1;
end
end
end
end
always @(gOE_n or gCE_n or RESETNeg or RST )
begin
//Output Disable Control
if (gOE_n || gCE_n || (~RESETNeg && ~RST))
DOut_zd = 8'bZ;
end
reg BuffInOE , BuffInCE , BuffInADDR;
wire BuffOutOE, BuffOutCE, BuffOutADDR;
BUFFER BUFOE (BuffOutOE, BuffInOE);
BUFFER BUFCE (BuffOutCE, BuffInCE);
BUFFER BUFADDR (BuffOutADDR, BuffInADDR);
initial
begin
BuffInOE = 1'b1;
BuffInCE = 1'b1;
BuffInADDR = 1'b1;
end
always @(posedge BuffOutOE)
begin
OEDQ_01 = $time;
end
always @(posedge BuffOutCE)
begin
CEDQ_01 = $time;
end
always @(posedge BuffOutADDR)
begin
ADDRDQ_01 = $time;
end
function integer sa;
input [7:0] sect;
begin
sa = sect * (SecSize + 1);
end
endfunction
task MemRead;
inout[7:0] DOut_zd;
begin
if (Mem[sa(SecAddr)+Address]==-1)
DOut_zd = 8'bx;
else
DOut_zd = Mem[sa(SecAddr)+Address];
end
endtask
endmodule
module BUFFER (OUT,IN);
input IN;
output OUT;
buf ( OUT, IN);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD0_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSHOLD0_PP_BLACKBOX_V
/**
* bushold0: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates internal node weak driver).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bushold0 (
X ,
RESET,
VPWR ,
VGND ,
VPB ,
VNB
);
inout X ;
input RESET;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD0_PP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////////////////
// CRC_checker.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH decoder
// Module Name: CRC_checker
// File Name: CRC_checker.v
//
// Version: v1.0.0
//
// Description: Cyclic redundancy check (CRC) decoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module CRC_Checker
#(
parameter DATA_WIDTH = 32,
parameter HASH_LENGTH = 64,
parameter INPUT_COUNT_BITS = 13,
parameter INPUT_COUNT = 4352
)
(
i_clk ,
i_RESET ,
i_execute_crc_chk ,
i_message_valid ,
i_message ,
o_crc_chk_start ,
o_last_message ,
o_crc_chk_complete ,
o_parity_chk
);
input i_clk ;
input i_RESET ;
input i_execute_crc_chk ;
input i_message_valid ;
input [DATA_WIDTH-1:0] i_message ;
output o_crc_chk_start ;
output o_last_message ;
output o_crc_chk_complete ;
output o_parity_chk ;
localparam CRC_CHK_FSM_BIT = 5;
localparam CrcChkReset = 5'b00001;
localparam CrcChkStart = 5'b00010;
localparam CrcChkFeedBack = 5'b00100;
localparam CrcChkMessageTransferPause = 5'b01000;
localparam CrcChkParityCheck = 5'b10000;
reg [DATA_WIDTH-1:0] r_message ;
reg [CRC_CHK_FSM_BIT-1:0] r_cur_state ;
reg [CRC_CHK_FSM_BIT-1:0] r_next_state ;
reg [INPUT_COUNT_BITS-1:0] r_counter ;
reg [HASH_LENGTH-1:0] r_parity_code ;
wire [HASH_LENGTH-1:0] w_next_parity_code ;
wire w_valid_execution ;
CRC_parallel_m_lfs_XOR
#(
.DATA_WIDTH (DATA_WIDTH ),
.HASH_LENGTH (HASH_LENGTH)
)
CRC_mLFSXOR_matrix (
.i_message (r_message ),
.i_cur_parity (r_parity_code ),
.o_next_parity (w_next_parity_code));
assign w_valid_execution = i_execute_crc_chk & i_message_valid;
assign o_crc_chk_start = (r_cur_state == CrcChkStart);
assign o_last_message = (i_message_valid == 1) & (r_counter == INPUT_COUNT-1);
assign o_crc_chk_complete = (r_counter == INPUT_COUNT);
assign o_parity_chk = (r_counter == INPUT_COUNT)? (|w_next_parity_code): 0;
always @ (posedge i_clk)
begin
if (i_RESET)
r_cur_state <= CrcChkReset;
else
r_cur_state <= r_next_state;
end
always @ (*)
begin
case (r_cur_state)
CrcChkReset:
r_next_state <= (w_valid_execution) ? (CrcChkStart) : (CrcChkReset);
CrcChkStart:
r_next_state <= (i_message_valid) ? (CrcChkFeedBack) : (CrcChkMessageTransferPause);
CrcChkFeedBack:
r_next_state <= (o_crc_chk_complete) ? (CrcChkParityCheck) :
((i_message_valid) ? (CrcChkFeedBack) : (CrcChkMessageTransferPause));
CrcChkMessageTransferPause:
r_next_state <= (i_message_valid) ? (CrcChkFeedBack) : (CrcChkMessageTransferPause);
CrcChkParityCheck:
r_next_state <= CrcChkReset;
default:
r_next_state <= CrcChkReset;
endcase
end
always @ (posedge i_clk)
begin
if (i_RESET) begin
r_counter <= 0;
r_message <= 0;
r_parity_code <= 0;
end
else begin
case (r_next_state)
CrcChkReset: begin
r_counter <= 0;
r_message <= 0;
r_parity_code <= 0;
end
CrcChkStart: begin
r_counter <= 1;
r_message <= i_message;
r_parity_code <= 0;
end
CrcChkFeedBack: begin
r_counter <= r_counter + 1'b1;
r_message <= i_message;
r_parity_code <= w_next_parity_code;
end
CrcChkMessageTransferPause: begin
r_counter <= r_counter;
r_message <= r_message;
r_parity_code <= r_parity_code;
end
CrcChkParityCheck: begin
r_counter <= 0;
r_message <= 0;
r_parity_code <= w_next_parity_code;
end
default: begin
r_counter <= 0;
r_message <= 0;
r_parity_code <= 0;
end
endcase
end
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [4*8:1] vstr;
const string s = "a"; // Check static assignment
string s2;
string s3;
reg eq;
// Operators == != < <= > >= {a,b} {a{b}} a[b]
// a.len, a.putc, a.getc, a.toupper, a.tolower, a.compare, a.icompare, a.substr
// a.atoi, a.atohex, a.atooct, a.atobin, a.atoreal,
// a.itoa, a.hextoa, a.octoa, a.bintoa, a.realtoa
initial begin
$sformat(vstr, "s=%s", s);
`checks(vstr, "s=a");
`checks(s, "a");
`checks({s,s,s}, "aaa");
`checks({4{s}}, "aaaa");
// Constification
`checkh(s == "a", 1'b1);
`checkh(s == "b", 1'b0);
`checkh(s != "a", 1'b0);
`checkh(s != "b", 1'b1);
`checkh(s > " ", 1'b1);
`checkh(s > "a", 1'b0);
`checkh(s >= "a", 1'b1);
`checkh(s >= "b", 1'b0);
`checkh(s < "a", 1'b0);
`checkh(s < "b", 1'b1);
`checkh(s <= " ", 1'b0);
`checkh(s <= "a", 1'b1);
end
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
s2 = "c0";
end
else if (cyc==1) begin
$sformat(vstr, "s2%s", s2);
`checks(vstr, "s2c0");
end
else if (cyc==2) begin
s3 = s2;
$sformat(vstr, "s2%s", s3);
`checks(vstr, "s2c0");
end
else if (cyc==3) begin
s2 = "a";
s3 = "b";
end
else if (cyc==4) begin
`checks({s2,s3}, "ab");
`checks({3{s3}}, "bbb");
`checkh(s == "a", 1'b1);
`checkh(s == "b", 1'b0);
`checkh(s != "a", 1'b0);
`checkh(s != "b", 1'b1);
`checkh(s > " ", 1'b1);
`checkh(s > "a", 1'b0);
`checkh(s >= "a", 1'b1);
`checkh(s >= "b", 1'b0);
`checkh(s < "a", 1'b0);
`checkh(s < "b", 1'b1);
`checkh(s <= " ", 1'b0);
`checkh(s <= "a", 1'b1);
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
module tiny(clk, reset, sel, addr, w, data, out, done);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [`WIDTH_D0:0] data;
output [`WIDTH_D0:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
wire [`WIDTH_D0:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [`WIDTH_D0:0] ram_a_data_out, ram_b_data_out;
/* for const */
wire [`WIDTH_D0:0] const0_out, const1_out;
wire const0_effective, const1_effective;
/* for muxer */
wire [`WIDTH_D0:0] muxer0_out, muxer1_out;
/* for ROM */
wire [8:0] rom_addr;
wire [27:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
assign out = ram_a_data_out;
select
select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
rom
rom0 (clk, rom_addr, rom_q);
FSM
fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
const_
const0 (clk, ram_a_addr, const0_out, const0_effective),
const1 (clk, ram_b_addr, const1_out, const1_effective);
ram
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
muxer
muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out),
muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out);
PE
pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[`WIDTH:0], muxer0_out[`WIDTH:0], ram_b_data_in[`WIDTH:0]);
assign ram_b_data_in[`WIDTH_D0:`WIDTH+1] = 0;
endmodule
module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
module muxer(from_ram, from_const, const_effective, out);
input [`WIDTH_D0:0] from_ram, from_const;
input const_effective;
output [`WIDTH_D0:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
|
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module adc_interface
(input clock, input reset, input enable,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe,
input wire [11:0] rx_a_a, input wire [11:0] rx_b_a, input wire [11:0] rx_a_b, input wire [11:0] rx_b_b,
output wire [31:0] rssi_0, output wire [31:0] rssi_1, output wire [31:0] rssi_2, output wire [31:0] rssi_3,
output reg [15:0] ddc0_in_i, output reg [15:0] ddc0_in_q,
output reg [15:0] ddc1_in_i, output reg [15:0] ddc1_in_q,
output reg [15:0] ddc2_in_i, output reg [15:0] ddc2_in_q,
output reg [15:0] ddc3_in_i, output reg [15:0] ddc3_in_q,
output wire [3:0] rx_numchan);
// Buffer at input to chip
reg [11:0] adc0,adc1,adc2,adc3;
always @(posedge clock)
begin
adc0 <= #1 rx_a_a;
adc1 <= #1 rx_b_a;
adc2 <= #1 rx_a_b;
adc3 <= #1 rx_b_b;
end
// then scale and subtract dc offset
wire [3:0] dco_en;
wire [15:0] adc0_corr,adc1_corr,adc2_corr,adc3_corr;
setting_reg #(`FR_DC_OFFSET_CL_EN) sr_dco_en(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(dco_en));
rx_dcoffset #(`FR_ADC_OFFSET_0) rx_dcoffset0(.clock(clock),.enable(dco_en[0]),.reset(reset),.adc_in({adc0[11],adc0,3'b0}),.adc_out(adc0_corr),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
rx_dcoffset #(`FR_ADC_OFFSET_1) rx_dcoffset1(.clock(clock),.enable(dco_en[1]),.reset(reset),.adc_in({adc1[11],adc1,3'b0}),.adc_out(adc1_corr),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
rx_dcoffset #(`FR_ADC_OFFSET_2) rx_dcoffset2(.clock(clock),.enable(dco_en[2]),.reset(reset),.adc_in({adc2[11],adc2,3'b0}),.adc_out(adc2_corr),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
rx_dcoffset #(`FR_ADC_OFFSET_3) rx_dcoffset3(.clock(clock),.enable(dco_en[3]),.reset(reset),.adc_in({adc3[11],adc3,3'b0}),.adc_out(adc3_corr),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
// Level sensing for AGC
rssi rssi_block_0 (.clock(clock),.reset(reset),.enable(enable),.adc(adc0),.rssi(rssi_0[15:0]),.over_count(rssi_0[31:16]));
rssi rssi_block_1 (.clock(clock),.reset(reset),.enable(enable),.adc(adc1),.rssi(rssi_1[15:0]),.over_count(rssi_1[31:16]));
rssi rssi_block_2 (.clock(clock),.reset(reset),.enable(enable),.adc(adc2),.rssi(rssi_2[15:0]),.over_count(rssi_2[31:16]));
rssi rssi_block_3 (.clock(clock),.reset(reset),.enable(enable),.adc(adc3),.rssi(rssi_3[15:0]),.over_count(rssi_3[31:16]));
// And mux to the appropriate outputs
wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux;
wire rx_realsignals;
setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),
.in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]}));
assign rx_numchan[0] = 1'b0;
always @(posedge clock)
begin
ddc0_in_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? adc3_corr : adc2_corr) : (ddc0mux[0] ? adc1_corr : adc0_corr);
ddc0_in_q <= #1 rx_realsignals ? 16'd0 : ddc0mux[3] ? (ddc0mux[2] ? adc3_corr : adc2_corr) : (ddc0mux[2] ? adc1_corr : adc0_corr);
ddc1_in_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? adc3_corr : adc2_corr) : (ddc1mux[0] ? adc1_corr : adc0_corr);
ddc1_in_q <= #1 rx_realsignals ? 16'd0 : ddc1mux[3] ? (ddc1mux[2] ? adc3_corr : adc2_corr) : (ddc1mux[2] ? adc1_corr : adc0_corr);
ddc2_in_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? adc3_corr : adc2_corr) : (ddc2mux[0] ? adc1_corr : adc0_corr);
ddc2_in_q <= #1 rx_realsignals ? 16'd0 : ddc2mux[3] ? (ddc2mux[2] ? adc3_corr : adc2_corr) : (ddc2mux[2] ? adc1_corr : adc0_corr);
ddc3_in_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? adc3_corr : adc2_corr) : (ddc3mux[0] ? adc1_corr : adc0_corr);
ddc3_in_q <= #1 rx_realsignals ? 16'd0 : ddc3mux[3] ? (ddc3mux[2] ? adc3_corr : adc2_corr) : (ddc3mux[2] ? adc1_corr : adc0_corr);
end
endmodule // adc_interface
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 11
(* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "system_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "system_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDT\
H=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_11_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
reg probepresent /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
probepresent <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
probepresent <= jdo[19] ? 1
: jdo[18] ? 0
: probepresent;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset)
begin
jtag_break <= probepresent;
resetlatch <= 1;
end
else if (~debugack & debugreq & probepresent)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
byteena_a,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q_a;
output [ 31: 0] q_b;
input [ 7: 0] address_a;
input [ 7: 0] address_b;
input [ 3: 0] byteena_a;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 31: 0] data_a;
input [ 31: 0] data_b;
input wren_a;
input wren_b;
wire [ 31: 0] q_a;
wire [ 31: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.byteena_a (byteena_a),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "CYCLONEIVE",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 256,
the_altsyncram.numwords_b = 256,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8,
the_altsyncram.widthad_b = 8,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_ocimem (
// inputs:
address,
begintransfer,
byteenable,
chipselect,
clk,
debugaccess,
jdo,
jrst_n,
resetrequest,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
oci_ram_readdata
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] oci_ram_readdata;
input [ 8: 0] address;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input resetrequest;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonWr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon;
wire [ 31: 0] cfgdout;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] sramdout;
assign avalon = begintransfer & ~resetrequest;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
MonWr <= 1'b0;
MonRd <= 1'b0;
MonRd1 <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonRd <= 1'b1;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
MonRd <= 1'b1;
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonDReg <= jdo[34 : 3];
MonWr <= 1'b1;
end
else
begin
if (~avalon)
begin
MonWr <= 0;
MonRd <= 0;
end
if (MonRd1)
MonDReg <= MonAReg[10] ? cfgdout : sramdout;
end
MonRd1 <= MonRd;
end
end
//niosII_system_nios2_0_ociram_lpm_dram_bdp_component, which is an nios_tdp_ram
niosII_system_nios2_0_ociram_lpm_dram_bdp_component_module niosII_system_nios2_0_ociram_lpm_dram_bdp_component
(
.address_a (address[7 : 0]),
.address_b (MonAReg[9 : 2]),
.byteena_a (byteenable),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (writedata),
.data_b (MonDReg[31 : 0]),
.q_a (oci_ram_readdata),
.q_b (sramdout),
.wren_a (chipselect & write & debugaccess &
~address[8]
),
.wren_b (MonWr)
);
//synthesis translate_off
`ifdef NO_PLI
defparam niosII_system_nios2_0_ociram_lpm_dram_bdp_component.lpm_file = "niosII_system_nios2_0_ociram_default_contents.dat";
`else
defparam niosII_system_nios2_0_ociram_lpm_dram_bdp_component.lpm_file = "niosII_system_nios2_0_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam niosII_system_nios2_0_ociram_lpm_dram_bdp_component.lpm_file = "niosII_system_nios2_0_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgdout = (MonAReg[4 : 2] == 3'd0)? 32'h04004020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001b1b :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h04004000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input chipselect;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = chipselect & write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000111111;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000111111);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 24: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 26: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 26: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 26: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 26: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] excaddr;
wire instr_retired;
wire is_advanced_exception;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
wire sync_pending;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign is_advanced_exception = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign excaddr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_pending = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_pending;
assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | is_advanced_exception)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_frametype <= 4'b0010;
pending_excaddr <= excaddr;
if (is_fast_tlb_miss_exception)
pending_exctype <= 1'b1;
else
pending_exctype <= 1'b0;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (pending_frametype == 4'b0010))
itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype};
else if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 26: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//niosII_system_nios2_0_nios2_oci_trc_ctrl_td_mode, which is an e_instance
niosII_system_nios2_0_nios2_oci_td_mode niosII_system_nios2_0_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
)
;
output [ 1: 0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_tm_count;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_tm_count = 0;
end // 3'b000
3'b001: begin
compute_tm_count = 1;
end // 3'b001
3'b010: begin
compute_tm_count = 1;
end // 3'b010
3'b011: begin
compute_tm_count = 2;
end // 3'b011
3'b100: begin
compute_tm_count = 1;
end // 3'b100
3'b101: begin
compute_tm_count = 2;
end // 3'b101
3'b110: begin
compute_tm_count = 2;
end // 3'b110
3'b111: begin
compute_tm_count = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
)
;
output [ 3: 0] fifowp_inc;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 3: 0] fifowp_inc;
always @(free2 or free3 or tm_count)
begin
if (free3 & (tm_count == 3))
fifowp_inc = 3;
else if (free2 & (tm_count >= 2))
fifowp_inc = 2;
else if (tm_count >= 1)
fifowp_inc = 1;
else
fifowp_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
)
;
output [ 4: 0] fifocount_inc;
input empty;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 4: 0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)
begin
if (empty)
fifocount_inc = tm_count[1 : 0];
else if (free3 & (tm_count == 3))
fifocount_inc = 2;
else if (free2 & (tm_count >= 2))
fifocount_inc = 1;
else if (tm_count >= 1)
fifocount_inc = 0;
else
fifocount_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_tm_count_tm_count;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
wire [ 35: 0] fifo_read_mux;
reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifocount_inc_fifocount;
wire [ 35: 0] fifohead;
reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifowp1;
wire [ 3: 0] fifowp2;
wire [ 3: 0] fifowp_inc_fifowp;
wire free2;
wire free3;
wire itm_valid;
reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] ovr_pending_atm;
wire [ 35: 0] ovr_pending_dtm;
wire [ 1: 0] tm_count;
wire tm_count_ge1;
wire tm_count_ge2;
wire tm_count_ge3;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign free2 = ~fifocount[4];
assign free3 = ~fifocount[4] & ~&fifocount[3 : 0];
assign empty = ~|fifocount;
assign fifowp1 = fifowp + 1;
assign fifowp2 = fifowp + 2;
//niosII_system_nios2_0_nios2_oci_compute_tm_count_tm_count, which is an e_instance
niosII_system_nios2_0_nios2_oci_compute_tm_count niosII_system_nios2_0_nios2_oci_compute_tm_count_tm_count
(
.atm_valid (atm_valid),
.compute_tm_count (compute_tm_count_tm_count),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign tm_count = compute_tm_count_tm_count;
//niosII_system_nios2_0_nios2_oci_fifowp_inc_fifowp, which is an e_instance
niosII_system_nios2_0_nios2_oci_fifowp_inc niosII_system_nios2_0_nios2_oci_fifowp_inc_fifowp
(
.fifowp_inc (fifowp_inc_fifowp),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//niosII_system_nios2_0_nios2_oci_fifocount_inc_fifocount, which is an e_instance
niosII_system_nios2_0_nios2_oci_fifocount_inc niosII_system_nios2_0_nios2_oci_fifocount_inc_fifocount
(
.empty (empty),
.fifocount_inc (fifocount_inc_fifocount),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//the_niosII_system_nios2_0_oci_test_bench, which is an e_instance
niosII_system_nios2_0_oci_test_bench the_niosII_system_nios2_0_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fiforp <= 0;
fifowp <= 0;
fifocount <= 0;
ovf_pending <= 1;
end
else
begin
fifowp <= fifowp + fifowp_inc_fifowp;
fifocount <= fifocount + fifocount_inc_fifocount;
if (~empty)
fiforp <= fiforp + 1;
if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count)))
ovf_pending <= 1;
else if (atm_valid | dtm_valid)
ovf_pending <= 0;
end
end
assign fifohead = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm;
assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm :
(((fifowp == 4'd0) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm :
(((fifowp == 4'd1) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm :
(((fifowp == 4'd2) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm :
(((fifowp == 4'd3) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm :
(((fifowp == 4'd4) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm :
(((fifowp == 4'd5) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm :
(((fifowp == 4'd6) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm :
(((fifowp == 4'd7) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm :
(((fifowp == 4'd8) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm :
(((fifowp == 4'd9) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm :
(((fifowp == 4'd10) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm :
(((fifowp == 4'd11) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm :
(((fifowp == 4'd12) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm :
(((fifowp == 4'd13) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm :
(((fifowp == 4'd14) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm :
(((fifowp == 4'd15) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign tm_count_ge1 = |tm_count;
assign tm_count_ge2 = tm_count[1];
assign tm_count_ge3 = &tm_count;
assign ovr_pending_atm = {ovf_pending, atm[34 : 0]};
assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]};
assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 :
(fiforp == 4'd1)? fifo_1 :
(fiforp == 4'd2)? fifo_2 :
(fiforp == 4'd3)? fifo_3 :
(fiforp == 4'd4)? fifo_4 :
(fiforp == 4'd5)? fifo_5 :
(fiforp == 4'd6)? fifo_6 :
(fiforp == 4'd7)? fifo_7 :
(fiforp == 4'd8)? fifo_8 :
(fiforp == 4'd9)? fifo_9 :
(fiforp == 4'd10)? fifo_10 :
(fiforp == 4'd11)? fifo_11 :
(fiforp == 4'd12)? fifo_12 :
(fiforp == 4'd13)? fifo_13 :
(fiforp == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_traceram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 35: 0] q_a;
output [ 35: 0] q_b;
input [ 6: 0] address_a;
input [ 6: 0] address_b;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 35: 0] data_a;
input [ 35: 0] data_b;
input wren_a;
input wren_b;
wire [ 35: 0] q_a;
wire [ 35: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "CYCLONEIVE",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 128,
the_altsyncram.numwords_b = 128,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 36,
the_altsyncram.width_b = 36,
the_altsyncram.widthad_a = 7,
the_altsyncram.widthad_b = 7,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 35: 0] trc_jtag_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire [ 35: 0] unused_bdpram_port_q_a;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = (0) ?
trc_jtag_data : 0;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
//niosII_system_nios2_0_traceram_lpm_dram_bdp_component, which is an nios_tdp_ram
niosII_system_nios2_0_traceram_lpm_dram_bdp_component_module niosII_system_nios2_0_traceram_lpm_dram_bdp_component
(
.address_a (trc_im_addr),
.address_b (trc_jtag_addr),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (trc_im_data),
.data_b (jdo[36 : 1]),
.q_a (unused_bdpram_port_q_a),
.q_b (trc_jtag_data),
.wren_a (tw_valid & trc_enb),
.wren_b (take_action_tracemem_b)
);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address,
av_ld_data_aligned_filtered,
begintransfer,
byteenable,
chipselect,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess,
hbreak_enabled,
reset,
reset_n,
test_ending,
test_has_ended,
write,
writedata,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 24: 0] F_pc;
input [ 8: 0] address;
input [ 31: 0] av_ld_data_aligned_filtered;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input [ 26: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess;
input hbreak_enabled;
input reset;
input reset_n;
input test_ending;
input test_has_ended;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] MonDReg;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
wire clkx2;
wire [ 26: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
niosII_system_nios2_0_nios2_oci_debug the_niosII_system_nios2_0_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
niosII_system_nios2_0_nios2_ocimem the_niosII_system_nios2_0_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.begintransfer (begintransfer),
.byteenable (byteenable),
.chipselect (chipselect),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.oci_ram_readdata (oci_ram_readdata),
.resetrequest (resetrequest),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.write (write),
.writedata (writedata)
);
niosII_system_nios2_0_nios2_avalon_reg the_niosII_system_nios2_0_nios2_avalon_reg
(
.address (address),
.chipselect (chipselect),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
niosII_system_nios2_0_nios2_oci_break the_niosII_system_nios2_0_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
niosII_system_nios2_0_nios2_oci_xbrk the_niosII_system_nios2_0_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
niosII_system_nios2_0_nios2_oci_dbrk the_niosII_system_nios2_0_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
niosII_system_nios2_0_nios2_oci_itrace the_niosII_system_nios2_0_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
niosII_system_nios2_0_nios2_oci_dtrace the_niosII_system_nios2_0_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
niosII_system_nios2_0_nios2_oci_fifo the_niosII_system_nios2_0_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
niosII_system_nios2_0_nios2_oci_pib the_niosII_system_nios2_0_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
niosII_system_nios2_0_nios2_oci_im the_niosII_system_nios2_0_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign readdata = address[8] ? oci_reg_readdata : oci_ram_readdata;
assign jtag_debug_module_debugaccess_to_roms = debugack;
niosII_system_nios2_0_jtag_debug_module_wrapper the_niosII_system_nios2_0_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0 (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_begintransfer,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_select,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
no_ci_readra
)
;
output [ 26: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 26: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input jtag_debug_module_begintransfer;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_select;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 24: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 26: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 24: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 24: 0] F_pc_no_crst_nxt;
wire [ 24: 0] F_pc_nxt;
wire [ 24: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 26: 0] F_pcb;
wire [ 26: 0] F_pcb_nxt;
wire [ 26: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 26: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 26: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
wire d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 26: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_niosII_system_nios2_0_test_bench, which is an e_instance
niosII_system_nios2_0_test_bench the_niosII_system_nios2_0_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_alu_result (E_alu_result),
.E_mem_byte_en (E_mem_byte_en),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_exception (R_ctrl_exception),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_bstatus_reg (W_bstatus_reg),
.W_cmp_result (W_cmp_result),
.W_estatus_reg (W_estatus_reg),
.W_ienable_reg (W_ienable_reg),
.W_ipending_reg (W_ipending_reg),
.W_mem_baddr (W_mem_baddr),
.W_rf_wr_data (W_rf_wr_data),
.W_status_reg (W_status_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.d_write_nxt (d_write_nxt),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000111111;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 16781320 :
(F_pc_sel_nxt == 2'b01)? 16785928 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[26 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 16781312;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//niosII_system_nios2_0_register_bank_a, which is an nios_sdp_ram
niosII_system_nios2_0_register_bank_a_module niosII_system_nios2_0_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam niosII_system_nios2_0_register_bank_a.lpm_file = "niosII_system_nios2_0_rf_ram_a.dat";
`else
defparam niosII_system_nios2_0_register_bank_a.lpm_file = "niosII_system_nios2_0_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam niosII_system_nios2_0_register_bank_a.lpm_file = "niosII_system_nios2_0_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//niosII_system_nios2_0_register_bank_b, which is an nios_sdp_ram
niosII_system_nios2_0_register_bank_b_module niosII_system_nios2_0_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam niosII_system_nios2_0_register_bank_b.lpm_file = "niosII_system_nios2_0_rf_ram_b.dat";
`else
defparam niosII_system_nios2_0_register_bank_b.lpm_file = "niosII_system_nios2_0_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam niosII_system_nios2_0_register_bank_b.lpm_file = "niosII_system_nios2_0_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[26 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
0;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[26 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000111111;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000111111;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
niosII_system_nios2_0_nios2_oci the_niosII_system_nios2_0_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.begintransfer (jtag_debug_module_begintransfer),
.byteenable (jtag_debug_module_byteenable),
.chipselect (jtag_debug_module_select),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.write (jtag_debug_module_write),
.writedata (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_icmp(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall, i_settings);
parameter DATA_WIDTH = 32;
parameter MODE_WIDTH = 4;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output reg o_dataout;
output o_dataout_valid;
input i_stall;
input [MODE_WIDTH-1:0] i_settings;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire signed [DATA_WIDTH-1:0] sdataa;
wire signed [DATA_WIDTH-1:0] sdatab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & ~i_stall);
assign sdataa = dataa;
assign sdatab = datab;
always @(*)
begin
case (i_settings)
5'h0: // EQ
begin
o_dataout <= (dataa == datab) ? 1'b1 : 1'b0;
end
5'h1: // NE
begin
o_dataout <= (dataa != datab) ? 1'b1 : 1'b0;
end
5'h2: // UGT
begin
o_dataout <= (dataa > datab) ? 1'b1 : 1'b0;
end
5'h3: // UGE
begin
o_dataout <= (dataa >= datab) ? 1'b1 : 1'b0;
end
5'h4: // ULT
begin
o_dataout <= (dataa < datab) ? 1'b1 : 1'b0;
end
5'h5: // ULE
begin
o_dataout <= (dataa <= datab) ? 1'b1 : 1'b0;
end
5'h6: // SGT
begin
o_dataout <= (sdataa > sdatab) ? 1'b1 : 1'b0;
end
5'h7: // SGE
begin
o_dataout <= (sdataa >= sdatab) ? 1'b1 : 1'b0;
end
5'h8: // SLT
begin
o_dataout <= (sdataa < sdatab) ? 1'b1 : 1'b0;
end
5'h9: // SLE
begin
o_dataout <= (sdataa <= sdatab) ? 1'b1 : 1'b0;
end
default:
begin
o_dataout <= 1'b0;
end
endcase
end
assign o_dataout_valid = is_fifo_a_valid & is_fifo_b_valid;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module title2 (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("title2.mif"),
.C_INIT_FILE("title2.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(10404),
.C_READ_DEPTH_A(10404),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(10404),
.C_READ_DEPTH_B(10404),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("4"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 6.227751 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(14'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_wr_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_awready ,
input wire s_awvalid ,
output wire m_awvalid ,
input wire m_awready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
output wire b_push ,
input wire b_full ,
output wire a_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE_WAIT = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] next_state;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
end else begin
state <= next_state;
end
end
// Next state transitions.
always @( * )
begin
next_state = state;
case (state)
SM_IDLE:
if (s_awvalid) begin
next_state = SM_CMD_EN;
end else
next_state = state;
SM_CMD_EN:
if (m_awready & next_pending)
next_state = SM_CMD_ACCEPTED;
else if (m_awready & ~next_pending & b_full)
next_state = SM_DONE_WAIT;
else if (m_awready & ~next_pending & ~b_full)
next_state = SM_IDLE;
else
next_state = state;
SM_CMD_ACCEPTED:
next_state = SM_CMD_EN;
SM_DONE_WAIT:
if (!b_full)
next_state = SM_IDLE;
else
next_state = state;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_awvalid = (state == SM_CMD_EN);
assign next = ((state == SM_CMD_ACCEPTED)
| (((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE))) ;
assign a_push = (state == SM_IDLE);
assign s_awready = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
assign b_push = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_clock.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_clock.v
// Description : PIPE Clock Module for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Clock Module -------------------------------------------------
module pcie3_7x_0_pipe_clock #
(
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_CLK_SHARING_EN= "FALSE", // Enable Clock Sharing
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
parameter PCIE_OOBCLK_MODE = 1, // PCIe oob clock mode
parameter PCIE_DEBUG_MODE = 0 // PCIe Debug mode
)
(
//---------- Input -------------------------------------
input CLK_CLK,
input CLK_TXOUTCLK,
input [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
input CLK_RST_N,
input [PCIE_LANE-1:0] CLK_PCLK_SEL,
input [PCIE_LANE-1:0] CLK_PCLK_SEL_SLAVE,
input CLK_GEN3,
//---------- Output ------------------------------------
output CLK_PCLK,
output CLK_PCLK_SLAVE,
output CLK_RXUSRCLK,
output [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
output CLK_DCLK,
output CLK_OOBCLK,
output CLK_USERCLK1,
output CLK_USERCLK2,
output CLK_MMCM_LOCK
);
//---------- Select Clock Divider ----------------------
localparam DIVCLK_DIVIDE = (PCIE_REFCLK_FREQ == 2) ? 1 :
(PCIE_REFCLK_FREQ == 1) ? 1 : 1;
localparam CLKFBOUT_MULT_F = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKIN1_PERIOD = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKOUT0_DIVIDE_F = 8;
localparam CLKOUT1_DIVIDE = 4;
localparam CLKOUT2_DIVIDE = (PCIE_USERCLK1_FREQ == 5) ? 2 :
(PCIE_USERCLK1_FREQ == 4) ? 4 :
(PCIE_USERCLK1_FREQ == 3) ? 8 :
(PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
localparam CLKOUT3_DIVIDE = (PCIE_USERCLK2_FREQ == 5) ? 2 :
(PCIE_USERCLK2_FREQ == 4) ? 4 :
(PCIE_USERCLK2_FREQ == 3) ? 8 :
(PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
localparam CLKOUT4_DIVIDE = 20;
localparam PCIE_GEN1_MODE = 1'b0; // PCIe link speed is GEN1 only
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg1 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg2 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0;
//---------- Internal Signals --------------------------
wire refclk;
wire mmcm_fb;
wire clk_125mhz;
wire clk_125mhz_buf;
wire clk_250mhz;
wire userclk1;
wire userclk2;
wire oobclk;
reg pclk_sel = 1'd0;
reg pclk_sel_slave = 1'd0;
//---------- Output Registers --------------------------
wire pclk_1;
wire pclk;
wire userclk1_1;
wire userclk2_1;
wire mmcm_lock;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Input FF ----------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
pclk_sel_slave_reg1 <= {PCIE_LANE{1'd0}};
gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
pclk_sel_slave_reg2 <= {PCIE_LANE{1'd0}};
gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= CLK_PCLK_SEL;
pclk_sel_slave_reg1 <= CLK_PCLK_SEL_SLAVE;
gen3_reg1 <= CLK_GEN3;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
pclk_sel_slave_reg2 <= pclk_sel_slave_reg1;
gen3_reg2 <= gen3_reg1;
end
end
/*
//---------- Select Reference clock or TXOUTCLK --------------------------------
generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
begin : refclk_i
//---------- Select Reference Clock ----------------------------------------
BUFG refclk_i
(
//---------- Input -------------------------------------
.I (CLK_CLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
else
begin : txoutclk_i
//---------- Select TXOUTCLK -----------------------------------------------
BUFG txoutclk_i
(
//---------- Input -------------------------------------
.I (CLK_TXOUTCLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
endgenerate
*/
//---------- MMCM --------------------------------------------------------------
MMCME2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKIN1_PERIOD),
.REF_JITTER1 (0.010)
)
mmcm_i
(
//---------- Input ------------------------------------
.CLKIN1 (CLK_TXOUTCLK),
.CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues
//.CLKIN2 (refclk), // not used, comment out CLKIN2 if it cause implementation issues
.CLKINSEL (1'd1),
.CLKFBIN (mmcm_fb),
.RST (!CLK_RST_N),
.PWRDWN (1'd0),
//---------- Output ------------------------------------
.CLKFBOUT (mmcm_fb),
.CLKFBOUTB (),
.CLKOUT0 (clk_125mhz),
.CLKOUT0B (),
.CLKOUT1 (clk_250mhz),
.CLKOUT1B (),
.CLKOUT2 (userclk1),
.CLKOUT2B (),
.CLKOUT3 (userclk2),
.CLKOUT3B (),
.CLKOUT4 (oobclk),
.CLKOUT5 (),
.CLKOUT6 (),
.LOCKED (mmcm_lock),
//---------- Dynamic Reconfiguration -------------------
.DCLK ( 1'd0),
.DADDR ( 7'd0),
.DEN ( 1'd0),
.DWE ( 1'd0),
.DI (16'd0),
.DO (),
.DRDY (),
//---------- Dynamic Phase Shift -----------------------
.PSCLK (1'd0),
.PSEN (1'd0),
.PSINCDEC (1'd0),
.PSDONE (),
//---------- Status ------------------------------------
.CLKINSTOPPED (),
.CLKFBSTOPPED ()
);
//---------- Select PCLK MUX ---------------------------------------------------
generate if (PCIE_LINK_SPEED != 1)
begin : pclk_i1_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_i1
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel),
.S1 ( pclk_sel),
//---------- Output --------------------------------
.O (pclk_1)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_i1_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_i1
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (clk_125mhz_buf)
);
assign pclk_1 = clk_125mhz_buf;
end
endgenerate
//---------- Select PCLK MUX for Slave---------------------------------------------------
generate if(PCIE_CLK_SHARING_EN == "FALSE")
//---------- PCLK MUX for Slave------------------//
begin : pclk_slave_disable
assign CLK_PCLK_SLAVE = 1'b0;
end
else if (PCIE_LINK_SPEED != 1)
begin : pclk_slave_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_slave
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel_slave),
.S1 ( pclk_sel_slave),
//---------- Output --------------------------------
.O (CLK_PCLK_SLAVE)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_slave_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_slave
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_PCLK_SLAVE)
);
end
endgenerate
//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE"))
begin : rxoutclk_per_lane
//---------- Generate per Lane -------------------------
for (i=0; i<PCIE_LANE; i=i+1)
begin : rxoutclk_i
//---------- RXOUTCLK Buffer -----------------------
BUFG rxoutclk_i
(
//---------- Input -----------------------------
.I (CLK_RXOUTCLK_IN[i]),
//---------- Output ----------------------------
.O (CLK_RXOUTCLK_OUT[i])
);
end
end
else
//---------- Disable RXOUTCLK Buffer for Normal Operation
begin : rxoutclk_i_disable
assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
end
endgenerate
//---------- Generate DCLK Buffer ----------------------------------------------
generate if (PCIE_USERCLK2_FREQ <= 3)
//---------- Disable DCLK Buffer -----------------------
begin : dclk_i
assign CLK_DCLK = userclk2_1; // always less than 125Mhz
end
else
begin : dclk_i_bufg
//---------- DCLK Buffer -------------------------------
BUFG dclk_i
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_DCLK)
);
end
endgenerate
//---------- Generate USERCLK1 Buffer ------------------------------------------
generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK1_FREQ == 3)
//---------- USERCLK1 same as PCLK -------------------
begin :userclk1_i1_no_bufg
assign userclk1_1 = pclk_1;
end
else
begin : userclk1_i1
//---------- USERCLK1 Buffer ---------------------------
BUFG usrclk1_i1
(
//---------- Input ---------------------------------
.I (userclk1),
//---------- Output --------------------------------
.O (userclk1_1)
);
end
endgenerate
//---------- Generate USERCLK2 Buffer ------------------------------------------
generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK2_FREQ == 3 )
//---------- USERCLK2 same as PCLK -------------------
begin : userclk2_i1_no_bufg0
assign userclk2_1 = pclk_1;
end
else if (PCIE_USERCLK2_FREQ == PCIE_USERCLK1_FREQ )
//---------- USERCLK2 same as USERCLK1 -------------------
begin : userclk2_i1_no_bufg1
assign userclk2_1 = userclk1_1;
end
else
begin : userclk2_i1
//---------- USERCLK2 Buffer ---------------------------
BUFG usrclk2_i1
(
//---------- Input ---------------------------------
.I (userclk2),
//---------- Output --------------------------------
.O (userclk2_1)
);
end
endgenerate
//---------- Generate OOBCLK Buffer --------------------------------------------
generate if (PCIE_OOBCLK_MODE == 2)
begin : oobclk_i1
//---------- OOBCLK Buffer -----------------------------
BUFG oobclk_i1
(
//---------- Input ---------------------------------
.I (oobclk),
//---------- Output --------------------------------
.O (CLK_OOBCLK)
);
end
else
//---------- Disable OOBCLK Buffer ---------------------
begin : oobclk_i1_disable
assign CLK_OOBCLK = pclk;
end
endgenerate
// Disabled Second Stage Buffers
assign pclk = pclk_1;
assign CLK_RXUSRCLK = pclk_1;
assign CLK_USERCLK1 = userclk1_1;
assign CLK_USERCLK2 = userclk2_1;
//---------- Select PCLK -------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel <= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_reg2)
pclk_sel <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_reg2))
pclk_sel <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel <= pclk_sel;
end
end
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel_slave<= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_slave_reg2)
pclk_sel_slave <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_slave_reg2))
pclk_sel_slave <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel_slave <= pclk_sel_slave;
end
end
//---------- PIPE Clock Output -------------------------------------------------
assign CLK_PCLK = pclk;
assign CLK_MMCM_LOCK = mmcm_lock;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.2
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module dut_dmul_64ns_64ns_64_6_max_dsp
#(parameter
ID = 1,
NUM_STAGE = 6,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
dut_ap_dmul_4_max_dsp dut_ap_dmul_4_max_dsp_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:39:13 09/04/2015
// Design Name:
// Module Name: First_Phase_M
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module First_Phase_M
//SINGLE PRECISION PARAMETERS
# (parameter W = 32)
//DOUBLE PRECISION PARAMETERS
/*# (parameter W = 64) */
(
input wire clk, //system clock
input wire rst, //module reset
input wire load, //load signal
input wire [W-1:0] Data_MX, //Data X and Y are the operands
input wire [W-1:0] Data_MY,
output wire [W-1:0] Op_MX, //Both Op signals are the outputs
output wire [W-1:0] Op_MY
);
//Module's Body
//Both registers could be set with the parameter signal
//to be 32 or 64 bitwidth
RegisterMult #(.W(W)) XMRegister ( //Data X input register
.clk(clk),
.rst(rst),
.load(load),
.D(Data_MX),
.Q(Op_MX)
);
RegisterMult #(.W(W)) YMRegister ( //Data Y input register
.clk(clk),
.rst(rst),
.load(load),
.D(Data_MY),
.Q(Op_MY)
);
endmodule
|
//
// lfsr128.v -- a linear feedback shift register with 128 bits
// (actually constructed from 4 instances of a 32-bit lfsr)
//
`include "../../src/fpga/LogicProbe.v"
`timescale 1ns/1ns
module lfsr128(clk, reset_in_n, s, rs232_txd);
input clk;
input reset_in_n;
output [3:0] s;
output rs232_txd;
wire reset;
reg [3:0] reset_counter;
reg [31:0] lfsr0;
reg [31:0] lfsr1;
reg [31:0] lfsr2;
reg [31:0] lfsr3;
wire trigger;
wire sample;
wire [127:0] log_data;
assign reset = (reset_counter == 4'hF) ? 0 : 1;
always @(posedge clk) begin
if (reset_in_n == 0) begin
reset_counter <= 4'h0;
end else begin
if (reset_counter != 4'hF) begin
reset_counter <= reset_counter + 1;
end
end
end
always @(posedge clk) begin
if (reset == 1) begin
lfsr0 <= 32'hC70337DB;
lfsr1 <= 32'h7F4D514F;
lfsr2 <= 32'h75377599;
lfsr3 <= 32'h7D5937A3;
end else begin
if (lfsr0[0] == 0) begin
lfsr0 <= lfsr0 >> 1;
end else begin
lfsr0 <= (lfsr0 >> 1) ^ 32'hD0000001;
end
if (lfsr1[0] == 0) begin
lfsr1 <= lfsr1 >> 1;
end else begin
lfsr1 <= (lfsr1 >> 1) ^ 32'hD0000001;
end
if (lfsr2[0] == 0) begin
lfsr2 <= lfsr2 >> 1;
end else begin
lfsr2 <= (lfsr2 >> 1) ^ 32'hD0000001;
end
if (lfsr3[0] == 0) begin
lfsr3 <= lfsr3 >> 1;
end else begin
lfsr3 <= (lfsr3 >> 1) ^ 32'hD0000001;
end
end
end
assign s[3] = lfsr0[27];
assign s[2] = lfsr1[13];
assign s[1] = lfsr2[23];
assign s[0] = lfsr3[11];
assign trigger = (lfsr0 == 32'h7119C0CD) ? 1 : 0;
assign sample = 1;
assign log_data = { lfsr0, lfsr1, lfsr2, lfsr3 };
LogicProbe lp(clk, reset, trigger, sample, log_data, rs232_txd);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_TB_V
`define SKY130_FD_SC_MS__AND2_TB_V
/**
* and2: 2-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__and2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_TB_V
|
module elsif_test();
`define DEFINED
integer i;
initial begin
i = 0;
`ifdef DEFINED
`ifdef DEFINED
i = i + 1;
`elsif DEFINED
i = 100;
`else
i = 110;
`endif
`elsif DEFINED
`ifdef DEFINED
i = 120;
`elsif DEFINED
i = 130;
`else
i = 140;
`endif
`else
`ifdef DEFINED
i = 150;
`elsif DEFINED
i = 160;
`else
i = 170;
`endif
`endif
`ifdef UNDEFINED
`ifdef DEFINED
i = 200;
`elsif DEFINED
i = 210;
`else
i = 220;
`endif
`elsif DEFINED
`ifdef UNDEFINED
i = 230;
`elsif DEFINED
i = i + 1;
`else
i = 240;
`endif
`else
`ifdef UNDEFINED
i = 250;
`elsif DEFINED
i = 260;
`else
i = 270;
`endif
`endif
`ifdef UNDEFINED
`ifdef UNDEFINED
i = 300;
`elsif UNDEFINED
i = 310;
`else
i = 320;
`endif
`elsif UNDEFINED
`ifdef UNDEFINED
i = 330;
`elsif UNDEFINED
i = 340;
`else
i = 350;
`endif
`else
`ifdef UNDEFINED
i = 360;
`elsif UNDEFINED
i = 370;
`else
i = i + 1;
`endif
`endif
if (i == 3)
$display("PASSED");
else
$display("Test FAILED: %d", i);
end
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
module test_fg_bd_fifo;
// Parameters
parameter ADDR_WIDTH = 10;
parameter DEST_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_bd_valid = 0;
reg [7:0] input_bd_dest = 0;
reg [31:0] input_bd_burst_len = 0;
reg output_bd_ready = 0;
// Outputs
wire input_bd_ready;
wire output_bd_valid;
wire [7:0] output_bd_dest;
wire [31:0] output_bd_burst_len;
wire [ADDR_WIDTH-1:0] count;
wire [ADDR_WIDTH+32-1:0] byte_count;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_bd_valid,
input_bd_dest,
input_bd_burst_len,
output_bd_ready);
$to_myhdl(input_bd_ready,
output_bd_valid,
output_bd_dest,
output_bd_burst_len,
count,
byte_count);
// dump file
$dumpfile("test_fg_bd_fifo.lxt");
$dumpvars(0, test_fg_bd_fifo);
end
fg_bd_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEST_WIDTH(DEST_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// burst descriptor input
.input_bd_valid(input_bd_valid),
.input_bd_ready(input_bd_ready),
.input_bd_dest(input_bd_dest),
.input_bd_burst_len(input_bd_burst_len),
// burst descriptor output
.output_bd_valid(output_bd_valid),
.output_bd_ready(output_bd_ready),
.output_bd_dest(output_bd_dest),
.output_bd_burst_len(output_bd_burst_len),
// status
.count(count),
.byte_count(byte_count)
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_regc.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_regc(
rstn,
sw_clk,
/* Goes to port 0 of REG */
reg_rd_req_port0,
reg_rd_dv_port0,
reg_rd_addr_port0,
reg_rd_data_port0,
reg_rd_bytes_port0,
reg_rd_qos_port0,
/* Goes to port 1 of REG */
reg_rd_req_port1,
reg_rd_dv_port1,
reg_rd_addr_port1,
reg_rd_data_port1,
reg_rd_bytes_port1,
reg_rd_qos_port1
);
input rstn;
input sw_clk;
input reg_rd_req_port0;
output reg_rd_dv_port0;
input[31:0] reg_rd_addr_port0;
output[1023:0] reg_rd_data_port0;
input[7:0] reg_rd_bytes_port0;
input [3:0] reg_rd_qos_port0;
input reg_rd_req_port1;
output reg_rd_dv_port1;
input[31:0] reg_rd_addr_port1;
output[1023:0] reg_rd_data_port1;
input[7:0] reg_rd_bytes_port1;
input[3:0] reg_rd_qos_port1;
wire [3:0] rd_qos;
reg [1023:0] rd_data;
wire [31:0] rd_addr;
wire [7:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_rd reg_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(reg_rd_qos_port0),
.qos2(reg_rd_qos_port1),
.prt_req1(reg_rd_req_port0),
.prt_req2(reg_rd_req_port1),
.prt_data1(reg_rd_data_port0),
.prt_data2(reg_rd_data_port1),
.prt_addr1(reg_rd_addr_port0),
.prt_addr2(reg_rd_addr_port1),
.prt_bytes1(reg_rd_bytes_port0),
.prt_bytes2(reg_rd_bytes_port1),
.prt_dv1(reg_rd_dv_port0),
.prt_dv2(reg_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_reg_map regm();
reg state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
rd_dv <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
rd_dv <= 0;
if(rd_req) begin
regm.read_reg_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [7:0] a;
reg [6:-1] b;
initial begin
a = 1;
b = 2;
if (a !== 8'h01) begin
$display("FAILED -- to initialize a: %b", a);
$finish;
end
if (b !== 8'h02) begin
$display("FAILED -- to initialize b: %b", b);
$finish;
end
b = a;
if (b !== 8'h01) begin
$display("FAILED -- to copy a to b: %b", b);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_prp_rx_tag # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_tag_alloc,
input [7:0] pcie_alloc_tag,
input [5:4] pcie_tag_alloc_len,
output pcie_tag_full_n,
input [7:0] cpld_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
input cpld_fifo_wr_en,
input cpld_fifo_tag_last,
output fifo_wr_en,
output [P_FIFO_DEPTH_WIDTH-1:0] fifo_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] fifo_wr_data,
output [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
output [P_FIFO_DEPTH_WIDTH:0] rear_addr
);
localparam LP_PCIE_TAG_PREFIX = 5'b00001;
localparam LP_PCIE_TAG_WITDH = 3;
localparam LP_NUM_OF_PCIE_TAG = 6;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_rear;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_front;
reg [P_FIFO_DEPTH_WIDTH:0] r_alloc_base_addr;
reg [LP_PCIE_TAG_WITDH-1:0] r_pcie_tag [LP_NUM_OF_PCIE_TAG-1:0];
reg [P_FIFO_DEPTH_WIDTH:0] r_pcie_tag_addr [LP_NUM_OF_PCIE_TAG-1:0];
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg [C_PCIE_DATA_WIDTH-1:0] r_cpld_fifo_wr_data;
reg r_cpld_fifo_wr_en;
reg r_cpld_fifo_tag_last;
wire [LP_NUM_OF_PCIE_TAG-1:0] w_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_alloc_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_update_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_free_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_valid;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg [P_FIFO_DEPTH_WIDTH-1:0] r_fifo_wr_addr;
assign pcie_tag_full_n = ~((r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] ^ r_pcie_tag_front[LP_NUM_OF_PCIE_TAG])
& (r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] == r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0]));
assign fifo_wr_en = r_cpld_fifo_wr_en;
assign fifo_wr_addr = r_fifo_wr_addr;
assign fifo_wr_data = r_cpld_fifo_wr_data;
assign rear_full_addr = r_alloc_base_addr;
assign rear_addr = r_rear_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_rear <= 1;
r_alloc_base_addr <= 0;
r_pcie_tag[0] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[1] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[2] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[3] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[4] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[5] <= {LP_PCIE_TAG_WITDH{1'b1}};
end
else begin
if(pcie_tag_alloc == 1) begin
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1]};
r_alloc_base_addr <= r_alloc_base_addr + pcie_tag_alloc_len;
if(r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG];
end
if(r_pcie_tag_alloc_mask[0])
r_pcie_tag[0] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[1])
r_pcie_tag[1] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[2])
r_pcie_tag[2] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[3])
r_pcie_tag[3] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[4])
r_pcie_tag[4] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[5])
r_pcie_tag[5] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
end
end
always @ (*)
begin
if(pcie_tag_alloc == 1)
r_pcie_tag_alloc_mask <= r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0];
else
r_pcie_tag_alloc_mask <= 0;
if(cpld_fifo_wr_en == 1)
r_pcie_tag_update_mask <= w_pcie_tag_hit;
else
r_pcie_tag_update_mask <= 0;
if(r_cpld_fifo_tag_last == 1)
r_pcie_tag_invalid_mask <= r_pcie_tag_hit;
else
r_pcie_tag_invalid_mask <= 0;
r_pcie_tag_free_mask <= r_pcie_tag_valid & r_pcie_tag_invalid & r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0];
end
always @ (posedge pcie_user_clk)
begin
case({r_pcie_tag_update_mask[0], r_pcie_tag_alloc_mask[0]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[0] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[0] <= r_pcie_tag_addr[0] + 1;
endcase
case({r_pcie_tag_update_mask[1], r_pcie_tag_alloc_mask[1]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[1] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[1] <= r_pcie_tag_addr[1] + 1;
endcase
case({r_pcie_tag_update_mask[2], r_pcie_tag_alloc_mask[2]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[2] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[2] <= r_pcie_tag_addr[2] + 1;
endcase
case({r_pcie_tag_update_mask[3], r_pcie_tag_alloc_mask[3]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[3] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[3] <= r_pcie_tag_addr[3] + 1;
endcase
case({r_pcie_tag_update_mask[4], r_pcie_tag_alloc_mask[4]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[4] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[4] <= r_pcie_tag_addr[4] + 1;
endcase
case({r_pcie_tag_update_mask[5], r_pcie_tag_alloc_mask[5]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[5] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[5] <= r_pcie_tag_addr[5] + 1;
endcase
end
assign w_pcie_tag_hit[0] = (r_pcie_tag[0] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[0];
assign w_pcie_tag_hit[1] = (r_pcie_tag[1] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[1];
assign w_pcie_tag_hit[2] = (r_pcie_tag[2] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[2];
assign w_pcie_tag_hit[3] = (r_pcie_tag[3] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[3];
assign w_pcie_tag_hit[4] = (r_pcie_tag[4] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[4];
assign w_pcie_tag_hit[5] = (r_pcie_tag[5] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[5];
always @ (posedge pcie_user_clk)
begin
r_cpld_fifo_tag_last <= cpld_fifo_tag_last;
r_cpld_fifo_wr_en <= cpld_fifo_wr_en;
r_cpld_fifo_wr_data <= cpld_fifo_wr_data;
end
always @ (posedge pcie_user_clk)
begin
r_pcie_tag_hit <= w_pcie_tag_hit;
case(w_pcie_tag_hit) // synthesis parallel_case
6'b000001: r_fifo_wr_addr <= r_pcie_tag_addr[0][P_FIFO_DEPTH_WIDTH-1:0];
6'b000010: r_fifo_wr_addr <= r_pcie_tag_addr[1][P_FIFO_DEPTH_WIDTH-1:0];
6'b000100: r_fifo_wr_addr <= r_pcie_tag_addr[2][P_FIFO_DEPTH_WIDTH-1:0];
6'b001000: r_fifo_wr_addr <= r_pcie_tag_addr[3][P_FIFO_DEPTH_WIDTH-1:0];
6'b010000: r_fifo_wr_addr <= r_pcie_tag_addr[4][P_FIFO_DEPTH_WIDTH-1:0];
6'b100000: r_fifo_wr_addr <= r_pcie_tag_addr[5][P_FIFO_DEPTH_WIDTH-1:0];
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_front <= 1;
r_rear_addr <= 0;
r_pcie_tag_valid <= 0;
r_pcie_tag_invalid <= 0;
end
else begin
r_pcie_tag_valid <= (r_pcie_tag_valid | r_pcie_tag_alloc_mask) & ~r_pcie_tag_free_mask;
r_pcie_tag_invalid <= (r_pcie_tag_invalid | r_pcie_tag_invalid_mask) & ~r_pcie_tag_free_mask;
if(r_pcie_tag_free_mask != 0) begin
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1]};
if(r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_front[LP_NUM_OF_PCIE_TAG];
end
case(r_pcie_tag_free_mask) // synthesis parallel_case
6'b000001: r_rear_addr <= r_pcie_tag_addr[0];
6'b000010: r_rear_addr <= r_pcie_tag_addr[1];
6'b000100: r_rear_addr <= r_pcie_tag_addr[2];
6'b001000: r_rear_addr <= r_pcie_tag_addr[3];
6'b010000: r_rear_addr <= r_pcie_tag_addr[4];
6'b100000: r_rear_addr <= r_pcie_tag_addr[5];
endcase
end
end
endmodule
|
//==========================================
// Function : Code Gray counter.
// Coder : Alex Claros F.
// Date : 15/May/2005.
//=======================================
`timescale 1ns/1ps
module vgafb_graycounter
#(parameter COUNTER_WIDTH = 2)
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] BinaryCount;
/////////Code///////////////////////
always @ (posedge Clk)
if (Clear_in) begin
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
end
else if (Enable_in) begin
BinaryCount <= BinaryCount + 1;
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's 32x32 multiply for ASIC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// 32x32 multiply for ASIC ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`ifdef OR1200_ASIC_MULTP2_32X32
module PP_LOW ( ONEPOS, ONENEG, TWONEG, INA, INB, PPBIT );
input ONEPOS;
input ONENEG;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = (ONEPOS & INA) | (ONENEG & INB) | TWONEG;
endmodule
module PP_MIDDLE ( ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, INC, IND, PPBIT );
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
input INC;
input IND;
output PPBIT;
assign PPBIT = ~ (( ~ (INA & TWOPOS)) & ( ~ (INB & TWONEG)) & ( ~ (INC & ONEPOS)) & ( ~ (IND & ONENEG)));
endmodule
module PP_HIGH ( ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, PPBIT );
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = ~ ((INA & ONEPOS) | (INB & ONENEG) | (INA & TWOPOS) | (INB & TWONEG));
endmodule
module R_GATE ( INA, INB, INC, PPBIT );
input INA;
input INB;
input INC;
output PPBIT;
assign PPBIT = ( ~ (INA & INB)) & INC;
endmodule
module DECODER ( INA, INB, INC, TWOPOS, TWONEG, ONEPOS, ONENEG );
input INA;
input INB;
input INC;
output TWOPOS;
output TWONEG;
output ONEPOS;
output ONENEG;
assign TWOPOS = ~ ( ~ (INA & INB & ( ~ INC)));
assign TWONEG = ~ ( ~ (( ~ INA) & ( ~ INB) & INC));
assign ONEPOS = (( ~ INA) & INB & ( ~ INC)) | (( ~ INC) & ( ~ INB) & INA);
assign ONENEG = (INA & ( ~ INB) & INC) | (INC & INB & ( ~ INA));
endmodule
module BOOTHCODER_33_32 ( OPA, OPB, SUMMAND );
input [0:32] OPA;
input [0:31] OPB;
output [0:575] SUMMAND;
wire [0:32] INV_MULTIPLICAND;
wire [0:63] INT_MULTIPLIER;
wire LOGIC_ONE, LOGIC_ZERO;
assign LOGIC_ONE = 1;
assign LOGIC_ZERO = 0;
DECODER DEC_0 (.INA (LOGIC_ZERO) , .INB (OPB[0]) , .INC (OPB[1]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) );
assign INV_MULTIPLICAND[0] = ~ OPA[0];
PP_LOW PPL_0 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[0]) );
R_GATE RGATE_0 (.INA (LOGIC_ZERO) , .INB (OPB[0]) , .INC (OPB[1]) , .PPBIT (SUMMAND[1]) );
assign INV_MULTIPLICAND[1] = ~ OPA[1];
PP_MIDDLE PPM_0 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[2]) );
assign INV_MULTIPLICAND[2] = ~ OPA[2];
PP_MIDDLE PPM_1 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[3]) );
assign INV_MULTIPLICAND[3] = ~ OPA[3];
PP_MIDDLE PPM_2 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[6]) );
assign INV_MULTIPLICAND[4] = ~ OPA[4];
PP_MIDDLE PPM_3 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[8]) );
assign INV_MULTIPLICAND[5] = ~ OPA[5];
PP_MIDDLE PPM_4 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[12]) );
assign INV_MULTIPLICAND[6] = ~ OPA[6];
PP_MIDDLE PPM_5 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[15]) );
assign INV_MULTIPLICAND[7] = ~ OPA[7];
PP_MIDDLE PPM_6 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[20]) );
assign INV_MULTIPLICAND[8] = ~ OPA[8];
PP_MIDDLE PPM_7 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[24]) );
assign INV_MULTIPLICAND[9] = ~ OPA[9];
PP_MIDDLE PPM_8 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[30]) );
assign INV_MULTIPLICAND[10] = ~ OPA[10];
PP_MIDDLE PPM_9 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[35]) );
assign INV_MULTIPLICAND[11] = ~ OPA[11];
PP_MIDDLE PPM_10 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[42]) );
assign INV_MULTIPLICAND[12] = ~ OPA[12];
PP_MIDDLE PPM_11 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[48]) );
assign INV_MULTIPLICAND[13] = ~ OPA[13];
PP_MIDDLE PPM_12 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[56]) );
assign INV_MULTIPLICAND[14] = ~ OPA[14];
PP_MIDDLE PPM_13 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[63]) );
assign INV_MULTIPLICAND[15] = ~ OPA[15];
PP_MIDDLE PPM_14 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[72]) );
assign INV_MULTIPLICAND[16] = ~ OPA[16];
PP_MIDDLE PPM_15 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[80]) );
assign INV_MULTIPLICAND[17] = ~ OPA[17];
PP_MIDDLE PPM_16 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[90]) );
assign INV_MULTIPLICAND[18] = ~ OPA[18];
PP_MIDDLE PPM_17 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[99]) );
assign INV_MULTIPLICAND[19] = ~ OPA[19];
PP_MIDDLE PPM_18 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[110]) );
assign INV_MULTIPLICAND[20] = ~ OPA[20];
PP_MIDDLE PPM_19 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[120]) );
assign INV_MULTIPLICAND[21] = ~ OPA[21];
PP_MIDDLE PPM_20 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[132]) );
assign INV_MULTIPLICAND[22] = ~ OPA[22];
PP_MIDDLE PPM_21 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[143]) );
assign INV_MULTIPLICAND[23] = ~ OPA[23];
PP_MIDDLE PPM_22 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[156]) );
assign INV_MULTIPLICAND[24] = ~ OPA[24];
PP_MIDDLE PPM_23 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[168]) );
assign INV_MULTIPLICAND[25] = ~ OPA[25];
PP_MIDDLE PPM_24 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[182]) );
assign INV_MULTIPLICAND[26] = ~ OPA[26];
PP_MIDDLE PPM_25 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[195]) );
assign INV_MULTIPLICAND[27] = ~ OPA[27];
PP_MIDDLE PPM_26 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[210]) );
assign INV_MULTIPLICAND[28] = ~ OPA[28];
PP_MIDDLE PPM_27 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[224]) );
assign INV_MULTIPLICAND[29] = ~ OPA[29];
PP_MIDDLE PPM_28 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[240]) );
assign INV_MULTIPLICAND[30] = ~ OPA[30];
PP_MIDDLE PPM_29 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[255]) );
assign INV_MULTIPLICAND[31] = ~ OPA[31];
PP_MIDDLE PPM_30 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[272]) );
assign INV_MULTIPLICAND[32] = ~ OPA[32];
PP_MIDDLE PPM_31 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[288]) );
PP_HIGH PPH_0 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[304]) );
assign SUMMAND[305] = 1;
DECODER DEC_1 (.INA (OPB[1]) , .INB (OPB[2]) , .INC (OPB[3]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) );
PP_LOW PPL_1 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[4]) );
R_GATE RGATE_1 (.INA (OPB[1]) , .INB (OPB[2]) , .INC (OPB[3]) , .PPBIT (SUMMAND[5]) );
PP_MIDDLE PPM_32 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[7]) );
PP_MIDDLE PPM_33 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[9]) );
PP_MIDDLE PPM_34 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[13]) );
PP_MIDDLE PPM_35 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[16]) );
PP_MIDDLE PPM_36 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[21]) );
PP_MIDDLE PPM_37 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[25]) );
PP_MIDDLE PPM_38 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[31]) );
PP_MIDDLE PPM_39 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[36]) );
PP_MIDDLE PPM_40 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[43]) );
PP_MIDDLE PPM_41 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[49]) );
PP_MIDDLE PPM_42 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[57]) );
PP_MIDDLE PPM_43 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[64]) );
PP_MIDDLE PPM_44 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[73]) );
PP_MIDDLE PPM_45 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[81]) );
PP_MIDDLE PPM_46 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[91]) );
PP_MIDDLE PPM_47 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[100]) );
PP_MIDDLE PPM_48 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[111]) );
PP_MIDDLE PPM_49 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[121]) );
PP_MIDDLE PPM_50 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[133]) );
PP_MIDDLE PPM_51 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[144]) );
PP_MIDDLE PPM_52 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[157]) );
PP_MIDDLE PPM_53 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[169]) );
PP_MIDDLE PPM_54 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[183]) );
PP_MIDDLE PPM_55 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[196]) );
PP_MIDDLE PPM_56 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[211]) );
PP_MIDDLE PPM_57 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[225]) );
PP_MIDDLE PPM_58 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[241]) );
PP_MIDDLE PPM_59 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[256]) );
PP_MIDDLE PPM_60 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[273]) );
PP_MIDDLE PPM_61 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[289]) );
PP_MIDDLE PPM_62 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[306]) );
PP_MIDDLE PPM_63 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[321]) );
assign SUMMAND[322] = LOGIC_ONE;
PP_HIGH PPH_1 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[337]) );
DECODER DEC_2 (.INA (OPB[3]) , .INB (OPB[4]) , .INC (OPB[5]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) );
PP_LOW PPL_2 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[10]) );
R_GATE RGATE_2 (.INA (OPB[3]) , .INB (OPB[4]) , .INC (OPB[5]) , .PPBIT (SUMMAND[11]) );
PP_MIDDLE PPM_64 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[14]) );
PP_MIDDLE PPM_65 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[17]) );
PP_MIDDLE PPM_66 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[22]) );
PP_MIDDLE PPM_67 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[26]) );
PP_MIDDLE PPM_68 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[32]) );
PP_MIDDLE PPM_69 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[37]) );
PP_MIDDLE PPM_70 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[44]) );
PP_MIDDLE PPM_71 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[50]) );
PP_MIDDLE PPM_72 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[58]) );
PP_MIDDLE PPM_73 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[65]) );
PP_MIDDLE PPM_74 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[74]) );
PP_MIDDLE PPM_75 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[82]) );
PP_MIDDLE PPM_76 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[92]) );
PP_MIDDLE PPM_77 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[101]) );
PP_MIDDLE PPM_78 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[112]) );
PP_MIDDLE PPM_79 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[122]) );
PP_MIDDLE PPM_80 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[134]) );
PP_MIDDLE PPM_81 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[145]) );
PP_MIDDLE PPM_82 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[158]) );
PP_MIDDLE PPM_83 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[170]) );
PP_MIDDLE PPM_84 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[184]) );
PP_MIDDLE PPM_85 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[197]) );
PP_MIDDLE PPM_86 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[212]) );
PP_MIDDLE PPM_87 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[226]) );
PP_MIDDLE PPM_88 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[242]) );
PP_MIDDLE PPM_89 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[257]) );
PP_MIDDLE PPM_90 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[274]) );
PP_MIDDLE PPM_91 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[290]) );
PP_MIDDLE PPM_92 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[307]) );
PP_MIDDLE PPM_93 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[323]) );
PP_MIDDLE PPM_94 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[338]) );
PP_MIDDLE PPM_95 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[352]) );
assign SUMMAND[353] = LOGIC_ONE;
PP_HIGH PPH_2 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[367]) );
DECODER DEC_3 (.INA (OPB[5]) , .INB (OPB[6]) , .INC (OPB[7]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) );
PP_LOW PPL_3 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[18]) );
R_GATE RGATE_3 (.INA (OPB[5]) , .INB (OPB[6]) , .INC (OPB[7]) , .PPBIT (SUMMAND[19]) );
PP_MIDDLE PPM_96 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[23]) );
PP_MIDDLE PPM_97 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[27]) );
PP_MIDDLE PPM_98 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[33]) );
PP_MIDDLE PPM_99 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[38]) );
PP_MIDDLE PPM_100 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[45]) );
PP_MIDDLE PPM_101 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[51]) );
PP_MIDDLE PPM_102 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[59]) );
PP_MIDDLE PPM_103 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[66]) );
PP_MIDDLE PPM_104 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[75]) );
PP_MIDDLE PPM_105 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[83]) );
PP_MIDDLE PPM_106 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[93]) );
PP_MIDDLE PPM_107 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[102]) );
PP_MIDDLE PPM_108 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[113]) );
PP_MIDDLE PPM_109 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[123]) );
PP_MIDDLE PPM_110 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[135]) );
PP_MIDDLE PPM_111 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[146]) );
PP_MIDDLE PPM_112 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[159]) );
PP_MIDDLE PPM_113 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[171]) );
PP_MIDDLE PPM_114 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[185]) );
PP_MIDDLE PPM_115 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[198]) );
PP_MIDDLE PPM_116 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[213]) );
PP_MIDDLE PPM_117 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[227]) );
PP_MIDDLE PPM_118 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[243]) );
PP_MIDDLE PPM_119 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[258]) );
PP_MIDDLE PPM_120 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[275]) );
PP_MIDDLE PPM_121 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[291]) );
PP_MIDDLE PPM_122 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[308]) );
PP_MIDDLE PPM_123 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[324]) );
PP_MIDDLE PPM_124 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[339]) );
PP_MIDDLE PPM_125 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[354]) );
PP_MIDDLE PPM_126 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[368]) );
PP_MIDDLE PPM_127 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[381]) );
assign SUMMAND[382] = LOGIC_ONE;
PP_HIGH PPH_3 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[395]) );
DECODER DEC_4 (.INA (OPB[7]) , .INB (OPB[8]) , .INC (OPB[9]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) );
PP_LOW PPL_4 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[28]) );
R_GATE RGATE_4 (.INA (OPB[7]) , .INB (OPB[8]) , .INC (OPB[9]) , .PPBIT (SUMMAND[29]) );
PP_MIDDLE PPM_128 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[34]) );
PP_MIDDLE PPM_129 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[39]) );
PP_MIDDLE PPM_130 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[46]) );
PP_MIDDLE PPM_131 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[52]) );
PP_MIDDLE PPM_132 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[60]) );
PP_MIDDLE PPM_133 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[67]) );
PP_MIDDLE PPM_134 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[76]) );
PP_MIDDLE PPM_135 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[84]) );
PP_MIDDLE PPM_136 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[94]) );
PP_MIDDLE PPM_137 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[103]) );
PP_MIDDLE PPM_138 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[114]) );
PP_MIDDLE PPM_139 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[124]) );
PP_MIDDLE PPM_140 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[136]) );
PP_MIDDLE PPM_141 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[147]) );
PP_MIDDLE PPM_142 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[160]) );
PP_MIDDLE PPM_143 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[172]) );
PP_MIDDLE PPM_144 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[186]) );
PP_MIDDLE PPM_145 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[199]) );
PP_MIDDLE PPM_146 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[214]) );
PP_MIDDLE PPM_147 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[228]) );
PP_MIDDLE PPM_148 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[244]) );
PP_MIDDLE PPM_149 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[259]) );
PP_MIDDLE PPM_150 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[276]) );
PP_MIDDLE PPM_151 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[292]) );
PP_MIDDLE PPM_152 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[309]) );
PP_MIDDLE PPM_153 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[325]) );
PP_MIDDLE PPM_154 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[340]) );
PP_MIDDLE PPM_155 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[355]) );
PP_MIDDLE PPM_156 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[369]) );
PP_MIDDLE PPM_157 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[383]) );
PP_MIDDLE PPM_158 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[396]) );
PP_MIDDLE PPM_159 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[408]) );
assign SUMMAND[409] = LOGIC_ONE;
PP_HIGH PPH_4 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[421]) );
DECODER DEC_5 (.INA (OPB[9]) , .INB (OPB[10]) , .INC (OPB[11]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) );
PP_LOW PPL_5 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[40]) );
R_GATE RGATE_5 (.INA (OPB[9]) , .INB (OPB[10]) , .INC (OPB[11]) , .PPBIT (SUMMAND[41]) );
PP_MIDDLE PPM_160 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[47]) );
PP_MIDDLE PPM_161 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[53]) );
PP_MIDDLE PPM_162 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[61]) );
PP_MIDDLE PPM_163 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[68]) );
PP_MIDDLE PPM_164 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[77]) );
PP_MIDDLE PPM_165 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[85]) );
PP_MIDDLE PPM_166 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[95]) );
PP_MIDDLE PPM_167 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[104]) );
PP_MIDDLE PPM_168 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[115]) );
PP_MIDDLE PPM_169 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[125]) );
PP_MIDDLE PPM_170 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[137]) );
PP_MIDDLE PPM_171 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[148]) );
PP_MIDDLE PPM_172 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[161]) );
PP_MIDDLE PPM_173 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[173]) );
PP_MIDDLE PPM_174 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[187]) );
PP_MIDDLE PPM_175 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[200]) );
PP_MIDDLE PPM_176 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[215]) );
PP_MIDDLE PPM_177 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[229]) );
PP_MIDDLE PPM_178 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[245]) );
PP_MIDDLE PPM_179 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[260]) );
PP_MIDDLE PPM_180 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[277]) );
PP_MIDDLE PPM_181 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[293]) );
PP_MIDDLE PPM_182 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[310]) );
PP_MIDDLE PPM_183 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[326]) );
PP_MIDDLE PPM_184 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[341]) );
PP_MIDDLE PPM_185 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[356]) );
PP_MIDDLE PPM_186 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[370]) );
PP_MIDDLE PPM_187 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[384]) );
PP_MIDDLE PPM_188 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[397]) );
PP_MIDDLE PPM_189 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[410]) );
PP_MIDDLE PPM_190 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[422]) );
PP_MIDDLE PPM_191 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[433]) );
assign SUMMAND[434] = LOGIC_ONE;
PP_HIGH PPH_5 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[445]) );
DECODER DEC_6 (.INA (OPB[11]) , .INB (OPB[12]) , .INC (OPB[13]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) );
PP_LOW PPL_6 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[54]) );
R_GATE RGATE_6 (.INA (OPB[11]) , .INB (OPB[12]) , .INC (OPB[13]) , .PPBIT (SUMMAND[55]) );
PP_MIDDLE PPM_192 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[62]) );
PP_MIDDLE PPM_193 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[69]) );
PP_MIDDLE PPM_194 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[78]) );
PP_MIDDLE PPM_195 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[86]) );
PP_MIDDLE PPM_196 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[96]) );
PP_MIDDLE PPM_197 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[105]) );
PP_MIDDLE PPM_198 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[116]) );
PP_MIDDLE PPM_199 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[126]) );
PP_MIDDLE PPM_200 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[138]) );
PP_MIDDLE PPM_201 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[149]) );
PP_MIDDLE PPM_202 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[162]) );
PP_MIDDLE PPM_203 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[174]) );
PP_MIDDLE PPM_204 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[188]) );
PP_MIDDLE PPM_205 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[201]) );
PP_MIDDLE PPM_206 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[216]) );
PP_MIDDLE PPM_207 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[230]) );
PP_MIDDLE PPM_208 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[246]) );
PP_MIDDLE PPM_209 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[261]) );
PP_MIDDLE PPM_210 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[278]) );
PP_MIDDLE PPM_211 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[294]) );
PP_MIDDLE PPM_212 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[311]) );
PP_MIDDLE PPM_213 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[327]) );
PP_MIDDLE PPM_214 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[342]) );
PP_MIDDLE PPM_215 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[357]) );
PP_MIDDLE PPM_216 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[371]) );
PP_MIDDLE PPM_217 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[385]) );
PP_MIDDLE PPM_218 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[398]) );
PP_MIDDLE PPM_219 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[411]) );
PP_MIDDLE PPM_220 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[423]) );
PP_MIDDLE PPM_221 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[435]) );
PP_MIDDLE PPM_222 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[446]) );
PP_MIDDLE PPM_223 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[456]) );
assign SUMMAND[457] = LOGIC_ONE;
PP_HIGH PPH_6 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[467]) );
DECODER DEC_7 (.INA (OPB[13]) , .INB (OPB[14]) , .INC (OPB[15]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) );
PP_LOW PPL_7 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[70]) );
R_GATE RGATE_7 (.INA (OPB[13]) , .INB (OPB[14]) , .INC (OPB[15]) , .PPBIT (SUMMAND[71]) );
PP_MIDDLE PPM_224 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[79]) );
PP_MIDDLE PPM_225 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[87]) );
PP_MIDDLE PPM_226 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[97]) );
PP_MIDDLE PPM_227 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[106]) );
PP_MIDDLE PPM_228 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[117]) );
PP_MIDDLE PPM_229 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[127]) );
PP_MIDDLE PPM_230 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[139]) );
PP_MIDDLE PPM_231 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[150]) );
PP_MIDDLE PPM_232 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[163]) );
PP_MIDDLE PPM_233 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[175]) );
PP_MIDDLE PPM_234 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[189]) );
PP_MIDDLE PPM_235 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[202]) );
PP_MIDDLE PPM_236 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[217]) );
PP_MIDDLE PPM_237 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[231]) );
PP_MIDDLE PPM_238 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[247]) );
PP_MIDDLE PPM_239 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[262]) );
PP_MIDDLE PPM_240 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[279]) );
PP_MIDDLE PPM_241 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[295]) );
PP_MIDDLE PPM_242 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[312]) );
PP_MIDDLE PPM_243 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[328]) );
PP_MIDDLE PPM_244 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[343]) );
PP_MIDDLE PPM_245 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[358]) );
PP_MIDDLE PPM_246 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[372]) );
PP_MIDDLE PPM_247 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[386]) );
PP_MIDDLE PPM_248 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[399]) );
PP_MIDDLE PPM_249 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[412]) );
PP_MIDDLE PPM_250 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[424]) );
PP_MIDDLE PPM_251 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[436]) );
PP_MIDDLE PPM_252 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[447]) );
PP_MIDDLE PPM_253 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[458]) );
PP_MIDDLE PPM_254 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[468]) );
PP_MIDDLE PPM_255 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[477]) );
assign SUMMAND[478] = LOGIC_ONE;
PP_HIGH PPH_7 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[487]) );
DECODER DEC_8 (.INA (OPB[15]) , .INB (OPB[16]) , .INC (OPB[17]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) );
PP_LOW PPL_8 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[88]) );
R_GATE RGATE_8 (.INA (OPB[15]) , .INB (OPB[16]) , .INC (OPB[17]) , .PPBIT (SUMMAND[89]) );
PP_MIDDLE PPM_256 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[98]) );
PP_MIDDLE PPM_257 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[107]) );
PP_MIDDLE PPM_258 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[118]) );
PP_MIDDLE PPM_259 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[128]) );
PP_MIDDLE PPM_260 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[140]) );
PP_MIDDLE PPM_261 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[151]) );
PP_MIDDLE PPM_262 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[164]) );
PP_MIDDLE PPM_263 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[176]) );
PP_MIDDLE PPM_264 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[190]) );
PP_MIDDLE PPM_265 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[203]) );
PP_MIDDLE PPM_266 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[218]) );
PP_MIDDLE PPM_267 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[232]) );
PP_MIDDLE PPM_268 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[248]) );
PP_MIDDLE PPM_269 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[263]) );
PP_MIDDLE PPM_270 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[280]) );
PP_MIDDLE PPM_271 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[296]) );
PP_MIDDLE PPM_272 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[313]) );
PP_MIDDLE PPM_273 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[329]) );
PP_MIDDLE PPM_274 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[344]) );
PP_MIDDLE PPM_275 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[359]) );
PP_MIDDLE PPM_276 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[373]) );
PP_MIDDLE PPM_277 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[387]) );
PP_MIDDLE PPM_278 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[400]) );
PP_MIDDLE PPM_279 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[413]) );
PP_MIDDLE PPM_280 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[425]) );
PP_MIDDLE PPM_281 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[437]) );
PP_MIDDLE PPM_282 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[448]) );
PP_MIDDLE PPM_283 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[459]) );
PP_MIDDLE PPM_284 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[469]) );
PP_MIDDLE PPM_285 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[479]) );
PP_MIDDLE PPM_286 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[488]) );
PP_MIDDLE PPM_287 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[496]) );
assign SUMMAND[497] = LOGIC_ONE;
PP_HIGH PPH_8 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[505]) );
DECODER DEC_9 (.INA (OPB[17]) , .INB (OPB[18]) , .INC (OPB[19]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) );
PP_LOW PPL_9 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[108]) );
R_GATE RGATE_9 (.INA (OPB[17]) , .INB (OPB[18]) , .INC (OPB[19]) , .PPBIT (SUMMAND[109]) );
PP_MIDDLE PPM_288 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[119]) );
PP_MIDDLE PPM_289 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[129]) );
PP_MIDDLE PPM_290 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[141]) );
PP_MIDDLE PPM_291 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[152]) );
PP_MIDDLE PPM_292 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[165]) );
PP_MIDDLE PPM_293 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[177]) );
PP_MIDDLE PPM_294 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[191]) );
PP_MIDDLE PPM_295 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[204]) );
PP_MIDDLE PPM_296 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[219]) );
PP_MIDDLE PPM_297 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[233]) );
PP_MIDDLE PPM_298 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[249]) );
PP_MIDDLE PPM_299 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[264]) );
PP_MIDDLE PPM_300 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[281]) );
PP_MIDDLE PPM_301 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[297]) );
PP_MIDDLE PPM_302 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[314]) );
PP_MIDDLE PPM_303 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[330]) );
PP_MIDDLE PPM_304 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[345]) );
PP_MIDDLE PPM_305 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[360]) );
PP_MIDDLE PPM_306 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[374]) );
PP_MIDDLE PPM_307 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[388]) );
PP_MIDDLE PPM_308 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[401]) );
PP_MIDDLE PPM_309 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[414]) );
PP_MIDDLE PPM_310 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[426]) );
PP_MIDDLE PPM_311 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[438]) );
PP_MIDDLE PPM_312 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[449]) );
PP_MIDDLE PPM_313 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[460]) );
PP_MIDDLE PPM_314 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[470]) );
PP_MIDDLE PPM_315 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[480]) );
PP_MIDDLE PPM_316 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[489]) );
PP_MIDDLE PPM_317 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[498]) );
PP_MIDDLE PPM_318 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[506]) );
PP_MIDDLE PPM_319 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[513]) );
assign SUMMAND[514] = LOGIC_ONE;
PP_HIGH PPH_9 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[521]) );
DECODER DEC_10 (.INA (OPB[19]) , .INB (OPB[20]) , .INC (OPB[21]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) );
PP_LOW PPL_10 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[130]) );
R_GATE RGATE_10 (.INA (OPB[19]) , .INB (OPB[20]) , .INC (OPB[21]) , .PPBIT (SUMMAND[131]) );
PP_MIDDLE PPM_320 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[142]) );
PP_MIDDLE PPM_321 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[153]) );
PP_MIDDLE PPM_322 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[166]) );
PP_MIDDLE PPM_323 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[178]) );
PP_MIDDLE PPM_324 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[192]) );
PP_MIDDLE PPM_325 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[205]) );
PP_MIDDLE PPM_326 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[220]) );
PP_MIDDLE PPM_327 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[234]) );
PP_MIDDLE PPM_328 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[250]) );
PP_MIDDLE PPM_329 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[265]) );
PP_MIDDLE PPM_330 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[282]) );
PP_MIDDLE PPM_331 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[298]) );
PP_MIDDLE PPM_332 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[315]) );
PP_MIDDLE PPM_333 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[331]) );
PP_MIDDLE PPM_334 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[346]) );
PP_MIDDLE PPM_335 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[361]) );
PP_MIDDLE PPM_336 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[375]) );
PP_MIDDLE PPM_337 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[389]) );
PP_MIDDLE PPM_338 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[402]) );
PP_MIDDLE PPM_339 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[415]) );
PP_MIDDLE PPM_340 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[427]) );
PP_MIDDLE PPM_341 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[439]) );
PP_MIDDLE PPM_342 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[450]) );
PP_MIDDLE PPM_343 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[461]) );
PP_MIDDLE PPM_344 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[471]) );
PP_MIDDLE PPM_345 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[481]) );
PP_MIDDLE PPM_346 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[490]) );
PP_MIDDLE PPM_347 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[499]) );
PP_MIDDLE PPM_348 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[507]) );
PP_MIDDLE PPM_349 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[515]) );
PP_MIDDLE PPM_350 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[522]) );
PP_MIDDLE PPM_351 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[528]) );
assign SUMMAND[529] = LOGIC_ONE;
PP_HIGH PPH_10 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[535]) );
DECODER DEC_11 (.INA (OPB[21]) , .INB (OPB[22]) , .INC (OPB[23]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) );
PP_LOW PPL_11 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[154]) );
R_GATE RGATE_11 (.INA (OPB[21]) , .INB (OPB[22]) , .INC (OPB[23]) , .PPBIT (SUMMAND[155]) );
PP_MIDDLE PPM_352 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[167]) );
PP_MIDDLE PPM_353 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[179]) );
PP_MIDDLE PPM_354 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[193]) );
PP_MIDDLE PPM_355 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[206]) );
PP_MIDDLE PPM_356 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[221]) );
PP_MIDDLE PPM_357 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[235]) );
PP_MIDDLE PPM_358 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[251]) );
PP_MIDDLE PPM_359 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[266]) );
PP_MIDDLE PPM_360 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[283]) );
PP_MIDDLE PPM_361 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[299]) );
PP_MIDDLE PPM_362 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[316]) );
PP_MIDDLE PPM_363 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[332]) );
PP_MIDDLE PPM_364 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[347]) );
PP_MIDDLE PPM_365 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[362]) );
PP_MIDDLE PPM_366 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[376]) );
PP_MIDDLE PPM_367 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[390]) );
PP_MIDDLE PPM_368 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[403]) );
PP_MIDDLE PPM_369 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[416]) );
PP_MIDDLE PPM_370 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[428]) );
PP_MIDDLE PPM_371 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[440]) );
PP_MIDDLE PPM_372 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[451]) );
PP_MIDDLE PPM_373 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[462]) );
PP_MIDDLE PPM_374 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[472]) );
PP_MIDDLE PPM_375 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[482]) );
PP_MIDDLE PPM_376 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[491]) );
PP_MIDDLE PPM_377 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[500]) );
PP_MIDDLE PPM_378 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[508]) );
PP_MIDDLE PPM_379 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[516]) );
PP_MIDDLE PPM_380 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[523]) );
PP_MIDDLE PPM_381 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[530]) );
PP_MIDDLE PPM_382 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[536]) );
PP_MIDDLE PPM_383 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[541]) );
assign SUMMAND[542] = LOGIC_ONE;
PP_HIGH PPH_11 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[547]) );
DECODER DEC_12 (.INA (OPB[23]) , .INB (OPB[24]) , .INC (OPB[25]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) );
PP_LOW PPL_12 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[180]) );
R_GATE RGATE_12 (.INA (OPB[23]) , .INB (OPB[24]) , .INC (OPB[25]) , .PPBIT (SUMMAND[181]) );
PP_MIDDLE PPM_384 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[194]) );
PP_MIDDLE PPM_385 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[207]) );
PP_MIDDLE PPM_386 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[222]) );
PP_MIDDLE PPM_387 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[236]) );
PP_MIDDLE PPM_388 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[252]) );
PP_MIDDLE PPM_389 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[267]) );
PP_MIDDLE PPM_390 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[284]) );
PP_MIDDLE PPM_391 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[300]) );
PP_MIDDLE PPM_392 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[317]) );
PP_MIDDLE PPM_393 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[333]) );
PP_MIDDLE PPM_394 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[348]) );
PP_MIDDLE PPM_395 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[363]) );
PP_MIDDLE PPM_396 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[377]) );
PP_MIDDLE PPM_397 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[391]) );
PP_MIDDLE PPM_398 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[404]) );
PP_MIDDLE PPM_399 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[417]) );
PP_MIDDLE PPM_400 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[429]) );
PP_MIDDLE PPM_401 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[441]) );
PP_MIDDLE PPM_402 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[452]) );
PP_MIDDLE PPM_403 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[463]) );
PP_MIDDLE PPM_404 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[473]) );
PP_MIDDLE PPM_405 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[483]) );
PP_MIDDLE PPM_406 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[492]) );
PP_MIDDLE PPM_407 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[501]) );
PP_MIDDLE PPM_408 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[509]) );
PP_MIDDLE PPM_409 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[517]) );
PP_MIDDLE PPM_410 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[524]) );
PP_MIDDLE PPM_411 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[531]) );
PP_MIDDLE PPM_412 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[537]) );
PP_MIDDLE PPM_413 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[543]) );
PP_MIDDLE PPM_414 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[548]) );
PP_MIDDLE PPM_415 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[552]) );
assign SUMMAND[553] = LOGIC_ONE;
PP_HIGH PPH_12 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[557]) );
DECODER DEC_13 (.INA (OPB[25]) , .INB (OPB[26]) , .INC (OPB[27]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) );
PP_LOW PPL_13 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[208]) );
R_GATE RGATE_13 (.INA (OPB[25]) , .INB (OPB[26]) , .INC (OPB[27]) , .PPBIT (SUMMAND[209]) );
PP_MIDDLE PPM_416 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[223]) );
PP_MIDDLE PPM_417 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[237]) );
PP_MIDDLE PPM_418 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[253]) );
PP_MIDDLE PPM_419 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[268]) );
PP_MIDDLE PPM_420 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[285]) );
PP_MIDDLE PPM_421 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[301]) );
PP_MIDDLE PPM_422 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[318]) );
PP_MIDDLE PPM_423 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[334]) );
PP_MIDDLE PPM_424 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[349]) );
PP_MIDDLE PPM_425 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[364]) );
PP_MIDDLE PPM_426 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[378]) );
PP_MIDDLE PPM_427 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[392]) );
PP_MIDDLE PPM_428 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[405]) );
PP_MIDDLE PPM_429 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[418]) );
PP_MIDDLE PPM_430 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[430]) );
PP_MIDDLE PPM_431 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[442]) );
PP_MIDDLE PPM_432 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[453]) );
PP_MIDDLE PPM_433 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[464]) );
PP_MIDDLE PPM_434 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[474]) );
PP_MIDDLE PPM_435 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[484]) );
PP_MIDDLE PPM_436 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[493]) );
PP_MIDDLE PPM_437 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[502]) );
PP_MIDDLE PPM_438 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[510]) );
PP_MIDDLE PPM_439 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[518]) );
PP_MIDDLE PPM_440 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[525]) );
PP_MIDDLE PPM_441 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[532]) );
PP_MIDDLE PPM_442 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[538]) );
PP_MIDDLE PPM_443 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[544]) );
PP_MIDDLE PPM_444 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[549]) );
PP_MIDDLE PPM_445 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[554]) );
PP_MIDDLE PPM_446 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[558]) );
PP_MIDDLE PPM_447 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[561]) );
assign SUMMAND[562] = LOGIC_ONE;
PP_HIGH PPH_13 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[565]) );
DECODER DEC_14 (.INA (OPB[27]) , .INB (OPB[28]) , .INC (OPB[29]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) );
PP_LOW PPL_14 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[238]) );
R_GATE RGATE_14 (.INA (OPB[27]) , .INB (OPB[28]) , .INC (OPB[29]) , .PPBIT (SUMMAND[239]) );
PP_MIDDLE PPM_448 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[254]) );
PP_MIDDLE PPM_449 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[269]) );
PP_MIDDLE PPM_450 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[286]) );
PP_MIDDLE PPM_451 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[302]) );
PP_MIDDLE PPM_452 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[319]) );
PP_MIDDLE PPM_453 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[335]) );
PP_MIDDLE PPM_454 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[350]) );
PP_MIDDLE PPM_455 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[365]) );
PP_MIDDLE PPM_456 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[379]) );
PP_MIDDLE PPM_457 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[393]) );
PP_MIDDLE PPM_458 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[406]) );
PP_MIDDLE PPM_459 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[419]) );
PP_MIDDLE PPM_460 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[431]) );
PP_MIDDLE PPM_461 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[443]) );
PP_MIDDLE PPM_462 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[454]) );
PP_MIDDLE PPM_463 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[465]) );
PP_MIDDLE PPM_464 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[475]) );
PP_MIDDLE PPM_465 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[485]) );
PP_MIDDLE PPM_466 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[494]) );
PP_MIDDLE PPM_467 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[503]) );
PP_MIDDLE PPM_468 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[511]) );
PP_MIDDLE PPM_469 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[519]) );
PP_MIDDLE PPM_470 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[526]) );
PP_MIDDLE PPM_471 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[533]) );
PP_MIDDLE PPM_472 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[539]) );
PP_MIDDLE PPM_473 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[545]) );
PP_MIDDLE PPM_474 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[550]) );
PP_MIDDLE PPM_475 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[555]) );
PP_MIDDLE PPM_476 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[559]) );
PP_MIDDLE PPM_477 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[563]) );
PP_MIDDLE PPM_478 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[566]) );
PP_MIDDLE PPM_479 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[568]) );
assign SUMMAND[569] = LOGIC_ONE;
PP_HIGH PPH_14 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[571]) );
DECODER DEC_15 (.INA (OPB[29]) , .INB (OPB[30]) , .INC (OPB[31]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) );
PP_LOW PPL_15 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[270]) );
R_GATE RGATE_15 (.INA (OPB[29]) , .INB (OPB[30]) , .INC (OPB[31]) , .PPBIT (SUMMAND[271]) );
PP_MIDDLE PPM_480 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[287]) );
PP_MIDDLE PPM_481 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[303]) );
PP_MIDDLE PPM_482 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[320]) );
PP_MIDDLE PPM_483 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[336]) );
PP_MIDDLE PPM_484 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[351]) );
PP_MIDDLE PPM_485 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[366]) );
PP_MIDDLE PPM_486 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[380]) );
PP_MIDDLE PPM_487 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[394]) );
PP_MIDDLE PPM_488 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[407]) );
PP_MIDDLE PPM_489 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[420]) );
PP_MIDDLE PPM_490 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[432]) );
PP_MIDDLE PPM_491 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[444]) );
PP_MIDDLE PPM_492 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[455]) );
PP_MIDDLE PPM_493 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[466]) );
PP_MIDDLE PPM_494 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[476]) );
PP_MIDDLE PPM_495 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[486]) );
PP_MIDDLE PPM_496 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[495]) );
PP_MIDDLE PPM_497 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[504]) );
PP_MIDDLE PPM_498 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[512]) );
PP_MIDDLE PPM_499 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[520]) );
PP_MIDDLE PPM_500 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[527]) );
PP_MIDDLE PPM_501 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[534]) );
PP_MIDDLE PPM_502 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[540]) );
PP_MIDDLE PPM_503 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[546]) );
PP_MIDDLE PPM_504 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[551]) );
PP_MIDDLE PPM_505 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[556]) );
PP_MIDDLE PPM_506 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[560]) );
PP_MIDDLE PPM_507 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[564]) );
PP_MIDDLE PPM_508 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[567]) );
PP_MIDDLE PPM_509 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[570]) );
PP_MIDDLE PPM_510 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[572]) );
PP_MIDDLE PPM_511 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[573]) );
assign SUMMAND[574] = LOGIC_ONE;
PP_HIGH PPH_15 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[575]) );
endmodule
module FULL_ADDER ( DATA_A, DATA_B, DATA_C, SAVE, CARRY );
input DATA_A;
input DATA_B;
input DATA_C;
output SAVE;
output CARRY;
wire TMP;
assign TMP = DATA_A ^ DATA_B;
assign SAVE = TMP ^ DATA_C;
assign CARRY = ~ (( ~ (TMP & DATA_C)) & ( ~ (DATA_A & DATA_B)));
endmodule
module HALF_ADDER ( DATA_A, DATA_B, SAVE, CARRY );
input DATA_A;
input DATA_B;
output SAVE;
output CARRY;
assign SAVE = DATA_A ^ DATA_B;
assign CARRY = DATA_A & DATA_B;
endmodule
module FLIPFLOP ( DIN, RST, CLK, DOUT );
input DIN;
input RST;
input CLK;
output DOUT;
reg DOUT_reg;
always @ ( posedge RST or posedge CLK ) begin
if (RST)
DOUT_reg <= 1'b0;
else
DOUT_reg <= #1 DIN;
end
assign DOUT = DOUT_reg;
endmodule
module WALLACE_33_32 ( SUMMAND, RST, CLK, CARRY, SUM );
input [0:575] SUMMAND;
input RST;
input CLK;
output [0:62] CARRY;
output [0:63] SUM;
wire [0:7] LATCHED_PP;
wire [0:523] INT_CARRY;
wire [0:669] INT_SUM;
HALF_ADDER HA_0 (.DATA_A (SUMMAND[0]) , .DATA_B (SUMMAND[1]) , .SAVE (INT_SUM[0]) , .CARRY (INT_CARRY[0]) );
FLIPFLOP LA_0 (.DIN (INT_SUM[0]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[0]) );
FLIPFLOP LA_1 (.DIN (INT_CARRY[0]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[0]) );
assign INT_SUM[1] = SUMMAND[2];
assign CARRY[1] = 0;
FLIPFLOP LA_2 (.DIN (INT_SUM[1]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[1]) );
FULL_ADDER FA_0 (.DATA_A (SUMMAND[3]) , .DATA_B (SUMMAND[4]) , .DATA_C (SUMMAND[5]) , .SAVE (INT_SUM[2]) , .CARRY (INT_CARRY[1]) );
FLIPFLOP LA_3 (.DIN (INT_SUM[2]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[2]) );
FLIPFLOP LA_4 (.DIN (INT_CARRY[1]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[2]) );
HALF_ADDER HA_1 (.DATA_A (SUMMAND[6]) , .DATA_B (SUMMAND[7]) , .SAVE (INT_SUM[3]) , .CARRY (INT_CARRY[2]) );
FLIPFLOP LA_5 (.DIN (INT_SUM[3]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[3]) );
FLIPFLOP LA_6 (.DIN (INT_CARRY[2]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[3]) );
FULL_ADDER FA_1 (.DATA_A (SUMMAND[8]) , .DATA_B (SUMMAND[9]) , .DATA_C (SUMMAND[10]) , .SAVE (INT_SUM[4]) , .CARRY (INT_CARRY[4]) );
assign INT_SUM[5] = SUMMAND[11];
HALF_ADDER HA_2 (.DATA_A (INT_SUM[4]) , .DATA_B (INT_SUM[5]) , .SAVE (INT_SUM[6]) , .CARRY (INT_CARRY[3]) );
FLIPFLOP LA_7 (.DIN (INT_SUM[6]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[4]) );
FLIPFLOP LA_8 (.DIN (INT_CARRY[3]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[4]) );
FULL_ADDER FA_2 (.DATA_A (SUMMAND[12]) , .DATA_B (SUMMAND[13]) , .DATA_C (SUMMAND[14]) , .SAVE (INT_SUM[7]) , .CARRY (INT_CARRY[6]) );
HALF_ADDER HA_3 (.DATA_A (INT_SUM[7]) , .DATA_B (INT_CARRY[4]) , .SAVE (INT_SUM[8]) , .CARRY (INT_CARRY[5]) );
FLIPFLOP LA_9 (.DIN (INT_SUM[8]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[5]) );
FLIPFLOP LA_10 (.DIN (INT_CARRY[5]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[5]) );
FULL_ADDER FA_3 (.DATA_A (SUMMAND[15]) , .DATA_B (SUMMAND[16]) , .DATA_C (SUMMAND[17]) , .SAVE (INT_SUM[9]) , .CARRY (INT_CARRY[8]) );
HALF_ADDER HA_4 (.DATA_A (SUMMAND[18]) , .DATA_B (SUMMAND[19]) , .SAVE (INT_SUM[10]) , .CARRY (INT_CARRY[9]) );
FULL_ADDER FA_4 (.DATA_A (INT_SUM[9]) , .DATA_B (INT_SUM[10]) , .DATA_C (INT_CARRY[6]) , .SAVE (INT_SUM[11]) , .CARRY (INT_CARRY[7]) );
FLIPFLOP LA_11 (.DIN (INT_SUM[11]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[6]) );
FLIPFLOP LA_12 (.DIN (INT_CARRY[7]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[6]) );
FULL_ADDER FA_5 (.DATA_A (SUMMAND[20]) , .DATA_B (SUMMAND[21]) , .DATA_C (SUMMAND[22]) , .SAVE (INT_SUM[12]) , .CARRY (INT_CARRY[11]) );
assign INT_SUM[13] = SUMMAND[23];
FULL_ADDER FA_6 (.DATA_A (INT_SUM[12]) , .DATA_B (INT_SUM[13]) , .DATA_C (INT_CARRY[8]) , .SAVE (INT_SUM[14]) , .CARRY (INT_CARRY[12]) );
assign INT_SUM[15] = INT_CARRY[9];
HALF_ADDER HA_5 (.DATA_A (INT_SUM[14]) , .DATA_B (INT_SUM[15]) , .SAVE (INT_SUM[16]) , .CARRY (INT_CARRY[10]) );
FLIPFLOP LA_13 (.DIN (INT_SUM[16]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[7]) );
FLIPFLOP LA_14 (.DIN (INT_CARRY[10]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[7]) );
FULL_ADDER FA_7 (.DATA_A (SUMMAND[24]) , .DATA_B (SUMMAND[25]) , .DATA_C (SUMMAND[26]) , .SAVE (INT_SUM[17]) , .CARRY (INT_CARRY[14]) );
FULL_ADDER FA_8 (.DATA_A (SUMMAND[27]) , .DATA_B (SUMMAND[28]) , .DATA_C (SUMMAND[29]) , .SAVE (INT_SUM[18]) , .CARRY (INT_CARRY[15]) );
FULL_ADDER FA_9 (.DATA_A (INT_SUM[17]) , .DATA_B (INT_SUM[18]) , .DATA_C (INT_CARRY[11]) , .SAVE (INT_SUM[19]) , .CARRY (INT_CARRY[16]) );
HALF_ADDER HA_6 (.DATA_A (INT_SUM[19]) , .DATA_B (INT_CARRY[12]) , .SAVE (INT_SUM[20]) , .CARRY (INT_CARRY[13]) );
FLIPFLOP LA_15 (.DIN (INT_SUM[20]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[8]) );
FLIPFLOP LA_16 (.DIN (INT_CARRY[13]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[8]) );
FULL_ADDER FA_10 (.DATA_A (SUMMAND[30]) , .DATA_B (SUMMAND[31]) , .DATA_C (SUMMAND[32]) , .SAVE (INT_SUM[21]) , .CARRY (INT_CARRY[18]) );
HALF_ADDER HA_7 (.DATA_A (SUMMAND[33]) , .DATA_B (SUMMAND[34]) , .SAVE (INT_SUM[22]) , .CARRY (INT_CARRY[19]) );
FULL_ADDER FA_11 (.DATA_A (INT_SUM[21]) , .DATA_B (INT_SUM[22]) , .DATA_C (INT_CARRY[14]) , .SAVE (INT_SUM[23]) , .CARRY (INT_CARRY[20]) );
assign INT_SUM[24] = INT_CARRY[15];
FULL_ADDER FA_12 (.DATA_A (INT_SUM[23]) , .DATA_B (INT_SUM[24]) , .DATA_C (INT_CARRY[16]) , .SAVE (INT_SUM[25]) , .CARRY (INT_CARRY[17]) );
FLIPFLOP LA_17 (.DIN (INT_SUM[25]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[9]) );
FLIPFLOP LA_18 (.DIN (INT_CARRY[17]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[9]) );
FULL_ADDER FA_13 (.DATA_A (SUMMAND[35]) , .DATA_B (SUMMAND[36]) , .DATA_C (SUMMAND[37]) , .SAVE (INT_SUM[26]) , .CARRY (INT_CARRY[22]) );
FULL_ADDER FA_14 (.DATA_A (SUMMAND[38]) , .DATA_B (SUMMAND[39]) , .DATA_C (SUMMAND[40]) , .SAVE (INT_SUM[27]) , .CARRY (INT_CARRY[23]) );
assign INT_SUM[28] = SUMMAND[41];
FULL_ADDER FA_15 (.DATA_A (INT_SUM[26]) , .DATA_B (INT_SUM[27]) , .DATA_C (INT_SUM[28]) , .SAVE (INT_SUM[29]) , .CARRY (INT_CARRY[24]) );
HALF_ADDER HA_8 (.DATA_A (INT_CARRY[18]) , .DATA_B (INT_CARRY[19]) , .SAVE (INT_SUM[30]) , .CARRY (INT_CARRY[25]) );
FULL_ADDER FA_16 (.DATA_A (INT_SUM[29]) , .DATA_B (INT_SUM[30]) , .DATA_C (INT_CARRY[20]) , .SAVE (INT_SUM[31]) , .CARRY (INT_CARRY[21]) );
FLIPFLOP LA_19 (.DIN (INT_SUM[31]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[10]) );
FLIPFLOP LA_20 (.DIN (INT_CARRY[21]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[10]) );
FULL_ADDER FA_17 (.DATA_A (SUMMAND[42]) , .DATA_B (SUMMAND[43]) , .DATA_C (SUMMAND[44]) , .SAVE (INT_SUM[32]) , .CARRY (INT_CARRY[27]) );
FULL_ADDER FA_18 (.DATA_A (SUMMAND[45]) , .DATA_B (SUMMAND[46]) , .DATA_C (SUMMAND[47]) , .SAVE (INT_SUM[33]) , .CARRY (INT_CARRY[28]) );
FULL_ADDER FA_19 (.DATA_A (INT_SUM[32]) , .DATA_B (INT_SUM[33]) , .DATA_C (INT_CARRY[22]) , .SAVE (INT_SUM[34]) , .CARRY (INT_CARRY[29]) );
assign INT_SUM[35] = INT_CARRY[23];
FULL_ADDER FA_20 (.DATA_A (INT_SUM[34]) , .DATA_B (INT_SUM[35]) , .DATA_C (INT_CARRY[24]) , .SAVE (INT_SUM[36]) , .CARRY (INT_CARRY[30]) );
assign INT_SUM[37] = INT_CARRY[25];
HALF_ADDER HA_9 (.DATA_A (INT_SUM[36]) , .DATA_B (INT_SUM[37]) , .SAVE (INT_SUM[38]) , .CARRY (INT_CARRY[26]) );
FLIPFLOP LA_21 (.DIN (INT_SUM[38]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[11]) );
FLIPFLOP LA_22 (.DIN (INT_CARRY[26]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[11]) );
FULL_ADDER FA_21 (.DATA_A (SUMMAND[48]) , .DATA_B (SUMMAND[49]) , .DATA_C (SUMMAND[50]) , .SAVE (INT_SUM[39]) , .CARRY (INT_CARRY[32]) );
FULL_ADDER FA_22 (.DATA_A (SUMMAND[51]) , .DATA_B (SUMMAND[52]) , .DATA_C (SUMMAND[53]) , .SAVE (INT_SUM[40]) , .CARRY (INT_CARRY[33]) );
assign INT_SUM[41] = SUMMAND[54];
assign INT_SUM[42] = SUMMAND[55];
FULL_ADDER FA_23 (.DATA_A (INT_SUM[39]) , .DATA_B (INT_SUM[40]) , .DATA_C (INT_SUM[41]) , .SAVE (INT_SUM[43]) , .CARRY (INT_CARRY[34]) );
FULL_ADDER FA_24 (.DATA_A (INT_SUM[42]) , .DATA_B (INT_CARRY[27]) , .DATA_C (INT_CARRY[28]) , .SAVE (INT_SUM[44]) , .CARRY (INT_CARRY[35]) );
FULL_ADDER FA_25 (.DATA_A (INT_SUM[43]) , .DATA_B (INT_SUM[44]) , .DATA_C (INT_CARRY[29]) , .SAVE (INT_SUM[45]) , .CARRY (INT_CARRY[36]) );
HALF_ADDER HA_10 (.DATA_A (INT_SUM[45]) , .DATA_B (INT_CARRY[30]) , .SAVE (INT_SUM[46]) , .CARRY (INT_CARRY[31]) );
FLIPFLOP LA_23 (.DIN (INT_SUM[46]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[12]) );
FLIPFLOP LA_24 (.DIN (INT_CARRY[31]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[12]) );
FULL_ADDER FA_26 (.DATA_A (SUMMAND[56]) , .DATA_B (SUMMAND[57]) , .DATA_C (SUMMAND[58]) , .SAVE (INT_SUM[47]) , .CARRY (INT_CARRY[38]) );
FULL_ADDER FA_27 (.DATA_A (SUMMAND[59]) , .DATA_B (SUMMAND[60]) , .DATA_C (SUMMAND[61]) , .SAVE (INT_SUM[48]) , .CARRY (INT_CARRY[39]) );
assign INT_SUM[49] = SUMMAND[62];
FULL_ADDER FA_28 (.DATA_A (INT_SUM[47]) , .DATA_B (INT_SUM[48]) , .DATA_C (INT_SUM[49]) , .SAVE (INT_SUM[50]) , .CARRY (INT_CARRY[40]) );
HALF_ADDER HA_11 (.DATA_A (INT_CARRY[32]) , .DATA_B (INT_CARRY[33]) , .SAVE (INT_SUM[51]) , .CARRY (INT_CARRY[41]) );
FULL_ADDER FA_29 (.DATA_A (INT_SUM[50]) , .DATA_B (INT_SUM[51]) , .DATA_C (INT_CARRY[34]) , .SAVE (INT_SUM[52]) , .CARRY (INT_CARRY[42]) );
assign INT_SUM[53] = INT_CARRY[35];
FULL_ADDER FA_30 (.DATA_A (INT_SUM[52]) , .DATA_B (INT_SUM[53]) , .DATA_C (INT_CARRY[36]) , .SAVE (INT_SUM[54]) , .CARRY (INT_CARRY[37]) );
FLIPFLOP LA_25 (.DIN (INT_SUM[54]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[13]) );
FLIPFLOP LA_26 (.DIN (INT_CARRY[37]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[13]) );
FULL_ADDER FA_31 (.DATA_A (SUMMAND[63]) , .DATA_B (SUMMAND[64]) , .DATA_C (SUMMAND[65]) , .SAVE (INT_SUM[55]) , .CARRY (INT_CARRY[44]) );
FULL_ADDER FA_32 (.DATA_A (SUMMAND[66]) , .DATA_B (SUMMAND[67]) , .DATA_C (SUMMAND[68]) , .SAVE (INT_SUM[56]) , .CARRY (INT_CARRY[45]) );
FULL_ADDER FA_33 (.DATA_A (SUMMAND[69]) , .DATA_B (SUMMAND[70]) , .DATA_C (SUMMAND[71]) , .SAVE (INT_SUM[57]) , .CARRY (INT_CARRY[46]) );
FULL_ADDER FA_34 (.DATA_A (INT_SUM[55]) , .DATA_B (INT_SUM[56]) , .DATA_C (INT_SUM[57]) , .SAVE (INT_SUM[58]) , .CARRY (INT_CARRY[47]) );
HALF_ADDER HA_12 (.DATA_A (INT_CARRY[38]) , .DATA_B (INT_CARRY[39]) , .SAVE (INT_SUM[59]) , .CARRY (INT_CARRY[48]) );
FULL_ADDER FA_35 (.DATA_A (INT_SUM[58]) , .DATA_B (INT_SUM[59]) , .DATA_C (INT_CARRY[40]) , .SAVE (INT_SUM[60]) , .CARRY (INT_CARRY[49]) );
assign INT_SUM[61] = INT_CARRY[41];
FULL_ADDER FA_36 (.DATA_A (INT_SUM[60]) , .DATA_B (INT_SUM[61]) , .DATA_C (INT_CARRY[42]) , .SAVE (INT_SUM[62]) , .CARRY (INT_CARRY[43]) );
FLIPFLOP LA_27 (.DIN (INT_SUM[62]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[14]) );
FLIPFLOP LA_28 (.DIN (INT_CARRY[43]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[14]) );
FULL_ADDER FA_37 (.DATA_A (SUMMAND[72]) , .DATA_B (SUMMAND[73]) , .DATA_C (SUMMAND[74]) , .SAVE (INT_SUM[63]) , .CARRY (INT_CARRY[51]) );
FULL_ADDER FA_38 (.DATA_A (SUMMAND[75]) , .DATA_B (SUMMAND[76]) , .DATA_C (SUMMAND[77]) , .SAVE (INT_SUM[64]) , .CARRY (INT_CARRY[52]) );
HALF_ADDER HA_13 (.DATA_A (SUMMAND[78]) , .DATA_B (SUMMAND[79]) , .SAVE (INT_SUM[65]) , .CARRY (INT_CARRY[53]) );
FULL_ADDER FA_39 (.DATA_A (INT_SUM[63]) , .DATA_B (INT_SUM[64]) , .DATA_C (INT_SUM[65]) , .SAVE (INT_SUM[66]) , .CARRY (INT_CARRY[54]) );
FULL_ADDER FA_40 (.DATA_A (INT_CARRY[44]) , .DATA_B (INT_CARRY[45]) , .DATA_C (INT_CARRY[46]) , .SAVE (INT_SUM[67]) , .CARRY (INT_CARRY[55]) );
FULL_ADDER FA_41 (.DATA_A (INT_SUM[66]) , .DATA_B (INT_SUM[67]) , .DATA_C (INT_CARRY[47]) , .SAVE (INT_SUM[68]) , .CARRY (INT_CARRY[56]) );
assign INT_SUM[69] = INT_CARRY[48];
FULL_ADDER FA_42 (.DATA_A (INT_SUM[68]) , .DATA_B (INT_SUM[69]) , .DATA_C (INT_CARRY[49]) , .SAVE (INT_SUM[70]) , .CARRY (INT_CARRY[50]) );
FLIPFLOP LA_29 (.DIN (INT_SUM[70]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[15]) );
FLIPFLOP LA_30 (.DIN (INT_CARRY[50]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[15]) );
FULL_ADDER FA_43 (.DATA_A (SUMMAND[80]) , .DATA_B (SUMMAND[81]) , .DATA_C (SUMMAND[82]) , .SAVE (INT_SUM[71]) , .CARRY (INT_CARRY[58]) );
FULL_ADDER FA_44 (.DATA_A (SUMMAND[83]) , .DATA_B (SUMMAND[84]) , .DATA_C (SUMMAND[85]) , .SAVE (INT_SUM[72]) , .CARRY (INT_CARRY[59]) );
FULL_ADDER FA_45 (.DATA_A (SUMMAND[86]) , .DATA_B (SUMMAND[87]) , .DATA_C (SUMMAND[88]) , .SAVE (INT_SUM[73]) , .CARRY (INT_CARRY[60]) );
assign INT_SUM[74] = SUMMAND[89];
FULL_ADDER FA_46 (.DATA_A (INT_SUM[71]) , .DATA_B (INT_SUM[72]) , .DATA_C (INT_SUM[73]) , .SAVE (INT_SUM[75]) , .CARRY (INT_CARRY[61]) );
FULL_ADDER FA_47 (.DATA_A (INT_SUM[74]) , .DATA_B (INT_CARRY[51]) , .DATA_C (INT_CARRY[52]) , .SAVE (INT_SUM[76]) , .CARRY (INT_CARRY[62]) );
assign INT_SUM[77] = INT_CARRY[53];
FULL_ADDER FA_48 (.DATA_A (INT_SUM[75]) , .DATA_B (INT_SUM[76]) , .DATA_C (INT_SUM[77]) , .SAVE (INT_SUM[78]) , .CARRY (INT_CARRY[63]) );
HALF_ADDER HA_14 (.DATA_A (INT_CARRY[54]) , .DATA_B (INT_CARRY[55]) , .SAVE (INT_SUM[79]) , .CARRY (INT_CARRY[64]) );
FULL_ADDER FA_49 (.DATA_A (INT_SUM[78]) , .DATA_B (INT_SUM[79]) , .DATA_C (INT_CARRY[56]) , .SAVE (INT_SUM[80]) , .CARRY (INT_CARRY[57]) );
FLIPFLOP LA_31 (.DIN (INT_SUM[80]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[16]) );
FLIPFLOP LA_32 (.DIN (INT_CARRY[57]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[16]) );
FULL_ADDER FA_50 (.DATA_A (SUMMAND[90]) , .DATA_B (SUMMAND[91]) , .DATA_C (SUMMAND[92]) , .SAVE (INT_SUM[81]) , .CARRY (INT_CARRY[65]) );
FULL_ADDER FA_51 (.DATA_A (SUMMAND[93]) , .DATA_B (SUMMAND[94]) , .DATA_C (SUMMAND[95]) , .SAVE (INT_SUM[82]) , .CARRY (INT_CARRY[66]) );
FULL_ADDER FA_52 (.DATA_A (SUMMAND[96]) , .DATA_B (SUMMAND[97]) , .DATA_C (SUMMAND[98]) , .SAVE (INT_SUM[83]) , .CARRY (INT_CARRY[67]) );
FULL_ADDER FA_53 (.DATA_A (INT_SUM[81]) , .DATA_B (INT_SUM[82]) , .DATA_C (INT_SUM[83]) , .SAVE (INT_SUM[84]) , .CARRY (INT_CARRY[68]) );
FULL_ADDER FA_54 (.DATA_A (INT_CARRY[58]) , .DATA_B (INT_CARRY[59]) , .DATA_C (INT_CARRY[60]) , .SAVE (INT_SUM[85]) , .CARRY (INT_CARRY[69]) );
FULL_ADDER FA_55 (.DATA_A (INT_SUM[84]) , .DATA_B (INT_SUM[85]) , .DATA_C (INT_CARRY[61]) , .SAVE (INT_SUM[86]) , .CARRY (INT_CARRY[70]) );
assign INT_SUM[87] = INT_CARRY[62];
FULL_ADDER FA_56 (.DATA_A (INT_SUM[86]) , .DATA_B (INT_SUM[87]) , .DATA_C (INT_CARRY[63]) , .SAVE (INT_SUM[88]) , .CARRY (INT_CARRY[71]) );
assign INT_SUM[90] = INT_CARRY[64];
FLIPFLOP LA_33 (.DIN (INT_SUM[88]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[89]) );
FLIPFLOP LA_34 (.DIN (INT_SUM[90]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[91]) );
HALF_ADDER HA_15 (.DATA_A (INT_SUM[89]) , .DATA_B (INT_SUM[91]) , .SAVE (SUM[17]) , .CARRY (CARRY[17]) );
FULL_ADDER FA_57 (.DATA_A (SUMMAND[99]) , .DATA_B (SUMMAND[100]) , .DATA_C (SUMMAND[101]) , .SAVE (INT_SUM[92]) , .CARRY (INT_CARRY[73]) );
FULL_ADDER FA_58 (.DATA_A (SUMMAND[102]) , .DATA_B (SUMMAND[103]) , .DATA_C (SUMMAND[104]) , .SAVE (INT_SUM[93]) , .CARRY (INT_CARRY[74]) );
FULL_ADDER FA_59 (.DATA_A (SUMMAND[105]) , .DATA_B (SUMMAND[106]) , .DATA_C (SUMMAND[107]) , .SAVE (INT_SUM[94]) , .CARRY (INT_CARRY[75]) );
assign INT_SUM[95] = SUMMAND[108];
assign INT_SUM[96] = SUMMAND[109];
FULL_ADDER FA_60 (.DATA_A (INT_SUM[92]) , .DATA_B (INT_SUM[93]) , .DATA_C (INT_SUM[94]) , .SAVE (INT_SUM[97]) , .CARRY (INT_CARRY[76]) );
FULL_ADDER FA_61 (.DATA_A (INT_SUM[95]) , .DATA_B (INT_SUM[96]) , .DATA_C (INT_CARRY[65]) , .SAVE (INT_SUM[98]) , .CARRY (INT_CARRY[77]) );
assign INT_SUM[99] = INT_CARRY[66];
assign INT_SUM[100] = INT_CARRY[67];
FULL_ADDER FA_62 (.DATA_A (INT_SUM[97]) , .DATA_B (INT_SUM[98]) , .DATA_C (INT_SUM[99]) , .SAVE (INT_SUM[101]) , .CARRY (INT_CARRY[78]) );
FULL_ADDER FA_63 (.DATA_A (INT_SUM[100]) , .DATA_B (INT_CARRY[68]) , .DATA_C (INT_CARRY[69]) , .SAVE (INT_SUM[102]) , .CARRY (INT_CARRY[79]) );
FULL_ADDER FA_64 (.DATA_A (INT_SUM[101]) , .DATA_B (INT_SUM[102]) , .DATA_C (INT_CARRY[70]) , .SAVE (INT_SUM[103]) , .CARRY (INT_CARRY[80]) );
FLIPFLOP LA_35 (.DIN (INT_SUM[103]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[104]) );
FLIPFLOP LA_36 (.DIN (INT_CARRY[71]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[72]) );
HALF_ADDER HA_16 (.DATA_A (INT_SUM[104]) , .DATA_B (INT_CARRY[72]) , .SAVE (SUM[18]) , .CARRY (CARRY[18]) );
FULL_ADDER FA_65 (.DATA_A (SUMMAND[110]) , .DATA_B (SUMMAND[111]) , .DATA_C (SUMMAND[112]) , .SAVE (INT_SUM[105]) , .CARRY (INT_CARRY[82]) );
FULL_ADDER FA_66 (.DATA_A (SUMMAND[113]) , .DATA_B (SUMMAND[114]) , .DATA_C (SUMMAND[115]) , .SAVE (INT_SUM[106]) , .CARRY (INT_CARRY[83]) );
FULL_ADDER FA_67 (.DATA_A (SUMMAND[116]) , .DATA_B (SUMMAND[117]) , .DATA_C (SUMMAND[118]) , .SAVE (INT_SUM[107]) , .CARRY (INT_CARRY[84]) );
assign INT_SUM[108] = SUMMAND[119];
FULL_ADDER FA_68 (.DATA_A (INT_SUM[105]) , .DATA_B (INT_SUM[106]) , .DATA_C (INT_SUM[107]) , .SAVE (INT_SUM[109]) , .CARRY (INT_CARRY[85]) );
FULL_ADDER FA_69 (.DATA_A (INT_SUM[108]) , .DATA_B (INT_CARRY[73]) , .DATA_C (INT_CARRY[74]) , .SAVE (INT_SUM[110]) , .CARRY (INT_CARRY[86]) );
assign INT_SUM[111] = INT_CARRY[75];
FULL_ADDER FA_70 (.DATA_A (INT_SUM[109]) , .DATA_B (INT_SUM[110]) , .DATA_C (INT_SUM[111]) , .SAVE (INT_SUM[112]) , .CARRY (INT_CARRY[87]) );
HALF_ADDER HA_17 (.DATA_A (INT_CARRY[76]) , .DATA_B (INT_CARRY[77]) , .SAVE (INT_SUM[113]) , .CARRY (INT_CARRY[88]) );
FULL_ADDER FA_71 (.DATA_A (INT_SUM[112]) , .DATA_B (INT_SUM[113]) , .DATA_C (INT_CARRY[78]) , .SAVE (INT_SUM[114]) , .CARRY (INT_CARRY[89]) );
assign INT_SUM[116] = INT_CARRY[79];
FLIPFLOP LA_37 (.DIN (INT_SUM[114]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[115]) );
FLIPFLOP LA_38 (.DIN (INT_SUM[116]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[117]) );
FLIPFLOP LA_39 (.DIN (INT_CARRY[80]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[81]) );
FULL_ADDER FA_72 (.DATA_A (INT_SUM[115]) , .DATA_B (INT_SUM[117]) , .DATA_C (INT_CARRY[81]) , .SAVE (SUM[19]) , .CARRY (CARRY[19]) );
FULL_ADDER FA_73 (.DATA_A (SUMMAND[120]) , .DATA_B (SUMMAND[121]) , .DATA_C (SUMMAND[122]) , .SAVE (INT_SUM[118]) , .CARRY (INT_CARRY[91]) );
FULL_ADDER FA_74 (.DATA_A (SUMMAND[123]) , .DATA_B (SUMMAND[124]) , .DATA_C (SUMMAND[125]) , .SAVE (INT_SUM[119]) , .CARRY (INT_CARRY[92]) );
FULL_ADDER FA_75 (.DATA_A (SUMMAND[126]) , .DATA_B (SUMMAND[127]) , .DATA_C (SUMMAND[128]) , .SAVE (INT_SUM[120]) , .CARRY (INT_CARRY[93]) );
FULL_ADDER FA_76 (.DATA_A (SUMMAND[129]) , .DATA_B (SUMMAND[130]) , .DATA_C (SUMMAND[131]) , .SAVE (INT_SUM[121]) , .CARRY (INT_CARRY[94]) );
FULL_ADDER FA_77 (.DATA_A (INT_SUM[118]) , .DATA_B (INT_SUM[119]) , .DATA_C (INT_SUM[120]) , .SAVE (INT_SUM[122]) , .CARRY (INT_CARRY[95]) );
FULL_ADDER FA_78 (.DATA_A (INT_SUM[121]) , .DATA_B (INT_CARRY[82]) , .DATA_C (INT_CARRY[83]) , .SAVE (INT_SUM[123]) , .CARRY (INT_CARRY[96]) );
assign INT_SUM[124] = INT_CARRY[84];
FULL_ADDER FA_79 (.DATA_A (INT_SUM[122]) , .DATA_B (INT_SUM[123]) , .DATA_C (INT_SUM[124]) , .SAVE (INT_SUM[125]) , .CARRY (INT_CARRY[97]) );
HALF_ADDER HA_18 (.DATA_A (INT_CARRY[85]) , .DATA_B (INT_CARRY[86]) , .SAVE (INT_SUM[126]) , .CARRY (INT_CARRY[98]) );
FULL_ADDER FA_80 (.DATA_A (INT_SUM[125]) , .DATA_B (INT_SUM[126]) , .DATA_C (INT_CARRY[87]) , .SAVE (INT_SUM[127]) , .CARRY (INT_CARRY[99]) );
assign INT_SUM[129] = INT_CARRY[88];
FLIPFLOP LA_40 (.DIN (INT_SUM[127]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[128]) );
FLIPFLOP LA_41 (.DIN (INT_SUM[129]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[130]) );
FLIPFLOP LA_42 (.DIN (INT_CARRY[89]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[90]) );
FULL_ADDER FA_81 (.DATA_A (INT_SUM[128]) , .DATA_B (INT_SUM[130]) , .DATA_C (INT_CARRY[90]) , .SAVE (SUM[20]) , .CARRY (CARRY[20]) );
FULL_ADDER FA_82 (.DATA_A (SUMMAND[132]) , .DATA_B (SUMMAND[133]) , .DATA_C (SUMMAND[134]) , .SAVE (INT_SUM[131]) , .CARRY (INT_CARRY[101]) );
FULL_ADDER FA_83 (.DATA_A (SUMMAND[135]) , .DATA_B (SUMMAND[136]) , .DATA_C (SUMMAND[137]) , .SAVE (INT_SUM[132]) , .CARRY (INT_CARRY[102]) );
FULL_ADDER FA_84 (.DATA_A (SUMMAND[138]) , .DATA_B (SUMMAND[139]) , .DATA_C (SUMMAND[140]) , .SAVE (INT_SUM[133]) , .CARRY (INT_CARRY[103]) );
assign INT_SUM[134] = SUMMAND[141];
assign INT_SUM[135] = SUMMAND[142];
FULL_ADDER FA_85 (.DATA_A (INT_SUM[131]) , .DATA_B (INT_SUM[132]) , .DATA_C (INT_SUM[133]) , .SAVE (INT_SUM[136]) , .CARRY (INT_CARRY[104]) );
FULL_ADDER FA_86 (.DATA_A (INT_SUM[134]) , .DATA_B (INT_SUM[135]) , .DATA_C (INT_CARRY[91]) , .SAVE (INT_SUM[137]) , .CARRY (INT_CARRY[105]) );
FULL_ADDER FA_87 (.DATA_A (INT_CARRY[92]) , .DATA_B (INT_CARRY[93]) , .DATA_C (INT_CARRY[94]) , .SAVE (INT_SUM[138]) , .CARRY (INT_CARRY[106]) );
FULL_ADDER FA_88 (.DATA_A (INT_SUM[136]) , .DATA_B (INT_SUM[137]) , .DATA_C (INT_SUM[138]) , .SAVE (INT_SUM[139]) , .CARRY (INT_CARRY[107]) );
HALF_ADDER HA_19 (.DATA_A (INT_CARRY[95]) , .DATA_B (INT_CARRY[96]) , .SAVE (INT_SUM[140]) , .CARRY (INT_CARRY[108]) );
FULL_ADDER FA_89 (.DATA_A (INT_SUM[139]) , .DATA_B (INT_SUM[140]) , .DATA_C (INT_CARRY[97]) , .SAVE (INT_SUM[141]) , .CARRY (INT_CARRY[109]) );
assign INT_SUM[143] = INT_CARRY[98];
FLIPFLOP LA_43 (.DIN (INT_SUM[141]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[142]) );
FLIPFLOP LA_44 (.DIN (INT_SUM[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[144]) );
FLIPFLOP LA_45 (.DIN (INT_CARRY[99]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[100]) );
FULL_ADDER FA_90 (.DATA_A (INT_SUM[142]) , .DATA_B (INT_SUM[144]) , .DATA_C (INT_CARRY[100]) , .SAVE (SUM[21]) , .CARRY (CARRY[21]) );
FULL_ADDER FA_91 (.DATA_A (SUMMAND[143]) , .DATA_B (SUMMAND[144]) , .DATA_C (SUMMAND[145]) , .SAVE (INT_SUM[145]) , .CARRY (INT_CARRY[111]) );
FULL_ADDER FA_92 (.DATA_A (SUMMAND[146]) , .DATA_B (SUMMAND[147]) , .DATA_C (SUMMAND[148]) , .SAVE (INT_SUM[146]) , .CARRY (INT_CARRY[112]) );
FULL_ADDER FA_93 (.DATA_A (SUMMAND[149]) , .DATA_B (SUMMAND[150]) , .DATA_C (SUMMAND[151]) , .SAVE (INT_SUM[147]) , .CARRY (INT_CARRY[113]) );
FULL_ADDER FA_94 (.DATA_A (SUMMAND[152]) , .DATA_B (SUMMAND[153]) , .DATA_C (SUMMAND[154]) , .SAVE (INT_SUM[148]) , .CARRY (INT_CARRY[114]) );
assign INT_SUM[149] = SUMMAND[155];
FULL_ADDER FA_95 (.DATA_A (INT_SUM[145]) , .DATA_B (INT_SUM[146]) , .DATA_C (INT_SUM[147]) , .SAVE (INT_SUM[150]) , .CARRY (INT_CARRY[115]) );
FULL_ADDER FA_96 (.DATA_A (INT_SUM[148]) , .DATA_B (INT_SUM[149]) , .DATA_C (INT_CARRY[101]) , .SAVE (INT_SUM[151]) , .CARRY (INT_CARRY[116]) );
HALF_ADDER HA_20 (.DATA_A (INT_CARRY[102]) , .DATA_B (INT_CARRY[103]) , .SAVE (INT_SUM[152]) , .CARRY (INT_CARRY[117]) );
FULL_ADDER FA_97 (.DATA_A (INT_SUM[150]) , .DATA_B (INT_SUM[151]) , .DATA_C (INT_SUM[152]) , .SAVE (INT_SUM[153]) , .CARRY (INT_CARRY[118]) );
FULL_ADDER FA_98 (.DATA_A (INT_CARRY[104]) , .DATA_B (INT_CARRY[105]) , .DATA_C (INT_CARRY[106]) , .SAVE (INT_SUM[154]) , .CARRY (INT_CARRY[119]) );
FULL_ADDER FA_99 (.DATA_A (INT_SUM[153]) , .DATA_B (INT_SUM[154]) , .DATA_C (INT_CARRY[107]) , .SAVE (INT_SUM[155]) , .CARRY (INT_CARRY[120]) );
assign INT_SUM[157] = INT_CARRY[108];
FLIPFLOP LA_46 (.DIN (INT_SUM[155]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[156]) );
FLIPFLOP LA_47 (.DIN (INT_SUM[157]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[158]) );
FLIPFLOP LA_48 (.DIN (INT_CARRY[109]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[110]) );
FULL_ADDER FA_100 (.DATA_A (INT_SUM[156]) , .DATA_B (INT_SUM[158]) , .DATA_C (INT_CARRY[110]) , .SAVE (SUM[22]) , .CARRY (CARRY[22]) );
FULL_ADDER FA_101 (.DATA_A (SUMMAND[156]) , .DATA_B (SUMMAND[157]) , .DATA_C (SUMMAND[158]) , .SAVE (INT_SUM[159]) , .CARRY (INT_CARRY[122]) );
FULL_ADDER FA_102 (.DATA_A (SUMMAND[159]) , .DATA_B (SUMMAND[160]) , .DATA_C (SUMMAND[161]) , .SAVE (INT_SUM[160]) , .CARRY (INT_CARRY[123]) );
FULL_ADDER FA_103 (.DATA_A (SUMMAND[162]) , .DATA_B (SUMMAND[163]) , .DATA_C (SUMMAND[164]) , .SAVE (INT_SUM[161]) , .CARRY (INT_CARRY[124]) );
FULL_ADDER FA_104 (.DATA_A (SUMMAND[165]) , .DATA_B (SUMMAND[166]) , .DATA_C (SUMMAND[167]) , .SAVE (INT_SUM[162]) , .CARRY (INT_CARRY[125]) );
FULL_ADDER FA_105 (.DATA_A (INT_SUM[159]) , .DATA_B (INT_SUM[160]) , .DATA_C (INT_SUM[161]) , .SAVE (INT_SUM[163]) , .CARRY (INT_CARRY[126]) );
FULL_ADDER FA_106 (.DATA_A (INT_SUM[162]) , .DATA_B (INT_CARRY[111]) , .DATA_C (INT_CARRY[112]) , .SAVE (INT_SUM[164]) , .CARRY (INT_CARRY[127]) );
HALF_ADDER HA_21 (.DATA_A (INT_CARRY[113]) , .DATA_B (INT_CARRY[114]) , .SAVE (INT_SUM[165]) , .CARRY (INT_CARRY[128]) );
FULL_ADDER FA_107 (.DATA_A (INT_SUM[163]) , .DATA_B (INT_SUM[164]) , .DATA_C (INT_SUM[165]) , .SAVE (INT_SUM[166]) , .CARRY (INT_CARRY[129]) );
FULL_ADDER FA_108 (.DATA_A (INT_CARRY[115]) , .DATA_B (INT_CARRY[116]) , .DATA_C (INT_CARRY[117]) , .SAVE (INT_SUM[167]) , .CARRY (INT_CARRY[130]) );
FULL_ADDER FA_109 (.DATA_A (INT_SUM[166]) , .DATA_B (INT_SUM[167]) , .DATA_C (INT_CARRY[118]) , .SAVE (INT_SUM[168]) , .CARRY (INT_CARRY[131]) );
assign INT_SUM[170] = INT_CARRY[119];
FLIPFLOP LA_49 (.DIN (INT_SUM[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[169]) );
FLIPFLOP LA_50 (.DIN (INT_SUM[170]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[171]) );
FLIPFLOP LA_51 (.DIN (INT_CARRY[120]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[121]) );
FULL_ADDER FA_110 (.DATA_A (INT_SUM[169]) , .DATA_B (INT_SUM[171]) , .DATA_C (INT_CARRY[121]) , .SAVE (SUM[23]) , .CARRY (CARRY[23]) );
FULL_ADDER FA_111 (.DATA_A (SUMMAND[168]) , .DATA_B (SUMMAND[169]) , .DATA_C (SUMMAND[170]) , .SAVE (INT_SUM[172]) , .CARRY (INT_CARRY[133]) );
FULL_ADDER FA_112 (.DATA_A (SUMMAND[171]) , .DATA_B (SUMMAND[172]) , .DATA_C (SUMMAND[173]) , .SAVE (INT_SUM[173]) , .CARRY (INT_CARRY[134]) );
FULL_ADDER FA_113 (.DATA_A (SUMMAND[174]) , .DATA_B (SUMMAND[175]) , .DATA_C (SUMMAND[176]) , .SAVE (INT_SUM[174]) , .CARRY (INT_CARRY[135]) );
FULL_ADDER FA_114 (.DATA_A (SUMMAND[177]) , .DATA_B (SUMMAND[178]) , .DATA_C (SUMMAND[179]) , .SAVE (INT_SUM[175]) , .CARRY (INT_CARRY[136]) );
HALF_ADDER HA_22 (.DATA_A (SUMMAND[180]) , .DATA_B (SUMMAND[181]) , .SAVE (INT_SUM[176]) , .CARRY (INT_CARRY[137]) );
FULL_ADDER FA_115 (.DATA_A (INT_SUM[172]) , .DATA_B (INT_SUM[173]) , .DATA_C (INT_SUM[174]) , .SAVE (INT_SUM[177]) , .CARRY (INT_CARRY[138]) );
FULL_ADDER FA_116 (.DATA_A (INT_SUM[175]) , .DATA_B (INT_SUM[176]) , .DATA_C (INT_CARRY[122]) , .SAVE (INT_SUM[178]) , .CARRY (INT_CARRY[139]) );
FULL_ADDER FA_117 (.DATA_A (INT_CARRY[123]) , .DATA_B (INT_CARRY[124]) , .DATA_C (INT_CARRY[125]) , .SAVE (INT_SUM[179]) , .CARRY (INT_CARRY[140]) );
FULL_ADDER FA_118 (.DATA_A (INT_SUM[177]) , .DATA_B (INT_SUM[178]) , .DATA_C (INT_SUM[179]) , .SAVE (INT_SUM[180]) , .CARRY (INT_CARRY[141]) );
FULL_ADDER FA_119 (.DATA_A (INT_CARRY[126]) , .DATA_B (INT_CARRY[127]) , .DATA_C (INT_CARRY[128]) , .SAVE (INT_SUM[181]) , .CARRY (INT_CARRY[142]) );
FULL_ADDER FA_120 (.DATA_A (INT_SUM[180]) , .DATA_B (INT_SUM[181]) , .DATA_C (INT_CARRY[129]) , .SAVE (INT_SUM[182]) , .CARRY (INT_CARRY[143]) );
assign INT_SUM[184] = INT_CARRY[130];
FLIPFLOP LA_52 (.DIN (INT_SUM[182]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[183]) );
FLIPFLOP LA_53 (.DIN (INT_SUM[184]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[185]) );
FLIPFLOP LA_54 (.DIN (INT_CARRY[131]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[132]) );
FULL_ADDER FA_121 (.DATA_A (INT_SUM[183]) , .DATA_B (INT_SUM[185]) , .DATA_C (INT_CARRY[132]) , .SAVE (SUM[24]) , .CARRY (CARRY[24]) );
FULL_ADDER FA_122 (.DATA_A (SUMMAND[182]) , .DATA_B (SUMMAND[183]) , .DATA_C (SUMMAND[184]) , .SAVE (INT_SUM[186]) , .CARRY (INT_CARRY[145]) );
FULL_ADDER FA_123 (.DATA_A (SUMMAND[185]) , .DATA_B (SUMMAND[186]) , .DATA_C (SUMMAND[187]) , .SAVE (INT_SUM[187]) , .CARRY (INT_CARRY[146]) );
FULL_ADDER FA_124 (.DATA_A (SUMMAND[188]) , .DATA_B (SUMMAND[189]) , .DATA_C (SUMMAND[190]) , .SAVE (INT_SUM[188]) , .CARRY (INT_CARRY[147]) );
FULL_ADDER FA_125 (.DATA_A (SUMMAND[191]) , .DATA_B (SUMMAND[192]) , .DATA_C (SUMMAND[193]) , .SAVE (INT_SUM[189]) , .CARRY (INT_CARRY[148]) );
assign INT_SUM[190] = SUMMAND[194];
FULL_ADDER FA_126 (.DATA_A (INT_SUM[186]) , .DATA_B (INT_SUM[187]) , .DATA_C (INT_SUM[188]) , .SAVE (INT_SUM[191]) , .CARRY (INT_CARRY[149]) );
FULL_ADDER FA_127 (.DATA_A (INT_SUM[189]) , .DATA_B (INT_SUM[190]) , .DATA_C (INT_CARRY[133]) , .SAVE (INT_SUM[192]) , .CARRY (INT_CARRY[150]) );
FULL_ADDER FA_128 (.DATA_A (INT_CARRY[134]) , .DATA_B (INT_CARRY[135]) , .DATA_C (INT_CARRY[136]) , .SAVE (INT_SUM[193]) , .CARRY (INT_CARRY[151]) );
assign INT_SUM[194] = INT_CARRY[137];
FULL_ADDER FA_129 (.DATA_A (INT_SUM[191]) , .DATA_B (INT_SUM[192]) , .DATA_C (INT_SUM[193]) , .SAVE (INT_SUM[195]) , .CARRY (INT_CARRY[152]) );
FULL_ADDER FA_130 (.DATA_A (INT_SUM[194]) , .DATA_B (INT_CARRY[138]) , .DATA_C (INT_CARRY[139]) , .SAVE (INT_SUM[196]) , .CARRY (INT_CARRY[153]) );
assign INT_SUM[197] = INT_CARRY[140];
FULL_ADDER FA_131 (.DATA_A (INT_SUM[195]) , .DATA_B (INT_SUM[196]) , .DATA_C (INT_SUM[197]) , .SAVE (INT_SUM[198]) , .CARRY (INT_CARRY[154]) );
HALF_ADDER HA_23 (.DATA_A (INT_CARRY[141]) , .DATA_B (INT_CARRY[142]) , .SAVE (INT_SUM[200]) , .CARRY (INT_CARRY[156]) );
FLIPFLOP LA_55 (.DIN (INT_SUM[198]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[199]) );
FLIPFLOP LA_56 (.DIN (INT_SUM[200]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[201]) );
FLIPFLOP LA_57 (.DIN (INT_CARRY[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[144]) );
FULL_ADDER FA_132 (.DATA_A (INT_SUM[199]) , .DATA_B (INT_SUM[201]) , .DATA_C (INT_CARRY[144]) , .SAVE (SUM[25]) , .CARRY (CARRY[25]) );
FULL_ADDER FA_133 (.DATA_A (SUMMAND[195]) , .DATA_B (SUMMAND[196]) , .DATA_C (SUMMAND[197]) , .SAVE (INT_SUM[202]) , .CARRY (INT_CARRY[158]) );
FULL_ADDER FA_134 (.DATA_A (SUMMAND[198]) , .DATA_B (SUMMAND[199]) , .DATA_C (SUMMAND[200]) , .SAVE (INT_SUM[203]) , .CARRY (INT_CARRY[159]) );
FULL_ADDER FA_135 (.DATA_A (SUMMAND[201]) , .DATA_B (SUMMAND[202]) , .DATA_C (SUMMAND[203]) , .SAVE (INT_SUM[204]) , .CARRY (INT_CARRY[160]) );
FULL_ADDER FA_136 (.DATA_A (SUMMAND[204]) , .DATA_B (SUMMAND[205]) , .DATA_C (SUMMAND[206]) , .SAVE (INT_SUM[205]) , .CARRY (INT_CARRY[161]) );
FULL_ADDER FA_137 (.DATA_A (SUMMAND[207]) , .DATA_B (SUMMAND[208]) , .DATA_C (SUMMAND[209]) , .SAVE (INT_SUM[206]) , .CARRY (INT_CARRY[162]) );
FULL_ADDER FA_138 (.DATA_A (INT_SUM[202]) , .DATA_B (INT_SUM[203]) , .DATA_C (INT_SUM[204]) , .SAVE (INT_SUM[207]) , .CARRY (INT_CARRY[163]) );
FULL_ADDER FA_139 (.DATA_A (INT_SUM[205]) , .DATA_B (INT_SUM[206]) , .DATA_C (INT_CARRY[145]) , .SAVE (INT_SUM[208]) , .CARRY (INT_CARRY[164]) );
FULL_ADDER FA_140 (.DATA_A (INT_CARRY[146]) , .DATA_B (INT_CARRY[147]) , .DATA_C (INT_CARRY[148]) , .SAVE (INT_SUM[209]) , .CARRY (INT_CARRY[165]) );
FULL_ADDER FA_141 (.DATA_A (INT_SUM[207]) , .DATA_B (INT_SUM[208]) , .DATA_C (INT_SUM[209]) , .SAVE (INT_SUM[210]) , .CARRY (INT_CARRY[166]) );
FULL_ADDER FA_142 (.DATA_A (INT_CARRY[149]) , .DATA_B (INT_CARRY[150]) , .DATA_C (INT_CARRY[151]) , .SAVE (INT_SUM[211]) , .CARRY (INT_CARRY[167]) );
FULL_ADDER FA_143 (.DATA_A (INT_SUM[210]) , .DATA_B (INT_SUM[211]) , .DATA_C (INT_CARRY[152]) , .SAVE (INT_SUM[212]) , .CARRY (INT_CARRY[168]) );
assign INT_SUM[214] = INT_CARRY[153];
FLIPFLOP LA_58 (.DIN (INT_SUM[212]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[213]) );
FLIPFLOP LA_59 (.DIN (INT_SUM[214]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[215]) );
FLIPFLOP LA_60 (.DIN (INT_CARRY[154]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[155]) );
FULL_ADDER FA_144 (.DATA_A (INT_SUM[213]) , .DATA_B (INT_SUM[215]) , .DATA_C (INT_CARRY[155]) , .SAVE (INT_SUM[216]) , .CARRY (INT_CARRY[170]) );
FLIPFLOP LA_61 (.DIN (INT_CARRY[156]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[157]) );
assign INT_SUM[217] = INT_CARRY[157];
HALF_ADDER HA_24 (.DATA_A (INT_SUM[216]) , .DATA_B (INT_SUM[217]) , .SAVE (SUM[26]) , .CARRY (CARRY[26]) );
FULL_ADDER FA_145 (.DATA_A (SUMMAND[210]) , .DATA_B (SUMMAND[211]) , .DATA_C (SUMMAND[212]) , .SAVE (INT_SUM[218]) , .CARRY (INT_CARRY[171]) );
FULL_ADDER FA_146 (.DATA_A (SUMMAND[213]) , .DATA_B (SUMMAND[214]) , .DATA_C (SUMMAND[215]) , .SAVE (INT_SUM[219]) , .CARRY (INT_CARRY[172]) );
FULL_ADDER FA_147 (.DATA_A (SUMMAND[216]) , .DATA_B (SUMMAND[217]) , .DATA_C (SUMMAND[218]) , .SAVE (INT_SUM[220]) , .CARRY (INT_CARRY[173]) );
FULL_ADDER FA_148 (.DATA_A (SUMMAND[219]) , .DATA_B (SUMMAND[220]) , .DATA_C (SUMMAND[221]) , .SAVE (INT_SUM[221]) , .CARRY (INT_CARRY[174]) );
HALF_ADDER HA_25 (.DATA_A (SUMMAND[222]) , .DATA_B (SUMMAND[223]) , .SAVE (INT_SUM[222]) , .CARRY (INT_CARRY[175]) );
FULL_ADDER FA_149 (.DATA_A (INT_SUM[218]) , .DATA_B (INT_SUM[219]) , .DATA_C (INT_SUM[220]) , .SAVE (INT_SUM[223]) , .CARRY (INT_CARRY[176]) );
FULL_ADDER FA_150 (.DATA_A (INT_SUM[221]) , .DATA_B (INT_SUM[222]) , .DATA_C (INT_CARRY[158]) , .SAVE (INT_SUM[224]) , .CARRY (INT_CARRY[177]) );
FULL_ADDER FA_151 (.DATA_A (INT_CARRY[159]) , .DATA_B (INT_CARRY[160]) , .DATA_C (INT_CARRY[161]) , .SAVE (INT_SUM[225]) , .CARRY (INT_CARRY[178]) );
assign INT_SUM[226] = INT_CARRY[162];
FULL_ADDER FA_152 (.DATA_A (INT_SUM[223]) , .DATA_B (INT_SUM[224]) , .DATA_C (INT_SUM[225]) , .SAVE (INT_SUM[227]) , .CARRY (INT_CARRY[179]) );
FULL_ADDER FA_153 (.DATA_A (INT_SUM[226]) , .DATA_B (INT_CARRY[163]) , .DATA_C (INT_CARRY[164]) , .SAVE (INT_SUM[228]) , .CARRY (INT_CARRY[180]) );
assign INT_SUM[229] = INT_CARRY[165];
FULL_ADDER FA_154 (.DATA_A (INT_SUM[227]) , .DATA_B (INT_SUM[228]) , .DATA_C (INT_SUM[229]) , .SAVE (INT_SUM[230]) , .CARRY (INT_CARRY[181]) );
assign INT_SUM[232] = INT_CARRY[166];
assign INT_SUM[234] = INT_CARRY[167];
FLIPFLOP LA_62 (.DIN (INT_SUM[230]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[231]) );
FLIPFLOP LA_63 (.DIN (INT_SUM[232]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[233]) );
FLIPFLOP LA_64 (.DIN (INT_SUM[234]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[235]) );
FULL_ADDER FA_155 (.DATA_A (INT_SUM[231]) , .DATA_B (INT_SUM[233]) , .DATA_C (INT_SUM[235]) , .SAVE (INT_SUM[236]) , .CARRY (INT_CARRY[183]) );
FLIPFLOP LA_65 (.DIN (INT_CARRY[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[169]) );
assign INT_SUM[237] = INT_CARRY[169];
FULL_ADDER FA_156 (.DATA_A (INT_SUM[236]) , .DATA_B (INT_SUM[237]) , .DATA_C (INT_CARRY[170]) , .SAVE (SUM[27]) , .CARRY (CARRY[27]) );
FULL_ADDER FA_157 (.DATA_A (SUMMAND[224]) , .DATA_B (SUMMAND[225]) , .DATA_C (SUMMAND[226]) , .SAVE (INT_SUM[238]) , .CARRY (INT_CARRY[184]) );
FULL_ADDER FA_158 (.DATA_A (SUMMAND[227]) , .DATA_B (SUMMAND[228]) , .DATA_C (SUMMAND[229]) , .SAVE (INT_SUM[239]) , .CARRY (INT_CARRY[185]) );
FULL_ADDER FA_159 (.DATA_A (SUMMAND[230]) , .DATA_B (SUMMAND[231]) , .DATA_C (SUMMAND[232]) , .SAVE (INT_SUM[240]) , .CARRY (INT_CARRY[186]) );
FULL_ADDER FA_160 (.DATA_A (SUMMAND[233]) , .DATA_B (SUMMAND[234]) , .DATA_C (SUMMAND[235]) , .SAVE (INT_SUM[241]) , .CARRY (INT_CARRY[187]) );
FULL_ADDER FA_161 (.DATA_A (SUMMAND[236]) , .DATA_B (SUMMAND[237]) , .DATA_C (SUMMAND[238]) , .SAVE (INT_SUM[242]) , .CARRY (INT_CARRY[188]) );
assign INT_SUM[243] = SUMMAND[239];
FULL_ADDER FA_162 (.DATA_A (INT_SUM[238]) , .DATA_B (INT_SUM[239]) , .DATA_C (INT_SUM[240]) , .SAVE (INT_SUM[244]) , .CARRY (INT_CARRY[189]) );
FULL_ADDER FA_163 (.DATA_A (INT_SUM[241]) , .DATA_B (INT_SUM[242]) , .DATA_C (INT_SUM[243]) , .SAVE (INT_SUM[245]) , .CARRY (INT_CARRY[190]) );
FULL_ADDER FA_164 (.DATA_A (INT_CARRY[171]) , .DATA_B (INT_CARRY[172]) , .DATA_C (INT_CARRY[173]) , .SAVE (INT_SUM[246]) , .CARRY (INT_CARRY[191]) );
assign INT_SUM[247] = INT_CARRY[174];
assign INT_SUM[248] = INT_CARRY[175];
FULL_ADDER FA_165 (.DATA_A (INT_SUM[244]) , .DATA_B (INT_SUM[245]) , .DATA_C (INT_SUM[246]) , .SAVE (INT_SUM[249]) , .CARRY (INT_CARRY[192]) );
FULL_ADDER FA_166 (.DATA_A (INT_SUM[247]) , .DATA_B (INT_SUM[248]) , .DATA_C (INT_CARRY[176]) , .SAVE (INT_SUM[250]) , .CARRY (INT_CARRY[193]) );
assign INT_SUM[251] = INT_CARRY[177];
assign INT_SUM[252] = INT_CARRY[178];
FULL_ADDER FA_167 (.DATA_A (INT_SUM[249]) , .DATA_B (INT_SUM[250]) , .DATA_C (INT_SUM[251]) , .SAVE (INT_SUM[253]) , .CARRY (INT_CARRY[194]) );
FULL_ADDER FA_168 (.DATA_A (INT_SUM[252]) , .DATA_B (INT_CARRY[179]) , .DATA_C (INT_CARRY[180]) , .SAVE (INT_SUM[255]) , .CARRY (INT_CARRY[196]) );
FLIPFLOP LA_66 (.DIN (INT_SUM[253]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[254]) );
FLIPFLOP LA_67 (.DIN (INT_SUM[255]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[256]) );
FLIPFLOP LA_68 (.DIN (INT_CARRY[181]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[182]) );
FULL_ADDER FA_169 (.DATA_A (INT_SUM[254]) , .DATA_B (INT_SUM[256]) , .DATA_C (INT_CARRY[182]) , .SAVE (INT_SUM[257]) , .CARRY (INT_CARRY[198]) );
HALF_ADDER HA_26 (.DATA_A (INT_SUM[257]) , .DATA_B (INT_CARRY[183]) , .SAVE (SUM[28]) , .CARRY (CARRY[28]) );
FULL_ADDER FA_170 (.DATA_A (SUMMAND[240]) , .DATA_B (SUMMAND[241]) , .DATA_C (SUMMAND[242]) , .SAVE (INT_SUM[258]) , .CARRY (INT_CARRY[199]) );
FULL_ADDER FA_171 (.DATA_A (SUMMAND[243]) , .DATA_B (SUMMAND[244]) , .DATA_C (SUMMAND[245]) , .SAVE (INT_SUM[259]) , .CARRY (INT_CARRY[200]) );
FULL_ADDER FA_172 (.DATA_A (SUMMAND[246]) , .DATA_B (SUMMAND[247]) , .DATA_C (SUMMAND[248]) , .SAVE (INT_SUM[260]) , .CARRY (INT_CARRY[201]) );
FULL_ADDER FA_173 (.DATA_A (SUMMAND[249]) , .DATA_B (SUMMAND[250]) , .DATA_C (SUMMAND[251]) , .SAVE (INT_SUM[261]) , .CARRY (INT_CARRY[202]) );
FULL_ADDER FA_174 (.DATA_A (SUMMAND[252]) , .DATA_B (SUMMAND[253]) , .DATA_C (SUMMAND[254]) , .SAVE (INT_SUM[262]) , .CARRY (INT_CARRY[203]) );
FULL_ADDER FA_175 (.DATA_A (INT_SUM[258]) , .DATA_B (INT_SUM[259]) , .DATA_C (INT_SUM[260]) , .SAVE (INT_SUM[263]) , .CARRY (INT_CARRY[204]) );
FULL_ADDER FA_176 (.DATA_A (INT_SUM[261]) , .DATA_B (INT_SUM[262]) , .DATA_C (INT_CARRY[184]) , .SAVE (INT_SUM[264]) , .CARRY (INT_CARRY[205]) );
FULL_ADDER FA_177 (.DATA_A (INT_CARRY[185]) , .DATA_B (INT_CARRY[186]) , .DATA_C (INT_CARRY[187]) , .SAVE (INT_SUM[265]) , .CARRY (INT_CARRY[206]) );
assign INT_SUM[266] = INT_CARRY[188];
FULL_ADDER FA_178 (.DATA_A (INT_SUM[263]) , .DATA_B (INT_SUM[264]) , .DATA_C (INT_SUM[265]) , .SAVE (INT_SUM[267]) , .CARRY (INT_CARRY[207]) );
FULL_ADDER FA_179 (.DATA_A (INT_SUM[266]) , .DATA_B (INT_CARRY[189]) , .DATA_C (INT_CARRY[190]) , .SAVE (INT_SUM[268]) , .CARRY (INT_CARRY[208]) );
assign INT_SUM[269] = INT_CARRY[191];
FULL_ADDER FA_180 (.DATA_A (INT_SUM[267]) , .DATA_B (INT_SUM[268]) , .DATA_C (INT_SUM[269]) , .SAVE (INT_SUM[270]) , .CARRY (INT_CARRY[209]) );
HALF_ADDER HA_27 (.DATA_A (INT_CARRY[192]) , .DATA_B (INT_CARRY[193]) , .SAVE (INT_SUM[272]) , .CARRY (INT_CARRY[211]) );
FLIPFLOP LA_69 (.DIN (INT_SUM[270]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[271]) );
FLIPFLOP LA_70 (.DIN (INT_SUM[272]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[273]) );
FLIPFLOP LA_71 (.DIN (INT_CARRY[194]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[195]) );
FULL_ADDER FA_181 (.DATA_A (INT_SUM[271]) , .DATA_B (INT_SUM[273]) , .DATA_C (INT_CARRY[195]) , .SAVE (INT_SUM[274]) , .CARRY (INT_CARRY[213]) );
FLIPFLOP LA_72 (.DIN (INT_CARRY[196]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[197]) );
assign INT_SUM[275] = INT_CARRY[197];
FULL_ADDER FA_182 (.DATA_A (INT_SUM[274]) , .DATA_B (INT_SUM[275]) , .DATA_C (INT_CARRY[198]) , .SAVE (SUM[29]) , .CARRY (CARRY[29]) );
FULL_ADDER FA_183 (.DATA_A (SUMMAND[255]) , .DATA_B (SUMMAND[256]) , .DATA_C (SUMMAND[257]) , .SAVE (INT_SUM[276]) , .CARRY (INT_CARRY[214]) );
FULL_ADDER FA_184 (.DATA_A (SUMMAND[258]) , .DATA_B (SUMMAND[259]) , .DATA_C (SUMMAND[260]) , .SAVE (INT_SUM[277]) , .CARRY (INT_CARRY[215]) );
FULL_ADDER FA_185 (.DATA_A (SUMMAND[261]) , .DATA_B (SUMMAND[262]) , .DATA_C (SUMMAND[263]) , .SAVE (INT_SUM[278]) , .CARRY (INT_CARRY[216]) );
FULL_ADDER FA_186 (.DATA_A (SUMMAND[264]) , .DATA_B (SUMMAND[265]) , .DATA_C (SUMMAND[266]) , .SAVE (INT_SUM[279]) , .CARRY (INT_CARRY[217]) );
FULL_ADDER FA_187 (.DATA_A (SUMMAND[267]) , .DATA_B (SUMMAND[268]) , .DATA_C (SUMMAND[269]) , .SAVE (INT_SUM[280]) , .CARRY (INT_CARRY[218]) );
assign INT_SUM[281] = SUMMAND[270];
assign INT_SUM[282] = SUMMAND[271];
FULL_ADDER FA_188 (.DATA_A (INT_SUM[276]) , .DATA_B (INT_SUM[277]) , .DATA_C (INT_SUM[278]) , .SAVE (INT_SUM[283]) , .CARRY (INT_CARRY[219]) );
FULL_ADDER FA_189 (.DATA_A (INT_SUM[279]) , .DATA_B (INT_SUM[280]) , .DATA_C (INT_SUM[281]) , .SAVE (INT_SUM[284]) , .CARRY (INT_CARRY[220]) );
FULL_ADDER FA_190 (.DATA_A (INT_SUM[282]) , .DATA_B (INT_CARRY[199]) , .DATA_C (INT_CARRY[200]) , .SAVE (INT_SUM[285]) , .CARRY (INT_CARRY[221]) );
FULL_ADDER FA_191 (.DATA_A (INT_CARRY[201]) , .DATA_B (INT_CARRY[202]) , .DATA_C (INT_CARRY[203]) , .SAVE (INT_SUM[286]) , .CARRY (INT_CARRY[222]) );
FULL_ADDER FA_192 (.DATA_A (INT_SUM[283]) , .DATA_B (INT_SUM[284]) , .DATA_C (INT_SUM[285]) , .SAVE (INT_SUM[287]) , .CARRY (INT_CARRY[223]) );
FULL_ADDER FA_193 (.DATA_A (INT_SUM[286]) , .DATA_B (INT_CARRY[204]) , .DATA_C (INT_CARRY[205]) , .SAVE (INT_SUM[288]) , .CARRY (INT_CARRY[224]) );
assign INT_SUM[289] = INT_CARRY[206];
FULL_ADDER FA_194 (.DATA_A (INT_SUM[287]) , .DATA_B (INT_SUM[288]) , .DATA_C (INT_SUM[289]) , .SAVE (INT_SUM[290]) , .CARRY (INT_CARRY[225]) );
HALF_ADDER HA_28 (.DATA_A (INT_CARRY[207]) , .DATA_B (INT_CARRY[208]) , .SAVE (INT_SUM[292]) , .CARRY (INT_CARRY[227]) );
FLIPFLOP LA_73 (.DIN (INT_SUM[290]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[291]) );
FLIPFLOP LA_74 (.DIN (INT_SUM[292]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[293]) );
FLIPFLOP LA_75 (.DIN (INT_CARRY[209]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[210]) );
FULL_ADDER FA_195 (.DATA_A (INT_SUM[291]) , .DATA_B (INT_SUM[293]) , .DATA_C (INT_CARRY[210]) , .SAVE (INT_SUM[294]) , .CARRY (INT_CARRY[229]) );
FLIPFLOP LA_76 (.DIN (INT_CARRY[211]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[212]) );
assign INT_SUM[295] = INT_CARRY[212];
FULL_ADDER FA_196 (.DATA_A (INT_SUM[294]) , .DATA_B (INT_SUM[295]) , .DATA_C (INT_CARRY[213]) , .SAVE (SUM[30]) , .CARRY (CARRY[30]) );
FULL_ADDER FA_197 (.DATA_A (SUMMAND[272]) , .DATA_B (SUMMAND[273]) , .DATA_C (SUMMAND[274]) , .SAVE (INT_SUM[296]) , .CARRY (INT_CARRY[230]) );
FULL_ADDER FA_198 (.DATA_A (SUMMAND[275]) , .DATA_B (SUMMAND[276]) , .DATA_C (SUMMAND[277]) , .SAVE (INT_SUM[297]) , .CARRY (INT_CARRY[231]) );
FULL_ADDER FA_199 (.DATA_A (SUMMAND[278]) , .DATA_B (SUMMAND[279]) , .DATA_C (SUMMAND[280]) , .SAVE (INT_SUM[298]) , .CARRY (INT_CARRY[232]) );
FULL_ADDER FA_200 (.DATA_A (SUMMAND[281]) , .DATA_B (SUMMAND[282]) , .DATA_C (SUMMAND[283]) , .SAVE (INT_SUM[299]) , .CARRY (INT_CARRY[233]) );
FULL_ADDER FA_201 (.DATA_A (SUMMAND[284]) , .DATA_B (SUMMAND[285]) , .DATA_C (SUMMAND[286]) , .SAVE (INT_SUM[300]) , .CARRY (INT_CARRY[234]) );
assign INT_SUM[301] = SUMMAND[287];
FULL_ADDER FA_202 (.DATA_A (INT_SUM[296]) , .DATA_B (INT_SUM[297]) , .DATA_C (INT_SUM[298]) , .SAVE (INT_SUM[302]) , .CARRY (INT_CARRY[235]) );
FULL_ADDER FA_203 (.DATA_A (INT_SUM[299]) , .DATA_B (INT_SUM[300]) , .DATA_C (INT_SUM[301]) , .SAVE (INT_SUM[303]) , .CARRY (INT_CARRY[236]) );
FULL_ADDER FA_204 (.DATA_A (INT_CARRY[214]) , .DATA_B (INT_CARRY[215]) , .DATA_C (INT_CARRY[216]) , .SAVE (INT_SUM[304]) , .CARRY (INT_CARRY[237]) );
assign INT_SUM[305] = INT_CARRY[217];
assign INT_SUM[306] = INT_CARRY[218];
FULL_ADDER FA_205 (.DATA_A (INT_SUM[302]) , .DATA_B (INT_SUM[303]) , .DATA_C (INT_SUM[304]) , .SAVE (INT_SUM[307]) , .CARRY (INT_CARRY[238]) );
FULL_ADDER FA_206 (.DATA_A (INT_SUM[305]) , .DATA_B (INT_SUM[306]) , .DATA_C (INT_CARRY[219]) , .SAVE (INT_SUM[308]) , .CARRY (INT_CARRY[239]) );
FULL_ADDER FA_207 (.DATA_A (INT_CARRY[220]) , .DATA_B (INT_CARRY[221]) , .DATA_C (INT_CARRY[222]) , .SAVE (INT_SUM[309]) , .CARRY (INT_CARRY[240]) );
FULL_ADDER FA_208 (.DATA_A (INT_SUM[307]) , .DATA_B (INT_SUM[308]) , .DATA_C (INT_SUM[309]) , .SAVE (INT_SUM[310]) , .CARRY (INT_CARRY[241]) );
HALF_ADDER HA_29 (.DATA_A (INT_CARRY[223]) , .DATA_B (INT_CARRY[224]) , .SAVE (INT_SUM[312]) , .CARRY (INT_CARRY[243]) );
FLIPFLOP LA_77 (.DIN (INT_SUM[310]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[311]) );
FLIPFLOP LA_78 (.DIN (INT_SUM[312]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[313]) );
FLIPFLOP LA_79 (.DIN (INT_CARRY[225]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[226]) );
FULL_ADDER FA_209 (.DATA_A (INT_SUM[311]) , .DATA_B (INT_SUM[313]) , .DATA_C (INT_CARRY[226]) , .SAVE (INT_SUM[314]) , .CARRY (INT_CARRY[245]) );
FLIPFLOP LA_80 (.DIN (INT_CARRY[227]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[228]) );
assign INT_SUM[315] = INT_CARRY[228];
FULL_ADDER FA_210 (.DATA_A (INT_SUM[314]) , .DATA_B (INT_SUM[315]) , .DATA_C (INT_CARRY[229]) , .SAVE (SUM[31]) , .CARRY (CARRY[31]) );
FULL_ADDER FA_211 (.DATA_A (SUMMAND[288]) , .DATA_B (SUMMAND[289]) , .DATA_C (SUMMAND[290]) , .SAVE (INT_SUM[316]) , .CARRY (INT_CARRY[246]) );
FULL_ADDER FA_212 (.DATA_A (SUMMAND[291]) , .DATA_B (SUMMAND[292]) , .DATA_C (SUMMAND[293]) , .SAVE (INT_SUM[317]) , .CARRY (INT_CARRY[247]) );
FULL_ADDER FA_213 (.DATA_A (SUMMAND[294]) , .DATA_B (SUMMAND[295]) , .DATA_C (SUMMAND[296]) , .SAVE (INT_SUM[318]) , .CARRY (INT_CARRY[248]) );
FULL_ADDER FA_214 (.DATA_A (SUMMAND[297]) , .DATA_B (SUMMAND[298]) , .DATA_C (SUMMAND[299]) , .SAVE (INT_SUM[319]) , .CARRY (INT_CARRY[249]) );
FULL_ADDER FA_215 (.DATA_A (SUMMAND[300]) , .DATA_B (SUMMAND[301]) , .DATA_C (SUMMAND[302]) , .SAVE (INT_SUM[320]) , .CARRY (INT_CARRY[250]) );
assign INT_SUM[321] = SUMMAND[303];
FULL_ADDER FA_216 (.DATA_A (INT_SUM[316]) , .DATA_B (INT_SUM[317]) , .DATA_C (INT_SUM[318]) , .SAVE (INT_SUM[322]) , .CARRY (INT_CARRY[251]) );
FULL_ADDER FA_217 (.DATA_A (INT_SUM[319]) , .DATA_B (INT_SUM[320]) , .DATA_C (INT_SUM[321]) , .SAVE (INT_SUM[323]) , .CARRY (INT_CARRY[252]) );
FULL_ADDER FA_218 (.DATA_A (INT_CARRY[230]) , .DATA_B (INT_CARRY[231]) , .DATA_C (INT_CARRY[232]) , .SAVE (INT_SUM[324]) , .CARRY (INT_CARRY[253]) );
HALF_ADDER HA_30 (.DATA_A (INT_CARRY[233]) , .DATA_B (INT_CARRY[234]) , .SAVE (INT_SUM[325]) , .CARRY (INT_CARRY[254]) );
FULL_ADDER FA_219 (.DATA_A (INT_SUM[322]) , .DATA_B (INT_SUM[323]) , .DATA_C (INT_SUM[324]) , .SAVE (INT_SUM[326]) , .CARRY (INT_CARRY[255]) );
FULL_ADDER FA_220 (.DATA_A (INT_SUM[325]) , .DATA_B (INT_CARRY[235]) , .DATA_C (INT_CARRY[236]) , .SAVE (INT_SUM[327]) , .CARRY (INT_CARRY[256]) );
assign INT_SUM[328] = INT_CARRY[237];
FULL_ADDER FA_221 (.DATA_A (INT_SUM[326]) , .DATA_B (INT_SUM[327]) , .DATA_C (INT_SUM[328]) , .SAVE (INT_SUM[329]) , .CARRY (INT_CARRY[257]) );
FULL_ADDER FA_222 (.DATA_A (INT_CARRY[238]) , .DATA_B (INT_CARRY[239]) , .DATA_C (INT_CARRY[240]) , .SAVE (INT_SUM[331]) , .CARRY (INT_CARRY[259]) );
FLIPFLOP LA_81 (.DIN (INT_SUM[329]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[330]) );
FLIPFLOP LA_82 (.DIN (INT_SUM[331]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[332]) );
FLIPFLOP LA_83 (.DIN (INT_CARRY[241]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[242]) );
FULL_ADDER FA_223 (.DATA_A (INT_SUM[330]) , .DATA_B (INT_SUM[332]) , .DATA_C (INT_CARRY[242]) , .SAVE (INT_SUM[333]) , .CARRY (INT_CARRY[261]) );
FLIPFLOP LA_84 (.DIN (INT_CARRY[243]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[244]) );
assign INT_SUM[334] = INT_CARRY[244];
FULL_ADDER FA_224 (.DATA_A (INT_SUM[333]) , .DATA_B (INT_SUM[334]) , .DATA_C (INT_CARRY[245]) , .SAVE (SUM[32]) , .CARRY (CARRY[32]) );
FULL_ADDER FA_225 (.DATA_A (SUMMAND[304]) , .DATA_B (SUMMAND[305]) , .DATA_C (SUMMAND[306]) , .SAVE (INT_SUM[335]) , .CARRY (INT_CARRY[262]) );
FULL_ADDER FA_226 (.DATA_A (SUMMAND[307]) , .DATA_B (SUMMAND[308]) , .DATA_C (SUMMAND[309]) , .SAVE (INT_SUM[336]) , .CARRY (INT_CARRY[263]) );
FULL_ADDER FA_227 (.DATA_A (SUMMAND[310]) , .DATA_B (SUMMAND[311]) , .DATA_C (SUMMAND[312]) , .SAVE (INT_SUM[337]) , .CARRY (INT_CARRY[264]) );
FULL_ADDER FA_228 (.DATA_A (SUMMAND[313]) , .DATA_B (SUMMAND[314]) , .DATA_C (SUMMAND[315]) , .SAVE (INT_SUM[338]) , .CARRY (INT_CARRY[265]) );
FULL_ADDER FA_229 (.DATA_A (SUMMAND[316]) , .DATA_B (SUMMAND[317]) , .DATA_C (SUMMAND[318]) , .SAVE (INT_SUM[339]) , .CARRY (INT_CARRY[266]) );
assign INT_SUM[340] = SUMMAND[319];
assign INT_SUM[341] = SUMMAND[320];
FULL_ADDER FA_230 (.DATA_A (INT_SUM[335]) , .DATA_B (INT_SUM[336]) , .DATA_C (INT_SUM[337]) , .SAVE (INT_SUM[342]) , .CARRY (INT_CARRY[267]) );
FULL_ADDER FA_231 (.DATA_A (INT_SUM[338]) , .DATA_B (INT_SUM[339]) , .DATA_C (INT_SUM[340]) , .SAVE (INT_SUM[343]) , .CARRY (INT_CARRY[268]) );
FULL_ADDER FA_232 (.DATA_A (INT_SUM[341]) , .DATA_B (INT_CARRY[246]) , .DATA_C (INT_CARRY[247]) , .SAVE (INT_SUM[344]) , .CARRY (INT_CARRY[269]) );
FULL_ADDER FA_233 (.DATA_A (INT_CARRY[248]) , .DATA_B (INT_CARRY[249]) , .DATA_C (INT_CARRY[250]) , .SAVE (INT_SUM[345]) , .CARRY (INT_CARRY[270]) );
FULL_ADDER FA_234 (.DATA_A (INT_SUM[342]) , .DATA_B (INT_SUM[343]) , .DATA_C (INT_SUM[344]) , .SAVE (INT_SUM[346]) , .CARRY (INT_CARRY[271]) );
FULL_ADDER FA_235 (.DATA_A (INT_SUM[345]) , .DATA_B (INT_CARRY[251]) , .DATA_C (INT_CARRY[252]) , .SAVE (INT_SUM[347]) , .CARRY (INT_CARRY[272]) );
assign INT_SUM[348] = INT_CARRY[253];
assign INT_SUM[349] = INT_CARRY[254];
FULL_ADDER FA_236 (.DATA_A (INT_SUM[346]) , .DATA_B (INT_SUM[347]) , .DATA_C (INT_SUM[348]) , .SAVE (INT_SUM[350]) , .CARRY (INT_CARRY[273]) );
FULL_ADDER FA_237 (.DATA_A (INT_SUM[349]) , .DATA_B (INT_CARRY[255]) , .DATA_C (INT_CARRY[256]) , .SAVE (INT_SUM[352]) , .CARRY (INT_CARRY[275]) );
FLIPFLOP LA_85 (.DIN (INT_SUM[350]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[351]) );
FLIPFLOP LA_86 (.DIN (INT_SUM[352]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[353]) );
FLIPFLOP LA_87 (.DIN (INT_CARRY[257]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[258]) );
FULL_ADDER FA_238 (.DATA_A (INT_SUM[351]) , .DATA_B (INT_SUM[353]) , .DATA_C (INT_CARRY[258]) , .SAVE (INT_SUM[354]) , .CARRY (INT_CARRY[277]) );
FLIPFLOP LA_88 (.DIN (INT_CARRY[259]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[260]) );
assign INT_SUM[355] = INT_CARRY[260];
FULL_ADDER FA_239 (.DATA_A (INT_SUM[354]) , .DATA_B (INT_SUM[355]) , .DATA_C (INT_CARRY[261]) , .SAVE (SUM[33]) , .CARRY (CARRY[33]) );
FULL_ADDER FA_240 (.DATA_A (SUMMAND[321]) , .DATA_B (SUMMAND[322]) , .DATA_C (SUMMAND[323]) , .SAVE (INT_SUM[356]) , .CARRY (INT_CARRY[278]) );
FULL_ADDER FA_241 (.DATA_A (SUMMAND[324]) , .DATA_B (SUMMAND[325]) , .DATA_C (SUMMAND[326]) , .SAVE (INT_SUM[357]) , .CARRY (INT_CARRY[279]) );
FULL_ADDER FA_242 (.DATA_A (SUMMAND[327]) , .DATA_B (SUMMAND[328]) , .DATA_C (SUMMAND[329]) , .SAVE (INT_SUM[358]) , .CARRY (INT_CARRY[280]) );
FULL_ADDER FA_243 (.DATA_A (SUMMAND[330]) , .DATA_B (SUMMAND[331]) , .DATA_C (SUMMAND[332]) , .SAVE (INT_SUM[359]) , .CARRY (INT_CARRY[281]) );
FULL_ADDER FA_244 (.DATA_A (SUMMAND[333]) , .DATA_B (SUMMAND[334]) , .DATA_C (SUMMAND[335]) , .SAVE (INT_SUM[360]) , .CARRY (INT_CARRY[282]) );
assign INT_SUM[361] = SUMMAND[336];
FULL_ADDER FA_245 (.DATA_A (INT_SUM[356]) , .DATA_B (INT_SUM[357]) , .DATA_C (INT_SUM[358]) , .SAVE (INT_SUM[362]) , .CARRY (INT_CARRY[283]) );
FULL_ADDER FA_246 (.DATA_A (INT_SUM[359]) , .DATA_B (INT_SUM[360]) , .DATA_C (INT_SUM[361]) , .SAVE (INT_SUM[363]) , .CARRY (INT_CARRY[284]) );
FULL_ADDER FA_247 (.DATA_A (INT_CARRY[262]) , .DATA_B (INT_CARRY[263]) , .DATA_C (INT_CARRY[264]) , .SAVE (INT_SUM[364]) , .CARRY (INT_CARRY[285]) );
assign INT_SUM[365] = INT_CARRY[265];
assign INT_SUM[366] = INT_CARRY[266];
FULL_ADDER FA_248 (.DATA_A (INT_SUM[362]) , .DATA_B (INT_SUM[363]) , .DATA_C (INT_SUM[364]) , .SAVE (INT_SUM[367]) , .CARRY (INT_CARRY[286]) );
FULL_ADDER FA_249 (.DATA_A (INT_SUM[365]) , .DATA_B (INT_SUM[366]) , .DATA_C (INT_CARRY[267]) , .SAVE (INT_SUM[368]) , .CARRY (INT_CARRY[287]) );
FULL_ADDER FA_250 (.DATA_A (INT_CARRY[268]) , .DATA_B (INT_CARRY[269]) , .DATA_C (INT_CARRY[270]) , .SAVE (INT_SUM[369]) , .CARRY (INT_CARRY[288]) );
FULL_ADDER FA_251 (.DATA_A (INT_SUM[367]) , .DATA_B (INT_SUM[368]) , .DATA_C (INT_SUM[369]) , .SAVE (INT_SUM[370]) , .CARRY (INT_CARRY[289]) );
HALF_ADDER HA_31 (.DATA_A (INT_CARRY[271]) , .DATA_B (INT_CARRY[272]) , .SAVE (INT_SUM[372]) , .CARRY (INT_CARRY[291]) );
FLIPFLOP LA_89 (.DIN (INT_SUM[370]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[371]) );
FLIPFLOP LA_90 (.DIN (INT_SUM[372]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[373]) );
FLIPFLOP LA_91 (.DIN (INT_CARRY[273]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[274]) );
FULL_ADDER FA_252 (.DATA_A (INT_SUM[371]) , .DATA_B (INT_SUM[373]) , .DATA_C (INT_CARRY[274]) , .SAVE (INT_SUM[374]) , .CARRY (INT_CARRY[293]) );
FLIPFLOP LA_92 (.DIN (INT_CARRY[275]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[276]) );
assign INT_SUM[375] = INT_CARRY[276];
FULL_ADDER FA_253 (.DATA_A (INT_SUM[374]) , .DATA_B (INT_SUM[375]) , .DATA_C (INT_CARRY[277]) , .SAVE (SUM[34]) , .CARRY (CARRY[34]) );
FULL_ADDER FA_254 (.DATA_A (SUMMAND[337]) , .DATA_B (SUMMAND[338]) , .DATA_C (SUMMAND[339]) , .SAVE (INT_SUM[376]) , .CARRY (INT_CARRY[294]) );
FULL_ADDER FA_255 (.DATA_A (SUMMAND[340]) , .DATA_B (SUMMAND[341]) , .DATA_C (SUMMAND[342]) , .SAVE (INT_SUM[377]) , .CARRY (INT_CARRY[295]) );
FULL_ADDER FA_256 (.DATA_A (SUMMAND[343]) , .DATA_B (SUMMAND[344]) , .DATA_C (SUMMAND[345]) , .SAVE (INT_SUM[378]) , .CARRY (INT_CARRY[296]) );
FULL_ADDER FA_257 (.DATA_A (SUMMAND[346]) , .DATA_B (SUMMAND[347]) , .DATA_C (SUMMAND[348]) , .SAVE (INT_SUM[379]) , .CARRY (INT_CARRY[297]) );
FULL_ADDER FA_258 (.DATA_A (SUMMAND[349]) , .DATA_B (SUMMAND[350]) , .DATA_C (SUMMAND[351]) , .SAVE (INT_SUM[380]) , .CARRY (INT_CARRY[298]) );
FULL_ADDER FA_259 (.DATA_A (INT_SUM[376]) , .DATA_B (INT_SUM[377]) , .DATA_C (INT_SUM[378]) , .SAVE (INT_SUM[381]) , .CARRY (INT_CARRY[299]) );
FULL_ADDER FA_260 (.DATA_A (INT_SUM[379]) , .DATA_B (INT_SUM[380]) , .DATA_C (INT_CARRY[278]) , .SAVE (INT_SUM[382]) , .CARRY (INT_CARRY[300]) );
FULL_ADDER FA_261 (.DATA_A (INT_CARRY[279]) , .DATA_B (INT_CARRY[280]) , .DATA_C (INT_CARRY[281]) , .SAVE (INT_SUM[383]) , .CARRY (INT_CARRY[301]) );
assign INT_SUM[384] = INT_CARRY[282];
FULL_ADDER FA_262 (.DATA_A (INT_SUM[381]) , .DATA_B (INT_SUM[382]) , .DATA_C (INT_SUM[383]) , .SAVE (INT_SUM[385]) , .CARRY (INT_CARRY[302]) );
FULL_ADDER FA_263 (.DATA_A (INT_SUM[384]) , .DATA_B (INT_CARRY[283]) , .DATA_C (INT_CARRY[284]) , .SAVE (INT_SUM[386]) , .CARRY (INT_CARRY[303]) );
assign INT_SUM[387] = INT_CARRY[285];
FULL_ADDER FA_264 (.DATA_A (INT_SUM[385]) , .DATA_B (INT_SUM[386]) , .DATA_C (INT_SUM[387]) , .SAVE (INT_SUM[388]) , .CARRY (INT_CARRY[304]) );
FULL_ADDER FA_265 (.DATA_A (INT_CARRY[286]) , .DATA_B (INT_CARRY[287]) , .DATA_C (INT_CARRY[288]) , .SAVE (INT_SUM[390]) , .CARRY (INT_CARRY[306]) );
FLIPFLOP LA_93 (.DIN (INT_SUM[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[389]) );
FLIPFLOP LA_94 (.DIN (INT_SUM[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[391]) );
FLIPFLOP LA_95 (.DIN (INT_CARRY[289]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[290]) );
FULL_ADDER FA_266 (.DATA_A (INT_SUM[389]) , .DATA_B (INT_SUM[391]) , .DATA_C (INT_CARRY[290]) , .SAVE (INT_SUM[392]) , .CARRY (INT_CARRY[308]) );
FLIPFLOP LA_96 (.DIN (INT_CARRY[291]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[292]) );
assign INT_SUM[393] = INT_CARRY[292];
FULL_ADDER FA_267 (.DATA_A (INT_SUM[392]) , .DATA_B (INT_SUM[393]) , .DATA_C (INT_CARRY[293]) , .SAVE (SUM[35]) , .CARRY (CARRY[35]) );
FULL_ADDER FA_268 (.DATA_A (SUMMAND[352]) , .DATA_B (SUMMAND[353]) , .DATA_C (SUMMAND[354]) , .SAVE (INT_SUM[394]) , .CARRY (INT_CARRY[309]) );
FULL_ADDER FA_269 (.DATA_A (SUMMAND[355]) , .DATA_B (SUMMAND[356]) , .DATA_C (SUMMAND[357]) , .SAVE (INT_SUM[395]) , .CARRY (INT_CARRY[310]) );
FULL_ADDER FA_270 (.DATA_A (SUMMAND[358]) , .DATA_B (SUMMAND[359]) , .DATA_C (SUMMAND[360]) , .SAVE (INT_SUM[396]) , .CARRY (INT_CARRY[311]) );
FULL_ADDER FA_271 (.DATA_A (SUMMAND[361]) , .DATA_B (SUMMAND[362]) , .DATA_C (SUMMAND[363]) , .SAVE (INT_SUM[397]) , .CARRY (INT_CARRY[312]) );
FULL_ADDER FA_272 (.DATA_A (SUMMAND[364]) , .DATA_B (SUMMAND[365]) , .DATA_C (SUMMAND[366]) , .SAVE (INT_SUM[398]) , .CARRY (INT_CARRY[313]) );
FULL_ADDER FA_273 (.DATA_A (INT_SUM[394]) , .DATA_B (INT_SUM[395]) , .DATA_C (INT_SUM[396]) , .SAVE (INT_SUM[399]) , .CARRY (INT_CARRY[314]) );
FULL_ADDER FA_274 (.DATA_A (INT_SUM[397]) , .DATA_B (INT_SUM[398]) , .DATA_C (INT_CARRY[294]) , .SAVE (INT_SUM[400]) , .CARRY (INT_CARRY[315]) );
FULL_ADDER FA_275 (.DATA_A (INT_CARRY[295]) , .DATA_B (INT_CARRY[296]) , .DATA_C (INT_CARRY[297]) , .SAVE (INT_SUM[401]) , .CARRY (INT_CARRY[316]) );
assign INT_SUM[402] = INT_CARRY[298];
FULL_ADDER FA_276 (.DATA_A (INT_SUM[399]) , .DATA_B (INT_SUM[400]) , .DATA_C (INT_SUM[401]) , .SAVE (INT_SUM[403]) , .CARRY (INT_CARRY[317]) );
FULL_ADDER FA_277 (.DATA_A (INT_SUM[402]) , .DATA_B (INT_CARRY[299]) , .DATA_C (INT_CARRY[300]) , .SAVE (INT_SUM[404]) , .CARRY (INT_CARRY[318]) );
assign INT_SUM[405] = INT_CARRY[301];
FULL_ADDER FA_278 (.DATA_A (INT_SUM[403]) , .DATA_B (INT_SUM[404]) , .DATA_C (INT_SUM[405]) , .SAVE (INT_SUM[406]) , .CARRY (INT_CARRY[319]) );
HALF_ADDER HA_32 (.DATA_A (INT_CARRY[302]) , .DATA_B (INT_CARRY[303]) , .SAVE (INT_SUM[408]) , .CARRY (INT_CARRY[321]) );
FLIPFLOP LA_97 (.DIN (INT_SUM[406]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[407]) );
FLIPFLOP LA_98 (.DIN (INT_SUM[408]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[409]) );
FLIPFLOP LA_99 (.DIN (INT_CARRY[304]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[305]) );
FULL_ADDER FA_279 (.DATA_A (INT_SUM[407]) , .DATA_B (INT_SUM[409]) , .DATA_C (INT_CARRY[305]) , .SAVE (INT_SUM[410]) , .CARRY (INT_CARRY[323]) );
FLIPFLOP LA_100 (.DIN (INT_CARRY[306]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[307]) );
assign INT_SUM[411] = INT_CARRY[307];
FULL_ADDER FA_280 (.DATA_A (INT_SUM[410]) , .DATA_B (INT_SUM[411]) , .DATA_C (INT_CARRY[308]) , .SAVE (SUM[36]) , .CARRY (CARRY[36]) );
FULL_ADDER FA_281 (.DATA_A (SUMMAND[367]) , .DATA_B (SUMMAND[368]) , .DATA_C (SUMMAND[369]) , .SAVE (INT_SUM[412]) , .CARRY (INT_CARRY[324]) );
FULL_ADDER FA_282 (.DATA_A (SUMMAND[370]) , .DATA_B (SUMMAND[371]) , .DATA_C (SUMMAND[372]) , .SAVE (INT_SUM[413]) , .CARRY (INT_CARRY[325]) );
FULL_ADDER FA_283 (.DATA_A (SUMMAND[373]) , .DATA_B (SUMMAND[374]) , .DATA_C (SUMMAND[375]) , .SAVE (INT_SUM[414]) , .CARRY (INT_CARRY[326]) );
FULL_ADDER FA_284 (.DATA_A (SUMMAND[376]) , .DATA_B (SUMMAND[377]) , .DATA_C (SUMMAND[378]) , .SAVE (INT_SUM[415]) , .CARRY (INT_CARRY[327]) );
HALF_ADDER HA_33 (.DATA_A (SUMMAND[379]) , .DATA_B (SUMMAND[380]) , .SAVE (INT_SUM[416]) , .CARRY (INT_CARRY[328]) );
FULL_ADDER FA_285 (.DATA_A (INT_SUM[412]) , .DATA_B (INT_SUM[413]) , .DATA_C (INT_SUM[414]) , .SAVE (INT_SUM[417]) , .CARRY (INT_CARRY[329]) );
FULL_ADDER FA_286 (.DATA_A (INT_SUM[415]) , .DATA_B (INT_SUM[416]) , .DATA_C (INT_CARRY[309]) , .SAVE (INT_SUM[418]) , .CARRY (INT_CARRY[330]) );
FULL_ADDER FA_287 (.DATA_A (INT_CARRY[310]) , .DATA_B (INT_CARRY[311]) , .DATA_C (INT_CARRY[312]) , .SAVE (INT_SUM[419]) , .CARRY (INT_CARRY[331]) );
assign INT_SUM[420] = INT_CARRY[313];
FULL_ADDER FA_288 (.DATA_A (INT_SUM[417]) , .DATA_B (INT_SUM[418]) , .DATA_C (INT_SUM[419]) , .SAVE (INT_SUM[421]) , .CARRY (INT_CARRY[332]) );
FULL_ADDER FA_289 (.DATA_A (INT_SUM[420]) , .DATA_B (INT_CARRY[314]) , .DATA_C (INT_CARRY[315]) , .SAVE (INT_SUM[422]) , .CARRY (INT_CARRY[333]) );
assign INT_SUM[423] = INT_CARRY[316];
FULL_ADDER FA_290 (.DATA_A (INT_SUM[421]) , .DATA_B (INT_SUM[422]) , .DATA_C (INT_SUM[423]) , .SAVE (INT_SUM[424]) , .CARRY (INT_CARRY[334]) );
HALF_ADDER HA_34 (.DATA_A (INT_CARRY[317]) , .DATA_B (INT_CARRY[318]) , .SAVE (INT_SUM[426]) , .CARRY (INT_CARRY[336]) );
FLIPFLOP LA_101 (.DIN (INT_SUM[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[425]) );
FLIPFLOP LA_102 (.DIN (INT_SUM[426]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[427]) );
FLIPFLOP LA_103 (.DIN (INT_CARRY[319]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[320]) );
FULL_ADDER FA_291 (.DATA_A (INT_SUM[425]) , .DATA_B (INT_SUM[427]) , .DATA_C (INT_CARRY[320]) , .SAVE (INT_SUM[428]) , .CARRY (INT_CARRY[338]) );
FLIPFLOP LA_104 (.DIN (INT_CARRY[321]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[322]) );
assign INT_SUM[429] = INT_CARRY[322];
FULL_ADDER FA_292 (.DATA_A (INT_SUM[428]) , .DATA_B (INT_SUM[429]) , .DATA_C (INT_CARRY[323]) , .SAVE (SUM[37]) , .CARRY (CARRY[37]) );
FULL_ADDER FA_293 (.DATA_A (SUMMAND[381]) , .DATA_B (SUMMAND[382]) , .DATA_C (SUMMAND[383]) , .SAVE (INT_SUM[430]) , .CARRY (INT_CARRY[339]) );
FULL_ADDER FA_294 (.DATA_A (SUMMAND[384]) , .DATA_B (SUMMAND[385]) , .DATA_C (SUMMAND[386]) , .SAVE (INT_SUM[431]) , .CARRY (INT_CARRY[340]) );
FULL_ADDER FA_295 (.DATA_A (SUMMAND[387]) , .DATA_B (SUMMAND[388]) , .DATA_C (SUMMAND[389]) , .SAVE (INT_SUM[432]) , .CARRY (INT_CARRY[341]) );
FULL_ADDER FA_296 (.DATA_A (SUMMAND[390]) , .DATA_B (SUMMAND[391]) , .DATA_C (SUMMAND[392]) , .SAVE (INT_SUM[433]) , .CARRY (INT_CARRY[342]) );
HALF_ADDER HA_35 (.DATA_A (SUMMAND[393]) , .DATA_B (SUMMAND[394]) , .SAVE (INT_SUM[434]) , .CARRY (INT_CARRY[343]) );
FULL_ADDER FA_297 (.DATA_A (INT_SUM[430]) , .DATA_B (INT_SUM[431]) , .DATA_C (INT_SUM[432]) , .SAVE (INT_SUM[435]) , .CARRY (INT_CARRY[344]) );
FULL_ADDER FA_298 (.DATA_A (INT_SUM[433]) , .DATA_B (INT_SUM[434]) , .DATA_C (INT_CARRY[324]) , .SAVE (INT_SUM[436]) , .CARRY (INT_CARRY[345]) );
FULL_ADDER FA_299 (.DATA_A (INT_CARRY[325]) , .DATA_B (INT_CARRY[326]) , .DATA_C (INT_CARRY[327]) , .SAVE (INT_SUM[437]) , .CARRY (INT_CARRY[346]) );
assign INT_SUM[438] = INT_CARRY[328];
FULL_ADDER FA_300 (.DATA_A (INT_SUM[435]) , .DATA_B (INT_SUM[436]) , .DATA_C (INT_SUM[437]) , .SAVE (INT_SUM[439]) , .CARRY (INT_CARRY[347]) );
FULL_ADDER FA_301 (.DATA_A (INT_SUM[438]) , .DATA_B (INT_CARRY[329]) , .DATA_C (INT_CARRY[330]) , .SAVE (INT_SUM[440]) , .CARRY (INT_CARRY[348]) );
assign INT_SUM[441] = INT_CARRY[331];
FULL_ADDER FA_302 (.DATA_A (INT_SUM[439]) , .DATA_B (INT_SUM[440]) , .DATA_C (INT_SUM[441]) , .SAVE (INT_SUM[442]) , .CARRY (INT_CARRY[349]) );
HALF_ADDER HA_36 (.DATA_A (INT_CARRY[332]) , .DATA_B (INT_CARRY[333]) , .SAVE (INT_SUM[444]) , .CARRY (INT_CARRY[351]) );
FLIPFLOP LA_105 (.DIN (INT_SUM[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[443]) );
FLIPFLOP LA_106 (.DIN (INT_SUM[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[445]) );
FLIPFLOP LA_107 (.DIN (INT_CARRY[334]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[335]) );
FULL_ADDER FA_303 (.DATA_A (INT_SUM[443]) , .DATA_B (INT_SUM[445]) , .DATA_C (INT_CARRY[335]) , .SAVE (INT_SUM[446]) , .CARRY (INT_CARRY[353]) );
FLIPFLOP LA_108 (.DIN (INT_CARRY[336]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[337]) );
assign INT_SUM[447] = INT_CARRY[337];
FULL_ADDER FA_304 (.DATA_A (INT_SUM[446]) , .DATA_B (INT_SUM[447]) , .DATA_C (INT_CARRY[338]) , .SAVE (SUM[38]) , .CARRY (CARRY[38]) );
FULL_ADDER FA_305 (.DATA_A (SUMMAND[395]) , .DATA_B (SUMMAND[396]) , .DATA_C (SUMMAND[397]) , .SAVE (INT_SUM[448]) , .CARRY (INT_CARRY[354]) );
FULL_ADDER FA_306 (.DATA_A (SUMMAND[398]) , .DATA_B (SUMMAND[399]) , .DATA_C (SUMMAND[400]) , .SAVE (INT_SUM[449]) , .CARRY (INT_CARRY[355]) );
FULL_ADDER FA_307 (.DATA_A (SUMMAND[401]) , .DATA_B (SUMMAND[402]) , .DATA_C (SUMMAND[403]) , .SAVE (INT_SUM[450]) , .CARRY (INT_CARRY[356]) );
FULL_ADDER FA_308 (.DATA_A (SUMMAND[404]) , .DATA_B (SUMMAND[405]) , .DATA_C (SUMMAND[406]) , .SAVE (INT_SUM[451]) , .CARRY (INT_CARRY[357]) );
assign INT_SUM[452] = SUMMAND[407];
FULL_ADDER FA_309 (.DATA_A (INT_SUM[448]) , .DATA_B (INT_SUM[449]) , .DATA_C (INT_SUM[450]) , .SAVE (INT_SUM[453]) , .CARRY (INT_CARRY[358]) );
FULL_ADDER FA_310 (.DATA_A (INT_SUM[451]) , .DATA_B (INT_SUM[452]) , .DATA_C (INT_CARRY[339]) , .SAVE (INT_SUM[454]) , .CARRY (INT_CARRY[359]) );
FULL_ADDER FA_311 (.DATA_A (INT_CARRY[340]) , .DATA_B (INT_CARRY[341]) , .DATA_C (INT_CARRY[342]) , .SAVE (INT_SUM[455]) , .CARRY (INT_CARRY[360]) );
assign INT_SUM[456] = INT_CARRY[343];
FULL_ADDER FA_312 (.DATA_A (INT_SUM[453]) , .DATA_B (INT_SUM[454]) , .DATA_C (INT_SUM[455]) , .SAVE (INT_SUM[457]) , .CARRY (INT_CARRY[361]) );
FULL_ADDER FA_313 (.DATA_A (INT_SUM[456]) , .DATA_B (INT_CARRY[344]) , .DATA_C (INT_CARRY[345]) , .SAVE (INT_SUM[458]) , .CARRY (INT_CARRY[362]) );
assign INT_SUM[459] = INT_CARRY[346];
FULL_ADDER FA_314 (.DATA_A (INT_SUM[457]) , .DATA_B (INT_SUM[458]) , .DATA_C (INT_SUM[459]) , .SAVE (INT_SUM[460]) , .CARRY (INT_CARRY[363]) );
HALF_ADDER HA_37 (.DATA_A (INT_CARRY[347]) , .DATA_B (INT_CARRY[348]) , .SAVE (INT_SUM[462]) , .CARRY (INT_CARRY[365]) );
FLIPFLOP LA_109 (.DIN (INT_SUM[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[461]) );
FLIPFLOP LA_110 (.DIN (INT_SUM[462]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[463]) );
FLIPFLOP LA_111 (.DIN (INT_CARRY[349]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[350]) );
FULL_ADDER FA_315 (.DATA_A (INT_SUM[461]) , .DATA_B (INT_SUM[463]) , .DATA_C (INT_CARRY[350]) , .SAVE (INT_SUM[464]) , .CARRY (INT_CARRY[367]) );
FLIPFLOP LA_112 (.DIN (INT_CARRY[351]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[352]) );
assign INT_SUM[465] = INT_CARRY[352];
FULL_ADDER FA_316 (.DATA_A (INT_SUM[464]) , .DATA_B (INT_SUM[465]) , .DATA_C (INT_CARRY[353]) , .SAVE (SUM[39]) , .CARRY (CARRY[39]) );
FULL_ADDER FA_317 (.DATA_A (SUMMAND[408]) , .DATA_B (SUMMAND[409]) , .DATA_C (SUMMAND[410]) , .SAVE (INT_SUM[466]) , .CARRY (INT_CARRY[368]) );
FULL_ADDER FA_318 (.DATA_A (SUMMAND[411]) , .DATA_B (SUMMAND[412]) , .DATA_C (SUMMAND[413]) , .SAVE (INT_SUM[467]) , .CARRY (INT_CARRY[369]) );
FULL_ADDER FA_319 (.DATA_A (SUMMAND[414]) , .DATA_B (SUMMAND[415]) , .DATA_C (SUMMAND[416]) , .SAVE (INT_SUM[468]) , .CARRY (INT_CARRY[370]) );
FULL_ADDER FA_320 (.DATA_A (SUMMAND[417]) , .DATA_B (SUMMAND[418]) , .DATA_C (SUMMAND[419]) , .SAVE (INT_SUM[469]) , .CARRY (INT_CARRY[371]) );
FULL_ADDER FA_321 (.DATA_A (SUMMAND[420]) , .DATA_B (INT_CARRY[354]) , .DATA_C (INT_CARRY[355]) , .SAVE (INT_SUM[470]) , .CARRY (INT_CARRY[372]) );
assign INT_SUM[471] = INT_CARRY[356];
assign INT_SUM[472] = INT_CARRY[357];
FULL_ADDER FA_322 (.DATA_A (INT_SUM[466]) , .DATA_B (INT_SUM[467]) , .DATA_C (INT_SUM[468]) , .SAVE (INT_SUM[473]) , .CARRY (INT_CARRY[373]) );
FULL_ADDER FA_323 (.DATA_A (INT_SUM[469]) , .DATA_B (INT_SUM[470]) , .DATA_C (INT_SUM[471]) , .SAVE (INT_SUM[474]) , .CARRY (INT_CARRY[374]) );
FULL_ADDER FA_324 (.DATA_A (INT_SUM[472]) , .DATA_B (INT_CARRY[358]) , .DATA_C (INT_CARRY[359]) , .SAVE (INT_SUM[475]) , .CARRY (INT_CARRY[375]) );
assign INT_SUM[476] = INT_CARRY[360];
FULL_ADDER FA_325 (.DATA_A (INT_SUM[473]) , .DATA_B (INT_SUM[474]) , .DATA_C (INT_SUM[475]) , .SAVE (INT_SUM[477]) , .CARRY (INT_CARRY[376]) );
FULL_ADDER FA_326 (.DATA_A (INT_SUM[476]) , .DATA_B (INT_CARRY[361]) , .DATA_C (INT_CARRY[362]) , .SAVE (INT_SUM[479]) , .CARRY (INT_CARRY[378]) );
FLIPFLOP LA_113 (.DIN (INT_SUM[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[478]) );
FLIPFLOP LA_114 (.DIN (INT_SUM[479]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[480]) );
FLIPFLOP LA_115 (.DIN (INT_CARRY[363]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[364]) );
FULL_ADDER FA_327 (.DATA_A (INT_SUM[478]) , .DATA_B (INT_SUM[480]) , .DATA_C (INT_CARRY[364]) , .SAVE (INT_SUM[481]) , .CARRY (INT_CARRY[380]) );
FLIPFLOP LA_116 (.DIN (INT_CARRY[365]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[366]) );
assign INT_SUM[482] = INT_CARRY[366];
FULL_ADDER FA_328 (.DATA_A (INT_SUM[481]) , .DATA_B (INT_SUM[482]) , .DATA_C (INT_CARRY[367]) , .SAVE (SUM[40]) , .CARRY (CARRY[40]) );
FULL_ADDER FA_329 (.DATA_A (SUMMAND[421]) , .DATA_B (SUMMAND[422]) , .DATA_C (SUMMAND[423]) , .SAVE (INT_SUM[483]) , .CARRY (INT_CARRY[381]) );
FULL_ADDER FA_330 (.DATA_A (SUMMAND[424]) , .DATA_B (SUMMAND[425]) , .DATA_C (SUMMAND[426]) , .SAVE (INT_SUM[484]) , .CARRY (INT_CARRY[382]) );
FULL_ADDER FA_331 (.DATA_A (SUMMAND[427]) , .DATA_B (SUMMAND[428]) , .DATA_C (SUMMAND[429]) , .SAVE (INT_SUM[485]) , .CARRY (INT_CARRY[383]) );
FULL_ADDER FA_332 (.DATA_A (SUMMAND[430]) , .DATA_B (SUMMAND[431]) , .DATA_C (SUMMAND[432]) , .SAVE (INT_SUM[486]) , .CARRY (INT_CARRY[384]) );
FULL_ADDER FA_333 (.DATA_A (INT_SUM[483]) , .DATA_B (INT_SUM[484]) , .DATA_C (INT_SUM[485]) , .SAVE (INT_SUM[487]) , .CARRY (INT_CARRY[385]) );
FULL_ADDER FA_334 (.DATA_A (INT_SUM[486]) , .DATA_B (INT_CARRY[368]) , .DATA_C (INT_CARRY[369]) , .SAVE (INT_SUM[488]) , .CARRY (INT_CARRY[386]) );
FULL_ADDER FA_335 (.DATA_A (INT_CARRY[370]) , .DATA_B (INT_CARRY[371]) , .DATA_C (INT_CARRY[372]) , .SAVE (INT_SUM[489]) , .CARRY (INT_CARRY[387]) );
FULL_ADDER FA_336 (.DATA_A (INT_SUM[487]) , .DATA_B (INT_SUM[488]) , .DATA_C (INT_SUM[489]) , .SAVE (INT_SUM[490]) , .CARRY (INT_CARRY[388]) );
FULL_ADDER FA_337 (.DATA_A (INT_CARRY[373]) , .DATA_B (INT_CARRY[374]) , .DATA_C (INT_CARRY[375]) , .SAVE (INT_SUM[492]) , .CARRY (INT_CARRY[390]) );
FLIPFLOP LA_117 (.DIN (INT_SUM[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[491]) );
FLIPFLOP LA_118 (.DIN (INT_SUM[492]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[493]) );
FLIPFLOP LA_119 (.DIN (INT_CARRY[376]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[377]) );
FULL_ADDER FA_338 (.DATA_A (INT_SUM[491]) , .DATA_B (INT_SUM[493]) , .DATA_C (INT_CARRY[377]) , .SAVE (INT_SUM[494]) , .CARRY (INT_CARRY[392]) );
FLIPFLOP LA_120 (.DIN (INT_CARRY[378]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[379]) );
assign INT_SUM[495] = INT_CARRY[379];
FULL_ADDER FA_339 (.DATA_A (INT_SUM[494]) , .DATA_B (INT_SUM[495]) , .DATA_C (INT_CARRY[380]) , .SAVE (SUM[41]) , .CARRY (CARRY[41]) );
FULL_ADDER FA_340 (.DATA_A (SUMMAND[433]) , .DATA_B (SUMMAND[434]) , .DATA_C (SUMMAND[435]) , .SAVE (INT_SUM[496]) , .CARRY (INT_CARRY[393]) );
FULL_ADDER FA_341 (.DATA_A (SUMMAND[436]) , .DATA_B (SUMMAND[437]) , .DATA_C (SUMMAND[438]) , .SAVE (INT_SUM[497]) , .CARRY (INT_CARRY[394]) );
FULL_ADDER FA_342 (.DATA_A (SUMMAND[439]) , .DATA_B (SUMMAND[440]) , .DATA_C (SUMMAND[441]) , .SAVE (INT_SUM[498]) , .CARRY (INT_CARRY[395]) );
FULL_ADDER FA_343 (.DATA_A (SUMMAND[442]) , .DATA_B (SUMMAND[443]) , .DATA_C (SUMMAND[444]) , .SAVE (INT_SUM[499]) , .CARRY (INT_CARRY[396]) );
FULL_ADDER FA_344 (.DATA_A (INT_SUM[496]) , .DATA_B (INT_SUM[497]) , .DATA_C (INT_SUM[498]) , .SAVE (INT_SUM[500]) , .CARRY (INT_CARRY[397]) );
FULL_ADDER FA_345 (.DATA_A (INT_SUM[499]) , .DATA_B (INT_CARRY[381]) , .DATA_C (INT_CARRY[382]) , .SAVE (INT_SUM[501]) , .CARRY (INT_CARRY[398]) );
HALF_ADDER HA_38 (.DATA_A (INT_CARRY[383]) , .DATA_B (INT_CARRY[384]) , .SAVE (INT_SUM[502]) , .CARRY (INT_CARRY[399]) );
FULL_ADDER FA_346 (.DATA_A (INT_SUM[500]) , .DATA_B (INT_SUM[501]) , .DATA_C (INT_SUM[502]) , .SAVE (INT_SUM[503]) , .CARRY (INT_CARRY[400]) );
FULL_ADDER FA_347 (.DATA_A (INT_CARRY[385]) , .DATA_B (INT_CARRY[386]) , .DATA_C (INT_CARRY[387]) , .SAVE (INT_SUM[505]) , .CARRY (INT_CARRY[402]) );
FLIPFLOP LA_121 (.DIN (INT_SUM[503]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[504]) );
FLIPFLOP LA_122 (.DIN (INT_SUM[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[506]) );
FLIPFLOP LA_123 (.DIN (INT_CARRY[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[389]) );
FULL_ADDER FA_348 (.DATA_A (INT_SUM[504]) , .DATA_B (INT_SUM[506]) , .DATA_C (INT_CARRY[389]) , .SAVE (INT_SUM[507]) , .CARRY (INT_CARRY[404]) );
FLIPFLOP LA_124 (.DIN (INT_CARRY[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[391]) );
assign INT_SUM[508] = INT_CARRY[391];
FULL_ADDER FA_349 (.DATA_A (INT_SUM[507]) , .DATA_B (INT_SUM[508]) , .DATA_C (INT_CARRY[392]) , .SAVE (SUM[42]) , .CARRY (CARRY[42]) );
FULL_ADDER FA_350 (.DATA_A (SUMMAND[445]) , .DATA_B (SUMMAND[446]) , .DATA_C (SUMMAND[447]) , .SAVE (INT_SUM[509]) , .CARRY (INT_CARRY[405]) );
FULL_ADDER FA_351 (.DATA_A (SUMMAND[448]) , .DATA_B (SUMMAND[449]) , .DATA_C (SUMMAND[450]) , .SAVE (INT_SUM[510]) , .CARRY (INT_CARRY[406]) );
FULL_ADDER FA_352 (.DATA_A (SUMMAND[451]) , .DATA_B (SUMMAND[452]) , .DATA_C (SUMMAND[453]) , .SAVE (INT_SUM[511]) , .CARRY (INT_CARRY[407]) );
assign INT_SUM[512] = SUMMAND[454];
assign INT_SUM[513] = SUMMAND[455];
FULL_ADDER FA_353 (.DATA_A (INT_SUM[509]) , .DATA_B (INT_SUM[510]) , .DATA_C (INT_SUM[511]) , .SAVE (INT_SUM[514]) , .CARRY (INT_CARRY[408]) );
FULL_ADDER FA_354 (.DATA_A (INT_SUM[512]) , .DATA_B (INT_SUM[513]) , .DATA_C (INT_CARRY[393]) , .SAVE (INT_SUM[515]) , .CARRY (INT_CARRY[409]) );
FULL_ADDER FA_355 (.DATA_A (INT_CARRY[394]) , .DATA_B (INT_CARRY[395]) , .DATA_C (INT_CARRY[396]) , .SAVE (INT_SUM[516]) , .CARRY (INT_CARRY[410]) );
FULL_ADDER FA_356 (.DATA_A (INT_SUM[514]) , .DATA_B (INT_SUM[515]) , .DATA_C (INT_SUM[516]) , .SAVE (INT_SUM[517]) , .CARRY (INT_CARRY[411]) );
FULL_ADDER FA_357 (.DATA_A (INT_CARRY[397]) , .DATA_B (INT_CARRY[398]) , .DATA_C (INT_CARRY[399]) , .SAVE (INT_SUM[519]) , .CARRY (INT_CARRY[413]) );
FLIPFLOP LA_125 (.DIN (INT_SUM[517]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[518]) );
FLIPFLOP LA_126 (.DIN (INT_SUM[519]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[520]) );
FLIPFLOP LA_127 (.DIN (INT_CARRY[400]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[401]) );
FULL_ADDER FA_358 (.DATA_A (INT_SUM[518]) , .DATA_B (INT_SUM[520]) , .DATA_C (INT_CARRY[401]) , .SAVE (INT_SUM[521]) , .CARRY (INT_CARRY[415]) );
FLIPFLOP LA_128 (.DIN (INT_CARRY[402]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[403]) );
assign INT_SUM[522] = INT_CARRY[403];
FULL_ADDER FA_359 (.DATA_A (INT_SUM[521]) , .DATA_B (INT_SUM[522]) , .DATA_C (INT_CARRY[404]) , .SAVE (SUM[43]) , .CARRY (CARRY[43]) );
FULL_ADDER FA_360 (.DATA_A (SUMMAND[456]) , .DATA_B (SUMMAND[457]) , .DATA_C (SUMMAND[458]) , .SAVE (INT_SUM[523]) , .CARRY (INT_CARRY[416]) );
FULL_ADDER FA_361 (.DATA_A (SUMMAND[459]) , .DATA_B (SUMMAND[460]) , .DATA_C (SUMMAND[461]) , .SAVE (INT_SUM[524]) , .CARRY (INT_CARRY[417]) );
FULL_ADDER FA_362 (.DATA_A (SUMMAND[462]) , .DATA_B (SUMMAND[463]) , .DATA_C (SUMMAND[464]) , .SAVE (INT_SUM[525]) , .CARRY (INT_CARRY[418]) );
HALF_ADDER HA_39 (.DATA_A (SUMMAND[465]) , .DATA_B (SUMMAND[466]) , .SAVE (INT_SUM[526]) , .CARRY (INT_CARRY[419]) );
FULL_ADDER FA_363 (.DATA_A (INT_SUM[523]) , .DATA_B (INT_SUM[524]) , .DATA_C (INT_SUM[525]) , .SAVE (INT_SUM[527]) , .CARRY (INT_CARRY[420]) );
FULL_ADDER FA_364 (.DATA_A (INT_SUM[526]) , .DATA_B (INT_CARRY[405]) , .DATA_C (INT_CARRY[406]) , .SAVE (INT_SUM[528]) , .CARRY (INT_CARRY[421]) );
assign INT_SUM[529] = INT_CARRY[407];
FULL_ADDER FA_365 (.DATA_A (INT_SUM[527]) , .DATA_B (INT_SUM[528]) , .DATA_C (INT_SUM[529]) , .SAVE (INT_SUM[530]) , .CARRY (INT_CARRY[422]) );
FULL_ADDER FA_366 (.DATA_A (INT_CARRY[408]) , .DATA_B (INT_CARRY[409]) , .DATA_C (INT_CARRY[410]) , .SAVE (INT_SUM[532]) , .CARRY (INT_CARRY[424]) );
FLIPFLOP LA_129 (.DIN (INT_SUM[530]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[531]) );
FLIPFLOP LA_130 (.DIN (INT_SUM[532]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[533]) );
FLIPFLOP LA_131 (.DIN (INT_CARRY[411]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[412]) );
FULL_ADDER FA_367 (.DATA_A (INT_SUM[531]) , .DATA_B (INT_SUM[533]) , .DATA_C (INT_CARRY[412]) , .SAVE (INT_SUM[534]) , .CARRY (INT_CARRY[426]) );
FLIPFLOP LA_132 (.DIN (INT_CARRY[413]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[414]) );
assign INT_SUM[535] = INT_CARRY[414];
FULL_ADDER FA_368 (.DATA_A (INT_SUM[534]) , .DATA_B (INT_SUM[535]) , .DATA_C (INT_CARRY[415]) , .SAVE (SUM[44]) , .CARRY (CARRY[44]) );
FULL_ADDER FA_369 (.DATA_A (SUMMAND[467]) , .DATA_B (SUMMAND[468]) , .DATA_C (SUMMAND[469]) , .SAVE (INT_SUM[536]) , .CARRY (INT_CARRY[427]) );
FULL_ADDER FA_370 (.DATA_A (SUMMAND[470]) , .DATA_B (SUMMAND[471]) , .DATA_C (SUMMAND[472]) , .SAVE (INT_SUM[537]) , .CARRY (INT_CARRY[428]) );
FULL_ADDER FA_371 (.DATA_A (SUMMAND[473]) , .DATA_B (SUMMAND[474]) , .DATA_C (SUMMAND[475]) , .SAVE (INT_SUM[538]) , .CARRY (INT_CARRY[429]) );
assign INT_SUM[539] = SUMMAND[476];
FULL_ADDER FA_372 (.DATA_A (INT_SUM[536]) , .DATA_B (INT_SUM[537]) , .DATA_C (INT_SUM[538]) , .SAVE (INT_SUM[540]) , .CARRY (INT_CARRY[430]) );
FULL_ADDER FA_373 (.DATA_A (INT_SUM[539]) , .DATA_B (INT_CARRY[416]) , .DATA_C (INT_CARRY[417]) , .SAVE (INT_SUM[541]) , .CARRY (INT_CARRY[431]) );
assign INT_SUM[542] = INT_CARRY[418];
assign INT_SUM[543] = INT_CARRY[419];
FULL_ADDER FA_374 (.DATA_A (INT_SUM[540]) , .DATA_B (INT_SUM[541]) , .DATA_C (INT_SUM[542]) , .SAVE (INT_SUM[544]) , .CARRY (INT_CARRY[432]) );
FULL_ADDER FA_375 (.DATA_A (INT_SUM[543]) , .DATA_B (INT_CARRY[420]) , .DATA_C (INT_CARRY[421]) , .SAVE (INT_SUM[546]) , .CARRY (INT_CARRY[434]) );
FLIPFLOP LA_133 (.DIN (INT_SUM[544]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[545]) );
FLIPFLOP LA_134 (.DIN (INT_SUM[546]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[547]) );
FLIPFLOP LA_135 (.DIN (INT_CARRY[422]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[423]) );
FULL_ADDER FA_376 (.DATA_A (INT_SUM[545]) , .DATA_B (INT_SUM[547]) , .DATA_C (INT_CARRY[423]) , .SAVE (INT_SUM[548]) , .CARRY (INT_CARRY[436]) );
FLIPFLOP LA_136 (.DIN (INT_CARRY[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[425]) );
assign INT_SUM[549] = INT_CARRY[425];
FULL_ADDER FA_377 (.DATA_A (INT_SUM[548]) , .DATA_B (INT_SUM[549]) , .DATA_C (INT_CARRY[426]) , .SAVE (SUM[45]) , .CARRY (CARRY[45]) );
FULL_ADDER FA_378 (.DATA_A (SUMMAND[477]) , .DATA_B (SUMMAND[478]) , .DATA_C (SUMMAND[479]) , .SAVE (INT_SUM[550]) , .CARRY (INT_CARRY[437]) );
FULL_ADDER FA_379 (.DATA_A (SUMMAND[480]) , .DATA_B (SUMMAND[481]) , .DATA_C (SUMMAND[482]) , .SAVE (INT_SUM[551]) , .CARRY (INT_CARRY[438]) );
FULL_ADDER FA_380 (.DATA_A (SUMMAND[483]) , .DATA_B (SUMMAND[484]) , .DATA_C (SUMMAND[485]) , .SAVE (INT_SUM[552]) , .CARRY (INT_CARRY[439]) );
assign INT_SUM[553] = SUMMAND[486];
FULL_ADDER FA_381 (.DATA_A (INT_SUM[550]) , .DATA_B (INT_SUM[551]) , .DATA_C (INT_SUM[552]) , .SAVE (INT_SUM[554]) , .CARRY (INT_CARRY[440]) );
FULL_ADDER FA_382 (.DATA_A (INT_SUM[553]) , .DATA_B (INT_CARRY[427]) , .DATA_C (INT_CARRY[428]) , .SAVE (INT_SUM[555]) , .CARRY (INT_CARRY[441]) );
assign INT_SUM[556] = INT_CARRY[429];
FULL_ADDER FA_383 (.DATA_A (INT_SUM[554]) , .DATA_B (INT_SUM[555]) , .DATA_C (INT_SUM[556]) , .SAVE (INT_SUM[557]) , .CARRY (INT_CARRY[442]) );
HALF_ADDER HA_40 (.DATA_A (INT_CARRY[430]) , .DATA_B (INT_CARRY[431]) , .SAVE (INT_SUM[559]) , .CARRY (INT_CARRY[444]) );
FLIPFLOP LA_137 (.DIN (INT_SUM[557]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[558]) );
FLIPFLOP LA_138 (.DIN (INT_SUM[559]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[560]) );
FLIPFLOP LA_139 (.DIN (INT_CARRY[432]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[433]) );
FULL_ADDER FA_384 (.DATA_A (INT_SUM[558]) , .DATA_B (INT_SUM[560]) , .DATA_C (INT_CARRY[433]) , .SAVE (INT_SUM[561]) , .CARRY (INT_CARRY[446]) );
FLIPFLOP LA_140 (.DIN (INT_CARRY[434]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[435]) );
assign INT_SUM[562] = INT_CARRY[435];
FULL_ADDER FA_385 (.DATA_A (INT_SUM[561]) , .DATA_B (INT_SUM[562]) , .DATA_C (INT_CARRY[436]) , .SAVE (SUM[46]) , .CARRY (CARRY[46]) );
FULL_ADDER FA_386 (.DATA_A (SUMMAND[487]) , .DATA_B (SUMMAND[488]) , .DATA_C (SUMMAND[489]) , .SAVE (INT_SUM[563]) , .CARRY (INT_CARRY[447]) );
FULL_ADDER FA_387 (.DATA_A (SUMMAND[490]) , .DATA_B (SUMMAND[491]) , .DATA_C (SUMMAND[492]) , .SAVE (INT_SUM[564]) , .CARRY (INT_CARRY[448]) );
FULL_ADDER FA_388 (.DATA_A (SUMMAND[493]) , .DATA_B (SUMMAND[494]) , .DATA_C (SUMMAND[495]) , .SAVE (INT_SUM[565]) , .CARRY (INT_CARRY[449]) );
FULL_ADDER FA_389 (.DATA_A (INT_SUM[563]) , .DATA_B (INT_SUM[564]) , .DATA_C (INT_SUM[565]) , .SAVE (INT_SUM[566]) , .CARRY (INT_CARRY[450]) );
FULL_ADDER FA_390 (.DATA_A (INT_CARRY[437]) , .DATA_B (INT_CARRY[438]) , .DATA_C (INT_CARRY[439]) , .SAVE (INT_SUM[567]) , .CARRY (INT_CARRY[451]) );
FULL_ADDER FA_391 (.DATA_A (INT_SUM[566]) , .DATA_B (INT_SUM[567]) , .DATA_C (INT_CARRY[440]) , .SAVE (INT_SUM[568]) , .CARRY (INT_CARRY[452]) );
assign INT_SUM[570] = INT_CARRY[441];
FLIPFLOP LA_141 (.DIN (INT_SUM[568]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[569]) );
FLIPFLOP LA_142 (.DIN (INT_SUM[570]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[571]) );
FLIPFLOP LA_143 (.DIN (INT_CARRY[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[443]) );
FULL_ADDER FA_392 (.DATA_A (INT_SUM[569]) , .DATA_B (INT_SUM[571]) , .DATA_C (INT_CARRY[443]) , .SAVE (INT_SUM[572]) , .CARRY (INT_CARRY[454]) );
FLIPFLOP LA_144 (.DIN (INT_CARRY[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[445]) );
assign INT_SUM[573] = INT_CARRY[445];
FULL_ADDER FA_393 (.DATA_A (INT_SUM[572]) , .DATA_B (INT_SUM[573]) , .DATA_C (INT_CARRY[446]) , .SAVE (SUM[47]) , .CARRY (CARRY[47]) );
FULL_ADDER FA_394 (.DATA_A (SUMMAND[496]) , .DATA_B (SUMMAND[497]) , .DATA_C (SUMMAND[498]) , .SAVE (INT_SUM[574]) , .CARRY (INT_CARRY[455]) );
FULL_ADDER FA_395 (.DATA_A (SUMMAND[499]) , .DATA_B (SUMMAND[500]) , .DATA_C (SUMMAND[501]) , .SAVE (INT_SUM[575]) , .CARRY (INT_CARRY[456]) );
FULL_ADDER FA_396 (.DATA_A (SUMMAND[502]) , .DATA_B (SUMMAND[503]) , .DATA_C (SUMMAND[504]) , .SAVE (INT_SUM[576]) , .CARRY (INT_CARRY[457]) );
FULL_ADDER FA_397 (.DATA_A (INT_SUM[574]) , .DATA_B (INT_SUM[575]) , .DATA_C (INT_SUM[576]) , .SAVE (INT_SUM[577]) , .CARRY (INT_CARRY[458]) );
FULL_ADDER FA_398 (.DATA_A (INT_CARRY[447]) , .DATA_B (INT_CARRY[448]) , .DATA_C (INT_CARRY[449]) , .SAVE (INT_SUM[578]) , .CARRY (INT_CARRY[459]) );
FULL_ADDER FA_399 (.DATA_A (INT_SUM[577]) , .DATA_B (INT_SUM[578]) , .DATA_C (INT_CARRY[450]) , .SAVE (INT_SUM[579]) , .CARRY (INT_CARRY[460]) );
assign INT_SUM[581] = INT_CARRY[451];
FLIPFLOP LA_145 (.DIN (INT_SUM[579]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[580]) );
FLIPFLOP LA_146 (.DIN (INT_SUM[581]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[582]) );
FLIPFLOP LA_147 (.DIN (INT_CARRY[452]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[453]) );
FULL_ADDER FA_400 (.DATA_A (INT_SUM[580]) , .DATA_B (INT_SUM[582]) , .DATA_C (INT_CARRY[453]) , .SAVE (INT_SUM[583]) , .CARRY (INT_CARRY[462]) );
HALF_ADDER HA_41 (.DATA_A (INT_SUM[583]) , .DATA_B (INT_CARRY[454]) , .SAVE (SUM[48]) , .CARRY (CARRY[48]) );
FULL_ADDER FA_401 (.DATA_A (SUMMAND[505]) , .DATA_B (SUMMAND[506]) , .DATA_C (SUMMAND[507]) , .SAVE (INT_SUM[584]) , .CARRY (INT_CARRY[463]) );
FULL_ADDER FA_402 (.DATA_A (SUMMAND[508]) , .DATA_B (SUMMAND[509]) , .DATA_C (SUMMAND[510]) , .SAVE (INT_SUM[585]) , .CARRY (INT_CARRY[464]) );
FULL_ADDER FA_403 (.DATA_A (SUMMAND[511]) , .DATA_B (SUMMAND[512]) , .DATA_C (INT_CARRY[455]) , .SAVE (INT_SUM[586]) , .CARRY (INT_CARRY[465]) );
HALF_ADDER HA_42 (.DATA_A (INT_CARRY[456]) , .DATA_B (INT_CARRY[457]) , .SAVE (INT_SUM[587]) , .CARRY (INT_CARRY[466]) );
FULL_ADDER FA_404 (.DATA_A (INT_SUM[584]) , .DATA_B (INT_SUM[585]) , .DATA_C (INT_SUM[586]) , .SAVE (INT_SUM[588]) , .CARRY (INT_CARRY[467]) );
FULL_ADDER FA_405 (.DATA_A (INT_SUM[587]) , .DATA_B (INT_CARRY[458]) , .DATA_C (INT_CARRY[459]) , .SAVE (INT_SUM[590]) , .CARRY (INT_CARRY[469]) );
FLIPFLOP LA_148 (.DIN (INT_SUM[588]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[589]) );
FLIPFLOP LA_149 (.DIN (INT_SUM[590]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[591]) );
FLIPFLOP LA_150 (.DIN (INT_CARRY[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[461]) );
FULL_ADDER FA_406 (.DATA_A (INT_SUM[589]) , .DATA_B (INT_SUM[591]) , .DATA_C (INT_CARRY[461]) , .SAVE (INT_SUM[592]) , .CARRY (INT_CARRY[471]) );
HALF_ADDER HA_43 (.DATA_A (INT_SUM[592]) , .DATA_B (INT_CARRY[462]) , .SAVE (SUM[49]) , .CARRY (CARRY[49]) );
FULL_ADDER FA_407 (.DATA_A (SUMMAND[513]) , .DATA_B (SUMMAND[514]) , .DATA_C (SUMMAND[515]) , .SAVE (INT_SUM[593]) , .CARRY (INT_CARRY[472]) );
FULL_ADDER FA_408 (.DATA_A (SUMMAND[516]) , .DATA_B (SUMMAND[517]) , .DATA_C (SUMMAND[518]) , .SAVE (INT_SUM[594]) , .CARRY (INT_CARRY[473]) );
assign INT_SUM[595] = SUMMAND[519];
assign INT_SUM[596] = SUMMAND[520];
FULL_ADDER FA_409 (.DATA_A (INT_SUM[593]) , .DATA_B (INT_SUM[594]) , .DATA_C (INT_SUM[595]) , .SAVE (INT_SUM[597]) , .CARRY (INT_CARRY[474]) );
assign INT_SUM[598] = INT_SUM[596];
FULL_ADDER FA_410 (.DATA_A (INT_SUM[597]) , .DATA_B (INT_SUM[598]) , .DATA_C (INT_CARRY[463]) , .SAVE (INT_SUM[599]) , .CARRY (INT_CARRY[475]) );
FULL_ADDER FA_411 (.DATA_A (INT_CARRY[464]) , .DATA_B (INT_CARRY[465]) , .DATA_C (INT_CARRY[466]) , .SAVE (INT_SUM[601]) , .CARRY (INT_CARRY[477]) );
FLIPFLOP LA_151 (.DIN (INT_SUM[599]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[600]) );
FLIPFLOP LA_152 (.DIN (INT_SUM[601]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[602]) );
FLIPFLOP LA_153 (.DIN (INT_CARRY[467]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[468]) );
FULL_ADDER FA_412 (.DATA_A (INT_SUM[600]) , .DATA_B (INT_SUM[602]) , .DATA_C (INT_CARRY[468]) , .SAVE (INT_SUM[603]) , .CARRY (INT_CARRY[479]) );
FLIPFLOP LA_154 (.DIN (INT_CARRY[469]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[470]) );
assign INT_SUM[604] = INT_CARRY[470];
FULL_ADDER FA_413 (.DATA_A (INT_SUM[603]) , .DATA_B (INT_SUM[604]) , .DATA_C (INT_CARRY[471]) , .SAVE (SUM[50]) , .CARRY (CARRY[50]) );
FULL_ADDER FA_414 (.DATA_A (SUMMAND[521]) , .DATA_B (SUMMAND[522]) , .DATA_C (SUMMAND[523]) , .SAVE (INT_SUM[605]) , .CARRY (INT_CARRY[480]) );
FULL_ADDER FA_415 (.DATA_A (SUMMAND[524]) , .DATA_B (SUMMAND[525]) , .DATA_C (SUMMAND[526]) , .SAVE (INT_SUM[606]) , .CARRY (INT_CARRY[481]) );
FULL_ADDER FA_416 (.DATA_A (SUMMAND[527]) , .DATA_B (INT_CARRY[472]) , .DATA_C (INT_CARRY[473]) , .SAVE (INT_SUM[607]) , .CARRY (INT_CARRY[482]) );
FULL_ADDER FA_417 (.DATA_A (INT_SUM[605]) , .DATA_B (INT_SUM[606]) , .DATA_C (INT_SUM[607]) , .SAVE (INT_SUM[608]) , .CARRY (INT_CARRY[483]) );
assign INT_SUM[610] = INT_CARRY[474];
FLIPFLOP LA_155 (.DIN (INT_SUM[608]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[609]) );
FLIPFLOP LA_156 (.DIN (INT_SUM[610]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[611]) );
FLIPFLOP LA_157 (.DIN (INT_CARRY[475]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[476]) );
FULL_ADDER FA_418 (.DATA_A (INT_SUM[609]) , .DATA_B (INT_SUM[611]) , .DATA_C (INT_CARRY[476]) , .SAVE (INT_SUM[612]) , .CARRY (INT_CARRY[485]) );
FLIPFLOP LA_158 (.DIN (INT_CARRY[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[478]) );
assign INT_SUM[613] = INT_CARRY[478];
FULL_ADDER FA_419 (.DATA_A (INT_SUM[612]) , .DATA_B (INT_SUM[613]) , .DATA_C (INT_CARRY[479]) , .SAVE (SUM[51]) , .CARRY (CARRY[51]) );
FULL_ADDER FA_420 (.DATA_A (SUMMAND[528]) , .DATA_B (SUMMAND[529]) , .DATA_C (SUMMAND[530]) , .SAVE (INT_SUM[614]) , .CARRY (INT_CARRY[486]) );
FULL_ADDER FA_421 (.DATA_A (SUMMAND[531]) , .DATA_B (SUMMAND[532]) , .DATA_C (SUMMAND[533]) , .SAVE (INT_SUM[615]) , .CARRY (INT_CARRY[487]) );
assign INT_SUM[616] = SUMMAND[534];
FULL_ADDER FA_422 (.DATA_A (INT_SUM[614]) , .DATA_B (INT_SUM[615]) , .DATA_C (INT_SUM[616]) , .SAVE (INT_SUM[617]) , .CARRY (INT_CARRY[488]) );
FULL_ADDER FA_423 (.DATA_A (INT_CARRY[480]) , .DATA_B (INT_CARRY[481]) , .DATA_C (INT_CARRY[482]) , .SAVE (INT_SUM[619]) , .CARRY (INT_CARRY[490]) );
FLIPFLOP LA_159 (.DIN (INT_SUM[617]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[618]) );
FLIPFLOP LA_160 (.DIN (INT_SUM[619]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[620]) );
FLIPFLOP LA_161 (.DIN (INT_CARRY[483]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[484]) );
FULL_ADDER FA_424 (.DATA_A (INT_SUM[618]) , .DATA_B (INT_SUM[620]) , .DATA_C (INT_CARRY[484]) , .SAVE (INT_SUM[621]) , .CARRY (INT_CARRY[492]) );
HALF_ADDER HA_44 (.DATA_A (INT_SUM[621]) , .DATA_B (INT_CARRY[485]) , .SAVE (SUM[52]) , .CARRY (CARRY[52]) );
FULL_ADDER FA_425 (.DATA_A (SUMMAND[535]) , .DATA_B (SUMMAND[536]) , .DATA_C (SUMMAND[537]) , .SAVE (INT_SUM[622]) , .CARRY (INT_CARRY[493]) );
FULL_ADDER FA_426 (.DATA_A (SUMMAND[538]) , .DATA_B (SUMMAND[539]) , .DATA_C (SUMMAND[540]) , .SAVE (INT_SUM[623]) , .CARRY (INT_CARRY[494]) );
FULL_ADDER FA_427 (.DATA_A (INT_SUM[622]) , .DATA_B (INT_SUM[623]) , .DATA_C (INT_CARRY[486]) , .SAVE (INT_SUM[624]) , .CARRY (INT_CARRY[495]) );
assign INT_SUM[626] = INT_CARRY[487];
FLIPFLOP LA_162 (.DIN (INT_SUM[624]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[625]) );
FLIPFLOP LA_163 (.DIN (INT_SUM[626]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[627]) );
FLIPFLOP LA_164 (.DIN (INT_CARRY[488]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[489]) );
FULL_ADDER FA_428 (.DATA_A (INT_SUM[625]) , .DATA_B (INT_SUM[627]) , .DATA_C (INT_CARRY[489]) , .SAVE (INT_SUM[628]) , .CARRY (INT_CARRY[497]) );
FLIPFLOP LA_165 (.DIN (INT_CARRY[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[491]) );
assign INT_SUM[629] = INT_CARRY[491];
FULL_ADDER FA_429 (.DATA_A (INT_SUM[628]) , .DATA_B (INT_SUM[629]) , .DATA_C (INT_CARRY[492]) , .SAVE (SUM[53]) , .CARRY (CARRY[53]) );
FULL_ADDER FA_430 (.DATA_A (SUMMAND[541]) , .DATA_B (SUMMAND[542]) , .DATA_C (SUMMAND[543]) , .SAVE (INT_SUM[630]) , .CARRY (INT_CARRY[498]) );
FULL_ADDER FA_431 (.DATA_A (SUMMAND[544]) , .DATA_B (SUMMAND[545]) , .DATA_C (SUMMAND[546]) , .SAVE (INT_SUM[631]) , .CARRY (INT_CARRY[499]) );
FULL_ADDER FA_432 (.DATA_A (INT_SUM[630]) , .DATA_B (INT_SUM[631]) , .DATA_C (INT_CARRY[493]) , .SAVE (INT_SUM[632]) , .CARRY (INT_CARRY[500]) );
assign INT_SUM[634] = INT_CARRY[494];
FLIPFLOP LA_166 (.DIN (INT_SUM[632]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[633]) );
FLIPFLOP LA_167 (.DIN (INT_SUM[634]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[635]) );
FLIPFLOP LA_168 (.DIN (INT_CARRY[495]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[496]) );
FULL_ADDER FA_433 (.DATA_A (INT_SUM[633]) , .DATA_B (INT_SUM[635]) , .DATA_C (INT_CARRY[496]) , .SAVE (INT_SUM[636]) , .CARRY (INT_CARRY[502]) );
HALF_ADDER HA_45 (.DATA_A (INT_SUM[636]) , .DATA_B (INT_CARRY[497]) , .SAVE (SUM[54]) , .CARRY (CARRY[54]) );
FULL_ADDER FA_434 (.DATA_A (SUMMAND[547]) , .DATA_B (SUMMAND[548]) , .DATA_C (SUMMAND[549]) , .SAVE (INT_SUM[637]) , .CARRY (INT_CARRY[503]) );
HALF_ADDER HA_46 (.DATA_A (SUMMAND[550]) , .DATA_B (SUMMAND[551]) , .SAVE (INT_SUM[638]) , .CARRY (INT_CARRY[504]) );
FULL_ADDER FA_435 (.DATA_A (INT_SUM[637]) , .DATA_B (INT_SUM[638]) , .DATA_C (INT_CARRY[498]) , .SAVE (INT_SUM[639]) , .CARRY (INT_CARRY[505]) );
assign INT_SUM[641] = INT_CARRY[499];
FLIPFLOP LA_169 (.DIN (INT_SUM[639]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[640]) );
FLIPFLOP LA_170 (.DIN (INT_SUM[641]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[642]) );
FLIPFLOP LA_171 (.DIN (INT_CARRY[500]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[501]) );
FULL_ADDER FA_436 (.DATA_A (INT_SUM[640]) , .DATA_B (INT_SUM[642]) , .DATA_C (INT_CARRY[501]) , .SAVE (INT_SUM[643]) , .CARRY (INT_CARRY[507]) );
HALF_ADDER HA_47 (.DATA_A (INT_SUM[643]) , .DATA_B (INT_CARRY[502]) , .SAVE (SUM[55]) , .CARRY (CARRY[55]) );
FULL_ADDER FA_437 (.DATA_A (SUMMAND[552]) , .DATA_B (SUMMAND[553]) , .DATA_C (SUMMAND[554]) , .SAVE (INT_SUM[644]) , .CARRY (INT_CARRY[508]) );
HALF_ADDER HA_48 (.DATA_A (SUMMAND[555]) , .DATA_B (SUMMAND[556]) , .SAVE (INT_SUM[645]) , .CARRY (INT_CARRY[509]) );
FULL_ADDER FA_438 (.DATA_A (INT_SUM[644]) , .DATA_B (INT_SUM[645]) , .DATA_C (INT_CARRY[503]) , .SAVE (INT_SUM[646]) , .CARRY (INT_CARRY[510]) );
assign INT_SUM[648] = INT_CARRY[504];
FLIPFLOP LA_172 (.DIN (INT_SUM[646]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[647]) );
FLIPFLOP LA_173 (.DIN (INT_SUM[648]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[649]) );
FLIPFLOP LA_174 (.DIN (INT_CARRY[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[506]) );
FULL_ADDER FA_439 (.DATA_A (INT_SUM[647]) , .DATA_B (INT_SUM[649]) , .DATA_C (INT_CARRY[506]) , .SAVE (INT_SUM[650]) , .CARRY (INT_CARRY[512]) );
HALF_ADDER HA_49 (.DATA_A (INT_SUM[650]) , .DATA_B (INT_CARRY[507]) , .SAVE (SUM[56]) , .CARRY (CARRY[56]) );
FULL_ADDER FA_440 (.DATA_A (SUMMAND[557]) , .DATA_B (SUMMAND[558]) , .DATA_C (SUMMAND[559]) , .SAVE (INT_SUM[651]) , .CARRY (INT_CARRY[513]) );
FULL_ADDER FA_441 (.DATA_A (SUMMAND[560]) , .DATA_B (INT_CARRY[508]) , .DATA_C (INT_CARRY[509]) , .SAVE (INT_SUM[653]) , .CARRY (INT_CARRY[515]) );
FLIPFLOP LA_175 (.DIN (INT_SUM[651]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[652]) );
FLIPFLOP LA_176 (.DIN (INT_SUM[653]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[654]) );
FLIPFLOP LA_177 (.DIN (INT_CARRY[510]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[511]) );
FULL_ADDER FA_442 (.DATA_A (INT_SUM[652]) , .DATA_B (INT_SUM[654]) , .DATA_C (INT_CARRY[511]) , .SAVE (INT_SUM[655]) , .CARRY (INT_CARRY[517]) );
HALF_ADDER HA_50 (.DATA_A (INT_SUM[655]) , .DATA_B (INT_CARRY[512]) , .SAVE (SUM[57]) , .CARRY (CARRY[57]) );
FULL_ADDER FA_443 (.DATA_A (SUMMAND[561]) , .DATA_B (SUMMAND[562]) , .DATA_C (SUMMAND[563]) , .SAVE (INT_SUM[656]) , .CARRY (INT_CARRY[518]) );
assign INT_SUM[658] = SUMMAND[564];
FLIPFLOP LA_178 (.DIN (INT_SUM[656]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[657]) );
FLIPFLOP LA_179 (.DIN (INT_SUM[658]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[659]) );
FLIPFLOP LA_180 (.DIN (INT_CARRY[513]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[514]) );
FULL_ADDER FA_444 (.DATA_A (INT_SUM[657]) , .DATA_B (INT_SUM[659]) , .DATA_C (INT_CARRY[514]) , .SAVE (INT_SUM[660]) , .CARRY (INT_CARRY[520]) );
FLIPFLOP LA_181 (.DIN (INT_CARRY[515]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[516]) );
assign INT_SUM[661] = INT_CARRY[516];
FULL_ADDER FA_445 (.DATA_A (INT_SUM[660]) , .DATA_B (INT_SUM[661]) , .DATA_C (INT_CARRY[517]) , .SAVE (SUM[58]) , .CARRY (CARRY[58]) );
FULL_ADDER FA_446 (.DATA_A (SUMMAND[565]) , .DATA_B (SUMMAND[566]) , .DATA_C (SUMMAND[567]) , .SAVE (INT_SUM[662]) , .CARRY (INT_CARRY[521]) );
FLIPFLOP LA_182 (.DIN (INT_SUM[662]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[663]) );
assign INT_SUM[664] = INT_SUM[663];
FLIPFLOP LA_183 (.DIN (INT_CARRY[518]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[519]) );
assign INT_SUM[665] = INT_CARRY[519];
FULL_ADDER FA_447 (.DATA_A (INT_SUM[664]) , .DATA_B (INT_SUM[665]) , .DATA_C (INT_CARRY[520]) , .SAVE (SUM[59]) , .CARRY (CARRY[59]) );
FLIPFLOP LA_184 (.DIN (SUMMAND[568]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[0]) );
FLIPFLOP LA_185 (.DIN (SUMMAND[569]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[1]) );
FLIPFLOP LA_186 (.DIN (SUMMAND[570]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[2]) );
FULL_ADDER FA_448 (.DATA_A (LATCHED_PP[0]) , .DATA_B (LATCHED_PP[1]) , .DATA_C (LATCHED_PP[2]) , .SAVE (INT_SUM[666]) , .CARRY (INT_CARRY[523]) );
FLIPFLOP LA_187 (.DIN (INT_CARRY[521]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[522]) );
assign INT_SUM[667] = INT_CARRY[522];
HALF_ADDER HA_51 (.DATA_A (INT_SUM[666]) , .DATA_B (INT_SUM[667]) , .SAVE (SUM[60]) , .CARRY (CARRY[60]) );
FLIPFLOP LA_188 (.DIN (SUMMAND[571]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[3]) );
assign INT_SUM[668] = LATCHED_PP[3];
FLIPFLOP LA_189 (.DIN (SUMMAND[572]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[4]) );
assign INT_SUM[669] = LATCHED_PP[4];
FULL_ADDER FA_449 (.DATA_A (INT_SUM[668]) , .DATA_B (INT_SUM[669]) , .DATA_C (INT_CARRY[523]) , .SAVE (SUM[61]) , .CARRY (CARRY[61]) );
FLIPFLOP LA_190 (.DIN (SUMMAND[573]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[5]) );
FLIPFLOP LA_191 (.DIN (SUMMAND[574]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[6]) );
HALF_ADDER HA_52 (.DATA_A (LATCHED_PP[5]) , .DATA_B (LATCHED_PP[6]) , .SAVE (SUM[62]) , .CARRY (CARRY[62]) );
FLIPFLOP LA_192 (.DIN (SUMMAND[575]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[7]) );
assign SUM[63] = LATCHED_PP[7];
endmodule
module INVBLOCK ( GIN, PHI, GOUT );
input GIN;
input PHI;
output GOUT;
assign GOUT = ~ GIN;
endmodule
module XXOR1 ( A, B, GIN, PHI, SUM );
input A;
input B;
input GIN;
input PHI;
output SUM;
assign SUM = ( ~ (A ^ B)) ^ GIN;
endmodule
module BLOCK0 ( A, B, PHI, POUT, GOUT );
input A;
input B;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (A | B);
assign GOUT = ~ (A & B);
endmodule
module BLOCK1 ( PIN1, PIN2, GIN1, GIN2, PHI, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 | PIN2);
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule
module BLOCK2 ( PIN1, PIN2, GIN1, GIN2, PHI, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 & PIN2);
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule
module BLOCK1A ( PIN2, GIN1, GIN2, PHI, GOUT );
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule
module BLOCK2A ( PIN2, GIN1, GIN2, PHI, GOUT );
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule
module PRESTAGE_64 ( A, B, CIN, PHI, POUT, GOUT );
input [0:63] A;
input [0:63] B;
input CIN;
input PHI;
output [0:63] POUT;
output [0:64] GOUT;
BLOCK0 U10 (A[0] , B[0] , PHI , POUT[0] , GOUT[1] );
BLOCK0 U11 (A[1] , B[1] , PHI , POUT[1] , GOUT[2] );
BLOCK0 U12 (A[2] , B[2] , PHI , POUT[2] , GOUT[3] );
BLOCK0 U13 (A[3] , B[3] , PHI , POUT[3] , GOUT[4] );
BLOCK0 U14 (A[4] , B[4] , PHI , POUT[4] , GOUT[5] );
BLOCK0 U15 (A[5] , B[5] , PHI , POUT[5] , GOUT[6] );
BLOCK0 U16 (A[6] , B[6] , PHI , POUT[6] , GOUT[7] );
BLOCK0 U17 (A[7] , B[7] , PHI , POUT[7] , GOUT[8] );
BLOCK0 U18 (A[8] , B[8] , PHI , POUT[8] , GOUT[9] );
BLOCK0 U19 (A[9] , B[9] , PHI , POUT[9] , GOUT[10] );
BLOCK0 U110 (A[10] , B[10] , PHI , POUT[10] , GOUT[11] );
BLOCK0 U111 (A[11] , B[11] , PHI , POUT[11] , GOUT[12] );
BLOCK0 U112 (A[12] , B[12] , PHI , POUT[12] , GOUT[13] );
BLOCK0 U113 (A[13] , B[13] , PHI , POUT[13] , GOUT[14] );
BLOCK0 U114 (A[14] , B[14] , PHI , POUT[14] , GOUT[15] );
BLOCK0 U115 (A[15] , B[15] , PHI , POUT[15] , GOUT[16] );
BLOCK0 U116 (A[16] , B[16] , PHI , POUT[16] , GOUT[17] );
BLOCK0 U117 (A[17] , B[17] , PHI , POUT[17] , GOUT[18] );
BLOCK0 U118 (A[18] , B[18] , PHI , POUT[18] , GOUT[19] );
BLOCK0 U119 (A[19] , B[19] , PHI , POUT[19] , GOUT[20] );
BLOCK0 U120 (A[20] , B[20] , PHI , POUT[20] , GOUT[21] );
BLOCK0 U121 (A[21] , B[21] , PHI , POUT[21] , GOUT[22] );
BLOCK0 U122 (A[22] , B[22] , PHI , POUT[22] , GOUT[23] );
BLOCK0 U123 (A[23] , B[23] , PHI , POUT[23] , GOUT[24] );
BLOCK0 U124 (A[24] , B[24] , PHI , POUT[24] , GOUT[25] );
BLOCK0 U125 (A[25] , B[25] , PHI , POUT[25] , GOUT[26] );
BLOCK0 U126 (A[26] , B[26] , PHI , POUT[26] , GOUT[27] );
BLOCK0 U127 (A[27] , B[27] , PHI , POUT[27] , GOUT[28] );
BLOCK0 U128 (A[28] , B[28] , PHI , POUT[28] , GOUT[29] );
BLOCK0 U129 (A[29] , B[29] , PHI , POUT[29] , GOUT[30] );
BLOCK0 U130 (A[30] , B[30] , PHI , POUT[30] , GOUT[31] );
BLOCK0 U131 (A[31] , B[31] , PHI , POUT[31] , GOUT[32] );
BLOCK0 U132 (A[32] , B[32] , PHI , POUT[32] , GOUT[33] );
BLOCK0 U133 (A[33] , B[33] , PHI , POUT[33] , GOUT[34] );
BLOCK0 U134 (A[34] , B[34] , PHI , POUT[34] , GOUT[35] );
BLOCK0 U135 (A[35] , B[35] , PHI , POUT[35] , GOUT[36] );
BLOCK0 U136 (A[36] , B[36] , PHI , POUT[36] , GOUT[37] );
BLOCK0 U137 (A[37] , B[37] , PHI , POUT[37] , GOUT[38] );
BLOCK0 U138 (A[38] , B[38] , PHI , POUT[38] , GOUT[39] );
BLOCK0 U139 (A[39] , B[39] , PHI , POUT[39] , GOUT[40] );
BLOCK0 U140 (A[40] , B[40] , PHI , POUT[40] , GOUT[41] );
BLOCK0 U141 (A[41] , B[41] , PHI , POUT[41] , GOUT[42] );
BLOCK0 U142 (A[42] , B[42] , PHI , POUT[42] , GOUT[43] );
BLOCK0 U143 (A[43] , B[43] , PHI , POUT[43] , GOUT[44] );
BLOCK0 U144 (A[44] , B[44] , PHI , POUT[44] , GOUT[45] );
BLOCK0 U145 (A[45] , B[45] , PHI , POUT[45] , GOUT[46] );
BLOCK0 U146 (A[46] , B[46] , PHI , POUT[46] , GOUT[47] );
BLOCK0 U147 (A[47] , B[47] , PHI , POUT[47] , GOUT[48] );
BLOCK0 U148 (A[48] , B[48] , PHI , POUT[48] , GOUT[49] );
BLOCK0 U149 (A[49] , B[49] , PHI , POUT[49] , GOUT[50] );
BLOCK0 U150 (A[50] , B[50] , PHI , POUT[50] , GOUT[51] );
BLOCK0 U151 (A[51] , B[51] , PHI , POUT[51] , GOUT[52] );
BLOCK0 U152 (A[52] , B[52] , PHI , POUT[52] , GOUT[53] );
BLOCK0 U153 (A[53] , B[53] , PHI , POUT[53] , GOUT[54] );
BLOCK0 U154 (A[54] , B[54] , PHI , POUT[54] , GOUT[55] );
BLOCK0 U155 (A[55] , B[55] , PHI , POUT[55] , GOUT[56] );
BLOCK0 U156 (A[56] , B[56] , PHI , POUT[56] , GOUT[57] );
BLOCK0 U157 (A[57] , B[57] , PHI , POUT[57] , GOUT[58] );
BLOCK0 U158 (A[58] , B[58] , PHI , POUT[58] , GOUT[59] );
BLOCK0 U159 (A[59] , B[59] , PHI , POUT[59] , GOUT[60] );
BLOCK0 U160 (A[60] , B[60] , PHI , POUT[60] , GOUT[61] );
BLOCK0 U161 (A[61] , B[61] , PHI , POUT[61] , GOUT[62] );
BLOCK0 U162 (A[62] , B[62] , PHI , POUT[62] , GOUT[63] );
BLOCK0 U163 (A[63] , B[63] , PHI , POUT[63] , GOUT[64] );
INVBLOCK U2 (CIN , PHI , GOUT[0] );
endmodule
module DBLC_0_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:63] PIN;
input [0:64] GIN;
input PHI;
output [0:62] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
BLOCK1A U21 (PIN[0] , GIN[0] , GIN[1] , PHI , GOUT[1] );
BLOCK1 U32 (PIN[0] , PIN[1] , GIN[1] , GIN[2] , PHI , POUT[0] , GOUT[2] );
BLOCK1 U33 (PIN[1] , PIN[2] , GIN[2] , GIN[3] , PHI , POUT[1] , GOUT[3] );
BLOCK1 U34 (PIN[2] , PIN[3] , GIN[3] , GIN[4] , PHI , POUT[2] , GOUT[4] );
BLOCK1 U35 (PIN[3] , PIN[4] , GIN[4] , GIN[5] , PHI , POUT[3] , GOUT[5] );
BLOCK1 U36 (PIN[4] , PIN[5] , GIN[5] , GIN[6] , PHI , POUT[4] , GOUT[6] );
BLOCK1 U37 (PIN[5] , PIN[6] , GIN[6] , GIN[7] , PHI , POUT[5] , GOUT[7] );
BLOCK1 U38 (PIN[6] , PIN[7] , GIN[7] , GIN[8] , PHI , POUT[6] , GOUT[8] );
BLOCK1 U39 (PIN[7] , PIN[8] , GIN[8] , GIN[9] , PHI , POUT[7] , GOUT[9] );
BLOCK1 U310 (PIN[8] , PIN[9] , GIN[9] , GIN[10] , PHI , POUT[8] , GOUT[10] );
BLOCK1 U311 (PIN[9] , PIN[10] , GIN[10] , GIN[11] , PHI , POUT[9] , GOUT[11] );
BLOCK1 U312 (PIN[10] , PIN[11] , GIN[11] , GIN[12] , PHI , POUT[10] , GOUT[12] );
BLOCK1 U313 (PIN[11] , PIN[12] , GIN[12] , GIN[13] , PHI , POUT[11] , GOUT[13] );
BLOCK1 U314 (PIN[12] , PIN[13] , GIN[13] , GIN[14] , PHI , POUT[12] , GOUT[14] );
BLOCK1 U315 (PIN[13] , PIN[14] , GIN[14] , GIN[15] , PHI , POUT[13] , GOUT[15] );
BLOCK1 U316 (PIN[14] , PIN[15] , GIN[15] , GIN[16] , PHI , POUT[14] , GOUT[16] );
BLOCK1 U317 (PIN[15] , PIN[16] , GIN[16] , GIN[17] , PHI , POUT[15] , GOUT[17] );
BLOCK1 U318 (PIN[16] , PIN[17] , GIN[17] , GIN[18] , PHI , POUT[16] , GOUT[18] );
BLOCK1 U319 (PIN[17] , PIN[18] , GIN[18] , GIN[19] , PHI , POUT[17] , GOUT[19] );
BLOCK1 U320 (PIN[18] , PIN[19] , GIN[19] , GIN[20] , PHI , POUT[18] , GOUT[20] );
BLOCK1 U321 (PIN[19] , PIN[20] , GIN[20] , GIN[21] , PHI , POUT[19] , GOUT[21] );
BLOCK1 U322 (PIN[20] , PIN[21] , GIN[21] , GIN[22] , PHI , POUT[20] , GOUT[22] );
BLOCK1 U323 (PIN[21] , PIN[22] , GIN[22] , GIN[23] , PHI , POUT[21] , GOUT[23] );
BLOCK1 U324 (PIN[22] , PIN[23] , GIN[23] , GIN[24] , PHI , POUT[22] , GOUT[24] );
BLOCK1 U325 (PIN[23] , PIN[24] , GIN[24] , GIN[25] , PHI , POUT[23] , GOUT[25] );
BLOCK1 U326 (PIN[24] , PIN[25] , GIN[25] , GIN[26] , PHI , POUT[24] , GOUT[26] );
BLOCK1 U327 (PIN[25] , PIN[26] , GIN[26] , GIN[27] , PHI , POUT[25] , GOUT[27] );
BLOCK1 U328 (PIN[26] , PIN[27] , GIN[27] , GIN[28] , PHI , POUT[26] , GOUT[28] );
BLOCK1 U329 (PIN[27] , PIN[28] , GIN[28] , GIN[29] , PHI , POUT[27] , GOUT[29] );
BLOCK1 U330 (PIN[28] , PIN[29] , GIN[29] , GIN[30] , PHI , POUT[28] , GOUT[30] );
BLOCK1 U331 (PIN[29] , PIN[30] , GIN[30] , GIN[31] , PHI , POUT[29] , GOUT[31] );
BLOCK1 U332 (PIN[30] , PIN[31] , GIN[31] , GIN[32] , PHI , POUT[30] , GOUT[32] );
BLOCK1 U333 (PIN[31] , PIN[32] , GIN[32] , GIN[33] , PHI , POUT[31] , GOUT[33] );
BLOCK1 U334 (PIN[32] , PIN[33] , GIN[33] , GIN[34] , PHI , POUT[32] , GOUT[34] );
BLOCK1 U335 (PIN[33] , PIN[34] , GIN[34] , GIN[35] , PHI , POUT[33] , GOUT[35] );
BLOCK1 U336 (PIN[34] , PIN[35] , GIN[35] , GIN[36] , PHI , POUT[34] , GOUT[36] );
BLOCK1 U337 (PIN[35] , PIN[36] , GIN[36] , GIN[37] , PHI , POUT[35] , GOUT[37] );
BLOCK1 U338 (PIN[36] , PIN[37] , GIN[37] , GIN[38] , PHI , POUT[36] , GOUT[38] );
BLOCK1 U339 (PIN[37] , PIN[38] , GIN[38] , GIN[39] , PHI , POUT[37] , GOUT[39] );
BLOCK1 U340 (PIN[38] , PIN[39] , GIN[39] , GIN[40] , PHI , POUT[38] , GOUT[40] );
BLOCK1 U341 (PIN[39] , PIN[40] , GIN[40] , GIN[41] , PHI , POUT[39] , GOUT[41] );
BLOCK1 U342 (PIN[40] , PIN[41] , GIN[41] , GIN[42] , PHI , POUT[40] , GOUT[42] );
BLOCK1 U343 (PIN[41] , PIN[42] , GIN[42] , GIN[43] , PHI , POUT[41] , GOUT[43] );
BLOCK1 U344 (PIN[42] , PIN[43] , GIN[43] , GIN[44] , PHI , POUT[42] , GOUT[44] );
BLOCK1 U345 (PIN[43] , PIN[44] , GIN[44] , GIN[45] , PHI , POUT[43] , GOUT[45] );
BLOCK1 U346 (PIN[44] , PIN[45] , GIN[45] , GIN[46] , PHI , POUT[44] , GOUT[46] );
BLOCK1 U347 (PIN[45] , PIN[46] , GIN[46] , GIN[47] , PHI , POUT[45] , GOUT[47] );
BLOCK1 U348 (PIN[46] , PIN[47] , GIN[47] , GIN[48] , PHI , POUT[46] , GOUT[48] );
BLOCK1 U349 (PIN[47] , PIN[48] , GIN[48] , GIN[49] , PHI , POUT[47] , GOUT[49] );
BLOCK1 U350 (PIN[48] , PIN[49] , GIN[49] , GIN[50] , PHI , POUT[48] , GOUT[50] );
BLOCK1 U351 (PIN[49] , PIN[50] , GIN[50] , GIN[51] , PHI , POUT[49] , GOUT[51] );
BLOCK1 U352 (PIN[50] , PIN[51] , GIN[51] , GIN[52] , PHI , POUT[50] , GOUT[52] );
BLOCK1 U353 (PIN[51] , PIN[52] , GIN[52] , GIN[53] , PHI , POUT[51] , GOUT[53] );
BLOCK1 U354 (PIN[52] , PIN[53] , GIN[53] , GIN[54] , PHI , POUT[52] , GOUT[54] );
BLOCK1 U355 (PIN[53] , PIN[54] , GIN[54] , GIN[55] , PHI , POUT[53] , GOUT[55] );
BLOCK1 U356 (PIN[54] , PIN[55] , GIN[55] , GIN[56] , PHI , POUT[54] , GOUT[56] );
BLOCK1 U357 (PIN[55] , PIN[56] , GIN[56] , GIN[57] , PHI , POUT[55] , GOUT[57] );
BLOCK1 U358 (PIN[56] , PIN[57] , GIN[57] , GIN[58] , PHI , POUT[56] , GOUT[58] );
BLOCK1 U359 (PIN[57] , PIN[58] , GIN[58] , GIN[59] , PHI , POUT[57] , GOUT[59] );
BLOCK1 U360 (PIN[58] , PIN[59] , GIN[59] , GIN[60] , PHI , POUT[58] , GOUT[60] );
BLOCK1 U361 (PIN[59] , PIN[60] , GIN[60] , GIN[61] , PHI , POUT[59] , GOUT[61] );
BLOCK1 U362 (PIN[60] , PIN[61] , GIN[61] , GIN[62] , PHI , POUT[60] , GOUT[62] );
BLOCK1 U363 (PIN[61] , PIN[62] , GIN[62] , GIN[63] , PHI , POUT[61] , GOUT[63] );
BLOCK1 U364 (PIN[62] , PIN[63] , GIN[63] , GIN[64] , PHI , POUT[62] , GOUT[64] );
endmodule
module DBLC_1_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:62] PIN;
input [0:64] GIN;
input PHI;
output [0:60] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
BLOCK2A U22 (PIN[0] , GIN[0] , GIN[2] , PHI , GOUT[2] );
BLOCK2A U23 (PIN[1] , GIN[1] , GIN[3] , PHI , GOUT[3] );
BLOCK2 U34 (PIN[0] , PIN[2] , GIN[2] , GIN[4] , PHI , POUT[0] , GOUT[4] );
BLOCK2 U35 (PIN[1] , PIN[3] , GIN[3] , GIN[5] , PHI , POUT[1] , GOUT[5] );
BLOCK2 U36 (PIN[2] , PIN[4] , GIN[4] , GIN[6] , PHI , POUT[2] , GOUT[6] );
BLOCK2 U37 (PIN[3] , PIN[5] , GIN[5] , GIN[7] , PHI , POUT[3] , GOUT[7] );
BLOCK2 U38 (PIN[4] , PIN[6] , GIN[6] , GIN[8] , PHI , POUT[4] , GOUT[8] );
BLOCK2 U39 (PIN[5] , PIN[7] , GIN[7] , GIN[9] , PHI , POUT[5] , GOUT[9] );
BLOCK2 U310 (PIN[6] , PIN[8] , GIN[8] , GIN[10] , PHI , POUT[6] , GOUT[10] );
BLOCK2 U311 (PIN[7] , PIN[9] , GIN[9] , GIN[11] , PHI , POUT[7] , GOUT[11] );
BLOCK2 U312 (PIN[8] , PIN[10] , GIN[10] , GIN[12] , PHI , POUT[8] , GOUT[12] );
BLOCK2 U313 (PIN[9] , PIN[11] , GIN[11] , GIN[13] , PHI , POUT[9] , GOUT[13] );
BLOCK2 U314 (PIN[10] , PIN[12] , GIN[12] , GIN[14] , PHI , POUT[10] , GOUT[14] );
BLOCK2 U315 (PIN[11] , PIN[13] , GIN[13] , GIN[15] , PHI , POUT[11] , GOUT[15] );
BLOCK2 U316 (PIN[12] , PIN[14] , GIN[14] , GIN[16] , PHI , POUT[12] , GOUT[16] );
BLOCK2 U317 (PIN[13] , PIN[15] , GIN[15] , GIN[17] , PHI , POUT[13] , GOUT[17] );
BLOCK2 U318 (PIN[14] , PIN[16] , GIN[16] , GIN[18] , PHI , POUT[14] , GOUT[18] );
BLOCK2 U319 (PIN[15] , PIN[17] , GIN[17] , GIN[19] , PHI , POUT[15] , GOUT[19] );
BLOCK2 U320 (PIN[16] , PIN[18] , GIN[18] , GIN[20] , PHI , POUT[16] , GOUT[20] );
BLOCK2 U321 (PIN[17] , PIN[19] , GIN[19] , GIN[21] , PHI , POUT[17] , GOUT[21] );
BLOCK2 U322 (PIN[18] , PIN[20] , GIN[20] , GIN[22] , PHI , POUT[18] , GOUT[22] );
BLOCK2 U323 (PIN[19] , PIN[21] , GIN[21] , GIN[23] , PHI , POUT[19] , GOUT[23] );
BLOCK2 U324 (PIN[20] , PIN[22] , GIN[22] , GIN[24] , PHI , POUT[20] , GOUT[24] );
BLOCK2 U325 (PIN[21] , PIN[23] , GIN[23] , GIN[25] , PHI , POUT[21] , GOUT[25] );
BLOCK2 U326 (PIN[22] , PIN[24] , GIN[24] , GIN[26] , PHI , POUT[22] , GOUT[26] );
BLOCK2 U327 (PIN[23] , PIN[25] , GIN[25] , GIN[27] , PHI , POUT[23] , GOUT[27] );
BLOCK2 U328 (PIN[24] , PIN[26] , GIN[26] , GIN[28] , PHI , POUT[24] , GOUT[28] );
BLOCK2 U329 (PIN[25] , PIN[27] , GIN[27] , GIN[29] , PHI , POUT[25] , GOUT[29] );
BLOCK2 U330 (PIN[26] , PIN[28] , GIN[28] , GIN[30] , PHI , POUT[26] , GOUT[30] );
BLOCK2 U331 (PIN[27] , PIN[29] , GIN[29] , GIN[31] , PHI , POUT[27] , GOUT[31] );
BLOCK2 U332 (PIN[28] , PIN[30] , GIN[30] , GIN[32] , PHI , POUT[28] , GOUT[32] );
BLOCK2 U333 (PIN[29] , PIN[31] , GIN[31] , GIN[33] , PHI , POUT[29] , GOUT[33] );
BLOCK2 U334 (PIN[30] , PIN[32] , GIN[32] , GIN[34] , PHI , POUT[30] , GOUT[34] );
BLOCK2 U335 (PIN[31] , PIN[33] , GIN[33] , GIN[35] , PHI , POUT[31] , GOUT[35] );
BLOCK2 U336 (PIN[32] , PIN[34] , GIN[34] , GIN[36] , PHI , POUT[32] , GOUT[36] );
BLOCK2 U337 (PIN[33] , PIN[35] , GIN[35] , GIN[37] , PHI , POUT[33] , GOUT[37] );
BLOCK2 U338 (PIN[34] , PIN[36] , GIN[36] , GIN[38] , PHI , POUT[34] , GOUT[38] );
BLOCK2 U339 (PIN[35] , PIN[37] , GIN[37] , GIN[39] , PHI , POUT[35] , GOUT[39] );
BLOCK2 U340 (PIN[36] , PIN[38] , GIN[38] , GIN[40] , PHI , POUT[36] , GOUT[40] );
BLOCK2 U341 (PIN[37] , PIN[39] , GIN[39] , GIN[41] , PHI , POUT[37] , GOUT[41] );
BLOCK2 U342 (PIN[38] , PIN[40] , GIN[40] , GIN[42] , PHI , POUT[38] , GOUT[42] );
BLOCK2 U343 (PIN[39] , PIN[41] , GIN[41] , GIN[43] , PHI , POUT[39] , GOUT[43] );
BLOCK2 U344 (PIN[40] , PIN[42] , GIN[42] , GIN[44] , PHI , POUT[40] , GOUT[44] );
BLOCK2 U345 (PIN[41] , PIN[43] , GIN[43] , GIN[45] , PHI , POUT[41] , GOUT[45] );
BLOCK2 U346 (PIN[42] , PIN[44] , GIN[44] , GIN[46] , PHI , POUT[42] , GOUT[46] );
BLOCK2 U347 (PIN[43] , PIN[45] , GIN[45] , GIN[47] , PHI , POUT[43] , GOUT[47] );
BLOCK2 U348 (PIN[44] , PIN[46] , GIN[46] , GIN[48] , PHI , POUT[44] , GOUT[48] );
BLOCK2 U349 (PIN[45] , PIN[47] , GIN[47] , GIN[49] , PHI , POUT[45] , GOUT[49] );
BLOCK2 U350 (PIN[46] , PIN[48] , GIN[48] , GIN[50] , PHI , POUT[46] , GOUT[50] );
BLOCK2 U351 (PIN[47] , PIN[49] , GIN[49] , GIN[51] , PHI , POUT[47] , GOUT[51] );
BLOCK2 U352 (PIN[48] , PIN[50] , GIN[50] , GIN[52] , PHI , POUT[48] , GOUT[52] );
BLOCK2 U353 (PIN[49] , PIN[51] , GIN[51] , GIN[53] , PHI , POUT[49] , GOUT[53] );
BLOCK2 U354 (PIN[50] , PIN[52] , GIN[52] , GIN[54] , PHI , POUT[50] , GOUT[54] );
BLOCK2 U355 (PIN[51] , PIN[53] , GIN[53] , GIN[55] , PHI , POUT[51] , GOUT[55] );
BLOCK2 U356 (PIN[52] , PIN[54] , GIN[54] , GIN[56] , PHI , POUT[52] , GOUT[56] );
BLOCK2 U357 (PIN[53] , PIN[55] , GIN[55] , GIN[57] , PHI , POUT[53] , GOUT[57] );
BLOCK2 U358 (PIN[54] , PIN[56] , GIN[56] , GIN[58] , PHI , POUT[54] , GOUT[58] );
BLOCK2 U359 (PIN[55] , PIN[57] , GIN[57] , GIN[59] , PHI , POUT[55] , GOUT[59] );
BLOCK2 U360 (PIN[56] , PIN[58] , GIN[58] , GIN[60] , PHI , POUT[56] , GOUT[60] );
BLOCK2 U361 (PIN[57] , PIN[59] , GIN[59] , GIN[61] , PHI , POUT[57] , GOUT[61] );
BLOCK2 U362 (PIN[58] , PIN[60] , GIN[60] , GIN[62] , PHI , POUT[58] , GOUT[62] );
BLOCK2 U363 (PIN[59] , PIN[61] , GIN[61] , GIN[63] , PHI , POUT[59] , GOUT[63] );
BLOCK2 U364 (PIN[60] , PIN[62] , GIN[62] , GIN[64] , PHI , POUT[60] , GOUT[64] );
endmodule
module DBLC_2_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:60] PIN;
input [0:64] GIN;
input PHI;
output [0:56] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
BLOCK1A U24 (PIN[0] , GIN[0] , GIN[4] , PHI , GOUT[4] );
BLOCK1A U25 (PIN[1] , GIN[1] , GIN[5] , PHI , GOUT[5] );
BLOCK1A U26 (PIN[2] , GIN[2] , GIN[6] , PHI , GOUT[6] );
BLOCK1A U27 (PIN[3] , GIN[3] , GIN[7] , PHI , GOUT[7] );
BLOCK1 U38 (PIN[0] , PIN[4] , GIN[4] , GIN[8] , PHI , POUT[0] , GOUT[8] );
BLOCK1 U39 (PIN[1] , PIN[5] , GIN[5] , GIN[9] , PHI , POUT[1] , GOUT[9] );
BLOCK1 U310 (PIN[2] , PIN[6] , GIN[6] , GIN[10] , PHI , POUT[2] , GOUT[10] );
BLOCK1 U311 (PIN[3] , PIN[7] , GIN[7] , GIN[11] , PHI , POUT[3] , GOUT[11] );
BLOCK1 U312 (PIN[4] , PIN[8] , GIN[8] , GIN[12] , PHI , POUT[4] , GOUT[12] );
BLOCK1 U313 (PIN[5] , PIN[9] , GIN[9] , GIN[13] , PHI , POUT[5] , GOUT[13] );
BLOCK1 U314 (PIN[6] , PIN[10] , GIN[10] , GIN[14] , PHI , POUT[6] , GOUT[14] );
BLOCK1 U315 (PIN[7] , PIN[11] , GIN[11] , GIN[15] , PHI , POUT[7] , GOUT[15] );
BLOCK1 U316 (PIN[8] , PIN[12] , GIN[12] , GIN[16] , PHI , POUT[8] , GOUT[16] );
BLOCK1 U317 (PIN[9] , PIN[13] , GIN[13] , GIN[17] , PHI , POUT[9] , GOUT[17] );
BLOCK1 U318 (PIN[10] , PIN[14] , GIN[14] , GIN[18] , PHI , POUT[10] , GOUT[18] );
BLOCK1 U319 (PIN[11] , PIN[15] , GIN[15] , GIN[19] , PHI , POUT[11] , GOUT[19] );
BLOCK1 U320 (PIN[12] , PIN[16] , GIN[16] , GIN[20] , PHI , POUT[12] , GOUT[20] );
BLOCK1 U321 (PIN[13] , PIN[17] , GIN[17] , GIN[21] , PHI , POUT[13] , GOUT[21] );
BLOCK1 U322 (PIN[14] , PIN[18] , GIN[18] , GIN[22] , PHI , POUT[14] , GOUT[22] );
BLOCK1 U323 (PIN[15] , PIN[19] , GIN[19] , GIN[23] , PHI , POUT[15] , GOUT[23] );
BLOCK1 U324 (PIN[16] , PIN[20] , GIN[20] , GIN[24] , PHI , POUT[16] , GOUT[24] );
BLOCK1 U325 (PIN[17] , PIN[21] , GIN[21] , GIN[25] , PHI , POUT[17] , GOUT[25] );
BLOCK1 U326 (PIN[18] , PIN[22] , GIN[22] , GIN[26] , PHI , POUT[18] , GOUT[26] );
BLOCK1 U327 (PIN[19] , PIN[23] , GIN[23] , GIN[27] , PHI , POUT[19] , GOUT[27] );
BLOCK1 U328 (PIN[20] , PIN[24] , GIN[24] , GIN[28] , PHI , POUT[20] , GOUT[28] );
BLOCK1 U329 (PIN[21] , PIN[25] , GIN[25] , GIN[29] , PHI , POUT[21] , GOUT[29] );
BLOCK1 U330 (PIN[22] , PIN[26] , GIN[26] , GIN[30] , PHI , POUT[22] , GOUT[30] );
BLOCK1 U331 (PIN[23] , PIN[27] , GIN[27] , GIN[31] , PHI , POUT[23] , GOUT[31] );
BLOCK1 U332 (PIN[24] , PIN[28] , GIN[28] , GIN[32] , PHI , POUT[24] , GOUT[32] );
BLOCK1 U333 (PIN[25] , PIN[29] , GIN[29] , GIN[33] , PHI , POUT[25] , GOUT[33] );
BLOCK1 U334 (PIN[26] , PIN[30] , GIN[30] , GIN[34] , PHI , POUT[26] , GOUT[34] );
BLOCK1 U335 (PIN[27] , PIN[31] , GIN[31] , GIN[35] , PHI , POUT[27] , GOUT[35] );
BLOCK1 U336 (PIN[28] , PIN[32] , GIN[32] , GIN[36] , PHI , POUT[28] , GOUT[36] );
BLOCK1 U337 (PIN[29] , PIN[33] , GIN[33] , GIN[37] , PHI , POUT[29] , GOUT[37] );
BLOCK1 U338 (PIN[30] , PIN[34] , GIN[34] , GIN[38] , PHI , POUT[30] , GOUT[38] );
BLOCK1 U339 (PIN[31] , PIN[35] , GIN[35] , GIN[39] , PHI , POUT[31] , GOUT[39] );
BLOCK1 U340 (PIN[32] , PIN[36] , GIN[36] , GIN[40] , PHI , POUT[32] , GOUT[40] );
BLOCK1 U341 (PIN[33] , PIN[37] , GIN[37] , GIN[41] , PHI , POUT[33] , GOUT[41] );
BLOCK1 U342 (PIN[34] , PIN[38] , GIN[38] , GIN[42] , PHI , POUT[34] , GOUT[42] );
BLOCK1 U343 (PIN[35] , PIN[39] , GIN[39] , GIN[43] , PHI , POUT[35] , GOUT[43] );
BLOCK1 U344 (PIN[36] , PIN[40] , GIN[40] , GIN[44] , PHI , POUT[36] , GOUT[44] );
BLOCK1 U345 (PIN[37] , PIN[41] , GIN[41] , GIN[45] , PHI , POUT[37] , GOUT[45] );
BLOCK1 U346 (PIN[38] , PIN[42] , GIN[42] , GIN[46] , PHI , POUT[38] , GOUT[46] );
BLOCK1 U347 (PIN[39] , PIN[43] , GIN[43] , GIN[47] , PHI , POUT[39] , GOUT[47] );
BLOCK1 U348 (PIN[40] , PIN[44] , GIN[44] , GIN[48] , PHI , POUT[40] , GOUT[48] );
BLOCK1 U349 (PIN[41] , PIN[45] , GIN[45] , GIN[49] , PHI , POUT[41] , GOUT[49] );
BLOCK1 U350 (PIN[42] , PIN[46] , GIN[46] , GIN[50] , PHI , POUT[42] , GOUT[50] );
BLOCK1 U351 (PIN[43] , PIN[47] , GIN[47] , GIN[51] , PHI , POUT[43] , GOUT[51] );
BLOCK1 U352 (PIN[44] , PIN[48] , GIN[48] , GIN[52] , PHI , POUT[44] , GOUT[52] );
BLOCK1 U353 (PIN[45] , PIN[49] , GIN[49] , GIN[53] , PHI , POUT[45] , GOUT[53] );
BLOCK1 U354 (PIN[46] , PIN[50] , GIN[50] , GIN[54] , PHI , POUT[46] , GOUT[54] );
BLOCK1 U355 (PIN[47] , PIN[51] , GIN[51] , GIN[55] , PHI , POUT[47] , GOUT[55] );
BLOCK1 U356 (PIN[48] , PIN[52] , GIN[52] , GIN[56] , PHI , POUT[48] , GOUT[56] );
BLOCK1 U357 (PIN[49] , PIN[53] , GIN[53] , GIN[57] , PHI , POUT[49] , GOUT[57] );
BLOCK1 U358 (PIN[50] , PIN[54] , GIN[54] , GIN[58] , PHI , POUT[50] , GOUT[58] );
BLOCK1 U359 (PIN[51] , PIN[55] , GIN[55] , GIN[59] , PHI , POUT[51] , GOUT[59] );
BLOCK1 U360 (PIN[52] , PIN[56] , GIN[56] , GIN[60] , PHI , POUT[52] , GOUT[60] );
BLOCK1 U361 (PIN[53] , PIN[57] , GIN[57] , GIN[61] , PHI , POUT[53] , GOUT[61] );
BLOCK1 U362 (PIN[54] , PIN[58] , GIN[58] , GIN[62] , PHI , POUT[54] , GOUT[62] );
BLOCK1 U363 (PIN[55] , PIN[59] , GIN[59] , GIN[63] , PHI , POUT[55] , GOUT[63] );
BLOCK1 U364 (PIN[56] , PIN[60] , GIN[60] , GIN[64] , PHI , POUT[56] , GOUT[64] );
endmodule
module DBLC_3_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:56] PIN;
input [0:64] GIN;
input PHI;
output [0:48] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
BLOCK2A U28 (PIN[0] , GIN[0] , GIN[8] , PHI , GOUT[8] );
BLOCK2A U29 (PIN[1] , GIN[1] , GIN[9] , PHI , GOUT[9] );
BLOCK2A U210 (PIN[2] , GIN[2] , GIN[10] , PHI , GOUT[10] );
BLOCK2A U211 (PIN[3] , GIN[3] , GIN[11] , PHI , GOUT[11] );
BLOCK2A U212 (PIN[4] , GIN[4] , GIN[12] , PHI , GOUT[12] );
BLOCK2A U213 (PIN[5] , GIN[5] , GIN[13] , PHI , GOUT[13] );
BLOCK2A U214 (PIN[6] , GIN[6] , GIN[14] , PHI , GOUT[14] );
BLOCK2A U215 (PIN[7] , GIN[7] , GIN[15] , PHI , GOUT[15] );
BLOCK2 U316 (PIN[0] , PIN[8] , GIN[8] , GIN[16] , PHI , POUT[0] , GOUT[16] );
BLOCK2 U317 (PIN[1] , PIN[9] , GIN[9] , GIN[17] , PHI , POUT[1] , GOUT[17] );
BLOCK2 U318 (PIN[2] , PIN[10] , GIN[10] , GIN[18] , PHI , POUT[2] , GOUT[18] );
BLOCK2 U319 (PIN[3] , PIN[11] , GIN[11] , GIN[19] , PHI , POUT[3] , GOUT[19] );
BLOCK2 U320 (PIN[4] , PIN[12] , GIN[12] , GIN[20] , PHI , POUT[4] , GOUT[20] );
BLOCK2 U321 (PIN[5] , PIN[13] , GIN[13] , GIN[21] , PHI , POUT[5] , GOUT[21] );
BLOCK2 U322 (PIN[6] , PIN[14] , GIN[14] , GIN[22] , PHI , POUT[6] , GOUT[22] );
BLOCK2 U323 (PIN[7] , PIN[15] , GIN[15] , GIN[23] , PHI , POUT[7] , GOUT[23] );
BLOCK2 U324 (PIN[8] , PIN[16] , GIN[16] , GIN[24] , PHI , POUT[8] , GOUT[24] );
BLOCK2 U325 (PIN[9] , PIN[17] , GIN[17] , GIN[25] , PHI , POUT[9] , GOUT[25] );
BLOCK2 U326 (PIN[10] , PIN[18] , GIN[18] , GIN[26] , PHI , POUT[10] , GOUT[26] );
BLOCK2 U327 (PIN[11] , PIN[19] , GIN[19] , GIN[27] , PHI , POUT[11] , GOUT[27] );
BLOCK2 U328 (PIN[12] , PIN[20] , GIN[20] , GIN[28] , PHI , POUT[12] , GOUT[28] );
BLOCK2 U329 (PIN[13] , PIN[21] , GIN[21] , GIN[29] , PHI , POUT[13] , GOUT[29] );
BLOCK2 U330 (PIN[14] , PIN[22] , GIN[22] , GIN[30] , PHI , POUT[14] , GOUT[30] );
BLOCK2 U331 (PIN[15] , PIN[23] , GIN[23] , GIN[31] , PHI , POUT[15] , GOUT[31] );
BLOCK2 U332 (PIN[16] , PIN[24] , GIN[24] , GIN[32] , PHI , POUT[16] , GOUT[32] );
BLOCK2 U333 (PIN[17] , PIN[25] , GIN[25] , GIN[33] , PHI , POUT[17] , GOUT[33] );
BLOCK2 U334 (PIN[18] , PIN[26] , GIN[26] , GIN[34] , PHI , POUT[18] , GOUT[34] );
BLOCK2 U335 (PIN[19] , PIN[27] , GIN[27] , GIN[35] , PHI , POUT[19] , GOUT[35] );
BLOCK2 U336 (PIN[20] , PIN[28] , GIN[28] , GIN[36] , PHI , POUT[20] , GOUT[36] );
BLOCK2 U337 (PIN[21] , PIN[29] , GIN[29] , GIN[37] , PHI , POUT[21] , GOUT[37] );
BLOCK2 U338 (PIN[22] , PIN[30] , GIN[30] , GIN[38] , PHI , POUT[22] , GOUT[38] );
BLOCK2 U339 (PIN[23] , PIN[31] , GIN[31] , GIN[39] , PHI , POUT[23] , GOUT[39] );
BLOCK2 U340 (PIN[24] , PIN[32] , GIN[32] , GIN[40] , PHI , POUT[24] , GOUT[40] );
BLOCK2 U341 (PIN[25] , PIN[33] , GIN[33] , GIN[41] , PHI , POUT[25] , GOUT[41] );
BLOCK2 U342 (PIN[26] , PIN[34] , GIN[34] , GIN[42] , PHI , POUT[26] , GOUT[42] );
BLOCK2 U343 (PIN[27] , PIN[35] , GIN[35] , GIN[43] , PHI , POUT[27] , GOUT[43] );
BLOCK2 U344 (PIN[28] , PIN[36] , GIN[36] , GIN[44] , PHI , POUT[28] , GOUT[44] );
BLOCK2 U345 (PIN[29] , PIN[37] , GIN[37] , GIN[45] , PHI , POUT[29] , GOUT[45] );
BLOCK2 U346 (PIN[30] , PIN[38] , GIN[38] , GIN[46] , PHI , POUT[30] , GOUT[46] );
BLOCK2 U347 (PIN[31] , PIN[39] , GIN[39] , GIN[47] , PHI , POUT[31] , GOUT[47] );
BLOCK2 U348 (PIN[32] , PIN[40] , GIN[40] , GIN[48] , PHI , POUT[32] , GOUT[48] );
BLOCK2 U349 (PIN[33] , PIN[41] , GIN[41] , GIN[49] , PHI , POUT[33] , GOUT[49] );
BLOCK2 U350 (PIN[34] , PIN[42] , GIN[42] , GIN[50] , PHI , POUT[34] , GOUT[50] );
BLOCK2 U351 (PIN[35] , PIN[43] , GIN[43] , GIN[51] , PHI , POUT[35] , GOUT[51] );
BLOCK2 U352 (PIN[36] , PIN[44] , GIN[44] , GIN[52] , PHI , POUT[36] , GOUT[52] );
BLOCK2 U353 (PIN[37] , PIN[45] , GIN[45] , GIN[53] , PHI , POUT[37] , GOUT[53] );
BLOCK2 U354 (PIN[38] , PIN[46] , GIN[46] , GIN[54] , PHI , POUT[38] , GOUT[54] );
BLOCK2 U355 (PIN[39] , PIN[47] , GIN[47] , GIN[55] , PHI , POUT[39] , GOUT[55] );
BLOCK2 U356 (PIN[40] , PIN[48] , GIN[48] , GIN[56] , PHI , POUT[40] , GOUT[56] );
BLOCK2 U357 (PIN[41] , PIN[49] , GIN[49] , GIN[57] , PHI , POUT[41] , GOUT[57] );
BLOCK2 U358 (PIN[42] , PIN[50] , GIN[50] , GIN[58] , PHI , POUT[42] , GOUT[58] );
BLOCK2 U359 (PIN[43] , PIN[51] , GIN[51] , GIN[59] , PHI , POUT[43] , GOUT[59] );
BLOCK2 U360 (PIN[44] , PIN[52] , GIN[52] , GIN[60] , PHI , POUT[44] , GOUT[60] );
BLOCK2 U361 (PIN[45] , PIN[53] , GIN[53] , GIN[61] , PHI , POUT[45] , GOUT[61] );
BLOCK2 U362 (PIN[46] , PIN[54] , GIN[54] , GIN[62] , PHI , POUT[46] , GOUT[62] );
BLOCK2 U363 (PIN[47] , PIN[55] , GIN[55] , GIN[63] , PHI , POUT[47] , GOUT[63] );
BLOCK2 U364 (PIN[48] , PIN[56] , GIN[56] , GIN[64] , PHI , POUT[48] , GOUT[64] );
endmodule
module DBLC_4_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:48] PIN;
input [0:64] GIN;
input PHI;
output [0:32] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
INVBLOCK U18 (GIN[8] , PHI , GOUT[8] );
INVBLOCK U19 (GIN[9] , PHI , GOUT[9] );
INVBLOCK U110 (GIN[10] , PHI , GOUT[10] );
INVBLOCK U111 (GIN[11] , PHI , GOUT[11] );
INVBLOCK U112 (GIN[12] , PHI , GOUT[12] );
INVBLOCK U113 (GIN[13] , PHI , GOUT[13] );
INVBLOCK U114 (GIN[14] , PHI , GOUT[14] );
INVBLOCK U115 (GIN[15] , PHI , GOUT[15] );
BLOCK1A U216 (PIN[0] , GIN[0] , GIN[16] , PHI , GOUT[16] );
BLOCK1A U217 (PIN[1] , GIN[1] , GIN[17] , PHI , GOUT[17] );
BLOCK1A U218 (PIN[2] , GIN[2] , GIN[18] , PHI , GOUT[18] );
BLOCK1A U219 (PIN[3] , GIN[3] , GIN[19] , PHI , GOUT[19] );
BLOCK1A U220 (PIN[4] , GIN[4] , GIN[20] , PHI , GOUT[20] );
BLOCK1A U221 (PIN[5] , GIN[5] , GIN[21] , PHI , GOUT[21] );
BLOCK1A U222 (PIN[6] , GIN[6] , GIN[22] , PHI , GOUT[22] );
BLOCK1A U223 (PIN[7] , GIN[7] , GIN[23] , PHI , GOUT[23] );
BLOCK1A U224 (PIN[8] , GIN[8] , GIN[24] , PHI , GOUT[24] );
BLOCK1A U225 (PIN[9] , GIN[9] , GIN[25] , PHI , GOUT[25] );
BLOCK1A U226 (PIN[10] , GIN[10] , GIN[26] , PHI , GOUT[26] );
BLOCK1A U227 (PIN[11] , GIN[11] , GIN[27] , PHI , GOUT[27] );
BLOCK1A U228 (PIN[12] , GIN[12] , GIN[28] , PHI , GOUT[28] );
BLOCK1A U229 (PIN[13] , GIN[13] , GIN[29] , PHI , GOUT[29] );
BLOCK1A U230 (PIN[14] , GIN[14] , GIN[30] , PHI , GOUT[30] );
BLOCK1A U231 (PIN[15] , GIN[15] , GIN[31] , PHI , GOUT[31] );
BLOCK1 U332 (PIN[0] , PIN[16] , GIN[16] , GIN[32] , PHI , POUT[0] , GOUT[32] );
BLOCK1 U333 (PIN[1] , PIN[17] , GIN[17] , GIN[33] , PHI , POUT[1] , GOUT[33] );
BLOCK1 U334 (PIN[2] , PIN[18] , GIN[18] , GIN[34] , PHI , POUT[2] , GOUT[34] );
BLOCK1 U335 (PIN[3] , PIN[19] , GIN[19] , GIN[35] , PHI , POUT[3] , GOUT[35] );
BLOCK1 U336 (PIN[4] , PIN[20] , GIN[20] , GIN[36] , PHI , POUT[4] , GOUT[36] );
BLOCK1 U337 (PIN[5] , PIN[21] , GIN[21] , GIN[37] , PHI , POUT[5] , GOUT[37] );
BLOCK1 U338 (PIN[6] , PIN[22] , GIN[22] , GIN[38] , PHI , POUT[6] , GOUT[38] );
BLOCK1 U339 (PIN[7] , PIN[23] , GIN[23] , GIN[39] , PHI , POUT[7] , GOUT[39] );
BLOCK1 U340 (PIN[8] , PIN[24] , GIN[24] , GIN[40] , PHI , POUT[8] , GOUT[40] );
BLOCK1 U341 (PIN[9] , PIN[25] , GIN[25] , GIN[41] , PHI , POUT[9] , GOUT[41] );
BLOCK1 U342 (PIN[10] , PIN[26] , GIN[26] , GIN[42] , PHI , POUT[10] , GOUT[42] );
BLOCK1 U343 (PIN[11] , PIN[27] , GIN[27] , GIN[43] , PHI , POUT[11] , GOUT[43] );
BLOCK1 U344 (PIN[12] , PIN[28] , GIN[28] , GIN[44] , PHI , POUT[12] , GOUT[44] );
BLOCK1 U345 (PIN[13] , PIN[29] , GIN[29] , GIN[45] , PHI , POUT[13] , GOUT[45] );
BLOCK1 U346 (PIN[14] , PIN[30] , GIN[30] , GIN[46] , PHI , POUT[14] , GOUT[46] );
BLOCK1 U347 (PIN[15] , PIN[31] , GIN[31] , GIN[47] , PHI , POUT[15] , GOUT[47] );
BLOCK1 U348 (PIN[16] , PIN[32] , GIN[32] , GIN[48] , PHI , POUT[16] , GOUT[48] );
BLOCK1 U349 (PIN[17] , PIN[33] , GIN[33] , GIN[49] , PHI , POUT[17] , GOUT[49] );
BLOCK1 U350 (PIN[18] , PIN[34] , GIN[34] , GIN[50] , PHI , POUT[18] , GOUT[50] );
BLOCK1 U351 (PIN[19] , PIN[35] , GIN[35] , GIN[51] , PHI , POUT[19] , GOUT[51] );
BLOCK1 U352 (PIN[20] , PIN[36] , GIN[36] , GIN[52] , PHI , POUT[20] , GOUT[52] );
BLOCK1 U353 (PIN[21] , PIN[37] , GIN[37] , GIN[53] , PHI , POUT[21] , GOUT[53] );
BLOCK1 U354 (PIN[22] , PIN[38] , GIN[38] , GIN[54] , PHI , POUT[22] , GOUT[54] );
BLOCK1 U355 (PIN[23] , PIN[39] , GIN[39] , GIN[55] , PHI , POUT[23] , GOUT[55] );
BLOCK1 U356 (PIN[24] , PIN[40] , GIN[40] , GIN[56] , PHI , POUT[24] , GOUT[56] );
BLOCK1 U357 (PIN[25] , PIN[41] , GIN[41] , GIN[57] , PHI , POUT[25] , GOUT[57] );
BLOCK1 U358 (PIN[26] , PIN[42] , GIN[42] , GIN[58] , PHI , POUT[26] , GOUT[58] );
BLOCK1 U359 (PIN[27] , PIN[43] , GIN[43] , GIN[59] , PHI , POUT[27] , GOUT[59] );
BLOCK1 U360 (PIN[28] , PIN[44] , GIN[44] , GIN[60] , PHI , POUT[28] , GOUT[60] );
BLOCK1 U361 (PIN[29] , PIN[45] , GIN[45] , GIN[61] , PHI , POUT[29] , GOUT[61] );
BLOCK1 U362 (PIN[30] , PIN[46] , GIN[46] , GIN[62] , PHI , POUT[30] , GOUT[62] );
BLOCK1 U363 (PIN[31] , PIN[47] , GIN[47] , GIN[63] , PHI , POUT[31] , GOUT[63] );
BLOCK1 U364 (PIN[32] , PIN[48] , GIN[48] , GIN[64] , PHI , POUT[32] , GOUT[64] );
endmodule
module DBLC_5_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:32] PIN;
input [0:64] GIN;
input PHI;
output [0:0] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
INVBLOCK U18 (GIN[8] , PHI , GOUT[8] );
INVBLOCK U19 (GIN[9] , PHI , GOUT[9] );
INVBLOCK U110 (GIN[10] , PHI , GOUT[10] );
INVBLOCK U111 (GIN[11] , PHI , GOUT[11] );
INVBLOCK U112 (GIN[12] , PHI , GOUT[12] );
INVBLOCK U113 (GIN[13] , PHI , GOUT[13] );
INVBLOCK U114 (GIN[14] , PHI , GOUT[14] );
INVBLOCK U115 (GIN[15] , PHI , GOUT[15] );
INVBLOCK U116 (GIN[16] , PHI , GOUT[16] );
INVBLOCK U117 (GIN[17] , PHI , GOUT[17] );
INVBLOCK U118 (GIN[18] , PHI , GOUT[18] );
INVBLOCK U119 (GIN[19] , PHI , GOUT[19] );
INVBLOCK U120 (GIN[20] , PHI , GOUT[20] );
INVBLOCK U121 (GIN[21] , PHI , GOUT[21] );
INVBLOCK U122 (GIN[22] , PHI , GOUT[22] );
INVBLOCK U123 (GIN[23] , PHI , GOUT[23] );
INVBLOCK U124 (GIN[24] , PHI , GOUT[24] );
INVBLOCK U125 (GIN[25] , PHI , GOUT[25] );
INVBLOCK U126 (GIN[26] , PHI , GOUT[26] );
INVBLOCK U127 (GIN[27] , PHI , GOUT[27] );
INVBLOCK U128 (GIN[28] , PHI , GOUT[28] );
INVBLOCK U129 (GIN[29] , PHI , GOUT[29] );
INVBLOCK U130 (GIN[30] , PHI , GOUT[30] );
INVBLOCK U131 (GIN[31] , PHI , GOUT[31] );
BLOCK2A U232 (PIN[0] , GIN[0] , GIN[32] , PHI , GOUT[32] );
BLOCK2A U233 (PIN[1] , GIN[1] , GIN[33] , PHI , GOUT[33] );
BLOCK2A U234 (PIN[2] , GIN[2] , GIN[34] , PHI , GOUT[34] );
BLOCK2A U235 (PIN[3] , GIN[3] , GIN[35] , PHI , GOUT[35] );
BLOCK2A U236 (PIN[4] , GIN[4] , GIN[36] , PHI , GOUT[36] );
BLOCK2A U237 (PIN[5] , GIN[5] , GIN[37] , PHI , GOUT[37] );
BLOCK2A U238 (PIN[6] , GIN[6] , GIN[38] , PHI , GOUT[38] );
BLOCK2A U239 (PIN[7] , GIN[7] , GIN[39] , PHI , GOUT[39] );
BLOCK2A U240 (PIN[8] , GIN[8] , GIN[40] , PHI , GOUT[40] );
BLOCK2A U241 (PIN[9] , GIN[9] , GIN[41] , PHI , GOUT[41] );
BLOCK2A U242 (PIN[10] , GIN[10] , GIN[42] , PHI , GOUT[42] );
BLOCK2A U243 (PIN[11] , GIN[11] , GIN[43] , PHI , GOUT[43] );
BLOCK2A U244 (PIN[12] , GIN[12] , GIN[44] , PHI , GOUT[44] );
BLOCK2A U245 (PIN[13] , GIN[13] , GIN[45] , PHI , GOUT[45] );
BLOCK2A U246 (PIN[14] , GIN[14] , GIN[46] , PHI , GOUT[46] );
BLOCK2A U247 (PIN[15] , GIN[15] , GIN[47] , PHI , GOUT[47] );
BLOCK2A U248 (PIN[16] , GIN[16] , GIN[48] , PHI , GOUT[48] );
BLOCK2A U249 (PIN[17] , GIN[17] , GIN[49] , PHI , GOUT[49] );
BLOCK2A U250 (PIN[18] , GIN[18] , GIN[50] , PHI , GOUT[50] );
BLOCK2A U251 (PIN[19] , GIN[19] , GIN[51] , PHI , GOUT[51] );
BLOCK2A U252 (PIN[20] , GIN[20] , GIN[52] , PHI , GOUT[52] );
BLOCK2A U253 (PIN[21] , GIN[21] , GIN[53] , PHI , GOUT[53] );
BLOCK2A U254 (PIN[22] , GIN[22] , GIN[54] , PHI , GOUT[54] );
BLOCK2A U255 (PIN[23] , GIN[23] , GIN[55] , PHI , GOUT[55] );
BLOCK2A U256 (PIN[24] , GIN[24] , GIN[56] , PHI , GOUT[56] );
BLOCK2A U257 (PIN[25] , GIN[25] , GIN[57] , PHI , GOUT[57] );
BLOCK2A U258 (PIN[26] , GIN[26] , GIN[58] , PHI , GOUT[58] );
BLOCK2A U259 (PIN[27] , GIN[27] , GIN[59] , PHI , GOUT[59] );
BLOCK2A U260 (PIN[28] , GIN[28] , GIN[60] , PHI , GOUT[60] );
BLOCK2A U261 (PIN[29] , GIN[29] , GIN[61] , PHI , GOUT[61] );
BLOCK2A U262 (PIN[30] , GIN[30] , GIN[62] , PHI , GOUT[62] );
BLOCK2A U263 (PIN[31] , GIN[31] , GIN[63] , PHI , GOUT[63] );
BLOCK2 U364 (PIN[0] , PIN[32] , GIN[32] , GIN[64] , PHI , POUT[0] , GOUT[64] );
endmodule
module XORSTAGE_64 ( A, B, PBIT, PHI, CARRY, SUM, COUT );
input [0:63] A;
input [0:63] B;
input PBIT;
input PHI;
input [0:64] CARRY;
output [0:63] SUM;
output COUT;
XXOR1 U20 (A[0] , B[0] , CARRY[0] , PHI , SUM[0] );
XXOR1 U21 (A[1] , B[1] , CARRY[1] , PHI , SUM[1] );
XXOR1 U22 (A[2] , B[2] , CARRY[2] , PHI , SUM[2] );
XXOR1 U23 (A[3] , B[3] , CARRY[3] , PHI , SUM[3] );
XXOR1 U24 (A[4] , B[4] , CARRY[4] , PHI , SUM[4] );
XXOR1 U25 (A[5] , B[5] , CARRY[5] , PHI , SUM[5] );
XXOR1 U26 (A[6] , B[6] , CARRY[6] , PHI , SUM[6] );
XXOR1 U27 (A[7] , B[7] , CARRY[7] , PHI , SUM[7] );
XXOR1 U28 (A[8] , B[8] , CARRY[8] , PHI , SUM[8] );
XXOR1 U29 (A[9] , B[9] , CARRY[9] , PHI , SUM[9] );
XXOR1 U210 (A[10] , B[10] , CARRY[10] , PHI , SUM[10] );
XXOR1 U211 (A[11] , B[11] , CARRY[11] , PHI , SUM[11] );
XXOR1 U212 (A[12] , B[12] , CARRY[12] , PHI , SUM[12] );
XXOR1 U213 (A[13] , B[13] , CARRY[13] , PHI , SUM[13] );
XXOR1 U214 (A[14] , B[14] , CARRY[14] , PHI , SUM[14] );
XXOR1 U215 (A[15] , B[15] , CARRY[15] , PHI , SUM[15] );
XXOR1 U216 (A[16] , B[16] , CARRY[16] , PHI , SUM[16] );
XXOR1 U217 (A[17] , B[17] , CARRY[17] , PHI , SUM[17] );
XXOR1 U218 (A[18] , B[18] , CARRY[18] , PHI , SUM[18] );
XXOR1 U219 (A[19] , B[19] , CARRY[19] , PHI , SUM[19] );
XXOR1 U220 (A[20] , B[20] , CARRY[20] , PHI , SUM[20] );
XXOR1 U221 (A[21] , B[21] , CARRY[21] , PHI , SUM[21] );
XXOR1 U222 (A[22] , B[22] , CARRY[22] , PHI , SUM[22] );
XXOR1 U223 (A[23] , B[23] , CARRY[23] , PHI , SUM[23] );
XXOR1 U224 (A[24] , B[24] , CARRY[24] , PHI , SUM[24] );
XXOR1 U225 (A[25] , B[25] , CARRY[25] , PHI , SUM[25] );
XXOR1 U226 (A[26] , B[26] , CARRY[26] , PHI , SUM[26] );
XXOR1 U227 (A[27] , B[27] , CARRY[27] , PHI , SUM[27] );
XXOR1 U228 (A[28] , B[28] , CARRY[28] , PHI , SUM[28] );
XXOR1 U229 (A[29] , B[29] , CARRY[29] , PHI , SUM[29] );
XXOR1 U230 (A[30] , B[30] , CARRY[30] , PHI , SUM[30] );
XXOR1 U231 (A[31] , B[31] , CARRY[31] , PHI , SUM[31] );
XXOR1 U232 (A[32] , B[32] , CARRY[32] , PHI , SUM[32] );
XXOR1 U233 (A[33] , B[33] , CARRY[33] , PHI , SUM[33] );
XXOR1 U234 (A[34] , B[34] , CARRY[34] , PHI , SUM[34] );
XXOR1 U235 (A[35] , B[35] , CARRY[35] , PHI , SUM[35] );
XXOR1 U236 (A[36] , B[36] , CARRY[36] , PHI , SUM[36] );
XXOR1 U237 (A[37] , B[37] , CARRY[37] , PHI , SUM[37] );
XXOR1 U238 (A[38] , B[38] , CARRY[38] , PHI , SUM[38] );
XXOR1 U239 (A[39] , B[39] , CARRY[39] , PHI , SUM[39] );
XXOR1 U240 (A[40] , B[40] , CARRY[40] , PHI , SUM[40] );
XXOR1 U241 (A[41] , B[41] , CARRY[41] , PHI , SUM[41] );
XXOR1 U242 (A[42] , B[42] , CARRY[42] , PHI , SUM[42] );
XXOR1 U243 (A[43] , B[43] , CARRY[43] , PHI , SUM[43] );
XXOR1 U244 (A[44] , B[44] , CARRY[44] , PHI , SUM[44] );
XXOR1 U245 (A[45] , B[45] , CARRY[45] , PHI , SUM[45] );
XXOR1 U246 (A[46] , B[46] , CARRY[46] , PHI , SUM[46] );
XXOR1 U247 (A[47] , B[47] , CARRY[47] , PHI , SUM[47] );
XXOR1 U248 (A[48] , B[48] , CARRY[48] , PHI , SUM[48] );
XXOR1 U249 (A[49] , B[49] , CARRY[49] , PHI , SUM[49] );
XXOR1 U250 (A[50] , B[50] , CARRY[50] , PHI , SUM[50] );
XXOR1 U251 (A[51] , B[51] , CARRY[51] , PHI , SUM[51] );
XXOR1 U252 (A[52] , B[52] , CARRY[52] , PHI , SUM[52] );
XXOR1 U253 (A[53] , B[53] , CARRY[53] , PHI , SUM[53] );
XXOR1 U254 (A[54] , B[54] , CARRY[54] , PHI , SUM[54] );
XXOR1 U255 (A[55] , B[55] , CARRY[55] , PHI , SUM[55] );
XXOR1 U256 (A[56] , B[56] , CARRY[56] , PHI , SUM[56] );
XXOR1 U257 (A[57] , B[57] , CARRY[57] , PHI , SUM[57] );
XXOR1 U258 (A[58] , B[58] , CARRY[58] , PHI , SUM[58] );
XXOR1 U259 (A[59] , B[59] , CARRY[59] , PHI , SUM[59] );
XXOR1 U260 (A[60] , B[60] , CARRY[60] , PHI , SUM[60] );
XXOR1 U261 (A[61] , B[61] , CARRY[61] , PHI , SUM[61] );
XXOR1 U262 (A[62] , B[62] , CARRY[62] , PHI , SUM[62] );
XXOR1 U263 (A[63] , B[63] , CARRY[63] , PHI , SUM[63] );
BLOCK1A U1 (PBIT , CARRY[0] , CARRY[64] , PHI , COUT );
endmodule
module DBLCTREE_64 ( PIN, GIN, PHI, GOUT, POUT );
input [0:63] PIN;
input [0:64] GIN;
input PHI;
output [0:64] GOUT;
output [0:0] POUT;
wire [0:62] INTPROP_0;
wire [0:64] INTGEN_0;
wire [0:60] INTPROP_1;
wire [0:64] INTGEN_1;
wire [0:56] INTPROP_2;
wire [0:64] INTGEN_2;
wire [0:48] INTPROP_3;
wire [0:64] INTGEN_3;
wire [0:32] INTPROP_4;
wire [0:64] INTGEN_4;
DBLC_0_64 U_0 (.PIN(PIN) , .GIN(GIN) , .PHI(PHI) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) );
DBLC_1_64 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .PHI(PHI) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) );
DBLC_2_64 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .PHI(PHI) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) );
DBLC_3_64 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .PHI(PHI) , .POUT(INTPROP_3) , .GOUT(INTGEN_3) );
DBLC_4_64 U_4 (.PIN(INTPROP_3) , .GIN(INTGEN_3) , .PHI(PHI) , .POUT(INTPROP_4) , .GOUT(INTGEN_4) );
DBLC_5_64 U_5 (.PIN(INTPROP_4) , .GIN(INTGEN_4) , .PHI(PHI) , .POUT(POUT) , .GOUT(GOUT) );
endmodule
module DBLCADDER_64_64 ( OPA, OPB, CIN, PHI, SUM, COUT );
input [0:63] OPA;
input [0:63] OPB;
input CIN;
input PHI;
output [0:63] SUM;
output COUT;
wire [0:63] INTPROP;
wire [0:64] INTGEN;
wire [0:0] PBIT;
wire [0:64] CARRY;
PRESTAGE_64 U1 (OPA , OPB , CIN , PHI , INTPROP , INTGEN );
DBLCTREE_64 U2 (INTPROP , INTGEN , PHI , CARRY , PBIT );
XORSTAGE_64 U3 (OPA[0:63] , OPB[0:63] , PBIT[0] , PHI , CARRY[0:64] , SUM , COUT );
endmodule
module MULTIPLIER_33_32 ( MULTIPLICAND, MULTIPLIER, RST, CLK, PHI, RESULT );
input [0:32] MULTIPLICAND;
input [0:31] MULTIPLIER;
input RST;
input CLK;
input PHI;
output [0:63] RESULT;
wire [0:575] PPBIT;
wire [0:64] INT_CARRY;
wire [0:63] INT_SUM;
wire LOGIC_ZERO;
wire [0:63] ARESULT;
reg [0:63] RESULT;
assign LOGIC_ZERO = 0;
BOOTHCODER_33_32 B (.OPA(MULTIPLICAND[0:32]) , .OPB(MULTIPLIER[0:31]) , .SUMMAND(PPBIT[0:575]) );
WALLACE_33_32 W (.SUMMAND(PPBIT[0:575]) , .RST(RST), .CLK (CLK) , .CARRY(INT_CARRY[1:63]) , .SUM(INT_SUM[0:63]) );
assign INT_CARRY[0] = LOGIC_ZERO;
DBLCADDER_64_64 D (.OPA(INT_SUM[0:63]) , .OPB(INT_CARRY[0:63]) , .CIN (LOGIC_ZERO) , .PHI (PHI) , .SUM(ARESULT[0:63]), .COUT() );
always @(posedge CLK or posedge RST)
if (RST)
RESULT <= #1 64'h0000_0000_0000_0000;
else
RESULT <= ARESULT;
endmodule
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
module or1200_amultp2_32x32 ( X, Y, RST, CLK, P );
input [31:0] X;
input [31:0] Y;
input RST;
input CLK;
output [63:0] P;
wire [0:32] A;
wire [0:31] B;
wire [0:63] Q;
assign A[0] = X[0];
assign A[1] = X[1];
assign A[2] = X[2];
assign A[3] = X[3];
assign A[4] = X[4];
assign A[5] = X[5];
assign A[6] = X[6];
assign A[7] = X[7];
assign A[8] = X[8];
assign A[9] = X[9];
assign A[10] = X[10];
assign A[11] = X[11];
assign A[12] = X[12];
assign A[13] = X[13];
assign A[14] = X[14];
assign A[15] = X[15];
assign A[16] = X[16];
assign A[17] = X[17];
assign A[18] = X[18];
assign A[19] = X[19];
assign A[20] = X[20];
assign A[21] = X[21];
assign A[22] = X[22];
assign A[23] = X[23];
assign A[24] = X[24];
assign A[25] = X[25];
assign A[26] = X[26];
assign A[27] = X[27];
assign A[28] = X[28];
assign A[29] = X[29];
assign A[30] = X[30];
assign A[31] = X[31];
assign A[32] = X[31];
assign B[0] = Y[0];
assign B[1] = Y[1];
assign B[2] = Y[2];
assign B[3] = Y[3];
assign B[4] = Y[4];
assign B[5] = Y[5];
assign B[6] = Y[6];
assign B[7] = Y[7];
assign B[8] = Y[8];
assign B[9] = Y[9];
assign B[10] = Y[10];
assign B[11] = Y[11];
assign B[12] = Y[12];
assign B[13] = Y[13];
assign B[14] = Y[14];
assign B[15] = Y[15];
assign B[16] = Y[16];
assign B[17] = Y[17];
assign B[18] = Y[18];
assign B[19] = Y[19];
assign B[20] = Y[20];
assign B[21] = Y[21];
assign B[22] = Y[22];
assign B[23] = Y[23];
assign B[24] = Y[24];
assign B[25] = Y[25];
assign B[26] = Y[26];
assign B[27] = Y[27];
assign B[28] = Y[28];
assign B[29] = Y[29];
assign B[30] = Y[30];
assign B[31] = Y[31];
assign P[0] = Q[0];
assign P[1] = Q[1];
assign P[2] = Q[2];
assign P[3] = Q[3];
assign P[4] = Q[4];
assign P[5] = Q[5];
assign P[6] = Q[6];
assign P[7] = Q[7];
assign P[8] = Q[8];
assign P[9] = Q[9];
assign P[10] = Q[10];
assign P[11] = Q[11];
assign P[12] = Q[12];
assign P[13] = Q[13];
assign P[14] = Q[14];
assign P[15] = Q[15];
assign P[16] = Q[16];
assign P[17] = Q[17];
assign P[18] = Q[18];
assign P[19] = Q[19];
assign P[20] = Q[20];
assign P[21] = Q[21];
assign P[22] = Q[22];
assign P[23] = Q[23];
assign P[24] = Q[24];
assign P[25] = Q[25];
assign P[26] = Q[26];
assign P[27] = Q[27];
assign P[28] = Q[28];
assign P[29] = Q[29];
assign P[30] = Q[30];
assign P[31] = Q[31];
assign P[32] = Q[32];
assign P[33] = Q[33];
assign P[34] = Q[34];
assign P[35] = Q[35];
assign P[36] = Q[36];
assign P[37] = Q[37];
assign P[38] = Q[38];
assign P[39] = Q[39];
assign P[40] = Q[40];
assign P[41] = Q[41];
assign P[42] = Q[42];
assign P[43] = Q[43];
assign P[44] = Q[44];
assign P[45] = Q[45];
assign P[46] = Q[46];
assign P[47] = Q[47];
assign P[48] = Q[48];
assign P[49] = Q[49];
assign P[50] = Q[50];
assign P[51] = Q[51];
assign P[52] = Q[52];
assign P[53] = Q[53];
assign P[54] = Q[54];
assign P[55] = Q[55];
assign P[56] = Q[56];
assign P[57] = Q[57];
assign P[58] = Q[58];
assign P[59] = Q[59];
assign P[60] = Q[60];
assign P[61] = Q[61];
assign P[62] = Q[62];
assign P[63] = Q[63];
MULTIPLIER_33_32 U1 (.MULTIPLICAND(A) , .MULTIPLIER(B) , .RST(RST), .CLK(CLK) , .PHI(1'b0) , .RESULT(Q) );
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:46:47 09/23/2013
// Design Name:
// Module Name: Comparador
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Comparador(clock, reset, write_value, read_value,
read_value_reg_en, led_success, led_fail);
input clock, reset, read_value_reg_en;
input [3:0] write_value, read_value;
output led_success, led_fail;
//Variable que guarda el valor del valor leido
reg [3:0] read_value_reg;
assign led_success = (write_value == read_value_reg);
assign led_fail = ~led_success;
//Guarda el valor leido en un registro con el enable
always @( posedge clock or posedge reset)
begin
if(reset)
begin
read_value_reg <= 4'b0;
end
else if (read_value_reg_en)
begin
read_value_reg <= read_value;
end
end
endmodule
|
/*
* Copyright 2010, Aleksander Osman, [email protected]. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*! \file ao68000.v
* \brief Main ao68000 IP Core source file.
*/
/***********************************************************************************************************************
* Definitions of microcode operations - parsed by ao68000_tool to generate the defines in the section below
**********************************************************************************************************************/
// OPERATIONS START
`define EA_REG_IDLE 3'd0
`define EA_REG_IR_2_0 3'd1
`define EA_REG_IR_11_9 3'd2
`define EA_REG_MOVEM_REG_2_0 3'd3
`define EA_REG_3b111 3'd4
`define EA_REG_3b100 3'd5
`define EA_MOD_IDLE 4'd0
`define EA_MOD_IR_5_3 4'd1
`define EA_MOD_MOVEM_MOD_5_3 4'd2
`define EA_MOD_IR_8_6 4'd3
`define EA_MOD_PREDEC 4'd4 // predecrement: -(An)
`define EA_MOD_3b111 4'd5 // extended mod
`define EA_MOD_DN_PREDEC 4'd6 // MOD.DN_PREDEC: Dn 3'b000 (ir[3] == 1'b0), -(An) 3'b100 (ir[3] == 1'b1)
`define EA_MOD_DN_AN_EXG 4'd7 // MOD.DN_AN_EXG: Dn 3'b000 (ir[7:3] == 5'b01000 or 5'b10001), An 3'b001 (ir[7:3] == 5'b01001)
`define EA_MOD_POSTINC 4'd8 // MOD.POSTINC: postincrement (An)+ 3'b011
`define EA_MOD_AN 4'd9 // MOD.AN: An 3'b001, saved result is sign-extended
`define EA_MOD_DN 4'd10 // MOD.DN: Dn 3'b000
`define EA_MOD_INDIRECTOFFSET 4'd11 // MOD.INDIRECTOFFSET: (d16, An) 3'b101
`define EA_TYPE_IDLE 4'd0
`define EA_TYPE_ALL 4'd1 // TYPE.ALL: all
`define EA_TYPE_CONTROL_POSTINC 4'd2 // TYPE.CONTROL_POSTINC: control or postincrement
`define EA_TYPE_CONTROLALTER_PREDEC 4'd3 // TYPE.CONTROLALTER_PREDEC: control alter or predecrement
`define EA_TYPE_CONTROL 4'd4 // TYPE.CONTROL: control
`define EA_TYPE_DATAALTER 4'd5 // TYPE.DATAALTER: data alter
`define EA_TYPE_DN_AN 4'd6 // TYPE.DN_AN: Dn, An
`define EA_TYPE_MEMORYALTER 4'd7 // TYPE.MEMORYALTER: memory alter
`define EA_TYPE_DATA 4'd8 // TYPE.DATA: data
`define OP1_IDLE 4'd0
`define OP1_FROM_OP2 4'd1 // move from operand2
`define OP1_FROM_ADDRESS 4'd2 // move from address
`define OP1_FROM_DATA 4'd3 // move from data, sign extend
`define OP1_FROM_IMMEDIATE 4'd4 // move immediate, sign extend
`define OP1_FROM_RESULT 4'd5 // move from result
`define OP1_MOVEQ 4'd6 // move moveq: { 24{ir[7]}, ir[7:0] }
`define OP1_FROM_PC 4'd7 // move from PC
`define OP1_LOAD_ZEROS 4'd8 // load zeros: 32'b0
`define OP1_LOAD_ONES 4'd9 // load ones: 32'hFFFFFFFF
`define OP1_FROM_SR 4'd10 // move from SR
`define OP1_FROM_USP 4'd11 // move from USP
`define OP1_FROM_AN 4'd12 // move from An, 32 bits
`define OP1_FROM_DN 4'd13 // move from Dn, sign extend
`define OP1_FROM_IR 4'd14 // move from ir[15:0]
`define OP1_FROM_FAULT_ADDRESS 4'd15 // move from fault_address
`define OP2_IDLE 3'd0
`define OP2_FROM_OP1 3'd1 // move from operand1
`define OP2_LOAD_1 3'd2 // load: 32'b1
`define OP2_LOAD_COUNT 3'd3 // load count
`define OP2_ADDQ_SUBQ 3'd4 // load addq_subq
`define OP2_MOVE_OFFSET 3'd5 // move offset
`define OP2_MOVE_ADDRESS_BUS_INFO 3'd6 // move address_bus_info
`define OP2_DECR_BY_1 3'd7 // decrement by 1
`define ADDRESS_IDLE 4'd0
`define ADDRESS_INCR_BY_SIZE 4'd1 // increment by size
`define ADDRESS_DECR_BY_SIZE 4'd2 // decrement by size
`define ADDRESS_INCR_BY_2 4'd3 // increment by 2
`define ADDRESS_FROM_AN_OUTPUT 4'd4 // move from An output
`define ADDRESS_FROM_BASE_INDEX_OFFSET 4'd5 // move from base+index+offset
`define ADDRESS_FROM_IMM_16 4'd6 // move from {16{ir1[15]}, ir1[15:0]}
`define ADDRESS_FROM_IMM_32 4'd7 // move from {ir1[15:0], ir2[15:0]}
`define ADDRESS_FROM_PC_INDEX_OFFSET 4'd8 // move from pc+index+offset
`define ADDRESS_FROM_TRAP 4'd9 // move trap {22'b0, trap[7:0], 2'b0}
`define SIZE_IDLE 4'd0
`define SIZE_BYTE 4'd1 // load byte: 3'b001
`define SIZE_WORD 4'd2 // load word: 3'b010
`define SIZE_LONG 4'd3 // load long: 3'b100
`define SIZE_1 4'd4 // SIZE.1: word ( ir[7:6] == 2'b00 ), long ( ir[7:6] == 2'b01 )
`define SIZE_1_PLUS 4'd5 // SIZE.1+: word ( ir[7:6] == 2'b10 ), long ( ir[7:6] == 2'b11 )
`define SIZE_2 4'd6 // SIZE.2: word ( ir[6] == 1'b0 ), long ( ir[6] == 1'b1 )
`define SIZE_3 4'd7 // SIZE.3: byte ( ir[7:6] == 2'b00 ), word ( ir[7:6] == 2'b01 ), long ( ir[7:6] == 2'b10 )
`define SIZE_4 4'd8 // SIZE.4: byte ( ir[13:12] == 2'b01 ), word( ir[13:12] == 2'b11 ), long ( ir[13:12] == 2'b10 )
`define SIZE_5 4'd9 // SIZE.5: word ( ir[8] == 1'b0 ), long ( ir[8] == 1'b1 )
`define SIZE_6 4'd10 // SIZE.6: byte ( ir[5:3] != 3'b000 ), long ( ir[5:3] == 3'b000 )
`define MOVEM_MODREG_IDLE 3'd0
`define MOVEM_MODREG_LOAD_0 3'd1 // load 6'b0
`define MOVEM_MODREG_LOAD_6b001111 3'd2 // load 6'b001111
`define MOVEM_MODREG_INCR_BY_1 3'd3 // increment by 1
`define MOVEM_MODREG_DECR_BY_1 3'd4 // decrement by 1
`define MOVEM_LOOP_IDLE 2'd0
`define MOVEM_LOOP_LOAD_0 2'd1 // load 4'b0
`define MOVEM_LOOP_INCR_BY_1 2'd2 // increment by 1
`define MOVEM_REG_IDLE 2'd0
`define MOVEM_REG_FROM_OP1 2'd1 // load from operand1[15:0]
`define MOVEM_REG_SHIFT_RIGHT 2'd2 // shift right
`define IR_IDLE 2'd0
`define IR_LOAD_WHEN_PREFETCH_VALID 2'd1 // load from prefetch_ir[79:64]
`define PC_IDLE 3'd0
`define PC_FROM_RESULT 3'd1 // move from result
`define PC_INCR_BY_2 3'd2 // increment by 2
`define PC_INCR_BY_4 3'd3 // increment by 4
`define PC_INCR_BY_SIZE 3'd4 // increment by size: 2 (size == 3'b001 || size == 3'b010), 4 (size == 3'b100)
`define PC_FROM_PREFETCH_IR 3'd5 // move from prefetch_ir
`define PC_INCR_BY_2_IN_MAIN_LOOP 3'd6 // increment by 2, in main loop, when valid prefetch and valid instruction
`define TRAP_IDLE 4'd0
`define TRAP_ILLEGAL_INSTR 4'd1 // move illegal_instr: 8'd4
`define TRAP_DIV_BY_ZERO 4'd2 // move divide_by_zero: 8'd5
`define TRAP_CHK 4'd3 // move chk: 8'd6
`define TRAP_TRAPV 4'd4 // move trapv: 8'd7
`define TRAP_PRIVIL_VIOLAT 4'd5 // move priv_viol: 8'd8
`define TRAP_TRACE 4'd6 // move trace: 8'd9
`define TRAP_TRAP 4'd7 // move trap: { 3'b0, 1'b1, ir[3:0] }
`define TRAP_FROM_DECODER 4'd8 // move from decoder_trap
`define TRAP_FROM_INTERRUPT 4'd9 // move from interrupt_trap
`define OFFSET_IDLE 2'd0
`define OFFSET_IMM_8 2'd1 // { 24{ir1[7]}, ir1[7:0] }
`define OFFSET_IMM_16 2'd2 // { 16{ir1[15]}, ir1[15:0] }
`define INDEX_IDLE 2'd0
`define INDEX_0 2'd1 // 32'b0
`define INDEX_LOAD_EXTENDED 2'd2 // load from extended instruction word
`define STOP_FLAG_IDLE 2'd0
`define STOP_FLAG_SET 2'd1 // set, continue when: trace,interrupt or reset
`define STOP_FLAG_CLEAR 2'd2 // clear
`define TRACE_FLAG_IDLE 2'd0
`define TRACE_FLAG_COPY_WHEN_NO_STOP 2'd1 // remember trace bit, move from sr[15]
`define GROUP_0_FLAG_IDLE 2'd0
`define GROUP_0_FLAG_SET 2'd1 // set, processing group zero exception
`define GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH 2'd2 // clear
`define INSTRUCTION_FLAG_IDLE 2'd0
`define INSTRUCTION_FLAG_SET 2'd1 // set, processing instruction
`define INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP 2'd2 // clear, in main loop, when valid prefetch and valid instruction
`define READ_MODIFY_WRITE_FLAG_IDLE 2'd0
`define READ_MODIFY_WRITE_FLAG_SET 2'd1 // set, execute a RMW cycle
`define READ_MODIFY_WRITE_FLAG_CLEAR 2'd2 // clear
`define DO_RESET_FLAG_IDLE 2'd0
`define DO_RESET_FLAG_SET 2'd1 // set, signal reset
`define DO_RESET_FLAG_CLEAR 2'd2 // clear
`define DO_INTERRUPT_FLAG_IDLE 2'd0
`define DO_INTERRUPT_FLAG_SET_IF_ACTIVE 2'd1 // set if interrupt active
`define DO_INTERRUPT_FLAG_CLEAR 2'd2 // clear
`define DO_READ_FLAG_IDLE 2'd0
`define DO_READ_FLAG_SET 2'd1 // set, perform read operation
`define DO_READ_FLAG_CLEAR 2'd2 // clear
`define DO_WRITE_FLAG_IDLE 2'd0
`define DO_WRITE_FLAG_SET 2'd1 // set, perform write operation
`define DO_WRITE_FLAG_CLEAR 2'd2 // clear
`define DO_BLOCKED_FLAG_IDLE 2'd0
`define DO_BLOCKED_FLAG_SET 2'd1 // set, block processor
`define DATA_WRITE_IDLE 2'd0
`define DATA_WRITE_FROM_RESULT 2'd1 // load data write register from result register
`define AN_ADDRESS_IDLE 2'd0 // load from ea_reg, user or supervisor
`define AN_ADDRESS_FROM_EXTENDED 2'd1 // load from extended instruction word: ir1[14:12], user or supervisor
`define AN_ADDRESS_USP 2'd2 // load USP address
`define AN_ADDRESS_SSP 2'd3 // load SSP address
`define AN_WRITE_ENABLE_IDLE 1'd0
`define AN_WRITE_ENABLE_SET 1'd1 // set write enable on An register
`define AN_INPUT_IDLE 2'd0 // load from result
`define AN_INPUT_FROM_ADDRESS 2'd1 // load from address
`define AN_INPUT_FROM_PREFETCH_IR 2'd2 // load from prefetch_ir, for reset, for SSP
`define DN_ADDRESS_IDLE 1'd0 // load from ea_reg
`define DN_ADDRESS_FROM_EXTENDED 1'd1 // load from extended instruction word: ir1[14:12]
`define DN_WRITE_ENABLE_IDLE 1'd0
`define DN_WRITE_ENABLE_SET 1'd1 // set write enable on Dn register
`define ALU_IDLE 5'd0
`define ALU_SR_SET_INTERRUPT 5'd1
`define ALU_SR_SET_TRAP 5'd2
`define ALU_MOVEP_M2R_1 5'd3
`define ALU_MOVEP_M2R_2 5'd4
`define ALU_MOVEP_M2R_3 5'd5
`define ALU_MOVEP_M2R_4 5'd6
`define ALU_MOVEP_R2M_1 5'd7
`define ALU_MOVEP_R2M_2 5'd8
`define ALU_MOVEP_R2M_3 5'd9
`define ALU_MOVEP_R2M_4 5'd10
`define ALU_SIGN_EXTEND 5'd11
`define ALU_ARITHMETIC_LOGIC 5'd12
`define ALU_ABCD_SBCD_ADDX_SUBX_prepare 5'd13
`define ALU_ABCD_SBCD_ADDX_SUBX 5'd14
`define ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare 5'd15
`define ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR 5'd16
`define ALU_MOVE 5'd17
`define ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ 5'd18
`define ALU_CHK 5'd19
`define ALU_MULS_MULU_DIVS_DIVU 5'd20
`define ALU_BCHG_BCLR_BSET_BTST 5'd21
`define ALU_TAS 5'd22
`define ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT 5'd23
`define ALU_SIMPLE_LONG_ADD 5'd24
`define ALU_SIMPLE_LONG_SUB 5'd25
`define ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR 5'd26
`define ALU_SIMPLE_MOVE 5'd27
`define ALU_LINK_MOVE 5'd28
`define BRANCH_IDLE 4'd0
`define BRANCH_movem_loop 4'd1 // BRANCH(movem_loop == 4'b1000)
`define BRANCH_movem_reg 4'd2 // BRANCH(movem_reg[0] == 0)
`define BRANCH_operand2 4'd3 // BRANCH(operand2[5:0] == 6'b0)
`define BRANCH_alu_signal 4'd4 // BRANCH(alu_signal == 1'b0)
`define BRANCH_alu_mult_div_ready 4'd5 // BRANCH(alu_mult_div_ready == 1'b1)
`define BRANCH_condition_0 4'd6 // BRANCH(condition == 1'b0)
`define BRANCH_condition_1 4'd7 // BRANCH(condition == 1'b1)
`define BRANCH_result 4'd8 // BRANCH(result[15:0] == 16'hFFFF)
`define BRANCH_V 4'd9 // BRANCH(V == 1'b0)
`define BRANCH_movep_16 4'd10 // BRANCH(ir[6] == 0)
`define BRANCH_stop_flag_wait_ir_decode 4'd11 // BRANCH(stop_flag == 1'b1) if no branch: wait for prefetch ir valid and decode instruction
`define BRANCH_ir 4'd12 // BRANCH(ir[7:0] != 8'b0)
`define BRANCH_trace_flag_and_interrupt 4'd13 // BRANCH(trace_flag == 1'b0 && interrupt_mask != 3'b000) if no branch: jump to main loop
`define BRANCH_group_0_flag 4'd14 // BRANCH(group_0_flag == 0)
`define BRANCH_procedure 4'd15 // call procedure, return from procedure
`define PROCEDURE_IDLE 4'd0
`define PROCEDURE_call_load_ea 4'd1 // load ea
`define PROCEDURE_call_perform_ea_read 4'd2 // perform_ea_read
`define PROCEDURE_call_perform_ea_write 4'd3 // perform_ea_write
`define PROCEDURE_call_save_ea 4'd4 // save ea
`define PROCEDURE_return 4'd5 // return from procedure
`define PROCEDURE_wait_finished 4'd6 // wait for finished signal from bus controler
`define PROCEDURE_wait_prefetch_valid 4'd7 // wait for prefetch ir valid, 64 bits
`define PROCEDURE_wait_prefetch_valid_32 4'd8 // wait for prefetch ir valid, 32 bits
`define PROCEDURE_jump_to_main_loop 4'd9 // jump to main loop
`define PROCEDURE_push_micropc 4'd10 // save current micro_pc
`define PROCEDURE_call_trap 4'd11 // call trap service procedure
`define PROCEDURE_pop_micropc 4'd12 // pop most recent micro_pc and forget
`define PROCEDURE_interrupt_mask 4'd13 // if interrupt active continue, else jump to main loop
`define PROCEDURE_call_read 4'd14 // load_ea + perform_ea_read
`define PROCEDURE_call_write 4'd15 // perform_ea_write + save_ea + return
// OPERATIONS END
/***********************************************************************************************************************
* Automatically generated by ao68000_tool microcode word bit assignments and addresses
**********************************************************************************************************************/
// MICROCODE - DO NOT EDIT BELOW
`define MICRO_DATA_ea_reg micro_data[2:0]
`define MICRO_DATA_ea_mod micro_data[6:3]
`define MICRO_DATA_ea_type micro_data[10:7]
`define MICRO_DATA_op1 micro_data[14:11]
`define MICRO_DATA_op2 micro_data[17:15]
`define MICRO_DATA_address micro_data[21:18]
`define MICRO_DATA_size micro_data[25:22]
`define MICRO_DATA_movem_modreg micro_data[28:26]
`define MICRO_DATA_movem_loop micro_data[30:29]
`define MICRO_DATA_movem_reg micro_data[32:31]
`define MICRO_DATA_ir micro_data[34:33]
`define MICRO_DATA_pc micro_data[37:35]
`define MICRO_DATA_trap micro_data[41:38]
`define MICRO_DATA_offset micro_data[43:42]
`define MICRO_DATA_index micro_data[45:44]
`define MICRO_DATA_stop_flag micro_data[47:46]
`define MICRO_DATA_trace_flag micro_data[49:48]
`define MICRO_DATA_group_0_flag micro_data[51:50]
`define MICRO_DATA_instruction_flag micro_data[53:52]
`define MICRO_DATA_read_modify_write_flag micro_data[55:54]
`define MICRO_DATA_do_reset_flag micro_data[57:56]
`define MICRO_DATA_do_interrupt_flag micro_data[59:58]
`define MICRO_DATA_do_read_flag micro_data[61:60]
`define MICRO_DATA_do_write_flag micro_data[63:62]
`define MICRO_DATA_do_blocked_flag micro_data[65:64]
`define MICRO_DATA_data_write micro_data[67:66]
`define MICRO_DATA_an_address micro_data[69:68]
`define MICRO_DATA_an_write_enable micro_data[70:70]
`define MICRO_DATA_an_input micro_data[72:71]
`define MICRO_DATA_dn_address micro_data[73:73]
`define MICRO_DATA_dn_write_enable micro_data[74:74]
`define MICRO_DATA_alu micro_data[79:75]
`define MICRO_DATA_branch micro_data[83:80]
`define MICRO_DATA_procedure micro_data[87:84]
`define MICROPC_MOVE 9'd232
`define MICROPC_MOVE_USP_to_An 9'd401
`define MICROPC_TAS 9'd333
`define MICROPC_BSR 9'd431
`define MICROPC_ADDRESS_BUS_TRAP 9'd3
`define MICROPC_MOVEP_register_to_memory 9'd106
`define MICROPC_NEGX_CLR_NEG_NOT_NBCD 9'd338
`define MICROPC_RTS 9'd472
`define MICROPC_MAIN_LOOP 9'd53
`define MICROPC_ADDA_SUBA 9'd269
`define MICROPC_MOVE_TO_CCR_MOVE_TO_SR 9'd392
`define MICROPC_MOVE_FROM_SR 9'd389
`define MICROPC_LOAD_EA_d8_PC_Xn 9'd79
`define MICROPC_TRAP_ENTRY 9'd35
`define MICROPC_PERFORM_EA_READ_memory 9'd89
`define MICROPC_RESET 9'd486
`define MICROPC_PERFORM_EA_WRITE_Dn 9'd91
`define MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_memory 9'd226
`define MICROPC_MOVEA 9'd240
`define MICROPC_TST 9'd345
`define MICROPC_BTST_register 9'd327
`define MICROPC_LOAD_EA_d8_An_Xn 9'd68
`define MICROPC_MULS_MULU_DIVS_DIVU 9'd291
`define MICROPC_MOVEQ 9'd308
`define MICROPC_CMPA 9'd276
`define MICROPC_EOR 9'd246
`define MICROPC_LOAD_EA_xxx_W 9'd72
`define MICROPC_DBcc 9'd375
`define MICROPC_CMPI 9'd184
`define MICROPC_LOAD_EA_xxx_L 9'd74
`define MICROPC_CMPM 9'd206
`define MICROPC_MOVE_USP_to_USP 9'd396
`define MICROPC_ADDQ_SUBQ_not_An 9'd349
`define MICROPC_ULNK 9'd420
`define MICROPC_EXG 9'd198
`define MICROPC_ADD_to_mem_SUB_to_mem_AND_to_mem_OR_to_mem 9'd251
`define MICROPC_Bcc_BRA 9'd363
`define MICROPC_PERFORM_EA_READ_An 9'd86
`define MICROPC_LOAD_EA_d16_PC 9'd76
`define MICROPC_NOP 9'd480
`define MICROPC_MOVEM_register_to_memory_predecrement 9'd131
`define MICROPC_RTE_RTR 9'd460
`define MICROPC_TRAP 9'd481
`define MICROPC_ADDQ_SUBQ_An 9'd352
`define MICROPC_MOVEM_register_to_memory_control 9'd147
`define MICROPC_BTST_immediate 9'd316
`define MICROPC_MOVEP_memory_to_register 9'd98
`define MICROPC_PERFORM_EA_WRITE_An 9'd92
`define MICROPC_CHK 9'd282
`define MICROPC_Scc 9'd356
`define MICROPC_JMP 9'd443
`define MICROPC_PEA 9'd168
`define MICROPC_SAVE_EA_minus_An 9'd97
`define MICROPC_ANDI_EORI_ORI_ADDI_SUBI 9'd174
`define MICROPC_BCHG_BCLR_BSET_immediate 9'd311
`define MICROPC_LOAD_EA_An 9'd62
`define MICROPC_PERFORM_EA_READ_imm 9'd87
`define MICROPC_ADD_to_Dn_SUB_to_Dn_AND_to_Dn_OR_to_Dn 9'd256
`define MICROPC_LEA 9'd162
`define MICROPC_TRAPV 9'd483
`define MICROPC_LINK 9'd404
`define MICROPC_ABCD_SBCD_ADDX_SUBX 9'd189
`define MICROPC_BCHG_BCLR_BSET_register 9'd322
`define MICROPC_PERFORM_EA_READ_Dn 9'd85
`define MICROPC_LOAD_EA_illegal_command 9'd83
`define MICROPC_ORI_to_CCR_ORI_to_SR_ANDI_to_CCR_ANDI_to_SR_EORI_to_CCR_EORI_to_SR 9'd178
`define MICROPC_CMP 9'd263
`define MICROPC_SWAP_EXT 9'd341
`define MICROPC_STOP 9'd489
`define MICROPC_PERFORM_EA_WRITE_memory 9'd93
`define MICROPC_JSR 9'd451
`define MICROPC_LOAD_EA_minus_An 9'd63
`define MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_immediate_register 9'd213
`define MICROPC_SAVE_EA_An_plus 9'd95
`define MICROPC_LOAD_EA_d16_An 9'd65
`define MICROPC_LOAD_EA_An_plus 9'd62
`define MICROPC_MOVEM_memory_to_register 9'd116
// MICROCODE - DO NOT EDIT ABOVE
/***********************************************************************************************************************
* ao68000 top level module
**********************************************************************************************************************/
/*! \brief ao68000 top level module.
*
* This module contains only instantiations of sub-modules and wire declarations.
*/
module ao68000 (
//****************** WISHBONE
input CLK_I, //% \copydoc CLK_I
input reset_n, //% \copydoc reset_n
output CYC_O, //% \copydoc CYC_O
output [31:2] ADR_O, //% \copydoc ADR_O
output [31:0] DAT_O, //% \copydoc DAT_O
input [31:0] DAT_I, //% \copydoc DAT_I
output [3:0] SEL_O, //% \copydoc SEL_O
output STB_O, //% \copydoc STB_O
output WE_O, //% \copydoc WE_O
input ACK_I, //% \copydoc ACK_I
input ERR_I, //% \copydoc ERR_I
input RTY_I, //% \copydoc RTY_I
// TAG_TYPE: TGC_O
output SGL_O, //% \copydoc SGL_O
output BLK_O, //% \copydoc BLK_O
output RMW_O, //% \copydoc RMW_O
// TAG_TYPE: TGA_O
output [2:0] CTI_O, //% \copydoc CTI_O
output [1:0] BTE_O, //% \copydoc BTE_O
// TAG_TYPE: TGC_O
output [2:0] fc_o, //% \copydoc fc_o
//****************** OTHER
/* interrupt acknowlege:
* ACK_I: interrupt vector on DAT_I[7:0]
* ERR_I: spurious interrupt
* RTY_I: autovector
*/
input [2:0] ipl_i, //% \copydoc ipl_i
output reset_o, //% \copydoc reset_o
output blocked_o //% \copydoc blocked_o
);
wire [15:0] sr;
wire [2:0] size;
wire [31:0] address;
wire address_type;
wire read_modify_write_flag;
wire [31:0] data_read;
wire [31:0] data_write;
wire [31:0] pc;
wire prefetch_ir_valid;
wire [79:0] prefetch_ir;
wire do_reset;
wire do_read;
wire do_write;
wire do_interrupt;
wire do_blocked;
wire jmp_address_trap;
wire jmp_bus_trap;
wire finished;
wire [7:0] interrupt_trap;
wire [2:0] interrupt_mask;
wire rw_state;
wire [2:0] fc_state;
wire [7:0] decoder_trap;
wire [31:0] usp;
wire [31:0] Dn_output;
wire [31:0] An_output;
wire [31:0] result;
wire [3:0] An_address;
wire [31:0] An_input;
wire [2:0] Dn_address;
wire [15:0] ir;
wire [8:0] decoder_micropc;
wire alu_signal;
wire alu_mult_div_ready;
wire [8:0] load_ea;
wire [8:0] perform_ea_read;
wire [8:0] perform_ea_write;
wire [8:0] save_ea;
wire trace_flag;
wire group_0_flag;
wire stop_flag;
wire [8:0] micro_pc;
wire [31:0] operand1;
wire [31:0] operand2;
wire [4:0] movem_loop;
wire [15:0] movem_reg;
wire condition;
wire [87:0] micro_data;
wire [31:0] fault_address_state;
wire [1:0] pc_change;
wire prefetch_ir_valid_32;
wire [3:0] ea_type;
wire [2:0] ea_mod;
wire [2:0] ea_reg;
wire [17:0] decoder_alu;
wire [17:0] decoder_alu_reg;
bus_control bus_control_m(
.CLK_I (CLK_I),
.reset_n (reset_n),
.CYC_O (CYC_O),
.ADR_O (ADR_O),
.DAT_O (DAT_O),
.DAT_I (DAT_I),
.SEL_O (SEL_O),
.STB_O (STB_O),
.WE_O (WE_O),
.ACK_I (ACK_I),
.ERR_I (ERR_I),
.RTY_I (RTY_I),
.SGL_O (SGL_O),
.BLK_O (BLK_O),
.RMW_O (RMW_O),
.CTI_O (CTI_O),
.BTE_O (BTE_O),
.fc_o (fc_o),
.ipl_i (ipl_i),
.reset_o (reset_o),
.blocked_o (blocked_o),
.supervisor_i (sr[13]),
.ipm_i (sr[10:8]),
.size_i (size),
.address_i (address),
.address_type_i (address_type),
.read_modify_write_i (read_modify_write_flag),
.data_write_i (data_write),
.data_read_o (data_read),
.pc_i (pc),
.pc_change_i (pc_change),
.prefetch_ir_o (prefetch_ir),
.prefetch_ir_valid_32_o (prefetch_ir_valid_32),
.prefetch_ir_valid_o (prefetch_ir_valid),
.prefetch_ir_valid_80_o (),
.do_reset_i (do_reset),
.do_blocked_i (do_blocked),
.do_read_i (do_read),
.do_write_i (do_write),
.do_interrupt_i (do_interrupt),
.jmp_address_trap_o (jmp_address_trap),
.jmp_bus_trap_o (jmp_bus_trap),
.finished_o (finished),
.interrupt_trap_o (interrupt_trap),
.interrupt_mask_o (interrupt_mask),
.rw_state_o (rw_state),
.fc_state_o (fc_state),
.fault_address_state_o (fault_address_state)
);
registers registers_m(
.clock (CLK_I),
.reset_n (reset_n),
.data_read (data_read),
.prefetch_ir (prefetch_ir),
.prefetch_ir_valid (prefetch_ir_valid),
.result (result),
.sr (sr),
.rw_state (rw_state),
.fc_state (fc_state),
.fault_address_state (fault_address_state),
.interrupt_trap (interrupt_trap),
.interrupt_mask (interrupt_mask),
.decoder_trap (decoder_trap),
.usp (usp),
.Dn_output (Dn_output),
.An_output (An_output),
.pc_change (pc_change),
.ea_reg (ea_reg),
.ea_reg_control (`MICRO_DATA_ea_reg),
.ea_mod (ea_mod),
.ea_mod_control (`MICRO_DATA_ea_mod),
.ea_type (ea_type),
.ea_type_control (`MICRO_DATA_ea_type),
.operand1 (operand1),
.operand1_control (`MICRO_DATA_op1),
.operand2 (operand2),
.operand2_control (`MICRO_DATA_op2),
.address (address),
.address_type (address_type),
.address_control (`MICRO_DATA_address),
.size (size),
.size_control (`MICRO_DATA_size),
.movem_modreg (),
.movem_modreg_control (`MICRO_DATA_movem_modreg),
.movem_loop (movem_loop),
.movem_loop_control (`MICRO_DATA_movem_loop),
.movem_reg (movem_reg),
.movem_reg_control (`MICRO_DATA_movem_reg),
.ir (ir),
.ir_control (`MICRO_DATA_ir),
.pc (pc),
.pc_control (`MICRO_DATA_pc),
.trap (),
.trap_control (`MICRO_DATA_trap),
.offset (),
.offset_control (`MICRO_DATA_offset),
.index (),
.index_control (`MICRO_DATA_index),
.stop_flag (stop_flag),
.stop_flag_control (`MICRO_DATA_stop_flag),
.trace_flag (trace_flag),
.trace_flag_control (`MICRO_DATA_trace_flag),
.group_0_flag (group_0_flag),
.group_0_flag_control (`MICRO_DATA_group_0_flag),
.instruction_flag (),
.instruction_flag_control (`MICRO_DATA_instruction_flag),
.read_modify_write_flag (read_modify_write_flag),
.read_modify_write_flag_control (`MICRO_DATA_read_modify_write_flag),
.do_reset_flag (do_reset),
.do_reset_flag_control (`MICRO_DATA_do_reset_flag),
.do_interrupt_flag (do_interrupt),
.do_interrupt_flag_control (`MICRO_DATA_do_interrupt_flag),
.do_read_flag (do_read),
.do_read_flag_control (`MICRO_DATA_do_read_flag),
.do_write_flag (do_write),
.do_write_flag_control (`MICRO_DATA_do_write_flag),
.do_blocked_flag (do_blocked),
.do_blocked_flag_control (`MICRO_DATA_do_blocked_flag),
.data_write (data_write),
.data_write_control (`MICRO_DATA_data_write),
.An_address (An_address),
.An_address_control (`MICRO_DATA_an_address),
.An_input (An_input),
.An_input_control (`MICRO_DATA_an_input),
.Dn_address (Dn_address),
.Dn_address_control (`MICRO_DATA_dn_address),
.decoder_alu (decoder_alu),
.decoder_alu_reg (decoder_alu_reg)
);
memory_registers memory_registers_m(
.clock (CLK_I),
.reset_n (reset_n),
.An_address (An_address),
.An_input (An_input),
.An_write_enable (`MICRO_DATA_an_write_enable),
.An_output (An_output),
.usp (usp),
.Dn_address (Dn_address),
.Dn_input (result),
.Dn_write_enable (`MICRO_DATA_dn_write_enable),
.Dn_size (size),
.Dn_output (Dn_output),
.micro_pc (micro_pc),
.micro_data (micro_data)
);
decoder decoder_m(
.clock (CLK_I),
.reset_n (reset_n),
.supervisor (sr[13]),
.ir (prefetch_ir[79:64]),
.decoder_trap (decoder_trap),
.decoder_micropc (decoder_micropc),
.decoder_alu (decoder_alu),
.load_ea (load_ea),
.perform_ea_read (perform_ea_read),
.perform_ea_write (perform_ea_write),
.save_ea (save_ea),
.ea_type (ea_type),
.ea_mod (ea_mod),
.ea_reg (ea_reg)
);
condition condition_m(
.cond (ir[11:8]),
.ccr (sr[7:0]),
.condition (condition)
);
alu alu_m(
.clock (CLK_I),
.reset_n (reset_n),
.address (address),
.ir (ir),
.size (size),
.operand1 (operand1),
.operand2 (operand2),
.interrupt_mask (interrupt_mask),
.alu_control (`MICRO_DATA_alu),
.sr (sr),
.result (result),
.alu_signal (alu_signal),
.alu_mult_div_ready (alu_mult_div_ready),
.decoder_alu_reg (decoder_alu_reg)
);
microcode_branch microcode_branch_m(
.clock (CLK_I),
.reset_n (reset_n),
.movem_loop (movem_loop),
.movem_reg (movem_reg),
.operand2 (operand2),
.alu_signal (alu_signal),
.alu_mult_div_ready (alu_mult_div_ready),
.condition (condition),
.result (result),
.overflow (sr[1]),
.stop_flag (stop_flag),
.ir (ir),
.decoder_trap (decoder_trap),
.trace_flag (trace_flag),
.group_0_flag (group_0_flag),
.interrupt_mask (interrupt_mask),
.load_ea (load_ea),
.perform_ea_read (perform_ea_read),
.perform_ea_write (perform_ea_write),
.save_ea (save_ea),
.decoder_micropc (decoder_micropc),
.prefetch_ir_valid_32 (prefetch_ir_valid_32),
.prefetch_ir_valid (prefetch_ir_valid),
.jmp_address_trap (jmp_address_trap),
.jmp_bus_trap (jmp_bus_trap),
.finished (finished),
.branch_control (`MICRO_DATA_branch),
.branch_offset (`MICRO_DATA_procedure),
.micro_pc (micro_pc)
);
endmodule
/***********************************************************************************************************************
* Bus control
**********************************************************************************************************************/
/*! \brief Initiate WISHBONE MASTER bus cycles.
*
* The bus_control module is the only module that has contact with signals from outside of the IP core.
* It is responsible for initiating WISHBONE MASTER bus cycles. The cycles can be divided into:
* - memory read cycles (supervisor data, supervisor program, user data, user program)
* - memory write cycles (supervisor data, user data),
* - interrupt acknowledge.
*
* Every cycle is supplemented with the following tags:
* - standard WISHBONE cycle tags: SGL_O, BLK_O, RMW_O,
* - register feedback WISHBONE address tags: CTI_O and BTE_O,
* - ao68000 specific cycle tag: fc_o which is equivalent to MC68000 function codes.
*
* The bus_control module is also responsible for registering interrupt inputs and initiating the interrupt acknowledge
* cycle in response to a microcode request. Microcode requests a interrupt acknowledge at the end of instruction
* processing, when the interrupt privilege level is higher than the current interrupt privilege mask, as specified
* in the MC68000 User's Manual.
*
* Finally, bus_control controls also two ao68000 specific core outputs:
* - blocked output, high when that the processor is blocked after encountering a double bus error. The only way
* to leave this block state is by reseting the ao68000 by the asynchronous reset input signal.
* - reset output, high when processing the RESET instruction. Can be used to reset external devices.
*/
module bus_control(
//******************************************* external
//****************** WISHBONE
input CLK_I,
input reset_n,
output reg CYC_O,
output reg [31:2] ADR_O,
output reg [31:0] DAT_O,
input [31:0] DAT_I,
output reg [3:0] SEL_O,
output reg STB_O,
output reg WE_O,
input ACK_I,
input ERR_I,
input RTY_I,
// TAG_TYPE: TGC_O
output reg SGL_O,
output reg BLK_O,
output reg RMW_O,
// TAG_TYPE: TGA_O
output reg [2:0] CTI_O,
output [1:0] BTE_O,
// TAG_TYPE: TGC_O
output reg [2:0] fc_o,
//****************** OTHER
input [2:0] ipl_i,
output reg reset_o = 1'b0,
output reg blocked_o = 1'b0,
//******************************************* internal
input supervisor_i,
input [2:0] ipm_i,
input [2:0] size_i,
input [31:0] address_i,
input address_type_i,
input read_modify_write_i,
input [31:0] data_write_i,
output reg [31:0] data_read_o,
input [31:0] pc_i,
input [1:0] pc_change_i,
output reg [79:0] prefetch_ir_o,
output reg prefetch_ir_valid_32_o = 1'b0,
output reg prefetch_ir_valid_o = 1'b0,
output reg prefetch_ir_valid_80_o = 1'b0,
input do_reset_i,
input do_blocked_i,
input do_read_i,
input do_write_i,
input do_interrupt_i,
output reg jmp_address_trap_o = 1'b0,
output reg jmp_bus_trap_o = 1'b0,
// read/write/interrupt
output reg finished_o,
output reg [7:0] interrupt_trap_o = 8'b0,
output reg [2:0] interrupt_mask_o = 3'b0,
/* mask==0 && trap==0 nothing
* mask!=0 interrupt with spurious interrupt
*/
// write = 0/read = 1
output reg rw_state_o,
output reg [2:0] fc_state_o,
output reg [31:0] fault_address_state_o
);
assign BTE_O = 2'b00;
wire [31:0] pc_i_plus_6;
assign pc_i_plus_6 = pc_i + 32'd6;
wire [31:0] pc_i_plus_4;
assign pc_i_plus_4 = pc_i + 32'd4;
wire [31:0] address_i_plus_4;
assign address_i_plus_4 = address_i + 32'd4;
reg [1:0] saved_pc_change = 2'b00;
parameter [4:0]
S_INIT = 5'd0,
S_RESET = 5'd1,
S_BLOCKED = 5'd2,
S_INT_1 = 5'd3,
S_READ_1 = 5'd4,
S_READ_2 = 5'd5,
S_READ_3 = 5'd6,
S_WAIT = 5'd7,
S_WRITE_1 = 5'd8,
S_WRITE_2 = 5'd9,
S_WRITE_3 = 5'd10,
S_PC_0 = 5'd11,
S_PC_1 = 5'd12,
S_PC_2 = 5'd13,
S_PC_3 = 5'd14,
S_PC_4 = 5'd15,
S_PC_5 = 5'd16,
S_PC_6 = 5'd17;
parameter [2:0]
FC_USER_DATA = 3'd1,
FC_USER_PROGRAM = 3'd2,
FC_SUPERVISOR_DATA = 3'd5, // all exception vector entries except reset
FC_SUPERVISOR_PROGRAM = 3'd6, // exception vector for reset
FC_CPU_SPACE = 3'd7; // interrupt acknowlege bus cycle
parameter [2:0]
CTI_CLASSIC_CYCLE = 3'd0,
CTI_CONST_CYCLE = 3'd1,
CTI_INCR_CYCLE = 3'd2,
CTI_END_OF_BURST = 3'd7;
parameter [7:0]
VECTOR_BUS_TRAP = 8'd2,
VECTOR_ADDRESS_TRAP = 8'd3;
reg [4:0] current_state;
reg [7:0] reset_counter;
reg [2:0] last_interrupt_mask;
always @(posedge CLK_I or negedge reset_n) begin
if(reset_n == 1'b0) begin
interrupt_mask_o <= 3'b000;
last_interrupt_mask <= 3'b000;
end
else if(ipl_i > ipm_i && do_interrupt_i == 1'b0) begin
interrupt_mask_o <= ipl_i;
last_interrupt_mask <= interrupt_mask_o;
end
else if(do_interrupt_i == 1'b1) begin
interrupt_mask_o <= last_interrupt_mask;
end
else begin
interrupt_mask_o <= 3'b000;
last_interrupt_mask <= 3'b000;
end
end
// change pc_i in middle of prefetch operation: undefined
always @(posedge CLK_I or negedge reset_n) begin
if(reset_n == 1'b0) begin
current_state <= S_INIT;
interrupt_trap_o <= 8'd0;
prefetch_ir_valid_o <= 1'b0;
prefetch_ir_valid_32_o <= 1'b0;
prefetch_ir_valid_80_o <= 1'b0;
jmp_address_trap_o <= 1'b0;
jmp_bus_trap_o <= 1'b0;
CYC_O <= 1'b0;
ADR_O <= 30'd0;
DAT_O <= 32'd0;
SEL_O <= 4'b0;
STB_O <= 1'b0;
WE_O <= 1'b0;
SGL_O <= 1'b0;
BLK_O <= 1'b0;
RMW_O <= 1'b0;
CTI_O <= 3'd0;
fc_o <= 3'd0;
reset_o <= 1'b0;
blocked_o <= 1'b0;
data_read_o <= 32'd0;
finished_o <= 1'b0;
rw_state_o <= 1'b0;
fc_state_o <= 3'd0;
fault_address_state_o <= 32'd0;
saved_pc_change <= 2'b0;
reset_counter <= 8'd0;
end
else begin
case(current_state)
S_INIT: begin
finished_o <= 1'b0;
jmp_address_trap_o <= 1'b0;
jmp_bus_trap_o <= 1'b0;
reset_o <= 1'b0;
blocked_o <= 1'b0;
// block
if(do_blocked_i == 1'b1) begin
blocked_o <= 1'b1;
current_state <= S_BLOCKED;
end
// reset
else if(do_reset_i == 1'b1) begin
reset_o <= 1'b1;
reset_counter <= 8'd124;
current_state <= S_RESET;
end
// read
else if(do_read_i == 1'b1) begin
WE_O <= 1'b0;
if(supervisor_i == 1'b1) fc_o <= (address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM;
else fc_o <= (address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM;
if(address_i[0] == 1'b1 && (size_i[0] == 1'b0)) begin // WORD or LONG WORD
fault_address_state_o <= address_i;
rw_state_o <= 1'b1;
fc_state_o <= (supervisor_i == 1'b1) ? ((address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM) :
((address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM);
interrupt_trap_o <= VECTOR_ADDRESS_TRAP;
jmp_address_trap_o <= 1'b1;
current_state <= S_WAIT;
end
else begin
CYC_O <= 1'b1;
ADR_O <= address_i[31:2];
SEL_O <= (size_i[0] == 1'b1 && address_i[1:0] == 2'b00)? 4'b1000 :
(size_i[0] == 1'b1 && address_i[1:0] == 2'b01)? 4'b0100 :
(size_i[0] == 1'b1 && address_i[1:0] == 2'b10)? 4'b0010 :
(size_i[0] == 1'b1 && address_i[1:0] == 2'b11)? 4'b0001 :
(size_i[1] == 1'b1 && address_i[1] == 2'b0)? 4'b1100 :
(size_i[0] == 1'b0 && address_i[1] == 2'b1)? 4'b0011 :
4'b1111;
STB_O <= 1'b1;
if(read_modify_write_i == 1'b1) begin
SGL_O <= 1'b0;
BLK_O <= 1'b0;
RMW_O <= 1'b1;
CTI_O <= CTI_END_OF_BURST;
end
else if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
SGL_O <= 1'b0;
BLK_O <= 1'b1;
RMW_O <= 1'b0;
CTI_O <= CTI_INCR_CYCLE;
end
else begin
SGL_O <= 1'b1;
BLK_O <= 1'b0;
RMW_O <= 1'b0;
CTI_O <= CTI_END_OF_BURST;
end
current_state <= S_READ_1;
end
end
// write
else if(do_write_i == 1'b1) begin
WE_O <= 1'b1;
if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_DATA;
else fc_o <= FC_USER_DATA;
if(address_i[0] == 1'b1 && size_i[0] == 1'b0) begin // WORD or LONG WORD
fault_address_state_o <= address_i;
rw_state_o <= 1'b0;
fc_state_o <= (supervisor_i == 1'b1) ? FC_SUPERVISOR_DATA : FC_USER_DATA;
interrupt_trap_o <= VECTOR_ADDRESS_TRAP;
jmp_address_trap_o <= 1'b1;
current_state <= S_WAIT;
end
else begin
CYC_O <= 1'b1;
ADR_O <= address_i[31:2];
STB_O <= 1'b1;
if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
DAT_O <= { 16'b0, data_write_i[31:16] };
SEL_O <= 4'b0011;
end
else if(address_i[1:0] == 2'b00 && size_i[2] == 1'b1) begin
DAT_O <= data_write_i[31:0];
SEL_O <= 4'b1111;
end
else if(address_i[1:0] == 2'b10 && size_i[1] == 1'b1) begin
DAT_O <= { 16'b0, data_write_i[15:0] };
SEL_O <= 4'b0011;
end
else if(address_i[1:0] == 2'b00 && size_i[1] == 1'b1) begin
DAT_O <= { data_write_i[15:0], 16'b0 };
SEL_O <= 4'b1100;
end
else if(address_i[1:0] == 2'b11 && size_i[0] == 1'b1) begin
DAT_O <= { 24'b0, data_write_i[7:0] };
SEL_O <= 4'b0001;
end
else if(address_i[1:0] == 2'b10 && size_i[0] == 1'b1) begin
DAT_O <= { 16'b0, data_write_i[7:0], 8'b0 };
SEL_O <= 4'b0010;
end
else if(address_i[1:0] == 2'b01 && size_i[0] == 1'b1) begin
DAT_O <= { 8'b0, data_write_i[7:0], 16'b0 };
SEL_O <= 4'b0100;
end
else if(address_i[1:0] == 2'b00 && size_i[0] == 1'b1) begin
DAT_O <= { data_write_i[7:0], 24'b0 };
SEL_O <= 4'b1000;
end
if(read_modify_write_i == 1'b1) begin
SGL_O <= 1'b0;
BLK_O <= 1'b0;
RMW_O <= 1'b1;
CTI_O <= CTI_END_OF_BURST;
end
else if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
SGL_O <= 1'b0;
BLK_O <= 1'b1;
RMW_O <= 1'b0;
CTI_O <= CTI_INCR_CYCLE;
end
else begin
SGL_O <= 1'b1;
BLK_O <= 1'b0;
RMW_O <= 1'b0;
CTI_O <= CTI_END_OF_BURST;
end
current_state <= S_WRITE_1;
end
end
// pc
else if(prefetch_ir_valid_o == 1'b0 || pc_change_i != 2'b00) begin
if(prefetch_ir_valid_o == 1'b0 || pc_change_i == 2'b10 || pc_change_i == 2'b11) begin
// load 4 words: [79:16] in 2,3 cycles
prefetch_ir_valid_32_o <= 1'b0;
prefetch_ir_valid_o <= 1'b0;
prefetch_ir_valid_80_o <= 1'b0;
current_state <= S_PC_0;
end
else if(prefetch_ir_valid_80_o == 1'b0 && pc_change_i == 2'b01) begin
// load 2 words: [31:0] in 1 cycle
prefetch_ir_valid_32_o <= 1'b1;
prefetch_ir_valid_o <= 1'b0;
prefetch_ir_valid_80_o <= 1'b0;
prefetch_ir_o <= { prefetch_ir_o[63:0], 16'b0 };
current_state <= S_PC_0;
end
else begin
// do not load any words
prefetch_ir_valid_32_o <= 1'b1;
prefetch_ir_valid_o <= 1'b1;
prefetch_ir_valid_80_o <= 1'b0;
prefetch_ir_o <= { prefetch_ir_o[63:0], 16'b0 };
end
end
// interrupt
else if(do_interrupt_i == 1'b1) begin
CYC_O <= 1'b1;
ADR_O <= { 27'b111_1111_1111_1111_1111_1111_1111, last_interrupt_mask };
SEL_O <= 4'b1111;
STB_O <= 1'b1;
WE_O <= 1'b0;
SGL_O <= 1'b1;
BLK_O <= 1'b0;
RMW_O <= 1'b0;
CTI_O <= CTI_END_OF_BURST;
fc_o <= FC_CPU_SPACE;
current_state <= S_INT_1;
end
end
S_RESET: begin
reset_counter <= reset_counter - 8'd1;
if(reset_counter == 8'd0) begin
finished_o <= 1'b1;
current_state <= S_WAIT;
end
end
S_BLOCKED: begin
end
S_INT_1: begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
interrupt_trap_o <= DAT_I[7:0];
finished_o <= 1'b1;
current_state <= S_WAIT;
end
else if(RTY_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
interrupt_trap_o <= 8'd24 + { 5'b0, interrupt_mask_o };
finished_o <= 1'b1;
current_state <= S_WAIT;
end
else if(ERR_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
interrupt_trap_o <= 8'd24; // spurious interrupt
finished_o <= 1'b1;
current_state <= S_WAIT;
end
end
S_PC_0: begin
WE_O <= 1'b0;
if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;
else fc_o <= FC_USER_PROGRAM;
if(pc_i[0] == 1'b1) begin
prefetch_ir_valid_32_o <= 1'b1;
prefetch_ir_valid_o <= 1'b1;
prefetch_ir_valid_80_o <= 1'b1;
fault_address_state_o <= pc_i;
rw_state_o <= 1'b1;
fc_state_o <= (supervisor_i == 1'b1) ? FC_SUPERVISOR_PROGRAM : FC_USER_PROGRAM;
interrupt_trap_o <= VECTOR_ADDRESS_TRAP;
jmp_address_trap_o <= 1'b1;
current_state <= S_WAIT;
end
else begin
CYC_O <= 1'b1;
if(prefetch_ir_valid_32_o == 1'b0) ADR_O <= pc_i[31:2];
else ADR_O <= pc_i_plus_6[31:2];
SEL_O <= (prefetch_ir_valid_32_o == 1'b0 && pc_i[1:0] == 2'b10)? 4'b0011 :
4'b1111;
STB_O <= 1'b1;
if(prefetch_ir_valid_32_o == 1'b0) begin
SGL_O <= 1'b0;
BLK_O <= 1'b1;
RMW_O <= 1'b0;
CTI_O <= CTI_INCR_CYCLE;
end
else begin
SGL_O <= 1'b1;
BLK_O <= 1'b0;
RMW_O <= 1'b0;
CTI_O <= CTI_END_OF_BURST;
end
saved_pc_change <= pc_change_i;
prefetch_ir_valid_32_o <= 1'b0;
current_state <= S_PC_1;
end
end
S_PC_1: begin
if(pc_change_i != 2'b00) saved_pc_change <= pc_change_i;
if(ACK_I == 1'b1) begin
if(CTI_O == CTI_INCR_CYCLE) begin
//CYC_O <= 1'b1;
ADR_O <= pc_i_plus_4[31:2];
SEL_O <= 4'b1111;
//STB_O <= 1'b1;
//WE_O <= 1'b0;
if(pc_i[1:0] == 2'b10) begin
SGL_O <= 1'b0;
BLK_O <= 1'b1;
RMW_O <= 1'b0;
CTI_O <= CTI_INCR_CYCLE;
end
else begin
SGL_O <= 1'b0;
BLK_O <= 1'b1;
RMW_O <= 1'b0;
CTI_O <= CTI_END_OF_BURST;
end
//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;
//else fc_o <= FC_USER_PROGRAM;
if(pc_i[1:0] == 2'b10) prefetch_ir_o <= { DAT_I[15:0], 64'b0 };
else prefetch_ir_o <= { DAT_I[31:0], 48'b0 };
current_state <= S_PC_3;
end
else begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
if(saved_pc_change == 2'b10 || saved_pc_change == 2'b11 || pc_change_i == 2'b10 || pc_change_i == 2'b11) begin
// load 4 words: [79:16] in 2,3 cycles
prefetch_ir_valid_32_o <= 1'b0;
prefetch_ir_valid_o <= 1'b0;
prefetch_ir_valid_80_o <= 1'b0;
current_state <= S_PC_0;
end
else if(saved_pc_change == 2'b01 || pc_change_i == 2'b01) begin
// do not load any words
prefetch_ir_valid_32_o <= 1'b1;
prefetch_ir_valid_o <= 1'b1;
prefetch_ir_valid_80_o <= 1'b0;
prefetch_ir_o <= { prefetch_ir_o[63:32], DAT_I[31:0], 16'b0 };
current_state <= S_INIT;
end
else begin
prefetch_ir_valid_32_o <= 1'b1;
prefetch_ir_valid_o <= 1'b1;
prefetch_ir_valid_80_o <= 1'b1;
prefetch_ir_o <= { prefetch_ir_o[79:32], DAT_I[31:0] };
current_state <= S_INIT;
end
end
end
else if(RTY_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
current_state <= S_PC_2;
end
else if(ERR_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
fault_address_state_o <= { ADR_O, 2'b00 };
rw_state_o <= ~WE_O;
fc_state_o <= fc_o;
interrupt_trap_o <= VECTOR_BUS_TRAP;
jmp_bus_trap_o <= 1'b1;
current_state <= S_WAIT;
end
end
S_PC_2: begin
CYC_O <= 1'b1;
STB_O <= 1'b1;
current_state <= S_PC_1;
end
S_PC_3: begin
if(ACK_I == 1'b1) begin
if(pc_i[1:0] == 2'b10) begin
//CYC_O <= 1'b1;
ADR_O <= pc_i_plus_6[31:2];
SEL_O <= 4'b1111;
//STB_O <= 1'b1;
//WE_O <= 1'b0;
SGL_O <= 1'b0;
BLK_O <= 1'b1;
RMW_O <= 1'b0;
CTI_O <= CTI_END_OF_BURST;
//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;
//else fc_o <= FC_USER_PROGRAM;
prefetch_ir_o <= { prefetch_ir_o[79:64], DAT_I[31:0], 32'b0 };
current_state <= S_PC_5;
end
else begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
prefetch_ir_o <= { prefetch_ir_o[79:48], DAT_I[31:0], 16'b0 };
prefetch_ir_valid_32_o <= 1'b1;
prefetch_ir_valid_o <= 1'b1;
prefetch_ir_valid_80_o <= 1'b0;
current_state <= S_INIT;
end
end
else if(RTY_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
current_state <= S_PC_4;
end
else if(ERR_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
fault_address_state_o <= { ADR_O, 2'b00 };
rw_state_o <= ~WE_O;
fc_state_o <= fc_o;
interrupt_trap_o <= VECTOR_BUS_TRAP;
jmp_bus_trap_o <= 1'b1;
current_state <= S_WAIT;
end
end
S_PC_4: begin
CYC_O <= 1'b1;
STB_O <= 1'b1;
current_state <= S_PC_3;
end
S_PC_5: begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
prefetch_ir_o <= { prefetch_ir_o[79:32], DAT_I[31:0] };
prefetch_ir_valid_32_o <= 1'b1;
prefetch_ir_valid_o <= 1'b1;
prefetch_ir_valid_80_o <= 1'b1;
current_state <= S_INIT;
end
else if(RTY_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
current_state <= S_PC_6;
end
else if(ERR_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
fault_address_state_o <= { ADR_O, 2'b00 };
rw_state_o <= ~WE_O;
fc_state_o <= fc_o;
interrupt_trap_o <= VECTOR_BUS_TRAP;
jmp_bus_trap_o <= 1'b1;
current_state <= S_WAIT;
end
end
S_PC_6: begin
CYC_O <= 1'b1;
STB_O <= 1'b1;
current_state <= S_PC_5;
end
//*******************
S_READ_1: begin
if(ACK_I == 1'b1) begin
if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
//CYC_O <= 1'b1;
ADR_O <= address_i_plus_4[31:2];
SEL_O <= 4'b1100;
//STB_O <= 1'b1;
//WE_O <= 1'b0;
//SGL_O <= 1'b0;
//BLK_O <= 1'b1;
//RMW_O <= 1'b0;
CTI_O <= CTI_END_OF_BURST;
//if(supervisor_i == 1'b1) fc_o <= (address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM;
//else fc_o <= (address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM;
data_read_o <= { DAT_I[15:0], 16'b0 };
current_state <= S_READ_2;
end
else begin
if(read_modify_write_i == 1'b1) begin
CYC_O <= 1'b1;
STB_O <= 1'b0;
end
else begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
end
if(address_i[1:0] == 2'b00 && size_i[2] == 1'b1) data_read_o <= DAT_I[31:0];
else if(address_i[1:0] == 2'b10 && size_i[1] == 1'b1) data_read_o <= { {16{DAT_I[15]}}, DAT_I[15:0] };
else if(address_i[1:0] == 2'b00 && size_i[1] == 1'b1) data_read_o <= { {16{DAT_I[31]}}, DAT_I[31:16] };
else if(address_i[1:0] == 2'b11 && size_i[0] == 1'b1) data_read_o <= { {24{DAT_I[7]}}, DAT_I[7:0] };
else if(address_i[1:0] == 2'b10 && size_i[0] == 1'b1) data_read_o <= { {24{DAT_I[15]}}, DAT_I[15:8] };
else if(address_i[1:0] == 2'b01 && size_i[0] == 1'b1) data_read_o <= { {24{DAT_I[23]}}, DAT_I[23:16] };
else if(address_i[1:0] == 2'b00 && size_i[0] == 1'b1) data_read_o <= { {24{DAT_I[31]}}, DAT_I[31:24] };
finished_o <= 1'b1;
current_state <= S_WAIT;
end
end
else if(RTY_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
current_state <= S_INIT;
end
else if(ERR_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
fault_address_state_o <= { ADR_O, 2'b00 };
rw_state_o <= ~WE_O;
fc_state_o <= fc_o;
interrupt_trap_o <= VECTOR_BUS_TRAP;
jmp_bus_trap_o <= 1'b1;
current_state <= S_WAIT;
end
end
S_READ_2: begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
data_read_o <= { data_read_o[31:16], DAT_I[31:16] };
finished_o <= 1'b1;
current_state <= S_WAIT;
end
else if(RTY_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
current_state <= S_READ_3;
end
else if(ERR_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
fault_address_state_o <= { ADR_O, 2'b00 };
rw_state_o <= ~WE_O;
fc_state_o <= fc_o;
interrupt_trap_o <= VECTOR_BUS_TRAP;
jmp_bus_trap_o <= 1'b1;
current_state <= S_WAIT;
end
end
S_READ_3: begin
CYC_O <= 1'b1;
STB_O <= 1'b1;
current_state <= S_READ_2;
end
S_WAIT: begin
jmp_address_trap_o <= 1'b0;
jmp_bus_trap_o <= 1'b0;
if(do_read_i == 1'b0 && do_write_i == 1'b0 && do_interrupt_i == 1'b0 && do_reset_i == 1'b0) begin
finished_o <= 1'b0;
current_state <= S_INIT;
end
end
//**********************
S_WRITE_1: begin
if(ACK_I == 1'b1) begin
if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
//CYC_O <= 1'b1;
ADR_O <= address_i_plus_4[31:2];
//STB_O <= 1'b1;
//WE_O <= 1'b1;
DAT_O <= { data_write_i[15:0], 16'b0 };
SEL_O <= 4'b1100;
//SGL_O <= 1'b0;
//BLK_O <= 1'b1;
//RMW_O <= 1'b0;
CTI_O <= CTI_END_OF_BURST;
//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_DATA;
//else fc_o <= FC_USER_DATA;
current_state <= S_WRITE_2;
end
else begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
finished_o <= 1'b1;
current_state <= S_WAIT;
end
end
else if(RTY_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
current_state <= S_INIT;
end
else if(ERR_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
fault_address_state_o <= { ADR_O, 2'b00 };
rw_state_o <= ~WE_O;
fc_state_o <= fc_o;
interrupt_trap_o <= VECTOR_BUS_TRAP;
jmp_bus_trap_o <= 1'b1;
current_state <= S_WAIT;
end
end
S_WRITE_2: begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
finished_o <= 1'b1;
current_state <= S_WAIT;
end
else if(RTY_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
current_state <= S_WRITE_3;
end
else if(ERR_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
fault_address_state_o <= { ADR_O, 2'b00 };
rw_state_o <= ~WE_O;
fc_state_o <= fc_o;
interrupt_trap_o <= VECTOR_BUS_TRAP;
jmp_bus_trap_o <= 1'b1;
current_state <= S_WAIT;
end
end
S_WRITE_3: begin
CYC_O <= 1'b1;
STB_O <= 1'b1;
current_state <= S_WRITE_2;
end
endcase
end
end
endmodule
/***********************************************************************************************************************
* Registers
**********************************************************************************************************************/
/*! \brief Microcode controlled registers.
*
* Most of the ao68000 IP core registers are located in this module. At every clock cycle the microcode controls what
* to save into these registers. Some of the more important registers include:
* - operand1, operand2 registers are inputs to the ALU,
* - address, size, do_read_flag, do_write_flag, do_interrupt_flag registers tell the bus_control module what kind
* of bus cycle to perform,
* - pc register stores the current program counter,
* - ir register stores the current instruction word,
* - ea_mod, ea_type registers store the currently selected addressing mode.
*/
module registers(
input clock,
input reset_n,
input [31:0] data_read,
input [79:0] prefetch_ir,
input prefetch_ir_valid,
input [31:0] result,
input [15:0] sr,
input rw_state,
input [2:0] fc_state,
input [31:0] fault_address_state,
input [7:0] interrupt_trap,
input [2:0] interrupt_mask,
input [7:0] decoder_trap,
input [31:0] usp,
input [31:0] Dn_output,
input [31:0] An_output,
output [1:0] pc_change,
output reg [2:0] ea_reg,
input [2:0] ea_reg_control,
output reg [2:0] ea_mod,
input [3:0] ea_mod_control,
output reg [3:0] ea_type,
input [3:0] ea_type_control,
// for DIVU/DIVS simulation, register must be not zero
output reg [31:0] operand1 = 32'hFFFFFFFF,
input [3:0] operand1_control,
output reg [31:0] operand2 = 32'hFFFFFFFF,
input [2:0] operand2_control,
output reg [31:0] address,
output reg address_type,
input [3:0] address_control,
output reg [2:0] size,
input [3:0] size_control,
output reg [5:0] movem_modreg,
input [2:0] movem_modreg_control,
output reg [4:0] movem_loop,
input [1:0] movem_loop_control,
output reg [15:0] movem_reg,
input [1:0] movem_reg_control,
output reg [15:0] ir,
input [1:0] ir_control,
output reg [31:0] pc,
input [2:0] pc_control,
output reg [7:0] trap,
input [3:0] trap_control,
output reg [31:0] offset,
input [1:0] offset_control,
output reg [31:0] index,
input [1:0] index_control,
output reg stop_flag,
input [1:0] stop_flag_control,
output reg trace_flag,
input [1:0] trace_flag_control,
output reg group_0_flag,
input [1:0] group_0_flag_control,
output reg instruction_flag,
input [1:0] instruction_flag_control,
output reg read_modify_write_flag,
input [1:0] read_modify_write_flag_control,
output reg do_reset_flag,
input [1:0] do_reset_flag_control,
output reg do_interrupt_flag,
input [1:0] do_interrupt_flag_control,
output reg do_read_flag,
input [1:0] do_read_flag_control,
output reg do_write_flag,
input [1:0] do_write_flag_control,
output reg do_blocked_flag,
input [1:0] do_blocked_flag_control,
output reg [31:0] data_write,
input [1:0] data_write_control,
output [3:0] An_address,
input [1:0] An_address_control,
output [31:0] An_input,
input [1:0] An_input_control,
output [2:0] Dn_address,
input Dn_address_control,
input [17:0] decoder_alu,
output reg [17:0] decoder_alu_reg
);
reg [31:0] pc_valid;
wire [31:0] pc_next =
(pc_control == `PC_FROM_RESULT)? result :
(pc_control == `PC_INCR_BY_2)? pc + 32'd2 :
(pc_control == `PC_INCR_BY_4)? pc + 32'd4 :
(pc_control == `PC_INCR_BY_SIZE)? (size[2] == 1'b0) ? pc + 32'd2 : pc + 32'd4 :
(pc_control == `PC_FROM_PREFETCH_IR)? prefetch_ir[47:16] :
(pc_control == `PC_INCR_BY_2_IN_MAIN_LOOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0)?
pc + 32'd2 :
pc;
// pc_change connected
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) begin
pc <= 32'd0;
pc_valid <= 32'd0;
end
else begin
pc <= pc_next;
if(pc_next[0] == 1'b0) pc_valid <= pc_next;
end
end
assign pc_change =
( pc_control == `PC_FROM_RESULT || pc_control == `PC_FROM_PREFETCH_IR
) ? 2'b11 :
( pc_control == `PC_INCR_BY_4 || (pc_control == `PC_INCR_BY_SIZE && size[2] == 1'b1)
) ? 2'b10 :
( pc_control == `PC_INCR_BY_2 || (pc_control == `PC_INCR_BY_SIZE && size[2] == 1'b0) ||
(pc_control == `PC_INCR_BY_2_IN_MAIN_LOOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0)
) ? 2'b01 :
2'b00;
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) begin
size <= 2'b00;
end
else if(size_control != `SIZE_IDLE) begin
// BYTE
size[0] <= (size_control == `SIZE_BYTE)
| ((size_control == `SIZE_3) && (ir[7:6] == 2'b00))
| ((size_control == `SIZE_4) && (ir[13:12] == 2'b01))
| ((size_control == `SIZE_6) && (ir[5:3] != 3'b000));
// WORD
size[1] <= (size_control == `SIZE_WORD)
| ((size_control == `SIZE_1) && (ir[7:6] == 2'b00))
| ((size_control == `SIZE_1_PLUS) && (ir[7:6] == 2'b10))
| ((size_control == `SIZE_2) && (ir[6] == 1'b0))
| ((size_control == `SIZE_3) && (ir[7:6] == 2'b01))
| ((size_control == `SIZE_4) && (ir[13:12] == 2'b11))
| ((size_control == `SIZE_5) && (ir[8] == 1'b0));
// LONG
size[2] <= (size_control == `SIZE_LONG)
| ((size_control == `SIZE_1) && (ir[7:6] != 2'b00))
| ((size_control == `SIZE_1_PLUS) && (ir[7:6] != 2'b10))
| ((size_control == `SIZE_2) && (ir[6] == 1'b1))
| ((size_control == `SIZE_3) && (ir[7] == 1'b1))
| ((size_control == `SIZE_4) && (ir[12] == 1'b0))
| ((size_control == `SIZE_5) && (ir[8] == 1'b1))
| ((size_control == `SIZE_6) && (ir[5:3] == 3'b000));
end
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) ea_reg <= 3'b000;
else if(ea_reg_control == `EA_REG_IR_2_0) ea_reg <= ir[2:0];
else if(ea_reg_control == `EA_REG_IR_11_9) ea_reg <= ir[11:9];
else if(ea_reg_control == `EA_REG_MOVEM_REG_2_0) ea_reg <= movem_modreg[2:0];
else if(ea_reg_control == `EA_REG_3b111) ea_reg <= 3'b111;
else if(ea_reg_control == `EA_REG_3b100) ea_reg <= 3'b100;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) ea_mod <= 3'b000;
else if(ea_mod_control == `EA_MOD_IR_5_3) ea_mod <= ir[5:3];
else if(ea_mod_control == `EA_MOD_MOVEM_MOD_5_3) ea_mod <= movem_modreg[5:3];
else if(ea_mod_control == `EA_MOD_IR_8_6) ea_mod <= ir[8:6];
else if(ea_mod_control == `EA_MOD_PREDEC) ea_mod <= 3'b100;
else if(ea_mod_control == `EA_MOD_3b111) ea_mod <= 3'b111;
else if(ea_mod_control == `EA_MOD_DN_PREDEC) ea_mod <= (ir[3] == 1'b0) ? /* Dn */ 3'b000 : /* -(An) */ 3'b100;
else if(ea_mod_control == `EA_MOD_DN_AN_EXG) ea_mod <= (ir[7:3] == 5'b01000 || ir[7:3] == 5'b10001) ? /* Dn */ 3'b000 : /* An */ 3'b001;
else if(ea_mod_control == `EA_MOD_POSTINC) ea_mod <= 3'b011;
else if(ea_mod_control == `EA_MOD_AN) ea_mod <= 3'b001;
else if(ea_mod_control == `EA_MOD_DN) ea_mod <= 3'b000;
else if(ea_mod_control == `EA_MOD_INDIRECTOFFSET) ea_mod <= 3'b101;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) ea_type <= `EA_TYPE_IDLE;
else if(ea_type_control == `EA_TYPE_ALL) ea_type <= `EA_TYPE_ALL;
else if(ea_type_control == `EA_TYPE_CONTROL_POSTINC) ea_type <= `EA_TYPE_CONTROL_POSTINC;
else if(ea_type_control == `EA_TYPE_CONTROLALTER_PREDEC) ea_type <= `EA_TYPE_CONTROLALTER_PREDEC;
else if(ea_type_control == `EA_TYPE_CONTROL) ea_type <= `EA_TYPE_CONTROL;
else if(ea_type_control == `EA_TYPE_DATAALTER) ea_type <= `EA_TYPE_DATAALTER;
else if(ea_type_control == `EA_TYPE_DN_AN) ea_type <= `EA_TYPE_DN_AN;
else if(ea_type_control == `EA_TYPE_MEMORYALTER) ea_type <= `EA_TYPE_MEMORYALTER;
else if(ea_type_control == `EA_TYPE_DATA) ea_type <= `EA_TYPE_DATA;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) operand1 <= 32'hFFFFFFFF;
else if(operand1_control == `OP1_FROM_OP2) operand1 <= operand2;
else if(operand1_control == `OP1_FROM_ADDRESS) operand1 <= address;
else if(operand1_control == `OP1_FROM_DATA) operand1 <=
(size[0] == 1'b1) ? { {24{data_read[7]}}, data_read[7:0] } :
(size[1] == 1'b1) ? { {16{data_read[15]}}, data_read[15:0] } :
data_read[31:0];
else if(operand1_control == `OP1_FROM_IMMEDIATE) operand1 <=
(size[0] == 1'b1) ? { {24{prefetch_ir[71]}}, prefetch_ir[71:64] } :
(size[1] == 1'b1) ? { {16{prefetch_ir[79]}}, prefetch_ir[79:64] } :
prefetch_ir[79:48];
else if(operand1_control == `OP1_FROM_RESULT) operand1 <= result;
else if(operand1_control == `OP1_MOVEQ) operand1 <= { {24{ir[7]}}, ir[7:0] };
else if(operand1_control == `OP1_FROM_PC) operand1 <= pc_valid;
else if(operand1_control == `OP1_LOAD_ZEROS) operand1 <= 32'b0;
else if(operand1_control == `OP1_LOAD_ONES) operand1 <= 32'hFFFFFFFF;
else if(operand1_control == `OP1_FROM_SR) operand1 <= { 16'b0, sr[15], 1'b0, sr[13], 2'b0, sr[10:8], 3'b0, sr[4:0] };
else if(operand1_control == `OP1_FROM_USP) operand1 <= usp;
else if(operand1_control == `OP1_FROM_AN) operand1 <=
(size[1] == 1'b1) ? { {16{An_output[15]}}, An_output[15:0] } :
An_output[31:0];
else if(operand1_control == `OP1_FROM_DN) operand1 <=
(size[0] == 1'b1) ? { {24{Dn_output[7]}}, Dn_output[7:0] } :
(size[1] == 1'b1) ? { {16{Dn_output[15]}}, Dn_output[15:0] } :
Dn_output[31:0];
else if(operand1_control == `OP1_FROM_IR) operand1 <= { 16'b0, ir[15:0] };
else if(operand1_control == `OP1_FROM_FAULT_ADDRESS) operand1 <= fault_address_state;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) operand2 <= 32'hFFFFFFFF;
else if(operand2_control == `OP2_FROM_OP1) operand2 <= operand1;
else if(operand2_control == `OP2_LOAD_1) operand2 <= 32'd1;
else if(operand2_control == `OP2_LOAD_COUNT) operand2 <=
(ir[5] == 1'b0) ? ( (ir[11:9] == 3'b000) ? 32'b1000 : { 29'b0, ir[11:9] } ) :
{ 26'b0, operand2[5:0] };
else if(operand2_control == `OP2_ADDQ_SUBQ) operand2 <= (ir[11:9] == 3'b000) ? 32'b1000 : { 29'b0, ir[11:9] };
else if(operand2_control == `OP2_MOVE_OFFSET) operand2 <= (ir[7:0] == 8'b0) ? operand2[31:0] : { {24{ir[7]}}, ir[7:0] };
else if(operand2_control == `OP2_MOVE_ADDRESS_BUS_INFO) operand2 <= { 16'b0, 11'b0, rw_state, instruction_flag, fc_state};
else if(operand2_control == `OP2_DECR_BY_1) operand2 <= operand2 - 32'b1;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) address <= 32'b0;
else if(address_control == `ADDRESS_INCR_BY_SIZE) address <= ((size[0]) && ea_reg == 3'b111) ? address + 32'd2 : address + {29'd0,size};
else if(address_control == `ADDRESS_DECR_BY_SIZE) address <= ((size[0]) && ea_reg == 3'b111) ? address - 32'd2 : address - {29'd0,size};
else if(address_control == `ADDRESS_INCR_BY_2) address <= address + 32'd2;
else if(address_control == `ADDRESS_FROM_AN_OUTPUT) address <= An_output;
else if(address_control == `ADDRESS_FROM_BASE_INDEX_OFFSET) address <= address + index + offset;
else if(address_control == `ADDRESS_FROM_IMM_16) address <= { {16{prefetch_ir[79]}}, prefetch_ir[79:64] };
else if(address_control == `ADDRESS_FROM_IMM_32) address <= prefetch_ir[79:48];
else if(address_control == `ADDRESS_FROM_PC_INDEX_OFFSET) address <= pc_valid + index + offset;
else if(address_control == `ADDRESS_FROM_TRAP) address <= {22'b0, trap[7:0], 2'b0};
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) address_type <= 1'b0;
else if(address_control == `ADDRESS_FROM_PC_INDEX_OFFSET) address_type <= 1'b1;
else if(address_control != `ADDRESS_IDLE) address_type <= 1'b0;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) movem_modreg <= 6'b0;
else if(movem_modreg_control == `MOVEM_MODREG_LOAD_0) movem_modreg <= 6'b0;
else if(movem_modreg_control == `MOVEM_MODREG_LOAD_6b001111)movem_modreg <= 6'b001111;
else if(movem_modreg_control == `MOVEM_MODREG_INCR_BY_1) movem_modreg <= movem_modreg + 6'd1;
else if(movem_modreg_control == `MOVEM_MODREG_DECR_BY_1) movem_modreg <= movem_modreg - 6'd1;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) movem_loop <= 5'b0;
else if(movem_loop_control == `MOVEM_LOOP_LOAD_0) movem_loop <= 5'b0;
else if(movem_loop_control == `MOVEM_LOOP_INCR_BY_1) movem_loop <= movem_loop + 5'd1;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) movem_reg <= 16'b0;
else if(movem_reg_control == `MOVEM_REG_FROM_OP1) movem_reg <= operand1[15:0];
else if(movem_reg_control == `MOVEM_REG_SHIFT_RIGHT) movem_reg <= { 1'b0, movem_reg[15:1] };
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) ir <= 16'b0;
else if(ir_control == `IR_LOAD_WHEN_PREFETCH_VALID && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0)
ir <= prefetch_ir[79:64];
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) decoder_alu_reg <= 18'b0;
else if(ir_control == `IR_LOAD_WHEN_PREFETCH_VALID && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0)
decoder_alu_reg <= decoder_alu;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) trap <= 8'd0;
else if(trap_control == `TRAP_ILLEGAL_INSTR) trap <= 8'd4;
else if(trap_control == `TRAP_DIV_BY_ZERO) trap <= 8'd5;
else if(trap_control == `TRAP_CHK) trap <= 8'd6;
else if(trap_control == `TRAP_TRAPV) trap <= 8'd7;
else if(trap_control == `TRAP_PRIVIL_VIOLAT) trap <= 8'd8;
else if(trap_control == `TRAP_TRACE) trap <= 8'd9;
else if(trap_control == `TRAP_TRAP) trap <= { 4'b0010, ir[3:0] };
else if(trap_control == `TRAP_FROM_DECODER) trap <= decoder_trap;
else if(trap_control == `TRAP_FROM_INTERRUPT) trap <= interrupt_trap;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) offset <= 32'd0;
else if(offset_control == `OFFSET_IMM_8) offset <= { {24{prefetch_ir[71]}}, prefetch_ir[71:64] };
else if(offset_control == `OFFSET_IMM_16) offset <= { {16{prefetch_ir[79]}}, prefetch_ir[79:64] };
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) index <= 32'd0;
else if(index_control == `INDEX_0) index <= 32'd0;
else if(index_control == `INDEX_LOAD_EXTENDED) index <=
(prefetch_ir[79] == 1'b0) ?
( (prefetch_ir[75] == 1'b0) ?
{ {16{Dn_output[15]}}, Dn_output[15:0] } : Dn_output[31:0]
) :
( (prefetch_ir[75] == 1'b0) ?
{ {16{An_output[15]}}, An_output[15:0] } : An_output[31:0]
);
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) stop_flag <= 1'b0;
else if(stop_flag_control == `STOP_FLAG_SET) stop_flag <= 1'b1;
else if(stop_flag_control == `STOP_FLAG_CLEAR) stop_flag <= 1'b0;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) trace_flag <= 1'b0;
else if(trace_flag_control == `TRACE_FLAG_COPY_WHEN_NO_STOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0)
trace_flag <= sr[15];
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) group_0_flag <= 1'b0;
else if(group_0_flag_control == `GROUP_0_FLAG_SET) group_0_flag <= 1'b1;
else if(group_0_flag_control == `GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0)
group_0_flag <= 1'b0;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) instruction_flag <= 1'b0;
else if(instruction_flag_control == `INSTRUCTION_FLAG_SET) instruction_flag <= 1'b1;
else if(instruction_flag_control == `INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0)
instruction_flag <= 1'b0;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) read_modify_write_flag <= 1'b0;
else if(read_modify_write_flag_control == `READ_MODIFY_WRITE_FLAG_SET) read_modify_write_flag <= 1'b1;
else if(read_modify_write_flag_control == `READ_MODIFY_WRITE_FLAG_CLEAR) read_modify_write_flag <= 1'b0;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) do_reset_flag <= 1'b0;
else if(do_reset_flag_control == `DO_RESET_FLAG_SET) do_reset_flag <= 1'b1;
else if(do_reset_flag_control == `DO_RESET_FLAG_CLEAR) do_reset_flag <= 1'b0;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) do_interrupt_flag <= 1'b0;
else if(do_interrupt_flag_control == `DO_INTERRUPT_FLAG_SET_IF_ACTIVE) do_interrupt_flag <= (interrupt_mask != 3'b000) ? 1'b1 : 1'b0;
else if(do_interrupt_flag_control == `DO_INTERRUPT_FLAG_CLEAR) do_interrupt_flag <= 1'b0;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) do_read_flag <= 1'b0;
else if(do_read_flag_control == `DO_READ_FLAG_SET) do_read_flag <= 1'b1;
else if(do_read_flag_control == `DO_READ_FLAG_CLEAR) do_read_flag <= 1'b0;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) do_write_flag <= 1'b0;
else if(do_write_flag_control == `DO_WRITE_FLAG_SET) do_write_flag <= 1'b1;
else if(do_write_flag_control == `DO_WRITE_FLAG_CLEAR) do_write_flag <= 1'b0;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) do_blocked_flag <= 1'b0;
else if(do_blocked_flag_control == `DO_BLOCKED_FLAG_SET) do_blocked_flag <= 1'b1;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) data_write <= 32'd0;
else if(data_write_control == `DATA_WRITE_FROM_RESULT) data_write <= result;
end
assign An_address =
(An_address_control == `AN_ADDRESS_FROM_EXTENDED) ? { sr[13], prefetch_ir[78:76] } :
(An_address_control == `AN_ADDRESS_USP) ? 4'b0111 :
(An_address_control == `AN_ADDRESS_SSP) ? 4'b1111 :
{ sr[13], ea_reg };
assign An_input =
(An_input_control == `AN_INPUT_FROM_ADDRESS) ? address :
(An_input_control == `AN_INPUT_FROM_PREFETCH_IR) ? prefetch_ir[79:48] :
result;
assign Dn_address = (Dn_address_control == `DN_ADDRESS_FROM_EXTENDED) ? prefetch_ir[78:76] : ea_reg;
endmodule
/***********************************************************************************************************************
* Memory registers
**********************************************************************************************************************/
/*! \brief Contains the microcode ROM and D0-D7, A0-A7 registers.
*
* The memory_registers module contains:
* - data and address registers (D0-D7, A0-A7) implemented as an on-chip RAM.
* - the microcode implemented as an on-chip ROM.
*
* Currently this module contains <em>altsyncram</em> instantiations
* from Altera Megafunction/LPM library.
*/
module memory_registers(
input clock,
input reset_n,
// 0000,0001,0010,0011,0100,0101,0110: A0-A6, 0111: USP, 1111: SSP
input [3:0] An_address,
input [31:0] An_input,
input An_write_enable,
output [31:0] An_output,
output reg [31:0] usp,
input [2:0] Dn_address,
input [31:0] Dn_input,
input Dn_write_enable,
// 001: byte, 010: word, 100: long
input [2:0] Dn_size,
output [31:0] Dn_output,
input [8:0] micro_pc,
output [87:0] micro_data
);
wire An_ram_write_enable = (An_address == 4'b0111) ? 1'b0 : An_write_enable;
wire [31:0] An_ram_output;
assign An_output = (An_address == 4'b0111) ? usp : An_ram_output;
wire [3:0] dn_byteena = (Dn_size[0] == 1'b1) ? 4'b0001 :
(Dn_size[1] == 1'b1) ? 4'b0011 :
(Dn_size[2] == 1'b1) ? 4'b1111 :
4'b0000;
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) usp <= 32'd0;
else if(An_address == 4'b0111 && An_write_enable) usp <= An_input;
end
// Register set An implemented as RAM.
altsyncram an_ram_inst(
.clock0 (clock),
.address_a (An_address[2:0]),
.byteena_a (4'b1111),
.wren_a (An_ram_write_enable),
.data_a (An_input),
.q_a (An_ram_output)
);
defparam
an_ram_inst.operation_mode = "SINGLE_PORT",
an_ram_inst.width_a = 32,
an_ram_inst.widthad_a = 3,
an_ram_inst.width_byteena_a = 4;
// Register set Dn implemented as RAM.
altsyncram dn_ram_inst(
.clock0 (clock),
.address_a (Dn_address),
.byteena_a (dn_byteena),
.wren_a (Dn_write_enable),
.data_a (Dn_input),
.q_a (Dn_output)
);
defparam
dn_ram_inst.operation_mode = "SINGLE_PORT",
dn_ram_inst.width_a = 32,
dn_ram_inst.widthad_a = 3,
dn_ram_inst.width_byteena_a = 4;
// Microcode ROM
altsyncram micro_rom_inst(
.clock0 (clock),
.address_a (micro_pc),
.q_a (micro_data)
);
defparam
micro_rom_inst.operation_mode = "ROM",
micro_rom_inst.width_a = 88,
micro_rom_inst.widthad_a = 9,
micro_rom_inst.init_file = "ao68000_microcode.mif";
endmodule
/***********************************************************************************************************************
* Instruction decoder
**********************************************************************************************************************/
/*! \brief Decode instruction and addressing mode.
*
* The decoder is an instruction and addressing mode decoder. For instructions it takes as input the ir register
* from the registers module. The output of the decoder, in this case, is a microcode address of the first microcode
* word that performs the instruction.
*
* In case of addressing mode decoding, the output is the address of the first microcode word that performs the operand
* loading or saving. This address is obtained from the currently selected addressing mode saved in the ea_mod
* and ea_type registers in the registers module.
*/
module decoder(
input clock,
input reset_n,
input supervisor,
input [15:0] ir,
// zero: no trap
output [7:0] decoder_trap,
output [8:0] decoder_micropc,
output [17:0] decoder_alu,
output [8:0] save_ea,
output [8:0] perform_ea_write,
output [8:0] perform_ea_read,
output [8:0] load_ea,
input [3:0] ea_type,
input [2:0] ea_mod,
input [2:0] ea_reg
);
parameter [7:0]
NO_TRAP = 8'd0,
ILLEGAL_INSTRUCTION_TRAP = 8'd4,
PRIVILEGE_VIOLATION_TRAP = 8'd8,
ILLEGAL_1010_INSTRUCTION_TRAP = 8'd10,
ILLEGAL_1111_INSTRUCTION_TRAP = 8'd11;
parameter [8:0]
UNUSED_MICROPC = 9'd0;
assign { decoder_trap, decoder_micropc } =
(reset_n == 1'b0) ? { NO_TRAP, UNUSED_MICROPC } :
// Privilege violation and illegal instruction
// ANDI to SR,EORI to SR,ORI to SR,RESET,STOP,RTE,MOVE TO SR,MOVE USP TO USP,MOVE USP TO An privileged instructions
( ( ir[15:0] == 16'b0000_0010_01_111_100 ||
ir[15:0] == 16'b0000_1010_01_111_100 ||
ir[15:0] == 16'b0000_0000_01_111_100 ||
ir[15:0] == 16'b0100_1110_0111_0000 ||
ir[15:0] == 16'b0100_1110_0111_0010 ||
ir[15:0] == 16'b0100_1110_0111_0011 ||
(ir[15:6] == 10'b0100_0110_11 && ir[5:3] != 3'b001 && ir[5:0] != 6'b111_101 && ir[5:0] != 6'b111_110 && ir[5:0] != 6'b111_111) ||
ir[15:3] == 13'b0100_1110_0110_0 ||
ir[15:3] == 13'b0100_1110_0110_1 ) && supervisor == 1'b0 ) ? { PRIVILEGE_VIOLATION_TRAP, UNUSED_MICROPC } :
// ILLEGAL, illegal instruction
( ir[15:0] == 16'b0100_1010_11_111100 ) ? { ILLEGAL_INSTRUCTION_TRAP, UNUSED_MICROPC } :
// 1010 illegal instruction
( ir[15:12] == 4'b1010 ) ? { ILLEGAL_1010_INSTRUCTION_TRAP, UNUSED_MICROPC } :
// 1111 illegal instruction
( ir[15:12] == 4'b1111 ) ? { ILLEGAL_1111_INSTRUCTION_TRAP, UNUSED_MICROPC } :
// instruction decoding
// ANDI,EORI,ORI,ADDI,SUBI
( ir[15:12] == 4'b0000 && ir[11:9] != 3'b100 && ir[11:9] != 3'b110 && ir[11:9] != 3'b111 && ir[8] == 1'b0 &&
(ir[7:6] == 2'b00 || ir[7:6] == 2'b01 || ir[7:6] == 2'b10) && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001)) &&
ir[15:0] != 16'b0000_000_0_00_111100 && ir[15:0] != 16'b0000_000_0_01_111100 &&
ir[15:0] != 16'b0000_001_0_00_111100 && ir[15:0] != 16'b0000_001_0_01_111100 &&
ir[15:0] != 16'b0000_101_0_00_111100 && ir[15:0] != 16'b0000_101_0_01_111100 ) ? { NO_TRAP, `MICROPC_ANDI_EORI_ORI_ADDI_SUBI } :
// ORI to CCR,ORI to SR,ANDI to CCR,ANDI to SR,EORI to CCR,EORI to SR
( ir[15:0] == 16'b0000_000_0_00_111100 || ir[15:0] == 16'b0000_000_0_01_111100 ||
ir[15:0] == 16'b0000_001_0_00_111100 || ir[15:0] == 16'b0000_001_0_01_111100 ||
ir[15:0] == 16'b0000_101_0_00_111100 || ir[15:0] == 16'b0000_101_0_01_111100 ) ?
{ NO_TRAP, `MICROPC_ORI_to_CCR_ORI_to_SR_ANDI_to_CCR_ANDI_to_SR_EORI_to_CCR_EORI_to_SR } :
// BTST register
( ir[15:12] == 4'b0000 && ir[8:6] == 3'b100 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_BTST_register } :
// MOVEP memory to register
( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] == 3'b001 && ( ir[7:6] == 2'b00 || ir[7:6] == 2'b01 ) ) ?
{ NO_TRAP, `MICROPC_MOVEP_memory_to_register } :
// MOVEP register to memory
( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] == 3'b001 && ( ir[7:6] == 2'b10 || ir[7:6] == 2'b11 ) ) ?
{ NO_TRAP, `MICROPC_MOVEP_register_to_memory } :
// BCHG,BCLR,BSET register
( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] != 3'b001 && ir[8:6] != 3'b100 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_BCHG_BCLR_BSET_register } :
// BTST immediate
( ir[15:12] == 4'b0000 && ir[11:8] == 4'b1000 && ir[7:6] == 2'b00 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
) ? { NO_TRAP, `MICROPC_BTST_immediate } :
// BCHG,BCLR,BSET immediate
( ir[15:12] == 4'b0000 && ir[11:8] == 4'b1000 && ir[7:6] != 2'b00 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_BCHG_BCLR_BSET_immediate } :
// CMPI
( ir[15:12] == 4'b0000 && ir[8] == 1'b0 && ir[11:9] == 3'b110 && ir[7:6] != 2'b11 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_CMPI } :
// MOVE
( ir[15:14] == 2'b00 && ir[13:12] != 2'b00 && ir[8:6] != 3'b001 &&
(ir[8:6] != 3'b111 || (ir[11:6] == 6'b000_111 || ir[11:6] == 6'b001_111)) &&
(ir[13:12] != 2'b01 || ir[5:3] != 3'b001) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_MOVE } :
// MOVEA
( ir[15:14] == 2'b00 && (ir[13:12] == 2'b11 || ir[13:12] == 2'b10) && ir[8:6] == 3'b001 &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_MOVEA } :
// NEGX,CLR,NEG,NOT,NBCD
( ir[15:12] == 4'b0100 && ir[5:3] != 3'b001 && (ir[5:3] != 3'b111 || ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001) &&
( (ir[11:8] == 4'b0000 && ir[7:6] != 2'b11) || (ir[11:8] == 4'b0010 && ir[7:6] != 2'b11) ||
(ir[11:8] == 4'b0100 && ir[7:6] != 2'b11) || (ir[11:8] == 4'b0110 && ir[7:6] != 2'b11) ||
(ir[11:6] == 6'b1000_00)
)
) ? { NO_TRAP, `MICROPC_NEGX_CLR_NEG_NOT_NBCD } :
// MOVE FROM SR
( ir[15:6] == 10'b0100_0000_11 && ir[5:3] != 3'b001 && (ir[5:3] != 3'b111 || ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001)
) ? { NO_TRAP, `MICROPC_MOVE_FROM_SR } :
// CHK
( ir[15:12] == 4'b0100 && ir[8:6] == 3'b110 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_CHK } :
// LEA
( ir[15:12] == 4'b0100 && ir[8:6] == 3'b111 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
) ? { NO_TRAP, `MICROPC_LEA } :
// MOVE TO CCR, MOVE TO SR
( (ir[15:6] == 10'b0100_0100_11 || ir[15:6] == 10'b0100_0110_11) && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_MOVE_TO_CCR_MOVE_TO_SR } :
// SWAP,EXT
( ir[15:12] == 4'b0100 && (ir[11:3] == 9'b1000_01_000 || (ir[11:7] == 5'b1000_1 && ir[5:3] == 3'b000) ) ) ? { NO_TRAP, `MICROPC_SWAP_EXT } :
// PEA
( ir[15:6] == 10'b0100_1000_01 && ir[5:3] != 3'b000 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
) ? { NO_TRAP, `MICROPC_PEA } :
// MOVEM register to memory, predecrement
( ir[15:7] == 9'b0100_1000_1 && ir[5:3] == 3'b100 ) ? { NO_TRAP, `MICROPC_MOVEM_register_to_memory_predecrement } :
// MOVEM register to memory, control
( ir[15:7] == 9'b0100_1000_1 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
(ir[5:3] != 3'b111 || ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001)
) ? { NO_TRAP, `MICROPC_MOVEM_register_to_memory_control } :
// TST
( ir[15:8] == 8'b0100_1010 && ir[7:6] != 2'b11 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_TST } :
// TAS
( ir[15:6] == 10'b0100_1010_11 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_TAS } :
// MOVEM memory to register
( ir[15:7] == 9'b0100_1100_1 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b011 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
) ? { NO_TRAP, `MICROPC_MOVEM_memory_to_register } :
// TRAP
( ir[15:4] == 12'b0100_1110_0100 ) ? { NO_TRAP, `MICROPC_TRAP } :
// LINK
( ir[15:3] == 13'b0100_1110_0101_0 ) ? { NO_TRAP, `MICROPC_LINK } :
// UNLK
( ir[15:3] == 13'b0100_1110_0101_1 ) ? { NO_TRAP, `MICROPC_ULNK } :
// MOVE USP to USP
( ir[15:3] == 13'b0100_1110_0110_0 ) ? { NO_TRAP, `MICROPC_MOVE_USP_to_USP } :
// MOVE USP to An
( ir[15:3] == 13'b0100_1110_0110_1 ) ? { NO_TRAP, `MICROPC_MOVE_USP_to_An } :
// RESET
( ir[15:0] == 16'b0100_1110_0111_0000 ) ? { NO_TRAP, `MICROPC_RESET } :
// NOP
( ir[15:0] == 16'b0100_1110_0111_0001 ) ? { NO_TRAP, `MICROPC_NOP } :
// STOP
( ir[15:0] == 16'b0100_1110_0111_0010 ) ? { NO_TRAP, `MICROPC_STOP } :
// RTE,RTR
( ir[15:0] == 16'b0100_1110_0111_0011 || ir[15:0] == 16'b0100_1110_0111_0111 ) ? { NO_TRAP, `MICROPC_RTE_RTR } :
// RTS
( ir[15:0] == 16'b0100_1110_0111_0101 ) ? { NO_TRAP, `MICROPC_RTS } :
// TRAPV
( ir[15:0] == 16'b0100_1110_0111_0110 ) ? { NO_TRAP, `MICROPC_TRAPV } :
// JSR
( ir[15:6] == 10'b0100_1110_10 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
) ? { NO_TRAP, `MICROPC_JSR } :
// JMP
( ir[15:6] == 10'b0100_1110_11 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
) ? { NO_TRAP, `MICROPC_JMP } :
// ADDQ,SUBQ not An
( ir[15:12] == 4'b0101 && ir[7:6] != 2'b11 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_ADDQ_SUBQ_not_An } :
// ADDQ,SUBQ An
( ir[15:12] == 4'b0101 && ir[7:6] != 2'b11 && ir[7:6] != 2'b00 && ir[5:3] == 3'b001 ) ? { NO_TRAP, `MICROPC_ADDQ_SUBQ_An } :
// Scc
( ir[15:12] == 4'b0101 && ir[7:6] == 2'b11 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_Scc } :
// DBcc
( ir[15:12] == 4'b0101 && ir[7:6] == 2'b11 && ir[5:3] == 3'b001 ) ? { NO_TRAP, `MICROPC_DBcc } :
// BSR
( ir[15:12] == 4'b0110 && ir[11:8] == 4'b0001 ) ? { NO_TRAP, `MICROPC_BSR } :
// Bcc,BRA
( ir[15:12] == 4'b0110 && ir[11:8] != 4'b0001 ) ? { NO_TRAP, `MICROPC_Bcc_BRA } :
// MOVEQ
( ir[15:12] == 4'b0111 && ir[8] == 1'b0 ) ? { NO_TRAP, `MICROPC_MOVEQ } :
// CMP
( (ir[15:12] == 4'b1011) && (ir[8:6] == 3'b000 || ir[8:6] == 3'b001 || ir[8:6] == 3'b010) &&
(ir[8:6] != 3'b000 || ir[5:3] != 3'b001) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_CMP } :
// CMPA
( (ir[15:12] == 4'b1011) && (ir[8:6] == 3'b011 || ir[8:6] == 3'b111) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_CMPA } :
// CMPM
( ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] == 3'b001) ? { NO_TRAP, `MICROPC_CMPM } :
// EOR
( ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_EOR } :
// ADD to mem,SUB to mem,AND to mem,OR to mem
( (ir[15:12] == 4'b1101 || ir[15:12] == 4'b1001 || ir[15:12] == 4'b1100 || ir[15:12] == 4'b1000) &&
(ir[8:4] == 5'b10001 || ir[8:4] == 5'b10010 || ir[8:4] == 5'b10011 ||
ir[8:4] == 5'b10101 || ir[8:4] == 5'b10110 || ir[8:4] == 5'b10111 ||
ir[8:4] == 5'b11001 || ir[8:4] == 5'b11010 || ir[8:4] == 5'b11011) &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_ADD_to_mem_SUB_to_mem_AND_to_mem_OR_to_mem } :
// ADD to Dn,SUB to Dn,AND to Dn,OR to Dn
( (ir[15:12] == 4'b1101 || ir[15:12] == 4'b1001 || ir[15:12] == 4'b1100 || ir[15:12] == 4'b1000) &&
(ir[8:6] == 3'b000 || ir[8:6] == 3'b001 || ir[8:6] == 3'b010) &&
(ir[12] != 1'b1 || ir[8:6] != 3'b000 || ir[5:3] != 3'b001) && (ir[12] == 1'b1 || ir[5:3] != 3'b001) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_ADD_to_Dn_SUB_to_Dn_AND_to_Dn_OR_to_Dn } :
// ADDA,SUBA
( (ir[15:12] == 4'b1101 || ir[15:12] == 4'b1001) && (ir[8:6] == 3'b011 || ir[8:6] == 3'b111) &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_ADDA_SUBA } :
// ABCD,SBCD,ADDX,SUBX
( ((ir[15:12] == 4'b1100 || ir[15:12] == 4'b1000) && ir[8:4] == 5'b10000) ||
((ir[15:12] == 4'b1101 || ir[15:12] == 4'b1001) && (ir[8:4] == 5'b10000 || ir[8:4] == 5'b10100 || ir[8:4] == 5'b11000) ) ) ?
{ NO_TRAP, `MICROPC_ABCD_SBCD_ADDX_SUBX } :
// EXG
( ir[15:12] == 4'b1100 && (ir[8:3] == 6'b101000 || ir[8:3] == 6'b101001 || ir[8:3] == 6'b110001) ) ? { NO_TRAP, `MICROPC_EXG } :
// MULS,MULU,DIVS,DIVU
( (ir[15:12] == 4'b1100 || ir[15:12] == 4'b1000) && ir[7:6] == 2'b11 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 ||
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
) ? { NO_TRAP, `MICROPC_MULS_MULU_DIVS_DIVU } :
// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all memory
( ir[15:12] == 4'b1110 && ir[11] == 1'b0 && ir[7:6] == 2'b11 && ir[5:3] != 3'b000 && ir[5:3] != 3'b001 &&
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
) ? { NO_TRAP, `MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_memory } :
// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all immediate/register
( ir[15:12] == 4'b1110 && (ir[7:6] == 2'b00 || ir[7:6] == 2'b01 || ir[7:6] == 2'b10) ) ?
{ NO_TRAP, `MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_immediate_register } :
// else
{ ILLEGAL_INSTRUCTION_TRAP, UNUSED_MICROPC }
;
// load ea
assign load_ea =
(
(ea_type == `EA_TYPE_ALL && (ea_mod == 3'b000 || ea_mod == 3'b001 || (ea_mod == 3'b111 && ea_reg == 3'b100))) ||
(ea_type == `EA_TYPE_DATAALTER && ea_mod == 3'b000) ||
(ea_type == `EA_TYPE_DN_AN && (ea_mod == 3'b000 || ea_mod == 3'b001)) ||
(ea_type == `EA_TYPE_DATA && (ea_mod == 3'b000 || (ea_mod == 3'b111 && ea_reg == 3'b100)))
) ? 9'd0 // no ea needed
:
(ea_mod == 3'b010 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER ||
ea_type == `EA_TYPE_DATA
)) ? `MICROPC_LOAD_EA_An // (An)
:
(ea_mod == 3'b011 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_MEMORYALTER ||
ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_LOAD_EA_An_plus // (An)+
:
(ea_mod == 3'b100 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROLALTER_PREDEC || ea_type == `EA_TYPE_DATAALTER ||
ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_LOAD_EA_minus_An // -(An)
:
(ea_mod == 3'b101 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_LOAD_EA_d16_An // (d16, An)
:
(ea_mod == 3'b110 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_LOAD_EA_d8_An_Xn // (d8, An, Xn)
:
(ea_mod == 3'b111 && ea_reg == 3'b000 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_LOAD_EA_xxx_W // (xxx).W
:
(ea_mod == 3'b111 && ea_reg == 3'b001 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_LOAD_EA_xxx_L // (xxx).L
:
(ea_mod == 3'b111 && ea_reg == 3'b010 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_LOAD_EA_d16_PC // (d16, PC)
:
(ea_mod == 3'b111 && ea_reg == 3'b011 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_LOAD_EA_d8_PC_Xn // (d8, PC, Xn)
:
`MICROPC_LOAD_EA_illegal_command // illegal command
;
// perform ea read
assign perform_ea_read =
( ea_mod == 3'b000 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_DN_AN ||
ea_type == `EA_TYPE_DATA) ) ?
`MICROPC_PERFORM_EA_READ_Dn :
( ea_mod == 3'b001 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DN_AN) ) ? `MICROPC_PERFORM_EA_READ_An :
( ea_mod == 3'b111 && ea_reg == 3'b100 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DATA) ) ?
`MICROPC_PERFORM_EA_READ_imm :
`MICROPC_PERFORM_EA_READ_memory
;
// perform ea write
assign perform_ea_write =
( ea_mod == 3'b000 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_DN_AN ||
ea_type == `EA_TYPE_DATA) ) ?
`MICROPC_PERFORM_EA_WRITE_Dn :
( ea_mod == 3'b001 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DN_AN) ) ? `MICROPC_PERFORM_EA_WRITE_An :
`MICROPC_PERFORM_EA_WRITE_memory
;
// save ea
assign save_ea =
(ea_mod == 3'b011 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_MEMORYALTER ||
ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_SAVE_EA_An_plus // (An)+
:
(ea_mod == 3'b100 && (
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROLALTER_PREDEC || ea_type == `EA_TYPE_DATAALTER ||
ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
)) ? `MICROPC_SAVE_EA_minus_An // -(An)
:
9'd0 // no ea needed
;
// ALU decoding optimization
// Thanks to Frederic Requin
// not used: 7, 13, 17
assign decoder_alu[0] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b000) // OR
|| (ir[15:12] == 4'b1000));
assign decoder_alu[1] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b001) // AND
|| (ir[15:12] == 4'b1100));
assign decoder_alu[2] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b101) // EOR
|| (ir[15:12] == 4'b1011 && (ir[8:7] == 2'b10 || ir[8:6] == 3'b110) && ir[5:3] != 3'b001));
assign decoder_alu[3] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b011) // ADD
|| (ir[15:12] == 4'b1101)
|| (ir[15:12] == 4'b0101 && ir[8] == 1'b0));
assign decoder_alu[4] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b010) // SUB
|| (ir[15:12] == 4'b1001)
|| (ir[15:12] == 4'b0101 && ir[8] == 1'b1));
assign decoder_alu[5] = ((ir[15:12] == 4'b0000 && ir[11:9] == 3'b110) // CMP
|| (ir[15:12] == 4'b1011 && (ir[8:7] == 2'b10 || ir[8:6] == 3'b110) && ir[5:3] == 3'b001)
|| (ir[15:12] == 4'b1011 && (ir[8:7] == 2'b00 || ir[8:6] == 3'b010)));
assign decoder_alu[6] = ((ir[15:12] == 4'b1101) // ADDA,ADDQ
|| (ir[15:12] == 4'b0101 && ir[8] == 1'b0));
assign decoder_alu[7] = ((ir[15:12] == 4'b1001) // SUBA,CMPA,SUBQ
|| (ir[15:12] == 4'b1011)
|| (ir[15:12] == 4'b0101 && ir[8] == 1'b1));
assign decoder_alu[8] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) // ASL
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) && ir[8] == 1'b1);
assign decoder_alu[9] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b01) // LSL
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b01)) && ir[8] == 1'b1);
assign decoder_alu[10] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b11) // ROL
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b11)) && ir[8] == 1'b1);
assign decoder_alu[11] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b10) // ROXL
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b10)) && ir[8] == 1'b1);
assign decoder_alu[12] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) // ASR
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) && ir[8] == 1'b0);
assign decoder_alu[13] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b01) // LSR
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b01)) && ir[8] == 1'b0);
assign decoder_alu[14] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b11) // ROR
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b11)) && ir[8] == 1'b0);
assign decoder_alu[15] = (((ir[7:6] == 2'b11 && ir[10:9] == 2'b10) // ROXR
|| (ir[7:6] != 2'b11 && ir[4:3] == 2'b10)) && ir[8] == 1'b0);
assign decoder_alu[16] = ((ir[15:8] == 8'b0100_0110) // SR operations
|| (ir[15:0] == 16'b0100_1110_0111_0011)
|| (ir[15:0] == 16'b0100_1110_0111_0010)
|| (ir[15:0] == 16'b0000_000_0_01_111100)
|| (ir[15:0] == 16'b0000_001_0_01_111100)
|| (ir[15:0] == 16'b0000_101_0_01_111100));
assign decoder_alu[17] = ((ir[15:8] == 8'b0100_0100) // CCR operations
|| (ir[15:0] == 16'b0100_1110_0111_0111)
|| (ir[15:0] == 16'b0000_000_0_00_111100)
|| (ir[15:0] == 16'b0000_001_0_00_111100)
|| (ir[15:0] == 16'b0000_101_0_00_111100));
endmodule
/***********************************************************************************************************************
* Condition
**********************************************************************************************************************/
/*! \brief Condition tests.
*
* The condition module implements the condition tests of the MC68000. Its inputs are the condition codes
* and the currently selected test. The output is binary: the test is true or false. The output of the condition module
* is an input to the microcode_branch module, that decides which microcode word to execute next.
*/
module condition(
input [3:0] cond,
input [7:0] ccr,
output condition
);
wire C,V,Z,N;
assign C = ccr[0];
assign V = ccr[1];
assign Z = ccr[2];
assign N = ccr[3];
assign condition = (cond == 4'b0000) ? 1'b1 : // true
(cond == 4'b0001) ? 1'b0 : // false
(cond == 4'b0010) ? ~C & ~Z : // high
(cond == 4'b0011) ? C | Z : // low or same
(cond == 4'b0100) ? ~C : // carry clear
(cond == 4'b0101) ? C : // carry set
(cond == 4'b0110) ? ~Z : // not equal
(cond == 4'b0111) ? Z : // equal
(cond == 4'b1000) ? ~V : // overflow clear
(cond == 4'b1001) ? V : // overflow set
(cond == 4'b1010) ? ~N : // plus
(cond == 4'b1011) ? N : // minus
(cond == 4'b1100) ? (N & V) | (~N & ~V) : // greater or equal
(cond == 4'b1101) ? (N & ~V) | (~N & V) : // less than
(cond == 4'b1110) ? (N & V & ~Z) | (~N & ~V & ~Z) : // greater than
(cond == 4'b1111) ? (Z) | (N & ~V) | (~N & V) : // less or equal
1'b0;
endmodule
/***********************************************************************************************************************
* ALU
**********************************************************************************************************************/
/*! \brief Arithmetic and Logic Unit.
*
* The alu module is responsible for performing all of the arithmetic and logic operations of the ao68000 processor.
* It operates on two 32-bit registers: operand1 and operand2 from the registers module. The output is saved into
* a result 32-bit register. This register is located in the alu module.
*
* The alu module also contains the status register (SR) with the condition code register. The microcode decides what
* operation the alu performs.
*/
module alu(
input clock,
input reset_n,
// only zero bit
input [31:0] address,
// only ir[11:9] and ir[6]
input [15:0] ir,
// byte 2'b00, word 2'b01, long 2'b10
input [2:0] size,
input [31:0] operand1,
input [31:0] operand2,
input [2:0] interrupt_mask,
input [4:0] alu_control,
output reg [15:0] sr,
output reg [31:0] result,
output reg alu_signal,
output alu_mult_div_ready,
input [17:0] decoder_alu_reg
);
//****************************************************** Altera-specific multiplication and division modules START
/* Multiplication and division modules.
*
* Currently this module contains:
* - <em>lpm_mult</em> instantiation from Altera Megafunction/LPM library,
* - a sequential state machine for division written by Frederic Requin
*/
wire mult_div_sign = ir[8];
// 18-2 - division calculation, 1 - waiting for result read, 0 - idle
reg [4:0] div_count;
reg [16:0] quotient;
reg [31:0] dividend, divider;
// Compute the difference with borrow
wire [32:0] div_diff = (dividend - divider);
// Overflow flag: when (quotient >= 65536) or (signed division and (quotient >= 32768 or quotient < -32768))
wire div_overflow =
(quotient[16] == 1'b1 ||
(mult_div_sign == 1'b1 && (
((operand1[31] ^ operand2[15]) == 1'b0 && quotient[15] == 1'b1) ||
((operand1[31] ^ operand2[15]) == 1'b1 && quotient[15:0] > 16'd32768) )));
wire [15:0] div_quotient =
// positive quotient
(((operand1[31] ^ operand2[15]) & mult_div_sign) == 1'b0)? quotient[15:0] :
// negative quotient
-quotient[15:0];
wire [15:0] div_remainder =
// positive remainder
((operand1[31] & mult_div_sign) == 1'b0)? dividend[15:0] :
// negative remainder
-dividend[15:0];
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) begin
div_count <= 5'd0;
end
// Cycle #0 : load the registers
else if(alu_control == `ALU_MULS_MULU_DIVS_DIVU && ir[15:12] == 4'b1000 && div_count == 5'd0) begin
// 17 cycles to finish + wait state
div_count <= 5'd18;
// Clear the quotient
quotient <= 17'd0;
// Unsigned divide or positive numerator
if ((!mult_div_sign) || (!operand1[31])) dividend <= operand1;
// Negative numerator
else dividend <= -operand1;
// Unsigned divide or positive denominator
if ((!mult_div_sign) || (!operand2[15])) divider <= {operand2[15:0],16'd0};
// Negative denominator
else divider <= {-operand2[15:0],16'd0};
end
// Cycles #1-17 : division calculation
else if(div_count > 5'd1) begin
// Check difference's sign
if (!div_diff[32]) begin
// Difference is positive : shift a one
dividend <= div_diff[31:0];
quotient <= {quotient[15:0], 1'b1};
end
else begin
// Difference is negative : shift a zero
quotient <= {quotient[15:0], 1'b0};
end
// Shift right divider
divider <= {1'b0, divider[31:1]};
// Count one bit
div_count <= div_count - 5'd1;
end
// result read
else if(alu_control == `ALU_MULS_MULU_DIVS_DIVU && ir[15:12] == 4'b1000 && div_count == 5'd1) begin
// goto idle
div_count <= div_count - 5'd1;
end
end
// MULS/MULU: 16-bit operand1[15:0] signed/unsigned * operand2[15:0] signed/unsigned = 32-bit result signed/unsigned
// Optimization by Frederic Requin
wire [33:0] mult_result;
lpm_mult muls(
.clock (clock),
.dataa ({operand1[15] & mult_div_sign, operand1[15:0]}),
.datab ({operand2[15] & mult_div_sign, operand2[15:0]}),
.result (mult_result)
);
defparam
muls.lpm_widtha = 17,
muls.lpm_widthb = 17,
muls.lpm_widthp = 34,
muls.lpm_representation = "SIGNED",
muls.lpm_pipeline = 1;
// multiplication ready in one cycle, division ready when div_count in waiting or idle state
assign alu_mult_div_ready = (div_count == 5'd1 || div_count == 5'd0);
//****************************************************** Altera-specific multiplication and division modules END
wire [5:0] result_ABCD_13_8a = {1'b0, operand1[3:0]} + {1'b0, operand2[3:0]} + {4'b0, sr[4]};
wire [5:0] result_ABCD_19_14 = {1'b0, operand1[7:4]} + {1'b0, operand2[7:4]};
wire [8:0] result_ABCD_31_23 = operand1[7:0] + operand2[7:0] + {7'b0, sr[4]};
wire [5:0] result_ABCD_13_8b = (result_ABCD_13_8a > 6'd9) ? (result_ABCD_13_8a + 6'd6) : result_ABCD_13_8a;
wire [5:0] result_SBCD_13_8a = 6'd32 + {2'b0, operand1[3:0]} - {2'b0, operand2[3:0]} - {5'b0, sr[4]};
wire [5:0] result_SBCD_19_14 = 6'd32 + {2'b0, operand1[7:4]} - {2'b0, operand2[7:4]};
wire [8:0] result_SBCD_31_23 = operand1[7:0] - operand2[7:0] - {7'b0, sr[4]};
wire [5:0] result_SBCD_13_8b = (result_SBCD_13_8a < 6'd32) ? (result_SBCD_13_8a - 6'd6) : result_SBCD_13_8a;
wire [5:0] result_ABCD2_19_14a = (result[13:8] > 6'h1F) ? (result[19:14] + 6'd2) :
(result[13:8] > 6'h0F) ? (result[19:14] + 6'd1) :
result[19:14];
wire [5:0] result_ABCD2_19_14b = (result_ABCD2_19_14a > 6'd9) ? (result_ABCD2_19_14a + 6'd6) : result_ABCD2_19_14a;
wire [3:0] result_ABCD2_7_4 = result_ABCD2_19_14b[3:0];
wire [3:0] result_ABCD2_3_0 = result[11:8];
wire [31:0] result_ABCD2 = {result[31:20], result_ABCD2_19_14b, result[13:8], result_ABCD2_7_4, result_ABCD2_3_0};
wire [5:0] result_SBCD2_19_14a = (result[13:8] < 6'd16) ? (result[19:14] - 6'd2) :
(result[13:8] < 6'd32) ? (result[19:14] - 6'd1) :
result[19:14];
wire [5:0] result_SBCD2_19_14b = (result_SBCD2_19_14a < 6'd32 && result[31] == 1'b1) ? (result_SBCD2_19_14a - 6'd6) : result_SBCD2_19_14a;
wire [3:0] result_SBCD2_7_4 = result_SBCD2_19_14b[3:0];
wire [3:0] result_SBCD2_3_0 = result[11:8];
wire [31:0] result_SBCD2 = {result[31:20], result_SBCD2_19_14b, result[13:8], result_SBCD2_7_4, result_SBCD2_3_0};
wire [15:0] result_CHK = operand1[15:0] - operand2[15:0];
wire result_BITS8_val = ~(operand1[ operand2[2:0] ]);
wire result_BITS8_bit = (ir[7:6] == 2'b01) ? result_BITS8_val : (ir[7:6] == 2'b10) ? 1'b0 : 1'b1;
wire [31:0] result_BITS8 = { operand1[31:8],
(operand2[2:0] == 3'd7)? result_BITS8_bit : operand1[7],
(operand2[2:0] == 3'd6)? result_BITS8_bit : operand1[6],
(operand2[2:0] == 3'd5)? result_BITS8_bit : operand1[5],
(operand2[2:0] == 3'd4)? result_BITS8_bit : operand1[4],
(operand2[2:0] == 3'd3)? result_BITS8_bit : operand1[3],
(operand2[2:0] == 3'd2)? result_BITS8_bit : operand1[2],
(operand2[2:0] == 3'd1)? result_BITS8_bit : operand1[1],
(operand2[2:0] == 3'd0)? result_BITS8_bit : operand1[0] };
wire result_BITS32_val = ~(operand1[ operand2[4:0] ]);
wire result_BITS32_bit = (ir[7:6] == 2'b01) ? result_BITS32_val : (ir[7:6] == 2'b10) ? 1'b0 : 1'b1;
wire [31:0] result_BITS32 = { (operand2[4:0] == 5'd31)? result_BITS32_bit : operand1[31],
(operand2[4:0] == 5'd30)? result_BITS32_bit : operand1[30],
(operand2[4:0] == 5'd29)? result_BITS32_bit : operand1[29],
(operand2[4:0] == 5'd28)? result_BITS32_bit : operand1[28],
(operand2[4:0] == 5'd27)? result_BITS32_bit : operand1[27],
(operand2[4:0] == 5'd26)? result_BITS32_bit : operand1[26],
(operand2[4:0] == 5'd25)? result_BITS32_bit : operand1[25],
(operand2[4:0] == 5'd24)? result_BITS32_bit : operand1[24],
(operand2[4:0] == 5'd23)? result_BITS32_bit : operand1[23],
(operand2[4:0] == 5'd22)? result_BITS32_bit : operand1[22],
(operand2[4:0] == 5'd21)? result_BITS32_bit : operand1[21],
(operand2[4:0] == 5'd20)? result_BITS32_bit : operand1[20],
(operand2[4:0] == 5'd19)? result_BITS32_bit : operand1[19],
(operand2[4:0] == 5'd18)? result_BITS32_bit : operand1[18],
(operand2[4:0] == 5'd17)? result_BITS32_bit : operand1[17],
(operand2[4:0] == 5'd16)? result_BITS32_bit : operand1[16],
(operand2[4:0] == 5'd15)? result_BITS32_bit : operand1[15],
(operand2[4:0] == 5'd14)? result_BITS32_bit : operand1[14],
(operand2[4:0] == 5'd13)? result_BITS32_bit : operand1[13],
(operand2[4:0] == 5'd12)? result_BITS32_bit : operand1[12],
(operand2[4:0] == 5'd11)? result_BITS32_bit : operand1[11],
(operand2[4:0] == 5'd10)? result_BITS32_bit : operand1[10],
(operand2[4:0] == 5'd9 )? result_BITS32_bit : operand1[9 ],
(operand2[4:0] == 5'd8 )? result_BITS32_bit : operand1[8 ],
(operand2[4:0] == 5'd7 )? result_BITS32_bit : operand1[7 ],
(operand2[4:0] == 5'd6 )? result_BITS32_bit : operand1[6 ],
(operand2[4:0] == 5'd5 )? result_BITS32_bit : operand1[5 ],
(operand2[4:0] == 5'd4 )? result_BITS32_bit : operand1[4 ],
(operand2[4:0] == 5'd3 )? result_BITS32_bit : operand1[3 ],
(operand2[4:0] == 5'd2 )? result_BITS32_bit : operand1[2 ],
(operand2[4:0] == 5'd1 )? result_BITS32_bit : operand1[1 ],
(operand2[4:0] == 5'd0 )? result_BITS32_bit : operand1[0 ] };
wire [4:0] result_NBCD_3_0a = 5'd25 - operand1[3:0];
wire [4:0] result_NBCD_7_4a = (operand1[3:0] > 4'd9) ? (5'd24 - operand1[7:4]) : (5'd25 - operand1[7:4]);
wire [3:0] result_NBCD_3_0b = (sr[4] == 1'b0 && result_NBCD_3_0a[3:0] == 4'd9 && result_NBCD_7_4a[3:0] == 4'd9)? 4'd0 :
(sr[4] == 1'b0 && (result_NBCD_3_0a[3:0] == 4'd9 || result_NBCD_3_0a[3:0] == 4'd15))? 4'd0 :
(sr[4] == 1'b0)? result_NBCD_3_0a[3:0] + 4'd1 :
result_NBCD_3_0a[3:0];
wire [3:0] result_NBCD_7_4b = (sr[4] == 1'b0 && result_NBCD_3_0a[3:0] == 4'd9 && result_NBCD_7_4a[3:0] == 4'd9)? 4'd0 :
(sr[4] == 1'b0 && (result_NBCD_3_0a[3:0] == 4'd9 || result_NBCD_3_0a[3:0] == 4'd15))? result_NBCD_7_4a[3:0] + 4'd1 :
result_NBCD_7_4a[3:0];
wire [31:0] result_blocking =
// OR,OR to mem,OR to Dn
(alu_control == `ALU_ARITHMETIC_LOGIC && decoder_alu_reg[0])? operand1[31:0] | operand2[31:0] :
// AND,AND to mem,AND to Dn
(alu_control == `ALU_ARITHMETIC_LOGIC && decoder_alu_reg[1])? operand1[31:0] & operand2[31:0] :
// EORI,EOR
(alu_control == `ALU_ARITHMETIC_LOGIC && decoder_alu_reg[2])? operand1[31:0] ^ operand2[31:0] :
// ADD,ADD to mem,ADD to Dn,ADDQ
(alu_control == `ALU_ARITHMETIC_LOGIC && decoder_alu_reg[3])? operand1[31:0] + operand2[31:0] :
// SUBI,CMPI,CMPM,SUB to mem,SUB to Dn,CMP,SUBQ
(alu_control == `ALU_ARITHMETIC_LOGIC && (decoder_alu_reg[4] | decoder_alu_reg[5]))? operand1[31:0] - operand2[31:0] :
// ABCD
(alu_control == `ALU_ABCD_SBCD_ADDX_SUBX_prepare && ir[14:12] == 3'b100)? { result_ABCD_31_23, result[22:20], result_ABCD_19_14, result_ABCD_13_8b, result[7:0] } :
// SBCD
(alu_control == `ALU_ABCD_SBCD_ADDX_SUBX_prepare && ir[14:12] == 3'b000)? { result_SBCD_31_23, result[22:20], result_SBCD_19_14, result_SBCD_13_8b, result[7:0] } :
// ABCD2
(alu_control == `ALU_ABCD_SBCD_ADDX_SUBX && ir[14:12] == 3'b100)? result_ABCD2 :
// SBCD2
(alu_control == `ALU_ABCD_SBCD_ADDX_SUBX && ir[14:12] == 3'b000)? result_SBCD2 :
// ADDX
(alu_control == `ALU_ABCD_SBCD_ADDX_SUBX && ir[14:12] == 3'b101)? operand1[31:0] + operand2[31:0] + sr[4] :
// SUBX
(alu_control == `ALU_ABCD_SBCD_ADDX_SUBX && ir[14:12] == 3'b001)? operand1[31:0] - operand2[31:0] - sr[4] :
// shift/rotate prepare
(alu_control == `ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare)? operand1[31:0] :
// ASL / LSL / ROL / ROXL
(alu_control == `ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR &&
(decoder_alu_reg[8] | decoder_alu_reg[9] | decoder_alu_reg[10] | decoder_alu_reg[11]))? {operand1[30:0], lbit} :
// ASR / LSR / ROR / ROXR
(alu_control == `ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR)? {rbit, operand1[31:17], (size[1]) ? rbit : operand1[16], operand1[15:9],
(size[0]) ? rbit : operand1[8], operand1[7:1] } :
// MOVE
(alu_control == `ALU_MOVE)? operand1 :
// ADDA,ADDQ
(alu_control == `ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ && decoder_alu_reg[6])? operand1[31:0] + operand2[31:0] :
// SUBA,CMPA,SUBQ
(alu_control == `ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ)? operand1[31:0] - operand2[31:0] :
// CHK
(alu_control == `ALU_CHK)? { result[31:16], result_CHK } :
// NEGX / CLR / NEG / NOT
(alu_control == `ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT &&
((ir[11:8] == 4'b0000) || (ir[11:8] == 4'b0010) || (ir[11:8] == 4'b0100) || (ir[11:8] == 4'b0110)))?
32'b0 - (operand1[31:0] & {32{ir[10] | ~ir[9]}}) - ((sr[4] & ~ir[10] & ~ir[9]) | (ir[10] & ir[9])) :
// NBCD
(alu_control == `ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT && ir[11:6] == 6'b1000_00)? { result[31:8], result_NBCD_7_4b, result_NBCD_3_0b } :
// SWAP
(alu_control == `ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT && ir[11:6] == 6'b1000_01)? { operand1[15:0], operand1[31:16] } :
// EXT byte to word
(alu_control == `ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT && ir[11:6] == 6'b1000_10)? { result[31:16], {8{operand1[7]}}, operand1[7:0] } :
// EXT word to long
(alu_control == `ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT && ir[11:6] == 6'b1000_11)? { {16{operand1[15]}}, operand1[15:0] } :
// else
result[31:0];
// ALU internal defines
`define Sm ((size[0] == 1'b1) ? operand2[7] : (size[1] == 1'b1) ? operand2[15] : operand2[31])
`define Dm ((size[0] == 1'b1) ? operand1[7] : (size[1] == 1'b1) ? operand1[15] : operand1[31])
`define Rm ((size[0] == 1'b1) ? result_blocking[7] : (size[1] == 1'b1) ? result_blocking[15] : result_blocking[31])
`define Z ((size[0] == 1'b1) ? (result_blocking[7:0] == 8'b0) :(size[1] == 1'b1) ? (result_blocking[15:0] == 16'b0) : (result_blocking[31:0] == 32'b0))
// ALU operations
reg [2:0] interrupt_mask_copy;
reg was_interrupt;
// Bit being shifted left
wire lbit = (`Dm & decoder_alu_reg[10]) | (sr[4] & decoder_alu_reg[11]);
// Bit being shifted right
wire rbit = (`Dm & decoder_alu_reg[12]) | (operand1[0] & decoder_alu_reg[14]) | (sr[4] & decoder_alu_reg[15]);
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) begin
sr <= { 1'b0, 1'b0, 1'b1, 2'b0, 3'b111, 8'b0 };
result <= 32'd0;
alu_signal <= 1'b0;
interrupt_mask_copy <= 3'b0;
was_interrupt <= 1'b0;
end
else begin
case(alu_control)
`ALU_SR_SET_INTERRUPT: begin
interrupt_mask_copy <= interrupt_mask[2:0];
was_interrupt <= 1'b1;
end
`ALU_SR_SET_TRAP: begin
if(was_interrupt == 1'b1) begin
sr <= { 1'b0, sr[14], 1'b1, sr[12:11], interrupt_mask_copy[2:0], sr[7:0] };
end
else begin
sr <= { 1'b0, sr[14], 1'b1, sr[12:0] };
end
was_interrupt <= 1'b0;
end
`ALU_MOVEP_M2R_1: begin
if(ir[6] == 1'b1) result[31:24] <= operand1[7:0];
else result[15:8] <= operand1[7:0];
//CCR: no change
end
`ALU_MOVEP_M2R_2: begin
if(ir[6] == 1'b1) result[23:16] <= operand1[7:0];
else result[7:0] <= operand1[7:0];
//CCR: no change
end
`ALU_MOVEP_M2R_3: begin
if(ir[6] == 1'b1) result[15:8] <= operand1[7:0];
//CCR: no change
end
`ALU_MOVEP_M2R_4: begin
if(ir[6] == 1'b1) result[7:0] <= operand1[7:0];
//CCR: no change
end
`ALU_MOVEP_R2M_1: begin
if(ir[6] == 1'b1) result[7:0] <= operand1[31:24];
else result[7:0] <= operand1[15:8];
// CCR: no change
end
`ALU_MOVEP_R2M_2: begin
if(ir[6] == 1'b1) result[7:0] <= operand1[23:16];
else result[7:0] <= operand1[7:0];
// CCR: no change
end
`ALU_MOVEP_R2M_3: begin
result[7:0] <= operand1[15:8];
// CCR: no change
end
`ALU_MOVEP_R2M_4: begin
result[7:0] <= operand1[7:0];
// CCR: no change
end
`ALU_SIGN_EXTEND: begin
// move operand1 with sign-extension to result
if(size[1] == 1'b1) begin
result <= { {16{operand1[15]}}, operand1[15:0] };
end
else begin
result <= operand1;
end
// CCR: no change
end
`ALU_ARITHMETIC_LOGIC: begin
result <= result_blocking;
// Z
sr[2] <= `Z;
// N
sr[3] <= `Rm;
// CMPI,CMPM,CMP
if(decoder_alu_reg[5]) begin
// C,V
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
// X not affected
end
// ADDI,ADD to mem,ADD to Dn,ADDQ
else if(decoder_alu_reg[3]) begin
// C,X,V
sr[0] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm);
sr[4] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm); //=ccr[0];
sr[1] <= (`Sm & `Dm & ~`Rm) | (~`Sm & ~`Dm & `Rm);
end
// SUBI,SUB to mem,SUB to Dn,SUBQ
else if(decoder_alu_reg[4]) begin
// C,X,V
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
end
// ANDI,EORI,ORI,EOR,OR to mem,AND to mem,OR to Dn,AND to Dn
else begin
// C,V
sr[0] <= 1'b0;
sr[1] <= 1'b0;
// X not affected
end
end
`ALU_ABCD_SBCD_ADDX_SUBX_prepare: begin
result <= result_blocking;
end
`ALU_ABCD_SBCD_ADDX_SUBX: begin
// ABCD
if( ir[14:12] == 3'b100) begin
result <= result_ABCD2;
// C
sr[0] <= (result_ABCD2[19:14] > 6'd9) ? 1'b1 : 1'b0;
// X = C
sr[4] <= (result_ABCD2[19:14] > 6'd9) ? 1'b1 : 1'b0;
// V
sr[1] <= (result_ABCD2[30] == 1'b0 && result_ABCD2[7] == 1'b1) ? 1'b1 : 1'b0;
end
// SBCD
else if( ir[14:12] == 3'b000 ) begin
result <= result_SBCD2;
// C
sr[0] <= (result_SBCD2[19:14] < 6'd32) ? 1'b1 : 1'b0;
// X = C
sr[4] <= (result_SBCD2[19:14] < 6'd32) ? 1'b1 : 1'b0;
// V
sr[1] <= (result_SBCD2[30] == 1'b1 && result_SBCD2[7] == 1'b0) ? 1'b1 : 1'b0;
end
// ADDX
else if( ir[14:12] == 3'b101 ) begin
result <= result_blocking;
// C,X,V
sr[0] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm);
sr[4] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm); //=ccr[0];
sr[1] <= (`Sm & `Dm & ~`Rm) | (~`Sm & ~`Dm & `Rm);
end
// SUBX
else if( ir[14:12] == 3'b001 ) begin
result[31:0] <= result_blocking;
// C,X,V
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
end
// Z
sr[2] <= sr[2] & `Z;
// N
sr[3] <= `Rm;
end
`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare: begin
// 32-bit load even for 8-bit and 16-bit operations
// The extra bits will be anyway discarded during register / memory write
result[31:0] <= result_blocking;
// V cleared
sr[1] <= 1'b0;
// C for ROXL,ROXR: set to X
if(decoder_alu_reg[11] | decoder_alu_reg[15]) begin
sr[0] <= sr[4];
end
else begin
// C cleared
sr[0] <= 1'b0;
end
// N set
sr[3] <= `Rm;
// Z set
sr[2] <= `Z;
end
`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR: begin
// ASL / LSL / ROL / ROXL
if (decoder_alu_reg[8] | decoder_alu_reg[9] | decoder_alu_reg[10] | decoder_alu_reg[11]) begin
result[31:0] <= result_blocking;
sr[0] <= `Dm; // C for ASL / LSL / ROL / ROXL
if (decoder_alu_reg[8])
sr[1] <= (sr[1] == 1'b0)? (`Rm != `Dm) : 1'b1; // V for ASL
else
sr[1] <= 1'b0; // V for LSL / ROL / ROXL
if (!decoder_alu_reg[10]) sr[4] <= `Dm; // X for ASL / LSL / ROXL
end
// ASR / LSR / ROR / ROXR
else begin
result[31:0] <= result_blocking;
sr[0] <= operand1[0]; // C for ASR / LSR / ROR / ROXR
sr[1] <= 1'b0; // V for ASR / LSR / ROR / ROXR
if (!decoder_alu_reg[14]) sr[4] <= operand1[0]; // X for ASR / LSR / ROXR
end
// N set
sr[3] <= `Rm;
// Z set
sr[2] <= `Z;
end
`ALU_MOVE: begin
result <= result_blocking;
// X not affected
// C cleared
sr[0] <= 1'b0;
// V cleared
sr[1] <= 1'b0;
// N set
sr[3] <= `Rm;
// Z set
sr[2] <= `Z;
end
`ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ: begin
// ADDA: 1101
// CMPA: 1011
// SUBA: 1001
// ADDQ,SUBQ: 0101 xxx0,1
// operation requires that operand2 was sign extended
result[31:0] <= result_blocking;
// for CMPA
if( ir[15:12] == 4'b1011 ) begin
// Z
sr[2] <= `Z;
// N
sr[3] <= `Rm;
// C,V
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
// X not affected
end
// for ADDA,SUBA,ADDQ,SUBQ: ccr not affected
end
`ALU_CHK: begin
result <= result_blocking;
// undocumented behavior: Z flag, see 68knotes.txt
//sr[2] <= (operand1[15:0] == 16'b0) ? 1'b1 : 1'b0;
// undocumented behavior: C,V flags, see 68knotes.txt
//sr[0] <= 1'b0;
//sr[1] <= 1'b0;
// C,X,V
// sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
// sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];
// sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
// +: 0-1, 0-0=0, 1-1=0
// -: 0-0=1, 1-0, 1-1=1
// operand1 - operand2 > 0
if( operand1[15:0] != operand2[15:0] && ((~`Dm & `Sm) | (~`Dm & ~`Sm & ~`Rm) | (`Dm & `Sm & ~`Rm)) == 1'b1 ) begin
// clear N
sr[3] <= 1'b0;
alu_signal <= 1'b1;
end
// operand1 < 0
else if( operand1[15] == 1'b1 ) begin
// set N
sr[3] <= 1'b1;
alu_signal <= 1'b1;
end
// no trap
else begin
// N undefined: not affected
alu_signal <= 1'b0;
end
// X not affected
end
`ALU_MULS_MULU_DIVS_DIVU: begin
// division by 0
if(ir[15:12] == 4'b1000 && operand2[15:0] == 16'b0) begin
// X not affected
// C cleared
sr[0] <= 1'b0;
// V,Z,N undefined: cleared
sr[1] <= 1'b0;
sr[2] <= 1'b0;
sr[3] <= 1'b0;
// set trap
alu_signal <= 1'b1;
end
// division in idle state
else if(ir[15:12] == 4'b1000 && div_count == 5'd0) begin
alu_signal <= 1'b0;
end
// division overflow: divu, divs
else if(ir[15:12] == 4'b1000 && div_overflow == 1'b1) begin
// X not affected
// C cleared
sr[0] <= 1'b0;
// V set
sr[1] <= 1'b1;
// Z,N undefined: cleared and set
sr[2] <= 1'b0;
sr[3] <= 1'b1;
// set trap
alu_signal <= 1'b1;
end
// division
else if( ir[15:12] == 4'b1000 ) begin
result[31:0] <= {div_remainder, div_quotient};
// X not affected
// C cleared
sr[0] <= 1'b0;
// V cleared
sr[1] <= 1'b0;
// Z
sr[2] <= (div_quotient == 16'b0);
// N
sr[3] <= (div_quotient[15] == 1'b1);
// set trap
alu_signal <= 1'b0;
end
// multiplication
else if( ir[15:12] == 4'b1100 ) begin
result[31:0] <= mult_result[31:0];
// X not affected
// C cleared
sr[0] <= 1'b0;
// V cleared
sr[1] <= 1'b0;
// Z
sr[2] <= (mult_result[31:0] == 32'b0);
// N
sr[3] <= (mult_result[31] == 1'b1);
// set trap
alu_signal <= 1'b0;
end
end
`ALU_BCHG_BCLR_BSET_BTST: begin // 97 LE
// byte
if( ir[5:3] != 3'b000 ) begin
sr[2] <= result_BITS8_val;
result <= result_BITS8;
end
// long
else if( ir[5:3] == 3'b000 ) begin
sr[2] <= result_BITS32_val;
result <= result_BITS32;
end
// C,V,N,X not affected
end
`ALU_TAS: begin
result[7:0] <= { 1'b1, operand1[6:0] };
// X not affected
// C cleared
sr[0] <= 1'b0;
// V cleared
sr[1] <= 1'b0;
// N set
sr[3] <= (operand1[7] == 1'b1);
// Z set
sr[2] <= (operand1[7:0] == 8'b0);
end
`ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT: begin
// NEGX / CLR / NEG / NOT
// Optimization thanks to Frederic Requin
if ((ir[11:8] == 4'b0000) || (ir[11:8] == 4'b0010) || (ir[11:8] == 4'b0100) || (ir[11:8] == 4'b0110))
result <= result_blocking;
// NBCD
else if( ir[11:6] == 6'b1000_00 ) begin
result <= result_blocking;
//V undefined: unchanged
//Z
sr[2] <= sr[2] & `Z;
//C,X
sr[0] <= (operand1[7:0] == 8'd0 && sr[4] == 1'b0) ? 1'b0 : 1'b1;
sr[4] <= (operand1[7:0] == 8'd0 && sr[4] == 1'b0) ? 1'b0 : 1'b1; //=C
end
// SWAP
else if( ir[11:6] == 6'b1000_01 ) result <= result_blocking;
// EXT byte to word
else if( ir[11:6] == 6'b1000_10 ) result <= result_blocking;
// EXT word to long
else if( ir[11:6] == 6'b1000_11 ) result <= result_blocking;
// N set if negative else clear
sr[3] <= `Rm;
// CLR,NOT,SWAP,EXT
if( ir[11:8] == 4'b0010 || ir[11:8] == 4'b0110 || ir[11:6] == 6'b1000_01 || ir[11:7] == 5'b1000_1 ) begin
// X not affected
// C,V cleared
sr[0] <= 1'b0;
sr[1] <= 1'b0;
// Z set
sr[2] <= `Z;
end
// NEGX
else if( ir[11:8] == 4'b0000 ) begin
// C set if borrow
sr[0] <= `Dm | `Rm;
// X=C
sr[4] <= `Dm | `Rm;
// V set if overflow
sr[1] <= `Dm & `Rm;
// Z cleared if nonzero else unchanged
sr[2] <= sr[2] & `Z;
end
// NEG
else if( ir[11:8] == 4'b0100 ) begin
// C clear if zero else set
sr[0] <= `Dm | `Rm;
// X=C
sr[4] <= `Dm | `Rm;
// V set if overflow
sr[1] <= `Dm & `Rm;
// Z set if zero else clear
sr[2] <= `Z;
end
end
`ALU_SIMPLE_LONG_ADD: begin
result <= operand1[31:0] + operand2[31:0];
// CCR not affected
end
`ALU_SIMPLE_LONG_SUB: begin
result <= operand1[31:0] - operand2[31:0];
// CCR not affected
end
`ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR: begin
// MOVE TO SR,RTE,STOP,ORI to SR,ANDI to SR,EORI to SR
if(decoder_alu_reg[16]) sr <= { operand1[15], 1'b0, operand1[13], 2'b0, operand1[10:8], 3'b0, operand1[4:0] };
// MOVE TO CCR,RTR,ORI to CCR,ANDI to CCR,EORI to CCR
else sr <= { sr[15:8], 3'b0, operand1[4:0] };
end
`ALU_SIMPLE_MOVE: begin
result <= operand1;
// CCR not affected
end
`ALU_LINK_MOVE: begin
if(ir[3:0] == 3'b111) begin
result <= operand1 - 32'd4;
end
else begin
result <= operand1;
end
// CCR not affected
end
endcase
end
end
endmodule
/***********************************************************************************************************************
* Microcode branch
**********************************************************************************************************************/
/*! \brief Select the next microcode word to execute.
*
* The microcode_branch module is responsible for selecting the next microcode word to execute. This decision is based
* on the value of the current microcode word, the value of the interrupt privilege level, the state of the current
* bus cycle and other internal signals.
*
* The microcode_branch module implements a simple stack for the microcode addresses. This makes it possible to call
* subroutines inside the microcode.
*/
module microcode_branch(
input clock,
input reset_n,
input [4:0] movem_loop,
input [15:0] movem_reg,
input [31:0] operand2,
input alu_signal,
input alu_mult_div_ready,
input condition,
input [31:0] result,
input overflow,
input stop_flag,
input [15:0] ir,
input [7:0] decoder_trap,
input trace_flag,
input group_0_flag,
input [2:0] interrupt_mask,
input [8:0] load_ea,
input [8:0] perform_ea_read,
input [8:0] perform_ea_write,
input [8:0] save_ea,
input [8:0] decoder_micropc,
input prefetch_ir_valid_32,
input prefetch_ir_valid,
input jmp_address_trap,
input jmp_bus_trap,
input finished,
input [3:0] branch_control,
input [3:0] branch_offset,
output [8:0] micro_pc
);
reg [8:0] micro_pc_0 = 9'd0;
reg [8:0] micro_pc_1;
reg [8:0] micro_pc_2;
reg [8:0] micro_pc_3;
assign micro_pc =
(reset_n == 1'b0) ? 9'd0 :
(jmp_address_trap == 1'b1 || jmp_bus_trap == 1'b1) ? `MICROPC_ADDRESS_BUS_TRAP :
( (branch_control == `BRANCH_movem_loop && movem_loop == 5'b10000) ||
(branch_control == `BRANCH_movem_reg && movem_reg[0] == 0) ||
(branch_control == `BRANCH_operand2 && operand2[5:0] == 6'b0) ||
(branch_control == `BRANCH_alu_signal && alu_signal == 1'b0) ||
(branch_control == `BRANCH_alu_mult_div_ready && alu_mult_div_ready == 1'b1) ||
(branch_control == `BRANCH_condition_0 && condition == 1'b0) ||
(branch_control == `BRANCH_condition_1 && condition == 1'b1) ||
(branch_control == `BRANCH_result && result[15:0] == 16'hFFFF) ||
(branch_control == `BRANCH_V && overflow == 1'b0) ||
(branch_control == `BRANCH_movep_16 && ir[6] == 1'b0) ||
(branch_control == `BRANCH_stop_flag_wait_ir_decode && stop_flag == 1'b1) ||
(branch_control == `BRANCH_ir && ir[7:0] != 8'b0) ||
(branch_control == `BRANCH_trace_flag_and_interrupt && trace_flag == 1'b0 && interrupt_mask != 3'b000) ||
(branch_control == `BRANCH_group_0_flag && group_0_flag == 1'b0)
) ? micro_pc_0 + { 5'd0, branch_offset } :
(branch_control == `BRANCH_stop_flag_wait_ir_decode && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0) ? decoder_micropc :
(branch_control == `BRANCH_trace_flag_and_interrupt && trace_flag == 1'b0 && interrupt_mask == 3'b000) ? `MICROPC_MAIN_LOOP :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_jump_to_main_loop) ? `MICROPC_MAIN_LOOP :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_load_ea && load_ea != 9'd0) ? load_ea :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_perform_ea_read) ? perform_ea_read :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_perform_ea_write) ? perform_ea_write :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_save_ea && save_ea != 9'd0) ? save_ea :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_read && load_ea != 9'd0) ? load_ea :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_read && load_ea == 9'd0) ? perform_ea_read :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_write) ? perform_ea_write :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_trap) ? `MICROPC_TRAP_ENTRY :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_return) ? micro_pc_1 :
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_interrupt_mask && interrupt_mask == 3'b000) ? `MICROPC_MAIN_LOOP :
( (branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_wait_finished && finished == 1'b0) ||
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_wait_prefetch_valid && prefetch_ir_valid == 1'b0) ||
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_wait_prefetch_valid_32 && prefetch_ir_valid_32 == 1'b0) ||
(branch_control == `BRANCH_stop_flag_wait_ir_decode && prefetch_ir_valid == 1'b0)
) ? micro_pc_0 :
micro_pc_0 + 9'd1
;
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) micro_pc_0 <= 9'd0;
else micro_pc_0 <= micro_pc;
end
always @(posedge clock or negedge reset_n) begin
if(reset_n == 1'b0) begin
micro_pc_1 <= 9'd0;
micro_pc_2 <= 9'd0;
micro_pc_3 <= 9'd0;
end
else if(branch_control == `BRANCH_stop_flag_wait_ir_decode && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0)
begin
micro_pc_1 <= micro_pc_0 + { 5'd0, branch_offset };
micro_pc_2 <= micro_pc_1;
micro_pc_3 <= micro_pc_2;
end
else if(branch_control == `BRANCH_procedure) begin
if(branch_offset == `PROCEDURE_call_read && load_ea != 9'd0) begin
micro_pc_1 <= perform_ea_read;
micro_pc_2 <= micro_pc_0 + 9'd1;
micro_pc_3 <= micro_pc_1;
end
else if(branch_offset == `PROCEDURE_call_read && load_ea == 9'd0) begin
micro_pc_1 <= micro_pc_0 + 9'd1;
micro_pc_2 <= micro_pc_1;
micro_pc_3 <= micro_pc_2;
end
else if(branch_offset == `PROCEDURE_call_write && save_ea != 9'd0) begin
micro_pc_1 <= save_ea;
micro_pc_2 <= micro_pc_1;
micro_pc_3 <= micro_pc_2;
end
else if((branch_offset == `PROCEDURE_call_load_ea && load_ea != 9'd0) ||
(branch_offset == `PROCEDURE_call_perform_ea_read) ||
(branch_offset == `PROCEDURE_call_perform_ea_write) ||
(branch_offset == `PROCEDURE_call_save_ea && save_ea != 9'd0) ||
(branch_offset == `PROCEDURE_call_trap) )
begin
micro_pc_1 <= micro_pc_0 + 9'd1;
micro_pc_2 <= micro_pc_1;
micro_pc_3 <= micro_pc_2;
end
else if(branch_offset == `PROCEDURE_return) begin
micro_pc_1 <= micro_pc_2;
micro_pc_2 <= micro_pc_3;
micro_pc_3 <= 9'd0;
end
else if(branch_offset == `PROCEDURE_push_micropc) begin
micro_pc_1 <= micro_pc_0;
micro_pc_2 <= micro_pc_1;
micro_pc_3 <= micro_pc_2;
end
else if(branch_offset == `PROCEDURE_pop_micropc) begin
micro_pc_1 <= micro_pc_2;
micro_pc_2 <= micro_pc_3;
micro_pc_3 <= 9'd0;
end
end
end
endmodule
|
/*
* Copyright (c) 2002 Richard M. Myers
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`timescale 10 ns/ 10 ns
module top ;
reg clk ;
reg [11:0] x_os_integ, y_os_integ;
reg [5:0] x_os, y_os;
initial
begin
//$dumpfile("show_math.vcd");
//$dumpvars(1, top);
clk = 1'h0 ;
x_os = 6'h01;
y_os = 6'h3f;
x_os_integ = 12'h000;
y_os_integ = 12'h000;
end
initial
begin
#60;
forever #3 clk = ~clk ; // 16Mhz
end
always @( posedge clk )
begin
// Integration period set above depending on configured modem speed.
x_os_integ <= x_os_integ + {{6{x_os[5]}}, {x_os[5:0]}};
y_os_integ <= y_os_integ + {{6{y_os[5]}}, {y_os[5:0]}};
$display ("%x %x", x_os_integ, y_os_integ);
end
initial
begin
#200 $finish ;
end
endmodule
|
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
localparam rep = 1<<(4-WIDTH);
wire [3:0] I;
generate
if(WIDTH == 1) begin
assign I = {1'b0, 1'b0, 1'b0, A[0]};
end else if(WIDTH == 2) begin
assign I = {1'b0, 1'b0, A[1], A[0]};
end else if(WIDTH == 3) begin
assign I = {1'b0, A[2], A[1], A[0]};
end else if(WIDTH == 4) begin
assign I = {A[3], A[2], A[1], A[0]};
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y));
endmodule
// DFFs
module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
// IO- "$__" cells for the iopadmap pass.
module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(1'b0)); endmodule
module \$__FACADE_INPAD (input I, output O); FACADE_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.PAD(I), .O(O)); endmodule
module \$__FACADE_TOUTPAD (input I, T, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(T)); endmodule
module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(T)); endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND3B_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_BLACKBOX_V
|
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