text
stringlengths 992
1.04M
|
|---|
module Mux2(select,data_i00,data_i01,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
output reg [(Size) - ('b1):0] data_o;
always @ (select or data_i00 or data_i01) begin
case (select)
'b0:data_o = data_i00;
'b1:data_o = data_i01;
endcase // case (select)
end
endmodule // Mux2
module Mux4(select,data_i00,data_i01,data_i02,data_i03,data_o);
parameter Size = 8;
input wire [('d2) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03) begin
case (select)
'b00: data_o = data_i00;
'b01: data_o = data_i01;
'b10: data_o = data_i02;
'b11: data_o = data_i03;
endcase
end
endmodule // Mux4
module Mux8(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_o);
parameter Size = 8;
input wire [('d3) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07) begin
case (select)
'b000: data_o = data_i00;
'b001: data_o = data_i01;
'b010: data_o = data_i02;
'b011: data_o = data_i03;
'b100: data_o = data_i04;
'b101: data_o = data_i05;
'b110: data_o = data_i06;
'b111: data_o = data_i07;
endcase
end
endmodule // Mux8
module Mux16(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_o);
parameter Size = 8;
input wire [('d4) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15) begin
case (select)
'b0000: data_o = data_i00;
'b0001: data_o = data_i01;
'b0010: data_o = data_i02;
'b0011: data_o = data_i03;
'b0100: data_o = data_i04;
'b0101: data_o = data_i05;
'b0110: data_o = data_i06;
'b0111: data_o = data_i07;
'b1000: data_o = data_i08;
'b1001: data_o = data_i09;
'b1010: data_o = data_i10;
'b1011: data_o = data_i11;
'b1100: data_o = data_i12;
'b1101: data_o = data_i13;
'b1110: data_o = data_i14;
'b1111: data_o = data_i15;
endcase
end
endmodule // Mux16
module Mux32(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_i16,data_i17,data_i18,data_i19,data_i20,data_i21,data_i22,data_i23,data_i24,data_i25,data_i26,data_i27,data_i28,data_i29,data_i30,data_i31,data_o);
parameter Size = 8;
input wire [('d5) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
input wire [(Size) - ('b1):0] data_i16;
input wire [(Size) - ('b1):0] data_i17;
input wire [(Size) - ('b1):0] data_i18;
input wire [(Size) - ('b1):0] data_i19;
input wire [(Size) - ('b1):0] data_i20;
input wire [(Size) - ('b1):0] data_i21;
input wire [(Size) - ('b1):0] data_i22;
input wire [(Size) - ('b1):0] data_i23;
input wire [(Size) - ('b1):0] data_i24;
input wire [(Size) - ('b1):0] data_i25;
input wire [(Size) - ('b1):0] data_i26;
input wire [(Size) - ('b1):0] data_i27;
input wire [(Size) - ('b1):0] data_i28;
input wire [(Size) - ('b1):0] data_i29;
input wire [(Size) - ('b1):0] data_i30;
input wire [(Size) - ('b1):0] data_i31;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15 or
data_i16 or data_i17 or data_i18 or data_i19 or data_i20 or data_i21 or data_i22 or data_i23 or
data_i24 or data_i25 or data_i26 or data_i27 or data_i28 or data_i29 or data_i30 or data_i31) begin
case (select)
'b00000: data_o = data_i00;
'b00001: data_o = data_i01;
'b00010: data_o = data_i02;
'b00011: data_o = data_i03;
'b00100: data_o = data_i04;
'b00101: data_o = data_i05;
'b00110: data_o = data_i06;
'b00111: data_o = data_i07;
'b01000: data_o = data_i08;
'b01001: data_o = data_i09;
'b01010: data_o = data_i10;
'b01011: data_o = data_i11;
'b01100: data_o = data_i12;
'b01101: data_o = data_i13;
'b01110: data_o = data_i14;
'b01111: data_o = data_i15;
'b10000: data_o = data_i16;
'b10001: data_o = data_i17;
'b10010: data_o = data_i18;
'b10011: data_o = data_i19;
'b10100: data_o = data_i20;
'b10101: data_o = data_i21;
'b10110: data_o = data_i22;
'b10111: data_o = data_i23;
'b11000: data_o = data_i24;
'b11001: data_o = data_i25;
'b11010: data_o = data_i26;
'b11011: data_o = data_i27;
'b11100: data_o = data_i28;
'b11101: data_o = data_i29;
'b11110: data_o = data_i30;
'b11111: data_o = data_i31;
endcase
end
endmodule // Mux32
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
`define SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tapvpwrvgnd ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_FUNCTIONAL_V |
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_dcache.v
// Title : Data cache
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Support for user-selected resource usage when implementing
// : cache memory. Additional parameters must be defined when
// : invoking lm32_ram.v
// =============================================================================
`include "lm32_include.v"
`ifdef CFG_DCACHE_ENABLED
`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
`define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
`define LM32_DC_TMEM_ADDR_WIDTH addr_set_width
`define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0
`define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
`define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0
`define LM32_DC_TAGS_WIDTH (addr_tag_width+1)
`define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0
`define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1
`define LM32_DC_TAGS_VALID_RNG 0
`define LM32_DC_STATE_RNG 2:0
`define LM32_DC_STATE_FLUSH 3'b001
`define LM32_DC_STATE_CHECK 3'b010
`define LM32_DC_STATE_REFILL 3'b100
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_dcache (
// ----- Inputs -----
clk_i,
rst_i,
stall_a,
stall_x,
stall_m,
address_x,
address_m,
load_q_m,
store_q_m,
store_data,
store_byte_select,
refill_ready,
refill_data,
dflush,
`ifdef CFG_MMU_ENABLED
dtlb_miss_x,
`endif
// ----- Outputs -----
stall_request,
restart_request,
refill_request,
refill_address,
refilling,
load_data
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter associativity = 1; // Associativity of the cache (Number of ways)
parameter sets = 512; // Number of sets
parameter bytes_per_line = 16; // Number of bytes per cache line
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
localparam addr_offset_width = `CLOG2(bytes_per_line)-2;
localparam addr_set_width = `CLOG2(sets);
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
`ifdef CFG_MMU_ENABLED
localparam addr_tag_lsb = (addr_offset_msb+1);
`else
localparam addr_tag_lsb = (addr_set_msb+1);
`endif
localparam addr_tag_msb = `CLOG2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS);
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_a; // Stall A stage
input stall_x; // Stall X stage
input stall_m; // Stall M stage
input [`LM32_WORD_RNG] address_x; // X stage load/store address
input [`LM32_WORD_RNG] address_m; // M stage load/store address
input load_q_m; // Load instruction in M stage
input store_q_m; // Store instruction in M stage
input [`LM32_WORD_RNG] store_data; // Data to store
input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified
input refill_ready; // Indicates next word of refill data is ready
input [`LM32_WORD_RNG] refill_data; // Refill data
input dflush; // Indicates cache should be flushed
`ifdef CFG_MMU_ENABLED
input dtlb_miss_x; // Indicates if a DTLB miss has occured
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output stall_request; // Request pipeline be stalled because cache is busy
wire stall_request;
output restart_request; // Request to restart instruction that caused the cache miss
reg restart_request;
output refill_request; // Request a refill
reg refill_request;
output [`LM32_WORD_RNG] refill_address; // Address to refill from
reg [`LM32_WORD_RNG] refill_address;
output refilling; // Indicates if the cache is currently refilling
reg refilling;
output [`LM32_WORD_RNG] load_data; // Data read from cache
wire [`LM32_WORD_RNG] load_data;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire read_port_enable; // Cache memory read port clock enable
wire write_port_enable; // Cache memory write port clock enable
wire [0:associativity-1] way_tmem_we; // Tag memory write enable
wire [0:associativity-1] way_dmem_we; // Data memory write enable
wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory
wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
wire [0:associativity-1] way_valid; // Indicates which ways are valid
wire [0:associativity-1] way_match; // Indicates which ways matched
wire miss; // Indicates no ways matched
wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address
wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
wire flushing; // Indicates if cache is currently flushing
wire check; // Indicates if cache is currently checking for hits/misses
wire refill; // Indicates if cache is currently refilling
wire valid_store; // Indicates if there is a valid store instruction
reg [associativity-1:0] refill_way_select; // Which way should be refilled
reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled
wire last_refill; // Indicates when on last cycle of cache refill
reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
genvar i, j;
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
// Way data
if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
begin : data_memories
lm32_ram
#(
// ----- Parameters -------
.data_width (32),
.address_width (`LM32_DC_DMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
) way_0_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (dmem_read_address),
.enable_read (read_port_enable),
.write_address (dmem_write_address),
.enable_write (write_port_enable),
.write_enable (way_dmem_we[i]),
.write_data (dmem_write_data),
// ----- Outputs -------
.read_data (way_data[i])
);
end
else
begin
for (j = 0; j < 4; j = j + 1)
begin : byte_memories
lm32_ram
#(
// ----- Parameters -------
.data_width (8),
.address_width (`LM32_DC_DMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
) way_0_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (dmem_read_address),
.enable_read (read_port_enable),
.write_address (dmem_write_address),
.enable_write (write_port_enable),
.write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
.write_data (dmem_write_data[(j+1)*8-1:j*8]),
// ----- Outputs -------
.read_data (way_data[i][(j+1)*8-1:j*8])
);
end
end
// Way tags
lm32_ram
#(
// ----- Parameters -------
.data_width (`LM32_DC_TAGS_WIDTH),
.address_width (`LM32_DC_TMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
) way_0_tag_ram
(
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (tmem_read_address),
.enable_read (read_port_enable),
.write_address (tmem_write_address),
.enable_write (`TRUE),
.write_enable (way_tmem_we[i]),
.write_data (tmem_write_data),
// ----- Outputs -------
.read_data ({way_tag[i], way_valid[i]})
);
end
endgenerate
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
// Compute which ways in the cache match the address being read
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
end
endgenerate
// Select data from way that matched the address being read
generate
if (associativity == 1)
begin : data_1
assign load_data = way_data[0];
end
else if (associativity == 2)
begin : data_2
assign load_data = way_match[0] ? way_data[0] : way_data[1];
end
endgenerate
generate
if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
begin
// Select data to write to data memories
always @(*)
begin
if (refill == `TRUE)
dmem_write_data = refill_data;
else
begin
dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
end
end
end
else
begin
// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
always @(*)
begin
if (refill == `TRUE)
dmem_write_data = refill_data;
else
dmem_write_data = store_data;
end
end
endgenerate
// Compute address to use to index into the data memories
generate
if (bytes_per_line > 4)
assign dmem_write_address = (refill == `TRUE)
? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
: address_m[`LM32_DC_ADDR_IDX_RNG];
else
assign dmem_write_address = (refill == `TRUE)
? refill_address[`LM32_DC_ADDR_SET_RNG]
: address_m[`LM32_DC_ADDR_IDX_RNG];
endgenerate
assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
// Compute address to use to index into the tag memories
assign tmem_write_address = (flushing == `TRUE)
? flush_set
: refill_address[`LM32_DC_ADDR_SET_RNG];
assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
// Compute signal to indicate when we are on the last refill accesses
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
assign last_refill = `TRUE;
endgenerate
// Compute data and tag memory access enable
assign read_port_enable = (stall_x == `FALSE);
assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
// Determine when we have a valid store
assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
// Compute data and tag memory write enables
generate
if (associativity == 1)
begin : we_1
assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
end
else
begin : we_2
assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
end
endgenerate
// On the last refill cycle set the valid bit, for all other writes it should be cleared
assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
// Signals that indicate which state we are in
assign flushing = state[0];
assign check = state[1];
assign refill = state[2];
assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE)
`ifdef CFG_MMU_ENABLED
&& (~dtlb_miss_x)
`endif
;
assign stall_request = (check == `FALSE);
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
// Record way selected for replacement on a cache miss
generate
if (associativity >= 2)
begin : way_select
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
begin
if (refill_request == `TRUE)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
end
endgenerate
// Record whether we are currently refilling
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refilling <= `FALSE;
else
refilling <= refill;
end
// Instruction cache control FSM
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
state <= `LM32_DC_STATE_FLUSH;
flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
refill_request <= `FALSE;
refill_address <= {`LM32_WORD_WIDTH{1'bx}};
restart_request <= `FALSE;
end
else
begin
case (state)
// Flush the cache
`LM32_DC_STATE_FLUSH:
begin
if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
state <= `LM32_DC_STATE_CHECK;
flush_set <= flush_set - 1'b1;
end
// Check for cache misses
`LM32_DC_STATE_CHECK:
begin
if (stall_a == `FALSE)
restart_request <= `FALSE;
if (miss == `TRUE)
begin
refill_request <= `TRUE;
refill_address <= address_m;
state <= `LM32_DC_STATE_REFILL;
end
else if (dflush == `TRUE)
state <= `LM32_DC_STATE_FLUSH;
end
// Refill a cache line
`LM32_DC_STATE_REFILL:
begin
refill_request <= `FALSE;
if (refill_ready == `TRUE)
begin
if (last_refill == `TRUE)
begin
restart_request <= `TRUE;
state <= `LM32_DC_STATE_CHECK;
end
end
end
endcase
end
end
generate
if (bytes_per_line > 4)
begin
// Refill offset
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refill_offset <= {addr_offset_width{1'b0}};
else
begin
case (state)
// Check for cache misses
`LM32_DC_STATE_CHECK:
begin
if (miss == `TRUE)
refill_offset <= {addr_offset_width{1'b0}};
end
// Refill a cache line
`LM32_DC_STATE_REFILL:
begin
if (refill_ready == `TRUE)
refill_offset <= refill_offset + 1'b1;
end
endcase
end
end
end
endgenerate
endmodule
`endif
|
// Quartus Prime Verilog Template
// Single Port ROM
module sin_rom
(
input [7:0] addr,
input clk,
output reg [7:0] q
);
// Declare the ROM variable
reg [7:0] sine[255:0];
initial
begin
sine[0]<= 8'd127;
sine[1]<= 8'd130;
sine[2]<= 8'd133;
sine[3]<= 8'd136;
sine[4]<= 8'd139;
sine[5]<= 8'd143;
sine[6]<= 8'd146;
sine[7]<= 8'd149;
sine[8]<= 8'd152;
sine[9]<= 8'd155;
sine[10]<= 8'd158;
sine[11]<= 8'd161;
sine[12]<= 8'd164;
sine[13]<= 8'd167;
sine[14]<= 8'd170;
sine[15]<= 8'd173;
sine[16]<= 8'd176;
sine[17]<= 8'd178;
sine[18]<= 8'd181;
sine[19]<= 8'd184;
sine[20]<= 8'd187;
sine[21]<= 8'd190;
sine[22]<= 8'd192;
sine[23]<= 8'd195;
sine[24]<= 8'd198;
sine[25]<= 8'd200;
sine[26]<= 8'd203;
sine[27]<= 8'd205;
sine[28]<= 8'd208;
sine[29]<= 8'd210;
sine[30]<= 8'd212;
sine[31]<= 8'd215;
sine[32]<= 8'd217;
sine[33]<= 8'd219;
sine[34]<= 8'd221;
sine[35]<= 8'd223;
sine[36]<= 8'd225;
sine[37]<= 8'd227;
sine[38]<= 8'd229;
sine[39]<= 8'd231;
sine[40]<= 8'd233;
sine[41]<= 8'd234;
sine[42]<= 8'd236;
sine[43]<= 8'd238;
sine[44]<= 8'd239;
sine[45]<= 8'd240;
sine[46]<= 8'd242;
sine[47]<= 8'd243;
sine[48]<= 8'd244;
sine[49]<= 8'd245;
sine[50]<= 8'd247;
sine[51]<= 8'd248;
sine[52]<= 8'd249;
sine[53]<= 8'd249;
sine[54]<= 8'd250;
sine[55]<= 8'd251;
sine[56]<= 8'd252;
sine[57]<= 8'd252;
sine[58]<= 8'd253;
sine[59]<= 8'd253;
sine[60]<= 8'd253;
sine[61]<= 8'd254;
sine[62]<= 8'd254;
sine[63]<= 8'd254;
sine[64]<= 8'd254;
sine[65]<= 8'd254;
sine[66]<= 8'd254;
sine[67]<= 8'd254;
sine[68]<= 8'd253;
sine[69]<= 8'd253;
sine[70]<= 8'd253;
sine[71]<= 8'd252;
sine[72]<= 8'd252;
sine[73]<= 8'd251;
sine[74]<= 8'd250;
sine[75]<= 8'd249;
sine[76]<= 8'd249;
sine[77]<= 8'd248;
sine[78]<= 8'd247;
sine[79]<= 8'd245;
sine[80]<= 8'd244;
sine[81]<= 8'd243;
sine[82]<= 8'd242;
sine[83]<= 8'd240;
sine[84]<= 8'd239;
sine[85]<= 8'd238;
sine[86]<= 8'd236;
sine[87]<= 8'd234;
sine[88]<= 8'd233;
sine[89]<= 8'd231;
sine[90]<= 8'd229;
sine[91]<= 8'd227;
sine[92]<= 8'd225;
sine[93]<= 8'd223;
sine[94]<= 8'd221;
sine[95]<= 8'd219;
sine[96]<= 8'd217;
sine[97]<= 8'd215;
sine[98]<= 8'd212;
sine[99]<= 8'd210;
sine[100]<= 8'd208;
sine[101]<= 8'd205;
sine[102]<= 8'd203;
sine[103]<= 8'd200;
sine[104]<= 8'd198;
sine[105]<= 8'd195;
sine[106]<= 8'd192;
sine[107]<= 8'd190;
sine[108]<= 8'd187;
sine[109]<= 8'd184;
sine[110]<= 8'd181;
sine[111]<= 8'd178;
sine[112]<= 8'd176;
sine[113]<= 8'd173;
sine[114]<= 8'd170;
sine[115]<= 8'd167;
sine[116]<= 8'd164;
sine[117]<= 8'd161;
sine[118]<= 8'd158;
sine[119]<= 8'd155;
sine[120]<= 8'd152;
sine[121]<= 8'd149;
sine[122]<= 8'd146;
sine[123]<= 8'd143;
sine[124]<= 8'd139;
sine[125]<= 8'd136;
sine[126]<= 8'd133;
sine[127]<= 8'd130;
sine[128]<= 8'd127;
sine[129]<= 8'd124;
sine[130]<= 8'd121;
sine[131]<= 8'd118;
sine[132]<= 8'd115;
sine[133]<= 8'd111;
sine[134]<= 8'd108;
sine[135]<= 8'd105;
sine[136]<= 8'd102;
sine[137]<= 8'd99;
sine[138]<= 8'd96;
sine[139]<= 8'd93;
sine[140]<= 8'd90;
sine[141]<= 8'd87;
sine[142]<= 8'd84;
sine[143]<= 8'd81;
sine[144]<= 8'd78;
sine[145]<= 8'd76;
sine[146]<= 8'd73;
sine[147]<= 8'd70;
sine[148]<= 8'd67;
sine[149]<= 8'd64;
sine[150]<= 8'd62;
sine[151]<= 8'd59;
sine[152]<= 8'd56;
sine[153]<= 8'd54;
sine[154]<= 8'd51;
sine[155]<= 8'd49;
sine[156]<= 8'd46;
sine[157]<= 8'd44;
sine[158]<= 8'd42;
sine[159]<= 8'd39;
sine[160]<= 8'd37;
sine[161]<= 8'd35;
sine[162]<= 8'd33;
sine[163]<= 8'd31;
sine[164]<= 8'd29;
sine[165]<= 8'd27;
sine[166]<= 8'd25;
sine[167]<= 8'd23;
sine[168]<= 8'd21;
sine[169]<= 8'd20;
sine[170]<= 8'd18;
sine[171]<= 8'd16;
sine[172]<= 8'd15;
sine[173]<= 8'd14;
sine[174]<= 8'd12;
sine[175]<= 8'd11;
sine[176]<= 8'd10;
sine[177]<= 8'd9;
sine[178]<= 8'd7;
sine[179]<= 8'd6;
sine[180]<= 8'd5;
sine[181]<= 8'd5;
sine[182]<= 8'd4;
sine[183]<= 8'd3;
sine[184]<= 8'd2;
sine[185]<= 8'd2;
sine[186]<= 8'd1;
sine[187]<= 8'd1;
sine[188]<= 8'd1;
sine[189]<= 8'd0;
sine[190]<= 8'd0;
sine[191]<= 8'd0;
sine[192]<= 8'd0;
sine[193]<= 8'd0;
sine[194]<= 8'd0;
sine[195]<= 8'd0;
sine[196]<= 8'd1;
sine[197]<= 8'd1;
sine[198]<= 8'd1;
sine[199]<= 8'd2;
sine[200]<= 8'd2;
sine[201]<= 8'd3;
sine[202]<= 8'd4;
sine[203]<= 8'd5;
sine[204]<= 8'd5;
sine[205]<= 8'd6;
sine[206]<= 8'd7;
sine[207]<= 8'd9;
sine[208]<= 8'd10;
sine[209]<= 8'd11;
sine[210]<= 8'd12;
sine[211]<= 8'd14;
sine[212]<= 8'd15;
sine[213]<= 8'd16;
sine[214]<= 8'd18;
sine[215]<= 8'd20;
sine[216]<= 8'd21;
sine[217]<= 8'd23;
sine[218]<= 8'd25;
sine[219]<= 8'd27;
sine[220]<= 8'd29;
sine[221]<= 8'd31;
sine[222]<= 8'd33;
sine[223]<= 8'd35;
sine[224]<= 8'd37;
sine[225]<= 8'd39;
sine[226]<= 8'd42;
sine[227]<= 8'd44;
sine[228]<= 8'd46;
sine[229]<= 8'd49;
sine[230]<= 8'd51;
sine[231]<= 8'd54;
sine[232]<= 8'd56;
sine[233]<= 8'd59;
sine[234]<= 8'd62;
sine[235]<= 8'd64;
sine[236]<= 8'd67;
sine[237]<= 8'd70;
sine[238]<= 8'd73;
sine[239]<= 8'd76;
sine[240]<= 8'd78;
sine[241]<= 8'd81;
sine[242]<= 8'd84;
sine[243]<= 8'd87;
sine[244]<= 8'd90;
sine[245]<= 8'd93;
sine[246]<= 8'd96;
sine[247]<= 8'd99;
sine[248]<= 8'd102;
sine[249]<= 8'd105;
sine[250]<= 8'd108;
sine[251]<= 8'd111;
sine[252]<= 8'd115;
sine[253]<= 8'd118;
sine[254]<= 8'd121;
sine[255]<= 8'd124;
end
always @ (posedge clk)
begin
q <= sine[addr];
end
endmodule
|
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcierd_tl_cfg_sample.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This module extracts the configuration space register information from
// the multiplexed tl_cfg_ctl interface from the Hard IP core. And synchronizes
// this info, as well as the tl_cfg_sts info to the Application clock.
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_tl_cfg_sample #(
parameter HIP_SV = 0
)(
input pld_clk, // 125Mhz or 250Mhz
input rstn,
input [ 3: 0] tl_cfg_add, // from core_clk domain
input [ 31: 0] tl_cfg_ctl, // from core_clk domain
input tl_cfg_ctl_wr, // from core_clk domain
input [ 52: 0] tl_cfg_sts, // from core_clk domain
input tl_cfg_sts_wr, // from core_clk domain
output reg [ 12: 0] cfg_busdev, // synced to pld_clk
output reg [ 31: 0] cfg_devcsr, // synced to pld_clk
output reg [ 31: 0] cfg_linkcsr, // synced to pld_clk
output reg [31:0] cfg_prmcsr,
output reg [19:0] cfg_io_bas,
output reg [19:0] cfg_io_lim,
output reg [11:0] cfg_np_bas,
output reg [11:0] cfg_np_lim,
output reg [43:0] cfg_pr_bas,
output reg [43:0] cfg_pr_lim,
output reg [23:0] cfg_tcvcmap,
output reg [15:0] cfg_msicsr
);
reg tl_cfg_ctl_wr_r;
reg tl_cfg_ctl_wr_rr;
reg tl_cfg_ctl_wr_rrr;
reg tl_cfg_sts_wr_r;
reg tl_cfg_sts_wr_rr;
reg tl_cfg_sts_wr_rrr;
//Synchronise to pld side
always @(posedge pld_clk or negedge rstn) begin
if (rstn == 0) begin
tl_cfg_ctl_wr_r <= 0;
tl_cfg_ctl_wr_rr <= 0;
tl_cfg_ctl_wr_rrr <= 0;
tl_cfg_sts_wr_r <= 0;
tl_cfg_sts_wr_rr <= 0;
tl_cfg_sts_wr_rrr <= 0;
end
else begin
tl_cfg_ctl_wr_r <= tl_cfg_ctl_wr;
tl_cfg_ctl_wr_rr <= tl_cfg_ctl_wr_r;
tl_cfg_ctl_wr_rrr <= tl_cfg_ctl_wr_rr;
tl_cfg_sts_wr_r <= tl_cfg_sts_wr;
tl_cfg_sts_wr_rr <= tl_cfg_sts_wr_r;
tl_cfg_sts_wr_rrr <= tl_cfg_sts_wr_rr;
end
end
//Configuration Demux logic
always @(posedge pld_clk or negedge rstn) begin
if (rstn == 0) begin
cfg_busdev <= 16'h0;
cfg_devcsr <= 32'h0;
cfg_linkcsr <= 32'h0;
cfg_msicsr <= 16'h0;
cfg_tcvcmap <= 24'h0;
cfg_prmcsr <= 32'h0;
cfg_io_bas <= 20'h0;
cfg_io_lim <= 20'h0;
cfg_np_bas <= 12'h0;
cfg_np_lim <= 12'h0;
cfg_pr_bas <= 44'h0;
cfg_pr_lim <= 44'h0;
end
else begin
cfg_prmcsr[26:25] <= 2'h0;
cfg_prmcsr[23:16] <= 8'h0;
cfg_devcsr[31:20] <= 12'h0;
// tl_cfg_sts sampling
if ((tl_cfg_sts_wr_rrr != tl_cfg_sts_wr_rr) || (HIP_SV==1)) begin
cfg_devcsr[19 : 16] <= tl_cfg_sts[52 : 49];
cfg_linkcsr[31:16] <= tl_cfg_sts[46 : 31];
cfg_prmcsr[31:27] <= tl_cfg_sts[29:25];
cfg_prmcsr[24] <= tl_cfg_sts[24];
end
// tl_cfg_ctl_sampling
if ((tl_cfg_ctl_wr_rrr != tl_cfg_ctl_wr_rr) || (HIP_SV==1)) begin
if (tl_cfg_add==4'h0) cfg_devcsr[15:0] <= tl_cfg_ctl[31:16];
if (tl_cfg_add==4'h2) cfg_linkcsr[15:0] <= tl_cfg_ctl[31:16];
if (tl_cfg_add==4'h3) cfg_prmcsr[15:0] <= tl_cfg_ctl[23:8];
if (tl_cfg_add==4'h5) cfg_io_bas <= tl_cfg_ctl[19:0];
if (tl_cfg_add==4'h6) cfg_io_lim <= tl_cfg_ctl[19:0];
if (tl_cfg_add==4'h7) cfg_np_bas <= tl_cfg_ctl[23:12];
if (tl_cfg_add==4'h7) cfg_np_lim <= tl_cfg_ctl[11:0];
if (tl_cfg_add==4'h8) cfg_pr_bas[31:0] <= tl_cfg_ctl[31:0];
if (tl_cfg_add==4'h9) cfg_pr_bas[43:32] <= tl_cfg_ctl[11:0];
if (tl_cfg_add==4'hA) cfg_pr_lim[31:0] <= tl_cfg_ctl[31:0];
if (tl_cfg_add==4'hB) cfg_pr_lim[43:32] <= tl_cfg_ctl[11:0];
if (tl_cfg_add==4'hD) cfg_msicsr[15:0] <= tl_cfg_ctl[15:0];
if (tl_cfg_add==4'hE) cfg_tcvcmap[23:0] <= tl_cfg_ctl[23:0];
if (tl_cfg_add==4'hF) cfg_busdev <= tl_cfg_ctl[12:0];
end
end
end
endmodule
|
module wr_port_mux_8to1 (
wr_port_select,
port0_wr_en,
port0_wr_mask,
port0_wr_addr,
port0_wr_data,
port1_wr_en,
port1_wr_mask,
port1_wr_addr,
port1_wr_data,
port2_wr_en,
port2_wr_mask,
port2_wr_addr,
port2_wr_data,
port3_wr_en,
port3_wr_mask,
port3_wr_addr,
port3_wr_data,
port4_wr_en,
port4_wr_mask,
port4_wr_addr,
port4_wr_data,
port5_wr_en,
port5_wr_mask,
port5_wr_addr,
port5_wr_data,
port6_wr_en,
port6_wr_mask,
port6_wr_addr,
port6_wr_data,
port7_wr_en,
port7_wr_mask,
port7_wr_addr,
port7_wr_data,
muxed_port_wr_en,
muxed_port_wr_mask,
muxed_port_wr_addr,
muxed_port_wr_data
);
output muxed_port_wr_en;
output [63:0] muxed_port_wr_mask;
output [9:0] muxed_port_wr_addr;
output [2047:0] muxed_port_wr_data;
input [15:0] wr_port_select;
input port0_wr_en;
input [63:0] port0_wr_mask;
input [9:0] port0_wr_addr;
input [2047:0] port0_wr_data;
input port1_wr_en;
input [63:0] port1_wr_mask;
input [9:0] port1_wr_addr;
input [2047:0] port1_wr_data;
input port2_wr_en;
input [63:0] port2_wr_mask;
input [9:0] port2_wr_addr;
input [2047:0] port2_wr_data;
input port3_wr_en;
input [63:0] port3_wr_mask;
input [9:0] port3_wr_addr;
input [2047:0] port3_wr_data;
input port4_wr_en;
input [63:0] port4_wr_mask;
input [9:0] port4_wr_addr;
input [2047:0] port4_wr_data;
input port5_wr_en;
input [63:0] port5_wr_mask;
input [9:0] port5_wr_addr;
input [2047:0] port5_wr_data;
input port6_wr_en;
input [63:0] port6_wr_mask;
input [9:0] port6_wr_addr;
input [2047:0] port6_wr_data;
input port7_wr_en;
input [63:0] port7_wr_mask;
input [9:0] port7_wr_addr;
input [2047:0] port7_wr_data;
reg muxed_port_wr_en;
reg [63:0] muxed_port_wr_mask;
reg [9:0] muxed_port_wr_addr;
reg [2047:0] muxed_port_wr_data;
always @ (
wr_port_select or
port0_wr_en or
port0_wr_mask or
port0_wr_addr or
port0_wr_data or
port1_wr_en or
port1_wr_mask or
port1_wr_addr or
port1_wr_data or
port2_wr_en or
port2_wr_mask or
port2_wr_addr or
port2_wr_data or
port3_wr_en or
port3_wr_mask or
port3_wr_addr or
port3_wr_data or
port4_wr_en or
port4_wr_mask or
port4_wr_addr or
port4_wr_data or
port5_wr_en or
port5_wr_mask or
port5_wr_addr or
port5_wr_data or
port6_wr_en or
port6_wr_mask or
port6_wr_addr or
port6_wr_data or
port7_wr_en or
port7_wr_mask or
port7_wr_addr or
port7_wr_data
) begin
casex(wr_port_select)
16'h0001:
begin
muxed_port_wr_en <= port0_wr_en;
muxed_port_wr_mask <= port0_wr_mask & {64{port0_wr_en}};
muxed_port_wr_addr <= port0_wr_addr;
muxed_port_wr_data <= port0_wr_data;
end
16'h0002:
begin
muxed_port_wr_en <= port1_wr_en;
muxed_port_wr_mask <= port1_wr_mask & {64{port1_wr_en}};
muxed_port_wr_addr <= port1_wr_addr;
muxed_port_wr_data <= port1_wr_data;
end
16'h0004:
begin
muxed_port_wr_en <= port2_wr_en;
muxed_port_wr_mask <= port2_wr_mask & {64{port2_wr_en}};
muxed_port_wr_addr <= port2_wr_addr;
muxed_port_wr_data <= port2_wr_data;
end
16'h0008:
begin
muxed_port_wr_en <= port3_wr_en;
muxed_port_wr_mask <= port3_wr_mask & {64{port3_wr_en}};
muxed_port_wr_addr <= port3_wr_addr;
muxed_port_wr_data <= port3_wr_data;
end
16'h0010:
begin
muxed_port_wr_en <= port4_wr_en;
muxed_port_wr_mask <= port4_wr_mask & {64{port4_wr_en}};
muxed_port_wr_addr <= port4_wr_addr;
muxed_port_wr_data <= port4_wr_data;
end
16'h0020:
begin
muxed_port_wr_en <= port5_wr_en;
muxed_port_wr_mask <= port5_wr_mask & {64{port5_wr_en}};
muxed_port_wr_addr <= port5_wr_addr;
muxed_port_wr_data <= port5_wr_data;
end
16'h0040:
begin
muxed_port_wr_en <= port6_wr_en;
muxed_port_wr_mask <= port6_wr_mask & {64{port6_wr_en}};
muxed_port_wr_addr <= port6_wr_addr;
muxed_port_wr_data <= port6_wr_data;
end
16'h0080:
begin
muxed_port_wr_en <= port7_wr_en;
muxed_port_wr_mask <= port7_wr_mask & {64{port7_wr_en}};
muxed_port_wr_addr <= port7_wr_addr;
muxed_port_wr_data <= port7_wr_data;
end
16'b0000:
begin
muxed_port_wr_en <= 1'b0;
muxed_port_wr_mask <= 64'b0;
muxed_port_wr_addr <= {10{1'bx}};
muxed_port_wr_data <= {2048{1'bx}};
end
default:
begin
muxed_port_wr_en <= 1'bx;
muxed_port_wr_mask <= {64{1'bx}};
muxed_port_wr_addr <= {10{1'bx}};
muxed_port_wr_data <= {2048{1'bx}};
end
endcase
end
endmodule
|
module s400 (
TEST,
FM,
blif_clk_net,
CLR,
blif_reset_net,
YLW1,
RED2,
GRN1,
RED1,
YLW2,
GRN2);
// Start PIs
input TEST;
input FM;
input blif_clk_net;
input CLR;
input blif_reset_net;
// Start POs
output YLW1;
output RED2;
output GRN1;
output RED1;
output YLW2;
output GRN2;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_179;
wire GRN1;
wire net_176;
wire net_159;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire net_117;
wire net_12;
wire net_151;
wire net_74;
wire net_53;
wire net_93;
wire net_210;
wire net_205;
wire net_168;
wire net_135;
wire net_130;
wire net_147;
wire net_127;
wire net_14;
wire net_113;
wire net_26;
wire net_76;
wire blif_clk_net;
wire net_101;
wire net_32;
wire net_187;
wire net_111;
wire net_90;
wire net_40;
wire net_100;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire CLR;
wire net_141;
wire net_160;
wire net_83;
wire net_115;
wire RED1;
wire net_4;
wire net_95;
wire net_17;
wire net_173;
wire net_78;
wire net_27;
wire net_164;
wire net_56;
wire net_87;
wire net_0;
wire net_155;
wire net_35;
wire net_191;
wire net_16;
wire net_22;
wire net_181;
wire net_193;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire net_120;
wire net_201;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_162;
wire YLW1;
wire FM;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire net_207;
wire net_199;
wire net_136;
wire net_134;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire net_185;
wire net_34;
wire net_108;
wire net_183;
wire TEST;
wire net_178;
wire net_208;
wire net_150;
wire net_63;
wire net_212;
wire net_152;
wire net_30;
wire net_116;
wire net_189;
wire net_175;
wire net_91;
wire net_24;
wire net_55;
wire net_99;
wire net_106;
wire net_186;
wire net_46;
wire net_140;
wire net_118;
wire net_148;
wire net_104;
wire net_146;
wire net_72;
wire net_122;
wire net_25;
wire net_7;
wire net_70;
wire net_194;
wire net_172;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire net_138;
wire net_13;
wire net_184;
wire net_94;
wire net_11;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire net_196;
wire net_170;
wire net_29;
wire net_68;
wire net_214;
wire net_149;
wire net_142;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_158;
wire net_15;
wire net_41;
wire net_57;
wire net_198;
wire net_71;
wire net_209;
wire net_153;
wire net_156;
wire net_3;
wire net_84;
wire net_174;
wire net_154;
wire net_1;
wire net_92;
wire net_112;
wire net_103;
wire net_213;
wire net_139;
wire net_43;
wire YLW2;
wire net_10;
wire net_180;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_171;
wire net_79;
wire net_143;
wire net_97;
wire net_190;
wire net_88;
wire net_182;
wire net_192;
wire net_145;
wire net_60;
wire net_197;
wire net_204;
wire net_81;
wire RED2;
wire net_163;
wire net_58;
wire GRN2;
wire net_67;
wire net_82;
wire net_64;
wire net_202;
wire net_37;
wire net_188;
wire net_110;
wire net_121;
wire net_73;
wire net_200;
wire net_48;
wire net_33;
wire net_177;
wire net_8;
wire net_75;
wire net_86;
wire net_211;
wire net_133;
wire net_206;
wire net_203;
wire net_195;
wire net_125;
// Start cells
AND4_X4 inst_145 ( .ZN(net_86), .A1(net_80), .A4(net_73), .A2(net_47), .A3(net_37) );
INV_X2 inst_103 ( .A(net_136), .ZN(net_135) );
DFFR_X2 inst_125 ( .RN(net_118), .D(net_43), .QN(net_6), .CK(net_209) );
CLKBUF_X2 inst_207 ( .A(net_172), .Z(net_201) );
DFFR_X1 inst_138 ( .RN(net_118), .D(net_97), .QN(RED2), .CK(net_177) );
CLKBUF_X2 inst_159 ( .A(net_152), .Z(net_153) );
CLKBUF_X2 inst_218 ( .A(net_211), .Z(net_212) );
NOR3_X2 inst_15 ( .A1(net_132), .A2(net_112), .ZN(net_75), .A3(net_54) );
CLKBUF_X2 inst_197 ( .A(net_190), .Z(net_191) );
DFFR_X1 inst_134 ( .RN(net_118), .D(net_72), .Q(YLW2), .CK(net_200) );
CLKBUF_X2 inst_179 ( .A(net_172), .Z(net_173) );
NOR2_X4 inst_24 ( .A1(net_130), .ZN(net_100), .A2(net_29) );
INV_X2 inst_114 ( .ZN(net_15), .A(net_10) );
XNOR2_X1 inst_6 ( .ZN(net_101), .A(net_100), .B(net_99) );
CLKBUF_X2 inst_194 ( .A(net_187), .Z(net_188) );
DFFR_X2 inst_131 ( .RN(net_118), .D(net_103), .QN(net_12), .CK(net_173) );
NAND2_X2 inst_76 ( .A1(net_141), .ZN(net_110), .A2(net_109) );
CLKBUF_X2 inst_214 ( .A(net_207), .Z(net_208) );
CLKBUF_X2 inst_180 ( .A(net_145), .Z(net_174) );
CLKBUF_X2 inst_160 ( .A(net_153), .Z(net_154) );
CLKBUF_X2 inst_150 ( .A(blif_clk_net), .Z(net_144) );
NOR2_X2 inst_33 ( .A1(net_126), .A2(net_76), .ZN(net_69) );
CLKBUF_X2 inst_172 ( .A(net_165), .Z(net_166) );
INV_X4 inst_83 ( .ZN(net_16), .A(net_0) );
NAND3_X2 inst_47 ( .ZN(net_102), .A1(net_100), .A2(net_99), .A3(net_66) );
NOR3_X2 inst_19 ( .ZN(net_105), .A3(net_104), .A1(net_90), .A2(net_83) );
INV_X1 inst_123 ( .ZN(net_118), .A(blif_reset_net) );
INV_X2 inst_121 ( .A(net_100), .ZN(net_93) );
XNOR2_X2 inst_2 ( .ZN(net_54), .A(net_53), .B(net_40) );
OR3_X2 inst_8 ( .A2(net_66), .ZN(net_50), .A1(net_49), .A3(net_48) );
INV_X2 inst_118 ( .ZN(net_33), .A(net_32) );
INV_X4 inst_86 ( .ZN(net_29), .A(net_16) );
CLKBUF_X2 inst_153 ( .A(net_145), .Z(net_147) );
NOR3_X2 inst_20 ( .ZN(net_106), .A3(net_104), .A1(net_94), .A2(net_89) );
NOR2_X2 inst_27 ( .ZN(net_80), .A1(net_2), .A2(CLR) );
NOR2_X2 inst_38 ( .A2(net_129), .ZN(net_92), .A1(net_56) );
INV_X4 inst_100 ( .ZN(net_112), .A(net_109) );
NAND2_X4 inst_52 ( .ZN(net_136), .A1(net_131), .A2(net_70) );
INV_X4 inst_90 ( .ZN(net_58), .A(net_19) );
DFFR_X1 inst_140 ( .RN(net_118), .D(net_107), .QN(net_9), .CK(net_160) );
CLKBUF_X2 inst_209 ( .A(net_202), .Z(net_203) );
CLKBUF_X2 inst_211 ( .A(net_189), .Z(net_205) );
NOR2_X1 inst_40 ( .A2(net_90), .ZN(net_89), .A1(net_88) );
CLKBUF_X2 inst_162 ( .A(net_155), .Z(net_156) );
CLKBUF_X2 inst_167 ( .A(net_155), .Z(net_161) );
INV_X4 inst_93 ( .ZN(net_99), .A(net_1) );
INV_X4 inst_81 ( .ZN(net_70), .A(net_12) );
INV_X4 inst_95 ( .A(net_57), .ZN(net_45) );
XNOR2_X2 inst_1 ( .A(net_51), .ZN(net_30), .B(FM) );
NAND2_X2 inst_72 ( .A2(net_128), .ZN(net_104), .A1(net_45) );
DFFR_X1 inst_139 ( .RN(net_118), .D(net_96), .QN(YLW1), .CK(net_146) );
CLKBUF_X2 inst_155 ( .A(net_148), .Z(net_149) );
NAND2_X2 inst_59 ( .ZN(net_48), .A1(net_16), .A2(net_1) );
DFFR_X1 inst_135 ( .RN(net_118), .D(net_79), .Q(RED1), .CK(net_193) );
CLKBUF_X2 inst_196 ( .A(net_189), .Z(net_190) );
NAND3_X2 inst_44 ( .A3(net_80), .A2(net_58), .A1(net_51), .ZN(net_41) );
NAND2_X4 inst_55 ( .A1(net_125), .ZN(net_98), .A2(net_28) );
CLKBUF_X2 inst_174 ( .A(net_167), .Z(net_168) );
INV_X2 inst_115 ( .ZN(net_88), .A(net_10) );
NOR2_X2 inst_37 ( .A1(net_130), .ZN(net_125), .A2(net_1) );
CLKBUF_X2 inst_210 ( .A(net_203), .Z(net_204) );
AND2_X2 inst_148 ( .ZN(net_53), .A2(net_34), .A1(net_26) );
CLKBUF_X2 inst_164 ( .A(net_157), .Z(net_158) );
CLKBUF_X2 inst_191 ( .A(net_184), .Z(net_185) );
XNOR2_X2 inst_5 ( .ZN(net_108), .A(net_102), .B(net_58) );
CLKBUF_X2 inst_157 ( .A(net_150), .Z(net_151) );
INV_X4 inst_84 ( .ZN(net_66), .A(net_2) );
NAND2_X4 inst_51 ( .A2(net_140), .ZN(net_137), .A1(net_131) );
DFFR_X1 inst_142 ( .RN(net_118), .D(net_114), .QN(net_0), .CK(net_154) );
INV_X4 inst_80 ( .ZN(net_49), .A(net_5) );
CLKBUF_X2 inst_173 ( .A(net_166), .Z(net_167) );
INV_X2 inst_105 ( .A(net_133), .ZN(net_132) );
CLKBUF_X2 inst_213 ( .A(net_206), .Z(net_207) );
NAND2_X2 inst_68 ( .ZN(net_84), .A1(net_81), .A2(net_67) );
CLKBUF_X2 inst_216 ( .A(net_195), .Z(net_210) );
INV_X4 inst_78 ( .ZN(net_87), .A(net_9) );
NAND4_X2 inst_42 ( .A1(net_66), .ZN(net_63), .A4(net_62), .A2(net_51), .A3(net_17) );
CLKBUF_X2 inst_175 ( .A(net_168), .Z(net_169) );
NAND2_X4 inst_53 ( .A2(net_137), .A1(net_136), .ZN(net_119) );
CLKBUF_X2 inst_205 ( .A(net_156), .Z(net_199) );
CLKBUF_X2 inst_177 ( .A(net_170), .Z(net_171) );
CLKBUF_X2 inst_183 ( .A(net_176), .Z(net_177) );
DFFR_X2 inst_133 ( .RN(net_118), .D(net_106), .QN(net_10), .CK(net_164) );
NOR2_X2 inst_26 ( .ZN(net_81), .A1(net_5), .A2(CLR) );
CLKBUF_X2 inst_151 ( .A(net_144), .Z(net_145) );
INV_X2 inst_112 ( .ZN(net_13), .A(net_11) );
NAND2_X2 inst_64 ( .ZN(net_55), .A2(net_41), .A1(net_39) );
INV_X2 inst_107 ( .A(net_129), .ZN(net_128) );
NAND2_X2 inst_67 ( .ZN(net_73), .A2(net_65), .A1(net_49) );
CLKBUF_X2 inst_181 ( .A(net_165), .Z(net_175) );
DFFR_X2 inst_127 ( .RN(net_118), .D(net_78), .QN(net_8), .CK(net_198) );
NAND2_X2 inst_70 ( .ZN(net_91), .A2(net_84), .A1(net_63) );
CLKBUF_X2 inst_186 ( .A(net_179), .Z(net_180) );
DFFR_X2 inst_129 ( .QN(net_124), .RN(net_118), .D(net_77), .CK(net_196) );
INV_X4 inst_92 ( .A(net_29), .ZN(net_28) );
NOR2_X2 inst_29 ( .A2(net_34), .ZN(net_27), .A1(net_26) );
CLKBUF_X2 inst_189 ( .A(net_182), .Z(net_183) );
NOR3_X2 inst_17 ( .ZN(net_78), .A3(net_76), .A1(net_53), .A2(net_27) );
NOR3_X2 inst_11 ( .ZN(net_64), .A1(net_51), .A3(net_48), .A2(net_19) );
AND3_X2 inst_146 ( .A3(net_122), .ZN(net_114), .A1(net_111), .A2(net_109) );
CLKBUF_X2 inst_188 ( .A(net_167), .Z(net_182) );
NOR3_X2 inst_14 ( .ZN(net_72), .A3(net_60), .A1(net_33), .A2(net_21) );
CLKBUF_X2 inst_202 ( .A(net_195), .Z(net_196) );
CLKBUF_X2 inst_206 ( .A(net_199), .Z(net_200) );
CLKBUF_X2 inst_187 ( .A(net_180), .Z(net_181) );
INV_X1 inst_122 ( .ZN(net_26), .A(net_8) );
NOR2_X2 inst_31 ( .ZN(net_44), .A1(net_42), .A2(net_30) );
NOR2_X2 inst_25 ( .A2(net_127), .A1(net_124), .ZN(net_34) );
DFFR_X2 inst_126 ( .QN(net_127), .RN(net_118), .D(net_69), .CK(net_204) );
CLKBUF_X2 inst_158 ( .A(net_150), .Z(net_152) );
DFFR_X1 inst_141 ( .RN(net_118), .D(net_117), .QN(net_1), .CK(net_156) );
NAND2_X2 inst_62 ( .A2(net_133), .ZN(net_76), .A1(net_45) );
CLKBUF_X2 inst_200 ( .A(net_174), .Z(net_194) );
INV_X2 inst_110 ( .ZN(net_139), .A(net_125) );
NAND2_X2 inst_74 ( .ZN(net_96), .A1(net_95), .A2(net_85) );
NAND2_X2 inst_57 ( .ZN(net_140), .A2(net_11), .A1(net_10) );
NOR2_X2 inst_35 ( .A1(net_136), .ZN(net_90), .A2(net_11) );
INV_X4 inst_99 ( .A(net_66), .ZN(net_31) );
NAND3_X2 inst_48 ( .A2(net_139), .A1(net_138), .ZN(net_121), .A3(net_93) );
NAND2_X2 inst_69 ( .ZN(net_85), .A1(net_84), .A2(net_68) );
NAND3_X2 inst_46 ( .A2(net_109), .ZN(net_79), .A1(net_50), .A3(net_46) );
INV_X4 inst_82 ( .ZN(net_17), .A(CLR) );
DFFR_X1 inst_136 ( .RN(net_118), .D(net_82), .Q(GRN2), .CK(net_191) );
NOR2_X2 inst_30 ( .ZN(net_43), .A1(net_42), .A2(net_22) );
INV_X4 inst_102 ( .ZN(net_115), .A(net_111) );
INV_X2 inst_108 ( .ZN(net_143), .A(net_128) );
CLKBUF_X2 inst_165 ( .A(net_158), .Z(net_159) );
NOR2_X2 inst_32 ( .ZN(net_61), .A2(net_60), .A1(net_57) );
NOR3_X2 inst_22 ( .A1(net_115), .ZN(net_113), .A2(net_112), .A3(net_108) );
DFFR_X1 inst_144 ( .RN(net_118), .D(net_113), .QN(net_3), .CK(net_174) );
NOR2_X2 inst_34 ( .A2(net_131), .ZN(net_71), .A1(net_70) );
NOR3_X2 inst_12 ( .A2(net_58), .ZN(net_52), .A3(net_38), .A1(net_18) );
CLKBUF_X2 inst_195 ( .A(net_188), .Z(net_189) );
NAND2_X4 inst_56 ( .A1(net_121), .ZN(net_111), .A2(net_36) );
NAND2_X2 inst_71 ( .ZN(net_95), .A2(net_91), .A1(net_88) );
NOR3_X2 inst_21 ( .A3(net_143), .A1(net_142), .A2(net_112), .ZN(net_107) );
INV_X2 inst_104 ( .A(net_136), .ZN(net_134) );
NAND2_X2 inst_60 ( .A1(net_51), .ZN(net_37), .A2(net_36) );
CLKBUF_X2 inst_215 ( .A(net_208), .Z(net_209) );
CLKBUF_X2 inst_169 ( .A(net_162), .Z(net_163) );
CLKBUF_X2 inst_168 ( .A(net_161), .Z(net_162) );
INV_X4 inst_97 ( .ZN(net_35), .A(net_28) );
CLKBUF_X2 inst_161 ( .A(net_144), .Z(net_155) );
DFFR_X2 inst_124 ( .RN(net_118), .D(net_44), .QN(net_4), .CK(net_214) );
NOR3_X2 inst_18 ( .A1(net_134), .A3(net_104), .ZN(net_103), .A2(net_71) );
NOR3_X2 inst_16 ( .ZN(net_77), .A3(net_76), .A1(net_34), .A2(net_24) );
CLKBUF_X2 inst_208 ( .A(net_201), .Z(net_202) );
INV_X4 inst_88 ( .ZN(net_18), .A(net_17) );
CLKBUF_X2 inst_220 ( .A(net_213), .Z(net_214) );
XNOR2_X2 inst_3 ( .ZN(net_142), .A(net_94), .B(net_87) );
CLKBUF_X2 inst_156 ( .A(net_149), .Z(net_150) );
OR2_X4 inst_9 ( .ZN(net_60), .A1(net_35), .A2(net_1) );
INV_X2 inst_113 ( .ZN(net_14), .A(CLR) );
CLKBUF_X2 inst_170 ( .A(net_163), .Z(net_164) );
CLKBUF_X2 inst_198 ( .A(net_158), .Z(net_192) );
NAND2_X4 inst_50 ( .A1(net_133), .ZN(net_131), .A2(net_6) );
DFFR_X1 inst_137 ( .RN(net_118), .D(net_86), .Q(GRN1), .CK(net_181) );
CLKBUF_X2 inst_199 ( .A(net_192), .Z(net_193) );
NOR2_X1 inst_41 ( .ZN(net_122), .A2(net_100), .A1(net_92) );
DFFR_X2 inst_130 ( .RN(net_118), .D(net_91), .QN(net_5), .CK(net_186) );
INV_X4 inst_91 ( .A(net_58), .ZN(net_36) );
DFFR_X2 inst_132 ( .RN(net_118), .D(net_105), .QN(net_11), .CK(net_169) );
DFFR_X1 inst_143 ( .RN(net_118), .D(net_116), .QN(net_2), .CK(net_151) );
CLKBUF_X2 inst_176 ( .A(net_146), .Z(net_170) );
CLKBUF_X2 inst_152 ( .A(net_145), .Z(net_146) );
NAND2_X2 inst_58 ( .ZN(net_38), .A1(net_29), .A2(net_1) );
NOR2_X2 inst_36 ( .A2(net_135), .ZN(net_83), .A1(net_13) );
AND2_X4 inst_147 ( .ZN(net_32), .A2(net_14), .A1(net_2) );
INV_X4 inst_87 ( .ZN(net_57), .A(net_17) );
NAND2_X2 inst_61 ( .ZN(net_39), .A2(net_32), .A1(net_23) );
CLKBUF_X2 inst_203 ( .A(net_179), .Z(net_197) );
NAND3_X2 inst_45 ( .ZN(net_46), .A3(net_31), .A1(net_25), .A2(net_20) );
INV_X4 inst_96 ( .A(net_36), .ZN(net_25) );
CLKBUF_X2 inst_212 ( .A(net_205), .Z(net_206) );
INV_X4 inst_101 ( .ZN(net_62), .A(net_38) );
XOR2_X2 inst_0 ( .Z(net_22), .B(net_6), .A(TEST) );
CLKBUF_X2 inst_184 ( .A(net_174), .Z(net_178) );
NOR4_X2 inst_10 ( .ZN(net_82), .A1(net_81), .A3(net_80), .A2(net_61), .A4(net_59) );
XNOR2_X2 inst_4 ( .ZN(net_141), .A(net_98), .B(net_66) );
NAND2_X2 inst_65 ( .ZN(net_67), .A1(net_66), .A2(net_64) );
CLKBUF_X2 inst_178 ( .A(net_171), .Z(net_172) );
INV_X4 inst_89 ( .A(net_49), .ZN(net_20) );
NOR2_X2 inst_28 ( .A2(net_126), .A1(net_123), .ZN(net_24) );
INV_X2 inst_111 ( .A(net_124), .ZN(net_123) );
NAND2_X2 inst_66 ( .ZN(net_68), .A1(net_62), .A2(net_55) );
INV_X2 inst_117 ( .A(net_58), .ZN(net_23) );
INV_X4 inst_98 ( .A(net_109), .ZN(net_42) );
CLKBUF_X2 inst_190 ( .A(net_183), .Z(net_184) );
NAND2_X2 inst_63 ( .A2(net_62), .A1(net_51), .ZN(net_47) );
OR3_X4 inst_7 ( .A2(net_81), .A1(net_80), .ZN(net_74), .A3(net_52) );
CLKBUF_X2 inst_204 ( .A(net_162), .Z(net_198) );
CLKBUF_X2 inst_185 ( .A(net_178), .Z(net_179) );
CLKBUF_X2 inst_182 ( .A(net_175), .Z(net_176) );
NAND2_X4 inst_49 ( .ZN(net_133), .A1(net_120), .A2(net_40) );
INV_X2 inst_120 ( .ZN(net_65), .A(net_64) );
CLKBUF_X2 inst_154 ( .A(net_147), .Z(net_148) );
NOR3_X2 inst_13 ( .ZN(net_59), .A1(net_58), .A2(net_57), .A3(net_56) );
INV_X2 inst_119 ( .ZN(net_56), .A(net_35) );
NAND2_X2 inst_75 ( .ZN(net_97), .A2(net_95), .A1(net_74) );
CLKBUF_X2 inst_192 ( .A(net_185), .Z(net_186) );
CLKBUF_X2 inst_166 ( .A(net_159), .Z(net_160) );
INV_X2 inst_116 ( .ZN(net_21), .A(net_20) );
CLKBUF_X2 inst_163 ( .A(net_155), .Z(net_157) );
INV_X4 inst_85 ( .ZN(net_40), .A(net_7) );
NAND2_X4 inst_54 ( .ZN(net_130), .A1(net_119), .A2(net_87) );
INV_X4 inst_79 ( .ZN(net_19), .A(net_3) );
INV_X2 inst_109 ( .A(net_127), .ZN(net_126) );
INV_X2 inst_106 ( .A(net_130), .ZN(net_129) );
CLKBUF_X2 inst_219 ( .A(net_212), .Z(net_213) );
CLKBUF_X2 inst_201 ( .A(net_194), .Z(net_195) );
CLKBUF_X2 inst_193 ( .A(net_170), .Z(net_187) );
AND2_X2 inst_149 ( .ZN(net_94), .A2(net_90), .A1(net_15) );
NAND3_X2 inst_43 ( .A2(net_127), .A3(net_124), .ZN(net_120), .A1(net_8) );
NOR2_X2 inst_39 ( .ZN(net_116), .A2(net_115), .A1(net_110) );
DFFR_X2 inst_128 ( .RN(net_118), .D(net_75), .QN(net_7), .CK(net_197) );
NAND2_X2 inst_73 ( .ZN(net_138), .A1(net_129), .A2(net_66) );
CLKBUF_X2 inst_217 ( .A(net_210), .Z(net_211) );
NOR3_X2 inst_23 ( .ZN(net_117), .A1(net_115), .A2(net_112), .A3(net_101) );
CLKBUF_X2 inst_171 ( .A(net_163), .Z(net_165) );
INV_X4 inst_77 ( .ZN(net_51), .A(net_4) );
INV_X4 inst_94 ( .ZN(net_109), .A(net_57) );
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate defparam
module module_a (out0,in0);
input in0;
output [5:0] out0;
parameter [5:0] ident0 = 0;
parameter [5:0] ident1 = 5'h11;
reg [5:0] out0;
// Basic MUX switches on in0
always @ (in0)
begin
if(in0)
out0 = ident0;
else
out0 = ident1;
end
endmodule // module_a
module module_b (out0,out1,in0,in1);
input in0;
input in1;
output [5:0] out0;
output [5:0] out1;
module_a testmodA (.out0(out0),.in0(in0));
module_a testmodB (.out0(out1),.in0(in1));
endmodule // module_b
module main ();
reg in0,in1;
reg error;
wire [5:0] out0,out1;
defparam NameB.testmodA.ident0 = 5'h4;
defparam NameB.testmodB.ident0 = 5'h5;
defparam NameB.testmodB.ident1 = 5'h6;
module_b NameB (.out0(out0),.out1(out1),
.in0(in0),.in1(in1));
initial
begin
error = 0;
#1 ;
in0 = 0;
#1 ;
if(out0 != 5'h11)
begin
$display("FAILED - defparam3.5A - Defparam testmodA.ident0");
$display("out0 = %h",out0);
error = 1;
end
#1 ;
in0 = 1;
#1 ;
if(out0 != 5'h4)
begin
$display("FAILED - defparam3.5A - Defparam testmodA.ident0");
error = 1;
end
#1;
in1 = 0;
#1;
if(out0 != 5'h4) // Validate the 0 side didn't change!
begin
$display("FAILED - defparam3.5A - Defparam testmodA.ident0");
error = 1;
end
if(out1 != 5'h6)
begin
$display("FAILED - defparam3.5A - Defparam testmodB.ident1");
error = 1;
end
#1;
in1 = 1;
#1;
if(out1 != 5'h5)
begin
$display("FAILED - defparam3.5A - Defparam testmodB.ident0");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module timer (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
module PLLE2_BASE (/*AUTOARG*/
// Outputs
LOCKED, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5,
CLKFBOUT,
// Inputs
CLKIN1, RST, PWRDWN, CLKFBIN
);
parameter BANDWIDTH = 0;
parameter CLKFBOUT_MULT = 1;
parameter CLKFBOUT_PHASE = 0;
parameter CLKIN1_PERIOD = 10;
parameter DIVCLK_DIVIDE = 1;
parameter REF_JITTER1 = 0;
parameter STARTUP_WAIT = 0;
parameter CLKOUT0_DIVIDE = 1;
parameter CLKOUT0_DUTY_CYCLE = 0.5;
parameter CLKOUT0_PHASE = 0;
parameter CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 0.5;
parameter CLKOUT1_PHASE = 0;
parameter CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 0.5;
parameter CLKOUT2_PHASE = 0;
parameter CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 0.5;
parameter CLKOUT3_PHASE = 0;
parameter CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 0.5;
parameter CLKOUT4_PHASE = 0;
parameter CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 0.5;
parameter CLKOUT5_PHASE = 0;
//#LOCAL DERIVED PARAMETERS
parameter VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT;
parameter CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE * (CLKOUT0_PHASE/360);
parameter CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
parameter CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
parameter CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
parameter CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
parameter CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
//inputs
input CLKIN1;
input RST;
input PWRDWN;
input CLKFBIN;
//outputs
output LOCKED;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output CLKFBOUT;
//##############
//#VCO
//##############
reg vco_clk;
initial
begin
vco_clk = 1'b0;
end
always
#(VCO_PERIOD/2) vco_clk = ~vco_clk;
//##############
//#DIVIDERS
//##############
wire [3:0] DIVCFG[5:0];
wire [5:0] CLKOUT_DIV;
assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE);
assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
//ugly POR reset
reg POR;
initial
begin
POR=1'b1;
#1
POR=1'b0;
end
genvar i;
generate for(i=0; i<6; i=i+1)
begin : gen_clkdiv
clock_divider clkdiv (/*AUTOINST*/
// Outputs
.clkout (CLKOUT_DIV[i]),
// Inputs
.clkin (vco_clk),
.divcfg (DIVCFG[i]),
.reset (RST | POR)
);
end
endgenerate
//##############
//#PHASE DELAY
//##############
reg CLKOUT0;
reg CLKOUT1;
reg CLKOUT2;
reg CLKOUT3;
reg CLKOUT4;
reg CLKOUT5;
always @ (CLKOUT_DIV)
begin
CLKOUT0 <= #(CLK0_DELAY) CLKOUT_DIV[0];
CLKOUT1 <= #(CLK1_DELAY) CLKOUT_DIV[1];
CLKOUT2 <= #(CLK2_DELAY) CLKOUT_DIV[2];
CLKOUT3 <= #(CLK3_DELAY) CLKOUT_DIV[3];
CLKOUT4 <= #(CLK4_DELAY) CLKOUT_DIV[4];
CLKOUT5 <= #(CLK5_DELAY) CLKOUT_DIV[5];
end
//##############
//#DUMMY DRIVES
//##############
assign CLKFBOUT=CLKIN1;
assign LOCKED=1'b0;
endmodule // PLLE2_BASE
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/11/2016 02:09:05 PM
// Design Name:
// Module Name: Rotate_Mux_Array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Rotate_Mux_Array
#(parameter SWR=26)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
output wire [SWR-1:0] Data_o
);
genvar j;//Create a variable for the loop FOR
generate for (j=0; j <= SWR-1; j=j+1) begin // generate enough Multiplexers modules for each bit
case (j)
SWR-1-j:begin
assign Data_o[j]=Data_i[SWR-1-j];
end
default:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[SWR-1-j]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs_pma.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma.v,v $
//
// $Revision: #1 $
// $Date: 2010/04/12 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs_pma /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */ (
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
gxb_cal_blk_clk,
gxb_pwrdn_in,
magic_sleep_n,
mdio_in,
read,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
pcs_pwrdn_out,
readdata,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b1; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 ? LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output pcs_pwrdn_out;
output [31: 0] readdata;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input gxb_cal_blk_clk;
input gxb_pwrdn_in;
input magic_sleep_n;
input mdio_in;
input read;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
wire MAC_PCS_reset;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire led_an;
wire led_char_err;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire [5:0] rx_err;
wire [17: 0] rx_err_stat;
wire [3:0] rx_frm_type;
wire sd_loopback;
wire tbi_rx_clk;
wire [9:0] tbi_rx_d;
wire tbi_tx_clk;
wire [9:0] tbi_tx_d;
wire tx_ff_uflow;
wire txp;
wire waitrequest;
wire [9:0] tbi_rx_d_lvds;
reg pma_digital_rst0;
reg pma_digital_rst1;
reg pma_digital_rst2;
reg [9:0] tbi_rx_d_flip;
reg [9:0] tbi_tx_d_flip;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
always @(posedge clk or posedge reset)
begin
if (reset == 1)
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= reset;
pma_digital_rst2 <= reset;
end
else
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= pma_digital_rst0;
pma_digital_rst2 <= pma_digital_rst1;
end
end
// Assign the digital reset of the PMA to the MAC_PCS logic
// --------------------------------------------------------
assign MAC_PCS_reset = pma_digital_rst2;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_ena altera_tse_mac_pcs_pma_ena_inst
(
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err),
.led_col (led_col),
.led_crs (led_crs),
.led_disp_err (led_disp_err),
.led_link (led_link),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (MAC_PCS_reset),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frm_type (rx_frm_type),
.sd_loopback (sd_loopback),
.tbi_rx_clk (tbi_rx_clk),
.tbi_rx_d (tbi_rx_d),
.tbi_tx_clk (tbi_tx_clk),
.tbi_tx_d (tbi_tx_d),
.tx_ff_uflow (tx_ff_uflow),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1)
begin
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
end
endgenerate
// Either one of these blocks below will be instantiated depending on the parameterization
// that is chosen.
// ---------------------------------------------------------------------------------------
// Instantiation of the Alt2gxb block as the PMA for devices other than ArriaGX
// ----------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 0)
begin
altera_tse_alt2gxb_basic the_altera_tse_alt2gxb_basic
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.rx_analogreset (reset),
.rx_clkout (tbi_rx_clk),
.rx_cruclk (ref_clk),
.rx_datain (rxp),
.rx_dataout (tbi_rx_d),
.rx_digitalreset (pma_digital_rst2),
.rx_patterndetect (),
.rx_seriallpbken (sd_loopback),
.tx_clkout (tbi_tx_clk),
.tx_datain (tbi_tx_d),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2)
);
end
endgenerate
// Instantiation of the Alt2gxb block as the PMA for ArriaGX device
// ----------------------------------------------------------------
generate if (DEVICE_FAMILY == "ARRIAGX")
begin
altera_tse_alt2gxb_arriagx the_altera_tse_alt2gxb_arriagx
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.rx_analogreset (reset),
.rx_clkout (tbi_rx_clk),
.rx_cruclk (ref_clk),
.rx_datain (rxp),
.rx_dataout (tbi_rx_d),
.rx_digitalreset (pma_digital_rst2),
.rx_patterndetect (),
.rx_seriallpbken (sd_loopback),
.tx_clkout (tbi_tx_clk),
.tx_datain (tbi_tx_d),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2)
);
end
endgenerate
// Instantiation of the LVDS SERDES block as the PMA for Stratix III devices
//
// IEEE 802.3 Clause 36 PCS requires that bit 0 of TBI_DATA to be transmitted
// first. However, ALTLVDS had bit 9 transmit first. hence, we need a bit
// reversal algorithm.
// -------------------------------------------------------------------------
generate if (DEVICE_FAMILY != "ARRIAGX" && TRANSCEIVER_OPTION == 1)
begin
assign tbi_tx_clk = ref_clk;
assign tbi_rx_d = tbi_rx_d_flip;
always @(posedge tbi_rx_clk or posedge reset)
begin
if (reset == 1)
tbi_rx_d_flip <= 0;
else
begin
tbi_rx_d_flip[0] <= tbi_rx_d_lvds[9];
tbi_rx_d_flip[1] <= tbi_rx_d_lvds[8];
tbi_rx_d_flip[2] <= tbi_rx_d_lvds[7];
tbi_rx_d_flip[3] <= tbi_rx_d_lvds[6];
tbi_rx_d_flip[4] <= tbi_rx_d_lvds[5];
tbi_rx_d_flip[5] <= tbi_rx_d_lvds[4];
tbi_rx_d_flip[6] <= tbi_rx_d_lvds[3];
tbi_rx_d_flip[7] <= tbi_rx_d_lvds[2];
tbi_rx_d_flip[8] <= tbi_rx_d_lvds[1];
tbi_rx_d_flip[9] <= tbi_rx_d_lvds[0];
end
end
always @(posedge ref_clk or posedge reset)
begin
if (reset == 1)
tbi_tx_d_flip <= 0;
else
begin
tbi_tx_d_flip[0] <= tbi_tx_d[9];
tbi_tx_d_flip[1] <= tbi_tx_d[8];
tbi_tx_d_flip[2] <= tbi_tx_d[7];
tbi_tx_d_flip[3] <= tbi_tx_d[6];
tbi_tx_d_flip[4] <= tbi_tx_d[5];
tbi_tx_d_flip[5] <= tbi_tx_d[4];
tbi_tx_d_flip[6] <= tbi_tx_d[3];
tbi_tx_d_flip[7] <= tbi_tx_d[2];
tbi_tx_d_flip[8] <= tbi_tx_d[1];
tbi_tx_d_flip[9] <= tbi_tx_d[0];
end
end
altera_tse_pma_lvds_rx the_altera_tse_pma_lvds_rx
(
.rx_divfwdclk (tbi_rx_clk),
.rx_in (rxp),
.rx_inclock (ref_clk),
.rx_out (tbi_rx_d_lvds),
.rx_outclock (),
.rx_reset (reset)
);
altera_tse_pma_lvds_tx the_altera_tse_pma_lvds_tx
(
.tx_in (tbi_tx_d_flip),
.tx_inclock (ref_clk),
.tx_out (txp)
);
end
endgenerate
endmodule
|
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008-2008 by Wilson Snyder.
module autoinst_moddefine (/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire q; // From `SUBNAME_B of `SUBMOD_A.v, ...
// End of automatics
`define SUBMOD_A submod_mod
`define SUBNAME_B subname_b
`SUBMOD_A `SUBNAME_B
(/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a));
`SUBMOD_UNDEFED subundefed
(/*AUTOINST*/
// Outputs
.q (q));
submod_decl_from_def subundefed
(/*AUTOINST*/
// Outputs
.q (q));
endmodule
module submod_mod (/*AUTOARG*/
// Outputs
q,
// Inputs
a
);
input a;
output q;
endmodule
module SUBMOD_UNDEFED (/*AUTOARG*/
// Outputs
q
);
output q;
endmodule
`define SUBMOD_DECL submod_decl_from_def
module `SUBMOD_DECL (/*AUTOARG*/
// Outputs
q
);
output q;
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_LP_V
`define SKY130_FD_SC_LP__A2BB2O_LP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_lp (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_lp (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_LP_V
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_fifo_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_fifo_64.lxt");
$dumpvars(0, test_axis_fifo_64);
end
axis_fifo_64 #(
.ADDR_WIDTH(2),
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:18 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_1/bram_2048_1_stub.v
// Design : bram_2048_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module bram_2048_1(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [10:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
module decoder ( cx, d );
input [8:0] cx;
output [2:0] d;
wire n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154,
n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165,
n166, n167, n168, n169, n170;
MUX2X1 U47 ( .B(n133), .A(n134), .S(cx[2]), .Y(d[2]) );
NOR2X1 U48 ( .A(n135), .B(n136), .Y(n134) );
INVX1 U49 ( .A(n137), .Y(n135) );
MUX2X1 U50 ( .B(n137), .A(n138), .S(cx[1]), .Y(d[1]) );
NOR2X1 U51 ( .A(n139), .B(n136), .Y(n138) );
NAND2X1 U52 ( .A(n140), .B(n141), .Y(n136) );
INVX1 U53 ( .A(n142), .Y(n140) );
MUX2X1 U54 ( .B(n141), .A(n143), .S(cx[0]), .Y(d[0]) );
NOR2X1 U55 ( .A(n142), .B(n144), .Y(n143) );
NAND2X1 U56 ( .A(n137), .B(n133), .Y(n144) );
INVX1 U57 ( .A(n139), .Y(n133) );
NOR2X1 U58 ( .A(n145), .B(n146), .Y(n139) );
NAND3X1 U59 ( .A(n147), .B(cx[6]), .C(n148), .Y(n146) );
NAND3X1 U60 ( .A(n149), .B(n150), .C(n151), .Y(n145) );
NAND3X1 U61 ( .A(n147), .B(n152), .C(n153), .Y(n137) );
NOR2X1 U62 ( .A(n149), .B(n154), .Y(n153) );
NAND2X1 U63 ( .A(n150), .B(n155), .Y(n154) );
INVX1 U64 ( .A(n156), .Y(n150) );
NAND3X1 U65 ( .A(n157), .B(n158), .C(n159), .Y(n142) );
INVX1 U66 ( .A(n160), .Y(n159) );
OAI21X1 U67 ( .A(n152), .B(cx[6]), .C(n147), .Y(n160) );
NOR2X1 U68 ( .A(n161), .B(n148), .Y(n152) );
MUX2X1 U69 ( .B(n162), .A(n163), .S(n149), .Y(n158) );
INVX1 U70 ( .A(n164), .Y(n149) );
NOR2X1 U71 ( .A(n156), .B(n155), .Y(n162) );
INVX1 U72 ( .A(cx[6]), .Y(n155) );
MUX2X1 U73 ( .B(n156), .A(n148), .S(n161), .Y(n157) );
OR2X1 U74 ( .A(n165), .B(n166), .Y(n141) );
NAND3X1 U75 ( .A(n147), .B(n156), .C(cx[6]), .Y(n166) );
XNOR2X1 U76 ( .A(cx[0]), .B(n167), .Y(n156) );
XOR2X1 U77 ( .A(cx[4]), .B(cx[1]), .Y(n167) );
XNOR2X1 U78 ( .A(cx[0]), .B(n168), .Y(n147) );
XOR2X1 U79 ( .A(cx[5]), .B(cx[2]), .Y(n168) );
NAND3X1 U80 ( .A(n161), .B(n163), .C(n164), .Y(n165) );
XNOR2X1 U81 ( .A(cx[0]), .B(cx[8]), .Y(n164) );
INVX1 U82 ( .A(n148), .Y(n163) );
XOR2X1 U83 ( .A(n169), .B(n170), .Y(n148) );
XOR2X1 U84 ( .A(cx[7]), .B(cx[2]), .Y(n170) );
INVX1 U85 ( .A(cx[1]), .Y(n169) );
INVX1 U86 ( .A(n151), .Y(n161) );
XNOR2X1 U87 ( .A(cx[2]), .B(cx[3]), .Y(n151) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_V |
// nios_tester_mm_interconnect_0_avalon_st_adapter_009.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module nios_tester_mm_interconnect_0_avalon_st_adapter_009 #(
parameter inBitsPerSymbol = 130,
parameter inUsePackets = 0,
parameter inDataWidth = 130,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 130,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [129:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [129:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_tester_mm_interconnect_0_avalon_st_adapter_009_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_dec_fix.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ecc_dec_fix
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_data, ecc_single, ecc_multiple,
// Inputs
clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid
);
input clk;
input rst;
// Compute syndromes.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns;
genvar k;
genvar m;
generate
for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word
for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
assign syndrome_ns[k*ECC_WIDTH+m] =
^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
end
end
endgenerate
reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r;
always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
// Extract payload bits from raw DRAM bits and register.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
genvar i;
generate
for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload
assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
end
endgenerate
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
// Regenerate h_matrix from h_rows leaving out the identity part
// since we're not going to correct the ECC bits themselves.
genvar n;
genvar p;
wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
generate
for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
end
end
endgenerate
// Compute flip bits.
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits;
genvar q;
genvar r;
generate
for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word
for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
assign flip_bits[q*DATA_WIDTH+r] =
h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
end
end
endgenerate
// Correct data.
output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
input correct_en;
integer s;
always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
for (s=0; s<2*nCK_PER_CLK; s=s+1)
if (correct_en)
rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
// Copy raw payload bits if ECC_TEST is ON.
localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
genvar t;
generate
if (RAW_BIT_WIDTH > 0)
for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits
always @(/*AS*/ecc_rddata_r)
rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
end
endgenerate
// Generate status information.
input ecc_status_valid;
output wire [2*nCK_PER_CLK-1:0] ecc_single;
output wire [2*nCK_PER_CLK-1:0] ecc_multiple;
genvar v;
generate
for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status
wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
assign ecc_single[v] = ecc_status_valid && ~zero && odd;
assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
end
endgenerate
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_afi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM
* from Cadence.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_afi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_BYTES,
RD_QOS,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
S_RDISSUECAP1_EN,
S_WRISSUECAP1_EN,
S_RCOUNT,
S_WCOUNT,
S_RACOUNT,
S_WACOUNT
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output [max_burst_bits-1:0] WR_DATA;
output [addr_width-1:0] WR_ADDR;
output [max_transfer_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
output reg[max_transfer_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
output [axi_qos_width-1:0] WR_QOS;
output reg [axi_qos_width-1:0] RD_QOS;
input S_RDISSUECAP1_EN;
input S_WRISSUECAP1_EN;
output [7:0] S_RCOUNT;
output [7:0] S_WCOUNT;
output [2:0] S_RACOUNT;
output [5:0] S_WACOUNT;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
wire wr_intr_fifo_full;
reg temp_wr_intr_fifo_full;
/* Interconnect WR_FIFO model instance */
processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
/* Register the async 'full' signal to S_ACLK clock */
always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* Internal nets/regs for calling slave BFM API's*/
reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
/* Address Write Channel handshake*/
reg[int_cntr_width-1:0] aw_cnt = 0;//
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1];
reg aw_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* keep track of count values */
reg[7:0] wcount;
reg[5:0] wacount;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
//if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_wr_lat_number = afi_wr_min;
AVG_CASE : get_wr_lat_number = afi_wr_avg;
WORST_CASE : get_wr_lat_number = afi_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min);
2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg);
default : get_wr_lat_number = ($random()%60+ afi_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_rd_lat_number = afi_rd_min;
AVG_CASE : get_rd_lat_number = afi_rd_avg;
WORST_CASE : get_rd_lat_number = afi_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min);
2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg);
default : get_rd_lat_number = ($random()%60+ afi_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
assign S_WCOUNT = wcount;
assign S_WACOUNT = wacount;
// FIFO_STATUS (only if AFI port) 1- full
function automatic wrfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - wcount;
if(fifo_space_left < fifo_space_exp)
wrfifo_full = 1;
else
wrfifo_full = 0;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS;
end
end
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
wacount = 0;
end else begin
if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_cntr_width-2:0]],
awlen[aw_cnt[int_cntr_width-2:0]],
awsize[aw_cnt[int_cntr_width-2:0]],
awbrst[aw_cnt[int_cntr_width-2:0]],
awlock[aw_cnt[int_cntr_width-2:0]],
awcache[aw_cnt[int_cntr_width-2:0]],
awprot[aw_cnt[int_cntr_width-2:0]],
awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1;
aw_cnt = aw_cnt + 1;
wacount = wacount + 1;
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end else begin
if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
else if(decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
reg[max_burst_bits-1:0] temp_wr_data;
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_fifo_wr_ptr = 0;
wcount = 0;
end else begin
enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
/* Fill AFI_WR_data FIFO */
if(bresp === AXI_OK ) begin
if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
end else
valid_data_bytes = 0;
temp_wr_data = aligned_wr_data;
wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Write Response Channel handshake */
reg wr_int_state;
/* Reading from the wr_fifo and sending to Interconnect fifo*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_int_state = 1'b0;
wr_bresp_cnt = 0;
wr_fifo_rd_ptr = 0;
end else begin
case(wr_int_state)
1'b0 : begin
wr_int_state = 1'b0;
if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
wr_int_state = 1'b1;
/* start filling the write response fifo at the same time */
fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
wacount = wacount - 1;
wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
end
end
1'b1 : begin
wr_int_state = 0;
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1];
reg ar_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_rresp;
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
reg [7:0] rcount;
reg [2:0] racount;
wire rd_intr_fifo_full, rd_intr_fifo_empty;
wire read_fifo_empty;
/* signals to communicate with interconnect RD_FIFO model */
reg rd_req, invalid_rd_req;
/* REad control Info
56:25 : Address (32)
24:22 : Size (3)
21:20 : BRST (2)
19:16 : LEN (4)
15:10 : RID (6)
9:8 : RRSP (2)
7:0 : byte cnt (8)
*/
reg [rd_info_bits-1:0] read_control_info;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
reg temp_rd_intr_fifo_empty;
processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign S_RCOUNT = rcount;
assign S_RACOUNT = racount;
/* Register the asynch signal empty coming from Interconnect READ FIFO */
always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
// FIFO_STATUS (only if AFI port) 1- full
function automatic rdfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - rcount;
if(fifo_space_left < fifo_space_exp)
rdfifo_full = 1;
else
rdfifo_full = 0;
end
endfunction
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS;
end
end
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
racount = 0;
end else begin
if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_cntr_width-2:0]],
arlen[ar_cnt[int_cntr_width-2:0]],
arsize[ar_cnt[int_cntr_width-2:0]],
arbrst[ar_cnt[int_cntr_width-2:0]],
arlock[ar_cnt[int_cntr_width-2:0]],
arcache[ar_cnt[int_cntr_width-2:0]],
arprot[ar_cnt[int_cntr_width-2:0]],
arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
racount = racount + 1;
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg rd_fifo_state;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
rd_req = 0;
invalid_rd_req= 0;
RD_QOS = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
rd_fifo_state = WAIT_RD_VALID;
rd_req = 1;
racount = racount - 1;
read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes };
wr_rresp_cnt = wr_rresp_cnt + 1;
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
rd_req = 0;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* thread to fill in the AFI RD_FIFO */
reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
reg tmp_state;
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
rcount = 0;
tmp_state = 0;
end else begin
case(tmp_state)
0 : begin
tmp_state = 0;
if(!temp_rd_intr_fifo_empty) begin
rd_intr_fifo.read_mem(temp_rd_data);
tmp_state = 1;
end
end
1 : begin
tmp_state = 1;
if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
tmp_state = 0;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
rd_delayed = 1;
end
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
temp_read_data = aligned_rd_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb],
tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb],
tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb],
temp_read_data,
temp_read_rsp);
rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
rresp_time_cnt = rresp_time_cnt+1;
rd_latency_count = get_rd_lat_number(1);
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
end
end /// else
end /// always
endmodule
|
// Dependencies
//
// Revision: Neale Ratzlaff
// Revision 0.01 = File Created
//
module SmartRemote(
input A,B,C,
AnalogLdir,
AnalogRdir,
output Len_Out,
Ldir_Out,
Ren_Out,
Rdir_Out
);
// Ground connection
supply0 GND;
// Wires
wire LenO_Wire, LdirO_Wire, RenO_Wire, RdirO_Wire; // Outputs
wire Len, Ldir, Ren, Rdir; // Connections
// IO wire assignment
assign Len_Out = LenO_Wire;
assign LDir_Out = LdirO_Wire;
assign Ren_Out = RenO_Wire;
assign Rdir_Out = RdirO_Wire;
// Section two booger set to be picked
Boogers2 Boog(
.BoogerA(A), // Inputs
.BoogerB(B),
.BoogerC(C),
.Re(Ren), // Outputs
.Le(Len),
.Rd(Rdir),
.Ld(Ldir));
// Array of multiplexers
Mux mux_0( .D0(GND), .D1(Len), .s(S), .Y(LenO_Wire ) );
Mux mux_1( .D0(ALdir), .D1(Ldir), .s(S), .Y(LdirO_Wire) );
Mux mux_2( .D0(GND), . D1(Ren), .s(S), .Y(RenO_Wire ) );
Mux mux_3( .D0(ARdir), .D1(Rdir), .s(S), .Y(RdirO_WIre) );
assign S = AnalogLdir & AnalogRdir; // And Gate
endmodule
module Mux( // Multiplexor Model
input D0, D1, s,
output Y
);
assign Y = s ? D1:D0;
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Wrapper for Xilinx Spartan-6 RAM Block //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// 2048 words x 32 bits with a per byte write enable //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module xs6_sram_2048x32_byte_en
#(
parameter SRAM0_INIT_0 = 256'h0,
parameter SRAM0_INIT_1 = 256'h0,
parameter SRAM0_INIT_2 = 256'h0,
parameter SRAM0_INIT_3 = 256'h0,
parameter SRAM0_INIT_4 = 256'h0,
parameter SRAM0_INIT_5 = 256'h0,
parameter SRAM0_INIT_6 = 256'h0,
parameter SRAM0_INIT_7 = 256'h0,
parameter SRAM0_INIT_8 = 256'h0,
parameter SRAM0_INIT_9 = 256'h0,
parameter SRAM0_INIT_10 = 256'h0,
parameter SRAM0_INIT_11 = 256'h0,
parameter SRAM0_INIT_12 = 256'h0,
parameter SRAM0_INIT_13 = 256'h0,
parameter SRAM0_INIT_14 = 256'h0,
parameter SRAM0_INIT_15 = 256'h0,
parameter SRAM0_INIT_16 = 256'h0,
parameter SRAM0_INIT_17 = 256'h0,
parameter SRAM0_INIT_18 = 256'h0,
parameter SRAM0_INIT_19 = 256'h0,
parameter SRAM0_INIT_20 = 256'h0,
parameter SRAM0_INIT_21 = 256'h0,
parameter SRAM0_INIT_22 = 256'h0,
parameter SRAM0_INIT_23 = 256'h0,
parameter SRAM0_INIT_24 = 256'h0,
parameter SRAM0_INIT_25 = 256'h0,
parameter SRAM0_INIT_26 = 256'h0,
parameter SRAM0_INIT_27 = 256'h0,
parameter SRAM0_INIT_28 = 256'h0,
parameter SRAM0_INIT_29 = 256'h0,
parameter SRAM0_INIT_30 = 256'h0,
parameter SRAM0_INIT_31 = 256'h0,
parameter SRAM0_INIT_32 = 256'h0,
parameter SRAM0_INIT_33 = 256'h0,
parameter SRAM0_INIT_34 = 256'h0,
parameter SRAM0_INIT_35 = 256'h0,
parameter SRAM0_INIT_36 = 256'h0,
parameter SRAM0_INIT_37 = 256'h0,
parameter SRAM0_INIT_38 = 256'h0,
parameter SRAM0_INIT_39 = 256'h0,
parameter SRAM0_INIT_40 = 256'h0,
parameter SRAM0_INIT_41 = 256'h0,
parameter SRAM0_INIT_42 = 256'h0,
parameter SRAM0_INIT_43 = 256'h0,
parameter SRAM0_INIT_44 = 256'h0,
parameter SRAM0_INIT_45 = 256'h0,
parameter SRAM0_INIT_46 = 256'h0,
parameter SRAM0_INIT_47 = 256'h0,
parameter SRAM0_INIT_48 = 256'h0,
parameter SRAM0_INIT_49 = 256'h0,
parameter SRAM0_INIT_50 = 256'h0,
parameter SRAM0_INIT_51 = 256'h0,
parameter SRAM0_INIT_52 = 256'h0,
parameter SRAM0_INIT_53 = 256'h0,
parameter SRAM0_INIT_54 = 256'h0,
parameter SRAM0_INIT_55 = 256'h0,
parameter SRAM0_INIT_56 = 256'h0,
parameter SRAM0_INIT_57 = 256'h0,
parameter SRAM0_INIT_58 = 256'h0,
parameter SRAM0_INIT_59 = 256'h0,
parameter SRAM0_INIT_60 = 256'h0,
parameter SRAM0_INIT_61 = 256'h0,
parameter SRAM0_INIT_62 = 256'h0,
parameter SRAM0_INIT_63 = 256'h0,
parameter SRAM1_INIT_0 = 256'h0,
parameter SRAM1_INIT_1 = 256'h0,
parameter SRAM1_INIT_2 = 256'h0,
parameter SRAM1_INIT_3 = 256'h0,
parameter SRAM1_INIT_4 = 256'h0,
parameter SRAM1_INIT_5 = 256'h0,
parameter SRAM1_INIT_6 = 256'h0,
parameter SRAM1_INIT_7 = 256'h0,
parameter SRAM1_INIT_8 = 256'h0,
parameter SRAM1_INIT_9 = 256'h0,
parameter SRAM1_INIT_10 = 256'h0,
parameter SRAM1_INIT_11 = 256'h0,
parameter SRAM1_INIT_12 = 256'h0,
parameter SRAM1_INIT_13 = 256'h0,
parameter SRAM1_INIT_14 = 256'h0,
parameter SRAM1_INIT_15 = 256'h0,
parameter SRAM1_INIT_16 = 256'h0,
parameter SRAM1_INIT_17 = 256'h0,
parameter SRAM1_INIT_18 = 256'h0,
parameter SRAM1_INIT_19 = 256'h0,
parameter SRAM1_INIT_20 = 256'h0,
parameter SRAM1_INIT_21 = 256'h0,
parameter SRAM1_INIT_22 = 256'h0,
parameter SRAM1_INIT_23 = 256'h0,
parameter SRAM1_INIT_24 = 256'h0,
parameter SRAM1_INIT_25 = 256'h0,
parameter SRAM1_INIT_26 = 256'h0,
parameter SRAM1_INIT_27 = 256'h0,
parameter SRAM1_INIT_28 = 256'h0,
parameter SRAM1_INIT_29 = 256'h0,
parameter SRAM1_INIT_30 = 256'h0,
parameter SRAM1_INIT_31 = 256'h0,
parameter SRAM1_INIT_32 = 256'h0,
parameter SRAM1_INIT_33 = 256'h0,
parameter SRAM1_INIT_34 = 256'h0,
parameter SRAM1_INIT_35 = 256'h0,
parameter SRAM1_INIT_36 = 256'h0,
parameter SRAM1_INIT_37 = 256'h0,
parameter SRAM1_INIT_38 = 256'h0,
parameter SRAM1_INIT_39 = 256'h0,
parameter SRAM1_INIT_40 = 256'h0,
parameter SRAM1_INIT_41 = 256'h0,
parameter SRAM1_INIT_42 = 256'h0,
parameter SRAM1_INIT_43 = 256'h0,
parameter SRAM1_INIT_44 = 256'h0,
parameter SRAM1_INIT_45 = 256'h0,
parameter SRAM1_INIT_46 = 256'h0,
parameter SRAM1_INIT_47 = 256'h0,
parameter SRAM1_INIT_48 = 256'h0,
parameter SRAM1_INIT_49 = 256'h0,
parameter SRAM1_INIT_50 = 256'h0,
parameter SRAM1_INIT_51 = 256'h0,
parameter SRAM1_INIT_52 = 256'h0,
parameter SRAM1_INIT_53 = 256'h0,
parameter SRAM1_INIT_54 = 256'h0,
parameter SRAM1_INIT_55 = 256'h0,
parameter SRAM1_INIT_56 = 256'h0,
parameter SRAM1_INIT_57 = 256'h0,
parameter SRAM1_INIT_58 = 256'h0,
parameter SRAM1_INIT_59 = 256'h0,
parameter SRAM1_INIT_60 = 256'h0,
parameter SRAM1_INIT_61 = 256'h0,
parameter SRAM1_INIT_62 = 256'h0,
parameter SRAM1_INIT_63 = 256'h0,
parameter SRAM2_INIT_0 = 256'h0,
parameter SRAM2_INIT_1 = 256'h0,
parameter SRAM2_INIT_2 = 256'h0,
parameter SRAM2_INIT_3 = 256'h0,
parameter SRAM2_INIT_4 = 256'h0,
parameter SRAM2_INIT_5 = 256'h0,
parameter SRAM2_INIT_6 = 256'h0,
parameter SRAM2_INIT_7 = 256'h0,
parameter SRAM2_INIT_8 = 256'h0,
parameter SRAM2_INIT_9 = 256'h0,
parameter SRAM2_INIT_10 = 256'h0,
parameter SRAM2_INIT_11 = 256'h0,
parameter SRAM2_INIT_12 = 256'h0,
parameter SRAM2_INIT_13 = 256'h0,
parameter SRAM2_INIT_14 = 256'h0,
parameter SRAM2_INIT_15 = 256'h0,
parameter SRAM2_INIT_16 = 256'h0,
parameter SRAM2_INIT_17 = 256'h0,
parameter SRAM2_INIT_18 = 256'h0,
parameter SRAM2_INIT_19 = 256'h0,
parameter SRAM2_INIT_20 = 256'h0,
parameter SRAM2_INIT_21 = 256'h0,
parameter SRAM2_INIT_22 = 256'h0,
parameter SRAM2_INIT_23 = 256'h0,
parameter SRAM2_INIT_24 = 256'h0,
parameter SRAM2_INIT_25 = 256'h0,
parameter SRAM2_INIT_26 = 256'h0,
parameter SRAM2_INIT_27 = 256'h0,
parameter SRAM2_INIT_28 = 256'h0,
parameter SRAM2_INIT_29 = 256'h0,
parameter SRAM2_INIT_30 = 256'h0,
parameter SRAM2_INIT_31 = 256'h0,
parameter SRAM2_INIT_32 = 256'h0,
parameter SRAM2_INIT_33 = 256'h0,
parameter SRAM2_INIT_34 = 256'h0,
parameter SRAM2_INIT_35 = 256'h0,
parameter SRAM2_INIT_36 = 256'h0,
parameter SRAM2_INIT_37 = 256'h0,
parameter SRAM2_INIT_38 = 256'h0,
parameter SRAM2_INIT_39 = 256'h0,
parameter SRAM2_INIT_40 = 256'h0,
parameter SRAM2_INIT_41 = 256'h0,
parameter SRAM2_INIT_42 = 256'h0,
parameter SRAM2_INIT_43 = 256'h0,
parameter SRAM2_INIT_44 = 256'h0,
parameter SRAM2_INIT_45 = 256'h0,
parameter SRAM2_INIT_46 = 256'h0,
parameter SRAM2_INIT_47 = 256'h0,
parameter SRAM2_INIT_48 = 256'h0,
parameter SRAM2_INIT_49 = 256'h0,
parameter SRAM2_INIT_50 = 256'h0,
parameter SRAM2_INIT_51 = 256'h0,
parameter SRAM2_INIT_52 = 256'h0,
parameter SRAM2_INIT_53 = 256'h0,
parameter SRAM2_INIT_54 = 256'h0,
parameter SRAM2_INIT_55 = 256'h0,
parameter SRAM2_INIT_56 = 256'h0,
parameter SRAM2_INIT_57 = 256'h0,
parameter SRAM2_INIT_58 = 256'h0,
parameter SRAM2_INIT_59 = 256'h0,
parameter SRAM2_INIT_60 = 256'h0,
parameter SRAM2_INIT_61 = 256'h0,
parameter SRAM2_INIT_62 = 256'h0,
parameter SRAM2_INIT_63 = 256'h0,
parameter SRAM3_INIT_0 = 256'h0,
parameter SRAM3_INIT_1 = 256'h0,
parameter SRAM3_INIT_2 = 256'h0,
parameter SRAM3_INIT_3 = 256'h0,
parameter SRAM3_INIT_4 = 256'h0,
parameter SRAM3_INIT_5 = 256'h0,
parameter SRAM3_INIT_6 = 256'h0,
parameter SRAM3_INIT_7 = 256'h0,
parameter SRAM3_INIT_8 = 256'h0,
parameter SRAM3_INIT_9 = 256'h0,
parameter SRAM3_INIT_10 = 256'h0,
parameter SRAM3_INIT_11 = 256'h0,
parameter SRAM3_INIT_12 = 256'h0,
parameter SRAM3_INIT_13 = 256'h0,
parameter SRAM3_INIT_14 = 256'h0,
parameter SRAM3_INIT_15 = 256'h0,
parameter SRAM3_INIT_16 = 256'h0,
parameter SRAM3_INIT_17 = 256'h0,
parameter SRAM3_INIT_18 = 256'h0,
parameter SRAM3_INIT_19 = 256'h0,
parameter SRAM3_INIT_20 = 256'h0,
parameter SRAM3_INIT_21 = 256'h0,
parameter SRAM3_INIT_22 = 256'h0,
parameter SRAM3_INIT_23 = 256'h0,
parameter SRAM3_INIT_24 = 256'h0,
parameter SRAM3_INIT_25 = 256'h0,
parameter SRAM3_INIT_26 = 256'h0,
parameter SRAM3_INIT_27 = 256'h0,
parameter SRAM3_INIT_28 = 256'h0,
parameter SRAM3_INIT_29 = 256'h0,
parameter SRAM3_INIT_30 = 256'h0,
parameter SRAM3_INIT_31 = 256'h0,
parameter SRAM3_INIT_32 = 256'h0,
parameter SRAM3_INIT_33 = 256'h0,
parameter SRAM3_INIT_34 = 256'h0,
parameter SRAM3_INIT_35 = 256'h0,
parameter SRAM3_INIT_36 = 256'h0,
parameter SRAM3_INIT_37 = 256'h0,
parameter SRAM3_INIT_38 = 256'h0,
parameter SRAM3_INIT_39 = 256'h0,
parameter SRAM3_INIT_40 = 256'h0,
parameter SRAM3_INIT_41 = 256'h0,
parameter SRAM3_INIT_42 = 256'h0,
parameter SRAM3_INIT_43 = 256'h0,
parameter SRAM3_INIT_44 = 256'h0,
parameter SRAM3_INIT_45 = 256'h0,
parameter SRAM3_INIT_46 = 256'h0,
parameter SRAM3_INIT_47 = 256'h0,
parameter SRAM3_INIT_48 = 256'h0,
parameter SRAM3_INIT_49 = 256'h0,
parameter SRAM3_INIT_50 = 256'h0,
parameter SRAM3_INIT_51 = 256'h0,
parameter SRAM3_INIT_52 = 256'h0,
parameter SRAM3_INIT_53 = 256'h0,
parameter SRAM3_INIT_54 = 256'h0,
parameter SRAM3_INIT_55 = 256'h0,
parameter SRAM3_INIT_56 = 256'h0,
parameter SRAM3_INIT_57 = 256'h0,
parameter SRAM3_INIT_58 = 256'h0,
parameter SRAM3_INIT_59 = 256'h0,
parameter SRAM3_INIT_60 = 256'h0,
parameter SRAM3_INIT_61 = 256'h0,
parameter SRAM3_INIT_62 = 256'h0,
parameter SRAM3_INIT_63 = 256'h0,
parameter UNUSED = 1'd1
)
(
input i_clk,
input [31:0] i_write_data,
input i_write_enable,
input [10:0] i_address,
input [3:0] i_byte_enable,
output [31:0] o_read_data
);
wire [3:0] wea;
wire [31:0] data_out [3:0];
assign o_read_data = { data_out[3][7:0], data_out[2][7:0],
data_out[1][7:0], data_out[0][7:0] };
assign wea = {4{i_write_enable}} & i_byte_enable;
RAMB16BWER #(
.INIT_00 ( SRAM0_INIT_0 ),
.INIT_01 ( SRAM0_INIT_1 ),
.INIT_02 ( SRAM0_INIT_2 ),
.INIT_03 ( SRAM0_INIT_3 ),
.INIT_04 ( SRAM0_INIT_4 ),
.INIT_05 ( SRAM0_INIT_5 ),
.INIT_06 ( SRAM0_INIT_6 ),
.INIT_07 ( SRAM0_INIT_7 ),
.INIT_08 ( SRAM0_INIT_8 ),
.INIT_09 ( SRAM0_INIT_9 ),
.INIT_0A ( SRAM0_INIT_10 ),
.INIT_0B ( SRAM0_INIT_11 ),
.INIT_0C ( SRAM0_INIT_12 ),
.INIT_0D ( SRAM0_INIT_13 ),
.INIT_0E ( SRAM0_INIT_14 ),
.INIT_0F ( SRAM0_INIT_15 ),
.INIT_10 ( SRAM0_INIT_16 ),
.INIT_11 ( SRAM0_INIT_17 ),
.INIT_12 ( SRAM0_INIT_18 ),
.INIT_13 ( SRAM0_INIT_19 ),
.INIT_14 ( SRAM0_INIT_20 ),
.INIT_15 ( SRAM0_INIT_21 ),
.INIT_16 ( SRAM0_INIT_22 ),
.INIT_17 ( SRAM0_INIT_23 ),
.INIT_18 ( SRAM0_INIT_24 ),
.INIT_19 ( SRAM0_INIT_25 ),
.INIT_1A ( SRAM0_INIT_26 ),
.INIT_1B ( SRAM0_INIT_27 ),
.INIT_1C ( SRAM0_INIT_28 ),
.INIT_1D ( SRAM0_INIT_29 ),
.INIT_1E ( SRAM0_INIT_30 ),
.INIT_1F ( SRAM0_INIT_31 ),
.INIT_20 ( SRAM0_INIT_32 ),
.INIT_21 ( SRAM0_INIT_33 ),
.INIT_22 ( SRAM0_INIT_34 ),
.INIT_23 ( SRAM0_INIT_35 ),
.INIT_24 ( SRAM0_INIT_36 ),
.INIT_25 ( SRAM0_INIT_37 ),
.INIT_26 ( SRAM0_INIT_38 ),
.INIT_27 ( SRAM0_INIT_39 ),
.INIT_28 ( SRAM0_INIT_40 ),
.INIT_29 ( SRAM0_INIT_41 ),
.INIT_2A ( SRAM0_INIT_42 ),
.INIT_2B ( SRAM0_INIT_43 ),
.INIT_2C ( SRAM0_INIT_44 ),
.INIT_2D ( SRAM0_INIT_45 ),
.INIT_2E ( SRAM0_INIT_46 ),
.INIT_2F ( SRAM0_INIT_47 ),
.INIT_30 ( SRAM0_INIT_48 ),
.INIT_31 ( SRAM0_INIT_49 ),
.INIT_32 ( SRAM0_INIT_50 ),
.INIT_33 ( SRAM0_INIT_51 ),
.INIT_34 ( SRAM0_INIT_52 ),
.INIT_35 ( SRAM0_INIT_53 ),
.INIT_36 ( SRAM0_INIT_54 ),
.INIT_37 ( SRAM0_INIT_55 ),
.INIT_38 ( SRAM0_INIT_56 ),
.INIT_39 ( SRAM0_INIT_57 ),
.INIT_3A ( SRAM0_INIT_58 ),
.INIT_3B ( SRAM0_INIT_59 ),
.INIT_3C ( SRAM0_INIT_60 ),
.INIT_3D ( SRAM0_INIT_61 ),
.INIT_3E ( SRAM0_INIT_62 ),
.INIT_3F ( SRAM0_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram0 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( {wea[3], wea[3], wea[3], wea[3]} ),
.DOA ( data_out[3] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[31:24]} )
);
RAMB16BWER #(
.INIT_00 ( SRAM1_INIT_0 ),
.INIT_01 ( SRAM1_INIT_1 ),
.INIT_02 ( SRAM1_INIT_2 ),
.INIT_03 ( SRAM1_INIT_3 ),
.INIT_04 ( SRAM1_INIT_4 ),
.INIT_05 ( SRAM1_INIT_5 ),
.INIT_06 ( SRAM1_INIT_6 ),
.INIT_07 ( SRAM1_INIT_7 ),
.INIT_08 ( SRAM1_INIT_8 ),
.INIT_09 ( SRAM1_INIT_9 ),
.INIT_0A ( SRAM1_INIT_10 ),
.INIT_0B ( SRAM1_INIT_11 ),
.INIT_0C ( SRAM1_INIT_12 ),
.INIT_0D ( SRAM1_INIT_13 ),
.INIT_0E ( SRAM1_INIT_14 ),
.INIT_0F ( SRAM1_INIT_15 ),
.INIT_10 ( SRAM1_INIT_16 ),
.INIT_11 ( SRAM1_INIT_17 ),
.INIT_12 ( SRAM1_INIT_18 ),
.INIT_13 ( SRAM1_INIT_19 ),
.INIT_14 ( SRAM1_INIT_20 ),
.INIT_15 ( SRAM1_INIT_21 ),
.INIT_16 ( SRAM1_INIT_22 ),
.INIT_17 ( SRAM1_INIT_23 ),
.INIT_18 ( SRAM1_INIT_24 ),
.INIT_19 ( SRAM1_INIT_25 ),
.INIT_1A ( SRAM1_INIT_26 ),
.INIT_1B ( SRAM1_INIT_27 ),
.INIT_1C ( SRAM1_INIT_28 ),
.INIT_1D ( SRAM1_INIT_29 ),
.INIT_1E ( SRAM1_INIT_30 ),
.INIT_1F ( SRAM1_INIT_31 ),
.INIT_20 ( SRAM1_INIT_32 ),
.INIT_21 ( SRAM1_INIT_33 ),
.INIT_22 ( SRAM1_INIT_34 ),
.INIT_23 ( SRAM1_INIT_35 ),
.INIT_24 ( SRAM1_INIT_36 ),
.INIT_25 ( SRAM1_INIT_37 ),
.INIT_26 ( SRAM1_INIT_38 ),
.INIT_27 ( SRAM1_INIT_39 ),
.INIT_28 ( SRAM1_INIT_40 ),
.INIT_29 ( SRAM1_INIT_41 ),
.INIT_2A ( SRAM1_INIT_42 ),
.INIT_2B ( SRAM1_INIT_43 ),
.INIT_2C ( SRAM1_INIT_44 ),
.INIT_2D ( SRAM1_INIT_45 ),
.INIT_2E ( SRAM1_INIT_46 ),
.INIT_2F ( SRAM1_INIT_47 ),
.INIT_30 ( SRAM1_INIT_48 ),
.INIT_31 ( SRAM1_INIT_49 ),
.INIT_32 ( SRAM1_INIT_50 ),
.INIT_33 ( SRAM1_INIT_51 ),
.INIT_34 ( SRAM1_INIT_52 ),
.INIT_35 ( SRAM1_INIT_53 ),
.INIT_36 ( SRAM1_INIT_54 ),
.INIT_37 ( SRAM1_INIT_55 ),
.INIT_38 ( SRAM1_INIT_56 ),
.INIT_39 ( SRAM1_INIT_57 ),
.INIT_3A ( SRAM1_INIT_58 ),
.INIT_3B ( SRAM1_INIT_59 ),
.INIT_3C ( SRAM1_INIT_60 ),
.INIT_3D ( SRAM1_INIT_61 ),
.INIT_3E ( SRAM1_INIT_62 ),
.INIT_3F ( SRAM1_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram1 (
.REGCEA(1'd0),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ({wea[2], wea[2], wea[2], wea[2]} ),
.DOA ( data_out[2] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[23:16]} )
);
RAMB16BWER #(
.INIT_00 ( SRAM2_INIT_0 ),
.INIT_01 ( SRAM2_INIT_1 ),
.INIT_02 ( SRAM2_INIT_2 ),
.INIT_03 ( SRAM2_INIT_3 ),
.INIT_04 ( SRAM2_INIT_4 ),
.INIT_05 ( SRAM2_INIT_5 ),
.INIT_06 ( SRAM2_INIT_6 ),
.INIT_07 ( SRAM2_INIT_7 ),
.INIT_08 ( SRAM2_INIT_8 ),
.INIT_09 ( SRAM2_INIT_9 ),
.INIT_0A ( SRAM2_INIT_10 ),
.INIT_0B ( SRAM2_INIT_11 ),
.INIT_0C ( SRAM2_INIT_12 ),
.INIT_0D ( SRAM2_INIT_13 ),
.INIT_0E ( SRAM2_INIT_14 ),
.INIT_0F ( SRAM2_INIT_15 ),
.INIT_10 ( SRAM2_INIT_16 ),
.INIT_11 ( SRAM2_INIT_17 ),
.INIT_12 ( SRAM2_INIT_18 ),
.INIT_13 ( SRAM2_INIT_19 ),
.INIT_14 ( SRAM2_INIT_20 ),
.INIT_15 ( SRAM2_INIT_21 ),
.INIT_16 ( SRAM2_INIT_22 ),
.INIT_17 ( SRAM2_INIT_23 ),
.INIT_18 ( SRAM2_INIT_24 ),
.INIT_19 ( SRAM2_INIT_25 ),
.INIT_1A ( SRAM2_INIT_26 ),
.INIT_1B ( SRAM2_INIT_27 ),
.INIT_1C ( SRAM2_INIT_28 ),
.INIT_1D ( SRAM2_INIT_29 ),
.INIT_1E ( SRAM2_INIT_30 ),
.INIT_1F ( SRAM2_INIT_31 ),
.INIT_20 ( SRAM2_INIT_32 ),
.INIT_21 ( SRAM2_INIT_33 ),
.INIT_22 ( SRAM2_INIT_34 ),
.INIT_23 ( SRAM2_INIT_35 ),
.INIT_24 ( SRAM2_INIT_36 ),
.INIT_25 ( SRAM2_INIT_37 ),
.INIT_26 ( SRAM2_INIT_38 ),
.INIT_27 ( SRAM2_INIT_39 ),
.INIT_28 ( SRAM2_INIT_40 ),
.INIT_29 ( SRAM2_INIT_41 ),
.INIT_2A ( SRAM2_INIT_42 ),
.INIT_2B ( SRAM2_INIT_43 ),
.INIT_2C ( SRAM2_INIT_44 ),
.INIT_2D ( SRAM2_INIT_45 ),
.INIT_2E ( SRAM2_INIT_46 ),
.INIT_2F ( SRAM2_INIT_47 ),
.INIT_30 ( SRAM2_INIT_48 ),
.INIT_31 ( SRAM2_INIT_49 ),
.INIT_32 ( SRAM2_INIT_50 ),
.INIT_33 ( SRAM2_INIT_51 ),
.INIT_34 ( SRAM2_INIT_52 ),
.INIT_35 ( SRAM2_INIT_53 ),
.INIT_36 ( SRAM2_INIT_54 ),
.INIT_37 ( SRAM2_INIT_55 ),
.INIT_38 ( SRAM2_INIT_56 ),
.INIT_39 ( SRAM2_INIT_57 ),
.INIT_3A ( SRAM2_INIT_58 ),
.INIT_3B ( SRAM2_INIT_59 ),
.INIT_3C ( SRAM2_INIT_60 ),
.INIT_3D ( SRAM2_INIT_61 ),
.INIT_3E ( SRAM2_INIT_62 ),
.INIT_3F ( SRAM2_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram2 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( {wea[1], wea[1], wea[1], wea[1]} ),
.DOA ( data_out[1] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[15:08]} )
);
RAMB16BWER #(
.INIT_00 ( SRAM3_INIT_0 ),
.INIT_01 ( SRAM3_INIT_1 ),
.INIT_02 ( SRAM3_INIT_2 ),
.INIT_03 ( SRAM3_INIT_3 ),
.INIT_04 ( SRAM3_INIT_4 ),
.INIT_05 ( SRAM3_INIT_5 ),
.INIT_06 ( SRAM3_INIT_6 ),
.INIT_07 ( SRAM3_INIT_7 ),
.INIT_08 ( SRAM3_INIT_8 ),
.INIT_09 ( SRAM3_INIT_9 ),
.INIT_0A ( SRAM3_INIT_10 ),
.INIT_0B ( SRAM3_INIT_11 ),
.INIT_0C ( SRAM3_INIT_12 ),
.INIT_0D ( SRAM3_INIT_13 ),
.INIT_0E ( SRAM3_INIT_14 ),
.INIT_0F ( SRAM3_INIT_15 ),
.INIT_10 ( SRAM3_INIT_16 ),
.INIT_11 ( SRAM3_INIT_17 ),
.INIT_12 ( SRAM3_INIT_18 ),
.INIT_13 ( SRAM3_INIT_19 ),
.INIT_14 ( SRAM3_INIT_20 ),
.INIT_15 ( SRAM3_INIT_21 ),
.INIT_16 ( SRAM3_INIT_22 ),
.INIT_17 ( SRAM3_INIT_23 ),
.INIT_18 ( SRAM3_INIT_24 ),
.INIT_19 ( SRAM3_INIT_25 ),
.INIT_1A ( SRAM3_INIT_26 ),
.INIT_1B ( SRAM3_INIT_27 ),
.INIT_1C ( SRAM3_INIT_28 ),
.INIT_1D ( SRAM3_INIT_29 ),
.INIT_1E ( SRAM3_INIT_30 ),
.INIT_1F ( SRAM3_INIT_31 ),
.INIT_20 ( SRAM3_INIT_32 ),
.INIT_21 ( SRAM3_INIT_33 ),
.INIT_22 ( SRAM3_INIT_34 ),
.INIT_23 ( SRAM3_INIT_35 ),
.INIT_24 ( SRAM3_INIT_36 ),
.INIT_25 ( SRAM3_INIT_37 ),
.INIT_26 ( SRAM3_INIT_38 ),
.INIT_27 ( SRAM3_INIT_39 ),
.INIT_28 ( SRAM3_INIT_40 ),
.INIT_29 ( SRAM3_INIT_41 ),
.INIT_2A ( SRAM3_INIT_42 ),
.INIT_2B ( SRAM3_INIT_43 ),
.INIT_2C ( SRAM3_INIT_44 ),
.INIT_2D ( SRAM3_INIT_45 ),
.INIT_2E ( SRAM3_INIT_46 ),
.INIT_2F ( SRAM3_INIT_47 ),
.INIT_30 ( SRAM3_INIT_48 ),
.INIT_31 ( SRAM3_INIT_49 ),
.INIT_32 ( SRAM3_INIT_50 ),
.INIT_33 ( SRAM3_INIT_51 ),
.INIT_34 ( SRAM3_INIT_52 ),
.INIT_35 ( SRAM3_INIT_53 ),
.INIT_36 ( SRAM3_INIT_54 ),
.INIT_37 ( SRAM3_INIT_55 ),
.INIT_38 ( SRAM3_INIT_56 ),
.INIT_39 ( SRAM3_INIT_57 ),
.INIT_3A ( SRAM3_INIT_58 ),
.INIT_3B ( SRAM3_INIT_59 ),
.INIT_3C ( SRAM3_INIT_60 ),
.INIT_3D ( SRAM3_INIT_61 ),
.INIT_3E ( SRAM3_INIT_62 ),
.INIT_3F ( SRAM3_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram3 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.WEA ({wea[0], wea[0], wea[0], wea[0]} ),
.DOA ( data_out[0] ),
.ADDRA ({i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIA ( {24'd0, i_write_data[7:0]} ),
.DIB ( 32'd0 ),
.DIPA ( 4'd0 ),
.DIPB ( 4'd0 ),
.DOPA ( ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 )
);
endmodule
|
`timescale 1 ns / 1 ps
`include "BoardInit_AXI_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module BoardInit_AXI_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
task automatic COMPARE_LITE_DATA;
input expected;
input actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr_scramble
*/
module test_lfsr_scramble_64;
// Parameters
parameter LFSR_WIDTH = 58;
parameter LFSR_POLY = 58'h8000000001;
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}};
parameter LFSR_CONFIG = "FIBONACCI";
parameter REVERSE = 1;
parameter DATA_WIDTH = 64;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] data_in = 0;
reg data_in_valid = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
data_in,
data_in_valid
);
$to_myhdl(
data_out
);
// dump file
$dumpfile("test_lfsr_scramble_64.lxt");
$dumpvars(0, test_lfsr_scramble_64);
end
lfsr_scramble #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_INIT(LFSR_INIT),
.LFSR_CONFIG(LFSR_CONFIG),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_out(data_out)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [223:0] sum;
wire [255:0] mglehy = {32{~crc}};
wire [215:0] drricx = {27{crc}};
wire [15:0] apqrli = {2{~crc}};
wire [2:0] szlfpf = crc[2:0];
wire [15:0] dzosui = {2{crc}};
wire [31:0] zndrba = {16{crc[1:0]}};
wire [223:0] bxiouf;
vliw vliw (
// Outputs
.bxiouf (bxiouf),
// Inputs
.mglehy (mglehy[255:0]),
.drricx (drricx[215:0]),
.apqrli (apqrli[15:0]),
.szlfpf (szlfpf[2:0]),
.dzosui (dzosui[15:0]),
.zndrba (zndrba[31:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 224'h0;
end
else if (cyc<90) begin
//$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf);
sum <= {sum[222:0],sum[223]} ^ bxiouf;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b01110000) $stop;
if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module vliw (
input[255:0] mglehy,
input[215:0] drricx,
input[15:0] apqrli,
input[2:0] szlfpf,
input[15:0] dzosui,
input[31:0] zndrba,
output [223:0] bxiouf
);
wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]})
| ({29{apqrli}} & {mglehy[247:0], drricx});
wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128])
| ({21{dzosui}} & zhknfc[335:0]);
wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
wire [223:0] rzyeut = viuvoc[335:112];
wire [223:0] bxiouf = {rzyeut[7:0],
rzyeut[15:8],
rzyeut[23:16],
rzyeut[31:24],
rzyeut[39:32],
rzyeut[47:40],
rzyeut[55:48],
rzyeut[63:56],
rzyeut[71:64],
rzyeut[79:72],
rzyeut[87:80],
rzyeut[95:88],
rzyeut[103:96],
rzyeut[111:104],
rzyeut[119:112],
rzyeut[127:120],
rzyeut[135:128],
rzyeut[143:136],
rzyeut[151:144],
rzyeut[159:152],
rzyeut[167:160],
rzyeut[175:168],
rzyeut[183:176],
rzyeut[191:184],
rzyeut[199:192],
rzyeut[207:200],
rzyeut[215:208],
rzyeut[223:216]};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2020 by Yutetsu TAKATSUKASA. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef VCS
`define NO_TIME
`endif
`ifdef NC
`define NO_TIME
`define NO_INTEGER
`define NO_SHORTREAL
`endif
`ifdef MS
`define NO_BITS_TO_SCALAR
`endif
`ifdef VERILATOR
`define NO_SHORTREAL
`define NO_UNPACK_STRUCT
//%Error-TASKNSVAR: Unsupported: Function/task input argument is not simple variable
`define NO_INOUT_COMPLEX_TYPE
`endif
`ifdef NO_BITS_TO_SCALAR
`define ARE_SAME(act, exp) ($bits((act)) == 1 ? (act) == ((exp) & 1) : (act) == (exp))
`else
`define ARE_SAME(act, exp) ((act) == (($bits(act))'(exp)))
`endif
`define CHECK_VAL(act, exp) if (`ARE_SAME(act, exp)) begin \
if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \
end else begin \
$display("Mismatch %s expected:%d actual:%d at %d", `"act`", int'(exp), int'(act), `__LINE__); \
$stop; \
end
`define CHECK_CHANDLE_VAL(act, exp) if ((act) == (exp)) begin \
if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":non-null as expected"); \
end else begin \
$display("Mismatch %s expected:%s but %s at %d", `"act`", \
(exp) != null ? "null" : "non-null", \
(act) != null ? "null" : "non-null", `__LINE__); \
$stop; \
end
`define CHECK_STRING_VAL(act, exp) if ((act) == (exp)) begin \
if (ENABLE_VERBOSE_MESSAGE)$display(`"act`", ":", (act), " as expected"); \
end else begin \
$display("Mismatch %s expected:%s actual:%s at %d", `"act`", (exp), (act), `__LINE__); \
$stop; \
end
`define UPDATE_VAL(var, val) `CHECK_VAL(var, val); var += 1
`define UPDATE_0D(val) `UPDATE_VAL(val, 42)
`define UPDATE_1D(val) `UPDATE_VAL(val[0], 43); \
`UPDATE_VAL(val[1], 44)
`define UPDATE_2D(val) `UPDATE_VAL(val[0][1], 45); \
`UPDATE_VAL(val[1][1], 46); \
`UPDATE_VAL(val[2][1], 47)
`define UPDATE_3D(val) `UPDATE_VAL(val[0][0][0], 48); \
`UPDATE_VAL(val[1][0][0], 49); \
`UPDATE_VAL(val[2][0][0], 50); \
`UPDATE_VAL(val[3][0][0], 51)
`define CHECK_0D(val) `CHECK_VAL((val), 43)
`define CHECK_1D(val) `CHECK_VAL(val[0], 44); \
`CHECK_VAL(val[1], 45)
`define CHECK_2D(val) `CHECK_VAL(val[0][1], 46); \
`CHECK_VAL(val[1][1], 47); `CHECK_VAL(val[2][1], 48)
`define CHECK_3D(val) `CHECK_VAL(val[0][0][0], 49); \
`CHECK_VAL(val[1][0][0], 50); \
`CHECK_VAL(val[2][0][0], 51); \
`CHECK_VAL(val[3][0][0], 52)
`define CHECK_DOUBLE_VAL(act, exp) if ((act) == (exp)) begin \
if (ENABLE_VERBOSE_MESSAGE)$display("%s:%f as expected", `"act`", (act)); \
end else begin \
$display("Mismatch %s expected:%d actual:%f at %f", `"act`", (exp), (act), `__LINE__); \
$stop; \
end
`define CHECK_DOUBLE_0D(val) `CHECK_DOUBLE_VAL((val), 43.0)
`define CHECK_DOUBLE_1D(val) `CHECK_DOUBLE_VAL(val[0], 44.0); \
`CHECK_DOUBLE_VAL(val[1], 45.0)
`define CHECK_DOUBLE_2D(val) `CHECK_DOUBLE_VAL(val[0][1], 46.0); \
`CHECK_DOUBLE_VAL(val[1][1], 47.0); \
`CHECK_DOUBLE_VAL(val[2][1], 48.0)
`define CHECK_DOUBLE_3D(val) `CHECK_DOUBLE_VAL(val[0][0][0], 49.0); \
`CHECK_DOUBLE_VAL(val[1][0][0], 50.0); \
`CHECK_DOUBLE_VAL(val[2][0][0], 51.0); \
`CHECK_DOUBLE_VAL(val[3][0][0], 52.0)
`define SET_VALUE_0D(val) \
/*verilator lint_off WIDTH */ \
val = 42
/*verilator lint_on WIDTH */
`define SET_VALUE_1D(val) \
/*verilator lint_off WIDTH */ \
val[0] = 43; val[1] = 44 \
/*verilator lint_on WIDTH */
`define SET_VALUE_2D(val) \
/*verilator lint_off WIDTH */ \
val[0][1] = 45; val[1][1] = 46; val[2][1] = 47 \
/*verilator lint_on WIDTH */
`define SET_VALUES(val) \
/*verilator lint_off WIDTH */ \
val[3][2][1] = 42; \
val[2][1][0] = 43; val[2][1][1] = 44; \
val[1][0][1] = 45; val[1][1][1] = 46; val[1][2][1] = 47; \
val[0][0][0] = 48; val[1][0][0] = 49; val[2][0][0] = 50; val[3][0][0] = 51 \
/*verilator lint_on WIDTH */
module t;
localparam ENABLE_VERBOSE_MESSAGE = 0;
// Legal output argument types for DPI functions
//======================================================================
// Type definitions
//======================================================================
typedef byte byte_t;
typedef byte_t byte_array_t[4][3][2];
typedef byte unsigned byte_unsigned_t;
typedef byte_unsigned_t byte_unsigned_array_t[4][3][2];
typedef shortint shortint_t;
typedef shortint_t shortint_array_t[4][3][2];
typedef shortint unsigned shortint_unsigned_t;
typedef shortint_unsigned_t shortint_unsigned_array_t[4][3][2];
typedef int int_t;
typedef int_t int_array_t[4][3][2];
typedef int unsigned int_unsigned_t;
typedef int_unsigned_t int_unsigned_array_t[4][3][2];
typedef longint longint_t;
typedef longint_t longint_array_t[4][3][2];
typedef longint unsigned longint_unsigned_t;
typedef longint_unsigned_t longint_unsigned_array_t[4][3][2];
`ifndef NO_TIME
typedef time time_t;
typedef time_t time_array_t[4][3][2];
`endif
`ifndef NO_INTEGER
typedef integer integer_t;
typedef integer_t integer_array_t[4][3][2];
`endif
typedef real real_t;
typedef real_t real_array_t[4][3][2];
`ifndef NO_SHORTREAL
typedef shortreal shortreal_t;
typedef shortreal_t shortreal_array_t[4][3][2];
`endif
typedef chandle chandle_t;
typedef chandle_t chandle_array_t[4][3][2];
typedef string string_t;
typedef string_t string_array_t[4][3][2];
typedef bit bit1_t;
typedef bit1_t bit1_array_t[4][3][2];
typedef bit [6:0] bit7_t;
typedef bit7_t bit7_array_t[4][3][2];
typedef bit [120:0] bit121_t;
typedef bit121_t bit121_array_t[4][3][2];
typedef logic logic1_t;
typedef logic1_t logic1_array_t[4][3][2];
typedef logic [6:0] logic7_t;
typedef logic7_t logic7_array_t[4][3][2];
typedef logic [120:0] logic121_t;
typedef logic121_t logic121_array_t[4][3][2];
typedef struct packed {
logic [6:0] val;
} pack_struct_t;
typedef pack_struct_t pack_struct_array_t[4][3][2];
`ifndef NO_UNPACK_STRUCT
typedef struct {
logic [120:0] val;
} unpack_struct_t;
typedef unpack_struct_t unpack_struct_array_t[4][3][2];
`endif
//======================================================================
// Imports
//======================================================================
// Returns non-null pointer
import "DPI-C" function chandle get_non_null();
import "DPI-C" function void i_byte_0d(inout byte_t val);
import "DPI-C" function void i_byte_1d(inout byte_t val[2]);
import "DPI-C" function void i_byte_2d(inout byte_t val[3][2]);
import "DPI-C" function void i_byte_3d(inout byte_array_t val);
import "DPI-C" function void i_byte_unsigned_0d(inout byte unsigned val);
import "DPI-C" function void i_byte_unsigned_1d(inout byte unsigned val[2]);
import "DPI-C" function void i_byte_unsigned_2d(inout byte unsigned val[3][2]);
import "DPI-C" function void i_byte_unsigned_3d(inout byte_unsigned_array_t val);
import "DPI-C" function void i_shortint_0d(inout shortint val);
import "DPI-C" function void i_shortint_1d(inout shortint val[2]);
import "DPI-C" function void i_shortint_2d(inout shortint val[3][2]);
import "DPI-C" function void i_shortint_3d(inout shortint_array_t val);
import "DPI-C" function void i_shortint_unsigned_0d(inout shortint unsigned val);
import "DPI-C" function void i_shortint_unsigned_1d(inout shortint unsigned val[2]);
import "DPI-C" function void i_shortint_unsigned_2d(inout shortint unsigned val[3][2]);
import "DPI-C" function void i_shortint_unsigned_3d(inout shortint_unsigned_array_t val);
import "DPI-C" function void i_int_0d(inout int val);
import "DPI-C" function void i_int_1d(inout int val[2]);
import "DPI-C" function void i_int_2d(inout int val[3][2]);
import "DPI-C" function void i_int_3d(inout int_array_t val);
import "DPI-C" function void i_int_unsigned_0d(inout int unsigned val);
import "DPI-C" function void i_int_unsigned_1d(inout int unsigned val[2]);
import "DPI-C" function void i_int_unsigned_2d(inout int unsigned val[3][2]);
import "DPI-C" function void i_int_unsigned_3d(inout int_unsigned_array_t val);
import "DPI-C" function void i_longint_0d(inout longint val);
import "DPI-C" function void i_longint_1d(inout longint val[2]);
import "DPI-C" function void i_longint_2d(inout longint val[3][2]);
import "DPI-C" function void i_longint_3d(inout longint_array_t val);
import "DPI-C" function void i_longint_unsigned_0d(inout longint unsigned val);
import "DPI-C" function void i_longint_unsigned_1d(inout longint unsigned val[2]);
import "DPI-C" function void i_longint_unsigned_2d(inout longint unsigned val[3][2]);
import "DPI-C" function void i_longint_unsigned_3d(inout longint_unsigned_array_t val);
`ifndef NO_TIME
import "DPI-C" function void i_time_0d(inout time val);
import "DPI-C" function void i_time_1d(inout time val[2]);
import "DPI-C" function void i_time_2d(inout time val[3][2]);
import "DPI-C" function void i_time_3d(inout time_array_t val);
`endif
`ifndef NO_INTEGER
import "DPI-C" function void i_integer_0d(inout integer val);
import "DPI-C" function void i_integer_1d(inout integer val[2]);
import "DPI-C" function void i_integer_2d(inout integer val[3][2]);
import "DPI-C" function void i_integer_3d(inout integer_array_t val);
`endif
import "DPI-C" function void i_real_0d(inout real val);
import "DPI-C" function void i_real_1d(inout real val[2]);
import "DPI-C" function void i_real_2d(inout real val[3][2]);
import "DPI-C" function void i_real_3d(inout real_array_t val);
`ifndef NO_SHORTREAL
import "DPI-C" function void i_shortreal_0d(inout shortreal val);
import "DPI-C" function void i_shortreal_1d(inout shortreal val[2]);
import "DPI-C" function void i_shortreal_2d(inout shortreal val[3][2]);
import "DPI-C" function void i_shortreal_3d(inout shortreal_array_t val);
`endif
import "DPI-C" function void i_chandle_0d(inout chandle val);
import "DPI-C" function void i_chandle_1d(inout chandle val[2]);
import "DPI-C" function void i_chandle_2d(inout chandle val[3][2]);
import "DPI-C" function void i_chandle_3d(inout chandle_array_t val);
import "DPI-C" function void i_string_0d(inout string val);
import "DPI-C" function void i_string_1d(inout string val[2]);
import "DPI-C" function void i_string_2d(inout string val[3][2]);
import "DPI-C" function void i_string_3d(inout string_array_t val);
import "DPI-C" function void i_bit1_0d(inout bit val);
import "DPI-C" function void i_bit1_1d(inout bit val[2]);
import "DPI-C" function void i_bit1_2d(inout bit val[3][2]);
import "DPI-C" function void i_bit1_3d(inout bit1_array_t val);
import "DPI-C" function void i_bit7_0d(inout bit[6:0] val);
import "DPI-C" function void i_bit7_1d(inout bit[6:0] val[2]);
import "DPI-C" function void i_bit7_2d(inout bit[6:0] val[3][2]);
import "DPI-C" function void i_bit7_3d(inout bit7_array_t val);
import "DPI-C" function void i_bit121_0d(inout bit[120:0] val);
import "DPI-C" function void i_bit121_1d(inout bit[120:0] val[2]);
import "DPI-C" function void i_bit121_2d(inout bit[120:0] val[3][2]);
import "DPI-C" function void i_bit121_3d(inout bit121_array_t val);
import "DPI-C" function void i_logic1_0d(inout logic val);
import "DPI-C" function void i_logic1_1d(inout logic val[2]);
import "DPI-C" function void i_logic1_2d(inout logic val[3][2]);
import "DPI-C" function void i_logic1_3d(inout logic1_array_t val);
import "DPI-C" function void i_logic7_0d(inout logic[6:0] val);
import "DPI-C" function void i_logic7_1d(inout logic[6:0] val[2]);
import "DPI-C" function void i_logic7_2d(inout logic[6:0] val[3][2]);
import "DPI-C" function void i_logic7_3d(inout logic7_array_t val);
import "DPI-C" function void i_logic121_0d(inout logic[120:0] val);
import "DPI-C" function void i_logic121_1d(inout logic[120:0] val[2]);
import "DPI-C" function void i_logic121_2d(inout logic[120:0] val[3][2]);
import "DPI-C" function void i_logic121_3d(inout logic121_array_t val);
import "DPI-C" function void i_pack_struct_0d(inout pack_struct_t val);
import "DPI-C" function void i_pack_struct_1d(inout pack_struct_t val[2]);
import "DPI-C" function void i_pack_struct_2d(inout pack_struct_t val[3][2]);
import "DPI-C" function void i_pack_struct_3d(inout pack_struct_array_t val);
`ifndef NO_UNPACK_STRUCT
import "DPI-C" function void i_unpack_struct_0d(inout unpack_struct_t val);
import "DPI-C" function void i_unpack_struct_1d(inout unpack_struct_t val[2]);
import "DPI-C" function void i_unpack_struct_2d(inout unpack_struct_t val[3][2]);
import "DPI-C" function void i_unpack_struct_3d(inout unpack_struct_array_t val);
`endif
//======================================================================
// Exports
//======================================================================
export "DPI-C" function e_byte_0d;
export "DPI-C" function e_byte_1d;
export "DPI-C" function e_byte_2d;
export "DPI-C" function e_byte_3d;
export "DPI-C" function e_byte_unsigned_0d;
export "DPI-C" function e_byte_unsigned_1d;
export "DPI-C" function e_byte_unsigned_2d;
export "DPI-C" function e_byte_unsigned_3d;
export "DPI-C" function e_shortint_0d;
export "DPI-C" function e_shortint_1d;
export "DPI-C" function e_shortint_2d;
export "DPI-C" function e_shortint_3d;
export "DPI-C" function e_shortint_unsigned_0d;
export "DPI-C" function e_shortint_unsigned_1d;
export "DPI-C" function e_shortint_unsigned_2d;
export "DPI-C" function e_shortint_unsigned_3d;
export "DPI-C" function e_int_0d;
export "DPI-C" function e_int_1d;
export "DPI-C" function e_int_2d;
export "DPI-C" function e_int_3d;
export "DPI-C" function e_int_unsigned_0d;
export "DPI-C" function e_int_unsigned_1d;
export "DPI-C" function e_int_unsigned_2d;
export "DPI-C" function e_int_unsigned_3d;
export "DPI-C" function e_longint_0d;
export "DPI-C" function e_longint_1d;
export "DPI-C" function e_longint_2d;
export "DPI-C" function e_longint_3d;
export "DPI-C" function e_longint_unsigned_0d;
export "DPI-C" function e_longint_unsigned_1d;
export "DPI-C" function e_longint_unsigned_2d;
export "DPI-C" function e_longint_unsigned_3d;
`ifndef NO_TIME
export "DPI-C" function e_time_0d;
export "DPI-C" function e_time_1d;
export "DPI-C" function e_time_2d;
export "DPI-C" function e_time_3d;
`endif
`ifndef NO_INTEGER
export "DPI-C" function e_integer_0d;
export "DPI-C" function e_integer_1d;
export "DPI-C" function e_integer_2d;
export "DPI-C" function e_integer_3d;
`endif
export "DPI-C" function e_real_0d;
export "DPI-C" function e_real_1d;
export "DPI-C" function e_real_2d;
export "DPI-C" function e_real_3d;
`ifndef NO_SHORTREAL
export "DPI-C" function e_shortreal_0d;
export "DPI-C" function e_shortreal_1d;
export "DPI-C" function e_shortreal_2d;
export "DPI-C" function e_shortreal_3d;
`endif
export "DPI-C" function e_chandle_0d;
export "DPI-C" function e_chandle_1d;
export "DPI-C" function e_chandle_2d;
export "DPI-C" function e_chandle_3d;
export "DPI-C" function e_string_0d;
export "DPI-C" function e_string_1d;
export "DPI-C" function e_string_2d;
export "DPI-C" function e_string_3d;
export "DPI-C" function e_bit1_0d;
export "DPI-C" function e_bit1_1d;
export "DPI-C" function e_bit1_2d;
export "DPI-C" function e_bit1_3d;
export "DPI-C" function e_bit7_0d;
export "DPI-C" function e_bit7_1d;
export "DPI-C" function e_bit7_2d;
export "DPI-C" function e_bit7_3d;
export "DPI-C" function e_bit121_0d;
export "DPI-C" function e_bit121_1d;
export "DPI-C" function e_bit121_2d;
export "DPI-C" function e_bit121_3d;
export "DPI-C" function e_logic1_0d;
export "DPI-C" function e_logic1_1d;
export "DPI-C" function e_logic1_2d;
export "DPI-C" function e_logic1_3d;
export "DPI-C" function e_logic7_0d;
export "DPI-C" function e_logic7_1d;
export "DPI-C" function e_logic7_2d;
export "DPI-C" function e_logic7_3d;
export "DPI-C" function e_logic121_0d;
export "DPI-C" function e_logic121_1d;
export "DPI-C" function e_logic121_2d;
export "DPI-C" function e_logic121_3d;
export "DPI-C" function e_pack_struct_0d;
export "DPI-C" function e_pack_struct_1d;
export "DPI-C" function e_pack_struct_2d;
export "DPI-C" function e_pack_struct_3d;
`ifndef NO_UNPACK_STRUCT
export "DPI-C" function e_unpack_struct_0d;
export "DPI-C" function e_unpack_struct_1d;
export "DPI-C" function e_unpack_struct_2d;
export "DPI-C" function e_unpack_struct_3d;
`endif
//======================================================================
// Definitions of exported functions
//======================================================================
function void e_byte_0d(inout byte val); `UPDATE_0D(val); endfunction
function void e_byte_1d(inout byte val[2]); `UPDATE_1D(val); endfunction
function void e_byte_2d(inout byte val[3][2]); `UPDATE_2D(val); endfunction
function void e_byte_3d(inout byte_array_t val); `UPDATE_3D(val); endfunction
function void e_byte_unsigned_0d(inout byte unsigned val); `UPDATE_0D(val); endfunction
function void e_byte_unsigned_1d(inout byte unsigned val[2]); `UPDATE_1D(val); endfunction
function void e_byte_unsigned_2d(inout byte unsigned val[3][2]); `UPDATE_2D(val); endfunction
function void e_byte_unsigned_3d(inout byte_unsigned_array_t val); `UPDATE_3D(val); endfunction
function void e_shortint_0d(inout shortint val); `UPDATE_0D(val); endfunction
function void e_shortint_1d(inout shortint val[2]); `UPDATE_1D(val); endfunction
function void e_shortint_2d(inout shortint val[3][2]); `UPDATE_2D(val); endfunction
function void e_shortint_3d(inout shortint_array_t val); `UPDATE_3D(val); endfunction
function void e_shortint_unsigned_0d(inout shortint unsigned val); `UPDATE_0D(val); endfunction
function void e_shortint_unsigned_1d(inout shortint unsigned val[2]); `UPDATE_1D(val); endfunction
function void e_shortint_unsigned_2d(inout shortint unsigned val[3][2]); `UPDATE_2D(val); endfunction
function void e_shortint_unsigned_3d(inout shortint_unsigned_array_t val); `UPDATE_3D(val); endfunction
function void e_int_0d(inout int val); `UPDATE_0D(val); endfunction
function void e_int_1d(inout int val[2]); `UPDATE_1D(val); endfunction
function void e_int_2d(inout int val[3][2]); `UPDATE_2D(val); endfunction
function void e_int_3d(inout int_array_t val); `UPDATE_3D(val); endfunction
function void e_int_unsigned_0d(inout int unsigned val); `UPDATE_0D(val); endfunction
function void e_int_unsigned_1d(inout int unsigned val[2]); `UPDATE_1D(val); endfunction
function void e_int_unsigned_2d(inout int unsigned val[3][2]); `UPDATE_2D(val); endfunction
function void e_int_unsigned_3d(inout int_unsigned_array_t val); `UPDATE_3D(val); endfunction
function void e_longint_0d(inout longint val); `UPDATE_0D(val); endfunction
function void e_longint_1d(inout longint val[2]); `UPDATE_1D(val); endfunction
function void e_longint_2d(inout longint val[3][2]); `UPDATE_2D(val); endfunction
function void e_longint_3d(inout longint_array_t val); `UPDATE_3D(val); endfunction
function void e_longint_unsigned_0d(inout longint unsigned val); `UPDATE_0D(val); endfunction
function void e_longint_unsigned_1d(inout longint unsigned val[2]); `UPDATE_1D(val); endfunction
function void e_longint_unsigned_2d(inout longint unsigned val[3][2]); `UPDATE_2D(val); endfunction
function void e_longint_unsigned_3d(inout longint_unsigned_array_t val); `UPDATE_3D(val); endfunction
`ifndef NO_TIME
function void e_time_0d(inout time val); `UPDATE_0D(val); endfunction
function void e_time_1d(inout time val[2]); `UPDATE_1D(val); endfunction
function void e_time_2d(inout time val[3][2]); `UPDATE_2D(val); endfunction
function void e_time_3d(inout time_array_t val); `UPDATE_3D(val); endfunction
`endif
`ifndef NO_INTEGER
function void e_integer_0d(inout integer val); `UPDATE_0D(val); endfunction
function void e_integer_1d(inout integer val[2]); `UPDATE_1D(val); endfunction
function void e_integer_2d(inout integer val[3][2]); `UPDATE_2D(val); endfunction
function void e_integer_3d(inout integer_array_t val); `UPDATE_3D(val); endfunction
`endif
function void e_real_0d(inout real val); `UPDATE_0D(val); endfunction
function void e_real_1d(inout real val[2]); `UPDATE_1D(val); endfunction
function void e_real_2d(inout real val[3][2]); `UPDATE_2D(val); endfunction
function void e_real_3d(inout real_array_t val); `UPDATE_3D(val); endfunction
`ifndef NO_SHORTREAL
function void e_shortreal_0d(inout shortreal val); `UPDATE_0D(val); endfunction
function void e_shortreal_1d(inout shortreal val[2]); `UPDATE_1D(val); endfunction
function void e_shortreal_2d(inout shortreal val[3][2]); `UPDATE_2D(val); endfunction
function void e_shortreal_3d(inout shortreal_array_t val); `UPDATE_3D(val); endfunction
`endif
function void e_chandle_0d(inout chandle val);
`CHECK_CHANDLE_VAL(val, get_non_null());
val = null;
endfunction
function void e_chandle_1d(inout chandle val[2]);
`CHECK_CHANDLE_VAL(val[0], get_non_null());
`CHECK_CHANDLE_VAL(val[1], get_non_null());
val[0] = null;
val[1] = null;
endfunction
function void e_chandle_2d(inout chandle val[3][2]);
`CHECK_CHANDLE_VAL(val[0][1], get_non_null());
`CHECK_CHANDLE_VAL(val[1][1], get_non_null());
`CHECK_CHANDLE_VAL(val[2][1], get_non_null());
val[0][1] = null;
val[1][1] = null;
val[2][1] = null;
endfunction
function void e_chandle_3d(inout chandle_array_t val);
`CHECK_CHANDLE_VAL(val[0][0][0], get_non_null());
`CHECK_CHANDLE_VAL(val[1][0][0], get_non_null());
`CHECK_CHANDLE_VAL(val[2][0][0], get_non_null());
`CHECK_CHANDLE_VAL(val[3][0][0], get_non_null());
val[0][0][0] = null;
val[1][0][0] = null;
val[2][0][0] = null;
val[3][0][0] = null;
endfunction
function void e_string_0d(inout string val);
`CHECK_STRING_VAL(val, "42");
val = "43";
endfunction
function void e_string_1d(inout string val[2]);
`CHECK_STRING_VAL(val[0], "43");
`CHECK_STRING_VAL(val[1], "44");
val[0] = "44";
val[1] = "45";
endfunction
function void e_string_2d(inout string val[3][2]);
`CHECK_STRING_VAL(val[0][1], "45");
`CHECK_STRING_VAL(val[1][1], "46");
`CHECK_STRING_VAL(val[2][1], "47");
val[0][1] = "46";
val[1][1] = "47";
val[2][1] = "48";
endfunction
function void e_string_3d(inout string_array_t val);
`CHECK_STRING_VAL(val[0][0][0], "48");
`CHECK_STRING_VAL(val[1][0][0], "49");
`CHECK_STRING_VAL(val[2][0][0], "50");
`CHECK_STRING_VAL(val[3][0][0], "51");
val[0][0][0] = "49";
val[1][0][0] = "50";
val[2][0][0] = "51";
val[3][0][0] = "52";
endfunction
function void e_bit1_0d(inout bit val); `UPDATE_0D(val); endfunction
function void e_bit1_1d(inout bit val[2]); `UPDATE_1D(val); endfunction
function void e_bit1_2d(inout bit val[3][2]); `UPDATE_2D(val); endfunction
function void e_bit1_3d(inout bit1_array_t val); `UPDATE_3D(val); endfunction
function void e_bit7_0d(inout bit[6:0] val); `UPDATE_0D(val); endfunction
function void e_bit7_1d(inout bit[6:0] val[2]); `UPDATE_1D(val); endfunction
function void e_bit7_2d(inout bit[6:0] val[3][2]); `UPDATE_2D(val); endfunction
function void e_bit7_3d(inout bit7_array_t val); `UPDATE_3D(val); endfunction
function void e_bit121_0d(inout bit[120:0] val); `UPDATE_0D(val); endfunction
function void e_bit121_1d(inout bit[120:0] val[2]); `UPDATE_1D(val); endfunction
function void e_bit121_2d(inout bit[120:0] val[3][2]); `UPDATE_2D(val); endfunction
function void e_bit121_3d(inout bit121_array_t val); `UPDATE_3D(val); endfunction
function void e_logic1_0d(inout logic val); `UPDATE_0D(val); endfunction
function void e_logic1_1d(inout logic val[2]); `UPDATE_1D(val); endfunction
function void e_logic1_2d(inout logic val[3][2]); `UPDATE_2D(val); endfunction
function void e_logic1_3d(inout logic1_array_t val); `UPDATE_3D(val); endfunction
function void e_logic7_0d(inout logic[6:0] val); `UPDATE_0D(val); endfunction
function void e_logic7_1d(inout logic[6:0] val[2]); `UPDATE_1D(val); endfunction
function void e_logic7_2d(inout logic[6:0] val[3][2]); `UPDATE_2D(val); endfunction
function void e_logic7_3d(inout logic7_array_t val); `UPDATE_3D(val); endfunction
function void e_logic121_0d(inout logic[120:0] val); `UPDATE_0D(val); endfunction
function void e_logic121_1d(inout logic[120:0] val[2]); `UPDATE_1D(val); endfunction
function void e_logic121_2d(inout logic[120:0] val[3][2]); `UPDATE_2D(val); endfunction
function void e_logic121_3d(inout logic121_array_t val); `UPDATE_3D(val); endfunction
function void e_pack_struct_0d(inout pack_struct_t val); `UPDATE_0D(val); endfunction
function void e_pack_struct_1d(inout pack_struct_t val[2]); `UPDATE_1D(val); endfunction
function void e_pack_struct_2d(inout pack_struct_t val[3][2]); `UPDATE_2D(val); endfunction
function void e_pack_struct_3d(inout pack_struct_array_t val); `UPDATE_3D(val); endfunction
`ifndef NO_UNPACK_STRUCT
function void e_unpack_struct_0d(inout unpack_struct_t val);
`CHECK_VAL(val.val, 42);
val.val = 43;
endfunction
function void e_unpack_struct_1d(inout unpack_struct_t val[2]);
`CHECK_VAL(val[0].val, 43);
`CHECK_VAL(val[1].val, 44);
val[0].val = 44;
val[1].val = 45;
endfunction
function void e_unpack_struct_2d(inout unpack_struct_t val[3][2]);
`CHECK_VAL(val[0][1].val, 45);
`CHECK_VAL(val[1][1].val, 46);
`CHECK_VAL(val[2][1].val, 47);
val[0][1].val = 46;
val[1][1].val = 47;
val[2][1].val = 48;
endfunction
function void e_unpack_struct_3d(inout unpack_struct_array_t val);
`CHECK_VAL(val[0][0][0].val, 48);
`CHECK_VAL(val[1][0][0].val, 49);
`CHECK_VAL(val[2][0][0].val, 50);
`CHECK_VAL(val[3][0][0].val, 51);
val[0][0][0].val = 49;
val[1][0][0].val = 50;
val[2][0][0].val = 51;
val[3][0][0].val = 52;
endfunction
`endif
//======================================================================
// Invoke all imported functions
//======================================================================
import "DPI-C" context function void check_exports();
initial begin
byte_t byte_array_0d;
byte_t byte_array_1d[2];
byte_t byte_array_2d[3][2];
byte_array_t byte_array;
byte_unsigned_t byte_unsigned_array_0d;
byte_unsigned_t byte_unsigned_array_1d[2];
byte_unsigned_t byte_unsigned_array_2d[3][2];
byte_unsigned_array_t byte_unsigned_array;
shortint_t shortint_array_0d;
shortint_t shortint_array_1d[2];
shortint_t shortint_array_2d[3][2];
shortint_array_t shortint_array;
shortint_unsigned_t shortint_unsigned_array_0d;
shortint_unsigned_t shortint_unsigned_array_1d[2];
shortint_unsigned_t shortint_unsigned_array_2d[3][2];
shortint_unsigned_array_t shortint_unsigned_array;
int_t int_array_0d;
int_t int_array_1d[2];
int_t int_array_2d[3][2];
int_array_t int_array;
int_unsigned_t int_unsigned_array_0d;
int_unsigned_t int_unsigned_array_1d[2];
int_unsigned_t int_unsigned_array_2d[3][2];
int_unsigned_array_t int_unsigned_array;
longint_t longint_array_0d;
longint_t longint_array_1d[2];
longint_t longint_array_2d[3][2];
longint_array_t longint_array;
longint_unsigned_t longint_unsigned_array_0d;
longint_unsigned_t longint_unsigned_array_1d[2];
longint_unsigned_t longint_unsigned_array_2d[3][2];
longint_unsigned_array_t longint_unsigned_array;
`ifndef NO_TIME
time_t time_array_0d;
time_t time_array_1d[2];
time_t time_array_2d[3][2];
time_array_t time_array;
`endif
`ifndef NO_INTEGER
integer_t integer_array_0d;
integer_t integer_array_1d[2];
integer_t integer_array_2d[3][2];
integer_array_t integer_array;
`endif
real_t real_array_0d;
real_t real_array_1d[2];
real_t real_array_2d[3][2];
real_array_t real_array;
`ifndef NO_SHORTREAL
shortreal_t shortreal_array_0d;
shortreal_t shortreal_array_1d[2];
shortreal_t shortreal_array_2d[3][2];
shortreal_array_t shortreal_array;
`endif
chandle_t chandle_array_0d;
chandle_t chandle_array_1d[2];
chandle_t chandle_array_2d[3][2];
chandle_array_t chandle_array;
string_t string_array_0d;
string_t string_array_1d[2];
string_t string_array_2d[3][2];
string_array_t string_array;
bit1_t bit1_array_0d;
bit1_t bit1_array_1d[2];
bit1_t bit1_array_2d[3][2];
bit1_array_t bit1_array;
bit7_t bit7_array_0d;
bit7_t bit7_array_1d[2];
bit7_t bit7_array_2d[3][2];
bit7_array_t bit7_array;
bit121_t bit121_array_0d;
bit121_t bit121_array_1d[2];
bit121_t bit121_array_2d[3][2];
bit121_array_t bit121_array;
logic1_t logic1_array_0d;
logic1_t logic1_array_1d[2];
logic1_t logic1_array_2d[3][2];
logic1_array_t logic1_array;
logic7_t logic7_array_0d;
logic7_t logic7_array_1d[2];
logic7_t logic7_array_2d[3][2];
logic7_array_t logic7_array;
logic121_t logic121_array_0d;
logic121_t logic121_array_1d[2];
logic121_t logic121_array_2d[3][2];
logic121_array_t logic121_array;
pack_struct_t pack_struct_array_0d;
pack_struct_t pack_struct_array_1d[2];
pack_struct_t pack_struct_array_2d[3][2];
pack_struct_array_t pack_struct_array;
`ifndef NO_UNPACK_STRUCT
unpack_struct_t unpack_struct_array_0d;
unpack_struct_t unpack_struct_array_1d[2];
unpack_struct_t unpack_struct_array_2d[3][2];
unpack_struct_array_t unpack_struct_array;
`endif
`SET_VALUES(byte_array);
`SET_VALUE_0D(byte_array_0d);
`SET_VALUE_1D(byte_array_1d);
`SET_VALUE_2D(byte_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_byte_0d(byte_array[3][2][1]);
`CHECK_0D(byte_array[3][2][1]);
i_byte_1d(byte_array[2][1]);
`CHECK_1D(byte_array[2][1]);
i_byte_2d(byte_array[1]);
`CHECK_2D(byte_array[1]);
`endif
i_byte_0d(byte_array_0d);
`CHECK_0D(byte_array_0d);
i_byte_1d(byte_array_1d);
`CHECK_1D(byte_array_1d);
i_byte_2d(byte_array_2d);
`CHECK_2D(byte_array_2d);
i_byte_3d(byte_array);
`CHECK_3D(byte_array);
`SET_VALUES(byte_unsigned_array);
`SET_VALUE_0D(byte_unsigned_array_0d);
`SET_VALUE_1D(byte_unsigned_array_1d);
`SET_VALUE_2D(byte_unsigned_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_byte_unsigned_0d(byte_unsigned_array[3][2][1]);
`CHECK_0D(byte_unsigned_array[3][2][1]);
i_byte_unsigned_1d(byte_unsigned_array[2][1]);
`CHECK_1D(byte_unsigned_array[2][1]);
i_byte_unsigned_2d(byte_unsigned_array[1]);
`CHECK_2D(byte_unsigned_array[1]);
`endif
i_byte_unsigned_0d(byte_unsigned_array_0d);
`CHECK_0D(byte_unsigned_array_0d);
i_byte_unsigned_1d(byte_unsigned_array_1d);
`CHECK_1D(byte_unsigned_array_1d);
i_byte_unsigned_2d(byte_unsigned_array_2d);
`CHECK_2D(byte_unsigned_array_2d);
i_byte_unsigned_3d(byte_unsigned_array);
`CHECK_3D(byte_unsigned_array);
`SET_VALUES(shortint_array);
`SET_VALUE_0D(shortint_array_0d);
`SET_VALUE_1D(shortint_array_1d);
`SET_VALUE_2D(shortint_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_shortint_0d(shortint_array[3][2][1]);
`CHECK_0D(shortint_array[3][2][1]);
i_shortint_1d(shortint_array[2][1]);
`CHECK_1D(shortint_array[2][1]);
i_shortint_2d(shortint_array[1]);
`CHECK_2D(shortint_array[1]);
`endif
i_shortint_0d(shortint_array_0d);
`CHECK_0D(shortint_array_0d);
i_shortint_1d(shortint_array_1d);
`CHECK_1D(shortint_array_1d);
i_shortint_2d(shortint_array_2d);
`CHECK_2D(shortint_array_2d);
i_shortint_3d(shortint_array);
`CHECK_3D(shortint_array);
`SET_VALUES(shortint_unsigned_array);
`SET_VALUE_0D(shortint_unsigned_array_0d);
`SET_VALUE_1D(shortint_unsigned_array_1d);
`SET_VALUE_2D(shortint_unsigned_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_shortint_unsigned_0d(shortint_unsigned_array[3][2][1]);
`CHECK_0D(shortint_unsigned_array[3][2][1]);
i_shortint_unsigned_1d(shortint_unsigned_array[2][1]);
`CHECK_1D(shortint_unsigned_array[2][1]);
i_shortint_unsigned_2d(shortint_unsigned_array[1]);
`CHECK_2D(shortint_unsigned_array[1]);
`endif
i_shortint_unsigned_0d(shortint_unsigned_array_0d);
`CHECK_0D(shortint_unsigned_array_0d);
i_shortint_unsigned_1d(shortint_unsigned_array_1d);
`CHECK_1D(shortint_unsigned_array_1d);
i_shortint_unsigned_2d(shortint_unsigned_array_2d);
`CHECK_2D(shortint_unsigned_array_2d);
i_shortint_unsigned_3d(shortint_unsigned_array);
`CHECK_3D(shortint_unsigned_array);
`SET_VALUES(int_array);
`SET_VALUE_0D(int_array_0d);
`SET_VALUE_1D(int_array_1d);
`SET_VALUE_2D(int_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_int_0d(int_array[3][2][1]);
`CHECK_0D(int_array[3][2][1]);
i_int_1d(int_array[2][1]);
`CHECK_1D(int_array[2][1]);
i_int_2d(int_array[1]);
`CHECK_2D(int_array[1]);
`endif
i_int_0d(int_array_0d);
`CHECK_0D(int_array_0d);
i_int_1d(int_array_1d);
`CHECK_1D(int_array_1d);
i_int_2d(int_array_2d);
`CHECK_2D(int_array_2d);
i_int_3d(int_array);
`CHECK_3D(int_array);
`SET_VALUES(int_unsigned_array);
`SET_VALUE_0D(int_unsigned_array_0d);
`SET_VALUE_1D(int_unsigned_array_1d);
`SET_VALUE_2D(int_unsigned_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_int_unsigned_0d(int_unsigned_array[3][2][1]);
`CHECK_0D(int_unsigned_array[3][2][1]);
i_int_unsigned_1d(int_unsigned_array[2][1]);
`CHECK_1D(int_unsigned_array[2][1]);
i_int_unsigned_2d(int_unsigned_array[1]);
`CHECK_2D(int_unsigned_array[1]);
`endif
i_int_unsigned_0d(int_unsigned_array_0d);
`CHECK_0D(int_unsigned_array_0d);
i_int_unsigned_1d(int_unsigned_array_1d);
`CHECK_1D(int_unsigned_array_1d);
i_int_unsigned_2d(int_unsigned_array_2d);
`CHECK_2D(int_unsigned_array_2d);
i_int_unsigned_3d(int_unsigned_array);
`CHECK_3D(int_unsigned_array);
`SET_VALUES(longint_array);
`SET_VALUE_0D(longint_array_0d);
`SET_VALUE_1D(longint_array_1d);
`SET_VALUE_2D(longint_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_longint_0d(longint_array[3][2][1]);
`CHECK_0D(longint_array[3][2][1]);
i_longint_1d(longint_array[2][1]);
`CHECK_1D(longint_array[2][1]);
i_longint_2d(longint_array[1]);
`CHECK_2D(longint_array[1]);
`endif
i_longint_0d(longint_array_0d);
`CHECK_0D(longint_array_0d);
i_longint_1d(longint_array_1d);
`CHECK_1D(longint_array_1d);
i_longint_2d(longint_array_2d);
`CHECK_2D(longint_array_2d);
i_longint_3d(longint_array);
`CHECK_3D(longint_array);
`SET_VALUES(longint_unsigned_array);
`SET_VALUE_0D(longint_unsigned_array_0d);
`SET_VALUE_1D(longint_unsigned_array_1d);
`SET_VALUE_2D(longint_unsigned_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_longint_unsigned_0d(longint_unsigned_array[3][2][1]);
`CHECK_0D(longint_unsigned_array[3][2][1]);
i_longint_unsigned_1d(longint_unsigned_array[2][1]);
`CHECK_1D(longint_unsigned_array[2][1]);
i_longint_unsigned_2d(longint_unsigned_array[1]);
`CHECK_2D(longint_unsigned_array[1]);
`endif
i_longint_unsigned_0d(longint_unsigned_array_0d);
`CHECK_0D(longint_unsigned_array_0d);
i_longint_unsigned_1d(longint_unsigned_array_1d);
`CHECK_1D(longint_unsigned_array_1d);
i_longint_unsigned_2d(longint_unsigned_array_2d);
`CHECK_2D(longint_unsigned_array_2d);
i_longint_unsigned_3d(longint_unsigned_array);
`CHECK_3D(longint_unsigned_array);
`ifndef NO_TIME
`SET_VALUES(time_array);
`SET_VALUE_0D(time_array_0d);
`SET_VALUE_1D(time_array_1d);
`SET_VALUE_2D(time_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_time_0d(time_array[3][2][1]);
`CHECK_0D(time_array[3][2][1]);
i_time_1d(time_array[2][1]);
`CHECK_1D(time_array[2][1]);
i_time_2d(time_array[1]);
`CHECK_2D(time_array[1]);
`endif
i_time_0d(time_array_0d);
`CHECK_0D(time_array_0d);
i_time_1d(time_array_1d);
`CHECK_1D(time_array_1d);
i_time_2d(time_array_2d);
`CHECK_2D(time_array_2d);
i_time_3d(time_array);
`CHECK_3D(time_array);
`endif
`ifndef NO_INTEGER
`SET_VALUES(integer_array);
`SET_VALUE_0D(integer_array_0d);
`SET_VALUE_1D(integer_array_1d);
`SET_VALUE_2D(integer_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_integer_0d(integer_array[3][2][1]);
`CHECK_0D(integer_array[3][2][1]);
i_integer_1d(integer_array[2][1]);
`CHECK_1D(integer_array[2][1]);
i_integer_2d(integer_array[1]);
`CHECK_2D(integer_array[1]);
`endif
i_integer_0d(integer_array_0d);
`CHECK_0D(integer_array_0d);
i_integer_1d(integer_array_1d);
`CHECK_1D(integer_array_1d);
i_integer_2d(integer_array_2d);
`CHECK_2D(integer_array_2d);
i_integer_3d(integer_array);
`CHECK_3D(integer_array);
`endif
`SET_VALUES(real_array);
`SET_VALUE_0D(real_array_0d);
`SET_VALUE_1D(real_array_1d);
`SET_VALUE_2D(real_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_real_0d(real_array[3][2][1]);
`CHECK_DOUBLE_0D(real_array[3][2][1]);
i_real_1d(real_array[2][1]);
`CHECK_DOUBLE_1D(real_array[2][1]);
i_real_2d(real_array[1]);
`CHECK_DOUBLE_2D(real_array[1]);
`endif
i_real_0d(real_array_0d);
`CHECK_DOUBLE_0D(real_array_0d);
i_real_1d(real_array_1d);
`CHECK_DOUBLE_1D(real_array_1d);
i_real_2d(real_array_2d);
`CHECK_DOUBLE_2D(real_array_2d);
i_real_3d(real_array);
`CHECK_DOUBLE_3D(real_array);
`ifndef NO_SHORTREAL
`SET_VALUES(shortreal_array);
`SET_VALUE_0D(shortreal_array_0d);
`SET_VALUE_1D(shortreal_array_1d);
`SET_VALUE_2D(shortreal_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_shortreal_0d(shortreal_array[3][2][1]);
`CHECK_DOUBLE_0D(shortreal_array[3][2][1]);
i_shortreal_1d(shortreal_array[2][1]);
`CHECK_DOUBLE_1D(shortreal_array[2][1]);
i_shortreal_2d(shortreal_array[1]);
`CHECK_DOUBLE_2D(shortreal_array[1]);
`endif
i_shortreal_0d(shortreal_array_0d);
`CHECK_DOUBLE_0D(shortreal_array_0d);
i_shortreal_1d(shortreal_array_1d);
`CHECK_DOUBLE_1D(shortreal_array_1d);
i_shortreal_2d(shortreal_array_2d);
`CHECK_DOUBLE_2D(shortreal_array_2d);
i_shortreal_3d(shortreal_array);
`CHECK_DOUBLE_3D(shortreal_array);
`endif
for (int i = 0; i < 4; ++i)
for (int j = 0; j < 3; ++j)
for (int k = 0; k < 2; ++k)
chandle_array[i][j][k] = null;
`ifndef NO_INOUT_COMPLEX_TYPE
i_chandle_0d(chandle_array[3][2][1]);
`CHECK_CHANDLE_VAL(chandle_array[3][2][1], get_non_null());
i_chandle_1d(chandle_array[2][1]);
`CHECK_CHANDLE_VAL(chandle_array[2][1][0], get_non_null());
`CHECK_CHANDLE_VAL(chandle_array[2][1][1], get_non_null());
i_chandle_2d(chandle_array[1]);
`CHECK_CHANDLE_VAL(chandle_array[1][0][1], get_non_null());
`CHECK_CHANDLE_VAL(chandle_array[1][1][1], get_non_null());
`CHECK_CHANDLE_VAL(chandle_array[1][2][1], get_non_null());
`endif
chandle_array_0d = null;
i_chandle_0d(chandle_array_0d);
`CHECK_CHANDLE_VAL(chandle_array_0d, get_non_null());
chandle_array_1d[0] = null;
chandle_array_1d[1] = null;
i_chandle_1d(chandle_array_1d);
`CHECK_CHANDLE_VAL(chandle_array_1d[0], get_non_null());
`CHECK_CHANDLE_VAL(chandle_array_1d[1], get_non_null());
chandle_array_2d[0][1] = null;
chandle_array_2d[1][1] = null;
chandle_array_2d[2][1] = null;
i_chandle_2d(chandle_array_2d);
`CHECK_CHANDLE_VAL(chandle_array_2d[0][1], get_non_null());
`CHECK_CHANDLE_VAL(chandle_array_2d[1][1], get_non_null());
`CHECK_CHANDLE_VAL(chandle_array_2d[2][1], get_non_null());
i_chandle_3d(chandle_array);
`CHECK_CHANDLE_VAL(chandle_array[0][0][0], get_non_null());
`CHECK_CHANDLE_VAL(chandle_array[1][0][0], get_non_null());
`CHECK_CHANDLE_VAL(chandle_array[2][0][0], get_non_null());
`CHECK_CHANDLE_VAL(chandle_array[3][0][0], get_non_null());
`ifndef NO_INOUT_COMPLEX_TYPE
string_array[3][2][1] = "42";
i_string_0d(string_array[3][2][1]);
`CHECK_STRING_VAL(string_array[3][2][1], "43");
string_array[2][1][0] = "43";
string_array[2][1][1] = "44";
i_string_1d(string_array[2][1]);
`CHECK_STRING_VAL(string_array[2][1][0], "44");
`CHECK_STRING_VAL(string_array[2][1][1], "45");
string_array[1][0][1] = "45";
string_array[1][1][1] = "46";
string_array[1][2][1] = "47";
i_string_2d(string_array[1]);
`CHECK_STRING_VAL(string_array[1][0][1], "46");
`CHECK_STRING_VAL(string_array[1][1][1], "47");
`CHECK_STRING_VAL(string_array[1][2][1], "48");
`endif
string_array_0d = "42";
i_string_0d(string_array_0d);
`CHECK_STRING_VAL(string_array_0d, "43");
string_array_1d[0] = "43";
string_array_1d[1] = "44";
i_string_1d(string_array_1d);
`CHECK_STRING_VAL(string_array_1d[0], "44");
`CHECK_STRING_VAL(string_array_1d[1], "45");
string_array_2d[0][1] = "45";
string_array_2d[1][1] = "46";
string_array_2d[2][1] = "47";
i_string_2d(string_array_2d);
`CHECK_STRING_VAL(string_array_2d[0][1], "46");
`CHECK_STRING_VAL(string_array_2d[1][1], "47");
`CHECK_STRING_VAL(string_array_2d[2][1], "48");
string_array[0][0][0] = "48";
string_array[1][0][0] = "49";
string_array[2][0][0] = "50";
string_array[3][0][0] = "51";
i_string_3d(string_array);
`CHECK_STRING_VAL(string_array[0][0][0], "49");
`CHECK_STRING_VAL(string_array[1][0][0], "50");
`CHECK_STRING_VAL(string_array[2][0][0], "51");
`CHECK_STRING_VAL(string_array[3][0][0], "52");
`SET_VALUES(bit1_array);
`SET_VALUE_0D(bit1_array_0d);
`SET_VALUE_1D(bit1_array_1d);
`SET_VALUE_2D(bit1_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_bit1_0d(bit1_array[3][2][1]);
`CHECK_0D(bit1_array[3][2][1]);
i_bit1_1d(bit1_array[2][1]);
`CHECK_1D(bit1_array[2][1]);
i_bit1_2d(bit1_array[1]);
`CHECK_2D(bit1_array[1]);
`endif
i_bit1_0d(bit1_array_0d);
`CHECK_0D(bit1_array_0d);
i_bit1_1d(bit1_array_1d);
`CHECK_1D(bit1_array_1d);
i_bit1_2d(bit1_array_2d);
`CHECK_2D(bit1_array_2d);
i_bit1_3d(bit1_array);
`CHECK_3D(bit1_array);
`SET_VALUES(bit7_array);
`SET_VALUE_0D(bit7_array_0d);
`SET_VALUE_1D(bit7_array_1d);
`SET_VALUE_2D(bit7_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_bit7_0d(bit7_array[3][2][1]);
`CHECK_0D(bit7_array[3][2][1]);
i_bit7_1d(bit7_array[2][1]);
`CHECK_1D(bit7_array[2][1]);
i_bit7_2d(bit7_array[1]);
`CHECK_2D(bit7_array[1]);
`endif
i_bit7_0d(bit7_array_0d);
`CHECK_0D(bit7_array_0d);
i_bit7_1d(bit7_array_1d);
`CHECK_1D(bit7_array_1d);
i_bit7_2d(bit7_array_2d);
`CHECK_2D(bit7_array_2d);
i_bit7_3d(bit7_array);
`CHECK_3D(bit7_array);
`SET_VALUES(bit121_array);
`SET_VALUE_0D(bit121_array_0d);
`SET_VALUE_1D(bit121_array_1d);
`SET_VALUE_2D(bit121_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_bit121_0d(bit121_array[3][2][1]);
`CHECK_0D(bit121_array[3][2][1]);
i_bit121_1d(bit121_array[2][1]);
`CHECK_1D(bit121_array[2][1]);
i_bit121_2d(bit121_array[1]);
`CHECK_2D(bit121_array[1]);
`endif
i_bit121_0d(bit121_array_0d);
`CHECK_0D(bit121_array_0d);
i_bit121_1d(bit121_array_1d);
`CHECK_1D(bit121_array_1d);
i_bit121_2d(bit121_array_2d);
`CHECK_2D(bit121_array_2d);
i_bit121_3d(bit121_array);
`CHECK_3D(bit121_array);
`SET_VALUES(logic1_array);
`SET_VALUE_0D(logic1_array_0d);
`SET_VALUE_1D(logic1_array_1d);
`SET_VALUE_2D(logic1_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_logic1_0d(logic1_array[3][2][1]);
`CHECK_0D(logic1_array[3][2][1]);
i_logic1_1d(logic1_array[2][1]);
`CHECK_1D(logic1_array[2][1]);
i_logic1_2d(logic1_array[1]);
`CHECK_2D(logic1_array[1]);
`endif
i_logic1_0d(logic1_array_0d);
`CHECK_0D(logic1_array_0d);
i_logic1_1d(logic1_array_1d);
`CHECK_1D(logic1_array_1d);
i_logic1_2d(logic1_array_2d);
`CHECK_2D(logic1_array_2d);
i_logic1_3d(logic1_array);
`CHECK_3D(logic1_array);
`SET_VALUES(logic7_array);
`SET_VALUE_0D(logic7_array_0d);
`SET_VALUE_1D(logic7_array_1d);
`SET_VALUE_2D(logic7_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_logic7_0d(logic7_array[3][2][1]);
`CHECK_0D(logic7_array[3][2][1]);
i_logic7_1d(logic7_array[2][1]);
`CHECK_1D(logic7_array[2][1]);
i_logic7_2d(logic7_array[1]);
`CHECK_2D(logic7_array[1]);
`endif
i_logic7_0d(logic7_array_0d);
`CHECK_0D(logic7_array_0d);
i_logic7_1d(logic7_array_1d);
`CHECK_1D(logic7_array_1d);
i_logic7_2d(logic7_array_2d);
`CHECK_2D(logic7_array_2d);
i_logic7_3d(logic7_array);
`CHECK_3D(logic7_array);
`SET_VALUES(logic121_array);
`SET_VALUE_0D(logic121_array_0d);
`SET_VALUE_1D(logic121_array_1d);
`SET_VALUE_2D(logic121_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_logic121_0d(logic121_array[3][2][1]);
`CHECK_0D(logic121_array[3][2][1]);
i_logic121_1d(logic121_array[2][1]);
`CHECK_1D(logic121_array[2][1]);
i_logic121_2d(logic121_array[1]);
`CHECK_2D(logic121_array[1]);
`endif
i_logic121_0d(logic121_array_0d);
`CHECK_0D(logic121_array_0d);
i_logic121_1d(logic121_array_1d);
`CHECK_1D(logic121_array_1d);
i_logic121_2d(logic121_array_2d);
`CHECK_2D(logic121_array_2d);
i_logic121_3d(logic121_array);
`CHECK_3D(logic121_array);
`SET_VALUES(pack_struct_array);
`SET_VALUE_0D(pack_struct_array_0d);
`SET_VALUE_1D(pack_struct_array_1d);
`SET_VALUE_2D(pack_struct_array_2d);
`ifndef NO_INOUT_COMPLEX_TYPE
i_pack_struct_0d(pack_struct_array[3][2][1]);
`CHECK_0D(pack_struct_array[3][2][1]);
i_pack_struct_1d(pack_struct_array[2][1]);
`CHECK_1D(pack_struct_array[2][1]);
i_pack_struct_2d(pack_struct_array[1]);
`CHECK_2D(pack_struct_array[1]);
`endif
i_pack_struct_0d(pack_struct_array_0d);
`CHECK_0D(pack_struct_array_0d);
i_pack_struct_1d(pack_struct_array_1d);
`CHECK_1D(pack_struct_array_1d);
i_pack_struct_2d(pack_struct_array_2d);
`CHECK_2D(pack_struct_array_2d);
i_pack_struct_3d(pack_struct_array);
`CHECK_3D(pack_struct_array);
`ifndef NO_UNPACK_STRUCT
unpack_struct_array[3][2][1].val = 42;
i_unpack_struct_0d(unpack_struct_array[3][2][1]);
`CHECK_VAL(unpack_struct_array[3][2][1].val, 43);
unpack_struct_array[2][1][0].val = 43;
unpack_struct_array[2][1][1].val = 44;
i_unpack_struct_1d(unpack_struct_array[2][1]);
`CHECK_VAL(unpack_struct_array[2][1][0].val, 44);
`CHECK_VAL(unpack_struct_array[2][1][1].val, 45);
unpack_struct_array[1][0][1].val = 45;
unpack_struct_array[1][1][1].val = 46;
unpack_struct_array[1][2][1].val = 47;
i_unpack_struct_2d(unpack_struct_array[1]);
`CHECK_VAL(unpack_struct_array[1][0][1].val, 46);
`CHECK_VAL(unpack_struct_array[1][1][1].val, 47);
`CHECK_VAL(unpack_struct_array[1][2][1].val, 48);
unpack_struct_array[0][0][0].val = 48;
unpack_struct_array[1][0][0].val = 49;
unpack_struct_array[2][0][0].val = 50;
unpack_struct_array[3][0][0].val = 51;
i_unpack_struct_3d(unpack_struct_array);
`CHECK_VAL(unpack_struct_array[0][0][0].val, 49);
`CHECK_VAL(unpack_struct_array[1][0][0].val, 50);
`CHECK_VAL(unpack_struct_array[2][0][0].val, 51);
`CHECK_VAL(unpack_struct_array[3][0][0].val, 52);
`endif
check_exports();
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ps/1ps
module srio_gen2_0_srio_rst
(
input cfg_clk, // CFG interface clock
input log_clk, // LOG interface clock
input phy_clk, // PHY interface clock
input gt_pcs_clk, // GT Fabric interface clock
input sys_rst, // Global reset signal
input port_initialized, // Port is intialized
input phy_rcvd_link_reset, // Received 4 consecutive reset symbols
input force_reinit, // Force reinitialization
input clk_lock, // Indicates the MMCM has achieved a stable clock
output reg controlled_force_reinit, // Force reinitialization
output cfg_rst, // CFG dedicated reset
output log_rst, // LOG dedicated reset
output buf_rst, // BUF dedicated reset
output phy_rst, // PHY dedicated reset
output gt_pcs_rst // GT dedicated reset
);
// {{{ Parameter declarations -----------
// Reset State Machine
localparam IDLE = 4'b0001;
localparam LINKRESET = 4'b0010;
localparam PHY_RESET1 = 4'b0100;
localparam PHY_RESET2 = 4'b1000;
// }}} End Parameter declarations -------
wire sys_rst_buffered;
// {{{ wire declarations ----------------
reg [0:3] reset_state = IDLE;
reg [0:3] reset_next_state = IDLE;
(* ASYNC_REG = "TRUE" *)
reg [3:0] cfg_rst_srl;
(* ASYNC_REG = "TRUE" *)
reg [3:0] log_rst_srl;
(* ASYNC_REG = "TRUE" *)
reg [3:0] phy_rst_srl;
(* ASYNC_REG = "TRUE" *)
reg [3:0] gt_pcs_rst_srl;
reg sys_rst_int;
wire reset_condition = sys_rst || phy_rcvd_link_reset || sys_rst_int;
// }}} End wire declarations ------------
assign cfg_rst = cfg_rst_srl[3];
always @(posedge cfg_clk or posedge reset_condition) begin
if (reset_condition) begin
cfg_rst_srl <= 4'b1111;
end else if (clk_lock) begin
cfg_rst_srl <= {cfg_rst_srl[2:0], 1'b0};
end
end
assign log_rst = log_rst_srl[3];
always @(posedge log_clk or posedge reset_condition) begin
if (reset_condition) begin
log_rst_srl <= 4'b1111;
end else if (clk_lock) begin
log_rst_srl <= {log_rst_srl[2:0], 1'b0};
end
end
// The Buffer actively manages the reset due to the
// nature of the domain crossing being done in the buffer.
assign buf_rst = reset_condition;
assign phy_rst = phy_rst_srl[3];
always @(posedge phy_clk or posedge reset_condition) begin
if (reset_condition) begin
phy_rst_srl <= 4'b1111;
end else if (clk_lock) begin
phy_rst_srl <= {phy_rst_srl[2:0], 1'b0};
end
end
assign gt_pcs_rst = gt_pcs_rst_srl[3];
always @(posedge gt_pcs_clk or posedge reset_condition) begin
if (reset_condition) begin
gt_pcs_rst_srl <= 4'b1111;
end else if (clk_lock) begin
gt_pcs_rst_srl <= {gt_pcs_rst_srl[2:0], 1'b0};
end
end
// This controller is used to properly send link reset requests that were
// made by the user.
always@(posedge log_clk) begin
reset_state <= reset_next_state;
end
always @* begin
casex (reset_state)
IDLE: begin
// Current State Outputs
sys_rst_int = 1'b0;
controlled_force_reinit = 1'b0;
// Next State Outputs
if (force_reinit)
reset_next_state = LINKRESET;
else
reset_next_state = IDLE;
end
LINKRESET: begin
// Current State Outputs
sys_rst_int = 1'b0;
controlled_force_reinit = 1'b1;
// Next State Outputs
if (~port_initialized)
reset_next_state = PHY_RESET1;
else
reset_next_state = LINKRESET;
end
PHY_RESET1: begin
// Current State Outputs
sys_rst_int = 1'b1;
controlled_force_reinit = 1'b0;
// Next State Outputs
reset_next_state = PHY_RESET2;
end
PHY_RESET2: begin
// Current State Outputs
sys_rst_int = 1'b1;
controlled_force_reinit = 1'b0;
// Next State Outputs
if (force_reinit)
reset_next_state = PHY_RESET2;
else
reset_next_state = IDLE;
end
default: begin
// Current State Outputs
sys_rst_int = 1'b0;
controlled_force_reinit = 1'b0;
// Next State Outputs
reset_next_state = IDLE;
end
endcase
end
endmodule
// {{{ DISCLAIMER OF LIABILITY
// -----------------------------------------------------------------
// (c) Copyright 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// }}}
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninjasymbol.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ninjasymbol (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/ninjasymbol.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/ninjasymbol.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/ninjasymbol.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module qam_dem_top_mounstrito_cos_lut_rom (
addr0, ce0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 15;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./qam_dem_top_mounstrito_cos_lut_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module qam_dem_top_mounstrito_cos_lut(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd15;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
qam_dem_top_mounstrito_cos_lut_rom qam_dem_top_mounstrito_cos_lut_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
// megafunction wizard: %ALTFP_DIV%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_div
// ============================================================
// File Name: acl_fp_div.v
// Megafunction Name(s):
// altfp_div
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_div CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix IV" OPTIMIZE="SPEED" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock dataa datab result
//VERSION_BEGIN 11.0 cbx_altbarrel_shift 2011:04:27:21:07:19:SJ cbx_altfp_div 2011:04:27:21:07:19:SJ cbx_altsyncram 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_abs 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_divide 2011:04:27:21:07:19:SJ cbx_lpm_mult 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_padd 2011:04:27:21:07:19:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altfp_div_pst CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" FILE_NAME="acl_fp_div.v:a" PIPELINE=14 WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab result
//VERSION_BEGIN 11.0 cbx_altbarrel_shift 2011:04:27:21:07:19:SJ cbx_altfp_div 2011:04:27:21:07:19:SJ cbx_altsyncram 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_abs 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_divide 2011:04:27:21:07:19:SJ cbx_lpm_mult 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_padd 2011:04:27:21:07:19:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ VERSION_END
//synthesis_resources = altsyncram 1 lpm_add_sub 4 lpm_compare 1 lpm_mult 5 mux21 74 reg 847
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_div_altfp_div_pst_g1f
(
aclr,
clk_en,
clock,
dataa,
datab,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] wire_altsyncram3_q_a;
reg a_is_infinity_dffe_0;
reg a_is_infinity_dffe_1;
reg a_is_infinity_dffe_10;
reg a_is_infinity_dffe_11;
reg a_is_infinity_dffe_12;
reg a_is_infinity_dffe_2;
reg a_is_infinity_dffe_3;
reg a_is_infinity_dffe_4;
reg a_is_infinity_dffe_5;
reg a_is_infinity_dffe_6;
reg a_is_infinity_dffe_7;
reg a_is_infinity_dffe_8;
reg a_is_infinity_dffe_9;
reg a_zero_b_not_dffe_0;
reg a_zero_b_not_dffe_1;
reg a_zero_b_not_dffe_10;
reg a_zero_b_not_dffe_11;
reg a_zero_b_not_dffe_12;
reg a_zero_b_not_dffe_2;
reg a_zero_b_not_dffe_3;
reg a_zero_b_not_dffe_4;
reg a_zero_b_not_dffe_5;
reg a_zero_b_not_dffe_6;
reg a_zero_b_not_dffe_7;
reg a_zero_b_not_dffe_8;
reg a_zero_b_not_dffe_9;
reg [33:0] b1_dffe_0;
reg [33:0] b1_dffe_1;
reg b_is_infinity_dffe_0;
reg b_is_infinity_dffe_1;
reg b_is_infinity_dffe_10;
reg b_is_infinity_dffe_11;
reg b_is_infinity_dffe_12;
reg b_is_infinity_dffe_2;
reg b_is_infinity_dffe_3;
reg b_is_infinity_dffe_4;
reg b_is_infinity_dffe_5;
reg b_is_infinity_dffe_6;
reg b_is_infinity_dffe_7;
reg b_is_infinity_dffe_8;
reg b_is_infinity_dffe_9;
reg both_exp_zeros_dffe;
reg divbyzero_pipe_dffe_0;
reg divbyzero_pipe_dffe_1;
reg divbyzero_pipe_dffe_10;
reg divbyzero_pipe_dffe_11;
reg divbyzero_pipe_dffe_12;
reg divbyzero_pipe_dffe_2;
reg divbyzero_pipe_dffe_3;
reg divbyzero_pipe_dffe_4;
reg divbyzero_pipe_dffe_5;
reg divbyzero_pipe_dffe_6;
reg divbyzero_pipe_dffe_7;
reg divbyzero_pipe_dffe_8;
reg divbyzero_pipe_dffe_9;
reg [16:0] e1_dffe_0;
reg [16:0] e1_dffe_1;
reg [16:0] e1_dffe_perf_0;
reg [16:0] e1_dffe_perf_1;
reg [16:0] e1_dffe_perf_2;
reg [16:0] e1_dffe_perf_3;
reg [7:0] exp_result_dffe_0;
reg [7:0] exp_result_dffe_1;
reg [7:0] exp_result_dffe_10;
reg [7:0] exp_result_dffe_11;
reg [7:0] exp_result_dffe_2;
reg [7:0] exp_result_dffe_3;
reg [7:0] exp_result_dffe_4;
reg [7:0] exp_result_dffe_5;
reg [7:0] exp_result_dffe_6;
reg [7:0] exp_result_dffe_7;
reg [7:0] exp_result_dffe_8;
reg [7:0] exp_result_dffe_9;
reg frac_a_smaller_dffe1;
reg [22:0] man_a_dffe1_dffe1;
reg [22:0] man_b_dffe1_dffe1;
reg [22:0] man_result_dffe;
reg nan_pipe_dffe_0;
reg nan_pipe_dffe_1;
reg nan_pipe_dffe_10;
reg nan_pipe_dffe_11;
reg nan_pipe_dffe_12;
reg nan_pipe_dffe_2;
reg nan_pipe_dffe_3;
reg nan_pipe_dffe_4;
reg nan_pipe_dffe_5;
reg nan_pipe_dffe_6;
reg nan_pipe_dffe_7;
reg nan_pipe_dffe_8;
reg nan_pipe_dffe_9;
reg over_under_dffe_0;
reg over_under_dffe_1;
reg over_under_dffe_10;
reg over_under_dffe_2;
reg over_under_dffe_3;
reg over_under_dffe_4;
reg over_under_dffe_5;
reg over_under_dffe_6;
reg over_under_dffe_7;
reg over_under_dffe_8;
reg over_under_dffe_9;
reg [33:0] q_partial_perf_dffe_0;
reg [33:0] q_partial_perf_dffe_1;
reg [16:0] quotient_j_dffe;
reg [16:0] quotient_k_dffe_0;
reg [16:0] quotient_k_dffe_perf_0;
reg [16:0] quotient_k_dffe_perf_1;
reg [16:0] quotient_k_dffe_perf_2;
reg [16:0] quotient_k_dffe_perf_3;
reg [49:0] remainder_j_dffe_0;
reg [49:0] remainder_j_dffe_1;
reg [49:0] remainder_j_dffe_perf_0;
reg [49:0] remainder_j_dffe_perf_1;
reg [49:0] remainder_j_dffe_perf_2;
reg sign_pipe_dffe_0;
reg sign_pipe_dffe_1;
reg sign_pipe_dffe_10;
reg sign_pipe_dffe_11;
reg sign_pipe_dffe_12;
reg sign_pipe_dffe_13;
reg sign_pipe_dffe_2;
reg sign_pipe_dffe_3;
reg sign_pipe_dffe_4;
reg sign_pipe_dffe_5;
reg sign_pipe_dffe_6;
reg sign_pipe_dffe_7;
reg sign_pipe_dffe_8;
reg sign_pipe_dffe_9;
wire wire_bias_addition_overflow;
wire [8:0] wire_bias_addition_result;
wire [8:0] wire_exp_sub_result;
wire [30:0] wire_quotient_process_result;
wire [49:0] wire_remainder_sub_0_result;
wire wire_cmpr2_alb;
wire [34:0] wire_a1_prod_result;
wire [33:0] wire_b1_prod_result;
wire [33:0] wire_q_partial_0_result;
wire [33:0] wire_q_partial_1_result;
wire [50:0] wire_remainder_mult_0_result;
wire [7:0]wire_exp_result_muxa_dataout;
wire [24:0]wire_man_a_adjusteda_dataout;
wire [22:0]wire_man_result_muxa_dataout;
wire [8:0]wire_select_bias_2a_dataout;
wire [8:0]wire_select_biasa_dataout;
wire a_is_infinity_w;
wire a_is_nan_w;
wire a_zero_b_not;
wire [33:0] b1_dffe_w;
wire b_is_infinity_w;
wire b_is_nan_w;
wire bias_addition_overf_w;
wire [7:0] bias_addition_w;
wire both_exp_zeros;
wire [8:0] e0_dffe1_wo;
wire [8:0] e0_w;
wire [50:0] e1_w;
wire [7:0] exp_a_all_one_w;
wire [7:0] exp_a_not_zero_w;
wire [7:0] exp_add_output_all_one;
wire [7:0] exp_add_output_not_zero;
wire [7:0] exp_b_all_one_w;
wire [7:0] exp_b_not_zero_w;
wire [7:0] exp_result_mux_out;
wire exp_result_mux_sel_w;
wire [7:0] exp_result_w;
wire exp_sign_w;
wire [8:0] exp_sub_a_w;
wire [8:0] exp_sub_b_w;
wire [8:0] exp_sub_w;
wire frac_a_smaller_dffe1_wi;
wire frac_a_smaller_dffe1_wo;
wire frac_a_smaller_w;
wire guard_bit;
wire [24:0] man_a_adjusted_w;
wire [22:0] man_a_dffe1_wi;
wire [22:0] man_a_dffe1_wo;
wire [22:0] man_a_not_zero_w;
wire [23:0] man_b_adjusted_w;
wire [22:0] man_b_dffe1_wi;
wire [22:0] man_b_dffe1_wo;
wire [22:0] man_b_not_zero_w;
wire [22:0] man_result_dffe_wi;
wire [22:0] man_result_dffe_wo;
wire man_result_mux_select;
wire [22:0] man_result_w;
wire [22:0] man_zeros_w;
wire [7:0] overflow_ones_w;
wire overflow_underflow;
wire overflow_w;
wire [61:0] quotient_accumulate_w;
wire quotient_process_cin_w;
wire [99:0] remainder_j_w;
wire round_bit;
wire [8:0] select_bias_out_2_w;
wire [8:0] select_bias_out_w;
wire [4:0] sticky_bits;
wire underflow_w;
wire [7:0] underflow_zeros_w;
wire [8:0] value_add_one_w;
wire [8:0] value_normal_w;
wire [8:0] value_zero_w;
altsyncram altsyncram3
(
.address_a(datab[22:14]),
.clock0(clock),
.clocken0(clk_en),
.eccstatus(),
.q_a(wire_altsyncram3_q_a),
.q_b()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr0(1'b0),
.aclr1(1'b0),
.address_b({1{1'b1}}),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a({1{1'b1}}),
.byteena_b({1{1'b1}}),
.clock1(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_a({9{1'b1}}),
.data_b({1{1'b1}}),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_a(1'b0),
.wren_b(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
altsyncram3.init_file = "acl_fp_div.hex",
altsyncram3.operation_mode = "ROM",
altsyncram3.width_a = 9,
altsyncram3.widthad_a = 9,
altsyncram3.intended_device_family = "Stratix IV",
altsyncram3.lpm_type = "altsyncram";
// synopsys translate_off
initial
a_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_0 <= a_is_infinity_w;
// synopsys translate_off
initial
a_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_1 <= a_is_infinity_dffe_0;
// synopsys translate_off
initial
a_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_10 <= a_is_infinity_dffe_9;
// synopsys translate_off
initial
a_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_11 <= a_is_infinity_dffe_10;
// synopsys translate_off
initial
a_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_12 <= a_is_infinity_dffe_11;
// synopsys translate_off
initial
a_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_2 <= a_is_infinity_dffe_1;
// synopsys translate_off
initial
a_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_3 <= a_is_infinity_dffe_2;
// synopsys translate_off
initial
a_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_4 <= a_is_infinity_dffe_3;
// synopsys translate_off
initial
a_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_5 <= a_is_infinity_dffe_4;
// synopsys translate_off
initial
a_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_6 <= a_is_infinity_dffe_5;
// synopsys translate_off
initial
a_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_7 <= a_is_infinity_dffe_6;
// synopsys translate_off
initial
a_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_8 <= a_is_infinity_dffe_7;
// synopsys translate_off
initial
a_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_9 <= a_is_infinity_dffe_8;
// synopsys translate_off
initial
a_zero_b_not_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_0 <= a_zero_b_not;
// synopsys translate_off
initial
a_zero_b_not_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_1 <= a_zero_b_not_dffe_0;
// synopsys translate_off
initial
a_zero_b_not_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_10 <= a_zero_b_not_dffe_9;
// synopsys translate_off
initial
a_zero_b_not_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_11 <= a_zero_b_not_dffe_10;
// synopsys translate_off
initial
a_zero_b_not_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_12 <= a_zero_b_not_dffe_11;
// synopsys translate_off
initial
a_zero_b_not_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_2 <= a_zero_b_not_dffe_1;
// synopsys translate_off
initial
a_zero_b_not_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_3 <= a_zero_b_not_dffe_2;
// synopsys translate_off
initial
a_zero_b_not_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_4 <= a_zero_b_not_dffe_3;
// synopsys translate_off
initial
a_zero_b_not_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_5 <= a_zero_b_not_dffe_4;
// synopsys translate_off
initial
a_zero_b_not_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_6 <= a_zero_b_not_dffe_5;
// synopsys translate_off
initial
a_zero_b_not_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_7 <= a_zero_b_not_dffe_6;
// synopsys translate_off
initial
a_zero_b_not_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_8 <= a_zero_b_not_dffe_7;
// synopsys translate_off
initial
a_zero_b_not_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_9 <= a_zero_b_not_dffe_8;
// synopsys translate_off
initial
b1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_0 <= 34'b0;
else if (clk_en == 1'b1) b1_dffe_0 <= wire_b1_prod_result;
// synopsys translate_off
initial
b1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_1 <= 34'b0;
else if (clk_en == 1'b1) b1_dffe_1 <= b1_dffe_0;
// synopsys translate_off
initial
b_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_0 <= b_is_infinity_w;
// synopsys translate_off
initial
b_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_1 <= b_is_infinity_dffe_0;
// synopsys translate_off
initial
b_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_10 <= b_is_infinity_dffe_9;
// synopsys translate_off
initial
b_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_11 <= b_is_infinity_dffe_10;
// synopsys translate_off
initial
b_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_12 <= b_is_infinity_dffe_11;
// synopsys translate_off
initial
b_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_2 <= b_is_infinity_dffe_1;
// synopsys translate_off
initial
b_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_3 <= b_is_infinity_dffe_2;
// synopsys translate_off
initial
b_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_4 <= b_is_infinity_dffe_3;
// synopsys translate_off
initial
b_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_5 <= b_is_infinity_dffe_4;
// synopsys translate_off
initial
b_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_6 <= b_is_infinity_dffe_5;
// synopsys translate_off
initial
b_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_7 <= b_is_infinity_dffe_6;
// synopsys translate_off
initial
b_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_8 <= b_is_infinity_dffe_7;
// synopsys translate_off
initial
b_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_9 <= b_is_infinity_dffe_8;
// synopsys translate_off
initial
both_exp_zeros_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_exp_zeros_dffe <= 1'b0;
else if (clk_en == 1'b1) both_exp_zeros_dffe <= ((~ exp_b_not_zero_w[7]) & (~ exp_a_not_zero_w[7]));
// synopsys translate_off
initial
divbyzero_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_0 <= ((((~ exp_b_not_zero_w[7]) & (~ a_is_nan_w)) & exp_a_not_zero_w[7]) & (~ a_is_infinity_w));
// synopsys translate_off
initial
divbyzero_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_1 <= divbyzero_pipe_dffe_0;
// synopsys translate_off
initial
divbyzero_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_10 <= divbyzero_pipe_dffe_9;
// synopsys translate_off
initial
divbyzero_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_11 <= divbyzero_pipe_dffe_10;
// synopsys translate_off
initial
divbyzero_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_12 <= divbyzero_pipe_dffe_11;
// synopsys translate_off
initial
divbyzero_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_2 <= divbyzero_pipe_dffe_1;
// synopsys translate_off
initial
divbyzero_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_3 <= divbyzero_pipe_dffe_2;
// synopsys translate_off
initial
divbyzero_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_4 <= divbyzero_pipe_dffe_3;
// synopsys translate_off
initial
divbyzero_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_5 <= divbyzero_pipe_dffe_4;
// synopsys translate_off
initial
divbyzero_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_6 <= divbyzero_pipe_dffe_5;
// synopsys translate_off
initial
divbyzero_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_7 <= divbyzero_pipe_dffe_6;
// synopsys translate_off
initial
divbyzero_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_8 <= divbyzero_pipe_dffe_7;
// synopsys translate_off
initial
divbyzero_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_9 <= divbyzero_pipe_dffe_8;
// synopsys translate_off
initial
e1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_0 <= e1_w[16:0];
// synopsys translate_off
initial
e1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_1 <= e1_w[33:17];
// synopsys translate_off
initial
e1_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_0 <= e1_dffe_0;
// synopsys translate_off
initial
e1_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_1 <= e1_dffe_perf_0;
// synopsys translate_off
initial
e1_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_2 <= e1_dffe_perf_1;
// synopsys translate_off
initial
e1_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_3 <= e1_dffe_perf_2;
// synopsys translate_off
initial
exp_result_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_0 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_0 <= exp_result_mux_out;
// synopsys translate_off
initial
exp_result_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_1 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_1 <= exp_result_dffe_0;
// synopsys translate_off
initial
exp_result_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_10 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_10 <= exp_result_dffe_9;
// synopsys translate_off
initial
exp_result_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_11 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_11 <= exp_result_dffe_10;
// synopsys translate_off
initial
exp_result_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_2 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_2 <= exp_result_dffe_1;
// synopsys translate_off
initial
exp_result_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_3 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_3 <= exp_result_dffe_2;
// synopsys translate_off
initial
exp_result_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_4 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_4 <= exp_result_dffe_3;
// synopsys translate_off
initial
exp_result_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_5 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_5 <= exp_result_dffe_4;
// synopsys translate_off
initial
exp_result_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_6 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_6 <= exp_result_dffe_5;
// synopsys translate_off
initial
exp_result_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_7 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_7 <= exp_result_dffe_6;
// synopsys translate_off
initial
exp_result_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_8 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_8 <= exp_result_dffe_7;
// synopsys translate_off
initial
exp_result_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_9 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_9 <= exp_result_dffe_8;
// synopsys translate_off
initial
frac_a_smaller_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) frac_a_smaller_dffe1 <= 1'b0;
else if (clk_en == 1'b1) frac_a_smaller_dffe1 <= frac_a_smaller_dffe1_wi;
// synopsys translate_off
initial
man_a_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_a_dffe1_dffe1 <= 23'b0;
else if (clk_en == 1'b1) man_a_dffe1_dffe1 <= man_a_dffe1_wi;
// synopsys translate_off
initial
man_b_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_b_dffe1_dffe1 <= 23'b0;
else if (clk_en == 1'b1) man_b_dffe1_dffe1 <= man_b_dffe1_wi;
// synopsys translate_off
initial
man_result_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_dffe <= 23'b0;
else if (clk_en == 1'b1) man_result_dffe <= man_result_dffe_wi;
// synopsys translate_off
initial
nan_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_0 <= (((a_is_nan_w | b_is_nan_w) | (a_is_infinity_w & b_is_infinity_w)) | ((~ exp_a_not_zero_w[7]) & (~ exp_b_not_zero_w[7])));
// synopsys translate_off
initial
nan_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_1 <= nan_pipe_dffe_0;
// synopsys translate_off
initial
nan_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_10 <= nan_pipe_dffe_9;
// synopsys translate_off
initial
nan_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_11 <= nan_pipe_dffe_10;
// synopsys translate_off
initial
nan_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_12 <= nan_pipe_dffe_11;
// synopsys translate_off
initial
nan_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_2 <= nan_pipe_dffe_1;
// synopsys translate_off
initial
nan_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_3 <= nan_pipe_dffe_2;
// synopsys translate_off
initial
nan_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_4 <= nan_pipe_dffe_3;
// synopsys translate_off
initial
nan_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_5 <= nan_pipe_dffe_4;
// synopsys translate_off
initial
nan_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_6 <= nan_pipe_dffe_5;
// synopsys translate_off
initial
nan_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_7 <= nan_pipe_dffe_6;
// synopsys translate_off
initial
nan_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_8 <= nan_pipe_dffe_7;
// synopsys translate_off
initial
nan_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_9 <= nan_pipe_dffe_8;
// synopsys translate_off
initial
over_under_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_0 <= overflow_underflow;
// synopsys translate_off
initial
over_under_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_1 <= over_under_dffe_0;
// synopsys translate_off
initial
over_under_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_10 <= over_under_dffe_9;
// synopsys translate_off
initial
over_under_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_2 <= over_under_dffe_1;
// synopsys translate_off
initial
over_under_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_3 <= over_under_dffe_2;
// synopsys translate_off
initial
over_under_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_4 <= over_under_dffe_3;
// synopsys translate_off
initial
over_under_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_5 <= over_under_dffe_4;
// synopsys translate_off
initial
over_under_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_6 <= over_under_dffe_5;
// synopsys translate_off
initial
over_under_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_7 <= over_under_dffe_6;
// synopsys translate_off
initial
over_under_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_8 <= over_under_dffe_7;
// synopsys translate_off
initial
over_under_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_9 <= over_under_dffe_8;
// synopsys translate_off
initial
q_partial_perf_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_0 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_0 <= wire_q_partial_0_result;
// synopsys translate_off
initial
q_partial_perf_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_1 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_1 <= wire_q_partial_1_result;
// synopsys translate_off
initial
quotient_j_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_j_dffe <= 17'b0;
else if (clk_en == 1'b1) quotient_j_dffe <= q_partial_perf_dffe_0[32:16];
// synopsys translate_off
initial
quotient_k_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_0 <= quotient_k_dffe_perf_3;
// synopsys translate_off
initial
quotient_k_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_0 <= quotient_accumulate_w[30:14];
// synopsys translate_off
initial
quotient_k_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_1 <= quotient_k_dffe_perf_0;
// synopsys translate_off
initial
quotient_k_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_2 <= quotient_k_dffe_perf_1;
// synopsys translate_off
initial
quotient_k_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_3 <= quotient_k_dffe_perf_2;
// synopsys translate_off
initial
remainder_j_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_0 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_0 <= remainder_j_w[49:0];
// synopsys translate_off
initial
remainder_j_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_1 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_1 <= remainder_j_dffe_perf_2;
// synopsys translate_off
initial
remainder_j_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_0 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_0 <= remainder_j_dffe_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_1 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_1 <= remainder_j_dffe_perf_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_2 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_2 <= remainder_j_dffe_perf_1;
// synopsys translate_off
initial
sign_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_0 <= (dataa[31] ^ datab[31]);
// synopsys translate_off
initial
sign_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_1 <= sign_pipe_dffe_0;
// synopsys translate_off
initial
sign_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_10 <= sign_pipe_dffe_9;
// synopsys translate_off
initial
sign_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_11 <= sign_pipe_dffe_10;
// synopsys translate_off
initial
sign_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_12 <= sign_pipe_dffe_11;
// synopsys translate_off
initial
sign_pipe_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_13 <= sign_pipe_dffe_12;
// synopsys translate_off
initial
sign_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_2 <= sign_pipe_dffe_1;
// synopsys translate_off
initial
sign_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_3 <= sign_pipe_dffe_2;
// synopsys translate_off
initial
sign_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_4 <= sign_pipe_dffe_3;
// synopsys translate_off
initial
sign_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_5 <= sign_pipe_dffe_4;
// synopsys translate_off
initial
sign_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_6 <= sign_pipe_dffe_5;
// synopsys translate_off
initial
sign_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_7 <= sign_pipe_dffe_6;
// synopsys translate_off
initial
sign_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_8 <= sign_pipe_dffe_7;
// synopsys translate_off
initial
sign_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_9 <= sign_pipe_dffe_8;
lpm_add_sub bias_addition
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_w),
.datab(select_bias_out_2_w),
.overflow(wire_bias_addition_overflow),
.result(wire_bias_addition_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
bias_addition.lpm_direction = "ADD",
bias_addition.lpm_pipeline = 1,
bias_addition.lpm_representation = "SIGNED",
bias_addition.lpm_width = 9,
bias_addition.lpm_type = "lpm_add_sub";
lpm_add_sub exp_sub
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_a_w),
.datab(exp_sub_b_w),
.overflow(),
.result(wire_exp_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_sub.lpm_direction = "SUB",
exp_sub.lpm_pipeline = 1,
exp_sub.lpm_representation = "SIGNED",
exp_sub.lpm_width = 9,
exp_sub.lpm_type = "lpm_add_sub";
lpm_add_sub quotient_process
(
.aclr(aclr),
.cin(quotient_process_cin_w),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({quotient_accumulate_w[61:45], {14{1'b0}}}),
.datab({{14{1'b0}}, q_partial_perf_dffe_1[32:22], {6{1'b1}}}),
.overflow(),
.result(wire_quotient_process_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quotient_process.lpm_direction = "ADD",
quotient_process.lpm_pipeline = 1,
quotient_process.lpm_representation = "UNSIGNED",
quotient_process.lpm_width = 31,
quotient_process.lpm_type = "lpm_add_sub";
lpm_add_sub remainder_sub_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({remainder_j_dffe_1[49:15], {15{1'b0}}}),
.datab(wire_remainder_mult_0_result[49:0]),
.overflow(),
.result(wire_remainder_sub_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_sub_0.lpm_direction = "SUB",
remainder_sub_0.lpm_pipeline = 1,
remainder_sub_0.lpm_representation = "UNSIGNED",
remainder_sub_0.lpm_width = 50,
remainder_sub_0.lpm_type = "lpm_add_sub";
lpm_compare cmpr2
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr2_alb),
.aleb(),
.aneb(),
.dataa(dataa[22:0]),
.datab(datab[22:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 23,
cmpr2.lpm_type = "lpm_compare";
lpm_mult a1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_a_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_a1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
a1_prod.lpm_pipeline = 3,
a1_prod.lpm_representation = "UNSIGNED",
a1_prod.lpm_widtha = 25,
a1_prod.lpm_widthb = 10,
a1_prod.lpm_widthp = 35,
a1_prod.lpm_type = "lpm_mult",
a1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult b1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_b_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_b1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
b1_prod.lpm_pipeline = 3,
b1_prod.lpm_representation = "UNSIGNED",
b1_prod.lpm_widtha = 24,
b1_prod.lpm_widthb = 10,
b1_prod.lpm_widthp = 34,
b1_prod.lpm_type = "lpm_mult",
b1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[49:33]),
.datab(e1_w[16:0]),
.result(wire_q_partial_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_0.lpm_pipeline = 1,
q_partial_0.lpm_representation = "UNSIGNED",
q_partial_0.lpm_widtha = 17,
q_partial_0.lpm_widthb = 17,
q_partial_0.lpm_widthp = 34,
q_partial_0.lpm_type = "lpm_mult",
q_partial_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[99:83]),
.datab(e1_w[50:34]),
.result(wire_q_partial_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_1.lpm_pipeline = 1,
q_partial_1.lpm_representation = "UNSIGNED",
q_partial_1.lpm_widtha = 17,
q_partial_1.lpm_widthb = 17,
q_partial_1.lpm_widthp = 34,
q_partial_1.lpm_type = "lpm_mult",
q_partial_1.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult remainder_mult_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(b1_dffe_w[33:0]),
.datab(q_partial_perf_dffe_0[32:16]),
.result(wire_remainder_mult_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_mult_0.lpm_pipeline = 3,
remainder_mult_0.lpm_representation = "UNSIGNED",
remainder_mult_0.lpm_widtha = 34,
remainder_mult_0.lpm_widthb = 17,
remainder_mult_0.lpm_widthp = 51,
remainder_mult_0.lpm_type = "lpm_mult",
remainder_mult_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign wire_exp_result_muxa_dataout = (exp_result_mux_sel_w === 1'b1) ? underflow_zeros_w : exp_result_w;
assign wire_man_a_adjusteda_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? {1'b1, man_a_dffe1_wo, 1'b0} : {1'b0, 1'b1, man_a_dffe1_wo};
assign wire_man_result_muxa_dataout = (man_result_mux_select === 1'b1) ? {nan_pipe_dffe_12, man_zeros_w[21:0]} : wire_quotient_process_result[28:6];
assign wire_select_bias_2a_dataout = (both_exp_zeros === 1'b1) ? value_zero_w : select_bias_out_w;
assign wire_select_biasa_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? value_normal_w : value_add_one_w;
assign
a_is_infinity_w = (exp_a_all_one_w[7] & (~ man_a_not_zero_w[22])),
a_is_nan_w = (exp_a_all_one_w[7] & man_a_not_zero_w[22]),
a_zero_b_not = (exp_b_not_zero_w[7] & (~ exp_a_not_zero_w[7])),
b1_dffe_w = {b1_dffe_1},
b_is_infinity_w = (exp_b_all_one_w[7] & (~ man_b_not_zero_w[22])),
b_is_nan_w = (exp_b_all_one_w[7] & man_b_not_zero_w[22]),
bias_addition_overf_w = wire_bias_addition_overflow,
bias_addition_w = wire_bias_addition_result[7:0],
both_exp_zeros = both_exp_zeros_dffe,
e0_dffe1_wo = e0_w,
e0_w = wire_altsyncram3_q_a,
e1_w = {e1_dffe_1, e1_dffe_perf_3, (~ wire_b1_prod_result[33:17])},
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_add_output_all_one = {(bias_addition_w[7] & exp_add_output_all_one[6]), (bias_addition_w[6] & exp_add_output_all_one[5]), (bias_addition_w[5] & exp_add_output_all_one[4]), (bias_addition_w[4] & exp_add_output_all_one[3]), (bias_addition_w[3] & exp_add_output_all_one[2]), (bias_addition_w[2] & exp_add_output_all_one[1]), (bias_addition_w[1] & exp_add_output_all_one[0]), bias_addition_w[0]},
exp_add_output_not_zero = {(bias_addition_w[7] | exp_add_output_not_zero[6]), (bias_addition_w[6] | exp_add_output_not_zero[5]), (bias_addition_w[5] | exp_add_output_not_zero[4]), (bias_addition_w[4] | exp_add_output_not_zero[3]), (bias_addition_w[3] | exp_add_output_not_zero[2]), (bias_addition_w[2] | exp_add_output_not_zero[1]), (bias_addition_w[1] | exp_add_output_not_zero[0]), bias_addition_w[0]},
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_result_mux_out = wire_exp_result_muxa_dataout,
exp_result_mux_sel_w = ((((a_zero_b_not_dffe_1 | b_is_infinity_dffe_1) | ((~ bias_addition_overf_w) & exp_sign_w)) | (((~ exp_add_output_not_zero[7]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)),
exp_result_w = (({8{((~ bias_addition_overf_w) & (~ exp_sign_w))}} & bias_addition_w) | ({8{(((bias_addition_overf_w | divbyzero_pipe_dffe_1) | nan_pipe_dffe_1) | a_is_infinity_dffe_1)}} & overflow_ones_w)),
exp_sign_w = wire_bias_addition_result[8],
exp_sub_a_w = {1'b0, dataa[30:23]},
exp_sub_b_w = {1'b0, datab[30:23]},
exp_sub_w = wire_exp_sub_result,
frac_a_smaller_dffe1_wi = frac_a_smaller_w,
frac_a_smaller_dffe1_wo = frac_a_smaller_dffe1,
frac_a_smaller_w = wire_cmpr2_alb,
guard_bit = q_partial_perf_dffe_1[22],
man_a_adjusted_w = wire_man_a_adjusteda_dataout,
man_a_dffe1_wi = dataa[22:0],
man_a_dffe1_wo = man_a_dffe1_dffe1,
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), (dataa[12] | man_a_not_zero_w[11]), (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_adjusted_w = {1'b1, man_b_dffe1_wo},
man_b_dffe1_wi = datab[22:0],
man_b_dffe1_wo = man_b_dffe1_dffe1,
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), (datab[12] | man_b_not_zero_w[11]), (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
man_result_dffe_wi = man_result_w,
man_result_dffe_wo = man_result_dffe,
man_result_mux_select = (((((over_under_dffe_10 | a_zero_b_not_dffe_12) | nan_pipe_dffe_12) | b_is_infinity_dffe_12) | a_is_infinity_dffe_12) | divbyzero_pipe_dffe_12),
man_result_w = wire_man_result_muxa_dataout,
man_zeros_w = {23{1'b0}},
overflow_ones_w = {8{1'b1}},
overflow_underflow = (overflow_w | underflow_w),
overflow_w = ((bias_addition_overf_w | ((exp_add_output_all_one[7] & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (((~ nan_pipe_dffe_1) & (~ a_is_infinity_dffe_1)) & (~ divbyzero_pipe_dffe_1))),
quotient_accumulate_w = {quotient_k_dffe_0, {14{1'b0}}, quotient_j_dffe, {14{1'b0}}},
quotient_process_cin_w = (round_bit & (guard_bit | sticky_bits[4])),
remainder_j_w = {wire_remainder_sub_0_result[35:0], {14{1'b0}}, wire_a1_prod_result[34:0], {15{1'b0}}},
result = {sign_pipe_dffe_13, exp_result_dffe_11, man_result_dffe_wo},
round_bit = q_partial_perf_dffe_1[21],
select_bias_out_2_w = wire_select_bias_2a_dataout,
select_bias_out_w = wire_select_biasa_dataout,
sticky_bits = {(q_partial_perf_dffe_1[20] | sticky_bits[3]), (q_partial_perf_dffe_1[19] | sticky_bits[2]), (q_partial_perf_dffe_1[18] | sticky_bits[1]), (q_partial_perf_dffe_1[17] | sticky_bits[0]), q_partial_perf_dffe_1[16]},
underflow_w = ((((((~ bias_addition_overf_w) & exp_sign_w) | (((~ exp_add_output_not_zero[7]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)) & (~ a_zero_b_not_dffe_1)) & (~ b_is_infinity_dffe_1)),
underflow_zeros_w = {8{1'b0}},
value_add_one_w = 9'b001111111,
value_normal_w = 9'b001111110,
value_zero_w = {9{1'b0}};
endmodule //acl_fp_div_altfp_div_pst_g1f
//synthesis_resources = altsyncram 1 lpm_add_sub 4 lpm_compare 1 lpm_mult 5 mux21 74 reg 847
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_div_altfp_div_2vh
(
clk_en,
clock,
dataa,
datab,
result) ;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_altfp_div_pst1_result;
wire aclr;
acl_fp_div_altfp_div_pst_g1f altfp_div_pst1
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(wire_altfp_div_pst1_result));
assign
aclr = 1'b0,
result = wire_altfp_div_pst1_result;
endmodule //acl_fp_div_altfp_div_2vh
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_div (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
acl_fp_div_altfp_div_2vh acl_fp_div_altfp_div_2vh_component (
.clk_en (enable),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_bb.v TRUE
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v2_3_bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
wire [BM_CNT_WIDTH-1:0] temp;
// always @(/*AS*/accept_req or accept_this_bm or adv_queue
// or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
// or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin
//// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
//// else begin
// q_entry_ns = q_entry_r;
// if ((~idle_r_lcl && adv_queue) ||
// (idle_r_lcl && accept_req && ~accept_this_bm))
// q_entry_ns = q_entry_r - BM_CNT_ONE;
// if (accept_this_bm)
//// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
// q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
// if (bm_end_lcl) begin
// q_entry_ns = idle_cnt + idlers_below;
// if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
//// end
// end
// end
assign temp = idle_cnt + idlers_below;
always @ (*)
begin
if (accept_req & bm_end_lcl)
q_entry_ns = temp - BM_CNT_ONE;
else if (bm_end_lcl)
q_entry_ns = temp;
else if (accept_this_bm)
q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
else if ((!idle_r_lcl & adv_queue) |
(idle_r_lcl & accept_req & !accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
else
q_entry_ns = q_entry_r;
end
always @(posedge clk)
if (rst)
q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0];
else
q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
logic [3:0] array_simp [1:0] [3:0]; // big endian array
int irep[1:2][1:6];
initial begin
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//array_simp[0] = '{ 1:4'd3, default:13 };
//if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3210_1234) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3210_3210) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3333_3333) $stop;
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
// Replication
irep = '{2{ '{3 {4, 5}}}};
if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]}
!= {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]}
!= {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_2048x8(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 8;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x8_bist artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we),
.DO(doq[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we),
.DO(doq[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we),
.DO(doq[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we),
.DO(doq[7:6])
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
//
// Copyright (c) 2001 Stephan Gehring
//
// (Modified by Stephan Williams to include PASS/FAIL messages.)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [7:0] x;
initial begin
x = 'h4000 + 'hzz; // iverilog doesn't like 'hzz
if (x !== 8'hxx) begin
$display("FAILED -- x = %b", x);
$finish;
end
$display("PASSED");
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NOR3_FUNCTIONAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_FUNCTIONAL_PP_V |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_interconnect_model.v
*
* Date : 2012-11
*
* Description : Mimics Top_interconnect Switch.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_interconnect_model (
rstn,
sw_clk,
w_qos_gp0,
w_qos_gp1,
w_qos_hp0,
w_qos_hp1,
w_qos_hp2,
w_qos_hp3,
r_qos_gp0,
r_qos_gp1,
r_qos_hp0,
r_qos_hp1,
r_qos_hp2,
r_qos_hp3,
wr_ack_ddr_gp0,
wr_ack_ocm_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ddr_gp0,
wr_dv_ocm_gp0,
rd_req_ddr_gp0,
rd_req_ocm_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ddr_gp0,
rd_data_ocm_gp0,
rd_data_reg_gp0,
rd_dv_ddr_gp0,
rd_dv_ocm_gp0,
rd_dv_reg_gp0,
wr_ack_ddr_gp1,
wr_ack_ocm_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ddr_gp1,
wr_dv_ocm_gp1,
rd_req_ddr_gp1,
rd_req_ocm_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ddr_gp1,
rd_data_ocm_gp1,
rd_data_reg_gp1,
rd_dv_ddr_gp1,
rd_dv_ocm_gp1,
rd_dv_reg_gp1,
wr_ack_ddr_hp0,
wr_ack_ocm_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
wr_dv_ocm_hp0,
rd_req_ddr_hp0,
rd_req_ocm_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_data_ocm_hp0,
rd_dv_ddr_hp0,
rd_dv_ocm_hp0,
wr_ack_ddr_hp1,
wr_ack_ocm_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
wr_dv_ocm_hp1,
rd_req_ddr_hp1,
rd_req_ocm_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_data_ocm_hp1,
rd_dv_ddr_hp1,
rd_dv_ocm_hp1,
wr_ack_ddr_hp2,
wr_ack_ocm_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
wr_dv_ocm_hp2,
rd_req_ddr_hp2,
rd_req_ocm_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_data_ocm_hp2,
rd_dv_ddr_hp2,
rd_dv_ocm_hp2,
wr_ack_ddr_hp3,
wr_ack_ocm_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
wr_dv_ocm_hp3,
rd_req_ddr_hp3,
rd_req_ocm_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_data_ocm_hp3,
rd_dv_ddr_hp3,
rd_dv_ocm_hp3,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3,
/* Goes to port1 of OCM */
ocm_wr_qos_port1,
ocm_rd_qos_port1,
ocm_wr_dv_port1,
ocm_wr_data_port1,
ocm_wr_addr_port1,
ocm_wr_bytes_port1,
ocm_wr_ack_port1,
ocm_rd_req_port1,
ocm_rd_data_port1,
ocm_rd_addr_port1,
ocm_rd_bytes_port1,
ocm_rd_dv_port1,
/* Goes to port1 for RegMap */
reg_rd_qos_port1,
reg_rd_req_port1,
reg_rd_data_port1,
reg_rd_addr_port1,
reg_rd_bytes_port1,
reg_rd_dv_port1
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
input [axi_qos_width-1:0] w_qos_gp0;
input [axi_qos_width-1:0] w_qos_gp1;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_gp0;
input [axi_qos_width-1:0] r_qos_gp1;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp3;
output [axi_qos_width-1:0] ocm_wr_qos_port1;
output [axi_qos_width-1:0] ocm_rd_qos_port1;
output wr_ack_ddr_gp0;
output wr_ack_ocm_gp0;
input[max_burst_bits-1:0] wr_data_gp0;
input[addr_width-1:0] wr_addr_gp0;
input[max_burst_bytes_width:0] wr_bytes_gp0;
input wr_dv_ddr_gp0;
input wr_dv_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_reg_gp0;
input[addr_width-1:0] rd_addr_gp0;
input[max_burst_bytes_width:0] rd_bytes_gp0;
output[max_burst_bits-1:0] rd_data_ddr_gp0;
output[max_burst_bits-1:0] rd_data_ocm_gp0;
output[max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ddr_gp0;
output rd_dv_ocm_gp0;
output rd_dv_reg_gp0;
output wr_ack_ddr_gp1;
output wr_ack_ocm_gp1;
input[max_burst_bits-1:0] wr_data_gp1;
input[addr_width-1:0] wr_addr_gp1;
input[max_burst_bytes_width:0] wr_bytes_gp1;
input wr_dv_ddr_gp1;
input wr_dv_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_reg_gp1;
input[addr_width-1:0] rd_addr_gp1;
input[max_burst_bytes_width:0] rd_bytes_gp1;
output[max_burst_bits-1:0] rd_data_ddr_gp1;
output[max_burst_bits-1:0] rd_data_ocm_gp1;
output[max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ddr_gp1;
output rd_dv_ocm_gp1;
output rd_dv_reg_gp1;
output wr_ack_ddr_hp0;
output wr_ack_ocm_hp0;
input[max_burst_bits-1:0] wr_data_hp0;
input[addr_width-1:0] wr_addr_hp0;
input[max_burst_bytes_width:0] wr_bytes_hp0;
input wr_dv_ddr_hp0;
input wr_dv_ocm_hp0;
input rd_req_ddr_hp0;
input rd_req_ocm_hp0;
input[addr_width-1:0] rd_addr_hp0;
input[max_burst_bytes_width:0] rd_bytes_hp0;
output[max_burst_bits-1:0] rd_data_ddr_hp0;
output[max_burst_bits-1:0] rd_data_ocm_hp0;
output rd_dv_ddr_hp0;
output rd_dv_ocm_hp0;
output wr_ack_ddr_hp1;
output wr_ack_ocm_hp1;
input[max_burst_bits-1:0] wr_data_hp1;
input[addr_width-1:0] wr_addr_hp1;
input[max_burst_bytes_width:0] wr_bytes_hp1;
input wr_dv_ddr_hp1;
input wr_dv_ocm_hp1;
input rd_req_ddr_hp1;
input rd_req_ocm_hp1;
input[addr_width-1:0] rd_addr_hp1;
input[max_burst_bytes_width:0] rd_bytes_hp1;
output[max_burst_bits-1:0] rd_data_ddr_hp1;
output[max_burst_bits-1:0] rd_data_ocm_hp1;
output rd_dv_ddr_hp1;
output rd_dv_ocm_hp1;
output wr_ack_ddr_hp2;
output wr_ack_ocm_hp2;
input[max_burst_bits-1:0] wr_data_hp2;
input[addr_width-1:0] wr_addr_hp2;
input[max_burst_bytes_width:0] wr_bytes_hp2;
input wr_dv_ddr_hp2;
input wr_dv_ocm_hp2;
input rd_req_ddr_hp2;
input rd_req_ocm_hp2;
input[addr_width-1:0] rd_addr_hp2;
input[max_burst_bytes_width:0] rd_bytes_hp2;
output[max_burst_bits-1:0] rd_data_ddr_hp2;
output[max_burst_bits-1:0] rd_data_ocm_hp2;
output rd_dv_ddr_hp2;
output rd_dv_ocm_hp2;
output wr_ack_ddr_hp3;
output wr_ack_ocm_hp3;
input[max_burst_bits-1:0] wr_data_hp3;
input[addr_width-1:0] wr_addr_hp3;
input[max_burst_bytes_width:0] wr_bytes_hp3;
input wr_dv_ddr_hp3;
input wr_dv_ocm_hp3;
input rd_req_ddr_hp3;
input rd_req_ocm_hp3;
input[addr_width-1:0] rd_addr_hp3;
input[max_burst_bytes_width:0] rd_bytes_hp3;
output[max_burst_bits-1:0] rd_data_ddr_hp3;
output[max_burst_bits-1:0] rd_data_ocm_hp3;
output rd_dv_ddr_hp3;
output rd_dv_ocm_hp3;
/* Goes to port 1 of DDR */
input ddr_wr_ack_port1;
output ddr_wr_dv_port1;
output ddr_rd_req_port1;
input ddr_rd_dv_port1;
output[addr_width-1:0] ddr_wr_addr_port1;
output[max_burst_bits-1:0] ddr_wr_data_port1;
output[max_burst_bytes_width:0] ddr_wr_bytes_port1;
output[addr_width-1:0] ddr_rd_addr_port1;
input[max_burst_bits-1:0] ddr_rd_data_port1;
output[max_burst_bytes_width:0] ddr_rd_bytes_port1;
output [axi_qos_width-1:0] ddr_wr_qos_port1;
output [axi_qos_width-1:0] ddr_rd_qos_port1;
/* Goes to port2 of DDR */
input ddr_wr_ack_port2;
output ddr_wr_dv_port2;
output ddr_rd_req_port2;
input ddr_rd_dv_port2;
output[addr_width-1:0] ddr_wr_addr_port2;
output[max_burst_bits-1:0] ddr_wr_data_port2;
output[max_burst_bytes_width:0] ddr_wr_bytes_port2;
output[addr_width-1:0] ddr_rd_addr_port2;
input[max_burst_bits-1:0] ddr_rd_data_port2;
output[max_burst_bytes_width:0] ddr_rd_bytes_port2;
output [axi_qos_width-1:0] ddr_wr_qos_port2;
output [axi_qos_width-1:0] ddr_rd_qos_port2;
/* Goes to port3 of DDR */
input ddr_wr_ack_port3;
output ddr_wr_dv_port3;
output ddr_rd_req_port3;
input ddr_rd_dv_port3;
output[addr_width-1:0] ddr_wr_addr_port3;
output[max_burst_bits-1:0] ddr_wr_data_port3;
output[max_burst_bytes_width:0] ddr_wr_bytes_port3;
output[addr_width-1:0] ddr_rd_addr_port3;
input[max_burst_bits-1:0] ddr_rd_data_port3;
output[max_burst_bytes_width:0] ddr_rd_bytes_port3;
output [axi_qos_width-1:0] ddr_wr_qos_port3;
output [axi_qos_width-1:0] ddr_rd_qos_port3;
/* Goes to port1 of OCM */
input ocm_wr_ack_port1;
output ocm_wr_dv_port1;
output ocm_rd_req_port1;
input ocm_rd_dv_port1;
output[max_burst_bits-1:0] ocm_wr_data_port1;
output[addr_width-1:0] ocm_wr_addr_port1;
output[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[max_burst_bits-1:0] ocm_rd_data_port1;
output[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bytes_width:0] ocm_rd_bytes_port1;
/* Goes to port1 of REG */
output [axi_qos_width-1:0] reg_rd_qos_port1;
output reg_rd_req_port1;
input reg_rd_dv_port1;
input[max_burst_bits-1:0] reg_rd_data_port1;
output[addr_width-1:0] reg_rd_addr_port1;
output[max_burst_bytes_width:0] reg_rd_bytes_port1;
wire ocm_wr_dv_osw0;
wire ocm_wr_dv_osw1;
wire[max_burst_bits-1:0] ocm_wr_data_osw0;
wire[max_burst_bits-1:0] ocm_wr_data_osw1;
wire[addr_width-1:0] ocm_wr_addr_osw0;
wire[addr_width-1:0] ocm_wr_addr_osw1;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1;
wire ocm_wr_ack_osw0;
wire ocm_wr_ack_osw1;
wire ocm_rd_req_osw0;
wire ocm_rd_req_osw1;
wire[max_burst_bits-1:0] ocm_rd_data_osw0;
wire[max_burst_bits-1:0] ocm_rd_data_osw1;
wire[addr_width-1:0] ocm_rd_addr_osw0;
wire[addr_width-1:0] ocm_rd_addr_osw1;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1;
wire ocm_rd_dv_osw0;
wire ocm_rd_dv_osw1;
wire [axi_qos_width-1:0] ocm_wr_qos_osw0;
wire [axi_qos_width-1:0] ocm_wr_qos_osw1;
wire [axi_qos_width-1:0] ocm_rd_qos_osw0;
wire [axi_qos_width-1:0] ocm_rd_qos_osw1;
processing_system7_bfm_v2_0_fmsw_gp fmsw (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_gp0(w_qos_gp0),
.r_qos_gp0(r_qos_gp0),
.wr_ack_ocm_gp0(wr_ack_ocm_gp0),
.wr_ack_ddr_gp0(wr_ack_ddr_gp0),
.wr_data_gp0(wr_data_gp0),
.wr_addr_gp0(wr_addr_gp0),
.wr_bytes_gp0(wr_bytes_gp0),
.wr_dv_ocm_gp0(wr_dv_ocm_gp0),
.wr_dv_ddr_gp0(wr_dv_ddr_gp0),
.rd_req_ocm_gp0(rd_req_ocm_gp0),
.rd_req_ddr_gp0(rd_req_ddr_gp0),
.rd_req_reg_gp0(rd_req_reg_gp0),
.rd_addr_gp0(rd_addr_gp0),
.rd_bytes_gp0(rd_bytes_gp0),
.rd_data_ddr_gp0(rd_data_ddr_gp0),
.rd_data_ocm_gp0(rd_data_ocm_gp0),
.rd_data_reg_gp0(rd_data_reg_gp0),
.rd_dv_ocm_gp0(rd_dv_ocm_gp0),
.rd_dv_ddr_gp0(rd_dv_ddr_gp0),
.rd_dv_reg_gp0(rd_dv_reg_gp0),
.w_qos_gp1(w_qos_gp1),
.r_qos_gp1(r_qos_gp1),
.wr_ack_ocm_gp1(wr_ack_ocm_gp1),
.wr_ack_ddr_gp1(wr_ack_ddr_gp1),
.wr_data_gp1(wr_data_gp1),
.wr_addr_gp1(wr_addr_gp1),
.wr_bytes_gp1(wr_bytes_gp1),
.wr_dv_ocm_gp1(wr_dv_ocm_gp1),
.wr_dv_ddr_gp1(wr_dv_ddr_gp1),
.rd_req_ocm_gp1(rd_req_ocm_gp1),
.rd_req_ddr_gp1(rd_req_ddr_gp1),
.rd_req_reg_gp1(rd_req_reg_gp1),
.rd_addr_gp1(rd_addr_gp1),
.rd_bytes_gp1(rd_bytes_gp1),
.rd_data_ddr_gp1(rd_data_ddr_gp1),
.rd_data_ocm_gp1(rd_data_ocm_gp1),
.rd_data_reg_gp1(rd_data_reg_gp1),
.rd_dv_ocm_gp1(rd_dv_ocm_gp1),
.rd_dv_ddr_gp1(rd_dv_ddr_gp1),
.rd_dv_reg_gp1(rd_dv_reg_gp1),
.ocm_wr_ack (ocm_wr_ack_osw0),
.ocm_wr_dv (ocm_wr_dv_osw0),
.ocm_rd_req (ocm_rd_req_osw0),
.ocm_rd_dv (ocm_rd_dv_osw0),
.ocm_wr_addr(ocm_wr_addr_osw0),
.ocm_wr_data(ocm_wr_data_osw0),
.ocm_wr_bytes(ocm_wr_bytes_osw0),
.ocm_rd_addr(ocm_rd_addr_osw0),
.ocm_rd_data(ocm_rd_data_osw0),
.ocm_rd_bytes(ocm_rd_bytes_osw0),
.ocm_wr_qos(ocm_wr_qos_osw0),
.ocm_rd_qos(ocm_rd_qos_osw0),
.ddr_wr_qos(ddr_wr_qos_port1),
.ddr_rd_qos(ddr_rd_qos_port1),
.reg_rd_qos(reg_rd_qos_port1),
.ddr_wr_ack(ddr_wr_ack_port1),
.ddr_wr_dv(ddr_wr_dv_port1),
.ddr_rd_req(ddr_rd_req_port1),
.ddr_rd_dv(ddr_rd_dv_port1),
.ddr_wr_addr(ddr_wr_addr_port1),
.ddr_wr_data(ddr_wr_data_port1),
.ddr_wr_bytes(ddr_wr_bytes_port1),
.ddr_rd_addr(ddr_rd_addr_port1),
.ddr_rd_data(ddr_rd_data_port1),
.ddr_rd_bytes(ddr_rd_bytes_port1),
.reg_rd_req(reg_rd_req_port1),
.reg_rd_dv(reg_rd_dv_port1),
.reg_rd_addr(reg_rd_addr_port1),
.reg_rd_data(reg_rd_data_port1),
.reg_rd_bytes(reg_rd_bytes_port1)
);
processing_system7_bfm_v2_0_ssw_hp ssw(
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp0(w_qos_hp0),
.r_qos_hp0(r_qos_hp0),
.w_qos_hp1(w_qos_hp1),
.r_qos_hp1(r_qos_hp1),
.w_qos_hp2(w_qos_hp2),
.r_qos_hp2(r_qos_hp2),
.w_qos_hp3(w_qos_hp3),
.r_qos_hp3(r_qos_hp3),
.wr_ack_ddr_hp0(wr_ack_ddr_hp0),
.wr_data_hp0(wr_data_hp0),
.wr_addr_hp0(wr_addr_hp0),
.wr_bytes_hp0(wr_bytes_hp0),
.wr_dv_ddr_hp0(wr_dv_ddr_hp0),
.rd_req_ddr_hp0(rd_req_ddr_hp0),
.rd_addr_hp0(rd_addr_hp0),
.rd_bytes_hp0(rd_bytes_hp0),
.rd_data_ddr_hp0(rd_data_ddr_hp0),
.rd_data_ocm_hp0(rd_data_ocm_hp0),
.rd_dv_ddr_hp0(rd_dv_ddr_hp0),
.wr_ack_ocm_hp0(wr_ack_ocm_hp0),
.wr_dv_ocm_hp0(wr_dv_ocm_hp0),
.rd_req_ocm_hp0(rd_req_ocm_hp0),
.rd_dv_ocm_hp0(rd_dv_ocm_hp0),
.wr_ack_ddr_hp1(wr_ack_ddr_hp1),
.wr_data_hp1(wr_data_hp1),
.wr_addr_hp1(wr_addr_hp1),
.wr_bytes_hp1(wr_bytes_hp1),
.wr_dv_ddr_hp1(wr_dv_ddr_hp1),
.rd_req_ddr_hp1(rd_req_ddr_hp1),
.rd_addr_hp1(rd_addr_hp1),
.rd_bytes_hp1(rd_bytes_hp1),
.rd_data_ddr_hp1(rd_data_ddr_hp1),
.rd_data_ocm_hp1(rd_data_ocm_hp1),
.rd_dv_ddr_hp1(rd_dv_ddr_hp1),
.wr_ack_ocm_hp1(wr_ack_ocm_hp1),
.wr_dv_ocm_hp1(wr_dv_ocm_hp1),
.rd_req_ocm_hp1(rd_req_ocm_hp1),
.rd_dv_ocm_hp1(rd_dv_ocm_hp1),
.wr_ack_ddr_hp2(wr_ack_ddr_hp2),
.wr_data_hp2(wr_data_hp2),
.wr_addr_hp2(wr_addr_hp2),
.wr_bytes_hp2(wr_bytes_hp2),
.wr_dv_ddr_hp2(wr_dv_ddr_hp2),
.rd_req_ddr_hp2(rd_req_ddr_hp2),
.rd_addr_hp2(rd_addr_hp2),
.rd_bytes_hp2(rd_bytes_hp2),
.rd_data_ddr_hp2(rd_data_ddr_hp2),
.rd_data_ocm_hp2(rd_data_ocm_hp2),
.rd_dv_ddr_hp2(rd_dv_ddr_hp2),
.wr_ack_ocm_hp2(wr_ack_ocm_hp2),
.wr_dv_ocm_hp2(wr_dv_ocm_hp2),
.rd_req_ocm_hp2(rd_req_ocm_hp2),
.rd_dv_ocm_hp2(rd_dv_ocm_hp2),
.wr_ack_ddr_hp3(wr_ack_ddr_hp3),
.wr_data_hp3(wr_data_hp3),
.wr_addr_hp3(wr_addr_hp3),
.wr_bytes_hp3(wr_bytes_hp3),
.wr_dv_ddr_hp3(wr_dv_ddr_hp3),
.rd_req_ddr_hp3(rd_req_ddr_hp3),
.rd_addr_hp3(rd_addr_hp3),
.rd_bytes_hp3(rd_bytes_hp3),
.rd_data_ddr_hp3(rd_data_ddr_hp3),
.rd_data_ocm_hp3(rd_data_ocm_hp3),
.rd_dv_ddr_hp3(rd_dv_ddr_hp3),
.wr_ack_ocm_hp3(wr_ack_ocm_hp3),
.wr_dv_ocm_hp3(wr_dv_ocm_hp3),
.rd_req_ocm_hp3(rd_req_ocm_hp3),
.rd_dv_ocm_hp3(rd_dv_ocm_hp3),
.ddr_wr_ack0(ddr_wr_ack_port2),
.ddr_wr_dv0(ddr_wr_dv_port2),
.ddr_rd_req0(ddr_rd_req_port2),
.ddr_rd_dv0(ddr_rd_dv_port2),
.ddr_wr_addr0(ddr_wr_addr_port2),
.ddr_wr_data0(ddr_wr_data_port2),
.ddr_wr_bytes0(ddr_wr_bytes_port2),
.ddr_rd_addr0(ddr_rd_addr_port2),
.ddr_rd_data0(ddr_rd_data_port2),
.ddr_rd_bytes0(ddr_rd_bytes_port2),
.ddr_wr_qos0(ddr_wr_qos_port2),
.ddr_rd_qos0(ddr_rd_qos_port2),
.ddr_wr_ack1(ddr_wr_ack_port3),
.ddr_wr_dv1(ddr_wr_dv_port3),
.ddr_rd_req1(ddr_rd_req_port3),
.ddr_rd_dv1(ddr_rd_dv_port3),
.ddr_wr_addr1(ddr_wr_addr_port3),
.ddr_wr_data1(ddr_wr_data_port3),
.ddr_wr_bytes1(ddr_wr_bytes_port3),
.ddr_rd_addr1(ddr_rd_addr_port3),
.ddr_rd_data1(ddr_rd_data_port3),
.ddr_rd_bytes1(ddr_rd_bytes_port3),
.ddr_wr_qos1(ddr_wr_qos_port3),
.ddr_rd_qos1(ddr_rd_qos_port3),
.ocm_wr_qos(ocm_wr_qos_osw1),
.ocm_rd_qos(ocm_rd_qos_osw1),
.ocm_wr_ack (ocm_wr_ack_osw1),
.ocm_wr_dv (ocm_wr_dv_osw1),
.ocm_rd_req (ocm_rd_req_osw1),
.ocm_rd_dv (ocm_rd_dv_osw1),
.ocm_wr_addr(ocm_wr_addr_osw1),
.ocm_wr_data(ocm_wr_data_osw1),
.ocm_wr_bytes(ocm_wr_bytes_osw1),
.ocm_rd_addr(ocm_rd_addr_osw1),
.ocm_rd_data(ocm_rd_data_osw1),
.ocm_rd_bytes(ocm_rd_bytes_osw1)
);
processing_system7_bfm_v2_0_arb_wr osw_wr (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_osw0), /// chk
.qos2(ocm_wr_qos_osw1), /// chk
.prt_dv1(ocm_wr_dv_osw0),
.prt_dv2(ocm_wr_dv_osw1),
.prt_data1(ocm_wr_data_osw0),
.prt_data2(ocm_wr_data_osw1),
.prt_addr1(ocm_wr_addr_osw0),
.prt_addr2(ocm_wr_addr_osw1),
.prt_bytes1(ocm_wr_bytes_osw0),
.prt_bytes2(ocm_wr_bytes_osw1),
.prt_ack1(ocm_wr_ack_osw0),
.prt_ack2(ocm_wr_ack_osw1),
.prt_req(ocm_wr_dv_port1),
.prt_qos(ocm_wr_qos_port1),
.prt_data(ocm_wr_data_port1),
.prt_addr(ocm_wr_addr_port1),
.prt_bytes(ocm_wr_bytes_port1),
.prt_ack(ocm_wr_ack_port1)
);
processing_system7_bfm_v2_0_arb_rd osw_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_osw0), // chk
.qos2(ocm_rd_qos_osw1), // chk
.prt_req1(ocm_rd_req_osw0),
.prt_req2(ocm_rd_req_osw1),
.prt_data1(ocm_rd_data_osw0),
.prt_data2(ocm_rd_data_osw1),
.prt_addr1(ocm_rd_addr_osw0),
.prt_addr2(ocm_rd_addr_osw1),
.prt_bytes1(ocm_rd_bytes_osw0),
.prt_bytes2(ocm_rd_bytes_osw1),
.prt_dv1(ocm_rd_dv_osw0),
.prt_dv2(ocm_rd_dv_osw1),
.prt_req(ocm_rd_req_port1),
.prt_qos(ocm_rd_qos_port1),
.prt_data(ocm_rd_data_port1),
.prt_addr(ocm_rd_addr_port1),
.prt_bytes(ocm_rd_bytes_port1),
.prt_dv(ocm_rd_dv_port1)
);
endmodule
|
/*
* This module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
dut xx (.clk(clk));
// This defparam sets the desired with of the U instance vector.
defparam main.xx.wid = wid;
// These defparams set parameters within U instances.
defparam main.xx.sub[0].U.number = 0;
defparam main.xx.sub[1].U.number = 1;
defparam main.xx.sub[2].U.number = 2;
defparam main.xx.sub[3].U.number = 3;
defparam main.xx.sub[4].U.number = 4;
initial begin
clk = 0;
#1 clk = 1;
while (clk != 0)
#1 clk = clk << 1;
$finish(0);
end
endmodule // main
module dut #(parameter wid = 1) (input [wid-1:0] clk);
genvar i;
for (i = 0 ; i < wid ; i = i+1) begin : sub
target U (.clk(clk[i]));
end
endmodule //
module target(input wire clk);
parameter number = 999;
always @(posedge clk)
$display("%m: number=%0d", number);
endmodule // target
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: dtysky
//
// Create Date: 2015/01/16 18:34:13
// Design Name: ALU32
// Module Name: ADDSUB32
// Project Name: MIPS_CPU
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ADD(
input a,b,c,
output g,p,s
);
assign s = a ^ b ^ c;
assign g = a & b;
assign p = a | b;
endmodule
module G_P(
input[1:0] g,p,
input c_in,
output g_out,p_out,c_out
);
assign g_out = g[1] | p[1] & g[0];
assign p_out = p[1] & p[0];
assign c_out = g[0] | p[0] & c_in;
endmodule
// module ADDSUB32(
// input[31:0] a,b;
// input sub;
// output[31:0] s
// );
// wire[31:0] g,p;
// wire[31:0] s;
// generate
// genvar i;
// for (i=0;i<16;i=i+1)
// begin : ADD
// end
// endgenerate
// endmodule
module CLA2 (
input[1:0] a,b,
input c_in,
output g_out,p_out,
output[1:0] s
);
wire[1:0] g,p;
wire c_out;
ADD ADD0 (a[0],b[0],c_in,g[0],p[0],s[0]);
ADD ADD1 (a[1],b[1],c_out,g[1],p[1],s[1]);
G_P G_P0 (g,p,c_in,g_out,p_out,c_out);
endmodule
module CLA4 (
input[3:0] a,b,
input c_in,
output g_out,p_out,
output[3:0] s
);
wire[1:0] g,p;
wire c_out;
CLA2 CLA20 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]);
CLA2 CLA21 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]);
G_P G_P0 (g,p,c_in,g_out,p_out,c_out);
endmodule
module CLA8 (
input[7:0] a,b,
input c_in,
output g_out,p_out,
output[7:0] s
);
wire[1:0] g,p;
wire c_out;
CLA4 CLA40 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]);
CLA4 CLA41 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]);
G_P G_P0 (g,p,c_in,g_out,p_out,c_out);
endmodule
module CLA16 (
input[15:0] a,b,
input c_in,
output g_out,p_out,
output[15:0] s
);
wire[1:0] g,p;
wire c_out;
CLA8 CLA80 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]);
CLA8 CLA81 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]);
G_P G_P0 (g,p,c_in,g_out,p_out,c_out);
endmodule
module CLA32 (
input[31:0] a,b,
input c_in,
output[31:0] s
);
wire[1:0] g,p;
wire c_out;
CLA16 CLA160 (a[15:0],b[15:0],c_in,g[0],p[0],s[15:0]);
CLA16 CLA161 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]);
G_P G_P0 (g,p,c_in,g_out,p_out,c_out);
endmodule
module ADDSUB32(
input[31:0] a,b,
input sub,
output[31:0] s
);
CLA32 CLA320(a,b^{32{sub}},sub,s);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__XOR3_PP_SYMBOL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_SYMBOL_V
`define SKY130_FD_SC_LP__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v2_3_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Jul 25 2012
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_tempmon #
(
parameter TCQ = 100, // Register delay (sim only)
parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source
parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk)
parameter tTEMPSAMPLE = 10000000 // ps (10 us)
)
(
input clk, // Fabric clock
input xadc_clk,
input rst, // System reset
input [11:0] device_temp_i, // User device temperature
output [11:0] device_temp // Sampled temperature
);
//***************************************************************************
// Function cdiv
// Description:
// This function performs ceiling division (divide and round-up)
// Inputs:
// num: integer to be divided
// div: divisor
// Outputs:
// cdiv: result of ceiling division (num/div, rounded up)
//***************************************************************************
function integer cdiv (input integer num, input integer div);
begin
// perform division, then add 1 if and only if remainder is non-zero
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
end
endfunction // cdiv
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
// Synchronization registers
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5;
// Output register
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r;
wire [11:0] device_temp_lcl;
reg [3:0] sync_cntr = 4'b0000;
reg device_temp_sync_r4_neq_r3;
// (* ASYNC_REG = "TRUE" *) reg rst_r1;
// (* ASYNC_REG = "TRUE" *) reg rst_r2;
// // Synchronization rst to XADC clock domain
// always @(posedge xadc_clk) begin
// rst_r1 <= rst;
// rst_r2 <= rst_r1;
// end
// Synchronization counter
always @(posedge clk) begin
device_temp_sync_r1 <= #TCQ device_temp_lcl;
device_temp_sync_r2 <= #TCQ device_temp_sync_r1;
device_temp_sync_r3 <= #TCQ device_temp_sync_r2;
device_temp_sync_r4 <= #TCQ device_temp_sync_r3;
device_temp_sync_r5 <= #TCQ device_temp_sync_r4;
device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0;
end
always @(posedge clk)
if(rst || (device_temp_sync_r4_neq_r3))
sync_cntr <= #TCQ 4'b0000;
else if(~&sync_cntr)
sync_cntr <= #TCQ sync_cntr + 4'b0001;
always @(posedge clk)
if(&sync_cntr)
device_temp_r <= #TCQ device_temp_sync_r5;
assign device_temp = device_temp_r;
generate
if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature
assign device_temp_lcl = device_temp_i;
end else begin : xadc_supplied_temperature
// calculate polling timer width and limit
localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD);
localparam nTEMPSAMP_CLKS = nTEMPSAMP;
localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6;
localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS);
// Temperature sampler FSM encoding
localparam INIT_IDLE = 2'b00;
localparam REQUEST_READ_TEMP = 2'b01;
localparam WAIT_FOR_READ = 2'b10;
localparam READ = 2'b11;
// polling timer and tick
reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}};
reg sample_timer_en = 1'b0;
reg sample_timer_clr = 1'b0;
reg sample_en = 1'b0;
// Temperature sampler state
reg [2:0] tempmon_state = INIT_IDLE;
reg [2:0] tempmon_next_state = INIT_IDLE;
// XADC interfacing
reg xadc_den = 1'b0;
wire xadc_drdy;
wire [15:0] xadc_do;
reg xadc_drdy_r = 1'b0;
reg [15:0] xadc_do_r = 1'b0;
// Temperature storage
reg [11:0] temperature = 12'b0;
// Reset sync
(* ASYNC_REG = "TRUE" *) reg rst_r1;
(* ASYNC_REG = "TRUE" *) reg rst_r2;
// Synchronization rst to XADC clock domain
always @(posedge xadc_clk) begin
rst_r1 <= rst;
rst_r2 <= rst_r1;
end
// XADC polling interval timer
always @ (posedge xadc_clk)
if(rst_r2 || sample_timer_clr)
sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}};
else if(sample_timer_en)
sample_timer <= #TCQ sample_timer + 1'b1;
// XADC sampler state transition
always @(posedge xadc_clk)
if(rst_r2)
tempmon_state <= #TCQ INIT_IDLE;
else
tempmon_state <= #TCQ tempmon_next_state;
// Sample enable
always @(posedge xadc_clk)
sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0;
// XADC sampler next state transition
always @(tempmon_state or sample_en or xadc_drdy_r) begin
tempmon_next_state = tempmon_state;
case(tempmon_state)
INIT_IDLE:
if(sample_en)
tempmon_next_state = REQUEST_READ_TEMP;
REQUEST_READ_TEMP:
tempmon_next_state = WAIT_FOR_READ;
WAIT_FOR_READ:
if(xadc_drdy_r)
tempmon_next_state = READ;
READ:
tempmon_next_state = INIT_IDLE;
default:
tempmon_next_state = INIT_IDLE;
endcase
end
// Sample timer clear
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == WAIT_FOR_READ))
sample_timer_clr <= #TCQ 1'b0;
else if(tempmon_state == REQUEST_READ_TEMP)
sample_timer_clr <= #TCQ 1'b1;
// Sample timer enable
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP))
sample_timer_en <= #TCQ 1'b0;
else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ))
sample_timer_en <= #TCQ 1'b1;
// XADC enable
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == WAIT_FOR_READ))
xadc_den <= #TCQ 1'b0;
else if(tempmon_state == REQUEST_READ_TEMP)
xadc_den <= #TCQ 1'b1;
// Register XADC outputs
always @(posedge xadc_clk)
if(rst_r2) begin
xadc_drdy_r <= #TCQ 1'b0;
xadc_do_r <= #TCQ 16'b0;
end
else begin
xadc_drdy_r <= #TCQ xadc_drdy;
xadc_do_r <= #TCQ xadc_do;
end
// Store current read value
always @(posedge xadc_clk)
if(rst_r2)
temperature <= #TCQ 12'b0;
else if(tempmon_state == READ)
temperature <= #TCQ xadc_do_r[15:4];
assign device_temp_lcl = temperature;
// XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter
// 7 Series
// Xilinx HDL Libraries Guide, version 14.1
XADC #(
// INIT_40 - INIT_42: XADC configuration registers
.INIT_40(16'h1000), // config reg 0
.INIT_41(16'h2fff), // config reg 1
.INIT_42(16'h0800), // config reg 2
// INIT_48 - INIT_4F: Sequence Registers
.INIT_48(16'h0101), // Sequencer channel selection
.INIT_49(16'h0000), // Sequencer channel selection
.INIT_4A(16'h0100), // Sequencer Average selection
.INIT_4B(16'h0000), // Sequencer Average selection
.INIT_4C(16'h0000), // Sequencer Bipolar selection
.INIT_4D(16'h0000), // Sequencer Bipolar selection
.INIT_4E(16'h0000), // Sequencer Acq time selection
.INIT_4F(16'h0000), // Sequencer Acq time selection
// INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
.INIT_50(16'hb5ed), // Temp alarm trigger
.INIT_51(16'h57e4), // Vccint upper alarm limit
.INIT_52(16'ha147), // Vccaux upper alarm limit
.INIT_53(16'hca33), // Temp alarm OT upper
.INIT_54(16'ha93a), // Temp alarm reset
.INIT_55(16'h52c6), // Vccint lower alarm limit
.INIT_56(16'h9555), // Vccaux lower alarm limit
.INIT_57(16'hae4e), // Temp alarm OT reset
.INIT_58(16'h5999), // VBRAM upper alarm limit
.INIT_5C(16'h5111), // VBRAM lower alarm limit
// Simulation attributes: Set for proepr simulation behavior
.SIM_DEVICE("7SERIES") // Select target device (values)
)
XADC_inst (
// ALARMS: 8-bit (each) output: ALM, OT
.ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
.OT(), // 1-bit output: Over-Temperature alarm
// Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
.DO(xadc_do), // 16-bit output: DRP output data bus
.DRDY(xadc_drdy), // 1-bit output: DRP data ready
// STATUS: 1-bit (each) output: XADC status ports
.BUSY(), // 1-bit output: ADC busy output
.CHANNEL(), // 5-bit output: Channel selection outputs
.EOC(), // 1-bit output: End of Conversion
.EOS(), // 1-bit output: End of Sequence
.JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output
.JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock
.JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred
.MUXADDR(), // 5-bit output: External MUX channel decode
// Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
.VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input
.VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input
// CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
.CONVST(1'b0), // 1-bit input: Convert start input
.CONVSTCLK(1'b0), // 1-bit input: Convert start input
.RESET(1'b0), // 1-bit input: Active-high reset
// Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
.VN(1'b0), // 1-bit input: N-side analog input
.VP(1'b0), // 1-bit input: P-side analog input
// Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
.DADDR(7'b0), // 7-bit input: DRP address bus
.DCLK(xadc_clk), // 1-bit input: DRP clock
.DEN(xadc_den), // 1-bit input: DRP enable signal
.DI(16'b0), // 16-bit input: DRP input data bus
.DWE(1'b0) // 1-bit input: DRP write enable
);
// End of XADC_inst instantiation
end
endgenerate
endmodule
|
`timescale 1ps / 1ps
module fpu_mul_tb;
reg clk;
reg rst;
reg enable;
reg [1:0]rmode;
reg [63:0]opa;
reg [63:0]opb;
wire ready;
wire [63:0]outfp;
fpu_mul UUT (
.clk(clk),
.rst(rst),
.enable(enable),
.rmode(rmode),
.opa(opa),
.opb(opb),
.ready(ready),
.outfp(outfp));
initial
begin : STIMUL
#0
enable = 1'b0;
rst = 1'b1;
#10000; //0
enable = 1'b1;
rst = 1'b0;
//inputA:9.6300000000e+001
//inputB:-2.5600000000e-001
opa = 64'b0100000001011000000100110011001100110011001100110011001100110011;
opb = 64'b1011111111010000011000100100110111010010111100011010100111111100;
rmode = 2'b11;
#10000;
//inputA:3.6600000000e+000
//inputB:2.2500000000e+000
opa = 64'b0100000000001101010001111010111000010100011110101110000101001000;
opb = 64'b0100000000000010000000000000000000000000000000000000000000000000;
rmode = 2'b00;
#10000;
//inputA:-5.6970000000e+001
//inputB:1.2340000000e-001
opa = 64'b1100000001001100011111000010100011110101110000101000111101011100;
opb = 64'b0011111110111111100101110010010001110100010100111000111011110011;
rmode = 2'b11;
#10000;
//inputA:4.5680000000e+001
//inputB:2.1300000000e+000
opa = 64'b0100000001000110110101110000101000111101011100001010001111010111;
opb = 64'b0100000000000001000010100011110101110000101000111101011100001010;
rmode = 2'b00;
#10000;
//inputA:3.0000000000e-311
//inputB:-4.0000000000e+060
opa = 64'b0000000000000000000001011000010111000011011011101010101101110011;
opb = 64'b1100110010000011111010011110010011100100110000101111001101000100;
rmode = 2'b10;
#10000;
//inputA:4.6300000000e+001
//inputB:2.3110000000e+001
opa = 64'b0100000001000111001001100110011001100110011001100110011001100110;
opb = 64'b0100000000110111000111000010100011110101110000101000111101011100;
rmode = 2'b00;
#10000;
//inputA:5.0000000000e-250
//inputB:-1.#INF000000e+000
opa = 64'b0000110000101100101000111000111100110101000010110010001011011111;
opb = 64'b1111111111110000000000000000000000000000000000000000000000000000;
rmode = 2'b11;
#10000;
//inputA:
//inputB:
opa = 64'b0100000000111111111111111111111111111111111111111111111111111110;
opb = 64'b0100000000110000000000000000000000000000000000000000000000000001;
rmode = 2'b00;
#10000;
//inputA:1.2000000000e-001
//inputB:5.2000000000e+001
opa = 64'b0011111110111110101110000101000111101011100001010001111010111000;
opb = 64'b0100000001001010000000000000000000000000000000000000000000000000;
rmode = 2'b00;
#10000;
//inputA:8.9999000000e+004
//inputB:1.6000000000e+001
opa = 64'b0100000011110101111110001111000000000000000000000000000000000000;
opb = 64'b0100000000110000000000000000000000000000000000000000000000000000;
rmode = 2'b10;
#120000;
//Output:-2.465280000000000e+001
if (outfp==64'hC038A71DE69AD42D)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:8.235000000000001e+000
if (outfp==64'h40207851EB851EB8)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:-7.030098000000000e+000
if (outfp==64'hC01C1ED20296B335)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:9.729840000000000e+001
if (outfp==64'h40585318FC504817)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:-0
if (outfp==64'h8000000000000000)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:1.069993000000000e+003
if (outfp==64'h4090B7F8D4FDF3B6)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:-INF
if (outfp==64'hFFF0000000000000)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output
if (outfp==64'h4080000000000000)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:6.240000000000000e+000
if (outfp==64'h4018F5C28F5C28F6)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:1.439984000000000e+006
if (outfp==64'h4135F8F000000000)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#290000; //10000
$finish;
end // end of stimulus process
always
begin : CLOCK_clk
clk = 1'b0;
#5000;
clk = 1'b1;
#5000;
end
endmodule
|
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module tb_dsu_tx(clk, rst, TxD_start, TxD_data, TxD, TxD_busy);
input clk, rst, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter Baud = 115200;
//parameter Baud = 9600;
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
`ifdef FPGA_50MHZ
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h00097; //for 115200 BPS at 50MHz.
`endif
`ifdef FPGA_32MHZ
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h000ec; //for 115200 BPS at 32MHZ
`endif
`ifdef FPGA_64MHZ
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h00076; //for 115200 BPS at 64MHZ
`endif
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
BaudGeneratorAcc <= 16'h0000;
else if(TxD_busy)
BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
end
// Transmitter state machine
reg [3:0] state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_dataReg;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
TxD_dataReg <= 8'h00;
else if(TxD_ready & TxD_start)
TxD_dataReg <= TxD_data;
end
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
state <= 4'h0;
else
case(state)
4'b0000: if(TxD_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0011; // stop1
4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase
end
// Output mux
reg muxbit;
always @ ( * )
begin
case(state[2:0])
3'd0: muxbit <= TxD_dataD[0];
3'd1: muxbit <= TxD_dataD[1];
3'd2: muxbit <= TxD_dataD[2];
3'd3: muxbit <= TxD_dataD[3];
3'd4: muxbit <= TxD_dataD[4];
3'd5: muxbit <= TxD_dataD[5];
3'd6: muxbit <= TxD_dataD[6];
3'd7: muxbit <= TxD_dataD[7];
endcase
end
// Put together the start, data and stop bits
reg TxD;
always@(posedge clk or `dsu_RST_EVENT rst)
begin
if(rst==`dsu_RST_VALUE)
TxD <= 1'b1;
else
TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
end
endmodule |
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
University of Illinois/NCSA
Open Source License
Copyright(C) 2004, The Board of Trustees of the
University of Illinois. All rights reserved
IVM 1.0
Developed by:
Advanced Computing Systems Group
Center for Reliable and High-Performance Computing
University of Illinois at Urbana-Champaign
http://www.crhc.uiuc.edu/ACS
-- with support from --
Center for Circuits and Systems Solutions (C2S2)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the Software), to
deal with the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimers.
Redistributions in binary, gate-level, layout-level, or physical form must
reproduce the above copyright notice, this list of conditions and the
following disclaimers in the documentation and/or other materials provided
with the distribution.
Neither the names of Advanced Computing Systems Group, Center for Reliable
and High-Performance Computing, Center for Circuits and Systems Solution
(C2S2), University of Illinois at Urbana-Champaign, nor the names of its
contributors may be used to endorse or promote products derived from this
Software without specific prior written permission.
THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
WITH THE SOFTWARE.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*******************************************************************************
File: MUXn_8_1.v
Description: This file contains the definition of a n-bit 8-to-1 MUX
******************************************************************************/
`timescale 1ns/100ps
/*
* FUNC_NAME: MUXn_2_1
*
* DESCRIPTION:
* Definition for a n-bit 2-to-1 MUX
*
* INPUT:
* mux_in0 - the input to be output if mux_sel is 0
* mux_in1 - the input to be output if mux_sel is 1
* mux_sel - chooses between the inputs
*
* OUTPUT:
* mux_out - the output of the mux
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 25-apr-03
* LAST MODIFICATION:
* <modifier's name> <date modified>
*/
module MUXn_2_1(mux_in0, mux_in1, mux_sel, mux_out);
parameter MuxLen = 63;
// outputs
output [MuxLen:0] mux_out;
// inputs
input [MuxLen:0] mux_in0;
input [MuxLen:0] mux_in1;
input mux_sel;
// internal vars
// assign vars
// assing outputs
reg [MuxLen:0] mux_out;
// instantiate other modules
// code
always @(mux_in0 or mux_in1 or mux_sel)
begin
if (mux_sel == 1'b1)
mux_out = mux_in1;
else
mux_out = mux_in0;
end
endmodule // MUXn_2_1
/*
* FUNC_NAME: MUXn_4_1
*
* DESCRIPTION:
* Definition for a n-bit 4-to-1 MUX
*
* INPUT:
* mux_in0 - the input to be output if mux_sel is 00
* mux_in1 - the input to be output if mux_sel is 01
* mux_in2 - the input to be output if mux_sel is 10
* mux_in3 - the input to be output if mux_sel is 11
* mux_sel - chooses between the inputs
*
* OUTPUT:
* mux_out - the output of the mux
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 25-apr-03
* LAST MODIFICATION:
* <modifier's name> <date modified>
*/
module MUXn_4_1(mux_in0, mux_in1, mux_in2, mux_in3, mux_sel, mux_out);
parameter MuxLen = 63;
// outputs
output [MuxLen:0] mux_out;
// inputs
input [MuxLen:0] mux_in0;
input [MuxLen:0] mux_in1;
input [MuxLen:0] mux_in2;
input [MuxLen:0] mux_in3;
input [1:0] mux_sel;
// internal vars
wire [MuxLen:0] mux_tmp0;
wire [MuxLen:0] mux_tmp1;
// assign vars
// assing outputs
// instantiate other modules
MUXn_2_1 #(MuxLen) mux0(mux_in0, mux_in1, mux_sel[0], mux_tmp0);
MUXn_2_1 #(MuxLen) mux1(mux_in2, mux_in3, mux_sel[0], mux_tmp1);
MUXn_2_1 #(MuxLen) msel(mux_tmp0, mux_tmp1, mux_sel[1], mux_out);
// code
endmodule // MUXn_4_1
/*
* FUNC_NAME: MUXn_8_1
*
* DESCRIPTION:
* Definition for a n-bit 8-to-1 MUX
*
* INPUT:
* mux_in0 - the input to be output if mux_sel is 000
* mux_in1 - the input to be output if mux_sel is 001
* mux_in2 - the input to be output if mux_sel is 010
* mux_in3 - the input to be output if mux_sel is 011
* mux_in4 - the input to be output if mux_sel is 100
* mux_in5 - the input to be output if mux_sel is 101
* mux_in6 - the input to be output if mux_sel is 110
* mux_in7 - the input to be output if mux_sel is 111
* mux_sel - chooses between the inputs
*
* OUTPUT:
* mux_out - the output of the mux
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 25-apr-03
* LAST MODIFICATION:
* <modifier's name> <date modified>
*/
module MUXn_8_1(mux_in0, mux_in1, mux_in2, mux_in3, mux_in4, mux_in5, mux_in6, mux_in7, mux_sel, mux_out);
parameter MuxLen = 63;
// outputs
output [MuxLen:0] mux_out;
// inputs
input [MuxLen:0] mux_in0;
input [MuxLen:0] mux_in1;
input [MuxLen:0] mux_in2;
input [MuxLen:0] mux_in3;
input [MuxLen:0] mux_in4;
input [MuxLen:0] mux_in5;
input [MuxLen:0] mux_in6;
input [MuxLen:0] mux_in7;
input [2:0] mux_sel;
// internal vars
wire [MuxLen:0] mux_tmp0;
wire [MuxLen:0] mux_tmp1;
// assign vars
// assing outputs
// instantiate other modules
MUXn_4_1 #(MuxLen) mux0(mux_in0, mux_in1, mux_in2, mux_in3, mux_sel[1:0], mux_tmp0);
MUXn_4_1 #(MuxLen) mux1(mux_in4, mux_in5, mux_in6, mux_in7, mux_sel[1:0], mux_tmp1);
MUXn_2_1 #(MuxLen) msel(mux_tmp0, mux_tmp1, mux_sel[2], mux_out);
// code
endmodule // MUXn_8_1
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:25:14 02/11/2016
// Design Name:
// Module Name: memorycontroller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Asynchronous SRAM controller for byte access
// After outputting a byte to read, the result is available 70ns later.
module MemoryController(
input clk,
input read_a, // Set to 1 to read from RAM
input read_b, // Set to 1 to read from RAM
input write, // Set to 1 to write to RAM
input [21:0] addr, // Address to read / write
input [7:0] din, // Data to write
output reg [7:0] dout_a, // Last read data a
output reg [7:0] dout_b, // Last read data b
output reg busy, // 1 while an operation is in progress
output MemWR, // Write Enable. WRITE when Low.
output [18:0] MemAdr,
inout [7:0] MemDB,
input [13:0] debugaddr,
output [15:0] debugdata
);
reg MemOE;
reg RamWR;
reg sramWR = 1'b1;
reg [7:0] data_to_write;
reg [18:0] MemAdrReg;
wire [7:0] vram_dout;
wire [7:0] ram_dout;
wire [7:0] prgrom_dout;
wire [7:0] chrrom_dout;
wire [7:0] prgram_dout;
wire prgrom_ena = addr[21:18] == 4'b0000;
wire chrrom_ena = addr[21:18] == 4'b1000;
wire vram_ena = addr[21:18] == 4'b1100;
wire ram_ena = addr[21:18] == 4'b1110;
wire prgram_ena = addr[21:18] == 4'b1111;
wire [7:0] memory_dout = prgrom_ena ? prgrom_dout :
chrrom_ena ? chrrom_dout :
vram_ena ? vram_dout :
ram_ena ? ram_dout : prgram_dout;
ram2k vram(clk, vram_ena, RamWR, addr[10:0], data_to_write, vram_dout); // VRAM in BRAM
ram2k ram(clk, ram_ena, RamWR, addr[10:0], data_to_write, ram_dout); // RAM in BRAM
ram8k prg_ram(clk, prgram_ena, RamWR, addr[12:0], data_to_write, prgram_dout); // Cart RAM in BRAM
assign chrrom_dout = MemDB;
assign prgrom_dout = MemDB;
assign MemDB = (!sramWR) ? data_to_write : 8'bz;
assign MemAdr = MemAdrReg;
assign MemWR = sramWR;
reg [1:0] cycles;
reg r_read_a;
always @(posedge clk) begin
// Initiate read or write
if (!busy) begin
if (read_a || read_b || write) begin
if (prgrom_ena) begin
MemAdrReg <= {1'b0, addr[17:0]}; // PRGROM in SRAM
end else if (chrrom_ena) begin
MemAdrReg <= {1'b1, addr[17:0]}; // CHRROM in SRAM
end
RamWR <= write;
sramWR <= !((write == 1) && (prgrom_ena || chrrom_ena));
MemOE <= !(write == 0);
busy <= 1;
data_to_write <= din;
cycles <= 0;
r_read_a <= read_a;
end else begin
MemOE <= 1;
RamWR <= 0;
sramWR <= 1;
busy <= 0;
cycles <= 0;
end
end else begin
if (cycles == 2) begin
// Now we have waited 3x45 = 135ns, latch incoming data on read.
if (!MemOE) begin
if (r_read_a) dout_a <= memory_dout;
else dout_b <= memory_dout;
end
MemOE <= 1; // Deassert Output Enable.
RamWR <= 0; // Deassert Write
sramWR <= 1;
busy <= 0;
cycles <= 0;
end else begin
cycles <= cycles + 1;
end
end
end
endmodule // MemoryController
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O221AI_PP_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o221ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_PP_SYMBOL_V
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4kx16_dc.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);
always @(posedge clock)
case (addr)
3'd0 : data <= #1 -16'd49;
3'd1 : data <= #1 16'd165;
3'd2 : data <= #1 -16'd412;
3'd3 : data <= #1 16'd873;
3'd4 : data <= #1 -16'd1681;
3'd5 : data <= #1 16'd3135;
3'd6 : data <= #1 -16'd6282;
3'd7 : data <= #1 16'd20628;
endcase // case(addr)
endmodule // coeff_rom
|
/*
* Check the basic parsing.
*/
// A global timeunit and timeprecision are OK
timeunit 100us;
timeprecision 1us;
/*
* Check the various timeunit/precision combinations (this is valid SV syntax).
*/
// A local time unit is OK.
module check_tu;
timeunit 10us;
endmodule
// A local time precision is OK.
module check_tp;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK.
module check_tup;
timeunit 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK (check both orders).
module check_tpu;
timeprecision 10us;
timeunit 10us;
endmodule
/*
* Now do the same with repeat declarations (this is valid SV syntax).
*/
// A global timeunit and timeprecision are OK
timeunit 100us;
timeprecision 1us;
// A local time unit is OK.
module check_tu_d;
timeunit 10us;
timeunit 10us;
endmodule
// A local time precision is OK.
module check_tp_d;
timeprecision 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK.
module check_tup_d;
timeunit 10us;
timeprecision 10us;
timeunit 10us;
timeprecision 10us;
endmodule
// Both a local time unit and precision are OK (check both orders).
module check_tpu_d;
timeprecision 10us;
timeunit 10us;
timeprecision 10us;
timeunit 10us;
endmodule
/*
* Now check all the valid timeunit and time precision values.
*/
module check_100s;
timeunit 100s;
timeprecision 100s;
endmodule
module check_10s;
timeunit 10s;
timeprecision 10s;
endmodule
module check_1s;
timeunit 1s;
timeprecision 1s;
endmodule
module check_100ms;
timeunit 100ms;
timeprecision 100ms;
endmodule
module check_10ms;
timeunit 10ms;
timeprecision 10ms;
endmodule
module check_1ms;
timeunit 1ms;
timeprecision 1ms;
endmodule
module check_100us;
timeunit 100us;
timeprecision 100us;
endmodule
module check_10us;
timeunit 10us;
timeprecision 10us;
endmodule
module check_1us;
timeunit 1us;
timeprecision 1us;
endmodule
module check_100ns;
timeunit 100ns;
timeprecision 100ns;
endmodule
module check_10ns;
timeunit 10ns;
timeprecision 10ns;
endmodule
module check_1ns;
timeunit 1ns;
timeprecision 1ns;
endmodule
module check_100ps;
timeunit 100ps;
timeprecision 100ps;
endmodule
module check_10ps;
timeunit 10ps;
timeprecision 10ps;
endmodule
module check_1ps;
timeunit 1ps;
timeprecision 1ps;
endmodule
module check_100fs;
timeunit 100fs;
timeprecision 100fs;
endmodule
module check_10fs;
timeunit 10fs;
timeprecision 10fs;
endmodule
module check_1fs;
timeunit 1fs;
timeprecision 1fs;
endmodule
module check1;
initial begin
$printtimescale(check_100s);
$printtimescale(check_10s);
$printtimescale(check_1s);
$printtimescale(check_100ms);
$printtimescale(check_10ms);
$printtimescale(check_1ms);
$printtimescale(check_100us);
$printtimescale(check_10us);
$printtimescale(check_1us);
$printtimescale(check_100ns);
$printtimescale(check_10ns);
$printtimescale(check_1ns);
$printtimescale(check_100ps);
$printtimescale(check_10ps);
$printtimescale(check_1ps);
$printtimescale(check_100fs);
$printtimescale(check_10fs);
$printtimescale(check_1fs);
$display("");
$printtimescale(check_tu);
$printtimescale(check_tp);
$printtimescale(check_tup);
$printtimescale(check_tpu);
$display("");
$printtimescale(check_tu_d);
$printtimescale(check_tp_d);
$printtimescale(check_tup_d);
$printtimescale(check_tpu_d);
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casex/endcase w/ null_statement as default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
casex (val1 & val2 )
3'b000,3'b001: result = 0;
3'b11x: result = 2;
3'b001: result = 1;
default result = 3;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
if(result !=0)
begin
$display("FAILED casex 3.9E - default: ");
error = 1;
end
val1 = 3'b001;
val2 = 3'b011;
if(result !=1)
begin
$display("FAILED casex 3.9E - default: ");
error = 1;
end
val1 = 3'b111; // Should get no-action - expr = 3'b010
val2 = 3'b010;
if(result !=3)
begin
$display("FAILED casex 3.9E - default: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// file: hashing_clock_multiplier.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___400.000______0.000______50.0_______85.815_____89.971
// CLK_OUT2___100.000______0.000______50.0______112.316_____89.971
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________200.000____________0.010
`timescale 1ps/1ps
module hashing_clock_multiplier_clk_wiz
(// Clock in ports
input clk_in1_p,
input clk_in1_n,
// Clock out ports
output tx_hash_clk,
output tx_comm_clk
);
// Input buffering
//------------------------------------
IBUFGDS clkin1_ibufgds
(.O (clk_in1_hashing_clock_multiplier),
.I (clk_in1_p),
.IB (clk_in1_n));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_hashing_clock_multiplier;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (5.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (2.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout_hashing_clock_multiplier),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (tx_hash_clk_hashing_clock_multiplier),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (tx_comm_clk_hashing_clock_multiplier),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_hashing_clock_multiplier),
.CLKIN1 (clk_in1_hashing_clock_multiplier),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (tx_hash_clk),
.I (tx_hash_clk_hashing_clock_multiplier));
BUFG clkout2_buf
(.O (tx_comm_clk),
.I (tx_comm_clk_hashing_clock_multiplier));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off WIDTH
//============================================================
reg bad;
initial begin
bad=0;
c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888);
c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888);
c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0);
c96(96'h0003, 96'h0002, 96'h0001, 96'h0001);
c96(96'h0003, 96'h0003, 96'h0001, 96'h0000);
c96(96'h0003, 96'h0004, 96'h0000, 96'h0003);
c96(96'h0000, 96'hffff, 96'h0000, 96'h0000);
c96(96'hffff, 96'h0001, 96'hffff, 96'h0000);
c96(96'hffff, 96'hffff, 96'h0001, 96'h0000);
c96(96'hffff, 96'h0003, 96'h5555, 96'h0000);
c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000);
c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000);
c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe);
c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70);
c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000);
c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000);
c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005);
c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000);
c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001);
c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000);
c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001);
c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899);
c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000);
c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff);
c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab);
c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff);
c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000);
c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000);
c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000);
c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000);
c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000);
c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000);
c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000);
c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000);
c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000);
c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000);
c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002);
c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff);
c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888);
if (bad) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
task c96;
input [95:0] u;
input [95:0] v;
input [95:0] expq;
input [95:0] expr;
c96u( u, v, expq, expr);
c96s( u, v, expq, expr);
c96s(-u, v,-expq,-expr);
c96s( u,-v,-expq, expr);
c96s(-u,-v, expq,-expr);
endtask
task c96u;
input [95:0] u;
input [95:0] v;
input [95:0] expq;
input [95:0] expr;
reg [95:0] gotq;
reg [95:0] gotr;
gotq = u/v;
gotr = u%v;
if (gotq != expq && v!=0) begin
bad = 1;
end
if (gotr != expr && v!=0) begin
bad = 1;
end
if (bad
`ifdef TEST_VERBOSE
|| 1
`endif
) begin
$write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
// Test for v=0 to prevent Xs causing grief
if (gotq != expq && v!=0) $write(" BADQ");
if (gotr != expr && v!=0) $write(" BADR");
$write("\n");
end
endtask
task c96s;
input signed [95:0] u;
input signed [95:0] v;
input signed [95:0] expq;
input signed [95:0] expr;
reg signed [95:0] gotq;
reg signed [95:0] gotr;
gotq = u/v;
gotr = u%v;
if (gotq != expq && v!=0) begin
bad = 1;
end
if (gotr != expr && v!=0) begin
bad = 1;
end
if (bad
`ifdef TEST_VERBOSE
|| 1
`endif
) begin
$write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
// Test for v=0 to prevent Xs causing grief
if (gotq != expq && v!=0) $write(" BADQ");
if (gotr != expr && v!=0) $write(" BADR");
$write("\n");
end
endtask
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////////
module arduino_switch_digital_uart_bit(
// configuration
input gpio_sel, // 0=digital I/O, 1= uart
// Shield connector side
input tri_i_out, // data from shield pin to switch
output reg tri_o_out, // data from switch to shield pin
output reg tri_t_out, // tri state control from switch to shield pin
// PL side
// digital I/O
output tri_i_in, // data from switch to PL
input tri_o_in, // data from PL to switch
input tri_t_in, // tri state control from PL to switch
// RX and TX of UART
output rx_i_in, // rx data from switch to UART
input tx_o_in, // tx data from UART to switch
input tx_t_in // tx tri state control from UART to switch
);
reg [1:0] tri_i_out_demux;
assign {rx_i_in, tri_i_in} = tri_i_out_demux;
always @(gpio_sel, tri_o_in, tx_o_in)
case (gpio_sel)
1'h0: tri_o_out = tri_o_in; // digital I/O
1'h1: tri_o_out = tx_o_in; // tx
endcase
always @(gpio_sel, tri_i_out)
begin
tri_i_out_demux = {2{1'b0}};
case (gpio_sel)
1'h0: tri_i_out_demux[0] = tri_i_out; // digital I/O
1'h1: tri_i_out_demux[1] = tri_i_out; // rx
endcase
end
always @(gpio_sel, tri_t_in, tx_t_in)
case (gpio_sel)
1'h0: tri_t_out = tri_t_in; // digital I/O
1'h1: tri_t_out = tx_t_in; // tx
endcase
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_0_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_0_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_0_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_0_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
module top;
reg pass;
reg in;
wire ca;
assign ca = in;
initial begin
pass = 1'b1;
if (ca !== 1'bx || in !== 1'bx) begin
$display("Failed T0 check, in %b, ca %b", in, ca);
pass = 1'b0;
end
in = 1'b0;
#1;
if (ca !== 1'b0 || in !== 1'b0) begin
$display("Failed 0 check, in %b, ca %b", in, ca);
pass = 1'b0;
end
in = 1'b1;
#1;
if (ca !== 1'b1 || in !== 1'b1) begin
$display("Failed 1 check, in %b, ca %b", in, ca);
pass = 1'b0;
end
force ca = 1'b0;
#1;
if (ca !== 1'b0 || in !== 1'b1) begin
$display("Failed force 0 check, in %b, ca %b", in, ca);
pass = 1'b0;
end
in = 1'bx;
#1;
if (ca !== 1'b0 || in !== 1'bx) begin
$display("Failed change a check, in %b, ca %b", in, ca);
pass = 1'b0;
end
force ca = 1'b1;
#1;
if (ca !== 1'b1 || in !== 1'bx) begin
$display("Failed force 1 check, in %b, ca %b", in, ca);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
module MicrophoneSampler(
output spi_clk,
output spi_mosi,
output spi_cs,
input spi_miso,
input clk,
input rst,
output [7:0] sample
);
localparam DELAY_20KHZ = 16'h1388; // decimal 5000 (100 mill / 20,000 = 5000)
localparam DELAY_40KHZ = 16'h09C4; // decimal 2500 (100 mill / 40,000 = 2500)
reg [12:0] counter; // 16-bit counter
reg start_conv;
wire [9:0] sample_out;
Microphone mic(spi_clk, spi_mosi, spi_cs, spi_miso, clk, rst, start_conv, , sample_out);
assign sample = sample_out[9:2];
always @ (posedge clk) begin
if(rst) begin
counter <= 13'b0;
start_conv <= 1'b0;
end else begin
if(counter == DELAY_40KHZ) begin
start_conv <= 1'b1;
counter <= 13'b0;
end
else begin
start_conv <= 1'b0;
counter <= counter + 1'b1;
/*
sample <= 10'h0;
if(sample_out >= 10'h1FF)
sample[0] <= 1'b1;
if(sample_out >= 10'h23F)
sample[1] <= 1'b1;
if(sample_out >= 10'h27F)
sample[2] <= 1'b1;
if(sample_out >= 10'h2BF)
sample[3] <= 1'b1;
if(sample_out >= 10'h2FF)
sample[4] <= 1'b1;
if(sample_out >= 10'h33F)
sample[5] <= 1'b1;
if(sample_out >= 10'h37F)
sample[6] <= 1'b1;
if(sample_out >= 10'h3BF)
sample[7] <= 1'b1;
*/
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Company: Xilinx
// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
// Sam Bobrowicz (Digilent Inc.)
// Date: 5/30/2013
// Design Name: MMCME2 DRP
// Module Name: mmcme2_drp.v
// Version: 1.03
// Target Devices: 7 Series
// Tool versions: 14.5
// Description: This calls the DRP register calculation functions and
// provides a state machine to perform MMCM reconfiguration
// based on the calulated values stored in a initialized
// ROM.
//
// Revisions: 1/13/11 Updated ROM[18,41] LOCKED bitmask to 16'HFC00
// 5/30/13 Adding Fractional support for CLKFBOUT_MULT_F, CLKOUT0_DIVIDE_F
// 2/02/14 (Digilent, Sam Bobrowicz) Modified to use values provided from a top
// level to output CLK0 with runtime configurable frequency. Also added
// parameter for controlling what the default output clock is (affecting
// the automatically generated timing constraints).
//
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2009-2010 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module mmcme2_drp
#(
parameter DIV_F = 5
)
(
// These signals are controlled by user logic interface and are covered
// in more detail within the XAPP.
input SEN,
input SCLK,
input RST,
output reg SRDY,
input [35:0] S1_CLKOUT0,
input [35:0] S1_CLKFBOUT,
input [13:0] S1_DIVCLK,
input [39:0] S1_LOCK,
input [9:0] S1_DIGITAL_FILT,
input REF_CLK,
output PXL_CLK,
output CLKFBOUT_O,
input CLKFBOUT_I,
output LOCKED_O
);
// 100 ps delay for behavioral simulations
localparam TCQ = 100;
wire [38:0] rom [12:0]; // 39 bit word 13 words deep array of reg writes to perform (no longer a ROM)
reg [3:0] rom_addr;
reg [38:0] rom_do;
reg next_srdy;
reg [3:0] next_rom_addr;
reg [6:0] next_daddr;
reg next_dwe;
reg next_den;
reg next_rst_mmcm;
reg [15:0] next_di;
// These signals are to be connected to the MMCM_ADV by port name.
// Their use matches the MMCM port description in the Device User Guide.
wire [15:0] DO;
wire DRDY;
wire LOCKED;
reg DWE;
reg DEN;
reg [6:0] DADDR;
reg [15:0] DI;
wire DCLK;
reg RST_MMCM;
// Pass SCLK to DCLK for the MMCM
assign DCLK = SCLK;
// rom entries contain (in order) the address, a bitmask, and a bitset
//***********************************************************************
// State 1 Initialization
//***********************************************************************
// Store the power bits
assign rom[0] = {7'h28, 16'h0000, 16'hFFFF};
// Store CLKOUT0 divide and phase
assign rom[1] = {7'h08, 16'h1000, S1_CLKOUT0[15:0]};
assign rom[2] = {7'h09, 16'h8000, S1_CLKOUT0[31:16]};
// Store CLKOUT0 additional frac values
assign rom[3] = {7'h07, 16'hC3FF, 2'b00 , S1_CLKOUT0[35:32], 10'h000};
// Store CLKFBOUT additional frac values
assign rom[4] = {7'h13, 16'hC3FF, 2'b00 , S1_CLKFBOUT[35:32], 10'h000};
// Store the input divider
assign rom[5] = {7'h16, 16'hC000, {2'h0, S1_DIVCLK[13:0]} };
// Store CLKFBOUT divide and phase
assign rom[6] = {7'h14, 16'h1000, S1_CLKFBOUT[15:0]};
assign rom[7] = {7'h15, 16'h8000, S1_CLKFBOUT[31:16]};
// Store the lock settings
assign rom[8] = {7'h18, 16'hFC00, {6'h00, S1_LOCK[29:20]} };
assign rom[9] = {7'h19, 16'h8000, {1'b0 , S1_LOCK[34:30], S1_LOCK[9:0]} };
assign rom[10] = {7'h1A, 16'h8000, {1'b0 , S1_LOCK[39:35], S1_LOCK[19:10]} };
// Store the filter settings
assign rom[11] = {7'h4E, 16'h66FF,
S1_DIGITAL_FILT[9], 2'h0, S1_DIGITAL_FILT[8:7], 2'h0,
S1_DIGITAL_FILT[6], 8'h00 };
assign rom[12] = {7'h4F, 16'h666F,
S1_DIGITAL_FILT[5], 2'h0, S1_DIGITAL_FILT[4:3], 2'h0,
S1_DIGITAL_FILT[2:1], 2'h0, S1_DIGITAL_FILT[0], 4'h0 };
// Output the initialized rom value based on rom_addr each clock cycle
always @(posedge SCLK) begin
rom_do<= #TCQ rom[rom_addr];
end
//**************************************************************************
// Everything below is associated whith the state machine that is used to
// Read/Modify/Write to the MMCM.
//**************************************************************************
// State Definitions
localparam RESTART = 4'h1;
localparam WAIT_LOCK = 4'h2;
localparam WAIT_SEN = 4'h3;
localparam ADDRESS = 4'h4;
localparam WAIT_A_DRDY = 4'h5;
localparam BITMASK = 4'h6;
localparam BITSET = 4'h7;
localparam WRITE = 4'h8;
localparam WAIT_DRDY = 4'h9;
// State sync
reg [3:0] current_state = RESTART;
reg [3:0] next_state = RESTART;
// These variables are used to keep track of the number of iterations that
// each state takes to reconfigure.
// STATE_COUNT_CONST is used to reset the counters and should match the
// number of registers necessary to reconfigure each state.
localparam STATE_COUNT_CONST = 13;
reg [3:0] state_count = STATE_COUNT_CONST;
reg [3:0] next_state_count = STATE_COUNT_CONST;
// This block assigns the next register value from the state machine below
always @(posedge SCLK) begin
DADDR <= #TCQ next_daddr;
DWE <= #TCQ next_dwe;
DEN <= #TCQ next_den;
RST_MMCM <= #TCQ next_rst_mmcm;
DI <= #TCQ next_di;
SRDY <= #TCQ next_srdy;
rom_addr <= #TCQ next_rom_addr;
state_count <= #TCQ next_state_count;
end
// This block assigns the next state, reset is syncronous.
always @(posedge SCLK) begin
if(RST) begin
current_state <= #TCQ RESTART;
end else begin
current_state <= #TCQ next_state;
end
end
always @* begin
// Setup the default values
next_srdy = 1'b0;
next_daddr = DADDR;
next_dwe = 1'b0;
next_den = 1'b0;
next_rst_mmcm = RST_MMCM;
next_di = DI;
next_rom_addr = rom_addr;
next_state_count = state_count;
case (current_state)
// If RST is asserted reset the machine
RESTART: begin
next_daddr = 7'h00;
next_di = 16'h0000;
next_rom_addr = 6'h00;
next_rst_mmcm = 1'b1;
next_state = WAIT_LOCK;
end
// Waits for the MMCM to assert LOCKED - once it does asserts SRDY
WAIT_LOCK: begin
// Make sure reset is de-asserted
next_rst_mmcm = 1'b0;
// Reset the number of registers left to write for the next
// reconfiguration event.
next_state_count = STATE_COUNT_CONST ;
if(LOCKED) begin
// MMCM is locked, go on to wait for the SEN signal
next_state = WAIT_SEN;
// Assert SRDY to indicate that the reconfiguration module is
// ready
next_srdy = 1'b1;
end else begin
// Keep waiting, locked has not asserted yet
next_state = WAIT_LOCK;
end
end
// Wait for the next SEN pulse and set the ROM addr appropriately
WAIT_SEN: begin
if (SEN) begin
// SEN was asserted
next_rom_addr = 8'h00;
// Go on to address the MMCM
next_state = ADDRESS;
end else begin
// Keep waiting for SEN to be asserted
next_state = WAIT_SEN;
end
end
// Set the address on the MMCM and assert DEN to read the value
ADDRESS: begin
// Reset the DCM through the reconfiguration
next_rst_mmcm = 1'b1;
// Enable a read from the MMCM and set the MMCM address
next_den = 1'b1;
next_daddr = rom_do[38:32];
// Wait for the data to be ready
next_state = WAIT_A_DRDY;
end
// Wait for DRDY to assert after addressing the MMCM
WAIT_A_DRDY: begin
if (DRDY) begin
// Data is ready, mask out the bits to save
next_state = BITMASK;
end else begin
// Keep waiting till data is ready
next_state = WAIT_A_DRDY;
end
end
// Zero out the bits that are not set in the mask stored in rom
BITMASK: begin
// Do the mask
next_di = rom_do[31:16] & DO;
// Go on to set the bits
next_state = BITSET;
end
// After the input is masked, OR the bits with calculated value in rom
BITSET: begin
// Set the bits that need to be assigned
next_di = rom_do[15:0] | DI;
// Set the next address to read from ROM
next_rom_addr = rom_addr + 1'b1;
// Go on to write the data to the MMCM
next_state = WRITE;
end
// DI is setup so assert DWE, DEN, and RST_MMCM. Subtract one from the
// state count and go to wait for DRDY.
WRITE: begin
// Set WE and EN on MMCM
next_dwe = 1'b1;
next_den = 1'b1;
// Decrement the number of registers left to write
next_state_count = state_count - 1'b1;
// Wait for the write to complete
next_state = WAIT_DRDY;
end
// Wait for DRDY to assert from the MMCM. If the state count is not 0
// jump to ADDRESS (continue reconfiguration). If state count is
// 0 wait for lock.
WAIT_DRDY: begin
if(DRDY) begin
// Write is complete
if(state_count > 0) begin
// If there are more registers to write keep going
next_state = ADDRESS;
end else begin
// There are no more registers to write so wait for the MMCM
// to lock
next_state = WAIT_LOCK;
end
end else begin
// Keep waiting for write to complete
next_state = WAIT_DRDY;
end
end
// If in an unknown state reset the machine
default: begin
next_state = RESTART;
end
endcase
end
//////////////////////////////////////////////////////////////////////////////////////
///////// MMCM Instantiation ///////////
//////////////////////////////////////////////////////////////////////////////////////
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (DIV_F),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (CLKFBOUT_O),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (PXL_CLK),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (CLKFBOUT_I),
.CLKIN1 (REF_CLK),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (DADDR),
.DCLK (DCLK),
.DEN (DEN),
.DI (DI),
.DO (DO),
.DRDY (DRDY),
.DWE (DWE),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RST_MMCM));
assign LOCKED_O = LOCKED;
endmodule
|
// diseño de una fifo ciclica, para implementar en cada bloque de proyecto
// ferney alberto beltran 2016 electrónica digital 1 universidad Nacional
module fifo
#(
parameter adr_width = 10,
parameter dat_width = 8
)
(
input clk, reset,
input rd, wr,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(posedge reset, posedge wr, posedge rd)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule
|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_external_sdram_controller_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 42: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 42: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 42: 0] entry_0;
reg [ 42: 0] entry_1;
wire full;
reg rd_address;
reg [ 42: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_external_sdram_controller (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 12: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 23: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 23: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 8: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 23: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 42: 0] fifo_read_data;
reg [ 12: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 3: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 14: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 12: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
wasca_external_sdram_controller_input_efifo_module the_wasca_external_sdram_controller_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[23],f_addr[9]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 11600;
else if (refresh_counter == 0)
refresh_counter <= 18095;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {13{1'b1}};
i_count <= {4{1'b0}};
end
else
begin
i_addr <= {13{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 2;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 8;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{3{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[23],active_addr[9]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[22 : 10]} == {f_addr[22 : 10]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {4{1'b0}},f_addr[8 : 0] } : { {4{1'b0}},active_addr[8 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 13'b0000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 4'b0000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 2;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[22 : 10];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 3;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 2;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {13{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 8;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_1_V
`define SKY130_FD_SC_LS__O311A_1_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_1_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_1024x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x32_bist artisan_ssp(
`else
art_hssp_1024x32 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x32_bist vs_ssp(
`else
vs_hdsp_1024x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:0]),
.EN(ce),
.WE(we),
.DO(doq[3:0])
);
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:4]),
.EN(ce),
.WE(we),
.DO(doq[7:4])
);
//
// Block 2
//
RAMB4_S4 ramb4_s4_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[11:8]),
.EN(ce),
.WE(we),
.DO(doq[11:8])
);
//
// Block 3
//
RAMB4_S4 ramb4_s4_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:12]),
.EN(ce),
.WE(we),
.DO(doq[15:12])
);
//
// Block 4
//
RAMB4_S4 ramb4_s4_4(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[19:16]),
.EN(ce),
.WE(we),
.DO(doq[19:16])
);
//
// Block 5
//
RAMB4_S4 ramb4_s4_5(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[23:20]),
.EN(ce),
.WE(we),
.DO(doq[23:20])
);
//
// Block 6
//
RAMB4_S4 ramb4_s4_6(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[27:24]),
.EN(ce),
.WE(we),
.DO(doq[27:24])
);
//
// Block 7
//
RAMB4_S4 ramb4_s4_7(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[31:28]),
.EN(ce),
.WE(we),
.DO(doq[31:28])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.ADDR({1'b0,addr}),
.DI(di[7:0]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[7:0]),
.DOP()
);
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.ADDR({1'b0,addr}),
.DI(di[15:8]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[15:8]),
.DOP()
);
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.ADDR({1'b0,addr}),
.DI(di[23:16]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[23:16]),
.DOP()
);
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.ADDR({1'b0,addr}),
.DI(di[31:24]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[31:24]),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 c2 c3 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" clk2_divide_by=50 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" clk3_divide_by=2 clk3_duty_cycle=50 clk3_multiply_by=1 clk3_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_USED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:21:18:09:22:SJ cbx_altiobuf_bidir 2015:10:21:18:09:22:SJ cbx_altiobuf_in 2015:10:21:18:09:22:SJ cbx_altiobuf_out 2015:10:21:18:09:22:SJ cbx_altpll 2015:10:21:18:09:23:SJ cbx_altpll_avalon 2015:10:21:18:09:22:SJ cbx_cycloneii 2015:10:21:18:09:23:SJ cbx_lpm_add_sub 2015:10:21:18:09:23:SJ cbx_lpm_compare 2015:10:21:18:09:23:SJ cbx_lpm_counter 2015:10:21:18:09:23:SJ cbx_lpm_decode 2015:10:21:18:09:23:SJ cbx_lpm_mux 2015:10:21:18:09:23:SJ cbx_lpm_shiftreg 2015:10:21:18:09:23:SJ cbx_mgl 2015:10:21:18:12:49:SJ cbx_nadder 2015:10:21:18:09:23:SJ cbx_stratix 2015:10:21:18:09:23:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_stratixiii 2015:10:21:18:09:23:SJ cbx_stratixv 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 15.1 cbx_mgl 2015:10:21:18:12:49:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 15.1 cbx_mgl 2015:10:21:18:12:49:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module niosii_altpll_0_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //niosii_altpll_0_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module niosii_altpll_0_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
niosii_altpll_0_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //niosii_altpll_0_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" clk2_divide_by=50 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" clk3_divide_by=2 clk3_duty_cycle=50 clk3_multiply_by=1 clk3_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_USED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:21:18:09:22:SJ cbx_altiobuf_bidir 2015:10:21:18:09:22:SJ cbx_altiobuf_in 2015:10:21:18:09:22:SJ cbx_altiobuf_out 2015:10:21:18:09:22:SJ cbx_altpll 2015:10:21:18:09:23:SJ cbx_cycloneii 2015:10:21:18:09:23:SJ cbx_lpm_add_sub 2015:10:21:18:09:23:SJ cbx_lpm_compare 2015:10:21:18:09:23:SJ cbx_lpm_counter 2015:10:21:18:09:23:SJ cbx_lpm_decode 2015:10:21:18:09:23:SJ cbx_lpm_mux 2015:10:21:18:09:23:SJ cbx_mgl 2015:10:21:18:12:49:SJ cbx_nadder 2015:10:21:18:09:23:SJ cbx_stratix 2015:10:21:18:09:23:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_stratixiii 2015:10:21:18:09:23:SJ cbx_stratixv 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ VERSION_END
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module niosii_altpll_0_altpll_non2
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 2,
pll7.clk0_phase_shift = "0",
pll7.clk1_divide_by = 1,
pll7.clk1_duty_cycle = 50,
pll7.clk1_multiply_by = 1,
pll7.clk1_phase_shift = "0",
pll7.clk2_divide_by = 50,
pll7.clk2_duty_cycle = 50,
pll7.clk2_multiply_by = 1,
pll7.clk2_phase_shift = "0",
pll7.clk3_divide_by = 2,
pll7.clk3_duty_cycle = 50,
pll7.clk3_multiply_by = 1,
pll7.clk3_phase_shift = "0",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //niosii_altpll_0_altpll_non2
//synthesis_resources = cycloneive_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module niosii_altpll_0
(
address,
areset,
c0,
c1,
c2,
c3,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
output c3;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
niosii_altpll_0_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
niosii_altpll_0_altpll_non2 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
c2 = wire_sd1_clk[2],
c3 = wire_sd1_clk[3],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //niosii_altpll_0
//VALID FILE
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:03:52 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0_1/system_ov7670_controller_0_0_stub.v
// Design : system_ov7670_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_0_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
`default_nettype none
module square_root32(
input wire iCLOCK,
input wire inRESET,
//Input Data
input wire iDATA_REQ,
output wire oDATA_BUSY,
input wire [31:0] iDATA,
//Output
output wire oDATA_VALID,
input wire iDATA_BUSY,
output wire [15:0] oDATA
);
localparam P_L_ELEMENTS0_DFF = 0;
localparam P_L_ELEMENTS1_DFF = 1;
localparam P_L_ELEMENTS2_DFF = 0;
localparam P_L_ELEMENTS3_DFF = 1;
localparam P_L_ELEMENTS4_DFF = 0;
localparam P_L_ELEMENTS5_DFF = 1;
localparam P_L_ELEMENTS6_DFF = 0;
localparam P_L_ELEMENTS7_DFF = 1;
localparam P_L_ELEMENTS8_DFF = 0;
localparam P_L_ELEMENTS9_DFF = 1;
localparam P_L_ELEMENTS10_DFF = 0;
localparam P_L_ELEMENTS11_DFF = 1;
localparam P_L_ELEMENTS12_DFF = 0;
localparam P_L_ELEMENTS13_DFF = 1;
localparam P_L_ELEMENTS14_DFF = 0;
localparam P_L_ELEMENTS15_DFF = 1;
wire [15:0] elements_out_valid;
wire [15:0] element_out_busy;
wire [0:0] element_out_p0;
wire [1:0] element_out_p1;
wire [2:0] element_out_p2;
wire [3:0] element_out_p3;
wire [4:0] element_out_p4;
wire [5:0] element_out_p5;
wire [6:0] element_out_p6;
wire [7:0] element_out_p7;
wire [8:0] element_out_p8;
wire [9:0] element_out_p9;
wire [10:0] element_out_p10;
wire [11:0] element_out_p11;
wire [12:0] element_out_p12;
wire [13:0] element_out_p13;
wire [14:0] element_out_p14;
wire [15:0] element_out_p15;
wire [31:0] element_out_i[0:15];
square_root32_element #(2, P_L_ELEMENTS0_DFF) SQUARE_ELEMENTS0(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(iDATA_REQ),
.oDATA_BUSY(oDATA_BUSY),
.iDATA_P(1'b1),
.iDATA_I(iDATA),
//Output
.oDATA_VALID(elements_out_valid[0]),
.iDATA_BUSY(element_out_busy[0]),
.oDATA_P(element_out_p0),
.oDATA_I(element_out_i[0])
);
square_root32_element #(4, P_L_ELEMENTS1_DFF) SQUARE_ELEMENTS1(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[0]),
.oDATA_BUSY(element_out_busy[0]),
.iDATA_P({element_out_p0, 1'b1}),
.iDATA_I(element_out_i[0]),
//Output
.oDATA_VALID(elements_out_valid[1]),
.iDATA_BUSY(element_out_busy[1]),
.oDATA_P(element_out_p1),
.oDATA_I(element_out_i[1])
);
square_root32_element #(6, P_L_ELEMENTS2_DFF) SQUARE_ELEMENTS2(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[1]),
.oDATA_BUSY(element_out_busy[1]),
.iDATA_P({element_out_p1, 1'b1}),
.iDATA_I(element_out_i[1]),
//Output
.oDATA_VALID(elements_out_valid[2]),
.iDATA_BUSY(element_out_busy[2]),
.oDATA_P(element_out_p2),
.oDATA_I(element_out_i[2])
);
square_root32_element #(8, P_L_ELEMENTS3_DFF) SQUARE_ELEMENTS3(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[2]),
.oDATA_BUSY(element_out_busy[2]),
.iDATA_P({element_out_p2, 1'b1}),
.iDATA_I(element_out_i[2]),
//Output
.oDATA_VALID(elements_out_valid[3]),
.iDATA_BUSY(element_out_busy[3]),
.oDATA_P(element_out_p3),
.oDATA_I(element_out_i[3])
);
square_root32_element #(10, P_L_ELEMENTS4_DFF) SQUARE_ELEMENTS4(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[3]),
.oDATA_BUSY(element_out_busy[3]),
.iDATA_P({element_out_p3, 1'b1}),
.iDATA_I(element_out_i[3]),
//Output
.oDATA_VALID(elements_out_valid[4]),
.iDATA_BUSY(element_out_busy[4]),
.oDATA_P(element_out_p4),
.oDATA_I(element_out_i[4])
);
square_root32_element #(12, P_L_ELEMENTS5_DFF) SQUARE_ELEMENTS5(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[4]),
.oDATA_BUSY(element_out_busy[4]),
.iDATA_P({element_out_p4, 1'b1}),
.iDATA_I(element_out_i[4]),
//Output
.oDATA_VALID(elements_out_valid[5]),
.iDATA_BUSY(element_out_busy[5]),
.oDATA_P(element_out_p5),
.oDATA_I(element_out_i[5])
);
square_root32_element #(14, P_L_ELEMENTS6_DFF) SQUARE_ELEMENTS6(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[5]),
.oDATA_BUSY(element_out_busy[5]),
.iDATA_P({element_out_p5, 1'b1}),
.iDATA_I(element_out_i[5]),
//Output
.oDATA_VALID(elements_out_valid[6]),
.iDATA_BUSY(element_out_busy[6]),
.oDATA_P(element_out_p6),
.oDATA_I(element_out_i[6])
);
square_root32_element #(16, P_L_ELEMENTS7_DFF) SQUARE_ELEMENTS7(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[6]),
.oDATA_BUSY(element_out_busy[6]),
.iDATA_P({element_out_p6, 1'b1}),
.iDATA_I(element_out_i[6]),
//Output
.oDATA_VALID(elements_out_valid[7]),
.iDATA_BUSY(element_out_busy[7]),
.oDATA_P(element_out_p7),
.oDATA_I(element_out_i[7])
);
square_root32_element #(18, P_L_ELEMENTS8_DFF) SQUARE_ELEMENTS8(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[7]),
.oDATA_BUSY(element_out_busy[7]),
.iDATA_P({element_out_p7, 1'b1}),
.iDATA_I(element_out_i[7]),
//Output
.oDATA_VALID(elements_out_valid[8]),
.iDATA_BUSY(element_out_busy[8]),
.oDATA_P(element_out_p8),
.oDATA_I(element_out_i[8])
);
square_root32_element #(20, P_L_ELEMENTS9_DFF) SQUARE_ELEMENTS9(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[8]),
.oDATA_BUSY(element_out_busy[8]),
.iDATA_P({element_out_p8, 1'b1}),
.iDATA_I(element_out_i[8]),
//Output
.oDATA_VALID(elements_out_valid[9]),
.iDATA_BUSY(element_out_busy[9]),
.oDATA_P(element_out_p9),
.oDATA_I(element_out_i[9])
);
square_root32_element #(22, P_L_ELEMENTS10_DFF) SQUARE_ELEMENTS10(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[9]),
.oDATA_BUSY(element_out_busy[9]),
.iDATA_P({element_out_p9, 1'b1}),
.iDATA_I(element_out_i[9]),
//Output
.oDATA_VALID(elements_out_valid[10]),
.iDATA_BUSY(element_out_busy[10]),
.oDATA_P(element_out_p10),
.oDATA_I(element_out_i[10])
);
square_root32_element #(24, P_L_ELEMENTS11_DFF) SQUARE_ELEMENTS11(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[10]),
.oDATA_BUSY(element_out_busy[10]),
.iDATA_P({element_out_p10, 1'b1}),
.iDATA_I(element_out_i[10]),
//Output
.oDATA_VALID(elements_out_valid[11]),
.iDATA_BUSY(element_out_busy[11]),
.oDATA_P(element_out_p11),
.oDATA_I(element_out_i[11])
);
square_root32_element #(26, P_L_ELEMENTS12_DFF) SQUARE_ELEMENTS12(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[11]),
.oDATA_BUSY(element_out_busy[11]),
.iDATA_P({element_out_p11, 1'b1}),
.iDATA_I(element_out_i[11]),
//Output
.oDATA_VALID(elements_out_valid[12]),
.iDATA_BUSY(element_out_busy[12]),
.oDATA_P(element_out_p12),
.oDATA_I(element_out_i[12])
);
square_root32_element #(28, P_L_ELEMENTS13_DFF) SQUARE_ELEMENTS13(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[12]),
.oDATA_BUSY(element_out_busy[12]),
.iDATA_P({element_out_p12, 1'b1}),
.iDATA_I(element_out_i[12]),
//Output
.oDATA_VALID(elements_out_valid[13]),
.iDATA_BUSY(element_out_busy[13]),
.oDATA_P(element_out_p13),
.oDATA_I(element_out_i[13])
);
square_root32_element #(30, P_L_ELEMENTS14_DFF) SQUARE_ELEMENTS14(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[13]),
.oDATA_BUSY(element_out_busy[13]),
.iDATA_P({element_out_p13, 1'b1}),
.iDATA_I(element_out_i[13]),
//Output
.oDATA_VALID(elements_out_valid[14]),
.iDATA_BUSY(element_out_busy[14]),
.oDATA_P(element_out_p14),
.oDATA_I(element_out_i[14])
);
square_root32_element #(32, P_L_ELEMENTS15_DFF) SQUARE_ELEMENTS15(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Input
.iDATA_REQ(elements_out_valid[14]),
.oDATA_BUSY(element_out_busy[14]),
.iDATA_P({element_out_p14, 1'b1}),
.iDATA_I(element_out_i[14]),
//Output
.oDATA_VALID(elements_out_valid[15]),
.iDATA_BUSY(element_out_busy[15]),
.oDATA_P(element_out_p15),
.oDATA_I(element_out_i[15])
);
assign oDATA_VALID = elements_out_valid[15];
assign element_out_busy[15] = iDATA_BUSY;
assign oDATA = element_out_p15;
endmodule
`default_nettype wire
|
/*******************************************************************************
* Function: Packet-->Memory Mapped Transaction Converter
* Author: Andreas Olofsson
* License: MIT (see LICENSE file in OH! repository)
*
* Documentation:
*
* see ./enoc_pack.v for packet formatting
*
******************************************************************************/
module enoc_unpack
#(parameter AW = 32, // address width
parameter PW = 104) // packet width
(
//Input packet
input [PW-1:0] packet_in,
//Write
output cmd_write,//start write
output cmd_write_stop,//stop burst
//Read
output cmd_read,
//Atomic read/write
output cmd_atomic_add,
output cmd_atomic_and,
output cmd_atomic_or,
output cmd_atomic_xor,
output cmd_cas,
//Command Fields
output [3:0] cmd_opcode,//raw opcode
output [3:0] cmd_length,//bust length(up to 16)
output [2:0] cmd_size,//size of each transfer
output [7:0] cmd_user, //user field
//Address/Data
output [AW-1:0] dstaddr, // read/write target address
output [AW-1:0] srcaddr, // read return address
output [2*AW-1:0] data // write data
);
wire [15:0] cmd;
//############################################
// Command Decode
//############################################
enoc_decode enoc_decode (//Input
.cmd_in (cmd[15:0]),
// Outputs
.cmd_write (cmd_write),
.cmd_write_stop (cmd_write_stop),
.cmd_read (cmd_read),
.cmd_cas (cmd_cas),
.cmd_atomic_add (cmd_atomic_add),
.cmd_atomic_and (cmd_atomic_and),
.cmd_atomic_or (cmd_atomic_or),
.cmd_atomic_xor (cmd_atomic_xor),
.cmd_opcode (cmd_opcode[3:0]),
.cmd_user (cmd_user[7:0]),
.cmd_length (cmd_length[3:0]),
.cmd_size (cmd_size[2:0]));
generate
//######################
// 16-Bit ("lite/apb like")
//######################
if(AW==16) begin : aw16
if(PW==40) begin : p40
assign cmd[7:0] = packet_in[7:0];
assign cmd[15:8] = 8'b0;
assign dstaddr[15:0] = packet_in[23:8];
assign srcaddr[15:0] = packet_in[39:24];
assign data[31:0] = {16'b0,packet_in[39:24]};
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw16
//######################
// 32-Bit
//######################
if(AW==32) begin : aw32
if(PW==80) begin: p80
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[31:0] = packet_in[79:48];
assign data[31:0] = packet_in[79:48];
assign data[63:32] = 32'b0;
end
else if(PW==112) begin: p112
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[31:0] = packet_in[79:48];
assign data[63:0] = packet_in[111:48];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw32
//######################
// 64-Bit
//######################
if(AW==64) begin : aw64
if(PW==144) begin: p144
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[127:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = 64'b0;
end
else if(PW==208) begin: p208
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[63:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = packet_in[207:144];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw64
//######################
// 128-Bit
//######################
if(AW==128) begin : aw128
if(PW==272) begin: p272
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[63:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = packet_in[207:144];
assign srcaddr[127:64] = packet_in[207:144];
assign dstaddr[127:64] = packet_in[271:208];
assign data[255:128] = 128'b0;
end
else if(PW==400) begin: p400
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[63:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = packet_in[207:144];
assign srcaddr[127:64] = packet_in[207:144];
assign dstaddr[127:64] = packet_in[271:208];
assign data[255:128] = packet_in[399:272];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw128
endgenerate
endmodule // enoc_unpack
|
`include "defines.v"
`timescale 1ns/1ps
module tb(
input `control_w port0_ci,
input `data_w port0_di,
output `control_w port0_co,
output `data_w port0_do,
input `control_w port1_ci,
input `data_w port1_di,
output `control_w port1_co,
output `data_w port1_do,
input `control_w port2_ci,
input `data_w port2_di,
output `control_w port2_co,
output `data_w port2_do,
input `control_w port3_ci,
input `data_w port3_di,
output `control_w port3_co,
output `data_w port3_do,
input `control_w port4_ci,
input `data_w port4_di,
output `control_w port4_co,
output `data_w port4_do
);
wire injrd, injack;
reg clk, rst;
reg `control_w flit0c;
reg `data_w flit0d;
brouter r(
.clk(clk),
.rst(rst),
.port0_ci(flit0c), .port0_co(port0_co),
.port1_ci(port1_ci), .port1_co(port1_co),
.port2_ci(port2_ci), .port2_co(port2_co),
.port3_ci(port3_ci), .port3_co(port3_co),
.port4_ci(port4_ci), .port4_co(port4_co),
.port0_di(flit0d), .port0_do(port0_do),
.port1_di(port1_di), .port1_do(port1_do),
.port2_di(port2_di), .port2_do(port2_do),
.port3_di(port3_di), .port3_do(port3_do),
.port4_di(port4_di), .port4_do(port4_do),
.port4_ready(injrd)
);
initial begin
clk = 0;
rst = 0;
flit0c = 22'h200001;
flit0d = 128'h0123456789abcdef0123456789abcdef;
#1;
clk = 1;
#1;
clk = 0;
flit0c = 22'h0;
flit0d = 128'h0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
#1;
clk = 1;
#1;
clk = 0;
$display("port0 %04x, port1 %04x, port2 %04x, port3 %04x, port4 %04x\n",
port0_co, port1_co, port2_co, port3_co, port4_co);
$display("port0 %16x, port1 %16x, port2 %16x, port3 %16x, port4 %16x\n",
port0_do, port1_do, port2_do, port3_do, port4_do);
end
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/17.0std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2017/01/22 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 09/01/2016 06:29:42 PM
// Design Name:
// Module Name: KOA_FPGA
// Project Name: Recursive Karatsuba Offman Multiplication
// Target Devices:
// Tool Versions:
// Description: RKOA optimization for DSP
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module KOA_FPGA
//#(parameter SW = 24)
#(parameter SW = 54)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-3)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
if (SW<=18) begin
multiplier_C #(.W(SW)/*,.level(level1)*/) main(
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(sgf_result_o)
);
end else begin
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_FPGA #(.SW(SW/2)/*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_FPGA #(.SW(SW/2)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
KOA_FPGA #(.SW(SW/2+1)/*,.level(level1)*/) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({leftside1,S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_FPGA #(.SW(SW/2)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_FPGA #(.SW((SW/2)+1)/*,.level(level2)*/) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
KOA_FPGA #(.SW(SW/2+2)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({leftside2,S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
endcase
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
`define DEBUG
// Output Left-Justified 24bit 192kHz 2ch (Stereo) Audio Stream
module dac_drv(
input wire clk,
input wire rst,
output wire bck_o,
output wire data_o,
output wire lrck_o,
input wire [1:0] ack_i,
input wire [23:0] data_i,
output wire [1:0] pop_o);
// 256fs * 192kHz = 49.152Mhz
reg [7:0] clk_counter;
always @(posedge clk)
if(rst)
clk_counter <= 0;
else
clk_counter <= clk_counter + 1;
// generate bck = 4x clk = 64fs * 192kHz = 12.28Mhz
wire bck_int_o = clk_counter[1];
reg bck_ff;
always @(posedge clk)
bck_ff <= bck_int_o;
assign bck_o = bck_ff;
// generate lrck = 256x clk = 192kHz
wire lrck_int_o = ~clk_counter[7];
reg lrck_ff;
always @(posedge clk)
lrck_ff <= lrck_int_o;
assign lrck_o = lrck_ff;
// generate data
reg [23:0] data_i_ff [1:0];
always @(posedge clk) begin
if(rst) begin
data_i_ff[0] <= 0;
data_i_ff[1] <= 0;
end else if(ack_i[0])
data_i_ff[0] <= data_i;
else if (ack_i[1])
data_i_ff[1] <= data_i;
end
assign pop_o[1] = (clk_counter == 8'b00000000);
assign pop_o[0] = (clk_counter == 8'b10000000);
reg [31:0] data_o_ff;
wire data_int_o = data_o_ff[31];
reg data_o_buf_ff;
always @(posedge clk)
data_o_buf_ff <= data_int_o;
assign data_o = data_o_buf_ff;
wire chsel = clk_counter[7];
always @(posedge clk) begin
if(clk_counter[6:0] == 7'h7f) begin
`ifdef DEBUG
$display("dac_drv: lr %d send %h", lrck_o, data_i_ff[chsel]);
`endif
data_o_ff <= {data_i_ff[chsel], 8'b0};
end else if(clk_counter[1:0] == 2'b11) begin
data_o_ff <= {data_o_ff[30:0], 1'b0};
end
end
endmodule
|
(** * UseAuto: Theory and Practice of Automation in Coq Proofs *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
(* Chapter maintained by Arthur Chargueraud *)
(** In a machine-checked proof, every single detail has to be
justified. This can result in huge proof scripts. Fortunately,
Coq comes with a proof-search mechanism and with several decision
procedures that enable the system to automatically synthesize
simple pieces of proof. Automation is very powerful when set up
appropriately. The purpose of this chapter is to explain the
basics of working of automation.
The chapter is organized in two parts. The first part focuses on a
general mechanism called "proof search." In short, proof search
consists in naively trying to apply lemmas and assumptions in all
possible ways. The second part describes "decision procedures",
which are tactics that are very good at solving proof obligations
that fall in some particular fragment of the logic of Coq.
Many of the examples used in this chapter consist of small lemmas
that have been made up to illustrate particular aspects of automation.
These examples are completely independent from the rest of the Software
Foundations course. This chapter also contains some bigger examples
which are used to explain how to use automation in realistic proofs.
These examples are taken from other chapters of the course (mostly
from STLC), and the proofs that we present make use of the tactics
from the library [LibTactics.v], which is presented in the chapter
[UseTactics]. *)
Require Import LibTactics.
(* ####################################################### *)
(** * Basic Features of Proof Search *)
(** The idea of proof search is to replace a sequence of tactics
applying lemmas and assumptions with a call to a single tactic,
for example [auto]. This form of proof automation saves a lot of
effort. It typically leads to much shorter proof scripts, and to
scripts that are typically more robust to change. If one makes a
little change to a definition, a proof that exploits automation
probably won't need to be modified at all. Of course, using too
much automation is a bad idea. When a proof script no longer
records the main arguments of a proof, it becomes difficult to fix
it when it gets broken after a change in a definition. Overall, a
reasonable use of automation is generally a big win, as it saves a
lot of time both in building proof scripts and in subsequently
maintaining those proof scripts. *)
(* ####################################################### *)
(** ** Strength of Proof Search *)
(** We are going to study four proof-search tactics: [auto], [eauto],
[iauto] and [jauto]. The tactics [auto] and [eauto] are builtin
in Coq. The tactic [iauto] is a shorthand for the builtin tactic
[try solve [intuition eauto]]. The tactic [jauto] is defined in
the library [LibTactics], and simply performs some preprocessing
of the goal before calling [eauto]. The goal of this chapter is
to explain the general principles of proof search and to give
rule of thumbs for guessing which of the four tactics mentioned
above is best suited for solving a given goal.
Proof search is a compromise between efficiency and
expressiveness, that is, a tradeoff between how complex goals the
tactic can solve and how much time the tactic requires for
terminating. The tactic [auto] builds proofs only by using the
basic tactics [reflexivity], [assumption], and [apply]. The tactic
[eauto] can also exploit [eapply]. The tactic [jauto] extends
[eauto] by being able to open conjunctions and existentials that
occur in the context. The tactic [iauto] is able to deal with
conjunctions, disjunctions, and negation in a quite clever way;
however it is not able to open existentials from the context.
Also, [iauto] usually becomes very slow when the goal involves
several disjunctions.
Note that proof search tactics never perform any rewriting
step (tactics [rewrite], [subst]), nor any case analysis on an
arbitrary data structure or predicate (tactics [destruct] and
[inversion]), nor any proof by induction (tactic [induction]). So,
proof search is really intended to automate the final steps from
the various branches of a proof. It is not able to discover the
overall structure of a proof. *)
(* ####################################################### *)
(** ** Basics *)
(** The tactic [auto] is able to solve a goal that can be proved
using a sequence of [intros], [apply], [assumption], and [reflexivity].
Two examples follow. The first one shows the ability for
[auto] to call [reflexivity] at any time. In fact, calling
[reflexivity] is always the first thing that [auto] tries to do. *)
Lemma solving_by_reflexivity :
2 + 3 = 5.
Proof. auto. Qed.
(** The second example illustrates a proof where a sequence of
two calls to [apply] are needed. The goal is to prove that
if [Q n] implies [P n] for any [n] and if [Q n] holds for any [n],
then [P 2] holds. *)
Lemma solving_by_apply : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. auto. Qed.
(** We can ask [auto] to tell us what proof it came up with,
by invoking [info_auto] in place of [auto]. *)
Lemma solving_by_apply' : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. info_auto. Qed.
(* The output is: [intro P; intro Q; intro H;] *)
(* followed with [intro H0; simple apply H; simple apply H0]. *)
(* i.e., the sequence [intros P Q H H0; apply H; apply H0]. *)
(** The tactic [auto] can invoke [apply] but not [eapply]. So, [auto]
cannot exploit lemmas whose instantiation cannot be directly
deduced from the proof goal. To exploit such lemmas, one needs to
invoke the tactic [eauto], which is able to call [eapply].
In the following example, the first hypothesis asserts that [P n]
is true when [Q m] is true for some [m], and the goal is to prove
that [Q 1] implies [P 2]. This implication follows direction from
the hypothesis by instantiating [m] as the value [1]. The
following proof script shows that [eauto] successfully solves the
goal, whereas [auto] is not able to do so. *)
Lemma solving_by_eapply : forall (P Q : nat->Prop),
(forall n m, Q m -> P n) ->
Q 1 -> P 2.
Proof. auto. eauto. Qed.
(** Remark: Again, we can use [info_eauto] to see what proof [eauto]
comes up with. *)
(* ####################################################### *)
(** ** Conjunctions *)
(** So far, we've seen that [eauto] is stronger than [auto] in the
sense that it can deal with [eapply]. In the same way, we are going
to see how [jauto] and [iauto] are stronger than [auto] and [eauto]
in the sense that they provide better support for conjunctions. *)
(** The tactics [auto] and [eauto] can prove a goal of the form
[F /\ F'], where [F] and [F'] are two propositions, as soon as
both [F] and [F'] can be proved in the current context.
An example follows. *)
Lemma solving_conj_goal : forall (P : nat->Prop) (F : Prop),
(forall n, P n) -> F -> F /\ P 2.
Proof. auto. Qed.
(** However, when an assumption is a conjunction, [auto] and [eauto]
are not able to exploit this conjunction. It can be quite
surprising at first that [eauto] can prove very complex goals but
that it fails to prove that [F /\ F'] implies [F]. The tactics
[iauto] and [jauto] are able to decompose conjunctions from the context.
Here is an example. *)
Lemma solving_conj_hyp : forall (F F' : Prop),
F /\ F' -> F.
Proof. auto. eauto. jauto. (* or [iauto] *) Qed.
(** The tactic [jauto] is implemented by first calling a
pre-processing tactic called [jauto_set], and then calling
[eauto]. So, to understand how [jauto] works, one can directly
call the tactic [jauto_set]. *)
Lemma solving_conj_hyp' : forall (F F' : Prop),
F /\ F' -> F.
Proof. intros. jauto_set. eauto. Qed.
(** Next is a more involved goal that can be solved by [iauto] and
[jauto]. *)
Lemma solving_conj_more : forall (P Q R : nat->Prop) (F : Prop),
(F /\ (forall n m, (Q m /\ R n) -> P n)) ->
(F -> R 2) ->
Q 1 ->
P 2 /\ F.
Proof. jauto. (* or [iauto] *) Qed.
(** The strategy of [iauto] and [jauto] is to run a global analysis of
the top-level conjunctions, and then call [eauto]. For this
reason, those tactics are not good at dealing with conjunctions
that occur as the conclusion of some universally quantified
hypothesis. The following example illustrates a general weakness
of Coq proof search mechanisms. *)
Lemma solving_conj_hyp_forall : forall (P Q : nat->Prop),
(forall n, P n /\ Q n) -> P 2.
Proof.
auto. eauto. iauto. jauto.
(* Nothing works, so we have to do some of the work by hand *)
intros. destruct (H 2). auto.
Qed.
(** This situation is slightly disappointing, since automation is
able to prove the following goal, which is very similar. The
only difference is that the universal quantification has been
distributed over the conjunction. *)
Lemma solved_by_jauto : forall (P Q : nat->Prop) (F : Prop),
(forall n, P n) /\ (forall n, Q n) -> P 2.
Proof. jauto. (* or [iauto] *) Qed.
(* ####################################################### *)
(** ** Disjunctions *)
(** The tactics [auto] and [eauto] can handle disjunctions that
occur in the goal. *)
Lemma solving_disj_goal : forall (F F' : Prop),
F -> F \/ F'.
Proof. auto. Qed.
(** However, only [iauto] is able to automate reasoning on the
disjunctions that appear in the context. For example, [iauto] can
prove that [F \/ F'] entails [F' \/ F]. *)
Lemma solving_disj_hyp : forall (F F' : Prop),
F \/ F' -> F' \/ F.
Proof. auto. eauto. jauto. iauto. Qed.
(** More generally, [iauto] can deal with complex combinations of
conjunctions, disjunctions, and negations. Here is an example. *)
Lemma solving_tauto : forall (F1 F2 F3 : Prop),
((~F1 /\ F3) \/ (F2 /\ ~F3)) ->
(F2 -> F1) ->
(F2 -> F3) ->
~F2.
Proof. iauto. Qed.
(** However, the ability of [iauto] to automatically perform a case
analysis on disjunctions comes with a downside: [iauto] may be
very slow. If the context involves several hypotheses with
disjunctions, [iauto] typically generates an exponential number of
subgoals on which [eauto] is called. One major advantage of [jauto]
compared with [iauto] is that it never spends time performing this
kind of case analyses. *)
(* ####################################################### *)
(** ** Existentials *)
(** The tactics [eauto], [iauto], and [jauto] can prove goals whose
conclusion is an existential. For example, if the goal is [exists
x, f x], the tactic [eauto] introduces an existential variable,
say [?25], in place of [x]. The remaining goal is [f ?25], and
[eauto] tries to solve this goal, allowing itself to instantiate
[?25] with any appropriate value. For example, if an assumption [f
2] is available, then the variable [?25] gets instantiated with
[2] and the goal is solved, as shown below. *)
Lemma solving_exists_goal : forall (f : nat->Prop),
f 2 -> exists x, f x.
Proof.
auto. (* observe that [auto] does not deal with existentials, *)
eauto. (* whereas [eauto], [iauto] and [jauto] solve the goal *)
Qed.
(** A major strength of [jauto] over the other proof search tactics is
that it is able to exploit the existentially-quantified
hypotheses, i.e., those of the form [exists x, P]. *)
Lemma solving_exists_hyp : forall (f g : nat->Prop),
(forall x, f x -> g x) ->
(exists a, f a) ->
(exists a, g a).
Proof.
auto. eauto. iauto. (* All of these tactics fail, *)
jauto. (* whereas [jauto] succeeds. *)
(* For the details, run [intros. jauto_set. eauto] *)
Qed.
(* ####################################################### *)
(** ** Negation *)
(** The tactics [auto] and [eauto] suffer from some limitations with
respect to the manipulation of negations, mostly related to the
fact that negation, written [~ P], is defined as [P -> False] but
that the unfolding of this definition is not performed
automatically. Consider the following example. *)
Lemma negation_study_1 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof.
intros P H0 HX.
eauto. (* It fails to see that [HX] applies *)
unfold not in *. eauto.
Qed.
(** For this reason, the tactics [iauto] and [jauto] systematically
invoke [unfold not in *] as part of their pre-processing. So,
they are able to solve the previous goal right away. *)
Lemma negation_study_2 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof. jauto. (* or [iauto] *) Qed.
(** We will come back later on to the behavior of proof search with
respect to the unfolding of definitions. *)
(* ####################################################### *)
(** ** Equalities *)
(** Coq's proof-search feature is not good at exploiting equalities.
It can do very basic operations, like exploiting reflexivity
and symmetry, but that's about it. Here is a simple example
that [auto] can solve, by first calling [symmetry] and then
applying the hypothesis. *)
Lemma equality_by_auto : forall (f g : nat->Prop),
(forall x, f x = g x) -> g 2 = f 2.
Proof. auto. Qed.
(** To automate more advanced reasoning on equalities, one should
rather try to use the tactic [congruence], which is presented at
the end of this chapter in the "Decision Procedures" section. *)
(* ####################################################### *)
(** * How Proof Search Works *)
(* ####################################################### *)
(** ** Search Depth *)
(** The tactic [auto] works as follows. It first tries to call
[reflexivity] and [assumption]. If one of these calls solves the
goal, the job is done. Otherwise [auto] tries to apply the most
recently introduced assumption that can be applied to the goal
without producing and error. This application produces
subgoals. There are two possible cases. If the sugboals produced
can be solved by a recursive call to [auto], then the job is done.
Otherwise, if this application produces at least one subgoal that
[auto] cannot solve, then [auto] starts over by trying to apply
the second most recently introduced assumption. It continues in a
similar fashion until it finds a proof or until no assumption
remains to be tried.
It is very important to have a clear idea of the backtracking
process involved in the execution of the [auto] tactic; otherwise
its behavior can be quite puzzling. For example, [auto] is not
able to solve the following triviality. *)
Lemma search_depth_0 :
True /\ True /\ True /\ True /\ True /\ True.
Proof.
auto.
Abort.
(** The reason [auto] fails to solve the goal is because there are
too many conjunctions. If there had been only five of them, [auto]
would have successfully solved the proof, but six is too many.
The tactic [auto] limits the number of lemmas and hypotheses
that can be applied in a proof, so as to ensure that the proof
search eventually terminates. By default, the maximal number
of steps is five. One can specify a different bound, writing
for example [auto 6] to search for a proof involving at most
six steps. For example, [auto 6] would solve the previous lemma.
(Similarly, one can invoke [eauto 6] or [intuition eauto 6].)
The argument [n] of [auto n] is called the "search depth."
The tactic [auto] is simply defined as a shorthand for [auto 5].
The behavior of [auto n] can be summarized as follows. It first
tries to solve the goal using [reflexivity] and [assumption]. If
this fails, it tries to apply a hypothesis (or a lemma that has
been registered in the hint database), and this application
produces a number of sugoals. The tactic [auto (n-1)] is then
called on each of those subgoals. If all the subgoals are solved,
the job is completed, otherwise [auto n] tries to apply a
different hypothesis.
During the process, [auto n] calls [auto (n-1)], which in turn
might call [auto (n-2)], and so on. The tactic [auto 0] only
tries [reflexivity] and [assumption], and does not try to apply
any lemma. Overall, this means that when the maximal number of
steps allowed has been exceeded, the [auto] tactic stops searching
and backtracks to try and investigate other paths. *)
(** The following lemma admits a unique proof that involves exactly
three steps. So, [auto n] proves this goal iff [n] is greater than
three. *)
Lemma search_depth_1 : forall (P : nat->Prop),
P 0 ->
(P 0 -> P 1) ->
(P 1 -> P 2) ->
(P 2).
Proof.
auto 0. (* does not find the proof *)
auto 1. (* does not find the proof *)
auto 2. (* does not find the proof *)
auto 3. (* finds the proof *)
(* more generally, [auto n] solves the goal if [n >= 3] *)
Qed.
(** We can generalize the example by introducing an assumption
asserting that [P k] is derivable from [P (k-1)] for all [k],
and keep the assumption [P 0]. The tactic [auto], which is the
same as [auto 5], is able to derive [P k] for all values of [k]
less than 5. For example, it can prove [P 4]. *)
Lemma search_depth_3 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4).
Proof. auto. Qed.
(** However, to prove [P 5], one needs to call at least [auto 6]. *)
Lemma search_depth_4 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 5).
Proof. auto. auto 6. Qed.
(** Because [auto] looks for proofs at a limited depth, there are
cases where [auto] can prove a goal [F] and can prove a goal
[F'] but cannot prove [F /\ F']. In the following example,
[auto] can prove [P 4] but it is not able to prove [P 4 /\ P 4],
because the splitting of the conjunction consumes one proof step.
To prove the conjunction, one needs to increase the search depth,
using at least [auto 6]. *)
Lemma search_depth_5 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4 /\ P 4).
Proof. auto. auto 6. Qed.
(* ####################################################### *)
(** ** Backtracking *)
(** In the previous section, we have considered proofs where
at each step there was a unique assumption that [auto]
could apply. In general, [auto] can have several choices
at every step. The strategy of [auto] consists of trying all
of the possibilities (using a depth-first search exploration).
To illustrate how automation works, we are going to extend the
previous example with an additional assumption asserting that
[P k] is also derivable from [P (k+1)]. Adding this hypothesis
offers a new possibility that [auto] could consider at every step.
There exists a special command that one can use for tracing
all the steps that proof-search considers. To view such a
trace, one should write [debug eauto]. (For some reason, the
command [debug auto] does not exist, so we have to use the
command [debug eauto] instead.) *)
Lemma working_of_auto_1 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 2).
(* Uncomment "debug" in the following line to see the debug trace: *)
Proof. intros P H1 H2 H3. (* debug *) eauto. Qed.
(** The output message produced by [debug eauto] is as follows.
<<
depth=5
depth=4 apply H3
depth=3 apply H3
depth=3 exact H1
>>
The depth indicates the value of [n] with which [eauto n] is
called. The tactics shown in the message indicate that the first
thing that [eauto] has tried to do is to apply [H3]. The effect of
applying [H3] is to replace the goal [P 2] with the goal [P 1].
Then, again, [H3] has been applied, changing the goal [P 1] into
[P 0]. At that point, the goal was exactly the hypothesis [H1].
It seems that [eauto] was quite lucky there, as it never even
tried to use the hypothesis [H2] at any time. The reason is that
[auto] always tries to use the most recently introduced hypothesis
first, and [H3] is a more recent hypothesis than [H2] in the goal.
So, let's permute the hypotheses [H2] and [H3] and see what
happens. *)
Lemma working_of_auto_2 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Goal: *) (P 2).
Proof. intros P H1 H3 H2. (* debug *) eauto. Qed.
(** This time, the output message suggests that the proof search
investigates many possibilities. Replacing [debug eauto] with
[info_eauto], we observe that the proof that [eauto] comes up
with is actually not the simplest one.
[apply H2; apply H3; apply H3; apply H3; exact H1]
This proof goes through the proof obligation [P 3], even though
it is not any useful. The following tree drawing describes
all the goals that automation has been through.
<<
|5||4||3||2||1||0| -- below, tabulation indicates the depth
[P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 6]
-> [P 7]
-> [P 5]
-> [P 4]
-> [P 5]
-> [P 3]
--> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 0]
-> !! Done !!
>>
The first few lines read as follows. To prove [P 2], [eauto 5]
has first tried to apply [H2], producing the subgoal [P 3].
To solve it, [eauto 4] has tried again to apply [H2], producing
the goal [P 4]. Similarly, the search goes through [P 5], [P 6]
and [P 7]. When reaching [P 7], the tactic [eauto 0] is called
but as it is not allowed to try and apply any lemma, it fails.
So, we come back to the goal [P 6], and try this time to apply
hypothesis [H3], producing the subgoal [P 5]. Here again,
[eauto 0] fails to solve this goal.
The process goes on and on, until backtracking to [P 3] and trying
to apply [H2] three times in a row, going through [P 2] and [P 1]
and [P 0]. This search tree explains why [eauto] came up with a
proof starting with [apply H2]. *)
(* ####################################################### *)
(** ** Adding Hints *)
(** By default, [auto] (and [eauto]) only tries to apply the
hypotheses that appear in the proof context. There are two
possibilities for telling [auto] to exploit a lemma that have
been proved previously: either adding the lemma as an assumption
just before calling [auto], or adding the lemma as a hint, so
that it can be used by every calls to [auto].
The first possibility is useful to have [auto] exploit a lemma
that only serves at this particular point. To add the lemma as
hypothesis, one can type [generalize mylemma; intros], or simply
[lets: mylemma] (the latter requires [LibTactics.v]).
The second possibility is useful for lemmas that need to be
exploited several times. The syntax for adding a lemma as a hint
is [Hint Resolve mylemma]. For example, the lemma asserting than
any number is less than or equal to itself, [forall x, x <= x],
called [Le.le_refl] in the Coq standard library, can be added as a
hint as follows. *)
Hint Resolve Le.le_refl.
(** A convenient shorthand for adding all the constructors of an
inductive datatype as hints is the command [Hint Constructors
mydatatype].
Warning: some lemmas, such as transitivity results, should
not be added as hints as they would very badly affect the
performance of proof search. The description of this problem
and the presentation of a general work-around for transitivity
lemmas appear further on. *)
(* ####################################################### *)
(** ** Integration of Automation in Tactics *)
(** The library "LibTactics" introduces a convenient feature for
invoking automation after calling a tactic. In short, it suffices
to add the symbol star ([*]) to the name of a tactic. For example,
[apply* H] is equivalent to [apply H; auto_star], where [auto_star]
is a tactic that can be defined as needed. By default, [auto_star]
first tries to solve the goal using [auto], and if this does not
succeed then it tries to call [jauto]. Even though [jauto] is
strictly stronger than [auto], it makes sense to call [auto] first:
when [auto] succeeds it may save a lot of time, and when [auto]
fails to prove the goal, it fails very quickly.
The definition of [auto_star], which determines the meaning of the
star symbol, can be modified whenever needed. Simply write:
Ltac auto_star ::= a_new_definition.
]]
Observe the use of [::=] instead of [:=], which indicates that the
tactic is being rebound to a new definition. So, the default
definition is as follows. *)
Ltac auto_star ::= try solve [ auto | jauto ].
(** Nearly all standard Coq tactics and all the tactics from
"LibTactics" can be called with a star symbol. For example, one
can invoke [subst*], [destruct* H], [inverts* H], [lets* I: H x],
[specializes* H x], and so on... There are two notable exceptions.
The tactic [auto*] is just another name for the tactic
[auto_star]. And the tactic [apply* H] calls [eapply H] (or the
more powerful [applys H] if needed), and then calls [auto_star].
Note that there is no [eapply* H] tactic, use [apply* H]
instead. *)
(** In large developments, it can be convenient to use two degrees of
automation. Typically, one would use a fast tactic, like [auto],
and a slower but more powerful tactic, like [jauto]. To allow for
a smooth coexistence of the two form of automation, [LibTactics.v]
also defines a "tilde" version of tactics, like [apply~ H],
[destruct~ H], [subst~], [auto~] and so on. The meaning of the
tilde symbol is described by the [auto_tilde] tactic, whose
default implementation is [auto]. *)
Ltac auto_tilde ::= auto.
(** In the examples that follow, only [auto_star] is needed. *)
(* ####################################################### *)
(** * Examples of Use of Automation *)
(** Let's see how to use proof search in practice on the main theorems
of the "Software Foundations" course, proving in particular
results such as determinism, preservation and progress. *)
(* ####################################################### *)
(** ** Determinism *)
Module DeterministicImp.
Require Import Imp.
(** Recall the original proof of the determinism lemma for the IMP
language, shown below. *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
(ceval_cases (induction E1) Case); intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to true".
reflexivity.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to false".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Qed.
(** Exercise: rewrite this proof using [auto] whenever possible.
(The solution uses [auto] 9 times.) *)
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** In fact, using automation is not just a matter of calling [auto]
in place of one or two other tactics. Using automation is about
rethinking the organization of sequences of tactics so as to
minimize the effort involved in writing and maintaining the proof.
This process is eased by the use of the tactics from
[LibTactics.v]. So, before trying to optimize the way automation
is used, let's first rewrite the proof of determinism:
- use [introv H] instead of [intros x H],
- use [gen x] instead of [generalize dependent x],
- use [inverts H] instead of [inversion H; subst],
- use [tryfalse] to handle contradictions, and get rid of
the cases where [beval st b1 = true] and [beval st b1 = false]
both appear in the context,
- stop using [ceval_cases] to label subcases. *)
Theorem ceval_deterministic'': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
auto.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
Qed.
(** To obtain a nice clean proof script, we have to remove the calls
[assert (st' = st'0)]. Such a tactic invokation is not nice
because it refers to some variables whose name has been
automatically generated. This kind of tactics tend to be very
brittle. The tactic [assert (st' = st'0)] is used to assert the
conclusion that we want to derive from the induction
hypothesis. So, rather than stating this conclusion explicitly, we
are going to ask Coq to instantiate the induction hypothesis,
using automation to figure out how to instantiate it. The tactic
[forwards], described in [LibTactics.v] precisely helps with
instantiating a fact. So, let's see how it works out on our
example. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* Let's replay the proof up to the [assert] tactic. *)
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto. auto.
(* We duplicate the goal for comparing different proofs. *)
dup 4.
(* The old proof: *)
assert (st' = st'0). apply IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, without automation: *)
forwards: IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with automation: *)
forwards: IHE1_1. eauto.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with integrated automation: *)
forwards*: IHE1_1.
(* produces [H: st' = st'0]. *) skip.
Abort.
(** To polish the proof script, it remains to factorize the calls
to [auto], using the star symbol. The proof of determinism can then
be rewritten in only four lines, including no more than 10 tactics. *)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts* E2; tryfalse.
forwards*: IHE1_1. subst*.
forwards*: IHE1_1. subst*.
Qed.
End DeterministicImp.
(* ####################################################### *)
(** ** Preservation for STLC *)
Module PreservationProgressStlc.
Require Import StlcProp.
Import STLC.
Import STLCProp.
(** Consider the proof of perservation of STLC, shown below.
This proof already uses [eauto] through the triple-dot
mechanism. *)
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
(has_type_cases (induction HT) Case); intros t' HE; subst Gamma.
Case "T_Var".
inversion HE.
Case "T_Abs".
inversion HE.
Case "T_App".
inversion HE; subst...
(* (step_cases (inversion HE) SCase); subst...*)
(* The ST_App1 and ST_App2 cases are immediate by induction, and
auto takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Case "T_True".
inversion HE.
Case "T_False".
inversion HE.
Case "T_If".
inversion HE; subst...
Qed.
(** Exercise: rewrite this proof using tactics from [LibTactics]
and calling automation using the star symbol rather than the
triple-dot notation. More precisely, make use of the tactics
[inverts*] and [applys*] to call [auto*] after a call to
[inverts] or to [applys]. The solution is three lines long.*)
Theorem preservation' : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof.
(* FILL IN HERE *) admit.
Qed.
(* ####################################################### *)
(** ** Progress for STLC *)
(** Consider the proof of the progress theorem. *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
(has_type_cases (induction Ht) Case); subst Gamma...
Case "T_Var".
inversion H.
Case "T_App".
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is a value".
inversion H; subst; try solve by inversion.
exists ([x0:=t2]t)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_If".
right. destruct IHHt1...
destruct t1; try solve by inversion...
inversion H. exists (tif x0 t2 t3)...
Qed.
(** Exercise: optimize the above proof.
Hint: make use of [destruct*] and [inverts*].
The solution consists of 10 short lines. *)
Theorem progress' : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof.
(* FILL IN HERE *) admit.
Qed.
End PreservationProgressStlc.
(* ####################################################### *)
(** ** BigStep and SmallStep *)
Module Semantics.
Require Import Smallstep.
(** Consider the proof relating a small-step reduction judgment
to a big-step reduction judgment. *)
Theorem multistep__eval : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
intros t v Hnorm.
unfold normal_form_of in Hnorm.
inversion Hnorm as [Hs Hnf]; clear Hnorm.
rewrite nf_same_as_value in Hnf. inversion Hnf. clear Hnf.
exists n. split. reflexivity.
multi_cases (induction Hs) Case; subst.
Case "multi_refl".
apply E_Const.
Case "multi_step".
eapply step__eval. eassumption. apply IHHs. reflexivity.
Qed.
(** Our goal is to optimize the above proof. It is generally
easier to isolate inductions into separate lemmas. So,
we are going to first prove an intermediate result
that consists of the judgment over which the induction
is being performed. *)
(** Exercise: prove the following result, using tactics
[introv], [induction] and [subst], and [apply*].
The solution is 3 lines long. *)
Theorem multistep_eval_ind : forall t v,
t ==>* v -> forall n, C n = v -> t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** Exercise: using the lemma above, simplify the proof of
the result [multistep__eval]. You should use the tactics
[introv], [inverts], [split*] and [apply*].
The solution is 2 lines long. *)
Theorem multistep__eval' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** If we try to combine the two proofs into a single one,
we will likely fail, because of a limitation of the
[induction] tactic. Indeed, this tactic looses
information when applied to a predicate whose arguments
are not reduced to variables, such as [t ==>* (C n)].
You will thus need to use the more powerful tactic called
[dependent induction]. This tactic is available only after
importing the [Program] library, as shown below. *)
Require Import Program.
(** Exercise: prove the lemma [multistep__eval] without invoking
the lemma [multistep_eval_ind], that is, by inlining the proof
by induction involved in [multistep_eval_ind], using the
tactic [dependent induction] instead of [induction].
The solution is 5 lines long. *)
Theorem multistep__eval'' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
End Semantics.
(* ####################################################### *)
(** ** Preservation for STLCRef *)
Module PreservationProgressReferences.
Require Import References.
Import STLCRef.
Hint Resolve store_weakening extends_refl.
(** The proof of preservation for [STLCRef] can be found in chapter
[References]. It contains 58 lines (not counting the labelling of
cases). The optimized proof script is more than twice shorter. The
following material explains how to build the optimized proof
script. The resulting optimized proof script for the preservation
theorem appears afterwards. *)
Theorem preservation : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
(* old: [Proof. with eauto using store_weakening, extends_refl.]
new: [Proof.], and the two lemmas are registered as hints
before the proof of the lemma, possibly inside a section in
order to restrict the scope of the hints. *)
remember (@empty ty) as Gamma. introv Ht. gen t'.
(has_type_cases (induction Ht) Case); introv HST Hstep;
(* old: [subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl)]
new: [subst Gamma; inverts Hstep; eauto.]
We want to be more precise on what exactly we substitute,
and we do not want to call [try (solve by inversion)] which
is way to slow. *)
subst Gamma; inverts Hstep; eauto.
Case "T_App".
SCase "ST_AppAbs".
(* old:
exists ST. inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing... *)
(* new: we use [inverts] in place of [inversion] and [splits] to
split the conjunction, and [applys*] in place of [eapply...] *)
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
SCase "ST_App1".
(* old:
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: The tactic [eapply IHHt1 in H0...] applies [IHHt1] to [H0].
But [H0] is only thing that [IHHt1] could be applied to, so
there [eauto] can figure this out on its own. The tactic
[forwards] is used to instantiate all the arguments of [IHHt1],
producing existential variables and subgoals when needed. *)
forwards: IHHt1. eauto. eauto. eauto.
(* At this point, we need to decompose the hypothesis [H] that has
just been created by [forwards]. This is done by the first part
of the preprocessing phase of [jauto]. *)
jauto_set_hyps; intros.
(* It remains to decompose the goal, which is done by the second
part of the preprocessing phase of [jauto]. *)
jauto_set_goal; intros.
(* All the subgoals produced can then be solved by [eauto]. *)
eauto. eauto. eauto.
SCase "ST_App2".
(* old:
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: this time, we need to call [forwards] on [IHHt2],
and we call [jauto] right away, by writing [forwards*],
proving the goal in a single tactic! *)
forwards*: IHHt2.
(* The same trick works for many of the other subgoals. *)
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
Case "T_Ref".
SCase "ST_RefValue".
(* old:
exists (snoc ST T1).
inversion HST; subst.
split.
apply extends_snoc.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (snoc ST T1))).
apply T_Loc.
rewrite <- H. rewrite length_snoc. omega.
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_snoc...
apply store_well_typed_snoc; assumption. *)
(* new: in this proof case, we need to perform an inversion
without removing the hypothesis. The tactic [inverts keep]
serves exactly this purpose. *)
exists (snoc ST T1). inverts keep HST. splits.
(* The proof of the first subgoal needs not be changed *)
apply extends_snoc.
(* For the second subgoal, we use the tactic [applys_eq] to avoid
a manual [replace] before [T_loc] can be applied. *)
applys_eq T_Loc 1.
(* To justify the inequality, there is no need to call [rewrite <- H],
because the tactic [omega] is able to exploit [H] on its own.
So, only the rewriting of [lenght_snoc] and the call to the
tactic [omega] remain. *)
rewrite length_snoc. omega.
(* The next proof case is hard to polish because it relies on the
lemma [nth_eq_snoc] whose statement is not automation-friendly.
We'll come back to this proof case further on. *)
unfold store_Tlookup. rewrite <- H. rewrite* nth_eq_snoc.
(* Last, we replace [apply ..; assumption] with [apply* ..] *)
apply* store_well_typed_snoc.
forwards*: IHHt.
Case "T_Deref".
SCase "ST_DerefLoc".
(* old:
exists ST. split; try split...
destruct HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst... *)
(* new: we start by calling [exists ST] and [splits*]. *)
exists ST. splits*.
(* new: we replace [destruct HST as [_ Hsty]] by the following *)
lets [_ Hsty]: HST.
(* new: then we use the tactic [applys_eq] to avoid the need to
perform a manual [replace] before applying [Hsty]. *)
applys_eq* Hsty 1.
(* new: we then can call [inverts] in place of [inversion;subst] *)
inverts* Ht.
forwards*: IHHt.
Case "T_Assign".
SCase "ST_Assign".
(* old:
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst... *)
(* new: simply using nicer tactics *)
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(** Let's come back to the proof case that was hard to optimize.
The difficulty comes from the statement of [nth_eq_snoc], which
takes the form [nth (length l) (snoc l x) d = x]. This lemma is
hard to exploit because its first argument, [length l], mentions
a list [l] that has to be exactly the same as the [l] occuring in
[snoc l x]. In practice, the first argument is often a natural
number [n] that is provably equal to [length l] yet that is not
syntactically equal to [length l]. There is a simple fix for
making [nth_eq_snoc] easy to apply: introduce the intermediate
variable [n] explicitly, so that the goal becomes
[nth n (snoc l x) d = x], with a premise asserting [n = length l]. *)
Lemma nth_eq_snoc' : forall (A : Type) (l : list A) (x d : A) (n : nat),
n = length l -> nth n (snoc l x) d = x.
Proof. intros. subst. apply nth_eq_snoc. Qed.
(** The proof case for [ref] from the preservation theorem then
becomes much easier to prove, because [rewrite nth_eq_snoc']
now succeeds. *)
Lemma preservation_ref : forall (st:store) (ST : store_ty) T1,
length ST = length st ->
TRef T1 = TRef (store_Tlookup (length st) (snoc ST T1)).
Proof.
intros. dup.
(* A first proof, with an explicit [unfold] *)
unfold store_Tlookup. rewrite* nth_eq_snoc'.
(* A second proof, with a call to [fequal] *)
fequal. symmetry. apply* nth_eq_snoc'.
Qed.
(** The optimized proof of preservation is summarized next. *)
Theorem preservation' : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
remember (@empty ty) as Gamma. introv Ht. gen t'.
induction Ht; introv HST Hstep; subst Gamma; inverts Hstep; eauto.
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
exists (snoc ST T1). inverts keep HST. splits.
apply extends_snoc.
applys_eq T_Loc 1.
rewrite length_snoc. omega.
unfold store_Tlookup. rewrite* nth_eq_snoc'.
apply* store_well_typed_snoc.
forwards*: IHHt.
exists ST. splits*. lets [_ Hsty]: HST.
applys_eq* Hsty 1. inverts* Ht.
forwards*: IHHt.
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(* ####################################################### *)
(** ** Progress for STLCRef *)
(** The proof of progress for [STLCRef] can be found in chapter
[References]. It contains 53 lines and the optimized proof script
is, here again, half the length. *)
Theorem progress : forall ST t T st,
has_type empty ST t T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof.
introv Ht HST. remember (@empty ty) as Gamma.
induction Ht; subst Gamma; tryfalse; try solve [left*].
right. destruct* IHHt1 as [K|].
inverts K; inverts Ht1.
destruct* IHHt2.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1].
destruct* IHHt2 as [M|].
inverts M; try solve [inverts Ht2]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1]. destruct* n.
right. destruct* IHHt.
right. destruct* IHHt as [K|].
inverts K; inverts Ht as M.
inverts HST as N. rewrite* N in M.
right. destruct* IHHt1 as [K|].
destruct* IHHt2.
inverts K; inverts Ht1 as M.
inverts HST as N. rewrite* N in M.
Qed.
End PreservationProgressReferences.
(* ####################################################### *)
(** ** Subtyping *)
Module SubtypingInversion.
Require Import Sub.
(** Consider the inversion lemma for typing judgment
of abstractions in a type system with subtyping. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst...
Qed.
(** Exercise: optimize the proof script, using
[introv], [lets] and [inverts*]. In particular,
you will find it useful to replace the pattern
[apply K in H. destruct H as I] with [lets I: K H].
The solution is 4 lines. *)
Lemma abs_arrow' : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** The lemma [substitution_preserves_typing] has already been used to
illustrate the working of [lets] and [applys] in chapter
[UseTactics]. Optimize further this proof using automation (with
the star symbol), and using the tactic [cases_if']. The solution
is 33 lines, including the [Case] instructions (21 lines without
them). *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof.
(* FILL IN HERE *) admit.
Qed.
End SubtypingInversion.
(* ####################################################### *)
(** * Advanced Topics in Proof Search *)
(* ####################################################### *)
(** ** Stating Lemmas in the Right Way *)
(** Due to its depth-first strategy, [eauto] can get exponentially
slower as the depth search increases, even when a short proof
exists. In general, to make proof search run reasonably fast, one
should avoid using a depth search greater than 5 or 6. Moreover,
one should try to minimize the number of applicable lemmas, and
usually put first the hypotheses whose proof usefully instantiates
the existential variables.
In fact, the ability for [eauto] to solve certain goals actually
depends on the order in which the hypotheses are stated. This point
is illustrated through the following example, in which [P] is
a predicate on natural numbers. This predicate is such that
[P n] holds for any [n] as soon as [P m] holds for at least one [m]
different from zero. The goal is to prove that [P 2] implies [P 1].
When the hypothesis about [P] is stated in the form
[forall n m, P m -> m <> 0 -> P n], then [eauto] works. However, with
[forall n m, m <> 0 -> P m -> P n], the tactic [eauto] fails. *)
Lemma order_matters_1 : forall (P : nat->Prop),
(forall n m, P m -> m <> 0 -> P n) -> P 2 -> P 1.
Proof.
eauto. (* Success *)
(* The proof: [intros P H K. eapply H. apply K. auto.] *)
Qed.
Lemma order_matters_2 : forall (P : nat->Prop),
(forall n m, m <> 0 -> P m -> P n) -> P 5 -> P 1.
Proof.
eauto. (* Failure *)
(* To understand why, let us replay the previous proof *)
intros P H K.
eapply H.
(* The application of [eapply] has left two subgoals,
[?X <> 0] and [P ?X], where [?X] is an existential variable. *)
(* Solving the first subgoal is easy for [eauto]: it suffices
to instantiate [?X] as the value [1], which is the simplest
value that satisfies [?X <> 0]. *)
eauto.
(* But then the second goal becomes [P 1], which is where we
started from. So, [eauto] gets stuck at this point. *)
Abort.
(** It is very important to understand that the hypothesis [forall n
m, P m -> m <> 0 -> P n] is eauto-friendly, whereas [forall n m, m
<> 0 -> P m -> P n] really isn't. Guessing a value of [m] for
which [P m] holds and then checking that [m <> 0] holds works well
because there are few values of [m] for which [P m] holds. So, it
is likely that [eauto] comes up with the right one. On the other
hand, guessing a value of [m] for which [m <> 0] and then checking
that [P m] holds does not work well, because there are many values
of [m] that satisfy [m <> 0] but not [P m]. *)
(* ####################################################### *)
(** ** Unfolding of Definitions During Proof-Search *)
(** The use of intermediate definitions is generally encouraged in a
formal development as it usually leads to more concise and more
readable statements. Yet, definitions can make it a little harder
to automate proofs. The problem is that it is not obvious for a
proof search mechanism to know when definitions need to be
unfolded. Note that a naive strategy that consists in unfolding
all definitions before calling proof search does not scale up to
large proofs, so we avoid it. This section introduces a few
techniques for avoiding to manually unfold definitions before
calling proof search. *)
(** To illustrate the treatment of definitions, let [P] be an abstract
predicate on natural numbers, and let [myFact] be a definition
denoting the proposition [P x] holds for any [x] less than or
equal to 3. *)
Axiom P : nat -> Prop.
Definition myFact := forall x, x <= 3 -> P x.
(** Proving that [myFact] under the assumption that [P x] holds for
any [x] should be trivial. Yet, [auto] fails to prove it unless we
unfold the definition of [myFact] explicitly. *)
Lemma demo_hint_unfold_goal_1 :
(forall x, P x) -> myFact.
Proof.
auto. (* Proof search doesn't know what to do, *)
unfold myFact. auto. (* unless we unfold the definition. *)
Qed.
(** To automate the unfolding of definitions that appear as proof
obligation, one can use the command [Hint Unfold myFact] to tell
Coq that it should always try to unfold [myFact] when [myFact]
appears in the goal. *)
Hint Unfold myFact.
(** This time, automation is able to see through the definition
of [myFact]. *)
Lemma demo_hint_unfold_goal_2 :
(forall x, P x) -> myFact.
Proof. auto. Qed.
(** However, the [Hint Unfold] mechanism only works for unfolding
definitions that appear in the goal. In general, proof search does
not unfold definitions from the context. For example, assume we
want to prove that [P 3] holds under the assumption that [True ->
myFact]. *)
Lemma demo_hint_unfold_context_1 :
(True -> myFact) -> P 3.
Proof.
intros.
auto. (* fails *)
unfold myFact in *. auto. (* succeeds *)
Qed.
(** There is actually one exception to the previous rule: a constant
occuring in an hypothesis is automatically unfolded if the
hypothesis can be directly applied to the current goal. For example,
[auto] can prove [myFact -> P 3], as illustrated below. *)
Lemma demo_hint_unfold_context_2 :
myFact -> P 3.
Proof. auto. Qed.
(* ####################################################### *)
(** ** Automation for Proving Absurd Goals *)
(** In this section, we'll see that lemmas concluding on a negation
are generally not useful as hints, and that lemmas whose
conclusion is [False] can be useful hints but having too many of
them makes proof search inefficient. We'll also see a practical
work-around to the efficiency issue. *)
(** Consider the following lemma, which asserts that a number
less than or equal to 3 is not greater than 3. *)
Parameter le_not_gt : forall x,
(x <= 3) -> ~ (x > 3).
(** Equivalently, one could state that a number greater than three is
not less than or equal to 3. *)
Parameter gt_not_le : forall x,
(x > 3) -> ~ (x <= 3).
(** In fact, both statements are equivalent to a third one stating
that [x <= 3] and [x > 3] are contradictory, in the sense that
they imply [False]. *)
Parameter le_gt_false : forall x,
(x <= 3) -> (x > 3) -> False.
(** The following investigation aim at figuring out which of the three
statments is the most convenient with respect to proof
automation. The following material is enclosed inside a [Section],
so as to restrict the scope of the hints that we are adding. In
other words, after the end of the section, the hints added within
the section will no longer be active.*)
Section DemoAbsurd1.
(** Let's try to add the first lemma, [le_not_gt], as hint,
and see whether we can prove that the proposition
[exists x, x <= 3 /\ x > 3] is absurd. *)
Hint Resolve le_not_gt.
Lemma demo_auto_absurd_1 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
intros. jauto_set. (* decomposes the assumption *)
(* debug *) eauto. (* does not see that [le_not_gt] could apply *)
eapply le_not_gt. eauto. eauto.
Qed.
(** The lemma [gt_not_le] is symmetric to [le_not_gt], so it will not
be any better. The third lemma, [le_gt_false], is a more useful
hint, because it concludes on [False], so proof search will try to
apply it when the current goal is [False]. *)
Hint Resolve le_gt_false.
Lemma demo_auto_absurd_2 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
dup.
(* detailed version: *)
intros. jauto_set. (* debug *) eauto.
(* short version: *)
jauto.
Qed.
(** In summary, a lemma of the form [H1 -> H2 -> False] is a much more
effective hint than [H1 -> ~ H2], even though the two statments
are equivalent up to the definition of the negation symbol [~]. *)
(** That said, one should be careful with adding lemmas whose
conclusion is [False] as hint. The reason is that whenever
reaching the goal [False], the proof search mechanism will
potentially try to apply all the hints whose conclusion is [False]
before applying the appropriate one. *)
End DemoAbsurd1.
(** Adding lemmas whose conclusion is [False] as hint can be, locally,
a very effective solution. However, this approach does not scale
up for global hints. For most practical applications, it is
reasonable to give the name of the lemmas to be exploited for
deriving a contradiction. The tactic [false H], provided by
[LibTactics] serves that purpose: [false H] replaces the goal
with [False] and calls [eapply H]. Its behavior is described next.
Observe that any of the three statements [le_not_gt], [gt_not_le]
or [le_gt_false] can be used. *)
Lemma demo_false : forall x,
(x <= 3) -> (x > 3) -> 4 = 5.
Proof.
intros. dup 4.
(* A failed proof: *)
false. eapply le_gt_false.
auto. (* here, [auto] does not prove [?x <= 3] by using [H] but
by using the lemma [le_refl : forall x, x <= x]. *)
(* The second subgoal becomes [3 > 3], which is not provable. *)
skip.
(* A correct proof: *)
false. eapply le_gt_false.
eauto. (* here, [eauto] uses [H], as expected, to prove [?x <= 3] *)
eauto. (* so the second subgoal becomes [x > 3] *)
(* The same proof using [false]: *)
false le_gt_false. eauto. eauto.
(* The lemmas [le_not_gt] and [gt_not_le] work as well *)
false le_not_gt. eauto. eauto.
Qed.
(** In the above example, [false le_gt_false; eauto] proves the goal,
but [false le_gt_false; auto] does not, because [auto] does not
correctly instantiate the existential variable. Note that [false*
le_gt_false] would not work either, because the star symbol tries
to call [auto] first. So, there are two possibilities for
completing the proof: either call [false le_gt_false; eauto], or
call [false* (le_gt_false 3)]. *)
(* ####################################################### *)
(** ** Automation for Transitivity Lemmas *)
(** Some lemmas should never be added as hints, because they would
very badly slow down proof search. The typical example is that of
transitivity results. This section describes the problem and
presents a general workaround.
Consider a subtyping relation, written [subtype S T], that relates
two object [S] and [T] of type [typ]. Assume that this relation
has been proved reflexive and transitive. The corresponding lemmas
are named [subtype_refl] and [subtype_trans]. *)
Parameter typ : Type.
Parameter subtype : typ -> typ -> Prop.
Parameter subtype_refl : forall T,
subtype T T.
Parameter subtype_trans : forall S T U,
subtype S T -> subtype T U -> subtype S U.
(** Adding reflexivity as hint is generally a good idea,
so let's add reflexivity of subtyping as hint. *)
Hint Resolve subtype_refl.
(** Adding transitivity as hint is generally a bad idea. To
understand why, let's add it as hint and see what happens.
Because we cannot remove hints once we've added them, we are going
to open a "Section," so as to restrict the scope of the
transitivity hint to that section. *)
Section HintsTransitivity.
Hint Resolve subtype_trans.
(** Now, consider the goal [forall S T, subtype S T], which clearly has
no hope of being solved. Let's call [eauto] on this goal. *)
Lemma transitivity_bad_hint_1 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 106 applications... *)
Abort.
(** Note that after closing the section, the hint [subtype_trans]
is no longer active. *)
End HintsTransitivity.
(** In the previous example, the proof search has spent a lot of time
trying to apply transitivity and reflexivity in every possible
way. Its process can be summarized as follows. The first goal is
[subtype S T]. Since reflexivity does not apply, [eauto] invokes
transitivity, which produces two subgoals, [subtype S ?X] and
[subtype ?X T]. Solving the first subgoal, [subtype S ?X], is
straightforward, it suffices to apply reflexivity. This unifies
[?X] with [S]. So, the second sugoal, [subtype ?X T],
becomes [subtype S T], which is exactly what we started from...
The problem with the transitivity lemma is that it is applicable
to any goal concluding on a subtyping relation. Because of this,
[eauto] keeps trying to apply it even though it most often doesn't
help to solve the goal. So, one should never add a transitivity
lemma as a hint for proof search. *)
(** There is a general workaround for having automation to exploit
transitivity lemmas without giving up on efficiency. This workaround
relies on a powerful mechanism called "external hint." This
mechanism allows to manually describe the condition under which
a particular lemma should be tried out during proof search.
For the case of transitivity of subtyping, we are going to tell
Coq to try and apply the transitivity lemma on a goal of the form
[subtype S U] only when the proof context already contains an
assumption either of the form [subtype S T] or of the form
[subtype T U]. In other words, we only apply the transitivity
lemma when there is some evidence that this application might
help. To set up this "external hint," one has to write the
following. *)
Hint Extern 1 (subtype ?S ?U) =>
match goal with
| H: subtype S ?T |- _ => apply (@subtype_trans S T U)
| H: subtype ?T U |- _ => apply (@subtype_trans S T U)
end.
(** This hint declaration can be understood as follows.
- "Hint Extern" introduces the hint.
- The number "1" corresponds to a priority for proof search.
It doesn't matter so much what priority is used in practice.
- The pattern [subtype ?S ?U] describes the kind of goal on
which the pattern should apply. The question marks are used
to indicate that the variables [?S] and [?U] should be bound
to some value in the rest of the hint description.
- The construction [match goal with ... end] tries to recognize
patterns in the goal, or in the proof context, or both.
- The first pattern is [H: subtype S ?T |- _]. It indices that
the context should contain an hypothesis [H] of type
[subtype S ?T], where [S] has to be the same as in the goal,
and where [?T] can have any value.
- The symbol [|- _] at the end of [H: subtype S ?T |- _] indicates
that we do not impose further condition on how the proof
obligation has to look like.
- The branch [=> apply (@subtype_trans S T U)] that follows
indicates that if the goal has the form [subtype S U] and if
there exists an hypothesis of the form [subtype S T], then
we should try and apply transitivity lemma instantiated on
the arguments [S], [T] and [U]. (Note: the symbol [@] in front of
[subtype_trans] is only actually needed when the "Implicit Arguments"
feature is activated.)
- The other branch, which corresponds to an hypothesis of the form
[H: subtype ?T U] is symmetrical.
Note: the same external hint can be reused for any other transitive
relation, simply by renaming [subtype] into the name of that relation. *)
(** Let us see an example illustrating how the hint works. *)
Lemma transitivity_workaround_1 : forall T1 T2 T3 T4,
subtype T1 T2 -> subtype T2 T3 -> subtype T3 T4 -> subtype T1 T4.
Proof.
intros. (* debug *) eauto. (* The trace shows the external hint being used *)
Qed.
(** We may also check that the new external hint does not suffer from the
complexity blow up. *)
Lemma transitivity_workaround_2 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 0 applications *)
Abort.
(* ####################################################### *)
(** * Decision Procedures *)
(** A decision procedure is able to solve proof obligations whose
statement admits a particular form. This section describes three
useful decision procedures. The tactic [omega] handles goals
involving arithmetic and inequalities, but not general
multiplications. The tactic [ring] handles goals involving
arithmetic, including multiplications, but does not support
inequalities. The tactic [congruence] is able to prove equalities
and inequalities by exploiting equalities available in the proof
context. *)
(* ####################################################### *)
(** ** Omega *)
(** The tactic [omega] supports natural numbers (type [nat]) as well as
integers (type [Z], available by including the module [ZArith]).
It supports addition, substraction, equalities and inequalities.
Before using [omega], one needs to import the module [Omega],
as follows. *)
Require Import Omega.
(** Here is an example. Let [x] and [y] be two natural numbers
(they cannot be negative). Assume [y] is less than 4, assume
[x+x+1] is less than [y], and assume [x] is not zero. Then,
it must be the case that [x] is equal to one. *)
Lemma omega_demo_1 : forall (x y : nat),
(y <= 4) -> (x + x + 1 <= y) -> (x <> 0) -> (x = 1).
Proof. intros. omega. Qed.
(** Another example: if [z] is the mean of [x] and [y], and if the
difference between [x] and [y] is at most [4], then the difference
between [x] and [z] is at most 2. *)
Lemma omega_demo_2 : forall (x y z : nat),
(x + y = z + z) -> (x - y <= 4) -> (x - z <= 2).
Proof. intros. omega. Qed.
(** One can proof [False] using [omega] if the mathematical facts
from the context are contradictory. In the following example,
the constraints on the values [x] and [y] cannot be all
satisfied in the same time. *)
Lemma omega_demo_3 : forall (x y : nat),
(x + 5 <= y) -> (y - x < 3) -> False.
Proof. intros. omega. Qed.
(** Note: [omega] can prove a goal by contradiction only if its
conclusion is reduced [False]. The tactic [omega] always fails
when the conclusion is an arbitrary proposition [P], even though
[False] implies any proposition [P] (by [ex_falso_quodlibet]). *)
Lemma omega_demo_4 : forall (x y : nat) (P : Prop),
(x + 5 <= y) -> (y - x < 3) -> P.
Proof.
intros.
(* Calling [omega] at this point fails with the message:
"Omega: Can't solve a goal with proposition variables" *)
(* So, one needs to replace the goal by [False] first. *)
false. omega.
Qed.
(* ####################################################### *)
(** ** Ring *)
(** Compared with [omega], the tactic [ring] adds support for
multiplications, however it gives up the ability to reason on
inequations. Moreover, it supports only integers (type [Z]) and
not natural numbers (type [nat]). Here is an example showing how
to use [ring]. *)
Module RingDemo.
Require Import ZArith.
Open Scope Z_scope.
(* Arithmetic symbols are now interpreted in [Z] *)
Lemma ring_demo : forall (x y z : Z),
x * (y + z) - z * 3 * x
= x * y - 2 * x * z.
Proof. intros. ring. Qed.
End RingDemo.
(* ####################################################### *)
(** ** Congruence *)
(** The tactic [congruence] is able to exploit equalities from the
proof context in order to automatically perform the rewriting
operations necessary to establish a goal. It is slightly more
powerful than the tactic [subst], which can only handle equalities
of the form [x = e] where [x] is a variable and [e] an
expression. *)
Lemma congruence_demo_1 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
f (g x) (g y) = z ->
2 = g x ->
g y = h z ->
f 2 (h z) = z.
Proof. intros. congruence. Qed.
(** Moreover, [congruence] is able to exploit universally quantified
equalities, for example [forall a, g a = h a]. *)
Lemma congruence_demo_2 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
(forall a, g a = h a) ->
f (g x) (g y) = z ->
g x = 2 ->
f 2 (h y) = z.
Proof. congruence. Qed.
(** Next is an example where [congruence] is very useful. *)
Lemma congruence_demo_4 : forall (f g : nat->nat),
(forall a, f a = g a) ->
f (g (g 2)) = g (f (f 2)).
Proof. congruence. Qed.
(** The tactic [congruence] is able to prove a contradiction if the
goal entails an equality that contradicts an inequality available
in the proof context. *)
Lemma congruence_demo_3 :
forall (f g h : nat->nat) (x : nat),
(forall a, f a = h a) ->
g x = f x ->
g x <> h x ->
False.
Proof. congruence. Qed.
(** One of the strengths of [congruence] is that it is a very fast
tactic. So, one should not hesitate to invoke it wherever it might
help. *)
(* ####################################################### *)
(** * Summary *)
(** Let us summarize the main automation tactics available.
- [auto] automatically applies [reflexivity], [assumption], and [apply].
- [eauto] moreover tries [eapply], and in particular can instantiate
existentials in the conclusion.
- [iauto] extends [eauto] with support for negation, conjunctions, and
disjunctions. However, its support for disjunction can make it
exponentially slow.
- [jauto] extends [eauto] with support for negation, conjunctions, and
existential at the head of hypothesis.
- [congruence] helps reasoning about equalities and inequalities.
- [omega] proves arithmetic goals with equalities and inequalities,
but it does not support multiplication.
- [ring] proves arithmetic goals with multiplications, but does not
support inequalities.
In order to set up automation appropriately, keep in mind the following
rule of thumbs:
- automation is all about balance: not enough automation makes proofs
not very robust on change, whereas too much automation makes proofs
very hard to fix when they break.
- if a lemma is not goal directed (i.e., some of its variables do not
occur in its conclusion), then the premises need to be ordered in
such a way that proving the first premises maximizes the chances of
correctly instantiating the variables that do not occur in the conclusion.
- a lemma whose conclusion is [False] should only be added as a local
hint, i.e., as a hint within the current section.
- a transitivity lemma should never be considered as hint; if automation
of transitivity reasoning is really necessary, an [Extern Hint] needs
to be set up.
- a definition usually needs to be accompanied with a [Hint Unfold].
Becoming a master in the black art of automation certainly requires
some investment, however this investment will pay off very quickly.
*)
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:16:45 08/23/2013
// Design Name: modulo_uno
// Module Name: C:/Users/Fabian/Documents/Taller Diseno/Xilinx/Lab1/maquina_mealy/text_figure_uno.v
// Project Name: maquina_mealy
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: modulo_uno
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module text_figure_uno;
// Inputs
reg clk;
reg rst;
reg L;
// Outputs
wire P;
// Instantiate the Unit Under Test (UUT)
modulo_uno uut (
.clk(clk),
.rst(rst),
.L(L),
.P(P)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
L = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
clk = 1;
#50
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
`ifdef verilator
`define CLOG2 $clog2
`else
`define CLOG2 clog2_emulate
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Need temp wires as function has different width rules than $clog2
wire [127:0] pows = 128'h1<<crc[7:0];
wire [127:0] npows = ~pows;
wire [31:0] out = `CLOG2(crc[7:0]);
wire [31:0] out2 = `CLOG2(crc);
wire [31:0] out3 = `CLOG2(pows);
wire [31:0] out4 = `CLOG2(npows);
// Aggregate outputs into a single result vector
wire [63:0] result = {out4[15:0], out3[15:0], out2[15:0], out[15:0]};
`define EXPECTED_SUM 64'h73c48afee4f0cb57
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
crc <= 64'h0;
if (`CLOG2(32'h0) != 0) $stop;
if (`CLOG2(32'h1) != 0) $stop;
if (`CLOG2(32'h4) != 2) $stop;
if (`CLOG2(32'h7) != 3) $stop;
if (`CLOG2(32'h8) != 3) $stop;
if (`CLOG2(32'h9) != 4) $stop;
if (`CLOG2({32{1'b1}}) != 32) $stop;
if (`CLOG2({1'b1,32'b0}) != 32) $stop;
if (`CLOG2({64{1'b1}}) != 64) $stop;
if (`CLOG2({1'b1,64'b0}) != 64) $stop;
if (`CLOG2({128{1'b1}}) != 128) $stop;
if (`CLOG2({1'b1,128'b0}) != 128) $stop;
if (`CLOG2({2'b10,128'b0}) != 129) $stop;
end
else if (cyc==1) begin
crc <= 64'h1;
if (result[31:0] != {16'd0, 16'd0}) $stop;
end
else if (cyc==2) begin
crc <= 64'h3;
if (result[31:0] != {16'd0, 16'd0}) $stop;
end
else if (cyc==3) begin
crc <= {64{1'b1}};
if (result[31:0] != {16'd2, 16'd2}) $stop;
end
else if (cyc==4) begin
if (result[31:0] != {16'd64, 16'd8}) $stop;
end
else if (cyc==8) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hcbc77bb9b3784ea0) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer clog2_emulate(input [130:0] arg);
begin
if (arg!=0) arg = arg - 1;
for (clog2_emulate=0; arg!=0; clog2_emulate=clog2_emulate+1)
arg = (arg >> 1);
end
endfunction
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_MNC_getFT for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_MNC_getFT
// Module Name: NPCG_Toggle_MNC_getFT
// File Name: NPCG_Toggle_MNC_getFT.v
//
// Version: v1.0.0
//
// Description: Get feature execution FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_MNC_N_init
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
iWaySelect ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
input [NumberOfWays - 1:0] iWaySelect ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
// FSM Parameters/Wires/Regs
localparam N_i_FSM_BIT = 6; // NAND initialization
localparam N_i_RESET = 6'b00_0001;
localparam N_i_READY = 6'b00_0010;
localparam N_i_00001 = 6'b00_0100; // capture, CAL start
localparam N_i_00002 = 6'b00_1000; // CA data
localparam N_i_00003 = 6'b01_0000; // Timer start ready, Timer Loop
localparam N_i_00004 = 6'b10_0000; // wait for request done
reg [N_i_FSM_BIT-1:0] r_N_i_cur_state ;
reg [N_i_FSM_BIT-1:0] r_N_i_nxt_state ;
// Internal Wires/Regs
reg [4:0] rSourceID ;
reg rCMDReady ;
reg [NumberOfWays - 1:0] rWaySelect ;
wire wLastStep ;
reg [7:0] rPM_PCommand ;
reg [2:0] rPM_PCommandOption ;
reg [15:0] rPM_NumOfData ;
reg rPM_CASelect ;
reg [7:0] rPM_CAData ;
wire wPCGStart ;
wire wCapture ;
wire wPMReady ;
wire wCALReady ;
wire wCALStart ;
wire wCALDone ;
wire wTMReady ;
wire wTMStart ;
wire wTMDone ;
reg [3:0] rTM_counter ;
wire wTM_LoopDone ;
// Control Signals
// Flow Contorl
assign wPCGStart = (iOpcode[5:0] == 6'b101100) & (iTargetID[4:0] == 5'b00101) & iCMDValid;
assign wCapture = (r_N_i_cur_state[N_i_FSM_BIT-1:0] == N_i_READY);
assign wPMReady = (iPM_Ready[5:0] == 6'b111111);
assign wCALReady = wPMReady;
assign wCALStart = wCALReady & rPM_PCommand[3];
assign wCALDone = iPM_LastStep[3];
assign wTMReady = wPMReady;
assign wTMStart = wTMReady & rPM_PCommand[0];
assign wTMDone = iPM_LastStep[0];
assign wTM_LoopDone = (rTM_counter[3:0] == 4'd10);
assign wLastStep = wTMDone & wTM_LoopDone & (r_N_i_cur_state[N_i_FSM_BIT-1:0] == N_i_00004);
// FSM: read STatus
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
r_N_i_cur_state <= N_i_RESET;
end else begin
r_N_i_cur_state <= r_N_i_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (r_N_i_cur_state)
N_i_RESET: begin
r_N_i_nxt_state <= N_i_READY;
end
N_i_READY: begin
r_N_i_nxt_state <= (wPCGStart)? N_i_00001:N_i_READY;
end
N_i_00001: begin
r_N_i_nxt_state <= (wCALStart)? N_i_00002:N_i_00001;
end
N_i_00002: begin
r_N_i_nxt_state <= N_i_00003;
end
N_i_00003: begin
r_N_i_nxt_state <= (wTM_LoopDone)? N_i_00004:N_i_00003;
end
N_i_00004: begin
r_N_i_nxt_state <= (wLastStep)? N_i_READY:N_i_00004;
end
default:
r_N_i_nxt_state <= N_i_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rSourceID[4:0] <= 0;
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end else begin
case (r_N_i_nxt_state)
N_i_RESET: begin
rSourceID[4:0] <= 0;
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end
N_i_READY: begin
rSourceID[4:0] <= 0;
rCMDReady <= 1;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end
N_i_00001: begin
rSourceID[4:0] <= (wCapture)? iSourceID[4:0]:rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= (wCapture)? iWaySelect[NumberOfWays - 1:0]:rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_1000;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 15'h0000;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end
N_i_00002: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 1'b0;
rPM_CAData[7:0] <= 8'hFF;
rTM_counter[3:0] <= 4'b0001;
end
N_i_00003: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_0001;
rPM_PCommandOption[2:0] <= 3'b001; // CE on
rPM_NumOfData[15:0] <= 16'd50000; // real condition
//rPM_NumOfData[15:0] <= 16'd5; // test condition
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= (wTMDone)? (rTM_counter[3:0] + 1'b1):(rTM_counter[3:0]);
end
N_i_00004: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_0000;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= rTM_counter[3:0];
end
endcase
end
end
// Output
assign oCMDReady = rCMDReady;
assign oStart = wPCGStart;
assign oLastStep = wLastStep;
assign oPM_PCommand[7:0] = rPM_PCommand[7:0];
assign oPM_PCommandOption[2:0] = rPM_PCommandOption[2:0];
assign oPM_TargetWay[NumberOfWays - 1:0] = rWaySelect[NumberOfWays - 1:0];
assign oPM_NumOfData[15:0] = rPM_NumOfData[15:0];
assign oPM_CASelect = rPM_CASelect;
assign oPM_CAData[7:0] = rPM_CAData[7:0];
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_ddrc.v
*
* Date : 2012-11
*
* Description : Module that acts as controller for sparse memory (DDR).
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_5.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_5) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_5_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_5_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_5" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_5_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
// To match RTL : In RTL, write enable of the primitive is tied to all 1's and
// the enable of the primitive is ANDing of wea(0) and ena. so eventually, the
// write operation depends on both enable and write enable. So, the below code
// which is actually doing the write operation only on enable ignoring the wea
// is removed to be in consistent with RTL.
// To Fix CR855535 (The fix to this CR is reverted to match RTL)
//assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_5
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h966e272fd829e672
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] out;
// End of automatics
`ifdef verilator
`define dontOptimize $c1("1")
`else
`define dontOptimize 1'b1
`endif
always @(posedge clk) begin
out <= in;
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
if (in[0])
out <= ~in;
end
endmodule
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//
// Computes the ECC for an 32-bit data stream based on the data and address of
// data in the stream.
//
// data_i - 32-bit input data
// addr_i - address of data in stream
// ecc_o - 24-bit ecc value for the current 8-bit value
//
module hamm_4096x1_1x32 (
input wire [31:0] data_i,
input wire [6:0] addr_i,
output wire [23:0] ecc_o
);
wire [31:0] d = data_i;
// compute xor of all bits in data_i
wire [7:0] data_xor = ^d;
// calculate even bits for bit addresses then byte addresses
assign ecc_o[0] = d[0] ^ d[2] ^ d[4] ^ d[6] ^ d[8] ^ d[10] ^ d[12] ^ d[14] ^ d[16] ^ d[18] ^ d[20] ^ d[22] ^ d[24] ^ d[26] ^ d[28] ^ d[30];
assign ecc_o[1] = d[0] ^ d[1] ^ d[4] ^ d[5] ^ d[8] ^ d[9] ^ d[12] ^ d[13] ^ d[16] ^ d[17] ^ d[20] ^ d[21] ^ d[24] ^ d[25] ^ d[28] ^ d[29];
assign ecc_o[2] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[24] ^ d[25] ^ d[26] ^ d[27];
assign ecc_o[3] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23];
assign ecc_o[4] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15];
assign ecc_o[5] = ~addr_i[0] & data_xor;
assign ecc_o[6] = ~addr_i[1] & data_xor;
assign ecc_o[7] = ~addr_i[2] & data_xor;
assign ecc_o[8] = ~addr_i[3] & data_xor;
assign ecc_o[9] = ~addr_i[4] & data_xor;
assign ecc_o[10] = ~addr_i[5] & data_xor;
assign ecc_o[11] = ~addr_i[6] & data_xor;
// calculate odd bits for bit addresses then byte addresses
assign ecc_o[12+0] = d[1] ^ d[3] ^ d[5] ^ d[7] ^ d[9] ^ d[11] ^ d[13] ^ d[15] ^ d[17] ^ d[19] ^ d[21] ^ d[23] ^ d[25] ^ d[27] ^ d[29] ^ d[31];
assign ecc_o[12+1] = d[2] ^ d[3] ^ d[6] ^ d[7] ^ d[10] ^ d[11] ^ d[14] ^ d[15] ^ d[18] ^ d[19] ^ d[22] ^ d[23] ^ d[26] ^ d[27] ^ d[30] ^ d[31];
assign ecc_o[12+2] = d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
assign ecc_o[12+3] = d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
assign ecc_o[12+4] = d[16] ^ d[17] ^ d[18] ^ d[19] ^ d[20] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[30] ^ d[31];
assign ecc_o[12+5] = addr_i[0] & data_xor;
assign ecc_o[12+6] = addr_i[1] & data_xor;
assign ecc_o[12+7] = addr_i[2] & data_xor;
assign ecc_o[12+8] = addr_i[3] & data_xor;
assign ecc_o[12+9] = addr_i[4] & data_xor;
assign ecc_o[12+10] = addr_i[5] & data_xor;
assign ecc_o[12+11] = addr_i[6] & data_xor;
endmodule
//
// Performs hamming calculations on up to 4096 bits (512 bytes) and computes a
// 24-bit hamming ECC
//
// clk, rst -
// standard clocking and reset signals
// data_i, valid_i, sof_i, eof_i -
// 8-bit input data bus on its way to/from the flash device
// data_o, valid_o, sof_o, eof_o, ecc_o -
// 8-bit output data bus and ecc on its way to/from the flash device
// pipelined one clock cycle after input
//
module hamm_4096x1_512x32 (
input wire clk,
input wire rst,
input wire [31:0] data_i,
input wire valid_i,
input wire sof_i,
input wire eof_i,
output wire [31:0] data_o,
output wire valid_o,
output wire sof_o,
output wire eof_o,
output wire [23:0] ecc_o
);
// register all inputs to ease timing
reg [31:0] data_r;
reg valid_r;
reg sof_r;
reg eof_r;
always @(posedge clk) begin
data_r <= data_i;
valid_r <= valid_i;
sof_r <= sof_i;
eof_r <= eof_i;
end
reg [6:0] addr_r;
wire [23:0] byte_ecc;
hamm_4096x1_1x32 hamm_4096x1_1x32 (
.data_i ( data_r ),
.addr_i ( addr_r ),
.ecc_o ( byte_ecc )
);
reg [23:0] ecc_r;
always @(posedge clk) begin
// sync reset all registers to 0
if(rst) begin
addr_r <= 0;
ecc_r <= 0;
end else begin
if(valid_r) begin
// clear ecc when sof_i is asserted
if(sof_r) begin
// computed for addr_r == 0
ecc_r <= byte_ecc;
addr_r <= 1;
// otherwise keep computing ecc
end else begin
// computed for addr_r++
ecc_r <= ecc_r ^ byte_ecc;
// reset addr_r on eof
addr_r <= eof_r ? 0 : addr_r + 1;
end
end
end
end
// output data_o one clock cycle after data_i
assign data_o = data_r;
assign valid_o = valid_r;
assign sof_o = sof_r;
assign eof_o = eof_r;
// ecc_o is output when eof_o is high
assign ecc_o = eof_r ? ecc_r ^ byte_ecc : 0;
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Inverse_Park_Transform.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Inverse_Park_Transform
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Transform_dq_to_ABC/Inverse_Park_Transform
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Inverse_Park_Transform
(
direct_voltage,
quadrature_voltage,
sin_coefficient,
cos_coefficient,
alpha_voltage,
beta_voltage
);
input signed [17:0] direct_voltage; // sfix18_En12
input signed [17:0] quadrature_voltage; // sfix18_En12
input signed [17:0] sin_coefficient; // sfix18_En16
input signed [17:0] cos_coefficient; // sfix18_En16
output signed [17:0] alpha_voltage; // sfix18_En10
output signed [17:0] beta_voltage; // sfix18_En10
wire signed [35:0] Product2_out1; // sfix36_En28
wire signed [35:0] Product3_out1; // sfix36_En28
wire signed [35:0] alpha_voltage_1; // sfix36_En28
wire signed [17:0] Convert_Data_Type_out1; // sfix18_En10
wire signed [35:0] Product_out1; // sfix36_En28
wire signed [35:0] Product1_out1; // sfix36_En28
wire signed [35:0] beta_voltage_1; // sfix36_En28
wire signed [17:0] Convert_Data_Type1_out1; // sfix18_En10
// Inverse Park Transform
//
// Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta)
// <S40>/Product2
assign Product2_out1 = direct_voltage * cos_coefficient;
// <S40>/Product3
assign Product3_out1 = quadrature_voltage * sin_coefficient;
// <S40>/Add1
assign alpha_voltage_1 = Product2_out1 - Product3_out1;
// <S40>/Convert_Data_Type
controllerHdl_Convert_Data_Type_block2 u_Convert_Data_Type (.In1(alpha_voltage_1), // sfix36_En28
.Out1(Convert_Data_Type_out1) // sfix18_En10
);
assign alpha_voltage = Convert_Data_Type_out1;
// <S40>/Product
assign Product_out1 = direct_voltage * sin_coefficient;
// <S40>/Product1
assign Product1_out1 = quadrature_voltage * cos_coefficient;
// <S40>/Add
assign beta_voltage_1 = Product_out1 + Product1_out1;
// <S40>/Convert_Data_Type1
controllerHdl_Convert_Data_Type1 u_Convert_Data_Type1 (.In1(beta_voltage_1), // sfix36_En28
.Out1(Convert_Data_Type1_out1) // sfix18_En10
);
assign beta_voltage = Convert_Data_Type1_out1;
endmodule // controllerHdl_Inverse_Park_Transform
|
/*
Execute Module (64-bit, Secondary)
The secondary execute units omit some features:
Can't access memory.
Dont have a multiply or shift.
...
*/
`include "CoreDefs.v"
module ExOp64_3B(
/* verilator lint_off UNUSED */
clock, reset,
opCmd, opStepPc,
regIdRs, regValRs,
regIdRt, regValRt,
regIdRn, regValRn,
immValRi, idInGenPc,
regOutId, regOutVal,
regOutOK, ctlInSr
);
input clock;
input reset;
input[7:0] opCmd; //command opcode
input[3:0] opStepPc;
input[63:0] idInGenPc; //ID's Next PC (Next Fetch)
input[6:0] regIdRs;
input[6:0] regIdRt;
input[6:0] regIdRn;
input[63:0] regValRs; //Rs input value
input[63:0] regValRt; //Rt input value
input[63:0] regValRn; //Rn input value
input[63:0] immValRi; //immediate/disp value
output[63:0] regOutVal; //Rn output value
output[6:0] regOutId; //Rn, value to write
output[1:0] regOutOK; //execute status
/* Special Registers */
input[63:0] ctlInSr; //SR in
// input[63:0] ctlInPr; //PR in
// input[63:0] ctlInPc; //PC in
// input[63:0] ctlInMach; //MACH:MACL in
// input[63:0] ctlInMacl; //MACH:MACL in
// output[63:0] ctlOutMach; //MACH:MACL out
// output[63:0] ctlOutMacl; //MACH:MACL out
/* Temporary */
reg[63:0] tRegOutVal; //Rn, output value
reg[6:0] tRegOutId; //Rn, output register
reg[1:0] tRegOutOK; //execute status
/* verilator lint_off UNOPTFLAT */
reg[63:0] tAguRtRi; //AGU Rt+Ri
reg[63:0] tAguRtRiSc; //AGU (Rt+Ri)*Sc
reg[63:0] tAguAddr; //AGU Address
/* verilator lint_on UNOPTFLAT */
assign regOutVal = tRegOutVal;
assign regOutId = tRegOutId;
assign regOutOK = tRegOutOK;
reg tInAluC;
reg tOutAluC;
reg tTriggerExc;
/*
reg[63:0] tShadValRs;
reg[ 7:0] tShadValRt;
wire[63:0] tShadValRn;
reg[ 2:0] tShadOp;
ExShad64 sh64(
clock, reset,
tShadValRs, tShadValRt,
tShadValRn, tShadOp);
*/
reg[64:0] tAluDn1;
reg[64:0] tAluDn2;
reg tAluQ0;
reg tAluM0;
reg tAluT0;
reg tAluQ1;
reg tAluM1;
reg tAluT1;
reg tAluQ2;
reg tAluM2;
reg tAluT2;
/* EX */
always @*
begin
tRegOutVal=0;
tRegOutId=UREG_ZZR;
tRegOutOK=UMEM_OK_OK;
tInAluC=1'bX;
tOutAluC=1'bX;
// tMacValRs=64'hX;
// tMacValRt=64'hX;
// tMacValRu=64'hX;
// tMacOp=0;
// tShadValRs=32'hXXXXXXXX;
// tShadValRt=8'hXX;
// tShadOp=0;
tTriggerExc=0;
// tCtlNxtPc=ctlInPc+{28'h0, opStepPc};
// tCtlPrPc=tCtlNxtPc + 2;
// tCtlBraPc=tCtlPrPc + (immValRi<<1);
/*
tAguRtRi=regValRt+immValRi;
if(regIdRt==UREG_R0)
begin
tAguAddr=opCmd[2]?
(regValRs+tAguRtRi):
(regValRn+tAguRtRi);
end
else
begin
case(opCmd[2:0])
3'h0: tAguAddr=regValRn+tAguRtRi;
3'h1: tAguAddr=regValRn+(tAguRtRi<<1);
3'h2: tAguAddr=regValRn+(tAguRtRi<<2);
3'h3: tAguAddr=regValRn+(tAguRtRi<<3);
3'h4: tAguAddr=regValRs+tAguRtRi;
3'h5: tAguAddr=regValRs+(tAguRtRi<<1);
3'h6: tAguAddr=regValRs+(tAguRtRi<<2);
3'h7: tAguAddr=regValRs+(tAguRtRi<<3);
endcase
end
*/
/*
tAguRtRi=regValRt+immValRi;
case(opCmd[1:0])
2'h0: tAguRtRiSc=tAguRtRi;
2'h1: tAguRtRiSc={tAguRtRi[62:0], 1'b0};
2'h2: tAguRtRiSc={tAguRtRi[61:0], 2'b0};
2'h3: tAguRtRiSc={tAguRtRi[60:0], 3'b0};
endcase
tAguAddr=(opCmd[2]?regValRs:regValRn)+
((regIdRt==UREG_R0)?tAguRtRi:tAguRtRiSc);
*/
casez(opCmd)
UCMD_NONE: begin
end
UCMD_MOV_RR: begin
tRegOutVal=regValRs;
tRegOutId=regIdRn;
end
UCMD_MOV_RI: begin
tRegOutVal=immValRi;
tRegOutId=regIdRn;
end
/*
UCMD_LEAB_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_LEAW_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_LEAL_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
UCMD_LEAQ_MR: begin
tRegOutVal=tAguAddr;
tRegOutId=regIdRn;
end
*/
UCMD_ALU_ADD: begin
tRegOutVal=regValRs+regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_SUB: begin
tRegOutVal=regValRs-regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_MUL: begin
// tRegOutVal=regValRs*regValRt;
tRegOutId=regIdRn;
// tMacValRs = {32'h0, regValRs};
// tMacValRt = {32'h0, regValRt};
// tMacOp = 2'h3;
end
UCMD_ALU_AND: begin
tRegOutVal=regValRs®ValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_OR: begin
tRegOutVal=regValRs|regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_XOR: begin
tRegOutVal=regValRs^regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_ADDC: begin
tInAluC=ctlInSr[0];
{tOutAluC, tRegOutVal}=
{ 1'b0, regValRs+regValRt}+
{64'h0, tInAluC};
// tCtlOutSr[0]=tOutAluC;
tRegOutId=regIdRn;
end
UCMD_ALU_SUBC: begin
tInAluC=ctlInSr[0];
{tOutAluC, tRegOutVal}=
{ 1'b0, regValRs-regValRt}-
{64'h0, tInAluC};
// tCtlOutSr[0]=tOutAluC;
tRegOutId=regIdRn;
end
UCMD_ALU_ADDV: begin
{tOutAluC, tRegOutVal}=
{ regValRs[63], regValRs}+
{ regValRt[63], regValRt};
// tCtlOutSr[0]=tOutAluC^tRegOutVal[31];
tRegOutId=regIdRn;
end
UCMD_ALU_SUBV: begin
{tOutAluC, tRegOutVal}=
{ regValRs[63], regValRs}-
{ regValRt[63], regValRt};
// tCtlOutSr[0]=tOutAluC^tRegOutVal[31];
tRegOutId=regIdRn;
end
/*
UCMD_ALU_SHAD: begin
tShadValRs=regValRs;
tShadOp=2;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_SHLD: begin
tShadValRs=regValRs;
tShadOp=1;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_SHADR: begin
tShadValRs=regValRs;
tShadOp=4;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
UCMD_ALU_SHLDR: begin
tShadValRs=regValRs;
tShadOp=3;
tShadValRt=regValRt[7:0];
tRegOutId=regIdRn;
end
*/
UCMD_ALU_LDSH16: begin
tRegOutVal={regValRs[47:0], 16'h0} +
regValRt;
tRegOutId=regIdRn;
end
UCMD_ALU_NOT: begin
tRegOutVal=~regValRs;
tRegOutId=regIdRn;
end
UCMD_ALU_SWAPB: begin
tRegOutVal={
regValRs[55:48],
regValRs[63:56],
regValRs[39:32],
regValRs[47:40],
regValRs[23:16],
regValRs[31:24],
regValRs[ 7: 0],
regValRs[15: 8]
};
tRegOutId=regIdRn;
end
UCMD_ALU_SWAPW: begin
tRegOutVal={
regValRs[47:32],
regValRs[63:48],
regValRs[15: 0],
regValRs[31:16]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTUB: begin
tRegOutVal={56'h0, regValRs[7:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTUW: begin
tRegOutVal={48'h0, regValRs[15:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTSB: begin
tRegOutVal={regValRs[7]?56'hFF_FFFF_FFFF_FFFF:56'h0, regValRs[7:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_EXTSW: begin
tRegOutVal={regValRs[15]?48'hFFFF_FFFF_FFFF:48'h0, regValRs[15:0]};
tRegOutId=regIdRn;
end
UCMD_ALU_NEG: begin
tRegOutVal=-regValRs;
tRegOutId=regIdRn;
end
UCMD_ALU_NEGC: begin
{tOutAluC, tRegOutVal}=
{1'b1, ~regValRs}+
(ctlInSr[0] ? 65'h0 : 65'h1);
tRegOutId=regIdRn;
end
default: begin end
endcase
end
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
`timescale 1ns / 1ps
module controler_tb();
reg power, start_pause, weight_ch, mode_ch, clk_src;
wire power_light;
wire start_pause_light, water_in_light, washing_light, rinsing_light, dewatering_light, water_out_light;
wire [7:0]anodes, cnodes;
wire [2:0]weight_ch_light;
wire [2:0]state;
wire alarm;
parameter TIME = 1000, DELAY = 10;
controler #(32,0) CONTROLER (.power(power),
.start_pause(start_pause),
.weight_ch(weight_ch),
.mode_ch(mode_ch),
.clk_src(clk_src),
.start_pause_light(start_pause_light),
.weight_ch_light(weight_ch_light),
.water_in_light(water_in_light),
.washing_light(washing_light),
.rinsing_light(rinsing_light),
.dewatering_light(dewatering_light),
.water_out_light(water_out_light),
.power_light(power_light),
.state(state),
.alarm(alarm),
.anodes(anodes),
.cnodes(cnodes)
);
initial begin
power = 0;
clk_src = 0;
start_pause = 0;
weight_ch = 0;
mode_ch = 0;
#TIME $finish;
end
always begin
#(DELAY/10) clk_src = ~clk_src;
end
always begin
#(2*DELAY) mode_ch = 1;
#(2*DELAY) weight_ch = 1; mode_ch = 0; // cann't change when machine isn't turn on
#(2*DELAY) power = 1; weight_ch = 0;
#(2*DELAY) mode_ch = 1; weight_ch = 1;
#(DELAY/10) mode_ch = 0; weight_ch = 0;
#(2*DELAY) start_pause = 1;
#(2*DELAY) mode_ch = 1; weight_ch = 1; // cann't change when machine is start
#((2*DELAY)/10) mode_ch = 0; weight_ch = 0;
#(2*DELAY) start_pause = 0;
#(2*DELAY) mode_ch = 1; weight_ch = 1; // change when machine is pause
#(DELAY/10) mode_ch = 0; weight_ch = 0;
#(2*DELAY) start_pause = 1; // start in new mode
#(2*DELAY) start_pause = 0;
#(5*DELAY) start_pause = 1; // test start_pause
#(73*DELAY) ;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:28:48 05/31/2011
// Design Name: upd77c25
// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/updtest.tf
// Project Name: sd2snes
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: upd77c25
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module updtest;
// Inputs
reg [7:0] DI;
reg A0;
reg nCS;
reg nRD;
reg nWR;
reg RST;
reg CLK;
reg PGM_WR;
reg [23:0] PGM_DI;
reg [10:0] PGM_WR_ADDR;
reg DAT_WR;
reg [15:0] DAT_DI;
reg [9:0] DAT_WR_ADDR;
// debug
wire [15:0] SR;
wire [15:0] DR;
wire [10:0] PC;
wire [15:0] A;
wire [15:0] B;
wire [5:0] FL_A;
wire [5:0] FL_B;
// Outputs
wire [7:0] DO;
// variables
integer i;
// Instantiate the Unit Under Test (UUT)
upd77c25 uut (
.DI(DI),
.DO(DO),
.A0(A0),
.nCS(nCS),
.nRD(nRD),
.nWR(nWR),
.DP_nCS(1'b1),
.RST(RST),
.CLK(CLK),
.PGM_WR(PGM_WR),
.PGM_DI(PGM_DI),
.PGM_WR_ADDR(PGM_WR_ADDR),
.DAT_WR(DAT_WR),
.DAT_DI(DAT_DI),
.DAT_WR_ADDR(DAT_WR_ADDR),
.SR(SR),
.DR(DR),
.PC(PC),
.A(A),
.B(B),
.FL_A(FL_A),
.FL_B(FL_B)
);
initial begin
// Initialize Inputs
DI = 0;
A0 = 0;
nCS = 0;
nRD = 1;
nWR = 1;
RST = 1;
CLK = 0;
PGM_WR = 0;
PGM_DI = 0;
PGM_WR_ADDR = 0;
DAT_WR = 0;
DAT_DI = 0;
DAT_WR_ADDR = 0;
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
nRD = 0;
#100 nRD = 1;
for (i=0; i < 1; i = i + 1) begin
#200 nRD = 0;
#200 nRD = 1;
end
#1000 DI = 8'h02;
nWR = 0;
#200 nWR = 1;
#3000 DI = 8'hc2;
for (i=0; i < 6; i = i + 1) begin
#400 nWR = 0;
#400 nWR = 1;
#400 nWR = 0;
#400 nWR = 1;
end
#15000;
#200 nWR = 0;
#200 nWR = 1;
#200 nWR = 0;
#200 nWR = 1;
#50000;
for (i=0; i < 10; i = i + 1) begin
#200 nRD = 0;
#200 nRD = 1;
end
#200 DI = 8'h06;
nWR = 0;
#200 nWR = 1;
#200 DI = 8'h7f;
for (i=0; i < 3; i = i + 1) begin
#400 nWR = 0;
#400 nWR = 1;
#400 nWR = 0;
#400 nWR = 1;
end
#15000;
for (i=0; i < 10; i = i + 1) begin
#200 nRD = 0;
#200 nRD = 1;
end
end
always #6 CLK = ~CLK;
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Mon Aug 29 03:22:14 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/nop/PCIe_bandwidth/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
/* Model for xilinx async fifo*/
module fifo_async_104x32
(/*AUTOARG*/
// Outputs
full, prog_full, dout, empty, valid,
// Inputs
rst, wr_clk, rd_clk, wr_en, din, rd_en
);
parameter DW = 104;//104 wide
parameter DEPTH = 16; //
// almost_full,
// wr_rst, rd_rst,
//##########
//# RESET/CLOCK
//##########
input wr_rst; //asynchronous reset
input rd_rst; //asynchronous reset
input wr_clk; //write clock
input rd_clk; //read clock
//##########
//# FIFO WRITE
//##########
input wr_en;
input [DW-1:0] din;
output full;
output prog_full;
output almost_full;
//###########
//# FIFO READ
//###########
input rd_en;
output [DW-1:0] dout;
output empty;
output valid;
input rst;
defparam fifo_model.DW=104;
defparam fifo_model.DEPTH=32;
fifo_async_model fifo_model (/*AUTOINST*/
// Outputs
.full (full),
.prog_full (prog_full),
//.almost_full (almost_full),
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.rst (rst),
//.wr_rst (wr_rst),
//.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
endmodule // fifo_async
// Local Variables:
// verilog-library-directories:("." "../../memory/hdl")
// End:
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
`include "macro.v"
module id_ex_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`ALU_OPERATOR_BUS] id_operator,
input wire[`ALU_CATEGORY_BUS] id_category,
input wire[`REGS_DATA_BUS] id_operand1,
input wire[`REGS_DATA_BUS] id_operand2,
input wire[`REGS_ADDR_BUS] id_write_addr,
input wire id_write_enable,
input wire[`REGS_DATA_BUS] id_return_target,
input wire id_is_curr_in_delayslot,
input wire input_is_next_in_delayslot,
input wire[`REGS_DATA_BUS] id_instruction,
output reg[`ALU_OPERATOR_BUS] ex_operator,
output reg[`ALU_CATEGORY_BUS] ex_category,
output reg[`REGS_DATA_BUS] ex_operand1,
output reg[`REGS_DATA_BUS] ex_operand2,
output reg[`REGS_ADDR_BUS] ex_write_addr,
output reg ex_write_enable,
output reg[`REGS_DATA_BUS] ex_return_target,
output reg ex_is_curr_in_delayslot,
output reg is_curr_in_delayslot,
output reg[`REGS_DATA_BUS] ex_instruction
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
ex_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but I used 0
ex_category <= 0; // FIXME: EXE_RES_NOP should be used here, but I used 0
ex_operand1 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but I used 0
ex_write_enable <= `DISABLE;
ex_return_target <= 0; // FIXME: NOPRegAddr should be used here, but I used 0
ex_is_curr_in_delayslot <= `FALSE;
is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
end else if (stall[2] == `ENABLE && stall[3] == `DISABLE) begin
ex_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but I used 0
ex_category <= 0; // FIXME: EXE_RES_NOP should be used here, but I used 0
ex_operand1 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
ex_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but I used 0
ex_write_enable <= `DISABLE;
ex_return_target <= 0;
ex_is_curr_in_delayslot <= `FALSE;
ex_instruction <= 0; // FIXME: ZERO_WORD should be used here, but I used 0
end else if (stall[2] == `DISABLE) begin
ex_operator <= id_operator;
ex_category <= id_category;
ex_operand1 <= id_operand1;
ex_operand2 <= id_operand2;
ex_write_addr <= id_write_addr;
ex_write_enable <= id_write_enable;
ex_return_target <= id_return_target;
ex_is_curr_in_delayslot <= id_is_curr_in_delayslot;
is_curr_in_delayslot <= input_is_next_in_delayslot;
ex_instruction <= id_instruction;
end
end
endmodule // id_ex_buffer
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:53:27 11/22/2016
// Design Name:
// Module Name: number_in
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module number_in(
input [31:0] num_a,
input [31:0] num_b,
input [31:0] result,
input [4:0] code,
input btnm,
output reg [32:0] num_out
);
reg [31:0] new;
reg [6:0] i;
reg [1:0] state;
reg b_state;
parameter [1:0] numA = 2'b00;
parameter [1:0] numB = 2'b01;
parameter [1:0] numC = 2'b10;
initial state = 2'b00;
initial b_state = 0;
always @(*)
begin
if(btnm)
begin
if(~b_state)
begin
b_state = 1;
if(state == numA) //Estado A
begin
if(code > 9 && code < 15) //Cambia estado
begin
state = numB;
end
end
else if(state == numB) //Estado B
begin
if(code == 15) //Cambia estado
begin
state = numC;
end
end
else
begin
if(code == 16) //Cambia estado
begin
state = numA;
end
end
end
end
else
begin
b_state = 0;
end
end
always @(state)
begin
case (state)
numA: new = num_a;
numB: new = num_b;
numC: new = result;
default: new = num_a;
endcase
if(new[31])
begin
for(i = 0; i < 32; i = i + 1)
num_out[i] = ~new[i];
num_out = num_out + 1'b1;
num_out[32] = 1'b1;
end
else
begin
num_out = new;
end
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [3:0] sw,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
/*
* Ethernet: 100BASE-T MII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
input wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_en,
input wire phy_col,
input wire phy_crs,
output wire phy_reset_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// XFCP UART interface
wire [7:0] xfcp_uart_interface_down_tdata;
wire xfcp_uart_interface_down_tvalid;
wire xfcp_uart_interface_down_tready;
wire xfcp_uart_interface_down_tlast;
wire xfcp_uart_interface_down_tuser;
wire [7:0] xfcp_uart_interface_up_tdata;
wire xfcp_uart_interface_up_tvalid;
wire xfcp_uart_interface_up_tready;
wire xfcp_uart_interface_up_tlast;
wire xfcp_uart_interface_up_tuser;
xfcp_interface_uart
xfcp_interface_uart_inst (
.clk(clk),
.rst(rst),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.down_xfcp_in_tdata(xfcp_uart_interface_up_tdata),
.down_xfcp_in_tvalid(xfcp_uart_interface_up_tvalid),
.down_xfcp_in_tready(xfcp_uart_interface_up_tready),
.down_xfcp_in_tlast(xfcp_uart_interface_up_tlast),
.down_xfcp_in_tuser(xfcp_uart_interface_up_tuser),
.down_xfcp_out_tdata(xfcp_uart_interface_down_tdata),
.down_xfcp_out_tvalid(xfcp_uart_interface_down_tvalid),
.down_xfcp_out_tready(xfcp_uart_interface_down_tready),
.down_xfcp_out_tlast(xfcp_uart_interface_down_tlast),
.down_xfcp_out_tuser(xfcp_uart_interface_down_tuser),
.prescale(125000000/(115200*8))
);
// XFCP Ethernet interface
wire [7:0] xfcp_udp_interface_down_tdata;
wire xfcp_udp_interface_down_tvalid;
wire xfcp_udp_interface_down_tready;
wire xfcp_udp_interface_down_tlast;
wire xfcp_udp_interface_down_tuser;
wire [7:0] xfcp_udp_interface_up_tdata;
wire xfcp_udp_interface_up_tvalid;
wire xfcp_udp_interface_up_tready;
wire xfcp_udp_interface_up_tlast;
wire xfcp_udp_interface_up_tuser;
// AXI between MAC and Ethernet modules
wire [7:0] rx_eth_axis_tdata;
wire rx_eth_axis_tvalid;
wire rx_eth_axis_tready;
wire rx_eth_axis_tlast;
wire rx_eth_axis_tuser;
wire [7:0] tx_eth_axis_tdata;
wire tx_eth_axis_tvalid;
wire tx_eth_axis_tready;
wire tx_eth_axis_tlast;
wire tx_eth_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [15:0] local_port = 16'd14000;
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
assign phy_reset_n = ~rst;
assign led = 0;
eth_mac_mii_fifo #(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE("BUFR"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_eth_axis_tdata),
.tx_axis_tvalid(tx_eth_axis_tvalid),
.tx_axis_tready(tx_eth_axis_tready),
.tx_axis_tlast(tx_eth_axis_tlast),
.tx_axis_tuser(tx_eth_axis_tuser),
.rx_axis_tdata(rx_eth_axis_tdata),
.rx_axis_tvalid(rx_eth_axis_tvalid),
.rx_axis_tready(rx_eth_axis_tready),
.rx_axis_tlast(rx_eth_axis_tlast),
.rx_axis_tuser(rx_eth_axis_tuser),
.mii_rx_clk(phy_rx_clk),
.mii_rxd(phy_rxd),
.mii_rx_dv(phy_rx_dv),
.mii_rx_er(phy_rx_er),
.mii_tx_clk(phy_tx_clk),
.mii_txd(phy_txd),
.mii_tx_en(phy_tx_en),
.mii_tx_er(),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(12)
);
xfcp_interface_udp
xfcp_interface_udp_inst (
.clk(clk),
.rst(rst),
.s_eth_axis_tdata(rx_eth_axis_tdata),
.s_eth_axis_tvalid(rx_eth_axis_tvalid),
.s_eth_axis_tready(rx_eth_axis_tready),
.s_eth_axis_tlast(rx_eth_axis_tlast),
.s_eth_axis_tuser(rx_eth_axis_tuser),
.m_eth_axis_tdata(tx_eth_axis_tdata),
.m_eth_axis_tvalid(tx_eth_axis_tvalid),
.m_eth_axis_tready(tx_eth_axis_tready),
.m_eth_axis_tlast(tx_eth_axis_tlast),
.m_eth_axis_tuser(tx_eth_axis_tuser),
.down_xfcp_in_tdata(xfcp_udp_interface_up_tdata),
.down_xfcp_in_tvalid(xfcp_udp_interface_up_tvalid),
.down_xfcp_in_tready(xfcp_udp_interface_up_tready),
.down_xfcp_in_tlast(xfcp_udp_interface_up_tlast),
.down_xfcp_in_tuser(xfcp_udp_interface_up_tuser),
.down_xfcp_out_tdata(xfcp_udp_interface_down_tdata),
.down_xfcp_out_tvalid(xfcp_udp_interface_down_tvalid),
.down_xfcp_out_tready(xfcp_udp_interface_down_tready),
.down_xfcp_out_tlast(xfcp_udp_interface_down_tlast),
.down_xfcp_out_tuser(xfcp_udp_interface_down_tuser),
.local_mac(local_mac),
.local_ip(local_ip),
.local_port(local_port),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask)
);
// XFCP 2x1 switch
wire [7:0] xfcp_interface_switch_down_tdata;
wire xfcp_interface_switch_down_tvalid;
wire xfcp_interface_switch_down_tready;
wire xfcp_interface_switch_down_tlast;
wire xfcp_interface_switch_down_tuser;
wire [7:0] xfcp_interface_switch_up_tdata;
wire xfcp_interface_switch_up_tvalid;
wire xfcp_interface_switch_up_tready;
wire xfcp_interface_switch_up_tlast;
wire xfcp_interface_switch_up_tuser;
xfcp_arb #(
.PORTS(2)
)
xfcp_interface_arb_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata({xfcp_udp_interface_down_tdata, xfcp_uart_interface_down_tdata}),
.up_xfcp_in_tvalid({xfcp_udp_interface_down_tvalid, xfcp_uart_interface_down_tvalid}),
.up_xfcp_in_tready({xfcp_udp_interface_down_tready, xfcp_uart_interface_down_tready}),
.up_xfcp_in_tlast({xfcp_udp_interface_down_tlast, xfcp_uart_interface_down_tlast}),
.up_xfcp_in_tuser({xfcp_udp_interface_down_tuser, xfcp_uart_interface_down_tuser}),
.up_xfcp_out_tdata({xfcp_udp_interface_up_tdata, xfcp_uart_interface_up_tdata}),
.up_xfcp_out_tvalid({xfcp_udp_interface_up_tvalid, xfcp_uart_interface_up_tvalid}),
.up_xfcp_out_tready({xfcp_udp_interface_up_tready, xfcp_uart_interface_up_tready}),
.up_xfcp_out_tlast({xfcp_udp_interface_up_tlast, xfcp_uart_interface_up_tlast}),
.up_xfcp_out_tuser({xfcp_udp_interface_up_tuser, xfcp_uart_interface_up_tuser}),
.down_xfcp_in_tdata(xfcp_interface_switch_up_tdata),
.down_xfcp_in_tvalid(xfcp_interface_switch_up_tvalid),
.down_xfcp_in_tready(xfcp_interface_switch_up_tready),
.down_xfcp_in_tlast(xfcp_interface_switch_up_tlast),
.down_xfcp_in_tuser(xfcp_interface_switch_up_tuser),
.down_xfcp_out_tdata(xfcp_interface_switch_down_tdata),
.down_xfcp_out_tvalid(xfcp_interface_switch_down_tvalid),
.down_xfcp_out_tready(xfcp_interface_switch_down_tready),
.down_xfcp_out_tlast(xfcp_interface_switch_down_tlast),
.down_xfcp_out_tuser(xfcp_interface_switch_down_tuser)
);
// XFCP 1x4 switch
wire [7:0] xfcp_switch_port_0_down_tdata;
wire xfcp_switch_port_0_down_tvalid;
wire xfcp_switch_port_0_down_tready;
wire xfcp_switch_port_0_down_tlast;
wire xfcp_switch_port_0_down_tuser;
wire [7:0] xfcp_switch_port_0_up_tdata;
wire xfcp_switch_port_0_up_tvalid;
wire xfcp_switch_port_0_up_tready;
wire xfcp_switch_port_0_up_tlast;
wire xfcp_switch_port_0_up_tuser;
wire [7:0] xfcp_switch_port_1_down_tdata;
wire xfcp_switch_port_1_down_tvalid;
wire xfcp_switch_port_1_down_tready;
wire xfcp_switch_port_1_down_tlast;
wire xfcp_switch_port_1_down_tuser;
wire [7:0] xfcp_switch_port_1_up_tdata;
wire xfcp_switch_port_1_up_tvalid;
wire xfcp_switch_port_1_up_tready;
wire xfcp_switch_port_1_up_tlast;
wire xfcp_switch_port_1_up_tuser;
wire [7:0] xfcp_switch_port_2_down_tdata;
wire xfcp_switch_port_2_down_tvalid;
wire xfcp_switch_port_2_down_tready;
wire xfcp_switch_port_2_down_tlast;
wire xfcp_switch_port_2_down_tuser;
wire [7:0] xfcp_switch_port_2_up_tdata;
wire xfcp_switch_port_2_up_tvalid;
wire xfcp_switch_port_2_up_tready;
wire xfcp_switch_port_2_up_tlast;
wire xfcp_switch_port_2_up_tuser;
wire [7:0] xfcp_switch_port_3_down_tdata;
wire xfcp_switch_port_3_down_tvalid;
wire xfcp_switch_port_3_down_tready;
wire xfcp_switch_port_3_down_tlast;
wire xfcp_switch_port_3_down_tuser;
wire [7:0] xfcp_switch_port_3_up_tdata;
wire xfcp_switch_port_3_up_tvalid;
wire xfcp_switch_port_3_up_tready;
wire xfcp_switch_port_3_up_tlast;
wire xfcp_switch_port_3_up_tuser;
xfcp_switch #(
.PORTS(4),
.XFCP_ID_TYPE(16'h0100),
.XFCP_ID_STR("XFCP switch"),
.XFCP_EXT_ID(0),
.XFCP_EXT_ID_STR("Arty")
)
xfcp_switch_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_interface_switch_down_tdata),
.up_xfcp_in_tvalid(xfcp_interface_switch_down_tvalid),
.up_xfcp_in_tready(xfcp_interface_switch_down_tready),
.up_xfcp_in_tlast(xfcp_interface_switch_down_tlast),
.up_xfcp_in_tuser(xfcp_interface_switch_down_tuser),
.up_xfcp_out_tdata(xfcp_interface_switch_up_tdata),
.up_xfcp_out_tvalid(xfcp_interface_switch_up_tvalid),
.up_xfcp_out_tready(xfcp_interface_switch_up_tready),
.up_xfcp_out_tlast(xfcp_interface_switch_up_tlast),
.up_xfcp_out_tuser(xfcp_interface_switch_up_tuser),
.down_xfcp_in_tdata( {xfcp_switch_port_3_up_tdata, xfcp_switch_port_2_up_tdata, xfcp_switch_port_1_up_tdata, xfcp_switch_port_0_up_tdata }),
.down_xfcp_in_tvalid( {xfcp_switch_port_3_up_tvalid, xfcp_switch_port_2_up_tvalid, xfcp_switch_port_1_up_tvalid, xfcp_switch_port_0_up_tvalid }),
.down_xfcp_in_tready( {xfcp_switch_port_3_up_tready, xfcp_switch_port_2_up_tready, xfcp_switch_port_1_up_tready, xfcp_switch_port_0_up_tready }),
.down_xfcp_in_tlast( {xfcp_switch_port_3_up_tlast, xfcp_switch_port_2_up_tlast, xfcp_switch_port_1_up_tlast, xfcp_switch_port_0_up_tlast }),
.down_xfcp_in_tuser( {xfcp_switch_port_3_up_tuser, xfcp_switch_port_2_up_tuser, xfcp_switch_port_1_up_tuser, xfcp_switch_port_0_up_tuser }),
.down_xfcp_out_tdata( {xfcp_switch_port_3_down_tdata, xfcp_switch_port_2_down_tdata, xfcp_switch_port_1_down_tdata, xfcp_switch_port_0_down_tdata }),
.down_xfcp_out_tvalid({xfcp_switch_port_3_down_tvalid, xfcp_switch_port_2_down_tvalid, xfcp_switch_port_1_down_tvalid, xfcp_switch_port_0_down_tvalid}),
.down_xfcp_out_tready({xfcp_switch_port_3_down_tready, xfcp_switch_port_2_down_tready, xfcp_switch_port_1_down_tready, xfcp_switch_port_0_down_tready}),
.down_xfcp_out_tlast( {xfcp_switch_port_3_down_tlast, xfcp_switch_port_2_down_tlast, xfcp_switch_port_1_down_tlast, xfcp_switch_port_0_down_tlast }),
.down_xfcp_out_tuser( {xfcp_switch_port_3_down_tuser, xfcp_switch_port_2_down_tuser, xfcp_switch_port_1_down_tuser, xfcp_switch_port_0_down_tuser })
);
// XFCP WB RAM 0
wire [7:0] ram_0_wb_adr_i;
wire [31:0] ram_0_wb_dat_i;
wire [31:0] ram_0_wb_dat_o;
wire ram_0_wb_we_i;
wire [3:0] ram_0_wb_sel_i;
wire ram_0_wb_stb_i;
wire ram_0_wb_ack_o;
wire ram_0_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 0"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_0 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_0_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_0_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_0_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_0_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_0_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_0_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_0_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_0_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_0_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_0_up_tuser),
.wb_adr_o(ram_0_wb_adr_i),
.wb_dat_i(ram_0_wb_dat_o),
.wb_dat_o(ram_0_wb_dat_i),
.wb_we_o(ram_0_wb_we_i),
.wb_sel_o(ram_0_wb_sel_i),
.wb_stb_o(ram_0_wb_stb_i),
.wb_ack_i(ram_0_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_0_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_0_inst (
.clk(clk),
.adr_i(ram_0_wb_adr_i),
.dat_i(ram_0_wb_dat_i),
.dat_o(ram_0_wb_dat_o),
.we_i(ram_0_wb_we_i),
.sel_i(ram_0_wb_sel_i),
.stb_i(ram_0_wb_stb_i),
.ack_o(ram_0_wb_ack_o),
.cyc_i(ram_0_wb_cyc_i)
);
// XFCP WB RAM 1
wire [7:0] ram_1_wb_adr_i;
wire [31:0] ram_1_wb_dat_i;
wire [31:0] ram_1_wb_dat_o;
wire ram_1_wb_we_i;
wire [3:0] ram_1_wb_sel_i;
wire ram_1_wb_stb_i;
wire ram_1_wb_ack_o;
wire ram_1_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 1"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_1 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_1_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_1_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_1_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_1_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_1_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_1_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_1_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_1_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_1_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_1_up_tuser),
.wb_adr_o(ram_1_wb_adr_i),
.wb_dat_i(ram_1_wb_dat_o),
.wb_dat_o(ram_1_wb_dat_i),
.wb_we_o(ram_1_wb_we_i),
.wb_sel_o(ram_1_wb_sel_i),
.wb_stb_o(ram_1_wb_stb_i),
.wb_ack_i(ram_1_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_1_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_1_inst (
.clk(clk),
.adr_i(ram_1_wb_adr_i),
.dat_i(ram_1_wb_dat_i),
.dat_o(ram_1_wb_dat_o),
.we_i(ram_1_wb_we_i),
.sel_i(ram_1_wb_sel_i),
.stb_i(ram_1_wb_stb_i),
.ack_o(ram_1_wb_ack_o),
.cyc_i(ram_1_wb_cyc_i)
);
// XFCP WB RAM 2
wire [7:0] ram_2_wb_adr_i;
wire [31:0] ram_2_wb_dat_i;
wire [31:0] ram_2_wb_dat_o;
wire ram_2_wb_we_i;
wire [3:0] ram_2_wb_sel_i;
wire ram_2_wb_stb_i;
wire ram_2_wb_ack_o;
wire ram_2_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 2"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_2 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_2_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_2_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_2_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_2_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_2_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_2_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_2_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_2_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_2_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_2_up_tuser),
.wb_adr_o(ram_2_wb_adr_i),
.wb_dat_i(ram_2_wb_dat_o),
.wb_dat_o(ram_2_wb_dat_i),
.wb_we_o(ram_2_wb_we_i),
.wb_sel_o(ram_2_wb_sel_i),
.wb_stb_o(ram_2_wb_stb_i),
.wb_ack_i(ram_2_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_2_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_2_inst (
.clk(clk),
.adr_i(ram_2_wb_adr_i),
.dat_i(ram_2_wb_dat_i),
.dat_o(ram_2_wb_dat_o),
.we_i(ram_2_wb_we_i),
.sel_i(ram_2_wb_sel_i),
.stb_i(ram_2_wb_stb_i),
.ack_o(ram_2_wb_ack_o),
.cyc_i(ram_2_wb_cyc_i)
);
// XFCP WB RAM 3
wire [7:0] ram_3_wb_adr_i;
wire [31:0] ram_3_wb_dat_i;
wire [31:0] ram_3_wb_dat_o;
wire ram_3_wb_we_i;
wire [3:0] ram_3_wb_sel_i;
wire ram_3_wb_stb_i;
wire ram_3_wb_ack_o;
wire ram_3_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 3"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_3 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_3_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_3_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_3_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_3_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_3_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_3_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_3_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_3_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_3_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_3_up_tuser),
.wb_adr_o(ram_3_wb_adr_i),
.wb_dat_i(ram_3_wb_dat_o),
.wb_dat_o(ram_3_wb_dat_i),
.wb_we_o(ram_3_wb_we_i),
.wb_sel_o(ram_3_wb_sel_i),
.wb_stb_o(ram_3_wb_stb_i),
.wb_ack_i(ram_3_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_3_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_3_inst (
.clk(clk),
.adr_i(ram_3_wb_adr_i),
.dat_i(ram_3_wb_dat_i),
.dat_o(ram_3_wb_dat_o),
.we_i(ram_3_wb_we_i),
.sel_i(ram_3_wb_sel_i),
.stb_i(ram_3_wb_stb_i),
.ack_o(ram_3_wb_ack_o),
.cyc_i(ram_3_wb_cyc_i)
);
endmodule
|
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
(* DowngradeIPIdentifiedWarnings="yes" *)
(* X_CORE_INFO = "ila,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "system_ila_0_0,ila,{}" *)
(* CORE_GENERATION_INFO = "system_ila_0_0,ila,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=5.0,x_ipLanguage=VERILOG,C_XLNX_HW_PROBE_INFO=NUM_OF_PROBES=4_DATA_DEPTH=1024_PROBE0_WIDTH=1_PROBE0_MU_CNT=1_PROBE1_WIDTH=1_PROBE1_MU_CNT=1_PROBE2_WIDTH=1_PROBE2_MU_CNT=1_PROBE3_WIDTH=1_PROBE3_MU_CNT=1_PROBE4_WIDTH=1_PROBE4_MU_CNT=1_PROBE5_WIDTH=1_PROBE5_MU_CNT=1_PROBE6_WIDTH=1_PROBE6_MU_CNT=1_PROBE7_WIDTH=1_PROBE7_MU_CNT=1_PROBE8_WIDTH=1_PROBE8_MU_CNT=1_PROBE9_WIDTH=1_PROBE9_MU_CNT=1_PROBE10_WIDTH=1_PROBE10_MU_CNT=1_PROBE11_WIDTH=1_PROBE11_MU_CNT=1_PROBE12_WIDTH=1_PROBE12_MU_CNT=1_PROBE13_WIDTH=1_PROBE13_MU_CNT=1_PROBE14_WIDTH=1_PROBE14_MU_CNT=1_PROBE15_WIDTH=1_PROBE15_MU_CNT=1_PROBE16_WIDTH=1_PROBE16_MU_CNT=1_PROBE17_WIDTH=1_PROBE17_MU_CNT=1_PROBE18_WIDTH=1_PROBE18_MU_CNT=1_PROBE19_WIDTH=1_PROBE19_MU_CNT=1_PROBE20_WIDTH=1_PROBE20_MU_CNT=1_PROBE21_WIDTH=1_PROBE21_MU_CNT=1_PROBE22_WIDTH=1_PROBE22_MU_CNT=1_PROBE23_WIDTH=1_PROBE23_MU_CNT=1_PROBE24_WIDTH=1_PROBE24_MU_CNT=1_PROBE25_WIDTH=1_PROBE25_MU_CNT=1_PROBE26_WIDTH=1_PROBE26_MU_CNT=1_PROBE27_WIDTH=1_PROBE27_MU_CNT=1_PROBE28_WIDTH=1_PROBE28_MU_CNT=1_PROBE29_WIDTH=1_PROBE29_MU_CNT=1_PROBE30_WIDTH=1_PROBE30_MU_CNT=1_PROBE31_WIDTH=1_PROBE31_MU_CNT=1_PROBE32_WIDTH=1_PROBE32_MU_CNT=1_PROBE33_WIDTH=1_PROBE33_MU_CNT=1_PROBE34_WIDTH=1_PROBE34_MU_CNT=1_PROBE35_WIDTH=1_PROBE35_MU_CNT=1_PROBE36_WIDTH=1_PROBE36_MU_CNT=1_PROBE37_WIDTH=1_PROBE37_MU_CNT=1_PROBE38_WIDTH=1_PROBE38_MU_CNT=1_PROBE39_WIDTH=1_PROBE39_MU_CNT=1_PROBE40_WIDTH=1_PROBE40_MU_CNT=1_PROBE41_WIDTH=1_PROBE41_MU_CNT=1_PROBE42_WIDTH=1_PROBE42_MU_CNT=1_PROBE43_WIDTH=1_PROBE43_MU_CNT=1_PROBE44_WIDTH=1_PROBE44_MU_CNT=1_PROBE45_WIDTH=1_PROBE45_MU_CNT=1_PROBE46_WIDTH=1_PROBE46_MU_CNT=1_PROBE47_WIDTH=1_PROBE47_MU_CNT=1_PROBE48_WIDTH=1_PROBE48_MU_CNT=1_PROBE49_WIDTH=1_PROBE49_MU_CNT=1_PROBE50_WIDTH=1_PROBE50_MU_CNT=1_PROBE51_WIDTH=1_PROBE51_MU_CNT=1_PROBE52_WIDTH=1_PROBE52_MU_CNT=1_PROBE53_WIDTH=1_PROBE53_MU_CNT=1_PROBE54_WIDTH=1_PROBE54_MU_CNT=1_PROBE55_WIDTH=1_PROBE55_MU_CNT=1_PROBE56_WIDTH=1_PROBE56_MU_CNT=1_PROBE57_WIDTH=1_PROBE57_MU_CNT=1_PROBE58_WIDTH=1_PROBE58_MU_CNT=1_PROBE59_WIDTH=1_PROBE59_MU_CNT=1_PROBE60_WIDTH=1_PROBE60_MU_CNT=1_PROBE61_WIDTH=1_PROBE61_MU_CNT=1_PROBE62_WIDTH=1_PROBE62_MU_CNT=1_PROBE63_WIDTH=1_PROBE63_MU_CNT=1_PROBE64_WIDTH=1_PROBE64_MU_CNT=1_PROBE65_WIDTH=1_PROBE65_MU_CNT=1_PROBE66_WIDTH=1_PROBE66_MU_CNT=1_PROBE67_WIDTH=1_PROBE67_MU_CNT=1_PROBE68_WIDTH=1_PROBE68_MU_CNT=1_PROBE69_WIDTH=1_PROBE69_MU_CNT=1_PROBE70_WIDTH=1_PROBE70_MU_CNT=1_PROBE71_WIDTH=1_PROBE71_MU_CNT=1_PROBE72_WIDTH=1_PROBE72_MU_CNT=1_PROBE73_WIDTH=1_PROBE73_MU_CNT=1_PROBE74_WIDTH=1_PROBE74_MU_CNT=1_PROBE75_WIDTH=1_PROBE75_MU_CNT=1_PROBE76_WIDTH=1_PROBE76_MU_CNT=1_PROBE77_WIDTH=1_PROBE77_MU_CNT=1_PROBE78_WIDTH=1_PROBE78_MU_CNT=1_PROBE79_WIDTH=1_PROBE79_MU_CNT=1_PROBE80_WIDTH=1_PROBE80_MU_CNT=1_PROBE81_WIDTH=1_PROBE81_MU_CNT=1_PROBE82_WIDTH=1_PROBE82_MU_CNT=1_PROBE83_WIDTH=1_PROBE83_MU_CNT=1_PROBE84_WIDTH=1_PROBE84_MU_CNT=1_PROBE85_WIDTH=1_PROBE85_MU_CNT=1_PROBE86_WIDTH=1_PROBE86_MU_CNT=1_PROBE87_WIDTH=1_PROBE87_MU_CNT=1_PROBE88_WIDTH=1_PROBE88_MU_CNT=1_PROBE89_WIDTH=1_PROBE89_MU_CNT=1_PROBE90_WIDTH=1_PROBE90_MU_CNT=1_PROBE91_WIDTH=1_PROBE91_MU_CNT=1_PROBE92_WIDTH=1_PROBE92_MU_CNT=1_PROBE93_WIDTH=1_PROBE93_MU_CNT=1_PROBE94_WIDTH=1_PROBE94_MU_CNT=1_PROBE95_WIDTH=1_PROBE95_MU_CNT=1_PROBE96_WIDTH=1_PROBE96_MU_CNT=1_PROBE97_WIDTH=1_PROBE97_MU_CNT=1_PROBE98_WIDTH=1_PROBE98_MU_CNT=1_PROBE99_WIDTH=1_PROBE99_MU_CNT=1_PROBE100_WIDTH=1_PROBE100_MU_CNT=1_PROBE101_WIDTH=1_PROBE101_MU_CNT=1_PROBE102_WIDTH=1_PROBE102_MU_CNT=1_PROBE103_WIDTH=1_PROBE103_MU_CNT=1_PROBE104_WIDTH=1_PROBE104_MU_CNT=1_PROBE105_WIDTH=1_PROBE105_MU_CNT=1_PROBE106_WIDTH=1_PROBE106_MU_CNT=1_PROBE107_WIDTH=1_PROBE107_MU_CNT=1_PROBE108_WIDTH=1_PROBE108_MU_CNT=1_PROBE109_WIDTH=1_PROBE109_MU_CNT=1_PROBE110_WIDTH=1_PROBE110_MU_CNT=1_PROBE111_WIDTH=1_PROBE111_MU_CNT=1_PROBE112_WIDTH=1_PROBE112_MU_CNT=1_PROBE113_WIDTH=1_PROBE113_MU_CNT=1_PROBE114_WIDTH=1_PROBE114_MU_CNT=1_PROBE115_WIDTH=1_PROBE115_MU_CNT=1_PROBE116_WIDTH=1_PROBE116_MU_CNT=1_PROBE117_WIDTH=1_PROBE117_MU_CNT=1_PROBE118_WIDTH=1_PROBE118_MU_CNT=1_PROBE119_WIDTH=1_PROBE119_MU_CNT=1_PROBE120_WIDTH=1_PROBE120_MU_CNT=1_PROBE121_WIDTH=1_PROBE121_MU_CNT=1_PROBE122_WIDTH=1_PROBE122_MU_CNT=1_PROBE123_WIDTH=1_PROBE123_MU_CNT=1_PROBE124_WIDTH=1_PROBE124_MU_CNT=1_PROBE125_WIDTH=1_PROBE125_MU_CNT=1_PROBE126_WIDTH=1_PROBE126_MU_CNT=1_PROBE127_WIDTH=1_PROBE127_MU_CNT=1_PROBE128_WIDTH=1_PROBE128_MU_CNT=1_PROBE129_WIDTH=1_PROBE129_MU_CNT=1_PROBE130_WIDTH=1_PROBE130_MU_CNT=1_PROBE131_WIDTH=1_PROBE131_MU_CNT=1_PROBE132_WIDTH=1_PROBE132_MU_CNT=1_PROBE133_WIDTH=1_PROBE133_MU_CNT=1_PROBE134_WIDTH=1_PROBE134_MU_CNT=1_PROBE135_WIDTH=1_PROBE135_MU_CNT=1_PROBE136_WIDTH=1_PROBE136_MU_CNT=1_PROBE137_WIDTH=1_PROBE137_MU_CNT=1_PROBE138_WIDTH=1_PROBE138_MU_CNT=1_PROBE139_WIDTH=1_PROBE139_MU_CNT=1_PROBE140_WIDTH=1_PROBE140_MU_CNT=1_PROBE141_WIDTH=1_PROBE141_MU_CNT=1_PROBE142_WIDTH=1_PROBE142_MU_CNT=1_PROBE143_WIDTH=1_PROBE143_MU_CNT=1_PROBE144_WIDTH=1_PROBE144_MU_CNT=1_PROBE145_WIDTH=1_PROBE145_MU_CNT=1_PROBE146_WIDTH=1_PROBE146_MU_CNT=1_PROBE147_WIDTH=1_PROBE147_MU_CNT=1_PROBE148_WIDTH=1_PROBE148_MU_CNT=1_PROBE149_WIDTH=1_PROBE149_MU_CNT=1_PROBE150_WIDTH=1_PROBE150_MU_CNT=1_PROBE151_WIDTH=1_PROBE151_MU_CNT=1_PROBE152_WIDTH=1_PROBE152_MU_CNT=1_PROBE153_WIDTH=1_PROBE153_MU_CNT=1_PROBE154_WIDTH=1_PROBE154_MU_CNT=1_PROBE155_WIDTH=1_PROBE155_MU_CNT=1_PROBE156_WIDTH=1_PROBE156_MU_CNT=1_PROBE157_WIDTH=1_PROBE157_MU_CNT=1_PROBE158_WIDTH=1_PROBE158_MU_CNT=1_PROBE159_WIDTH=1_PROBE159_MU_CNT=1_PROBE160_WIDTH=1_PROBE160_MU_CNT=1_PROBE161_WIDTH=1_PROBE161_MU_CNT=1_PROBE162_WIDTH=1_PROBE162_MU_CNT=1_PROBE163_WIDTH=1_PROBE163_MU_CNT=1_PROBE164_WIDTH=1_PROBE164_MU_CNT=1_PROBE165_WIDTH=1_PROBE165_MU_CNT=1_PROBE166_WIDTH=1_PROBE166_MU_CNT=1_PROBE167_WIDTH=1_PROBE167_MU_CNT=1_PROBE168_WIDTH=1_PROBE168_MU_CNT=1_PROBE169_WIDTH=1_PROBE169_MU_CNT=1_PROBE170_WIDTH=1_PROBE170_MU_CNT=1_PROBE171_WIDTH=1_PROBE171_MU_CNT=1_PROBE172_WIDTH=1_PROBE172_MU_CNT=1_PROBE173_WIDTH=1_PROBE173_MU_CNT=1_PROBE174_WIDTH=1_PROBE174_MU_CNT=1_PROBE175_WIDTH=1_PROBE175_MU_CNT=1_PROBE176_WIDTH=1_PROBE176_MU_CNT=1_PROBE177_WIDTH=1_PROBE177_MU_CNT=1_PROBE178_WIDTH=1_PROBE178_MU_CNT=1_PROBE179_WIDTH=1_PROBE179_MU_CNT=1_PROBE180_WIDTH=1_PROBE180_MU_CNT=1_PROBE181_WIDTH=1_PROBE181_MU_CNT=1_PROBE182_WIDTH=1_PROBE182_MU_CNT=1_PROBE183_WIDTH=1_PROBE183_MU_CNT=1_PROBE184_WIDTH=1_PROBE184_MU_CNT=1_PROBE185_WIDTH=1_PROBE185_MU_CNT=1_PROBE186_WIDTH=1_PROBE186_MU_CNT=1_PROBE187_WIDTH=1_PROBE187_MU_CNT=1_PROBE188_WIDTH=1_PROBE188_MU_CNT=1_PROBE189_WIDTH=1_PROBE189_MU_CNT=1_PROBE190_WIDTH=1_PROBE190_MU_CNT=1_PROBE191_WIDTH=1_PROBE191_MU_CNT=1_PROBE192_WIDTH=1_PROBE192_MU_CNT=1_PROBE193_WIDTH=1_PROBE193_MU_CNT=1_PROBE194_WIDTH=1_PROBE194_MU_CNT=1_PROBE195_WIDTH=1_PROBE195_MU_CNT=1_PROBE196_WIDTH=1_PROBE196_MU_CNT=1_PROBE197_WIDTH=1_PROBE197_MU_CNT=1_PROBE198_WIDTH=1_PROBE198_MU_CNT=1_PROBE199_WIDTH=1_PROBE199_MU_CNT=1_PROBE200_WIDTH=1_PROBE200_MU_CNT=1_PROBE201_WIDTH=1_PROBE201_MU_CNT=1_PROBE202_WIDTH=1_PROBE202_MU_CNT=1_PROBE203_WIDTH=1_PROBE203_MU_CNT=1_PROBE204_WIDTH=1_PROBE204_MU_CNT=1_PROBE205_WIDTH=1_PROBE205_MU_CNT=1_PROBE206_WIDTH=1_PROBE206_MU_CNT=1_PROBE207_WIDTH=1_PROBE207_MU_CNT=1_PROBE208_WIDTH=1_PROBE208_MU_CNT=1_PROBE209_WIDTH=1_PROBE209_MU_CNT=1_PROBE210_WIDTH=1_PROBE210_MU_CNT=1_PROBE211_WIDTH=1_PROBE211_MU_CNT=1_PROBE212_WIDTH=1_PROBE212_MU_CNT=1_PROBE213_WIDTH=1_PROBE213_MU_CNT=1_PROBE214_WIDTH=1_PROBE214_MU_CNT=1_PROBE215_WIDTH=1_PROBE215_MU_CNT=1_PROBE216_WIDTH=1_PROBE216_MU_CNT=1_PROBE217_WIDTH=1_PROBE217_MU_CNT=1_PROBE218_WIDTH=1_PROBE218_MU_CNT=1_PROBE219_WIDTH=1_PROBE219_MU_CNT=1_PROBE220_WIDTH=1_PROBE220_MU_CNT=1_PROBE221_WIDTH=1_PROBE221_MU_CNT=1_PROBE222_WIDTH=1_PROBE222_MU_CNT=1_PROBE223_WIDTH=1_PROBE223_MU_CNT=1_PROBE224_WIDTH=1_PROBE224_MU_CNT=1_PROBE225_WIDTH=1_PROBE225_MU_CNT=1_PROBE226_WIDTH=1_PROBE226_MU_CNT=1_PROBE227_WIDTH=1_PROBE227_MU_CNT=1_PROBE228_WIDTH=1_PROBE228_MU_CNT=1_PROBE229_WIDTH=1_PROBE229_MU_CNT=1_PROBE230_WIDTH=1_PROBE230_MU_CNT=1_PROBE231_WIDTH=1_PROBE231_MU_CNT=1_PROBE232_WIDTH=1_PROBE232_MU_CNT=1_PROBE233_WIDTH=1_PROBE233_MU_CNT=1_PROBE234_WIDTH=1_PROBE234_MU_CNT=1_PROBE235_WIDTH=1_PROBE235_MU_CNT=1_PROBE236_WIDTH=1_PROBE236_MU_CNT=1_PROBE237_WIDTH=1_PROBE237_MU_CNT=1_PROBE238_WIDTH=1_PROBE238_MU_CNT=1_PROBE239_WIDTH=1_PROBE239_MU_CNT=1_PROBE240_WIDTH=1_PROBE240_MU_CNT=1_PROBE241_WIDTH=1_PROBE241_MU_CNT=1_PROBE242_WIDTH=1_PROBE242_MU_CNT=1_PROBE243_WIDTH=1_PROBE243_MU_CNT=1_PROBE244_WIDTH=1_PROBE244_MU_CNT=1_PROBE245_WIDTH=1_PROBE245_MU_CNT=1_PROBE246_WIDTH=1_PROBE246_MU_CNT=1_PROBE247_WIDTH=1_PROBE247_MU_CNT=1_PROBE248_WIDTH=1_PROBE248_MU_CNT=1_PROBE249_WIDTH=1_PROBE249_MU_CNT=1_PROBE250_WIDTH=1_PROBE250_MU_CNT=1_PROBE251_WIDTH=1_PROBE251_MU_CNT=1_PROBE252_WIDTH=1_PROBE252_MU_CNT=1_PROBE253_WIDTH=1_PROBE253_MU_CNT=1_PROBE254_WIDTH=1_PROBE254_MU_CNT=1_PROBE255_WIDTH=1_PROBE255_MU_CNT=1_PROBE256_WIDTH=1_PROBE256_MU_CNT=1_PROBE257_WIDTH=1_PROBE257_MU_CNT=1_PROBE258_WIDTH=1_PROBE258_MU_CNT=1_PROBE259_WIDTH=1_PROBE259_MU_CNT=1_PROBE260_WIDTH=1_PROBE260_MU_CNT=1_PROBE261_WIDTH=1_PROBE261_MU_CNT=1_PROBE262_WIDTH=1_PROBE262_MU_CNT=1_PROBE263_WIDTH=1_PROBE263_MU_CNT=1_PROBE264_WIDTH=1_PROBE264_MU_CNT=1_PROBE265_WIDTH=1_PROBE265_MU_CNT=1_PROBE266_WIDTH=1_PROBE266_MU_CNT=1_PROBE267_WIDTH=1_PROBE267_MU_CNT=1_PROBE268_WIDTH=1_PROBE268_MU_CNT=1_PROBE269_WIDTH=1_PROBE269_MU_CNT=1_PROBE270_WIDTH=1_PROBE270_MU_CNT=1_PROBE271_WIDTH=1_PROBE271_MU_CNT=1_PROBE272_WIDTH=1_PROBE272_MU_CNT=1_PROBE273_WIDTH=1_PROBE273_MU_CNT=1_PROBE274_WIDTH=1_PROBE274_MU_CNT=1_PROBE275_WIDTH=1_PROBE275_MU_CNT=1_PROBE276_WIDTH=1_PROBE276_MU_CNT=1_PROBE277_WIDTH=1_PROBE277_MU_CNT=1_PROBE278_WIDTH=1_PROBE278_MU_CNT=1_PROBE279_WIDTH=1_PROBE279_MU_CNT=1_PROBE280_WIDTH=1_PROBE280_MU_CNT=1_PROBE281_WIDTH=1_PROBE281_MU_CNT=1_PROBE282_WIDTH=1_PROBE282_MU_CNT=1_PROBE283_WIDTH=1_PROBE283_MU_CNT=1_PROBE284_WIDTH=1_PROBE284_MU_CNT=1_PROBE285_WIDTH=1_PROBE285_MU_CNT=1_PROBE286_WIDTH=1_PROBE286_MU_CNT=1_PROBE287_WIDTH=1_PROBE287_MU_CNT=1_PROBE288_WIDTH=1_PROBE288_MU_CNT=1_PROBE289_WIDTH=1_PROBE289_MU_CNT=1_PROBE290_WIDTH=1_PROBE290_MU_CNT=1_PROBE291_WIDTH=1_PROBE291_MU_CNT=1_PROBE292_WIDTH=1_PROBE292_MU_CNT=1_PROBE293_WIDTH=1_PROBE293_MU_CNT=1_PROBE294_WIDTH=1_PROBE294_MU_CNT=1_PROBE295_WIDTH=1_PROBE295_MU_CNT=1_PROBE296_WIDTH=1_PROBE296_MU_CNT=1_PROBE297_WIDTH=1_PROBE297_MU_CNT=1_PROBE298_WIDTH=1_PROBE298_MU_CNT=1_PROBE299_WIDTH=1_PROBE299_MU_CNT=1_PROBE300_WIDTH=1_PROBE300_MU_CNT=1_PROBE301_WIDTH=1_PROBE301_MU_CNT=1_PROBE302_WIDTH=1_PROBE302_MU_CNT=1_PROBE303_WIDTH=1_PROBE303_MU_CNT=1_PROBE304_WIDTH=1_PROBE304_MU_CNT=1_PROBE305_WIDTH=1_PROBE305_MU_CNT=1_PROBE306_WIDTH=1_PROBE306_MU_CNT=1_PROBE307_WIDTH=1_PROBE307_MU_CNT=1_PROBE308_WIDTH=1_PROBE308_MU_CNT=1_PROBE309_WIDTH=1_PROBE309_MU_CNT=1_PROBE310_WIDTH=1_PROBE310_MU_CNT=1_PROBE311_WIDTH=1_PROBE311_MU_CNT=1_PROBE312_WIDTH=1_PROBE312_MU_CNT=1_PROBE313_WIDTH=1_PROBE313_MU_CNT=1_PROBE314_WIDTH=1_PROBE314_MU_CNT=1_PROBE315_WIDTH=1_PROBE315_MU_CNT=1_PROBE316_WIDTH=1_PROBE316_MU_CNT=1_PROBE317_WIDTH=1_PROBE317_MU_CNT=1_PROBE318_WIDTH=1_PROBE318_MU_CNT=1_PROBE319_WIDTH=1_PROBE319_MU_CNT=1_PROBE320_WIDTH=1_PROBE320_MU_CNT=1_PROBE321_WIDTH=1_PROBE321_MU_CNT=1_PROBE322_WIDTH=1_PROBE322_MU_CNT=1_PROBE323_WIDTH=1_PROBE323_MU_CNT=1_PROBE324_WIDTH=1_PROBE324_MU_CNT=1_PROBE325_WIDTH=1_PROBE325_MU_CNT=1_PROBE326_WIDTH=1_PROBE326_MU_CNT=1_PROBE327_WIDTH=1_PROBE327_MU_CNT=1_PROBE328_WIDTH=1_PROBE328_MU_CNT=1_PROBE329_WIDTH=1_PROBE329_MU_CNT=1_PROBE330_WIDTH=1_PROBE330_MU_CNT=1_PROBE331_WIDTH=1_PROBE331_MU_CNT=1_PROBE332_WIDTH=1_PROBE332_MU_CNT=1_PROBE333_WIDTH=1_PROBE333_MU_CNT=1_PROBE334_WIDTH=1_PROBE334_MU_CNT=1_PROBE335_WIDTH=1_PROBE335_MU_CNT=1_PROBE336_WIDTH=1_PROBE336_MU_CNT=1_PROBE337_WIDTH=1_PROBE337_MU_CNT=1_PROBE338_WIDTH=1_PROBE338_MU_CNT=1_PROBE339_WIDTH=1_PROBE339_MU_CNT=1_PROBE340_WIDTH=1_PROBE340_MU_CNT=1_PROBE341_WIDTH=1_PROBE341_MU_CNT=1_PROBE342_WIDTH=1_PROBE342_MU_CNT=1_PROBE343_WIDTH=1_PROBE343_MU_CNT=1_PROBE344_WIDTH=1_PROBE344_MU_CNT=1_PROBE345_WIDTH=1_PROBE345_MU_CNT=1_PROBE346_WIDTH=1_PROBE346_MU_CNT=1_PROBE347_WIDTH=1_PROBE347_MU_CNT=1_PROBE348_WIDTH=1_PROBE348_MU_CNT=1_PROBE349_WIDTH=1_PROBE349_MU_CNT=1_PROBE350_WIDTH=1_PROBE350_MU_CNT=1_PROBE351_WIDTH=1_PROBE351_MU_CNT=1_PROBE352_WIDTH=1_PROBE352_MU_CNT=1_PROBE353_WIDTH=1_PROBE353_MU_CNT=1_PROBE354_WIDTH=1_PROBE354_MU_CNT=1_PROBE355_WIDTH=1_PROBE355_MU_CNT=1_PROBE356_WIDTH=1_PROBE356_MU_CNT=1_PROBE357_WIDTH=1_PROBE357_MU_CNT=1_PROBE358_WIDTH=1_PROBE358_MU_CNT=1_PROBE359_WIDTH=1_PROBE359_MU_CNT=1_PROBE360_WIDTH=1_PROBE360_MU_CNT=1_PROBE361_WIDTH=1_PROBE361_MU_CNT=1_PROBE362_WIDTH=1_PROBE362_MU_CNT=1_PROBE363_WIDTH=1_PROBE363_MU_CNT=1_PROBE364_WIDTH=1_PROBE364_MU_CNT=1_PROBE365_WIDTH=1_PROBE365_MU_CNT=1_PROBE366_WIDTH=1_PROBE366_MU_CNT=1_PROBE367_WIDTH=1_PROBE367_MU_CNT=1_PROBE368_WIDTH=1_PROBE368_MU_CNT=1_PROBE369_WIDTH=1_PROBE369_MU_CNT=1_PROBE370_WIDTH=1_PROBE370_MU_CNT=1_PROBE371_WIDTH=1_PROBE371_MU_CNT=1_PROBE372_WIDTH=1_PROBE372_MU_CNT=1_PROBE373_WIDTH=1_PROBE373_MU_CNT=1_PROBE374_WIDTH=1_PROBE374_MU_CNT=1_PROBE375_WIDTH=1_PROBE375_MU_CNT=1_PROBE376_WIDTH=1_PROBE376_MU_CNT=1_PROBE377_WIDTH=1_PROBE377_MU_CNT=1_PROBE378_WIDTH=1_PROBE378_MU_CNT=1_PROBE379_WIDTH=1_PROBE379_MU_CNT=1_PROBE380_WIDTH=1_PROBE380_MU_CNT=1_PROBE381_WIDTH=1_PROBE381_MU_CNT=1_PROBE382_WIDTH=1_PROBE382_MU_CNT=1_PROBE383_WIDTH=1_PROBE383_MU_CNT=1_PROBE384_WIDTH=1_PROBE384_MU_CNT=1_PROBE385_WIDTH=1_PROBE385_MU_CNT=1_PROBE386_WIDTH=1_PROBE386_MU_CNT=1_PROBE387_WIDTH=1_PROBE387_MU_CNT=1_PROBE388_WIDTH=1_PROBE388_MU_CNT=1_PROBE389_WIDTH=1_PROBE389_MU_CNT=1_PROBE390_WIDTH=1_PROBE390_MU_CNT=1_PROBE391_WIDTH=1_PROBE391_MU_CNT=1_PROBE392_WIDTH=1_PROBE392_MU_CNT=1_PROBE393_WIDTH=1_PROBE393_MU_CNT=1_PROBE394_WIDTH=1_PROBE394_MU_CNT=1_PROBE395_WIDTH=1_PROBE395_MU_CNT=1_PROBE396_WIDTH=1_PROBE396_MU_CNT=1_PROBE397_WIDTH=1_PROBE397_MU_CNT=1_PROBE398_WIDTH=1_PROBE398_MU_CNT=1_PROBE399_WIDTH=1_PROBE399_MU_CNT=1_PROBE400_WIDTH=1_PROBE400_MU_CNT=1_PROBE401_WIDTH=1_PROBE401_MU_CNT=1_PROBE402_WIDTH=1_PROBE402_MU_CNT=1_PROBE403_WIDTH=1_PROBE403_MU_CNT=1_PROBE404_WIDTH=1_PROBE404_MU_CNT=1_PROBE405_WIDTH=1_PROBE405_MU_CNT=1_PROBE406_WIDTH=1_PROBE406_MU_CNT=1_PROBE407_WIDTH=1_PROBE407_MU_CNT=1_PROBE408_WIDTH=1_PROBE408_MU_CNT=1_PROBE409_WIDTH=1_PROBE409_MU_CNT=1_PROBE410_WIDTH=1_PROBE410_MU_CNT=1_PROBE411_WIDTH=1_PROBE411_MU_CNT=1_PROBE412_WIDTH=1_PROBE412_MU_CNT=1_PROBE413_WIDTH=1_PROBE413_MU_CNT=1_PROBE414_WIDTH=1_PROBE414_MU_CNT=1_PROBE415_WIDTH=1_PROBE415_MU_CNT=1_PROBE416_WIDTH=1_PROBE416_MU_CNT=1_PROBE417_WIDTH=1_PROBE417_MU_CNT=1_PROBE418_WIDTH=1_PROBE418_MU_CNT=1_PROBE419_WIDTH=1_PROBE419_MU_CNT=1_PROBE420_WIDTH=1_PROBE420_MU_CNT=1_PROBE421_WIDTH=1_PROBE421_MU_CNT=1_PROBE422_WIDTH=1_PROBE422_MU_CNT=1_PROBE423_WIDTH=1_PROBE423_MU_CNT=1_PROBE424_WIDTH=1_PROBE424_MU_CNT=1_PROBE425_WIDTH=1_PROBE425_MU_CNT=1_PROBE426_WIDTH=1_PROBE426_MU_CNT=1_PROBE427_WIDTH=1_PROBE427_MU_CNT=1_PROBE428_WIDTH=1_PROBE428_MU_CNT=1_PROBE429_WIDTH=1_PROBE429_MU_CNT=1_PROBE430_WIDTH=1_PROBE430_MU_CNT=1_PROBE431_WIDTH=1_PROBE431_MU_CNT=1_PROBE432_WIDTH=1_PROBE432_MU_CNT=1_PROBE433_WIDTH=1_PROBE433_MU_CNT=1_PROBE434_WIDTH=1_PROBE434_MU_CNT=1_PROBE435_WIDTH=1_PROBE435_MU_CNT=1_PROBE436_WIDTH=1_PROBE436_MU_CNT=1_PROBE437_WIDTH=1_PROBE437_MU_CNT=1_PROBE438_WIDTH=1_PROBE438_MU_CNT=1_PROBE439_WIDTH=1_PROBE439_MU_CNT=1_PROBE440_WIDTH=1_PROBE440_MU_CNT=1_PROBE441_WIDTH=1_PROBE441_MU_CNT=1_PROBE442_WIDTH=1_PROBE442_MU_CNT=1_PROBE443_WIDTH=1_PROBE443_MU_CNT=1_PROBE444_WIDTH=1_PROBE444_MU_CNT=1_PROBE445_WIDTH=1_PROBE445_MU_CNT=1_PROBE446_WIDTH=1_PROBE446_MU_CNT=1_PROBE447_WIDTH=1_PROBE447_MU_CNT=1_PROBE448_WIDTH=1_PROBE448_MU_CNT=1_PROBE449_WIDTH=1_PROBE449_MU_CNT=1_PROBE450_WIDTH=1_PROBE450_MU_CNT=1_PROBE451_WIDTH=1_PROBE451_MU_CNT=1_PROBE452_WIDTH=1_PROBE452_MU_CNT=1_PROBE453_WIDTH=1_PROBE453_MU_CNT=1_PROBE454_WIDTH=1_PROBE454_MU_CNT=1_PROBE455_WIDTH=1_PROBE455_MU_CNT=1_PROBE456_WIDTH=1_PROBE456_MU_CNT=1_PROBE457_WIDTH=1_PROBE457_MU_CNT=1_PROBE458_WIDTH=1_PROBE458_MU_CNT=1_PROBE459_WIDTH=1_PROBE459_MU_CNT=1_PROBE460_WIDTH=1_PROBE460_MU_CNT=1_PROBE461_WIDTH=1_PROBE461_MU_CNT=1_PROBE462_WIDTH=1_PROBE462_MU_CNT=1_PROBE463_WIDTH=1_PROBE463_MU_CNT=1_PROBE464_WIDTH=1_PROBE464_MU_CNT=1_PROBE465_WIDTH=1_PROBE465_MU_CNT=1_PROBE466_WIDTH=1_PROBE466_MU_CNT=1_PROBE467_WIDTH=1_PROBE467_MU_CNT=1_PROBE468_WIDTH=1_PROBE468_MU_CNT=1_PROBE469_WIDTH=1_PROBE469_MU_CNT=1_PROBE470_WIDTH=1_PROBE470_MU_CNT=1_PROBE471_WIDTH=1_PROBE471_MU_CNT=1_PROBE472_WIDTH=1_PROBE472_MU_CNT=1_PROBE473_WIDTH=1_PROBE473_MU_CNT=1_PROBE474_WIDTH=1_PROBE474_MU_CNT=1_PROBE475_WIDTH=1_PROBE475_MU_CNT=1_PROBE476_WIDTH=1_PROBE476_MU_CNT=1_PROBE477_WIDTH=1_PROBE477_MU_CNT=1_PROBE478_WIDTH=1_PROBE478_MU_CNT=1_PROBE479_WIDTH=1_PROBE479_MU_CNT=1_PROBE480_WIDTH=1_PROBE480_MU_CNT=1_PROBE481_WIDTH=1_PROBE481_MU_CNT=1_PROBE482_WIDTH=1_PROBE482_MU_CNT=1_PROBE483_WIDTH=1_PROBE483_MU_CNT=1_PROBE484_WIDTH=1_PROBE484_MU_CNT=1_PROBE485_WIDTH=1_PROBE485_MU_CNT=1_PROBE486_WIDTH=1_PROBE486_MU_CNT=1_PROBE487_WIDTH=1_PROBE487_MU_CNT=1_PROBE488_WIDTH=1_PROBE488_MU_CNT=1_PROBE489_WIDTH=1_PROBE489_MU_CNT=1_PROBE490_WIDTH=1_PROBE490_MU_CNT=1_PROBE491_WIDTH=1_PROBE491_MU_CNT=1_PROBE492_WIDTH=1_PROBE492_MU_CNT=1_PROBE493_WIDTH=1_PROBE493_MU_CNT=1_PROBE494_WIDTH=1_PROBE494_MU_CNT=1_PROBE495_WIDTH=1_PROBE495_MU_CNT=1_PROBE496_WIDTH=1_PROBE496_MU_CNT=1_PROBE497_WIDTH=1_PROBE497_MU_CNT=1_PROBE498_WIDTH=1_PROBE498_MU_CNT=1_PROBE499_WIDTH=1_PROBE499_MU_CNT=1_PROBE500_WIDTH=1_PROBE500_MU_CNT=1_PROBE501_WIDTH=1_PROBE501_MU_CNT=1_PROBE502_WIDTH=1_PROBE502_MU_CNT=1_PROBE503_WIDTH=1_PROBE503_MU_CNT=1_PROBE504_WIDTH=1_PROBE504_MU_CNT=1_PROBE505_WIDTH=1_PROBE505_MU_CNT=1_PROBE506_WIDTH=1_PROBE506_MU_CNT=1_PROBE507_WIDTH=1_PROBE507_MU_CNT=1_PROBE508_WIDTH=1_PROBE508_MU_CNT=1_PROBE509_WIDTH=1_PROBE509_MU_CNT=1_PROBE510_WIDTH=1_PROBE510_MU_CNT=1_PROBE511_WIDTH=1_PROBE511_MU_CNT=1_PROBE512_WIDTH=1_PROBE512_MU_CNT=1_PROBE513_WIDTH=1_PROBE513_MU_CNT=1_PROBE514_WIDTH=1_PROBE514_MU_CNT=1_PROBE515_WIDTH=1_PROBE515_MU_CNT=1_PROBE516_WIDTH=1_PROBE516_MU_CNT=1_PROBE517_WIDTH=1_PROBE517_MU_CNT=1_PROBE518_WIDTH=1_PROBE518_MU_CNT=1_PROBE519_WIDTH=1_PROBE519_MU_CNT=1_PROBE520_WIDTH=1_PROBE520_MU_CNT=1_PROBE521_WIDTH=1_PROBE521_MU_CNT=1_PROBE522_WIDTH=1_PROBE522_MU_CNT=1_PROBE523_WIDTH=1_PROBE523_MU_CNT=1_PROBE524_WIDTH=1_PROBE524_MU_CNT=1_PROBE525_WIDTH=1_PROBE525_MU_CNT=1_PROBE526_WIDTH=1_PROBE526_MU_CNT=1_PROBE527_WIDTH=1_PROBE527_MU_CNT=1_PROBE528_WIDTH=1_PROBE528_MU_CNT=1_PROBE529_WIDTH=1_PROBE529_MU_CNT=1_PROBE530_WIDTH=1_PROBE530_MU_CNT=1_PROBE531_WIDTH=1_PROBE531_MU_CNT=1_PROBE532_WIDTH=1_PROBE532_MU_CNT=1_PROBE533_WIDTH=1_PROBE533_MU_CNT=1_PROBE534_WIDTH=1_PROBE534_MU_CNT=1_PROBE535_WIDTH=1_PROBE535_MU_CNT=1_PROBE536_WIDTH=1_PROBE536_MU_CNT=1_PROBE537_WIDTH=1_PROBE537_MU_CNT=1_PROBE538_WIDTH=1_PROBE538_MU_CNT=1_PROBE539_WIDTH=1_PROBE539_MU_CNT=1_PROBE540_WIDTH=1_PROBE540_MU_CNT=1_PROBE541_WIDTH=1_PROBE541_MU_CNT=1_PROBE542_WIDTH=1_PROBE542_MU_CNT=1_PROBE543_WIDTH=1_PROBE543_MU_CNT=1_PROBE544_WIDTH=1_PROBE544_MU_CNT=1_PROBE545_WIDTH=1_PROBE545_MU_CNT=1_PROBE546_WIDTH=1_PROBE546_MU_CNT=1_PROBE547_WIDTH=1_PROBE547_MU_CNT=1_PROBE548_WIDTH=1_PROBE548_MU_CNT=1_PROBE549_WIDTH=1_PROBE549_MU_CNT=1_PROBE550_WIDTH=1_PROBE550_MU_CNT=1_PROBE551_WIDTH=1_PROBE551_MU_CNT=1_PROBE552_WIDTH=1_PROBE552_MU_CNT=1_PROBE553_WIDTH=1_PROBE553_MU_CNT=1_PROBE554_WIDTH=1_PROBE554_MU_CNT=1_PROBE555_WIDTH=1_PROBE555_MU_CNT=1_PROBE556_WIDTH=1_PROBE556_MU_CNT=1_PROBE557_WIDTH=1_PROBE557_MU_CNT=1_PROBE558_WIDTH=1_PROBE558_MU_CNT=1_PROBE559_WIDTH=1_PROBE559_MU_CNT=1_PROBE560_WIDTH=1_PROBE560_MU_CNT=1_PROBE561_WIDTH=1_PROBE561_MU_CNT=1_PROBE562_WIDTH=1_PROBE562_MU_CNT=1_PROBE563_WIDTH=1_PROBE563_MU_CNT=1_PROBE564_WIDTH=1_PROBE564_MU_CNT=1_PROBE565_WIDTH=1_PROBE565_MU_CNT=1_PROBE566_WIDTH=1_PROBE566_MU_CNT=1_PROBE567_WIDTH=1_PROBE567_MU_CNT=1_PROBE568_WIDTH=1_PROBE568_MU_CNT=1_PROBE569_WIDTH=1_PROBE569_MU_CNT=1_PROBE570_WIDTH=1_PROBE570_MU_CNT=1_PROBE571_WIDTH=1_PROBE571_MU_CNT=1_PROBE572_WIDTH=1_PROBE572_MU_CNT=1_PROBE573_WIDTH=1_PROBE573_MU_CNT=1_PROBE574_WIDTH=1_PROBE574_MU_CNT=1_PROBE575_WIDTH=1_PROBE575_MU_CNT=1_PROBE576_WIDTH=1_PROBE576_MU_CNT=1_PROBE577_WIDTH=1_PROBE577_MU_CNT=1_PROBE578_WIDTH=1_PROBE578_MU_CNT=1_PROBE579_WIDTH=1_PROBE579_MU_CNT=1_PROBE580_WIDTH=1_PROBE580_MU_CNT=1_PROBE581_WIDTH=1_PROBE581_MU_CNT=1_PROBE582_WIDTH=1_PROBE582_MU_CNT=1_PROBE583_WIDTH=1_PROBE583_MU_CNT=1_PROBE584_WIDTH=1_PROBE584_MU_CNT=1_PROBE585_WIDTH=1_PROBE585_MU_CNT=1_PROBE586_WIDTH=1_PROBE586_MU_CNT=1_PROBE587_WIDTH=1_PROBE587_MU_CNT=1_PROBE588_WIDTH=1_PROBE588_MU_CNT=1_PROBE589_WIDTH=1_PROBE589_MU_CNT=1_PROBE590_WIDTH=1_PROBE590_MU_CNT=1_PROBE591_WIDTH=1_PROBE591_MU_CNT=1_PROBE592_WIDTH=1_PROBE592_MU_CNT=1_PROBE593_WIDTH=1_PROBE593_MU_CNT=1_PROBE594_WIDTH=1_PROBE594_MU_CNT=1_PROBE595_WIDTH=1_PROBE595_MU_CNT=1_PROBE596_WIDTH=1_PROBE596_MU_CNT=1_PROBE597_WIDTH=1_PROBE597_MU_CNT=1_PROBE598_WIDTH=1_PROBE598_MU_CNT=1_PROBE599_WIDTH=1_PROBE599_MU_CNT=1_PROBE600_WIDTH=1_PROBE600_MU_CNT=1_PROBE601_WIDTH=1_PROBE601_MU_CNT=1_PROBE602_WIDTH=1_PROBE602_MU_CNT=1_PROBE603_WIDTH=1_PROBE603_MU_CNT=1_PROBE604_WIDTH=1_PROBE604_MU_CNT=1_PROBE605_WIDTH=1_PROBE605_MU_CNT=1_PROBE606_WIDTH=1_PROBE606_MU_CNT=1_PROBE607_WIDTH=1_PROBE607_MU_CNT=1_PROBE608_WIDTH=1_PROBE608_MU_CNT=1_PROBE609_WIDTH=1_PROBE609_MU_CNT=1_PROBE610_WIDTH=1_PROBE610_MU_CNT=1_PROBE611_WIDTH=1_PROBE611_MU_CNT=1_PROBE612_WIDTH=1_PROBE612_MU_CNT=1_PROBE613_WIDTH=1_PROBE613_MU_CNT=1_PROBE614_WIDTH=1_PROBE614_MU_CNT=1_PROBE615_WIDTH=1_PROBE615_MU_CNT=1_PROBE616_WIDTH=1_PROBE616_MU_CNT=1_PROBE617_WIDTH=1_PROBE617_MU_CNT=1_PROBE618_WIDTH=1_PROBE618_MU_CNT=1_PROBE619_WIDTH=1_PROBE619_MU_CNT=1_PROBE620_WIDTH=1_PROBE620_MU_CNT=1_PROBE621_WIDTH=1_PROBE621_MU_CNT=1_PROBE622_WIDTH=1_PROBE622_MU_CNT=1_PROBE623_WIDTH=1_PROBE623_MU_CNT=1_PROBE624_WIDTH=1_PROBE624_MU_CNT=1_PROBE625_WIDTH=1_PROBE625_MU_CNT=1_PROBE626_WIDTH=1_PROBE626_MU_CNT=1_PROBE627_WIDTH=1_PROBE627_MU_CNT=1_PROBE628_WIDTH=1_PROBE628_MU_CNT=1_PROBE629_WIDTH=1_PROBE629_MU_CNT=1_PROBE630_WIDTH=1_PROBE630_MU_CNT=1_PROBE631_WIDTH=1_PROBE631_MU_CNT=1_PROBE632_WIDTH=1_PROBE632_MU_CNT=1_PROBE633_WIDTH=1_PROBE633_MU_CNT=1_PROBE634_WIDTH=1_PROBE634_MU_CNT=1_PROBE635_WIDTH=1_PROBE635_MU_CNT=1_PROBE636_WIDTH=1_PROBE636_MU_CNT=1_PROBE637_WIDTH=1_PROBE637_MU_CNT=1_PROBE638_WIDTH=1_PROBE638_MU_CNT=1_PROBE639_WIDTH=1_PROBE639_MU_CNT=1_PROBE640_WIDTH=1_PROBE640_MU_CNT=1_PROBE641_WIDTH=1_PROBE641_MU_CNT=1_PROBE642_WIDTH=1_PROBE642_MU_CNT=1_PROBE643_WIDTH=1_PROBE643_MU_CNT=1_PROBE644_WIDTH=1_PROBE644_MU_CNT=1_PROBE645_WIDTH=1_PROBE645_MU_CNT=1_PROBE646_WIDTH=1_PROBE646_MU_CNT=1_PROBE647_WIDTH=1_PROBE647_MU_CNT=1_PROBE648_WIDTH=1_PROBE648_MU_CNT=1_PROBE649_WIDTH=1_PROBE649_MU_CNT=1_PROBE650_WIDTH=1_PROBE650_MU_CNT=1_PROBE651_WIDTH=1_PROBE651_MU_CNT=1_PROBE652_WIDTH=1_PROBE652_MU_CNT=1_PROBE653_WIDTH=1_PROBE653_MU_CNT=1_PROBE654_WIDTH=1_PROBE654_MU_CNT=1_PROBE655_WIDTH=1_PROBE655_MU_CNT=1_PROBE656_WIDTH=1_PROBE656_MU_CNT=1_PROBE657_WIDTH=1_PROBE657_MU_CNT=1_PROBE658_WIDTH=1_PROBE658_MU_CNT=1_PROBE659_WIDTH=1_PROBE659_MU_CNT=1_PROBE660_WIDTH=1_PROBE660_MU_CNT=1_PROBE661_WIDTH=1_PROBE661_MU_CNT=1_PROBE662_WIDTH=1_PROBE662_MU_CNT=1_PROBE663_WIDTH=1_PROBE663_MU_CNT=1_PROBE664_WIDTH=1_PROBE664_MU_CNT=1_PROBE665_WIDTH=1_PROBE665_MU_CNT=1_PROBE666_WIDTH=1_PROBE666_MU_CNT=1_PROBE667_WIDTH=1_PROBE667_MU_CNT=1_PROBE668_WIDTH=1_PROBE668_MU_CNT=1_PROBE669_WIDTH=1_PROBE669_MU_CNT=1_PROBE670_WIDTH=1_PROBE670_MU_CNT=1_PROBE671_WIDTH=1_PROBE671_MU_CNT=1_PROBE672_WIDTH=1_PROBE672_MU_CNT=1_PROBE673_WIDTH=1_PROBE673_MU_CNT=1_PROBE674_WIDTH=1_PROBE674_MU_CNT=1_PROBE675_WIDTH=1_PROBE675_MU_CNT=1_PROBE676_WIDTH=1_PROBE676_MU_CNT=1_PROBE677_WIDTH=1_PROBE677_MU_CNT=1_PROBE678_WIDTH=1_PROBE678_MU_CNT=1_PROBE679_WIDTH=1_PROBE679_MU_CNT=1_PROBE680_WIDTH=1_PROBE680_MU_CNT=1_PROBE681_WIDTH=1_PROBE681_MU_CNT=1_PROBE682_WIDTH=1_PROBE682_MU_CNT=1_PROBE683_WIDTH=1_PROBE683_MU_CNT=1_PROBE684_WIDTH=1_PROBE684_MU_CNT=1_PROBE685_WIDTH=1_PROBE685_MU_CNT=1_PROBE686_WIDTH=1_PROBE686_MU_CNT=1_PROBE687_WIDTH=1_PROBE687_MU_CNT=1_PROBE688_WIDTH=1_PROBE688_MU_CNT=1_PROBE689_WIDTH=1_PROBE689_MU_CNT=1_PROBE690_WIDTH=1_PROBE690_MU_CNT=1_PROBE691_WIDTH=1_PROBE691_MU_CNT=1_PROBE692_WIDTH=1_PROBE692_MU_CNT=1_PROBE693_WIDTH=1_PROBE693_MU_CNT=1_PROBE694_WIDTH=1_PROBE694_MU_CNT=1_PROBE695_WIDTH=1_PROBE695_MU_CNT=1_PROBE696_WIDTH=1_PROBE696_MU_CNT=1_PROBE697_WIDTH=1_PROBE697_MU_CNT=1_PROBE698_WIDTH=1_PROBE698_MU_CNT=1_PROBE699_WIDTH=1_PROBE699_MU_CNT=1_PROBE700_WIDTH=1_PROBE700_MU_CNT=1_PROBE701_WIDTH=1_PROBE701_MU_CNT=1_PROBE702_WIDTH=1_PROBE702_MU_CNT=1_PROBE703_WIDTH=1_PROBE703_MU_CNT=1_PROBE704_WIDTH=1_PROBE704_MU_CNT=1_PROBE705_WIDTH=1_PROBE705_MU_CNT=1_PROBE706_WIDTH=1_PROBE706_MU_CNT=1_PROBE707_WIDTH=1_PROBE707_MU_CNT=1_PROBE708_WIDTH=1_PROBE708_MU_CNT=1_PROBE709_WIDTH=1_PROBE709_MU_CNT=1_PROBE710_WIDTH=1_PROBE710_MU_CNT=1_PROBE711_WIDTH=1_PROBE711_MU_CNT=1_PROBE712_WIDTH=1_PROBE712_MU_CNT=1_PROBE713_WIDTH=1_PROBE713_MU_CNT=1_PROBE714_WIDTH=1_PROBE714_MU_CNT=1_PROBE715_WIDTH=1_PROBE715_MU_CNT=1_PROBE716_WIDTH=1_PROBE716_MU_CNT=1_PROBE717_WIDTH=1_PROBE717_MU_CNT=1_PROBE718_WIDTH=1_PROBE718_MU_CNT=1_PROBE719_WIDTH=1_PROBE719_MU_CNT=1_PROBE720_WIDTH=1_PROBE720_MU_CNT=1_PROBE721_WIDTH=1_PROBE721_MU_CNT=1_PROBE722_WIDTH=1_PROBE722_MU_CNT=1_PROBE723_WIDTH=1_PROBE723_MU_CNT=1_PROBE724_WIDTH=1_PROBE724_MU_CNT=1_PROBE725_WIDTH=1_PROBE725_MU_CNT=1_PROBE726_WIDTH=1_PROBE726_MU_CNT=1_PROBE727_WIDTH=1_PROBE727_MU_CNT=1_PROBE728_WIDTH=1_PROBE728_MU_CNT=1_PROBE729_WIDTH=1_PROBE729_MU_CNT=1_PROBE730_WIDTH=1_PROBE730_MU_CNT=1_PROBE731_WIDTH=1_PROBE731_MU_CNT=1_PROBE732_WIDTH=1_PROBE732_MU_CNT=1_PROBE733_WIDTH=1_PROBE733_MU_CNT=1_PROBE734_WIDTH=1_PROBE734_MU_CNT=1_PROBE735_WIDTH=1_PROBE735_MU_CNT=1_PROBE736_WIDTH=1_PROBE736_MU_CNT=1_PROBE737_WIDTH=1_PROBE737_MU_CNT=1_PROBE738_WIDTH=1_PROBE738_MU_CNT=1_PROBE739_WIDTH=1_PROBE739_MU_CNT=1_PROBE740_WIDTH=1_PROBE740_MU_CNT=1_PROBE741_WIDTH=1_PROBE741_MU_CNT=1_PROBE742_WIDTH=1_PROBE742_MU_CNT=1_PROBE743_WIDTH=1_PROBE743_MU_CNT=1_PROBE744_WIDTH=1_PROBE744_MU_CNT=1_PROBE745_WIDTH=1_PROBE745_MU_CNT=1_PROBE746_WIDTH=1_PROBE746_MU_CNT=1_PROBE747_WIDTH=1_PROBE747_MU_CNT=1_PROBE748_WIDTH=1_PROBE748_MU_CNT=1_PROBE749_WIDTH=1_PROBE749_MU_CNT=1_PROBE750_WIDTH=1_PROBE750_MU_CNT=1_PROBE751_WIDTH=1_PROBE751_MU_CNT=1_PROBE752_WIDTH=1_PROBE752_MU_CNT=1_PROBE753_WIDTH=1_PROBE753_MU_CNT=1_PROBE754_WIDTH=1_PROBE754_MU_CNT=1_PROBE755_WIDTH=1_PROBE755_MU_CNT=1_PROBE756_WIDTH=1_PROBE756_MU_CNT=1_PROBE757_WIDTH=1_PROBE757_MU_CNT=1_PROBE758_WIDTH=1_PROBE758_MU_CNT=1_PROBE759_WIDTH=1_PROBE759_MU_CNT=1_PROBE760_WIDTH=1_PROBE760_MU_CNT=1_PROBE761_WIDTH=1_PROBE761_MU_CNT=1_PROBE762_WIDTH=1_PROBE762_MU_CNT=1_PROBE763_WIDTH=1_PROBE763_MU_CNT=1_PROBE764_WIDTH=1_PROBE764_MU_CNT=1_PROBE765_WIDTH=1_PROBE765_MU_CNT=1_PROBE766_WIDTH=1_PROBE766_MU_CNT=1_PROBE767_WIDTH=1_PROBE767_MU_CNT=1_PROBE768_WIDTH=1_PROBE768_MU_CNT=1_PROBE769_WIDTH=1_PROBE769_MU_CNT=1_PROBE770_WIDTH=1_PROBE770_MU_CNT=1_PROBE771_WIDTH=1_PROBE771_MU_CNT=1_PROBE772_WIDTH=1_PROBE772_MU_CNT=1_PROBE773_WIDTH=1_PROBE773_MU_CNT=1_PROBE774_WIDTH=1_PROBE774_MU_CNT=1_PROBE775_WIDTH=1_PROBE775_MU_CNT=1_PROBE776_WIDTH=1_PROBE776_MU_CNT=1_PROBE777_WIDTH=1_PROBE777_MU_CNT=1_PROBE778_WIDTH=1_PROBE778_MU_CNT=1_PROBE779_WIDTH=1_PROBE779_MU_CNT=1_PROBE780_WIDTH=1_PROBE780_MU_CNT=1_PROBE781_WIDTH=1_PROBE781_MU_CNT=1_PROBE782_WIDTH=1_PROBE782_MU_CNT=1_PROBE783_WIDTH=1_PROBE783_MU_CNT=1_PROBE784_WIDTH=1_PROBE784_MU_CNT=1_PROBE785_WIDTH=1_PROBE785_MU_CNT=1_PROBE786_WIDTH=1_PROBE786_MU_CNT=1_PROBE787_WIDTH=1_PROBE787_MU_CNT=1_PROBE788_WIDTH=1_PROBE788_MU_CNT=1_PROBE789_WIDTH=1_PROBE789_MU_CNT=1_PROBE790_WIDTH=1_PROBE790_MU_CNT=1_PROBE791_WIDTH=1_PROBE791_MU_CNT=1_PROBE792_WIDTH=1_PROBE792_MU_CNT=1_PROBE793_WIDTH=1_PROBE793_MU_CNT=1_PROBE794_WIDTH=1_PROBE794_MU_CNT=1_PROBE795_WIDTH=1_PROBE795_MU_CNT=1_PROBE796_WIDTH=1_PROBE796_MU_CNT=1_PROBE797_WIDTH=1_PROBE797_MU_CNT=1_PROBE798_WIDTH=1_PROBE798_MU_CNT=1_PROBE799_WIDTH=1_PROBE799_MU_CNT=1_PROBE800_WIDTH=1_PROBE800_MU_CNT=1_PROBE801_WIDTH=1_PROBE801_MU_CNT=1_PROBE802_WIDTH=1_PROBE802_MU_CNT=1_PROBE803_WIDTH=1_PROBE803_MU_CNT=1_PROBE804_WIDTH=1_PROBE804_MU_CNT=1_PROBE805_WIDTH=1_PROBE805_MU_CNT=1_PROBE806_WIDTH=1_PROBE806_MU_CNT=1_PROBE807_WIDTH=1_PROBE807_MU_CNT=1_PROBE808_WIDTH=1_PROBE808_MU_CNT=1_PROBE809_WIDTH=1_PROBE809_MU_CNT=1_PROBE810_WIDTH=1_PROBE810_MU_CNT=1_PROBE811_WIDTH=1_PROBE811_MU_CNT=1_PROBE812_WIDTH=1_PROBE812_MU_CNT=1_PROBE813_WIDTH=1_PROBE813_MU_CNT=1_PROBE814_WIDTH=1_PROBE814_MU_CNT=1_PROBE815_WIDTH=1_PROBE815_MU_CNT=1_PROBE816_WIDTH=1_PROBE816_MU_CNT=1_PROBE817_WIDTH=1_PROBE817_MU_CNT=1_PROBE818_WIDTH=1_PROBE818_MU_CNT=1_PROBE819_WIDTH=1_PROBE819_MU_CNT=1_PROBE820_WIDTH=1_PROBE820_MU_CNT=1_PROBE821_WIDTH=1_PROBE821_MU_CNT=1_PROBE822_WIDTH=1_PROBE822_MU_CNT=1_PROBE823_WIDTH=1_PROBE823_MU_CNT=1_PROBE824_WIDTH=1_PROBE824_MU_CNT=1_PROBE825_WIDTH=1_PROBE825_MU_CNT=1_PROBE826_WIDTH=1_PROBE826_MU_CNT=1_PROBE827_WIDTH=1_PROBE827_MU_CNT=1_PROBE828_WIDTH=1_PROBE828_MU_CNT=1_PROBE829_WIDTH=1_PROBE829_MU_CNT=1_PROBE830_WIDTH=1_PROBE830_MU_CNT=1_PROBE831_WIDTH=1_PROBE831_MU_CNT=1_PROBE832_WIDTH=1_PROBE832_MU_CNT=1_PROBE833_WIDTH=1_PROBE833_MU_CNT=1_PROBE834_WIDTH=1_PROBE834_MU_CNT=1_PROBE835_WIDTH=1_PROBE835_MU_CNT=1_PROBE836_WIDTH=1_PROBE836_MU_CNT=1_PROBE837_WIDTH=1_PROBE837_MU_CNT=1_PROBE838_WIDTH=1_PROBE838_MU_CNT=1_PROBE839_WIDTH=1_PROBE839_MU_CNT=1_PROBE840_WIDTH=1_PROBE840_MU_CNT=1_PROBE841_WIDTH=1_PROBE841_MU_CNT=1_PROBE842_WIDTH=1_PROBE842_MU_CNT=1_PROBE843_WIDTH=1_PROBE843_MU_CNT=1_PROBE844_WIDTH=1_PROBE844_MU_CNT=1_PROBE845_WIDTH=1_PROBE845_MU_CNT=1_PROBE846_WIDTH=1_PROBE846_MU_CNT=1_PROBE847_WIDTH=1_PROBE847_MU_CNT=1_PROBE848_WIDTH=1_PROBE848_MU_CNT=1_PROBE849_WIDTH=1_PROBE849_MU_CNT=1_PROBE850_WIDTH=1_PROBE850_MU_CNT=1_PROBE851_WIDTH=1_PROBE851_MU_CNT=1_PROBE852_WIDTH=1_PROBE852_MU_CNT=1_PROBE853_WIDTH=1_PROBE853_MU_CNT=1_PROBE854_WIDTH=1_PROBE854_MU_CNT=1_PROBE855_WIDTH=1_PROBE855_MU_CNT=1_PROBE856_WIDTH=1_PROBE856_MU_CNT=1_PROBE857_WIDTH=1_PROBE857_MU_CNT=1_PROBE858_WIDTH=1_PROBE858_MU_CNT=1_PROBE859_WIDTH=1_PROBE859_MU_CNT=1_PROBE860_WIDTH=1_PROBE860_MU_CNT=1_PROBE861_WIDTH=1_PROBE861_MU_CNT=1_PROBE862_WIDTH=1_PROBE862_MU_CNT=1_PROBE863_WIDTH=1_PROBE863_MU_CNT=1_PROBE864_WIDTH=1_PROBE864_MU_CNT=1_PROBE865_WIDTH=1_PROBE865_MU_CNT=1_PROBE866_WIDTH=1_PROBE866_MU_CNT=1_PROBE867_WIDTH=1_PROBE867_MU_CNT=1_PROBE868_WIDTH=1_PROBE868_MU_CNT=1_PROBE869_WIDTH=1_PROBE869_MU_CNT=1_PROBE870_WIDTH=1_PROBE870_MU_CNT=1_PROBE871_WIDTH=1_PROBE871_MU_CNT=1_PROBE872_WIDTH=1_PROBE872_MU_CNT=1_PROBE873_WIDTH=1_PROBE873_MU_CNT=1_PROBE874_WIDTH=1_PROBE874_MU_CNT=1_PROBE875_WIDTH=1_PROBE875_MU_CNT=1_PROBE876_WIDTH=1_PROBE876_MU_CNT=1_PROBE877_WIDTH=1_PROBE877_MU_CNT=1_PROBE878_WIDTH=1_PROBE878_MU_CNT=1_PROBE879_WIDTH=1_PROBE879_MU_CNT=1_PROBE880_WIDTH=1_PROBE880_MU_CNT=1_PROBE881_WIDTH=1_PROBE881_MU_CNT=1_PROBE882_WIDTH=1_PROBE882_MU_CNT=1_PROBE883_WIDTH=1_PROBE883_MU_CNT=1_PROBE884_WIDTH=1_PROBE884_MU_CNT=1_PROBE885_WIDTH=1_PROBE885_MU_CNT=1_PROBE886_WIDTH=1_PROBE886_MU_CNT=1_PROBE887_WIDTH=1_PROBE887_MU_CNT=1_PROBE888_WIDTH=1_PROBE888_MU_CNT=1_PROBE889_WIDTH=1_PROBE889_MU_CNT=1_PROBE890_WIDTH=1_PROBE890_MU_CNT=1_PROBE891_WIDTH=1_PROBE891_MU_CNT=1_PROBE892_WIDTH=1_PROBE892_MU_CNT=1_PROBE893_WIDTH=1_PROBE893_MU_CNT=1_PROBE894_WIDTH=1_PROBE894_MU_CNT=1_PROBE895_WIDTH=1_PROBE895_MU_CNT=1_PROBE896_WIDTH=1_PROBE896_MU_CNT=1_PROBE897_WIDTH=1_PROBE897_MU_CNT=1_PROBE898_WIDTH=1_PROBE898_MU_CNT=1_PROBE899_WIDTH=1_PROBE899_MU_CNT=1_PROBE900_WIDTH=1_PROBE900_MU_CNT=1_PROBE901_WIDTH=1_PROBE901_MU_CNT=1_PROBE902_WIDTH=1_PROBE902_MU_CNT=1_PROBE903_WIDTH=1_PROBE903_MU_CNT=1_PROBE904_WIDTH=1_PROBE904_MU_CNT=1_PROBE905_WIDTH=1_PROBE905_MU_CNT=1_PROBE906_WIDTH=1_PROBE906_MU_CNT=1_PROBE907_WIDTH=1_PROBE907_MU_CNT=1_PROBE908_WIDTH=1_PROBE908_MU_CNT=1_PROBE909_WIDTH=1_PROBE909_MU_CNT=1_PROBE910_WIDTH=1_PROBE910_MU_CNT=1_PROBE911_WIDTH=1_PROBE911_MU_CNT=1_PROBE912_WIDTH=1_PROBE912_MU_CNT=1_PROBE913_WIDTH=1_PROBE913_MU_CNT=1_PROBE914_WIDTH=1_PROBE914_MU_CNT=1_PROBE915_WIDTH=1_PROBE915_MU_CNT=1_PROBE916_WIDTH=1_PROBE916_MU_CNT=1_PROBE917_WIDTH=1_PROBE917_MU_CNT=1_PROBE918_WIDTH=1_PROBE918_MU_CNT=1_PROBE919_WIDTH=1_PROBE919_MU_CNT=1_PROBE920_WIDTH=1_PROBE920_MU_CNT=1_PROBE921_WIDTH=1_PROBE921_MU_CNT=1_PROBE922_WIDTH=1_PROBE922_MU_CNT=1_PROBE923_WIDTH=1_PROBE923_MU_CNT=1_PROBE924_WIDTH=1_PROBE924_MU_CNT=1_PROBE925_WIDTH=1_PROBE925_MU_CNT=1_PROBE926_WIDTH=1_PROBE926_MU_CNT=1_PROBE927_WIDTH=1_PROBE927_MU_CNT=1_PROBE928_WIDTH=1_PROBE928_MU_CNT=1_PROBE929_WIDTH=1_PROBE929_MU_CNT=1_PROBE930_WIDTH=1_PROBE930_MU_CNT=1_PROBE931_WIDTH=1_PROBE931_MU_CNT=1_PROBE932_WIDTH=1_PROBE932_MU_CNT=1_PROBE933_WIDTH=1_PROBE933_MU_CNT=1_PROBE934_WIDTH=1_PROBE934_MU_CNT=1_PROBE935_WIDTH=1_PROBE935_MU_CNT=1_PROBE936_WIDTH=1_PROBE936_MU_CNT=1_PROBE937_WIDTH=1_PROBE937_MU_CNT=1_PROBE938_WIDTH=1_PROBE938_MU_CNT=1_PROBE939_WIDTH=1_PROBE939_MU_CNT=1_PROBE940_WIDTH=1_PROBE940_MU_CNT=1_PROBE941_WIDTH=1_PROBE941_MU_CNT=1_PROBE942_WIDTH=1_PROBE942_MU_CNT=1_PROBE943_WIDTH=1_PROBE943_MU_CNT=1_PROBE944_WIDTH=1_PROBE944_MU_CNT=1_PROBE945_WIDTH=1_PROBE945_MU_CNT=1_PROBE946_WIDTH=1_PROBE946_MU_CNT=1_PROBE947_WIDTH=1_PROBE947_MU_CNT=1_PROBE948_WIDTH=1_PROBE948_MU_CNT=1_PROBE949_WIDTH=1_PROBE949_MU_CNT=1_PROBE950_WIDTH=1_PROBE950_MU_CNT=1_PROBE951_WIDTH=1_PROBE951_MU_CNT=1_PROBE952_WIDTH=1_PROBE952_MU_CNT=1_PROBE953_WIDTH=1_PROBE953_MU_CNT=1_PROBE954_WIDTH=1_PROBE954_MU_CNT=1_PROBE955_WIDTH=1_PROBE955_MU_CNT=1_PROBE956_WIDTH=1_PROBE956_MU_CNT=1_PROBE957_WIDTH=1_PROBE957_MU_CNT=1_PROBE958_WIDTH=1_PROBE958_MU_CNT=1_PROBE959_WIDTH=1_PROBE959_MU_CNT=1_PROBE960_WIDTH=1_PROBE960_MU_CNT=1_PROBE961_WIDTH=1_PROBE961_MU_CNT=1_PROBE962_WIDTH=1_PROBE962_MU_CNT=1_PROBE963_WIDTH=1_PROBE963_MU_CNT=1_PROBE964_WIDTH=1_PROBE964_MU_CNT=1_PROBE965_WIDTH=1_PROBE965_MU_CNT=1_PROBE966_WIDTH=1_PROBE966_MU_CNT=1_PROBE967_WIDTH=1_PROBE967_MU_CNT=1_PROBE968_WIDTH=1_PROBE968_MU_CNT=1_PROBE969_WIDTH=1_PROBE969_MU_CNT=1_PROBE970_WIDTH=1_PROBE970_MU_CNT=1_PROBE971_WIDTH=1_PROBE971_MU_CNT=1_PROBE972_WIDTH=1_PROBE972_MU_CNT=1_PROBE973_WIDTH=1_PROBE973_MU_CNT=1_PROBE974_WIDTH=1_PROBE974_MU_CNT=1_PROBE975_WIDTH=1_PROBE975_MU_CNT=1_PROBE976_WIDTH=1_PROBE976_MU_CNT=1_PROBE977_WIDTH=1_PROBE977_MU_CNT=1_PROBE978_WIDTH=1_PROBE978_MU_CNT=1_PROBE979_WIDTH=1_PROBE979_MU_CNT=1_PROBE980_WIDTH=1_PROBE980_MU_CNT=1_PROBE981_WIDTH=1_PROBE981_MU_CNT=1_PROBE982_WIDTH=1_PROBE982_MU_CNT=1_PROBE983_WIDTH=1_PROBE983_MU_CNT=1_PROBE984_WIDTH=1_PROBE984_MU_CNT=1_PROBE985_WIDTH=1_PROBE985_MU_CNT=1_PROBE986_WIDTH=1_PROBE986_MU_CNT=1_PROBE987_WIDTH=1_PROBE987_MU_CNT=1_PROBE988_WIDTH=1_PROBE988_MU_CNT=1_PROBE989_WIDTH=1_PROBE989_MU_CNT=1_PROBE990_WIDTH=1_PROBE990_MU_CNT=1_PROBE991_WIDTH=1_PROBE991_MU_CNT=1_PROBE992_WIDTH=1_PROBE992_MU_CNT=1_PROBE993_WIDTH=1_PROBE993_MU_CNT=1_PROBE994_WIDTH=1_PROBE994_MU_CNT=1_PROBE995_WIDTH=1_PROBE995_MU_CNT=1_PROBE996_WIDTH=1_PROBE996_MU_CNT=1_PROBE997_WIDTH=1_PROBE997_MU_CNT=1_PROBE998_WIDTH=1_PROBE998_MU_CNT=1_PROBE999_WIDTH=1_PROBE999_MU_CNT=1_PROBE1000_WIDTH=1_PROBE1000_MU_CNT=1_PROBE1001_WIDTH=1_PROBE1001_MU_CNT=1_PROBE1002_WIDTH=1_PROBE1002_MU_CNT=1_PROBE1003_WIDTH=1_PROBE1003_MU_CNT=1_PROBE1004_WIDTH=1_PROBE1004_MU_CNT=1_PROBE1005_WIDTH=1_PROBE1005_MU_CNT=1_PROBE1006_WIDTH=1_PROBE1006_MU_CNT=1_PROBE1007_WIDTH=1_PROBE1007_MU_CNT=1_PROBE1008_WIDTH=1_PROBE1008_MU_CNT=1_PROBE1009_WIDTH=1_PROBE1009_MU_CNT=1_PROBE1010_WIDTH=1_PROBE1010_MU_CNT=1_PROBE1011_WIDTH=1_PROBE1011_MU_CNT=1_PROBE1012_WIDTH=1_PROBE1012_MU_CNT=1_PROBE1013_WIDTH=1_PROBE1013_MU_CNT=1_PROBE1014_WIDTH=1_PROBE1014_MU_CNT=1_PROBE1015_WIDTH=1_PROBE1015_MU_CNT=1_PROBE1016_WIDTH=1_PROBE1016_MU_CNT=1_PROBE1017_WIDTH=1_PROBE1017_MU_CNT=1_PROBE1018_WIDTH=1_PROBE1018_MU_CNT=1_PROBE1019_WIDTH=1_PROBE1019_MU_CNT=1_PROBE1020_WIDTH=1_PROBE1020_MU_CNT=1_PROBE1021_WIDTH=1_PROBE1021_MU_CNT=1_PROBE1022_WIDTH=1_PROBE1022_MU_CNT=1_PROBE1023_WIDTH=1_PROBE1023_MU_CNT=1,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=1,C_CORE_INFO1=0,C_CORE_INFO2=0,C_CAPTURE_TYPE=0,C_MU_TYPE=0,C_TC_TYPE=0,C_NUM_OF_PROBES=4,C_DATA_DEPTH=1024,C_MAJOR_VERSION=2013,C_MINOR_VERSION=3,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=4,C_CORE_MINOR_VER=0,C_XSDB_SLAVE_TYPE=17,C_NEXT_SLAVE=0,C_CSE_DRV_VER=1,C_USE_TEST_REG=1,C_PIPE_IFACE=1,C_RAM_STYLE=SUBCORE,C_TRIGOUT_EN=0,C_TRIGIN_EN=0,C_ADV_TRIGGER=0,C_EN_STRG_QUAL=0,C_INPUT_PIPE_STAGES=0,C_PROBE0_WIDTH=1,C_PROBE1_WIDTH=1,C_PROBE2_WIDTH=1,C_PROBE3_WIDTH=1,C_PROBE4_WIDTH=1,C_PROBE5_WIDTH=1,C_PROBE6_WIDTH=1,C_PROBE7_WIDTH=1,C_PROBE8_WIDTH=1,C_PROBE9_WIDTH=1,C_PROBE10_WIDTH=1,C_PROBE11_WIDTH=1,C_PROBE12_WIDTH=1,C_PROBE13_WIDTH=1,C_PROBE14_WIDTH=1,C_PROBE15_WIDTH=1,C_PROBE16_WIDTH=1,C_PROBE17_WIDTH=1,C_PROBE18_WIDTH=1,C_PROBE19_WIDTH=1,C_PROBE20_WIDTH=1,C_PROBE21_WIDTH=1,C_PROBE22_WIDTH=1,C_PROBE23_WIDTH=1,C_PROBE24_WIDTH=1,C_PROBE25_WIDTH=1,C_PROBE26_WIDTH=1,C_PROBE27_WIDTH=1,C_PROBE28_WIDTH=1,C_PROBE29_WIDTH=1,C_PROBE30_WIDTH=1,C_PROBE31_WIDTH=1,C_PROBE32_WIDTH=1,C_PROBE33_WIDTH=1,C_PROBE34_WIDTH=1,C_PROBE35_WIDTH=1,C_PROBE36_WIDTH=1,C_PROBE37_WIDTH=1,C_PROBE38_WIDTH=1,C_PROBE39_WIDTH=1,C_PROBE40_WIDTH=1,C_PROBE41_WIDTH=1,C_PROBE42_WIDTH=1,C_PROBE43_WIDTH=1,C_PROBE44_WIDTH=1,C_PROBE45_WIDTH=1,C_PROBE46_WIDTH=1,C_PROBE47_WIDTH=1,C_PROBE48_WIDTH=1,C_PROBE49_WIDTH=1,C_PROBE50_WIDTH=1,C_PROBE51_WIDTH=1,C_PROBE52_WIDTH=1,C_PROBE53_WIDTH=1,C_PROBE54_WIDTH=1,C_PROBE55_WIDTH=1,C_PROBE56_WIDTH=1,C_PROBE57_WIDTH=1,C_PROBE58_WIDTH=1,C_PROBE59_WIDTH=1,C_PROBE60_WIDTH=1,C_PROBE61_WIDTH=1,C_PROBE62_WIDTH=1,C_PROBE63_WIDTH=1,C_PROBE64_WIDTH=1,C_PROBE65_WIDTH=1,C_PROBE66_WIDTH=1,C_PROBE67_WIDTH=1,C_PROBE68_WIDTH=1,C_PROBE69_WIDTH=1,C_PROBE70_WIDTH=1,C_PROBE71_WIDTH=1,C_PROBE72_WIDTH=1,C_PROBE73_WIDTH=1,C_PROBE74_WIDTH=1,C_PROBE75_WIDTH=1,C_PROBE76_WIDTH=1,C_PROBE77_WIDTH=1,C_PROBE78_WIDTH=1,C_PROBE79_WIDTH=1,C_PROBE80_WIDTH=1,C_PROBE81_WIDTH=1,C_PROBE82_WIDTH=1,C_PROBE83_WIDTH=1,C_PROBE84_WIDTH=1,C_PROBE85_WIDTH=1,C_PROBE86_WIDTH=1,C_PROBE87_WIDTH=1,C_PROBE88_WIDTH=1,C_PROBE89_WIDTH=1,C_PROBE90_WIDTH=1,C_PROBE91_WIDTH=1,C_PROBE92_WIDTH=1,C_PROBE93_WIDTH=1,C_PROBE94_WIDTH=1,C_PROBE95_WIDTH=1,C_PROBE96_WIDTH=1,C_PROBE97_WIDTH=1,C_PROBE98_WIDTH=1,C_PROBE99_WIDTH=1,C_PROBE100_WIDTH=1,C_PROBE101_WIDTH=1,C_PROBE102_WIDTH=1,C_PROBE103_WIDTH=1,C_PROBE104_WIDTH=1,C_PROBE105_WIDTH=1,C_PROBE106_WIDTH=1,C_PROBE107_WIDTH=1,C_PROBE108_WIDTH=1,C_PROBE109_WIDTH=1,C_PROBE110_WIDTH=1,C_PROBE111_WIDTH=1,C_PROBE112_WIDTH=1,C_PROBE113_WIDTH=1,C_PROBE114_WIDTH=1,C_PROBE115_WIDTH=1,C_PROBE116_WIDTH=1,C_PROBE117_WIDTH=1,C_PROBE118_WIDTH=1,C_PROBE119_WIDTH=1,C_PROBE120_WIDTH=1,C_PROBE121_WIDTH=1,C_PROBE122_WIDTH=1,C_PROBE123_WIDTH=1,C_PROBE124_WIDTH=1,C_PROBE125_WIDTH=1,C_PROBE126_WIDTH=1,C_PROBE127_WIDTH=1,C_PROBE128_WIDTH=1,C_PROBE129_WIDTH=1,C_PROBE130_WIDTH=1,C_PROBE131_WIDTH=1,C_PROBE132_WIDTH=1,C_PROBE133_WIDTH=1,C_PROBE134_WIDTH=1,C_PROBE135_WIDTH=1,C_PROBE136_WIDTH=1,C_PROBE137_WIDTH=1,C_PROBE138_WIDTH=1,C_PROBE139_WIDTH=1,C_PROBE140_WIDTH=1,C_PROBE141_WIDTH=1,C_PROBE142_WIDTH=1,C_PROBE143_WIDTH=1,C_PROBE144_WIDTH=1,C_PROBE145_WIDTH=1,C_PROBE146_WIDTH=1,C_PROBE147_WIDTH=1,C_PROBE148_WIDTH=1,C_PROBE149_WIDTH=1,C_PROBE150_WIDTH=1,C_PROBE151_WIDTH=1,C_PROBE152_WIDTH=1,C_PROBE153_WIDTH=1,C_PROBE154_WIDTH=1,C_PROBE155_WIDTH=1,C_PROBE156_WIDTH=1,C_PROBE157_WIDTH=1,C_PROBE158_WIDTH=1,C_PROBE159_WIDTH=1,C_PROBE160_WIDTH=1,C_PROBE161_WIDTH=1,C_PROBE162_WIDTH=1,C_PROBE163_WIDTH=1,C_PROBE164_WIDTH=1,C_PROBE165_WIDTH=1,C_PROBE166_WIDTH=1,C_PROBE167_WIDTH=1,C_PROBE168_WIDTH=1,C_PROBE169_WIDTH=1,C_PROBE170_WIDTH=1,C_PROBE171_WIDTH=1,C_PROBE172_WIDTH=1,C_PROBE173_WIDTH=1,C_PROBE174_WIDTH=1,C_PROBE175_WIDTH=1,C_PROBE176_WIDTH=1,C_PROBE177_WIDTH=1,C_PROBE178_WIDTH=1,C_PROBE179_WIDTH=1,C_PROBE180_WIDTH=1,C_PROBE181_WIDTH=1,C_PROBE182_WIDTH=1,C_PROBE183_WIDTH=1,C_PROBE184_WIDTH=1,C_PROBE185_WIDTH=1,C_PROBE186_WIDTH=1,C_PROBE187_WIDTH=1,C_PROBE188_WIDTH=1,C_PROBE189_WIDTH=1,C_PROBE190_WIDTH=1,C_PROBE191_WIDTH=1,C_PROBE192_WIDTH=1,C_PROBE193_WIDTH=1,C_PROBE194_WIDTH=1,C_PROBE195_WIDTH=1,C_PROBE196_WIDTH=1,C_PROBE197_WIDTH=1,C_PROBE198_WIDTH=1,C_PROBE199_WIDTH=1,C_PROBE200_WIDTH=1,C_PROBE201_WIDTH=1,C_PROBE202_WIDTH=1,C_PROBE203_WIDTH=1,C_PROBE204_WIDTH=1,C_PROBE205_WIDTH=1,C_PROBE206_WIDTH=1,C_PROBE207_WIDTH=1,C_PROBE208_WIDTH=1,C_PROBE209_WIDTH=1,C_PROBE210_WIDTH=1,C_PROBE211_WIDTH=1,C_PROBE212_WIDTH=1,C_PROBE213_WIDTH=1,C_PROBE214_WIDTH=1,C_PROBE215_WIDTH=1,C_PROBE216_WIDTH=1,C_PROBE217_WIDTH=1,C_PROBE218_WIDTH=1,C_PROBE219_WIDTH=1,C_PROBE220_WIDTH=1,C_PROBE221_WIDTH=1,C_PROBE222_WIDTH=1,C_PROBE223_WIDTH=1,C_PROBE224_WIDTH=1,C_PROBE225_WIDTH=1,C_PROBE226_WIDTH=1,C_PROBE227_WIDTH=1,C_PROBE228_WIDTH=1,C_PROBE229_WIDTH=1,C_PROBE230_WIDTH=1,C_PROBE231_WIDTH=1,C_PROBE232_WIDTH=1,C_PROBE233_WIDTH=1,C_PROBE234_WIDTH=1,C_PROBE235_WIDTH=1,C_PROBE236_WIDTH=1,C_PROBE237_WIDTH=1,C_PROBE238_WIDTH=1,C_PROBE239_WIDTH=1,C_PROBE240_WIDTH=1,C_PROBE241_WIDTH=1,C_PROBE242_WIDTH=1,C_PROBE243_WIDTH=1,C_PROBE244_WIDTH=1,C_PROBE245_WIDTH=1,C_PROBE246_WIDTH=1,C_PROBE247_WIDTH=1,C_PROBE248_WIDTH=1,C_PROBE249_WIDTH=1,C_PROBE250_WIDTH=1,C_PROBE251_WIDTH=1,C_PROBE252_WIDTH=1,C_PROBE253_WIDTH=1,C_PROBE254_WIDTH=1,C_PROBE255_WIDTH=1,C_PROBE256_WIDTH=1,C_PROBE257_WIDTH=1,C_PROBE258_WIDTH=1,C_PROBE259_WIDTH=1,C_PROBE260_WIDTH=1,C_PROBE261_WIDTH=1,C_PROBE262_WIDTH=1,C_PROBE263_WIDTH=1,C_PROBE264_WIDTH=1,C_PROBE265_WIDTH=1,C_PROBE266_WIDTH=1,C_PROBE267_WIDTH=1,C_PROBE268_WIDTH=1,C_PROBE269_WIDTH=1,C_PROBE270_WIDTH=1,C_PROBE271_WIDTH=1,C_PROBE272_WIDTH=1,C_PROBE273_WIDTH=1,C_PROBE274_WIDTH=1,C_PROBE275_WIDTH=1,C_PROBE276_WIDTH=1,C_PROBE277_WIDTH=1,C_PROBE278_WIDTH=1,C_PROBE279_WIDTH=1,C_PROBE280_WIDTH=1,C_PROBE281_WIDTH=1,C_PROBE282_WIDTH=1,C_PROBE283_WIDTH=1,C_PROBE284_WIDTH=1,C_PROBE285_WIDTH=1,C_PROBE286_WIDTH=1,C_PROBE287_WIDTH=1,C_PROBE288_WIDTH=1,C_PROBE289_WIDTH=1,C_PROBE290_WIDTH=1,C_PROBE291_WIDTH=1,C_PROBE292_WIDTH=1,C_PROBE293_WIDTH=1,C_PROBE294_WIDTH=1,C_PROBE295_WIDTH=1,C_PROBE296_WIDTH=1,C_PROBE297_WIDTH=1,C_PROBE298_WIDTH=1,C_PROBE299_WIDTH=1,C_PROBE300_WIDTH=1,C_PROBE301_WIDTH=1,C_PROBE302_WIDTH=1,C_PROBE303_WIDTH=1,C_PROBE304_WIDTH=1,C_PROBE305_WIDTH=1,C_PROBE306_WIDTH=1,C_PROBE307_WIDTH=1,C_PROBE308_WIDTH=1,C_PROBE309_WIDTH=1,C_PROBE310_WIDTH=1,C_PROBE311_WIDTH=1,C_PROBE312_WIDTH=1,C_PROBE313_WIDTH=1,C_PROBE314_WIDTH=1,C_PROBE315_WIDTH=1,C_PROBE316_WIDTH=1,C_PROBE317_WIDTH=1,C_PROBE318_WIDTH=1,C_PROBE319_WIDTH=1,C_PROBE320_WIDTH=1,C_PROBE321_WIDTH=1,C_PROBE322_WIDTH=1,C_PROBE323_WIDTH=1,C_PROBE324_WIDTH=1,C_PROBE325_WIDTH=1,C_PROBE326_WIDTH=1,C_PROBE327_WIDTH=1,C_PROBE328_WIDTH=1,C_PROBE329_WIDTH=1,C_PROBE330_WIDTH=1,C_PROBE331_WIDTH=1,C_PROBE332_WIDTH=1,C_PROBE333_WIDTH=1,C_PROBE334_WIDTH=1,C_PROBE335_WIDTH=1,C_PROBE336_WIDTH=1,C_PROBE337_WIDTH=1,C_PROBE338_WIDTH=1,C_PROBE339_WIDTH=1,C_PROBE340_WIDTH=1,C_PROBE341_WIDTH=1,C_PROBE342_WIDTH=1,C_PROBE343_WIDTH=1,C_PROBE344_WIDTH=1,C_PROBE345_WIDTH=1,C_PROBE346_WIDTH=1,C_PROBE347_WIDTH=1,C_PROBE348_WIDTH=1,C_PROBE349_WIDTH=1,C_PROBE350_WIDTH=1,C_PROBE351_WIDTH=1,C_PROBE352_WIDTH=1,C_PROBE353_WIDTH=1,C_PROBE354_WIDTH=1,C_PROBE355_WIDTH=1,C_PROBE356_WIDTH=1,C_PROBE357_WIDTH=1,C_PROBE358_WIDTH=1,C_PROBE359_WIDTH=1,C_PROBE360_WIDTH=1,C_PROBE361_WIDTH=1,C_PROBE362_WIDTH=1,C_PROBE363_WIDTH=1,C_PROBE364_WIDTH=1,C_PROBE365_WIDTH=1,C_PROBE366_WIDTH=1,C_PROBE367_WIDTH=1,C_PROBE368_WIDTH=1,C_PROBE369_WIDTH=1,C_PROBE370_WIDTH=1,C_PROBE371_WIDTH=1,C_PROBE372_WIDTH=1,C_PROBE373_WIDTH=1,C_PROBE374_WIDTH=1,C_PROBE375_WIDTH=1,C_PROBE376_WIDTH=1,C_PROBE377_WIDTH=1,C_PROBE378_WIDTH=1,C_PROBE379_WIDTH=1,C_PROBE380_WIDTH=1,C_PROBE381_WIDTH=1,C_PROBE382_WIDTH=1,C_PROBE383_WIDTH=1,C_PROBE384_WIDTH=1,C_PROBE385_WIDTH=1,C_PROBE386_WIDTH=1,C_PROBE387_WIDTH=1,C_PROBE388_WIDTH=1,C_PROBE389_WIDTH=1,C_PROBE390_WIDTH=1,C_PROBE391_WIDTH=1,C_PROBE392_WIDTH=1,C_PROBE393_WIDTH=1,C_PROBE394_WIDTH=1,C_PROBE395_WIDTH=1,C_PROBE396_WIDTH=1,C_PROBE397_WIDTH=1,C_PROBE398_WIDTH=1,C_PROBE399_WIDTH=1,C_PROBE400_WIDTH=1,C_PROBE401_WIDTH=1,C_PROBE402_WIDTH=1,C_PROBE403_WIDTH=1,C_PROBE404_WIDTH=1,C_PROBE405_WIDTH=1,C_PROBE406_WIDTH=1,C_PROBE407_WIDTH=1,C_PROBE408_WIDTH=1,C_PROBE409_WIDTH=1,C_PROBE410_WIDTH=1,C_PROBE411_WIDTH=1,C_PROBE412_WIDTH=1,C_PROBE413_WIDTH=1,C_PROBE414_WIDTH=1,C_PROBE415_WIDTH=1,C_PROBE416_WIDTH=1,C_PROBE417_WIDTH=1,C_PROBE418_WIDTH=1,C_PROBE419_WIDTH=1,C_PROBE420_WIDTH=1,C_PROBE421_WIDTH=1,C_PROBE422_WIDTH=1,C_PROBE423_WIDTH=1,C_PROBE424_WIDTH=1,C_PROBE425_WIDTH=1,C_PROBE426_WIDTH=1,C_PROBE427_WIDTH=1,C_PROBE428_WIDTH=1,C_PROBE429_WIDTH=1,C_PROBE430_WIDTH=1,C_PROBE431_WIDTH=1,C_PROBE432_WIDTH=1,C_PROBE433_WIDTH=1,C_PROBE434_WIDTH=1,C_PROBE435_WIDTH=1,C_PROBE436_WIDTH=1,C_PROBE437_WIDTH=1,C_PROBE438_WIDTH=1,C_PROBE439_WIDTH=1,C_PROBE440_WIDTH=1,C_PROBE441_WIDTH=1,C_PROBE442_WIDTH=1,C_PROBE443_WIDTH=1,C_PROBE444_WIDTH=1,C_PROBE445_WIDTH=1,C_PROBE446_WIDTH=1,C_PROBE447_WIDTH=1,C_PROBE448_WIDTH=1,C_PROBE449_WIDTH=1,C_PROBE450_WIDTH=1,C_PROBE451_WIDTH=1,C_PROBE452_WIDTH=1,C_PROBE453_WIDTH=1,C_PROBE454_WIDTH=1,C_PROBE455_WIDTH=1,C_PROBE456_WIDTH=1,C_PROBE457_WIDTH=1,C_PROBE458_WIDTH=1,C_PROBE459_WIDTH=1,C_PROBE460_WIDTH=1,C_PROBE461_WIDTH=1,C_PROBE462_WIDTH=1,C_PROBE463_WIDTH=1,C_PROBE464_WIDTH=1,C_PROBE465_WIDTH=1,C_PROBE466_WIDTH=1,C_PROBE467_WIDTH=1,C_PROBE468_WIDTH=1,C_PROBE469_WIDTH=1,C_PROBE470_WIDTH=1,C_PROBE471_WIDTH=1,C_PROBE472_WIDTH=1,C_PROBE473_WIDTH=1,C_PROBE474_WIDTH=1,C_PROBE475_WIDTH=1,C_PROBE476_WIDTH=1,C_PROBE477_WIDTH=1,C_PROBE478_WIDTH=1,C_PROBE479_WIDTH=1,C_PROBE480_WIDTH=1,C_PROBE481_WIDTH=1,C_PROBE482_WIDTH=1,C_PROBE483_WIDTH=1,C_PROBE484_WIDTH=1,C_PROBE485_WIDTH=1,C_PROBE486_WIDTH=1,C_PROBE487_WIDTH=1,C_PROBE488_WIDTH=1,C_PROBE489_WIDTH=1,C_PROBE490_WIDTH=1,C_PROBE491_WIDTH=1,C_PROBE492_WIDTH=1,C_PROBE493_WIDTH=1,C_PROBE494_WIDTH=1,C_PROBE495_WIDTH=1,C_PROBE496_WIDTH=1,C_PROBE497_WIDTH=1,C_PROBE498_WIDTH=1,C_PROBE499_WIDTH=1,C_PROBE500_WIDTH=1,C_PROBE501_WIDTH=1,C_PROBE502_WIDTH=1,C_PROBE503_WIDTH=1,C_PROBE504_WIDTH=1,C_PROBE505_WIDTH=1,C_PROBE506_WIDTH=1,C_PROBE507_WIDTH=1,C_PROBE508_WIDTH=1,C_PROBE509_WIDTH=1,C_PROBE510_WIDTH=1,C_PROBE511_WIDTH=1,C_PROBE512_WIDTH=1,C_PROBE513_WIDTH=1,C_PROBE514_WIDTH=1,C_PROBE515_WIDTH=1,C_PROBE516_WIDTH=1,C_PROBE517_WIDTH=1,C_PROBE518_WIDTH=1,C_PROBE519_WIDTH=1,C_PROBE520_WIDTH=1,C_PROBE521_WIDTH=1,C_PROBE522_WIDTH=1,C_PROBE523_WIDTH=1,C_PROBE524_WIDTH=1,C_PROBE525_WIDTH=1,C_PROBE526_WIDTH=1,C_PROBE527_WIDTH=1,C_PROBE528_WIDTH=1,C_PROBE529_WIDTH=1,C_PROBE530_WIDTH=1,C_PROBE531_WIDTH=1,C_PROBE532_WIDTH=1,C_PROBE533_WIDTH=1,C_PROBE534_WIDTH=1,C_PROBE535_WIDTH=1,C_PROBE536_WIDTH=1,C_PROBE537_WIDTH=1,C_PROBE538_WIDTH=1,C_PROBE539_WIDTH=1,C_PROBE540_WIDTH=1,C_PROBE541_WIDTH=1,C_PROBE542_WIDTH=1,C_PROBE543_WIDTH=1,C_PROBE544_WIDTH=1,C_PROBE545_WIDTH=1,C_PROBE546_WIDTH=1,C_PROBE547_WIDTH=1,C_PROBE548_WIDTH=1,C_PROBE549_WIDTH=1,C_PROBE550_WIDTH=1,C_PROBE551_WIDTH=1,C_PROBE552_WIDTH=1,C_PROBE553_WIDTH=1,C_PROBE554_WIDTH=1,C_PROBE555_WIDTH=1,C_PROBE556_WIDTH=1,C_PROBE557_WIDTH=1,C_PROBE558_WIDTH=1,C_PROBE559_WIDTH=1,C_PROBE560_WIDTH=1,C_PROBE561_WIDTH=1,C_PROBE562_WIDTH=1,C_PROBE563_WIDTH=1,C_PROBE564_WIDTH=1,C_PROBE565_WIDTH=1,C_PROBE566_WIDTH=1,C_PROBE567_WIDTH=1,C_PROBE568_WIDTH=1,C_PROBE569_WIDTH=1,C_PROBE570_WIDTH=1,C_PROBE571_WIDTH=1,C_PROBE572_WIDTH=1,C_PROBE573_WIDTH=1,C_PROBE574_WIDTH=1,C_PROBE575_WIDTH=1,C_PROBE576_WIDTH=1,C_PROBE577_WIDTH=1,C_PROBE578_WIDTH=1,C_PROBE579_WIDTH=1,C_PROBE580_WIDTH=1,C_PROBE581_WIDTH=1,C_PROBE582_WIDTH=1,C_PROBE583_WIDTH=1,C_PROBE584_WIDTH=1,C_PROBE585_WIDTH=1,C_PROBE586_WIDTH=1,C_PROBE587_WIDTH=1,C_PROBE588_WIDTH=1,C_PROBE589_WIDTH=1,C_PROBE590_WIDTH=1,C_PROBE591_WIDTH=1,C_PROBE592_WIDTH=1,C_PROBE593_WIDTH=1,C_PROBE594_WIDTH=1,C_PROBE595_WIDTH=1,C_PROBE596_WIDTH=1,C_PROBE597_WIDTH=1,C_PROBE598_WIDTH=1,C_PROBE599_WIDTH=1,C_PROBE600_WIDTH=1,C_PROBE601_WIDTH=1,C_PROBE602_WIDTH=1,C_PROBE603_WIDTH=1,C_PROBE604_WIDTH=1,C_PROBE605_WIDTH=1,C_PROBE606_WIDTH=1,C_PROBE607_WIDTH=1,C_PROBE608_WIDTH=1,C_PROBE609_WIDTH=1,C_PROBE610_WIDTH=1,C_PROBE611_WIDTH=1,C_PROBE612_WIDTH=1,C_PROBE613_WIDTH=1,C_PROBE614_WIDTH=1,C_PROBE615_WIDTH=1,C_PROBE616_WIDTH=1,C_PROBE617_WIDTH=1,C_PROBE618_WIDTH=1,C_PROBE619_WIDTH=1,C_PROBE620_WIDTH=1,C_PROBE621_WIDTH=1,C_PROBE622_WIDTH=1,C_PROBE623_WIDTH=1,C_PROBE624_WIDTH=1,C_PROBE625_WIDTH=1,C_PROBE626_WIDTH=1,C_PROBE627_WIDTH=1,C_PROBE628_WIDTH=1,C_PROBE629_WIDTH=1,C_PROBE630_WIDTH=1,C_PROBE631_WIDTH=1,C_PROBE632_WIDTH=1,C_PROBE633_WIDTH=1,C_PROBE634_WIDTH=1,C_PROBE635_WIDTH=1,C_PROBE636_WIDTH=1,C_PROBE637_WIDTH=1,C_PROBE638_WIDTH=1,C_PROBE639_WIDTH=1,C_PROBE640_WIDTH=1,C_PROBE641_WIDTH=1,C_PROBE642_WIDTH=1,C_PROBE643_WIDTH=1,C_PROBE644_WIDTH=1,C_PROBE645_WIDTH=1,C_PROBE646_WIDTH=1,C_PROBE647_WIDTH=1,C_PROBE648_WIDTH=1,C_PROBE649_WIDTH=1,C_PROBE650_WIDTH=1,C_PROBE651_WIDTH=1,C_PROBE652_WIDTH=1,C_PROBE653_WIDTH=1,C_PROBE654_WIDTH=1,C_PROBE655_WIDTH=1,C_PROBE656_WIDTH=1,C_PROBE657_WIDTH=1,C_PROBE658_WIDTH=1,C_PROBE659_WIDTH=1,C_PROBE660_WIDTH=1,C_PROBE661_WIDTH=1,C_PROBE662_WIDTH=1,C_PROBE663_WIDTH=1,C_PROBE664_WIDTH=1,C_PROBE665_WIDTH=1,C_PROBE666_WIDTH=1,C_PROBE667_WIDTH=1,C_PROBE668_WIDTH=1,C_PROBE669_WIDTH=1,C_PROBE670_WIDTH=1,C_PROBE671_WIDTH=1,C_PROBE672_WIDTH=1,C_PROBE673_WIDTH=1,C_PROBE674_WIDTH=1,C_PROBE675_WIDTH=1,C_PROBE676_WIDTH=1,C_PROBE677_WIDTH=1,C_PROBE678_WIDTH=1,C_PROBE679_WIDTH=1,C_PROBE680_WIDTH=1,C_PROBE681_WIDTH=1,C_PROBE682_WIDTH=1,C_PROBE683_WIDTH=1,C_PROBE684_WIDTH=1,C_PROBE685_WIDTH=1,C_PROBE686_WIDTH=1,C_PROBE687_WIDTH=1,C_PROBE688_WIDTH=1,C_PROBE689_WIDTH=1,C_PROBE690_WIDTH=1,C_PROBE691_WIDTH=1,C_PROBE692_WIDTH=1,C_PROBE693_WIDTH=1,C_PROBE694_WIDTH=1,C_PROBE695_WIDTH=1,C_PROBE696_WIDTH=1,C_PROBE697_WIDTH=1,C_PROBE698_WIDTH=1,C_PROBE699_WIDTH=1,C_PROBE700_WIDTH=1,C_PROBE701_WIDTH=1,C_PROBE702_WIDTH=1,C_PROBE703_WIDTH=1,C_PROBE704_WIDTH=1,C_PROBE705_WIDTH=1,C_PROBE706_WIDTH=1,C_PROBE707_WIDTH=1,C_PROBE708_WIDTH=1,C_PROBE709_WIDTH=1,C_PROBE710_WIDTH=1,C_PROBE711_WIDTH=1,C_PROBE712_WIDTH=1,C_PROBE713_WIDTH=1,C_PROBE714_WIDTH=1,C_PROBE715_WIDTH=1,C_PROBE716_WIDTH=1,C_PROBE717_WIDTH=1,C_PROBE718_WIDTH=1,C_PROBE719_WIDTH=1,C_PROBE720_WIDTH=1,C_PROBE721_WIDTH=1,C_PROBE722_WIDTH=1,C_PROBE723_WIDTH=1,C_PROBE724_WIDTH=1,C_PROBE725_WIDTH=1,C_PROBE726_WIDTH=1,C_PROBE727_WIDTH=1,C_PROBE728_WIDTH=1,C_PROBE729_WIDTH=1,C_PROBE730_WIDTH=1,C_PROBE731_WIDTH=1,C_PROBE732_WIDTH=1,C_PROBE733_WIDTH=1,C_PROBE734_WIDTH=1,C_PROBE735_WIDTH=1,C_PROBE736_WIDTH=1,C_PROBE737_WIDTH=1,C_PROBE738_WIDTH=1,C_PROBE739_WIDTH=1,C_PROBE740_WIDTH=1,C_PROBE741_WIDTH=1,C_PROBE742_WIDTH=1,C_PROBE743_WIDTH=1,C_PROBE744_WIDTH=1,C_PROBE745_WIDTH=1,C_PROBE746_WIDTH=1,C_PROBE747_WIDTH=1,C_PROBE748_WIDTH=1,C_PROBE749_WIDTH=1,C_PROBE750_WIDTH=1,C_PROBE751_WIDTH=1,C_PROBE752_WIDTH=1,C_PROBE753_WIDTH=1,C_PROBE754_WIDTH=1,C_PROBE755_WIDTH=1,C_PROBE756_WIDTH=1,C_PROBE757_WIDTH=1,C_PROBE758_WIDTH=1,C_PROBE759_WIDTH=1,C_PROBE760_WIDTH=1,C_PROBE761_WIDTH=1,C_PROBE762_WIDTH=1,C_PROBE763_WIDTH=1,C_PROBE764_WIDTH=1,C_PROBE765_WIDTH=1,C_PROBE766_WIDTH=1,C_PROBE767_WIDTH=1,C_PROBE768_WIDTH=1,C_PROBE769_WIDTH=1,C_PROBE770_WIDTH=1,C_PROBE771_WIDTH=1,C_PROBE772_WIDTH=1,C_PROBE773_WIDTH=1,C_PROBE774_WIDTH=1,C_PROBE775_WIDTH=1,C_PROBE776_WIDTH=1,C_PROBE777_WIDTH=1,C_PROBE778_WIDTH=1,C_PROBE779_WIDTH=1,C_PROBE780_WIDTH=1,C_PROBE781_WIDTH=1,C_PROBE782_WIDTH=1,C_PROBE783_WIDTH=1,C_PROBE784_WIDTH=1,C_PROBE785_WIDTH=1,C_PROBE786_WIDTH=1,C_PROBE787_WIDTH=1,C_PROBE788_WIDTH=1,C_PROBE789_WIDTH=1,C_PROBE790_WIDTH=1,C_PROBE791_WIDTH=1,C_PROBE792_WIDTH=1,C_PROBE793_WIDTH=1,C_PROBE794_WIDTH=1,C_PROBE795_WIDTH=1,C_PROBE796_WIDTH=1,C_PROBE797_WIDTH=1,C_PROBE798_WIDTH=1,C_PROBE799_WIDTH=1,C_PROBE800_WIDTH=1,C_PROBE801_WIDTH=1,C_PROBE802_WIDTH=1,C_PROBE803_WIDTH=1,C_PROBE804_WIDTH=1,C_PROBE805_WIDTH=1,C_PROBE806_WIDTH=1,C_PROBE807_WIDTH=1,C_PROBE808_WIDTH=1,C_PROBE809_WIDTH=1,C_PROBE810_WIDTH=1,C_PROBE811_WIDTH=1,C_PROBE812_WIDTH=1,C_PROBE813_WIDTH=1,C_PROBE814_WIDTH=1,C_PROBE815_WIDTH=1,C_PROBE816_WIDTH=1,C_PROBE817_WIDTH=1,C_PROBE818_WIDTH=1,C_PROBE819_WIDTH=1,C_PROBE820_WIDTH=1,C_PROBE821_WIDTH=1,C_PROBE822_WIDTH=1,C_PROBE823_WIDTH=1,C_PROBE824_WIDTH=1,C_PROBE825_WIDTH=1,C_PROBE826_WIDTH=1,C_PROBE827_WIDTH=1,C_PROBE828_WIDTH=1,C_PROBE829_WIDTH=1,C_PROBE830_WIDTH=1,C_PROBE831_WIDTH=1,C_PROBE832_WIDTH=1,C_PROBE833_WIDTH=1,C_PROBE834_WIDTH=1,C_PROBE835_WIDTH=1,C_PROBE836_WIDTH=1,C_PROBE837_WIDTH=1,C_PROBE838_WIDTH=1,C_PROBE839_WIDTH=1,C_PROBE840_WIDTH=1,C_PROBE841_WIDTH=1,C_PROBE842_WIDTH=1,C_PROBE843_WIDTH=1,C_PROBE844_WIDTH=1,C_PROBE845_WIDTH=1,C_PROBE846_WIDTH=1,C_PROBE847_WIDTH=1,C_PROBE848_WIDTH=1,C_PROBE849_WIDTH=1,C_PROBE850_WIDTH=1,C_PROBE851_WIDTH=1,C_PROBE852_WIDTH=1,C_PROBE853_WIDTH=1,C_PROBE854_WIDTH=1,C_PROBE855_WIDTH=1,C_PROBE856_WIDTH=1,C_PROBE857_WIDTH=1,C_PROBE858_WIDTH=1,C_PROBE859_WIDTH=1,C_PROBE860_WIDTH=1,C_PROBE861_WIDTH=1,C_PROBE862_WIDTH=1,C_PROBE863_WIDTH=1,C_PROBE864_WIDTH=1,C_PROBE865_WIDTH=1,C_PROBE866_WIDTH=1,C_PROBE867_WIDTH=1,C_PROBE868_WIDTH=1,C_PROBE869_WIDTH=1,C_PROBE870_WIDTH=1,C_PROBE871_WIDTH=1,C_PROBE872_WIDTH=1,C_PROBE873_WIDTH=1,C_PROBE874_WIDTH=1,C_PROBE875_WIDTH=1,C_PROBE876_WIDTH=1,C_PROBE877_WIDTH=1,C_PROBE878_WIDTH=1,C_PROBE879_WIDTH=1,C_PROBE880_WIDTH=1,C_PROBE881_WIDTH=1,C_PROBE882_WIDTH=1,C_PROBE883_WIDTH=1,C_PROBE884_WIDTH=1,C_PROBE885_WIDTH=1,C_PROBE886_WIDTH=1,C_PROBE887_WIDTH=1,C_PROBE888_WIDTH=1,C_PROBE889_WIDTH=1,C_PROBE890_WIDTH=1,C_PROBE891_WIDTH=1,C_PROBE892_WIDTH=1,C_PROBE893_WIDTH=1,C_PROBE894_WIDTH=1,C_PROBE895_WIDTH=1,C_PROBE896_WIDTH=1,C_PROBE897_WIDTH=1,C_PROBE898_WIDTH=1,C_PROBE899_WIDTH=1,C_PROBE900_WIDTH=1,C_PROBE901_WIDTH=1,C_PROBE902_WIDTH=1,C_PROBE903_WIDTH=1,C_PROBE904_WIDTH=1,C_PROBE905_WIDTH=1,C_PROBE906_WIDTH=1,C_PROBE907_WIDTH=1,C_PROBE908_WIDTH=1,C_PROBE909_WIDTH=1,C_PROBE910_WIDTH=1,C_PROBE911_WIDTH=1,C_PROBE912_WIDTH=1,C_PROBE913_WIDTH=1,C_PROBE914_WIDTH=1,C_PROBE915_WIDTH=1,C_PROBE916_WIDTH=1,C_PROBE917_WIDTH=1,C_PROBE918_WIDTH=1,C_PROBE919_WIDTH=1,C_PROBE920_WIDTH=1,C_PROBE921_WIDTH=1,C_PROBE922_WIDTH=1,C_PROBE923_WIDTH=1,C_PROBE924_WIDTH=1,C_PROBE925_WIDTH=1,C_PROBE926_WIDTH=1,C_PROBE927_WIDTH=1,C_PROBE928_WIDTH=1,C_PROBE929_WIDTH=1,C_PROBE930_WIDTH=1,C_PROBE931_WIDTH=1,C_PROBE932_WIDTH=1,C_PROBE933_WIDTH=1,C_PROBE934_WIDTH=1,C_PROBE935_WIDTH=1,C_PROBE936_WIDTH=1,C_PROBE937_WIDTH=1,C_PROBE938_WIDTH=1,C_PROBE939_WIDTH=1,C_PROBE940_WIDTH=1,C_PROBE941_WIDTH=1,C_PROBE942_WIDTH=1,C_PROBE943_WIDTH=1,C_PROBE944_WIDTH=1,C_PROBE945_WIDTH=1,C_PROBE946_WIDTH=1,C_PROBE947_WIDTH=1,C_PROBE948_WIDTH=1,C_PROBE949_WIDTH=1,C_PROBE950_WIDTH=1,C_PROBE951_WIDTH=1,C_PROBE952_WIDTH=1,C_PROBE953_WIDTH=1,C_PROBE954_WIDTH=1,C_PROBE955_WIDTH=1,C_PROBE956_WIDTH=1,C_PROBE957_WIDTH=1,C_PROBE958_WIDTH=1,C_PROBE959_WIDTH=1,C_PROBE960_WIDTH=1,C_PROBE961_WIDTH=1,C_PROBE962_WIDTH=1,C_PROBE963_WIDTH=1,C_PROBE964_WIDTH=1,C_PROBE965_WIDTH=1,C_PROBE966_WIDTH=1,C_PROBE967_WIDTH=1,C_PROBE968_WIDTH=1,C_PROBE969_WIDTH=1,C_PROBE970_WIDTH=1,C_PROBE971_WIDTH=1,C_PROBE972_WIDTH=1,C_PROBE973_WIDTH=1,C_PROBE974_WIDTH=1,C_PROBE975_WIDTH=1,C_PROBE976_WIDTH=1,C_PROBE977_WIDTH=1,C_PROBE978_WIDTH=1,C_PROBE979_WIDTH=1,C_PROBE980_WIDTH=1,C_PROBE981_WIDTH=1,C_PROBE982_WIDTH=1,C_PROBE983_WIDTH=1,C_PROBE984_WIDTH=1,C_PROBE985_WIDTH=1,C_PROBE986_WIDTH=1,C_PROBE987_WIDTH=1,C_PROBE988_WIDTH=1,C_PROBE989_WIDTH=1,C_PROBE990_WIDTH=1,C_PROBE991_WIDTH=1,C_PROBE992_WIDTH=1,C_PROBE993_WIDTH=1,C_PROBE994_WIDTH=1,C_PROBE995_WIDTH=1,C_PROBE996_WIDTH=1,C_PROBE997_WIDTH=1,C_PROBE998_WIDTH=1,C_PROBE999_WIDTH=1,C_PROBE1000_WIDTH=1,C_PROBE1001_WIDTH=1,C_PROBE1002_WIDTH=1,C_PROBE1003_WIDTH=1,C_PROBE1004_WIDTH=1,C_PROBE1005_WIDTH=1,C_PROBE1006_WIDTH=1,C_PROBE1007_WIDTH=1,C_PROBE1008_WIDTH=1,C_PROBE1009_WIDTH=1,C_PROBE1010_WIDTH=1,C_PROBE1011_WIDTH=1,C_PROBE1012_WIDTH=1,C_PROBE1013_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1}" *)
module system_ila_0_0 (
clk,
probe0,
probe1,
probe2,
probe3
);
input clk;
input [0 : 0] probe0;
input [0 : 0] probe1;
input [0 : 0] probe2;
input [0 : 0] probe3;
wire [16:0] sl_oport0;
wire [36:0] sl_iport0;
ila_v5_0_ila #(
.C_XLNX_HW_PROBE_INFO("NUM_OF_PROBES=4,DATA_DEPTH=1024,PROBE0_WIDTH=1,PROBE0_MU_CNT=1,PROBE1_WIDTH=1,PROBE1_MU_CNT=1,PROBE2_WIDTH=1,PROBE2_MU_CNT=1,PROBE3_WIDTH=1,PROBE3_MU_CNT=1,PROBE4_WIDTH=1,PROBE4_MU_CNT=1,PROBE5_WIDTH=1,PROBE5_MU_CNT=1,PROBE6_WIDTH=1,PROBE6_MU_CNT=1,PROBE7_WIDTH=1,PROBE7_MU_CNT=1,PROBE8_WIDTH=1,PROBE8_MU_CNT=1,PROBE9_WIDTH=1,PROBE9_MU_CNT=1,PROBE10_WIDTH=1,PROBE10_MU_CNT=1,PROBE11_WIDTH=1,PROBE11_MU_CNT=1,PROBE12_WIDTH=1,PROBE12_MU_CNT=1,PROBE13_WIDTH=1,PROBE13_MU_CNT=1,PROBE14_WIDTH=1,PROBE14_MU_CNT=1,PROBE15_WIDTH=1,PROBE15_MU_CNT=1,PROBE16_WIDTH=1,PROBE16_MU_CNT=1,PROBE17_WIDTH=1,PROBE17_MU_CNT=1,PROBE18_WIDTH=1,PROBE18_MU_CNT=1,PROBE19_WIDTH=1,PROBE19_MU_CNT=1,PROBE20_WIDTH=1,PROBE20_MU_CNT=1,PROBE21_WIDTH=1,PROBE21_MU_CNT=1,PROBE22_WIDTH=1,PROBE22_MU_CNT=1,PROBE23_WIDTH=1,PROBE23_MU_CNT=1,PROBE24_WIDTH=1,PROBE24_MU_CNT=1,PROBE25_WIDTH=1,PROBE25_MU_CNT=1,PROBE26_WIDTH=1,PROBE26_MU_CNT=1,PROBE27_WIDTH=1,PROBE27_MU_CNT=1,PROBE28_WIDTH=1,PROBE28_MU_CNT=1,PROBE29_WIDTH=1,PROBE29_MU_CNT=1,PROBE30_WIDTH=1,PROBE30_MU_CNT=1,PROBE31_WIDTH=1,PROBE31_MU_CNT=1,PROBE32_WIDTH=1,PROBE32_MU_CNT=1,PROBE33_WIDTH=1,PROBE33_MU_CNT=1,PROBE34_WIDTH=1,PROBE34_MU_CNT=1,PROBE35_WIDTH=1,PROBE35_MU_CNT=1,PROBE36_WIDTH=1,PROBE36_MU_CNT=1,PROBE37_WIDTH=1,PROBE37_MU_CNT=1,PROBE38_WIDTH=1,PROBE38_MU_CNT=1,PROBE39_WIDTH=1,PROBE39_MU_CNT=1,PROBE40_WIDTH=1,PROBE40_MU_CNT=1,PROBE41_WIDTH=1,PROBE41_MU_CNT=1,PROBE42_WIDTH=1,PROBE42_MU_CNT=1,PROBE43_WIDTH=1,PROBE43_MU_CNT=1,PROBE44_WIDTH=1,PROBE44_MU_CNT=1,PROBE45_WIDTH=1,PROBE45_MU_CNT=1,PROBE46_WIDTH=1,PROBE46_MU_CNT=1,PROBE47_WIDTH=1,PROBE47_MU_CNT=1,PROBE48_WIDTH=1,PROBE48_MU_CNT=1,PROBE49_WIDTH=1,PROBE49_MU_CNT=1,PROBE50_WIDTH=1,PROBE50_MU_CNT=1,PROBE51_WIDTH=1,PROBE51_MU_CNT=1,PROBE52_WIDTH=1,PROBE52_MU_CNT=1,PROBE53_WIDTH=1,PROBE53_MU_CNT=1,PROBE54_WIDTH=1,PROBE54_MU_CNT=1,PROBE55_WIDTH=1,PROBE55_MU_CNT=1,PROBE56_WIDTH=1,PROBE56_MU_CNT=1,PROBE57_WIDTH=1,PROBE57_MU_CNT=1,PROBE58_WIDTH=1,PROBE58_MU_CNT=1,PROBE59_WIDTH=1,PROBE59_MU_CNT=1,PROBE60_WIDTH=1,PROBE60_MU_CNT=1,PROBE61_WIDTH=1,PROBE61_MU_CNT=1,PROBE62_WIDTH=1,PROBE62_MU_CNT=1,PROBE63_WIDTH=1,PROBE63_MU_CNT=1,PROBE64_WIDTH=1,PROBE64_MU_CNT=1,PROBE65_WIDTH=1,PROBE65_MU_CNT=1,PROBE66_WIDTH=1,PROBE66_MU_CNT=1,PROBE67_WIDTH=1,PROBE67_MU_CNT=1,PROBE68_WIDTH=1,PROBE68_MU_CNT=1,PROBE69_WIDTH=1,PROBE69_MU_CNT=1,PROBE70_WIDTH=1,PROBE70_MU_CNT=1,PROBE71_WIDTH=1,PROBE71_MU_CNT=1,PROBE72_WIDTH=1,PROBE72_MU_CNT=1,PROBE73_WIDTH=1,PROBE73_MU_CNT=1,PROBE74_WIDTH=1,PROBE74_MU_CNT=1,PROBE75_WIDTH=1,PROBE75_MU_CNT=1,PROBE76_WIDTH=1,PROBE76_MU_CNT=1,PROBE77_WIDTH=1,PROBE77_MU_CNT=1,PROBE78_WIDTH=1,PROBE78_MU_CNT=1,PROBE79_WIDTH=1,PROBE79_MU_CNT=1,PROBE80_WIDTH=1,PROBE80_MU_CNT=1,PROBE81_WIDTH=1,PROBE81_MU_CNT=1,PROBE82_WIDTH=1,PROBE82_MU_CNT=1,PROBE83_WIDTH=1,PROBE83_MU_CNT=1,PROBE84_WIDTH=1,PROBE84_MU_CNT=1,PROBE85_WIDTH=1,PROBE85_MU_CNT=1,PROBE86_WIDTH=1,PROBE86_MU_CNT=1,PROBE87_WIDTH=1,PROBE87_MU_CNT=1,PROBE88_WIDTH=1,PROBE88_MU_CNT=1,PROBE89_WIDTH=1,PROBE89_MU_CNT=1,PROBE90_WIDTH=1,PROBE90_MU_CNT=1,PROBE91_WIDTH=1,PROBE91_MU_CNT=1,PROBE92_WIDTH=1,PROBE92_MU_CNT=1,PROBE93_WIDTH=1,PROBE93_MU_CNT=1,PROBE94_WIDTH=1,PROBE94_MU_CNT=1,PROBE95_WIDTH=1,PROBE95_MU_CNT=1,PROBE96_WIDTH=1,PROBE96_MU_CNT=1,PROBE97_WIDTH=1,PROBE97_MU_CNT=1,PROBE98_WIDTH=1,PROBE98_MU_CNT=1,PROBE99_WIDTH=1,PROBE99_MU_CNT=1,PROBE100_WIDTH=1,PROBE100_MU_CNT=1,PROBE101_WIDTH=1,PROBE101_MU_CNT=1,PROBE102_WIDTH=1,PROBE102_MU_CNT=1,PROBE103_WIDTH=1,PROBE103_MU_CNT=1,PROBE104_WIDTH=1,PROBE104_MU_CNT=1,PROBE105_WIDTH=1,PROBE105_MU_CNT=1,PROBE106_WIDTH=1,PROBE106_MU_CNT=1,PROBE107_WIDTH=1,PROBE107_MU_CNT=1,PROBE108_WIDTH=1,PROBE108_MU_CNT=1,PROBE109_WIDTH=1,PROBE109_MU_CNT=1,PROBE110_WIDTH=1,PROBE110_MU_CNT=1,PROBE111_WIDTH=1,PROBE111_MU_CNT=1,PROBE112_WIDTH=1,PROBE112_MU_CNT=1,PROBE113_WIDTH=1,PROBE113_MU_CNT=1,PROBE114_WIDTH=1,PROBE114_MU_CNT=1,PROBE115_WIDTH=1,PROBE115_MU_CNT=1,PROBE116_WIDTH=1,PROBE116_MU_CNT=1,PROBE117_WIDTH=1,PROBE117_MU_CNT=1,PROBE118_WIDTH=1,PROBE118_MU_CNT=1,PROBE119_WIDTH=1,PROBE119_MU_CNT=1,PROBE120_WIDTH=1,PROBE120_MU_CNT=1,PROBE121_WIDTH=1,PROBE121_MU_CNT=1,PROBE122_WIDTH=1,PROBE122_MU_CNT=1,PROBE123_WIDTH=1,PROBE123_MU_CNT=1,PROBE124_WIDTH=1,PROBE124_MU_CNT=1,PROBE125_WIDTH=1,PROBE125_MU_CNT=1,PROBE126_WIDTH=1,PROBE126_MU_CNT=1,PROBE127_WIDTH=1,PROBE127_MU_CNT=1,PROBE128_WIDTH=1,PROBE128_MU_CNT=1,PROBE129_WIDTH=1,PROBE129_MU_CNT=1,PROBE130_WIDTH=1,PROBE130_MU_CNT=1,PROBE131_WIDTH=1,PROBE131_MU_CNT=1,PROBE132_WIDTH=1,PROBE132_MU_CNT=1,PROBE133_WIDTH=1,PROBE133_MU_CNT=1,PROBE134_WIDTH=1,PROBE134_MU_CNT=1,PROBE135_WIDTH=1,PROBE135_MU_CNT=1,PROBE136_WIDTH=1,PROBE136_MU_CNT=1,PROBE137_WIDTH=1,PROBE137_MU_CNT=1,PROBE138_WIDTH=1,PROBE138_MU_CNT=1,PROBE139_WIDTH=1,PROBE139_MU_CNT=1,PROBE140_WIDTH=1,PROBE140_MU_CNT=1,PROBE141_WIDTH=1,PROBE141_MU_CNT=1,PROBE142_WIDTH=1,PROBE142_MU_CNT=1,PROBE143_WIDTH=1,PROBE143_MU_CNT=1,PROBE144_WIDTH=1,PROBE144_MU_CNT=1,PROBE145_WIDTH=1,PROBE145_MU_CNT=1,PROBE146_WIDTH=1,PROBE146_MU_CNT=1,PROBE147_WIDTH=1,PROBE147_MU_CNT=1,PROBE148_WIDTH=1,PROBE148_MU_CNT=1,PROBE149_WIDTH=1,PROBE149_MU_CNT=1,PROBE150_WIDTH=1,PROBE150_MU_CNT=1,PROBE151_WIDTH=1,PROBE151_MU_CNT=1,PROBE152_WIDTH=1,PROBE152_MU_CNT=1,PROBE153_WIDTH=1,PROBE153_MU_CNT=1,PROBE154_WIDTH=1,PROBE154_MU_CNT=1,PROBE155_WIDTH=1,PROBE155_MU_CNT=1,PROBE156_WIDTH=1,PROBE156_MU_CNT=1,PROBE157_WIDTH=1,PROBE157_MU_CNT=1,PROBE158_WIDTH=1,PROBE158_MU_CNT=1,PROBE159_WIDTH=1,PROBE159_MU_CNT=1,PROBE160_WIDTH=1,PROBE160_MU_CNT=1,PROBE161_WIDTH=1,PROBE161_MU_CNT=1,PROBE162_WIDTH=1,PROBE162_MU_CNT=1,PROBE163_WIDTH=1,PROBE163_MU_CNT=1,PROBE164_WIDTH=1,PROBE164_MU_CNT=1,PROBE165_WIDTH=1,PROBE165_MU_CNT=1,PROBE166_WIDTH=1,PROBE166_MU_CNT=1,PROBE167_WIDTH=1,PROBE167_MU_CNT=1,PROBE168_WIDTH=1,PROBE168_MU_CNT=1,PROBE169_WIDTH=1,PROBE169_MU_CNT=1,PROBE170_WIDTH=1,PROBE170_MU_CNT=1,PROBE171_WIDTH=1,PROBE171_MU_CNT=1,PROBE172_WIDTH=1,PROBE172_MU_CNT=1,PROBE173_WIDTH=1,PROBE173_MU_CNT=1,PROBE174_WIDTH=1,PROBE174_MU_CNT=1,PROBE175_WIDTH=1,PROBE175_MU_CNT=1,PROBE176_WIDTH=1,PROBE176_MU_CNT=1,PROBE177_WIDTH=1,PROBE177_MU_CNT=1,PROBE178_WIDTH=1,PROBE178_MU_CNT=1,PROBE179_WIDTH=1,PROBE179_MU_CNT=1,PROBE180_WIDTH=1,PROBE180_MU_CNT=1,PROBE181_WIDTH=1,PROBE181_MU_CNT=1,PROBE182_WIDTH=1,PROBE182_MU_CNT=1,PROBE183_WIDTH=1,PROBE183_MU_CNT=1,PROBE184_WIDTH=1,PROBE184_MU_CNT=1,PROBE185_WIDTH=1,PROBE185_MU_CNT=1,PROBE186_WIDTH=1,PROBE186_MU_CNT=1,PROBE187_WIDTH=1,PROBE187_MU_CNT=1,PROBE188_WIDTH=1,PROBE188_MU_CNT=1,PROBE189_WIDTH=1,PROBE189_MU_CNT=1,PROBE190_WIDTH=1,PROBE190_MU_CNT=1,PROBE191_WIDTH=1,PROBE191_MU_CNT=1,PROBE192_WIDTH=1,PROBE192_MU_CNT=1,PROBE193_WIDTH=1,PROBE193_MU_CNT=1,PROBE194_WIDTH=1,PROBE194_MU_CNT=1,PROBE195_WIDTH=1,PROBE195_MU_CNT=1,PROBE196_WIDTH=1,PROBE196_MU_CNT=1,PROBE197_WIDTH=1,PROBE197_MU_CNT=1,PROBE198_WIDTH=1,PROBE198_MU_CNT=1,PROBE199_WIDTH=1,PROBE199_MU_CNT=1,PROBE200_WIDTH=1,PROBE200_MU_CNT=1,PROBE201_WIDTH=1,PROBE201_MU_CNT=1,PROBE202_WIDTH=1,PROBE202_MU_CNT=1,PROBE203_WIDTH=1,PROBE203_MU_CNT=1,PROBE204_WIDTH=1,PROBE204_MU_CNT=1,PROBE205_WIDTH=1,PROBE205_MU_CNT=1,PROBE206_WIDTH=1,PROBE206_MU_CNT=1,PROBE207_WIDTH=1,PROBE207_MU_CNT=1,PROBE208_WIDTH=1,PROBE208_MU_CNT=1,PROBE209_WIDTH=1,PROBE209_MU_CNT=1,PROBE210_WIDTH=1,PROBE210_MU_CNT=1,PROBE211_WIDTH=1,PROBE211_MU_CNT=1,PROBE212_WIDTH=1,PROBE212_MU_CNT=1,PROBE213_WIDTH=1,PROBE213_MU_CNT=1,PROBE214_WIDTH=1,PROBE214_MU_CNT=1,PROBE215_WIDTH=1,PROBE215_MU_CNT=1,PROBE216_WIDTH=1,PROBE216_MU_CNT=1,PROBE217_WIDTH=1,PROBE217_MU_CNT=1,PROBE218_WIDTH=1,PROBE218_MU_CNT=1,PROBE219_WIDTH=1,PROBE219_MU_CNT=1,PROBE220_WIDTH=1,PROBE220_MU_CNT=1,PROBE221_WIDTH=1,PROBE221_MU_CNT=1,PROBE222_WIDTH=1,PROBE222_MU_CNT=1,PROBE223_WIDTH=1,PROBE223_MU_CNT=1,PROBE224_WIDTH=1,PROBE224_MU_CNT=1,PROBE225_WIDTH=1,PROBE225_MU_CNT=1,PROBE226_WIDTH=1,PROBE226_MU_CNT=1,PROBE227_WIDTH=1,PROBE227_MU_CNT=1,PROBE228_WIDTH=1,PROBE228_MU_CNT=1,PROBE229_WIDTH=1,PROBE229_MU_CNT=1,PROBE230_WIDTH=1,PROBE230_MU_CNT=1,PROBE231_WIDTH=1,PROBE231_MU_CNT=1,PROBE232_WIDTH=1,PROBE232_MU_CNT=1,PROBE233_WIDTH=1,PROBE233_MU_CNT=1,PROBE234_WIDTH=1,PROBE234_MU_CNT=1,PROBE235_WIDTH=1,PROBE235_MU_CNT=1,PROBE236_WIDTH=1,PROBE236_MU_CNT=1,PROBE237_WIDTH=1,PROBE237_MU_CNT=1,PROBE238_WIDTH=1,PROBE238_MU_CNT=1,PROBE239_WIDTH=1,PROBE239_MU_CNT=1,PROBE240_WIDTH=1,PROBE240_MU_CNT=1,PROBE241_WIDTH=1,PROBE241_MU_CNT=1,PROBE242_WIDTH=1,PROBE242_MU_CNT=1,PROBE243_WIDTH=1,PROBE243_MU_CNT=1,PROBE244_WIDTH=1,PROBE244_MU_CNT=1,PROBE245_WIDTH=1,PROBE245_MU_CNT=1,PROBE246_WIDTH=1,PROBE246_MU_CNT=1,PROBE247_WIDTH=1,PROBE247_MU_CNT=1,PROBE248_WIDTH=1,PROBE248_MU_CNT=1,PROBE249_WIDTH=1,PROBE249_MU_CNT=1,PROBE250_WIDTH=1,PROBE250_MU_CNT=1,PROBE251_WIDTH=1,PROBE251_MU_CNT=1,PROBE252_WIDTH=1,PROBE252_MU_CNT=1,PROBE253_WIDTH=1,PROBE253_MU_CNT=1,PROBE254_WIDTH=1,PROBE254_MU_CNT=1,PROBE255_WIDTH=1,PROBE255_MU_CNT=1,PROBE256_WIDTH=1,PROBE256_MU_CNT=1,PROBE257_WIDTH=1,PROBE257_MU_CNT=1,PROBE258_WIDTH=1,PROBE258_MU_CNT=1,PROBE259_WIDTH=1,PROBE259_MU_CNT=1,PROBE260_WIDTH=1,PROBE260_MU_CNT=1,PROBE261_WIDTH=1,PROBE261_MU_CNT=1,PROBE262_WIDTH=1,PROBE262_MU_CNT=1,PROBE263_WIDTH=1,PROBE263_MU_CNT=1,PROBE264_WIDTH=1,PROBE264_MU_CNT=1,PROBE265_WIDTH=1,PROBE265_MU_CNT=1,PROBE266_WIDTH=1,PROBE266_MU_CNT=1,PROBE267_WIDTH=1,PROBE267_MU_CNT=1,PROBE268_WIDTH=1,PROBE268_MU_CNT=1,PROBE269_WIDTH=1,PROBE269_MU_CNT=1,PROBE270_WIDTH=1,PROBE270_MU_CNT=1,PROBE271_WIDTH=1,PROBE271_MU_CNT=1,PROBE272_WIDTH=1,PROBE272_MU_CNT=1,PROBE273_WIDTH=1,PROBE273_MU_CNT=1,PROBE274_WIDTH=1,PROBE274_MU_CNT=1,PROBE275_WIDTH=1,PROBE275_MU_CNT=1,PROBE276_WIDTH=1,PROBE276_MU_CNT=1,PROBE277_WIDTH=1,PROBE277_MU_CNT=1,PROBE278_WIDTH=1,PROBE278_MU_CNT=1,PROBE279_WIDTH=1,PROBE279_MU_CNT=1,PROBE280_WIDTH=1,PROBE280_MU_CNT=1,PROBE281_WIDTH=1,PROBE281_MU_CNT=1,PROBE282_WIDTH=1,PROBE282_MU_CNT=1,PROBE283_WIDTH=1,PROBE283_MU_CNT=1,PROBE284_WIDTH=1,PROBE284_MU_CNT=1,PROBE285_WIDTH=1,PROBE285_MU_CNT=1,PROBE286_WIDTH=1,PROBE286_MU_CNT=1,PROBE287_WIDTH=1,PROBE287_MU_CNT=1,PROBE288_WIDTH=1,PROBE288_MU_CNT=1,PROBE289_WIDTH=1,PROBE289_MU_CNT=1,PROBE290_WIDTH=1,PROBE290_MU_CNT=1,PROBE291_WIDTH=1,PROBE291_MU_CNT=1,PROBE292_WIDTH=1,PROBE292_MU_CNT=1,PROBE293_WIDTH=1,PROBE293_MU_CNT=1,PROBE294_WIDTH=1,PROBE294_MU_CNT=1,PROBE295_WIDTH=1,PROBE295_MU_CNT=1,PROBE296_WIDTH=1,PROBE296_MU_CNT=1,PROBE297_WIDTH=1,PROBE297_MU_CNT=1,PROBE298_WIDTH=1,PROBE298_MU_CNT=1,PROBE299_WIDTH=1,PROBE299_MU_CNT=1,PROBE300_WIDTH=1,PROBE300_MU_CNT=1,PROBE301_WIDTH=1,PROBE301_MU_CNT=1,PROBE302_WIDTH=1,PROBE302_MU_CNT=1,PROBE303_WIDTH=1,PROBE303_MU_CNT=1,PROBE304_WIDTH=1,PROBE304_MU_CNT=1,PROBE305_WIDTH=1,PROBE305_MU_CNT=1,PROBE306_WIDTH=1,PROBE306_MU_CNT=1,PROBE307_WIDTH=1,PROBE307_MU_CNT=1,PROBE308_WIDTH=1,PROBE308_MU_CNT=1,PROBE309_WIDTH=1,PROBE309_MU_CNT=1,PROBE310_WIDTH=1,PROBE310_MU_CNT=1,PROBE311_WIDTH=1,PROBE311_MU_CNT=1,PROBE312_WIDTH=1,PROBE312_MU_CNT=1,PROBE313_WIDTH=1,PROBE313_MU_CNT=1,PROBE314_WIDTH=1,PROBE314_MU_CNT=1,PROBE315_WIDTH=1,PROBE315_MU_CNT=1,PROBE316_WIDTH=1,PROBE316_MU_CNT=1,PROBE317_WIDTH=1,PROBE317_MU_CNT=1,PROBE318_WIDTH=1,PROBE318_MU_CNT=1,PROBE319_WIDTH=1,PROBE319_MU_CNT=1,PROBE320_WIDTH=1,PROBE320_MU_CNT=1,PROBE321_WIDTH=1,PROBE321_MU_CNT=1,PROBE322_WIDTH=1,PROBE322_MU_CNT=1,PROBE323_WIDTH=1,PROBE323_MU_CNT=1,PROBE324_WIDTH=1,PROBE324_MU_CNT=1,PROBE325_WIDTH=1,PROBE325_MU_CNT=1,PROBE326_WIDTH=1,PROBE326_MU_CNT=1,PROBE327_WIDTH=1,PROBE327_MU_CNT=1,PROBE328_WIDTH=1,PROBE328_MU_CNT=1,PROBE329_WIDTH=1,PROBE329_MU_CNT=1,PROBE330_WIDTH=1,PROBE330_MU_CNT=1,PROBE331_WIDTH=1,PROBE331_MU_CNT=1,PROBE332_WIDTH=1,PROBE332_MU_CNT=1,PROBE333_WIDTH=1,PROBE333_MU_CNT=1,PROBE334_WIDTH=1,PROBE334_MU_CNT=1,PROBE335_WIDTH=1,PROBE335_MU_CNT=1,PROBE336_WIDTH=1,PROBE336_MU_CNT=1,PROBE337_WIDTH=1,PROBE337_MU_CNT=1,PROBE338_WIDTH=1,PROBE338_MU_CNT=1,PROBE339_WIDTH=1,PROBE339_MU_CNT=1,PROBE340_WIDTH=1,PROBE340_MU_CNT=1,PROBE341_WIDTH=1,PROBE341_MU_CNT=1,PROBE342_WIDTH=1,PROBE342_MU_CNT=1,PROBE343_WIDTH=1,PROBE343_MU_CNT=1,PROBE344_WIDTH=1,PROBE344_MU_CNT=1,PROBE345_WIDTH=1,PROBE345_MU_CNT=1,PROBE346_WIDTH=1,PROBE346_MU_CNT=1,PROBE347_WIDTH=1,PROBE347_MU_CNT=1,PROBE348_WIDTH=1,PROBE348_MU_CNT=1,PROBE349_WIDTH=1,PROBE349_MU_CNT=1,PROBE350_WIDTH=1,PROBE350_MU_CNT=1,PROBE351_WIDTH=1,PROBE351_MU_CNT=1,PROBE352_WIDTH=1,PROBE352_MU_CNT=1,PROBE353_WIDTH=1,PROBE353_MU_CNT=1,PROBE354_WIDTH=1,PROBE354_MU_CNT=1,PROBE355_WIDTH=1,PROBE355_MU_CNT=1,PROBE356_WIDTH=1,PROBE356_MU_CNT=1,PROBE357_WIDTH=1,PROBE357_MU_CNT=1,PROBE358_WIDTH=1,PROBE358_MU_CNT=1,PROBE359_WIDTH=1,PROBE359_MU_CNT=1,PROBE360_WIDTH=1,PROBE360_MU_CNT=1,PROBE361_WIDTH=1,PROBE361_MU_CNT=1,PROBE362_WIDTH=1,PROBE362_MU_CNT=1,PROBE363_WIDTH=1,PROBE363_MU_CNT=1,PROBE364_WIDTH=1,PROBE364_MU_CNT=1,PROBE365_WIDTH=1,PROBE365_MU_CNT=1,PROBE366_WIDTH=1,PROBE366_MU_CNT=1,PROBE367_WIDTH=1,PROBE367_MU_CNT=1,PROBE368_WIDTH=1,PROBE368_MU_CNT=1,PROBE369_WIDTH=1,PROBE369_MU_CNT=1,PROBE370_WIDTH=1,PROBE370_MU_CNT=1,PROBE371_WIDTH=1,PROBE371_MU_CNT=1,PROBE372_WIDTH=1,PROBE372_MU_CNT=1,PROBE373_WIDTH=1,PROBE373_MU_CNT=1,PROBE374_WIDTH=1,PROBE374_MU_CNT=1,PROBE375_WIDTH=1,PROBE375_MU_CNT=1,PROBE376_WIDTH=1,PROBE376_MU_CNT=1,PROBE377_WIDTH=1,PROBE377_MU_CNT=1,PROBE378_WIDTH=1,PROBE378_MU_CNT=1,PROBE379_WIDTH=1,PROBE379_MU_CNT=1,PROBE380_WIDTH=1,PROBE380_MU_CNT=1,PROBE381_WIDTH=1,PROBE381_MU_CNT=1,PROBE382_WIDTH=1,PROBE382_MU_CNT=1,PROBE383_WIDTH=1,PROBE383_MU_CNT=1,PROBE384_WIDTH=1,PROBE384_MU_CNT=1,PROBE385_WIDTH=1,PROBE385_MU_CNT=1,PROBE386_WIDTH=1,PROBE386_MU_CNT=1,PROBE387_WIDTH=1,PROBE387_MU_CNT=1,PROBE388_WIDTH=1,PROBE388_MU_CNT=1,PROBE389_WIDTH=1,PROBE389_MU_CNT=1,PROBE390_WIDTH=1,PROBE390_MU_CNT=1,PROBE391_WIDTH=1,PROBE391_MU_CNT=1,PROBE392_WIDTH=1,PROBE392_MU_CNT=1,PROBE393_WIDTH=1,PROBE393_MU_CNT=1,PROBE394_WIDTH=1,PROBE394_MU_CNT=1,PROBE395_WIDTH=1,PROBE395_MU_CNT=1,PROBE396_WIDTH=1,PROBE396_MU_CNT=1,PROBE397_WIDTH=1,PROBE397_MU_CNT=1,PROBE398_WIDTH=1,PROBE398_MU_CNT=1,PROBE399_WIDTH=1,PROBE399_MU_CNT=1,PROBE400_WIDTH=1,PROBE400_MU_CNT=1,PROBE401_WIDTH=1,PROBE401_MU_CNT=1,PROBE402_WIDTH=1,PROBE402_MU_CNT=1,PROBE403_WIDTH=1,PROBE403_MU_CNT=1,PROBE404_WIDTH=1,PROBE404_MU_CNT=1,PROBE405_WIDTH=1,PROBE405_MU_CNT=1,PROBE406_WIDTH=1,PROBE406_MU_CNT=1,PROBE407_WIDTH=1,PROBE407_MU_CNT=1,PROBE408_WIDTH=1,PROBE408_MU_CNT=1,PROBE409_WIDTH=1,PROBE409_MU_CNT=1,PROBE410_WIDTH=1,PROBE410_MU_CNT=1,PROBE411_WIDTH=1,PROBE411_MU_CNT=1,PROBE412_WIDTH=1,PROBE412_MU_CNT=1,PROBE413_WIDTH=1,PROBE413_MU_CNT=1,PROBE414_WIDTH=1,PROBE414_MU_CNT=1,PROBE415_WIDTH=1,PROBE415_MU_CNT=1,PROBE416_WIDTH=1,PROBE416_MU_CNT=1,PROBE417_WIDTH=1,PROBE417_MU_CNT=1,PROBE418_WIDTH=1,PROBE418_MU_CNT=1,PROBE419_WIDTH=1,PROBE419_MU_CNT=1,PROBE420_WIDTH=1,PROBE420_MU_CNT=1,PROBE421_WIDTH=1,PROBE421_MU_CNT=1,PROBE422_WIDTH=1,PROBE422_MU_CNT=1,PROBE423_WIDTH=1,PROBE423_MU_CNT=1,PROBE424_WIDTH=1,PROBE424_MU_CNT=1,PROBE425_WIDTH=1,PROBE425_MU_CNT=1,PROBE426_WIDTH=1,PROBE426_MU_CNT=1,PROBE427_WIDTH=1,PROBE427_MU_CNT=1,PROBE428_WIDTH=1,PROBE428_MU_CNT=1,PROBE429_WIDTH=1,PROBE429_MU_CNT=1,PROBE430_WIDTH=1,PROBE430_MU_CNT=1,PROBE431_WIDTH=1,PROBE431_MU_CNT=1,PROBE432_WIDTH=1,PROBE432_MU_CNT=1,PROBE433_WIDTH=1,PROBE433_MU_CNT=1,PROBE434_WIDTH=1,PROBE434_MU_CNT=1,PROBE435_WIDTH=1,PROBE435_MU_CNT=1,PROBE436_WIDTH=1,PROBE436_MU_CNT=1,PROBE437_WIDTH=1,PROBE437_MU_CNT=1,PROBE438_WIDTH=1,PROBE438_MU_CNT=1,PROBE439_WIDTH=1,PROBE439_MU_CNT=1,PROBE440_WIDTH=1,PROBE440_MU_CNT=1,PROBE441_WIDTH=1,PROBE441_MU_CNT=1,PROBE442_WIDTH=1,PROBE442_MU_CNT=1,PROBE443_WIDTH=1,PROBE443_MU_CNT=1,PROBE444_WIDTH=1,PROBE444_MU_CNT=1,PROBE445_WIDTH=1,PROBE445_MU_CNT=1,PROBE446_WIDTH=1,PROBE446_MU_CNT=1,PROBE447_WIDTH=1,PROBE447_MU_CNT=1,PROBE448_WIDTH=1,PROBE448_MU_CNT=1,PROBE449_WIDTH=1,PROBE449_MU_CNT=1,PROBE450_WIDTH=1,PROBE450_MU_CNT=1,PROBE451_WIDTH=1,PROBE451_MU_CNT=1,PROBE452_WIDTH=1,PROBE452_MU_CNT=1,PROBE453_WIDTH=1,PROBE453_MU_CNT=1,PROBE454_WIDTH=1,PROBE454_MU_CNT=1,PROBE455_WIDTH=1,PROBE455_MU_CNT=1,PROBE456_WIDTH=1,PROBE456_MU_CNT=1,PROBE457_WIDTH=1,PROBE457_MU_CNT=1,PROBE458_WIDTH=1,PROBE458_MU_CNT=1,PROBE459_WIDTH=1,PROBE459_MU_CNT=1,PROBE460_WIDTH=1,PROBE460_MU_CNT=1,PROBE461_WIDTH=1,PROBE461_MU_CNT=1,PROBE462_WIDTH=1,PROBE462_MU_CNT=1,PROBE463_WIDTH=1,PROBE463_MU_CNT=1,PROBE464_WIDTH=1,PROBE464_MU_CNT=1,PROBE465_WIDTH=1,PROBE465_MU_CNT=1,PROBE466_WIDTH=1,PROBE466_MU_CNT=1,PROBE467_WIDTH=1,PROBE467_MU_CNT=1,PROBE468_WIDTH=1,PROBE468_MU_CNT=1,PROBE469_WIDTH=1,PROBE469_MU_CNT=1,PROBE470_WIDTH=1,PROBE470_MU_CNT=1,PROBE471_WIDTH=1,PROBE471_MU_CNT=1,PROBE472_WIDTH=1,PROBE472_MU_CNT=1,PROBE473_WIDTH=1,PROBE473_MU_CNT=1,PROBE474_WIDTH=1,PROBE474_MU_CNT=1,PROBE475_WIDTH=1,PROBE475_MU_CNT=1,PROBE476_WIDTH=1,PROBE476_MU_CNT=1,PROBE477_WIDTH=1,PROBE477_MU_CNT=1,PROBE478_WIDTH=1,PROBE478_MU_CNT=1,PROBE479_WIDTH=1,PROBE479_MU_CNT=1,PROBE480_WIDTH=1,PROBE480_MU_CNT=1,PROBE481_WIDTH=1,PROBE481_MU_CNT=1,PROBE482_WIDTH=1,PROBE482_MU_CNT=1,PROBE483_WIDTH=1,PROBE483_MU_CNT=1,PROBE484_WIDTH=1,PROBE484_MU_CNT=1,PROBE485_WIDTH=1,PROBE485_MU_CNT=1,PROBE486_WIDTH=1,PROBE486_MU_CNT=1,PROBE487_WIDTH=1,PROBE487_MU_CNT=1,PROBE488_WIDTH=1,PROBE488_MU_CNT=1,PROBE489_WIDTH=1,PROBE489_MU_CNT=1,PROBE490_WIDTH=1,PROBE490_MU_CNT=1,PROBE491_WIDTH=1,PROBE491_MU_CNT=1,PROBE492_WIDTH=1,PROBE492_MU_CNT=1,PROBE493_WIDTH=1,PROBE493_MU_CNT=1,PROBE494_WIDTH=1,PROBE494_MU_CNT=1,PROBE495_WIDTH=1,PROBE495_MU_CNT=1,PROBE496_WIDTH=1,PROBE496_MU_CNT=1,PROBE497_WIDTH=1,PROBE497_MU_CNT=1,PROBE498_WIDTH=1,PROBE498_MU_CNT=1,PROBE499_WIDTH=1,PROBE499_MU_CNT=1,PROBE500_WIDTH=1,PROBE500_MU_CNT=1,PROBE501_WIDTH=1,PROBE501_MU_CNT=1,PROBE502_WIDTH=1,PROBE502_MU_CNT=1,PROBE503_WIDTH=1,PROBE503_MU_CNT=1,PROBE504_WIDTH=1,PROBE504_MU_CNT=1,PROBE505_WIDTH=1,PROBE505_MU_CNT=1,PROBE506_WIDTH=1,PROBE506_MU_CNT=1,PROBE507_WIDTH=1,PROBE507_MU_CNT=1,PROBE508_WIDTH=1,PROBE508_MU_CNT=1,PROBE509_WIDTH=1,PROBE509_MU_CNT=1,PROBE510_WIDTH=1,PROBE510_MU_CNT=1,PROBE511_WIDTH=1,PROBE511_MU_CNT=1,PROBE512_WIDTH=1,PROBE512_MU_CNT=1,PROBE513_WIDTH=1,PROBE513_MU_CNT=1,PROBE514_WIDTH=1,PROBE514_MU_CNT=1,PROBE515_WIDTH=1,PROBE515_MU_CNT=1,PROBE516_WIDTH=1,PROBE516_MU_CNT=1,PROBE517_WIDTH=1,PROBE517_MU_CNT=1,PROBE518_WIDTH=1,PROBE518_MU_CNT=1,PROBE519_WIDTH=1,PROBE519_MU_CNT=1,PROBE520_WIDTH=1,PROBE520_MU_CNT=1,PROBE521_WIDTH=1,PROBE521_MU_CNT=1,PROBE522_WIDTH=1,PROBE522_MU_CNT=1,PROBE523_WIDTH=1,PROBE523_MU_CNT=1,PROBE524_WIDTH=1,PROBE524_MU_CNT=1,PROBE525_WIDTH=1,PROBE525_MU_CNT=1,PROBE526_WIDTH=1,PROBE526_MU_CNT=1,PROBE527_WIDTH=1,PROBE527_MU_CNT=1,PROBE528_WIDTH=1,PROBE528_MU_CNT=1,PROBE529_WIDTH=1,PROBE529_MU_CNT=1,PROBE530_WIDTH=1,PROBE530_MU_CNT=1,PROBE531_WIDTH=1,PROBE531_MU_CNT=1,PROBE532_WIDTH=1,PROBE532_MU_CNT=1,PROBE533_WIDTH=1,PROBE533_MU_CNT=1,PROBE534_WIDTH=1,PROBE534_MU_CNT=1,PROBE535_WIDTH=1,PROBE535_MU_CNT=1,PROBE536_WIDTH=1,PROBE536_MU_CNT=1,PROBE537_WIDTH=1,PROBE537_MU_CNT=1,PROBE538_WIDTH=1,PROBE538_MU_CNT=1,PROBE539_WIDTH=1,PROBE539_MU_CNT=1,PROBE540_WIDTH=1,PROBE540_MU_CNT=1,PROBE541_WIDTH=1,PROBE541_MU_CNT=1,PROBE542_WIDTH=1,PROBE542_MU_CNT=1,PROBE543_WIDTH=1,PROBE543_MU_CNT=1,PROBE544_WIDTH=1,PROBE544_MU_CNT=1,PROBE545_WIDTH=1,PROBE545_MU_CNT=1,PROBE546_WIDTH=1,PROBE546_MU_CNT=1,PROBE547_WIDTH=1,PROBE547_MU_CNT=1,PROBE548_WIDTH=1,PROBE548_MU_CNT=1,PROBE549_WIDTH=1,PROBE549_MU_CNT=1,PROBE550_WIDTH=1,PROBE550_MU_CNT=1,PROBE551_WIDTH=1,PROBE551_MU_CNT=1,PROBE552_WIDTH=1,PROBE552_MU_CNT=1,PROBE553_WIDTH=1,PROBE553_MU_CNT=1,PROBE554_WIDTH=1,PROBE554_MU_CNT=1,PROBE555_WIDTH=1,PROBE555_MU_CNT=1,PROBE556_WIDTH=1,PROBE556_MU_CNT=1,PROBE557_WIDTH=1,PROBE557_MU_CNT=1,PROBE558_WIDTH=1,PROBE558_MU_CNT=1,PROBE559_WIDTH=1,PROBE559_MU_CNT=1,PROBE560_WIDTH=1,PROBE560_MU_CNT=1,PROBE561_WIDTH=1,PROBE561_MU_CNT=1,PROBE562_WIDTH=1,PROBE562_MU_CNT=1,PROBE563_WIDTH=1,PROBE563_MU_CNT=1,PROBE564_WIDTH=1,PROBE564_MU_CNT=1,PROBE565_WIDTH=1,PROBE565_MU_CNT=1,PROBE566_WIDTH=1,PROBE566_MU_CNT=1,PROBE567_WIDTH=1,PROBE567_MU_CNT=1,PROBE568_WIDTH=1,PROBE568_MU_CNT=1,PROBE569_WIDTH=1,PROBE569_MU_CNT=1,PROBE570_WIDTH=1,PROBE570_MU_CNT=1,PROBE571_WIDTH=1,PROBE571_MU_CNT=1,PROBE572_WIDTH=1,PROBE572_MU_CNT=1,PROBE573_WIDTH=1,PROBE573_MU_CNT=1,PROBE574_WIDTH=1,PROBE574_MU_CNT=1,PROBE575_WIDTH=1,PROBE575_MU_CNT=1,PROBE576_WIDTH=1,PROBE576_MU_CNT=1,PROBE577_WIDTH=1,PROBE577_MU_CNT=1,PROBE578_WIDTH=1,PROBE578_MU_CNT=1,PROBE579_WIDTH=1,PROBE579_MU_CNT=1,PROBE580_WIDTH=1,PROBE580_MU_CNT=1,PROBE581_WIDTH=1,PROBE581_MU_CNT=1,PROBE582_WIDTH=1,PROBE582_MU_CNT=1,PROBE583_WIDTH=1,PROBE583_MU_CNT=1,PROBE584_WIDTH=1,PROBE584_MU_CNT=1,PROBE585_WIDTH=1,PROBE585_MU_CNT=1,PROBE586_WIDTH=1,PROBE586_MU_CNT=1,PROBE587_WIDTH=1,PROBE587_MU_CNT=1,PROBE588_WIDTH=1,PROBE588_MU_CNT=1,PROBE589_WIDTH=1,PROBE589_MU_CNT=1,PROBE590_WIDTH=1,PROBE590_MU_CNT=1,PROBE591_WIDTH=1,PROBE591_MU_CNT=1,PROBE592_WIDTH=1,PROBE592_MU_CNT=1,PROBE593_WIDTH=1,PROBE593_MU_CNT=1,PROBE594_WIDTH=1,PROBE594_MU_CNT=1,PROBE595_WIDTH=1,PROBE595_MU_CNT=1,PROBE596_WIDTH=1,PROBE596_MU_CNT=1,PROBE597_WIDTH=1,PROBE597_MU_CNT=1,PROBE598_WIDTH=1,PROBE598_MU_CNT=1,PROBE599_WIDTH=1,PROBE599_MU_CNT=1,PROBE600_WIDTH=1,PROBE600_MU_CNT=1,PROBE601_WIDTH=1,PROBE601_MU_CNT=1,PROBE602_WIDTH=1,PROBE602_MU_CNT=1,PROBE603_WIDTH=1,PROBE603_MU_CNT=1,PROBE604_WIDTH=1,PROBE604_MU_CNT=1,PROBE605_WIDTH=1,PROBE605_MU_CNT=1,PROBE606_WIDTH=1,PROBE606_MU_CNT=1,PROBE607_WIDTH=1,PROBE607_MU_CNT=1,PROBE608_WIDTH=1,PROBE608_MU_CNT=1,PROBE609_WIDTH=1,PROBE609_MU_CNT=1,PROBE610_WIDTH=1,PROBE610_MU_CNT=1,PROBE611_WIDTH=1,PROBE611_MU_CNT=1,PROBE612_WIDTH=1,PROBE612_MU_CNT=1,PROBE613_WIDTH=1,PROBE613_MU_CNT=1,PROBE614_WIDTH=1,PROBE614_MU_CNT=1,PROBE615_WIDTH=1,PROBE615_MU_CNT=1,PROBE616_WIDTH=1,PROBE616_MU_CNT=1,PROBE617_WIDTH=1,PROBE617_MU_CNT=1,PROBE618_WIDTH=1,PROBE618_MU_CNT=1,PROBE619_WIDTH=1,PROBE619_MU_CNT=1,PROBE620_WIDTH=1,PROBE620_MU_CNT=1,PROBE621_WIDTH=1,PROBE621_MU_CNT=1,PROBE622_WIDTH=1,PROBE622_MU_CNT=1,PROBE623_WIDTH=1,PROBE623_MU_CNT=1,PROBE624_WIDTH=1,PROBE624_MU_CNT=1,PROBE625_WIDTH=1,PROBE625_MU_CNT=1,PROBE626_WIDTH=1,PROBE626_MU_CNT=1,PROBE627_WIDTH=1,PROBE627_MU_CNT=1,PROBE628_WIDTH=1,PROBE628_MU_CNT=1,PROBE629_WIDTH=1,PROBE629_MU_CNT=1,PROBE630_WIDTH=1,PROBE630_MU_CNT=1,PROBE631_WIDTH=1,PROBE631_MU_CNT=1,PROBE632_WIDTH=1,PROBE632_MU_CNT=1,PROBE633_WIDTH=1,PROBE633_MU_CNT=1,PROBE634_WIDTH=1,PROBE634_MU_CNT=1,PROBE635_WIDTH=1,PROBE635_MU_CNT=1,PROBE636_WIDTH=1,PROBE636_MU_CNT=1,PROBE637_WIDTH=1,PROBE637_MU_CNT=1,PROBE638_WIDTH=1,PROBE638_MU_CNT=1,PROBE639_WIDTH=1,PROBE639_MU_CNT=1,PROBE640_WIDTH=1,PROBE640_MU_CNT=1,PROBE641_WIDTH=1,PROBE641_MU_CNT=1,PROBE642_WIDTH=1,PROBE642_MU_CNT=1,PROBE643_WIDTH=1,PROBE643_MU_CNT=1,PROBE644_WIDTH=1,PROBE644_MU_CNT=1,PROBE645_WIDTH=1,PROBE645_MU_CNT=1,PROBE646_WIDTH=1,PROBE646_MU_CNT=1,PROBE647_WIDTH=1,PROBE647_MU_CNT=1,PROBE648_WIDTH=1,PROBE648_MU_CNT=1,PROBE649_WIDTH=1,PROBE649_MU_CNT=1,PROBE650_WIDTH=1,PROBE650_MU_CNT=1,PROBE651_WIDTH=1,PROBE651_MU_CNT=1,PROBE652_WIDTH=1,PROBE652_MU_CNT=1,PROBE653_WIDTH=1,PROBE653_MU_CNT=1,PROBE654_WIDTH=1,PROBE654_MU_CNT=1,PROBE655_WIDTH=1,PROBE655_MU_CNT=1,PROBE656_WIDTH=1,PROBE656_MU_CNT=1,PROBE657_WIDTH=1,PROBE657_MU_CNT=1,PROBE658_WIDTH=1,PROBE658_MU_CNT=1,PROBE659_WIDTH=1,PROBE659_MU_CNT=1,PROBE660_WIDTH=1,PROBE660_MU_CNT=1,PROBE661_WIDTH=1,PROBE661_MU_CNT=1,PROBE662_WIDTH=1,PROBE662_MU_CNT=1,PROBE663_WIDTH=1,PROBE663_MU_CNT=1,PROBE664_WIDTH=1,PROBE664_MU_CNT=1,PROBE665_WIDTH=1,PROBE665_MU_CNT=1,PROBE666_WIDTH=1,PROBE666_MU_CNT=1,PROBE667_WIDTH=1,PROBE667_MU_CNT=1,PROBE668_WIDTH=1,PROBE668_MU_CNT=1,PROBE669_WIDTH=1,PROBE669_MU_CNT=1,PROBE670_WIDTH=1,PROBE670_MU_CNT=1,PROBE671_WIDTH=1,PROBE671_MU_CNT=1,PROBE672_WIDTH=1,PROBE672_MU_CNT=1,PROBE673_WIDTH=1,PROBE673_MU_CNT=1,PROBE674_WIDTH=1,PROBE674_MU_CNT=1,PROBE675_WIDTH=1,PROBE675_MU_CNT=1,PROBE676_WIDTH=1,PROBE676_MU_CNT=1,PROBE677_WIDTH=1,PROBE677_MU_CNT=1,PROBE678_WIDTH=1,PROBE678_MU_CNT=1,PROBE679_WIDTH=1,PROBE679_MU_CNT=1,PROBE680_WIDTH=1,PROBE680_MU_CNT=1,PROBE681_WIDTH=1,PROBE681_MU_CNT=1,PROBE682_WIDTH=1,PROBE682_MU_CNT=1,PROBE683_WIDTH=1,PROBE683_MU_CNT=1,PROBE684_WIDTH=1,PROBE684_MU_CNT=1,PROBE685_WIDTH=1,PROBE685_MU_CNT=1,PROBE686_WIDTH=1,PROBE686_MU_CNT=1,PROBE687_WIDTH=1,PROBE687_MU_CNT=1,PROBE688_WIDTH=1,PROBE688_MU_CNT=1,PROBE689_WIDTH=1,PROBE689_MU_CNT=1,PROBE690_WIDTH=1,PROBE690_MU_CNT=1,PROBE691_WIDTH=1,PROBE691_MU_CNT=1,PROBE692_WIDTH=1,PROBE692_MU_CNT=1,PROBE693_WIDTH=1,PROBE693_MU_CNT=1,PROBE694_WIDTH=1,PROBE694_MU_CNT=1,PROBE695_WIDTH=1,PROBE695_MU_CNT=1,PROBE696_WIDTH=1,PROBE696_MU_CNT=1,PROBE697_WIDTH=1,PROBE697_MU_CNT=1,PROBE698_WIDTH=1,PROBE698_MU_CNT=1,PROBE699_WIDTH=1,PROBE699_MU_CNT=1,PROBE700_WIDTH=1,PROBE700_MU_CNT=1,PROBE701_WIDTH=1,PROBE701_MU_CNT=1,PROBE702_WIDTH=1,PROBE702_MU_CNT=1,PROBE703_WIDTH=1,PROBE703_MU_CNT=1,PROBE704_WIDTH=1,PROBE704_MU_CNT=1,PROBE705_WIDTH=1,PROBE705_MU_CNT=1,PROBE706_WIDTH=1,PROBE706_MU_CNT=1,PROBE707_WIDTH=1,PROBE707_MU_CNT=1,PROBE708_WIDTH=1,PROBE708_MU_CNT=1,PROBE709_WIDTH=1,PROBE709_MU_CNT=1,PROBE710_WIDTH=1,PROBE710_MU_CNT=1,PROBE711_WIDTH=1,PROBE711_MU_CNT=1,PROBE712_WIDTH=1,PROBE712_MU_CNT=1,PROBE713_WIDTH=1,PROBE713_MU_CNT=1,PROBE714_WIDTH=1,PROBE714_MU_CNT=1,PROBE715_WIDTH=1,PROBE715_MU_CNT=1,PROBE716_WIDTH=1,PROBE716_MU_CNT=1,PROBE717_WIDTH=1,PROBE717_MU_CNT=1,PROBE718_WIDTH=1,PROBE718_MU_CNT=1,PROBE719_WIDTH=1,PROBE719_MU_CNT=1,PROBE720_WIDTH=1,PROBE720_MU_CNT=1,PROBE721_WIDTH=1,PROBE721_MU_CNT=1,PROBE722_WIDTH=1,PROBE722_MU_CNT=1,PROBE723_WIDTH=1,PROBE723_MU_CNT=1,PROBE724_WIDTH=1,PROBE724_MU_CNT=1,PROBE725_WIDTH=1,PROBE725_MU_CNT=1,PROBE726_WIDTH=1,PROBE726_MU_CNT=1,PROBE727_WIDTH=1,PROBE727_MU_CNT=1,PROBE728_WIDTH=1,PROBE728_MU_CNT=1,PROBE729_WIDTH=1,PROBE729_MU_CNT=1,PROBE730_WIDTH=1,PROBE730_MU_CNT=1,PROBE731_WIDTH=1,PROBE731_MU_CNT=1,PROBE732_WIDTH=1,PROBE732_MU_CNT=1,PROBE733_WIDTH=1,PROBE733_MU_CNT=1,PROBE734_WIDTH=1,PROBE734_MU_CNT=1,PROBE735_WIDTH=1,PROBE735_MU_CNT=1,PROBE736_WIDTH=1,PROBE736_MU_CNT=1,PROBE737_WIDTH=1,PROBE737_MU_CNT=1,PROBE738_WIDTH=1,PROBE738_MU_CNT=1,PROBE739_WIDTH=1,PROBE739_MU_CNT=1,PROBE740_WIDTH=1,PROBE740_MU_CNT=1,PROBE741_WIDTH=1,PROBE741_MU_CNT=1,PROBE742_WIDTH=1,PROBE742_MU_CNT=1,PROBE743_WIDTH=1,PROBE743_MU_CNT=1,PROBE744_WIDTH=1,PROBE744_MU_CNT=1,PROBE745_WIDTH=1,PROBE745_MU_CNT=1,PROBE746_WIDTH=1,PROBE746_MU_CNT=1,PROBE747_WIDTH=1,PROBE747_MU_CNT=1,PROBE748_WIDTH=1,PROBE748_MU_CNT=1,PROBE749_WIDTH=1,PROBE749_MU_CNT=1,PROBE750_WIDTH=1,PROBE750_MU_CNT=1,PROBE751_WIDTH=1,PROBE751_MU_CNT=1,PROBE752_WIDTH=1,PROBE752_MU_CNT=1,PROBE753_WIDTH=1,PROBE753_MU_CNT=1,PROBE754_WIDTH=1,PROBE754_MU_CNT=1,PROBE755_WIDTH=1,PROBE755_MU_CNT=1,PROBE756_WIDTH=1,PROBE756_MU_CNT=1,PROBE757_WIDTH=1,PROBE757_MU_CNT=1,PROBE758_WIDTH=1,PROBE758_MU_CNT=1,PROBE759_WIDTH=1,PROBE759_MU_CNT=1,PROBE760_WIDTH=1,PROBE760_MU_CNT=1,PROBE761_WIDTH=1,PROBE761_MU_CNT=1,PROBE762_WIDTH=1,PROBE762_MU_CNT=1,PROBE763_WIDTH=1,PROBE763_MU_CNT=1,PROBE764_WIDTH=1,PROBE764_MU_CNT=1,PROBE765_WIDTH=1,PROBE765_MU_CNT=1,PROBE766_WIDTH=1,PROBE766_MU_CNT=1,PROBE767_WIDTH=1,PROBE767_MU_CNT=1,PROBE768_WIDTH=1,PROBE768_MU_CNT=1,PROBE769_WIDTH=1,PROBE769_MU_CNT=1,PROBE770_WIDTH=1,PROBE770_MU_CNT=1,PROBE771_WIDTH=1,PROBE771_MU_CNT=1,PROBE772_WIDTH=1,PROBE772_MU_CNT=1,PROBE773_WIDTH=1,PROBE773_MU_CNT=1,PROBE774_WIDTH=1,PROBE774_MU_CNT=1,PROBE775_WIDTH=1,PROBE775_MU_CNT=1,PROBE776_WIDTH=1,PROBE776_MU_CNT=1,PROBE777_WIDTH=1,PROBE777_MU_CNT=1,PROBE778_WIDTH=1,PROBE778_MU_CNT=1,PROBE779_WIDTH=1,PROBE779_MU_CNT=1,PROBE780_WIDTH=1,PROBE780_MU_CNT=1,PROBE781_WIDTH=1,PROBE781_MU_CNT=1,PROBE782_WIDTH=1,PROBE782_MU_CNT=1,PROBE783_WIDTH=1,PROBE783_MU_CNT=1,PROBE784_WIDTH=1,PROBE784_MU_CNT=1,PROBE785_WIDTH=1,PROBE785_MU_CNT=1,PROBE786_WIDTH=1,PROBE786_MU_CNT=1,PROBE787_WIDTH=1,PROBE787_MU_CNT=1,PROBE788_WIDTH=1,PROBE788_MU_CNT=1,PROBE789_WIDTH=1,PROBE789_MU_CNT=1,PROBE790_WIDTH=1,PROBE790_MU_CNT=1,PROBE791_WIDTH=1,PROBE791_MU_CNT=1,PROBE792_WIDTH=1,PROBE792_MU_CNT=1,PROBE793_WIDTH=1,PROBE793_MU_CNT=1,PROBE794_WIDTH=1,PROBE794_MU_CNT=1,PROBE795_WIDTH=1,PROBE795_MU_CNT=1,PROBE796_WIDTH=1,PROBE796_MU_CNT=1,PROBE797_WIDTH=1,PROBE797_MU_CNT=1,PROBE798_WIDTH=1,PROBE798_MU_CNT=1,PROBE799_WIDTH=1,PROBE799_MU_CNT=1,PROBE800_WIDTH=1,PROBE800_MU_CNT=1,PROBE801_WIDTH=1,PROBE801_MU_CNT=1,PROBE802_WIDTH=1,PROBE802_MU_CNT=1,PROBE803_WIDTH=1,PROBE803_MU_CNT=1,PROBE804_WIDTH=1,PROBE804_MU_CNT=1,PROBE805_WIDTH=1,PROBE805_MU_CNT=1,PROBE806_WIDTH=1,PROBE806_MU_CNT=1,PROBE807_WIDTH=1,PROBE807_MU_CNT=1,PROBE808_WIDTH=1,PROBE808_MU_CNT=1,PROBE809_WIDTH=1,PROBE809_MU_CNT=1,PROBE810_WIDTH=1,PROBE810_MU_CNT=1,PROBE811_WIDTH=1,PROBE811_MU_CNT=1,PROBE812_WIDTH=1,PROBE812_MU_CNT=1,PROBE813_WIDTH=1,PROBE813_MU_CNT=1,PROBE814_WIDTH=1,PROBE814_MU_CNT=1,PROBE815_WIDTH=1,PROBE815_MU_CNT=1,PROBE816_WIDTH=1,PROBE816_MU_CNT=1,PROBE817_WIDTH=1,PROBE817_MU_CNT=1,PROBE818_WIDTH=1,PROBE818_MU_CNT=1,PROBE819_WIDTH=1,PROBE819_MU_CNT=1,PROBE820_WIDTH=1,PROBE820_MU_CNT=1,PROBE821_WIDTH=1,PROBE821_MU_CNT=1,PROBE822_WIDTH=1,PROBE822_MU_CNT=1,PROBE823_WIDTH=1,PROBE823_MU_CNT=1,PROBE824_WIDTH=1,PROBE824_MU_CNT=1,PROBE825_WIDTH=1,PROBE825_MU_CNT=1,PROBE826_WIDTH=1,PROBE826_MU_CNT=1,PROBE827_WIDTH=1,PROBE827_MU_CNT=1,PROBE828_WIDTH=1,PROBE828_MU_CNT=1,PROBE829_WIDTH=1,PROBE829_MU_CNT=1,PROBE830_WIDTH=1,PROBE830_MU_CNT=1,PROBE831_WIDTH=1,PROBE831_MU_CNT=1,PROBE832_WIDTH=1,PROBE832_MU_CNT=1,PROBE833_WIDTH=1,PROBE833_MU_CNT=1,PROBE834_WIDTH=1,PROBE834_MU_CNT=1,PROBE835_WIDTH=1,PROBE835_MU_CNT=1,PROBE836_WIDTH=1,PROBE836_MU_CNT=1,PROBE837_WIDTH=1,PROBE837_MU_CNT=1,PROBE838_WIDTH=1,PROBE838_MU_CNT=1,PROBE839_WIDTH=1,PROBE839_MU_CNT=1,PROBE840_WIDTH=1,PROBE840_MU_CNT=1,PROBE841_WIDTH=1,PROBE841_MU_CNT=1,PROBE842_WIDTH=1,PROBE842_MU_CNT=1,PROBE843_WIDTH=1,PROBE843_MU_CNT=1,PROBE844_WIDTH=1,PROBE844_MU_CNT=1,PROBE845_WIDTH=1,PROBE845_MU_CNT=1,PROBE846_WIDTH=1,PROBE846_MU_CNT=1,PROBE847_WIDTH=1,PROBE847_MU_CNT=1,PROBE848_WIDTH=1,PROBE848_MU_CNT=1,PROBE849_WIDTH=1,PROBE849_MU_CNT=1,PROBE850_WIDTH=1,PROBE850_MU_CNT=1,PROBE851_WIDTH=1,PROBE851_MU_CNT=1,PROBE852_WIDTH=1,PROBE852_MU_CNT=1,PROBE853_WIDTH=1,PROBE853_MU_CNT=1,PROBE854_WIDTH=1,PROBE854_MU_CNT=1,PROBE855_WIDTH=1,PROBE855_MU_CNT=1,PROBE856_WIDTH=1,PROBE856_MU_CNT=1,PROBE857_WIDTH=1,PROBE857_MU_CNT=1,PROBE858_WIDTH=1,PROBE858_MU_CNT=1,PROBE859_WIDTH=1,PROBE859_MU_CNT=1,PROBE860_WIDTH=1,PROBE860_MU_CNT=1,PROBE861_WIDTH=1,PROBE861_MU_CNT=1,PROBE862_WIDTH=1,PROBE862_MU_CNT=1,PROBE863_WIDTH=1,PROBE863_MU_CNT=1,PROBE864_WIDTH=1,PROBE864_MU_CNT=1,PROBE865_WIDTH=1,PROBE865_MU_CNT=1,PROBE866_WIDTH=1,PROBE866_MU_CNT=1,PROBE867_WIDTH=1,PROBE867_MU_CNT=1,PROBE868_WIDTH=1,PROBE868_MU_CNT=1,PROBE869_WIDTH=1,PROBE869_MU_CNT=1,PROBE870_WIDTH=1,PROBE870_MU_CNT=1,PROBE871_WIDTH=1,PROBE871_MU_CNT=1,PROBE872_WIDTH=1,PROBE872_MU_CNT=1,PROBE873_WIDTH=1,PROBE873_MU_CNT=1,PROBE874_WIDTH=1,PROBE874_MU_CNT=1,PROBE875_WIDTH=1,PROBE875_MU_CNT=1,PROBE876_WIDTH=1,PROBE876_MU_CNT=1,PROBE877_WIDTH=1,PROBE877_MU_CNT=1,PROBE878_WIDTH=1,PROBE878_MU_CNT=1,PROBE879_WIDTH=1,PROBE879_MU_CNT=1,PROBE880_WIDTH=1,PROBE880_MU_CNT=1,PROBE881_WIDTH=1,PROBE881_MU_CNT=1,PROBE882_WIDTH=1,PROBE882_MU_CNT=1,PROBE883_WIDTH=1,PROBE883_MU_CNT=1,PROBE884_WIDTH=1,PROBE884_MU_CNT=1,PROBE885_WIDTH=1,PROBE885_MU_CNT=1,PROBE886_WIDTH=1,PROBE886_MU_CNT=1,PROBE887_WIDTH=1,PROBE887_MU_CNT=1,PROBE888_WIDTH=1,PROBE888_MU_CNT=1,PROBE889_WIDTH=1,PROBE889_MU_CNT=1,PROBE890_WIDTH=1,PROBE890_MU_CNT=1,PROBE891_WIDTH=1,PROBE891_MU_CNT=1,PROBE892_WIDTH=1,PROBE892_MU_CNT=1,PROBE893_WIDTH=1,PROBE893_MU_CNT=1,PROBE894_WIDTH=1,PROBE894_MU_CNT=1,PROBE895_WIDTH=1,PROBE895_MU_CNT=1,PROBE896_WIDTH=1,PROBE896_MU_CNT=1,PROBE897_WIDTH=1,PROBE897_MU_CNT=1,PROBE898_WIDTH=1,PROBE898_MU_CNT=1,PROBE899_WIDTH=1,PROBE899_MU_CNT=1,PROBE900_WIDTH=1,PROBE900_MU_CNT=1,PROBE901_WIDTH=1,PROBE901_MU_CNT=1,PROBE902_WIDTH=1,PROBE902_MU_CNT=1,PROBE903_WIDTH=1,PROBE903_MU_CNT=1,PROBE904_WIDTH=1,PROBE904_MU_CNT=1,PROBE905_WIDTH=1,PROBE905_MU_CNT=1,PROBE906_WIDTH=1,PROBE906_MU_CNT=1,PROBE907_WIDTH=1,PROBE907_MU_CNT=1,PROBE908_WIDTH=1,PROBE908_MU_CNT=1,PROBE909_WIDTH=1,PROBE909_MU_CNT=1,PROBE910_WIDTH=1,PROBE910_MU_CNT=1,PROBE911_WIDTH=1,PROBE911_MU_CNT=1,PROBE912_WIDTH=1,PROBE912_MU_CNT=1,PROBE913_WIDTH=1,PROBE913_MU_CNT=1,PROBE914_WIDTH=1,PROBE914_MU_CNT=1,PROBE915_WIDTH=1,PROBE915_MU_CNT=1,PROBE916_WIDTH=1,PROBE916_MU_CNT=1,PROBE917_WIDTH=1,PROBE917_MU_CNT=1,PROBE918_WIDTH=1,PROBE918_MU_CNT=1,PROBE919_WIDTH=1,PROBE919_MU_CNT=1,PROBE920_WIDTH=1,PROBE920_MU_CNT=1,PROBE921_WIDTH=1,PROBE921_MU_CNT=1,PROBE922_WIDTH=1,PROBE922_MU_CNT=1,PROBE923_WIDTH=1,PROBE923_MU_CNT=1,PROBE924_WIDTH=1,PROBE924_MU_CNT=1,PROBE925_WIDTH=1,PROBE925_MU_CNT=1,PROBE926_WIDTH=1,PROBE926_MU_CNT=1,PROBE927_WIDTH=1,PROBE927_MU_CNT=1,PROBE928_WIDTH=1,PROBE928_MU_CNT=1,PROBE929_WIDTH=1,PROBE929_MU_CNT=1,PROBE930_WIDTH=1,PROBE930_MU_CNT=1,PROBE931_WIDTH=1,PROBE931_MU_CNT=1,PROBE932_WIDTH=1,PROBE932_MU_CNT=1,PROBE933_WIDTH=1,PROBE933_MU_CNT=1,PROBE934_WIDTH=1,PROBE934_MU_CNT=1,PROBE935_WIDTH=1,PROBE935_MU_CNT=1,PROBE936_WIDTH=1,PROBE936_MU_CNT=1,PROBE937_WIDTH=1,PROBE937_MU_CNT=1,PROBE938_WIDTH=1,PROBE938_MU_CNT=1,PROBE939_WIDTH=1,PROBE939_MU_CNT=1,PROBE940_WIDTH=1,PROBE940_MU_CNT=1,PROBE941_WIDTH=1,PROBE941_MU_CNT=1,PROBE942_WIDTH=1,PROBE942_MU_CNT=1,PROBE943_WIDTH=1,PROBE943_MU_CNT=1,PROBE944_WIDTH=1,PROBE944_MU_CNT=1,PROBE945_WIDTH=1,PROBE945_MU_CNT=1,PROBE946_WIDTH=1,PROBE946_MU_CNT=1,PROBE947_WIDTH=1,PROBE947_MU_CNT=1,PROBE948_WIDTH=1,PROBE948_MU_CNT=1,PROBE949_WIDTH=1,PROBE949_MU_CNT=1,PROBE950_WIDTH=1,PROBE950_MU_CNT=1,PROBE951_WIDTH=1,PROBE951_MU_CNT=1,PROBE952_WIDTH=1,PROBE952_MU_CNT=1,PROBE953_WIDTH=1,PROBE953_MU_CNT=1,PROBE954_WIDTH=1,PROBE954_MU_CNT=1,PROBE955_WIDTH=1,PROBE955_MU_CNT=1,PROBE956_WIDTH=1,PROBE956_MU_CNT=1,PROBE957_WIDTH=1,PROBE957_MU_CNT=1,PROBE958_WIDTH=1,PROBE958_MU_CNT=1,PROBE959_WIDTH=1,PROBE959_MU_CNT=1,PROBE960_WIDTH=1,PROBE960_MU_CNT=1,PROBE961_WIDTH=1,PROBE961_MU_CNT=1,PROBE962_WIDTH=1,PROBE962_MU_CNT=1,PROBE963_WIDTH=1,PROBE963_MU_CNT=1,PROBE964_WIDTH=1,PROBE964_MU_CNT=1,PROBE965_WIDTH=1,PROBE965_MU_CNT=1,PROBE966_WIDTH=1,PROBE966_MU_CNT=1,PROBE967_WIDTH=1,PROBE967_MU_CNT=1,PROBE968_WIDTH=1,PROBE968_MU_CNT=1,PROBE969_WIDTH=1,PROBE969_MU_CNT=1,PROBE970_WIDTH=1,PROBE970_MU_CNT=1,PROBE971_WIDTH=1,PROBE971_MU_CNT=1,PROBE972_WIDTH=1,PROBE972_MU_CNT=1,PROBE973_WIDTH=1,PROBE973_MU_CNT=1,PROBE974_WIDTH=1,PROBE974_MU_CNT=1,PROBE975_WIDTH=1,PROBE975_MU_CNT=1,PROBE976_WIDTH=1,PROBE976_MU_CNT=1,PROBE977_WIDTH=1,PROBE977_MU_CNT=1,PROBE978_WIDTH=1,PROBE978_MU_CNT=1,PROBE979_WIDTH=1,PROBE979_MU_CNT=1,PROBE980_WIDTH=1,PROBE980_MU_CNT=1,PROBE981_WIDTH=1,PROBE981_MU_CNT=1,PROBE982_WIDTH=1,PROBE982_MU_CNT=1,PROBE983_WIDTH=1,PROBE983_MU_CNT=1,PROBE984_WIDTH=1,PROBE984_MU_CNT=1,PROBE985_WIDTH=1,PROBE985_MU_CNT=1,PROBE986_WIDTH=1,PROBE986_MU_CNT=1,PROBE987_WIDTH=1,PROBE987_MU_CNT=1,PROBE988_WIDTH=1,PROBE988_MU_CNT=1,PROBE989_WIDTH=1,PROBE989_MU_CNT=1,PROBE990_WIDTH=1,PROBE990_MU_CNT=1,PROBE991_WIDTH=1,PROBE991_MU_CNT=1,PROBE992_WIDTH=1,PROBE992_MU_CNT=1,PROBE993_WIDTH=1,PROBE993_MU_CNT=1,PROBE994_WIDTH=1,PROBE994_MU_CNT=1,PROBE995_WIDTH=1,PROBE995_MU_CNT=1,PROBE996_WIDTH=1,PROBE996_MU_CNT=1,PROBE997_WIDTH=1,PROBE997_MU_CNT=1,PROBE998_WIDTH=1,PROBE998_MU_CNT=1,PROBE999_WIDTH=1,PROBE999_MU_CNT=1,PROBE1000_WIDTH=1,PROBE1000_MU_CNT=1,PROBE1001_WIDTH=1,PROBE1001_MU_CNT=1,PROBE1002_WIDTH=1,PROBE1002_MU_CNT=1,PROBE1003_WIDTH=1,PROBE1003_MU_CNT=1,PROBE1004_WIDTH=1,PROBE1004_MU_CNT=1,PROBE1005_WIDTH=1,PROBE1005_MU_CNT=1,PROBE1006_WIDTH=1,PROBE1006_MU_CNT=1,PROBE1007_WIDTH=1,PROBE1007_MU_CNT=1,PROBE1008_WIDTH=1,PROBE1008_MU_CNT=1,PROBE1009_WIDTH=1,PROBE1009_MU_CNT=1,PROBE1010_WIDTH=1,PROBE1010_MU_CNT=1,PROBE1011_WIDTH=1,PROBE1011_MU_CNT=1,PROBE1012_WIDTH=1,PROBE1012_MU_CNT=1,PROBE1013_WIDTH=1,PROBE1013_MU_CNT=1,PROBE1014_WIDTH=1,PROBE1014_MU_CNT=1,PROBE1015_WIDTH=1,PROBE1015_MU_CNT=1,PROBE1016_WIDTH=1,PROBE1016_MU_CNT=1,PROBE1017_WIDTH=1,PROBE1017_MU_CNT=1,PROBE1018_WIDTH=1,PROBE1018_MU_CNT=1,PROBE1019_WIDTH=1,PROBE1019_MU_CNT=1,PROBE1020_WIDTH=1,PROBE1020_MU_CNT=1,PROBE1021_WIDTH=1,PROBE1021_MU_CNT=1,PROBE1022_WIDTH=1,PROBE1022_MU_CNT=1,PROBE1023_WIDTH=1,PROBE1023_MU_CNT=1"),
.C_XDEVICEFAMILY("zynq"),
.C_CORE_TYPE(1),
.C_CORE_INFO1(0),
.C_CORE_INFO2(0),
.C_CAPTURE_TYPE(0),
.C_MU_TYPE(0),
.C_TC_TYPE(0),
.C_NUM_OF_PROBES(4),
.C_DATA_DEPTH(1024),
.C_MAJOR_VERSION(2013),
.C_MINOR_VERSION(3),
.C_BUILD_REVISION(0),
.C_CORE_MAJOR_VER(4),
.C_CORE_MINOR_VER(0),
.C_XSDB_SLAVE_TYPE(17),
.C_NEXT_SLAVE(0),
.C_CSE_DRV_VER(1),
.C_USE_TEST_REG(1),
.C_PIPE_IFACE(1),
.C_RAM_STYLE("SUBCORE"),
.C_TRIGOUT_EN(0),
.C_TRIGIN_EN(0),
.C_ADV_TRIGGER(0),
.C_EN_STRG_QUAL(0),
.C_INPUT_PIPE_STAGES(0),
.C_PROBE0_WIDTH(1),
.C_PROBE1_WIDTH(1),
.C_PROBE2_WIDTH(1),
.C_PROBE3_WIDTH(1),
.C_PROBE4_WIDTH(1),
.C_PROBE5_WIDTH(1),
.C_PROBE6_WIDTH(1),
.C_PROBE7_WIDTH(1),
.C_PROBE8_WIDTH(1),
.C_PROBE9_WIDTH(1),
.C_PROBE10_WIDTH(1),
.C_PROBE11_WIDTH(1),
.C_PROBE12_WIDTH(1),
.C_PROBE13_WIDTH(1),
.C_PROBE14_WIDTH(1),
.C_PROBE15_WIDTH(1),
.C_PROBE16_WIDTH(1),
.C_PROBE17_WIDTH(1),
.C_PROBE18_WIDTH(1),
.C_PROBE19_WIDTH(1),
.C_PROBE20_WIDTH(1),
.C_PROBE21_WIDTH(1),
.C_PROBE22_WIDTH(1),
.C_PROBE23_WIDTH(1),
.C_PROBE24_WIDTH(1),
.C_PROBE25_WIDTH(1),
.C_PROBE26_WIDTH(1),
.C_PROBE27_WIDTH(1),
.C_PROBE28_WIDTH(1),
.C_PROBE29_WIDTH(1),
.C_PROBE30_WIDTH(1),
.C_PROBE31_WIDTH(1),
.C_PROBE32_WIDTH(1),
.C_PROBE33_WIDTH(1),
.C_PROBE34_WIDTH(1),
.C_PROBE35_WIDTH(1),
.C_PROBE36_WIDTH(1),
.C_PROBE37_WIDTH(1),
.C_PROBE38_WIDTH(1),
.C_PROBE39_WIDTH(1),
.C_PROBE40_WIDTH(1),
.C_PROBE41_WIDTH(1),
.C_PROBE42_WIDTH(1),
.C_PROBE43_WIDTH(1),
.C_PROBE44_WIDTH(1),
.C_PROBE45_WIDTH(1),
.C_PROBE46_WIDTH(1),
.C_PROBE47_WIDTH(1),
.C_PROBE48_WIDTH(1),
.C_PROBE49_WIDTH(1),
.C_PROBE50_WIDTH(1),
.C_PROBE51_WIDTH(1),
.C_PROBE52_WIDTH(1),
.C_PROBE53_WIDTH(1),
.C_PROBE54_WIDTH(1),
.C_PROBE55_WIDTH(1),
.C_PROBE56_WIDTH(1),
.C_PROBE57_WIDTH(1),
.C_PROBE58_WIDTH(1),
.C_PROBE59_WIDTH(1),
.C_PROBE60_WIDTH(1),
.C_PROBE61_WIDTH(1),
.C_PROBE62_WIDTH(1),
.C_PROBE63_WIDTH(1),
.C_PROBE64_WIDTH(1),
.C_PROBE65_WIDTH(1),
.C_PROBE66_WIDTH(1),
.C_PROBE67_WIDTH(1),
.C_PROBE68_WIDTH(1),
.C_PROBE69_WIDTH(1),
.C_PROBE70_WIDTH(1),
.C_PROBE71_WIDTH(1),
.C_PROBE72_WIDTH(1),
.C_PROBE73_WIDTH(1),
.C_PROBE74_WIDTH(1),
.C_PROBE75_WIDTH(1),
.C_PROBE76_WIDTH(1),
.C_PROBE77_WIDTH(1),
.C_PROBE78_WIDTH(1),
.C_PROBE79_WIDTH(1),
.C_PROBE80_WIDTH(1),
.C_PROBE81_WIDTH(1),
.C_PROBE82_WIDTH(1),
.C_PROBE83_WIDTH(1),
.C_PROBE84_WIDTH(1),
.C_PROBE85_WIDTH(1),
.C_PROBE86_WIDTH(1),
.C_PROBE87_WIDTH(1),
.C_PROBE88_WIDTH(1),
.C_PROBE89_WIDTH(1),
.C_PROBE90_WIDTH(1),
.C_PROBE91_WIDTH(1),
.C_PROBE92_WIDTH(1),
.C_PROBE93_WIDTH(1),
.C_PROBE94_WIDTH(1),
.C_PROBE95_WIDTH(1),
.C_PROBE96_WIDTH(1),
.C_PROBE97_WIDTH(1),
.C_PROBE98_WIDTH(1),
.C_PROBE99_WIDTH(1),
.C_PROBE100_WIDTH(1),
.C_PROBE101_WIDTH(1),
.C_PROBE102_WIDTH(1),
.C_PROBE103_WIDTH(1),
.C_PROBE104_WIDTH(1),
.C_PROBE105_WIDTH(1),
.C_PROBE106_WIDTH(1),
.C_PROBE107_WIDTH(1),
.C_PROBE108_WIDTH(1),
.C_PROBE109_WIDTH(1),
.C_PROBE110_WIDTH(1),
.C_PROBE111_WIDTH(1),
.C_PROBE112_WIDTH(1),
.C_PROBE113_WIDTH(1),
.C_PROBE114_WIDTH(1),
.C_PROBE115_WIDTH(1),
.C_PROBE116_WIDTH(1),
.C_PROBE117_WIDTH(1),
.C_PROBE118_WIDTH(1),
.C_PROBE119_WIDTH(1),
.C_PROBE120_WIDTH(1),
.C_PROBE121_WIDTH(1),
.C_PROBE122_WIDTH(1),
.C_PROBE123_WIDTH(1),
.C_PROBE124_WIDTH(1),
.C_PROBE125_WIDTH(1),
.C_PROBE126_WIDTH(1),
.C_PROBE127_WIDTH(1),
.C_PROBE128_WIDTH(1),
.C_PROBE129_WIDTH(1),
.C_PROBE130_WIDTH(1),
.C_PROBE131_WIDTH(1),
.C_PROBE132_WIDTH(1),
.C_PROBE133_WIDTH(1),
.C_PROBE134_WIDTH(1),
.C_PROBE135_WIDTH(1),
.C_PROBE136_WIDTH(1),
.C_PROBE137_WIDTH(1),
.C_PROBE138_WIDTH(1),
.C_PROBE139_WIDTH(1),
.C_PROBE140_WIDTH(1),
.C_PROBE141_WIDTH(1),
.C_PROBE142_WIDTH(1),
.C_PROBE143_WIDTH(1),
.C_PROBE144_WIDTH(1),
.C_PROBE145_WIDTH(1),
.C_PROBE146_WIDTH(1),
.C_PROBE147_WIDTH(1),
.C_PROBE148_WIDTH(1),
.C_PROBE149_WIDTH(1),
.C_PROBE150_WIDTH(1),
.C_PROBE151_WIDTH(1),
.C_PROBE152_WIDTH(1),
.C_PROBE153_WIDTH(1),
.C_PROBE154_WIDTH(1),
.C_PROBE155_WIDTH(1),
.C_PROBE156_WIDTH(1),
.C_PROBE157_WIDTH(1),
.C_PROBE158_WIDTH(1),
.C_PROBE159_WIDTH(1),
.C_PROBE160_WIDTH(1),
.C_PROBE161_WIDTH(1),
.C_PROBE162_WIDTH(1),
.C_PROBE163_WIDTH(1),
.C_PROBE164_WIDTH(1),
.C_PROBE165_WIDTH(1),
.C_PROBE166_WIDTH(1),
.C_PROBE167_WIDTH(1),
.C_PROBE168_WIDTH(1),
.C_PROBE169_WIDTH(1),
.C_PROBE170_WIDTH(1),
.C_PROBE171_WIDTH(1),
.C_PROBE172_WIDTH(1),
.C_PROBE173_WIDTH(1),
.C_PROBE174_WIDTH(1),
.C_PROBE175_WIDTH(1),
.C_PROBE176_WIDTH(1),
.C_PROBE177_WIDTH(1),
.C_PROBE178_WIDTH(1),
.C_PROBE179_WIDTH(1),
.C_PROBE180_WIDTH(1),
.C_PROBE181_WIDTH(1),
.C_PROBE182_WIDTH(1),
.C_PROBE183_WIDTH(1),
.C_PROBE184_WIDTH(1),
.C_PROBE185_WIDTH(1),
.C_PROBE186_WIDTH(1),
.C_PROBE187_WIDTH(1),
.C_PROBE188_WIDTH(1),
.C_PROBE189_WIDTH(1),
.C_PROBE190_WIDTH(1),
.C_PROBE191_WIDTH(1),
.C_PROBE192_WIDTH(1),
.C_PROBE193_WIDTH(1),
.C_PROBE194_WIDTH(1),
.C_PROBE195_WIDTH(1),
.C_PROBE196_WIDTH(1),
.C_PROBE197_WIDTH(1),
.C_PROBE198_WIDTH(1),
.C_PROBE199_WIDTH(1),
.C_PROBE200_WIDTH(1),
.C_PROBE201_WIDTH(1),
.C_PROBE202_WIDTH(1),
.C_PROBE203_WIDTH(1),
.C_PROBE204_WIDTH(1),
.C_PROBE205_WIDTH(1),
.C_PROBE206_WIDTH(1),
.C_PROBE207_WIDTH(1),
.C_PROBE208_WIDTH(1),
.C_PROBE209_WIDTH(1),
.C_PROBE210_WIDTH(1),
.C_PROBE211_WIDTH(1),
.C_PROBE212_WIDTH(1),
.C_PROBE213_WIDTH(1),
.C_PROBE214_WIDTH(1),
.C_PROBE215_WIDTH(1),
.C_PROBE216_WIDTH(1),
.C_PROBE217_WIDTH(1),
.C_PROBE218_WIDTH(1),
.C_PROBE219_WIDTH(1),
.C_PROBE220_WIDTH(1),
.C_PROBE221_WIDTH(1),
.C_PROBE222_WIDTH(1),
.C_PROBE223_WIDTH(1),
.C_PROBE224_WIDTH(1),
.C_PROBE225_WIDTH(1),
.C_PROBE226_WIDTH(1),
.C_PROBE227_WIDTH(1),
.C_PROBE228_WIDTH(1),
.C_PROBE229_WIDTH(1),
.C_PROBE230_WIDTH(1),
.C_PROBE231_WIDTH(1),
.C_PROBE232_WIDTH(1),
.C_PROBE233_WIDTH(1),
.C_PROBE234_WIDTH(1),
.C_PROBE235_WIDTH(1),
.C_PROBE236_WIDTH(1),
.C_PROBE237_WIDTH(1),
.C_PROBE238_WIDTH(1),
.C_PROBE239_WIDTH(1),
.C_PROBE240_WIDTH(1),
.C_PROBE241_WIDTH(1),
.C_PROBE242_WIDTH(1),
.C_PROBE243_WIDTH(1),
.C_PROBE244_WIDTH(1),
.C_PROBE245_WIDTH(1),
.C_PROBE246_WIDTH(1),
.C_PROBE247_WIDTH(1),
.C_PROBE248_WIDTH(1),
.C_PROBE249_WIDTH(1),
.C_PROBE250_WIDTH(1),
.C_PROBE251_WIDTH(1),
.C_PROBE252_WIDTH(1),
.C_PROBE253_WIDTH(1),
.C_PROBE254_WIDTH(1),
.C_PROBE255_WIDTH(1),
.C_PROBE256_WIDTH(1),
.C_PROBE257_WIDTH(1),
.C_PROBE258_WIDTH(1),
.C_PROBE259_WIDTH(1),
.C_PROBE260_WIDTH(1),
.C_PROBE261_WIDTH(1),
.C_PROBE262_WIDTH(1),
.C_PROBE263_WIDTH(1),
.C_PROBE264_WIDTH(1),
.C_PROBE265_WIDTH(1),
.C_PROBE266_WIDTH(1),
.C_PROBE267_WIDTH(1),
.C_PROBE268_WIDTH(1),
.C_PROBE269_WIDTH(1),
.C_PROBE270_WIDTH(1),
.C_PROBE271_WIDTH(1),
.C_PROBE272_WIDTH(1),
.C_PROBE273_WIDTH(1),
.C_PROBE274_WIDTH(1),
.C_PROBE275_WIDTH(1),
.C_PROBE276_WIDTH(1),
.C_PROBE277_WIDTH(1),
.C_PROBE278_WIDTH(1),
.C_PROBE279_WIDTH(1),
.C_PROBE280_WIDTH(1),
.C_PROBE281_WIDTH(1),
.C_PROBE282_WIDTH(1),
.C_PROBE283_WIDTH(1),
.C_PROBE284_WIDTH(1),
.C_PROBE285_WIDTH(1),
.C_PROBE286_WIDTH(1),
.C_PROBE287_WIDTH(1),
.C_PROBE288_WIDTH(1),
.C_PROBE289_WIDTH(1),
.C_PROBE290_WIDTH(1),
.C_PROBE291_WIDTH(1),
.C_PROBE292_WIDTH(1),
.C_PROBE293_WIDTH(1),
.C_PROBE294_WIDTH(1),
.C_PROBE295_WIDTH(1),
.C_PROBE296_WIDTH(1),
.C_PROBE297_WIDTH(1),
.C_PROBE298_WIDTH(1),
.C_PROBE299_WIDTH(1),
.C_PROBE300_WIDTH(1),
.C_PROBE301_WIDTH(1),
.C_PROBE302_WIDTH(1),
.C_PROBE303_WIDTH(1),
.C_PROBE304_WIDTH(1),
.C_PROBE305_WIDTH(1),
.C_PROBE306_WIDTH(1),
.C_PROBE307_WIDTH(1),
.C_PROBE308_WIDTH(1),
.C_PROBE309_WIDTH(1),
.C_PROBE310_WIDTH(1),
.C_PROBE311_WIDTH(1),
.C_PROBE312_WIDTH(1),
.C_PROBE313_WIDTH(1),
.C_PROBE314_WIDTH(1),
.C_PROBE315_WIDTH(1),
.C_PROBE316_WIDTH(1),
.C_PROBE317_WIDTH(1),
.C_PROBE318_WIDTH(1),
.C_PROBE319_WIDTH(1),
.C_PROBE320_WIDTH(1),
.C_PROBE321_WIDTH(1),
.C_PROBE322_WIDTH(1),
.C_PROBE323_WIDTH(1),
.C_PROBE324_WIDTH(1),
.C_PROBE325_WIDTH(1),
.C_PROBE326_WIDTH(1),
.C_PROBE327_WIDTH(1),
.C_PROBE328_WIDTH(1),
.C_PROBE329_WIDTH(1),
.C_PROBE330_WIDTH(1),
.C_PROBE331_WIDTH(1),
.C_PROBE332_WIDTH(1),
.C_PROBE333_WIDTH(1),
.C_PROBE334_WIDTH(1),
.C_PROBE335_WIDTH(1),
.C_PROBE336_WIDTH(1),
.C_PROBE337_WIDTH(1),
.C_PROBE338_WIDTH(1),
.C_PROBE339_WIDTH(1),
.C_PROBE340_WIDTH(1),
.C_PROBE341_WIDTH(1),
.C_PROBE342_WIDTH(1),
.C_PROBE343_WIDTH(1),
.C_PROBE344_WIDTH(1),
.C_PROBE345_WIDTH(1),
.C_PROBE346_WIDTH(1),
.C_PROBE347_WIDTH(1),
.C_PROBE348_WIDTH(1),
.C_PROBE349_WIDTH(1),
.C_PROBE350_WIDTH(1),
.C_PROBE351_WIDTH(1),
.C_PROBE352_WIDTH(1),
.C_PROBE353_WIDTH(1),
.C_PROBE354_WIDTH(1),
.C_PROBE355_WIDTH(1),
.C_PROBE356_WIDTH(1),
.C_PROBE357_WIDTH(1),
.C_PROBE358_WIDTH(1),
.C_PROBE359_WIDTH(1),
.C_PROBE360_WIDTH(1),
.C_PROBE361_WIDTH(1),
.C_PROBE362_WIDTH(1),
.C_PROBE363_WIDTH(1),
.C_PROBE364_WIDTH(1),
.C_PROBE365_WIDTH(1),
.C_PROBE366_WIDTH(1),
.C_PROBE367_WIDTH(1),
.C_PROBE368_WIDTH(1),
.C_PROBE369_WIDTH(1),
.C_PROBE370_WIDTH(1),
.C_PROBE371_WIDTH(1),
.C_PROBE372_WIDTH(1),
.C_PROBE373_WIDTH(1),
.C_PROBE374_WIDTH(1),
.C_PROBE375_WIDTH(1),
.C_PROBE376_WIDTH(1),
.C_PROBE377_WIDTH(1),
.C_PROBE378_WIDTH(1),
.C_PROBE379_WIDTH(1),
.C_PROBE380_WIDTH(1),
.C_PROBE381_WIDTH(1),
.C_PROBE382_WIDTH(1),
.C_PROBE383_WIDTH(1),
.C_PROBE384_WIDTH(1),
.C_PROBE385_WIDTH(1),
.C_PROBE386_WIDTH(1),
.C_PROBE387_WIDTH(1),
.C_PROBE388_WIDTH(1),
.C_PROBE389_WIDTH(1),
.C_PROBE390_WIDTH(1),
.C_PROBE391_WIDTH(1),
.C_PROBE392_WIDTH(1),
.C_PROBE393_WIDTH(1),
.C_PROBE394_WIDTH(1),
.C_PROBE395_WIDTH(1),
.C_PROBE396_WIDTH(1),
.C_PROBE397_WIDTH(1),
.C_PROBE398_WIDTH(1),
.C_PROBE399_WIDTH(1),
.C_PROBE400_WIDTH(1),
.C_PROBE401_WIDTH(1),
.C_PROBE402_WIDTH(1),
.C_PROBE403_WIDTH(1),
.C_PROBE404_WIDTH(1),
.C_PROBE405_WIDTH(1),
.C_PROBE406_WIDTH(1),
.C_PROBE407_WIDTH(1),
.C_PROBE408_WIDTH(1),
.C_PROBE409_WIDTH(1),
.C_PROBE410_WIDTH(1),
.C_PROBE411_WIDTH(1),
.C_PROBE412_WIDTH(1),
.C_PROBE413_WIDTH(1),
.C_PROBE414_WIDTH(1),
.C_PROBE415_WIDTH(1),
.C_PROBE416_WIDTH(1),
.C_PROBE417_WIDTH(1),
.C_PROBE418_WIDTH(1),
.C_PROBE419_WIDTH(1),
.C_PROBE420_WIDTH(1),
.C_PROBE421_WIDTH(1),
.C_PROBE422_WIDTH(1),
.C_PROBE423_WIDTH(1),
.C_PROBE424_WIDTH(1),
.C_PROBE425_WIDTH(1),
.C_PROBE426_WIDTH(1),
.C_PROBE427_WIDTH(1),
.C_PROBE428_WIDTH(1),
.C_PROBE429_WIDTH(1),
.C_PROBE430_WIDTH(1),
.C_PROBE431_WIDTH(1),
.C_PROBE432_WIDTH(1),
.C_PROBE433_WIDTH(1),
.C_PROBE434_WIDTH(1),
.C_PROBE435_WIDTH(1),
.C_PROBE436_WIDTH(1),
.C_PROBE437_WIDTH(1),
.C_PROBE438_WIDTH(1),
.C_PROBE439_WIDTH(1),
.C_PROBE440_WIDTH(1),
.C_PROBE441_WIDTH(1),
.C_PROBE442_WIDTH(1),
.C_PROBE443_WIDTH(1),
.C_PROBE444_WIDTH(1),
.C_PROBE445_WIDTH(1),
.C_PROBE446_WIDTH(1),
.C_PROBE447_WIDTH(1),
.C_PROBE448_WIDTH(1),
.C_PROBE449_WIDTH(1),
.C_PROBE450_WIDTH(1),
.C_PROBE451_WIDTH(1),
.C_PROBE452_WIDTH(1),
.C_PROBE453_WIDTH(1),
.C_PROBE454_WIDTH(1),
.C_PROBE455_WIDTH(1),
.C_PROBE456_WIDTH(1),
.C_PROBE457_WIDTH(1),
.C_PROBE458_WIDTH(1),
.C_PROBE459_WIDTH(1),
.C_PROBE460_WIDTH(1),
.C_PROBE461_WIDTH(1),
.C_PROBE462_WIDTH(1),
.C_PROBE463_WIDTH(1),
.C_PROBE464_WIDTH(1),
.C_PROBE465_WIDTH(1),
.C_PROBE466_WIDTH(1),
.C_PROBE467_WIDTH(1),
.C_PROBE468_WIDTH(1),
.C_PROBE469_WIDTH(1),
.C_PROBE470_WIDTH(1),
.C_PROBE471_WIDTH(1),
.C_PROBE472_WIDTH(1),
.C_PROBE473_WIDTH(1),
.C_PROBE474_WIDTH(1),
.C_PROBE475_WIDTH(1),
.C_PROBE476_WIDTH(1),
.C_PROBE477_WIDTH(1),
.C_PROBE478_WIDTH(1),
.C_PROBE479_WIDTH(1),
.C_PROBE480_WIDTH(1),
.C_PROBE481_WIDTH(1),
.C_PROBE482_WIDTH(1),
.C_PROBE483_WIDTH(1),
.C_PROBE484_WIDTH(1),
.C_PROBE485_WIDTH(1),
.C_PROBE486_WIDTH(1),
.C_PROBE487_WIDTH(1),
.C_PROBE488_WIDTH(1),
.C_PROBE489_WIDTH(1),
.C_PROBE490_WIDTH(1),
.C_PROBE491_WIDTH(1),
.C_PROBE492_WIDTH(1),
.C_PROBE493_WIDTH(1),
.C_PROBE494_WIDTH(1),
.C_PROBE495_WIDTH(1),
.C_PROBE496_WIDTH(1),
.C_PROBE497_WIDTH(1),
.C_PROBE498_WIDTH(1),
.C_PROBE499_WIDTH(1),
.C_PROBE500_WIDTH(1),
.C_PROBE501_WIDTH(1),
.C_PROBE502_WIDTH(1),
.C_PROBE503_WIDTH(1),
.C_PROBE504_WIDTH(1),
.C_PROBE505_WIDTH(1),
.C_PROBE506_WIDTH(1),
.C_PROBE507_WIDTH(1),
.C_PROBE508_WIDTH(1),
.C_PROBE509_WIDTH(1),
.C_PROBE510_WIDTH(1),
.C_PROBE511_WIDTH(1),
.C_PROBE512_WIDTH(1),
.C_PROBE513_WIDTH(1),
.C_PROBE514_WIDTH(1),
.C_PROBE515_WIDTH(1),
.C_PROBE516_WIDTH(1),
.C_PROBE517_WIDTH(1),
.C_PROBE518_WIDTH(1),
.C_PROBE519_WIDTH(1),
.C_PROBE520_WIDTH(1),
.C_PROBE521_WIDTH(1),
.C_PROBE522_WIDTH(1),
.C_PROBE523_WIDTH(1),
.C_PROBE524_WIDTH(1),
.C_PROBE525_WIDTH(1),
.C_PROBE526_WIDTH(1),
.C_PROBE527_WIDTH(1),
.C_PROBE528_WIDTH(1),
.C_PROBE529_WIDTH(1),
.C_PROBE530_WIDTH(1),
.C_PROBE531_WIDTH(1),
.C_PROBE532_WIDTH(1),
.C_PROBE533_WIDTH(1),
.C_PROBE534_WIDTH(1),
.C_PROBE535_WIDTH(1),
.C_PROBE536_WIDTH(1),
.C_PROBE537_WIDTH(1),
.C_PROBE538_WIDTH(1),
.C_PROBE539_WIDTH(1),
.C_PROBE540_WIDTH(1),
.C_PROBE541_WIDTH(1),
.C_PROBE542_WIDTH(1),
.C_PROBE543_WIDTH(1),
.C_PROBE544_WIDTH(1),
.C_PROBE545_WIDTH(1),
.C_PROBE546_WIDTH(1),
.C_PROBE547_WIDTH(1),
.C_PROBE548_WIDTH(1),
.C_PROBE549_WIDTH(1),
.C_PROBE550_WIDTH(1),
.C_PROBE551_WIDTH(1),
.C_PROBE552_WIDTH(1),
.C_PROBE553_WIDTH(1),
.C_PROBE554_WIDTH(1),
.C_PROBE555_WIDTH(1),
.C_PROBE556_WIDTH(1),
.C_PROBE557_WIDTH(1),
.C_PROBE558_WIDTH(1),
.C_PROBE559_WIDTH(1),
.C_PROBE560_WIDTH(1),
.C_PROBE561_WIDTH(1),
.C_PROBE562_WIDTH(1),
.C_PROBE563_WIDTH(1),
.C_PROBE564_WIDTH(1),
.C_PROBE565_WIDTH(1),
.C_PROBE566_WIDTH(1),
.C_PROBE567_WIDTH(1),
.C_PROBE568_WIDTH(1),
.C_PROBE569_WIDTH(1),
.C_PROBE570_WIDTH(1),
.C_PROBE571_WIDTH(1),
.C_PROBE572_WIDTH(1),
.C_PROBE573_WIDTH(1),
.C_PROBE574_WIDTH(1),
.C_PROBE575_WIDTH(1),
.C_PROBE576_WIDTH(1),
.C_PROBE577_WIDTH(1),
.C_PROBE578_WIDTH(1),
.C_PROBE579_WIDTH(1),
.C_PROBE580_WIDTH(1),
.C_PROBE581_WIDTH(1),
.C_PROBE582_WIDTH(1),
.C_PROBE583_WIDTH(1),
.C_PROBE584_WIDTH(1),
.C_PROBE585_WIDTH(1),
.C_PROBE586_WIDTH(1),
.C_PROBE587_WIDTH(1),
.C_PROBE588_WIDTH(1),
.C_PROBE589_WIDTH(1),
.C_PROBE590_WIDTH(1),
.C_PROBE591_WIDTH(1),
.C_PROBE592_WIDTH(1),
.C_PROBE593_WIDTH(1),
.C_PROBE594_WIDTH(1),
.C_PROBE595_WIDTH(1),
.C_PROBE596_WIDTH(1),
.C_PROBE597_WIDTH(1),
.C_PROBE598_WIDTH(1),
.C_PROBE599_WIDTH(1),
.C_PROBE600_WIDTH(1),
.C_PROBE601_WIDTH(1),
.C_PROBE602_WIDTH(1),
.C_PROBE603_WIDTH(1),
.C_PROBE604_WIDTH(1),
.C_PROBE605_WIDTH(1),
.C_PROBE606_WIDTH(1),
.C_PROBE607_WIDTH(1),
.C_PROBE608_WIDTH(1),
.C_PROBE609_WIDTH(1),
.C_PROBE610_WIDTH(1),
.C_PROBE611_WIDTH(1),
.C_PROBE612_WIDTH(1),
.C_PROBE613_WIDTH(1),
.C_PROBE614_WIDTH(1),
.C_PROBE615_WIDTH(1),
.C_PROBE616_WIDTH(1),
.C_PROBE617_WIDTH(1),
.C_PROBE618_WIDTH(1),
.C_PROBE619_WIDTH(1),
.C_PROBE620_WIDTH(1),
.C_PROBE621_WIDTH(1),
.C_PROBE622_WIDTH(1),
.C_PROBE623_WIDTH(1),
.C_PROBE624_WIDTH(1),
.C_PROBE625_WIDTH(1),
.C_PROBE626_WIDTH(1),
.C_PROBE627_WIDTH(1),
.C_PROBE628_WIDTH(1),
.C_PROBE629_WIDTH(1),
.C_PROBE630_WIDTH(1),
.C_PROBE631_WIDTH(1),
.C_PROBE632_WIDTH(1),
.C_PROBE633_WIDTH(1),
.C_PROBE634_WIDTH(1),
.C_PROBE635_WIDTH(1),
.C_PROBE636_WIDTH(1),
.C_PROBE637_WIDTH(1),
.C_PROBE638_WIDTH(1),
.C_PROBE639_WIDTH(1),
.C_PROBE640_WIDTH(1),
.C_PROBE641_WIDTH(1),
.C_PROBE642_WIDTH(1),
.C_PROBE643_WIDTH(1),
.C_PROBE644_WIDTH(1),
.C_PROBE645_WIDTH(1),
.C_PROBE646_WIDTH(1),
.C_PROBE647_WIDTH(1),
.C_PROBE648_WIDTH(1),
.C_PROBE649_WIDTH(1),
.C_PROBE650_WIDTH(1),
.C_PROBE651_WIDTH(1),
.C_PROBE652_WIDTH(1),
.C_PROBE653_WIDTH(1),
.C_PROBE654_WIDTH(1),
.C_PROBE655_WIDTH(1),
.C_PROBE656_WIDTH(1),
.C_PROBE657_WIDTH(1),
.C_PROBE658_WIDTH(1),
.C_PROBE659_WIDTH(1),
.C_PROBE660_WIDTH(1),
.C_PROBE661_WIDTH(1),
.C_PROBE662_WIDTH(1),
.C_PROBE663_WIDTH(1),
.C_PROBE664_WIDTH(1),
.C_PROBE665_WIDTH(1),
.C_PROBE666_WIDTH(1),
.C_PROBE667_WIDTH(1),
.C_PROBE668_WIDTH(1),
.C_PROBE669_WIDTH(1),
.C_PROBE670_WIDTH(1),
.C_PROBE671_WIDTH(1),
.C_PROBE672_WIDTH(1),
.C_PROBE673_WIDTH(1),
.C_PROBE674_WIDTH(1),
.C_PROBE675_WIDTH(1),
.C_PROBE676_WIDTH(1),
.C_PROBE677_WIDTH(1),
.C_PROBE678_WIDTH(1),
.C_PROBE679_WIDTH(1),
.C_PROBE680_WIDTH(1),
.C_PROBE681_WIDTH(1),
.C_PROBE682_WIDTH(1),
.C_PROBE683_WIDTH(1),
.C_PROBE684_WIDTH(1),
.C_PROBE685_WIDTH(1),
.C_PROBE686_WIDTH(1),
.C_PROBE687_WIDTH(1),
.C_PROBE688_WIDTH(1),
.C_PROBE689_WIDTH(1),
.C_PROBE690_WIDTH(1),
.C_PROBE691_WIDTH(1),
.C_PROBE692_WIDTH(1),
.C_PROBE693_WIDTH(1),
.C_PROBE694_WIDTH(1),
.C_PROBE695_WIDTH(1),
.C_PROBE696_WIDTH(1),
.C_PROBE697_WIDTH(1),
.C_PROBE698_WIDTH(1),
.C_PROBE699_WIDTH(1),
.C_PROBE700_WIDTH(1),
.C_PROBE701_WIDTH(1),
.C_PROBE702_WIDTH(1),
.C_PROBE703_WIDTH(1),
.C_PROBE704_WIDTH(1),
.C_PROBE705_WIDTH(1),
.C_PROBE706_WIDTH(1),
.C_PROBE707_WIDTH(1),
.C_PROBE708_WIDTH(1),
.C_PROBE709_WIDTH(1),
.C_PROBE710_WIDTH(1),
.C_PROBE711_WIDTH(1),
.C_PROBE712_WIDTH(1),
.C_PROBE713_WIDTH(1),
.C_PROBE714_WIDTH(1),
.C_PROBE715_WIDTH(1),
.C_PROBE716_WIDTH(1),
.C_PROBE717_WIDTH(1),
.C_PROBE718_WIDTH(1),
.C_PROBE719_WIDTH(1),
.C_PROBE720_WIDTH(1),
.C_PROBE721_WIDTH(1),
.C_PROBE722_WIDTH(1),
.C_PROBE723_WIDTH(1),
.C_PROBE724_WIDTH(1),
.C_PROBE725_WIDTH(1),
.C_PROBE726_WIDTH(1),
.C_PROBE727_WIDTH(1),
.C_PROBE728_WIDTH(1),
.C_PROBE729_WIDTH(1),
.C_PROBE730_WIDTH(1),
.C_PROBE731_WIDTH(1),
.C_PROBE732_WIDTH(1),
.C_PROBE733_WIDTH(1),
.C_PROBE734_WIDTH(1),
.C_PROBE735_WIDTH(1),
.C_PROBE736_WIDTH(1),
.C_PROBE737_WIDTH(1),
.C_PROBE738_WIDTH(1),
.C_PROBE739_WIDTH(1),
.C_PROBE740_WIDTH(1),
.C_PROBE741_WIDTH(1),
.C_PROBE742_WIDTH(1),
.C_PROBE743_WIDTH(1),
.C_PROBE744_WIDTH(1),
.C_PROBE745_WIDTH(1),
.C_PROBE746_WIDTH(1),
.C_PROBE747_WIDTH(1),
.C_PROBE748_WIDTH(1),
.C_PROBE749_WIDTH(1),
.C_PROBE750_WIDTH(1),
.C_PROBE751_WIDTH(1),
.C_PROBE752_WIDTH(1),
.C_PROBE753_WIDTH(1),
.C_PROBE754_WIDTH(1),
.C_PROBE755_WIDTH(1),
.C_PROBE756_WIDTH(1),
.C_PROBE757_WIDTH(1),
.C_PROBE758_WIDTH(1),
.C_PROBE759_WIDTH(1),
.C_PROBE760_WIDTH(1),
.C_PROBE761_WIDTH(1),
.C_PROBE762_WIDTH(1),
.C_PROBE763_WIDTH(1),
.C_PROBE764_WIDTH(1),
.C_PROBE765_WIDTH(1),
.C_PROBE766_WIDTH(1),
.C_PROBE767_WIDTH(1),
.C_PROBE768_WIDTH(1),
.C_PROBE769_WIDTH(1),
.C_PROBE770_WIDTH(1),
.C_PROBE771_WIDTH(1),
.C_PROBE772_WIDTH(1),
.C_PROBE773_WIDTH(1),
.C_PROBE774_WIDTH(1),
.C_PROBE775_WIDTH(1),
.C_PROBE776_WIDTH(1),
.C_PROBE777_WIDTH(1),
.C_PROBE778_WIDTH(1),
.C_PROBE779_WIDTH(1),
.C_PROBE780_WIDTH(1),
.C_PROBE781_WIDTH(1),
.C_PROBE782_WIDTH(1),
.C_PROBE783_WIDTH(1),
.C_PROBE784_WIDTH(1),
.C_PROBE785_WIDTH(1),
.C_PROBE786_WIDTH(1),
.C_PROBE787_WIDTH(1),
.C_PROBE788_WIDTH(1),
.C_PROBE789_WIDTH(1),
.C_PROBE790_WIDTH(1),
.C_PROBE791_WIDTH(1),
.C_PROBE792_WIDTH(1),
.C_PROBE793_WIDTH(1),
.C_PROBE794_WIDTH(1),
.C_PROBE795_WIDTH(1),
.C_PROBE796_WIDTH(1),
.C_PROBE797_WIDTH(1),
.C_PROBE798_WIDTH(1),
.C_PROBE799_WIDTH(1),
.C_PROBE800_WIDTH(1),
.C_PROBE801_WIDTH(1),
.C_PROBE802_WIDTH(1),
.C_PROBE803_WIDTH(1),
.C_PROBE804_WIDTH(1),
.C_PROBE805_WIDTH(1),
.C_PROBE806_WIDTH(1),
.C_PROBE807_WIDTH(1),
.C_PROBE808_WIDTH(1),
.C_PROBE809_WIDTH(1),
.C_PROBE810_WIDTH(1),
.C_PROBE811_WIDTH(1),
.C_PROBE812_WIDTH(1),
.C_PROBE813_WIDTH(1),
.C_PROBE814_WIDTH(1),
.C_PROBE815_WIDTH(1),
.C_PROBE816_WIDTH(1),
.C_PROBE817_WIDTH(1),
.C_PROBE818_WIDTH(1),
.C_PROBE819_WIDTH(1),
.C_PROBE820_WIDTH(1),
.C_PROBE821_WIDTH(1),
.C_PROBE822_WIDTH(1),
.C_PROBE823_WIDTH(1),
.C_PROBE824_WIDTH(1),
.C_PROBE825_WIDTH(1),
.C_PROBE826_WIDTH(1),
.C_PROBE827_WIDTH(1),
.C_PROBE828_WIDTH(1),
.C_PROBE829_WIDTH(1),
.C_PROBE830_WIDTH(1),
.C_PROBE831_WIDTH(1),
.C_PROBE832_WIDTH(1),
.C_PROBE833_WIDTH(1),
.C_PROBE834_WIDTH(1),
.C_PROBE835_WIDTH(1),
.C_PROBE836_WIDTH(1),
.C_PROBE837_WIDTH(1),
.C_PROBE838_WIDTH(1),
.C_PROBE839_WIDTH(1),
.C_PROBE840_WIDTH(1),
.C_PROBE841_WIDTH(1),
.C_PROBE842_WIDTH(1),
.C_PROBE843_WIDTH(1),
.C_PROBE844_WIDTH(1),
.C_PROBE845_WIDTH(1),
.C_PROBE846_WIDTH(1),
.C_PROBE847_WIDTH(1),
.C_PROBE848_WIDTH(1),
.C_PROBE849_WIDTH(1),
.C_PROBE850_WIDTH(1),
.C_PROBE851_WIDTH(1),
.C_PROBE852_WIDTH(1),
.C_PROBE853_WIDTH(1),
.C_PROBE854_WIDTH(1),
.C_PROBE855_WIDTH(1),
.C_PROBE856_WIDTH(1),
.C_PROBE857_WIDTH(1),
.C_PROBE858_WIDTH(1),
.C_PROBE859_WIDTH(1),
.C_PROBE860_WIDTH(1),
.C_PROBE861_WIDTH(1),
.C_PROBE862_WIDTH(1),
.C_PROBE863_WIDTH(1),
.C_PROBE864_WIDTH(1),
.C_PROBE865_WIDTH(1),
.C_PROBE866_WIDTH(1),
.C_PROBE867_WIDTH(1),
.C_PROBE868_WIDTH(1),
.C_PROBE869_WIDTH(1),
.C_PROBE870_WIDTH(1),
.C_PROBE871_WIDTH(1),
.C_PROBE872_WIDTH(1),
.C_PROBE873_WIDTH(1),
.C_PROBE874_WIDTH(1),
.C_PROBE875_WIDTH(1),
.C_PROBE876_WIDTH(1),
.C_PROBE877_WIDTH(1),
.C_PROBE878_WIDTH(1),
.C_PROBE879_WIDTH(1),
.C_PROBE880_WIDTH(1),
.C_PROBE881_WIDTH(1),
.C_PROBE882_WIDTH(1),
.C_PROBE883_WIDTH(1),
.C_PROBE884_WIDTH(1),
.C_PROBE885_WIDTH(1),
.C_PROBE886_WIDTH(1),
.C_PROBE887_WIDTH(1),
.C_PROBE888_WIDTH(1),
.C_PROBE889_WIDTH(1),
.C_PROBE890_WIDTH(1),
.C_PROBE891_WIDTH(1),
.C_PROBE892_WIDTH(1),
.C_PROBE893_WIDTH(1),
.C_PROBE894_WIDTH(1),
.C_PROBE895_WIDTH(1),
.C_PROBE896_WIDTH(1),
.C_PROBE897_WIDTH(1),
.C_PROBE898_WIDTH(1),
.C_PROBE899_WIDTH(1),
.C_PROBE900_WIDTH(1),
.C_PROBE901_WIDTH(1),
.C_PROBE902_WIDTH(1),
.C_PROBE903_WIDTH(1),
.C_PROBE904_WIDTH(1),
.C_PROBE905_WIDTH(1),
.C_PROBE906_WIDTH(1),
.C_PROBE907_WIDTH(1),
.C_PROBE908_WIDTH(1),
.C_PROBE909_WIDTH(1),
.C_PROBE910_WIDTH(1),
.C_PROBE911_WIDTH(1),
.C_PROBE912_WIDTH(1),
.C_PROBE913_WIDTH(1),
.C_PROBE914_WIDTH(1),
.C_PROBE915_WIDTH(1),
.C_PROBE916_WIDTH(1),
.C_PROBE917_WIDTH(1),
.C_PROBE918_WIDTH(1),
.C_PROBE919_WIDTH(1),
.C_PROBE920_WIDTH(1),
.C_PROBE921_WIDTH(1),
.C_PROBE922_WIDTH(1),
.C_PROBE923_WIDTH(1),
.C_PROBE924_WIDTH(1),
.C_PROBE925_WIDTH(1),
.C_PROBE926_WIDTH(1),
.C_PROBE927_WIDTH(1),
.C_PROBE928_WIDTH(1),
.C_PROBE929_WIDTH(1),
.C_PROBE930_WIDTH(1),
.C_PROBE931_WIDTH(1),
.C_PROBE932_WIDTH(1),
.C_PROBE933_WIDTH(1),
.C_PROBE934_WIDTH(1),
.C_PROBE935_WIDTH(1),
.C_PROBE936_WIDTH(1),
.C_PROBE937_WIDTH(1),
.C_PROBE938_WIDTH(1),
.C_PROBE939_WIDTH(1),
.C_PROBE940_WIDTH(1),
.C_PROBE941_WIDTH(1),
.C_PROBE942_WIDTH(1),
.C_PROBE943_WIDTH(1),
.C_PROBE944_WIDTH(1),
.C_PROBE945_WIDTH(1),
.C_PROBE946_WIDTH(1),
.C_PROBE947_WIDTH(1),
.C_PROBE948_WIDTH(1),
.C_PROBE949_WIDTH(1),
.C_PROBE950_WIDTH(1),
.C_PROBE951_WIDTH(1),
.C_PROBE952_WIDTH(1),
.C_PROBE953_WIDTH(1),
.C_PROBE954_WIDTH(1),
.C_PROBE955_WIDTH(1),
.C_PROBE956_WIDTH(1),
.C_PROBE957_WIDTH(1),
.C_PROBE958_WIDTH(1),
.C_PROBE959_WIDTH(1),
.C_PROBE960_WIDTH(1),
.C_PROBE961_WIDTH(1),
.C_PROBE962_WIDTH(1),
.C_PROBE963_WIDTH(1),
.C_PROBE964_WIDTH(1),
.C_PROBE965_WIDTH(1),
.C_PROBE966_WIDTH(1),
.C_PROBE967_WIDTH(1),
.C_PROBE968_WIDTH(1),
.C_PROBE969_WIDTH(1),
.C_PROBE970_WIDTH(1),
.C_PROBE971_WIDTH(1),
.C_PROBE972_WIDTH(1),
.C_PROBE973_WIDTH(1),
.C_PROBE974_WIDTH(1),
.C_PROBE975_WIDTH(1),
.C_PROBE976_WIDTH(1),
.C_PROBE977_WIDTH(1),
.C_PROBE978_WIDTH(1),
.C_PROBE979_WIDTH(1),
.C_PROBE980_WIDTH(1),
.C_PROBE981_WIDTH(1),
.C_PROBE982_WIDTH(1),
.C_PROBE983_WIDTH(1),
.C_PROBE984_WIDTH(1),
.C_PROBE985_WIDTH(1),
.C_PROBE986_WIDTH(1),
.C_PROBE987_WIDTH(1),
.C_PROBE988_WIDTH(1),
.C_PROBE989_WIDTH(1),
.C_PROBE990_WIDTH(1),
.C_PROBE991_WIDTH(1),
.C_PROBE992_WIDTH(1),
.C_PROBE993_WIDTH(1),
.C_PROBE994_WIDTH(1),
.C_PROBE995_WIDTH(1),
.C_PROBE996_WIDTH(1),
.C_PROBE997_WIDTH(1),
.C_PROBE998_WIDTH(1),
.C_PROBE999_WIDTH(1),
.C_PROBE1000_WIDTH(1),
.C_PROBE1001_WIDTH(1),
.C_PROBE1002_WIDTH(1),
.C_PROBE1003_WIDTH(1),
.C_PROBE1004_WIDTH(1),
.C_PROBE1005_WIDTH(1),
.C_PROBE1006_WIDTH(1),
.C_PROBE1007_WIDTH(1),
.C_PROBE1008_WIDTH(1),
.C_PROBE1009_WIDTH(1),
.C_PROBE1010_WIDTH(1),
.C_PROBE1011_WIDTH(1),
.C_PROBE1012_WIDTH(1),
.C_PROBE1013_WIDTH(1),
.C_PROBE1014_WIDTH(1),
.C_PROBE1015_WIDTH(1),
.C_PROBE1016_WIDTH(1),
.C_PROBE1017_WIDTH(1),
.C_PROBE1018_WIDTH(1),
.C_PROBE1019_WIDTH(1),
.C_PROBE1020_WIDTH(1),
.C_PROBE1021_WIDTH(1),
.C_PROBE1022_WIDTH(1),
.C_PROBE1023_WIDTH(1),
.C_PROBE0_MU_CNT(1),
.C_PROBE1_MU_CNT(1),
.C_PROBE2_MU_CNT(1),
.C_PROBE3_MU_CNT(1),
.C_PROBE4_MU_CNT(1),
.C_PROBE5_MU_CNT(1),
.C_PROBE6_MU_CNT(1),
.C_PROBE7_MU_CNT(1),
.C_PROBE8_MU_CNT(1),
.C_PROBE9_MU_CNT(1),
.C_PROBE10_MU_CNT(1),
.C_PROBE11_MU_CNT(1),
.C_PROBE12_MU_CNT(1),
.C_PROBE13_MU_CNT(1),
.C_PROBE14_MU_CNT(1),
.C_PROBE15_MU_CNT(1),
.C_PROBE16_MU_CNT(1),
.C_PROBE17_MU_CNT(1),
.C_PROBE18_MU_CNT(1),
.C_PROBE19_MU_CNT(1),
.C_PROBE20_MU_CNT(1),
.C_PROBE21_MU_CNT(1),
.C_PROBE22_MU_CNT(1),
.C_PROBE23_MU_CNT(1),
.C_PROBE24_MU_CNT(1),
.C_PROBE25_MU_CNT(1),
.C_PROBE26_MU_CNT(1),
.C_PROBE27_MU_CNT(1),
.C_PROBE28_MU_CNT(1),
.C_PROBE29_MU_CNT(1),
.C_PROBE30_MU_CNT(1),
.C_PROBE31_MU_CNT(1),
.C_PROBE32_MU_CNT(1),
.C_PROBE33_MU_CNT(1),
.C_PROBE34_MU_CNT(1),
.C_PROBE35_MU_CNT(1),
.C_PROBE36_MU_CNT(1),
.C_PROBE37_MU_CNT(1),
.C_PROBE38_MU_CNT(1),
.C_PROBE39_MU_CNT(1),
.C_PROBE40_MU_CNT(1),
.C_PROBE41_MU_CNT(1),
.C_PROBE42_MU_CNT(1),
.C_PROBE43_MU_CNT(1),
.C_PROBE44_MU_CNT(1),
.C_PROBE45_MU_CNT(1),
.C_PROBE46_MU_CNT(1),
.C_PROBE47_MU_CNT(1),
.C_PROBE48_MU_CNT(1),
.C_PROBE49_MU_CNT(1),
.C_PROBE50_MU_CNT(1),
.C_PROBE51_MU_CNT(1),
.C_PROBE52_MU_CNT(1),
.C_PROBE53_MU_CNT(1),
.C_PROBE54_MU_CNT(1),
.C_PROBE55_MU_CNT(1),
.C_PROBE56_MU_CNT(1),
.C_PROBE57_MU_CNT(1),
.C_PROBE58_MU_CNT(1),
.C_PROBE59_MU_CNT(1),
.C_PROBE60_MU_CNT(1),
.C_PROBE61_MU_CNT(1),
.C_PROBE62_MU_CNT(1),
.C_PROBE63_MU_CNT(1),
.C_PROBE64_MU_CNT(1),
.C_PROBE65_MU_CNT(1),
.C_PROBE66_MU_CNT(1),
.C_PROBE67_MU_CNT(1),
.C_PROBE68_MU_CNT(1),
.C_PROBE69_MU_CNT(1),
.C_PROBE70_MU_CNT(1),
.C_PROBE71_MU_CNT(1),
.C_PROBE72_MU_CNT(1),
.C_PROBE73_MU_CNT(1),
.C_PROBE74_MU_CNT(1),
.C_PROBE75_MU_CNT(1),
.C_PROBE76_MU_CNT(1),
.C_PROBE77_MU_CNT(1),
.C_PROBE78_MU_CNT(1),
.C_PROBE79_MU_CNT(1),
.C_PROBE80_MU_CNT(1),
.C_PROBE81_MU_CNT(1),
.C_PROBE82_MU_CNT(1),
.C_PROBE83_MU_CNT(1),
.C_PROBE84_MU_CNT(1),
.C_PROBE85_MU_CNT(1),
.C_PROBE86_MU_CNT(1),
.C_PROBE87_MU_CNT(1),
.C_PROBE88_MU_CNT(1),
.C_PROBE89_MU_CNT(1),
.C_PROBE90_MU_CNT(1),
.C_PROBE91_MU_CNT(1),
.C_PROBE92_MU_CNT(1),
.C_PROBE93_MU_CNT(1),
.C_PROBE94_MU_CNT(1),
.C_PROBE95_MU_CNT(1),
.C_PROBE96_MU_CNT(1),
.C_PROBE97_MU_CNT(1),
.C_PROBE98_MU_CNT(1),
.C_PROBE99_MU_CNT(1),
.C_PROBE100_MU_CNT(1),
.C_PROBE101_MU_CNT(1),
.C_PROBE102_MU_CNT(1),
.C_PROBE103_MU_CNT(1),
.C_PROBE104_MU_CNT(1),
.C_PROBE105_MU_CNT(1),
.C_PROBE106_MU_CNT(1),
.C_PROBE107_MU_CNT(1),
.C_PROBE108_MU_CNT(1),
.C_PROBE109_MU_CNT(1),
.C_PROBE110_MU_CNT(1),
.C_PROBE111_MU_CNT(1),
.C_PROBE112_MU_CNT(1),
.C_PROBE113_MU_CNT(1),
.C_PROBE114_MU_CNT(1),
.C_PROBE115_MU_CNT(1),
.C_PROBE116_MU_CNT(1),
.C_PROBE117_MU_CNT(1),
.C_PROBE118_MU_CNT(1),
.C_PROBE119_MU_CNT(1),
.C_PROBE120_MU_CNT(1),
.C_PROBE121_MU_CNT(1),
.C_PROBE122_MU_CNT(1),
.C_PROBE123_MU_CNT(1),
.C_PROBE124_MU_CNT(1),
.C_PROBE125_MU_CNT(1),
.C_PROBE126_MU_CNT(1),
.C_PROBE127_MU_CNT(1),
.C_PROBE128_MU_CNT(1),
.C_PROBE129_MU_CNT(1),
.C_PROBE130_MU_CNT(1),
.C_PROBE131_MU_CNT(1),
.C_PROBE132_MU_CNT(1),
.C_PROBE133_MU_CNT(1),
.C_PROBE134_MU_CNT(1),
.C_PROBE135_MU_CNT(1),
.C_PROBE136_MU_CNT(1),
.C_PROBE137_MU_CNT(1),
.C_PROBE138_MU_CNT(1),
.C_PROBE139_MU_CNT(1),
.C_PROBE140_MU_CNT(1),
.C_PROBE141_MU_CNT(1),
.C_PROBE142_MU_CNT(1),
.C_PROBE143_MU_CNT(1),
.C_PROBE144_MU_CNT(1),
.C_PROBE145_MU_CNT(1),
.C_PROBE146_MU_CNT(1),
.C_PROBE147_MU_CNT(1),
.C_PROBE148_MU_CNT(1),
.C_PROBE149_MU_CNT(1),
.C_PROBE150_MU_CNT(1),
.C_PROBE151_MU_CNT(1),
.C_PROBE152_MU_CNT(1),
.C_PROBE153_MU_CNT(1),
.C_PROBE154_MU_CNT(1),
.C_PROBE155_MU_CNT(1),
.C_PROBE156_MU_CNT(1),
.C_PROBE157_MU_CNT(1),
.C_PROBE158_MU_CNT(1),
.C_PROBE159_MU_CNT(1),
.C_PROBE160_MU_CNT(1),
.C_PROBE161_MU_CNT(1),
.C_PROBE162_MU_CNT(1),
.C_PROBE163_MU_CNT(1),
.C_PROBE164_MU_CNT(1),
.C_PROBE165_MU_CNT(1),
.C_PROBE166_MU_CNT(1),
.C_PROBE167_MU_CNT(1),
.C_PROBE168_MU_CNT(1),
.C_PROBE169_MU_CNT(1),
.C_PROBE170_MU_CNT(1),
.C_PROBE171_MU_CNT(1),
.C_PROBE172_MU_CNT(1),
.C_PROBE173_MU_CNT(1),
.C_PROBE174_MU_CNT(1),
.C_PROBE175_MU_CNT(1),
.C_PROBE176_MU_CNT(1),
.C_PROBE177_MU_CNT(1),
.C_PROBE178_MU_CNT(1),
.C_PROBE179_MU_CNT(1),
.C_PROBE180_MU_CNT(1),
.C_PROBE181_MU_CNT(1),
.C_PROBE182_MU_CNT(1),
.C_PROBE183_MU_CNT(1),
.C_PROBE184_MU_CNT(1),
.C_PROBE185_MU_CNT(1),
.C_PROBE186_MU_CNT(1),
.C_PROBE187_MU_CNT(1),
.C_PROBE188_MU_CNT(1),
.C_PROBE189_MU_CNT(1),
.C_PROBE190_MU_CNT(1),
.C_PROBE191_MU_CNT(1),
.C_PROBE192_MU_CNT(1),
.C_PROBE193_MU_CNT(1),
.C_PROBE194_MU_CNT(1),
.C_PROBE195_MU_CNT(1),
.C_PROBE196_MU_CNT(1),
.C_PROBE197_MU_CNT(1),
.C_PROBE198_MU_CNT(1),
.C_PROBE199_MU_CNT(1),
.C_PROBE200_MU_CNT(1),
.C_PROBE201_MU_CNT(1),
.C_PROBE202_MU_CNT(1),
.C_PROBE203_MU_CNT(1),
.C_PROBE204_MU_CNT(1),
.C_PROBE205_MU_CNT(1),
.C_PROBE206_MU_CNT(1),
.C_PROBE207_MU_CNT(1),
.C_PROBE208_MU_CNT(1),
.C_PROBE209_MU_CNT(1),
.C_PROBE210_MU_CNT(1),
.C_PROBE211_MU_CNT(1),
.C_PROBE212_MU_CNT(1),
.C_PROBE213_MU_CNT(1),
.C_PROBE214_MU_CNT(1),
.C_PROBE215_MU_CNT(1),
.C_PROBE216_MU_CNT(1),
.C_PROBE217_MU_CNT(1),
.C_PROBE218_MU_CNT(1),
.C_PROBE219_MU_CNT(1),
.C_PROBE220_MU_CNT(1),
.C_PROBE221_MU_CNT(1),
.C_PROBE222_MU_CNT(1),
.C_PROBE223_MU_CNT(1),
.C_PROBE224_MU_CNT(1),
.C_PROBE225_MU_CNT(1),
.C_PROBE226_MU_CNT(1),
.C_PROBE227_MU_CNT(1),
.C_PROBE228_MU_CNT(1),
.C_PROBE229_MU_CNT(1),
.C_PROBE230_MU_CNT(1),
.C_PROBE231_MU_CNT(1),
.C_PROBE232_MU_CNT(1),
.C_PROBE233_MU_CNT(1),
.C_PROBE234_MU_CNT(1),
.C_PROBE235_MU_CNT(1),
.C_PROBE236_MU_CNT(1),
.C_PROBE237_MU_CNT(1),
.C_PROBE238_MU_CNT(1),
.C_PROBE239_MU_CNT(1),
.C_PROBE240_MU_CNT(1),
.C_PROBE241_MU_CNT(1),
.C_PROBE242_MU_CNT(1),
.C_PROBE243_MU_CNT(1),
.C_PROBE244_MU_CNT(1),
.C_PROBE245_MU_CNT(1),
.C_PROBE246_MU_CNT(1),
.C_PROBE247_MU_CNT(1),
.C_PROBE248_MU_CNT(1),
.C_PROBE249_MU_CNT(1),
.C_PROBE250_MU_CNT(1),
.C_PROBE251_MU_CNT(1),
.C_PROBE252_MU_CNT(1),
.C_PROBE253_MU_CNT(1),
.C_PROBE254_MU_CNT(1),
.C_PROBE255_MU_CNT(1),
.C_PROBE256_MU_CNT(1),
.C_PROBE257_MU_CNT(1),
.C_PROBE258_MU_CNT(1),
.C_PROBE259_MU_CNT(1),
.C_PROBE260_MU_CNT(1),
.C_PROBE261_MU_CNT(1),
.C_PROBE262_MU_CNT(1),
.C_PROBE263_MU_CNT(1),
.C_PROBE264_MU_CNT(1),
.C_PROBE265_MU_CNT(1),
.C_PROBE266_MU_CNT(1),
.C_PROBE267_MU_CNT(1),
.C_PROBE268_MU_CNT(1),
.C_PROBE269_MU_CNT(1),
.C_PROBE270_MU_CNT(1),
.C_PROBE271_MU_CNT(1),
.C_PROBE272_MU_CNT(1),
.C_PROBE273_MU_CNT(1),
.C_PROBE274_MU_CNT(1),
.C_PROBE275_MU_CNT(1),
.C_PROBE276_MU_CNT(1),
.C_PROBE277_MU_CNT(1),
.C_PROBE278_MU_CNT(1),
.C_PROBE279_MU_CNT(1),
.C_PROBE280_MU_CNT(1),
.C_PROBE281_MU_CNT(1),
.C_PROBE282_MU_CNT(1),
.C_PROBE283_MU_CNT(1),
.C_PROBE284_MU_CNT(1),
.C_PROBE285_MU_CNT(1),
.C_PROBE286_MU_CNT(1),
.C_PROBE287_MU_CNT(1),
.C_PROBE288_MU_CNT(1),
.C_PROBE289_MU_CNT(1),
.C_PROBE290_MU_CNT(1),
.C_PROBE291_MU_CNT(1),
.C_PROBE292_MU_CNT(1),
.C_PROBE293_MU_CNT(1),
.C_PROBE294_MU_CNT(1),
.C_PROBE295_MU_CNT(1),
.C_PROBE296_MU_CNT(1),
.C_PROBE297_MU_CNT(1),
.C_PROBE298_MU_CNT(1),
.C_PROBE299_MU_CNT(1),
.C_PROBE300_MU_CNT(1),
.C_PROBE301_MU_CNT(1),
.C_PROBE302_MU_CNT(1),
.C_PROBE303_MU_CNT(1),
.C_PROBE304_MU_CNT(1),
.C_PROBE305_MU_CNT(1),
.C_PROBE306_MU_CNT(1),
.C_PROBE307_MU_CNT(1),
.C_PROBE308_MU_CNT(1),
.C_PROBE309_MU_CNT(1),
.C_PROBE310_MU_CNT(1),
.C_PROBE311_MU_CNT(1),
.C_PROBE312_MU_CNT(1),
.C_PROBE313_MU_CNT(1),
.C_PROBE314_MU_CNT(1),
.C_PROBE315_MU_CNT(1),
.C_PROBE316_MU_CNT(1),
.C_PROBE317_MU_CNT(1),
.C_PROBE318_MU_CNT(1),
.C_PROBE319_MU_CNT(1),
.C_PROBE320_MU_CNT(1),
.C_PROBE321_MU_CNT(1),
.C_PROBE322_MU_CNT(1),
.C_PROBE323_MU_CNT(1),
.C_PROBE324_MU_CNT(1),
.C_PROBE325_MU_CNT(1),
.C_PROBE326_MU_CNT(1),
.C_PROBE327_MU_CNT(1),
.C_PROBE328_MU_CNT(1),
.C_PROBE329_MU_CNT(1),
.C_PROBE330_MU_CNT(1),
.C_PROBE331_MU_CNT(1),
.C_PROBE332_MU_CNT(1),
.C_PROBE333_MU_CNT(1),
.C_PROBE334_MU_CNT(1),
.C_PROBE335_MU_CNT(1),
.C_PROBE336_MU_CNT(1),
.C_PROBE337_MU_CNT(1),
.C_PROBE338_MU_CNT(1),
.C_PROBE339_MU_CNT(1),
.C_PROBE340_MU_CNT(1),
.C_PROBE341_MU_CNT(1),
.C_PROBE342_MU_CNT(1),
.C_PROBE343_MU_CNT(1),
.C_PROBE344_MU_CNT(1),
.C_PROBE345_MU_CNT(1),
.C_PROBE346_MU_CNT(1),
.C_PROBE347_MU_CNT(1),
.C_PROBE348_MU_CNT(1),
.C_PROBE349_MU_CNT(1),
.C_PROBE350_MU_CNT(1),
.C_PROBE351_MU_CNT(1),
.C_PROBE352_MU_CNT(1),
.C_PROBE353_MU_CNT(1),
.C_PROBE354_MU_CNT(1),
.C_PROBE355_MU_CNT(1),
.C_PROBE356_MU_CNT(1),
.C_PROBE357_MU_CNT(1),
.C_PROBE358_MU_CNT(1),
.C_PROBE359_MU_CNT(1),
.C_PROBE360_MU_CNT(1),
.C_PROBE361_MU_CNT(1),
.C_PROBE362_MU_CNT(1),
.C_PROBE363_MU_CNT(1),
.C_PROBE364_MU_CNT(1),
.C_PROBE365_MU_CNT(1),
.C_PROBE366_MU_CNT(1),
.C_PROBE367_MU_CNT(1),
.C_PROBE368_MU_CNT(1),
.C_PROBE369_MU_CNT(1),
.C_PROBE370_MU_CNT(1),
.C_PROBE371_MU_CNT(1),
.C_PROBE372_MU_CNT(1),
.C_PROBE373_MU_CNT(1),
.C_PROBE374_MU_CNT(1),
.C_PROBE375_MU_CNT(1),
.C_PROBE376_MU_CNT(1),
.C_PROBE377_MU_CNT(1),
.C_PROBE378_MU_CNT(1),
.C_PROBE379_MU_CNT(1),
.C_PROBE380_MU_CNT(1),
.C_PROBE381_MU_CNT(1),
.C_PROBE382_MU_CNT(1),
.C_PROBE383_MU_CNT(1),
.C_PROBE384_MU_CNT(1),
.C_PROBE385_MU_CNT(1),
.C_PROBE386_MU_CNT(1),
.C_PROBE387_MU_CNT(1),
.C_PROBE388_MU_CNT(1),
.C_PROBE389_MU_CNT(1),
.C_PROBE390_MU_CNT(1),
.C_PROBE391_MU_CNT(1),
.C_PROBE392_MU_CNT(1),
.C_PROBE393_MU_CNT(1),
.C_PROBE394_MU_CNT(1),
.C_PROBE395_MU_CNT(1),
.C_PROBE396_MU_CNT(1),
.C_PROBE397_MU_CNT(1),
.C_PROBE398_MU_CNT(1),
.C_PROBE399_MU_CNT(1),
.C_PROBE400_MU_CNT(1),
.C_PROBE401_MU_CNT(1),
.C_PROBE402_MU_CNT(1),
.C_PROBE403_MU_CNT(1),
.C_PROBE404_MU_CNT(1),
.C_PROBE405_MU_CNT(1),
.C_PROBE406_MU_CNT(1),
.C_PROBE407_MU_CNT(1),
.C_PROBE408_MU_CNT(1),
.C_PROBE409_MU_CNT(1),
.C_PROBE410_MU_CNT(1),
.C_PROBE411_MU_CNT(1),
.C_PROBE412_MU_CNT(1),
.C_PROBE413_MU_CNT(1),
.C_PROBE414_MU_CNT(1),
.C_PROBE415_MU_CNT(1),
.C_PROBE416_MU_CNT(1),
.C_PROBE417_MU_CNT(1),
.C_PROBE418_MU_CNT(1),
.C_PROBE419_MU_CNT(1),
.C_PROBE420_MU_CNT(1),
.C_PROBE421_MU_CNT(1),
.C_PROBE422_MU_CNT(1),
.C_PROBE423_MU_CNT(1),
.C_PROBE424_MU_CNT(1),
.C_PROBE425_MU_CNT(1),
.C_PROBE426_MU_CNT(1),
.C_PROBE427_MU_CNT(1),
.C_PROBE428_MU_CNT(1),
.C_PROBE429_MU_CNT(1),
.C_PROBE430_MU_CNT(1),
.C_PROBE431_MU_CNT(1),
.C_PROBE432_MU_CNT(1),
.C_PROBE433_MU_CNT(1),
.C_PROBE434_MU_CNT(1),
.C_PROBE435_MU_CNT(1),
.C_PROBE436_MU_CNT(1),
.C_PROBE437_MU_CNT(1),
.C_PROBE438_MU_CNT(1),
.C_PROBE439_MU_CNT(1),
.C_PROBE440_MU_CNT(1),
.C_PROBE441_MU_CNT(1),
.C_PROBE442_MU_CNT(1),
.C_PROBE443_MU_CNT(1),
.C_PROBE444_MU_CNT(1),
.C_PROBE445_MU_CNT(1),
.C_PROBE446_MU_CNT(1),
.C_PROBE447_MU_CNT(1),
.C_PROBE448_MU_CNT(1),
.C_PROBE449_MU_CNT(1),
.C_PROBE450_MU_CNT(1),
.C_PROBE451_MU_CNT(1),
.C_PROBE452_MU_CNT(1),
.C_PROBE453_MU_CNT(1),
.C_PROBE454_MU_CNT(1),
.C_PROBE455_MU_CNT(1),
.C_PROBE456_MU_CNT(1),
.C_PROBE457_MU_CNT(1),
.C_PROBE458_MU_CNT(1),
.C_PROBE459_MU_CNT(1),
.C_PROBE460_MU_CNT(1),
.C_PROBE461_MU_CNT(1),
.C_PROBE462_MU_CNT(1),
.C_PROBE463_MU_CNT(1),
.C_PROBE464_MU_CNT(1),
.C_PROBE465_MU_CNT(1),
.C_PROBE466_MU_CNT(1),
.C_PROBE467_MU_CNT(1),
.C_PROBE468_MU_CNT(1),
.C_PROBE469_MU_CNT(1),
.C_PROBE470_MU_CNT(1),
.C_PROBE471_MU_CNT(1),
.C_PROBE472_MU_CNT(1),
.C_PROBE473_MU_CNT(1),
.C_PROBE474_MU_CNT(1),
.C_PROBE475_MU_CNT(1),
.C_PROBE476_MU_CNT(1),
.C_PROBE477_MU_CNT(1),
.C_PROBE478_MU_CNT(1),
.C_PROBE479_MU_CNT(1),
.C_PROBE480_MU_CNT(1),
.C_PROBE481_MU_CNT(1),
.C_PROBE482_MU_CNT(1),
.C_PROBE483_MU_CNT(1),
.C_PROBE484_MU_CNT(1),
.C_PROBE485_MU_CNT(1),
.C_PROBE486_MU_CNT(1),
.C_PROBE487_MU_CNT(1),
.C_PROBE488_MU_CNT(1),
.C_PROBE489_MU_CNT(1),
.C_PROBE490_MU_CNT(1),
.C_PROBE491_MU_CNT(1),
.C_PROBE492_MU_CNT(1),
.C_PROBE493_MU_CNT(1),
.C_PROBE494_MU_CNT(1),
.C_PROBE495_MU_CNT(1),
.C_PROBE496_MU_CNT(1),
.C_PROBE497_MU_CNT(1),
.C_PROBE498_MU_CNT(1),
.C_PROBE499_MU_CNT(1),
.C_PROBE500_MU_CNT(1),
.C_PROBE501_MU_CNT(1),
.C_PROBE502_MU_CNT(1),
.C_PROBE503_MU_CNT(1),
.C_PROBE504_MU_CNT(1),
.C_PROBE505_MU_CNT(1),
.C_PROBE506_MU_CNT(1),
.C_PROBE507_MU_CNT(1),
.C_PROBE508_MU_CNT(1),
.C_PROBE509_MU_CNT(1),
.C_PROBE510_MU_CNT(1),
.C_PROBE511_MU_CNT(1),
.C_PROBE512_MU_CNT(1),
.C_PROBE513_MU_CNT(1),
.C_PROBE514_MU_CNT(1),
.C_PROBE515_MU_CNT(1),
.C_PROBE516_MU_CNT(1),
.C_PROBE517_MU_CNT(1),
.C_PROBE518_MU_CNT(1),
.C_PROBE519_MU_CNT(1),
.C_PROBE520_MU_CNT(1),
.C_PROBE521_MU_CNT(1),
.C_PROBE522_MU_CNT(1),
.C_PROBE523_MU_CNT(1),
.C_PROBE524_MU_CNT(1),
.C_PROBE525_MU_CNT(1),
.C_PROBE526_MU_CNT(1),
.C_PROBE527_MU_CNT(1),
.C_PROBE528_MU_CNT(1),
.C_PROBE529_MU_CNT(1),
.C_PROBE530_MU_CNT(1),
.C_PROBE531_MU_CNT(1),
.C_PROBE532_MU_CNT(1),
.C_PROBE533_MU_CNT(1),
.C_PROBE534_MU_CNT(1),
.C_PROBE535_MU_CNT(1),
.C_PROBE536_MU_CNT(1),
.C_PROBE537_MU_CNT(1),
.C_PROBE538_MU_CNT(1),
.C_PROBE539_MU_CNT(1),
.C_PROBE540_MU_CNT(1),
.C_PROBE541_MU_CNT(1),
.C_PROBE542_MU_CNT(1),
.C_PROBE543_MU_CNT(1),
.C_PROBE544_MU_CNT(1),
.C_PROBE545_MU_CNT(1),
.C_PROBE546_MU_CNT(1),
.C_PROBE547_MU_CNT(1),
.C_PROBE548_MU_CNT(1),
.C_PROBE549_MU_CNT(1),
.C_PROBE550_MU_CNT(1),
.C_PROBE551_MU_CNT(1),
.C_PROBE552_MU_CNT(1),
.C_PROBE553_MU_CNT(1),
.C_PROBE554_MU_CNT(1),
.C_PROBE555_MU_CNT(1),
.C_PROBE556_MU_CNT(1),
.C_PROBE557_MU_CNT(1),
.C_PROBE558_MU_CNT(1),
.C_PROBE559_MU_CNT(1),
.C_PROBE560_MU_CNT(1),
.C_PROBE561_MU_CNT(1),
.C_PROBE562_MU_CNT(1),
.C_PROBE563_MU_CNT(1),
.C_PROBE564_MU_CNT(1),
.C_PROBE565_MU_CNT(1),
.C_PROBE566_MU_CNT(1),
.C_PROBE567_MU_CNT(1),
.C_PROBE568_MU_CNT(1),
.C_PROBE569_MU_CNT(1),
.C_PROBE570_MU_CNT(1),
.C_PROBE571_MU_CNT(1),
.C_PROBE572_MU_CNT(1),
.C_PROBE573_MU_CNT(1),
.C_PROBE574_MU_CNT(1),
.C_PROBE575_MU_CNT(1),
.C_PROBE576_MU_CNT(1),
.C_PROBE577_MU_CNT(1),
.C_PROBE578_MU_CNT(1),
.C_PROBE579_MU_CNT(1),
.C_PROBE580_MU_CNT(1),
.C_PROBE581_MU_CNT(1),
.C_PROBE582_MU_CNT(1),
.C_PROBE583_MU_CNT(1),
.C_PROBE584_MU_CNT(1),
.C_PROBE585_MU_CNT(1),
.C_PROBE586_MU_CNT(1),
.C_PROBE587_MU_CNT(1),
.C_PROBE588_MU_CNT(1),
.C_PROBE589_MU_CNT(1),
.C_PROBE590_MU_CNT(1),
.C_PROBE591_MU_CNT(1),
.C_PROBE592_MU_CNT(1),
.C_PROBE593_MU_CNT(1),
.C_PROBE594_MU_CNT(1),
.C_PROBE595_MU_CNT(1),
.C_PROBE596_MU_CNT(1),
.C_PROBE597_MU_CNT(1),
.C_PROBE598_MU_CNT(1),
.C_PROBE599_MU_CNT(1),
.C_PROBE600_MU_CNT(1),
.C_PROBE601_MU_CNT(1),
.C_PROBE602_MU_CNT(1),
.C_PROBE603_MU_CNT(1),
.C_PROBE604_MU_CNT(1),
.C_PROBE605_MU_CNT(1),
.C_PROBE606_MU_CNT(1),
.C_PROBE607_MU_CNT(1),
.C_PROBE608_MU_CNT(1),
.C_PROBE609_MU_CNT(1),
.C_PROBE610_MU_CNT(1),
.C_PROBE611_MU_CNT(1),
.C_PROBE612_MU_CNT(1),
.C_PROBE613_MU_CNT(1),
.C_PROBE614_MU_CNT(1),
.C_PROBE615_MU_CNT(1),
.C_PROBE616_MU_CNT(1),
.C_PROBE617_MU_CNT(1),
.C_PROBE618_MU_CNT(1),
.C_PROBE619_MU_CNT(1),
.C_PROBE620_MU_CNT(1),
.C_PROBE621_MU_CNT(1),
.C_PROBE622_MU_CNT(1),
.C_PROBE623_MU_CNT(1),
.C_PROBE624_MU_CNT(1),
.C_PROBE625_MU_CNT(1),
.C_PROBE626_MU_CNT(1),
.C_PROBE627_MU_CNT(1),
.C_PROBE628_MU_CNT(1),
.C_PROBE629_MU_CNT(1),
.C_PROBE630_MU_CNT(1),
.C_PROBE631_MU_CNT(1),
.C_PROBE632_MU_CNT(1),
.C_PROBE633_MU_CNT(1),
.C_PROBE634_MU_CNT(1),
.C_PROBE635_MU_CNT(1),
.C_PROBE636_MU_CNT(1),
.C_PROBE637_MU_CNT(1),
.C_PROBE638_MU_CNT(1),
.C_PROBE639_MU_CNT(1),
.C_PROBE640_MU_CNT(1),
.C_PROBE641_MU_CNT(1),
.C_PROBE642_MU_CNT(1),
.C_PROBE643_MU_CNT(1),
.C_PROBE644_MU_CNT(1),
.C_PROBE645_MU_CNT(1),
.C_PROBE646_MU_CNT(1),
.C_PROBE647_MU_CNT(1),
.C_PROBE648_MU_CNT(1),
.C_PROBE649_MU_CNT(1),
.C_PROBE650_MU_CNT(1),
.C_PROBE651_MU_CNT(1),
.C_PROBE652_MU_CNT(1),
.C_PROBE653_MU_CNT(1),
.C_PROBE654_MU_CNT(1),
.C_PROBE655_MU_CNT(1),
.C_PROBE656_MU_CNT(1),
.C_PROBE657_MU_CNT(1),
.C_PROBE658_MU_CNT(1),
.C_PROBE659_MU_CNT(1),
.C_PROBE660_MU_CNT(1),
.C_PROBE661_MU_CNT(1),
.C_PROBE662_MU_CNT(1),
.C_PROBE663_MU_CNT(1),
.C_PROBE664_MU_CNT(1),
.C_PROBE665_MU_CNT(1),
.C_PROBE666_MU_CNT(1),
.C_PROBE667_MU_CNT(1),
.C_PROBE668_MU_CNT(1),
.C_PROBE669_MU_CNT(1),
.C_PROBE670_MU_CNT(1),
.C_PROBE671_MU_CNT(1),
.C_PROBE672_MU_CNT(1),
.C_PROBE673_MU_CNT(1),
.C_PROBE674_MU_CNT(1),
.C_PROBE675_MU_CNT(1),
.C_PROBE676_MU_CNT(1),
.C_PROBE677_MU_CNT(1),
.C_PROBE678_MU_CNT(1),
.C_PROBE679_MU_CNT(1),
.C_PROBE680_MU_CNT(1),
.C_PROBE681_MU_CNT(1),
.C_PROBE682_MU_CNT(1),
.C_PROBE683_MU_CNT(1),
.C_PROBE684_MU_CNT(1),
.C_PROBE685_MU_CNT(1),
.C_PROBE686_MU_CNT(1),
.C_PROBE687_MU_CNT(1),
.C_PROBE688_MU_CNT(1),
.C_PROBE689_MU_CNT(1),
.C_PROBE690_MU_CNT(1),
.C_PROBE691_MU_CNT(1),
.C_PROBE692_MU_CNT(1),
.C_PROBE693_MU_CNT(1),
.C_PROBE694_MU_CNT(1),
.C_PROBE695_MU_CNT(1),
.C_PROBE696_MU_CNT(1),
.C_PROBE697_MU_CNT(1),
.C_PROBE698_MU_CNT(1),
.C_PROBE699_MU_CNT(1),
.C_PROBE700_MU_CNT(1),
.C_PROBE701_MU_CNT(1),
.C_PROBE702_MU_CNT(1),
.C_PROBE703_MU_CNT(1),
.C_PROBE704_MU_CNT(1),
.C_PROBE705_MU_CNT(1),
.C_PROBE706_MU_CNT(1),
.C_PROBE707_MU_CNT(1),
.C_PROBE708_MU_CNT(1),
.C_PROBE709_MU_CNT(1),
.C_PROBE710_MU_CNT(1),
.C_PROBE711_MU_CNT(1),
.C_PROBE712_MU_CNT(1),
.C_PROBE713_MU_CNT(1),
.C_PROBE714_MU_CNT(1),
.C_PROBE715_MU_CNT(1),
.C_PROBE716_MU_CNT(1),
.C_PROBE717_MU_CNT(1),
.C_PROBE718_MU_CNT(1),
.C_PROBE719_MU_CNT(1),
.C_PROBE720_MU_CNT(1),
.C_PROBE721_MU_CNT(1),
.C_PROBE722_MU_CNT(1),
.C_PROBE723_MU_CNT(1),
.C_PROBE724_MU_CNT(1),
.C_PROBE725_MU_CNT(1),
.C_PROBE726_MU_CNT(1),
.C_PROBE727_MU_CNT(1),
.C_PROBE728_MU_CNT(1),
.C_PROBE729_MU_CNT(1),
.C_PROBE730_MU_CNT(1),
.C_PROBE731_MU_CNT(1),
.C_PROBE732_MU_CNT(1),
.C_PROBE733_MU_CNT(1),
.C_PROBE734_MU_CNT(1),
.C_PROBE735_MU_CNT(1),
.C_PROBE736_MU_CNT(1),
.C_PROBE737_MU_CNT(1),
.C_PROBE738_MU_CNT(1),
.C_PROBE739_MU_CNT(1),
.C_PROBE740_MU_CNT(1),
.C_PROBE741_MU_CNT(1),
.C_PROBE742_MU_CNT(1),
.C_PROBE743_MU_CNT(1),
.C_PROBE744_MU_CNT(1),
.C_PROBE745_MU_CNT(1),
.C_PROBE746_MU_CNT(1),
.C_PROBE747_MU_CNT(1),
.C_PROBE748_MU_CNT(1),
.C_PROBE749_MU_CNT(1),
.C_PROBE750_MU_CNT(1),
.C_PROBE751_MU_CNT(1),
.C_PROBE752_MU_CNT(1),
.C_PROBE753_MU_CNT(1),
.C_PROBE754_MU_CNT(1),
.C_PROBE755_MU_CNT(1),
.C_PROBE756_MU_CNT(1),
.C_PROBE757_MU_CNT(1),
.C_PROBE758_MU_CNT(1),
.C_PROBE759_MU_CNT(1),
.C_PROBE760_MU_CNT(1),
.C_PROBE761_MU_CNT(1),
.C_PROBE762_MU_CNT(1),
.C_PROBE763_MU_CNT(1),
.C_PROBE764_MU_CNT(1),
.C_PROBE765_MU_CNT(1),
.C_PROBE766_MU_CNT(1),
.C_PROBE767_MU_CNT(1),
.C_PROBE768_MU_CNT(1),
.C_PROBE769_MU_CNT(1),
.C_PROBE770_MU_CNT(1),
.C_PROBE771_MU_CNT(1),
.C_PROBE772_MU_CNT(1),
.C_PROBE773_MU_CNT(1),
.C_PROBE774_MU_CNT(1),
.C_PROBE775_MU_CNT(1),
.C_PROBE776_MU_CNT(1),
.C_PROBE777_MU_CNT(1),
.C_PROBE778_MU_CNT(1),
.C_PROBE779_MU_CNT(1),
.C_PROBE780_MU_CNT(1),
.C_PROBE781_MU_CNT(1),
.C_PROBE782_MU_CNT(1),
.C_PROBE783_MU_CNT(1),
.C_PROBE784_MU_CNT(1),
.C_PROBE785_MU_CNT(1),
.C_PROBE786_MU_CNT(1),
.C_PROBE787_MU_CNT(1),
.C_PROBE788_MU_CNT(1),
.C_PROBE789_MU_CNT(1),
.C_PROBE790_MU_CNT(1),
.C_PROBE791_MU_CNT(1),
.C_PROBE792_MU_CNT(1),
.C_PROBE793_MU_CNT(1),
.C_PROBE794_MU_CNT(1),
.C_PROBE795_MU_CNT(1),
.C_PROBE796_MU_CNT(1),
.C_PROBE797_MU_CNT(1),
.C_PROBE798_MU_CNT(1),
.C_PROBE799_MU_CNT(1),
.C_PROBE800_MU_CNT(1),
.C_PROBE801_MU_CNT(1),
.C_PROBE802_MU_CNT(1),
.C_PROBE803_MU_CNT(1),
.C_PROBE804_MU_CNT(1),
.C_PROBE805_MU_CNT(1),
.C_PROBE806_MU_CNT(1),
.C_PROBE807_MU_CNT(1),
.C_PROBE808_MU_CNT(1),
.C_PROBE809_MU_CNT(1),
.C_PROBE810_MU_CNT(1),
.C_PROBE811_MU_CNT(1),
.C_PROBE812_MU_CNT(1),
.C_PROBE813_MU_CNT(1),
.C_PROBE814_MU_CNT(1),
.C_PROBE815_MU_CNT(1),
.C_PROBE816_MU_CNT(1),
.C_PROBE817_MU_CNT(1),
.C_PROBE818_MU_CNT(1),
.C_PROBE819_MU_CNT(1),
.C_PROBE820_MU_CNT(1),
.C_PROBE821_MU_CNT(1),
.C_PROBE822_MU_CNT(1),
.C_PROBE823_MU_CNT(1),
.C_PROBE824_MU_CNT(1),
.C_PROBE825_MU_CNT(1),
.C_PROBE826_MU_CNT(1),
.C_PROBE827_MU_CNT(1),
.C_PROBE828_MU_CNT(1),
.C_PROBE829_MU_CNT(1),
.C_PROBE830_MU_CNT(1),
.C_PROBE831_MU_CNT(1),
.C_PROBE832_MU_CNT(1),
.C_PROBE833_MU_CNT(1),
.C_PROBE834_MU_CNT(1),
.C_PROBE835_MU_CNT(1),
.C_PROBE836_MU_CNT(1),
.C_PROBE837_MU_CNT(1),
.C_PROBE838_MU_CNT(1),
.C_PROBE839_MU_CNT(1),
.C_PROBE840_MU_CNT(1),
.C_PROBE841_MU_CNT(1),
.C_PROBE842_MU_CNT(1),
.C_PROBE843_MU_CNT(1),
.C_PROBE844_MU_CNT(1),
.C_PROBE845_MU_CNT(1),
.C_PROBE846_MU_CNT(1),
.C_PROBE847_MU_CNT(1),
.C_PROBE848_MU_CNT(1),
.C_PROBE849_MU_CNT(1),
.C_PROBE850_MU_CNT(1),
.C_PROBE851_MU_CNT(1),
.C_PROBE852_MU_CNT(1),
.C_PROBE853_MU_CNT(1),
.C_PROBE854_MU_CNT(1),
.C_PROBE855_MU_CNT(1),
.C_PROBE856_MU_CNT(1),
.C_PROBE857_MU_CNT(1),
.C_PROBE858_MU_CNT(1),
.C_PROBE859_MU_CNT(1),
.C_PROBE860_MU_CNT(1),
.C_PROBE861_MU_CNT(1),
.C_PROBE862_MU_CNT(1),
.C_PROBE863_MU_CNT(1),
.C_PROBE864_MU_CNT(1),
.C_PROBE865_MU_CNT(1),
.C_PROBE866_MU_CNT(1),
.C_PROBE867_MU_CNT(1),
.C_PROBE868_MU_CNT(1),
.C_PROBE869_MU_CNT(1),
.C_PROBE870_MU_CNT(1),
.C_PROBE871_MU_CNT(1),
.C_PROBE872_MU_CNT(1),
.C_PROBE873_MU_CNT(1),
.C_PROBE874_MU_CNT(1),
.C_PROBE875_MU_CNT(1),
.C_PROBE876_MU_CNT(1),
.C_PROBE877_MU_CNT(1),
.C_PROBE878_MU_CNT(1),
.C_PROBE879_MU_CNT(1),
.C_PROBE880_MU_CNT(1),
.C_PROBE881_MU_CNT(1),
.C_PROBE882_MU_CNT(1),
.C_PROBE883_MU_CNT(1),
.C_PROBE884_MU_CNT(1),
.C_PROBE885_MU_CNT(1),
.C_PROBE886_MU_CNT(1),
.C_PROBE887_MU_CNT(1),
.C_PROBE888_MU_CNT(1),
.C_PROBE889_MU_CNT(1),
.C_PROBE890_MU_CNT(1),
.C_PROBE891_MU_CNT(1),
.C_PROBE892_MU_CNT(1),
.C_PROBE893_MU_CNT(1),
.C_PROBE894_MU_CNT(1),
.C_PROBE895_MU_CNT(1),
.C_PROBE896_MU_CNT(1),
.C_PROBE897_MU_CNT(1),
.C_PROBE898_MU_CNT(1),
.C_PROBE899_MU_CNT(1),
.C_PROBE900_MU_CNT(1),
.C_PROBE901_MU_CNT(1),
.C_PROBE902_MU_CNT(1),
.C_PROBE903_MU_CNT(1),
.C_PROBE904_MU_CNT(1),
.C_PROBE905_MU_CNT(1),
.C_PROBE906_MU_CNT(1),
.C_PROBE907_MU_CNT(1),
.C_PROBE908_MU_CNT(1),
.C_PROBE909_MU_CNT(1),
.C_PROBE910_MU_CNT(1),
.C_PROBE911_MU_CNT(1),
.C_PROBE912_MU_CNT(1),
.C_PROBE913_MU_CNT(1),
.C_PROBE914_MU_CNT(1),
.C_PROBE915_MU_CNT(1),
.C_PROBE916_MU_CNT(1),
.C_PROBE917_MU_CNT(1),
.C_PROBE918_MU_CNT(1),
.C_PROBE919_MU_CNT(1),
.C_PROBE920_MU_CNT(1),
.C_PROBE921_MU_CNT(1),
.C_PROBE922_MU_CNT(1),
.C_PROBE923_MU_CNT(1),
.C_PROBE924_MU_CNT(1),
.C_PROBE925_MU_CNT(1),
.C_PROBE926_MU_CNT(1),
.C_PROBE927_MU_CNT(1),
.C_PROBE928_MU_CNT(1),
.C_PROBE929_MU_CNT(1),
.C_PROBE930_MU_CNT(1),
.C_PROBE931_MU_CNT(1),
.C_PROBE932_MU_CNT(1),
.C_PROBE933_MU_CNT(1),
.C_PROBE934_MU_CNT(1),
.C_PROBE935_MU_CNT(1),
.C_PROBE936_MU_CNT(1),
.C_PROBE937_MU_CNT(1),
.C_PROBE938_MU_CNT(1),
.C_PROBE939_MU_CNT(1),
.C_PROBE940_MU_CNT(1),
.C_PROBE941_MU_CNT(1),
.C_PROBE942_MU_CNT(1),
.C_PROBE943_MU_CNT(1),
.C_PROBE944_MU_CNT(1),
.C_PROBE945_MU_CNT(1),
.C_PROBE946_MU_CNT(1),
.C_PROBE947_MU_CNT(1),
.C_PROBE948_MU_CNT(1),
.C_PROBE949_MU_CNT(1),
.C_PROBE950_MU_CNT(1),
.C_PROBE951_MU_CNT(1),
.C_PROBE952_MU_CNT(1),
.C_PROBE953_MU_CNT(1),
.C_PROBE954_MU_CNT(1),
.C_PROBE955_MU_CNT(1),
.C_PROBE956_MU_CNT(1),
.C_PROBE957_MU_CNT(1),
.C_PROBE958_MU_CNT(1),
.C_PROBE959_MU_CNT(1),
.C_PROBE960_MU_CNT(1),
.C_PROBE961_MU_CNT(1),
.C_PROBE962_MU_CNT(1),
.C_PROBE963_MU_CNT(1),
.C_PROBE964_MU_CNT(1),
.C_PROBE965_MU_CNT(1),
.C_PROBE966_MU_CNT(1),
.C_PROBE967_MU_CNT(1),
.C_PROBE968_MU_CNT(1),
.C_PROBE969_MU_CNT(1),
.C_PROBE970_MU_CNT(1),
.C_PROBE971_MU_CNT(1),
.C_PROBE972_MU_CNT(1),
.C_PROBE973_MU_CNT(1),
.C_PROBE974_MU_CNT(1),
.C_PROBE975_MU_CNT(1),
.C_PROBE976_MU_CNT(1),
.C_PROBE977_MU_CNT(1),
.C_PROBE978_MU_CNT(1),
.C_PROBE979_MU_CNT(1),
.C_PROBE980_MU_CNT(1),
.C_PROBE981_MU_CNT(1),
.C_PROBE982_MU_CNT(1),
.C_PROBE983_MU_CNT(1),
.C_PROBE984_MU_CNT(1),
.C_PROBE985_MU_CNT(1),
.C_PROBE986_MU_CNT(1),
.C_PROBE987_MU_CNT(1),
.C_PROBE988_MU_CNT(1),
.C_PROBE989_MU_CNT(1),
.C_PROBE990_MU_CNT(1),
.C_PROBE991_MU_CNT(1),
.C_PROBE992_MU_CNT(1),
.C_PROBE993_MU_CNT(1),
.C_PROBE994_MU_CNT(1),
.C_PROBE995_MU_CNT(1),
.C_PROBE996_MU_CNT(1),
.C_PROBE997_MU_CNT(1),
.C_PROBE998_MU_CNT(1),
.C_PROBE999_MU_CNT(1),
.C_PROBE1000_MU_CNT(1),
.C_PROBE1001_MU_CNT(1),
.C_PROBE1002_MU_CNT(1),
.C_PROBE1003_MU_CNT(1),
.C_PROBE1004_MU_CNT(1),
.C_PROBE1005_MU_CNT(1),
.C_PROBE1006_MU_CNT(1),
.C_PROBE1007_MU_CNT(1),
.C_PROBE1008_MU_CNT(1),
.C_PROBE1009_MU_CNT(1),
.C_PROBE1010_MU_CNT(1),
.C_PROBE1011_MU_CNT(1),
.C_PROBE1012_MU_CNT(1),
.C_PROBE1013_MU_CNT(1),
.C_PROBE1014_MU_CNT(1),
.C_PROBE1015_MU_CNT(1),
.C_PROBE1016_MU_CNT(1),
.C_PROBE1017_MU_CNT(1),
.C_PROBE1018_MU_CNT(1),
.C_PROBE1019_MU_CNT(1),
.C_PROBE1020_MU_CNT(1),
.C_PROBE1021_MU_CNT(1),
.C_PROBE1022_MU_CNT(1),
.C_PROBE1023_MU_CNT(1)
) inst (
.clk(clk),
.sl_iport0(sl_iport0),
.sl_oport0(sl_oport0),
.probe0(probe0),
.probe1(probe1),
.probe2(probe2),
.probe3(probe3),
.probe4(0),
.probe5(0),
.probe6(0),
.probe7(0),
.probe8(0),
.probe9(0),
.probe10(0),
.probe11(0),
.probe12(0),
.probe13(0),
.probe14(0),
.probe15(0),
.probe16(0),
.probe17(0),
.probe18(0),
.probe19(0),
.probe20(0),
.probe21(0),
.probe22(0),
.probe23(0),
.probe24(0),
.probe25(0),
.probe26(0),
.probe27(0),
.probe28(0),
.probe29(0),
.probe30(0),
.probe31(0),
.probe32(0),
.probe33(0),
.probe34(0),
.probe35(0),
.probe36(0),
.probe37(0),
.probe38(0),
.probe39(0),
.probe40(0),
.probe41(0),
.probe42(0),
.probe43(0),
.probe44(0),
.probe45(0),
.probe46(0),
.probe47(0),
.probe48(0),
.probe49(0),
.probe50(0),
.probe51(0),
.probe52(0),
.probe53(0),
.probe54(0),
.probe55(0),
.probe56(0),
.probe57(0),
.probe58(0),
.probe59(0),
.probe60(0),
.probe61(0),
.probe62(0),
.probe63(0),
.probe64(0),
.probe65(0),
.probe66(0),
.probe67(0),
.probe68(0),
.probe69(0),
.probe70(0),
.probe71(0),
.probe72(0),
.probe73(0),
.probe74(0),
.probe75(0),
.probe76(0),
.probe77(0),
.probe78(0),
.probe79(0),
.probe80(0),
.probe81(0),
.probe82(0),
.probe83(0),
.probe84(0),
.probe85(0),
.probe86(0),
.probe87(0),
.probe88(0),
.probe89(0),
.probe90(0),
.probe91(0),
.probe92(0),
.probe93(0),
.probe94(0),
.probe95(0),
.probe96(0),
.probe97(0),
.probe98(0),
.probe99(0),
.probe100(0),
.probe101(0),
.probe102(0),
.probe103(0),
.probe104(0),
.probe105(0),
.probe106(0),
.probe107(0),
.probe108(0),
.probe109(0),
.probe110(0),
.probe111(0),
.probe112(0),
.probe113(0),
.probe114(0),
.probe115(0),
.probe116(0),
.probe117(0),
.probe118(0),
.probe119(0),
.probe120(0),
.probe121(0),
.probe122(0),
.probe123(0),
.probe124(0),
.probe125(0),
.probe126(0),
.probe127(0),
.probe128(0),
.probe129(0),
.probe130(0),
.probe131(0),
.probe132(0),
.probe133(0),
.probe134(0),
.probe135(0),
.probe136(0),
.probe137(0),
.probe138(0),
.probe139(0),
.probe140(0),
.probe141(0),
.probe142(0),
.probe143(0),
.probe144(0),
.probe145(0),
.probe146(0),
.probe147(0),
.probe148(0),
.probe149(0),
.probe150(0),
.probe151(0),
.probe152(0),
.probe153(0),
.probe154(0),
.probe155(0),
.probe156(0),
.probe157(0),
.probe158(0),
.probe159(0),
.probe160(0),
.probe161(0),
.probe162(0),
.probe163(0),
.probe164(0),
.probe165(0),
.probe166(0),
.probe167(0),
.probe168(0),
.probe169(0),
.probe170(0),
.probe171(0),
.probe172(0),
.probe173(0),
.probe174(0),
.probe175(0),
.probe176(0),
.probe177(0),
.probe178(0),
.probe179(0),
.probe180(0),
.probe181(0),
.probe182(0),
.probe183(0),
.probe184(0),
.probe185(0),
.probe186(0),
.probe187(0),
.probe188(0),
.probe189(0),
.probe190(0),
.probe191(0),
.probe192(0),
.probe193(0),
.probe194(0),
.probe195(0),
.probe196(0),
.probe197(0),
.probe198(0),
.probe199(0),
.probe200(0),
.probe201(0),
.probe202(0),
.probe203(0),
.probe204(0),
.probe205(0),
.probe206(0),
.probe207(0),
.probe208(0),
.probe209(0),
.probe210(0),
.probe211(0),
.probe212(0),
.probe213(0),
.probe214(0),
.probe215(0),
.probe216(0),
.probe217(0),
.probe218(0),
.probe219(0),
.probe220(0),
.probe221(0),
.probe222(0),
.probe223(0),
.probe224(0),
.probe225(0),
.probe226(0),
.probe227(0),
.probe228(0),
.probe229(0),
.probe230(0),
.probe231(0),
.probe232(0),
.probe233(0),
.probe234(0),
.probe235(0),
.probe236(0),
.probe237(0),
.probe238(0),
.probe239(0),
.probe240(0),
.probe241(0),
.probe242(0),
.probe243(0),
.probe244(0),
.probe245(0),
.probe246(0),
.probe247(0),
.probe248(0),
.probe249(0),
.probe250(0),
.probe251(0),
.probe252(0),
.probe253(0),
.probe254(0),
.probe255(0),
.probe256(0),
.probe257(0),
.probe258(0),
.probe259(0),
.probe260(0),
.probe261(0),
.probe262(0),
.probe263(0),
.probe264(0),
.probe265(0),
.probe266(0),
.probe267(0),
.probe268(0),
.probe269(0),
.probe270(0),
.probe271(0),
.probe272(0),
.probe273(0),
.probe274(0),
.probe275(0),
.probe276(0),
.probe277(0),
.probe278(0),
.probe279(0),
.probe280(0),
.probe281(0),
.probe282(0),
.probe283(0),
.probe284(0),
.probe285(0),
.probe286(0),
.probe287(0),
.probe288(0),
.probe289(0),
.probe290(0),
.probe291(0),
.probe292(0),
.probe293(0),
.probe294(0),
.probe295(0),
.probe296(0),
.probe297(0),
.probe298(0),
.probe299(0),
.probe300(0),
.probe301(0),
.probe302(0),
.probe303(0),
.probe304(0),
.probe305(0),
.probe306(0),
.probe307(0),
.probe308(0),
.probe309(0),
.probe310(0),
.probe311(0),
.probe312(0),
.probe313(0),
.probe314(0),
.probe315(0),
.probe316(0),
.probe317(0),
.probe318(0),
.probe319(0),
.probe320(0),
.probe321(0),
.probe322(0),
.probe323(0),
.probe324(0),
.probe325(0),
.probe326(0),
.probe327(0),
.probe328(0),
.probe329(0),
.probe330(0),
.probe331(0),
.probe332(0),
.probe333(0),
.probe334(0),
.probe335(0),
.probe336(0),
.probe337(0),
.probe338(0),
.probe339(0),
.probe340(0),
.probe341(0),
.probe342(0),
.probe343(0),
.probe344(0),
.probe345(0),
.probe346(0),
.probe347(0),
.probe348(0),
.probe349(0),
.probe350(0),
.probe351(0),
.probe352(0),
.probe353(0),
.probe354(0),
.probe355(0),
.probe356(0),
.probe357(0),
.probe358(0),
.probe359(0),
.probe360(0),
.probe361(0),
.probe362(0),
.probe363(0),
.probe364(0),
.probe365(0),
.probe366(0),
.probe367(0),
.probe368(0),
.probe369(0),
.probe370(0),
.probe371(0),
.probe372(0),
.probe373(0),
.probe374(0),
.probe375(0),
.probe376(0),
.probe377(0),
.probe378(0),
.probe379(0),
.probe380(0),
.probe381(0),
.probe382(0),
.probe383(0),
.probe384(0),
.probe385(0),
.probe386(0),
.probe387(0),
.probe388(0),
.probe389(0),
.probe390(0),
.probe391(0),
.probe392(0),
.probe393(0),
.probe394(0),
.probe395(0),
.probe396(0),
.probe397(0),
.probe398(0),
.probe399(0),
.probe400(0),
.probe401(0),
.probe402(0),
.probe403(0),
.probe404(0),
.probe405(0),
.probe406(0),
.probe407(0),
.probe408(0),
.probe409(0),
.probe410(0),
.probe411(0),
.probe412(0),
.probe413(0),
.probe414(0),
.probe415(0),
.probe416(0),
.probe417(0),
.probe418(0),
.probe419(0),
.probe420(0),
.probe421(0),
.probe422(0),
.probe423(0),
.probe424(0),
.probe425(0),
.probe426(0),
.probe427(0),
.probe428(0),
.probe429(0),
.probe430(0),
.probe431(0),
.probe432(0),
.probe433(0),
.probe434(0),
.probe435(0),
.probe436(0),
.probe437(0),
.probe438(0),
.probe439(0),
.probe440(0),
.probe441(0),
.probe442(0),
.probe443(0),
.probe444(0),
.probe445(0),
.probe446(0),
.probe447(0),
.probe448(0),
.probe449(0),
.probe450(0),
.probe451(0),
.probe452(0),
.probe453(0),
.probe454(0),
.probe455(0),
.probe456(0),
.probe457(0),
.probe458(0),
.probe459(0),
.probe460(0),
.probe461(0),
.probe462(0),
.probe463(0),
.probe464(0),
.probe465(0),
.probe466(0),
.probe467(0),
.probe468(0),
.probe469(0),
.probe470(0),
.probe471(0),
.probe472(0),
.probe473(0),
.probe474(0),
.probe475(0),
.probe476(0),
.probe477(0),
.probe478(0),
.probe479(0),
.probe480(0),
.probe481(0),
.probe482(0),
.probe483(0),
.probe484(0),
.probe485(0),
.probe486(0),
.probe487(0),
.probe488(0),
.probe489(0),
.probe490(0),
.probe491(0),
.probe492(0),
.probe493(0),
.probe494(0),
.probe495(0),
.probe496(0),
.probe497(0),
.probe498(0),
.probe499(0),
.probe500(0),
.probe501(0),
.probe502(0),
.probe503(0),
.probe504(0),
.probe505(0),
.probe506(0),
.probe507(0),
.probe508(0),
.probe509(0),
.probe510(0),
.probe511(0),
.probe512(0),
.probe513(0),
.probe514(0),
.probe515(0),
.probe516(0),
.probe517(0),
.probe518(0),
.probe519(0),
.probe520(0),
.probe521(0),
.probe522(0),
.probe523(0),
.probe524(0),
.probe525(0),
.probe526(0),
.probe527(0),
.probe528(0),
.probe529(0),
.probe530(0),
.probe531(0),
.probe532(0),
.probe533(0),
.probe534(0),
.probe535(0),
.probe536(0),
.probe537(0),
.probe538(0),
.probe539(0),
.probe540(0),
.probe541(0),
.probe542(0),
.probe543(0),
.probe544(0),
.probe545(0),
.probe546(0),
.probe547(0),
.probe548(0),
.probe549(0),
.probe550(0),
.probe551(0),
.probe552(0),
.probe553(0),
.probe554(0),
.probe555(0),
.probe556(0),
.probe557(0),
.probe558(0),
.probe559(0),
.probe560(0),
.probe561(0),
.probe562(0),
.probe563(0),
.probe564(0),
.probe565(0),
.probe566(0),
.probe567(0),
.probe568(0),
.probe569(0),
.probe570(0),
.probe571(0),
.probe572(0),
.probe573(0),
.probe574(0),
.probe575(0),
.probe576(0),
.probe577(0),
.probe578(0),
.probe579(0),
.probe580(0),
.probe581(0),
.probe582(0),
.probe583(0),
.probe584(0),
.probe585(0),
.probe586(0),
.probe587(0),
.probe588(0),
.probe589(0),
.probe590(0),
.probe591(0),
.probe592(0),
.probe593(0),
.probe594(0),
.probe595(0),
.probe596(0),
.probe597(0),
.probe598(0),
.probe599(0),
.probe600(0),
.probe601(0),
.probe602(0),
.probe603(0),
.probe604(0),
.probe605(0),
.probe606(0),
.probe607(0),
.probe608(0),
.probe609(0),
.probe610(0),
.probe611(0),
.probe612(0),
.probe613(0),
.probe614(0),
.probe615(0),
.probe616(0),
.probe617(0),
.probe618(0),
.probe619(0),
.probe620(0),
.probe621(0),
.probe622(0),
.probe623(0),
.probe624(0),
.probe625(0),
.probe626(0),
.probe627(0),
.probe628(0),
.probe629(0),
.probe630(0),
.probe631(0),
.probe632(0),
.probe633(0),
.probe634(0),
.probe635(0),
.probe636(0),
.probe637(0),
.probe638(0),
.probe639(0),
.probe640(0),
.probe641(0),
.probe642(0),
.probe643(0),
.probe644(0),
.probe645(0),
.probe646(0),
.probe647(0),
.probe648(0),
.probe649(0),
.probe650(0),
.probe651(0),
.probe652(0),
.probe653(0),
.probe654(0),
.probe655(0),
.probe656(0),
.probe657(0),
.probe658(0),
.probe659(0),
.probe660(0),
.probe661(0),
.probe662(0),
.probe663(0),
.probe664(0),
.probe665(0),
.probe666(0),
.probe667(0),
.probe668(0),
.probe669(0),
.probe670(0),
.probe671(0),
.probe672(0),
.probe673(0),
.probe674(0),
.probe675(0),
.probe676(0),
.probe677(0),
.probe678(0),
.probe679(0),
.probe680(0),
.probe681(0),
.probe682(0),
.probe683(0),
.probe684(0),
.probe685(0),
.probe686(0),
.probe687(0),
.probe688(0),
.probe689(0),
.probe690(0),
.probe691(0),
.probe692(0),
.probe693(0),
.probe694(0),
.probe695(0),
.probe696(0),
.probe697(0),
.probe698(0),
.probe699(0),
.probe700(0),
.probe701(0),
.probe702(0),
.probe703(0),
.probe704(0),
.probe705(0),
.probe706(0),
.probe707(0),
.probe708(0),
.probe709(0),
.probe710(0),
.probe711(0),
.probe712(0),
.probe713(0),
.probe714(0),
.probe715(0),
.probe716(0),
.probe717(0),
.probe718(0),
.probe719(0),
.probe720(0),
.probe721(0),
.probe722(0),
.probe723(0),
.probe724(0),
.probe725(0),
.probe726(0),
.probe727(0),
.probe728(0),
.probe729(0),
.probe730(0),
.probe731(0),
.probe732(0),
.probe733(0),
.probe734(0),
.probe735(0),
.probe736(0),
.probe737(0),
.probe738(0),
.probe739(0),
.probe740(0),
.probe741(0),
.probe742(0),
.probe743(0),
.probe744(0),
.probe745(0),
.probe746(0),
.probe747(0),
.probe748(0),
.probe749(0),
.probe750(0),
.probe751(0),
.probe752(0),
.probe753(0),
.probe754(0),
.probe755(0),
.probe756(0),
.probe757(0),
.probe758(0),
.probe759(0),
.probe760(0),
.probe761(0),
.probe762(0),
.probe763(0),
.probe764(0),
.probe765(0),
.probe766(0),
.probe767(0),
.probe768(0),
.probe769(0),
.probe770(0),
.probe771(0),
.probe772(0),
.probe773(0),
.probe774(0),
.probe775(0),
.probe776(0),
.probe777(0),
.probe778(0),
.probe779(0),
.probe780(0),
.probe781(0),
.probe782(0),
.probe783(0),
.probe784(0),
.probe785(0),
.probe786(0),
.probe787(0),
.probe788(0),
.probe789(0),
.probe790(0),
.probe791(0),
.probe792(0),
.probe793(0),
.probe794(0),
.probe795(0),
.probe796(0),
.probe797(0),
.probe798(0),
.probe799(0),
.probe800(0),
.probe801(0),
.probe802(0),
.probe803(0),
.probe804(0),
.probe805(0),
.probe806(0),
.probe807(0),
.probe808(0),
.probe809(0),
.probe810(0),
.probe811(0),
.probe812(0),
.probe813(0),
.probe814(0),
.probe815(0),
.probe816(0),
.probe817(0),
.probe818(0),
.probe819(0),
.probe820(0),
.probe821(0),
.probe822(0),
.probe823(0),
.probe824(0),
.probe825(0),
.probe826(0),
.probe827(0),
.probe828(0),
.probe829(0),
.probe830(0),
.probe831(0),
.probe832(0),
.probe833(0),
.probe834(0),
.probe835(0),
.probe836(0),
.probe837(0),
.probe838(0),
.probe839(0),
.probe840(0),
.probe841(0),
.probe842(0),
.probe843(0),
.probe844(0),
.probe845(0),
.probe846(0),
.probe847(0),
.probe848(0),
.probe849(0),
.probe850(0),
.probe851(0),
.probe852(0),
.probe853(0),
.probe854(0),
.probe855(0),
.probe856(0),
.probe857(0),
.probe858(0),
.probe859(0),
.probe860(0),
.probe861(0),
.probe862(0),
.probe863(0),
.probe864(0),
.probe865(0),
.probe866(0),
.probe867(0),
.probe868(0),
.probe869(0),
.probe870(0),
.probe871(0),
.probe872(0),
.probe873(0),
.probe874(0),
.probe875(0),
.probe876(0),
.probe877(0),
.probe878(0),
.probe879(0),
.probe880(0),
.probe881(0),
.probe882(0),
.probe883(0),
.probe884(0),
.probe885(0),
.probe886(0),
.probe887(0),
.probe888(0),
.probe889(0),
.probe890(0),
.probe891(0),
.probe892(0),
.probe893(0),
.probe894(0),
.probe895(0),
.probe896(0),
.probe897(0),
.probe898(0),
.probe899(0),
.probe900(0),
.probe901(0),
.probe902(0),
.probe903(0),
.probe904(0),
.probe905(0),
.probe906(0),
.probe907(0),
.probe908(0),
.probe909(0),
.probe910(0),
.probe911(0),
.probe912(0),
.probe913(0),
.probe914(0),
.probe915(0),
.probe916(0),
.probe917(0),
.probe918(0),
.probe919(0),
.probe920(0),
.probe921(0),
.probe922(0),
.probe923(0),
.probe924(0),
.probe925(0),
.probe926(0),
.probe927(0),
.probe928(0),
.probe929(0),
.probe930(0),
.probe931(0),
.probe932(0),
.probe933(0),
.probe934(0),
.probe935(0),
.probe936(0),
.probe937(0),
.probe938(0),
.probe939(0),
.probe940(0),
.probe941(0),
.probe942(0),
.probe943(0),
.probe944(0),
.probe945(0),
.probe946(0),
.probe947(0),
.probe948(0),
.probe949(0),
.probe950(0),
.probe951(0),
.probe952(0),
.probe953(0),
.probe954(0),
.probe955(0),
.probe956(0),
.probe957(0),
.probe958(0),
.probe959(0),
.probe960(0),
.probe961(0),
.probe962(0),
.probe963(0),
.probe964(0),
.probe965(0),
.probe966(0),
.probe967(0),
.probe968(0),
.probe969(0),
.probe970(0),
.probe971(0),
.probe972(0),
.probe973(0),
.probe974(0),
.probe975(0),
.probe976(0),
.probe977(0),
.probe978(0),
.probe979(0),
.probe980(0),
.probe981(0),
.probe982(0),
.probe983(0),
.probe984(0),
.probe985(0),
.probe986(0),
.probe987(0),
.probe988(0),
.probe989(0),
.probe990(0),
.probe991(0),
.probe992(0),
.probe993(0),
.probe994(0),
.probe995(0),
.probe996(0),
.probe997(0),
.probe998(0),
.probe999(0),
.probe1000(0),
.probe1001(0),
.probe1002(0),
.probe1003(0),
.probe1004(0),
.probe1005(0),
.probe1006(0),
.probe1007(0),
.probe1008(0),
.probe1009(0),
.probe1010(0),
.probe1011(0),
.probe1012(0),
.probe1013(0),
.probe1014(0),
.probe1015(0),
.probe1016(0),
.probe1017(0),
.probe1018(0),
.probe1019(0),
.probe1020(0),
.probe1021(0),
.probe1022(0),
.probe1023(0)
)/* synthesis syn_noprune=1 */;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SHA-160 ////
//// Secure Hash Algorithm (SHA-160) ////
//// ////
//// Author: marsgod ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/sha_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002-2004 marsgod ////
//// [email protected] ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`define SHA1_H0 32'h67452301
`define SHA1_H1 32'hefcdab89
`define SHA1_H2 32'h98badcfe
`define SHA1_H3 32'h10325476
`define SHA1_H4 32'hc3d2e1f0
`define SHA1_K0 32'h5a827999
`define SHA1_K1 32'h6ed9eba1
`define SHA1_K2 32'h8f1bbcdc
`define SHA1_K3 32'hca62c1d6
module sha1 (clk_i, reset, text_i, text_o, cmd_i, cmd_w_i, cmd_o);
input clk_i; // global clock input
input reset; // global reset input , active high
input [31:0] text_i; // text input 32bit
output [31:0] text_o; // text output 32bit
input [2:0] cmd_i; // command input
input cmd_w_i;// command input write enable
output [3:0] cmd_o; // command output(status)
/*
cmd
Busy Round W R
bit3 bit2 bit1 bit0
Busy Round W R
Busy:
0 idle
1 busy
Round:
0 first round
1 internal round
W:
0 No-op
1 write data
R:
0 No-op
1 read data
*/
reg [3:0] cmd;
wire [3:0] cmd_o;
reg [31:0] text_o;
reg [6:0] round;
wire [6:0] round_plus_1;
reg [2:0] read_counter;
reg [31:0] H0,H1,H2,H3,H4;
reg [31:0] W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14;
reg [31:0] Wt,Kt;
reg [31:0] A,B,C,D,E;
reg busy;
assign cmd_o = cmd;
always @ (posedge clk_i)
begin
if (reset)
cmd <= 4'b0000;
else
if (cmd_w_i)
cmd[2:0] <= cmd_i[2:0]; // busy bit can't write
else
begin
cmd[3] <= busy; // update busy bit
if (~busy)
cmd[1:0] <= 2'b00; // hardware auto clean R/W bits
end
end
// Hash functions
wire [31:0] SHA1_f1_BCD,SHA1_f2_BCD,SHA1_f3_BCD,SHA1_Wt_1;
wire [31:0] SHA1_ft_BCD;
wire [31:0] next_Wt,next_A,next_C;
wire [159:0] SHA1_result;
assign SHA1_f1_BCD = (B & C) ^ (~B & D);
assign SHA1_f2_BCD = B ^ C ^ D;
assign SHA1_f3_BCD = (B & C) ^ (C & D) ^ (B & D);
assign SHA1_ft_BCD = (round < 7'b0100101) ? SHA1_f1_BCD : (round < 7'b101001) ? SHA1_f2_BCD : (round < 7'b1111101) ? SHA1_f3_BCD : SHA1_f2_BCD;
// Odin II doesn't support binary operations inside concatenations presently.
//assign SHA1_Wt_1 = {W13 ^ W8 ^ W2 ^ W0};
assign SHA1_Wt_1 = W13 ^ W8 ^ W2 ^ W0;
assign next_Wt = {SHA1_Wt_1[30:0],SHA1_Wt_1[31]}; // NSA fix added
assign next_A = {A[26:0],A[31:27]} + SHA1_ft_BCD + E + Kt + Wt;
assign next_C = {B[1:0],B[31:2]};
assign SHA1_result = {A,B,C,D,E};
assign round_plus_1 = round + 1;
//------------------------------------------------------------------
// SHA round
//------------------------------------------------------------------
always @(posedge clk_i)
begin
if (reset)
begin
round <= 7'b0000000;
busy <= 1'b0;
W0 <= 32'b00000000000000000000000000000000;
W1 <= 32'b00000000000000000000000000000000;
W2 <= 32'b00000000000000000000000000000000;
W3 <= 32'b00000000000000000000000000000000;
W4 <= 32'b00000000000000000000000000000000;
W5 <= 32'b00000000000000000000000000000000;
W6 <= 32'b00000000000000000000000000000000;
W7 <= 32'b00000000000000000000000000000000;
W8 <= 32'b00000000000000000000000000000000;
W9 <= 32'b00000000000000000000000000000000;
W10 <= 32'b00000000000000000000000000000000;
W11 <= 32'b00000000000000000000000000000000;
W12 <= 32'b00000000000000000000000000000000;
W13 <= 32'b00000000000000000000000000000000;
W14 <= 32'b00000000000000000000000000000000;
Wt <= 32'b00000000000000000000000000000000;
A <= 32'b00000000000000000000000000000000;
B <= 32'b00000000000000000000000000000000;
C <= 32'b00000000000000000000000000000000;
D <= 32'b00000000000000000000000000000000;
E <= 32'b00000000000000000000000000000000;
H0 <= 32'b00000000000000000000000000000000;
H1 <= 32'b00000000000000000000000000000000;
H2 <= 32'b00000000000000000000000000000000;
H3 <= 32'b00000000000000000000000000000000;
H4 <= 32'b00000000000000000000000000000000;
end
else
begin
case (round)
7'b0000000:
begin
if (cmd[1])
begin
W0 <= text_i;
Wt <= text_i;
busy <= 1'b1;
round <= round_plus_1;
case (cmd[2])
1'b0: // sha-1 first message
begin
A <= `SHA1_H0;
B <= `SHA1_H1;
C <= `SHA1_H2;
D <= `SHA1_H3;
E <= `SHA1_H4;
H0 <= `SHA1_H0;
H1 <= `SHA1_H1;
H2 <= `SHA1_H2;
H3 <= `SHA1_H3;
H4 <= `SHA1_H4;
end
1'b1: // sha-1 internal message
begin
H0 <= A;
H1 <= B;
H2 <= C;
H3 <= D;
H4 <= E;
end
endcase
end
else
begin // IDLE
round <= 7'b0000000;
end
end
7'b0000001:
begin
W1 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000010:
begin
W2 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000011:
begin
W3 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000100:
begin
W4 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000101:
begin
W5 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000110:
begin
W6 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000111:
begin
W7 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001000:
begin
W8 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001001:
begin
W9 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001010:
begin
W10 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001011:
begin
W11 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001100:
begin
W12 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001101:
begin
W13 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001110:
begin
W14 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001111:
begin
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001111:
begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1010000:
begin
A <= next_A + H0;
B <= A + H1;
C <= next_C + H2;
D <= C + H3;
E <= D + H4;
round <= 7'b0000000;
busy <= 1'b0;
end
default:
begin
round <= 7'b0000000;
busy <= 1'b0;
end
endcase
end
end
//------------------------------------------------------------------
// Kt generator
//------------------------------------------------------------------
always @ (posedge clk_i)
begin
if (reset)
begin
Kt <= 32'b00000000000000000000000000000000;
end
else
begin
if (round < 7'b0100000)
Kt <= `SHA1_K0;
else
if (round < 7'b1010000)
Kt <= `SHA1_K1;
else
if (round < 7'b1111100)
Kt <= `SHA1_K2;
else
Kt <= `SHA1_K3;
end
end
//------------------------------------------------------------------
// read result
//------------------------------------------------------------------
always @ (posedge clk_i)
begin
if (reset)
begin
text_o <= 32'b00000000000000000000000000000000;
read_counter <= 3'b000;
end
else
begin
if (cmd[0])
begin
read_counter <= 3'b100; // sha-1 160/32=5
end
else
begin
if (~busy)
begin
case (read_counter)
3'b100: text_o <= SHA1_result[5*32-1:4*32];
3'b011: text_o <= SHA1_result[4*32-1:3*32];
3'b010: text_o <= SHA1_result[3*32-1:2*32];
3'b001: text_o <= SHA1_result[2*32-1:1*32];
3'b000: text_o <= SHA1_result[1*32-1:0*32];
default:text_o <= 3'b000;
endcase
if (|read_counter)
read_counter <= read_counter - 7'b0000001;
end
else
begin
text_o <= 32'b00000000000000000000000000000000;
end
end
end
end
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================
// FILE DETAILS
// Project : sonet framer
// File : sync1s.v
// Title :
// Dependencies :
// Description : Synchronizer :Transfers signal from faster clock
// domain to slower clock domain.
// =============================================================================
// REVISION HISTORY
// Version : 1.0
// Author(s) :
// Mod. Date : Dec 14, 2004
// Changes Made : Initial Creation
// =============================================================================
`timescale 1 ns / 1 ps
module sync1s (
f_clk ,
s_clk ,
rst_n ,
in_fclk,
out_sclk
);
parameter WIDTH = 1 ;
input f_clk ; // Fast clock.
input s_clk ; // Slow clock.
input rst_n ; // reset signal.
input [WIDTH-1:0] in_fclk ; // Input pulse in fast clock domain.
output [WIDTH-1:0] out_sclk ; // Output pulse in slow clock domain.
reg [WIDTH-1:0] f_reg1 ;
reg [WIDTH-1:0] f_reg2 ;
reg [WIDTH-1:0] f_reg3 ;
reg [WIDTH-1:0] s_reg1 ;
reg [WIDTH-1:0] s_reg2 ;
wire [WIDTH-1:0] hold_fb ;
wire [WIDTH-1:0] out_sclk ;
integer i ;
// register fast clock signal edge and hold it untill
// it is transfered into slower clock domain.
always @(posedge f_clk or negedge rst_n) begin
if (!rst_n)
f_reg1 <= {WIDTH{1'b0}};
else
for (i = 0; i <= WIDTH-1; i = i+1) begin
f_reg1[i] <= (hold_fb[i]=== 1'b1) ? f_reg1[i] : in_fclk[i];
end
end
// first register in slower clock domain, this can be
// a metastable flop.
always @(posedge s_clk or negedge rst_n) begin
if (!rst_n)
s_reg1 <= {WIDTH{1'b0}};
else
s_reg1 <= f_reg1;
end
// Cleaner registering in slower clock domain.
always @(posedge s_clk or negedge rst_n) begin
if (!rst_n)
s_reg2 <= {WIDTH{1'b0}};
else
s_reg2 <= s_reg1;
end
// Output signal.
assign out_sclk = s_reg2 ;
// Register clean output in slower clock domain into
// fast clock domains, this can be metastable flop.
always @(posedge f_clk or negedge rst_n) begin
if (!rst_n)
f_reg2 <= {WIDTH{1'b0}};
else
f_reg2 <= s_reg2;
end
// Cleaner registering in faster clock domain.
always @(posedge f_clk or negedge rst_n) begin
if (!rst_n)
f_reg3 <= {WIDTH{1'b0}};
else
f_reg3 <= f_reg2;
end
// generate feed back hold signal for holding
// input signal in fast clock domain, until it reaches
// slower clock domain.
assign hold_fb = f_reg1 ^ f_reg3;
endmodule
|
// altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_tbp
#( parameter
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
CFG_ENABLE_SHADOW_TBP = 0,
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary encoded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_DATA_ID_WIDTH = 10,
CFG_REG_REQ = 0,
CFG_REG_GRANT = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_DISABLE_READ_REODERING = 0,
CFG_DISABLE_PRIORITY = 0,
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_TYPE = 3,
T_PARAM_ACT_TO_RDWR_WIDTH = 4,
T_PARAM_ACT_TO_ACT_WIDTH = 4,
T_PARAM_ACT_TO_PCH_WIDTH = 4,
T_PARAM_RD_TO_PCH_WIDTH = 4,
T_PARAM_WR_TO_PCH_WIDTH = 4,
T_PARAM_PCH_TO_VALID_WIDTH = 4,
T_PARAM_RD_AP_TO_VALID_WIDTH = 4,
T_PARAM_WR_AP_TO_VALID_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
// Cmd gen interface
tbp_full,
tbp_empty,
cmd_gen_load,
cmd_gen_waiting_to_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// Arbiter interface
row_req,
act_req,
pch_req,
row_grant,
act_grant,
pch_grant,
col_req,
rd_req,
wr_req,
col_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_read,
tbp_write,
tbp_precharge,
tbp_activate,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_age,
tbp_priority,
tbp_rmw_correct,
tbp_rmw_partial,
sb_tbp_precharge_all,
sb_do_precharge_all,
// Timer value
t_param_act_to_rdwr,
t_param_act_to_act,
t_param_act_to_pch,
t_param_rd_to_pch,
t_param_wr_to_pch,
t_param_pch_to_valid,
t_param_rd_ap_to_valid,
t_param_wr_ap_to_valid,
// Misc interface
tbp_bank_closed,
tbp_timer_ready,
tbp_load,
data_complete,
data_rmw_complete,
data_rmw_fetch,
// Config interface
cfg_reorder_data,
cfg_starve_limit,
cfg_type,
cfg_enable_ecc,
cfg_enable_no_dm
);
localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2**CFG_MEM_IF_BA_WIDTH;
localparam TBP_COUNTER_OFFSET = (CFG_REG_GRANT) ? 2 : 1;
localparam RDWR_AP_TO_VALID_WIDTH = (T_PARAM_RD_AP_TO_VALID_WIDTH > T_PARAM_WR_AP_TO_VALID_WIDTH) ? T_PARAM_RD_AP_TO_VALID_WIDTH : T_PARAM_WR_AP_TO_VALID_WIDTH;
localparam COL_TIMER_WIDTH = T_PARAM_ACT_TO_RDWR_WIDTH;
localparam ROW_TIMER_WIDTH = (T_PARAM_ACT_TO_ACT_WIDTH > RDWR_AP_TO_VALID_WIDTH) ? T_PARAM_ACT_TO_ACT_WIDTH : RDWR_AP_TO_VALID_WIDTH;
localparam TRC_TIMER_WIDTH = T_PARAM_ACT_TO_ACT_WIDTH;
localparam COMBINED_TIMER_WIDTH = (ROW_TIMER_WIDTH > TRC_TIMER_WIDTH) ? ROW_TIMER_WIDTH : TRC_TIMER_WIDTH;
// Start of port declaration
input ctl_clk;
input ctl_reset_n;
output tbp_full;
output tbp_empty;
input cmd_gen_load;
input cmd_gen_waiting_to_load;
input [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
input cmd_gen_write;
input cmd_gen_read;
input [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
input [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
input cmd_gen_priority;
input cmd_gen_rmw_correct;
input cmd_gen_rmw_partial;
input cmd_gen_autopch;
input cmd_gen_complete;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output [CFG_CTL_TBP_NUM-1:0] row_req;
output [CFG_CTL_TBP_NUM-1:0] act_req;
output [CFG_CTL_TBP_NUM-1:0] pch_req;
input [CFG_CTL_TBP_NUM-1:0] row_grant;
input [CFG_CTL_TBP_NUM-1:0] act_grant;
input [CFG_CTL_TBP_NUM-1:0] pch_grant;
output [CFG_CTL_TBP_NUM-1:0] col_req;
output [CFG_CTL_TBP_NUM-1:0] rd_req;
output [CFG_CTL_TBP_NUM-1:0] wr_req;
input [CFG_CTL_TBP_NUM-1:0] col_grant;
input [CFG_CTL_TBP_NUM-1:0] rd_grant;
input [CFG_CTL_TBP_NUM-1:0] wr_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_row_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_col_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_act_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_pch_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_rd_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_wr_grant;
input or_row_grant;
input or_col_grant;
output [CFG_CTL_TBP_NUM-1:0] tbp_read;
output [CFG_CTL_TBP_NUM-1:0] tbp_write;
output [CFG_CTL_TBP_NUM-1:0] tbp_precharge;
output [CFG_CTL_TBP_NUM-1:0] tbp_activate;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
output [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
output [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_ap;
output [CFG_CTL_TBP_NUM-1:0] tbp_burst_chop;
output [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
output [CFG_CTL_TBP_NUM-1:0] tbp_priority;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
input [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
input [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] t_param_act_to_rdwr;
input [T_PARAM_ACT_TO_ACT_WIDTH-1:0] t_param_act_to_act;
input [T_PARAM_ACT_TO_PCH_WIDTH-1:0] t_param_act_to_pch;
input [T_PARAM_RD_TO_PCH_WIDTH-1:0] t_param_rd_to_pch;
input [T_PARAM_WR_TO_PCH_WIDTH-1:0] t_param_wr_to_pch;
input [T_PARAM_PCH_TO_VALID_WIDTH-1:0] t_param_pch_to_valid;
input [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] t_param_rd_ap_to_valid;
input [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] t_param_wr_ap_to_valid;
output [CFG_MEM_IF_CHIP-1:0] tbp_bank_closed;
output [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
output [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input data_rmw_complete;
output data_rmw_fetch;
input [CFG_PORT_WIDTH_REORDER_DATA-1:0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] cfg_starve_limit;
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
input cfg_enable_ecc;
input cfg_enable_no_dm;
// End of port declaration
// Logic operators
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load;
wire [CFG_CTL_TBP_NUM-1:0] load_tbp;
reg [CFG_CTL_TBP_NUM-1:0] load_tbp_index;
wire [CFG_CTL_TBP_NUM-1:0] flush_tbp;
reg [CFG_CTL_TBP_NUM-1:0] precharge_tbp;
reg [CFG_CTL_TBP_NUM-1:0] row_req;
reg [CFG_CTL_TBP_NUM-1:0] act_req;
reg [CFG_CTL_TBP_NUM-1:0] pch_req;
reg [CFG_CTL_TBP_NUM-1:0] col_req;
reg [CFG_CTL_TBP_NUM-1:0] rd_req;
reg [CFG_CTL_TBP_NUM-1:0] wr_req;
wire cfg_enable_rmw;
reg int_tbp_full;
wire int_tbp_empty;
reg [CFG_CTL_TBP_NUM-1:0] valid;
wire [CFG_CTL_TBP_NUM-1:0] valid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] write;
reg [CFG_CTL_TBP_NUM-1:0] read;
wire [CFG_CTL_TBP_NUM-1:0] precharge;
wire [CFG_CTL_TBP_NUM-1:0] activate;
reg [CFG_INT_SIZE_WIDTH-1:0] size [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] autopch;
reg [CFG_LOCAL_ID_WIDTH-1:0] localid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] priority_a;
reg [CFG_CTL_TBP_NUM-1:0] activated;
reg [CFG_CTL_TBP_NUM-1:0] activated_p;
reg [CFG_CTL_TBP_NUM-1:0] activated_combi;
reg [CFG_CTL_TBP_NUM-1:0] precharged;
reg [CFG_CTL_TBP_NUM-1:0] precharged_combi;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_r;
reg [CFG_CTL_TBP_NUM-1:0] open_row_passed;
wire [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush_r [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] done;
reg [CFG_CTL_TBP_NUM-1:0] done_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete;
reg [CFG_CTL_TBP_NUM-1:0] complete_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_wr;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_wr;
reg [CFG_CTL_TBP_NUM-1:0] wst;
reg [CFG_CTL_TBP_NUM-1:0] wst_p;
reg [CFG_CTL_TBP_NUM-1:0] ssb;
reg [CFG_CTL_TBP_NUM-1:0] ssbr;
reg [CFG_CTL_TBP_NUM-1:0] ap;
reg [CFG_CTL_TBP_NUM-1:0] real_ap;
reg [CFG_CTL_TBP_NUM-1:0] rmw_correct;
reg [CFG_CTL_TBP_NUM-1:0] rmw_partial;
reg [CFG_CTL_TBP_NUM-1:0] rmw;
reg [CFG_CTL_TBP_NUM-1:0] require_flush;
reg [CFG_CTL_TBP_NUM-1:0] require_flush_calc;
reg [CFG_CTL_TBP_NUM-1:0] require_pch_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] require_pch;
reg [CFG_CTL_TBP_NUM-1:0] burst_chop;
reg [CFG_CTL_TBP_NUM-1:0] age [CFG_CTL_TBP_NUM-1:0];
reg [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] starvation [CFG_CTL_TBP_NUM-1:0];
// bit vectors
reg [CFG_CTL_TBP_NUM-1:0] apvo_combi; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvo; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvc_combi; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] apvc; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] or_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_rpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_cpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbv;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbvt;
wire [CFG_CTL_TBP_NUM-1:0] tbp_read;
wire [CFG_CTL_TBP_NUM-1:0] tbp_write;
wire [CFG_CTL_TBP_NUM-1:0] tbp_ap;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
wire [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
wire [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
wire [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
wire [CFG_CTL_TBP_NUM-1:0] tbp_priority;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP-1:0] tbp_bank_closed;
wire [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
reg [CFG_MEM_IF_CHIP-1:0] bank_closed;
reg [CFG_MEM_IF_CHIP-1:0] timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] int_bank_closed [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] int_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_shadow_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] same_command_read;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_diff_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_command_read;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_diff_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank;
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_diff_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] pre_calculated_same_shadow_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [COL_TIMER_WIDTH-1:0] col_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] col_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] col_timer_pre_ready;
reg [COMBINED_TIMER_WIDTH-1:0] combined_timer [CFG_CTL_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] row_timer_combi [CFG_CTL_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] row_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] row_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] row_timer_pre_ready;
reg [TRC_TIMER_WIDTH-1:0] trc_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready_combi;
reg [CFG_CTL_TBP_NUM-1:0] pch_ready;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_to_pch_greater_than_row_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_to_pch_greater_than_row_timer;
reg compare_t_param_act_to_rdwr_less_than_offset;
reg compare_t_param_act_to_act_less_than_offset;
reg compare_t_param_act_to_pch_less_than_offset;
reg compare_t_param_rd_to_pch_less_than_offset;
reg compare_t_param_wr_to_pch_less_than_offset;
reg compare_t_param_pch_to_valid_less_than_offset;
reg compare_t_param_rd_ap_to_valid_less_than_offset;
reg compare_t_param_wr_ap_to_valid_less_than_offset;
reg compare_offset_t_param_act_to_rdwr_less_than_0;
reg compare_offset_t_param_act_to_rdwr_less_than_1;
reg [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] offset_t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_ACT_WIDTH-1:0] offset_t_param_act_to_act;
reg [T_PARAM_ACT_TO_PCH_WIDTH-1:0] offset_t_param_act_to_pch;
reg [T_PARAM_RD_TO_PCH_WIDTH-1:0] offset_t_param_rd_to_pch;
reg [T_PARAM_WR_TO_PCH_WIDTH-1:0] offset_t_param_wr_to_pch;
reg [T_PARAM_PCH_TO_VALID_WIDTH-1:0] offset_t_param_pch_to_valid;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] offset_t_param_rd_ap_to_valid;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] offset_t_param_wr_ap_to_valid;
reg [CFG_CTL_TBP_NUM-1:0] can_act;
reg [CFG_CTL_TBP_NUM-1:0] can_pch;
reg [CFG_CTL_TBP_NUM-1:0] can_rd;
reg [CFG_CTL_TBP_NUM-1:0] can_wr;
reg [CFG_CTL_TBP_NUM-1:0] finish_tbp;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] flush_shadow_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] shadow_row_timer [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_pre_ready;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_ready;
wire one = 1'b1;
wire zero = 1'b0;
integer i;
integer j;
genvar k;
//----------------------------------------------------------------------------------------------------
// Output port assignments
//----------------------------------------------------------------------------------------------------
assign tbp_read = read;
assign tbp_write = write;
assign tbp_ap = real_ap;
assign tbp_burst_chop = burst_chop;
assign tbp_precharge = precharge;
assign tbp_activate = activate;
assign tbp_priority = priority_a;
assign tbp_rmw_correct = rmw_correct;
assign tbp_rmw_partial = rmw_partial;
generate
begin
for(k=0; k<CFG_CTL_TBP_NUM; k=k+1)
begin : tbp_name
assign tbp_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = chipsel[k];
assign tbp_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = bank [k];
assign tbp_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = row [k];
assign tbp_col [(k*CFG_MEM_IF_COL_WIDTH)+CFG_MEM_IF_COL_WIDTH-1:k*CFG_MEM_IF_COL_WIDTH] = col [k];
assign tbp_localid[(k*CFG_LOCAL_ID_WIDTH)+CFG_LOCAL_ID_WIDTH-1:k*CFG_LOCAL_ID_WIDTH] = localid[k];
assign tbp_dataid [(k*CFG_DATA_ID_WIDTH)+CFG_DATA_ID_WIDTH-1:k*CFG_DATA_ID_WIDTH] = dataid [k];
assign tbp_age [(k*CFG_CTL_TBP_NUM)+CFG_CTL_TBP_NUM-1:k*CFG_CTL_TBP_NUM] = age [k];
assign tbp_size [(k*CFG_INT_SIZE_WIDTH)+CFG_INT_SIZE_WIDTH-1:k*CFG_INT_SIZE_WIDTH] = size [k];
end
for(k=0; k<CFG_CTL_SHADOW_TBP_NUM; k=k+1)
begin : tbp_shadow_name
if (CFG_ENABLE_SHADOW_TBP)
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = shadow_chipsel[k];
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = shadow_bank [k];
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = shadow_row [k];
end
else
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = 0;
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = 0;
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = 0;
end
end
end
endgenerate
assign tbp_full = int_tbp_full;
assign tbp_empty = int_tbp_empty;
assign int_tbp_empty = &(valid ^~ done); // empty if valid and done are the same
assign load_tbp = (~int_tbp_full & cmd_gen_load) ? load_tbp_index : 0;
assign flush_tbp = open_row_pass_flush_r | finish_tbp | (done & precharge_tbp);
assign tbp_load = load_tbp;
assign tbp_bank_closed = bank_closed;
assign tbp_timer_ready = timer_ready;
assign precharge = activated;
assign activate = ~activated;
//----------------------------------------------------------------------------------------------------
// TBP General Functions
//----------------------------------------------------------------------------------------------------
assign cfg_enable_rmw = cfg_enable_ecc | cfg_enable_no_dm;
assign valid_combi = (valid | load_tbp) & ~flush_tbp;
// Decide which TBP to load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
load_tbp_index <= 0;
end
else
begin
load_tbp_index <= ~valid_combi & (valid_combi + 1);
end
end
// Assert when TBP is full to prevent further load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tbp_full <= 0;
end
else
begin
int_tbp_full <= &valid_combi;
end
end
//----------------------------------------------------------------------------------------------------
// Finish TBP
//----------------------------------------------------------------------------------------------------
// Logic to determine when can we flush a done TBP
// in non-shadow TBP case, we can only flush once the timer finished counting
// in shadow TBP case, we can flush once it is pushed into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
finish_tbp[i] = push_tbp[i] | (done[i] & precharged[i] & row_timer_pre_ready[i] & trc_timer_pre_ready[i]);
end
else
begin
finish_tbp[i] = done[i] & precharged[i] & row_timer_pre_ready[i] & trc_timer_pre_ready[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Shadow TBP Logic
//----------------------------------------------------------------------------------------------------
// Determine when can we flush TBP
assign flush_shadow_tbp = shadow_valid & shadow_row_timer_pre_ready;
// Determine when it's ready to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_tbp[i]) // TBP might flush before shadow TBP is still allocated
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if ((col_grant[i] && real_ap[i]) || (pch_grant[i] && done[i])) // indicate ready to push TBP once TBP is done
begin
ready_to_push_tbp_combi[i] = 1'b1;
end
else
begin
ready_to_push_tbp_combi[i] = ready_to_push_tbp[i];
end
end
else
begin
ready_to_push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= ready_to_push_tbp_combi[i];
end
end
end
// Determine when to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
push_tbp_combi[i] = 1'b0;
end
else if (ready_to_push_tbp_combi[i] && shadow_row_timer_pre_ready[i]) // prevent pushing into an allocated shadow TBP
begin
push_tbp_combi[i] = 1'b1;
end
else
begin
push_tbp_combi[i] = push_tbp[i];
end
end
else
begin
push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= push_tbp_combi[i];
end
end
end
// Shadow TBP information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp_combi[i])
begin
shadow_chipsel[i] <= chipsel[i];
shadow_bank [i] <= bank [i];
shadow_row [i] <= row [i];
end
end
else
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_shadow_tbp[i])
begin
shadow_valid[i] <= 1'b0;
end
else if (push_tbp[i])
begin
shadow_valid[i] <= 1'b1;
end
end
else
begin
shadow_valid[i] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i])
begin
if (!row_timer_pre_ready[i] || !trc_timer_pre_ready[i])
begin
// Decide to take the larger timer value between row/trc timer
if (row_timer[i] > trc_timer[i])
begin
shadow_row_timer[i] <= row_timer[i] - 1'b1;
end
else
begin
shadow_row_timer[i] <= trc_timer[i] - 1'b1;
end
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b1;
shadow_row_timer_ready [i] <= 1'b1;
end
end
else
begin
if (shadow_row_timer[i] != 0)
begin
shadow_row_timer[i] <= shadow_row_timer[i] - 1'b1;
end
if (shadow_row_timer[i] <= 1)
begin
shadow_row_timer_ready[i] <= 1'b1;
end
if (shadow_row_timer[i] <= 2)
begin
shadow_row_timer_pre_ready[i] <= 1'b1;
end
end
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Request logic
//----------------------------------------------------------------------------------------------------
// Can_* logic for request logic, indicate whether TBP can request now
// Can activate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_act[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (activated_combi[i]) // activated, so there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (col_grant[i]) //done, there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (load_tbp[i]) // new TBP command, assume no open-row-pass (handled by statement above)
begin
can_act[i] <= 1'b1;
end
else if
(
!done[i] && valid[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
)
// precharge or precharge all command, re-enable since it is not done
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_act[i] <= 1'b1;
end
end
end
end
// Can precharge
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= one; // there is no logic required for precharge, keeping this for future use
end
end
end
// Can read
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_rd[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_rd[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't read since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_rd[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_rd[i] <= 1'b1;
end
end
end
end
// Can write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_wr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_wr[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't write since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_wr[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_wr[i] <= 1'b1;
end
end
end
end
// Row request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_req[i] = act_req[i] | pch_req[i];
end
end
// Column request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_req[i] = rd_req[i] | wr_req[i];
end
end
// Individual activate, precharge, read and write request logic
always @ (*)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
act_req[i] = nor_rpv[i] & nor_sbv[i] & nor_sbvt[i] & ~or_wrt[i] & can_act[i];
pch_req[i] = require_pch[i] & pch_ready[i] & can_pch[i];
rd_req [i] = nor_cpv[i] & can_rd[i] & complete_rd[i];
wr_req [i] = nor_cpv[i] & can_wr[i] & complete_wr[i];
end
end
//----------------------------------------------------------------------------------------------------
// Valid logic
//----------------------------------------------------------------------------------------------------
// Indicates that current TBP is valid after load an invalid after flush
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
valid[i] <= 1'b1;
end
else if (flush_tbp[i])
begin
valid[i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// TBP information
//----------------------------------------------------------------------------------------------------
// Keeps information from cmd_gen after load
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
chipsel [i] <= 0;
bank [i] <= 0;
row [i] <= 0;
col [i] <= 0;
write [i] <= 0;
read [i] <= 0;
size [i] <= 0;
autopch [i] <= 0;
localid [i] <= 0;
dataid [i] <= 0;
rmw_correct[i] <= 0;
rmw_partial[i] <= 0;
rmw [i] <= 0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
chipsel [i] <= cmd_gen_chipsel;
bank [i] <= cmd_gen_bank;
row [i] <= cmd_gen_row;
col [i] <= cmd_gen_col;
write [i] <= cmd_gen_write;
read [i] <= cmd_gen_read;
size [i] <= cmd_gen_size;
autopch [i] <= cmd_gen_autopch;
localid [i] <= cmd_gen_localid;
dataid [i] <= cmd_gen_dataid;
rmw_correct[i] <= cmd_gen_rmw_correct;
rmw_partial[i] <= cmd_gen_rmw_partial;
rmw [i] <= cmd_gen_rmw_partial | cmd_gen_rmw_correct;
end
end
end
// Priority information
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
priority_a[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_DISABLE_PRIORITY == 1)
begin
priority_a[i] <= zero;
end
else
begin
if (load_tbp[i])
begin
if (cfg_reorder_data) // priority will be ignored when data reordering is OFF
begin
priority_a[i] <= cmd_gen_priority;
end
else
begin
priority_a[i] <= 1'b0;
end
end
else if (starvation[i] == cfg_starve_limit) // assert priority when starvation limit is reached
begin
priority_a[i] <= 1'b1;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Row dependency vector
//----------------------------------------------------------------------------------------------------
// RPV, TBP is only allowed to request row command when RPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !push_tbp[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && (same_chip_bank_row[j] || (same_chip_bank[j] && (rmw_partial[j] || rmw_correct[j])))) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && same_chip_bank[j]) ||
(!cfg_reorder_data && valid[j] && same_chip_bank[j])
)
)
// (INTER_ROW) Set RPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set RPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// This is to prevent activate going to the later RMW commands
// (INTER_BANK) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (NON_REORDER) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs, to allow command reordering
begin
rpv_combi[i][j] = 1'b1;
end
else
begin
rpv_combi[i][j] = 1'b0;
end
end
else if (flush_tbp[j] || push_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
rpv_combi[i][j] = 1'b0;
end
else
begin
rpv_combi[i][j] = rpv[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (load_tbp[i])
begin
if (!flush_shadow_tbp[j] && ((shadow_valid[j] && same_shadow_chip_bank[j]) || (push_tbp[j] && same_chip_bank[j])))
// Set Shadow RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else
begin
shadow_rpv_combi[i][j] = 1'b0;
end
end
else if (push_tbp[j] && rpv[i][j])
// If there is a push_tbp and RPV is set to '1'
// We need to shift RPV to Shadow RPV
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else if (flush_shadow_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
shadow_rpv_combi[i][j] = 1'b0;
end
else
begin
shadow_rpv_combi[i][j] = shadow_rpv[i][j];
end
end
else
begin
shadow_rpv_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= ~|{shadow_rpv_combi[i], rpv_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
rpv[i][j] <= 1'b0;
end
else
begin
rpv[i][j] <= rpv_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= shadow_rpv_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Column dependency vector
//----------------------------------------------------------------------------------------------------
// CPV, TBP is only allowed to request column command when CPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !col_grant[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank_row[j] || (rmw[j] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct)) || same_command_read[j])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank [j] || (rmw[j] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct)) || same_command_read[j])) ||
(!cfg_reorder_data && valid[j] && !done[j])
)
)
// (INTER_ROW) Set CPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_ROW) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (INTER_BANK) Set CPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (INTER_BANK) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_BANK) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (NON_REORDER) Set CPV to '1' when a new TBP is loaded, all column command must be executed in order
begin
cpv_combi[i][j] = 1'b1;
end
else
begin
cpv_combi[i][j] = 1'b0;
end
end
else if (col_grant[j])
// (INTER_ROW) Set CPV to '0' after col_grant
// (INTER_BANK) Set CPV to '0' after col_grant
begin
cpv_combi[i][j] = 1'b0;
end
else
begin
cpv_combi[i][j] = cpv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
cpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= ~|cpv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
cpv[i][j] <= 1'b0;
end
else
begin
cpv[i][j] <= cpv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Activate related logic
//----------------------------------------------------------------------------------------------------
// Open-row-pass flush logic
// after a granted command and WST (open row pass to another TBP with same page from just granted command) OR
// after a done command and WST (open row pass to another TBP with same page from a done command with page open)
// Logic to determine which not-done TBP should be flushed to perform open-row-pass
always @ (*)
begin
not_done_tbp_row_pass_flush = col_grant & wst_p;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= not_done_tbp_row_pass_flush[i];
end
end
end
// Logic to determine which done TBP should be flushed to perform open-row-pass
always @ (*)
begin
done_tbp_row_pass_flush = done & wst_p & ~row_grant & ~precharge_tbp;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (done_tbp_row_pass_flush_r[i])
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
else
begin
done_tbp_row_pass_flush_r[i] <= done_tbp_row_pass_flush[i];
end
end
end
end
// Using done_tbp_row_pass_flush_r to improve timing
// it's acceptable to add one clock cycle latency when performing open-row-pass from a done command
// [REMARK] there is potential to optimize the flush logic (for done-open-row-pass case), because flush_tbp depends on open_row_pass_flush logic
assign open_row_pass_flush = not_done_tbp_row_pass_flush | done_tbp_row_pass_flush;
// Open-row-pass logic, TBP will pass related information to same page command (increase efficiency)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass[i] = |open_row_pass_flush && or_wrt[i] && |(wrt[i] & open_row_pass_flush);
end
end
// Open-row-passed logic, keep signal high once there is a open-row-pass to current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_passed[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (open_row_pass[i])
begin
open_row_passed[i] <= 1'b1;
end
else if (flush_tbp[i])
begin
open_row_passed[i] <= 1'b0;
end
end
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= 1'b0;
open_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= open_row_pass [i];
open_row_pass_flush_r[i] <= open_row_pass_flush[i];
end
end
end
// Activated logic
// indicate that current TBP is activated by activate command or open-row-pass
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (act_grant[i] || open_row_pass[i])
begin
activated_combi[i] = 1'b1;
end
else
begin
activated_combi[i] = 1'b0;
end
end
end
// activated need not to be validated with valid
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated [i] <= 1'b0;
activated_p[i] <= 1'b0;
end
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated_p[i] <= activated_combi[i]; // activated pulse
if (flush_tbp[i] || pch_grant[i])
begin
activated[i] <= 1'b0;
end
else if (precharge_tbp[i])
begin
activated[i] <= 1'b0;
end
else if (activated_combi[i])
begin
activated[i] <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Precharge related logic
//----------------------------------------------------------------------------------------------------
// Precharge all logic
// indicate which TBP is precharged cause of sideband precharge all command
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharge_tbp[i] = sb_tbp_precharge_all[i];
end
end
// Precharge logic
// indicate which TBP is precharged
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
precharged_combi[i] = 1'b0;
end
else if (activated_combi[i] && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW")
// Only required in INTER-ROW reordering case since TBP might request precharge after TBP load
// due to TBP interlock case
begin
precharged_combi[i] = 1'b0;
end
else if (col_grant[i] && real_ap[i])
begin
precharged_combi[i] = 1'b1;
end
else if (pch_grant[i])
begin
precharged_combi[i] = 1'b1;
end
else
begin
precharged_combi[i] = precharged[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= precharged_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Auto-precharge related logic
//----------------------------------------------------------------------------------------------------
// Auto precharge related logic, to determine which TBP should be closed or kept open
// OPP - autoprecharge when there is another command to same chip-bank different row
// CPP - do not autoprecharge when there is another command to the same chip-bank-row
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
apvo_combi[i] = 1'b0;
apvc_combi[i] = 1'b0;
end
else if
(
(load_tbp[i] && CFG_DATA_REORDERING_TYPE == "INTER_ROW") || // load self
(
(|load_tbp && !load_tbp[i]) && // load other TBP
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb[i]) ||
(!cfg_reorder_data && !ssb[i])
)
)
)
// (INTER_ROW) update multiple times whenever there is a load so that it'll get the latest AP info
// (INTER_BANK) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
// (NON_REORDER) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
begin
if
(
(load_tbp[i] && |(valid & same_chip_bank_diff_row) && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_diff_row[i])
)
// (INTER_ROW) on self load, set to '1' if other valid TBP is same-chip-bank-diff-row with self
// set to '1' if there is a new command with same-chip-bank-diff-row with current TBP
begin
apvo_combi[i] = 1'b1;
end
else
begin
apvo_combi[i] = apvo[i];
end
if ((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_row[i])
// set to '1' if there is a new command with same-chip-bank-row with current TBP
begin
apvc_combi[i] = 1'b1;
end
else
begin
apvc_combi[i] = apvc[i];
end
end
else
begin
apvo_combi[i] = apvo[i];
apvc_combi[i] = apvc[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= 1'b0;
apvc[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= apvo_combi[i];
apvc[i] <= apvc_combi[i];
end
end
end
// Auto precharge
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (apvc[i]) // keeping a page open have higher priority that keeping a close page (improve efficiency)
begin
ap[i] = 1'b0;
end
else if (apvo[i])
begin
ap[i] = 1'b1;
end
else
begin
ap[i] = autopch[i] | require_flush[i];
end
end
end
// Real auto-precharge
// purpose is to make pipelining easier in the future (if needed)
always @ (*)
begin
real_ap = ap;
end
//----------------------------------------------------------------------------------------------------
// Done logic
//----------------------------------------------------------------------------------------------------
// Indicate that current TBP has finished issuing column command
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (flush_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (col_grant[i])
begin
done_combi[i] = 1'b1;
end
else
begin
done_combi[i] = done[i];
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= done_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Complete logic
//----------------------------------------------------------------------------------------------------
reg [CFG_CTL_TBP_NUM-1:0] partial_vector_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] partial_vector [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] load_rmw_data;
reg [CFG_CTL_TBP_NUM-1:0] all_complete_vector;
reg all_complete;
wire data_rmw_fetch = data_rmw_complete && !all_complete;
// Partial information, to indicate which partial command should receive the current data_rmw_complete
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j)
begin
partial_vector_combi[i][j] = zero;
end
else
begin
if (load_tbp[i] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct) && cmd_gen_write) // only required for partial write commands
begin
if (!done[j] && valid[j] && rmw[j] && write[j] && !load_rmw_data[j] && !complete_wr[j]) // compare with current valid and not done RMW commands
begin
partial_vector_combi[i][j] = 1'b1;
end
else
begin
partial_vector_combi[i][j] = 1'b0;
end
end
else if (load_rmw_data[j])
begin
partial_vector_combi[i][j] = 1'b0;
end
else
begin
partial_vector_combi[i][j] = partial_vector[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
partial_vector[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
partial_vector[i][j] <= partial_vector_combi[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
load_rmw_data[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (~|partial_vector_combi[i] && data_rmw_complete)
begin
load_rmw_data[i] <= 1'b1;
end
else
begin
load_rmw_data[i] <= 1'b0;
end
end
end
end
// Indicate that the data for current TBP is complete and ready to be issued
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
if (cmd_gen_read)
begin
complete_combi_rd[i] = cmd_gen_complete;
complete_combi_wr[i] = 1'b0;
end
else
begin
complete_combi_rd[i] = 1'b0;
complete_combi_wr[i] = cmd_gen_complete;
end
end
else if (write[i] && !complete[i])
begin
complete_combi_rd[i] = complete_rd[i];
if (cfg_enable_rmw)
begin
complete_combi_wr[i] = load_rmw_data[i];
end
else
begin
complete_combi_wr[i] = data_complete[i];
end
end
else
begin
complete_combi_rd[i] = complete_rd[i];
complete_combi_wr[i] = complete_wr[i];
end
end
end
always @ (*)
begin
complete_combi = complete_combi_rd | complete_combi_wr;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
complete <= 0;
complete_rd <= 0;
complete_wr <= 0;
end
else
begin
complete <= complete_combi;
complete_rd <= complete_combi_rd;
complete_wr <= complete_combi_wr;
end
end
// To indicate that all TBP has completed, expect non-valid TBP
always @ (*)
begin
all_complete = &all_complete_vector;
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (!valid[i])
begin
all_complete_vector[i] = 1'b1;
end
else
begin
all_complete_vector[i] = complete[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Same bank vector logic
//----------------------------------------------------------------------------------------------------
// This bit vector (same bank vector) is to stop a TBP from requesting activate when another row in the same chip-bank was granted
// SBV stops TBP from requesting activate when there is another same-chip-bank-diff-row was granted
// prevents activate to and activated bank
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
// There is no need to SBV in INTER_BANK case
sbv_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if
(
(load_tbp[i] && !flush_tbp[j] && (activated[j] || activated_combi[j]) && same_chip_bank_diff_row[j]) ||
(activated_combi[j] && valid[i] && pre_calculated_same_chip_bank_diff_row [i][j])
)
// Set SBV to '1' if new TBP is same-chip-bank-diff-row with other existing TBP
// Set SBV to '1' if there is a row_grant or open-row-pass to other existing TBP with same-chip-bank-diff-row
begin
sbv_combi[i][j] = 1'b1;
end
else if (flush_tbp[j] || pch_grant[j] || precharge_tbp[j])
// Set SBV to '0' if there is a flush to other TBP
// Set SBV to '0' if there is a precharge to other TBP
// Set SBV to '0' if there is a precharge all command from sideband
begin
sbv_combi[i][j] = 1'b0;
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= ~|sbv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbv[i][j] <= 1'b0;
end
else
begin
sbv[i][j] <= sbv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Same bank timer vector logic
//----------------------------------------------------------------------------------------------------
// SBTV stops TBP from requesting activate when the timer for same-chip-bank is still running
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_tbp[i])
begin
sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j])
begin
sbvt_combi[i][j] = 1'b0;
end
else if
(
(pch_grant[j] || (col_grant[j] && real_ap[j])) &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when there is a precharge/auto-precharge to same-chip-bank address
begin
sbvt_combi[i][j] = 1'b1;
end
else if
(
precharged[j] && valid[j] &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when same-chip-bank address TBP is still in precharge state
begin
sbvt_combi[i][j] = ~row_timer_pre_ready[j];
end
else
begin
sbvt_combi[i][j] = zero;
end
end
else
begin
sbvt_combi[i][j] = sbvt[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
shadow_sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_shadow_tbp[j])
begin
shadow_sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j] && sbvt[i][j])
begin
shadow_sbvt_combi[i][j] = 1'b1;
end
else if (valid[i] && shadow_valid[j] && pre_calculated_same_shadow_chip_bank[i][j])
// Set to 'timer-pre-ready' when own TBP is valid, shadow TBP is valid and same chip-bank address
begin
shadow_sbvt_combi[i][j] = ~shadow_row_timer_pre_ready[j];
end
else
begin
shadow_sbvt_combi[i][j] = shadow_sbvt[i][j];
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbvt[i] <= ~|{shadow_sbvt_combi[i], sbvt_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbvt[i][j] <= 1'b0;
end
else
begin
sbvt[i][j] <= sbvt_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= shadow_sbvt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssb[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssb[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank[i])
begin
ssb[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank row logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank-row with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssbr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssbr[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank_row[i])
begin
ssbr[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will send transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will pass current TBP information (timing/page) over to other TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i]) // Reset back to '0'
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && precharged_combi[i] && done_combi[i]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && precharged_combi[i] ) ||
(!cfg_reorder_data && precharged_combi[i])
)
// Set to '0' when there is a precharge to current TBP, after a precharge, it's not possible to perform open-row-pass anymore
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if (open_row_pass_flush[i]) // make sure open-row-pass only asserts for one clock cycle
begin
wst_p[i] <= 1'b0;
end
else if
(
load_tbp[j] && same_chip_bank_row[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[i] && !(precharged_combi[i] && done_combi[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [i] && !(precharged_combi[i] )) ||
(!cfg_reorder_data && !ssb[i] && !precharged_combi[i])
)
)
// Set to '1' when there is a new TBP being loaded, with same-chip-bank-row with current TBP
// make sure current TBP is not precharged so that information can be pass over to same-chip-bank-row TBP
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
// (INTER_BANK) make sure SSB is not set (only set WST once)
// (NON_REORDER) make sure SSB is not set (only set WST once)
begin
wst [i] <= 1'b1;
wst_p[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will receive transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will receive TBP information (timing/page) from other TBP (also tells which TBP it is receiving from)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if
(
load_tbp[i] && !flush_tbp[j] && valid[j] && same_chip_bank_row[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[j]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [j]) ||
(!cfg_reorder_data && !ssb[j])
)
)
// Set to '1' when there is a new TBp being loaded, with same-chip-bank-row with other existing TBP
// provided other TBP is valid and not precharged
// (INTER_BANK) make sure SSB of other TBP is not set, to handle row interrupt case
begin
wrt_combi[i][j] = 1'b1;
end
else if (flush_tbp[j])
begin
wrt_combi[i][j] = 1'b0;
end
else
begin
wrt_combi[i][j] = wrt[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
wrt [i] <= 0;
or_wrt [i] <= 1'b0;
nor_wrt[i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
or_wrt [i] <= |wrt_combi[i];
nor_wrt[i] <= ~|wrt_combi[i];
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin
if (i == j)
wrt[i][j] <= 1'b0;
else
wrt[i][j] <= wrt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require flush logic
//----------------------------------------------------------------------------------------------------
// On demand flush selection, command with same chip-bank-diff-row first, we dont want to precharge twice
// if there are none, flush cmd to diff chip-bank, we might have cmd to the same row in tbp already
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_flush[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_CTL_TBP_NUM == 1)
begin
require_flush[i] <= cmd_gen_load | cmd_gen_waiting_to_load;
end
else
begin
if (|flush_tbp) // tbp will not be full on the next clock cycle
begin
require_flush[i] <= 1'b0;
end
else if (int_tbp_full && (cmd_gen_load | cmd_gen_waiting_to_load))
begin
if (same_chip_bank_row[i])
require_flush[i] <= 1'b0;
else
require_flush[i] <= 1'b1;
end
else
begin
require_flush[i] <= 1'b0;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require precharge logic
//----------------------------------------------------------------------------------------------------
// Precharge request logic, to clear up lockup state in TBP
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
require_pch_combi[i][j] = zero;
end
else
begin
if (i == j)
begin
require_pch_combi[i][j] = 1'b0;
end
else if (activated[i] && !done[i])
begin
if (cpv[i][j] && sbv[j][i])
begin
require_pch_combi[i][j] = 1'b1;
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
require_pch[i] <= 1'b0;
end
else
begin
// included real_ap since real_ap is part of precharge request (!apvc so that it will deassert pch_req when not needed)
require_pch[i] <= |require_pch_combi[i] | (done[i] & real_ap[i] & !apvc_combi[i]);
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Address/command comparison logic
//----------------------------------------------------------------------------------------------------
// Command comparator
always @ (*)
begin
if (CFG_DISABLE_READ_REODERING) // logic only enabled when parameter is set to '1'
begin
same_command_read = cmd_gen_same_read_cmd;
end
else
begin
same_command_read = {CFG_CTL_TBP_NUM{zero}};
end
end
always @ (*)
begin
same_shadow_command_read = {CFG_CTL_SHADOW_TBP_NUM{zero}};
end
// Address comparator
always @(*)
begin
same_chip_bank = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr;
same_chip_bank_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & cmd_gen_same_row_addr;
same_chip_bank_diff_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & ~cmd_gen_same_row_addr;
end
always @ (*)
begin
same_shadow_chip_bank = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr;
same_shadow_chip_bank_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & cmd_gen_same_shadow_row_addr;
same_shadow_chip_bank_diff_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & ~cmd_gen_same_shadow_row_addr;
end
// Registered version, to improve fMAX
generate
begin
genvar i_tbp;
genvar j_tbp;
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop
for (j_tbp = 0;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= same_chip_bank_diff_row [j_tbp];
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= same_chip_bank_row [j_tbp];
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
end
else if (load_tbp [j_tbp])
begin
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] != cmd_gen_row)
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] == cmd_gen_row)
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank)
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
begin
if (row [i_tbp] != row [j_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
end
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop_shadow
for (j_tbp = 0;j_tbp < CFG_CTL_SHADOW_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop_shadow
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
if (push_tbp [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_shadow_chip_bank [j_tbp];
end
else if (push_tbp [j_tbp])
begin
if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == shadow_chipsel [j_tbp] && bank [i_tbp] == shadow_bank [j_tbp])
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Bank specific timer related logic
//----------------------------------------------------------------------------------------------------
// Offset timing paramter to achieve accurate timing gap between commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 0;
compare_t_param_act_to_act_less_than_offset <= 0;
compare_t_param_act_to_pch_less_than_offset <= 0;
compare_t_param_rd_to_pch_less_than_offset <= 0;
compare_t_param_wr_to_pch_less_than_offset <= 0;
compare_t_param_pch_to_valid_less_than_offset <= 0;
compare_t_param_rd_ap_to_valid_less_than_offset <= 0;
compare_t_param_wr_ap_to_valid_less_than_offset <= 0;
compare_offset_t_param_act_to_rdwr_less_than_0 <= 0;
compare_offset_t_param_act_to_rdwr_less_than_1 <= 0;
end
else
begin
if (t_param_act_to_rdwr > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b1;
end
if (t_param_act_to_act > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_act_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_act_less_than_offset <= 1'b1;
end
if (t_param_act_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b1;
end
if (t_param_rd_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b1;
end
if (t_param_wr_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b1;
end
if (t_param_pch_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b1;
end
if (t_param_rd_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b1;
end
if (t_param_wr_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b1;
end
if (offset_t_param_act_to_rdwr <= 0)
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b0;
end
if (offset_t_param_act_to_rdwr <= 1)
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
offset_t_param_act_to_rdwr <= 0;
offset_t_param_act_to_act <= 0;
offset_t_param_act_to_pch <= 0;
offset_t_param_rd_to_pch <= 0;
offset_t_param_wr_to_pch <= 0;
offset_t_param_pch_to_valid <= 0;
offset_t_param_rd_ap_to_valid <= 0;
offset_t_param_wr_ap_to_valid <= 0;
end
else
begin
if (!compare_t_param_act_to_rdwr_less_than_offset)
begin
offset_t_param_act_to_rdwr <= t_param_act_to_rdwr - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_rdwr <= 0;
end
if (!compare_t_param_act_to_act_less_than_offset)
begin
offset_t_param_act_to_act <= t_param_act_to_act - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_act <= 0;
end
if (!compare_t_param_act_to_pch_less_than_offset)
begin
offset_t_param_act_to_pch <= t_param_act_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_pch <= 0;
end
if (!compare_t_param_rd_to_pch_less_than_offset)
begin
offset_t_param_rd_to_pch <= t_param_rd_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_to_pch <= 0;
end
if (!compare_t_param_wr_to_pch_less_than_offset)
begin
offset_t_param_wr_to_pch <= t_param_wr_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_to_pch <= 0;
end
if (!compare_t_param_pch_to_valid_less_than_offset)
begin
offset_t_param_pch_to_valid <= t_param_pch_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_pch_to_valid <= 0;
end
if (!compare_t_param_rd_ap_to_valid_less_than_offset)
begin
offset_t_param_rd_ap_to_valid <= t_param_rd_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_ap_to_valid <= 0;
end
if (!compare_t_param_wr_ap_to_valid_less_than_offset)
begin
offset_t_param_wr_ap_to_valid <= t_param_wr_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_ap_to_valid <= 0;
end
end
end
// Pre-calculated logic to improve timing, for row_timer and trc_timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
compare_t_param_rd_to_pch_greater_than_row_timer [i] <= 1'b0;
compare_t_param_wr_to_pch_greater_than_row_timer [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (t_param_rd_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
end
end
// Column timer logic
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b0;
col_timer_pre_ready[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (row_grant[i])
begin
if (compare_t_param_act_to_rdwr_less_than_offset)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b1;
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer [i] <= offset_t_param_act_to_rdwr;
if (compare_offset_t_param_act_to_rdwr_less_than_0)
begin
col_timer_ready [i] <= 1'b1;
end
else
begin
col_timer_ready [i] <= 1'b0;
end
if (compare_offset_t_param_act_to_rdwr_less_than_1)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
else
begin
if (col_timer[i] != 0)
begin
col_timer[i] <= col_timer[i] - 1'b1;
end
if (col_timer[i] <= 1)
begin
col_timer_ready[i] <= 1'b1;
end
else
begin
col_timer_ready[i] <= 1'b0;
end
if (col_timer[i] <= 2)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
end
// log2 result of open-row-pass-flush, to be used during timer information pass
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush[i] = log2(open_row_pass_flush & wrt[i]);
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= log2_open_row_pass_flush[i];
end
end
end
// Combined timer logic
// compare between row_timer and trc_timer and take the largest value
// to be used in open_row_pass only
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
combined_timer[i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_REG_GRANT == 0 && open_row_pass_r[i]) // for QR controller only
begin
if (col_grant[i])
begin
if (row_timer_combi[i] > combined_timer[log2_open_row_pass_flush_r[i]])
begin
combined_timer[i] <= row_timer_combi[i];
end
else
begin
combined_timer[i] <= (combined_timer[log2_open_row_pass_flush_r[i]] > 1'b1) ? (combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 1'b1;
end
end
else
begin
combined_timer[i] <= (combined_timer[log2_open_row_pass_flush_r[i]] > 1'b1) ? (combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 1'b1;
end
end
else
begin
if (row_timer_combi[i] > trc_timer[i])
begin
combined_timer[i] <= row_timer_combi[i];
end
else
begin
combined_timer[i] <= (trc_timer[i] > 1'b1) ? (trc_timer[i] - 1'b1) : 1'b1;
end
end
end
end
end
// Row timer logic
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (trc_timer[i] <= 1)
begin
trc_timer_pre_ready_combi[i] = 1'b1;
end
else
begin
trc_timer_pre_ready_combi[i] = 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b1;
trc_timer_pre_ready[i] <= 1'b1;
end
// We need to update the timer as soon as possible when CFG_REG_GRANT == 0
// because after open-row-pass, row grant can happen on the next clock cycle
else if (CFG_REG_GRANT == 0 && open_row_pass[i])
begin
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else if
(open_row_pass_r[i])
begin
trc_timer [i] <= combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else if (act_grant[i])
begin
trc_timer [i] <= offset_t_param_act_to_act;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (trc_timer[i] != 0)
begin
trc_timer[i] <= trc_timer[i] - 1'b1;
end
if (trc_timer[i] <= 1)
begin
trc_timer_ready[i] <= 1'b1;
end
if (trc_timer[i] <= 2)
begin
trc_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (rd_grant[i])
begin
if (real_ap[i])
begin
row_timer_combi[i] = offset_t_param_rd_ap_to_valid;
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_rd_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_rd_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_rd_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else if (wr_grant[i])
begin
if (real_ap[i])
begin
row_timer_combi[i] = offset_t_param_wr_ap_to_valid;
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_wr_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_wr_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_wr_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else
begin
if (row_timer[i] != 0)
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
else
begin
row_timer_combi[i] = 0;
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else if (act_grant[i])
begin
if (compare_t_param_act_to_pch_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRAS after precharge command
row_timer [i] <= offset_t_param_act_to_pch;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (pch_grant[i])
begin
if (compare_t_param_pch_to_valid_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRP after precharge command
row_timer [i] <= offset_t_param_pch_to_valid;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (col_grant[i])
begin
row_timer [i] <= row_timer_combi[i];
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (row_timer[i] != 0)
begin
row_timer[i] <= row_timer[i] - 1'b1;
end
if (row_timer[i] <= 1)
begin
row_timer_ready[i] <= 1'b1;
end
if (row_timer[i] <= 2)
begin
row_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
// Logic to let precharge request logic that it is ready to request now
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
pch_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (open_row_pass[i] || open_row_pass_r[i] || pch_grant[i] || col_grant[i])
// disable pch_ready after open-row-pass and grant
// since precharge is not needed immediately after TBP is loaded
begin
pch_ready[i] <= 1'b0;
end
else if (row_timer_pre_ready[i] && ((trc_timer_pre_ready[i] && open_row_passed[i]) || !open_row_passed[i]) && !precharged[i])
// disable pch_ready if current TBP is precharged
// only compare with trc_timer if TBP is an open_row_pass command
begin
pch_ready[i] <= 1'b1;
end
else
begin
pch_ready[i] <= 1'b0;
end
end
end
end
// Logic to let sideband know which chip contains active banks
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_bank_closed[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i && valid[j])
begin
if (sb_tbp_precharge_all[j])
begin
int_bank_closed[i][j] <= 1'b1;
end
else if (precharged_combi[j])
begin
int_bank_closed[i][j] <= 1'b1;
end
else if (activated_combi[j])
begin
int_bank_closed[i][j] <= 1'b0;
end
end
else
begin
int_bank_closed[i][j] <= 1'b1; // else default to '0'
end
end
end
end
end
// Logic to let sideband know which chip contains running timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i)
begin
if (col_grant[j] || row_grant[j])
begin
int_timer_ready[i][j] <= 1'b0;
end
else if (trc_timer_pre_ready[j] && row_timer_pre_ready[j])
begin
int_timer_ready[i][j] <= 1'b1;
end
else
begin
int_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (shadow_chipsel[j] == i)
begin
if (push_tbp[j])
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
else if (shadow_row_timer_pre_ready[j])
begin
int_shadow_timer_ready[i][j] <= 1'b1;
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
else
begin
int_shadow_timer_ready[i][j] <= one;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
bank_closed[i] = &int_bank_closed[i];
timer_ready[i] = &{int_shadow_timer_ready[i], int_timer_ready[i]};
end
end
//----------------------------------------------------------------------------------------------------
// Age logic
//----------------------------------------------------------------------------------------------------
// To tell the current age of each TBP entry
// so that arbiter will be able to grant the oldest entry (if there is a tie-break)
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
age[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j)
begin
age[i][j] <= 1'b0;
end
else
begin
if (load_tbp[i])
if (!flush_tbp[j] && (valid[j]))
age[i][j] <= 1'b1;
else
age[i][j] <= 1'b0;
else if (flush_tbp[j])
age[i][j] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Starvation logic
//----------------------------------------------------------------------------------------------------
// Logic will increments when there is a col_grant to other TBP
// will cause priority to be asserted when the count reaches starvation threshold
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
starvation[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i] || done[i]) // stop starvation count when the current TBP is done
starvation[i] <= 0;
else if (|col_grant && starvation[i] < cfg_starve_limit)
starvation[i] <= starvation[i]+1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Burst chop logic
//----------------------------------------------------------------------------------------------------
// Logic to determine whether we will issue burst chop in DDR3 mode only
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size <= 2'd2 && cmd_gen_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
burst_chop [i] <= 1'b1;
else if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 4)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 8)
begin
// Burst chop is not available in quarter rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// This module records profiling information. It is connected to the desired
// pipeline ports that are needed to be profiled.
// cntl_in signal determines when a profiling register is updated.
// incr_in signal determines the increment value for each counter.
// NUM_COUNTERS of profiling registers are instantiated. When the profile_shift
// signal is high, profiling registers are shifted out 1-bit at a time.
//
module acl_profiler
(
clock,
resetn,
enable,
profile_shift,
incr_cntl,
incr_val,
daisy_out
);
parameter COUNTER_WIDTH=64;
parameter INCREMENT_WIDTH=32;
parameter NUM_COUNTERS=4;
parameter TOTAL_INCREMENT_WIDTH=INCREMENT_WIDTH * NUM_COUNTERS;
input clock;
input resetn;
input enable;
input profile_shift;
input [NUM_COUNTERS-1:0] incr_cntl;
input [TOTAL_INCREMENT_WIDTH-1:0] incr_val;
output daisy_out;
// if there are NUM_COUNTER counters, there are NUM_COUNTER-1 connections between them
wire [NUM_COUNTERS-2:0] shift_wire;
wire [31:0] data_out [0:NUM_COUNTERS-1];// for debugging, always 32-bit for ease of modelsim
genvar n;
generate
for(n=0; n<NUM_COUNTERS; n++)
begin : counter_n
if(n == 0)
acl_profile_counter #(
.COUNTER_WIDTH( COUNTER_WIDTH ),
.INCREMENT_WIDTH( INCREMENT_WIDTH )
) counter (
.clock( clock ),
.resetn( resetn ),
.enable( enable ),
.shift( profile_shift ),
.incr_cntl( incr_cntl[n] ),
.shift_in( shift_wire[n] ),
.incr_val( incr_val[ ((n+1)*INCREMENT_WIDTH-1) : (n*INCREMENT_WIDTH) ] ),
.data_out( data_out[ n ] ),
.shift_out( daisy_out )
);
else if(n == NUM_COUNTERS-1)
acl_profile_counter #(
.COUNTER_WIDTH( COUNTER_WIDTH ),
.INCREMENT_WIDTH( INCREMENT_WIDTH )
) counter (
.clock( clock ),
.resetn( resetn ),
.enable( enable ),
.shift( profile_shift ),
.incr_cntl( incr_cntl[n] ),
.shift_in( 1'b0 ),
.incr_val( incr_val[ ((n+1)*INCREMENT_WIDTH-1) : (n*INCREMENT_WIDTH) ] ),
.data_out( data_out[ n ] ),
.shift_out( shift_wire[n-1] )
);
else
acl_profile_counter #(
.COUNTER_WIDTH( COUNTER_WIDTH ),
.INCREMENT_WIDTH( INCREMENT_WIDTH )
) counter (
.clock( clock ),
.resetn( resetn ),
.enable( enable ),
.shift( profile_shift ),
.incr_cntl( incr_cntl[n] ),
.shift_in( shift_wire[n] ),
.incr_val( incr_val[ ((n+1)*INCREMENT_WIDTH-1) : (n*INCREMENT_WIDTH) ] ),
.data_out( data_out[ n ] ),
.shift_out( shift_wire[n-1] )
);
end
endgenerate
endmodule
module acl_profile_counter
(
clock,
resetn,
enable,
shift,
incr_cntl,
shift_in,
incr_val,
data_out,
shift_out
);
parameter COUNTER_WIDTH=64;
parameter INCREMENT_WIDTH=32;
input clock;
input resetn;
input enable;
input shift;
input incr_cntl;
input shift_in;
input [INCREMENT_WIDTH-1:0] incr_val;
output [31:0] data_out;// for debugging, always 32-bit for ease of modelsim
output shift_out;
reg [COUNTER_WIDTH-1:0] counter;
always@(posedge clock or negedge resetn)
begin
if( !resetn )
counter <= { COUNTER_WIDTH{1'b0} };
else if(shift) // shift by one bit
counter <= { counter[COUNTER_WIDTH-2:0], shift_in };
else if(enable && incr_cntl) // increment counter
counter <= counter + incr_val;
end
assign data_out = counter;
assign shift_out = counter[COUNTER_WIDTH-1:COUNTER_WIDTH-1];
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module spimemio (
input clk, resetn,
input valid,
output ready,
input [23:0] addr,
output reg [31:0] rdata,
output flash_csb,
output flash_clk,
output flash_io0_oe,
output flash_io1_oe,
output flash_io2_oe,
output flash_io3_oe,
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
output flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di,
input [3:0] cfgreg_we,
input [31:0] cfgreg_di,
output [31:0] cfgreg_do
);
reg xfer_resetn;
reg din_valid;
wire din_ready;
reg [7:0] din_data;
reg [3:0] din_tag;
reg din_cont;
reg din_qspi;
reg din_ddr;
reg din_rd;
wire dout_valid;
wire [7:0] dout_data;
wire [3:0] dout_tag;
reg [23:0] buffer;
reg [23:0] rd_addr;
reg rd_valid;
reg rd_wait;
reg rd_inc;
assign ready = valid && (addr == rd_addr) && rd_valid;
wire jump = valid && !ready && (addr != rd_addr+4) && rd_valid;
reg softreset;
reg config_en; // cfgreg[31]
reg config_ddr; // cfgreg[22]
reg config_qspi; // cfgreg[21]
reg config_cont; // cfgreg[20]
reg [3:0] config_dummy; // cfgreg[19:16]
reg [3:0] config_oe; // cfgreg[11:8]
reg config_csb; // cfgreg[5]
reg config_clk; // cfgref[4]
reg [3:0] config_do; // cfgreg[3:0]
assign cfgreg_do[31] = config_en;
assign cfgreg_do[30:23] = 0;
assign cfgreg_do[22] = config_ddr;
assign cfgreg_do[21] = config_qspi;
assign cfgreg_do[20] = config_cont;
assign cfgreg_do[19:16] = config_dummy;
assign cfgreg_do[15:12] = 0;
assign cfgreg_do[11:8] = {flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe};
assign cfgreg_do[7:6] = 0;
assign cfgreg_do[5] = flash_csb;
assign cfgreg_do[4] = flash_clk;
assign cfgreg_do[3:0] = {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
always @(posedge clk) begin
softreset <= !config_en || cfgreg_we;
if (!resetn) begin
softreset <= 1;
config_en <= 1;
config_csb <= 0;
config_clk <= 0;
config_oe <= 0;
config_do <= 0;
config_ddr <= 0;
config_qspi <= 0;
config_cont <= 0;
config_dummy <= 8;
end else begin
if (cfgreg_we[0]) begin
config_csb <= cfgreg_di[5];
config_clk <= cfgreg_di[4];
config_do <= cfgreg_di[3:0];
end
if (cfgreg_we[1]) begin
config_oe <= cfgreg_di[11:8];
end
if (cfgreg_we[2]) begin
config_ddr <= cfgreg_di[22];
config_qspi <= cfgreg_di[21];
config_cont <= cfgreg_di[20];
config_dummy <= cfgreg_di[19:16];
end
if (cfgreg_we[3]) begin
config_en <= cfgreg_di[31];
end
end
end
wire xfer_csb;
wire xfer_clk;
wire xfer_io0_oe;
wire xfer_io1_oe;
wire xfer_io2_oe;
wire xfer_io3_oe;
wire xfer_io0_do;
wire xfer_io1_do;
wire xfer_io2_do;
wire xfer_io3_do;
reg xfer_io0_90;
reg xfer_io1_90;
reg xfer_io2_90;
reg xfer_io3_90;
always @(negedge clk) begin
xfer_io0_90 <= xfer_io0_do;
xfer_io1_90 <= xfer_io1_do;
xfer_io2_90 <= xfer_io2_do;
xfer_io3_90 <= xfer_io3_do;
end
assign flash_csb = config_en ? xfer_csb : config_csb;
assign flash_clk = config_en ? xfer_clk : config_clk;
assign flash_io0_oe = config_en ? xfer_io0_oe : config_oe[0];
assign flash_io1_oe = config_en ? xfer_io1_oe : config_oe[1];
assign flash_io2_oe = config_en ? xfer_io2_oe : config_oe[2];
assign flash_io3_oe = config_en ? xfer_io3_oe : config_oe[3];
assign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0];
assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1];
assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];
assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];
wire xfer_dspi = din_ddr && !din_qspi;
wire xfer_ddr = din_ddr && din_qspi;
spimemio_xfer xfer (
.clk (clk ),
.resetn (xfer_resetn ),
.din_valid (din_valid ),
.din_ready (din_ready ),
.din_data (din_data ),
.din_tag (din_tag ),
.din_cont (din_cont ),
.din_dspi (xfer_dspi ),
.din_qspi (din_qspi ),
.din_ddr (xfer_ddr ),
.din_rd (din_rd ),
.dout_valid (dout_valid ),
.dout_data (dout_data ),
.dout_tag (dout_tag ),
.flash_csb (xfer_csb ),
.flash_clk (xfer_clk ),
.flash_io0_oe (xfer_io0_oe ),
.flash_io1_oe (xfer_io1_oe ),
.flash_io2_oe (xfer_io2_oe ),
.flash_io3_oe (xfer_io3_oe ),
.flash_io0_do (xfer_io0_do ),
.flash_io1_do (xfer_io1_do ),
.flash_io2_do (xfer_io2_do ),
.flash_io3_do (xfer_io3_do ),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di)
);
reg [3:0] state;
always @(posedge clk) begin
xfer_resetn <= 1;
din_valid <= 0;
if (!resetn || softreset) begin
state <= 0;
xfer_resetn <= 0;
rd_valid <= 0;
din_tag <= 0;
din_cont <= 0;
din_qspi <= 0;
din_ddr <= 0;
din_rd <= 0;
end else begin
if (dout_valid && dout_tag == 1) buffer[ 7: 0] <= dout_data;
if (dout_valid && dout_tag == 2) buffer[15: 8] <= dout_data;
if (dout_valid && dout_tag == 3) buffer[23:16] <= dout_data;
if (dout_valid && dout_tag == 4) begin
rdata <= {dout_data, buffer};
rd_addr <= rd_inc ? rd_addr + 4 : addr;
rd_valid <= 1;
rd_wait <= rd_inc;
rd_inc <= 1;
end
if (valid)
rd_wait <= 0;
case (state)
0: begin
din_valid <= 1;
din_data <= 8'h ff;
din_tag <= 0;
if (din_ready) begin
din_valid <= 0;
state <= 1;
end
end
1: begin
if (dout_valid) begin
xfer_resetn <= 0;
state <= 2;
end
end
2: begin
din_valid <= 1;
din_data <= 8'h ab;
din_tag <= 0;
if (din_ready) begin
din_valid <= 0;
state <= 3;
end
end
3: begin
if (dout_valid) begin
xfer_resetn <= 0;
state <= 4;
end
end
4: begin
rd_inc <= 0;
din_valid <= 1;
din_tag <= 0;
case ({config_ddr, config_qspi})
2'b11: din_data <= 8'h ED;
2'b01: din_data <= 8'h EB;
2'b10: din_data <= 8'h BB;
2'b00: din_data <= 8'h 03;
endcase
if (din_ready) begin
din_valid <= 0;
state <= 5;
end
end
5: begin
if (valid && !ready) begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[23:16];
din_qspi <= config_qspi;
din_ddr <= config_ddr;
if (din_ready) begin
din_valid <= 0;
state <= 6;
end
end
end
6: begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[15:8];
if (din_ready) begin
din_valid <= 0;
state <= 7;
end
end
7: begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[7:0];
if (din_ready) begin
din_valid <= 0;
din_data <= 0;
state <= config_qspi || config_ddr ? 8 : 9;
end
end
8: begin
din_valid <= 1;
din_tag <= 0;
din_data <= config_cont ? 8'h A5 : 8'h FF;
if (din_ready) begin
din_rd <= 1;
din_data <= config_dummy;
din_valid <= 0;
state <= 9;
end
end
9: begin
din_valid <= 1;
din_tag <= 1;
if (din_ready) begin
din_valid <= 0;
state <= 10;
end
end
10: begin
din_valid <= 1;
din_data <= 8'h 00;
din_tag <= 2;
if (din_ready) begin
din_valid <= 0;
state <= 11;
end
end
11: begin
din_valid <= 1;
din_tag <= 3;
if (din_ready) begin
din_valid <= 0;
state <= 12;
end
end
12: begin
if (!rd_wait || valid) begin
din_valid <= 1;
din_tag <= 4;
if (din_ready) begin
din_valid <= 0;
state <= 9;
end
end
end
endcase
if (jump) begin
rd_inc <= 0;
rd_valid <= 0;
xfer_resetn <= 0;
if (config_cont) begin
state <= 5;
end else begin
state <= 4;
din_qspi <= 0;
din_ddr <= 0;
end
din_rd <= 0;
end
end
end
endmodule
module spimemio_xfer (
input clk, resetn,
input din_valid,
output din_ready,
input [7:0] din_data,
input [3:0] din_tag,
input din_cont,
input din_dspi,
input din_qspi,
input din_ddr,
input din_rd,
output dout_valid,
output [7:0] dout_data,
output [3:0] dout_tag,
output reg flash_csb,
output reg flash_clk,
output reg flash_io0_oe,
output reg flash_io1_oe,
output reg flash_io2_oe,
output reg flash_io3_oe,
output reg flash_io0_do,
output reg flash_io1_do,
output reg flash_io2_do,
output reg flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di
);
reg [7:0] obuffer;
reg [7:0] ibuffer;
reg [3:0] count;
reg [3:0] dummy_count;
reg xfer_cont;
reg xfer_dspi;
reg xfer_qspi;
reg xfer_ddr;
reg xfer_ddr_q;
reg xfer_rd;
reg [3:0] xfer_tag;
reg [3:0] xfer_tag_q;
reg [7:0] next_obuffer;
reg [7:0] next_ibuffer;
reg [3:0] next_count;
reg fetch;
reg next_fetch;
reg last_fetch;
always @(posedge clk) begin
xfer_ddr_q <= xfer_ddr;
xfer_tag_q <= xfer_tag;
end
assign din_ready = din_valid && resetn && next_fetch;
assign dout_valid = (xfer_ddr_q ? fetch && !last_fetch : next_fetch && !fetch) && resetn;
assign dout_data = ibuffer;
assign dout_tag = xfer_tag_q;
always @* begin
flash_io0_oe = 0;
flash_io1_oe = 0;
flash_io2_oe = 0;
flash_io3_oe = 0;
flash_io0_do = 0;
flash_io1_do = 0;
flash_io2_do = 0;
flash_io3_do = 0;
next_obuffer = obuffer;
next_ibuffer = ibuffer;
next_count = count;
next_fetch = 0;
if (dummy_count == 0) begin
casez ({xfer_ddr, xfer_qspi, xfer_dspi})
3'b 000: begin
flash_io0_oe = 1;
flash_io0_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[6:0], 1'b 0};
next_count = count - |count;
end else begin
next_ibuffer = {ibuffer[6:0], flash_io1_di};
end
next_fetch = (next_count == 0);
end
3'b 01?: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io2_oe = !xfer_rd;
flash_io3_oe = !xfer_rd;
flash_io0_do = obuffer[4];
flash_io1_do = obuffer[5];
flash_io2_do = obuffer[6];
flash_io3_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[3:0], 4'b 0000};
next_count = count - {|count, 2'b00};
end else begin
next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
end
next_fetch = (next_count == 0);
end
3'b 11?: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io2_oe = !xfer_rd;
flash_io3_oe = !xfer_rd;
flash_io0_do = obuffer[4];
flash_io1_do = obuffer[5];
flash_io2_do = obuffer[6];
flash_io3_do = obuffer[7];
next_obuffer = {obuffer[3:0], 4'b 0000};
next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
next_count = count - {|count, 2'b00};
next_fetch = (next_count == 0);
end
3'b ??1: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io0_do = obuffer[6];
flash_io1_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[5:0], 2'b 00};
next_count = count - {|count, 1'b0};
end else begin
next_ibuffer = {ibuffer[5:0], flash_io1_di, flash_io0_di};
end
next_fetch = (next_count == 0);
end
endcase
end
end
always @(posedge clk) begin
if (!resetn) begin
fetch <= 1;
last_fetch <= 1;
flash_csb <= 1;
flash_clk <= 0;
count <= 0;
dummy_count <= 0;
xfer_tag <= 0;
xfer_cont <= 0;
xfer_dspi <= 0;
xfer_qspi <= 0;
xfer_ddr <= 0;
xfer_rd <= 0;
end else begin
fetch <= next_fetch;
last_fetch <= xfer_ddr ? fetch : 1;
if (dummy_count) begin
flash_clk <= !flash_clk && !flash_csb;
dummy_count <= dummy_count - flash_clk;
end else
if (count) begin
flash_clk <= !flash_clk && !flash_csb;
obuffer <= next_obuffer;
ibuffer <= next_ibuffer;
count <= next_count;
end
if (din_valid && din_ready) begin
flash_csb <= 0;
flash_clk <= 0;
count <= 8;
dummy_count <= din_rd ? din_data : 0;
obuffer <= din_data;
xfer_tag <= din_tag;
xfer_cont <= din_cont;
xfer_dspi <= din_dspi;
xfer_qspi <= din_qspi;
xfer_ddr <= din_ddr;
xfer_rd <= din_rd;
end
end
end
endmodule
|
module cdda_interface (
output bck,
output sd,
output lrck,
input clk,
input rst,
input[10:0] sram_a,
input[31:0] sram_d_in,
output[7:0] sram_d_out,
input sram_cs,
input sram_oe,
input[3:0] sram_wstrb,
output sram_wait,
input[7:0] sdcard_dma_data,
input[8:0] sdcard_dma_addr,
input sdcard_dma_strobe,
);
parameter CLK_FREQUENCY = 33868800;
assign sram_wait = 1'b0;
reg [7:0] sram_d;
assign sram_d_out = sram_d;
wire consume_data;
wire [15:0] left_read_data, right_read_data;
wire [7:0] cpu_access_pos;
wire cpu_writes_to_buffer;
wire cpu_writes_left_low, cpu_writes_left_high;
wire cpu_writes_right_low, cpu_writes_right_high;
reg enabled_d, enabled_q;
reg dso_enabled_d, dso_enabled_q;
reg underflow_d, underflow_q;
reg dma_mode_d, dma_mode_q;
reg dma_buffer_select_d, dma_buffer_select_q;
reg [7:0] bufpos_d, bufpos_q;
reg [7:0] last_valid_data_d, last_valid_data_q;
reg [7:0] scratchpad_d, scratchpad_q;
wire [9:0] write_addr;
wire [3:0] write_strobe;
wire [15:0] write_data_l;
wire [15:0] write_data_r;
assign write_addr = (dma_mode_q? {dma_buffer_select_q, sdcard_dma_addr} : sram_a[9:0]);
assign write_strobe = (dma_mode_q? 1 << sdcard_dma_addr[1:0] : sram_wstrb);
assign write_data_l = (dma_mode_q? {2{sdcard_dma_data}} : sram_d_in[15:0]);
assign write_data_r = (dma_mode_q? {2{sdcard_dma_data}} : sram_d_in[31:16]);
assign cpu_access_pos = write_addr[9:2];
assign cpu_writes_to_buffer = (dma_mode_q? sdcard_dma_strobe : (sram_cs & sram_a[10]));
assign cpu_writes_left_low = cpu_writes_to_buffer & write_strobe[0];
assign cpu_writes_left_high = cpu_writes_to_buffer & write_strobe[1];
assign cpu_writes_right_low = cpu_writes_to_buffer & write_strobe[2];
assign cpu_writes_right_high = cpu_writes_to_buffer & write_strobe[3];
digital_sound_output #(.CLK_FREQUENCY(CLK_FREQUENCY))
dso_inst(.clk(clk), .rst(rst), .enabled(dso_enabled_q),
.left(left_read_data), .right(right_read_data),
.bck(bck), .sd(sd), .lrck(lrck), .consume(consume_data));
ide_data_buffer left_data(.clk(clk), .rst(rst),
.read_addr(bufpos_q),
.read_data(left_read_data),
.write_addr(cpu_access_pos),
.write_data(write_data_l),
.write_hi(cpu_writes_left_high),
.write_lo(cpu_writes_left_low));
ide_data_buffer right_data(.clk(clk), .rst(rst),
.read_addr(bufpos_q),
.read_data(right_read_data),
.write_addr(cpu_access_pos),
.write_data(write_data_r),
.write_hi(cpu_writes_right_high),
.write_lo(cpu_writes_right_low));
always @(*) begin
case (sram_a[3:2])
2'b00: sram_d = { 4'b0000, dma_buffer_select_q, dma_mode_q, underflow_q, enabled_q };
2'b01: sram_d = bufpos_q;
2'b10: sram_d = last_valid_data_q;
2'b11: sram_d = scratchpad_q;
default: sram_d = 0;
endcase // case (sram_a[3:2])
end
always @(*) begin
bufpos_d = bufpos_q;
underflow_d = underflow_q;
enabled_d = enabled_q;
last_valid_data_d = last_valid_data_q;
scratchpad_d = scratchpad_q;
dma_mode_d = dma_mode_q;
dma_buffer_select_d = dma_buffer_select_q;
if (enabled_q) begin
dso_enabled_d = 1'b1;
if (consume_data) begin
if (bufpos_q == last_valid_data_q)
underflow_d = 1'b1;
else
bufpos_d = bufpos_q+1;
end
end else begin
if (consume_data)
dso_enabled_d = 1'b0;
else
dso_enabled_d = dso_enabled_q;
end
if (sram_cs & sram_wstrb[0] & ~sram_a[10]) begin
case (sram_a[3:2])
2'b00: begin
enabled_d = sram_d_in[0];
if (sram_d_in[1]) underflow_d = 1'b0;
dma_mode_d = sram_d_in[2];
dma_buffer_select_d = sram_d_in[3];
end
2'b01: bufpos_d = sram_d_in[7:0];
2'b10: last_valid_data_d = sram_d_in[7:0];
2'b11: scratchpad_d = sram_d_in[7:0];
endcase // case (sram_a[3:2])
end
end
always @(posedge clk) begin
if (rst) begin
enabled_q <= 1'b0;
dso_enabled_q <= 1'b0;
underflow_q <= 1'b0;
bufpos_q <= 8'h00;
last_valid_data_q <= 8'h00;
scratchpad_q <= 8'h55;
dma_mode_q <= 1'b0;
dma_buffer_select_q <= 1'b0;
end else begin
enabled_q <= enabled_d;
dso_enabled_q <= dso_enabled_d;
underflow_q <= underflow_d;
bufpos_q <= bufpos_d;
last_valid_data_q <= last_valid_data_d;
scratchpad_q <= scratchpad_d;
dma_mode_q <= dma_mode_d;
dma_buffer_select_q <= dma_buffer_select_d;
end
end
endmodule // cdda_interface
|
//////////////////////////////////////////////////////////////////////////////////
// d_KES_PE_ELU_eMAXodr.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_KES_PE_ELU_eMAXodr
// File Name: d_KES_PE_ELU_eMAXodr.v
//
// Version: v1.1.1-256B_T14
//
// Description:
// - Processing Element: Error Locator Update module, maximum order + 1 (extended)
// - for binary version of inversion-less Berlekamp-Massey algorithm (iBM.b)
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.1.1
// - minor modification for releasing
//
// * v1.1.0
// - change state machine: divide states
// - insert additional registers
// - improve frequency characteristic
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_KES_parameters.vh"
`timescale 1ns / 1ps
module d_KES_PE_ELU_eMAXodr // error locate update module: maximum order + 1 (extended)
(
input wire i_clk,
input wire i_RESET_KES,
input wire i_stop_dec,
input wire i_EXECUTE_PE_ELU,
input wire [`D_KES_GF_ORDER-1:0] i_k_2i_Xm1,
input wire [`D_KES_GF_ORDER-1:0] i_d_2i,
input wire [`D_KES_GF_ORDER-1:0] i_delta_2im2,
output reg o_v_2i_X_deg_chk_bit
);
parameter [11:0] D_KES_VALUE_ZERO = 12'b0000_0000_0000;
parameter [11:0] D_KES_VALUE_ONE = 12'b0000_0000_0001;
// FSM parameters
parameter PE_ELU_RST = 2'b01; // reset
parameter PE_ELU_OUT = 2'b10; // output buffer update
// variable declaration
reg [1:0] r_cur_state;
reg [1:0] r_nxt_state;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X_term_A;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X_term_B;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X;
reg [`D_KES_GF_ORDER-1:0] r_v_2i_X;
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin
r_cur_state <= PE_ELU_RST;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
PE_ELU_RST: begin
r_nxt_state <= (i_EXECUTE_PE_ELU)? (PE_ELU_OUT):(PE_ELU_RST);
end
PE_ELU_OUT: begin
r_nxt_state <= PE_ELU_RST;
end
default: begin
r_nxt_state <= PE_ELU_RST;
end
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin // initializing
r_v_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= 0;
end
else begin
case (r_nxt_state)
PE_ELU_RST: begin // hold original data
r_v_2i_X[`D_KES_GF_ORDER-1:0] <= r_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
end
PE_ELU_OUT: begin // output update only
r_v_2i_X[`D_KES_GF_ORDER-1:0] <= w_v_2ip2_X[`D_KES_GF_ORDER-1:0]; // internal only
o_v_2i_X_deg_chk_bit <= |(w_v_2ip2_X[`D_KES_GF_ORDER-1:0]);
end
default: begin
r_v_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= 0;
end
endcase
end
end
d_parallel_FFM_gate_GF12 d_delta_2im2_FFM_v_2i_X (
.i_poly_form_A (i_delta_2im2[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (r_v_2i_X[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0]));
d_parallel_FFM_gate_GF12 d_d_2i_FFM_k_2i_Xm1 (
.i_poly_form_A (i_d_2i[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (i_k_2i_Xm1[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_v_2ip2_X_term_B[`D_KES_GF_ORDER-1:0]));
assign w_v_2ip2_X[`D_KES_GF_ORDER-1:0] = w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0] ^ w_v_2ip2_X_term_B[`D_KES_GF_ORDER-1:0];
endmodule
|
//======================================================================
//
// aes_encipher_block.v
// --------------------
// The AES encipher round. A pure combinational module that implements
// the initial round, main round and final round logic for
// enciper operations.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module aes_encipher_block(
input wire clk,
input wire reset_n,
input wire next,
input wire keylen,
output wire [3 : 0] round,
input wire [127 : 0] round_key,
output wire [31 : 0] sboxw,
input wire [31 : 0] new_sboxw,
input wire [127 : 0] block,
output wire [127 : 0] new_block,
output wire ready
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
localparam NO_UPDATE = 3'h0;
localparam INIT_UPDATE = 3'h1;
localparam SBOX_UPDATE = 3'h2;
localparam MAIN_UPDATE = 3'h3;
localparam FINAL_UPDATE = 3'h4;
localparam CTRL_IDLE = 2'h0;
localparam CTRL_INIT = 2'h1;
localparam CTRL_SBOX = 2'h2;
localparam CTRL_MAIN = 2'h3;
//----------------------------------------------------------------
// Round functions with sub functions.
//----------------------------------------------------------------
function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction // gm2
function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction // gm3
function [31 : 0] mixw(input [31 : 0] w);
reg [7 : 0] b0, b1, b2, b3;
reg [7 : 0] mb0, mb1, mb2, mb3;
begin
b0 = w[31 : 24];
b1 = w[23 : 16];
b2 = w[15 : 08];
b3 = w[07 : 00];
mb0 = gm2(b0) ^ gm3(b1) ^ b2 ^ b3;
mb1 = b0 ^ gm2(b1) ^ gm3(b2) ^ b3;
mb2 = b0 ^ b1 ^ gm2(b2) ^ gm3(b3);
mb3 = gm3(b0) ^ b1 ^ b2 ^ gm2(b3);
mixw = {mb0, mb1, mb2, mb3};
end
endfunction // mixw
function [127 : 0] mixcolumns(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = mixw(w0);
ws1 = mixw(w1);
ws2 = mixw(w2);
ws3 = mixw(w3);
mixcolumns = {ws0, ws1, ws2, ws3};
end
endfunction // mixcolumns
function [127 : 0] shiftrows(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = {w0[31 : 24], w1[23 : 16], w2[15 : 08], w3[07 : 00]};
ws1 = {w1[31 : 24], w2[23 : 16], w3[15 : 08], w0[07 : 00]};
ws2 = {w2[31 : 24], w3[23 : 16], w0[15 : 08], w1[07 : 00]};
ws3 = {w3[31 : 24], w0[23 : 16], w1[15 : 08], w2[07 : 00]};
shiftrows = {ws0, ws1, ws2, ws3};
end
endfunction // shiftrows
function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
begin
addroundkey = data ^ rkey;
end
endfunction // addroundkey
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [1 : 0] sword_ctr_reg;
reg [1 : 0] sword_ctr_new;
reg sword_ctr_we;
reg sword_ctr_inc;
reg sword_ctr_rst;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_rst;
reg round_ctr_inc;
reg [127 : 0] block_new;
reg [31 : 0] block_w0_reg;
reg [31 : 0] block_w1_reg;
reg [31 : 0] block_w2_reg;
reg [31 : 0] block_w3_reg;
reg block_w0_we;
reg block_w1_we;
reg block_w2_we;
reg block_w3_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [1 : 0] enc_ctrl_reg;
reg [1 : 0] enc_ctrl_new;
reg enc_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [2 : 0] update_type;
reg [31 : 0] muxed_sboxw;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign round = round_ctr_reg;
assign sboxw = muxed_sboxw;
assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
block_w0_reg <= 32'h0;
block_w1_reg <= 32'h0;
block_w2_reg <= 32'h0;
block_w3_reg <= 32'h0;
sword_ctr_reg <= 2'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
enc_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (block_w0_we)
block_w0_reg <= block_new[127 : 096];
if (block_w1_we)
block_w1_reg <= block_new[095 : 064];
if (block_w2_we)
block_w2_reg <= block_new[063 : 032];
if (block_w3_we)
block_w3_reg <= block_new[031 : 000];
if (sword_ctr_we)
sword_ctr_reg <= sword_ctr_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (enc_ctrl_we)
enc_ctrl_reg <= enc_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// round_logic
//
// The logic needed to implement init, main and final rounds.
//----------------------------------------------------------------
always @*
begin : round_logic
reg [127 : 0] old_block, shiftrows_block, mixcolumns_block;
reg [127 : 0] addkey_init_block, addkey_main_block, addkey_final_block;
block_new = 128'h0;
muxed_sboxw = 32'h0;
block_w0_we = 1'b0;
block_w1_we = 1'b0;
block_w2_we = 1'b0;
block_w3_we = 1'b0;
old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
shiftrows_block = shiftrows(old_block);
mixcolumns_block = mixcolumns(shiftrows_block);
addkey_init_block = addroundkey(block, round_key);
addkey_main_block = addroundkey(mixcolumns_block, round_key);
addkey_final_block = addroundkey(shiftrows_block, round_key);
case (update_type)
INIT_UPDATE:
begin
block_new = addkey_init_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
SBOX_UPDATE:
begin
block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
case (sword_ctr_reg)
2'h0:
begin
muxed_sboxw = block_w0_reg;
block_w0_we = 1'b1;
end
2'h1:
begin
muxed_sboxw = block_w1_reg;
block_w1_we = 1'b1;
end
2'h2:
begin
muxed_sboxw = block_w2_reg;
block_w2_we = 1'b1;
end
2'h3:
begin
muxed_sboxw = block_w3_reg;
block_w3_we = 1'b1;
end
endcase // case (sbox_mux_ctrl_reg)
end
MAIN_UPDATE:
begin
block_new = addkey_main_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
FINAL_UPDATE:
begin
block_new = addkey_final_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
default:
begin
end
endcase // case (update_type)
end // round_logic
//----------------------------------------------------------------
// sword_ctr
//
// The subbytes word counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : sword_ctr
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b0;
if (sword_ctr_rst)
begin
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b1;
end
else if (sword_ctr_inc)
begin
sword_ctr_new = sword_ctr_reg + 1'b1;
sword_ctr_we = 1'b1;
end
end // sword_ctr
//----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_rst)
begin
round_ctr_new = 4'h0;
round_ctr_we = 1'b1;
end
else if (round_ctr_inc)
begin
round_ctr_new = round_ctr_reg + 1'b1;
round_ctr_we = 1'b1;
end
end // round_ctr
//----------------------------------------------------------------
// encipher_ctrl
//
// The FSM that controls the encipher operations.
//----------------------------------------------------------------
always @*
begin: encipher_ctrl
reg [3 : 0] num_rounds;
// Default assignments.
sword_ctr_inc = 1'b0;
sword_ctr_rst = 1'b0;
round_ctr_inc = 1'b0;
round_ctr_rst = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
update_type = NO_UPDATE;
enc_ctrl_new = CTRL_IDLE;
enc_ctrl_we = 1'b0;
if (keylen == AES_256_BIT_KEY)
begin
num_rounds = AES256_ROUNDS;
end
else
begin
num_rounds = AES128_ROUNDS;
end
case(enc_ctrl_reg)
CTRL_IDLE:
begin
if (next)
begin
round_ctr_rst = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
enc_ctrl_new = CTRL_INIT;
enc_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
round_ctr_inc = 1'b1;
sword_ctr_rst = 1'b1;
update_type = INIT_UPDATE;
enc_ctrl_new = CTRL_SBOX;
enc_ctrl_we = 1'b1;
end
CTRL_SBOX:
begin
sword_ctr_inc = 1'b1;
update_type = SBOX_UPDATE;
if (sword_ctr_reg == 2'h3)
begin
enc_ctrl_new = CTRL_MAIN;
enc_ctrl_we = 1'b1;
end
end
CTRL_MAIN:
begin
sword_ctr_rst = 1'b1;
round_ctr_inc = 1'b1;
if (round_ctr_reg < num_rounds)
begin
update_type = MAIN_UPDATE;
enc_ctrl_new = CTRL_SBOX;
enc_ctrl_we = 1'b1;
end
else
begin
update_type = FINAL_UPDATE;
ready_new = 1'b1;
ready_we = 1'b1;
enc_ctrl_new = CTRL_IDLE;
enc_ctrl_we = 1'b1;
end
end
default:
begin
// Empty. Just here to make the synthesis tool happy.
end
endcase // case (enc_ctrl_reg)
end // encipher_ctrl
endmodule // aes_encipher_block
//======================================================================
// EOF aes_encipher_block.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_4_V
`define SKY130_FD_SC_HD__A311OI_4_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311oi_4 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_4_V
|