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systemc-code-database-new

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no_read_write();
wait(1, SC_NS);
}
// change the read and write signals not to read and not to write
void no_read_write () {
read.write(0);
write.write(0);
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Bus) {
sc_in_clk clk;
sc_in <bool> req; // X DIDN'T USED! X
sc_in <bool> read;
sc_in <bool> write;
sc_in <bool> call;
sc_in <sc_uint<13>> addr; // for both Mem. and Acc.
sc_in <sc_int<8>> data;
sc_out <bool> ack; // X DIDN'T USED! X
sc_out <bool> read_out;
sc_out <bool> write_out;
sc_out <bool> call_out;
sc_out <sc_uint<13>> addr_out; // for both Mem. and Acc.
sc_out <sc_int<8>> data_out;
/*
** module global variables
*/
SC_CTOR (Bus){
SC_METHOD (process);
sensitive << clk.pos();
}
void process () {
ack.write(req.read());
read_out.write(read.read());
write_out.write(write.read());
call_out.write(call.read());
addr_out.write(addr.read());
data_out.write(data.read());
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Controller) {
sc_in <sc_uint<4>> opcode, opselect;
sc_out <sc_uint<5>> aluOp;
sc_out <bool> regWrite, r, w, aluMux, regMux, wbMux, call;
/*
** module global variables
*/
sc_uint<4> opcd, opsel;
sc_uint<5> op;
//tmp
int c = 0;
SC_CTOR (Controller){
SC_METHOD (process);
sensitive << opcode << opselect;
}
void process () {
opcd = opcode.read();
opsel = opselect.read();
switch (opcd){
case 0b0000:
case 0b0001:
op = opsel;
op = opsel << 1;
op[0] = opcd[0];
aluOp.write(op); // concatinated to produce aluop
regWrite.write(1);
r.write(0);
w.write(0);
regMux.write(0); // r1 = rs